mirror of https://github.com/ARMmbed/mbed-os.git
Add one new target M2351, regard as M0+ with some V8M CPU control at first
cyliangtw
Cruz Monrreal II
parent
0ac5f32579
commit
949c330229
|
|
@ -0,0 +1,149 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2016 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_PERIPHERALNAMES_H
|
||||||
|
#define MBED_PERIPHERALNAMES_H
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
// NOTE: Check all module base addresses (XXX_BASE in BSP) for free bit fields to define module name
|
||||||
|
// which encodes module base address and module index/subindex.
|
||||||
|
#define NU_MODSUBINDEX_Pos 0
|
||||||
|
#define NU_MODSUBINDEX_Msk (0x1Ful << NU_MODSUBINDEX_Pos)
|
||||||
|
#define NU_MODINDEX_Pos 20
|
||||||
|
#define NU_MODINDEX_Msk (0xFul << NU_MODINDEX_Pos)
|
||||||
|
|
||||||
|
#define NU_MODNAME(MODBASE, INDEX, SUBINDEX) ((MODBASE) | ((INDEX) << NU_MODINDEX_Pos) | ((SUBINDEX) << NU_MODSUBINDEX_Pos))
|
||||||
|
#define NU_MODBASE(MODNAME) ((MODNAME) & ~(NU_MODINDEX_Msk | NU_MODSUBINDEX_Msk))
|
||||||
|
#define NU_MODINDEX(MODNAME) (((MODNAME) & NU_MODINDEX_Msk) >> NU_MODINDEX_Pos)
|
||||||
|
#define NU_MODSUBINDEX(MODNAME) (((MODNAME) & NU_MODSUBINDEX_Msk) >> NU_MODSUBINDEX_Pos)
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
typedef enum {
|
||||||
|
GPIO_A = (int) NU_MODNAME(GPIOA_BASE, 0, 0),
|
||||||
|
GPIO_B = (int) NU_MODNAME(GPIOB_BASE, 1, 0),
|
||||||
|
GPIO_C = (int) NU_MODNAME(GPIOC_BASE, 2, 0),
|
||||||
|
GPIO_D = (int) NU_MODNAME(GPIOD_BASE, 3, 0),
|
||||||
|
GPIO_E = (int) NU_MODNAME(GPIOE_BASE, 4, 0),
|
||||||
|
GPIO_F = (int) NU_MODNAME(GPIOF_BASE, 5, 0),
|
||||||
|
GPIO_G = (int) NU_MODNAME(GPIOF_BASE, 6, 0)
|
||||||
|
} GPIOName;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0),
|
||||||
|
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1),
|
||||||
|
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2),
|
||||||
|
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3),
|
||||||
|
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4),
|
||||||
|
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5),
|
||||||
|
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6),
|
||||||
|
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7),
|
||||||
|
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8),
|
||||||
|
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9),
|
||||||
|
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10),
|
||||||
|
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11),
|
||||||
|
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12),
|
||||||
|
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13),
|
||||||
|
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14),
|
||||||
|
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15)
|
||||||
|
} ADCName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
|
||||||
|
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
|
||||||
|
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
|
||||||
|
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
|
||||||
|
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
|
||||||
|
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
|
||||||
|
// NOTE: board-specific
|
||||||
|
STDIO_UART = UART_3
|
||||||
|
} UARTName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
|
||||||
|
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
|
||||||
|
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
|
||||||
|
SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0),
|
||||||
|
SPI_4 = (int) NU_MODNAME(SPI4_BASE, 4, 0),
|
||||||
|
SPI_5 = (int) NU_MODNAME(SPI5_BASE, 5, 0)
|
||||||
|
} SPIName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
I2C_0 = (int) NU_MODNAME(I2C0_BASE, 0, 0),
|
||||||
|
I2C_1 = (int) NU_MODNAME(I2C1_BASE, 1, 0),
|
||||||
|
I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0)
|
||||||
|
} I2CName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
PWM_0_0 = (int) NU_MODNAME(PWM0_BASE, 0, 0),
|
||||||
|
PWM_0_1 = (int) NU_MODNAME(PWM0_BASE, 0, 1),
|
||||||
|
PWM_0_2 = (int) NU_MODNAME(PWM0_BASE, 0, 2),
|
||||||
|
PWM_0_3 = (int) NU_MODNAME(PWM0_BASE, 0, 3),
|
||||||
|
PWM_0_4 = (int) NU_MODNAME(PWM0_BASE, 0, 4),
|
||||||
|
PWM_0_5 = (int) NU_MODNAME(PWM0_BASE, 0, 5),
|
||||||
|
|
||||||
|
PWM_1_0 = (int) NU_MODNAME(PWM1_BASE, 1, 0),
|
||||||
|
PWM_1_1 = (int) NU_MODNAME(PWM1_BASE, 1, 1),
|
||||||
|
PWM_1_2 = (int) NU_MODNAME(PWM1_BASE, 1, 2),
|
||||||
|
PWM_1_3 = (int) NU_MODNAME(PWM1_BASE, 1, 3),
|
||||||
|
PWM_1_4 = (int) NU_MODNAME(PWM1_BASE, 1, 4),
|
||||||
|
PWM_1_5 = (int) NU_MODNAME(PWM1_BASE, 1, 5),
|
||||||
|
|
||||||
|
BPWM_0_0 = (int) NU_MODNAME(BPWM0_BASE, 0, 0),
|
||||||
|
BPWM_0_1 = (int) NU_MODNAME(BPWM0_BASE, 0, 1),
|
||||||
|
BPWM_0_2 = (int) NU_MODNAME(BPWM0_BASE, 0, 2),
|
||||||
|
BPWM_0_3 = (int) NU_MODNAME(BPWM0_BASE, 0, 3),
|
||||||
|
BPWM_0_4 = (int) NU_MODNAME(BPWM0_BASE, 0, 4),
|
||||||
|
BPWM_0_5 = (int) NU_MODNAME(BPWM0_BASE, 0, 5),
|
||||||
|
|
||||||
|
BPWM_1_0 = (int) NU_MODNAME(BPWM1_BASE, 1, 0),
|
||||||
|
BPWM_1_1 = (int) NU_MODNAME(BPWM1_BASE, 1, 1),
|
||||||
|
BPWM_1_2 = (int) NU_MODNAME(BPWM1_BASE, 1, 2),
|
||||||
|
BPWM_1_3 = (int) NU_MODNAME(BPWM1_BASE, 1, 3),
|
||||||
|
BPWM_1_4 = (int) NU_MODNAME(BPWM1_BASE, 1, 4),
|
||||||
|
BPWM_1_5 = (int) NU_MODNAME(BPWM1_BASE, 1, 5)
|
||||||
|
|
||||||
|
} PWMName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
|
||||||
|
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0),
|
||||||
|
TIMER_2 = (int) NU_MODNAME(TMR23_BASE, 2, 0),
|
||||||
|
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + 0x100, 3, 0),
|
||||||
|
} TIMERName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0)
|
||||||
|
} RTCName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
DMA_0 = (int) NU_MODNAME(PDMA_BASE, 0, 0)
|
||||||
|
} DMAName;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0)
|
||||||
|
} CANName;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,578 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "PeripheralPins.h"
|
||||||
|
|
||||||
|
// =====
|
||||||
|
// Note: Commented lines are alternative possibilities which are not used per default.
|
||||||
|
// If you change them, you will have also to modify the corresponding xxx_api.c file
|
||||||
|
// for pwmout, analogin, analogout, ...
|
||||||
|
// =====
|
||||||
|
|
||||||
|
#if 0
|
||||||
|
//*** GPIO ***
|
||||||
|
const PinMap PinMap_GPIO[] = {
|
||||||
|
// GPIO A MFP
|
||||||
|
{PA_0, GPIO_A, SYS_GPA_MFPL_PA0MFP_GPIO},
|
||||||
|
{PA_1, GPIO_A, SYS_GPA_MFPL_PA1MFP_GPIO},
|
||||||
|
{PA_2, GPIO_A, SYS_GPA_MFPL_PA2MFP_GPIO},
|
||||||
|
{PA_3, GPIO_A, SYS_GPA_MFPL_PA3MFP_GPIO},
|
||||||
|
{PA_4, GPIO_A, SYS_GPA_MFPL_PA4MFP_GPIO},
|
||||||
|
{PA_5, GPIO_A, SYS_GPA_MFPL_PA5MFP_GPIO},
|
||||||
|
{PA_6, GPIO_A, SYS_GPA_MFPL_PA6MFP_GPIO},
|
||||||
|
{PA_7, GPIO_A, SYS_GPA_MFPL_PA7MFP_GPIO},
|
||||||
|
{PA_8, GPIO_A, SYS_GPA_MFPH_PA8MFP_GPIO},
|
||||||
|
{PA_9, GPIO_A, SYS_GPA_MFPH_PA9MFP_GPIO},
|
||||||
|
{PA_10, GPIO_A, SYS_GPA_MFPH_PA10MFP_GPIO},
|
||||||
|
{PA_11, GPIO_A, SYS_GPA_MFPH_PA11MFP_GPIO},
|
||||||
|
{PA_12, GPIO_A, SYS_GPA_MFPH_PA12MFP_GPIO},
|
||||||
|
{PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
|
||||||
|
{PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
|
||||||
|
{PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
|
||||||
|
|
||||||
|
// GPIO B MFP
|
||||||
|
{PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
|
||||||
|
{PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
|
||||||
|
{PB_2, GPIO_B, SYS_GPB_MFPL_PB2MFP_GPIO},
|
||||||
|
{PB_3, GPIO_B, SYS_GPB_MFPL_PB3MFP_GPIO},
|
||||||
|
{PB_4, GPIO_B, SYS_GPB_MFPL_PB4MFP_GPIO},
|
||||||
|
{PB_5, GPIO_B, SYS_GPB_MFPL_PB5MFP_GPIO},
|
||||||
|
{PB_6, GPIO_B, SYS_GPB_MFPL_PB6MFP_GPIO},
|
||||||
|
{PB_7, GPIO_B, SYS_GPB_MFPL_PB7MFP_GPIO},
|
||||||
|
{PB_8, GPIO_B, SYS_GPB_MFPH_PB8MFP_GPIO},
|
||||||
|
{PB_9, GPIO_B, SYS_GPB_MFPH_PB9MFP_GPIO},
|
||||||
|
{PB_10, GPIO_B, SYS_GPB_MFPH_PB10MFP_GPIO},
|
||||||
|
{PB_11, GPIO_B, SYS_GPB_MFPH_PB11MFP_GPIO},
|
||||||
|
{PB_12, GPIO_B, SYS_GPB_MFPH_PB12MFP_GPIO},
|
||||||
|
{PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
|
||||||
|
{PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
|
||||||
|
{PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
|
||||||
|
|
||||||
|
// GPIO C MFP
|
||||||
|
{PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
|
||||||
|
{PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
|
||||||
|
{PC_2, GPIO_C, SYS_GPC_MFPL_PC2MFP_GPIO},
|
||||||
|
{PC_3, GPIO_C, SYS_GPC_MFPL_PC3MFP_GPIO},
|
||||||
|
{PC_4, GPIO_C, SYS_GPC_MFPL_PC4MFP_GPIO},
|
||||||
|
{PC_5, GPIO_C, SYS_GPC_MFPL_PC5MFP_GPIO},
|
||||||
|
{PC_6, GPIO_C, SYS_GPC_MFPL_PC6MFP_GPIO},
|
||||||
|
{PC_7, GPIO_C, SYS_GPC_MFPL_PC7MFP_GPIO},
|
||||||
|
{PC_8, GPIO_C, SYS_GPC_MFPH_PC8MFP_GPIO},
|
||||||
|
{PC_9, GPIO_C, SYS_GPC_MFPH_PC9MFP_GPIO},
|
||||||
|
{PC_10, GPIO_C, SYS_GPC_MFPH_PC10MFP_GPIO},
|
||||||
|
{PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
|
||||||
|
{PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
|
||||||
|
{PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
|
||||||
|
{PC_14, GPIO_C, SYS_GPC_MFPH_PC14MFP_GPIO},
|
||||||
|
{PC_15, GPIO_C, SYS_GPC_MFPH_PC15MFP_GPIO},
|
||||||
|
|
||||||
|
// GPIO D MFP
|
||||||
|
{PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
|
||||||
|
{PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
|
||||||
|
{PD_2, GPIO_D, SYS_GPD_MFPL_PD2MFP_GPIO},
|
||||||
|
{PD_3, GPIO_D, SYS_GPD_MFPL_PD3MFP_GPIO},
|
||||||
|
{PD_4, GPIO_D, SYS_GPD_MFPL_PD4MFP_GPIO},
|
||||||
|
{PD_5, GPIO_D, SYS_GPD_MFPL_PD5MFP_GPIO},
|
||||||
|
{PD_6, GPIO_D, SYS_GPD_MFPL_PD6MFP_GPIO},
|
||||||
|
{PD_7, GPIO_D, SYS_GPD_MFPL_PD7MFP_GPIO},
|
||||||
|
{PD_8, GPIO_D, SYS_GPD_MFPH_PD8MFP_GPIO},
|
||||||
|
{PD_9, GPIO_D, SYS_GPD_MFPH_PD9MFP_GPIO},
|
||||||
|
{PD_10, GPIO_D, SYS_GPD_MFPH_PD10MFP_GPIO},
|
||||||
|
{PD_11, GPIO_D, SYS_GPD_MFPH_PD11MFP_GPIO},
|
||||||
|
{PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
|
||||||
|
{PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
|
||||||
|
{PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
|
||||||
|
{PD_15, GPIO_D, SYS_GPD_MFPH_PD15MFP_GPIO},
|
||||||
|
|
||||||
|
// GPIO E MFP
|
||||||
|
{PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
|
||||||
|
{PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
|
||||||
|
{PE_2, GPIO_E, SYS_GPE_MFPL_PE2MFP_GPIO},
|
||||||
|
{PE_3, GPIO_E, SYS_GPE_MFPL_PE3MFP_GPIO},
|
||||||
|
{PE_4, GPIO_E, SYS_GPE_MFPL_PE4MFP_GPIO},
|
||||||
|
{PE_5, GPIO_E, SYS_GPE_MFPL_PE5MFP_GPIO},
|
||||||
|
{PE_6, GPIO_E, SYS_GPE_MFPL_PE6MFP_GPIO},
|
||||||
|
{PE_7, GPIO_E, SYS_GPE_MFPL_PE7MFP_GPIO},
|
||||||
|
{PE_8, GPIO_E, SYS_GPE_MFPH_PE8MFP_GPIO},
|
||||||
|
{PE_9, GPIO_E, SYS_GPE_MFPH_PE9MFP_GPIO},
|
||||||
|
{PE_10, GPIO_E, SYS_GPE_MFPH_PE10MFP_GPIO},
|
||||||
|
{PE_11, GPIO_E, SYS_GPE_MFPH_PE11MFP_GPIO},
|
||||||
|
{PE_12, GPIO_E, SYS_GPE_MFPH_PE12MFP_GPIO},
|
||||||
|
{PE_13, GPIO_E, SYS_GPE_MFPH_PE13MFP_GPIO},
|
||||||
|
|
||||||
|
// GPIO F MFP
|
||||||
|
{PF_0, GPIO_F, SYS_GPF_MFPL_PF0MFP_GPIO},
|
||||||
|
{PF_1, GPIO_F, SYS_GPF_MFPL_PF1MFP_GPIO},
|
||||||
|
{PF_2, GPIO_F, SYS_GPF_MFPL_PF2MFP_GPIO},
|
||||||
|
{PF_3, GPIO_F, SYS_GPF_MFPL_PF3MFP_GPIO},
|
||||||
|
{PF_4, GPIO_F, SYS_GPF_MFPL_PF4MFP_GPIO},
|
||||||
|
{PF_5, GPIO_F, SYS_GPF_MFPL_PF5MFP_GPIO},
|
||||||
|
{PF_6, GPIO_F, SYS_GPF_MFPL_PF6MFP_GPIO},
|
||||||
|
{PF_7, GPIO_F, SYS_GPF_MFPL_PF7MFP_GPIO},
|
||||||
|
{PF_8, GPIO_F, SYS_GPF_MFPH_PF8MFP_GPIO},
|
||||||
|
{PF_9, GPIO_F, SYS_GPF_MFPH_PF9MFP_GPIO},
|
||||||
|
{PF_10, GPIO_F, SYS_GPF_MFPH_PF10MFP_GPIO},
|
||||||
|
{PF_11, GPIO_F, SYS_GPF_MFPH_PF11MFP_GPIO},
|
||||||
|
{PF_12, GPIO_F, SYS_GPF_MFPH_PF12MFP_GPIO},
|
||||||
|
{PF_13, GPIO_F, SYS_GPF_MFPH_PF13MFP_GPIO},
|
||||||
|
{PF_14, GPIO_F, SYS_GPF_MFPH_PF14MFP_GPIO},
|
||||||
|
{PF_15, GPIO_F, SYS_GPF_MFPH_PF15MFP_GPIO},
|
||||||
|
{PG_1, GPIO_G, SYS_GPG_MFPL_PG1MFP_GPIO},
|
||||||
|
{PG_2, GPIO_G, SYS_GPG_MFPL_PG2MFP_GPIO},
|
||||||
|
{PG_3, GPIO_G, SYS_GPG_MFPL_PG3MFP_GPIO},
|
||||||
|
{PG_4, GPIO_G, SYS_GPG_MFPL_PG4MFP_GPIO},
|
||||||
|
{PG_5, GPIO_G, SYS_GPG_MFPL_PG5MFP_GPIO},
|
||||||
|
{PG_7, GPIO_G, SYS_GPG_MFPL_PG7MFP_GPIO},
|
||||||
|
{PG_8, GPIO_G, SYS_GPG_MFPH_PG8MFP_GPIO},
|
||||||
|
{PG_9, GPIO_G, SYS_GPG_MFPH_PG9MFP_GPIO},
|
||||||
|
{PG_10, GPIO_G, SYS_GPG_MFPH_PG10MFP_GPIO},
|
||||||
|
{PG_11, GPIO_G, SYS_GPG_MFPH_PG11MFP_GPIO},
|
||||||
|
{PG_12, GPIO_G, SYS_GPG_MFPH_PG12MFP_GPIO},
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** ADC ***
|
||||||
|
|
||||||
|
const PinMap PinMap_ADC[] = {
|
||||||
|
{PB_0, ADC_0_0, SYS_GPB_MFPL_PB0MFP_EADC0_CH0},
|
||||||
|
{PB_1, ADC_0_1, SYS_GPB_MFPL_PB1MFP_EADC0_CH1},
|
||||||
|
{PB_2, ADC_0_2, SYS_GPB_MFPL_PB2MFP_EADC0_CH2},
|
||||||
|
{PB_3, ADC_0_3, SYS_GPB_MFPL_PB3MFP_EADC0_CH3},
|
||||||
|
{PB_4, ADC_0_4, SYS_GPB_MFPL_PB4MFP_EADC0_CH4},
|
||||||
|
{PB_5, ADC_0_13, SYS_GPB_MFPL_PB5MFP_EADC0_CH13},
|
||||||
|
{PB_6, ADC_0_14, SYS_GPB_MFPL_PB6MFP_EADC0_CH14},
|
||||||
|
{PB_7, ADC_0_15, SYS_GPB_MFPL_PB7MFP_EADC0_CH15},
|
||||||
|
{PB_8, ADC_0_5, SYS_GPB_MFPH_PB8MFP_EADC0_CH5},
|
||||||
|
{PB_9, ADC_0_6, SYS_GPB_MFPH_PB9MFP_EADC0_CH6},
|
||||||
|
{PB_10, ADC_0_7, SYS_GPB_MFPH_PB10MFP_EADC0_CH7},
|
||||||
|
{PB_11, ADC_0_8, SYS_GPB_MFPH_PB11MFP_EADC0_CH8},
|
||||||
|
{PB_12, ADC_0_9, SYS_GPB_MFPH_PB12MFP_EADC0_CH9},
|
||||||
|
{PB_13, ADC_0_10, SYS_GPB_MFPH_PB13MFP_EADC0_CH10},
|
||||||
|
{PB_14, ADC_0_11, SYS_GPB_MFPH_PB14MFP_EADC0_CH11},
|
||||||
|
{PB_15, ADC_0_12, SYS_GPB_MFPH_PB15MFP_EADC0_CH12},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//*** I2C ***
|
||||||
|
|
||||||
|
const PinMap PinMap_I2C_SDA[] = {
|
||||||
|
{PA_1, I2C_2, SYS_GPA_MFPL_PA1MFP_I2C2_SDA},
|
||||||
|
{PA_2, I2C_0, SYS_GPA_MFPL_PA2MFP_I2C0_SDA},
|
||||||
|
{PB_0, I2C_2, SYS_GPB_MFPL_PB0MFP_I2C2_SDA},
|
||||||
|
{PD_4, I2C_0, SYS_GPD_MFPL_PD4MFP_I2C0_SDA},
|
||||||
|
{PD_8, I2C_0, SYS_GPD_MFPH_PD8MFP_I2C0_SDA},
|
||||||
|
{PE_0, I2C_1, SYS_GPE_MFPL_PE0MFP_I2C1_SDA},
|
||||||
|
{PE_5, I2C_1, SYS_GPE_MFPL_PE5MFP_I2C1_SDA},
|
||||||
|
{PE_9, I2C_1, SYS_GPE_MFPH_PE9MFP_I2C1_SDA},
|
||||||
|
{PE_11, I2C_1, SYS_GPE_MFPH_PE11MFP_I2C1_SDA},
|
||||||
|
{PE_13, I2C_0, SYS_GPE_MFPH_PE13MFP_I2C0_SDA},
|
||||||
|
{PF_4, I2C_1, SYS_GPF_MFPL_PF4MFP_I2C1_SDA},
|
||||||
|
{PF_6, I2C_0, SYS_GPF_MFPL_PF6MFP_I2C0_SDA},
|
||||||
|
{PF_11, I2C_2, SYS_GPF_MFPH_PF11MFP_I2C2_SDA},
|
||||||
|
{PF_13, I2C_0, SYS_GPF_MFPH_PF13MFP_I2C0_SDA},
|
||||||
|
{PF_15, I2C_1, SYS_GPF_MFPH_PF15MFP_I2C1_SDA},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_I2C_SCL[] = {
|
||||||
|
{PA_0, I2C_2, SYS_GPA_MFPL_PA0MFP_I2C2_SCL},
|
||||||
|
{PA_3, I2C_0, SYS_GPA_MFPL_PA3MFP_I2C0_SCL},
|
||||||
|
{PB_1, I2C_2, SYS_GPB_MFPL_PB1MFP_I2C2_SCL},
|
||||||
|
{PC_4, I2C_1, SYS_GPC_MFPL_PC4MFP_I2C1_SCL},
|
||||||
|
{PD_5, I2C_0, SYS_GPD_MFPL_PD5MFP_I2C0_SCL},
|
||||||
|
{PD_9, I2C_0, SYS_GPD_MFPH_PD9MFP_I2C0_SCL},
|
||||||
|
{PE_4, I2C_1, SYS_GPE_MFPL_PE4MFP_I2C1_SCL},
|
||||||
|
{PE_8, I2C_1, SYS_GPE_MFPH_PE8MFP_I2C1_SCL},
|
||||||
|
{PE_10, I2C_1, SYS_GPE_MFPH_PE10MFP_I2C1_SCL},
|
||||||
|
{PE_12, I2C_0, SYS_GPE_MFPH_PE12MFP_I2C0_SCL},
|
||||||
|
{PF_3, I2C_1, SYS_GPF_MFPL_PF3MFP_I2C1_SCL},
|
||||||
|
{PF_5, I2C_0, SYS_GPF_MFPL_PF5MFP_I2C0_SCL},
|
||||||
|
{PF_10, I2C_2, SYS_GPF_MFPH_PF10MFP_I2C2_SCL},
|
||||||
|
{PF_12, I2C_0, SYS_GPF_MFPH_PF12MFP_I2C0_SCL},
|
||||||
|
{PF_14, I2C_1, SYS_GPF_MFPH_PF14MFP_I2C1_SCL},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//*** PWM ***
|
||||||
|
|
||||||
|
const PinMap PinMap_PWM[] = {
|
||||||
|
{PA_0, PWM_1_5, SYS_GPA_MFPL_PA0MFP_PWM1_CH5},
|
||||||
|
{PA_1, PWM_1_4, SYS_GPA_MFPL_PA1MFP_PWM1_CH4},
|
||||||
|
{PA_2, BPWM_1_3, SYS_GPA_MFPL_PA2MFP_BPWM1_CH3},
|
||||||
|
{PA_2, PWM_1_3, SYS_GPA_MFPL_PA2MFP_PWM1_CH3},
|
||||||
|
{PA_3, BPWM_1_2, SYS_GPA_MFPL_PA3MFP_BPWM1_CH2},
|
||||||
|
{PA_3, PWM_1_2, SYS_GPA_MFPL_PA3MFP_PWM1_CH2},
|
||||||
|
{PA_12, BPWM_0_5, SYS_GPA_MFPH_PA12MFP_BPWM0_CH5},
|
||||||
|
{PA_14, BPWM_1_0, SYS_GPA_MFPH_PA14MFP_BPWM1_CH0},
|
||||||
|
{PA_15, BPWM_1_1, SYS_GPA_MFPH_PA15MFP_BPWM1_CH1},
|
||||||
|
{PA_15, PWM_1_0, SYS_GPA_MFPH_PA15MFP_PWM1_CH0},
|
||||||
|
{PB_0, PWM_1_5, SYS_GPB_MFPL_PB0MFP_PWM1_CH5},
|
||||||
|
{PB_2, PWM_1_4, SYS_GPB_MFPL_PB2MFP_PWM1_CH4},
|
||||||
|
{PB_3, PWM_1_3, SYS_GPB_MFPL_PB3MFP_PWM1_CH3},
|
||||||
|
{PB_4, PWM_1_2, SYS_GPB_MFPL_PB4MFP_PWM1_CH2},
|
||||||
|
{PB_6, BPWM_0_0, SYS_GPB_MFPL_PB6MFP_BPWM0_CH0},
|
||||||
|
{PB_6, PWM_1_0, SYS_GPB_MFPL_PB6MFP_PWM1_CH0},
|
||||||
|
{PB_7, BPWM_0_1, SYS_GPB_MFPL_PB7MFP_BPWM0_CH1},
|
||||||
|
{PB_7, PWM_1_1, SYS_GPB_MFPL_PB7MFP_PWM1_CH1},
|
||||||
|
{PB_8, PWM_0_2, SYS_GPB_MFPH_PB8MFP_PWM0_CH2},
|
||||||
|
{PC_0, PWM_0_0, SYS_GPC_MFPL_PC0MFP_PWM0_CH0},
|
||||||
|
{PC_1, PWM_0_1, SYS_GPC_MFPL_PC1MFP_PWM0_CH1},
|
||||||
|
{PC_2, PWM_0_2, SYS_GPC_MFPL_PC2MFP_PWM0_CH2},
|
||||||
|
{PC_3, PWM_0_3, SYS_GPC_MFPL_PC3MFP_PWM0_CH3},
|
||||||
|
{PC_4, PWM_0_4, SYS_GPC_MFPL_PC4MFP_PWM0_CH4},
|
||||||
|
{PC_5, BPWM_0_1, SYS_GPC_MFPL_PC5MFP_BPWM0_CH1},
|
||||||
|
{PC_5, PWM_0_1, SYS_GPC_MFPL_PC5MFP_PWM0_CH1},
|
||||||
|
{PC_6, PWM_1_0, SYS_GPC_MFPL_PC6MFP_PWM1_CH0},
|
||||||
|
{PC_7, PWM_1_1, SYS_GPC_MFPL_PC7MFP_PWM1_CH1},
|
||||||
|
{PC_8, BPWM_0_0, SYS_GPC_MFPH_PC8MFP_BPWM0_CH0},
|
||||||
|
{PC_9, PWM_1_0, SYS_GPC_MFPH_PC9MFP_PWM1_CH0},
|
||||||
|
{PC_10, PWM_1_1, SYS_GPC_MFPH_PC10MFP_PWM1_CH1},
|
||||||
|
{PC_11, PWM_1_2, SYS_GPC_MFPH_PC11MFP_PWM1_CH2},
|
||||||
|
{PC_12, PWM_1_3, SYS_GPC_MFPH_PC12MFP_PWM1_CH3},
|
||||||
|
{PC_13, PWM_1_4, SYS_GPC_MFPH_PC13MFP_PWM1_CH4},
|
||||||
|
{PC_14, PWM_1_5, SYS_GPC_MFPH_PC14MFP_PWM1_CH5},
|
||||||
|
{PC_15, PWM_1_0, SYS_GPC_MFPH_PC15MFP_PWM1_CH0},
|
||||||
|
{PD_0, BPWM_0_2, SYS_GPD_MFPL_PD0MFP_BPWM0_CH2},
|
||||||
|
{PD_1, BPWM_0_3, SYS_GPD_MFPL_PD1MFP_BPWM0_CH3},
|
||||||
|
{PD_2, BPWM_0_4, SYS_GPD_MFPL_PD2MFP_BPWM0_CH4},
|
||||||
|
{PD_3, BPWM_0_5, SYS_GPD_MFPL_PD3MFP_BPWM0_CH5},
|
||||||
|
{PD_6, PWM_0_5, SYS_GPD_MFPL_PD6MFP_PWM0_CH5},
|
||||||
|
{PD_7, PWM_0_5, SYS_GPD_MFPL_PD7MFP_PWM0_CH5},
|
||||||
|
{PD_8, BPWM_0_1, SYS_GPD_MFPH_PD8MFP_BPWM0_CH1},
|
||||||
|
{PD_9, BPWM_0_2, SYS_GPD_MFPH_PD9MFP_BPWM0_CH2},
|
||||||
|
{PD_12, PWM_1_0, SYS_GPD_MFPH_PD12MFP_PWM1_CH0},
|
||||||
|
{PD_13, PWM_1_1, SYS_GPD_MFPH_PD13MFP_PWM1_CH1},
|
||||||
|
{PD_14, PWM_1_2, SYS_GPD_MFPH_PD14MFP_PWM1_CH2},
|
||||||
|
{PD_15, PWM_1_3, SYS_GPD_MFPH_PD15MFP_PWM1_CH3},
|
||||||
|
{PE_0, BPWM_0_0, SYS_GPE_MFPL_PE0MFP_BPWM0_CH0},
|
||||||
|
{PE_0, PWM_0_0, SYS_GPE_MFPL_PE0MFP_PWM0_CH0},
|
||||||
|
{PE_0, PWM_0_5, SYS_GPE_MFPL_PE0MFP_PWM0_CH5},
|
||||||
|
{PE_1, PWM_0_1, SYS_GPE_MFPL_PE1MFP_PWM0_CH1},
|
||||||
|
{PE_2, PWM_1_1, SYS_GPE_MFPL_PE2MFP_PWM1_CH1},
|
||||||
|
{PE_3, PWM_0_3, SYS_GPE_MFPL_PE3MFP_PWM0_CH3},
|
||||||
|
{PE_8, BPWM_1_0, SYS_GPE_MFPH_PE8MFP_BPWM1_CH0},
|
||||||
|
{PE_9, BPWM_1_1, SYS_GPE_MFPH_PE9MFP_BPWM1_CH1},
|
||||||
|
{PE_10, BPWM_1_2, SYS_GPE_MFPH_PE10MFP_BPWM1_CH2},
|
||||||
|
{PE_10, PWM_1_0, SYS_GPE_MFPH_PE10MFP_PWM1_CH0},
|
||||||
|
{PE_11, BPWM_1_3, SYS_GPE_MFPH_PE11MFP_BPWM1_CH3},
|
||||||
|
{PE_11, PWM_1_1, SYS_GPE_MFPH_PE11MFP_PWM1_CH1},
|
||||||
|
{PE_12, BPWM_1_4, SYS_GPE_MFPH_PE12MFP_BPWM1_CH4},
|
||||||
|
{PE_12, PWM_0_4, SYS_GPE_MFPH_PE12MFP_PWM0_CH4},
|
||||||
|
{PE_13, BPWM_1_5, SYS_GPE_MFPH_PE13MFP_BPWM1_CH5},
|
||||||
|
{PE_13, PWM_0_5, SYS_GPE_MFPH_PE13MFP_PWM0_CH5},
|
||||||
|
{PF_2, PWM_0_5, SYS_GPF_MFPL_PF2MFP_PWM0_CH5},
|
||||||
|
{PF_3, PWM_1_4, SYS_GPF_MFPL_PF3MFP_PWM1_CH4},
|
||||||
|
{PF_4, PWM_1_5, SYS_GPF_MFPL_PF4MFP_PWM1_CH5},
|
||||||
|
{PF_5, BPWM_1_0, SYS_GPF_MFPL_PF5MFP_BPWM1_CH0},
|
||||||
|
{PF_6, BPWM_1_1, SYS_GPF_MFPL_PF6MFP_BPWM1_CH1},
|
||||||
|
{PF_7, PWM_1_0, SYS_GPF_MFPL_PF7MFP_PWM1_CH0},
|
||||||
|
{PF_9, PWM_1_0, SYS_GPF_MFPH_PF9MFP_PWM1_CH0},
|
||||||
|
{PF_10, PWM_1_1, SYS_GPF_MFPH_PF10MFP_PWM1_CH1},
|
||||||
|
{PF_11, PWM_1_2, SYS_GPF_MFPH_PF11MFP_PWM1_CH2},
|
||||||
|
{PG_1, PWM_1_2, SYS_GPG_MFPL_PG1MFP_PWM1_CH2},
|
||||||
|
{PG_2, PWM_1_3, SYS_GPG_MFPL_PG2MFP_PWM1_CH3},
|
||||||
|
{PG_3, PWM_1_4, SYS_GPG_MFPL_PG3MFP_PWM1_CH4},
|
||||||
|
{PG_4, PWM_1_5, SYS_GPG_MFPL_PG4MFP_PWM1_CH5},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//*** SERIAL ***
|
||||||
|
|
||||||
|
const PinMap PinMap_UART_TX[] = {
|
||||||
|
{PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_TXD},
|
||||||
|
{PA_2, UART_0, SYS_GPA_MFPL_PA2MFP_UART0_TXD},
|
||||||
|
{PA_8, UART_3, SYS_GPA_MFPH_PA8MFP_UART3_TXD},
|
||||||
|
{PA_13, UART_2, SYS_GPA_MFPH_PA13MFP_UART2_TXD},
|
||||||
|
{PB_1, UART_2, SYS_GPB_MFPL_PB1MFP_UART2_TXD},
|
||||||
|
{PB_3, UART_1, SYS_GPB_MFPL_PB3MFP_UART1_TXD},
|
||||||
|
{PB_3, UART_3, SYS_GPB_MFPL_PB3MFP_UART3_TXD},
|
||||||
|
{PB_4, UART_2, SYS_GPB_MFPL_PB4MFP_UART2_TXD},
|
||||||
|
{PB_4, UART_4, SYS_GPB_MFPL_PB4MFP_UART4_TXD},
|
||||||
|
{PB_5, UART_5, SYS_GPB_MFPL_PB5MFP_UART5_TXD},
|
||||||
|
{PB_6, UART_4, SYS_GPB_MFPL_PB6MFP_UART4_TXD},
|
||||||
|
{PB_11, UART_5, SYS_GPB_MFPH_PB11MFP_UART5_TXD},
|
||||||
|
{PC_0, UART_3, SYS_GPC_MFPL_PC0MFP_UART3_TXD},
|
||||||
|
{PC_2, UART_2, SYS_GPC_MFPL_PC2MFP_UART2_TXD},
|
||||||
|
{PC_5, UART_4, SYS_GPC_MFPL_PC5MFP_UART4_TXD},
|
||||||
|
{PC_7, UART_0, SYS_GPC_MFPL_PC7MFP_UART0_TXD},
|
||||||
|
{PD_1, UART_0, SYS_GPD_MFPL_PD1MFP_UART0_TXD},
|
||||||
|
{PD_2, UART_3, SYS_GPD_MFPL_PD2MFP_UART3_TXD},
|
||||||
|
{PD_12, UART_3, SYS_GPD_MFPH_PD12MFP_UART3_TXD},
|
||||||
|
{PE_8, UART_1, SYS_GPE_MFPH_PE8MFP_UART1_TXD},
|
||||||
|
{PE_10, UART_3, SYS_GPE_MFPH_PE10MFP_UART3_TXD},
|
||||||
|
{PE_12, UART_1, SYS_GPE_MFPH_PE12MFP_UART1_TXD},
|
||||||
|
{PE_12, UART_4, SYS_GPE_MFPH_PE12MFP_UART4_TXD},
|
||||||
|
{PF_5, UART_3, SYS_GPF_MFPL_PF5MFP_UART3_TXD},
|
||||||
|
{PF_6, UART_0, SYS_GPF_MFPL_PF6MFP_UART0_TXD},
|
||||||
|
{PF_7, UART_3, SYS_GPF_MFPL_PF7MFP_UART3_TXD},
|
||||||
|
{PF_9, UART_3, SYS_GPF_MFPH_PF9MFP_UART3_TXD},
|
||||||
|
{PF_13, UART_5, SYS_GPF_MFPH_PF13MFP_UART5_TXD},
|
||||||
|
{PG_2, UART_2, SYS_GPG_MFPL_PG2MFP_UART2_TXD},
|
||||||
|
{PG_8, UART_0, SYS_GPG_MFPH_PG8MFP_UART0_TXD},
|
||||||
|
{PG_10, UART_5, SYS_GPG_MFPH_PG10MFP_UART5_TXD},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_UART_RX[] = {
|
||||||
|
{PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_RXD},
|
||||||
|
{PA_3, UART_0, SYS_GPA_MFPL_PA3MFP_UART0_RXD},
|
||||||
|
{PA_9, UART_3, SYS_GPA_MFPH_PA9MFP_UART3_RXD},
|
||||||
|
{PA_12, UART_2, SYS_GPA_MFPH_PA12MFP_UART2_RXD},
|
||||||
|
{PB_0, UART_2, SYS_GPB_MFPL_PB0MFP_UART2_RXD},
|
||||||
|
{PB_2, UART_1, SYS_GPB_MFPL_PB2MFP_UART1_RXD},
|
||||||
|
{PB_2, UART_3, SYS_GPB_MFPL_PB2MFP_UART3_RXD},
|
||||||
|
{PB_5, UART_2, SYS_GPB_MFPL_PB5MFP_UART2_RXD},
|
||||||
|
{PB_7, UART_4, SYS_GPB_MFPL_PB7MFP_UART4_RXD},
|
||||||
|
{PB_8, UART_4, SYS_GPB_MFPH_PB8MFP_UART4_RXD},
|
||||||
|
{PB_12, UART_5, SYS_GPB_MFPH_PB12MFP_UART5_RXD},
|
||||||
|
{PB_15, UART_5, SYS_GPB_MFPH_PB15MFP_UART5_RXD},
|
||||||
|
{PC_1, UART_3, SYS_GPC_MFPL_PC1MFP_UART3_RXD},
|
||||||
|
{PC_3, UART_2, SYS_GPC_MFPL_PC3MFP_UART2_RXD},
|
||||||
|
{PC_6, UART_0, SYS_GPC_MFPL_PC6MFP_UART0_RXD},
|
||||||
|
{PC_6, UART_4, SYS_GPC_MFPL_PC6MFP_UART4_RXD},
|
||||||
|
{PD_0, UART_0, SYS_GPD_MFPL_PD0MFP_UART0_RXD},
|
||||||
|
{PD_0, UART_5, SYS_GPD_MFPL_PD0MFP_UART5_RXD},
|
||||||
|
{PD_1, UART_5, SYS_GPD_MFPL_PD1MFP_UART5_RXD},
|
||||||
|
{PD_3, UART_3, SYS_GPD_MFPL_PD3MFP_UART3_RXD},
|
||||||
|
{PD_6, UART_0, SYS_GPD_MFPL_PD6MFP_UART0_RXD},
|
||||||
|
{PD_13, UART_3, SYS_GPD_MFPH_PD13MFP_UART3_RXD},
|
||||||
|
{PE_0, UART_4, SYS_GPE_MFPL_PE0MFP_UART4_RXD},
|
||||||
|
{PE_1, UART_1, SYS_GPE_MFPL_PE1MFP_UART1_RXD},
|
||||||
|
{PE_9, UART_1, SYS_GPE_MFPH_PE9MFP_UART1_RXD},
|
||||||
|
{PE_11, UART_3, SYS_GPE_MFPH_PE11MFP_UART3_RXD},
|
||||||
|
{PE_13, UART_1, SYS_GPE_MFPH_PE13MFP_UART1_RXD},
|
||||||
|
{PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_RXD},
|
||||||
|
{PF_5, UART_0, SYS_GPF_MFPL_PF5MFP_UART0_RXD},
|
||||||
|
{PF_6, UART_3, SYS_GPF_MFPL_PF6MFP_UART3_RXD},
|
||||||
|
{PF_10, UART_3, SYS_GPF_MFPH_PF10MFP_UART3_RXD},
|
||||||
|
{PF_12, UART_5, SYS_GPF_MFPH_PF12MFP_UART5_RXD},
|
||||||
|
{PG_1, UART_2, SYS_GPG_MFPL_PG1MFP_UART2_RXD},
|
||||||
|
{PG_7, UART_0, SYS_GPG_MFPL_PG7MFP_UART0_RXD},
|
||||||
|
{PG_9, UART_5, SYS_GPG_MFPH_PG9MFP_UART5_RXD},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_UART_RTS[] = {
|
||||||
|
{PA_1, UART_1, SYS_GPA_MFPL_PA1MFP_UART1_nRTS},
|
||||||
|
{PA_3, UART_0, SYS_GPA_MFPL_PA3MFP_UART0_nRTS},
|
||||||
|
{PA_11, UART_3, SYS_GPA_MFPH_PA11MFP_UART3_nRTS},
|
||||||
|
{PA_15, UART_2, SYS_GPA_MFPH_PA15MFP_UART2_nRTS},
|
||||||
|
{PB_8, UART_1, SYS_GPB_MFPH_PB8MFP_UART1_nRTS},
|
||||||
|
{PB_9, UART_5, SYS_GPB_MFPH_PB9MFP_UART5_nRTS},
|
||||||
|
{PB_12, UART_4, SYS_GPB_MFPH_PB12MFP_UART4_nRTS},
|
||||||
|
{PC_1, UART_2, SYS_GPC_MFPL_PC1MFP_UART2_nRTS},
|
||||||
|
{PC_7, UART_4, SYS_GPC_MFPL_PC7MFP_UART4_nRTS},
|
||||||
|
{PD_15, UART_3, SYS_GPD_MFPH_PD15MFP_UART3_nRTS},
|
||||||
|
{PE_8, UART_4, SYS_GPE_MFPH_PE8MFP_UART4_nRTS},
|
||||||
|
{PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nRTS},
|
||||||
|
{PF_15, UART_5, SYS_GPF_MFPH_PF15MFP_UART5_nRTS},
|
||||||
|
{PG_4, UART_2, SYS_GPG_MFPL_PG4MFP_UART2_nRTS},
|
||||||
|
{PG_12, UART_5, SYS_GPG_MFPH_PG12MFP_UART5_nRTS},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_UART_CTS[] = {
|
||||||
|
{PA_0, UART_1, SYS_GPA_MFPL_PA0MFP_UART1_nCTS},
|
||||||
|
{PA_2, UART_0, SYS_GPA_MFPL_PA2MFP_UART0_nCTS},
|
||||||
|
{PA_10, UART_3, SYS_GPA_MFPH_PA10MFP_UART3_nCTS},
|
||||||
|
{PA_14, UART_2, SYS_GPA_MFPH_PA14MFP_UART2_nCTS},
|
||||||
|
{PB_4, UART_1, SYS_GPB_MFPL_PB4MFP_UART1_nCTS},
|
||||||
|
{PB_10, UART_5, SYS_GPB_MFPH_PB10MFP_UART5_nCTS},
|
||||||
|
{PB_11, UART_4, SYS_GPB_MFPH_PB11MFP_UART4_nCTS},
|
||||||
|
{PC_0, UART_2, SYS_GPC_MFPL_PC0MFP_UART2_nCTS},
|
||||||
|
{PC_4, UART_4, SYS_GPC_MFPL_PC4MFP_UART4_nCTS},
|
||||||
|
{PD_14, UART_3, SYS_GPD_MFPH_PD14MFP_UART3_nCTS},
|
||||||
|
{PE_9, UART_4, SYS_GPE_MFPH_PE9MFP_UART4_nCTS},
|
||||||
|
{PE_10, UART_1, SYS_GPE_MFPH_PE10MFP_UART1_nCTS},
|
||||||
|
{PF_11, UART_3, SYS_GPF_MFPH_PF11MFP_UART3_nCTS},
|
||||||
|
{PF_14, UART_5, SYS_GPF_MFPH_PF14MFP_UART5_nCTS},
|
||||||
|
{PG_3, UART_2, SYS_GPG_MFPL_PG3MFP_UART2_nCTS},
|
||||||
|
{PG_11, UART_5, SYS_GPG_MFPH_PG11MFP_UART5_nCTS},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
//*** SPI ***
|
||||||
|
|
||||||
|
const PinMap PinMap_SPI_MOSI[] = {
|
||||||
|
{PA_1, SPI_5, SYS_GPA_MFPL_PA1MFP_SPI5_MOSI},
|
||||||
|
{PA_3, SPI_3, SYS_GPA_MFPL_PA3MFP_SPI3_MOSI},
|
||||||
|
{PA_5, SPI_1, SYS_GPA_MFPL_PA5MFP_SPI1_MOSI},
|
||||||
|
{PA_15, SPI_1, SYS_GPA_MFPH_PA15MFP_SPI1_MOSI},
|
||||||
|
{PB_0, SPI_0, SYS_GPB_MFPL_PB0MFP_SPI0_MOSI1},
|
||||||
|
{PB_1, SPI_1, SYS_GPB_MFPL_PB1MFP_SPI1_MOSI},
|
||||||
|
{PB_5, SPI_0, SYS_GPB_MFPL_PB5MFP_SPI0_MOSI0},
|
||||||
|
{PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MOSI},
|
||||||
|
{PB_12, SPI_4, SYS_GPB_MFPH_PB12MFP_SPI4_MOSI},
|
||||||
|
{PC_1, SPI_0, SYS_GPC_MFPL_PC1MFP_SPI0_MOSI1},
|
||||||
|
{PC_3, SPI_0, SYS_GPC_MFPL_PC3MFP_SPI0_MOSI0},
|
||||||
|
{PC_3, SPI_2, SYS_GPC_MFPL_PC3MFP_SPI2_MOSI},
|
||||||
|
{PC_3, SPI_5, SYS_GPC_MFPL_PC3MFP_SPI5_MOSI},
|
||||||
|
{PC_6, SPI_5, SYS_GPC_MFPL_PC6MFP_SPI5_MOSI},
|
||||||
|
{PC_10, SPI_2, SYS_GPC_MFPH_PC10MFP_SPI2_MOSI},
|
||||||
|
{PD_9, SPI_2, SYS_GPD_MFPH_PD9MFP_SPI2_MOSI},
|
||||||
|
{PD_11, SPI_1, SYS_GPD_MFPH_PD11MFP_SPI1_MOSI},
|
||||||
|
{PD_13, SPI_2, SYS_GPD_MFPH_PD13MFP_SPI2_MOSI},
|
||||||
|
{PE_3, SPI_1, SYS_GPE_MFPL_PE3MFP_SPI1_MOSI},
|
||||||
|
{PE_9, SPI_0, SYS_GPE_MFPH_PE9MFP_SPI0_MOSI1},
|
||||||
|
{PE_11, SPI_0, SYS_GPE_MFPH_PE11MFP_SPI0_MOSI0},
|
||||||
|
{PE_11, SPI_1, SYS_GPE_MFPH_PE11MFP_SPI1_MOSI},
|
||||||
|
{PE_13, SPI_5, SYS_GPE_MFPH_PE13MFP_SPI5_MOSI},
|
||||||
|
{PF_1, SPI_1, SYS_GPF_MFPL_PF1MFP_SPI1_MOSI},
|
||||||
|
{PF_10, SPI_2, SYS_GPF_MFPH_PF10MFP_SPI2_MOSI},
|
||||||
|
{PF_13, SPI_1, SYS_GPF_MFPH_PF13MFP_SPI1_MOSI},
|
||||||
|
{PG_2, SPI_0, SYS_GPG_MFPL_PG2MFP_SPI0_MOSI0},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_SPI_MISO[] = {
|
||||||
|
{PA_0, SPI_3, SYS_GPA_MFPL_PA0MFP_SPI3_MISO},
|
||||||
|
{PA_0, SPI_5, SYS_GPA_MFPL_PA0MFP_SPI5_MISO},
|
||||||
|
{PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_MISO},
|
||||||
|
{PA_14, SPI_1, SYS_GPA_MFPH_PA14MFP_SPI1_MISO},
|
||||||
|
{PB_1, SPI_0, SYS_GPB_MFPL_PB1MFP_SPI0_MISO1},
|
||||||
|
{PB_3, SPI_0, SYS_GPB_MFPL_PB3MFP_SPI0_MISO0},
|
||||||
|
{PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_MISO},
|
||||||
|
{PB_6, SPI_0, SYS_GPB_MFPL_PB6MFP_SPI0_MISO0},
|
||||||
|
{PB_6, SPI_1, SYS_GPB_MFPL_PB6MFP_SPI1_MISO},
|
||||||
|
{PB_11, SPI_4, SYS_GPB_MFPH_PB11MFP_SPI4_MISO},
|
||||||
|
{PC_0, SPI_0, SYS_GPC_MFPL_PC0MFP_SPI0_MISO1},
|
||||||
|
{PC_2, SPI_0, SYS_GPC_MFPL_PC2MFP_SPI0_MISO0},
|
||||||
|
{PC_2, SPI_5, SYS_GPC_MFPL_PC2MFP_SPI5_MISO},
|
||||||
|
{PC_4, SPI_2, SYS_GPC_MFPL_PC4MFP_SPI2_MISO},
|
||||||
|
{PC_7, SPI_5, SYS_GPC_MFPL_PC7MFP_SPI5_MISO},
|
||||||
|
{PC_11, SPI_2, SYS_GPC_MFPH_PC11MFP_SPI2_MISO},
|
||||||
|
{PD_1, SPI_2, SYS_GPD_MFPL_PD1MFP_SPI2_MISO},
|
||||||
|
{PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_MISO},
|
||||||
|
{PD_12, SPI_1, SYS_GPD_MFPH_PD12MFP_SPI1_MISO},
|
||||||
|
{PD_14, SPI_2, SYS_GPD_MFPH_PD14MFP_SPI2_MISO},
|
||||||
|
{PE_2, SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MISO},
|
||||||
|
{PE_8, SPI_0, SYS_GPE_MFPH_PE8MFP_SPI0_MISO1},
|
||||||
|
{PE_10, SPI_0, SYS_GPE_MFPH_PE10MFP_SPI0_MISO0},
|
||||||
|
{PE_10, SPI_1, SYS_GPE_MFPH_PE10MFP_SPI1_MISO},
|
||||||
|
{PE_12, SPI_5, SYS_GPE_MFPH_PE12MFP_SPI5_MISO},
|
||||||
|
{PF_7, SPI_1, SYS_GPF_MFPL_PF7MFP_SPI1_MISO},
|
||||||
|
{PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MISO},
|
||||||
|
{PF_12, SPI_1, SYS_GPF_MFPH_PF12MFP_SPI1_MISO},
|
||||||
|
{PG_1, SPI_0, SYS_GPG_MFPL_PG1MFP_SPI0_MISO0},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_SPI_SCLK[] = {
|
||||||
|
{PA_0, SPI_1, SYS_GPA_MFPL_PA0MFP_SPI1_I2SMCLK},
|
||||||
|
{PA_1, SPI_3, SYS_GPA_MFPL_PA1MFP_SPI3_CLK},
|
||||||
|
{PA_3, SPI_5, SYS_GPA_MFPL_PA3MFP_SPI5_CLK},
|
||||||
|
{PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK},
|
||||||
|
{PA_12, SPI_1, SYS_GPA_MFPH_PA12MFP_SPI1_I2SMCLK},
|
||||||
|
{PA_12, SPI_2, SYS_GPA_MFPH_PA12MFP_SPI2_I2SMCLK},
|
||||||
|
{PA_12, SPI_3, SYS_GPA_MFPH_PA12MFP_SPI3_I2SMCLK},
|
||||||
|
{PA_13, SPI_1, SYS_GPA_MFPH_PA13MFP_SPI1_CLK},
|
||||||
|
{PB_2, SPI_0, SYS_GPB_MFPL_PB2MFP_SPI0_CLK},
|
||||||
|
{PB_2, SPI_1, SYS_GPB_MFPL_PB2MFP_SPI1_CLK},
|
||||||
|
{PB_4, SPI_4, SYS_GPB_MFPL_PB4MFP_SPI4_CLK},
|
||||||
|
{PB_7, SPI_0, SYS_GPB_MFPL_PB7MFP_SPI0_CLK},
|
||||||
|
{PB_7, SPI_1, SYS_GPB_MFPL_PB7MFP_SPI1_CLK},
|
||||||
|
{PB_9, SPI_4, SYS_GPB_MFPH_PB9MFP_SPI4_I2SMCLK},
|
||||||
|
{PB_10, SPI_4, SYS_GPB_MFPH_PB10MFP_SPI4_CLK},
|
||||||
|
{PC_0, SPI_2, SYS_GPC_MFPL_PC0MFP_SPI2_CLK},
|
||||||
|
{PC_1, SPI_2, SYS_GPC_MFPL_PC1MFP_SPI2_I2SMCLK},
|
||||||
|
{PC_4, SPI_0, SYS_GPC_MFPL_PC4MFP_SPI0_CLK},
|
||||||
|
{PC_4, SPI_5, SYS_GPC_MFPL_PC4MFP_SPI5_CLK},
|
||||||
|
{PC_5, SPI_2, SYS_GPC_MFPL_PC5MFP_SPI2_I2SMCLK},
|
||||||
|
{PC_8, SPI_2, SYS_GPC_MFPH_PC8MFP_SPI2_I2SMCLK},
|
||||||
|
{PC_9, SPI_2, SYS_GPC_MFPH_PC9MFP_SPI2_I2SMCLK},
|
||||||
|
{PC_12, SPI_2, SYS_GPC_MFPH_PC12MFP_SPI2_CLK},
|
||||||
|
{PC_15, SPI_3, SYS_GPC_MFPH_PC15MFP_SPI3_I2SMCLK},
|
||||||
|
{PD_0, SPI_1, SYS_GPD_MFPL_PD0MFP_SPI1_I2SMCLK},
|
||||||
|
{PD_1, SPI_3, SYS_GPD_MFPL_PD1MFP_SPI3_I2SMCLK},
|
||||||
|
{PD_2, SPI_2, SYS_GPD_MFPL_PD2MFP_SPI2_CLK},
|
||||||
|
{PD_3, SPI_1, SYS_GPD_MFPL_PD3MFP_SPI1_I2SMCLK},
|
||||||
|
{PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_CLK},
|
||||||
|
{PD_10, SPI_1, SYS_GPD_MFPH_PD10MFP_SPI1_CLK},
|
||||||
|
{PD_15, SPI_2, SYS_GPD_MFPH_PD15MFP_SPI2_CLK},
|
||||||
|
{PE_0, SPI_0, SYS_GPE_MFPL_PE0MFP_SPI0_CLK},
|
||||||
|
{PE_0, SPI_2, SYS_GPE_MFPL_PE0MFP_SPI2_CLK},
|
||||||
|
{PE_5, SPI_5, SYS_GPE_MFPL_PE5MFP_SPI5_CLK},
|
||||||
|
{PE_9, SPI_1, SYS_GPE_MFPH_PE9MFP_SPI1_I2SMCLK},
|
||||||
|
{PE_11, SPI_5, SYS_GPE_MFPH_PE11MFP_SPI5_CLK},
|
||||||
|
{PE_13, SPI_0, SYS_GPE_MFPH_PE13MFP_SPI0_CLK},
|
||||||
|
{PE_13, SPI_1, SYS_GPE_MFPH_PE13MFP_SPI1_CLK},
|
||||||
|
{PF_2, SPI_1, SYS_GPF_MFPL_PF2MFP_SPI1_CLK},
|
||||||
|
{PF_7, SPI_2, SYS_GPF_MFPL_PF7MFP_SPI2_I2SMCLK},
|
||||||
|
{PF_8, SPI_2, SYS_GPF_MFPH_PF8MFP_SPI2_CLK},
|
||||||
|
{PF_15, SPI_1, SYS_GPF_MFPH_PF15MFP_SPI1_CLK},
|
||||||
|
{PG_3, SPI_0, SYS_GPG_MFPL_PG3MFP_SPI0_CLK},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_SPI_SSEL[] = {
|
||||||
|
{PA_2, SPI_3, SYS_GPA_MFPL_PA2MFP_SPI3_SS},
|
||||||
|
{PA_2, SPI_5, SYS_GPA_MFPL_PA2MFP_SPI5_SS},
|
||||||
|
{PA_4, SPI_1, SYS_GPA_MFPL_PA4MFP_SPI1_SS},
|
||||||
|
{PB_0, SPI_1, SYS_GPB_MFPL_PB0MFP_SPI1_SS},
|
||||||
|
{PB_4, SPI_0, SYS_GPB_MFPL_PB4MFP_SPI0_SS},
|
||||||
|
{PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_SS},
|
||||||
|
{PB_8, SPI_4, SYS_GPB_MFPH_PB8MFP_SPI4_SS},
|
||||||
|
{PB_15, SPI_1, SYS_GPB_MFPH_PB15MFP_SPI1_SS},
|
||||||
|
{PC_2, SPI_2, SYS_GPC_MFPL_PC2MFP_SPI2_SS},
|
||||||
|
{PC_5, SPI_0, SYS_GPC_MFPL_PC5MFP_SPI0_SS},
|
||||||
|
{PC_5, SPI_5, SYS_GPC_MFPL_PC5MFP_SPI5_SS},
|
||||||
|
{PC_13, SPI_2, SYS_GPC_MFPH_PC13MFP_SPI2_SS},
|
||||||
|
{PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_SS},
|
||||||
|
{PD_8, SPI_2, SYS_GPD_MFPH_PD8MFP_SPI2_SS},
|
||||||
|
{PD_12, SPI_2, SYS_GPD_MFPH_PD12MFP_SPI2_SS},
|
||||||
|
{PE_0, SPI_0, SYS_GPE_MFPL_PE0MFP_SPI0_SS},
|
||||||
|
{PE_4, SPI_5, SYS_GPE_MFPL_PE4MFP_SPI5_SS},
|
||||||
|
{PE_10, SPI_5, SYS_GPE_MFPH_PE10MFP_SPI5_SS},
|
||||||
|
{PE_12, SPI_0, SYS_GPE_MFPH_PE12MFP_SPI0_SS},
|
||||||
|
{PE_12, SPI_1, SYS_GPE_MFPH_PE12MFP_SPI1_SS},
|
||||||
|
{PF_0, SPI_1, SYS_GPF_MFPL_PF0MFP_SPI1_SS},
|
||||||
|
{PF_9, SPI_2, SYS_GPF_MFPH_PF9MFP_SPI2_SS},
|
||||||
|
{PF_14, SPI_1, SYS_GPF_MFPH_PF14MFP_SPI1_SS},
|
||||||
|
{PG_4, SPI_0, SYS_GPG_MFPL_PG4MFP_SPI0_SS},
|
||||||
|
{PG_8, SPI_1, SYS_GPG_MFPH_PG8MFP_SPI1_SS},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_CAN_TD[] = {
|
||||||
|
{PA_1, CAN_0, SYS_GPA_MFPL_PA1MFP_CAN0_TXD},
|
||||||
|
{PA_12, CAN_0, SYS_GPA_MFPH_PA12MFP_CAN0_TXD},
|
||||||
|
{PC_0, CAN_0, SYS_GPC_MFPL_PC0MFP_CAN0_TXD},
|
||||||
|
{PF_12, CAN_0, SYS_GPF_MFPH_PF12MFP_CAN0_TXD},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
||||||
|
const PinMap PinMap_CAN_RD[] = {
|
||||||
|
{PA_0, CAN_0, SYS_GPA_MFPL_PA0MFP_CAN0_RXD},
|
||||||
|
{PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
|
||||||
|
{PC_1, CAN_0, SYS_GPC_MFPL_PC1MFP_CAN0_RXD},
|
||||||
|
{PF_13, CAN_0, SYS_GPF_MFPH_PF13MFP_CAN0_RXD},
|
||||||
|
|
||||||
|
{NC, NC, 0}
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,77 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2016 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_PERIPHERALPINS_H
|
||||||
|
#define MBED_PERIPHERALPINS_H
|
||||||
|
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "PeripheralNames.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
//*** GPIO ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_GPIO[];
|
||||||
|
|
||||||
|
//*** ADC ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_ADC[];
|
||||||
|
|
||||||
|
//*** I2C ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_I2C_SDA[];
|
||||||
|
extern const PinMap PinMap_I2C_SCL[];
|
||||||
|
|
||||||
|
//*** PWM ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_PWM[];
|
||||||
|
|
||||||
|
//*** SERIAL ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_UART_TX[];
|
||||||
|
extern const PinMap PinMap_UART_RX[];
|
||||||
|
extern const PinMap PinMap_UART_RTS[];
|
||||||
|
extern const PinMap PinMap_UART_CTS[];
|
||||||
|
|
||||||
|
//*** SPI ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_SPI_MOSI[];
|
||||||
|
extern const PinMap PinMap_SPI_MISO[];
|
||||||
|
extern const PinMap PinMap_SPI_SCLK[];
|
||||||
|
extern const PinMap PinMap_SPI_SSEL[];
|
||||||
|
|
||||||
|
//*** SD ***
|
||||||
|
|
||||||
|
extern const PinMap PinMap_SD_CD[];
|
||||||
|
extern const PinMap PinMap_SD_CMD[];
|
||||||
|
extern const PinMap PinMap_SD_CLK[];
|
||||||
|
extern const PinMap PinMap_SD_DAT0[];
|
||||||
|
extern const PinMap PinMap_SD_DAT1[];
|
||||||
|
extern const PinMap PinMap_SD_DAT2[];
|
||||||
|
extern const PinMap PinMap_SD_DAT3[];
|
||||||
|
|
||||||
|
//*** CAN ***
|
||||||
|
|
||||||
|
extern PinMap const PinMap_CAN_TD[];
|
||||||
|
extern PinMap const PinMap_CAN_RD[];
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,133 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
#ifndef MBED_PINNAMES_H
|
||||||
|
#define MBED_PINNAMES_H
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define NU_PININDEX_Pos 0
|
||||||
|
#define NU_PININDEX_Msk (0xFFul << NU_PININDEX_Pos)
|
||||||
|
#define NU_PINPORT_Pos 8
|
||||||
|
#define NU_PINPORT_Msk (0xFul << NU_PINPORT_Pos)
|
||||||
|
#define NU_PIN_MODINDEX_Pos 12
|
||||||
|
#define NU_PIN_MODINDEX_Msk (0xFul << NU_PIN_MODINDEX_Pos)
|
||||||
|
#define NU_PIN_BIND_Pos 16
|
||||||
|
#define NU_PIN_BIND_Msk (0x1ul << NU_PIN_BIND_Pos)
|
||||||
|
|
||||||
|
#define NU_PININDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PININDEX_Msk) >> NU_PININDEX_Pos)
|
||||||
|
#define NU_PINPORT(PINNAME) (((unsigned int)(PINNAME) & NU_PINPORT_Msk) >> NU_PINPORT_Pos)
|
||||||
|
#define NU_PIN_BIND(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_BIND_Msk) >> NU_PIN_BIND_Pos)
|
||||||
|
#define NU_PIN_MODINDEX(PINNAME) (((unsigned int)(PINNAME) & NU_PIN_MODINDEX_Msk) >> NU_PIN_MODINDEX_Pos)
|
||||||
|
#define NU_PINNAME(PORT, PIN) ((((unsigned int) (PORT)) << (NU_PINPORT_Pos)) | (((unsigned int) (PIN)) << NU_PININDEX_Pos))
|
||||||
|
#define NU_PINNAME_BIND(PINNAME, modname) NU_PINNAME_BIND_(NU_PINPORT(PINNAME), NU_PININDEX(PINNAME), modname)
|
||||||
|
#define NU_PINNAME_BIND_(PORT, PIN, modname) ((((unsigned int)(PORT)) << NU_PINPORT_Pos) | (((unsigned int)(PIN)) << NU_PININDEX_Pos) | (NU_MODINDEX(modname) << NU_PIN_MODINDEX_Pos) | NU_PIN_BIND_Msk)
|
||||||
|
|
||||||
|
#define NU_PORT_BASE(port) ((GPIO_T *)(((uint32_t) GPIOA_BASE) + 0x40 * port))
|
||||||
|
#define NU_MFP_POS(pin) ((pin % 8) * 4)
|
||||||
|
#define NU_MFP_MSK(pin) (0xful << NU_MFP_POS(pin))
|
||||||
|
|
||||||
|
// LEGACY
|
||||||
|
#define NU_PINNAME_TO_PIN(PINNAME) NU_PININDEX(PINNAME)
|
||||||
|
#define NU_PINNAME_TO_PORT(PINNAME) NU_PINPORT(PINNAME)
|
||||||
|
#define NU_PINNAME_TO_MODSUBINDEX(PINNAME) NU_PIN_MODINDEX(PINNAME)
|
||||||
|
#define NU_PORT_N_PIN_TO_PINNAME(PORT, PIN) NU_PINNAME((PORT), (PIN))
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
PIN_INPUT,
|
||||||
|
PIN_OUTPUT
|
||||||
|
} PinDirection;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
PullNone = 0,
|
||||||
|
PullDown,
|
||||||
|
PullUp,
|
||||||
|
|
||||||
|
PushPull,
|
||||||
|
OpenDrain,
|
||||||
|
Quasi,
|
||||||
|
|
||||||
|
PullDefault = PullUp,
|
||||||
|
} PinMode;
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
// Not connected
|
||||||
|
NC = (int)0xFFFFFFFF,
|
||||||
|
|
||||||
|
// Generic naming
|
||||||
|
PA_0 = NU_PORT_N_PIN_TO_PINNAME(0, 0), PA_1, PA_2, PA_3, PA_4, PA_5, PA_6, PA_7, PA_8, PA_9, PA_10, PA_11, PA_12, PA_13, PA_14, PA_15,
|
||||||
|
PB_0 = NU_PORT_N_PIN_TO_PINNAME(1, 0), PB_1, PB_2, PB_3, PB_4, PB_5, PB_6, PB_7, PB_8, PB_9, PB_10, PB_11, PB_12, PB_13, PB_14, PB_15,
|
||||||
|
PC_0 = NU_PORT_N_PIN_TO_PINNAME(2, 0), PC_1, PC_2, PC_3, PC_4, PC_5, PC_6, PC_7, PC_8, PC_9, PC_10, PC_11, PC_12, PC_13, PC_14, PC_15,
|
||||||
|
PD_0 = NU_PORT_N_PIN_TO_PINNAME(3, 0), PD_1, PD_2, PD_3, PD_4, PD_5, PD_6, PD_7, PD_8, PD_9, PD_10, PD_11, PD_12, PD_13, PD_14, PD_15,
|
||||||
|
PE_0 = NU_PORT_N_PIN_TO_PINNAME(4, 0), PE_1, PE_2, PE_3, PE_4, PE_5, PE_6, PE_7, PE_8, PE_9, PE_10, PE_11, PE_12, PE_13,
|
||||||
|
PF_0 = NU_PORT_N_PIN_TO_PINNAME(5, 0), PF_1, PF_2, PF_3, PF_4, PF_5, PF_6, PF_7, PF_8, PF_9, PF_10, PF_11, PF_12, PF_13, PF_14, PF_15,
|
||||||
|
PG_0 = NU_PORT_N_PIN_TO_PINNAME(6, 0), PG_1, PG_2, PG_3, PG_4, PG_5, PG_6, PG_7, PG_8, PG_9, PG_10, PG_11, PG_12,
|
||||||
|
|
||||||
|
// Arduino UNO naming
|
||||||
|
A0 = PB_2,
|
||||||
|
A1 = PB_3,
|
||||||
|
A2 = PB_8,
|
||||||
|
A3 = PB_9,
|
||||||
|
A4 = PB_10,
|
||||||
|
A5 = PB_11,
|
||||||
|
A6 = PB_12,
|
||||||
|
A7 = PB_13,
|
||||||
|
|
||||||
|
D0 = PB_7,
|
||||||
|
D1 = PB_6,
|
||||||
|
D2 = PC_0,
|
||||||
|
D3 = PC_1,
|
||||||
|
D4 = PC_2,
|
||||||
|
D5 = PC_3,
|
||||||
|
D6 = PC_4,
|
||||||
|
D7 = PE_0,
|
||||||
|
D8 = PC_6,
|
||||||
|
D9 = PC_7,
|
||||||
|
D10 = PG_1,
|
||||||
|
D11 = PG_2,
|
||||||
|
D12 = PG_3,
|
||||||
|
D13 = PG_4,
|
||||||
|
D14 = PE_5,
|
||||||
|
D15 = PE_4,
|
||||||
|
|
||||||
|
// FIXME: other board-specific naming
|
||||||
|
// UART naming
|
||||||
|
USBTX = PG_10,
|
||||||
|
USBRX = PG_9,
|
||||||
|
STDIO_UART_TX = USBTX,
|
||||||
|
STDIO_UART_RX = USBRX,
|
||||||
|
// LED naming
|
||||||
|
LED1 = PC_14,
|
||||||
|
LED2 = PC_14,
|
||||||
|
LED3 = PC_14,
|
||||||
|
LED4 = D0, // No real LED. Just for passing ATS.
|
||||||
|
LED_RED = LED2,
|
||||||
|
LED_GREEN = LED3,
|
||||||
|
LED_BLUE = LED1,
|
||||||
|
// Button naming
|
||||||
|
// SW2 = PA_15,
|
||||||
|
// SW3 = PA_14,
|
||||||
|
|
||||||
|
} PinName;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif // MBED_PINNAMES_H
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2016 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_PORTNAMES_H
|
||||||
|
#define MBED_PORTNAMES_H
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef enum {
|
||||||
|
PortA = 0,
|
||||||
|
PortB = 1,
|
||||||
|
PortC = 2,
|
||||||
|
PortD = 3,
|
||||||
|
PortE = 4,
|
||||||
|
PortF = 5
|
||||||
|
} PortName;
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,24 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2016 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_DEVICE_H
|
||||||
|
#define MBED_DEVICE_H
|
||||||
|
|
||||||
|
#define DEVICE_ID_LENGTH 24
|
||||||
|
|
||||||
|
#include "objects.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,78 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2016 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
// NOTE: Ensurce mbed_sdk_init() will get called before C++ global object constructor.
|
||||||
|
#if defined(__CC_ARM) || defined(__GNUC__)
|
||||||
|
void mbed_sdk_init_forced(void) __attribute__((constructor(101)));
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
// TODO: How to achieve it in IAR?
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
void mbed_sdk_init(void)
|
||||||
|
{
|
||||||
|
// NOTE: Support singleton semantics to be called from other init functions
|
||||||
|
static int inited = 0;
|
||||||
|
if (inited) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
inited = 1;
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Init System Clock */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Unlock protected registers */
|
||||||
|
SYS_UnlockReg();
|
||||||
|
|
||||||
|
/* Enable HIRC clock (Internal RC 22.1184MHz) */
|
||||||
|
CLK_EnableXtalRC(CLK_PWRCTL_HIRCEN_Msk);
|
||||||
|
/* Enable HXT clock (external XTAL 12MHz) */
|
||||||
|
CLK_EnableXtalRC(CLK_PWRCTL_HXTEN_Msk);
|
||||||
|
/* Enable LIRC for lp_ticker */
|
||||||
|
CLK_EnableXtalRC(CLK_PWRCTL_LIRCEN_Msk);
|
||||||
|
/* Enable LXT for RTC */
|
||||||
|
CLK_EnableXtalRC(CLK_PWRCTL_LXTEN_Msk);
|
||||||
|
|
||||||
|
/* Wait for HIRC clock ready */
|
||||||
|
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
|
||||||
|
/* Wait for HXT clock ready */
|
||||||
|
CLK_WaitClockReady(CLK_STATUS_HXTSTB_Msk);
|
||||||
|
/* Wait for LIRC clock ready */
|
||||||
|
CLK_WaitClockReady(CLK_STATUS_LIRCSTB_Msk);
|
||||||
|
/* Wait for LXT clock ready */
|
||||||
|
CLK_WaitClockReady(CLK_STATUS_LXTSTB_Msk);
|
||||||
|
|
||||||
|
/* Select HCLK clock source as HIRC and HCLK clock divider as 1 */
|
||||||
|
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_HIRC, CLK_CLKDIV0_HCLK(1));
|
||||||
|
|
||||||
|
/* Set core clock as 48M from PLL */
|
||||||
|
CLK_SetCoreClock(FREQ_48MHZ);
|
||||||
|
|
||||||
|
|
||||||
|
/* Update System Core Clock */
|
||||||
|
/* User can use SystemCoreClockUpdate() to calculate SystemCoreClock. */
|
||||||
|
SystemCoreClockUpdate();
|
||||||
|
|
||||||
|
/* Lock protected registers */
|
||||||
|
SYS_LockReg();
|
||||||
|
}
|
||||||
|
|
||||||
|
void mbed_sdk_init_forced(void)
|
||||||
|
{
|
||||||
|
mbed_sdk_init();
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,121 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2017 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_OBJECTS_H
|
||||||
|
#define MBED_OBJECTS_H
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "PortNames.h"
|
||||||
|
#include "PeripheralNames.h"
|
||||||
|
#include "PinNames.h"
|
||||||
|
#include "dma_api.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
struct gpio_irq_s {
|
||||||
|
PinName pin;
|
||||||
|
uint32_t irq_handler;
|
||||||
|
uint32_t irq_id;
|
||||||
|
struct gpio_irq_s *next;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct port_s {
|
||||||
|
PortName port;
|
||||||
|
uint32_t mask;
|
||||||
|
PinDirection direction;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct analogin_s {
|
||||||
|
ADCName adc;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct serial_s {
|
||||||
|
UARTName uart;
|
||||||
|
PinName pin_tx;
|
||||||
|
PinName pin_rx;
|
||||||
|
|
||||||
|
uint32_t baudrate;
|
||||||
|
uint32_t databits;
|
||||||
|
uint32_t parity;
|
||||||
|
uint32_t stopbits;
|
||||||
|
|
||||||
|
void (*vec)(void);
|
||||||
|
uint32_t irq_handler;
|
||||||
|
uint32_t irq_id;
|
||||||
|
uint32_t irq_en;
|
||||||
|
uint32_t inten_msk;
|
||||||
|
|
||||||
|
// Async transfer related fields
|
||||||
|
DMAUsage dma_usage_tx;
|
||||||
|
DMAUsage dma_usage_rx;
|
||||||
|
int dma_chn_id_tx;
|
||||||
|
int dma_chn_id_rx;
|
||||||
|
uint32_t event;
|
||||||
|
void (*irq_handler_tx_async)(void);
|
||||||
|
void (*irq_handler_rx_async)(void);
|
||||||
|
};
|
||||||
|
|
||||||
|
struct spi_s {
|
||||||
|
SPIName spi;
|
||||||
|
PinName pin_miso;
|
||||||
|
PinName pin_mosi;
|
||||||
|
PinName pin_sclk;
|
||||||
|
PinName pin_ssel;
|
||||||
|
|
||||||
|
// Async transfer related fields
|
||||||
|
DMAUsage dma_usage;
|
||||||
|
int dma_chn_id_tx;
|
||||||
|
int dma_chn_id_rx;
|
||||||
|
uint32_t event;
|
||||||
|
uint32_t hdlr_async;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct i2c_s {
|
||||||
|
I2CName i2c;
|
||||||
|
int slaveaddr_state;
|
||||||
|
|
||||||
|
uint32_t tran_ctrl;
|
||||||
|
char * tran_beg;
|
||||||
|
char * tran_pos;
|
||||||
|
char * tran_end;
|
||||||
|
int inten;
|
||||||
|
|
||||||
|
// Async transfer related fields
|
||||||
|
DMAUsage dma_usage;
|
||||||
|
uint32_t event;
|
||||||
|
int stop;
|
||||||
|
uint32_t address;
|
||||||
|
uint32_t hdlr_async;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct pwmout_s {
|
||||||
|
PWMName pwm;
|
||||||
|
uint32_t period_us;
|
||||||
|
uint32_t pulsewidth_us;
|
||||||
|
};
|
||||||
|
|
||||||
|
struct sleep_s {
|
||||||
|
int powerdown;
|
||||||
|
};
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include "gpio_object.h"
|
||||||
|
|
||||||
|
#endif
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,32 @@
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
AREA |.text|, CODE, READONLY
|
||||||
|
__PC PROC
|
||||||
|
EXPORT __PC
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
SECTION .text:CODE:REORDER:NOROOT(1)
|
||||||
|
PUBLIC __PC
|
||||||
|
__PC
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
.text
|
||||||
|
.thumb
|
||||||
|
.thumb_func
|
||||||
|
.globl __PC
|
||||||
|
.type __PC, %function
|
||||||
|
__PC:
|
||||||
|
#endif
|
||||||
|
|
||||||
|
MOV r0, lr
|
||||||
|
BLX lr
|
||||||
|
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
ALIGN
|
||||||
|
END
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
ALIGNROM
|
||||||
|
END
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
.align
|
||||||
|
.pool
|
||||||
|
.size __PC, . - __PC
|
||||||
|
.end
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file acmp.c
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/07/07 7:50p $
|
||||||
|
* @brief Analog Comparator(ACMP) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ACMP_Driver ACMP Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the specified ACMP module
|
||||||
|
*
|
||||||
|
* @param[in] Acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum Comparator number.
|
||||||
|
* @param[in] u32NegSrc Comparator negative input selection. Including:
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_PIN
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_CRV
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_VBG
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_DAC
|
||||||
|
* @param[in] u32HysSel The hysteresis function option. Including:
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_30MV
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_20MV
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_10MV
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Configure hysteresis function, select the source of negative input and enable analog comparator.
|
||||||
|
*/
|
||||||
|
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysSel)
|
||||||
|
{
|
||||||
|
acmp->CTL[u32ChNum] = (acmp->CTL[u32ChNum] & (~(ACMP_CTL_NEGSEL_Msk | ACMP_CTL_HYSSEL_Msk))) | (u32NegSrc | u32HysSel | ACMP_CTL_ACMPEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Close analog comparator
|
||||||
|
*
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum Comparator number.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
|
||||||
|
*/
|
||||||
|
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum)
|
||||||
|
{
|
||||||
|
acmp->CTL[u32ChNum] &= (~ACMP_CTL_ACMPEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ACMP_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,389 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file ACMP.h
|
||||||
|
* @version V0.10
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/07/07 7:50p $
|
||||||
|
* @brief M0564 Series ACMP Driver Header File
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __ACMP_H__
|
||||||
|
#define __ACMP_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ACMP_Driver ACMP Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup ACMP_EXPORTED_CONSTANTS ACMP Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* ACMP_CTL constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define ACMP_CTL_FILTSEL_OFF (0UL << 13) /*!< ACMP_CTL setting for filter function disabled. */
|
||||||
|
#define ACMP_CTL_FILTSEL_1PCLK (1UL << 13) /*!< ACMP_CTL setting for 1 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_FILTSEL_2PCLK (2UL << 13) /*!< ACMP_CTL setting for 2 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_FILTSEL_4PCLK (3UL << 13) /*!< ACMP_CTL setting for 4 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_FILTSEL_8PCLK (4UL << 13) /*!< ACMP_CTL setting for 8 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_FILTSEL_16PCLK (5UL << 13) /*!< ACMP_CTL setting for 16 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_FILTSEL_32PCLK (6UL << 13) /*!< ACMP_CTL setting for 32 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_FILTSEL_64PCLK (7UL << 13) /*!< ACMP_CTL setting for 64 PCLK filter count. */
|
||||||
|
#define ACMP_CTL_INTPOL_RF (0UL << 8) /*!< ACMP_CTL setting for selecting rising edge and falling edge as interrupt condition. */
|
||||||
|
#define ACMP_CTL_INTPOL_R (1UL << 8) /*!< ACMP_CTL setting for selecting rising edge as interrupt condition. */
|
||||||
|
#define ACMP_CTL_INTPOL_F (2UL << 8) /*!< ACMP_CTL setting for selecting falling edge as interrupt condition. */
|
||||||
|
#define ACMP_CTL_POSSEL_P0 (0UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P0 pin as the source of ACMP V+. */
|
||||||
|
#define ACMP_CTL_POSSEL_P1 (1UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P1 pin as the source of ACMP V+. */
|
||||||
|
#define ACMP_CTL_POSSEL_P2 (2UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P2 pin as the source of ACMP V+. */
|
||||||
|
#define ACMP_CTL_POSSEL_P3 (3UL << 6) /*!< ACMP_CTL setting for selecting ACMPx_P3 pin as the source of ACMP V+. */
|
||||||
|
#define ACMP_CTL_NEGSEL_PIN (0UL << 4) /*!< ACMP_CTL setting for selecting the voltage of ACMP negative input pin as the source of ACMP V-. */
|
||||||
|
#define ACMP_CTL_NEGSEL_CRV (1UL << 4) /*!< ACMP_CTL setting for selecting internal comparator reference voltage as the source of ACMP V-. */
|
||||||
|
#define ACMP_CTL_NEGSEL_VBG (2UL << 4) /*!< ACMP_CTL setting for selecting internal Band-gap voltage as the source of ACMP V-. */
|
||||||
|
#define ACMP_CTL_NEGSEL_DAC (3UL << 4) /*!< ACMP_CTL setting for selecting DAC output voltage as the source of ACMP V-. */
|
||||||
|
#define ACMP_CTL_HYSTERESIS_30MV (3UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 30mV. */
|
||||||
|
#define ACMP_CTL_HYSTERESIS_20MV (2UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 20mV. */
|
||||||
|
#define ACMP_CTL_HYSTERESIS_10MV (1UL << 24) /*!< ACMP_CTL setting for enabling the hysteresis function at 10mV. */
|
||||||
|
#define ACMP_CTL_HYSTERESIS_DISABLE (0UL << 2) /*!< ACMP_CTL setting for disabling the hysteresis function. */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* ACMP_VREF constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define ACMP_VREF_CRVSSEL_VDDA (0UL << 6) /*!< ACMP_VREF setting for selecting analog supply voltage VDDA as the CRV source voltage */
|
||||||
|
#define ACMP_VREF_CRVSSEL_INTVREF (1UL << 6) /*!< ACMP_VREF setting for selecting internal reference voltage as the CRV source voltage */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ACMP_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup ACMP_EXPORTED_FUNCTIONS ACMP Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define Macros and functions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable output inverse function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set ACMPOINV bit of ACMP_CTL register to enable output inverse function.
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPOINV_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable output inverse function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear ACMPOINV bit of ACMP_CTL register to disable output inverse function.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_OUTPUT_INVERSE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPOINV_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select ACMP negative input source
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @param[in] u32Src is comparator negative input selection. Including:
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_PIN
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_CRV
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_VBG
|
||||||
|
* - \ref ACMP_CTL_NEGSEL_DAC
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set NEGSEL (ACMP_CTL[5:4]) to determine the source of negative input.
|
||||||
|
*/
|
||||||
|
#define ACMP_SET_NEG_SRC(acmp, u32ChNum, u32Src) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_NEGSEL_Msk) | (u32Src))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable hysteresis function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_HYSTERESIS_30MV)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable hysteresis function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set HYSSEL of ACMP_CTL register to disable hysteresis function.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_HYSTERESIS(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_HYSSEL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select hysteresis level
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @param[in] u32HysSel The hysteresis function option. Including:
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_30MV
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_20MV
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_10MV
|
||||||
|
* - \ref ACMP_CTL_HYSTERESIS_DISABLE
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define ACMP_CONFIG_HYSTERESIS(acmp, u32ChNum, u32HysSel) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_HYSSEL_Msk) | (u32HysSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable interrupt
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set ACMPIE bit of ACMP_CTL register to enable interrupt function.
|
||||||
|
* If wake-up function is enabled, the wake-up interrupt will be enabled as well.
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPIE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable interrupt
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear ACMPIE bit of ACMP_CTL register to disable interrupt function.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_INT(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPIE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ACMP
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set ACMPEN bit of ACMP_CTL register to enable analog comparator.
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_ACMPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ACMP
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear ACMPEN bit of ACMP_CTL register to disable analog comparator.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_ACMPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get ACMP output value
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return ACMP output value
|
||||||
|
* @details This macro will return the ACMP output value.
|
||||||
|
*/
|
||||||
|
#define ACMP_GET_OUTPUT(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPO0_Msk<<((u32ChNum))))?1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get ACMP interrupt flag
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return ACMP interrupt occurred (1) or not (0)
|
||||||
|
* @details This macro will return the ACMP interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ACMP_GET_INT_FLAG(acmp, u32ChNum) (((acmp)->STATUS & (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))?1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear ACMP interrupt flag
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write 1 to ACMPIFn bit of ACMP_STATUS register to clear interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ACMP_CLR_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_ACMPIF0_Msk<<((u32ChNum))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear ACMP wake-up interrupt flag
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write 1 to WKIFn bit of ACMP_STATUS register to clear interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ACMP_CLR_WAKEUP_INT_FLAG(acmp, u32ChNum) ((acmp)->STATUS = (ACMP_STATUS_WKIF0_Msk<<((u32ChNum))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ACMP wake-up function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set WKEN (ACMP_CTL[16]) to enable ACMP wake-up function.
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WKEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ACMP wake-up function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear WKEN (ACMP_CTL[16]) to disable ACMP wake-up function.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_WAKEUP(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WKEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select ACMP positive input pin
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @param[in] u32Pin Comparator positive pin selection. Including:
|
||||||
|
* - \ref ACMP_CTL_POSSEL_P0
|
||||||
|
* - \ref ACMP_CTL_POSSEL_P1
|
||||||
|
* - \ref ACMP_CTL_POSSEL_P2
|
||||||
|
* - \ref ACMP_CTL_POSSEL_P3
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set POSSEL (ACMP_CTL[7:6]) to determine the comparator positive input pin.
|
||||||
|
*/
|
||||||
|
#define ACMP_SELECT_P(acmp, u32ChNum, u32Pin) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_POSSEL_Msk) | (u32Pin))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ACMP filter function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set OUTSEL (ACMP_CTL[12]) to enable output filter function.
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_OUTSEL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ACMP filter function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear OUTSEL (ACMP_CTL[12]) to disable output filter function.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_FILTER(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_OUTSEL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set ACMP filter function
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @param[in] u32Cnt is comparator filter count setting.
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_OFF
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_1PCLK
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_2PCLK
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_4PCLK
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_8PCLK
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_16PCLK
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_32PCLK
|
||||||
|
* - \ref ACMP_CTL_FILTSEL_64PCLK
|
||||||
|
* @return None
|
||||||
|
* @details When ACMP output filter function is enabled, the output sampling count is determined by FILTSEL (ACMP_CTL[15:13]).
|
||||||
|
*/
|
||||||
|
#define ACMP_SET_FILTER(acmp, u32ChNum, u32Cnt) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_FILTSEL_Msk) | (u32Cnt))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select comparator reference voltage
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32Level The comparator reference voltage setting.
|
||||||
|
* The formula is:
|
||||||
|
* comparator reference voltage = CRV source voltage x (1/6 + u32Level/24)
|
||||||
|
* The range of u32Level is 0 ~ 15.
|
||||||
|
* @return None
|
||||||
|
* @details When CRV is selected as ACMP negative input source, the CRV level is determined by CRVCTL (ACMP_VREF[3:0]).
|
||||||
|
*/
|
||||||
|
#define ACMP_CRV_SEL(acmp, u32Level) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVCTL_Msk) | ((u32Level)<<ACMP_VREF_CRVCTL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select the source of CRV
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32Src is the source of CRV. Including:
|
||||||
|
* - \ref ACMP_VREF_CRVSSEL_VDDA
|
||||||
|
* - \ref ACMP_VREF_CRVSSEL_INTVREF
|
||||||
|
* @return None
|
||||||
|
* @details The source of CRV can be VDDA or internal reference voltage. The internal reference voltage level is determined by SYS_VREFCTL register.
|
||||||
|
*/
|
||||||
|
#define ACMP_SELECT_CRV_SRC(acmp, u32Src) ((acmp)->VREF = ((acmp)->VREF & ~ACMP_VREF_CRVSSEL_Msk) | (u32Src))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select ACMP interrupt condition
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @param[in] u32Cond Comparator interrupt condition selection. Including:
|
||||||
|
* - \ref ACMP_CTL_INTPOL_RF
|
||||||
|
* - \ref ACMP_CTL_INTPOL_R
|
||||||
|
* - \ref ACMP_CTL_INTPOL_F
|
||||||
|
* @return None
|
||||||
|
* @details The ACMP output interrupt condition can be rising edge, falling edge or any edge.
|
||||||
|
*/
|
||||||
|
#define ACMP_SELECT_INT_COND(acmp, u32ChNum, u32Cond) ((acmp)->CTL[(u32ChNum)] = ((acmp)->CTL[(u32ChNum)] & ~ACMP_CTL_INTPOL_Msk) | (u32Cond))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ACMP window latch mode
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set WLATEN (ACMP_CTL[17]) to enable ACMP window latch mode.
|
||||||
|
* When ACMP0/1_WLAT pin is at high level, ACMPO0/1 passes through window latch
|
||||||
|
* block; when ACMP0/1_WLAT pin is at low level, the output of window latch block,
|
||||||
|
* WLATOUT, is frozen.
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WLATEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ACMP window latch mode
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear WLATEN (ACMP_CTL[17]) to disable ACMP window latch mode.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_WINDOW_LATCH(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WLATEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ACMP window compare mode
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set WCMPSEL (ACMP_CTL[18]) to enable ACMP window compare mode.
|
||||||
|
* When window compare mode is enabled, user can connect the specific analog voltage
|
||||||
|
* source to either the positive inputs of both comparators or the negative inputs of
|
||||||
|
* both comparators. The upper bound and lower bound of the designated range are
|
||||||
|
* determined by the voltages applied to the other inputs of both comparators. If the
|
||||||
|
* output of a comparator is low and the other comparator outputs high, which means two
|
||||||
|
* comparators implies the upper and lower bound. User can directly monitor a specific
|
||||||
|
* analog voltage source via ACMPWO (ACMP_STATUS[16]).
|
||||||
|
*/
|
||||||
|
#define ACMP_ENABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] |= ACMP_CTL_WCMPSEL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ACMP window compare mode
|
||||||
|
* @param[in] acmp The pointer of the specified ACMP module
|
||||||
|
* @param[in] u32ChNum The ACMP number
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear WCMPSEL (ACMP_CTL[18]) to disable ACMP window compare mode.
|
||||||
|
*/
|
||||||
|
#define ACMP_DISABLE_WINDOW_COMPARE(acmp, u32ChNum) ((acmp)->CTL[(u32ChNum)] &= ~ACMP_CTL_WCMPSEL_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Function prototype declaration */
|
||||||
|
void ACMP_Open(ACMP_T *acmp, uint32_t u32ChNum, uint32_t u32NegSrc, uint32_t u32HysteresisEn);
|
||||||
|
void ACMP_Close(ACMP_T *acmp, uint32_t u32ChNum);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ACMP_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ACMP_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif //__ACMP_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,433 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file bootloader.h
|
||||||
|
* @version V1.00
|
||||||
|
* @brief Non-Secure Callable library header file of Boot Loader
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __BOOTLOADER_H__
|
||||||
|
#define __BOOTLOADER_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------*/
|
||||||
|
/* Redirect BL API function name to meet API Naming Rule */
|
||||||
|
/*---------------------------------------------------------*/
|
||||||
|
#define BL_GetVersion BL_Get_Version
|
||||||
|
#define BL_EnableFMC BL_FMC_Open
|
||||||
|
#define BL_DisableFMC BL_FMC_Close
|
||||||
|
#define BL_GetISPStatus BL_FMC_ISP_Status
|
||||||
|
#define BL_FlashRead BL_FMC_Read
|
||||||
|
#define BL_FlashMultiRead BL_FMC_MultiRead
|
||||||
|
#define BL_FlashWrite BL_FMC_Write
|
||||||
|
#define BL_FlashMultiWrite BL_FMC_MultiWrite
|
||||||
|
#define BL_FlashPageErase BL_FMC_Erase
|
||||||
|
#define BL_FlashChecksum BL_FMC_GetChkSum
|
||||||
|
#define BL_ReadCID BL_FMC_ReadCID
|
||||||
|
#define BL_ReadDID BL_FMC_ReadDID
|
||||||
|
#define BL_ReadPID BL_FMC_ReadPID
|
||||||
|
#define BL_ReadUCID BL_FMC_ReadUCID
|
||||||
|
#define BL_ReadUID BL_FMC_ReadUID
|
||||||
|
#define BL_CheckFlashAllOne BL_FMC_CheckAllOne
|
||||||
|
#define BL_CheckOPTStatus BL_FMC_Is_OTP_Locked
|
||||||
|
#define BL_EnableOTPLock BL_FMC_Lock_OTP
|
||||||
|
#define BL_ReadOTP BL_FMC_Read_OTP
|
||||||
|
#define BL_WriteOTP BL_FMC_Write_OTP
|
||||||
|
#define BL_GetKPROMStatus BL_FMC_Read_KPROM_STATUS
|
||||||
|
#define BL_TrgKPROMCompare BL_FMC_SKey_Compare
|
||||||
|
#define BL_GetNSBoundary BL_FMC_NSCBOUD
|
||||||
|
#define BL_SetFlashAllLock BL_FMC_Lock_All_Region
|
||||||
|
#define BL_SetXOMActive BL_FMC_Set_XOM_Active
|
||||||
|
#define BL_GetXOMStatus BL_FMC_Is_XOM_Actived
|
||||||
|
#define BL_SetXOMRegion BL_FMC_Set_XOM_Region
|
||||||
|
#define BL_ReadXOMRegion BL_FMC_Read_XOM_Region
|
||||||
|
#define BL_EraseXOMRegion BL_FMC_Erase_XOM
|
||||||
|
#define BL_EraseXOMStatus BL_FMC_XOM_Erase_Status
|
||||||
|
#define BL_ResetChip BL_Chip_Reset
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup BL_Driver Boot Loader Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup BL_EXPORTED_FUNCTIONS Boot Loader Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Bootloader Version Number
|
||||||
|
* @param None
|
||||||
|
* @return Version number of bootloader
|
||||||
|
* @details Return bootloader version number and it's fixed to be 0x16091414.
|
||||||
|
*/
|
||||||
|
uint32_t BL_GetVersion(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FMC ISP Function
|
||||||
|
* @param None
|
||||||
|
* @return Maximum APROM size
|
||||||
|
* @details This API will unlock register write-protect, enable relavive settings for access FMC ISP commands
|
||||||
|
* and return maximum APROM by chip package.
|
||||||
|
*/
|
||||||
|
uint32_t BL_EnableFMC(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable FMC ISP Function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This API will disable relavive settings for disable FMC ISP function and lock register write-protect
|
||||||
|
* until last ISP operation is finished.
|
||||||
|
*/
|
||||||
|
void BL_DisableFMC(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get FMC ISP Busy Status
|
||||||
|
* @param None
|
||||||
|
* @retval 0 ISP operation is finished
|
||||||
|
* @retval 1 ISP operation is in processing
|
||||||
|
* @details This API indicates ISP operation in in processing or finished.
|
||||||
|
*/
|
||||||
|
uint32_t BL_GetISPStatus(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get 32-bit data from Non-Secure Flash Address
|
||||||
|
* @param[in] u32Addr Flash address should be in non-secure area
|
||||||
|
* @retval 0xF0F00001 u32Addr isn't word aligned
|
||||||
|
* @retval 0xF0F00002 u32Addr isn't in non-secure area
|
||||||
|
* @retval The data of specified non-secure address
|
||||||
|
* @details To read word data from specified non-secure flash address.
|
||||||
|
*/
|
||||||
|
uint32_t BL_FlashRead(uint32_t u32Addr);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Multi-Word Data from Non-Secure Flash
|
||||||
|
* @param[in] u32Addr Starting flash address should be in non-secure area
|
||||||
|
* @param[out] pu32NSRamBuf Starting address to store reading data
|
||||||
|
* @param[in] u32Size Total read byte counts, it should be word aligned and maximum size is one page size.
|
||||||
|
* @retval 0xF0F00001 u32Addr or u32Size is invalid parameter
|
||||||
|
* @retval 0xF0F00002 u32Addr isn't in non-secure area
|
||||||
|
* @retval 0 Read operation is finished
|
||||||
|
* @details To read multi-words data start from specified non-secure flash address.
|
||||||
|
* And maximum read size is one page size, 20248 bytes.
|
||||||
|
*/
|
||||||
|
int32_t BL_FlashMultiRead(uint32_t u32Addr, uint32_t *pu32NSRamBuf, uint32_t u32Size);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Program 32-bit data into Non-Secure Flash Address
|
||||||
|
* @param[in] u32Addr Flash address should be in non-secure area
|
||||||
|
* @param[in] u32Data 32-bit Data to program
|
||||||
|
* @retval 0xF0F00001 u32Addr isn't word aligned
|
||||||
|
* @retval 0xF0F00002 u32Addr isn't in non-secure area
|
||||||
|
* @retval 0 Program command is finished
|
||||||
|
* @details To program word data into specified non-secure flash address.
|
||||||
|
*/
|
||||||
|
int32_t BL_FlashWrite(uint32_t u32Addr, uint32_t u32Data);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Program Multi-Word Data into Non-Secure Flash
|
||||||
|
* @param[in] u32Addr Starting flash address should be in non-secure area
|
||||||
|
* @param[in] pu32NSRamBuf Starting address to store data to be program
|
||||||
|
* @param[in] u32Size Total program byte counts, it should be word aligned and maximum size is one page size.
|
||||||
|
* @retval 0xF0F00001 u32Addr or u32Size is invalid parameter
|
||||||
|
* @retval 0xF0F00002 u32Addr isn't in non-secure area
|
||||||
|
* @retval 0 Program operation is finished
|
||||||
|
* @details To program multi-words data start from specified non-secure flash address.
|
||||||
|
* And maximum program size is one page size, 20248 bytes.
|
||||||
|
*/
|
||||||
|
int32_t BL_FlashMultiWrite(uint32_t u32Addr, uint32_t *pu32NSRamBuf, uint32_t u32Size);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Flash Page Erase
|
||||||
|
* @param[in] u32PageAddr Address of the non-secure flash page to be erased. It must be a page size aligned address.
|
||||||
|
* @retval 0xF0F00001 u32PageAddr isn't page size aligned
|
||||||
|
* @retval 0xF0F00002 u32PageAddr isn't in non-secure area
|
||||||
|
* @retval 0 Page erase success
|
||||||
|
* @retval -1 Page erase failed
|
||||||
|
* @details This API is used to perform page erase command on specified non-secure flash address.
|
||||||
|
* And this address must be a 2048 bytes page size aligned address.
|
||||||
|
*/
|
||||||
|
int32_t BL_FlashPageErase(uint32_t u32PageAddr);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified Non-Secure Area CRC32 Checksum
|
||||||
|
* @param[in] u32Addr Starting non-secure flash address. It must be a page size aligned address.
|
||||||
|
* @param[in] u32ByteCount Byte count of non-secure flash area to be calculated. It must be multiple of 2048 bytes.
|
||||||
|
* @retval 0xFFFFFFFF u32Addr isn't in non-secure area or u32ByteCount isn't page size aligned
|
||||||
|
* @retval Result of CRC32 checksum
|
||||||
|
* @details This API will calculate the CRC32 checksum result of specified non-secure flash area.
|
||||||
|
* And the starting address and calculated szie must be all 2048 bytes page size aligned.
|
||||||
|
*/
|
||||||
|
uint32_t BL_FlashChecksum(uint32_t u32Addr, uint32_t u32ByteCount);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Company ID
|
||||||
|
* @param None
|
||||||
|
* @return The company ID (32-bit)
|
||||||
|
* @details The company ID of Nuvoton is fixed to be 0xDA
|
||||||
|
*/
|
||||||
|
uint32_t BL_ReadCID(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Device ID
|
||||||
|
* @param None
|
||||||
|
* @return The device ID (32-bit)
|
||||||
|
* @details This function is used to read device ID.
|
||||||
|
*/
|
||||||
|
uint32_t BL_ReadDID(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Product ID
|
||||||
|
* @param None
|
||||||
|
* @return The product ID (32-bit)
|
||||||
|
* @details This function is used to read product ID.
|
||||||
|
*/
|
||||||
|
uint32_t BL_ReadPID(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read UCID
|
||||||
|
* @param[in] u32Index Index of the UCID to read and u32Index must be 0, 1, 2, or 3.
|
||||||
|
* @return The UCID of specified index
|
||||||
|
* @details This function is used to read unique chip ID (UCID).
|
||||||
|
*/
|
||||||
|
uint32_t BL_ReadUCID(uint32_t u32Index);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read UID
|
||||||
|
* @param[in] u32Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
|
||||||
|
* @return The 32-bit unique ID data of specified UID index
|
||||||
|
* @details To read out specified 32-bit unique ID.
|
||||||
|
*/
|
||||||
|
uint32_t BL_ReadUID(uint32_t u32Index);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Run Flash All One Verification and Get Result
|
||||||
|
* @param[in] u32Addr Starting non-secure flash address. It must be a page size aligned address.
|
||||||
|
* @param[in] u32ByteCount Byte count of non-secure flash area to be calculated. It must be multiple of 2048 bytes.
|
||||||
|
* @retval 0xA11FFFFF The contents of verified non-secure flash area are 0xFFFFFFFF
|
||||||
|
* @retval 0xA1100000 Some contents of verified non-secure flash area are not 0xFFFFFFFF
|
||||||
|
* @retval 0xF0F00001 u32Addr isn't page size aligned
|
||||||
|
* @retval 0xF0F00002 u32Addr or u32ByteCount are not page size aligned
|
||||||
|
* @retval 0xFFFFFFFF Unexpected error occurred
|
||||||
|
* @details This API is used to check specified non-secure flash area are all 0xFFFFFFFF or not.
|
||||||
|
*/
|
||||||
|
uint32_t BL_CheckFlashAllOne(uint32_t u32Addr, uint32_t u32ByteCount);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check the specified OTP is Locked or Unlock
|
||||||
|
* @param[in] u32OTP The specified OTP number, it must be between 0 ~ 255.
|
||||||
|
* @retval 1 Specified OTP is locked
|
||||||
|
* @retval 0 Specified OTP is unlocked
|
||||||
|
* @retval -1 Failed to read OTP lock status
|
||||||
|
* @retval -2 Invalid OTP number
|
||||||
|
* @details Use can use this API to check specified OPT is lock or unlock.
|
||||||
|
* If unlocked, user can program specified bit data from 1 to 0 in this OPT area.
|
||||||
|
*/
|
||||||
|
int32_t BL_CheckOPTStatus(uint32_t u32OTP);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Lock the specified OTP
|
||||||
|
* @param[in] u32OTP The specified OTP number, it must be between 0 ~ 255.
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Failed to execute write OTP command
|
||||||
|
* @retval -2 Invalid OTP number
|
||||||
|
* @details Use can use this API to lock specified OPT area.
|
||||||
|
* If locked, user can't modify data in this OPT area.
|
||||||
|
*/
|
||||||
|
int32_t BL_EnableOTPLock(uint32_t u32OTP);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read the 64-bits OTP Data
|
||||||
|
* @param[in] u32OTP The specified OTP number, it must be between 0 ~ 255.
|
||||||
|
* @param[in] low_word Low word of the 64-bits data
|
||||||
|
* @param[in] high_word High word of the 64-bits data
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Failed to read OTP data
|
||||||
|
* @retval -2 Invalid OTP number
|
||||||
|
* @details Thia API can get the specified 64-bits OTP data.
|
||||||
|
*/
|
||||||
|
int32_t BL_ReadOTP(uint32_t u32OTP, uint32_t *low_word, uint32_t *high_word);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Program a 64-bits OTP Data
|
||||||
|
* @param[in] u32OTP The specified OTP number, it must be between 0 ~ 255.
|
||||||
|
* @param[in] low_word Low word of the 64-bits data
|
||||||
|
* @param[in] high_word High word of the 64-bits data
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Failed to write OTP data
|
||||||
|
* @retval -2 Invalid OTP number
|
||||||
|
* @details Thia API can program 64-bits data to specified OTP area if current OTP is unlocked.
|
||||||
|
*/
|
||||||
|
int32_t BL_WriteOTP(uint32_t u32OTP, uint32_t low_word, uint32_t high_word);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read KPROM KPKEYSTS Register Status
|
||||||
|
* @param None
|
||||||
|
* @return KPKEYSTS register status
|
||||||
|
* @details This API can read KPROM KPKEYSTS register status.
|
||||||
|
*/
|
||||||
|
uint32_t BL_GetKPROMStatus(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Execute Security Key Comparison
|
||||||
|
* @param[in] key[3] Input key[0]~key[2] to be compared
|
||||||
|
* @retval 0 Key matched
|
||||||
|
* @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count.
|
||||||
|
* @retval -2 Key mismatched.
|
||||||
|
* @retval -3 No security key lock. Key comparison is not required.
|
||||||
|
* @details User can use this API to unlock KPROM protection then execute FMC program command well.
|
||||||
|
*/
|
||||||
|
int32_t BL_TrgKPROMCompare(uint32_t key[3]);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Non-Scure Boundary
|
||||||
|
* @param None
|
||||||
|
* @return Current non-secure boundary
|
||||||
|
* @details This API can get current non-secure boundary address.
|
||||||
|
*/
|
||||||
|
uint32_t BL_GetNSBoundary(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set All Flash Region Lock
|
||||||
|
* @param None
|
||||||
|
* @return Always return 0
|
||||||
|
* @details This API will protect all flash region read/write operate by ICE/TWICP/WRITER interface exclude OPT area.
|
||||||
|
*/
|
||||||
|
int32_t BL_SetFlashAllLock(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set XOM Active
|
||||||
|
* @param[in] u32XOM Specified XOM region, it must be between 0~3.
|
||||||
|
* @retval 0 Set XOM region active success
|
||||||
|
* @retval 1 Current XOM region is avtive
|
||||||
|
* @retval -1 Current XOM has not been configured yet
|
||||||
|
* @retval -2 Invalid u32XOM number
|
||||||
|
* @retval -3 XOM region isn't in non-secure area
|
||||||
|
* @details This API will set specified XOM region become active.
|
||||||
|
*/
|
||||||
|
int32_t BL_SetXOMActive(uint32_t u32XOM);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get XOM Active Status
|
||||||
|
* @param[in] u32XOM Specified XOM region, it must be between 0~3.
|
||||||
|
* @retval 0 Current XOM region isn't avtive yet
|
||||||
|
* @retval 1 Current XOM region is avtive
|
||||||
|
* @retval -2 Invalid u32XOM number
|
||||||
|
* @details This API will return specified XOM region is active or not.
|
||||||
|
*/
|
||||||
|
int32_t BL_GetXOMStatus(uint32_t u32XOM);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set XOM Setting
|
||||||
|
* @param[in] u32XOM Specified XOM region, it must be between 0~3
|
||||||
|
* @param[in] u32Base Base address of XOM region
|
||||||
|
* @param[in] u32PageCnt Page count of XOM region
|
||||||
|
* @param[in] u32SetActive 0: only configure XOM base and page count; 1: set XOM region avtive after XOM setting done.
|
||||||
|
* @retval 0 Set specified XOM success
|
||||||
|
* @retval 1 Current specified XOM region is active
|
||||||
|
* @retval -1 Current specified XOM region has been configured
|
||||||
|
* @retval -2 Invalid u32XOM number
|
||||||
|
* @retval -3 XOM region isn't in non-secure area
|
||||||
|
* @details This API will set specified XOM settings.
|
||||||
|
*/
|
||||||
|
int32_t BL_SetXOMRegion(uint32_t u32XOM, uint32_t u32Base, uint32_t u32PageCnt, uint32_t u32SetActive);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read XOM Setting
|
||||||
|
* @param[in] u32XOM Specified XOM region, it must be between 0~3
|
||||||
|
* @param[out] pu32Base Return specified XOM base address
|
||||||
|
* @param[out] pu32PageCnt Return specified XOM page count
|
||||||
|
* @retval 0 Read specified XOM setting success
|
||||||
|
* @retval -1 Get specified XOM status failed
|
||||||
|
* @retval -2 Invalid u32XOM number
|
||||||
|
* @retval -3 XOM region isn't in non-secure area
|
||||||
|
* @details This API will read specified XOM relative settings.
|
||||||
|
*/
|
||||||
|
int32_t BL_ReadXOMRegion(uint32_t u32XOM, uint32_t *pu32Base, uint32_t *pu32PageCnt);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Erase XOM Setting
|
||||||
|
* @param[in] u32XOMBase Specified valid XOM base address to be erase
|
||||||
|
* @retval 0 XOM page erase command finished
|
||||||
|
* @retval -1 XOM page erase command failed
|
||||||
|
* @retval -2 invalid u32XOMBase base address
|
||||||
|
* @retval -3 u32XOMBase base mismatched
|
||||||
|
* @details This API will erase specified XOM region data and relavive XOM setting.
|
||||||
|
*/
|
||||||
|
int32_t BL_EraseXOMRegion(uint32_t u32XOMBase);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get XOM Erased Status
|
||||||
|
* @param None
|
||||||
|
* @retval 0 XOM erase operation success
|
||||||
|
* @retval -1 XOM erase operation failed
|
||||||
|
* @details This API will return the XOM erase operation is success or not.
|
||||||
|
*/
|
||||||
|
int32_t BL_EraseXOMStatus(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Execute CHIP Reset
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This API will perform reset CHIP command to reset chip.
|
||||||
|
*/
|
||||||
|
void BL_ResetChip(void);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BL_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BL_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __BOOTLOADER_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,670 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file bpwm.c
|
||||||
|
* @version V1.00
|
||||||
|
* @brief M2351 series BPWM driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup BPWM_Driver BPWM Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure BPWM capture and get the nearest unit time.
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32UnitTimeNsec The unit time of counter
|
||||||
|
* @param[in] u32CaptureEdge The condition to latch the counter. This parameter is not used
|
||||||
|
* @return The nearest unit time in nano second.
|
||||||
|
* @details This function is used to Configure BPWM capture and get the nearest unit time.
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
|
||||||
|
{
|
||||||
|
uint32_t u32Src;
|
||||||
|
uint32_t u32PWMClockSrc;
|
||||||
|
uint32_t u32NearestUnitTimeNsec;
|
||||||
|
uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
|
||||||
|
|
||||||
|
//clock source is from PCLK
|
||||||
|
if((bpwm == BPWM0)||(bpwm == BPWM0_NS))
|
||||||
|
u32PWMClockSrc = CLK_GetPCLK0Freq();
|
||||||
|
else// if((bpwm == BPWM1)||(bpwm == BPWM1_NS))
|
||||||
|
u32PWMClockSrc = CLK_GetPCLK1Freq();
|
||||||
|
|
||||||
|
u32PWMClockSrc /= 1000;
|
||||||
|
for(u16Prescale = 1; u16Prescale <= 0x1000; u16Prescale++)
|
||||||
|
{
|
||||||
|
u32NearestUnitTimeNsec = (1000000 * u16Prescale) / u32PWMClockSrc;
|
||||||
|
if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
|
||||||
|
{
|
||||||
|
if(u16Prescale == 0x1000) //limit to the maximum unit time(nano second)
|
||||||
|
break;
|
||||||
|
if(!((1000000 * (u16Prescale + 1) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
|
||||||
|
break;
|
||||||
|
continue;
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
// convert to real register value
|
||||||
|
// all channels share a prescaler
|
||||||
|
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, --u16Prescale);
|
||||||
|
|
||||||
|
// set BPWM to down count type(edge aligned)
|
||||||
|
(bpwm)->CTL1 = (1UL);
|
||||||
|
|
||||||
|
BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR);
|
||||||
|
|
||||||
|
return (u32NearestUnitTimeNsec);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function Configure BPWM generator and get the nearest frequency in edge aligned(up counter type) auto-reload mode
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Frequency Target generator frequency
|
||||||
|
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0 ~ 100. 10 means 10%, 20 means 20%...
|
||||||
|
* @return Nearest frequency clock in nano second
|
||||||
|
* @note Since all channels shares a prescaler. Call this API to configure BPWM frequency may affect
|
||||||
|
* existing frequency of other channel.
|
||||||
|
* @note This function is used for initial stage.
|
||||||
|
* To change duty cycle later, it should get the configured period value and calculate the new comparator value.
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle)
|
||||||
|
{
|
||||||
|
uint32_t u32Src;
|
||||||
|
uint32_t u32PWMClockSrc;
|
||||||
|
uint32_t i;
|
||||||
|
uint16_t u16Prescale = 1, u16CNR = 0xFFFF;
|
||||||
|
|
||||||
|
//clock source is from PCLK
|
||||||
|
if((bpwm == BPWM0)||(bpwm == BPWM0_NS))
|
||||||
|
u32PWMClockSrc = CLK_GetPCLK0Freq();
|
||||||
|
else// if((bpwm == BPWM1)||(bpwm == BPWM1_NS))
|
||||||
|
u32PWMClockSrc = CLK_GetPCLK1Freq();
|
||||||
|
|
||||||
|
for(u16Prescale = 1; u16Prescale < 0xFFF; u16Prescale++)//prescale could be 0~0xFFF
|
||||||
|
{
|
||||||
|
i = (u32PWMClockSrc / u32Frequency) / u16Prescale;
|
||||||
|
// If target value is larger than CNR, need to use a larger prescaler
|
||||||
|
if(i > (0x10000))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
u16CNR = i;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
// Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register
|
||||||
|
i = u32PWMClockSrc / (u16Prescale * u16CNR);
|
||||||
|
|
||||||
|
// convert to real register value
|
||||||
|
// all channels share a prescaler
|
||||||
|
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, --u16Prescale);
|
||||||
|
// set BPWM to up counter type(edge aligned)
|
||||||
|
(bpwm)->CTL1 = BPWM_UP_COUNTER;
|
||||||
|
|
||||||
|
BPWM_SET_CNR(bpwm, u32ChannelNum, --u16CNR);
|
||||||
|
BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1) / 100);
|
||||||
|
|
||||||
|
|
||||||
|
(bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
|
||||||
|
(BPWM_OUTPUT_HIGH << (u32ChannelNum << (1 + BPWM_WGCTL0_ZPCTL0_Pos)));
|
||||||
|
(bpwm)->WGCTL1 = ((bpwm)->WGCTL1 & ~((BPWM_WGCTL1_CMPDCTL0_Msk | BPWM_WGCTL1_CMPUCTL0_Msk) << (u32ChannelNum << 1))) | \
|
||||||
|
(BPWM_OUTPUT_LOW << (u32ChannelNum << (1 + BPWM_WGCTL1_CMPUCTL0_Pos)));
|
||||||
|
|
||||||
|
return(i);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start BPWM module
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to start BPWM module.
|
||||||
|
* @note All channels share one counter.
|
||||||
|
*/
|
||||||
|
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->CNTEN = BPWM_CNTEN_CNTEN0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop BPWM module
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to stop BPWM module.
|
||||||
|
* @note All channels share one period.
|
||||||
|
*/
|
||||||
|
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->PERIOD = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop BPWM generation immediately by clear channel enable bit
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to stop BPWM generation immediately by clear channel enable bit.
|
||||||
|
* @note All channels share one counter.
|
||||||
|
*/
|
||||||
|
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->CNTEN &= ~BPWM_CNTEN_CNTEN0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable selected channel to trigger ADC
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Condition The condition to trigger ADC. Combination of following conditions:
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_POINT
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT
|
||||||
|
* - \ref BPWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable selected channel to trigger ADC
|
||||||
|
*/
|
||||||
|
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||||
|
{
|
||||||
|
if(u32ChannelNum < 4)
|
||||||
|
{
|
||||||
|
(bpwm)->EADCTS0 &= ~((BPWM_EADCTS0_TRGSEL0_Msk) << (u32ChannelNum * 8));
|
||||||
|
(bpwm)->EADCTS0 |= ((BPWM_EADCTS0_TRGEN0_Msk | u32Condition) << (u32ChannelNum * 8));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
(bpwm)->EADCTS1 &= ~((BPWM_EADCTS1_TRGSEL4_Msk) << ((u32ChannelNum - 4) * 8));
|
||||||
|
(bpwm)->EADCTS1 |= ((BPWM_EADCTS1_TRGEN4_Msk | u32Condition) << ((u32ChannelNum - 4) * 8));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable selected channel to trigger ADC
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~3
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable selected channel to trigger ADC
|
||||||
|
*/
|
||||||
|
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
if(u32ChannelNum < 4)
|
||||||
|
{
|
||||||
|
(bpwm)->EADCTS0 &= ~(BPWM_EADCTS0_TRGEN0_Msk << (u32ChannelNum * 8));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
(bpwm)->EADCTS1 &= ~(BPWM_EADCTS1_TRGEN4_Msk << ((u32ChannelNum - 4) * 8));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear selected channel trigger ADC flag
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Condition This parameter is not used
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to clear selected channel trigger ADC flag
|
||||||
|
*/
|
||||||
|
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition)
|
||||||
|
{
|
||||||
|
(bpwm)->STATUS = (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get selected channel trigger ADC flag
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @retval 0 The specified channel trigger ADC to start of conversion flag is not set
|
||||||
|
* @retval 1 The specified channel trigger ADC to start of conversion flag is set
|
||||||
|
* @details This function is used to get BPWM trigger ADC to start of conversion flag for specified channel
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
return (((bpwm)->STATUS & (BPWM_STATUS_EADCTRG0_Msk << u32ChannelNum)) ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable capture of selected channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||||
|
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable capture of selected channel(s)
|
||||||
|
*/
|
||||||
|
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->CAPINEN |= u32ChannelMask;
|
||||||
|
(bpwm)->CAPCTL |= u32ChannelMask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable capture of selected channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||||
|
* Bit 0 is channel 0, bit 1 is channel 1...
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable capture of selected channel(s)
|
||||||
|
*/
|
||||||
|
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->CAPINEN &= ~u32ChannelMask;
|
||||||
|
(bpwm)->CAPCTL &= ~u32ChannelMask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enables BPWM output generation of selected channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel.
|
||||||
|
* Set bit 0 to 1 enables channel 0 output, set bit 1 to 1 enables channel 1 output...
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enables BPWM output generation of selected channel(s)
|
||||||
|
*/
|
||||||
|
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->POEN |= u32ChannelMask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disables BPWM output generation of selected channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Set bit 0 to 1 disables channel 0 output, set bit 1 to 1 disables channel 1 output...
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disables BPWM output generation of selected channel(s)
|
||||||
|
*/
|
||||||
|
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask)
|
||||||
|
{
|
||||||
|
(bpwm)->POEN &= ~u32ChannelMask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable capture interrupt of selected channel.
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Edge Rising or falling edge to latch counter.
|
||||||
|
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
|
||||||
|
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable capture interrupt of selected channel.
|
||||||
|
*/
|
||||||
|
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
||||||
|
{
|
||||||
|
(bpwm)->CAPIEN |= (u32Edge << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable capture interrupt of selected channel.
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Edge Rising or falling edge to latch counter.
|
||||||
|
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
|
||||||
|
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable capture interrupt of selected channel.
|
||||||
|
*/
|
||||||
|
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
||||||
|
{
|
||||||
|
(bpwm)->CAPIEN &= ~(u32Edge << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear capture interrupt of selected channel.
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Edge Rising or falling edge to latch counter.
|
||||||
|
* - \ref BPWM_CAPTURE_INT_RISING_LATCH
|
||||||
|
* - \ref BPWM_CAPTURE_INT_FALLING_LATCH
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to clear capture interrupt of selected channel.
|
||||||
|
*/
|
||||||
|
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge)
|
||||||
|
{
|
||||||
|
(bpwm)->CAPIF = (u32Edge << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get capture interrupt of selected channel.
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @retval 0 No capture interrupt
|
||||||
|
* @retval 1 Rising edge latch interrupt
|
||||||
|
* @retval 2 Falling edge latch interrupt
|
||||||
|
* @retval 3 Rising and falling latch interrupt
|
||||||
|
* @details This function is used to get capture interrupt of selected channel.
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
return (((((bpwm)->CAPIF & (BYTE1_Msk << u32ChannelNum)) ? 1 : 0) << 1) | \
|
||||||
|
(((bpwm)->CAPIF & (BYTE0_Msk << u32ChannelNum)) ? 1 : 0));
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief Enable duty interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32IntDutyType Duty interrupt type, could be either
|
||||||
|
* - \ref BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP
|
||||||
|
* - \ref BPWM_DUTY_INT_UP_COUNT_MATCH_CMP
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable duty interrupt of selected channel.
|
||||||
|
*/
|
||||||
|
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType)
|
||||||
|
{
|
||||||
|
(bpwm)->INTEN |= (u32IntDutyType << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable duty interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable duty interrupt of selected channel
|
||||||
|
*/
|
||||||
|
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTEN &= ~((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear duty interrupt flag of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to clear duty interrupt flag of selected channel
|
||||||
|
*/
|
||||||
|
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTSTS = (BYTE2_Msk | BYTE3_Msk) << u32ChannelNum;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get duty interrupt flag of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @return Duty interrupt flag of specified channel
|
||||||
|
* @retval 0 Duty interrupt did not occur
|
||||||
|
* @retval 1 Duty interrupt occurred
|
||||||
|
* @details This function is used to get duty interrupt flag of selected channel
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
return ((((bpwm)->INTSTS & ((BYTE2_Msk | BYTE3_Msk) << u32ChannelNum))) ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable period interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @param[in] u32IntPeriodType Period interrupt type. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable period interrupt of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType)
|
||||||
|
{
|
||||||
|
(bpwm)->INTEN |= BPWM_INTEN_PIEN0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable period interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable period interrupt of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTEN &= ~BPWM_INTEN_PIEN0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear period interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to clear period interrupt of selected channel
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTSTS = BPWM_INTSTS_PIF0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get period interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return Period interrupt flag of specified channel
|
||||||
|
* @retval 0 Period interrupt did not occur
|
||||||
|
* @retval 1 Period interrupt occurred
|
||||||
|
* @details This function is used to get period interrupt of selected channel
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
return (((bpwm)->INTSTS & BPWM_INTSTS_PIF0_Msk) ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable zero interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable zero interrupt of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTEN |= BPWM_INTEN_ZIEN0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable zero interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable zero interrupt of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTEN &= ~BPWM_INTEN_ZIEN0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear zero interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to clear zero interrupt of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->INTSTS = BPWM_INTSTS_ZIF0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get zero interrupt of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return zero interrupt flag of specified channel
|
||||||
|
* @retval 0 zero interrupt did not occur
|
||||||
|
* @retval 1 zero interrupt occurred
|
||||||
|
* @details This function is used to get zero interrupt of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
return (((bpwm)->INTSTS & BPWM_INTSTS_ZIF0_Msk) ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable load mode of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32LoadMode BPWM counter loading mode.
|
||||||
|
* - \ref BPWM_LOAD_MODE_IMMEDIATE
|
||||||
|
* - \ref BPWM_LOAD_MODE_CENTER
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable load mode of selected channel.
|
||||||
|
*/
|
||||||
|
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
|
||||||
|
{
|
||||||
|
(bpwm)->CTL0 |= (u32LoadMode << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable load mode of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32LoadMode PWM counter loading mode.
|
||||||
|
* - \ref BPWM_LOAD_MODE_IMMEDIATE
|
||||||
|
* - \ref BPWM_LOAD_MODE_CENTER
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to disable load mode of selected channel.
|
||||||
|
*/
|
||||||
|
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode)
|
||||||
|
{
|
||||||
|
(bpwm)->CTL0 &= ~(u32LoadMode << u32ChannelNum);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable BPWM SYNC input pin inverse function
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @param[in] u32ClkSrcSel BPWM external clock source.
|
||||||
|
* - \ref BPWM_CLKSRC_BPWM_CLK
|
||||||
|
* - \ref BPWM_CLKSRC_TIMER0
|
||||||
|
* - \ref BPWM_CLKSRC_TIMER1
|
||||||
|
* - \ref BPWM_CLKSRC_TIMER2
|
||||||
|
* - \ref BPWM_CLKSRC_TIMER3
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to enable BPWM SYNC input pin inverse function.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel)
|
||||||
|
{
|
||||||
|
(bpwm)->CLKSRC = (u32ClkSrcSel);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the time-base counter reached its maximum value flag of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return Count to max interrupt flag of specified channel
|
||||||
|
* @retval 0 Count to max interrupt did not occur
|
||||||
|
* @retval 1 Count to max interrupt occurred
|
||||||
|
* @details This function is used to get the time-base counter reached its maximum value flag of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
return (((bpwm)->STATUS & BPWM_STATUS_CNTMAX0_Msk) ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the time-base counter reached its maximum value flag of selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* - BPWM0 : BPWM Group 0
|
||||||
|
* - BPWM1 : BPWM Group 1
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to clear the time-base counter reached its maximum value flag of selected channel.
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
*/
|
||||||
|
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
|
||||||
|
{
|
||||||
|
(bpwm)->STATUS = BPWM_STATUS_CNTMAX0_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BPWM_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,364 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file bpwm.h
|
||||||
|
* @version V1.00
|
||||||
|
* @brief M2351 series BPWM driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __BPWM_H__
|
||||||
|
#define __BPWM_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup BPWM_Driver BPWM Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup BPWM_EXPORTED_CONSTANTS PWM Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define BPWM_CHANNEL_NUM (6UL) /*!< BPWM channel number */
|
||||||
|
#define BPWM_CH_0_MASK (0x1UL) /*!< BPWM channel 0 mask \hideinitializer */
|
||||||
|
#define BPWM_CH_1_MASK (0x2UL) /*!< BPWM channel 1 mask \hideinitializer */
|
||||||
|
#define BPWM_CH_2_MASK (0x4UL) /*!< BPWM channel 2 mask \hideinitializer */
|
||||||
|
#define BPWM_CH_3_MASK (0x8UL) /*!< BPWM channel 3 mask \hideinitializer */
|
||||||
|
#define BPWM_CH_4_MASK (0x10UL) /*!< BPWM channel 4 mask \hideinitializer */
|
||||||
|
#define BPWM_CH_5_MASK (0x20UL) /*!< BPWM channel 5 mask \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Counter Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_UP_COUNTER (0UL) /*!< Up counter type */
|
||||||
|
#define BPWM_DOWN_COUNTER (1UL) /*!< Down counter type */
|
||||||
|
#define BPWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Aligned Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_EDGE_ALIGNED (1UL) /*!< BPWM working in edge aligned type(down count) */
|
||||||
|
#define BPWM_CENTER_ALIGNED (2UL) /*!< BPWM working in center aligned type */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Output Level Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_OUTPUT_NOTHING (0UL) /*!< BPWM output nothing */
|
||||||
|
#define BPWM_OUTPUT_LOW (1UL) /*!< BPWM output low */
|
||||||
|
#define BPWM_OUTPUT_HIGH (2UL) /*!< BPWM output high */
|
||||||
|
#define BPWM_OUTPUT_TOGGLE (3UL) /*!< BPWM output toggle */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Synchronous Start Function Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_SSCTL_SSRC_PWM0 (0UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
|
||||||
|
#define BPWM_SSCTL_SSRC_PWM1 (1UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
|
||||||
|
#define BPWM_SSCTL_SSRC_BPWM0 (2UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
|
||||||
|
#define BPWM_SSCTL_SSRC_BPWM1 (3UL<<BPWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Trigger Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< BPWM trigger ADC while counter of even channel matches zero point */
|
||||||
|
#define BPWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< BPWM trigger ADC while counter of even channel matches period point */
|
||||||
|
#define BPWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< BPWM trigger ADC while counter of even channel matches zero or period point */
|
||||||
|
#define BPWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< BPWM trigger ADC while counter of even channel matches up count to comparator point */
|
||||||
|
#define BPWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< BPWM trigger ADC while counter of even channel matches down count to comparator point */
|
||||||
|
#define BPWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< BPWM trigger ADC while counter of odd channel matches up count to comparator point */
|
||||||
|
#define BPWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< BPWM trigger ADC while counter of odd channel matches down count to comparator point */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Capture Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< BPWM capture interrupt if channel has rising transition */
|
||||||
|
#define BPWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< BPWM capture interrupt if channel has falling transition */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Duty Interrupt Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (BPWM_INTEN_CMPDIEN0_Msk) /*!< BPWM duty interrupt triggered if down count match comparator */
|
||||||
|
#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (BPWM_INTEN_CMPUIEN0_Msk) /*!< BPWM duty interrupt triggered if up down match comparator */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Load Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_LOAD_MODE_IMMEDIATE (BPWM_CTL0_IMMLDEN0_Msk) /*!< BPWM immediately load mode \hideinitializer */
|
||||||
|
#define BPWM_LOAD_MODE_CENTER (BPWM_CTL0_CTRLD0_Msk) /*!< BPWM center load mode \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Clock Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define BPWM_CLKSRC_BPWM_CLK (0UL) /*!< BPWM Clock source selects to BPWM0_CLK or BPWM1_CLK \hideinitializer */
|
||||||
|
#define BPWM_CLKSRC_TIMER0 (1UL) /*!< BPWM Clock source selects to TIMER0 overflow \hideinitializer */
|
||||||
|
#define BPWM_CLKSRC_TIMER1 (2UL) /*!< BPWM Clock source selects to TIMER1 overflow \hideinitializer */
|
||||||
|
#define BPWM_CLKSRC_TIMER2 (3UL) /*!< BPWM Clock source selects to TIMER2 overflow \hideinitializer */
|
||||||
|
#define BPWM_CLKSRC_TIMER3 (4UL) /*!< BPWM Clock source selects to TIMER3 overflow \hideinitializer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BPWM_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup BPWM_EXPORTED_FUNCTIONS BPWM Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable timer synchronous start counting function of specified channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
|
||||||
|
* - \ref BPWM_SSCTL_SSRC_PWM0
|
||||||
|
* - \ref BPWM_SSCTL_SSRC_PWM1
|
||||||
|
* - \ref BPWM_SSCTL_SSRC_BPWM0
|
||||||
|
* - \ref BPWM_SSCTL_SSRC_BPWM1
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_ENABLE_TIMER_SYNC(bpwm, u32ChannelMask, u32SyncSrc) ((bpwm)->SSCTL = ((bpwm)->SSCTL & ~BPWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | BPWM_SSCTL_SSEN0_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable timer synchronous start counting function of specified channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_DISABLE_TIMER_SYNC(bpwm, u32ChannelMask) ((bpwm)->SSCTL &= ~BPWM_SSCTL_SSEN0_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enable BPWM counter synchronous start counting function.
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to make selected BPWM0 and BPWM1 channel(s) start counting at the same time.
|
||||||
|
* To configure synchronous start counting channel(s) by BPWM_ENABLE_TIMER_SYNC() and BPWM_DISABLE_TIMER_SYNC().
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_TRIGGER_SYNC_START(bpwm) ((bpwm)->SSTRG = BPWM_SSTRG_CNTSEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enable output inverter of specified channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_ENABLE_OUTPUT_INVERTER(bpwm, u32ChannelMask) ((bpwm)->POLCTL = (u32ChannelMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get captured rising data
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_GET_CAPTURE_RISING_DATA(bpwm, u32ChannelNum) (*(__IO uint32_t *) (&((bpwm)->RCAPDAT0) + 2 * (u32ChannelNum)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get captured falling data
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_GET_CAPTURE_FALLING_DATA(bpwm, u32ChannelNum) (*(__IO uint32_t *) (&((bpwm)->FCAPDAT0) + 2 * (u32ChannelNum)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro mask output logic to high or low
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @param[in] u32LevelMask Output logic to high or low
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to mask output logic to high or low of specified channel(s).
|
||||||
|
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_MASK_OUTPUT(bpwm, u32ChannelMask, u32LevelMask) \
|
||||||
|
{ \
|
||||||
|
(bpwm)->MSKEN = (u32ChannelMask); \
|
||||||
|
(bpwm)->MSK = (u32LevelMask); \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the prescaler of all channels
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFFF
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescaler) ((bpwm)->CLKPSC = (u32Prescaler))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the duty of the selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @return None
|
||||||
|
* @note This new setting will take effect on next BPWM period
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_SET_CMR(bpwm, u32ChannelNum, u32CMR) ((bpwm)->CMPDAT[(u32ChannelNum)] = (u32CMR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get the comparator of the selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5
|
||||||
|
* @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @details This macro is used to get the comparator of specified channel.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_GET_CMR(bpwm, u32ChannelNum) ((bpwm)->CMPDAT[(u32ChannelNum)])
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the period of all channels
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. This parameter is not used.
|
||||||
|
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @return None
|
||||||
|
* @note This new setting will take effect on next BPWM period
|
||||||
|
* @note BPWM counter will stop if period length set to 0
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR) ((bpwm)->PERIOD = (u32CNR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get the period of the selected channel
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelNum BPWM channel number. Valid values are between 0~5.
|
||||||
|
* @return Return the period of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @details This macro is used to get the period of specified channel.
|
||||||
|
* @note All channels share the same period.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_GET_CNR(bpwm, u32ChannelNum) ((bpwm)->PERIOD)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the BPWM aligned type
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @param[in] u32AlignedType BPWM aligned type, valid values are:
|
||||||
|
* - \ref BPWM_EDGE_ALIGNED
|
||||||
|
* - \ref BPWM_CENTER_ALIGNED
|
||||||
|
* @return None
|
||||||
|
* @note All channels share channel 0's setting.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_SET_ALIGNED_TYPE(bpwm, u32ChannelMask, u32AlignedType) ((bpwm)->CTL1 = (u32AlignedType))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear counter of channel 0
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. This parameter is not used.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to clear counter of channel 0
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_CLR_COUNTER(bpwm, u32ChannelMask) ((bpwm)->CNTCLR = (BPWM_CNTCLR_CNTCLR0_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
|
||||||
|
* @param[in] bpwm The pointer of the specified BPWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @param[in] u32ZeroLevel output level at zero point, valid values are:
|
||||||
|
* - \ref BPWM_OUTPUT_NOTHING
|
||||||
|
* - \ref BPWM_OUTPUT_LOW
|
||||||
|
* - \ref BPWM_OUTPUT_HIGH
|
||||||
|
* - \ref BPWM_OUTPUT_TOGGLE
|
||||||
|
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
|
||||||
|
* - \ref BPWM_OUTPUT_NOTHING
|
||||||
|
* - \ref BPWM_OUTPUT_LOW
|
||||||
|
* - \ref BPWM_OUTPUT_HIGH
|
||||||
|
* - \ref BPWM_OUTPUT_TOGGLE
|
||||||
|
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
|
||||||
|
* - \ref BPWM_OUTPUT_NOTHING
|
||||||
|
* - \ref BPWM_OUTPUT_LOW
|
||||||
|
* - \ref BPWM_OUTPUT_HIGH
|
||||||
|
* - \ref BPWM_OUTPUT_TOGGLE
|
||||||
|
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
|
||||||
|
* - \ref BPWM_OUTPUT_NOTHING
|
||||||
|
* - \ref BPWM_OUTPUT_LOW
|
||||||
|
* - \ref BPWM_OUTPUT_HIGH
|
||||||
|
* - \ref BPWM_OUTPUT_TOGGLE
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s)
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define BPWM_SET_OUTPUT_LEVEL(bpwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
|
||||||
|
do{ \
|
||||||
|
int i; \
|
||||||
|
for(i = 0; i < 6; i++) { \
|
||||||
|
if((u32ChannelMask) & (1 << i)) { \
|
||||||
|
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (2 * i))) | ((u32ZeroLevel) << (2 * i))); \
|
||||||
|
(bpwm)->WGCTL0 = (((bpwm)->WGCTL0 & ~(3UL << (BPWM_WGCTL0_PRDPCTL0_Pos + (2 * i)))) | ((u32PeriodLevel) << (BPWM_WGCTL0_PRDPCTL0_Pos + (2 * i)))); \
|
||||||
|
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (2 * i))) | ((u32CmpUpLevel) << (2 * i))); \
|
||||||
|
(bpwm)->WGCTL1 = (((bpwm)->WGCTL1 & ~(3UL << (BPWM_WGCTL1_CMPDCTL0_Pos + (2 * i)))) | ((u32CmpDownLevel) << (BPWM_WGCTL1_CMPDCTL0_Pos + (2 * i)))); \
|
||||||
|
} \
|
||||||
|
} \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define BPWM functions prototype */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
|
||||||
|
uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
|
||||||
|
void BPWM_Start(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_Stop(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_ForceStop(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_EnableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||||
|
void BPWM_DisableADCTrigger(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_ClearADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||||
|
uint32_t BPWM_GetADCTriggerFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_EnableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_DisableCapture(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_EnableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_DisableOutput(BPWM_T *bpwm, uint32_t u32ChannelMask);
|
||||||
|
void BPWM_EnableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||||
|
void BPWM_DisableCaptureInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||||
|
void BPWM_ClearCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||||
|
uint32_t BPWM_GetCaptureIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
||||||
|
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_ClearDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t BPWM_GetDutyIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_EnablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||||||
|
void BPWM_DisablePeriodInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_ClearPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t BPWM_GetPeriodIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_EnableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_DisableZeroInt(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_ClearZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t BPWM_GetZeroIntFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_EnableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||||
|
void BPWM_DisableLoadMode(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||||
|
void BPWM_SetClockSource(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
|
||||||
|
uint32_t BPWM_GetWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BPWM_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group BPWM_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__BPWM_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,177 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file can.h
|
||||||
|
* @version V1.00
|
||||||
|
* @brief M2351 Series CAN Driver Header File
|
||||||
|
*
|
||||||
|
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __CAN_H__
|
||||||
|
#define __CAN_H__
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN_Driver CAN Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CAN_EXPORTED_CONSTANTS CAN Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CAN Test Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CAN_NORMAL_MODE 0 /*!< CAN select normal mode */
|
||||||
|
#define CAN_BASIC_MODE 1 /*!< CAN select basic mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Message ID Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CAN_STD_ID 0 /*!< CAN select standard ID */
|
||||||
|
#define CAN_EXT_ID 1 /*!< CAN select extended ID */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Message Frame Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */
|
||||||
|
#define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group M2351_CAN_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup M2351_CAN_EXPORTED_STRUCTS CAN Exported Structs
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @details CAN message structure
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t IdType; /*!< ID type */
|
||||||
|
uint32_t FrameType; /*!< Frame type */
|
||||||
|
uint32_t Id; /*!< Message ID */
|
||||||
|
uint8_t DLC; /*!< Data length */
|
||||||
|
uint8_t Data[8]; /*!< Data */
|
||||||
|
} STR_CANMSG_T;
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @details CAN mask message structure
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint8_t u8Xtd; /*!< Extended ID */
|
||||||
|
uint8_t u8Dir; /*!< Direction */
|
||||||
|
uint32_t u32Id; /*!< Message ID */
|
||||||
|
uint8_t u8IdType; /*!< ID type*/
|
||||||
|
} STR_CANMASK_T;
|
||||||
|
|
||||||
|
/*@}*/ /* end of group M2351_CAN_EXPORTED_STRUCTS */
|
||||||
|
|
||||||
|
/// @cond HIDDEN_SYMBOLS
|
||||||
|
#define MSG(id) (id)
|
||||||
|
/// @endcond //HIDDEN_SYMBOLS
|
||||||
|
|
||||||
|
/** @addtogroup M2351_CAN_EXPORTED_FUNCTIONS CAN Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get interrupt status.
|
||||||
|
*
|
||||||
|
* @param[in] can The base address of can module.
|
||||||
|
*
|
||||||
|
* @return CAN module status register value.
|
||||||
|
*
|
||||||
|
* @details Status Interrupt is generated by bits BOff (CAN_STATUS[7]), EWarn (CAN_STATUS[6]),
|
||||||
|
* EPass (CAN_STATUS[5]), RxOk (CAN_STATUS[4]), TxOk (CAN_STATUS[3]), and LEC (CAN_STATUS[2:0]).
|
||||||
|
*/
|
||||||
|
#define CAN_GET_INT_STATUS(can) ((can)->STATUS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified interrupt pending status.
|
||||||
|
*
|
||||||
|
* @param[in] can The base address of can module.
|
||||||
|
*
|
||||||
|
* @return The source of the interrupt.
|
||||||
|
*
|
||||||
|
* @details If several interrupts are pending, the CAN Interrupt Register will point to the pending interrupt
|
||||||
|
* with the highest priority, disregarding their chronological order.
|
||||||
|
*/
|
||||||
|
#define CAN_GET_INT_PENDING_STATUS(can) ((can)->IIDR)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable wake-up function.
|
||||||
|
*
|
||||||
|
* @param[in] can The base address of can module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to disable wake-up function.
|
||||||
|
*/
|
||||||
|
#define CAN_DISABLE_WAKEUP(can) ((can)->WU_EN = 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable wake-up function.
|
||||||
|
*
|
||||||
|
* @param[in] can The base address of can module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details User can wake-up system when there is a falling edge in the CAN_Rx pin.
|
||||||
|
*/
|
||||||
|
#define CAN_ENABLE_WAKEUP(can) ((can)->WU_EN = CAN_WU_EN_WAKUP_EN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified Message Object new data into bit value.
|
||||||
|
*
|
||||||
|
* @param[in] can The base address of can module.
|
||||||
|
* @param[in] u32MsgNum Specified Message Object number, valid value are from 0 to 31.
|
||||||
|
*
|
||||||
|
* @return Specified Message Object new data into bit value.
|
||||||
|
*
|
||||||
|
* @details The NewDat bit (CAN_IFn_MCON[15]) of a specific Message Object can be set/reset by the software through the IFn Message Interface Registers
|
||||||
|
* or by the Message Handler after reception of a Data Frame or after a successful transmission.
|
||||||
|
*/
|
||||||
|
#define CAN_GET_NEW_DATA_IN_BIT(can, u32MsgNum) ((u32MsgNum) < 16 ? (can)->NDAT1 & (1 << (u32MsgNum)) : (can)->NDAT2 & (1 << ((u32MsgNum)-16)))
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define CAN functions prototype */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
uint32_t CAN_SetBaudRate(CAN_T *tCAN, uint32_t u32BaudRate);
|
||||||
|
uint32_t CAN_Open(CAN_T *tCAN, uint32_t u32BaudRate, uint32_t u32Mode);
|
||||||
|
void CAN_Close(CAN_T *tCAN);
|
||||||
|
void CAN_CLR_INT_PENDING_BIT(CAN_T *tCAN, uint8_t u32MsgNum);
|
||||||
|
void CAN_EnableInt(CAN_T *tCAN, uint32_t u32Mask);
|
||||||
|
void CAN_DisableInt(CAN_T *tCAN, uint32_t u32Mask);
|
||||||
|
int32_t CAN_Transmit(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
|
||||||
|
int32_t CAN_Receive(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
|
||||||
|
int32_t CAN_SetMultiRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32MsgCount, uint32_t u32IDType, uint32_t u32ID);
|
||||||
|
int32_t CAN_SetRxMsg(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID);
|
||||||
|
int32_t CAN_SetRxMsgAndMsk(CAN_T *tCAN, uint32_t u32MsgNum , uint32_t u32IDType, uint32_t u32ID, uint32_t u32IDMask);
|
||||||
|
int32_t CAN_SetTxMsg(CAN_T *tCAN, uint32_t u32MsgNum , STR_CANMSG_T* pCanMsg);
|
||||||
|
int32_t CAN_TriggerTxMsg(CAN_T *tCAN, uint32_t u32MsgNum);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CAN_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CAN_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__CAN_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,744 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file clk.h
|
||||||
|
* @version V3.0
|
||||||
|
* @brief M2351 series Clock Controller (CLK) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __CLK_H__
|
||||||
|
#define __CLK_H__
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CLK_Driver CLK Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CLK_EXPORTED_CONSTANTS CLK Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define FREQ_24MHZ 24000000
|
||||||
|
#define FREQ_48MHZ 48000000
|
||||||
|
#define FREQ_50MHZ 50000000
|
||||||
|
#define FREQ_100MHZ 100000000
|
||||||
|
#define FREQ_200MHZ 200000000
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKSEL0 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKSEL0_HCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HXT */
|
||||||
|
#define CLK_CLKSEL0_HCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LXT */
|
||||||
|
#define CLK_CLKSEL0_HCLKSEL_PLL (0x02UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as PLL */
|
||||||
|
#define CLK_CLKSEL0_HCLKSEL_LIRC (0x03UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as LIRC */
|
||||||
|
#define CLK_CLKSEL0_HCLKSEL_HIRC (0x07UL<<CLK_CLKSEL0_HCLKSEL_Pos) /*!< Setting HCLK clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL0_STCLKSEL_HXT (0x00UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
|
||||||
|
#define CLK_CLKSEL0_STCLKSEL_LXT (0x01UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as LXT */
|
||||||
|
#define CLK_CLKSEL0_STCLKSEL_HXT_DIV2 (0x02UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HXT */
|
||||||
|
#define CLK_CLKSEL0_STCLKSEL_HCLK_DIV2 (0x03UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HCLK/2 */
|
||||||
|
#define CLK_CLKSEL0_STCLKSEL_HIRC_DIV2 (0x07UL<<CLK_CLKSEL0_STCLKSEL_Pos) /*!< Setting SysTick clock source as HIRC/2 */
|
||||||
|
#define CLK_CLKSEL0_STCLKSEL_HCLK (0x01UL<<SysTick_CTRL_CLKSOURCE_Pos) /*!< Setting SysTick clock source as HCLK */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL0_PCLK0SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK */
|
||||||
|
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/2 */
|
||||||
|
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV4 (0x02UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/4 */
|
||||||
|
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV8 (0x03UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/8 */
|
||||||
|
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV16 (0x04UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/16 */
|
||||||
|
#define CLK_CLKSEL0_PCLK0SEL_HCLK_DIV32 (0x05UL<<CLK_CLKSEL0_PCLK0SEL_Pos) /*!< Setting PCLK0 clock source as HCLK/32 */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL0_PCLK1SEL_HCLK (0x00UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK */
|
||||||
|
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV2 (0x01UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/2 */
|
||||||
|
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV4 (0x02UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/4 */
|
||||||
|
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV8 (0x03UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/8 */
|
||||||
|
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV16 (0x04UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/16 */
|
||||||
|
#define CLK_CLKSEL0_PCLK1SEL_HCLK_DIV32 (0x05UL<<CLK_CLKSEL0_PCLK1SEL_Pos) /*!< Setting PCLK1 clock source as HCLK/32 */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL0_SDH0SEL_HXT (0x00UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL0_SDH0SEL_PLL (0x01UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL0_SDH0SEL_HCLK (0x02UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HCLK */
|
||||||
|
#define CLK_CLKSEL0_SDH0SEL_HIRC (0x03UL<<CLK_CLKSEL0_SDH0SEL_Pos) /*!< Setting SDH0 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL0_USBHSEL_PLL (0x01UL<<CLK_CLKSEL0_USBHSEL_Pos) /*!< Setting USBH clock source as PLL */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1 (0x00UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1_DIV2 (0x01UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1/2 */
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1_DIV4 (0x02UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1/4 */
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1_DIV8 (0x03UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1/8 */
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1_DIV16 (0x04UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1/16 */
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1_DIV32 (0x05UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1/32 */
|
||||||
|
#define CLK_CLKSEL0_RTCP1SEL_PCLK1_DIV64 (0x06UL<<CLK_CLKSEL0_RTCP1SEL_Pos) /*!< Setting RTC Bus clock source as PCLK1/64 */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKSEL1 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKSEL1_WDTSEL_LXT (0x1UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */
|
||||||
|
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_DSRCSEL_HIRC (0x1UL<<CLK_CLKSEL1_DSRCSEL_Pos) /*!< Setting DSRC clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL1_TMR0SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as external trigger */
|
||||||
|
#define CLK_CLKSEL1_TMR0SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LIRC */
|
||||||
|
#define CLK_CLKSEL1_TMR0SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_TMR1SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_TMR1SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_TMR1SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL1_TMR1SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as external trigger */
|
||||||
|
#define CLK_CLKSEL1_TMR1SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as LIRC */
|
||||||
|
#define CLK_CLKSEL1_TMR1SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR1SEL_Pos) /*!< Setting Timer 1 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_TMR2SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_TMR2SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_TMR2SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL1_TMR2SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as external trigger */
|
||||||
|
#define CLK_CLKSEL1_TMR2SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as LIRC */
|
||||||
|
#define CLK_CLKSEL1_TMR2SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR2SEL_Pos) /*!< Setting Timer 2 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_TMR3SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_TMR3SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_TMR3SEL_PCLK1 (0x2UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL1_TMR3SEL_EXT_TRG (0x3UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as external trigger */
|
||||||
|
#define CLK_CLKSEL1_TMR3SEL_LIRC (0x5UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as LIRC */
|
||||||
|
#define CLK_CLKSEL1_TMR3SEL_HIRC (0x7UL<<CLK_CLKSEL1_TMR3SEL_Pos) /*!< Setting Timer 3 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_UART0SEL_HXT (0x0UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_UART0SEL_PLL (0x1UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL1_UART0SEL_LXT (0x2UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_UART0SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART0SEL_Pos) /*!< Setting UART0 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_UART1SEL_HXT (0x0UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_UART1SEL_PLL (0x1UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL1_UART1SEL_LXT (0x2UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_UART1SEL_HIRC (0x3UL<<CLK_CLKSEL1_UART1SEL_Pos) /*!< Setting UART1 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_CLKOSEL_HXT (0x0UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HXT */
|
||||||
|
#define CLK_CLKSEL1_CLKOSEL_LXT (0x1UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as LXT */
|
||||||
|
#define CLK_CLKSEL1_CLKOSEL_HCLK (0x2UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HCLK */
|
||||||
|
#define CLK_CLKSEL1_CLKOSEL_HIRC (0x3UL<<CLK_CLKSEL1_CLKOSEL_Pos) /*!< Setting CLKO clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL1_WWDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as HCLK/2048 */
|
||||||
|
#define CLK_CLKSEL1_WWDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WWDTSEL_Pos) /*!< Setting WWDT clock source as LIRC */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKSEL2 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKSEL2_PWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_PWM0SEL_Pos) /*!< Setting PWM0 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL2_PWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_PWM1SEL_Pos) /*!< Setting PWM1 clock source as PCLK1 */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_BPWM0SEL_PCLK0 (0x1UL<<CLK_CLKSEL2_BPWM0SEL_Pos) /*!< Setting BPWM0 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL2_BPWM1SEL_PCLK1 (0x1UL<<CLK_CLKSEL2_BPWM1SEL_Pos) /*!< Setting BPWM1 clock source as PCLK1 */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_SPI0SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL2_SPI0SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL2_SPI0SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL2_SPI0SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI0SEL_Pos) /*!< Setting SPI0 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_SPI1SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL2_SPI1SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL2_SPI1SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL2_SPI1SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI1SEL_Pos) /*!< Setting SPI1 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_SPI2SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL2_SPI2SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL2_SPI2SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL2_SPI2SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI2SEL_Pos) /*!< Setting SPI2 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_SPI3SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL2_SPI3SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL2_SPI3SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_SPI4SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI4SEL_Pos) /*!< Setting SPI4 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL2_SPI4SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI4SEL_Pos) /*!< Setting SPI4 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL2_SPI4SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI4SEL_Pos) /*!< Setting SPI4 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL2_SPI4SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI4SEL_Pos) /*!< Setting SPI4 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL2_SPI5SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL2_SPI5SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL2_SPI5SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL2_SPI5SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as HIRC */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKSEL3 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKSEL3_SC0SEL_HXT (0x0UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_SC0SEL_PLL (0x1UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_SC0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL3_SC0SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC0SEL_Pos) /*!< Setting SC0 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_SC1SEL_HXT (0x0UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_SC1SEL_PLL (0x1UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_SC1SEL_PCLK1 (0x2UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL3_SC1SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC1SEL_Pos) /*!< Setting SC1 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_SC2SEL_HXT (0x0UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_SC2SEL_PLL (0x1UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_SC2SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as PCLK1 */
|
||||||
|
#define CLK_CLKSEL3_SC2SEL_HIRC (0x3UL<<CLK_CLKSEL3_SC2SEL_Pos) /*!< Setting SC2 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_RTCSEL_LXT (0x0UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LXT */
|
||||||
|
#define CLK_CLKSEL3_RTCSEL_LIRC (0x1UL<<CLK_CLKSEL3_RTCSEL_Pos) /*!< Setting RTC clock source as LIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_I2S0SEL_HXT (0x0UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_I2S0SEL_PLL (0x1UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_I2S0SEL_PCLK0 (0x2UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as PCLK0 */
|
||||||
|
#define CLK_CLKSEL3_I2S0SEL_HIRC (0x3UL<<CLK_CLKSEL3_I2S0SEL_Pos) /*!< Setting I2S0 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_UART2SEL_HXT (0x0UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_UART2SEL_PLL (0x1UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_UART2SEL_LXT (0x2UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL3_UART2SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART2SEL_Pos) /*!< Setting UART2 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_UART3SEL_HXT (0x0UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_UART3SEL_PLL (0x1UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_UART3SEL_LXT (0x2UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL3_UART3SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART3SEL_Pos) /*!< Setting UART3 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_UART4SEL_HXT (0x0UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_UART4SEL_PLL (0x1UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_UART4SEL_LXT (0x2UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL3_UART4SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART4SEL_Pos) /*!< Setting UART4 clock source as HIRC */
|
||||||
|
|
||||||
|
#define CLK_CLKSEL3_UART5SEL_HXT (0x0UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as HXT */
|
||||||
|
#define CLK_CLKSEL3_UART5SEL_PLL (0x1UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as PLL */
|
||||||
|
#define CLK_CLKSEL3_UART5SEL_LXT (0x2UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as LXT */
|
||||||
|
#define CLK_CLKSEL3_UART5SEL_HIRC (0x3UL<<CLK_CLKSEL3_UART5SEL_Pos) /*!< Setting UART5 clock source as HIRC */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKDIV0 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKDIV0_HCLK(x) (((x)-1) << CLK_CLKDIV0_HCLKDIV_Pos) /*!< CLKDIV0 Setting for HCLK clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV0_USB(x) (((x)-1) << CLK_CLKDIV0_USBDIV_Pos) /*!< CLKDIV0 Setting for USB clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV0_UART0(x) (((x)-1) << CLK_CLKDIV0_UART0DIV_Pos) /*!< CLKDIV0 Setting for UART0 clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV0_UART1(x) (((x)-1) << CLK_CLKDIV0_UART1DIV_Pos) /*!< CLKDIV0 Setting for UART1 clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV0_EADC(x) (((x)-1) << CLK_CLKDIV0_EADCDIV_Pos) /*!< CLKDIV0 Setting for EADC clock divider. It could be 1~256 */
|
||||||
|
#define CLK_CLKDIV0_SDH0(x) (((x)-1) << CLK_CLKDIV0_SDH0DIV_Pos) /*!< CLKDIV0 Setting for SDH0 clock divider. It could be 1~256 */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKDIV1 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKDIV1_SC0(x) (((x)-1) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */
|
||||||
|
#define CLK_CLKDIV1_SC1(x) (((x)-1) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 */
|
||||||
|
#define CLK_CLKDIV1_SC2(x) (((x)-1) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 */
|
||||||
|
#define CLK_CLKDIV1_DSRC(x) (((x)-1) << CLK_CLKDIV1_DSRCDIV_Pos) /*!< CLKDIV1 Setting for DSRC clock divider. It could be 1~64 */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CLKDIV4 constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_CLKDIV4_UART2(x) (((x)-1) << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLKDIV4 Setting for UART2 clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV4_UART3(x) (((x)-1) << CLK_CLKDIV4_UART3DIV_Pos) /*!< CLKDIV4 Setting for UART3 clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV4_UART4(x) (((x)-1) << CLK_CLKDIV4_UART4DIV_Pos) /*!< CLKDIV4 Setting for UART4 clock divider. It could be 1~16 */
|
||||||
|
#define CLK_CLKDIV4_UART5(x) (((x)-1) << CLK_CLKDIV4_UART5DIV_Pos) /*!< CLKDIV4 Setting for UART5 clock divider. It could be 1~16 */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* PLLCTL constant definitions. PLL = FIN * (2*NF) / NR / NO */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_PLLCTL_PLLSRC_HXT 0x00000000UL /*!< For PLL clock source is HXT. 2MHz < FIN/NR < 8MHz */
|
||||||
|
#define CLK_PLLCTL_PLLSRC_HIRC 0x00080000UL /*!< For PLL clock source is HIRC. 2MHz < FIN/NR < 8MHz */
|
||||||
|
|
||||||
|
#define CLK_PLLCTL_NF(x) ((x)-2) /*!< x must be constant and 2 <= x <= 513. 96MHz < FIN*(2*NF)/NR < 200MHz */
|
||||||
|
#define CLK_PLLCTL_NR(x) (((x)-1)<<9) /*!< x must be constant and 2 <= x <= 33. 2MHz < FIN/NR < 8MHz */
|
||||||
|
|
||||||
|
#define CLK_PLLCTL_NO_1 0x0000UL /*!< For output divider is 1 */
|
||||||
|
#define CLK_PLLCTL_NO_2 0x4000UL /*!< For output divider is 2 */
|
||||||
|
#define CLK_PLLCTL_NO_4 0xC000UL /*!< For output divider is 4 */
|
||||||
|
|
||||||
|
#define CLK_PLLCTL_48MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with HXT */
|
||||||
|
#define CLK_PLLCTL_48MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_4) /*!< Predefined PLLCTL setting for 48MHz PLL output with HIRC */
|
||||||
|
|
||||||
|
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT */
|
||||||
|
#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2) | CLK_PLLCTL_NF(16) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HIRC */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* MODULE constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* APBCLK(31:30)|CLKSEL(29:28)|CLKSEL_Msk(27:25) |CLKSEL_Pos(24:20)|CLKDIV(19:18)|CLKDIV_Msk(17:10)|CLKDIV_Pos(9:5)|IP_EN_Pos(4:0) */
|
||||||
|
|
||||||
|
#define MODULE_APBCLK(x) (((x) >>30) & 0x3) /*!< Calculate AHBCLK/APBCLK offset on MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
|
||||||
|
#define MODULE_CLKSEL(x) (((x) >>28) & 0x3) /*!< Calculate CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
|
||||||
|
#define MODULE_CLKSEL_Msk(x) (((x) >>25) & 0x7) /*!< Calculate CLKSEL mask offset on MODULE index */
|
||||||
|
#define MODULE_CLKSEL_Pos(x) (((x) >>20) & 0x1f) /*!< Calculate CLKSEL position offset on MODULE index */
|
||||||
|
#define MODULE_CLKDIV(x) (((x) >>18) & 0x3) /*!< Calculate APBCLK CLKDIV on MODULE index, 0x0:CLKDIV0, 0x1:CLKDIV1, 0x4:CLKDIV4 */
|
||||||
|
#define MODULE_CLKDIV_Msk(x) (((x) >>10) & 0xff) /*!< Calculate CLKDIV mask offset on MODULE index */
|
||||||
|
#define MODULE_CLKDIV_Pos(x) (((x) >>5 ) & 0x1f) /*!< Calculate CLKDIV position offset on MODULE index */
|
||||||
|
#define MODULE_IP_EN_Pos(x) (((x) >>0 ) & 0x1f) /*!< Calculate APBCLK offset on MODULE index */
|
||||||
|
#define MODULE_NoMsk 0x0 /*!< Not mask on MODULE index */
|
||||||
|
#define NA MODULE_NoMsk /*!< Not Available */
|
||||||
|
|
||||||
|
#define MODULE_APBCLK_ENC(x) (((x) & 0x03) << 30) /*!< MODULE index, 0x0:AHBCLK, 0x1:APBCLK0, 0x2:APBCLK1 */
|
||||||
|
#define MODULE_CLKSEL_ENC(x) (((x) & 0x03) << 28) /*!< CLKSEL offset on MODULE index, 0x0:CLKSEL0, 0x1:CLKSEL1, 0x2:CLKSEL2, 0x3:CLKSEL3 */
|
||||||
|
#define MODULE_CLKSEL_Msk_ENC(x) (((x) & 0x07) << 25) /*!< CLKSEL mask offset on MODULE index */
|
||||||
|
#define MODULE_CLKSEL_Pos_ENC(x) (((x) & 0x1f) << 20) /*!< CLKSEL position offset on MODULE index */
|
||||||
|
#define MODULE_CLKDIV_ENC(x) (((x) & 0x03) << 18) /*!< APBCLK CLKDIV on MODULE index, 0x0:CLKDIV, 0x1:CLKDIV1, 0x4:CLKDIV4 */
|
||||||
|
#define MODULE_CLKDIV_Msk_ENC(x) (((x) & 0xff) << 10) /*!< CLKDIV mask offset on MODULE index */
|
||||||
|
#define MODULE_CLKDIV_Pos_ENC(x) (((x) & 0x1f) << 5) /*!< CLKDIV position offset on MODULE index */
|
||||||
|
#define MODULE_IP_EN_Pos_ENC(x) (((x) & 0x1f) << 0) /*!< AHBCLK/APBCLK offset on MODULE index */
|
||||||
|
|
||||||
|
|
||||||
|
//AHBCLK
|
||||||
|
#define PDMA0_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMA0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
|
||||||
|
|
||||||
|
#define PDMA1_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_PDMA1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PDMA Module */
|
||||||
|
|
||||||
|
#define ISP_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_ISPCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ISP Module */
|
||||||
|
|
||||||
|
#define EBI_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_EBICKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< EBI Module */
|
||||||
|
|
||||||
|
#define SDH0_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_SDH0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 0)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(20)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(24)) /*!< SDH0 Module */
|
||||||
|
|
||||||
|
#define CRC_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRCCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
|
||||||
|
|
||||||
|
#define CRPT_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_CRPTCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */
|
||||||
|
|
||||||
|
#define USBH_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_USBHCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xF)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBH Module */
|
||||||
|
|
||||||
|
//APBCLK0
|
||||||
|
#define WDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WDT Module */
|
||||||
|
|
||||||
|
#define WWDT_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_WDTCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(30)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< WWDT Module */
|
||||||
|
|
||||||
|
#define RTC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_RTCCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 8)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< RTC Module */
|
||||||
|
|
||||||
|
#define TMR0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC( 8)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR0 Module */
|
||||||
|
|
||||||
|
#define TMR1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR1CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(12)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR1 Module */
|
||||||
|
|
||||||
|
#define TMR2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR2CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(16)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR2 Module */
|
||||||
|
|
||||||
|
#define TMR3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_TMR3CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 7)|MODULE_CLKSEL_Pos_ENC(20)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TMR3 Module */
|
||||||
|
|
||||||
|
#define CLKO_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CLKOCKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CLKO Module */
|
||||||
|
|
||||||
|
#define ACMP01_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_ACMP01CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ACMP01 Module */
|
||||||
|
|
||||||
|
#define I2C0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C0CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C0 Module */
|
||||||
|
|
||||||
|
#define I2C1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C1CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C1 Module */
|
||||||
|
|
||||||
|
#define I2C2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2C2CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2C2 Module */
|
||||||
|
|
||||||
|
#define SPI0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI0CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(2)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI0 Module */
|
||||||
|
|
||||||
|
#define SPI1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI1CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(4)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI1 Module */
|
||||||
|
|
||||||
|
#define SPI2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI2CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(6)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI2 Module */
|
||||||
|
|
||||||
|
#define SPI3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_SPI3CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(10)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */
|
||||||
|
|
||||||
|
#define UART0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART0 Module */
|
||||||
|
|
||||||
|
#define UART1_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(26)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(12)) /*!< UART1 Module */
|
||||||
|
|
||||||
|
#define UART2_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART2CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
|
||||||
|
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< UART2 Module */
|
||||||
|
|
||||||
|
#define UART3_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART3CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(26)|\
|
||||||
|
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 4)) /*!< UART3 Module */
|
||||||
|
|
||||||
|
#define UART4_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART4CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(28)|\
|
||||||
|
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< UART4 Module */
|
||||||
|
|
||||||
|
#define UART5_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_UART5CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(30)|\
|
||||||
|
MODULE_CLKDIV_ENC( 3)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(12)) /*!< UART5 Module */
|
||||||
|
|
||||||
|
#define DSRC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_DSRCCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 1)|MODULE_CLKSEL_Pos_ENC( 3)|\
|
||||||
|
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0x1F)|MODULE_CLKDIV_Pos_ENC(24)) /*!< DSRC Module */
|
||||||
|
|
||||||
|
#define CAN0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_CAN0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */
|
||||||
|
|
||||||
|
#define OTG_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_OTGCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 1)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(24)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC( 4)) /*!< OTG Module */
|
||||||
|
|
||||||
|
#define USBD_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_USBDCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0x0F)|MODULE_CLKDIV_Pos_ENC(4)) /*!< USBD Module */
|
||||||
|
|
||||||
|
#define EADC_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_EADCCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC( 0)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< EADC Module */
|
||||||
|
|
||||||
|
#define I2S0_MODULE (MODULE_APBCLK_ENC( 1)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK0_I2S0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(16)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< I2S0 Module */
|
||||||
|
|
||||||
|
//APBCLK1
|
||||||
|
#define SC0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC0CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 0)|\
|
||||||
|
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 0)) /*!< SC0 Module */
|
||||||
|
|
||||||
|
#define SC1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC1CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 2)|\
|
||||||
|
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC( 8)) /*!< SC1 Module */
|
||||||
|
|
||||||
|
#define SC2_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SC2CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 3)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC( 4)|\
|
||||||
|
MODULE_CLKDIV_ENC( 1)|MODULE_CLKDIV_Msk_ENC(0xFF)|MODULE_CLKDIV_Pos_ENC(16)) /*!< SC2 Module */
|
||||||
|
|
||||||
|
#define SPI4_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SPI4CKEN_Pos) |\
|
||||||
|
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(12)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI4 Module */
|
||||||
|
|
||||||
|
#define SPI5_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_SPI5CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC( 2)|MODULE_CLKSEL_Msk_ENC( 3)|MODULE_CLKSEL_Pos_ENC(14)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI5 Module */
|
||||||
|
|
||||||
|
#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */
|
||||||
|
|
||||||
|
#define USCI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_USCI1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI1 Module */
|
||||||
|
|
||||||
|
#define DAC_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_DACCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< DAC Module */
|
||||||
|
|
||||||
|
#define PWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM0 Module */
|
||||||
|
|
||||||
|
#define PWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_PWM1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< PWM1 Module */
|
||||||
|
|
||||||
|
#define BPWM0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM0 Module */
|
||||||
|
|
||||||
|
#define BPWM1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_BPWM1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< BPWM1 Module */
|
||||||
|
|
||||||
|
#define QEI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_QEI0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI0 Module */
|
||||||
|
|
||||||
|
#define QEI1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_QEI1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< QEI1 Module */
|
||||||
|
|
||||||
|
#define TRNG_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_TRNGCKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< TRNG Module */
|
||||||
|
|
||||||
|
#define ECAP0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_ECAP0CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP0 Module */
|
||||||
|
|
||||||
|
#define ECAP1_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC(CLK_APBCLK1_ECAP1CKEN_Pos)|\
|
||||||
|
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
|
||||||
|
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< ECAP1 Module */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* PDMSEL constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Power-down mode */
|
||||||
|
#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Low leakage Power-down mode */
|
||||||
|
#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Fast Wake-up Power-down mode */
|
||||||
|
#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Standby Power-down mode */
|
||||||
|
#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Deep Power-down mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* WKTMRIS constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) */
|
||||||
|
#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* SWKDBCLKSEL constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_1 (0x0UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 1 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_2 (0x1UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_4 (0x2UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_8 (0x3UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_16 (0x4UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_32 (0x5UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_64 (0x6UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_128 (0x7UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_256 (0x8UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_2x256 (0x9UL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 2x256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_4x256 (0xaUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 4x256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_8x256 (0xbUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 8x256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_16x256 (0xcUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 16x256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_32x256 (0xdUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 32x256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_64x256 (0xeUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 64x256 clocks */
|
||||||
|
#define CLK_SWKDBCTL_SWKDBCLKSEL_128x256 (0xfUL << CLK_SWKDBCTL_SWKDBCLKSEL_Pos) /*!< Select Standby Power-down Pin De-bounce Sampling Cycle is 128x256 clocks */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* DPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_DPDWKPIN_DISABLE (0x0UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Disable Wake-up pin at Deep Power-down mode */
|
||||||
|
#define CLK_DPDWKPIN_RISING (0x1UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin rising edge at Deep Power-down mode */
|
||||||
|
#define CLK_DPDWKPIN_FALLING (0x2UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin falling edge at Deep Power-down mode */
|
||||||
|
#define CLK_DPDWKPIN_BOTHEDGE (0x3UL << CLK_PMUCTL_WKPINEN_Pos) /*!< Enable Wake-up pin both edge at Deep Power-down mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* SPD Pin Rising/Falling Edge Wake-up Enable constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CLK_SPDWKPIN_ENABLE (0x1UL << 0) /*!< Enable Standby Power-down Pin Wake-up */
|
||||||
|
#define CLK_SPDWKPIN_RISING (0x1UL << 1) /*!< Standby Power-down Wake-up on Standby Power-down Pin rising edge */
|
||||||
|
#define CLK_SPDWKPIN_FALLING (0x1UL << 2) /*!< Standby Power-down Wake-up on Standby Power-down Pin falling edge */
|
||||||
|
#define CLK_SPDWKPIN_DEBOUNCEEN (0x1UL << 8) /*!< Enable Standby power-down pin De-bounce function */
|
||||||
|
#define CLK_SPDWKPIN_DEBOUNCEDIS (0x0UL << 8) /*!< Disable Standby power-down pin De-bounce function */
|
||||||
|
|
||||||
|
#define CLK_DISABLE_WKTMR(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKTMREN_Msk) /*!< Disable Wake-up timer at Standby or Deep Power-down mode */
|
||||||
|
#define CLK_ENABLE_WKTMR(void) (CLK->PMUCTL |= CLK_PMUCTL_WKTMREN_Msk) /*!< Enable Wake-up timer at Standby or Deep Power-down mode */
|
||||||
|
#define CLK_DISABLE_DPDWKPIN(void) (CLK->PMUCTL &= ~CLK_PMUCTL_WKPINEN_Msk) /*!< Disable Wake-up pin at Deep Power-down mode */
|
||||||
|
#define CLK_DISABLE_SPDACMP(void) (CLK->PMUCTL &= ~CLK_PMUCTL_ACMPSPWK_Msk) /*!< Disable ACMP wake-up at Standby Power-down mode */
|
||||||
|
#define CLK_ENABLE_SPDACMP(void) (CLK->PMUCTL |= CLK_PMUCTL_ACMPSPWK_Msk) /*!< Enable ACMP wake-up at Standby Power-down mode */
|
||||||
|
#define CLK_DISABLE_SPDLVD(void) (CLK->PMUCTL &= ~CLK_PMUCTL_LVDSPWK_Msk) /*!< Disable LVD wake-up at Standby Power-down mode */
|
||||||
|
#define CLK_ENABLE_SPDLVD(void) (CLK->PMUCTL |= CLK_PMUCTL_LVDSPWK_Msk) /*!< Enable LVD wake-up at Standby Power-down mode */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CLK_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup CLK_EXPORTED_FUNCTIONS CLK Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Wake-up Timer Time-out Interval
|
||||||
|
*
|
||||||
|
* @param[in] u32Interval The de-bounce sampling cycle selection. It could be
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_128
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_256
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_512
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_1024
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_4096
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_8192
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_16384
|
||||||
|
* - \ref CLK_PMUCTL_WKTMRIS_65536
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set Wake-up Timer Time-out Interval.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define CLK_SET_WKTMR_INTERVAL(u32Interval) (CLK->PMUCTL |= (u32Interval))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set De-bounce Sampling Cycle Time
|
||||||
|
*
|
||||||
|
* @param[in] u32CycleSel The de-bounce sampling cycle selection. It could be
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_1
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_2x256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_4x256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_8x256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_16x256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_32x256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_64x256
|
||||||
|
* - \ref CLK_SWKDBCTL_SWKDBCLKSEL_128x256
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set Set De-bounce Sampling Cycle Time.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define CLK_SET_SPDDEBOUNCETIME(u32CycleSel) (CLK->SWKDBCTL = (u32CycleSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function execute delay function.
|
||||||
|
* @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
|
||||||
|
* 72MHz => 233016us, 50MHz => 335544us,
|
||||||
|
48MHz => 349525us, 28MHz => 699050us ...
|
||||||
|
* @return None
|
||||||
|
* @details Use the SysTick to generate the delay time and the UNIT is in us.
|
||||||
|
* The SysTick clock source is from HCLK, i.e the same as system core clock.
|
||||||
|
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void CLK_SysTickDelay(uint32_t us)
|
||||||
|
{
|
||||||
|
SysTick->LOAD = us * CyclesPerUs;
|
||||||
|
SysTick->VAL = (0x00);
|
||||||
|
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||||
|
|
||||||
|
/* Waiting for down-count to zero */
|
||||||
|
while((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
|
||||||
|
|
||||||
|
/* Disable SysTick counter */
|
||||||
|
SysTick->CTRL = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||||
|
/**
|
||||||
|
* @brief This function execute delay function.
|
||||||
|
* @param[in] us Delay time. The Max value is 2^24 / CPU Clock(MHz). Ex:
|
||||||
|
* 72MHz => 233016us, 50MHz => 335544us,
|
||||||
|
48MHz => 349525us, 28MHz => 699050us ...
|
||||||
|
* @return None
|
||||||
|
* @details Use the SysTick to generate the delay time and the UNIT is in us.
|
||||||
|
* The SysTick clock source is from HCLK, i.e the same as system core clock.
|
||||||
|
* User can use SystemCoreClockUpdate() to calculate CyclesPerUs automatically before using this function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void CLK_SysTickDelay_NS(uint32_t us)
|
||||||
|
{
|
||||||
|
SysTick_NS->LOAD = us * CyclesPerUs;
|
||||||
|
SysTick_NS->VAL = (0x00);
|
||||||
|
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
|
||||||
|
|
||||||
|
/* Waiting for down-count to zero */
|
||||||
|
while((SysTick_NS->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == 0);
|
||||||
|
|
||||||
|
/* Disable SysTick counter */
|
||||||
|
SysTick_NS->CTRL = 0;
|
||||||
|
}
|
||||||
|
#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void CLK_DisableCKO(void);
|
||||||
|
void CLK_EnableCKO(uint32_t u32ClkSrc, uint32_t u32ClkDiv, uint32_t u32ClkDivBy1En);
|
||||||
|
void CLK_PowerDown(void);
|
||||||
|
void CLK_Idle(void);
|
||||||
|
uint32_t CLK_GetHXTFreq(void);
|
||||||
|
uint32_t CLK_GetLXTFreq(void);
|
||||||
|
uint32_t CLK_GetHCLKFreq(void);
|
||||||
|
uint32_t CLK_GetPCLK0Freq(void);
|
||||||
|
uint32_t CLK_GetPCLK1Freq(void);
|
||||||
|
uint32_t CLK_GetCPUFreq(void);
|
||||||
|
uint32_t CLK_SetCoreClock(uint32_t u32Hclk);
|
||||||
|
void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||||
|
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv);
|
||||||
|
void CLK_SetSysTickClockSrc(uint32_t u32ClkSrc);
|
||||||
|
void CLK_EnableXtalRC(uint32_t u32ClkMask);
|
||||||
|
void CLK_DisableXtalRC(uint32_t u32ClkMask);
|
||||||
|
void CLK_EnableModuleClock(uint32_t u32ModuleIdx);
|
||||||
|
void CLK_DisableModuleClock(uint32_t u32ModuleIdx);
|
||||||
|
uint32_t CLK_EnablePLL(uint32_t u32PllClkSrc, uint32_t u32PllFreq);
|
||||||
|
void CLK_DisablePLL(void);
|
||||||
|
uint32_t CLK_WaitClockReady(uint32_t u32ClkMask);
|
||||||
|
void CLK_EnableSysTick(uint32_t u32ClkSrc, uint32_t u32Count);
|
||||||
|
void CLK_DisableSysTick(void);
|
||||||
|
void CLK_SetPowerDownMode(uint32_t u32PDMode);
|
||||||
|
void CLK_EnableDPDWKPin(uint32_t u32TriggerType);
|
||||||
|
uint32_t CLK_GetPMUWKSrc(void);
|
||||||
|
void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn);
|
||||||
|
uint32_t CLK_GetPLLClockFreq(void);
|
||||||
|
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx);
|
||||||
|
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx);
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CLK_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif //__CLK_H__
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,124 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file crc.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Cyclic Redundancy Check(CRC) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_Driver CRC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CRC Open
|
||||||
|
*
|
||||||
|
* @param[in] u32Mode CRC operation polynomial mode. Valid values are:
|
||||||
|
* - \ref CRC_CCITT
|
||||||
|
* - \ref CRC_8
|
||||||
|
* - \ref CRC_16
|
||||||
|
* - \ref CRC_32
|
||||||
|
* @param[in] u32Attribute CRC operation data attribute. Valid values are combined with:
|
||||||
|
* - \ref CRC_CHECKSUM_COM
|
||||||
|
* - \ref CRC_CHECKSUM_RVS
|
||||||
|
* - \ref CRC_WDATA_COM
|
||||||
|
* - \ref CRC_WDATA_RVS
|
||||||
|
* @param[in] u32Seed Seed value.
|
||||||
|
* @param[in] u32DataLen CPU Write Data Length. Valid values are:
|
||||||
|
* - \ref CRC_CPU_WDATA_8
|
||||||
|
* - \ref CRC_CPU_WDATA_16
|
||||||
|
* - \ref CRC_CPU_WDATA_32
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will enable the CRC controller by specify CRC operation mode, attribute, initial seed and write data length. \n
|
||||||
|
* After that, user can start to perform CRC calculate by calling CRC_WRITE_DATA macro or CRC_DAT register directly.
|
||||||
|
*/
|
||||||
|
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
|
||||||
|
{
|
||||||
|
CRC->SEED = u32Seed;
|
||||||
|
CRC->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
|
||||||
|
|
||||||
|
/* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
|
||||||
|
CRC->CTL |= CRC_CTL_CHKSINIT_Msk;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief CRC Open API for Non-Secure
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void CRC_Open_NS(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen)
|
||||||
|
{
|
||||||
|
CRC_NS->SEED = u32Seed;
|
||||||
|
CRC_NS->CTL = u32Mode | u32Attribute | u32DataLen | CRC_CTL_CRCEN_Msk;
|
||||||
|
|
||||||
|
/* Setting CRCRST bit will reload the initial seed value(CRC_SEED register) to CRC controller */
|
||||||
|
CRC_NS->CTL |= CRC_CTL_CHKSINIT_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get CRC Checksum
|
||||||
|
*
|
||||||
|
* @param[in] None
|
||||||
|
*
|
||||||
|
* @return Checksum Result
|
||||||
|
*
|
||||||
|
* @details This macro gets the CRC checksum result by current CRC polynomial mode.
|
||||||
|
*/
|
||||||
|
uint32_t CRC_GetChecksum(void)
|
||||||
|
{
|
||||||
|
switch(CRC->CTL & CRC_CTL_CRCMODE_Msk)
|
||||||
|
{
|
||||||
|
case CRC_CCITT:
|
||||||
|
case CRC_16:
|
||||||
|
return (CRC->CHECKSUM & 0xFFFF);
|
||||||
|
|
||||||
|
case CRC_32:
|
||||||
|
return (CRC->CHECKSUM);
|
||||||
|
|
||||||
|
case CRC_8:
|
||||||
|
return (CRC->CHECKSUM & 0xFF);
|
||||||
|
|
||||||
|
default:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief Get CRC Checksum API for Non-Secure
|
||||||
|
*/
|
||||||
|
uint32_t CRC_GetChecksum_NS(void)
|
||||||
|
{
|
||||||
|
switch(CRC_NS->CTL & CRC_CTL_CRCMODE_Msk)
|
||||||
|
{
|
||||||
|
case CRC_CCITT:
|
||||||
|
case CRC_16:
|
||||||
|
return (CRC_NS->CHECKSUM & 0xFFFF);
|
||||||
|
|
||||||
|
case CRC_32:
|
||||||
|
return (CRC_NS->CHECKSUM);
|
||||||
|
|
||||||
|
case CRC_8:
|
||||||
|
return (CRC_NS->CHECKSUM & 0xFF);
|
||||||
|
|
||||||
|
default:
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,125 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file crc.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Cyclic Redundancy Check(CRC) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __CRC_H__
|
||||||
|
#define __CRC_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_Driver CRC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRC_EXPORTED_CONSTANTS CRC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CRC Polynomial Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CRC_CCITT 0x00000000UL /*!<CRC Polynomial Mode - CCITT */
|
||||||
|
#define CRC_8 0x40000000UL /*!<CRC Polynomial Mode - CRC8 */
|
||||||
|
#define CRC_16 0x80000000UL /*!<CRC Polynomial Mode - CRC16 */
|
||||||
|
#define CRC_32 0xC0000000UL /*!<CRC Polynomial Mode - CRC32 */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Checksum, Write data Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CRC_CHECKSUM_COM 0x08000000UL /*!<CRC Checksum Complement */
|
||||||
|
#define CRC_CHECKSUM_RVS 0x02000000UL /*!<CRC Checksum Reverse */
|
||||||
|
#define CRC_WDATA_COM 0x04000000UL /*!<CRC Write Data Complement */
|
||||||
|
#define CRC_WDATA_RVS 0x01000000UL /*!<CRC Write Data Reverse */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* CPU Write Data Length Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define CRC_CPU_WDATA_8 0x00000000UL /*!<CRC CPU Write Data length is 8-bit */
|
||||||
|
#define CRC_CPU_WDATA_16 0x10000000UL /*!<CRC CPU Write Data length is 16-bit */
|
||||||
|
#define CRC_CPU_WDATA_32 0x20000000UL /*!<CRC CPU Write Data length is 32-bit */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set CRC Seed Value
|
||||||
|
*
|
||||||
|
* @param[in] u32Seed Seed value
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set CRC seed value.
|
||||||
|
*
|
||||||
|
* @note User must to perform CRC_RST(CRC_CTL[1] CRC Engine Reset) to reload the new seed value
|
||||||
|
* to CRC controller.
|
||||||
|
*/
|
||||||
|
#define CRC_SET_SEED(u32Seed) { CRC->SEED = (u32Seed); CRC->CTL |= CRC_CTL_CHKSINIT_Msk; }
|
||||||
|
/**
|
||||||
|
* @brief Set CRC Seed Value Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define CRC_SET_SEED_NS(u32Seed) { CRC_NS->SEED = (u32Seed); CRC_NS->CTL |= CRC_CTL_CHKSINIT_Msk; }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get CRC Seed Value
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return CRC seed value
|
||||||
|
*
|
||||||
|
* @details This macro gets the current CRC seed value.
|
||||||
|
*/
|
||||||
|
#define CRC_GET_SEED() (CRC->SEED)
|
||||||
|
/**
|
||||||
|
* @brief Get CRC Seed Value Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define CRC_GET_SEED_NS() (CRC_NS->SEED)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief CRC Write Data
|
||||||
|
*
|
||||||
|
* @param[in] u32Data Write data
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details User can write data directly to CRC Write Data Register(CRC_DAT) by this macro to perform CRC operation.
|
||||||
|
*/
|
||||||
|
#define CRC_WRITE_DATA(u32Data) (CRC->DAT = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief CRC Write Data Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define CRC_WRITE_DATA_NS(u32Data) (CRC_NS->DAT = (u32Data))
|
||||||
|
|
||||||
|
|
||||||
|
void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
|
||||||
|
void CRC_Open_NS(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_t u32DataLen);
|
||||||
|
uint32_t CRC_GetChecksum(void);
|
||||||
|
uint32_t CRC_GetChecksum_NS(void);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CRC_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,366 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file crypto.h
|
||||||
|
* @version V1.10
|
||||||
|
* @brief Cryptographic Accelerator driver header file
|
||||||
|
*
|
||||||
|
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __CRYPTO_H__
|
||||||
|
#define __CRYPTO_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup CRYPTO_Driver CRYPTO Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup CRYPTO_EXPORTED_CONSTANTS CRYPTO Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define PRNG_KEY_SIZE_64 0UL /*!< Select to generate 64-bit random key \hideinitializer */
|
||||||
|
#define PRNG_KEY_SIZE_128 1UL /*!< Select to generate 128-bit random key \hideinitializer */
|
||||||
|
#define PRNG_KEY_SIZE_192 2UL /*!< Select to generate 192-bit random key \hideinitializer */
|
||||||
|
#define PRNG_KEY_SIZE_256 3UL /*!< Select to generate 256-bit random key \hideinitializer */
|
||||||
|
|
||||||
|
#define PRNG_SEED_CONT 0UL /*!< PRNG using current seed \hideinitializer */
|
||||||
|
#define PRNG_SEED_RELOAD 1UL /*!< PRNG reload new seed \hideinitializer */
|
||||||
|
|
||||||
|
#define AES_KEY_SIZE_128 0UL /*!< AES select 128-bit key length \hideinitializer */
|
||||||
|
#define AES_KEY_SIZE_192 1UL /*!< AES select 192-bit key length \hideinitializer */
|
||||||
|
#define AES_KEY_SIZE_256 2UL /*!< AES select 256-bit key length \hideinitializer */
|
||||||
|
|
||||||
|
#define AES_MODE_ECB 0UL /*!< AES select ECB mode \hideinitializer */
|
||||||
|
#define AES_MODE_CBC 1UL /*!< AES select CBC mode \hideinitializer */
|
||||||
|
#define AES_MODE_CFB 2UL /*!< AES select CFB mode \hideinitializer */
|
||||||
|
#define AES_MODE_OFB 3UL /*!< AES select OFB mode \hideinitializer */
|
||||||
|
#define AES_MODE_CTR 4UL /*!< AES select CTR mode \hideinitializer */
|
||||||
|
#define AES_MODE_CBC_CS1 0x10UL /*!< AES select CBC CS1 mode \hideinitializer */
|
||||||
|
#define AES_MODE_CBC_CS2 0x11UL /*!< AES select CBC CS2 mode \hideinitializer */
|
||||||
|
#define AES_MODE_CBC_CS3 0x12UL /*!< AES select CBC CS3 mode \hideinitializer */
|
||||||
|
|
||||||
|
#define AES_NO_SWAP 0UL /*!< AES do not swap input and output data \hideinitializer */
|
||||||
|
#define AES_OUT_SWAP 1UL /*!< AES swap output data \hideinitializer */
|
||||||
|
#define AES_IN_SWAP 2UL /*!< AES swap input data \hideinitializer */
|
||||||
|
#define AES_IN_OUT_SWAP 3UL /*!< AES swap both input and output data \hideinitializer */
|
||||||
|
|
||||||
|
#define DES_MODE_ECB 0x000UL /*!< DES select ECB mode \hideinitializer */
|
||||||
|
#define DES_MODE_CBC 0x100UL /*!< DES select CBC mode \hideinitializer */
|
||||||
|
#define DES_MODE_CFB 0x200UL /*!< DES select CFB mode \hideinitializer */
|
||||||
|
#define DES_MODE_OFB 0x300UL /*!< DES select OFB mode \hideinitializer */
|
||||||
|
#define DES_MODE_CTR 0x400UL /*!< DES select CTR mode \hideinitializer */
|
||||||
|
#define TDES_MODE_ECB 0x004UL /*!< TDES select ECB mode \hideinitializer */
|
||||||
|
#define TDES_MODE_CBC 0x104UL /*!< TDES select CBC mode \hideinitializer */
|
||||||
|
#define TDES_MODE_CFB 0x204UL /*!< TDES select CFB mode \hideinitializer */
|
||||||
|
#define TDES_MODE_OFB 0x304UL /*!< TDES select OFB mode \hideinitializer */
|
||||||
|
#define TDES_MODE_CTR 0x404UL /*!< TDES select CTR mode \hideinitializer */
|
||||||
|
|
||||||
|
#define TDES_NO_SWAP 0UL /*!< TDES do not swap data \hideinitializer */
|
||||||
|
#define TDES_WHL_SWAP 1UL /*!< TDES swap high-low word \hideinitializer */
|
||||||
|
#define TDES_OUT_SWAP 2UL /*!< TDES swap output data \hideinitializer */
|
||||||
|
#define TDES_OUT_WHL_SWAP 3UL /*!< TDES swap output data and high-low word \hideinitializer */
|
||||||
|
#define TDES_IN_SWAP 4UL /*!< TDES swap input data \hideinitializer */
|
||||||
|
#define TDES_IN_WHL_SWAP 5UL /*!< TDES swap input data and high-low word \hideinitializer */
|
||||||
|
#define TDES_IN_OUT_SWAP 6UL /*!< TDES swap both input and output data \hideinitializer */
|
||||||
|
#define TDES_IN_OUT_WHL_SWAP 7UL /*!< TDES swap input, output and high-low word \hideinitializer */
|
||||||
|
|
||||||
|
#define SHA_MODE_SHA1 0UL /*!< SHA select SHA-1 160-bit \hideinitializer */
|
||||||
|
#define SHA_MODE_SHA224 5UL /*!< SHA select SHA-224 224-bit \hideinitializer */
|
||||||
|
#define SHA_MODE_SHA256 4UL /*!< SHA select SHA-256 256-bit \hideinitializer */
|
||||||
|
#define SHA_MODE_SHA384 7UL /*!< SHA select SHA-384 384-bit \hideinitializer */
|
||||||
|
#define SHA_MODE_SHA512 6UL /*!< SHA select SHA-512 512-bit \hideinitializer */
|
||||||
|
|
||||||
|
#define SHA_NO_SWAP 0UL /*!< SHA do not swap input and output data \hideinitializer */
|
||||||
|
#define SHA_OUT_SWAP 1UL /*!< SHA swap output data \hideinitializer */
|
||||||
|
#define SHA_IN_SWAP 2UL /*!< SHA swap input data \hideinitializer */
|
||||||
|
#define SHA_IN_OUT_SWAP 3UL /*!< SHA swap both input and output data \hideinitializer */
|
||||||
|
|
||||||
|
#define CRYPTO_DMA_FIRST 0x4UL /*!< Do first encrypt/decrypt in DMA cascade \hideinitializer */
|
||||||
|
#define CRYPTO_DMA_ONE_SHOT 0x5UL /*!< Do one shot encrypt/decrypt with DMA \hideinitializer */
|
||||||
|
#define CRYPTO_DMA_CONTINUE 0x6UL /*!< Do continuous encrypt/decrypt in DMA cascade \hideinitializer */
|
||||||
|
#define CRYPTO_DMA_LAST 0x7UL /*!< Do last encrypt/decrypt in DMA cascade \hideinitializer */
|
||||||
|
|
||||||
|
typedef enum
|
||||||
|
{
|
||||||
|
CURVE_P_192,
|
||||||
|
CURVE_P_224,
|
||||||
|
CURVE_P_256,
|
||||||
|
CURVE_P_384,
|
||||||
|
CURVE_P_521,
|
||||||
|
CURVE_K_163,
|
||||||
|
CURVE_K_233,
|
||||||
|
CURVE_K_283,
|
||||||
|
CURVE_K_409,
|
||||||
|
CURVE_K_571,
|
||||||
|
CURVE_B_163,
|
||||||
|
CURVE_B_233,
|
||||||
|
CURVE_B_283,
|
||||||
|
CURVE_B_409,
|
||||||
|
CURVE_B_571
|
||||||
|
}
|
||||||
|
E_ECC_CURVE;
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group M2351_CRYPTO_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup M2351_CRYPTO_EXPORTED_MACROS CRYPTO Exported Macros
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------------------------*/
|
||||||
|
/* Macros */
|
||||||
|
/*----------------------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables PRNG interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PRNG_ENABLE_INT(crpt) ((crpt)->INTEN |= CRPT_INTEN_PRNGIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables PRNG interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PRNG_DISABLE_INT(crpt) ((crpt)->INTEN &= ~CRPT_INTEN_PRNGIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro gets PRNG interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return PRNG interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PRNG_GET_INT_FLAG(crpt) ((crpt)->INTSTS & CRPT_INTSTS_PRNGIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clears PRNG interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PRNG_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = CRPT_INTSTS_PRNGIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables AES interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define AES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables AES interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define AES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_AESIEN_Msk|CRPT_INTEN_AESEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro gets AES interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return AES interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define AES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clears AES interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define AES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_AESIF_Msk|CRPT_INTSTS_AESEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables AES key protection.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define AES_ENABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL |= CRPT_AES_CTL_KEYPRT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables AES key protection.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define AES_DISABLE_KEY_PROTECT(crpt) ((crpt)->AES_CTL = ((crpt)->AES_CTL & ~CRPT_AES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_AES_CTL_KEYUNPRT_Pos)); \
|
||||||
|
((crpt)->AES_CTL &= ~CRPT_AES_CTL_KEYPRT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables TDES interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define TDES_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables TDES interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define TDES_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_TDESIEN_Msk|CRPT_INTEN_TDESEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro gets TDES interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return TDES interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define TDES_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clears TDES interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define TDES_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_TDESIF_Msk|CRPT_INTSTS_TDESEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables TDES key protection.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define TDES_ENABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL |= CRPT_TDES_CTL_KEYPRT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables TDES key protection.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define TDES_DISABLE_KEY_PROTECT(crpt) ((crpt)->TDES_CTL = ((crpt)->TDES_CTL & ~CRPT_TDES_CTL_KEYPRT_Msk) | (0x16UL<<CRPT_TDES_CTL_KEYUNPRT_Pos)); \
|
||||||
|
((crpt)->TDES_CTL &= ~CRPT_TDES_CTL_KEYPRT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables SHA interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SHA_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables SHA interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SHA_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_HMACIEN_Msk|CRPT_INTEN_HMACEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro gets SHA interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return SHA interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SHA_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clears SHA interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SHA_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_HMACIF_Msk|CRPT_INTSTS_HMACEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables ECC interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define ECC_ENABLE_INT(crpt) ((crpt)->INTEN |= (CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables ECC interrupt.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define ECC_DISABLE_INT(crpt) ((crpt)->INTEN &= ~(CRPT_INTEN_ECCIEN_Msk|CRPT_INTEN_ECCEIEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro gets ECC interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return ECC interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define ECC_GET_INT_FLAG(crpt) ((crpt)->INTSTS & (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clears ECC interrupt flag.
|
||||||
|
* @param crpt Specified cripto module
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define ECC_CLR_INT_FLAG(crpt) ((crpt)->INTSTS = (CRPT_INTSTS_ECCIF_Msk|CRPT_INTSTS_ECCEIF_Msk))
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group M2351_CRYPTO_EXPORTED_MACROS */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup M2351_CRYPTO_EXPORTED_FUNCTIONS CRYPTO Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Functions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
void PRNG_Open(CRPT_T *crpt, uint32_t u32KeySize, uint32_t u32SeedReload, uint32_t u32Seed);
|
||||||
|
void PRNG_Start(CRPT_T *crpt);
|
||||||
|
void PRNG_Read(CRPT_T *crpt, uint32_t u32RandKey[]);
|
||||||
|
void AES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, uint32_t u32OpMode, uint32_t u32KeySize, uint32_t u32SwapType);
|
||||||
|
void AES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);
|
||||||
|
void AES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[], uint32_t u32KeySize);
|
||||||
|
void AES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32IV[]);
|
||||||
|
void AES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
|
||||||
|
void TDES_Open(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32EncDec, int32_t Is3DES, int32_t Is3Key, uint32_t u32OpMode, uint32_t u32SwapType);
|
||||||
|
void TDES_Start(CRPT_T *crpt, int32_t u32Channel, uint32_t u32DMAMode);
|
||||||
|
void TDES_SetKey(CRPT_T *crpt, uint32_t u32Channel, uint32_t au32Keys[3][2]);
|
||||||
|
void TDES_SetInitVect(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32IVH, uint32_t u32IVL);
|
||||||
|
void TDES_SetDMATransfer(CRPT_T *crpt, uint32_t u32Channel, uint32_t u32SrcAddr, uint32_t u32DstAddr, uint32_t u32TransCnt);
|
||||||
|
void SHA_Open(CRPT_T *crpt, uint32_t u32OpMode, uint32_t u32SwapType, uint32_t hmac_key_len);
|
||||||
|
void SHA_Start(CRPT_T *crpt, uint32_t u32DMAMode);
|
||||||
|
void SHA_SetDMATransfer(CRPT_T *crpt, uint32_t u32SrcAddr, uint32_t u32TransCnt);
|
||||||
|
void SHA_Read(CRPT_T *crpt, uint32_t u32Digest[]);
|
||||||
|
void ECC_DriverISR(CRPT_T *crpt);
|
||||||
|
int32_t ECC_GeneratePublicKey(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *private_k, char public_k1[], char public_k2[]);
|
||||||
|
int32_t ECC_GenerateSignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *d, char *k, char *R, char *S);
|
||||||
|
int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message, char *public_k1, char *public_k2, char *R, char *S);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRYPTO_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group CRYPTO_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __CRYPTO_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,96 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file dac.c
|
||||||
|
* @version V1.00
|
||||||
|
* @brief M2351 series DAC driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Driver DAC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function make DAC module be ready to convert.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @param[in] u32TrgSrc Decides the trigger source. Valid values are:
|
||||||
|
* - \ref DAC_WRITE_DAT_TRIGGER :Write DAC_DAT trigger
|
||||||
|
* - \ref DAC_SOFTWARE_TRIGGER :Software trigger
|
||||||
|
* - \ref DAC_LOW_LEVEL_TRIGGER :STDAC pin low level trigger
|
||||||
|
* - \ref DAC_HIGH_LEVEL_TRIGGER :STDAC pin high level trigger
|
||||||
|
* - \ref DAC_FALLING_EDGE_TRIGGER :STDAC pin falling edge trigger
|
||||||
|
* - \ref DAC_RISING_EDGE_TRIGGER :STDAC pin rising edge trigger
|
||||||
|
* - \ref DAC_TIMER0_TRIGGER :Timer 0 trigger
|
||||||
|
* - \ref DAC_TIMER1_TRIGGER :Timer 1 trigger
|
||||||
|
* - \ref DAC_TIMER2_TRIGGER :Timer 2 trigger
|
||||||
|
* - \ref DAC_TIMER3_TRIGGER :Timer 3 trigger
|
||||||
|
* - \ref DAC_PWM0_TRIGGER :PWM0 trigger
|
||||||
|
* - \ref DAC_PWM1_TRIGGER :PWM1 trigger
|
||||||
|
* @return None
|
||||||
|
* @details The DAC conversion can be started by writing DAC_DAT, software trigger or hardware trigger.
|
||||||
|
* When TRGEN (DAC_CTL[4]) is 0, the data conversion is started by writing DAC_DAT register.
|
||||||
|
* When TRGEN (DAC_CTL[4]) is 1, the data conversion is started by SWTRG (DAC_SWTRG[0]) is set to 1,
|
||||||
|
* external STDAC pin, timer event, or PWM timer event.
|
||||||
|
*/
|
||||||
|
void DAC_Open(DAC_T *dac,
|
||||||
|
uint32_t u32Ch,
|
||||||
|
uint32_t u32TrgSrc)
|
||||||
|
{
|
||||||
|
/* It's necessary to enable DAC1 to use DAC0 for engineering sample. */
|
||||||
|
if((dac == DAC0)||(dac == DAC0_NS))
|
||||||
|
{
|
||||||
|
DAC1->CTL |= DAC_CTL_DACEN_Msk;
|
||||||
|
}
|
||||||
|
dac->CTL &= ~(DAC_CTL_ETRGSEL_Msk | DAC_CTL_TRGSEL_Msk | DAC_CTL_TRGEN_Msk);
|
||||||
|
|
||||||
|
dac->CTL |= (u32TrgSrc | DAC_CTL_DACEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable DAC analog power.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @return None
|
||||||
|
* @details Disable DAC analog power for saving power consumption.
|
||||||
|
*/
|
||||||
|
void DAC_Close(DAC_T *dac, uint32_t u32Ch)
|
||||||
|
{
|
||||||
|
dac->CTL &= (~DAC_CTL_DACEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set delay time for DAC to become stable.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Delay Decides the DAC conversion settling time, the range is from 0~(1023/PCLK1*1000000) micro seconds.
|
||||||
|
* @return Real DAC conversion settling time (micro second).
|
||||||
|
* @details For example, DAC controller clock speed is 48MHz and DAC conversion setting time is 1 us, SETTLET (DAC_TCTL[9:0]) value must be greater than 0x30.
|
||||||
|
* @note User needs to write appropriate value to meet DAC conversion settling time base on PCLK (APB clock) speed.
|
||||||
|
*/
|
||||||
|
int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
|
||||||
|
{
|
||||||
|
|
||||||
|
dac->TCTL = ((CLK_GetPCLK1Freq() * u32Delay / 1000000UL) & 0x3FFUL);
|
||||||
|
|
||||||
|
return ((dac->TCTL) * 1000000UL / CLK_GetPCLK1Freq());
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DAC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,254 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file dac.h
|
||||||
|
* @version V1.00
|
||||||
|
* @brief M2351 series DAC driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __DAC_H__
|
||||||
|
#define __DAC_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DAC_Driver DAC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup DAC_EXPORTED_CONSTANTS DAC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* DAC_CTL Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define DAC_CTL_LALIGN_RIGHT_ALIGN (0UL<<DAC_CTL_LALIGN_Pos) /*!< Right alignment. */
|
||||||
|
#define DAC_CTL_LALIGN_LEFT_ALIGN (1UL<<DAC_CTL_LALIGN_Pos) /*!< Left alignment */
|
||||||
|
|
||||||
|
#define DAC_WRITE_DAT_TRIGGER (0UL) /*!< Write DAC_DAT trigger */
|
||||||
|
#define DAC_SOFTWARE_TRIGGER (0UL|DAC_CTL_TRGEN_Msk) /*!< Software trigger */
|
||||||
|
#define DAC_LOW_LEVEL_TRIGGER ((0UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin low level trigger */
|
||||||
|
#define DAC_HIGH_LEVEL_TRIGGER ((1UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin high level trigger */
|
||||||
|
#define DAC_FALLING_EDGE_TRIGGER ((2UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin falling edge trigger */
|
||||||
|
#define DAC_RISING_EDGE_TRIGGER ((3UL<<DAC_CTL_ETRGSEL_Pos)|(1UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< STDAC pin rising edge trigger */
|
||||||
|
#define DAC_TIMER0_TRIGGER ((2UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 0 trigger */
|
||||||
|
#define DAC_TIMER1_TRIGGER ((3UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 1 trigger */
|
||||||
|
#define DAC_TIMER2_TRIGGER ((4UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 2 trigger */
|
||||||
|
#define DAC_TIMER3_TRIGGER ((5UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< Timer 3 trigger */
|
||||||
|
#define DAC_PWM0_TRIGGER ((6UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM0 trigger */
|
||||||
|
#define DAC_PWM1_TRIGGER ((7UL<<DAC_CTL_TRGSEL_Pos)|DAC_CTL_TRGEN_Msk) /*!< PWM1 trigger */
|
||||||
|
|
||||||
|
#define DAC_TRIGGER_MODE_DISABLE (0UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode disable */
|
||||||
|
#define DAC_TRIGGER_MODE_ENABLE (1UL<<DAC_CTL_TRGEN_Pos) /*!< Trigger mode enable */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DAC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup DAC_EXPORTED_FUNCTIONS DAC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* DAC Macro Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start the D/A conversion.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details User writes SWTRG bit (DAC_SWTRG[0]) to generate one shot pulse and it is cleared to 0 by hardware automatically.
|
||||||
|
*/
|
||||||
|
#define DAC_START_CONV(dac) ((dac)->SWTRG = DAC_SWTRG_SWTRG_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DAC data left-aligned.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details User has to load data into DAC_DAT[15:4] bits. DAC_DAT[31:16] and DAC_DAT[3:0] are ignored in DAC conversion.
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_LEFT_ALIGN(dac) ((dac)->CTL |= DAC_CTL_LALIGN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DAC data right-aligned.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details User has to load data into DAC_DAT[11:0] bits, DAC_DAT[31:12] are ignored in DAC conversion.
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_RIGHT_ALIGN(dac) ((dac)->CTL &= ~DAC_CTL_LALIGN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable output voltage buffer.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details The DAC integrates a voltage output buffer that can be used to reduce output impedance and
|
||||||
|
* drive external loads directly without having to add an external operational amplifier.
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_BYPASS_BUFFER(dac) ((dac)->CTL |= DAC_CTL_BYPASS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable output voltage buffer.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable output voltage buffer.
|
||||||
|
*/
|
||||||
|
#define DAC_DISABLE_BYPASS_BUFFER(dac) ((dac)->CTL &= ~DAC_CTL_BYPASS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the interrupt.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable DAC interrupt.
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_INT(dac, u32Ch) ((dac)->CTL |= DAC_CTL_DACIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the interrupt.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable DAC interrupt.
|
||||||
|
*/
|
||||||
|
#define DAC_DISABLE_INT(dac, u32Ch) ((dac)->CTL &= ~DAC_CTL_DACIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DMA under-run interrupt.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable DMA under-run interrupt.
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_DMAUDR_INT(dac) ((dac)->CTL |= DAC_CTL_DMAURIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable DMA under-run interrupt.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable DMA under-run interrupt.
|
||||||
|
*/
|
||||||
|
#define DAC_DISABLE_DMAUDR_INT(dac) ((dac)->CTL &= ~DAC_CTL_DMAURIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable PDMA mode.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details DAC DMA request is generated when a hardware trigger event occurs while DMAEN (DAC_CTL[2]) is set.
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_PDMA(dac) ((dac)->CTL |= DAC_CTL_DMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable PDMA mode.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable DMA mode.
|
||||||
|
*/
|
||||||
|
#define DAC_DISABLE_PDMA(dac) ((dac)->CTL &= ~DAC_CTL_DMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write data for conversion.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @param[in] u32Data Decides the data for conversion, valid range are between 0~0xFFF.
|
||||||
|
* @return None
|
||||||
|
* @details 12 bit left alignment: user has to load data into DAC_DAT[15:4] bits.
|
||||||
|
* 12 bit right alignment: user has to load data into DAC_DAT[11:0] bits.
|
||||||
|
*/
|
||||||
|
#define DAC_WRITE_DATA(dac, u32Ch, u32Data) ((dac)->DAT = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read DAC 12-bit holding data.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @return Return DAC 12-bit holding data.
|
||||||
|
* @details This macro is used to read DAC_DAT register.
|
||||||
|
*/
|
||||||
|
#define DAC_READ_DATA(dac, u32Ch) ((dac)->DAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the busy state of DAC.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @retval 0 Idle state.
|
||||||
|
* @retval 1 Busy state.
|
||||||
|
* @details This macro is used to read BUSY bit (DAC_STATUS[8]) to get busy state.
|
||||||
|
*/
|
||||||
|
#define DAC_IS_BUSY(dac, u32Ch) (((dac)->STATUS & DAC_STATUS_BUSY_Msk) >> DAC_STATUS_BUSY_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the interrupt flag.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @retval 0 DAC is in conversion state.
|
||||||
|
* @retval 1 DAC conversion finish.
|
||||||
|
* @details This macro is used to read FINISH bit (DAC_STATUS[0]) to get DAC conversion complete finish flag.
|
||||||
|
*/
|
||||||
|
#define DAC_GET_INT_FLAG(dac, u32Ch) ((dac)->STATUS & DAC_STATUS_FINISH_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the DMA under-run flag.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @retval 0 No DMA under-run error condition occurred.
|
||||||
|
* @retval 1 DMA under-run error condition occurred.
|
||||||
|
* @details This macro is used to read DMAUDR bit (DAC_STATUS[1]) to get DMA under-run state.
|
||||||
|
*/
|
||||||
|
#define DAC_GET_DMAUDR_FLAG(dac) (((dac)->STATUS & DAC_STATUS_DMAUDR_Msk) >> DAC_STATUS_DMAUDR_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clear the interrupt status bit.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @param[in] u32Ch Not used in M2351 Series DAC.
|
||||||
|
* @return None
|
||||||
|
* @details User writes FINISH bit (DAC_STATUS[0]) to clear DAC conversion complete finish flag.
|
||||||
|
*/
|
||||||
|
#define DAC_CLR_INT_FLAG(dac, u32Ch) ((dac)->STATUS = DAC_STATUS_FINISH_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clear the DMA under-run flag.
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* @details User writes DMAUDR bit (DAC_STATUS[1]) to clear DMA under-run flag.
|
||||||
|
*/
|
||||||
|
#define DAC_CLR_DMAUDR_FLAG(dac) ((dac)->STATUS = DAC_STATUS_DMAUDR_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DAC group mode
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define DAC_ENABLE_GROUP_MODE(dac) (DAC0->CTL |= DAC_CTL_GRPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable DAC group mode
|
||||||
|
* @param[in] dac The pointer of the specified DAC module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define DAC_DISABLE_GROUP_MODE(dac) (DAC0->CTL &= ~DAC_CTL_GRPEN_Msk)
|
||||||
|
|
||||||
|
void DAC_Open(DAC_T *dac, uint32_t u32Ch, uint32_t u32TrgSrc);
|
||||||
|
void DAC_Close(DAC_T *dac, uint32_t u32Ch);
|
||||||
|
int DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DAC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DAC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__DAC_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,110 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file dsrc.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Dedicated Short Range Communication Controller(DSRC) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DSRC_Driver DSRC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DSRC_EXPORTED_FUNCTIONS DSRC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Open DSRC Module
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mode Decides the DSRC operating mode. Valid values are:
|
||||||
|
* - \ref DSRC_MODE_FM0
|
||||||
|
* - \ref DSRC_MODE_MONCHESTER
|
||||||
|
* - \ref DSRC_MODE_SPI
|
||||||
|
* @param[in] u32crcEn Set 0 to disable CRC engine; set 1 to enable CRC engine
|
||||||
|
* @param[in] u32pdmaEn Set 0 to disable PDMA engine; set 1 to enable PDMA engine
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function make DSRC module be ready to transfer.
|
||||||
|
*/
|
||||||
|
void DSRC_Open(DSRC_T *dsrc, uint32_t u32Mode, uint32_t u32crcEn, uint32_t u32pdmaEn)
|
||||||
|
{
|
||||||
|
dsrc->CTL = (dsrc->CTL & ~DSRC_MODE_Msk) | u32Mode;
|
||||||
|
|
||||||
|
/* Enable DSRC */
|
||||||
|
dsrc->CTL |= DSRC_CTL_DSRCEN_Msk;
|
||||||
|
|
||||||
|
/* Enable TBP */
|
||||||
|
DSRC_ENABLE_TBP(dsrc);
|
||||||
|
|
||||||
|
if(u32crcEn == 1UL)
|
||||||
|
DSRC_ENABLE_CRC(dsrc); /* Enable CRC */
|
||||||
|
else
|
||||||
|
DSRC_DISABLE_CRC(dsrc); /* Disable CRC */
|
||||||
|
|
||||||
|
if(u32pdmaEn == 1UL)
|
||||||
|
{
|
||||||
|
/* Enable RX PDMA */
|
||||||
|
DSRC_ENABLE_RX_PDMA(dsrc);
|
||||||
|
/* Enable TX PDMA */
|
||||||
|
DSRC_ENABLE_TX_PDMA(dsrc);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Disable RX PDMA */
|
||||||
|
dsrc->CTL &= ~(DSRC_CTL_TRDMAEN_Msk);
|
||||||
|
/* Enable TX PDMA */
|
||||||
|
dsrc->CTL &= ~(DSRC_CTL_TTDMAEN_Msk);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Close DSRC Module
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable DSRC module.
|
||||||
|
*/
|
||||||
|
void DSRC_Close(DSRC_T *dsrc)
|
||||||
|
{
|
||||||
|
dsrc->CTL &= ~DSRC_CTL_DSRCEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Preamble
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mode Decides the premable size of DSRC module. Valid values are:
|
||||||
|
* - \ref DSRC_CTL_PREAMFMT_16, the premable pattern is u32Val[15:0]
|
||||||
|
* - \ref DSRC_CTL_PREAMFMT_32, the premable pattern is u32Val[31:0]
|
||||||
|
* @param[in] u32Val Preamble pattern value
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to decide the premable size and pattern of DSRC module.
|
||||||
|
* The valid premable pattern is selected by u32Mode setting.
|
||||||
|
*/
|
||||||
|
void DSRC_SetPreamble(DSRC_T *dsrc, uint32_t u32Mode, uint32_t u32Val)
|
||||||
|
{
|
||||||
|
dsrc->CTL = (dsrc->CTL & ~DSRC_CTL_PREAMFMT_Msk) | (u32Mode);
|
||||||
|
dsrc->PREAMBLE = u32Val;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DSRC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DSRC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,406 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file dsrc.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Dedicated Short Range Communication Controller(DSRC) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __DSRC_H__
|
||||||
|
#define __DSRC_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DSRC_Driver DSRC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup DSRC_EXPORTED_CONSTANTS DSRC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define DSRC_MODE_FM0 (DSRC_CTL_CODECEN_Msk) /*!< DSRC operates at FM0 mode */
|
||||||
|
#define DSRC_MODE_MONCHESTER (DSRC_CTL_CODECEN_Msk|DSRC_CTL_CODECFMT_Msk) /*!< DSRC operates at MONCHESTER mode */
|
||||||
|
#define DSRC_MODE_SPI (0) /*!< DSRC operates at SPI mode */
|
||||||
|
#define DSRC_MODE_Msk (DSRC_CTL_CODECEN_Msk|DSRC_CTL_CODECFMT_Msk) /*!< Mask setting of DSRC operates mode */
|
||||||
|
|
||||||
|
#define DSRC_CTL_WKPOL_RISING (0x0UL << DSRC_CTL_WKPOL_Pos) /*!< DSRC wakeup pin event at rising edge */
|
||||||
|
#define DSRC_CTL_WKPOL_FALLING (0x1UL << DSRC_CTL_WKPOL_Pos) /*!< DSRC wakeup pin event at falling edge */
|
||||||
|
#define DSRC_CTL_WKPOL_BOTH (0x2UL << DSRC_CTL_WKPOL_Pos) /*!< DSRC wakeup pin event at rising or falling edge */
|
||||||
|
|
||||||
|
#define DSRC_CTL_PREAMFMT_16 (0x0UL << DSRC_CTL_PREAMFMT_Pos) /*!< DSRC preamble pattern size is 16-bit */
|
||||||
|
#define DSRC_CTL_PREAMFMT_32 (0x1UL << DSRC_CTL_PREAMFMT_Pos) /*!< DSRC preamble pattern size is 32-bit */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DSRC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup DSRC_EXPORTED_FUNCTIONS DSRC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DSRC Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mask Interrupt mask to be enabled. A combination of
|
||||||
|
* - \ref DSRC_INTEN_CRCCORIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_CRCERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_STRFRMIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_STPFRMIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_RXDATERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_BRATERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_TTBPDIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_RTBPDIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_TXDONEIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T2TOIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T3TOIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T4TOIE_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_ENABLE_INT(dsrc, u32Mask) ((dsrc)->INTEN |= (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable DSRC Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
|
||||||
|
* - \ref DSRC_INTEN_CRCCORIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_CRCERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_STRFRMIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_STPFRMIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_RXDATERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_BRATERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_TTBPDIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_RTBPDIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_TXDONEIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T2TOIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T3TOIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T4TOIE_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_DISABLE_INT(dsrc, u32Mask) ((dsrc)->INTEN &= ~(u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Specify Interrupt Enabled Status
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mask Interrupt mask selected. A combination of
|
||||||
|
* - \ref DSRC_INTEN_CRCCORIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_CRCERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_STRFRMIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_STPFRMIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_RXDATERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_BRATERRIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_TTBPDIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_RTBPDIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_TXDONEIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T2TOIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T3TOIE_Msk
|
||||||
|
* - \ref DSRC_INTEN_T4TOIE_Msk
|
||||||
|
|
||||||
|
* @retval 0 Specified interrupts disabled
|
||||||
|
* @retval 1 Specified interrupts enabled
|
||||||
|
*/
|
||||||
|
#define DSRC_GET_INTEN_STS(dsrc, u32Mask) (((dsrc)->INTEN & (u32Mask))== (u32Mask) ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Specified Interrupt Flag Status
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mask Interrupt flags mask to be check. A combination of
|
||||||
|
* - \ref DSRC_STATUS_CRCCOR_Msk
|
||||||
|
* - \ref DSRC_STATUS_CRCERR_Msk
|
||||||
|
* - \ref DSRC_STATUS_STRFRM_Msk
|
||||||
|
* - \ref DSRC_STATUS_STPFRM_Msk
|
||||||
|
* - \ref DSRC_STATUS_RXDATERR_Msk
|
||||||
|
* - \ref DSRC_STATUS_BRATERR_Msk
|
||||||
|
* - \ref DSRC_STATUS_TTBPDONE_Msk
|
||||||
|
* - \ref DSRC_STATUS_RTBPDONE_Msk
|
||||||
|
* - \ref DSRC_STATUS_TXFINISH_Msk
|
||||||
|
* - \ref DSRC_STATUS_TTBPFULL_Msk
|
||||||
|
* - \ref DSRC_STATUS_T2TO_Msk
|
||||||
|
* - \ref DSRC_STATUS_T3TO_Msk
|
||||||
|
* - \ref DSRC_STATUS_T4TO_Msk
|
||||||
|
* - \ref DSRC_STATUS_CRC0_OK_Msk
|
||||||
|
* - \ref DSRC_STATUS_CRC1_OK_Msk
|
||||||
|
* - \ref DSRC_STATUS_EPWKF_Msk
|
||||||
|
*
|
||||||
|
* @retval 0 No specified interrupts
|
||||||
|
* @retval 1 Specified interrupts occurred
|
||||||
|
*/
|
||||||
|
#define DSRC_GET_INT_FLAG(dsrc, u32Mask) (((dsrc)->STATUS & (u32Mask))== (u32Mask) ? 1:0)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear DSRC related interrupts specified by u32Mask parameter.
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Mask Interrupt flags mask to be cleared. A combination of
|
||||||
|
* - \ref DSRC_STATUS_CRCCOR_Msk
|
||||||
|
* - \ref DSRC_STATUS_CRCERR_Msk
|
||||||
|
* - \ref DSRC_STATUS_STRFRM_Msk
|
||||||
|
* - \ref DSRC_STATUS_STPFRM_Msk
|
||||||
|
* - \ref DSRC_STATUS_RXDATERR_Msk
|
||||||
|
* - \ref DSRC_STATUS_BRATERR_Msk
|
||||||
|
* - \ref DSRC_STATUS_TTBPDONE_Msk
|
||||||
|
* - \ref DSRC_STATUS_RTBPDONE_Msk
|
||||||
|
* - \ref DSRC_STATUS_TXFINISH_Msk
|
||||||
|
* - \ref DSRC_STATUS_TTBPFULL_Msk
|
||||||
|
* - \ref DSRC_STATUS_T2TO_Msk
|
||||||
|
* - \ref DSRC_STATUS_T3TO_Msk
|
||||||
|
* - \ref DSRC_STATUS_T4TO_Msk
|
||||||
|
* - \ref DSRC_STATUS_CRC0_OK_Msk
|
||||||
|
* - \ref DSRC_STATUS_CRC1_OK_Msk
|
||||||
|
* - \ref DSRC_STATUS_EPWKF_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_CLR_INT_FLAG(dsrc, u32Mask) ((dsrc)->STATUS = (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable TBP Receive DMA
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_ENABLE_RX_PDMA(dsrc) ((dsrc)->CTL |= DSRC_CTL_TRDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable TBP Transmit DMA
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_ENABLE_TX_PDMA(dsrc) ((dsrc)->CTL |= DSRC_CTL_TTDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Force DSRC in RX state
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_FORCE_RX(dsrc) ((dsrc)->CTL |= DSRC_CTL_FORCERX_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Force DSRC in TX state
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_FORCE_TX(dsrc) ((dsrc)->CTL |= DSRC_CTL_FORCETX_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set DSRC RX On
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @note This function can be work well only if SWRXEN (DSRC_CTL[1] Software Control RX_ON Enable Bit) is enabled.
|
||||||
|
*/
|
||||||
|
#define DSRC_RXON(dsrc) ((dsrc)->CTL |= DSRC_CTL_RXON_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set DSRC RX Off
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_RXOFF(dsrc) ((dsrc)->CTL &= ~(DSRC_CTL_RXON_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Wakeup Pin Trigger type
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] type Decides which trigger type for DSRC wakeup pin, valid parameters are:
|
||||||
|
* - \ref DSRC_CTL_WKPOL_RISING
|
||||||
|
* - \ref DSRC_CTL_WKPOL_FALLING
|
||||||
|
* - \ref DSRC_CTL_WKPOL_BOTH
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_WKPOL_TRIGGER(dsrc, type) ((dsrc)->CTL = ((dsrc)->CTL & ~(DSRC_CTL_WKPOL_Msk)) | (type))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set DSRC Timer2 Timeout Period
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] prescale Prescale counter, it is should be 0~255
|
||||||
|
* @param[in] compared Timer compared value, it is should be 2~0xFFFFFF
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_SET_TMR2_TIMEOUT(dsrc, prescale, compared) ((dsrc)->TMR2 = ((prescale)<<DSRC_TMR2_PSC_Pos)|(compared))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set DSRC Timer3 Timeout Period
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] prescale Prescale counter, it is should be 0~255
|
||||||
|
* @param[in] compared Timer compared value, it is should be 2~0xFFFFFF
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_SET_TMR3_TIMEOUT(dsrc, prescale, compared) ((dsrc)->TMR3 = ((prescale)<<DSRC_TMR3_PSC_Pos)|(compared))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set DSRC Timer4 Timeout Period
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] prescale Prescale counter, it is should be 0~255
|
||||||
|
* @param[in] compared Timer compared value, it is should be 2~0xFFFFFF
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_SET_TMR4_TIMEOUT(dsrc, prescale, compared) ((dsrc)->TMR4 = ((prescale)<<DSRC_TMR4_PSC_Pos)|(compared))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set CRC Format
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32CRCMSB Decides CRC generation start data format. 0 means LSB; 1 means MSB
|
||||||
|
* @param[in] u32CRCREV Decides CRC checksum reverse. 0 to disable; 1 to enable
|
||||||
|
* @param[in] u32CRCFMT Decides 1'complement for CRC checksum. 0 to disable; 1 to enable
|
||||||
|
* @param[in] u32CRCBSWAP Decides received CRC value byte swap. 0 to disable; 1 to enable
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_SET_CRC_FMT(dsrc, u32CRCMSB, u32CRCREV, u32CRCFMT, u32CRCBSWAP) \
|
||||||
|
( (dsrc)->CTL = ((dsrc)->CTL & ~(DSRC_CTL_CRCMSB_Msk|DSRC_CTL_CHKSREV_Msk|DSRC_CTL_CHKSFMT_Msk|DSRC_CTL_CRCBSWAP_Msk)) | \
|
||||||
|
( ((u32CRCMSB)<<DSRC_CTL_CRCMSB_Pos) | ((u32CRCREV)<<DSRC_CTL_CHKSREV_Pos) | \
|
||||||
|
((u32CRCFMT)<<DSRC_CTL_CHKSFMT_Pos) | ((u32CRCBSWAP)<<DSRC_CTL_CRCBSWAP_Pos)) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Bit Rate Accuracy Range
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Val Bit rate accuracy range, valid value is between 0x0 ~ 0x4.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @note This function is only available for FM0 CODEC, and bit rate accuracy range are shown in following table:
|
||||||
|
* -
|
||||||
|
* | | | DSRC clock 4MHz | | | DSRC clock 12MHz|
|
||||||
|
* | :--|:------ |:--------------- | :-- |:------ |:--------------- |
|
||||||
|
* | 0 | >75% | 204 ~ 341 kH | 0 | >75% | 204 ~ 341 kHz |
|
||||||
|
* | 1 | >75% | 204 ~ 341 kH | 1 | >80% | 213 ~ 320 kHz |
|
||||||
|
* | 2 | >87.5% | 227 ~ 292 kHz | 2 | >84% | 220 ~ 304 kHz |
|
||||||
|
* | 3 | >87.5% | 227 ~ 292 kHz | 3 | >87.5% | 227 ~ 292 kHz |
|
||||||
|
* | 4 | X | Reserved | 4 | >71% | 198 ~ 355 kHz |
|
||||||
|
*/
|
||||||
|
#define DSRC_BITRATE_ACC_CTL(dsrc, u32Val) ((dsrc)->CTL = ((dsrc)->CTL & ~(DSRC_CTL_BRATEACC_Msk)) | ((u32Val)<<DSRC_CTL_BRATEACC_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set FM0 CODEC Deglitch
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Val Select FM0 CODEC deglitch setting, valid value is between 0x0 ~ 0x5 as
|
||||||
|
* 0 = disable to the codec deglitch selection.
|
||||||
|
* 1 = Filter the glitches that the width is 0.25us or less.
|
||||||
|
* 2 = Filter the glitches that the width is 0.50us or less.
|
||||||
|
* 3 = Filter the glitches that the width is 0.75us or less.
|
||||||
|
* 4 = Filter the glitches that the width is 1.00us or less.
|
||||||
|
* 5 = Filter the glitches that the width is 1.25us or less.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_SET_DEGLITCH(dsrc, u32Val) ((dsrc)->CTL2 = ((dsrc)->CTL2 & ~DSRC_CTL2_CODECDEGSEL_Msk) | ((u32Val)<<DSRC_CTL2_CODECDEGSEL_Pos))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DRSC CRC
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_ENABLE_CRC(dsrc) ((dsrc)->CTL |= DSRC_CTL_CRCEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable DRSC CRC
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_DISABLE_CRC(dsrc) ((dsrc)->CTL &= ~DSRC_CTL_CRCEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable DSRC TPB
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_ENABLE_TBP(dsrc) ((dsrc)->CTL |= DSRC_CTL_TBPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable DSRC TPB
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_DISABLE_TBP(dsrc) ((dsrc)->CTL &= ~DSRC_CTL_TBPEN_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Software Control RX_ON
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_ENABLE_SWRX(dsrc) ((dsrc)->CTL |= DSRC_CTL_SWRXEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Software Control RX_ON
|
||||||
|
*
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_DISABLE_SWRX(dsrc) ((dsrc)->CTL &= ~DSRC_CTL_SWRXEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set CRC Seed Mode.
|
||||||
|
* @param[in] dsrc The pointer of the DSRC module
|
||||||
|
* @param[in] u32Val Select transmit CRC seed initial value. 0 is : Seed0 1: Seed1
|
||||||
|
* 0 is CRCSEED0 (DSRC_CRCSEED[15:0]), 1 CRCSEED0 (DSRC_CRCSEED[31:15]).
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
#define DSRC_SET_CRC_SEED(dsrc, u32Val) ((dsrc)->CTL = ((dsrc)->CTL & ~DSRC_CTL_SEEDM_Msk)| ((u32Val)<<DSRC_CTL_SEEDM_Pos))
|
||||||
|
|
||||||
|
|
||||||
|
void DSRC_Open(DSRC_T *dsrc, uint32_t u32Mode, uint32_t u32crcEn, uint32_t u32pdmaEn);
|
||||||
|
void DSRC_SetPreamble(DSRC_T *dsrc, uint32_t u32Mode, uint32_t u32Val);
|
||||||
|
void DSRC_Close(DSRC_T *dsrc);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DSRC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group DSRC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __DSRC_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,145 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file eadc.c
|
||||||
|
* @version V2.00
|
||||||
|
* @brief M2351 series EADC driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EADC_Driver EADC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function make EADC_module be ready to convert.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32InputMode Decides the input mode.
|
||||||
|
* - \ref EADC_CTL_DIFFEN_SINGLE_END :Single end input mode.
|
||||||
|
* - \ref EADC_CTL_DIFFEN_DIFFERENTIAL :Differential input type.
|
||||||
|
* @return None
|
||||||
|
* @details This function is used to set analog input mode and enable A/D Converter.
|
||||||
|
* Before starting A/D conversion function, ADCEN bit (EADC_CTL[0]) should be set to 1.
|
||||||
|
* @note
|
||||||
|
*/
|
||||||
|
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode)
|
||||||
|
{
|
||||||
|
eadc->CTL &= (~(EADC_CTL_DIFFEN_Msk | 0x70000UL));
|
||||||
|
|
||||||
|
eadc->CTL |= (u32InputMode | EADC_CTL_ADCEN_Msk);
|
||||||
|
|
||||||
|
while(!(eadc->PWRM & EADC_PWRM_PWUPRDY_Msk));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable EADC_module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module..
|
||||||
|
* @return None
|
||||||
|
* @details Clear ADCEN bit (EADC_CTL[0]) to disable A/D converter analog circuit power consumption.
|
||||||
|
*/
|
||||||
|
void EADC_Close(EADC_T *eadc)
|
||||||
|
{
|
||||||
|
eadc->CTL &= ~EADC_CTL_ADCEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the sample control logic module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
|
||||||
|
* @param[in] u32TriggerSrc Decides the trigger source. Valid values are:
|
||||||
|
* - \ref EADC_SOFTWARE_TRIGGER : Disable trigger
|
||||||
|
* - \ref EADC_FALLING_EDGE_TRIGGER : STADC pin falling edge trigger
|
||||||
|
* - \ref EADC_RISING_EDGE_TRIGGER : STADC pin rising edge trigger
|
||||||
|
* - \ref EADC_FALLING_RISING_EDGE_TRIGGER : STADC pin both falling and rising edge trigger
|
||||||
|
* - \ref EADC_ADINT0_TRIGGER : ADC ADINT0 interrupt EOC pulse trigger
|
||||||
|
* - \ref EADC_ADINT1_TRIGGER : ADC ADINT1 interrupt EOC pulse trigger
|
||||||
|
* - \ref EADC_TIMER0_TRIGGER : Timer0 overflow pulse trigger
|
||||||
|
* - \ref EADC_TIMER1_TRIGGER : Timer1 overflow pulse trigger
|
||||||
|
* - \ref EADC_TIMER2_TRIGGER : Timer2 overflow pulse trigger
|
||||||
|
* - \ref EADC_TIMER3_TRIGGER : Timer3 overflow pulse trigger
|
||||||
|
* - \ref EADC_PWM0TG0_TRIGGER : PWM0TG0 trigger
|
||||||
|
* - \ref EADC_PWM0TG1_TRIGGER : PWM0TG1 trigger
|
||||||
|
* - \ref EADC_PWM0TG2_TRIGGER : PWM0TG2 trigger
|
||||||
|
* - \ref EADC_PWM0TG3_TRIGGER : PWM0TG3 trigger
|
||||||
|
* - \ref EADC_PWM0TG4_TRIGGER : PWM0TG4 trigger
|
||||||
|
* - \ref EADC_PWM0TG5_TRIGGER : PWM0TG5 trigger
|
||||||
|
* - \ref EADC_PWM1TG0_TRIGGER : PWM1TG0 trigger
|
||||||
|
* - \ref EADC_PWM1TG1_TRIGGER : PWM1TG1 trigger
|
||||||
|
* - \ref EADC_PWM1TG2_TRIGGER : PWM1TG2 trigger
|
||||||
|
* - \ref EADC_PWM1TG3_TRIGGER : PWM1TG3 trigger
|
||||||
|
* - \ref EADC_PWM1TG4_TRIGGER : PWM1TG4 trigger
|
||||||
|
* - \ref EADC_PWM1TG5_TRIGGER : PWM1TG5 trigger
|
||||||
|
* - \ref EADC_BPWM0TG_TRIGGER : BPWM0TG trigger
|
||||||
|
* - \ref EADC_BPWM1TG_TRIGGER : BPWM1TG trigger
|
||||||
|
* @param[in] u32Channel Specifies the sample module channel, valid value are from 0 to 15.
|
||||||
|
* @return None
|
||||||
|
* @details Each of ADC control logic modules 0~15 which is configurable for ADC converter channel EADC_CH0~15 and trigger source.
|
||||||
|
* sample module 16~18 is fixed for ADC channel 16, 17, 18 input sources as band-gap voltage, temperature sensor, and battery power (VBAT).
|
||||||
|
*/
|
||||||
|
void EADC_ConfigSampleModule(EADC_T *eadc, \
|
||||||
|
uint32_t u32ModuleNum, \
|
||||||
|
uint32_t u32TriggerSrc, \
|
||||||
|
uint32_t u32Channel)
|
||||||
|
{
|
||||||
|
eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | EADC_SCTL_TRGSEL_Msk | EADC_SCTL_CHSEL_Msk);
|
||||||
|
eadc->SCTL[u32ModuleNum] |= (u32TriggerSrc | u32Channel);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set trigger delay time.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
|
||||||
|
* @param[in] u32TriggerDelayTime Decides the trigger delay time, valid range are between 0~0xFF.
|
||||||
|
* @param[in] u32DelayClockDivider Decides the trigger delay clock divider. Valid values are:
|
||||||
|
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_1 : Trigger delay clock frequency is ADC_CLK/1
|
||||||
|
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_2 : Trigger delay clock frequency is ADC_CLK/2
|
||||||
|
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_4 : Trigger delay clock frequency is ADC_CLK/4
|
||||||
|
* - \ref EADC_SCTL_TRGDLYDIV_DIVIDER_16 : Trigger delay clock frequency is ADC_CLK/16
|
||||||
|
* @return None
|
||||||
|
* @details User can configure the trigger delay time by setting TRGDLYCNT (EADC_SCTLn[15:8], n=0~15) and TRGDLYDIV (EADC_SCTLn[7:6], n=0~15).
|
||||||
|
* Trigger delay time = (u32TriggerDelayTime) x Trigger delay clock period.
|
||||||
|
*/
|
||||||
|
void EADC_SetTriggerDelayTime(EADC_T *eadc, \
|
||||||
|
uint32_t u32ModuleNum, \
|
||||||
|
uint32_t u32TriggerDelayTime, \
|
||||||
|
uint32_t u32DelayClockDivider)
|
||||||
|
{
|
||||||
|
eadc->SCTL[u32ModuleNum] &= ~(EADC_SCTL_TRGDLYDIV_Msk | EADC_SCTL_TRGDLYCNT_Msk);
|
||||||
|
eadc->SCTL[u32ModuleNum] |= ((u32TriggerDelayTime << EADC_SCTL_TRGDLYCNT_Pos) | u32DelayClockDivider);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set ADC extend sample time.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
|
||||||
|
* @param[in] u32ExtendSampleTime Decides the extend sampling time, the range is from 0~255 ADC clock. Valid value are from 0 to 0xFF.
|
||||||
|
* @return None
|
||||||
|
* @details When A/D converting at high conversion rate, the sampling time of analog input voltage may not enough if input channel loading is heavy,
|
||||||
|
* user can extend A/D sampling time after trigger source is coming to get enough sampling time.
|
||||||
|
*/
|
||||||
|
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime)
|
||||||
|
{
|
||||||
|
eadc->SCTL[u32ModuleNum] &= ~EADC_SCTL_EXTSMPT_Msk;
|
||||||
|
|
||||||
|
eadc->SCTL[u32ModuleNum] |= (u32ExtendSampleTime << EADC_SCTL_EXTSMPT_Pos);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EADC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,560 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file eadc.h
|
||||||
|
* @version V0.10
|
||||||
|
* @brief M2351 series EADC driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __EADC_H__
|
||||||
|
#define __EADC_H__
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Include related headers */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EADC_Driver EADC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* EADC_CTL Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */
|
||||||
|
#define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */
|
||||||
|
|
||||||
|
#define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */
|
||||||
|
#define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* EADC_SCTL Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */
|
||||||
|
#define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */
|
||||||
|
#define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */
|
||||||
|
|
||||||
|
#define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */
|
||||||
|
#define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */
|
||||||
|
#define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */
|
||||||
|
#define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */
|
||||||
|
#define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */
|
||||||
|
#define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */
|
||||||
|
#define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */
|
||||||
|
#define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */
|
||||||
|
#define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */
|
||||||
|
#define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */
|
||||||
|
#define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG0 trigger */
|
||||||
|
#define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG1 trigger */
|
||||||
|
#define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG2 trigger */
|
||||||
|
#define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG3 trigger */
|
||||||
|
#define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG4 trigger */
|
||||||
|
#define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG5 trigger */
|
||||||
|
#define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG0 trigger */
|
||||||
|
#define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG1 trigger */
|
||||||
|
#define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG2 trigger */
|
||||||
|
#define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG3 trigger */
|
||||||
|
#define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG4 trigger */
|
||||||
|
#define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG5 trigger */
|
||||||
|
#define EADC_BPWM0TG_TRIGGER (0x14UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM0TG trigger */
|
||||||
|
#define EADC_BPWM1TG_TRIGGER (0x15UL<<EADC_SCTL_TRGSEL_Pos) /*!< BPWM1TG trigger */
|
||||||
|
|
||||||
|
#define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */
|
||||||
|
#define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */
|
||||||
|
#define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */
|
||||||
|
#define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* EADC_CMP Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */
|
||||||
|
#define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
|
||||||
|
#define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */
|
||||||
|
#define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */
|
||||||
|
#define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */
|
||||||
|
#define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* EADC Macro Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief A/D Converter Control Circuits Reset.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
|
||||||
|
*/
|
||||||
|
#define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADCRST_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable PDMA transfer.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
|
||||||
|
* user can enable this bit to generate a PDMA data transfer request.
|
||||||
|
* @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable PDMA transfer.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable PDMA transfer.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable double buffer mode.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
|
||||||
|
* @return None
|
||||||
|
* @details The ADC controller supports a double buffer mode in sample module 0~3.
|
||||||
|
* If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable double buffer mode.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
|
||||||
|
* @return None
|
||||||
|
* @details Sample has one sample result register.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set ADIFn at A/D end of conversion.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
|
||||||
|
* @return None
|
||||||
|
* @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set ADIFn at A/D start of conversion.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
|
||||||
|
* @return None
|
||||||
|
* @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the interrupt.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
|
||||||
|
* This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
|
||||||
|
* @return None
|
||||||
|
* @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
|
||||||
|
* If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the interrupt.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
|
||||||
|
* This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
|
||||||
|
* @return None
|
||||||
|
* @details Specific sample module A/D ADINT0 interrupt function Disabled.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the sample module interrupt.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
|
||||||
|
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
|
||||||
|
* This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
|
||||||
|
* @return None
|
||||||
|
* @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the sample module interrupt.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
|
||||||
|
* @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
|
||||||
|
* This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
|
||||||
|
* @return None
|
||||||
|
* @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the input mode output format.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32Format Decides the output format. Valid values are:
|
||||||
|
* - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
|
||||||
|
* - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
|
||||||
|
* @return None
|
||||||
|
* @details The macro is used to set A/D input mode output format.
|
||||||
|
*/
|
||||||
|
#define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start the A/D conversion.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
|
||||||
|
* This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
|
||||||
|
* Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
|
||||||
|
* @return None
|
||||||
|
* @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
|
||||||
|
*/
|
||||||
|
#define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Cancel the conversion for sample module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
|
||||||
|
* This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
|
||||||
|
* Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
|
||||||
|
* @return None
|
||||||
|
* @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
|
||||||
|
*/
|
||||||
|
#define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the conversion pending flag.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return Return the conversion pending sample module.
|
||||||
|
* @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
|
||||||
|
* the STPFn (n=0~18) bit is automatically cleared to 0.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the conversion data of the user-specified sample module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
|
||||||
|
* @return Return the conversion data of the user-specified sample module.
|
||||||
|
* @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the data overrun flag of the user-specified sample module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
|
||||||
|
* @return Return the data overrun flag of the user-specified sample module.
|
||||||
|
* @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the data valid flag of the user-specified sample module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
|
||||||
|
* @return Return the data valid flag of the user-specified sample module.
|
||||||
|
* @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the double data of the user-specified sample module.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
|
||||||
|
* @return Return the double data of the user-specified sample module.
|
||||||
|
* @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the user-specified interrupt flags.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
|
||||||
|
* Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
|
||||||
|
* Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
|
||||||
|
* @return Return the user-specified interrupt flags.
|
||||||
|
* @details This macro is used to get the user-specified interrupt flags.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the user-specified sample module overrun flags.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
|
||||||
|
* @return Return the user-specified sample module overrun flags.
|
||||||
|
* @details This macro is used to get the user-specified sample module overrun flags.
|
||||||
|
*/
|
||||||
|
#define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the selected interrupt status bits.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
|
||||||
|
* Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
|
||||||
|
* Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to clear clear the selected interrupt status bits.
|
||||||
|
*/
|
||||||
|
#define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the selected sample module overrun status bits.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
|
||||||
|
* Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to clear the selected sample module overrun status bits.
|
||||||
|
*/
|
||||||
|
#define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check all sample module A/D result data register overrun flags.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @retval 0 None of sample module data register overrun flag is set to 1.
|
||||||
|
* @retval 1 Any one of sample module data register overrun flag is set to 1.
|
||||||
|
* @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
|
||||||
|
*/
|
||||||
|
#define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check all sample module A/D result data register valid flags.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @retval 0 None of sample module data register valid flag is set to 1.
|
||||||
|
* @retval 1 Any one of sample module data register valid flag is set to 1.
|
||||||
|
* @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
|
||||||
|
*/
|
||||||
|
#define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check all A/D sample module start of conversion overrun flags.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @retval 0 None of sample module event overrun flag is set to 1.
|
||||||
|
* @retval 1 Any one of sample module event overrun flag is set to 1.
|
||||||
|
* @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
|
||||||
|
*/
|
||||||
|
#define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check all A/D interrupt flag overrun bits.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @retval 0 None of ADINT interrupt flag is overwritten to 1.
|
||||||
|
* @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
|
||||||
|
* @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
|
||||||
|
*/
|
||||||
|
#define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the busy state of EADC.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @retval 0 Idle state.
|
||||||
|
* @retval 1 Busy state.
|
||||||
|
* @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
|
||||||
|
*/
|
||||||
|
#define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the comparator 0 and enable it.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
|
||||||
|
* @param[in] u32Condition specifies the compare condition. Valid values are:
|
||||||
|
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
|
||||||
|
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
|
||||||
|
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
|
||||||
|
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
|
||||||
|
* @return None
|
||||||
|
* @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
|
||||||
|
* Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
|
||||||
|
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_CMP0(eadc,\
|
||||||
|
u32ModuleNum,\
|
||||||
|
u32Condition,\
|
||||||
|
u16CMPData,\
|
||||||
|
u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
|
||||||
|
(u32Condition) |\
|
||||||
|
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
|
||||||
|
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
|
||||||
|
EADC_CMP_ADCMPEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the comparator 1 and enable it.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
|
||||||
|
* @param[in] u32Condition specifies the compare condition. Valid values are:
|
||||||
|
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
|
||||||
|
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
|
||||||
|
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
|
||||||
|
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
|
||||||
|
* @return None
|
||||||
|
* @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
|
||||||
|
* Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
|
||||||
|
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_CMP1(eadc,\
|
||||||
|
u32ModuleNum,\
|
||||||
|
u32Condition,\
|
||||||
|
u16CMPData,\
|
||||||
|
u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
|
||||||
|
(u32Condition) |\
|
||||||
|
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
|
||||||
|
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
|
||||||
|
EADC_CMP_ADCMPEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the comparator 2 and enable it.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
|
||||||
|
* @param[in] u32Condition specifies the compare condition. Valid values are:
|
||||||
|
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
|
||||||
|
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
|
||||||
|
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
|
||||||
|
* @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
|
||||||
|
* @return None
|
||||||
|
* @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
|
||||||
|
* Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
|
||||||
|
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_CMP2(eadc,\
|
||||||
|
u32ModuleNum,\
|
||||||
|
u32Condition,\
|
||||||
|
u16CMPData,\
|
||||||
|
u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
|
||||||
|
(u32Condition) |\
|
||||||
|
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
|
||||||
|
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
|
||||||
|
EADC_CMP_ADCMPEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure the comparator 3 and enable it.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
|
||||||
|
* @param[in] u32Condition specifies the compare condition. Valid values are:
|
||||||
|
* - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
|
||||||
|
* - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
|
||||||
|
* @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
|
||||||
|
* @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
|
||||||
|
* @return None
|
||||||
|
* @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
|
||||||
|
* Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
|
||||||
|
* equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_CMP3(eadc,\
|
||||||
|
u32ModuleNum,\
|
||||||
|
u32Condition,\
|
||||||
|
u16CMPData,\
|
||||||
|
u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
|
||||||
|
(u32Condition) |\
|
||||||
|
((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
|
||||||
|
(((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
|
||||||
|
EADC_CMP_ADCMPEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the compare window mode.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
|
||||||
|
* @return None
|
||||||
|
* @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the compare window mode.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
|
||||||
|
* @return None
|
||||||
|
* @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the compare interrupt.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
|
||||||
|
* @return None
|
||||||
|
* @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
|
||||||
|
* and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
|
||||||
|
* if ADCMPIE is set to 1, a compare interrupt request is generated.
|
||||||
|
*/
|
||||||
|
#define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the compare interrupt.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable the compare interrupt.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable comparator 0.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable comparator 0.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable comparator 1.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable comparator 1.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable comparator 2.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable comparator 2.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable comparator 3.
|
||||||
|
* @param[in] eadc The pointer of the specified EADC module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable comparator 3.
|
||||||
|
*/
|
||||||
|
#define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define EADC functions prototype */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
|
||||||
|
void EADC_Close(EADC_T *eadc);
|
||||||
|
void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel);
|
||||||
|
void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
|
||||||
|
void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EADC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__EADC_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,299 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file ebi.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief External Bus Interface(EBI) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EBI_Driver EBI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize EBI for specify Bank
|
||||||
|
*
|
||||||
|
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||||
|
* - \ref EBI_BANK0
|
||||||
|
* - \ref EBI_BANK1
|
||||||
|
* - \ref EBI_BANK2
|
||||||
|
* @param[in] u32DataWidth Data bus width. Valid values are:
|
||||||
|
* - \ref EBI_BUSWIDTH_8BIT
|
||||||
|
* - \ref EBI_BUSWIDTH_16BIT
|
||||||
|
* @param[in] u32TimingClass Default timing configuration. Valid values are:
|
||||||
|
* - \ref EBI_TIMING_FASTEST
|
||||||
|
* - \ref EBI_TIMING_VERYFAST
|
||||||
|
* - \ref EBI_TIMING_FAST
|
||||||
|
* - \ref EBI_TIMING_NORMAL
|
||||||
|
* - \ref EBI_TIMING_SLOW
|
||||||
|
* - \ref EBI_TIMING_VERYSLOW
|
||||||
|
* - \ref EBI_TIMING_SLOWEST
|
||||||
|
* @param[in] u32BusMode Set EBI bus operate mode. Valid values are:
|
||||||
|
* - \ref EBI_OPMODE_NORMAL
|
||||||
|
* - \ref EBI_OPMODE_CACCESS
|
||||||
|
* - \ref EBI_OPMODE_ADSEPARATE
|
||||||
|
* @param[in] u32CSActiveLevel CS is active High/Low. Valid values are:
|
||||||
|
* - \ref EBI_CS_ACTIVE_HIGH
|
||||||
|
* - \ref EBI_CS_ACTIVE_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to open specify EBI bank with different bus width, timing setting and \n
|
||||||
|
* active level of CS pin to access EBI device.
|
||||||
|
* @note Write Buffer Enable(WBUFEN) and Extend Time Of ALE(TALE) are only available in EBI bank0 control register.
|
||||||
|
*/
|
||||||
|
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
|
||||||
|
{
|
||||||
|
uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0);
|
||||||
|
volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1);
|
||||||
|
|
||||||
|
if(u32DataWidth == EBI_BUSWIDTH_8BIT)
|
||||||
|
{
|
||||||
|
*pu32EBICTL &= ~EBI_CTL_DW16_Msk;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*pu32EBICTL |= EBI_CTL_DW16_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
*pu32EBICTL |= u32BusMode;
|
||||||
|
|
||||||
|
switch(u32TimingClass)
|
||||||
|
{
|
||||||
|
case EBI_TIMING_FASTEST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||||
|
*pu32EBITCTL = 0x0U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_VERYFAST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x03003318U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_FAST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||||
|
*pu32EBITCTL = 0x0U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_NORMAL:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x03003318U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_SLOW:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x07007738U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_VERYSLOW:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x07007738U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_SLOWEST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x07007738U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief Initialize EBI for specify Bank API for Non-Secure
|
||||||
|
*/
|
||||||
|
void EBI_Open_NS(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel)
|
||||||
|
{
|
||||||
|
uint32_t u32Index0 = (uint32_t)&EBI_NS->CTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
uint32_t u32Index1 = (uint32_t)&EBI_NS->TCTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0);
|
||||||
|
volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1);
|
||||||
|
|
||||||
|
if(u32DataWidth == EBI_BUSWIDTH_8BIT)
|
||||||
|
{
|
||||||
|
*pu32EBICTL &= ~EBI_CTL_DW16_Msk;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
*pu32EBICTL |= EBI_CTL_DW16_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
*pu32EBICTL |= u32BusMode;
|
||||||
|
|
||||||
|
switch(u32TimingClass)
|
||||||
|
{
|
||||||
|
case EBI_TIMING_FASTEST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||||
|
*pu32EBITCTL = 0x0U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_VERYFAST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_1 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x03003318U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_FAST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk;
|
||||||
|
*pu32EBITCTL = 0x0U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_NORMAL:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x3U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x03003318U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_SLOW:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_2 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x07007738U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_VERYSLOW:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_4 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x07007738U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case EBI_TIMING_SLOWEST:
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~(EBI_CTL_MCLKDIV_Msk | EBI_CTL_TALE_Msk)) |
|
||||||
|
(EBI_MCLKDIV_8 << EBI_CTL_MCLKDIV_Pos) |
|
||||||
|
(u32CSActiveLevel << EBI_CTL_CSPOLINV_Pos) | EBI_CTL_EN_Msk |
|
||||||
|
(0x7U << EBI_CTL_TALE_Pos) ;
|
||||||
|
*pu32EBITCTL = 0x07007738U;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable EBI on specify Bank
|
||||||
|
*
|
||||||
|
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||||
|
* - \ref EBI_BANK0
|
||||||
|
* - \ref EBI_BANK1
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to close specify EBI function.
|
||||||
|
*/
|
||||||
|
void EBI_Close(uint32_t u32Bank)
|
||||||
|
{
|
||||||
|
uint32_t u32Index = (uint32_t)&EBI->CTL0 + u32Bank * 0x10U;
|
||||||
|
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index);
|
||||||
|
|
||||||
|
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief Disable EBI on specify Bank API for Non-Secure
|
||||||
|
*/
|
||||||
|
void EBI_Close_NS(uint32_t u32Bank)
|
||||||
|
{
|
||||||
|
uint32_t u32Index = (uint32_t)&EBI_NS->CTL0 + u32Bank * 0x10U;
|
||||||
|
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index);
|
||||||
|
|
||||||
|
*pu32EBICTL &= ~EBI_CTL_EN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set EBI Bus Timing for specify Bank
|
||||||
|
*
|
||||||
|
* @param[in] u32Bank Bank number for EBI. Valid values are:
|
||||||
|
* - \ref EBI_BANK0
|
||||||
|
* - \ref EBI_BANK1
|
||||||
|
* - \ref EBI_BANK2
|
||||||
|
* @param[in] u32TimingConfig Configure EBI timing settings, includes TACC, TAHD, W2X and R2R setting.
|
||||||
|
* @param[in] u32MclkDiv Divider for MCLK. Valid values are:
|
||||||
|
* - \ref EBI_MCLKDIV_1
|
||||||
|
* - \ref EBI_MCLKDIV_2
|
||||||
|
* - \ref EBI_MCLKDIV_4
|
||||||
|
* - \ref EBI_MCLKDIV_8
|
||||||
|
* - \ref EBI_MCLKDIV_16
|
||||||
|
* - \ref EBI_MCLKDIV_32
|
||||||
|
* - \ref EBI_MCLKDIV_64
|
||||||
|
* - \ref EBI_MCLKDIV_128
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to configure specify EBI bus timing for access EBI device.
|
||||||
|
*/
|
||||||
|
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
|
||||||
|
{
|
||||||
|
uint32_t u32Index0 = (uint32_t)&EBI->CTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
uint32_t u32Index1 = (uint32_t)&EBI->TCTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0);
|
||||||
|
volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1);
|
||||||
|
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
|
||||||
|
*pu32EBITCTL = u32TimingConfig;
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief Set EBI Bus Timing for specify Bank API for Non-Secure
|
||||||
|
*/
|
||||||
|
void EBI_SetBusTiming_NS(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv)
|
||||||
|
{
|
||||||
|
uint32_t u32Index0 = (uint32_t)&EBI_NS->CTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
uint32_t u32Index1 = (uint32_t)&EBI_NS->TCTL0 + (uint32_t)u32Bank * 0x10U;
|
||||||
|
volatile uint32_t *pu32EBICTL = (uint32_t *)(u32Index0);
|
||||||
|
volatile uint32_t *pu32EBITCTL = (uint32_t *)(u32Index1);
|
||||||
|
|
||||||
|
*pu32EBICTL = (*pu32EBICTL & ~EBI_CTL_MCLKDIV_Msk) | (u32MclkDiv << EBI_CTL_MCLKDIV_Pos);
|
||||||
|
*pu32EBITCTL = u32TimingConfig;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EBI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,389 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file ebi.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief External Bus Interface(EBI) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __EBI_H__
|
||||||
|
#define __EBI_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EBI_Driver EBI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup EBI_EXPORTED_CONSTANTS EBI Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Miscellaneous Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EBI_BANK0_BASE_ADDR 0x60000000UL /*!< EBI bank0 base address */
|
||||||
|
#define EBI_BANK1_BASE_ADDR 0x60100000UL /*!< EBI bank1 base address */
|
||||||
|
#define EBI_BANK2_BASE_ADDR 0x60200000UL /*!< EBI bank2 base address */
|
||||||
|
#define EBI_BANK0_BASE_ADDR_NS 0x70000000UL /*!< EBI bank0 base address for Non-Secure */
|
||||||
|
#define EBI_BANK1_BASE_ADDR_NS 0x70100000UL /*!< EBI bank1 base address for Non-Secure */
|
||||||
|
#define EBI_BANK2_BASE_ADDR_NS 0x70200000UL /*!< EBI bank2 base address for Non-Secure */
|
||||||
|
#define EBI_MAX_SIZE 0x00100000UL /*!< Maximum EBI size for each bank is 1 MB */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Constants for EBI bank number */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EBI_BANK0 0UL /*!< EBI bank 0 */
|
||||||
|
#define EBI_BANK1 1UL /*!< EBI bank 1 */
|
||||||
|
#define EBI_BANK2 2UL /*!< EBI bank 2 */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Constants for EBI data bus width */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EBI_BUSWIDTH_8BIT 8UL /*!< EBI bus width is 8-bit */
|
||||||
|
#define EBI_BUSWIDTH_16BIT 16UL /*!< EBI bus width is 16-bit */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Constants for EBI CS Active Level */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EBI_CS_ACTIVE_LOW 0UL /*!< EBI CS active level is low */
|
||||||
|
#define EBI_CS_ACTIVE_HIGH 1UL /*!< EBI CS active level is high */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Constants for EBI MCLK divider and Timing */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define EBI_MCLKDIV_1 0x0UL /*!< EBI output clock(MCLK) is HCLK/1 */
|
||||||
|
#define EBI_MCLKDIV_2 0x1UL /*!< EBI output clock(MCLK) is HCLK/2 */
|
||||||
|
#define EBI_MCLKDIV_4 0x2UL /*!< EBI output clock(MCLK) is HCLK/4 */
|
||||||
|
#define EBI_MCLKDIV_8 0x3UL /*!< EBI output clock(MCLK) is HCLK/8 */
|
||||||
|
#define EBI_MCLKDIV_16 0x4UL /*!< EBI output clock(MCLK) is HCLK/16 */
|
||||||
|
#define EBI_MCLKDIV_32 0x5UL /*!< EBI output clock(MCLK) is HCLK/32 */
|
||||||
|
#define EBI_MCLKDIV_64 0x6UL /*!< EBI output clock(MCLK) is HCLK/64 */
|
||||||
|
#define EBI_MCLKDIV_128 0x7UL /*!< EBI output clock(MCLK) is HCLK/128 */
|
||||||
|
|
||||||
|
#define EBI_TIMING_FASTEST 0x0UL /*!< EBI timing is the fastest */
|
||||||
|
#define EBI_TIMING_VERYFAST 0x1UL /*!< EBI timing is very fast */
|
||||||
|
#define EBI_TIMING_FAST 0x2UL /*!< EBI timing is fast */
|
||||||
|
#define EBI_TIMING_NORMAL 0x3UL /*!< EBI timing is normal */
|
||||||
|
#define EBI_TIMING_SLOW 0x4UL /*!< EBI timing is slow */
|
||||||
|
#define EBI_TIMING_VERYSLOW 0x5UL /*!< EBI timing is very slow */
|
||||||
|
#define EBI_TIMING_SLOWEST 0x6UL /*!< EBI timing is the slowest */
|
||||||
|
|
||||||
|
#define EBI_OPMODE_NORMAL 0x0UL /*!< EBI bus operate in normal mode */
|
||||||
|
#define EBI_OPMODE_CACCESS (EBI_CTL_CACCESS_Msk) /*!< EBI bus operate in Continuous Data Access mode */
|
||||||
|
#define EBI_OPMODE_ADSEPARATE (EBI_CTL_ADSEPEN_Msk) /*!< EBI bus operate in AD Separate mode */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EBI_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup EBI_EXPORTED_FUNCTIONS EBI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 8-bit data on EBI bank0
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank0.
|
||||||
|
*
|
||||||
|
* @return 8-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 8-bit data from specify address on EBI bank0.
|
||||||
|
*/
|
||||||
|
#define EBI0_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 8-bit data on EBI bank0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI0_READ_DATA8_NS(u32Addr) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 8-bit data to EBI bank0
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank0.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 8-bit data to specify address on EBI bank0.
|
||||||
|
*/
|
||||||
|
#define EBI0_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 8-bit data to EBI bank0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI0_WRITE_DATA8_NS(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK0_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 16-bit data on EBI bank0
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank0.
|
||||||
|
*
|
||||||
|
* @return 16-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 16-bit data from specify address on EBI bank0.
|
||||||
|
*/
|
||||||
|
#define EBI0_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 16-bit data on EBI bank0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI0_READ_DATA16_NS(u32Addr) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 16-bit data to EBI bank0
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank0.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 16-bit data to specify address on EBI bank0.
|
||||||
|
*/
|
||||||
|
#define EBI0_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 16-bit data to EBI bank0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI0_WRITE_DATA16_NS(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK0_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit data on EBI bank0
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank0.
|
||||||
|
*
|
||||||
|
* @return 32-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 32-bit data from specify address on EBI bank0.
|
||||||
|
*/
|
||||||
|
#define EBI0_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit data on EBI bank0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI0_READ_DATA32_NS(u32Addr) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 32-bit data to EBI bank0
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank0.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 32-bit data to specify address on EBI bank0.
|
||||||
|
*/
|
||||||
|
#define EBI0_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 32-bit data to EBI bank0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI0_WRITE_DATA32_NS(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK0_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 8-bit data on EBI bank1
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank1.
|
||||||
|
*
|
||||||
|
* @return 8-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 8-bit data from specify address on EBI bank1.
|
||||||
|
*/
|
||||||
|
#define EBI1_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 8-bit data on EBI bank1 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI1_READ_DATA8_NS(u32Addr) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 8-bit data to EBI bank1
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank1.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 8-bit data to specify address on EBI bank1.
|
||||||
|
*/
|
||||||
|
#define EBI1_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 8-bit data to EBI bank1 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI1_WRITE_DATA8_NS(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK1_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 16-bit data on EBI bank1
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank1.
|
||||||
|
*
|
||||||
|
* @return 16-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 16-bit data from specify address on EBI bank1.
|
||||||
|
*/
|
||||||
|
#define EBI1_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 16-bit data on EBI bank1 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI1_READ_DATA16_NS(u32Addr) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 16-bit data to EBI bank1
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank1.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 16-bit data to specify address on EBI bank1.
|
||||||
|
*/
|
||||||
|
#define EBI1_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 16-bit data to EBI bank1 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI1_WRITE_DATA16_NS(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK1_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit data on EBI bank1
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank1.
|
||||||
|
*
|
||||||
|
* @return 32-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 32-bit data from specify address on EBI bank1.
|
||||||
|
*/
|
||||||
|
#define EBI1_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit data on EBI bank1 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI1_READ_DATA32_NS(u32Addr) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 32-bit data to EBI bank1
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank1.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 32-bit data to specify address on EBI bank1.
|
||||||
|
*/
|
||||||
|
#define EBI1_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 32-bit data to EBI bank1 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI1_WRITE_DATA32_NS(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK1_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 8-bit data on EBI bank2
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank2.
|
||||||
|
*
|
||||||
|
* @return 8-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 8-bit data from specify address on EBI bank2.
|
||||||
|
*/
|
||||||
|
#define EBI2_READ_DATA8(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 8-bit data on EBI bank2 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI2_READ_DATA8_NS(u32Addr) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 8-bit data to EBI bank2
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank2.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 8-bit data to specify address on EBI bank2.
|
||||||
|
*/
|
||||||
|
#define EBI2_WRITE_DATA8(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 8-bit data to EBI bank2 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI2_WRITE_DATA8_NS(u32Addr, u32Data) (*((volatile unsigned char *)(EBI_BANK2_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 16-bit data on EBI bank2
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank2.
|
||||||
|
*
|
||||||
|
* @return 16-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 16-bit data from specify address on EBI bank2.
|
||||||
|
*/
|
||||||
|
#define EBI2_READ_DATA16(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 16-bit data on EBI bank2 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI2_READ_DATA16_NS(u32Addr) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 16-bit data to EBI bank2
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank2.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 16-bit data to specify address on EBI bank2.
|
||||||
|
*/
|
||||||
|
#define EBI2_WRITE_DATA16(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 16-bit data to EBI bank2 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI2_WRITE_DATA16_NS(u32Addr, u32Data) (*((volatile unsigned short *)(EBI_BANK2_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit data on EBI bank2
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank2.
|
||||||
|
*
|
||||||
|
* @return 32-bit Data
|
||||||
|
*
|
||||||
|
* @details This macro is used to read 32-bit data from specify address on EBI bank2.
|
||||||
|
*/
|
||||||
|
#define EBI2_READ_DATA32(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))))
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit data on EBI bank2 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI2_READ_DATA32_NS(u32Addr) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR_NS+(u32Addr))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write 32-bit data to EBI bank2
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr The data address on EBI bank2.
|
||||||
|
* @param[in] u32Data Specify data to be written.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to write 32-bit data to specify address on EBI bank2.
|
||||||
|
*/
|
||||||
|
#define EBI2_WRITE_DATA32(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR+(u32Addr))) = (u32Data))
|
||||||
|
/**
|
||||||
|
* @brief Write 32-bit data to EBI bank2 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define EBI2_WRITE_DATA32_NS(u32Addr, u32Data) (*((volatile unsigned int *)(EBI_BANK2_BASE_ADDR_NS+(u32Addr))) = (u32Data))
|
||||||
|
|
||||||
|
|
||||||
|
void EBI_Open(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
|
||||||
|
void EBI_Open_NS(uint32_t u32Bank, uint32_t u32DataWidth, uint32_t u32TimingClass, uint32_t u32BusMode, uint32_t u32CSActiveLevel);
|
||||||
|
void EBI_Close(uint32_t u32Bank);
|
||||||
|
void EBI_Close_NS(uint32_t u32Bank);
|
||||||
|
void EBI_SetBusTiming(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
|
||||||
|
void EBI_SetBusTiming_NS(uint32_t u32Bank, uint32_t u32TimingConfig, uint32_t u32MclkDiv);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EBI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group EBI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __EBI_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,114 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file ecap.c
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/11/02 9:08a $
|
||||||
|
* @brief Enhanced Input Capture Timer (ECAP) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ECAP_Driver ECAP Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable ECAP funtion
|
||||||
|
* @param[in] ecap The pointer of the specified ECAP module.
|
||||||
|
* @param[in] u32FuncMask Input Caputer function select
|
||||||
|
* - \ref ECAP_DISABLE_COMPARE_RELOAD
|
||||||
|
* - \ref ECAP_COMPARE_FUNCTION
|
||||||
|
* - \ref ECAP_RELOAD_FUNCTION
|
||||||
|
* - \ref ECAP_RELOAD_COMPARE_FUNCTION
|
||||||
|
|
||||||
|
* @return None
|
||||||
|
* @details This macro enable input capture function and select compare and reload funciton.
|
||||||
|
*/
|
||||||
|
void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask)
|
||||||
|
{
|
||||||
|
/* Clear Input capture mode*/
|
||||||
|
ecap->CTL0 = ecap->CTL0 & ~(ECAP_CTL0_RLDEN_Msk | ECAP_CTL0_CMPEN_Msk);
|
||||||
|
|
||||||
|
/* Enable Input Capture and set mode */
|
||||||
|
ecap->CTL0 |= ECAP_CTL0_CAPEN_Msk |
|
||||||
|
((u32FuncMask) << ECAP_CTL0_RLDEN_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ECAP funtion
|
||||||
|
* @param[in] ecap The pointer of the specified ECAP module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable input capture function.
|
||||||
|
*/
|
||||||
|
void ECAP_Close(ECAP_T* ecap)
|
||||||
|
{
|
||||||
|
/* Disable Input Capture*/
|
||||||
|
ecap->CTL0 &= ~ECAP_CTL0_CAPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable input channel interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel Mask
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN0_Msk
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN1_Msk
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN2_Msk
|
||||||
|
* - \ref ECAP_CTL0_OVIEN_Msk
|
||||||
|
* - \ref ECAP_CTL0_CMPIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the input channel_n interrupt.
|
||||||
|
*/
|
||||||
|
void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
/* Enable input channel interrupt */
|
||||||
|
ecap->CTL0 |= (u32Mask);
|
||||||
|
|
||||||
|
/* Enable NVIC ECAP IRQ */
|
||||||
|
if(ecap == ECAP0)
|
||||||
|
NVIC_EnableIRQ(ECAP0_IRQn);
|
||||||
|
else
|
||||||
|
NVIC_EnableIRQ(ECAP1_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable input channel interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel number
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN0_Msk
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN1_Msk
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN2_Msk
|
||||||
|
* - \ref ECAP_CTL0_OVIEN_Msk
|
||||||
|
* - \ref ECAP_CTL0_CMPIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the input channel_n interrupt.
|
||||||
|
*/
|
||||||
|
void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
/* Disable input channel interrupt */
|
||||||
|
ecap->CTL0 &= ~(u32Mask);
|
||||||
|
|
||||||
|
/* Disable NVIC ECAP IRQ */
|
||||||
|
if(ecap == ECAP0)
|
||||||
|
NVIC_DisableIRQ(ECAP0_IRQn);
|
||||||
|
else
|
||||||
|
NVIC_DisableIRQ(ECAP1_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ECAP_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,462 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file ecap.h
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/08/12 9:31a $
|
||||||
|
* @brief EnHanced Input Capture Timer(ECAP) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __ECAP_H__
|
||||||
|
#define __ECAP_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ECAP_Driver ECAP Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup ECAP_EXPORTED_CONSTANTS ECAP Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define ECAP_IC0 (0UL) /*!< ECAP IC0 Unit */
|
||||||
|
#define ECAP_IC1 (1UL) /*!< ECAP IC1 Unit */
|
||||||
|
#define ECAP_IC2 (2UL) /*!< ECAP IC2 Unit */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* ECAP CTL0 constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define ECAP_NOISE_FILTER_CLKDIV_1 (0UL) /*!< Noise filter clock divide by 1 */
|
||||||
|
#define ECAP_NOISE_FILTER_CLKDIV_2 (1UL) /*!< Noise filter clock divide by 2 */
|
||||||
|
#define ECAP_NOISE_FILTER_CLKDIV_4 (2UL) /*!< Noise filter clock divide by 4 */
|
||||||
|
#define ECAP_NOISE_FILTER_CLKDIV_16 (3UL) /*!< Noise filter clock divide by 16 */
|
||||||
|
#define ECAP_NOISE_FILTER_CLKDIV_32 (4UL) /*!< Noise filter clock divide by 32 */
|
||||||
|
#define ECAP_NOISE_FILTER_CLKDIV_64 (5UL) /*!< Noise filter clock divide by 64 */
|
||||||
|
|
||||||
|
|
||||||
|
#define ECAP_CAP_INPUT_SRC_FROM_IC (0UL) /*!< CAP input source from IC */
|
||||||
|
#define ECAP_CAP_INPUT_SRC_FROM_CH (2UL) /*!< CAP input source from CH of QEI */
|
||||||
|
|
||||||
|
#define ECAP_CNT_CLR_EVENT_DISABLE (0UL) /*!< Input channel counter cleared event disabled */
|
||||||
|
#define ECAP_CNT_CLR_BY_CMP (1UL) /*!< Input channel counter cleared by Compare-Match */
|
||||||
|
#define ECAP_CNT_CLR_BY_CAPTURE (2UL) /*!< Input channel counter cleared by Capture */
|
||||||
|
#define ECAP_CNT_CLR_BY_CAMCMPF (3UL) /*!< Input channel counter cleared by Compare-Match & capture */
|
||||||
|
|
||||||
|
#define ECAP_DISABLE_COMPARE_RELOAD 0x00 /*!< Input capture compare and reload function disable*/
|
||||||
|
#define ECAP_RELOAD_FUNCTION 0x01 /*!< Input capture reload function */
|
||||||
|
#define ECAP_COMPARE_FUNCTION 0x02 /*!< Input capture compare function */
|
||||||
|
#define ECAP_RELOAD_COMPARE_FUNCTION 0x03 /*!< Input capture reload & compare function */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* ECAP CTL1 constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define ECAP_RISING_EDGE (0UL) /*!< ECAP capture rising edge selection */
|
||||||
|
#define ECAP_FALLING_EDGE (1UL) /*!< ECAP capture falling edge selection */
|
||||||
|
#define ECAP_RISING_FALLING_EDGE (2UL) /*!< ECAP capture either rising or falling edge selection */
|
||||||
|
|
||||||
|
#define ECAP_RELOAD_TRIG_SRC_CAPF0 (0UL) /*!< ECAP counter reload trigger source CAPF0 selection */
|
||||||
|
#define ECAP_RELOAD_TRIG_SRC_CAPF1 (1UL) /*!< ECAP counter reload trigger source CAPF1 selection */
|
||||||
|
#define ECAP_RELOAD_TRIG_SRC_CAPF2 (2UL) /*!< ECAP counter reload trigger source CAPF2 selection */
|
||||||
|
#define ECAP_RELOAD_TRIG_SRC_OVF (4UL) /*!< ECAP counter reload trigger source OVF selection */
|
||||||
|
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_1 (0UL) /*!< ECAP capture timer clock divide by 1 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_4 (1UL) /*!< ECAP capture timer clock divide by 4 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_16 (2UL) /*!< ECAP capture timer clock divide by 16 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_32 (3UL) /*!< ECAP capture timer clock divide by 32 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_64 (4UL) /*!< ECAP capture timer clock divide by 64 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_96 (5UL) /*!< ECAP capture timer clock divide by 96 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_112 (6UL) /*!< ECAP capture timer clock divide by 112 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLKDIV_128 (7UL) /*!< ECAP capture timer clock divide by 128 */
|
||||||
|
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK (0UL) /*!< ECAP capture timer/clock source from CAP_CLK */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP0 (1UL) /*!< ECAP capture timer/clock source from CAP0 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP1 (2UL) /*!< ECAP capture timer/clock source from CAP1 */
|
||||||
|
#define ECAP_CAPTURE_TIMER_CLK_SRC_CAP2 (3UL) /*!< ECAP capture timer/clock source from CAP2 */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ECAP_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup ECAP_EXPORTED_FUNCTIONS ECAP Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select noise filter clock pre-divide number
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32ClkSel The noise filter clock divide number
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_1
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_2
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_4
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_16
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set the sampling frequency of the noise filter cock.
|
||||||
|
*/
|
||||||
|
#define ECAP_SET_NOISE_FILTER_CLKDIV(ecap, u32ClkSel) ((ecap)->CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFCLKSEL_Msk)|((u32ClkSel)<<ECAP_CTL0_NFCLKSEL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable noise filter
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the noise filter of input capture.
|
||||||
|
*/
|
||||||
|
#define ECAP_NOISE_FILTER_DISABLE(ecap) ((ecap)->CTL0 |= ECAP_CTL0_NFDIS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable noise filter
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32ClkSel Select noise filter clock divide number
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_1
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_2
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_4
|
||||||
|
* - \ref ECAP_NOISE_FILTER_CLKDIV_16
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the noise filter of input capture and set noise filter clock divide.
|
||||||
|
*/
|
||||||
|
#define ECAP_NOISE_FILTER_ENABLE(ecap) ((ecap)->CTL0 = ((ecap)->CTL0 & ~ECAP_CTL0_NFDIS_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable input channel unit
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel mask
|
||||||
|
* - \ref ECAP_IC0
|
||||||
|
* - \ref ECAP_IC1
|
||||||
|
* - \ref ECAP_IC2
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the input channel_n to input capture.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 |= 1<<(u32Mask+4))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable input channel unit
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel mask
|
||||||
|
* - \ref ECAP_IC0
|
||||||
|
* - \ref ECAP_IC1
|
||||||
|
* - \ref ECAP_IC2
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the input channel_n to input capture.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_INPUT_CHANNEL(ecap, u32Mask) ((ecap)->CTL0 &= ~(1<<(u32Mask+4)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select input channel source
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Index The input channel number
|
||||||
|
* - \ref ECAP_IC0
|
||||||
|
* - \ref ECAP_IC1
|
||||||
|
* - \ref ECAP_IC2
|
||||||
|
* @param[in] u32Src The input source
|
||||||
|
* - \ref ECAP_CAP_INPUT_SRC_FROM_IC
|
||||||
|
* - \ref ECAP_CAP_INPUT_SRC_FROM_CH
|
||||||
|
* @return None
|
||||||
|
* @details This macro will select the input soure from ICx, CPOx, CHx, ADCMPO or OPDO.
|
||||||
|
*/
|
||||||
|
#define ECAP_SEL_INPUT_SRC(ecap, u32Index, u32Src) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CAPSEL0_Msk<<((u32Index)<<1)))|((u32Src)<<(ECAP_CTL0_CAPSEL0_Pos)<<((u32Index)<<1)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable input channel interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel mask
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN0_Msk
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN1_Msk
|
||||||
|
* - \ref ECAP_CTL0_CAPIEN2_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the input channel_n interrupt.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_INT(ecap, u32Mask) ((ecap)->CTL0 |= (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable input channel interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel mask
|
||||||
|
* - \ref ECAP_IC0
|
||||||
|
* - \ref ECAP_IC1
|
||||||
|
* - \ref ECAP_IC2
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the input channel_n interrupt.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_INT(ecap, u32Mask) ((ecap)->CTL0 &= ~(u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable input channel overflow interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the input channel overflow interrupt.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_OVF_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_OVIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable input channel overflow interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the input channel overflow interrupt.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_OVF_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_OVIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable input channel compare-match interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the input channel compare-match interrupt.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable input channel compare-match interrupt
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the input channel compare-match interrupt.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_CMP_MATCH_INT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to start capture counter
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will start capture counter up-counting.
|
||||||
|
*/
|
||||||
|
#define ECAP_CNT_START(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CNTEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to stop capture counter
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will stop capture counter up-counting.
|
||||||
|
*/
|
||||||
|
#define ECAP_CNT_STOP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CNTEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set event to clear capture counter
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Event The input channel number
|
||||||
|
* - \ref ECAP_CNT_CLR_EVENT_DISABLE
|
||||||
|
* - \ref ECAP_CNT_CLR_BY_CMP
|
||||||
|
* - \ref ECAP_CNT_CLR_BY_CAPTURE
|
||||||
|
* - \ref ECAP_CNT_CLR_BY_CAMCMPF
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable and select compare or capture event that can clear capture counter.
|
||||||
|
*/
|
||||||
|
#define ECAP_SET_CNT_CLEAR_EVENT(ecap, u32Event) ((ecap)->CTL0 = ((ecap)->CTL0 & ~(ECAP_CTL0_CMPCLR_Msk | ECAP_CTL0_CPTCLR_Msk))|((u32Event) << ECAP_CTL0_CMPCLR_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable reload function
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the reload function.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_RELOAD(ecap) ((ecap)->CTL0 |= ECAP_CTL0_RLDEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable reload function
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the reload function.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_RELOAD(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_RLDEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable compare function
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable the compare function.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_CMP(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CMPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable compare function
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable the compare function.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_CMP(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CMPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable input capture function.
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable input capture timer/counter.
|
||||||
|
*/
|
||||||
|
#define ECAP_ENABLE_CNT(ecap) ((ecap)->CTL0 |= ECAP_CTL0_CAPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable input capture function.
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable input capture timer/counter.
|
||||||
|
*/
|
||||||
|
#define ECAP_DISABLE_CNT(ecap) ((ecap)->CTL0 &= ~ECAP_CTL0_CAPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select input channel edge detection
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Index The input channel number
|
||||||
|
* - \ref ECAP_IC0
|
||||||
|
* - \ref ECAP_IC1
|
||||||
|
* - \ref ECAP_IC2
|
||||||
|
* @param[in] u32Edge The input source
|
||||||
|
* - \ref ECAP_RISING_EDGE
|
||||||
|
* - \ref ECAP_FALLING_EDGE
|
||||||
|
* - \ref ECAP_RISING_FALLING_EDGE
|
||||||
|
* @return None
|
||||||
|
* @details This macro will select input capture can detect falling edge, rising edge or either rising or falling edge change.
|
||||||
|
*/
|
||||||
|
#define ECAP_SEL_CAPTURE_EDGE(ecap, u32Index, u32Edge) ((ecap)->CTL1 = ((ecap)->CTL1 & ~(ECAP_CTL1_EDGESEL0_Msk<<((u32Index)<<1)))|((u32Edge)<<(ECAP_CTL1_EDGESEL0_Pos)<<((u32Index)<<1)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select ECAP counter reload trigger source
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32TrigSrc The input source
|
||||||
|
* - \ref ECAP_RELOAD_TRIG_SRC_CAPF0
|
||||||
|
* - \ref ECAP_RELOAD_TRIG_SRC_CAPF1
|
||||||
|
* - \ref ECAP_RELOAD_TRIG_SRC_CAPF2
|
||||||
|
* - \ref ECAP_RELOAD_TRIG_SRC_OVF
|
||||||
|
* @return None
|
||||||
|
* @details This macro will select capture counter reload trigger source.
|
||||||
|
*/
|
||||||
|
#define ECAP_SEL_RELOAD_TRIG_SRC(ecap, u32TrigSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_RLDSEL_Msk)|((u32TrigSrc)<<ECAP_CTL1_RLDSEL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select capture timer clock divide.
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Clkdiv The input source
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_1
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_4
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_16
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_32
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_64
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_96
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_112
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLKDIV_128
|
||||||
|
* @return None
|
||||||
|
* @details This macro will select capture timer clock has a pre-divider with eight divided option.
|
||||||
|
*/
|
||||||
|
#define ECAP_SEL_TIMER_CLK_DIV(ecap, u32Clkdiv) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CLKSEL_Msk)|((u32Clkdiv)<<ECAP_CTL1_CLKSEL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to select capture timer/counter clock source
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32ClkSrc The input source
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP_CLK
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP0
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP1
|
||||||
|
* - \ref ECAP_CAPTURE_TIMER_CLK_SRC_CAP2
|
||||||
|
* @return None
|
||||||
|
* @details This macro will select capture timer/clock clock source.
|
||||||
|
*/
|
||||||
|
#define ECAP_SEL_TIMER_CLK_SRC(ecap, u32ClkSrc) ((ecap)->CTL1 = ((ecap)->CTL1 & ~ECAP_CTL1_CNTSRC_Msk)|((u32ClkSrc)<<ECAP_CTL1_CNTSRC_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to read input capture status
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return Input capture status flags
|
||||||
|
* @details This macro will get the input capture interrupt status.
|
||||||
|
*/
|
||||||
|
#define ECAP_GET_INT_STATUS(ecap) ((ecap)->STATUS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get input channel interrupt flag
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel mask
|
||||||
|
* - \ref ECAP_STATUS_CAPTF0_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPTF1_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPTF2_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPOVF_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPCMPF_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write 1 to get the input channel_n interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ECAP_GET_CAPTURE_FLAG(ecap, u32Mask) (((ecap)->STATUS & (u32Mask))?1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear input channel interrupt flag
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Mask The input channel mask
|
||||||
|
* - \ref ECAP_STATUS_CAPTF0_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPTF1_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPTF2_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPOVF_Msk
|
||||||
|
* - \ref ECAP_STATUS_CAPCMPF_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write 1 to clear the input channel_n interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ECAP_CLR_CAPTURE_FLAG(ecap, u32Mask) ((ecap)->STATUS = (u32Mask))
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear input capture-match interrupt flag
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write 1 to clear the input capture-match interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ECAP_CLR_CMP_MATCH_FLAG(ecap) ((ecap)->STATUS = ECAP_STATUS_CAPCMPF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear input overflow interrupt flag
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write 1 to clear the input overflow interrupt flag.
|
||||||
|
*/
|
||||||
|
#define ECAP_CLR_OVF_FLAG(ecap) ((ecap)->STATUS = ECAP_STATUS_CAPOVF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set input capture counter value
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Val Counter value
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set a counter value of input capture.
|
||||||
|
*/
|
||||||
|
#define ECAP_SET_CNT_VALUE(ecap, u32Val) ((ecap)->CNT = (u32Val))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get input capture counter value
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @return Capture counter value
|
||||||
|
* @details This macro will get a counter value of input capture.
|
||||||
|
*/
|
||||||
|
#define ECAP_GET_CNT_VALUE(ecap) ((ecap)->CNT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get input capture counter hold value
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Index The input channel number
|
||||||
|
* - \ref ECAP_IC0
|
||||||
|
* - \ref ECAP_IC1
|
||||||
|
* - \ref ECAP_IC2
|
||||||
|
* @return Capture counter hold value
|
||||||
|
* @details This macro will get a hold value of input capture channel_n.
|
||||||
|
*/
|
||||||
|
#define ECAP_GET_CNT_HOLD_VALUE(ecap, u32Index) (*(__IO uint32_t *) (&((ecap)->HLD0) + (u32Index)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set input capture counter compare value
|
||||||
|
* @param[in] ecap Specify ECAP port
|
||||||
|
* @param[in] u32Val Input capture compare value
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set a compare value of input capture counter.
|
||||||
|
*/
|
||||||
|
#define ECAP_SET_CNT_CMP(ecap, u32Val) ((ecap)->CNTCMP = (u32Val))
|
||||||
|
|
||||||
|
void ECAP_Open(ECAP_T* ecap, uint32_t u32FuncMask);
|
||||||
|
void ECAP_Close(ECAP_T* ecap);
|
||||||
|
void ECAP_EnableINT(ECAP_T* ecap, uint32_t u32Mask);
|
||||||
|
void ECAP_DisableINT(ECAP_T* ecap, uint32_t u32Index);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ECAP_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group ECAP_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__ECAP_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,831 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file fmc.c
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/07/07 7:50p $
|
||||||
|
* @brief M2351 Series Flash Memory Controller(FMC) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include <stdio.h>
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FMC_Driver FMC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set boot source from LDROM or APROM after next software reset
|
||||||
|
*
|
||||||
|
* @param[in] i32BootSrc
|
||||||
|
* 1: Boot from LDROM
|
||||||
|
* 0: Boot from APROM
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to switch APROM boot or LDROM boot. User need to call
|
||||||
|
* FMC_SetBootSource to select boot source first, then use CPU reset or
|
||||||
|
* System Reset Request to reset system.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_SetBootSource(int32_t i32BootSrc)
|
||||||
|
{
|
||||||
|
if(i32BootSrc)
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_BS_Msk; /* Boot from LDROM */
|
||||||
|
else
|
||||||
|
FMC->ISPCTL &= ~FMC_ISPCTL_BS_Msk;/* Boot from APROM */
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ISP Functions
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will clear ISPEN bit of ISPCON to disable ISP function
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_Close(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable APROM update function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Disable APROM update function will forbid APROM programming when boot form APROM.
|
||||||
|
* APROM update is default to be disable.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_DisableAPUpdate(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable User Configuration update function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Disable User Configuration update function will forbid User Configuration programming.
|
||||||
|
* User Configuration update is default to be disable.
|
||||||
|
*/
|
||||||
|
void FMC_DisableConfigUpdate(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable LDROM update function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
|
||||||
|
* @details Disable LDROM update function will forbid LDROM programming.
|
||||||
|
* LDROM update is default to be disable.
|
||||||
|
*/
|
||||||
|
void FMC_DisableLDUpdate(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable APROM update function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable APROM to be able to program when boot from APROM.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_EnableAPUpdate(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable User Configuration update function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable User Configuration to be able to program.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_EnableConfigUpdate(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable LDROM update function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable LDROM to be able to program.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_EnableLDUpdate(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the current boot source
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 This chip is currently booting from APROM
|
||||||
|
* @retval 1 This chip is currently booting from LDROM
|
||||||
|
*
|
||||||
|
* @note This function only show the boot source.
|
||||||
|
* User need to read ISPSTA register to know if IAP mode supported or not in relative boot.
|
||||||
|
*/
|
||||||
|
int32_t FMC_GetBootSource(void)
|
||||||
|
{
|
||||||
|
if(FMC->ISPCTL & FMC_ISPCTL_BS_Msk)
|
||||||
|
return 1;
|
||||||
|
else
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FMC ISP function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details ISPEN bit of ISPCON must be set before we can use ISP commands.
|
||||||
|
* Therefore, To use all FMC function APIs, user needs to call FMC_Open() first to enable ISP functions.
|
||||||
|
*
|
||||||
|
* @note ISP functions are write-protected. user also needs to unlock it by calling SYS_UnlockReg() before using all ISP functions.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
void FMC_Open(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read the User Configuration words.
|
||||||
|
*
|
||||||
|
* @param[out] u32Config The word buffer to store the User Configuration data.
|
||||||
|
* @param[in] u32Count The word count to be read.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Failed
|
||||||
|
*
|
||||||
|
* @details This function is used to read the settings of user configuration.
|
||||||
|
* if u32Count = 1, Only CONFIG0 will be returned to the buffer specified by u32Config.
|
||||||
|
* if u32Count = 2, Both CONFIG0 and CONFIG1 will be returned.
|
||||||
|
*/
|
||||||
|
int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count)
|
||||||
|
{
|
||||||
|
int32_t i;
|
||||||
|
|
||||||
|
for(i = 0; i < u32Count; i++)
|
||||||
|
u32Config[i] = FMC_Read(FMC_CONFIG_BASE + i * 4);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write User Configuration
|
||||||
|
*
|
||||||
|
* @param[in] u32Config The word buffer to store the User Configuration data.
|
||||||
|
* @param[in] u32Count The word count to program to User Configuration.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Failed
|
||||||
|
*
|
||||||
|
* @details User must enable User Configuration update before writing it.
|
||||||
|
* User must erase User Configuration before writing it.
|
||||||
|
* User Configuration is also be page erase. User needs to backup necessary data
|
||||||
|
* before erase User Configuration.
|
||||||
|
*/
|
||||||
|
int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count)
|
||||||
|
{
|
||||||
|
int32_t i;
|
||||||
|
|
||||||
|
for(i = 0; i < u32Count; i++)
|
||||||
|
{
|
||||||
|
FMC_Write(FMC_CONFIG_BASE + i * 4, u32Config[i]);
|
||||||
|
if(FMC_Read(FMC_CONFIG_BASE + i * 4) != u32Config[i])
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Execute Flash Block erase
|
||||||
|
*
|
||||||
|
* @param[in] u32BlockAddr Address of the flash block to be erased.
|
||||||
|
* It must be a 4 pages aligned address.
|
||||||
|
*
|
||||||
|
* @return ISP page erase success or not.
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Erase failed
|
||||||
|
*
|
||||||
|
* @details Execute FMC_ISPCMD_BLOCK_ERASE command to erase a flash block. The block size is 4 pages.
|
||||||
|
*/
|
||||||
|
int32_t FMC_Erase_Block(uint32_t u32BlockAddr)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_BLOCK_ERASE;
|
||||||
|
FMC->ISPADDR = u32BlockAddr;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Execute Flash Bank erase
|
||||||
|
*
|
||||||
|
* @param[in] u32BankAddr Base address of the flash bank to be erased.
|
||||||
|
*
|
||||||
|
* @return ISP page erase success or not.
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Erase failed
|
||||||
|
*
|
||||||
|
* @details Execute FMC_ISPCMD_BANK_ERASE command to erase a flash block.
|
||||||
|
*/
|
||||||
|
int32_t FMC_Erase_Bank(uint32_t u32BankAddr)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_BANK_ERASE;
|
||||||
|
FMC->ISPADDR = u32BankAddr;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk) {
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write data to OTP
|
||||||
|
* @param[in] otp_num The OTP number.
|
||||||
|
* @param[in] low_word Low word of the 64-bits data.
|
||||||
|
* @param[in] high_word Low word of the 64-bits data.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Program failed.
|
||||||
|
* @retval -2 Invalid OTP number.
|
||||||
|
*
|
||||||
|
* @details Program a 64-bits data to the specified OTP.
|
||||||
|
*/
|
||||||
|
int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (otp_num > 255UL) {
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||||
|
FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL;
|
||||||
|
FMC->ISPDAT = low_word;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||||
|
FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL;
|
||||||
|
FMC->ISPDAT = high_word;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read data from OTP
|
||||||
|
*
|
||||||
|
* @param[in] otp_num The OTP number.
|
||||||
|
* @param[in] low_word Low word of the 64-bits data.
|
||||||
|
* @param[in] high_word Low word of the 64-bits data.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Read failed.
|
||||||
|
* @retval -2 Invalid OTP number.
|
||||||
|
*
|
||||||
|
* @details Read the 64-bits data from the specified OTP.
|
||||||
|
*/
|
||||||
|
int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (otp_num > 255UL) {
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READE_8;
|
||||||
|
FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ;
|
||||||
|
FMC->ISPDAT = 0x0UL;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
} else {
|
||||||
|
*low_word = FMC->MPDAT0;
|
||||||
|
*high_word = FMC->MPDAT1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Lock the specified OTP.
|
||||||
|
*
|
||||||
|
* @param[in] otp_num The OTP number.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Failed to write OTP lock bits.
|
||||||
|
* @retval -2 Invalid OTP number.
|
||||||
|
*
|
||||||
|
* @details To lock specified OTP number
|
||||||
|
*/
|
||||||
|
int32_t FMC_Lock_OTP(uint32_t otp_num)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (otp_num > 255UL) {
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||||
|
FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
|
||||||
|
FMC->ISPDAT = 0UL;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check the OTP is locked or not.
|
||||||
|
*
|
||||||
|
* @param[in] otp_num The OTP number.
|
||||||
|
*
|
||||||
|
* @retval 1 OTP is locked.
|
||||||
|
* @retval 0 OTP is not locked.
|
||||||
|
* @retval -1 Failed to read OTP lock bits.
|
||||||
|
* @retval -2 Invalid OTP number.
|
||||||
|
*
|
||||||
|
* @details To get specify OPT lock status
|
||||||
|
*/
|
||||||
|
int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (otp_num > 255UL) {
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||||
|
FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
|
||||||
|
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
} else {
|
||||||
|
if (FMC->ISPDAT != 0xFFFFFFFFUL) {
|
||||||
|
ret = 1; /* Lock work was progrmmed. OTP was locked. */
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Run CRC32 checksum calculation and get result.
|
||||||
|
*
|
||||||
|
* @param[in] u32addr Starting flash address. It must be a page aligned address.
|
||||||
|
* @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
|
||||||
|
*
|
||||||
|
* @return Success or not.
|
||||||
|
* @retval 0 Success.
|
||||||
|
* @retval 0xFFFFFFFF Invalid parameter.
|
||||||
|
*
|
||||||
|
* details Run ISP checksum command to calculate specify area
|
||||||
|
*/
|
||||||
|
uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
|
||||||
|
{
|
||||||
|
uint32_t ret;
|
||||||
|
|
||||||
|
if ((u32addr % 512UL) || (u32count % 512UL)) {
|
||||||
|
ret = 0xFFFFFFFF;
|
||||||
|
} else {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
|
||||||
|
FMC->ISPADDR = u32addr;
|
||||||
|
FMC->ISPDAT = u32count;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||||
|
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
|
||||||
|
FMC->ISPADDR = u32addr;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||||
|
|
||||||
|
ret = FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Run flash all one verification and get result.
|
||||||
|
*
|
||||||
|
* @param[in] u32addr Starting flash address. It must be a page aligned address.
|
||||||
|
* @param[in] u32count Byte count of flash to be calculated. It must be multiple of 512 bytes.
|
||||||
|
*
|
||||||
|
* @retval READ_ALLONE_YES The contents of verified flash area are 0xFFFFFFFF.
|
||||||
|
* @retval READ_ALLONE_NOT Some contents of verified flash area are not 0xFFFFFFFF.
|
||||||
|
* @retval READ_ALLONE_CMD_FAIL Unexpected error occurred.
|
||||||
|
*
|
||||||
|
* @details Run ISP check all one command to check specify area is all one or not.
|
||||||
|
*/
|
||||||
|
uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count)
|
||||||
|
{
|
||||||
|
uint32_t ret = READ_ALLONE_CMD_FAIL;
|
||||||
|
|
||||||
|
FMC->ISPSTS = 0x80UL; /* clear check all one bit */
|
||||||
|
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_RUN_ALL1;
|
||||||
|
FMC->ISPADDR = u32addr;
|
||||||
|
FMC->ISPDAT = u32count;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
|
||||||
|
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||||
|
|
||||||
|
do {
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ_ALL1;
|
||||||
|
FMC->ISPADDR = u32addr;
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
|
||||||
|
while (FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk) { }
|
||||||
|
} while (FMC->ISPDAT == 0UL);
|
||||||
|
|
||||||
|
if (FMC->ISPDAT == READ_ALLONE_YES) {
|
||||||
|
ret = FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (FMC->ISPDAT == READ_ALLONE_NOT) {
|
||||||
|
ret = FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Setup security key.
|
||||||
|
*
|
||||||
|
* @param[in] key Key 0~2 to be setup.
|
||||||
|
* @param[in] kpmax Maximum unmatched power-on counting number.
|
||||||
|
* @param[in] kemax Maximum unmatched counting number.
|
||||||
|
* @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG.
|
||||||
|
* @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. (This status is not supported on M2351)
|
||||||
|
*
|
||||||
|
* @retval 0 Success.
|
||||||
|
* @retval -1 Key is locked. Cannot overwrite the current key.
|
||||||
|
* @retval -2 Failed to erase flash.
|
||||||
|
* @retval -3 Failed to program key.
|
||||||
|
* @retval -4 Key lock function failed.
|
||||||
|
* @retval -5 CONFIG lock function failed.
|
||||||
|
* @retval -5 CONFIG lock function failed.
|
||||||
|
* @retval -6 SPROM lock function failed. (This status is not supported on M2351)
|
||||||
|
* @retval -7 KPMAX function failed.
|
||||||
|
* @retval -8 KEMAX function failed.
|
||||||
|
*
|
||||||
|
* @details Set security keys and setup key compare count. The Security key also can protect user config.
|
||||||
|
*/
|
||||||
|
int32_t FMC_SKey_Setup(uint32_t key[3], uint32_t kpmax, uint32_t kemax,
|
||||||
|
const int32_t lock_CONFIG, const int32_t lock_SPROM)
|
||||||
|
{
|
||||||
|
uint32_t lock_ctrl = 0UL;
|
||||||
|
uint32_t u32KeySts;
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (FMC->KPKEYSTS != 0x200UL) {
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (FMC_Erase(FMC_KPROM_BASE)) {
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (FMC_Erase(FMC_KPROM_BASE+0x200UL)) {
|
||||||
|
ret = -3;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!lock_CONFIG) {
|
||||||
|
lock_ctrl |= 0x1UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!lock_SPROM) {
|
||||||
|
lock_ctrl |= 0x2UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC_Write(FMC_KPROM_BASE, key[0]);
|
||||||
|
FMC_Write(FMC_KPROM_BASE+0x4UL, key[1]);
|
||||||
|
FMC_Write(FMC_KPROM_BASE+0x8UL, key[2]);
|
||||||
|
FMC_Write(FMC_KPROM_BASE+0xCUL, kpmax);
|
||||||
|
FMC_Write(FMC_KPROM_BASE+0x10UL, kemax);
|
||||||
|
FMC_Write(FMC_KPROM_BASE+0x14UL, lock_ctrl);
|
||||||
|
|
||||||
|
while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
|
||||||
|
|
||||||
|
u32KeySts = FMC->KPKEYSTS;
|
||||||
|
|
||||||
|
if (!(u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk)) {
|
||||||
|
/* Security key lock failed! */
|
||||||
|
ret = -4;
|
||||||
|
} else if ((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ||
|
||||||
|
((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) {
|
||||||
|
/* CONFIG lock failed! */
|
||||||
|
ret = -5;
|
||||||
|
} else if (((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) {
|
||||||
|
/* KPMAX failed! */
|
||||||
|
ret = -7;
|
||||||
|
} else if (((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) {
|
||||||
|
/* KEMAX failed! */
|
||||||
|
ret = -8;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Execute security key comparison.
|
||||||
|
*
|
||||||
|
* @param[in] key Key 0~2 to be compared.
|
||||||
|
*
|
||||||
|
* @retval 0 Key matched.
|
||||||
|
* @retval -1 Forbidden. Times of key comparison mismatch reach the maximum count.
|
||||||
|
* @retval -2 Key mismatched.
|
||||||
|
* @retval -3 No security key lock. Key comparison is not required.
|
||||||
|
*
|
||||||
|
@ details Inpue a keys to compare with security keys
|
||||||
|
*/
|
||||||
|
int32_t FMC_SKey_Compare(uint32_t key[3])
|
||||||
|
{
|
||||||
|
uint32_t u32KeySts;
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (FMC->KPKEYSTS & FMC_KPKEYSTS_FORBID_Msk) {
|
||||||
|
/* FMC_SKey_Compare - FORBID! */
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (!(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYLOCK_Msk)) {
|
||||||
|
/* FMC_SKey_Compare - key is not locked! */
|
||||||
|
ret = -3;
|
||||||
|
}
|
||||||
|
|
||||||
|
if (ret == 0) {
|
||||||
|
FMC->KPKEY0 = key[0];
|
||||||
|
FMC->KPKEY1 = key[1];
|
||||||
|
FMC->KPKEY2 = key[2];
|
||||||
|
FMC->KPKEYTRG = FMC_KPKEYTRG_KPKEYGO_Msk | FMC_KPKEYTRG_TCEN_Msk;
|
||||||
|
|
||||||
|
while (FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
|
||||||
|
|
||||||
|
u32KeySts = FMC->KPKEYSTS;
|
||||||
|
|
||||||
|
if (!(u32KeySts & FMC_KPKEYSTS_KEYMATCH_Msk)) {
|
||||||
|
/* Key mismatched! */
|
||||||
|
ret = -2;
|
||||||
|
} else if (u32KeySts & FMC_KPKEYSTS_KEYLOCK_Msk) {
|
||||||
|
/* Key matched, but still be locked! */
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check the XOM is actived or not.
|
||||||
|
*
|
||||||
|
* @param[in] xom_num The xom number(0~3).
|
||||||
|
*
|
||||||
|
* @retval 1 XOM is actived.
|
||||||
|
* @retval 0 XOM is not actived.
|
||||||
|
* @retval -2 Invalid XOM number.
|
||||||
|
*
|
||||||
|
* @details To get specify XOMRn(n=0~3) active status
|
||||||
|
*/
|
||||||
|
int32_t FMC_Is_XOM_Actived(uint32_t xom_num)
|
||||||
|
{
|
||||||
|
int32_t ret = 0, STS = 0;
|
||||||
|
|
||||||
|
if (xom_num >= 4UL)
|
||||||
|
{
|
||||||
|
return -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
STS = (((FMC->XOMSTS) & 0xf) & (1 << xom_num)) >> xom_num;
|
||||||
|
|
||||||
|
return STS;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Config XOM Region
|
||||||
|
* @param[in] otp_num The OTP number.
|
||||||
|
* @param[in] low_word Low word of the 64-bits data.
|
||||||
|
* @param[in] high_word Low word of the 64-bits data.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval 1 XOM is has already actived.
|
||||||
|
* @retval -1 Program failed.
|
||||||
|
* @retval -2 Invalid XOM number.
|
||||||
|
*
|
||||||
|
* @details Program XOM base address and XOM size(page)
|
||||||
|
*/
|
||||||
|
int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page)
|
||||||
|
{
|
||||||
|
int32_t ret = 0;
|
||||||
|
|
||||||
|
if (xom_num >= 4UL)
|
||||||
|
{
|
||||||
|
ret = -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(ret==0)
|
||||||
|
{
|
||||||
|
ret = FMC_Is_XOM_Actived(xom_num);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(ret==0)
|
||||||
|
{
|
||||||
|
FMC_Write(FMC_XOM_BASE + xom_num*0x10, xom_base);
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk){
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(ret==0)
|
||||||
|
{
|
||||||
|
FMC_Write(FMC_XOM_BASE + xom_num*0x10 + +0x04, xom_page); //[2k~512k, 0~255]
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(ret==0)
|
||||||
|
{
|
||||||
|
FMC_Write(FMC_XOM_BASE + xom_num*0x10 + 0x08, 0); //Active
|
||||||
|
if (FMC->ISPSTS & FMC_ISPSTS_ISPFF_Msk) {
|
||||||
|
FMC->ISPSTS |= FMC_ISPSTS_ISPFF_Msk;
|
||||||
|
ret = -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Execute Erase XOM Region
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr XOMRn(n=0~3) region base address
|
||||||
|
*
|
||||||
|
* @return XOM erase success or not.
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Erase failed
|
||||||
|
* @retval -2 Invalid XOM number.
|
||||||
|
*
|
||||||
|
* @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM.
|
||||||
|
*/
|
||||||
|
int32_t FMC_Erase_XOM(uint32_t xom_num)
|
||||||
|
{
|
||||||
|
uint32_t u32Addr, u32Active;
|
||||||
|
|
||||||
|
if (xom_num >= 4UL)
|
||||||
|
{
|
||||||
|
return -2;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32Active = FMC_Is_XOM_Actived(xom_num);
|
||||||
|
|
||||||
|
|
||||||
|
if(u32Active)
|
||||||
|
{
|
||||||
|
//u32Addr = inpw(((&(FMC->XOMR0STS) + xom_num*4) & 0xFFFFFF00) >> 8);
|
||||||
|
u32Addr = (inpw(0x4000C0D0 + xom_num*4) & 0xFFFFFF00) >> 8;
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
FMC->ISPDAT = 0x55aa03;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
|
||||||
|
/* Check ISPFF flag to know whether erase OK or fail. */
|
||||||
|
if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group FMC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
||||||
|
|
@ -0,0 +1,626 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file fmc.h
|
||||||
|
* @version V3.0
|
||||||
|
* $Revision: 2 $
|
||||||
|
* $Date: 16/07/29 3:11p $
|
||||||
|
* @brief M2351 Series Flash Memory Controller(FMC) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __FMC_H__
|
||||||
|
#define __FMC_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FMC_Driver FMC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup FMC_EXPORTED_CONSTANTS FMC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Global constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define ISBEN 0
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define Base Address */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define FMC_APROM_BASE 0x00000000UL /*!< APROM Base Address */
|
||||||
|
#define FMC_APROM_END 0x00080000UL /*!< APROM end address */
|
||||||
|
#define FMC_APROM_BANK0_END (FMC_APROM_END/2UL) /*!< APROM bank0 end address */
|
||||||
|
#define FMC_LDROM_BASE 0x00100000UL /*!< LDROM Base Address */
|
||||||
|
#define FMC_LDROM_END 0x00101000UL /*!< LDROM end address */
|
||||||
|
#define FMC_XOM_BASE 0x00200000UL /*!< XOM Base Address */
|
||||||
|
#define FMC_CONFIG_BASE 0x00300000UL /*!< CONFIG Base Address */
|
||||||
|
#define FMC_KPROM_BASE 0x00311000UL /*!< Security ROM base address */
|
||||||
|
#define FMC_OTP_BASE 0x00310000UL /*!< OTP flash base address */
|
||||||
|
|
||||||
|
#define FMC_CONFIG0_ADDR (FMC_CONFIG_BASE) /*!< CONFIG 0 Address */
|
||||||
|
#define FMC_CONFIG1_ADDR (FMC_CONFIG_BASE + 0x4) /*!< CONFIG 1 Address */
|
||||||
|
#define FMC_CONFIG2_ADDR (FMC_CONFIG_BASE + 0x8) /*!< CONFIG 2 Address */
|
||||||
|
#define FMC_CONFIG3_ADDR (FMC_CONFIG_BASE + 0xC) /*!< CONFIG 3 Address */
|
||||||
|
|
||||||
|
#define FMC_APROM_SIZE FMC_APROM_END /*!< APROM Size */
|
||||||
|
#define FMC_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size */
|
||||||
|
#define FMC_LDROM_SIZE 0x1000UL /*!< LDROM Size (4 Kbytes) */
|
||||||
|
#define FMC_OTP_ENTRY_CNT 256UL /*!< OTP entry number */
|
||||||
|
|
||||||
|
#define FMC_FLASH_PAGE_SIZE 0x800 /*!< Flash Page Size (2048 Bytes) */
|
||||||
|
#define FMC_FLASH_BLOCK_SIZE 0x2000 /*!< Flash Page Size (8192 Bytes) */
|
||||||
|
#define FMC_FLASH_BANK_SIZE (FMC_APROM_SIZE/2UL) /*!< APROM Bank Size */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* ISPCTL constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define FMC_ISPCTL_BS_LDROM 0x1 /*!< ISPCTL setting to select to boot from LDROM */
|
||||||
|
#define FMC_ISPCTL_BS_APROM 0x0 /*!< ISPCTL setting to select to boot from APROM */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* ISPCMD constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define FMC_ISPCMD_READ 0x00 /*!< ISP Command: Read Flash */
|
||||||
|
#define FMC_ISPCMD_READ_UID 0x04 /*!< ISP Command: Read Unique ID */
|
||||||
|
#define FMC_ISPCMD_READ_ALL1 0x08 /*!< ISP Command: Read all-one result */
|
||||||
|
#define FMC_ISPCMD_READ_CID 0x0B /*!< ISP Command: Read Company ID */
|
||||||
|
#define FMC_ISPCMD_READ_DID 0x0C /*!< ISP Command: Read Device ID */
|
||||||
|
#define FMC_ISPCMD_CHECKSUM 0x0D /*!< ISP Command: Read Checksum */
|
||||||
|
#define FMC_ISPCMD_PROGRAM 0x21 /*!< ISP Command: 32-bit Program Flash */
|
||||||
|
#define FMC_ISPCMD_PAGE_ERASE 0x22 /*!< ISP Command: Page Erase Flash */
|
||||||
|
#define FMC_ISPCMD_BANK_ERASE 0x23 /*!< ISP Command: Erase Flash bank 0 or 1 */
|
||||||
|
#define FMC_ISPCMD_BLOCK_ERASE 0x25 /*!< ISP Command: Erase 4 pages alignment of APROM in bank 0 or 1 */
|
||||||
|
#define FMC_ISPCMD_MULTI_PROG 0x27 /*!< ISP Command: Flash Multi-Word Program */
|
||||||
|
#define FMC_ISPCMD_RUN_ALL1 0x28 /*!< ISP Command: Run all-one verification*/
|
||||||
|
#define FMC_ISPCMD_CAL_CHECKSUM 0x2D /*!< ISP Command: Run Check Calculation */
|
||||||
|
#define FMC_ISPCMD_VECMAP 0x2E /*!< ISP Command: Set vector mapping */
|
||||||
|
#define FMC_ISPCMD_READE_8 0x40 /*!< ISP Command: 64-bit read Flash */
|
||||||
|
#define FMC_ISPCMD_WRITE_8 0x61 /*!< ISP Command: 64-bit program Flash */
|
||||||
|
|
||||||
|
#define READ_ALLONE_YES 0xA11FFFFFUL /*!< Check-all-one result is all one. */
|
||||||
|
#define READ_ALLONE_NOT 0xA1100000UL /*!< Check-all-one result is not all one. */
|
||||||
|
#define READ_ALLONE_CMD_FAIL 0xFFFFFFFFUL /*!< Check-all-one command failed. */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group FMC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup FMC_EXPORTED_FUNCTIONS FMC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* FMC Macro Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @brief Enable ISP Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will set ISPEN bit of ISPCTL control register to enable ISP function.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_ENABLE_ISP() (FMC->ISPCTL |= FMC_ISPCTL_ISPEN_Msk) /*!< Enable ISP Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable ISP Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will clear ISPEN bit of ISPCTL control register to disable ISP function.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_DISABLE_ISP() (FMC->ISPCTL &= ~FMC_ISPCTL_ISPEN_Msk) /*!< Disable ISP Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable LDROM Update Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will set LDUEN bit of ISPCTL control register to enable LDROM update function.
|
||||||
|
* User needs to set LDUEN bit before they can update LDROM.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_ENABLE_LD_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_LDUEN_Msk) /*!< Enable LDROM Update Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable LDROM Update Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will set ISPEN bit of ISPCTL control register to disable LDROM update function.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_DISABLE_LD_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_LDUEN_Msk) /*!< Disable LDROM Update Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable User Configuration Update Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will set CFGUEN bit of ISPCTL control register to enable User Configuration update function.
|
||||||
|
* User needs to set CFGUEN bit before they can update User Configuration area.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_ENABLE_CFG_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_CFGUEN_Msk) /*!< Enable CONFIG Update Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable User Configuration Update Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will clear CFGUEN bit of ISPCTL control register to disable User Configuration update function.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_DISABLE_CFG_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_CFGUEN_Msk) /*!< Disable CONFIG Update Function */
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable APROM Update Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will set APUEN bit of ISPCTL control register to enable APROM update function.
|
||||||
|
* User needs to set APUEN bit before they can update APROM in APROM boot mode.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_ENABLE_AP_UPDATE() (FMC->ISPCTL |= FMC_ISPCTL_APUEN_Msk) /*!< Enable APROM Update Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable APROM Update Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will clear APUEN bit of ISPCTL control register to disable APROM update function.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_DISABLE_AP_UPDATE() (FMC->ISPCTL &= ~FMC_ISPCTL_APUEN_Msk) /*!< Disable APROM Update Function */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Next Booting Selection function
|
||||||
|
*
|
||||||
|
* @param[in] x Booting from APROM(0)/LDROM(1)
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will set MCU next booting from LDROM/APROM.
|
||||||
|
*
|
||||||
|
* @note When use this macro, the Boot Loader booting selection MBS(CONFIG0[5]) must be set.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_SELECT_NEXT_BOOT(x) (FMC->ISPCTL = (FMC->ISPCTL & ~FMC_ISPCTL_BS_Msk) | ((x) << FMC_ISPCTL_BS_Pos)) /*!< Select Next Booting, x = 0 or 1 */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get MCU Booting Status
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will get status of chip next booting from LDROM/APROM.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define FMC_GET_BOOT_STATUS() ((FMC->ISPCTL & FMC_ISPCTL_BS_Msk)?1:0) /*!< Get MCU Booting Status */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* inline functions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @brief Program 32-bit data into specified address of flash
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
|
||||||
|
* @param[in] u32Data 32-bit Data to program
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To program word data into Flash include APROM, LDROM, Data Flash, and CONFIG.
|
||||||
|
* The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE void FMC_Write(uint32_t u32Addr, uint32_t u32Data)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
FMC->ISPDAT = u32Data;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Program 64-bit data into specified address of flash
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
|
||||||
|
* @param[in] u32Data0 32-bit Data to program
|
||||||
|
* @param[in] u32Data1 32-bit Data to program
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To program two words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
|
||||||
|
* The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE void FMC_Write8(uint32_t u32Addr, uint32_t u32Data0, uint32_t u32Data1)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_WRITE_8;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
FMC->MPDAT0 = u32Data0;
|
||||||
|
FMC->MPDAT1 = u32Data1;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read 32-bit Data from specified address of flash
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
|
||||||
|
*
|
||||||
|
* @return The data of specified address
|
||||||
|
*
|
||||||
|
* @details To read word data from Flash include APROM, LDROM, Data Flash, and CONFIG.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_Read(uint32_t u32Addr)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
FMC->ISPDAT = 0;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
|
||||||
|
return FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Flash page erase
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr Flash address including APROM, LDROM, Data Flash, and CONFIG
|
||||||
|
*
|
||||||
|
* @details To do flash page erase. The target address could be APROM, LDROM, Data Flash, or CONFIG.
|
||||||
|
* The page size is 2048 bytes.
|
||||||
|
*
|
||||||
|
* @retval 0 Success
|
||||||
|
* @retval -1 Erase failed
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE int32_t FMC_Erase(uint32_t u32Addr)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
|
||||||
|
/* Check ISPFF flag to know whether erase OK or fail. */
|
||||||
|
if(FMC->ISPCTL & FMC_ISPCTL_ISPFF_Msk)
|
||||||
|
{
|
||||||
|
FMC->ISPCTL |= FMC_ISPCTL_ISPFF_Msk;
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Unique ID
|
||||||
|
*
|
||||||
|
* @param[in] u8Index UID index. 0 = UID[31:0], 1 = UID[63:32], 2 = UID[95:64]
|
||||||
|
*
|
||||||
|
* @return The 32-bit unique ID data of specified UID index.
|
||||||
|
*
|
||||||
|
* @details To read out 96-bit Unique ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_ReadUID(uint8_t u8Index)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ_UID;
|
||||||
|
FMC->ISPADDR = ((uint32_t)u8Index << 2);
|
||||||
|
FMC->ISPDAT = 0;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
|
||||||
|
return FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read company ID
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return The company ID (32-bit)
|
||||||
|
*
|
||||||
|
* @details The company ID of Nuvoton is fixed to be 0xDA
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_ReadCID(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ_CID; /* Set ISP Command Code */
|
||||||
|
FMC->ISPADDR = 0x0; /* Must keep 0x0 when read CID */
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif /* To make sure ISP/CPU be Synchronized */
|
||||||
|
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) ; /* Waiting for ISP Done */
|
||||||
|
|
||||||
|
return FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read product ID
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return The product ID (32-bit)
|
||||||
|
*
|
||||||
|
* @details This function is used to read product ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_ReadPID(void)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ_DID; /* Set ISP Command Code */
|
||||||
|
FMC->ISPADDR = 0x04; /* Must keep 0x4 when read PID */
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif /* To make sure ISP/CPU be Synchronized */
|
||||||
|
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
|
||||||
|
|
||||||
|
return FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To read UCID
|
||||||
|
*
|
||||||
|
* @param[in] u32Index Index of the UCID to read. u32Index must be 0, 1, 2, or 3.
|
||||||
|
*
|
||||||
|
* @return The UCID of specified index
|
||||||
|
*
|
||||||
|
* @details This function is used to read unique chip ID (UCID).
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_ReadUCID(uint32_t u32Index)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_READ_UID; /* Set ISP Command Code */
|
||||||
|
FMC->ISPADDR = (0x04 * u32Index) + 0x10; /* The UCID is at offset 0x10 with word alignment. */
|
||||||
|
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; /* Trigger to start ISP procedure */
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif /* To make sure ISP/CPU be Synchronized */
|
||||||
|
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk); /* Waiting for ISP Done */
|
||||||
|
|
||||||
|
return FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set vector mapping address
|
||||||
|
*
|
||||||
|
* @param[in] u32PageAddr The page address to remap to address 0x0. The address must be page alignment.
|
||||||
|
*
|
||||||
|
* @return To set VECMAP to remap specified page address to 0x0.
|
||||||
|
*
|
||||||
|
* @details This function is used to set VECMAP to map specified page to vector page (0x0).
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE void FMC_SetVectorPageAddr(uint32_t u32PageAddr)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_VECMAP; /* Set ISP Command Code */
|
||||||
|
FMC->ISPADDR = u32PageAddr; /* The address of specified page which will be map to address 0x0. It must be page alignment. */
|
||||||
|
FMC->ISPTRG = 0x1; /* Trigger to start ISP procedure */
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif /* To make sure ISP/CPU be Synchronized */
|
||||||
|
while(FMC->ISPTRG); /* Waiting for ISP Done */
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get current vector mapping address.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return The current vector mapping address.
|
||||||
|
*
|
||||||
|
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* VECMAP only valid when new IAP function is enabled. (CBS = 10'b or 00'b)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_GetVECMAP(void)
|
||||||
|
{
|
||||||
|
return (FMC->ISPSTS & FMC_ISPSTS_VECMAP_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Flash Checksum
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr Specific flash start address
|
||||||
|
* @param[in] i32Size Specific a size of Flash area
|
||||||
|
*
|
||||||
|
* @return A checksum value of a flash block.
|
||||||
|
*
|
||||||
|
* @details To get VECMAP value which is the page address for remapping to vector page (0x0).
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t FMC_GetCheckSum(uint32_t u32Addr, int32_t i32Size)
|
||||||
|
{
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_CAL_CHECKSUM;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
FMC->ISPDAT = (uint32_t)i32Size;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
#if ISBEN
|
||||||
|
__ISB();
|
||||||
|
#endif
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_CHECKSUM;
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
while(FMC->ISPTRG);
|
||||||
|
|
||||||
|
return FMC->ISPDAT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Program Multi-Word data into specified address of flash
|
||||||
|
*
|
||||||
|
* @param[in] u32Addr Flash address include APROM, LDROM, Data Flash, and CONFIG
|
||||||
|
* @param[in] pu32Buf A data pointer is point to a data buffer start address;
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To program multi-words data into Flash include APROM, LDROM, Data Flash, and CONFIG.
|
||||||
|
* The corresponding functions in CONFIG are listed in FMC section of Technical Reference Manual.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE void FMC_Write256(uint32_t u32Addr, uint32_t *pu32Buf)
|
||||||
|
{
|
||||||
|
int32_t i, idx;
|
||||||
|
volatile uint32_t *pu32IspData;
|
||||||
|
//int32_t i32Err;
|
||||||
|
|
||||||
|
//i32Err = 0;
|
||||||
|
idx = 0;
|
||||||
|
FMC->ISPCMD = FMC_ISPCMD_MULTI_PROG;
|
||||||
|
FMC->ISPADDR = u32Addr;
|
||||||
|
|
||||||
|
retrigger:
|
||||||
|
|
||||||
|
//if(i32Err)
|
||||||
|
// printf("idx=%d ISPADDR = 0x%08x\n",idx, FMC->ISPADDR);
|
||||||
|
|
||||||
|
FMC->MPDAT0 = pu32Buf[idx + 0];
|
||||||
|
FMC->MPDAT1 = pu32Buf[idx + 1];
|
||||||
|
FMC->MPDAT2 = pu32Buf[idx + 2];
|
||||||
|
FMC->MPDAT3 = pu32Buf[idx + 3];
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
FMC->ISPTRG = 0x1;
|
||||||
|
|
||||||
|
pu32IspData = &FMC->MPDAT0;
|
||||||
|
idx += 4;
|
||||||
|
|
||||||
|
for(i = idx; i < 256 / 4; i += 4) // Max data length is 256 bytes (256/4 words)
|
||||||
|
{
|
||||||
|
|
||||||
|
__set_PRIMASK(1); // Mask interrupt to avoid status check coherence error
|
||||||
|
do
|
||||||
|
{
|
||||||
|
if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
|
||||||
|
{
|
||||||
|
__set_PRIMASK(0);
|
||||||
|
//printf("%d %x\n", i, FMC->MPADDR);
|
||||||
|
FMC->ISPADDR = FMC->MPADDR & (~0xful);
|
||||||
|
idx = (FMC->ISPADDR - u32Addr) / 4;
|
||||||
|
//i32Err = -1;
|
||||||
|
goto retrigger;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
while(FMC->MPSTS & (3 << FMC_MPSTS_D0_Pos));
|
||||||
|
|
||||||
|
// Update new data for D0
|
||||||
|
pu32IspData[0] = pu32Buf[i ];
|
||||||
|
pu32IspData[1] = pu32Buf[i + 1];
|
||||||
|
|
||||||
|
do
|
||||||
|
{
|
||||||
|
if((FMC->MPSTS & FMC_MPSTS_MPBUSY_Msk) == 0)
|
||||||
|
{
|
||||||
|
__set_PRIMASK(0);
|
||||||
|
//printf("%d %x\n", i, FMC->MPADDR);
|
||||||
|
FMC->ISPADDR = FMC->MPADDR & (~0xful);
|
||||||
|
idx = (FMC->ISPADDR - u32Addr) / 4;
|
||||||
|
//i32Err = -1;
|
||||||
|
goto retrigger;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
while(FMC->MPSTS & (3 << FMC_MPSTS_D2_Pos));
|
||||||
|
|
||||||
|
// Update new data for D2
|
||||||
|
pu32IspData[2] = pu32Buf[i + 2];
|
||||||
|
pu32IspData[3] = pu32Buf[i + 3];
|
||||||
|
__set_PRIMASK(0);
|
||||||
|
}
|
||||||
|
|
||||||
|
while(FMC->ISPSTS & FMC_ISPSTS_ISPBUSY_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
void FMC_Open(void);
|
||||||
|
void FMC_Close(void);
|
||||||
|
void FMC_EnableAPUpdate(void);
|
||||||
|
void FMC_DisableAPUpdate(void);
|
||||||
|
void FMC_EnableConfigUpdate(void);
|
||||||
|
void FMC_DisableConfigUpdate(void);
|
||||||
|
void FMC_EnableLDUpdate(void);
|
||||||
|
void FMC_DisableLDUpdate(void);
|
||||||
|
int32_t FMC_ReadConfig(uint32_t *u32Config, uint32_t u32Count);
|
||||||
|
int32_t FMC_WriteConfig(uint32_t *u32Config, uint32_t u32Count);
|
||||||
|
void FMC_SetBootSource(int32_t i32BootSrc);
|
||||||
|
int32_t FMC_GetBootSource(void);
|
||||||
|
int32_t FMC_Erase_Bank(uint32_t u32BankAddr);
|
||||||
|
int32_t FMC_Erase_Block(uint32_t u32BlockAddr);
|
||||||
|
int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word);
|
||||||
|
int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);
|
||||||
|
int32_t FMC_Lock_OTP(uint32_t otp_num);
|
||||||
|
int32_t FMC_Is_OTP_Locked(uint32_t otp_num);
|
||||||
|
uint32_t FMC_CheckAllOne(uint32_t u32addr, uint32_t u32count);
|
||||||
|
uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count);
|
||||||
|
int32_t FMC_SKey_Setup(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM);
|
||||||
|
int32_t FMC_SKey_Compare(uint32_t key[3]);
|
||||||
|
int32_t FMC_Is_XOM_Actived(uint32_t xom_num);
|
||||||
|
int32_t FMC_Config_XOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page);
|
||||||
|
int32_t FMC_Erase_XOM(uint32_t xom_num);
|
||||||
|
/*@}*/ /* end of group FMC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group FMC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __FMC_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,172 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file gpio.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series General Purpose I/O (GPIO) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_Driver GPIO Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set GPIO operation mode
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
* @param[in] u32Mode Operation mode. It could be
|
||||||
|
* - \ref GPIO_MODE_INPUT
|
||||||
|
* - \ref GPIO_MODE_OUTPUT
|
||||||
|
* - \ref GPIO_MODE_OPEN_DRAIN
|
||||||
|
* - \ref GPIO_MODE_QUASI
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to set specified GPIO operation mode.
|
||||||
|
*/
|
||||||
|
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
for(i = 0; i < GPIO_PIN_MAX; i++)
|
||||||
|
{
|
||||||
|
if(u32PinMask & (1 << i))
|
||||||
|
{
|
||||||
|
port->MODE = (port->MODE & ~(0x3 << (i << 1))) | (u32Mode << (i << 1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable GPIO interrupt
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF and PG.
|
||||||
|
* @param[in] u32Pin The pin of specified GPIO port. \n
|
||||||
|
* It could be 0 ~ 15 for PA, PB, PC, PD and PF GPIO port. \n
|
||||||
|
* It could be 0 ~ 13 for PE GPIO port. \n
|
||||||
|
* It could be 1 ~ 5, 7 ~ 12 for PG GPIO port.
|
||||||
|
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be
|
||||||
|
* - \ref GPIO_INT_RISING
|
||||||
|
* - \ref GPIO_INT_FALLING
|
||||||
|
* - \ref GPIO_INT_BOTH_EDGE
|
||||||
|
* - \ref GPIO_INT_HIGH
|
||||||
|
* - \ref GPIO_INT_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable specified GPIO pin interrupt.
|
||||||
|
*/
|
||||||
|
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
|
||||||
|
{
|
||||||
|
/* Configure interrupt mode of specified pin */
|
||||||
|
port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
|
||||||
|
|
||||||
|
/* Enable interrupt function of specified pin */
|
||||||
|
port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable GPIO interrupt
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF and PG.
|
||||||
|
* @param[in] u32Pin The pin of specified GPIO port. \n
|
||||||
|
* It could be 0 ~ 15 for PA, PB, PC, PD and PF GPIO port. \n
|
||||||
|
* It could be 0 ~ 13 for PE GPIO port. \n
|
||||||
|
* It could be 1 ~ 5, 7 ~ 12 for PG GPIO port.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable specified GPIO pin interrupt.
|
||||||
|
*/
|
||||||
|
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
|
||||||
|
{
|
||||||
|
/* Configure interrupt mode of specified pin */
|
||||||
|
port->INTTYPE &= ~(1UL << u32Pin);
|
||||||
|
|
||||||
|
/* Disable interrupt function of specified pin */
|
||||||
|
port->INTEN &= ~((0x00010001UL) << u32Pin);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set GPIO slew rate control
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
* @param[in] u32Mode Slew rate mode. It could be
|
||||||
|
* - \ref GPIO_SLEWCTL_NORMAL (maximum 40 MHz at 2.7V)
|
||||||
|
* - \ref GPIO_SLEWCTL_HIGH (maximum 80 MHz at 2.7V)
|
||||||
|
* - \ref GPIO_SLEWCTL_FAST (maximum 100 MHz at 2.7V)
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to set specified GPIO operation mode.
|
||||||
|
*/
|
||||||
|
void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
for(i = 0ul; i < GPIO_PIN_MAX; i++)
|
||||||
|
{
|
||||||
|
if(u32PinMask & (1ul << i))
|
||||||
|
{
|
||||||
|
port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set GPIO Pull-up and Pull-down control
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
* @param[in] u32Mode The pin mode of specified GPIO pin. It could be
|
||||||
|
* - \ref GPIO_PUSEL_DISABLE
|
||||||
|
* - \ref GPIO_PUSEL_PULL_UP
|
||||||
|
* - \ref GPIO_PUSEL_PULL_DOWN
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the pin mode of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
for(i = 0ul; i < GPIO_PIN_MAX; i++)
|
||||||
|
{
|
||||||
|
if(u32PinMask & (1ul << i))
|
||||||
|
{
|
||||||
|
port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group GPIO_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,584 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file GPIO.h
|
||||||
|
* @version V3.0
|
||||||
|
* @brief M2351 series General Purpose I/O (GPIO) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __GPIO_H__
|
||||||
|
#define __GPIO_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_Driver GPIO Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_EXPORTED_CONSTANTS GPIO Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define GPIO_PIN_MAX 16 /*!< Specify Maximum Pins of Each GPIO Port */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* GPIO_MODE Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define GPIO_MODE_INPUT 0x0UL /*!< Input Mode */
|
||||||
|
#define GPIO_MODE_OUTPUT 0x1UL /*!< Output Mode */
|
||||||
|
#define GPIO_MODE_OPEN_DRAIN 0x2UL /*!< Open-Drain Mode */
|
||||||
|
#define GPIO_MODE_QUASI 0x3UL /*!< Quasi-bidirectional Mode */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* GPIO Interrupt Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define GPIO_INT_RISING 0x00010000UL /*!< Interrupt enable by Input Rising Edge */
|
||||||
|
#define GPIO_INT_FALLING 0x00000001UL /*!< Interrupt enable by Input Falling Edge */
|
||||||
|
#define GPIO_INT_BOTH_EDGE 0x00010001UL /*!< Interrupt enable by both Rising Edge and Falling Edge */
|
||||||
|
#define GPIO_INT_HIGH 0x01010000UL /*!< Interrupt enable by Level-High */
|
||||||
|
#define GPIO_INT_LOW 0x01000001UL /*!< Interrupt enable by Level-Level */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* GPIO_INTTYPE Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define GPIO_INTTYPE_EDGE 0UL /*!< GPIO_INTTYPE Setting for Edge Trigger Mode */
|
||||||
|
#define GPIO_INTTYPE_LEVEL 1UL /*!< GPIO_INTTYPE Setting for Edge Level Mode */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* GPIO Slew Rate Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for nornal Mode */
|
||||||
|
#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */
|
||||||
|
#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* GPIO Pull-up And Pull-down Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define GPIO_PUSEL_DISABLE 0x0UL /*!< GPIO PUSEL setting for Disable Mode */
|
||||||
|
#define GPIO_PUSEL_PULL_UP 0x1UL /*!< GPIO PUSEL setting for Pull-up Mode */
|
||||||
|
#define GPIO_PUSEL_PULL_DOWN 0x2UL /*!< GPIO PUSEL setting for Pull-down Mode */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* GPIO_DBCTL Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define GPIO_DBCTL_ICLK_ON 0x00000020UL /*!< GPIO_DBCTL setting for all IO pins edge detection circuit is always active after reset */
|
||||||
|
#define GPIO_DBCTL_ICLK_OFF 0x00000000UL /*!< GPIO_DBCTL setting for edge detection circuit is active only if IO pin corresponding GPIOx_IEN bit is set to 1 */
|
||||||
|
|
||||||
|
#define GPIO_DBCTL_DBCLKSRC_LIRC 0x00000010UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the internal 10 kHz */
|
||||||
|
#define GPIO_DBCTL_DBCLKSRC_HCLK 0x00000000UL /*!< GPIO_DBCTL setting for de-bounce counter clock source is the HCLK */
|
||||||
|
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_1 0x00000000UL /*!< GPIO_DBCTL setting for sampling cycle = 1 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_2 0x00000001UL /*!< GPIO_DBCTL setting for sampling cycle = 2 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_4 0x00000002UL /*!< GPIO_DBCTL setting for sampling cycle = 4 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_8 0x00000003UL /*!< GPIO_DBCTL setting for sampling cycle = 8 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_16 0x00000004UL /*!< GPIO_DBCTL setting for sampling cycle = 16 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_32 0x00000005UL /*!< GPIO_DBCTL setting for sampling cycle = 32 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_64 0x00000006UL /*!< GPIO_DBCTL setting for sampling cycle = 64 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_128 0x00000007UL /*!< GPIO_DBCTL setting for sampling cycle = 128 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_256 0x00000008UL /*!< GPIO_DBCTL setting for sampling cycle = 256 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_512 0x00000009UL /*!< GPIO_DBCTL setting for sampling cycle = 512 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_1024 0x0000000AUL /*!< GPIO_DBCTL setting for sampling cycle = 1024 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_2048 0x0000000BUL /*!< GPIO_DBCTL setting for sampling cycle = 2048 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_4096 0x0000000CUL /*!< GPIO_DBCTL setting for sampling cycle = 4096 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_8192 0x0000000DUL /*!< GPIO_DBCTL setting for sampling cycle = 8192 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_16384 0x0000000EUL /*!< GPIO_DBCTL setting for sampling cycle = 16384 clocks */
|
||||||
|
#define GPIO_DBCTL_DBCLKSEL_32768 0x0000000FUL /*!< GPIO_DBCTL setting for sampling cycle = 32768 clocks */
|
||||||
|
|
||||||
|
|
||||||
|
/** Define GPIO Pin Data Input/Output. It could be used to control each I/O pin by pin address mapping.
|
||||||
|
* Example 1:
|
||||||
|
*
|
||||||
|
* PA0 = 1;
|
||||||
|
*
|
||||||
|
* It is used to set PA.0 to high;
|
||||||
|
*
|
||||||
|
* Example 2:
|
||||||
|
*
|
||||||
|
* if (PA0)
|
||||||
|
* PA0 = 0;
|
||||||
|
*
|
||||||
|
* If PA.0 pin status is high, then set PA.0 data output to low.
|
||||||
|
*/
|
||||||
|
#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
|
||||||
|
#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
|
||||||
|
#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
|
||||||
|
#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
|
||||||
|
#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
|
||||||
|
#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
|
||||||
|
#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
|
||||||
|
#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
|
||||||
|
#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
|
||||||
|
#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
|
||||||
|
#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
|
||||||
|
#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
|
||||||
|
#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
|
||||||
|
#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
|
||||||
|
#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
|
||||||
|
#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
|
||||||
|
#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
|
||||||
|
#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
|
||||||
|
#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
|
||||||
|
#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
|
||||||
|
#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
|
||||||
|
#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
|
||||||
|
#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
|
||||||
|
#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
|
||||||
|
#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
|
||||||
|
#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
|
||||||
|
#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
|
||||||
|
#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
|
||||||
|
#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
|
||||||
|
#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
|
||||||
|
#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
|
||||||
|
#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
|
||||||
|
#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
|
||||||
|
#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
|
||||||
|
#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
|
||||||
|
#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
|
||||||
|
#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
|
||||||
|
#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
|
||||||
|
#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
|
||||||
|
#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
|
||||||
|
#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
|
||||||
|
#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
|
||||||
|
#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
|
||||||
|
#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
|
||||||
|
#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
|
||||||
|
#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
|
||||||
|
#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
|
||||||
|
#define PC14 GPIO_PIN_DATA(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
|
||||||
|
#define PC15 GPIO_PIN_DATA(2, 15) /*!< Specify PC.15 Pin Data Input/Output */
|
||||||
|
#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
|
||||||
|
#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
|
||||||
|
#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
|
||||||
|
#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
|
||||||
|
#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
|
||||||
|
#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
|
||||||
|
#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
|
||||||
|
#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
|
||||||
|
#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
|
||||||
|
#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
|
||||||
|
#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
|
||||||
|
#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
|
||||||
|
#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
|
||||||
|
#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
|
||||||
|
#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
|
||||||
|
#define PD15 GPIO_PIN_DATA(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
|
||||||
|
#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
|
||||||
|
#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
|
||||||
|
#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
|
||||||
|
#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
|
||||||
|
#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
|
||||||
|
#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
|
||||||
|
#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
|
||||||
|
#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
|
||||||
|
#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
|
||||||
|
#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
|
||||||
|
#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
|
||||||
|
#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
|
||||||
|
#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
|
||||||
|
#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
|
||||||
|
#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
|
||||||
|
#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
|
||||||
|
#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
|
||||||
|
#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
|
||||||
|
#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
|
||||||
|
#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
|
||||||
|
#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
|
||||||
|
#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
|
||||||
|
#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */
|
||||||
|
#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */
|
||||||
|
#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output */
|
||||||
|
#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output */
|
||||||
|
#define PF12 GPIO_PIN_DATA(5, 12) /*!< Specify PF.12 Pin Data Input/Output */
|
||||||
|
#define PF13 GPIO_PIN_DATA(5, 13) /*!< Specify PF.13 Pin Data Input/Output */
|
||||||
|
#define PF14 GPIO_PIN_DATA(5, 14) /*!< Specify PF.14 Pin Data Input/Output */
|
||||||
|
#define PF15 GPIO_PIN_DATA(5, 15) /*!< Specify PF.15 Pin Data Input/Output */
|
||||||
|
#define PG1 GPIO_PIN_DATA(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output */
|
||||||
|
#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */
|
||||||
|
#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */
|
||||||
|
#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */
|
||||||
|
#define PG5 GPIO_PIN_DATA(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output */
|
||||||
|
#define PG7 GPIO_PIN_DATA(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output */
|
||||||
|
#define PG8 GPIO_PIN_DATA(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output */
|
||||||
|
#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */
|
||||||
|
#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output */
|
||||||
|
#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output */
|
||||||
|
#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output */
|
||||||
|
|
||||||
|
/* GPIO bit definitions for non-secure */
|
||||||
|
#define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
|
||||||
|
#define PA0_NS GPIO_PIN_DATA_NS(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
|
||||||
|
#define PA1_NS GPIO_PIN_DATA_NS(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
|
||||||
|
#define PA2_NS GPIO_PIN_DATA_NS(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
|
||||||
|
#define PA3_NS GPIO_PIN_DATA_NS(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
|
||||||
|
#define PA4_NS GPIO_PIN_DATA_NS(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
|
||||||
|
#define PA5_NS GPIO_PIN_DATA_NS(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
|
||||||
|
#define PA6_NS GPIO_PIN_DATA_NS(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
|
||||||
|
#define PA7_NS GPIO_PIN_DATA_NS(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
|
||||||
|
#define PA8_NS GPIO_PIN_DATA_NS(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
|
||||||
|
#define PA9_NS GPIO_PIN_DATA_NS(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
|
||||||
|
#define PA10_NS GPIO_PIN_DATA_NS(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
|
||||||
|
#define PA11_NS GPIO_PIN_DATA_NS(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
|
||||||
|
#define PA12_NS GPIO_PIN_DATA_NS(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
|
||||||
|
#define PA13_NS GPIO_PIN_DATA_NS(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
|
||||||
|
#define PA14_NS GPIO_PIN_DATA_NS(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
|
||||||
|
#define PA15_NS GPIO_PIN_DATA_NS(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
|
||||||
|
#define PB0_NS GPIO_PIN_DATA_NS(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
|
||||||
|
#define PB1_NS GPIO_PIN_DATA_NS(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
|
||||||
|
#define PB2_NS GPIO_PIN_DATA_NS(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
|
||||||
|
#define PB3_NS GPIO_PIN_DATA_NS(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
|
||||||
|
#define PB4_NS GPIO_PIN_DATA_NS(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
|
||||||
|
#define PB5_NS GPIO_PIN_DATA_NS(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
|
||||||
|
#define PB6_NS GPIO_PIN_DATA_NS(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
|
||||||
|
#define PB7_NS GPIO_PIN_DATA_NS(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
|
||||||
|
#define PB8_NS GPIO_PIN_DATA_NS(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
|
||||||
|
#define PB9_NS GPIO_PIN_DATA_NS(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
|
||||||
|
#define PB10_NS GPIO_PIN_DATA_NS(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
|
||||||
|
#define PB11_NS GPIO_PIN_DATA_NS(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
|
||||||
|
#define PB12_NS GPIO_PIN_DATA_NS(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
|
||||||
|
#define PB13_NS GPIO_PIN_DATA_NS(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
|
||||||
|
#define PB14_NS GPIO_PIN_DATA_NS(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
|
||||||
|
#define PB15_NS GPIO_PIN_DATA_NS(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
|
||||||
|
#define PC0_NS GPIO_PIN_DATA_NS(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
|
||||||
|
#define PC1_NS GPIO_PIN_DATA_NS(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
|
||||||
|
#define PC2_NS GPIO_PIN_DATA_NS(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
|
||||||
|
#define PC3_NS GPIO_PIN_DATA_NS(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
|
||||||
|
#define PC4_NS GPIO_PIN_DATA_NS(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
|
||||||
|
#define PC5_NS GPIO_PIN_DATA_NS(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
|
||||||
|
#define PC6_NS GPIO_PIN_DATA_NS(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
|
||||||
|
#define PC7_NS GPIO_PIN_DATA_NS(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
|
||||||
|
#define PC8_NS GPIO_PIN_DATA_NS(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
|
||||||
|
#define PC9_NS GPIO_PIN_DATA_NS(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
|
||||||
|
#define PC10_NS GPIO_PIN_DATA_NS(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
|
||||||
|
#define PC11_NS GPIO_PIN_DATA_NS(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
|
||||||
|
#define PC12_NS GPIO_PIN_DATA_NS(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
|
||||||
|
#define PC13_NS GPIO_PIN_DATA_NS(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
|
||||||
|
#define PC14_NS GPIO_PIN_DATA_NS(2, 14) /*!< Specify PC.14 Pin Data Input/Output */
|
||||||
|
#define PC15_NS GPIO_PIN_DATA_NS(2, 15) /*!< Specify PC.15 Pin Data Input/Output */
|
||||||
|
#define PD0_NS GPIO_PIN_DATA_NS(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
|
||||||
|
#define PD1_NS GPIO_PIN_DATA_NS(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
|
||||||
|
#define PD2_NS GPIO_PIN_DATA_NS(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
|
||||||
|
#define PD3_NS GPIO_PIN_DATA_NS(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
|
||||||
|
#define PD4_NS GPIO_PIN_DATA_NS(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
|
||||||
|
#define PD5_NS GPIO_PIN_DATA_NS(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
|
||||||
|
#define PD6_NS GPIO_PIN_DATA_NS(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
|
||||||
|
#define PD7_NS GPIO_PIN_DATA_NS(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
|
||||||
|
#define PD8_NS GPIO_PIN_DATA_NS(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
|
||||||
|
#define PD9_NS GPIO_PIN_DATA_NS(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
|
||||||
|
#define PD10_NS GPIO_PIN_DATA_NS(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
|
||||||
|
#define PD11_NS GPIO_PIN_DATA_NS(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
|
||||||
|
#define PD12_NS GPIO_PIN_DATA_NS(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
|
||||||
|
#define PD13_NS GPIO_PIN_DATA_NS(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
|
||||||
|
#define PD14_NS GPIO_PIN_DATA_NS(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
|
||||||
|
#define PD15_NS GPIO_PIN_DATA_NS(3, 15) /*!< Specify PD.15 Pin Data Input/Output */
|
||||||
|
#define PE0_NS GPIO_PIN_DATA_NS(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
|
||||||
|
#define PE1_NS GPIO_PIN_DATA_NS(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
|
||||||
|
#define PE2_NS GPIO_PIN_DATA_NS(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
|
||||||
|
#define PE3_NS GPIO_PIN_DATA_NS(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
|
||||||
|
#define PE4_NS GPIO_PIN_DATA_NS(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
|
||||||
|
#define PE5_NS GPIO_PIN_DATA_NS(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
|
||||||
|
#define PE6_NS GPIO_PIN_DATA_NS(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
|
||||||
|
#define PE7_NS GPIO_PIN_DATA_NS(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
|
||||||
|
#define PE8_NS GPIO_PIN_DATA_NS(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
|
||||||
|
#define PE9_NS GPIO_PIN_DATA_NS(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
|
||||||
|
#define PE10_NS GPIO_PIN_DATA_NS(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
|
||||||
|
#define PE11_NS GPIO_PIN_DATA_NS(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
|
||||||
|
#define PE12_NS GPIO_PIN_DATA_NS(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
|
||||||
|
#define PE13_NS GPIO_PIN_DATA_NS(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
|
||||||
|
#define PF0_NS GPIO_PIN_DATA_NS(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
|
||||||
|
#define PF1_NS GPIO_PIN_DATA_NS(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
|
||||||
|
#define PF2_NS GPIO_PIN_DATA_NS(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
|
||||||
|
#define PF3_NS GPIO_PIN_DATA_NS(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
|
||||||
|
#define PF4_NS GPIO_PIN_DATA_NS(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
|
||||||
|
#define PF5_NS GPIO_PIN_DATA_NS(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
|
||||||
|
#define PF6_NS GPIO_PIN_DATA_NS(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
|
||||||
|
#define PF7_NS GPIO_PIN_DATA_NS(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
|
||||||
|
#define PF8_NS GPIO_PIN_DATA_NS(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */
|
||||||
|
#define PF9_NS GPIO_PIN_DATA_NS(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */
|
||||||
|
#define PF10_NS GPIO_PIN_DATA_NS(5, 10) /*!< Specify PF.10 Pin Data Input/Output */
|
||||||
|
#define PF11_NS GPIO_PIN_DATA_NS(5, 11) /*!< Specify PF.11 Pin Data Input/Output */
|
||||||
|
#define PF12_NS GPIO_PIN_DATA_NS(5, 12) /*!< Specify PF.12 Pin Data Input/Output */
|
||||||
|
#define PF13_NS GPIO_PIN_DATA_NS(5, 13) /*!< Specify PF.13 Pin Data Input/Output */
|
||||||
|
#define PF14_NS GPIO_PIN_DATA_NS(5, 14) /*!< Specify PF.14 Pin Data Input/Output */
|
||||||
|
#define PF15_NS GPIO_PIN_DATA_NS(5, 15) /*!< Specify PF.15 Pin Data Input/Output */
|
||||||
|
#define PG1_NS GPIO_PIN_DATA_NS(6, 1 ) /*!< Specify PG.1 Pin Data Input/Output */
|
||||||
|
#define PG2_NS GPIO_PIN_DATA_NS(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */
|
||||||
|
#define PG3_NS GPIO_PIN_DATA_NS(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */
|
||||||
|
#define PG4_NS GPIO_PIN_DATA_NS(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */
|
||||||
|
#define PG5_NS GPIO_PIN_DATA_NS(6, 5 ) /*!< Specify PG.5 Pin Data Input/Output */
|
||||||
|
#define PG7_NS GPIO_PIN_DATA_NS(6, 7 ) /*!< Specify PG.7 Pin Data Input/Output */
|
||||||
|
#define PG8_NS GPIO_PIN_DATA_NS(6, 8 ) /*!< Specify PG.8 Pin Data Input/Output */
|
||||||
|
#define PG9_NS GPIO_PIN_DATA_NS(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */
|
||||||
|
#define PG10_NS GPIO_PIN_DATA_NS(6, 10) /*!< Specify PG.10 Pin Data Input/Output */
|
||||||
|
#define PG11_NS GPIO_PIN_DATA_NS(6, 11) /*!< Specify PG.11 Pin Data Input/Output */
|
||||||
|
#define PG12_NS GPIO_PIN_DATA_NS(6, 12) /*!< Specify PG.12 Pin Data Input/Output */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup GPIO_EXPORTED_FUNCTIONS GPIO Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear GPIO Pin Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear the interrupt status of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_CLR_INT_FLAG(port, u32PinMask) ((port)->INTSRC = (u32PinMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Pin De-bounce Function
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Disable the interrupt de-bounce function of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_DISABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN &= ~(u32PinMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Pin De-bounce Function
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable the interrupt de-bounce function of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_ENABLE_DEBOUNCE(port, u32PinMask) ((port)->DBEN |= (u32PinMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I/O Digital Input Path
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Disable I/O digital input path of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_DISABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF |= ((u32PinMask)<<16))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I/O Digital Input Path
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable I/O digital input path of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_ENABLE_DIGITAL_PATH(port, u32PinMask) ((port)->DINOFF &= ~((u32PinMask)<<16))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I/O DOUT mask
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Disable I/O DOUT mask of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_DISABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK &= ~(u32PinMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I/O DOUT mask
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable I/O DOUT mask of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_ENABLE_DOUT_MASK(port, u32PinMask) ((port)->DATMSK |= (u32PinMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get GPIO Pin Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32PinMask The single or multiple pins of specified GPIO port. \n
|
||||||
|
* It could be BIT0 ~ BIT15 for PA, PB, PC, PD and PF. \n
|
||||||
|
* It could be BIT0 ~ BIT13 for PE. \n
|
||||||
|
* It could be BIT1 ~ BIT5, BIT7 ~ BIT12 for PG.
|
||||||
|
*
|
||||||
|
* @retval 0 No interrupt at specified GPIO pin
|
||||||
|
* @retval 1 The specified GPIO pin generate an interrupt
|
||||||
|
*
|
||||||
|
* @details Get the interrupt status of specified GPIO pin.
|
||||||
|
*/
|
||||||
|
#define GPIO_GET_INT_FLAG(port, u32PinMask) ((port)->INTSRC & (u32PinMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set De-bounce Sampling Cycle Time
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32ClkSrc The de-bounce counter clock source. It could be GPIO_DBCTL_DBCLKSRC_HCLK or GPIO_DBCTL_DBCLKSRC_LIRC.
|
||||||
|
* @param[in] u32ClkSel The de-bounce sampling cycle selection. It could be
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_1
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_2
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_4
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_8
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_16
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_32
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_64
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_128
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_256
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_512
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_1024
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_2048
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_4096
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_8192
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_16384
|
||||||
|
* - \ref GPIO_DBCTL_DBCLKSEL_32768
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the interrupt de-bounce sampling cycle time based on the debounce counter clock source. \n
|
||||||
|
* Example: _GPIO_SET_DEBOUNCE_TIME(PA, GPIO_DBCTL_DBCLKSRC_LIRC, GPIO_DBCTL_DBCLKSEL_4). \n
|
||||||
|
* It's meaning the De-debounce counter clock source is internal 10 KHz and sampling cycle selection is 4. \n
|
||||||
|
* Then the target de-bounce sampling cycle time is (4)*(1/(10*1000)) s = 4*0.0001 s = 400 us,
|
||||||
|
* and system will sampling interrupt input once per 400 us.
|
||||||
|
*/
|
||||||
|
#define GPIO_SET_DEBOUNCE_TIME(port, u32ClkSrc, u32ClkSel) ((port)->DBCTL = (GPIO_DBCTL_ICLKON_Msk | (u32ClkSrc) | (u32ClkSel)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get GPIO Port IN Data
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
*
|
||||||
|
* @return The specified port data
|
||||||
|
*
|
||||||
|
* @details Get the PIN register of specified GPIO port.
|
||||||
|
*/
|
||||||
|
#define GPIO_GET_IN_DATA(port) ((port)->PIN)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set GPIO Port OUT Data
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF or PG.
|
||||||
|
* @param[in] u32Data GPIO port data.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the Data into specified GPIO port.
|
||||||
|
*/
|
||||||
|
#define GPIO_SET_OUT_DATA(port, u32Data) ((port)->DOUT = (u32Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Toggle Specified GPIO pin
|
||||||
|
*
|
||||||
|
* @param[in] u32Pin Pxy
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Toggle the specified GPIO pint.
|
||||||
|
*/
|
||||||
|
#define GPIO_TOGGLE(u32Pin) ((u32Pin) ^= 1)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable External GPIO interrupt
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF and PG.
|
||||||
|
* @param[in] u32Pin The pin of specified GPIO port. \n
|
||||||
|
* It could be 0 ~ 15 for PA, PB, PC, PD and PF GPIO port. \n
|
||||||
|
* It could be 0 ~ 13 for PE GPIO port. \n
|
||||||
|
* It could be 1 ~ 5, 7 ~ 12 for PG GPIO port.
|
||||||
|
* @param[in] u32IntAttribs The interrupt attribute of specified GPIO pin. It could be
|
||||||
|
* - \ref GPIO_INT_RISING
|
||||||
|
* - \ref GPIO_INT_FALLING
|
||||||
|
* - \ref GPIO_INT_BOTH_EDGE
|
||||||
|
* - \ref GPIO_INT_HIGH
|
||||||
|
* - \ref GPIO_INT_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable specified GPIO pin interrupt.
|
||||||
|
*/
|
||||||
|
#define GPIO_EnableEINT GPIO_EnableInt
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable External GPIO interrupt
|
||||||
|
*
|
||||||
|
* @param[in] port GPIO port. It could be PA, PB, PC, PD, PE, PF and PG.
|
||||||
|
* @param[in] u32Pin The pin of specified GPIO port. \n
|
||||||
|
* It could be 0 ~ 15 for PA, PB, PC, PD and PF GPIO port. \n
|
||||||
|
* It could be 0 ~ 13 for PE GPIO port. \n
|
||||||
|
* It could be 1 ~ 5, 7 ~ 12 for PG GPIO port.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable specified GPIO pin interrupt.
|
||||||
|
*/
|
||||||
|
#define GPIO_DisableEINT GPIO_DisableInt
|
||||||
|
|
||||||
|
|
||||||
|
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
|
||||||
|
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs);
|
||||||
|
void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin);
|
||||||
|
void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
|
||||||
|
void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group GPIO_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group GPIO_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__GPIO_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,89 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file hdiv.h
|
||||||
|
* @version V3.0
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/07/07 7:50p $
|
||||||
|
* @brief M0564 series Hardware Divider(HDIV) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __HDIV_H__
|
||||||
|
#define __HDIV_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup HDIV_Driver HDIV Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup HDIV_EXPORTED_FUNCTIONS HDIV Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Division function to calculate (x/y)
|
||||||
|
*
|
||||||
|
* @param[in] x the dividend of the division
|
||||||
|
* @param[in] y the divisor of the division
|
||||||
|
*
|
||||||
|
* @return The result of (x/y)
|
||||||
|
*
|
||||||
|
* @details This is a division function to calculate x/y
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE int32_t HDIV_Div(int32_t x, int16_t y)
|
||||||
|
{
|
||||||
|
uint32_t *p32;
|
||||||
|
|
||||||
|
p32 = (uint32_t *)HDIV_BASE;
|
||||||
|
*p32++ = (uint32_t)x;
|
||||||
|
*p32++ = (uint32_t)y;
|
||||||
|
return (int32_t) * p32;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To calculate the remainder of x/y, i.e., the result of x mod y.
|
||||||
|
*
|
||||||
|
* @param[in] x the dividend of the division
|
||||||
|
* @param[in] y the divisor of the division
|
||||||
|
*
|
||||||
|
* @return The remainder of (x/y)
|
||||||
|
*
|
||||||
|
* @details This function is used to calculate the remainder of x/y.
|
||||||
|
*/
|
||||||
|
static __INLINE int16_t HDIV_Mod(int32_t x, int16_t y)
|
||||||
|
{
|
||||||
|
uint32_t *p32;
|
||||||
|
|
||||||
|
p32 = (uint32_t *)HDIV_BASE;
|
||||||
|
*p32++ = (uint32_t)x;
|
||||||
|
*p32++ = (uint32_t)y;
|
||||||
|
return (int16_t)p32[1];
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group HDIV_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group HDIV_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__HDIV_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,515 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file i2c.h
|
||||||
|
* @version V3.0
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/07/07 7:50p $
|
||||||
|
* @brief M2351 series I2C Serial Interface Controller(I2C) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __I2C_H__
|
||||||
|
#define __I2C_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C_Driver I2C Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2C_EXPORTED_CONSTANTS I2C Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* I2C_CTL constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define I2C_CTL_STA_SI 0x28UL /*!< I2C_CTL setting for I2C control bits. It would set STA and SI bits */
|
||||||
|
#define I2C_CTL_STA_SI_AA 0x2CUL /*!< I2C_CTL setting for I2C control bits. It would set STA, SI and AA bits */
|
||||||
|
#define I2C_CTL_STO_SI 0x18UL /*!< I2C_CTL setting for I2C control bits. It would set STO and SI bits */
|
||||||
|
#define I2C_CTL_STO_SI_AA 0x1CUL /*!< I2C_CTL setting for I2C control bits. It would set STO, SI and AA bits */
|
||||||
|
#define I2C_CTL_SI 0x08UL /*!< I2C_CTL setting for I2C control bits. It would set SI bit */
|
||||||
|
#define I2C_CTL_SI_AA 0x0CUL /*!< I2C_CTL setting for I2C control bits. It would set SI and AA bits */
|
||||||
|
#define I2C_CTL_STA 0x20UL /*!< I2C_CTL setting for I2C control bits. It would set STA bit */
|
||||||
|
#define I2C_CTL_STO 0x10UL /*!< I2C_CTL setting for I2C control bits. It would set STO bit */
|
||||||
|
#define I2C_CTL_AA 0x04UL /*!< I2C_CTL setting for I2C control bits. It would set AA bit */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* I2C GCMode constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define I2C_GCMODE_ENABLE 1 /*!< Enable I2C GC Mode */
|
||||||
|
#define I2C_GCMODE_DISABLE 0 /*!< Disable I2C GC Mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* I2C SMBUS constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define I2C_SMBH_ENABLE 1 /*!< Enable SMBus Host Mode enable */
|
||||||
|
#define I2C_SMBD_ENABLE 0 /*!< Enable SMBus Device Mode enable */
|
||||||
|
#define I2C_PECTX_ENABLE 1 /*!< Enable SMBus Packet Error Check Transmit function */
|
||||||
|
#define I2C_PECTX_DISABLE 0 /*!< Disable SMBus Packet Error Check Transmit function */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2C_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup I2C_EXPORTED_FUNCTIONS I2C Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief The macro is used to set I2C bus condition at One Time
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
* @param[in] u8Ctrl A byte writes to I2C control register
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set I2C_CTL register to control I2C bus conditions of START, STOP, SI, ACK.
|
||||||
|
*/
|
||||||
|
#define I2C_SET_CONTROL_REG(i2c, u8Ctrl) ((i2c)->CTL = ((i2c)->CTL & ~0x3c) | (u8Ctrl))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief The macro is used to set START condition of I2C Bus
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the I2C bus START condition in I2C_CTL register.
|
||||||
|
*/
|
||||||
|
#define I2C_START(i2c) ((i2c)->CTL = ((i2c)->CTL | I2C_CTL_SI_Msk) | I2C_CTL_STA_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief The macro is used to set STOP condition of I2C Bus
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the I2C bus STOP condition in I2C_CTL register.
|
||||||
|
*/
|
||||||
|
#define I2C_STOP(i2c) ((i2c)->CTL = ((i2c)->CTL | I2C_CTL_SI_Msk) | I2C_CTL_STO_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief The macro is used to wait I2C bus status get ready
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details When a new status is presented of I2C bus, the SI flag will be set in I2C_CTL register.
|
||||||
|
*/
|
||||||
|
#define I2C_WAIT_READY(i2c) while(!((i2c)->CTL & I2C_CTL_SI_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief The macro is used to Read I2C Bus Data Register
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return A byte of I2C data register
|
||||||
|
*
|
||||||
|
* @details I2C controller read data from bus and save it in I2CDAT register.
|
||||||
|
*/
|
||||||
|
#define I2C_GET_DATA(i2c) ((i2c)->DAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write a Data to I2C Data Register
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
* @param[in] u8Data A byte that writes to data register
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details When write a data to I2C_DAT register, the I2C controller will shift it to I2C bus.
|
||||||
|
*/
|
||||||
|
#define I2C_SET_DATA(i2c, u8Data) ((i2c)->DAT = (u8Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get I2C Bus status code
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return I2C status code
|
||||||
|
*
|
||||||
|
* @details To get this status code to monitor I2C bus event.
|
||||||
|
*/
|
||||||
|
#define I2C_GET_STATUS(i2c) ((i2c)->STATUS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Time-out flag from I2C Bus
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @retval 0 I2C Bus time-out is not happened
|
||||||
|
* @retval 1 I2C Bus time-out is happened
|
||||||
|
*
|
||||||
|
* @details When I2C bus occurs time-out event, the time-out flag will be set.
|
||||||
|
*/
|
||||||
|
#define I2C_GET_TIMEOUT_FLAG(i2c) ( ((i2c)->TOCTL & I2C_TOCTL_TOIF_Msk) == I2C_TOCTL_TOIF_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To get wake-up flag from I2C Bus
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @retval 0 Chip is not woken-up from power-down mode
|
||||||
|
* @retval 1 Chip is woken-up from power-down mode
|
||||||
|
*
|
||||||
|
* @details I2C bus occurs wake-up event, wake-up flag will be set.
|
||||||
|
*/
|
||||||
|
#define I2C_GET_WAKEUP_FLAG(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKIF_Msk) == I2C_WKSTS_WKIF_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To clear wake-up flag
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details If wake-up flag is set, use this macro to clear it.
|
||||||
|
*/
|
||||||
|
#define I2C_CLEAR_WAKEUP_FLAG(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To get wake-up address frame ACK done flag from I2C Bus
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @retval 0 The ACK bit cycle of address match frame is not done
|
||||||
|
* @retval 1 The ACK bit cycle of address match frame is done in power-down
|
||||||
|
*
|
||||||
|
* @details I2C bus occurs wake-up event and address frame ACK is done, this flag will be set.
|
||||||
|
*
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2C_GET_WAKEUP_DONE(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WKAKDONE_Msk) == I2C_WKSTS_WKAKDONE_Msk ? 1 : 0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To clear address frame ACK done flag
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details If wake-up done is set, use this macro to clear it.
|
||||||
|
*
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2C_CLEAR_WAKEUP_DONE(i2c) ((i2c)->WKSTS = I2C_WKSTS_WKAKDONE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To get read/write status bit in address wakeup frame
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @retval 0 Write command be record on the address match wakeup frame
|
||||||
|
* @retval 1 Read command be record on the address match wakeup frame.
|
||||||
|
*
|
||||||
|
* @details I2C bus occurs wake-up event and address frame is received, this bit will record read/write status.
|
||||||
|
*
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2C_GET_WAKEUP_WR_STATUS(i2c) ( ((i2c)->WKSTS & I2C_WKSTS_WRSTSWK_Msk) == I2C_WKSTS_WRSTSWK_Msk ? 1 : 0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To get SMBus Status
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return SMBus status
|
||||||
|
*
|
||||||
|
* @details To get the Bus Management status of I2C_BUSSTS register
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_GET_STATUS(i2c) ((i2c)->BUSSTS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get SMBus CRC value
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return Packet error check byte value
|
||||||
|
*
|
||||||
|
* @details The CRC check value after a transmission or a reception by count by using CRC8
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_GET_PEC_VALUE(i2c) ((i2c)->PKTCRC)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SMBus Bytes number of Transmission or reception
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
* @param[in] u32PktSize Transmit / Receive bytes
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The transmission or receive byte number in one transaction when PECEN is set. The maximum is 255 bytes.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_SET_PACKET_BYTE_COUNT(i2c, u32PktSize) ((i2c)->PKTSIZE = (u32PktSize))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SMBus Alert function
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin will pull lo, and reply ACK when get ARP from host
|
||||||
|
* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is set, the Alert pin is supported to receive alert state(Lo trigger)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_ENABLE_ALERT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ALERTEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SMBus Alert pin function
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Device Mode(BMHEN=0): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin will pull hi, and reply NACK when get ARP from host
|
||||||
|
* Host Mode(BMHEN=1): If ALERTEN(I2C_BUSCTL[4]) is clear, the Alert pin is not supported to receive alert state(Lo trigger)
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_DISABLE_ALERT(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ALERTEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SMBus SUSCON pin is output mode
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output mode.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_SET_SUSCON_OUT(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SMBus SUSCON pin is input mode
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is input mode.
|
||||||
|
*
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_SET_SUSCON_IN(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SMBus SUSCON pin output high state
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output hi state.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_SET_SUSCON_HIGH(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_SCTLOSTS_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SMBus SUSCON pin output low state
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function to set SUSCON(I2C_BUSCTL[6]) pin is output lo state.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_SET_SUSCON_LOW(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_SCTLOSTS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SMBus Acknowledge control by manual
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The 9th bit can response the ACK or NACK according the received data by user. When the byte is received, SCLK line stretching to low between the 8th and 9th SCLK pulse.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_ACK_MANUAL(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKMEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SMBus Acknowledge control by manual
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Disable acknowledge response control by user.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_ACK_AUTO(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKMEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SMBus Acknowledge manual interrupt
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_9THBIT_INT_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_ACKM9SI_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SMBus Acknowledge manual interrupt
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable SMBUS acknowledge manual interrupt on the 9th clock cycle when SMBUS=1 and ACKMEN=1
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_9THBIT_INT_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_ACKM9SI_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SMBus PEC clear at REPEAT START
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the condition of REAEAT START can clear the PEC calculation.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_RST_PEC_AT_START_ENABLE(i2c) ((i2c)->BUSCTL |= I2C_BUSCTL_PECCLR_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SMBus PEC clear at Repeat START
|
||||||
|
*
|
||||||
|
* @param[in] i2c Specify I2C port
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable the condition of Repeat START can clear the PEC calculation.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define I2C_SMBUS_RST_PEC_AT_START_DISABLE(i2c) ((i2c)->BUSCTL &= ~I2C_BUSCTL_PECCLR_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable RX PDMA function.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set RXPDMAEN bit of I2C_CTL1 register to enable RX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define I2C_ENABLE_RX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_RXPDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable TX PDMA function.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set TXPDMAEN bit of I2C_CTL1 register to enable TX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define I2C_ENABLE_TX_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_TXPDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable RX PDMA transfer.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear RXPDMAEN bit of I2C_CTL1 register to disable RX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define I2C_DISABLE_RX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_RXPDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable TX PDMA transfer.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear TXPDMAEN bit of I2C_CTL1 register to disable TX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define I2C_DISABLE_TX_PDMA(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_TXPDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable PDMA stretch function.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details Enable this function is to stretch bus by hardware after PDMA transfer is done if SI is not cleared.
|
||||||
|
*/
|
||||||
|
#define I2C_ENABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMASTR_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable PDMA stretch function.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details I2C wil send STOP after PDMA transfers done automatically.
|
||||||
|
*/
|
||||||
|
#define I2C_DISABLE_PDMA_STRETCH(i2c) ((i2c)->CTL1 &= ~I2C_CTL1_PDMASTR_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset PDMA function.
|
||||||
|
* @param[in] i2c The pointer of the specified I2C module.
|
||||||
|
* @return None.
|
||||||
|
* @details I2C PDMA engine will be reset after this function is called.
|
||||||
|
*/
|
||||||
|
#define I2C_DISABLE_RST_PDMA(i2c) ((i2c)->CTL1 |= I2C_CTL1_PDMARST_Msk)
|
||||||
|
|
||||||
|
void I2C_ClearTimeoutFlag(I2C_T *i2c);
|
||||||
|
void I2C_Close(I2C_T *i2c);
|
||||||
|
void I2C_Trigger(I2C_T *i2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Si, uint8_t u8Ack);
|
||||||
|
void I2C_DisableInt(I2C_T *i2c);
|
||||||
|
void I2C_EnableInt(I2C_T *i2c);
|
||||||
|
uint32_t I2C_GetBusClockFreq(I2C_T *i2c);
|
||||||
|
uint32_t I2C_GetIntFlag(I2C_T *i2c);
|
||||||
|
uint32_t I2C_GetStatus(I2C_T *i2c);
|
||||||
|
uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock);
|
||||||
|
uint8_t I2C_GetData(I2C_T *i2c);
|
||||||
|
void I2C_SetSlaveAddr(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddr, uint8_t u8GCMode);
|
||||||
|
void I2C_SetSlaveAddrMask(I2C_T *i2c, uint8_t u8SlaveNo, uint8_t u8SlaveAddrMask);
|
||||||
|
uint32_t I2C_SetBusClockFreq(I2C_T *i2c, uint32_t u32BusClock);
|
||||||
|
void I2C_EnableTimeout(I2C_T *i2c, uint8_t u8LongTimeout);
|
||||||
|
void I2C_DisableTimeout(I2C_T *i2c);
|
||||||
|
void I2C_EnableWakeup(I2C_T *i2c);
|
||||||
|
void I2C_DisableWakeup(I2C_T *i2c);
|
||||||
|
void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
|
||||||
|
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, const uint8_t data);
|
||||||
|
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, const uint8_t *data, uint32_t u32wLen);
|
||||||
|
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t data);
|
||||||
|
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t *data, uint32_t u32wLen);
|
||||||
|
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t data);
|
||||||
|
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t *data, uint32_t u32wLen);
|
||||||
|
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
|
||||||
|
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||||
|
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
|
||||||
|
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||||
|
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
|
||||||
|
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||||
|
uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
|
||||||
|
void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
|
||||||
|
void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
|
||||||
|
void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
|
||||||
|
void I2C_SMBusClose(I2C_T *i2c);
|
||||||
|
void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
|
||||||
|
uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
|
||||||
|
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk);
|
||||||
|
void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
|
||||||
|
void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2C_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2C_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__I2C_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,249 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file i2s.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series I2S driver source file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_Driver I2S Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function is used to get I2S source clock frequency.
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @return I2S source clock frequency (Hz).
|
||||||
|
* @details Return the source clock frequency according to the setting of I2S_S (CLKSEL2[1:0]).
|
||||||
|
*/
|
||||||
|
static uint32_t I2S_GetSourceClockFreq(I2S_T *i2s)
|
||||||
|
{
|
||||||
|
uint32_t u32Freq, u32ClkSrcSel;
|
||||||
|
|
||||||
|
u32ClkSrcSel = CLK_GetModuleClockSource(I2S0_MODULE);
|
||||||
|
|
||||||
|
switch(u32ClkSrcSel << CLK_CLKSEL3_I2S0SEL_Pos)
|
||||||
|
{
|
||||||
|
case CLK_CLKSEL3_I2S0SEL_HXT:
|
||||||
|
u32Freq = __HXT;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CLK_CLKSEL3_I2S0SEL_PLL:
|
||||||
|
u32Freq = CLK_GetPLLClockFreq();
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CLK_CLKSEL3_I2S0SEL_HIRC:
|
||||||
|
u32Freq = __HIRC;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case CLK_CLKSEL3_I2S0SEL_PCLK0:
|
||||||
|
u32Freq = CLK_GetPCLK0Freq();
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
u32Freq = __HXT;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Freq;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function configures some parameters of I2S interface for general purpose use.
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @param[in] u32MasterSlave I2S operation mode. Valid values are:
|
||||||
|
* - \ref I2S_MODE_MASTER
|
||||||
|
* - \ref I2S_MODE_SLAVE
|
||||||
|
* @param[in] u32SampleRate Sample rate
|
||||||
|
* @param[in] u32WordWidth Data length. Valid values are:
|
||||||
|
* - \ref I2S_DATABIT_8
|
||||||
|
* - \ref I2S_DATABIT_16
|
||||||
|
* - \ref I2S_DATABIT_24
|
||||||
|
* - \ref I2S_DATABIT_32
|
||||||
|
* @param[in] u32Channels Audio format. Valid values are:
|
||||||
|
* - \ref I2S_MONO
|
||||||
|
* - \ref I2S_STEREO
|
||||||
|
* @param[in] u32DataFormat Data format. Valid values are:
|
||||||
|
* - \ref I2S_FORMAT_I2S
|
||||||
|
* - \ref I2S_FORMAT_MSB
|
||||||
|
* @return Real sample rate.
|
||||||
|
* @details This function will configure I2S controller according to the input parameters. Set TX and RX FIFO threshold to middle value.
|
||||||
|
* The actual sample rate may be different from the target sample rate. The real sample rate will be returned for reference.
|
||||||
|
* @note Both the TX and RX functions will be enabled.
|
||||||
|
*/
|
||||||
|
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat)
|
||||||
|
{
|
||||||
|
if (!(__PC() & (1 << 28)))
|
||||||
|
{
|
||||||
|
uint8_t u8Divider;
|
||||||
|
uint32_t u32BitRate, u32SrcClk;
|
||||||
|
|
||||||
|
/* Reset I2S */
|
||||||
|
SYS->IPRST1 |= SYS_IPRST1_I2S0RST_Msk;
|
||||||
|
SYS->IPRST1 &= ~SYS_IPRST1_I2S0RST_Msk;
|
||||||
|
|
||||||
|
/* Configure I2S controller according to input parameters. */
|
||||||
|
i2s->CTL0 = u32MasterSlave | u32WordWidth | u32Channels | u32DataFormat | I2S_FIFO_TX_LEVEL_WORD_4 | I2S_FIFO_RX_LEVEL_WORD_4;
|
||||||
|
|
||||||
|
/* Get I2S source clock frequency */
|
||||||
|
u32SrcClk = I2S_GetSourceClockFreq(i2s);
|
||||||
|
|
||||||
|
/* Calculate bit clock rate */
|
||||||
|
u32BitRate = u32SampleRate * (((u32WordWidth >> 4) & 0x3) + 1) * 16;
|
||||||
|
u8Divider = ((u32SrcClk / u32BitRate) >> 1) - 1;
|
||||||
|
i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_BCLKDIV_Msk) | (u8Divider << 8);
|
||||||
|
|
||||||
|
/* Calculate real sample rate */
|
||||||
|
u32BitRate = u32SrcClk / ((u8Divider + 1) * 2);
|
||||||
|
u32SampleRate = u32BitRate / ((((u32WordWidth >> 4) & 0x3) + 1) * 16);
|
||||||
|
|
||||||
|
/* Enable TX, RX and I2S controller */
|
||||||
|
i2s->CTL0 |= (I2S_CTL0_RXEN_Msk | I2S_CTL0_TXEN_Msk | I2S_CTL0_I2SEN_Msk);
|
||||||
|
|
||||||
|
return u32SampleRate;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S function.
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details Clear I2SEN (I2SCTL0[0]) to disable I2S function.
|
||||||
|
*/
|
||||||
|
void I2S_Close(I2S_T *i2s)
|
||||||
|
{
|
||||||
|
i2s->CTL0 &= ~I2S_CTL0_I2SEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable interrupt function.
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt bit.
|
||||||
|
* @return None
|
||||||
|
* @details This function enables the interrupt according to the mask parameter.
|
||||||
|
*/
|
||||||
|
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
i2s->IEN |= u32Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable interrupt function.
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt bit.
|
||||||
|
* @return None
|
||||||
|
* @details This function disables the interrupt according to the mask parameter.
|
||||||
|
*/
|
||||||
|
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
i2s->IEN &= ~u32Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable master clock (MCLK).
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @param[in] u32BusClock The target MCLK clock.
|
||||||
|
* @return Actual MCLK clock
|
||||||
|
* @details Set the master clock rate according to u32BusClock parameter and enable master clock output.
|
||||||
|
* The actual master clock rate may be different from the target master clock rate. The real master clock rate will be returned for reference.
|
||||||
|
*/
|
||||||
|
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock)
|
||||||
|
{
|
||||||
|
uint8_t u8Divider;
|
||||||
|
uint32_t u32SrcClk, u32Reg;
|
||||||
|
|
||||||
|
u32SrcClk = I2S_GetSourceClockFreq(i2s);
|
||||||
|
if(u32BusClock == u32SrcClk)
|
||||||
|
u8Divider = 0;
|
||||||
|
else
|
||||||
|
u8Divider = (u32SrcClk / u32BusClock) >> 1;
|
||||||
|
|
||||||
|
i2s->CLKDIV = (i2s->CLKDIV & ~I2S_CLKDIV_MCLKDIV_Msk) | u8Divider;
|
||||||
|
|
||||||
|
i2s->CTL0 |= I2S_CTL0_MCLKEN_Msk;
|
||||||
|
|
||||||
|
u32Reg = i2s->CLKDIV & I2S_CLKDIV_MCLKDIV_Msk;
|
||||||
|
|
||||||
|
if(u32Reg == 0)
|
||||||
|
return u32SrcClk;
|
||||||
|
else
|
||||||
|
return ((u32SrcClk >> 1) / u32Reg);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable master clock (MCLK).
|
||||||
|
* @param[in] i2s The base address of I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details Disable master clock output.
|
||||||
|
*/
|
||||||
|
void I2S_DisableMCLK(I2S_T *i2s)
|
||||||
|
{
|
||||||
|
i2s->CTL0 &= ~I2S_CTL0_MCLKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure FIFO threshold setting.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32TxThreshold Decides the TX FIFO threshold. It could be 0 ~ 7.
|
||||||
|
* @param[in] u32RxThreshold Decides the RX FIFO threshold. It could be 0 ~ 7.
|
||||||
|
* @return None
|
||||||
|
* @details Set TX FIFO threshold and RX FIFO threshold configurations.
|
||||||
|
*/
|
||||||
|
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
|
||||||
|
{
|
||||||
|
i2s->CTL1 = (i2s->CTL1 & ~(I2S_CTL1_TXTH_Msk | I2S_CTL1_RXTH_Msk)) |
|
||||||
|
(u32TxThreshold << I2S_CTL1_TXTH_Pos) |
|
||||||
|
(u32RxThreshold << I2S_CTL1_RXTH_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure PCM(TDM) function parameters, such as channel width, channel number and sync pulse width
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32ChannelWidth Channel width. Valid values are:
|
||||||
|
* - \ref I2S_TDM_WIDTH_8BIT
|
||||||
|
* - \ref I2S_TDM_WIDTH_16BIT
|
||||||
|
* - \ref I2S_TDM_WIDTH_24BIT
|
||||||
|
* - \ref I2S_TDM_WIDTH_32BIT
|
||||||
|
* @param[in] u32ChannelNum Channel number. Valid values are:
|
||||||
|
* - \ref I2S_TDM_2CH
|
||||||
|
* - \ref I2S_TDM_4CH
|
||||||
|
* - \ref I2S_TDM_6CH
|
||||||
|
* - \ref I2S_TDM_8CH
|
||||||
|
* @param[in] u32SyncWidth Width for sync pulse. Valid values are:
|
||||||
|
* - \ref I2S_TDM_SYNC_ONE_BCLK
|
||||||
|
* - \ref I2S_TDM_SYNC_ONE_CHANNEL
|
||||||
|
* @return None
|
||||||
|
* @details Set TX FIFO threshold and RX FIFO threshold configurations.
|
||||||
|
*/
|
||||||
|
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth)
|
||||||
|
{
|
||||||
|
i2s->CTL0 = (i2s->CTL0 & ~(I2S_CTL0_TDMCHNUM_Msk | I2S_CTL0_CHWIDTH_Msk | I2S_CTL0_PCMSYNC_Msk)) |
|
||||||
|
(u32ChannelWidth << I2S_CTL0_CHWIDTH_Pos) |
|
||||||
|
(u32ChannelNum << I2S_CTL0_TDMCHNUM_Pos) |
|
||||||
|
(u32SyncWidth << I2S_CTL0_PCMSYNC_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2S_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,332 @@
|
||||||
|
/****************************************************************************//**
|
||||||
|
* @file i2s.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series I2S driver header file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __I2S_H__
|
||||||
|
#define __I2S_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_Driver I2S Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup I2S_EXPORTED_CONSTANTS I2S Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define I2S_DATABIT_8 (0 << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 8-bit \hideinitializer */
|
||||||
|
#define I2S_DATABIT_16 (1 << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 16-bit \hideinitializer */
|
||||||
|
#define I2S_DATABIT_24 (2 << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 24-bit \hideinitializer */
|
||||||
|
#define I2S_DATABIT_32 (3 << I2S_CTL0_DATWIDTH_Pos) /*!< I2S data width is 32-bit \hideinitializer */
|
||||||
|
|
||||||
|
/* Audio Format */
|
||||||
|
#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
|
||||||
|
#define I2S_DISABLE_MONO 0 /*!< Stereo channel \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S Data Format */
|
||||||
|
#define I2S_FORMAT_I2S (0 << I2S_CTL0_FORMAT_Pos) /*!< I2S data format \hideinitializer */
|
||||||
|
#define I2S_FORMAT_I2S_MSB (1 << I2S_CTL0_FORMAT_Pos) /*!< I2S MSB data format \hideinitializer */
|
||||||
|
#define I2S_FORMAT_I2S_LSB (2 << I2S_CTL0_FORMAT_Pos) /*!< I2S LSB data format \hideinitializer */
|
||||||
|
#define I2S_FORMAT_PCM (4 << I2S_CTL0_FORMAT_Pos) /*!< PCM data format \hideinitializer */
|
||||||
|
#define I2S_FORMAT_PCM_MSB (5 << I2S_CTL0_FORMAT_Pos) /*!< PCM MSB data format \hideinitializer */
|
||||||
|
#define I2S_FORMAT_PCM_LSB (6 << I2S_CTL0_FORMAT_Pos) /*!< PCM LSB data format \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S Data Format */
|
||||||
|
#define I2S_ORDER_AT_MSB 0 /*!< Channel data is at MSB \hideinitializer */
|
||||||
|
#define I2S_ORDER_AT_LSB I2S_CTL0_ORDER_Msk /*!< Channel data is at LSB \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S TDM Channel Number */
|
||||||
|
#define I2S_TDM_2CH 0 /*!< Use TDM 2 channel \hideinitializer */
|
||||||
|
#define I2S_TDM_4CH 1 /*!< Use TDM 4 channel \hideinitializer */
|
||||||
|
#define I2S_TDM_6CH 2 /*!< Use TDM 6 channel \hideinitializer */
|
||||||
|
#define I2S_TDM_8CH 3 /*!< Use TDM 8 channel \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S TDM Channel Width */
|
||||||
|
#define I2S_TDM_WIDTH_8BIT 0 /*!< TDM channel witch is 8-bit \hideinitializer */
|
||||||
|
#define I2S_TDM_WIDTH_16BIT 1 /*!< TDM channel witch is 16-bit \hideinitializer */
|
||||||
|
#define I2S_TDM_WIDTH_24BIT 2 /*!< TDM channel witch is 24-bit \hideinitializer */
|
||||||
|
#define I2S_TDM_WIDTH_32BIT 3 /*!< TDM channel witch is 32-bit \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S TDM Sync Width */
|
||||||
|
#define I2S_TDM_SYNC_ONE_BCLK 0 /*!< TDM sync widht is one BLCK period \hideinitializer */
|
||||||
|
#define I2S_TDM_SYNC_ONE_CHANNEL 1 /*!< TDM sync widht is one channel period \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S Operation mode */
|
||||||
|
#define I2S_MODE_SLAVE I2S_CTL0_SLAVE_Msk /*!< As slave mode \hideinitializer */
|
||||||
|
#define I2S_MODE_MASTER 0 /*!< As master mode \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S FIFO Threshold */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_1 (1 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 1 word \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_2 (2 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 2 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_3 (3 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 3 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_4 (4 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 4 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_5 (5 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 5 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_6 (6 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 6 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_TX_LEVEL_WORD_7 (7 << I2S_CTL1_TXTH_Pos) /*!< TX threshold is 7 words \hideinitializer */
|
||||||
|
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_2 (1 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 2 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_3 (2 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 3 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_4 (3 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 4 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_5 (4 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 5 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_6 (5 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 6 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_7 (6 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 7 words \hideinitializer */
|
||||||
|
#define I2S_FIFO_RX_LEVEL_WORD_8 (7 << I2S_CTL1_RXTH_Pos) /*!< RX threshold is 8 words \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S Record Channel */
|
||||||
|
#define I2S_MONO_RIGHT 0 /*!< Record mono right channel \hideinitializer */
|
||||||
|
#define I2S_MONO_LEFT I2S_CTL0_RXLCH_Msk /*!< Record mono left channel \hideinitializer */
|
||||||
|
|
||||||
|
/* I2S Channel */
|
||||||
|
#define I2S_RIGHT 0 /*!< Select right channel \hideinitializer */
|
||||||
|
#define I2S_LEFT 1 /*!< Select left channel \hideinitializer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2S_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup I2S_EXPORTED_FUNCTIONS I2S Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* inline functions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/**
|
||||||
|
* @brief Enable zero cross detect function.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
static __INLINE void I2S_ENABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
|
||||||
|
{
|
||||||
|
if((u32ChMask > 0) && (u32ChMask < 9))
|
||||||
|
i2s->CTL1 |= (1 << (u32ChMask - 1));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable zero cross detect function.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32ChMask is the mask for channel number (valid value is from (1~8).
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
static __INLINE void I2S_DISABLE_TX_ZCD(I2S_T *i2s, uint32_t u32ChMask)
|
||||||
|
{
|
||||||
|
if((u32ChMask > 0) && (u32ChMask < 9))
|
||||||
|
i2s->CTL1 &= ~(1 << (u32ChMask - 1));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_ENABLE_TXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S Tx DMA function. I2S requests DMA to transfer data to Tx FIFO.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_DISABLE_TXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_ENABLE_RXDMA(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S Rx DMA function. I2S requests DMA to transfer data from Rx FIFO.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_DISABLE_RXDMA(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S Tx function .
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_ENABLE_TX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S Tx function .
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_DISABLE_TX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_TXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S Rx function .
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_ENABLE_RX(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S Rx function .
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_DISABLE_RX(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_RXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Tx Mute function .
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_ENABLE_TX_MUTE(i2s) ( (i2s)->CTL0 |= I2S_CTL0_MUTE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Tx Mute function .
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_DISABLE_TX_MUTE(i2s) ( (i2s)->CTL0 &= ~I2S_CTL0_MUTE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Tx FIFO. Internal pointer is reset to FIFO start point.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_CLR_TX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_TXFBCLR_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Rx FIFO. Internal pointer is reset to FIFO start point.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_CLR_RX_FIFO(i2s) ( (i2s)->CTL0 |= I2S_CTL0_RXFBCLR_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function sets the recording source channel when mono mode is used.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32Ch left or right channel. Valid values are:
|
||||||
|
* - \ref I2S_MONO_LEFT
|
||||||
|
* - \ref I2S_MONO_RIGHT
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
static __INLINE void I2S_SET_MONO_RX_CHANNEL(I2S_T *i2s, uint32_t u32Ch)
|
||||||
|
{
|
||||||
|
u32Ch == I2S_MONO_LEFT ?
|
||||||
|
(i2s->CTL0 |= I2S_CTL0_RXLCH_Msk) :
|
||||||
|
(i2s->CTL0 &= ~I2S_CTL0_RXLCH_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write data to I2S Tx FIFO.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32Data: The data written to FIFO.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TXFIFO = u32Data )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Rx FIFO.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return Data in Rx FIFO.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_READ_RX_FIFO(i2s) ( (i2s)->RXFIFO )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function gets the interrupt flag according to the mask parameter.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32Mask is the mask for the all interrupt flags.
|
||||||
|
* @return The masked bit value of interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 & (u32Mask) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function clears the interrupt flag according to the mask parameter.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32Mask is the mask for the all interrupt flags.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS0 |= (u32Mask) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function gets the zero crossing interrupt flag according to the mask parameter.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32Mask is the mask for the all interrupt flags.
|
||||||
|
* @return The masked bit value of interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_GET_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 & (u32Mask) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function clears the zero crossing interrupt flag according to the mask parameter.
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @param[in] u32Mask is the mask for the all interrupt flags.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_CLR_ZC_INT_FLAG(i2s, u32Mask) ( (i2s)->STATUS1 |= (u32Mask) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get transmit FIFO level
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return FIFO level
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_GET_TX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_TXCNT_Msk) >> I2S_STATUS1_TXCNT_Pos) & 0xF )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get receive FIFO level
|
||||||
|
* @param[in] i2s is the base address of I2S module.
|
||||||
|
* @return FIFO level
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define I2S_GET_RX_FIFO_LEVEL(i2s) ( (((i2s)->STATUS1 & I2S_STATUS1_RXCNT_Msk) >> I2S_STATUS1_RXCNT_Pos) & 0xF )
|
||||||
|
|
||||||
|
uint32_t I2S_Open(I2S_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
|
||||||
|
void I2S_Close(I2S_T *i2s);
|
||||||
|
void I2S_EnableInt(I2S_T *i2s, uint32_t u32Mask);
|
||||||
|
void I2S_DisableInt(I2S_T *i2s, uint32_t u32Mask);
|
||||||
|
uint32_t I2S_EnableMCLK(I2S_T *i2s, uint32_t u32BusClock);
|
||||||
|
void I2S_DisableMCLK(I2S_T *i2s);
|
||||||
|
void I2S_SetFIFO(I2S_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||||
|
void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelNum, uint32_t u32SyncWidth);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2S_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group I2S_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,331 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file otg.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series OTG driver header file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __OTG_H__
|
||||||
|
#define __OTG_H__
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Include related headers */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup OTG_Driver OTG Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup OTG_EXPORTED_CONSTANTS OTG Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* OTG constant definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define OTG_VBUS_EN_ACTIVE_HIGH (0UL) /*!< USB VBUS power switch enable signal is active high. */
|
||||||
|
#define OTG_VBUS_EN_ACTIVE_LOW (1UL) /*!< USB VBUS power switch enable signal is active low. */
|
||||||
|
#define OTG_VBUS_ST_VALID_HIGH (0UL) /*!< USB VBUS power switch valid status is high. */
|
||||||
|
#define OTG_VBUS_ST_VALID_LOW (1UL) /*!< USB VBUS power switch valid status is low. */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group OTG_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup OTG_EXPORTED_FUNCTIONS OTG Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define Macros and functions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable OTG function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable OTG function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_NS() (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable OTG function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable OTG function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_NS() (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable USB PHY
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
|
||||||
|
* This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable USB PHY Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_PHY_NS() (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable USB PHY
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable USB PHY Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_PHY_NS() (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ID detection function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable ID detection function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_ID_DETECT_NS() (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ID detection function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable ID detection function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_ID_DETECT_NS() (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable OTG wake-up function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable OTG wake-up function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_WAKEUP_NS() (OTG_NS->CTL |= OTG_CTL_WKEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable OTG wake-up function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable OTG wake-up function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_WAKEUP_NS() (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set the polarity of USB_VBUS_EN pin
|
||||||
|
* @param[in] u32Pol The polarity selection. Valid values are listed below.
|
||||||
|
* - \ref OTG_VBUS_EN_ACTIVE_HIGH
|
||||||
|
* - \ref OTG_VBUS_EN_ACTIVE_LOW
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
|
||||||
|
*/
|
||||||
|
#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set the polarity of USB_VBUS_EN pin Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_SET_VBUS_EN_POL_NS(u32Pol) (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set the polarity of USB_VBUS_ST pin
|
||||||
|
* @param[in] u32Pol The polarity selection. Valid values are listed below.
|
||||||
|
* - \ref OTG_VBUS_ST_VALID_HIGH
|
||||||
|
* - \ref OTG_VBUS_ST_VALID_LOW
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the polarity of external USB VBUS power switch status signal.
|
||||||
|
*/
|
||||||
|
#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to set the polarity of USB_VBUS_ST pin Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_SET_VBUS_STS_POL_NS(u32Pol) (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable OTG related interrupts
|
||||||
|
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
|
||||||
|
* - \ref OTG_INTEN_ROLECHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_VBEIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_SRPFIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_HNPFIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_GOIDLEIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_IDCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_PDEVIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_HOSTIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_BVLDCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_AVLDCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_VBCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_SECHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_SRPDETIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will enable OTG related interrupts specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to enable OTG related interrupts Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_ENABLE_INT_NS(u32Mask) (OTG_NS->INTEN |= (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable OTG related interrupts
|
||||||
|
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
|
||||||
|
* - \ref OTG_INTEN_ROLECHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_VBEIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_SRPFIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_HNPFIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_GOIDLEIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_IDCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_PDEVIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_HOSTIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_BVLDCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_AVLDCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_VBCHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_SECHGIEN_Msk
|
||||||
|
* - \ref OTG_INTEN_SRPDETIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will disable OTG related interrupts specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to disable OTG related interrupts Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_DISABLE_INT_NS(u32Mask) (OTG_NS->INTEN &= ~(u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get OTG related interrupt flags
|
||||||
|
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
|
||||||
|
* - \ref OTG_INTSTS_ROLECHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_VBEIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_SRPFIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_HNPFIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_GOIDLEIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_IDCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_PDEVIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_HOSTIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_BVLDCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_AVLDCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_VBCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_SECHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_SRPDETIF_Msk
|
||||||
|
* @return Interrupt flags of selected sources.
|
||||||
|
* @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get OTG related interrupt flags Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_GET_INT_FLAG_NS(u32Mask) (OTG_NS->INTSTS & (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear OTG related interrupt flags
|
||||||
|
* @param[in] u32Mask The combination of interrupt source. Each bit corresponds to a interrupt source. Valid values are listed below.
|
||||||
|
* - \ref OTG_INTSTS_ROLECHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_VBEIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_SRPFIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_HNPFIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_GOIDLEIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_IDCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_PDEVIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_HOSTIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_BVLDCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_AVLDCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_VBCHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_SECHGIF_Msk
|
||||||
|
* - \ref OTG_INTSTS_SRPDETIF_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear OTG related interrupt flags Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_CLR_INT_FLAG_NS(u32Mask) (OTG_NS->INTSTS = (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get OTG related status
|
||||||
|
* @param[in] u32Mask The combination of user specified source. Valid values are listed below.
|
||||||
|
* - \ref OTG_STATUS_OVERCUR_Msk
|
||||||
|
* - \ref OTG_STATUS_IDSTS_Msk
|
||||||
|
* - \ref OTG_STATUS_SESSEND_Msk
|
||||||
|
* - \ref OTG_STATUS_BVLD_Msk
|
||||||
|
* - \ref OTG_STATUS_AVLD_Msk
|
||||||
|
* - \ref OTG_STATUS_VBUSVLD_Msk
|
||||||
|
* @return The user specified status.
|
||||||
|
* @details This macro will return OTG related status specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to get OTG related status Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define OTG_GET_STATUS_NS(u32Mask) (OTG_NS->STATUS & (u32Mask))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group OTG_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group OTG_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif //__OTG_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,406 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file pdma.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series PDMA driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
static uint8_t u32ChSelect[PDMA_CH_MAX];
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PDMA_Driver PDMA Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PDMA Open
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Mask Channel enable bits.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function enable the PDMA channels.
|
||||||
|
*/
|
||||||
|
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
int volatile i;
|
||||||
|
|
||||||
|
for(i = 0UL; i < PDMA_CH_MAX; i++)
|
||||||
|
{
|
||||||
|
(pdma)->DSCT[i].CTL = 0UL;
|
||||||
|
u32ChSelect[i] = PDMA_MEM;
|
||||||
|
}
|
||||||
|
|
||||||
|
(pdma)->CHCTL |= u32Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief PDMA Close
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function disable all PDMA channels.
|
||||||
|
*/
|
||||||
|
void PDMA_Close(PDMA_T *pdma)
|
||||||
|
{
|
||||||
|
(pdma)->CHCTL = 0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set PDMA Transfer Count
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Width Data width. Valid values are
|
||||||
|
* - \ref PDMA_WIDTH_8
|
||||||
|
* - \ref PDMA_WIDTH_16
|
||||||
|
* - \ref PDMA_WIDTH_32
|
||||||
|
* @param[in] u32TransCount Transfer count
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set the selected channel data width and transfer count.
|
||||||
|
*/
|
||||||
|
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount)
|
||||||
|
{
|
||||||
|
(pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXCNT_Msk | PDMA_DSCT_CTL_TXWIDTH_Msk);
|
||||||
|
(pdma)->DSCT[u32Ch].CTL |= (u32Width | ((u32TransCount - 1UL) << PDMA_DSCT_CTL_TXCNT_Pos));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set PDMA Transfer Address
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32SrcAddr Source address
|
||||||
|
* @param[in] u32SrcCtrl Source control attribute. Valid values are
|
||||||
|
* - \ref PDMA_SAR_INC
|
||||||
|
* - \ref PDMA_SAR_FIX
|
||||||
|
* @param[in] u32DstAddr destination address
|
||||||
|
* @param[in] u32DstCtrl destination control attribute. Valid values are
|
||||||
|
* - \ref PDMA_DAR_INC
|
||||||
|
* - \ref PDMA_DAR_FIX
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set the selected channel source/destination address and attribute.
|
||||||
|
*/
|
||||||
|
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl)
|
||||||
|
{
|
||||||
|
(pdma)->DSCT[u32Ch].SA = u32SrcAddr;
|
||||||
|
(pdma)->DSCT[u32Ch].DA = u32DstAddr;
|
||||||
|
(pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_SAINC_Msk | PDMA_DSCT_CTL_DAINC_Msk);
|
||||||
|
(pdma)->DSCT[u32Ch].CTL |= (u32SrcCtrl | u32DstCtrl);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set PDMA Transfer Mode
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Peripheral The selected peripheral. Valid values are
|
||||||
|
* - \ref PDMA_MEM
|
||||||
|
* - \ref PDMA_USB_TX
|
||||||
|
* - \ref PDMA_USB_RX
|
||||||
|
* - \ref PDMA_UART0_TX
|
||||||
|
* - \ref PDMA_UART0_RX
|
||||||
|
* - \ref PDMA_UART1_TX
|
||||||
|
* - \ref PDMA_UART1_RX
|
||||||
|
* - \ref PDMA_UART2_TX
|
||||||
|
* - \ref PDMA_UART2_RX
|
||||||
|
* - \ref PDMA_UART3_TX
|
||||||
|
* - \ref PDMA_UART3_RX
|
||||||
|
* - \ref PDMA_UART4_TX
|
||||||
|
* - \ref PDMA_UART4_RX
|
||||||
|
* - \ref PDMA_UART5_TX
|
||||||
|
* - \ref PDMA_UART5_RX
|
||||||
|
* - \ref PDMA_USCI0_TX
|
||||||
|
* - \ref PDMA_USCI0_RX
|
||||||
|
* - \ref PDMA_USCI1_TX
|
||||||
|
* - \ref PDMA_USCI1_RX
|
||||||
|
* - \ref PDMA_SPI0_TX
|
||||||
|
* - \ref PDMA_SPI0_RX
|
||||||
|
* - \ref PDMA_SPI1_TX
|
||||||
|
* - \ref PDMA_SPI1_RX
|
||||||
|
* - \ref PDMA_SPI2_TX
|
||||||
|
* - \ref PDMA_SPI2_RX
|
||||||
|
* - \ref PDMA_SPI3_TX
|
||||||
|
* - \ref PDMA_SPI3_RX
|
||||||
|
* - \ref PDMA_SPI4_TX
|
||||||
|
* - \ref PDMA_SPI4_RX
|
||||||
|
* - \ref PDMA_SPI5_TX
|
||||||
|
* - \ref PDMA_SPI5_RX
|
||||||
|
* - \ref PDMA_PWM0_P1_RX
|
||||||
|
* - \ref PDMA_PWM0_P2_RX
|
||||||
|
* - \ref PDMA_PWM0_P3_RX
|
||||||
|
* - \ref PDMA_PWM1_P1_RX
|
||||||
|
* - \ref PDMA_PWM1_P2_RX
|
||||||
|
* - \ref PDMA_PWM1_P3_RX
|
||||||
|
* - \ref PDMA_I2C0_TX
|
||||||
|
* - \ref PDMA_I2C0_RX
|
||||||
|
* - \ref PDMA_I2C1_TX
|
||||||
|
* - \ref PDMA_I2C1_RX
|
||||||
|
* - \ref PDMA_I2C2_TX
|
||||||
|
* - \ref PDMA_I2C2_RX
|
||||||
|
* - \ref PDMA_I2S0_TX
|
||||||
|
* - \ref PDMA_I2S0_RX
|
||||||
|
* - \ref PDMA_TMR0
|
||||||
|
* - \ref PDMA_TMR1
|
||||||
|
* - \ref PDMA_TMR2
|
||||||
|
* - \ref PDMA_TMR3
|
||||||
|
* - \ref PDMA_ADC_RX
|
||||||
|
* - \ref PDMA_DAC0_TX
|
||||||
|
* - \ref PDMA_DAC1_TX
|
||||||
|
* @param[in] u32ScatterEn Scatter-gather mode enable
|
||||||
|
* @param[in] u32DescAddr Scatter-gather descriptor address
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set the selected channel transfer mode. Include peripheral setting.
|
||||||
|
*/
|
||||||
|
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr)
|
||||||
|
{
|
||||||
|
u32ChSelect[u32Ch] = u32Peripheral;
|
||||||
|
switch(u32Ch)
|
||||||
|
{
|
||||||
|
case 0UL:
|
||||||
|
(pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC0_Msk) | u32Peripheral;
|
||||||
|
break;
|
||||||
|
case 1UL:
|
||||||
|
(pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC1_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC1_Pos);
|
||||||
|
break;
|
||||||
|
case 2UL:
|
||||||
|
(pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC2_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC2_Pos);
|
||||||
|
break;
|
||||||
|
case 3UL:
|
||||||
|
(pdma)->REQSEL0_3 = ((pdma)->REQSEL0_3 & ~PDMA_REQSEL0_3_REQSRC3_Msk) | (u32Peripheral << PDMA_REQSEL0_3_REQSRC3_Pos);
|
||||||
|
break;
|
||||||
|
case 4UL:
|
||||||
|
(pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC4_Msk) | u32Peripheral;
|
||||||
|
break;
|
||||||
|
case 5UL:
|
||||||
|
(pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC5_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC5_Pos);
|
||||||
|
break;
|
||||||
|
case 6UL:
|
||||||
|
(pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC6_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC6_Pos);
|
||||||
|
break;
|
||||||
|
case 7UL:
|
||||||
|
(pdma)->REQSEL4_7 = ((pdma)->REQSEL4_7 & ~PDMA_REQSEL4_7_REQSRC7_Msk) | (u32Peripheral << PDMA_REQSEL4_7_REQSRC7_Pos);
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32ScatterEn)
|
||||||
|
{
|
||||||
|
(pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_SCATTER;
|
||||||
|
(pdma)->DSCT[u32Ch].FIRST = u32DescAddr - ((pdma)->SCATBA);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
(pdma)->DSCT[u32Ch].CTL = ((pdma)->DSCT[u32Ch].CTL & ~PDMA_DSCT_CTL_OPMODE_Msk) | PDMA_OP_BASIC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set PDMA Burst Type and Size
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32BurstType Burst mode or single mode. Valid values are
|
||||||
|
* - \ref PDMA_REQ_SINGLE
|
||||||
|
* - \ref PDMA_REQ_BURST
|
||||||
|
* @param[in] u32BurstSize Set the size of burst mode. Valid values are
|
||||||
|
* - \ref PDMA_BURST_128
|
||||||
|
* - \ref PDMA_BURST_64
|
||||||
|
* - \ref PDMA_BURST_32
|
||||||
|
* - \ref PDMA_BURST_16
|
||||||
|
* - \ref PDMA_BURST_8
|
||||||
|
* - \ref PDMA_BURST_4
|
||||||
|
* - \ref PDMA_BURST_2
|
||||||
|
* - \ref PDMA_BURST_1
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set the selected channel burst type and size.
|
||||||
|
*/
|
||||||
|
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize)
|
||||||
|
{
|
||||||
|
(pdma)->DSCT[u32Ch].CTL &= ~(PDMA_DSCT_CTL_TXTYPE_Msk | PDMA_DSCT_CTL_BURSIZE_Msk);
|
||||||
|
(pdma)->DSCT[u32Ch].CTL |= (u32BurstType | u32BurstSize);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable timeout function
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Mask Channel enable bits.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function enable timeout function of the selected channel(s).
|
||||||
|
* @note This function is only supported in channel 0 and channel 1.
|
||||||
|
*/
|
||||||
|
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
(pdma)->TOUTEN |= u32Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable timeout function
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Mask Channel enable bits.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function disable timeout function of the selected channel(s).
|
||||||
|
* @note This function is only supported in channel 0 and channel 1.
|
||||||
|
*/
|
||||||
|
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
(pdma)->TOUTEN &= ~u32Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set PDMA Timeout Count
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32OnOff Enable/disable timeout function
|
||||||
|
* @param[in] u32TimeOutCnt Timeout count
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function set the timeout count.
|
||||||
|
* @note This function is only supported in channel 0 and channel 1.
|
||||||
|
*/
|
||||||
|
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt)
|
||||||
|
{
|
||||||
|
switch(u32Ch)
|
||||||
|
{
|
||||||
|
case 0UL:
|
||||||
|
(pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC0_Msk) | u32TimeOutCnt;
|
||||||
|
break;
|
||||||
|
case 1UL:
|
||||||
|
(pdma)->TOC0_1 = ((pdma)->TOC0_1 & ~PDMA_TOC0_1_TOC1_Msk) | (u32TimeOutCnt << PDMA_TOC0_1_TOC1_Pos);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
;
|
||||||
|
}
|
||||||
|
if(u32OnOff)
|
||||||
|
(pdma)->TOUTEN |= (1UL << u32Ch);
|
||||||
|
else
|
||||||
|
(pdma)->TOUTEN &= ~(1UL << u32Ch);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger PDMA
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function trigger the selected channel.
|
||||||
|
*/
|
||||||
|
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch)
|
||||||
|
{
|
||||||
|
if(u32ChSelect[u32Ch] == PDMA_MEM)
|
||||||
|
(pdma)->SWREQ = (1UL << u32Ch);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Mask The Interrupt Type. Valid values are
|
||||||
|
* - \ref PDMA_INT_TRANS_DONE
|
||||||
|
* - \ref PDMA_INT_TABLE
|
||||||
|
* - \ref PDMA_INT_TIMEOUT
|
||||||
|
* - \ref PDMA_INT_ALIGN
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function enable the selected channel interrupt.
|
||||||
|
* @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1.
|
||||||
|
*/
|
||||||
|
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
switch(u32Mask)
|
||||||
|
{
|
||||||
|
case PDMA_INT_TRANS_DONE:
|
||||||
|
case PDMA_INT_ALIGN:
|
||||||
|
(pdma)->INTEN |= (1UL << u32Ch);
|
||||||
|
break;
|
||||||
|
case PDMA_INT_TABLE:
|
||||||
|
(pdma)->DSCT[u32Ch].CTL &= ~PDMA_DSCT_CTL_TBINTDIS_Msk;
|
||||||
|
break;
|
||||||
|
case PDMA_INT_TIMEOUT:
|
||||||
|
(pdma)->TOUTIEN |= (1UL << u32Ch);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Mask The Interrupt Type. Valid values are
|
||||||
|
* - \ref PDMA_INT_TRANS_DONE
|
||||||
|
* - \ref PDMA_INT_TABLE
|
||||||
|
* - \ref PDMA_INT_TIMEOUT
|
||||||
|
* - \ref PDMA_INT_ALIGN
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function disable the selected channel interrupt.
|
||||||
|
* @note PDMA_INT_TIMEOUT is only supported in channel 0 and channel 1.
|
||||||
|
* @note The transfer done interrupt is disabled when table empty interrupt is disabled(PDMA_INT_TEMPTY).
|
||||||
|
*/
|
||||||
|
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
switch(u32Mask)
|
||||||
|
{
|
||||||
|
case PDMA_INT_TRANS_DONE:
|
||||||
|
case PDMA_INT_ALIGN:
|
||||||
|
(pdma)->INTEN &= ~(1UL << u32Ch);
|
||||||
|
break;
|
||||||
|
case PDMA_INT_TABLE:
|
||||||
|
(pdma)->DSCT[u32Ch].CTL |= PDMA_DSCT_CTL_TBINTDIS_Msk;
|
||||||
|
break;
|
||||||
|
case PDMA_INT_TIMEOUT:
|
||||||
|
(pdma)->TOUTIEN &= ~(1UL << u32Ch);
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PDMA_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,356 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file pdma.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series PDMA driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __PDMA_H__
|
||||||
|
#define __PDMA_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PDMA_Driver PDMA Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PDMA_EXPORTED_CONSTANTS PDMA Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define PDMA_CH_MAX 8UL /*!< Specify Maximum Channels of PDMA \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Operation Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_OP_STOP 0x00000000UL /*!<DMA Stop Mode \hideinitializer */
|
||||||
|
#define PDMA_OP_BASIC 0x00000001UL /*!<DMA Basic Mode \hideinitializer */
|
||||||
|
#define PDMA_OP_SCATTER 0x00000002UL /*!<DMA Scatter-gather Mode \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Data Width Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_WIDTH_8 0x00000000UL /*!<DMA Transfer Width 8-bit \hideinitializer */
|
||||||
|
#define PDMA_WIDTH_16 0x00001000UL /*!<DMA Transfer Width 16-bit \hideinitializer */
|
||||||
|
#define PDMA_WIDTH_32 0x00002000UL /*!<DMA Transfer Width 32-bit \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Address Attribute Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_SAR_INC 0x00000000UL /*!<DMA SAR increment \hideinitializer */
|
||||||
|
#define PDMA_SAR_FIX 0x00000300UL /*!<DMA SAR fix address \hideinitializer */
|
||||||
|
#define PDMA_DAR_INC 0x00000000UL /*!<DMA DAR increment \hideinitializer */
|
||||||
|
#define PDMA_DAR_FIX 0x00000C00UL /*!<DMA DAR fix address \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Burst Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_REQ_SINGLE 0x00000004UL /*!<DMA Single Request \hideinitializer */
|
||||||
|
#define PDMA_REQ_BURST 0x00000000UL /*!<DMA Burst Request \hideinitializer */
|
||||||
|
|
||||||
|
#define PDMA_BURST_128 0x00000000UL /*!<DMA Burst 128 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_64 0x00000010UL /*!<DMA Burst 64 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_32 0x00000020UL /*!<DMA Burst 32 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_16 0x00000030UL /*!<DMA Burst 16 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_8 0x00000040UL /*!<DMA Burst 8 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_4 0x00000050UL /*!<DMA Burst 4 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_2 0x00000060UL /*!<DMA Burst 2 Transfers \hideinitializer */
|
||||||
|
#define PDMA_BURST_1 0x00000070UL /*!<DMA Burst 1 Transfers \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Table Interrupt Disable Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_TBINTDIS_ENABLE (0x0UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Enabled \hideinitializer */
|
||||||
|
#define PDMA_TBINTDIS_DISABLE (0x1UL<<PDMA_DSCT_CTL_TBINTDIS_Pos) /*!<DMA Table Interrupt Disabled \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Peripheral Transfer Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_MEM 0x00000000UL /*!<DMA Connect to Memory \hideinitializer */
|
||||||
|
#define PDMA_USB_TX 0x00000002UL /*!<DMA Connect to USB TX \hideinitializer */
|
||||||
|
#define PDMA_USB_RX 0x00000003UL /*!<DMA Connect to USB RX \hideinitializer */
|
||||||
|
#define PDMA_UART0_TX 0x00000004UL /*!<DMA Connect to UART0 TX \hideinitializer */
|
||||||
|
#define PDMA_UART0_RX 0x00000005UL /*!<DMA Connect to UART0 RX \hideinitializer */
|
||||||
|
#define PDMA_UART1_TX 0x00000006UL /*!<DMA Connect to UART1 TX \hideinitializer */
|
||||||
|
#define PDMA_UART1_RX 0x00000007UL /*!<DMA Connect to UART1 RX \hideinitializer */
|
||||||
|
#define PDMA_UART2_TX 0x00000008UL /*!<DMA Connect to UART2 TX \hideinitializer */
|
||||||
|
#define PDMA_UART2_RX 0x00000009UL /*!<DMA Connect to UART2 RX \hideinitializer */
|
||||||
|
#define PDMA_UART3_TX 0x0000000AUL /*!<DMA Connect to UART3 TX \hideinitializer */
|
||||||
|
#define PDMA_UART3_RX 0x0000000BUL /*!<DMA Connect to UART3 RX \hideinitializer */
|
||||||
|
#define PDMA_UART4_TX 0x0000000CUL /*!<DMA Connect to UART4 TX \hideinitializer */
|
||||||
|
#define PDMA_UART4_RX 0x0000000DUL /*!<DMA Connect to UART4 RX \hideinitializer */
|
||||||
|
#define PDMA_UART5_TX 0x0000000EUL /*!<DMA Connect to UART5 TX \hideinitializer */
|
||||||
|
#define PDMA_UART5_RX 0x0000000FUL /*!<DMA Connect to UART5 RX \hideinitializer */
|
||||||
|
#define PDMA_USCI0_TX 0x00000010UL /*!<DMA Connect to USCI0 TX \hideinitializer */
|
||||||
|
#define PDMA_USCI0_RX 0x00000011UL /*!<DMA Connect to USCI0 RX \hideinitializer */
|
||||||
|
#define PDMA_USCI1_TX 0x00000012UL /*!<DMA Connect to USCI1 TX \hideinitializer */
|
||||||
|
#define PDMA_USCI1_RX 0x00000013UL /*!<DMA Connect to USCI1 RX \hideinitializer */
|
||||||
|
#define PDMA_SPI0_TX 0x00000014UL /*!<DMA Connect to SPI0 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI0_RX 0x00000015UL /*!<DMA Connect to SPI0 RX \hideinitializer */
|
||||||
|
#define PDMA_SPI1_TX 0x00000016UL /*!<DMA Connect to SPI1 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI1_RX 0x00000017UL /*!<DMA Connect to SPI1 RX \hideinitializer */
|
||||||
|
#define PDMA_SPI2_TX 0x00000018UL /*!<DMA Connect to SPI2 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI2_RX 0x00000019UL /*!<DMA Connect to SPI2 RX \hideinitializer */
|
||||||
|
#define PDMA_SPI3_TX 0x0000001AUL /*!<DMA Connect to SPI3 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI3_RX 0x0000001BUL /*!<DMA Connect to SPI3 RX \hideinitializer */
|
||||||
|
#define PDMA_SPI4_TX 0x0000001CUL /*!<DMA Connect to SPI4 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI4_RX 0x0000001DUL /*!<DMA Connect to SPI4 RX \hideinitializer */
|
||||||
|
#define PDMA_PWM0_P1_RX 0x00000020UL /*!<DMA Connect to PWM0 P1 RX \hideinitializer */
|
||||||
|
#define PDMA_PWM0_P2_RX 0x00000021UL /*!<DMA Connect to PWM0 P2 RX \hideinitializer */
|
||||||
|
#define PDMA_PWM0_P3_RX 0x00000022UL /*!<DMA Connect to PWM0 P3 RX \hideinitializer */
|
||||||
|
#define PDMA_PWM1_P1_RX 0x00000023UL /*!<DMA Connect to PWM1 P1 RX \hideinitializer */
|
||||||
|
#define PDMA_PWM1_P2_RX 0x00000024UL /*!<DMA Connect to PWM1 P2 RX \hideinitializer */
|
||||||
|
#define PDMA_PWM1_P3_RX 0x00000025UL /*!<DMA Connect to PWM1 P3 RX \hideinitializer */
|
||||||
|
#define PDMA_I2C0_TX 0x00000026UL /*!<DMA Connect to I2C0 TX \hideinitializer */
|
||||||
|
#define PDMA_I2C0_RX 0x00000027UL /*!<DMA Connect to I2C0 RX \hideinitializer */
|
||||||
|
#define PDMA_I2C1_TX 0x00000028UL /*!<DMA Connect to I2C1 TX \hideinitializer */
|
||||||
|
#define PDMA_I2C1_RX 0x00000029UL /*!<DMA Connect to I2C1 RX \hideinitializer */
|
||||||
|
#define PDMA_I2C2_TX 0x0000002AUL /*!<DMA Connect to I2C2 TX \hideinitializer */
|
||||||
|
#define PDMA_I2C2_RX 0x0000002BUL /*!<DMA Connect to I2C2 RX \hideinitializer */
|
||||||
|
#define PDMA_I2S0_TX 0x0000002CUL /*!<DMA Connect to I2S0 TX \hideinitializer */
|
||||||
|
#define PDMA_I2S0_RX 0x0000002DUL /*!<DMA Connect to I2S0 RX \hideinitializer */
|
||||||
|
#define PDMA_TMR0 0x0000002EUL /*!<DMA Connect to TMR0 \hideinitializer */
|
||||||
|
#define PDMA_TMR1 0x0000002FUL /*!<DMA Connect to TMR1 \hideinitializer */
|
||||||
|
#define PDMA_TMR2 0x00000030UL /*!<DMA Connect to TMR2 \hideinitializer */
|
||||||
|
#define PDMA_TMR3 0x00000031UL /*!<DMA Connect to TMR3 \hideinitializer */
|
||||||
|
#define PDMA_ADC_RX 0x00000032UL /*!<DMA Connect to ADC RX \hideinitializer */
|
||||||
|
#define PDMA_DAC0_TX 0x00000033UL /*!<DMA Connect to DAC0 TX \hideinitializer */
|
||||||
|
#define PDMA_DAC1_TX 0x00000034UL /*!<DMA Connect to DAC1 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI5_TX 0x00000036UL /*!<DMA Connect to SPI5 TX \hideinitializer */
|
||||||
|
#define PDMA_SPI5_RX 0x00000037UL /*!<DMA Connect to SPI5 RX \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Interrupt Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PDMA_INT_TRANS_DONE 0x00000000UL /*!<Transfer Done Interrupt \hideinitializer */
|
||||||
|
#define PDMA_INT_TABLE 0x00000001UL /*!<Table Interrupt \hideinitializer */
|
||||||
|
#define PDMA_INT_TIMEOUT 0x00000002UL /*!<Timeout Interrupt \hideinitializer */
|
||||||
|
#define PDMA_INT_ALIGN 0x00000003UL /*!<Transfer Alignment Interrupt \hideinitializer */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PDMA_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup PDMA_EXPORTED_FUNCTIONS PDMA Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get PDMA Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro gets the interrupt status.
|
||||||
|
*/
|
||||||
|
#define PDMA_GET_INT_STATUS(pdma) ((uint32_t)((pdma)->INTSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Transfer Done Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Get the transfer done Interrupt status.
|
||||||
|
*/
|
||||||
|
#define PDMA_GET_TD_STS(pdma) ((uint32_t)((pdma)->TDSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Transfer Done Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Mask The channel mask
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear the transfer done Interrupt status.
|
||||||
|
*/
|
||||||
|
#define PDMA_CLR_TD_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->TDSTS = (u32Mask)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Target Abort Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Get the target abort Interrupt status.
|
||||||
|
*/
|
||||||
|
#define PDMA_GET_ABORT_STS(pdma) ((uint32_t)((pdma)->ABTSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Target Abort Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Mask The channel mask
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear the target abort Interrupt status.
|
||||||
|
*/
|
||||||
|
#define PDMA_CLR_ABORT_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ABTSTS = (u32Mask)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get PDMA Transfer Alignment Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Get the PDMA transfer alignment status.
|
||||||
|
*/
|
||||||
|
#define PDMA_GET_ALIGN_STS(pdma) ((uint32_t)((pdma)->ALIGN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear PDMA Transfer Alignment Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Mask The channel mask
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear the PDMA transfer alignment Interrupt status.
|
||||||
|
*/
|
||||||
|
#define PDMA_CLR_ALIGN_FLAG(pdma, u32Mask) ((uint32_t)((pdma)->ALIGN = (u32Mask)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Timeout Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear the selected channel timeout interrupt status.
|
||||||
|
* @note This function is only supported in channel 0 and channel 1.
|
||||||
|
*/
|
||||||
|
#define PDMA_CLR_TMOUT_FLAG(pdma, u32Ch) ((uint32_t)((pdma)->INTSTS = (1 << ((u32Ch) + 8))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Channel Status
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
*
|
||||||
|
* @retval 0 Idle state
|
||||||
|
* @retval 1 Busy state
|
||||||
|
*
|
||||||
|
* @details Check the selected channel is busy or not.
|
||||||
|
*/
|
||||||
|
#define PDMA_IS_CH_BUSY(pdma, u32Ch) ((uint32_t)((pdma)->TRGSTS & (1 << (u32Ch)))? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Source Address
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Addr The selected address
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro set the selected channel source address.
|
||||||
|
*/
|
||||||
|
#define PDMA_SET_SRC_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].SA = (u32Addr)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Destination Address
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Addr The selected address
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro set the selected channel destination address.
|
||||||
|
*/
|
||||||
|
#define PDMA_SET_DST_ADDR(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].DA = (u32Addr)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Transfer Count
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32TransCount Transfer Count
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro set the selected channel transfer count.
|
||||||
|
*/
|
||||||
|
#define PDMA_SET_TRANS_CNT(pdma, u32Ch, u32TransCount) ((uint32_t)((pdma)->DSCT[(u32Ch)].CTL=((pdma)->DSCT[(u32Ch)].CTL&~PDMA_DSCT_CTL_TXCNT_Msk)|(((u32TransCount)-1) << PDMA_DSCT_CTL_TXCNT_Pos)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Scatter-gather descriptor Address
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
* @param[in] u32Addr The descriptor address
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro set the selected channel scatter-gather descriptor address.
|
||||||
|
*/
|
||||||
|
#define PDMA_SET_SCATTER_DESC(pdma, u32Ch, u32Addr) ((uint32_t)((pdma)->DSCT[(u32Ch)].FIRST = (u32Addr) - ((pdma)->SCATBA)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Pause the channel
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro pause the selected channel.
|
||||||
|
*/
|
||||||
|
#define PDMA_PAUSE(pdma, u32Ch) ((uint32_t)((pdma)->PAUSE = (1 << (u32Ch))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset the channel
|
||||||
|
*
|
||||||
|
* @param[in] pdma The pointer of the specified PDMA module
|
||||||
|
* @param[in] u32Ch The selected channel
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro reset the selected channel.
|
||||||
|
*/
|
||||||
|
#define PDMA_RESET(pdma, u32Ch) ((uint32_t)((pdma)->CHRST = (1 << (u32Ch))))
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define PWM functions prototype */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
void PDMA_Open(PDMA_T *pdma, uint32_t u32Mask);
|
||||||
|
void PDMA_Close(PDMA_T *pdma);
|
||||||
|
void PDMA_SetTransferCnt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Width, uint32_t u32TransCount);
|
||||||
|
void PDMA_SetTransferAddr(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32SrcAddr, uint32_t u32SrcCtrl, uint32_t u32DstAddr, uint32_t u32DstCtrl);
|
||||||
|
void PDMA_SetTransferMode(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Peripheral, uint32_t u32ScatterEn, uint32_t u32DescAddr);
|
||||||
|
void PDMA_SetBurstType(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32BurstType, uint32_t u32BurstSize);
|
||||||
|
void PDMA_EnableTimeout(PDMA_T *pdma, uint32_t u32Mask);
|
||||||
|
void PDMA_DisableTimeout(PDMA_T *pdma, uint32_t u32Mask);
|
||||||
|
void PDMA_SetTimeOut(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32OnOff, uint32_t u32TimeOutCnt);
|
||||||
|
void PDMA_Trigger(PDMA_T *pdma, uint32_t u32Ch);
|
||||||
|
void PDMA_EnableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
|
||||||
|
void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PDMA_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PDMA_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__PDMA_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,623 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file pwm.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series PWM driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __PWM_H__
|
||||||
|
#define __PWM_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PWM_Driver PWM Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup PWM_EXPORTED_CONSTANTS PWM Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define PWM_CHANNEL_NUM (6UL) /*!< PWM channel number */
|
||||||
|
#define PWM_CH_0_MASK (0x1UL) /*!< PWM channel 0 mask \hideinitializer */
|
||||||
|
#define PWM_CH_1_MASK (0x2UL) /*!< PWM channel 1 mask \hideinitializer */
|
||||||
|
#define PWM_CH_2_MASK (0x4UL) /*!< PWM channel 2 mask \hideinitializer */
|
||||||
|
#define PWM_CH_3_MASK (0x8UL) /*!< PWM channel 3 mask \hideinitializer */
|
||||||
|
#define PWM_CH_4_MASK (0x10UL) /*!< PWM channel 4 mask \hideinitializer */
|
||||||
|
#define PWM_CH_5_MASK (0x20UL) /*!< PWM channel 5 mask \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Counter Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_UP_COUNTER (0UL) /*!< Up counter type */
|
||||||
|
#define PWM_DOWN_COUNTER (1UL) /*!< Down counter type */
|
||||||
|
#define PWM_UP_DOWN_COUNTER (2UL) /*!< Up-Down counter type */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Aligned Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_EDGE_ALIGNED (1UL) /*!< PWM working in edge aligned type(down count) */
|
||||||
|
#define PWM_CENTER_ALIGNED (2UL) /*!< PWM working in center aligned type */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Output Level Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_OUTPUT_NOTHING (0UL) /*!< PWM output nothing */
|
||||||
|
#define PWM_OUTPUT_LOW (1UL) /*!< PWM output low */
|
||||||
|
#define PWM_OUTPUT_HIGH (2UL) /*!< PWM output high */
|
||||||
|
#define PWM_OUTPUT_TOGGLE (3UL) /*!< PWM output toggle */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Synchronous Start Function Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_SSCTL_SSRC_PWM0 (0UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM0 */
|
||||||
|
#define PWM_SSCTL_SSRC_PWM1 (1UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from PWM1 */
|
||||||
|
#define PWM_SSCTL_SSRC_BPWM0 (2UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM0 */
|
||||||
|
#define PWM_SSCTL_SSRC_BPWM1 (3UL<<PWM_SSCTL_SSRC_Pos) /*!< Synchronous start source comes from BPWM1 */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Trigger Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_TRIGGER_ADC_EVEN_ZERO_POINT (0UL) /*!< PWM trigger ADC while counter of even channel matches zero point */
|
||||||
|
#define PWM_TRIGGER_ADC_EVEN_PERIOD_POINT (1UL) /*!< PWM trigger ADC while counter of even channel matches period point */
|
||||||
|
#define PWM_TRIGGER_ADC_EVEN_ZERO_OR_PERIOD_POINT (2UL) /*!< PWM trigger ADC while counter of even channel matches zero or period point */
|
||||||
|
#define PWM_TRIGGER_ADC_EVEN_COMPARE_UP_COUNT_POINT (3UL) /*!< PWM trigger ADC while counter of even channel matches up count to comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_EVEN_COMPARE_DOWN_COUNT_POINT (4UL) /*!< PWM trigger ADC while counter of even channel matches down count to comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_ODD_ZERO_POINT (5UL) /*!< PWM trigger ADC while counter of odd channel matches zero point */
|
||||||
|
#define PWM_TRIGGER_ADC_ODD_PERIOD_POINT (6UL) /*!< PWM trigger ADC while counter of odd channel matches period point */
|
||||||
|
#define PWM_TRIGGER_ADC_ODD_ZERO_OR_PERIOD_POINT (7UL) /*!< PWM trigger ADC while counter of odd channel matches zero or period point */
|
||||||
|
#define PWM_TRIGGER_ADC_ODD_COMPARE_UP_COUNT_POINT (8UL) /*!< PWM trigger ADC while counter of odd channel matches up count to comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_ODD_COMPARE_DOWN_COUNT_POINT (9UL) /*!< PWM trigger ADC while counter of odd channel matches down count to comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_UP_COUNT_POINT (10UL) /*!< PWM trigger ADC while counter of channel 0 matches up count to free comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_CH_0_FREE_COMPARE_DOWN_COUNT_POINT (11UL) /*!< PWM trigger ADC while counter of channel 0 matches down count to free comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_UP_COUNT_POINT (12UL) /*!< PWM trigger ADC while counter of channel 2 matches up count to free comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_CH_2_FREE_COMPARE_DOWN_COUNT_POINT (13UL) /*!< PWM trigger ADC while counter of channel 2 matches down count to free comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_UP_COUNT_POINT (14UL) /*!< PWM trigger ADC while counter of channel 4 matches up count to free comparator point */
|
||||||
|
#define PWM_TRIGGER_ADC_CH_4_FREE_COMPARE_DOWN_COUNT_POINT (15UL) /*!< PWM trigger ADC while counter of channel 4 matches down count to free comparator point */
|
||||||
|
|
||||||
|
#define PWM_TRIGGER_DAC_ZERO_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */
|
||||||
|
#define PWM_TRIGGER_DAC_PERIOD_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (PERIOD + 1) \hideinitializer */
|
||||||
|
#define PWM_TRIGGER_DAC_COMPARE_UP_COUNT_POINT (0x10000UL) /*!< PWM trigger ADC while counter up count to CMPDAT \hideinitializer */
|
||||||
|
#define PWM_TRIGGER_DAC_COMPARE_DOWN_COUNT_POINT (0x1000000UL) /*!< PWM trigger ADC while counter down count to CMPDAT \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Fail brake Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_FB_EDGE_ACMP0 (PWM_BRKCTL0_1_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_ACMP1 (PWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_BKP0 (PWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_BKP1 (PWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_ADCRM (PWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_SYS_CSS (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_SYS_BOD (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_SYS_RAM (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
|
||||||
|
#define PWM_FB_EDGE_SYS_COR (PWM_BRKCTL0_1_SYSEBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
|
||||||
|
|
||||||
|
#define PWM_FB_LEVEL_ACMP0 (PWM_BRKCTL0_1_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_ACMP1 (PWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_BKP0 (PWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_BKP1 (PWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_ADCRM (PWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_SYS_CSS (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_SYS_BOD (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_SYS_RAM (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
|
||||||
|
#define PWM_FB_LEVEL_SYS_COR (PWM_BRKCTL0_1_SYSLBEN_Msk | PWM_FAILBRK_CORBRKEN_Msk) /*!< System fail condition: core lockup detection as level-detect fault brake source */
|
||||||
|
|
||||||
|
#define PWM_FB_EDGE (0UL) /*!< edge-detect fault brake */
|
||||||
|
#define PWM_FB_LEVEL (8UL) /*!< level-detect fault brake */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Leading Edge Blanking Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_LEBCTL_TRGTYPE_RISING (0UL<<PWM_LEBCTL_TRGTYPE_Pos) /*!< PWM Leading Edge Blanking Trigger Type Is Rising Edge \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_TRGTYPE_FALLING (1UL<<PWM_LEBCTL_TRGTYPE_Pos) /*!< PWM Leading Edge Blanking Trigger Type Is Falling Edge \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_TRGTYPE_RISING_OR_FALLING (2UL<<PWM_LEBCTL_TRGTYPE_Pos) /*!< PWM Leading Edge Blanking Trigger Type Is Rising or Falling Edge \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN0 (PWM_LEBCTL_SRCEN0_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0 Enable \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN2 (PWM_LEBCTL_SRCEN2_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH2 Enable \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN4 (PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH4 Enable \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN0_2 (PWM_LEBCTL_SRCEN0_Msk|PWM_LEBCTL_SRCEN2_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0 and PWMx_CH2 Enable \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN0_4 (PWM_LEBCTL_SRCEN0_Msk|PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0 and PWMx_CH4 Enable \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN2_4 (PWM_LEBCTL_SRCEN2_Msk|PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH2 and PWMx_CH4 Enable \hideinitializer */
|
||||||
|
#define PWM_LEBCTL_SRCEN0_2_4 (PWM_LEBCTL_SRCEN0_Msk|PWM_LEBCTL_SRCEN2_Msk|PWM_LEBCTL_SRCEN4_Msk) /*!< PWM Leading Edge Blanking Source From PWMx_CH0, PWMx_CH2 and PWMx_CH4 Enable \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Capture Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_CAPTURE_INT_RISING_LATCH (1UL) /*!< PWM capture interrupt if channel has rising transition */
|
||||||
|
#define PWM_CAPTURE_INT_FALLING_LATCH (0x100UL) /*!< PWM capture interrupt if channel has falling transition */
|
||||||
|
|
||||||
|
#define PWM_CAPTURE_PDMA_RISING_LATCH (0x2UL) /*!< PWM capture rising latched data transfer by PDMA */
|
||||||
|
#define PWM_CAPTURE_PDMA_FALLING_LATCH (0x4UL) /*!< PWM capture falling latched data transfer by PDMA */
|
||||||
|
#define PWM_CAPTURE_PDMA_RISING_FALLING_LATCH (0x6UL) /*!< PWM capture rising and falling latched data transfer by PDMA */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Duty Interrupt Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (PWM_INTEN0_CMPDIEN0_Msk) /*!< PWM duty interrupt triggered if down count match comparator */
|
||||||
|
#define PWM_DUTY_INT_UP_COUNT_MATCH_CMP (PWM_INTEN0_CMPUIEN0_Msk) /*!< PWM duty interrupt triggered if up down match comparator */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Interrupt Flag Accumulator Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_IFA_EVEN_ZERO_POINT (0UL) /*!< PWM counter equal to zero in even channel \hideinitializer */
|
||||||
|
#define PWM_IFA_EVEN_PERIOD_POINT (1UL) /*!< PWM counter equal to period in even channel \hideinitializer */
|
||||||
|
#define PWM_IFA_EVEN_COMPARE_UP_COUNT_POINT (2UL) /*!< PWM counter up count to comparator value in even channel \hideinitializer */
|
||||||
|
#define PWM_IFA_EVEN_COMPARE_DOWN_COUNT_POINT (3UL) /*!< PWM counter down count to comparator value in even channel \hideinitializer */
|
||||||
|
#define PWM_IFA_ODD_ZERO_POINT (4UL) /*!< PWM counter equal to zero in odd channel \hideinitializer */
|
||||||
|
#define PWM_IFA_ODD_PERIOD_POINT (5UL) /*!< PWM counter equal to period in odd channel \hideinitializer */
|
||||||
|
#define PWM_IFA_ODD_COMPARE_UP_COUNT_POINT (6UL) /*!< PWM counter up count to comparator value in odd channel \hideinitializer */
|
||||||
|
#define PWM_IFA_ODD_COMPARE_DOWN_COUNT_POINT (7UL) /*!< PWM counter down count to comparator value in odd channel \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Load Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_LOAD_MODE_IMMEDIATE (PWM_CTL0_IMMLDEN0_Msk) /*!< PWM immediately load mode \hideinitializer */
|
||||||
|
#define PWM_LOAD_MODE_WINDOW (PWM_CTL0_WINLDEN0_Msk) /*!< PWM window load mode \hideinitializer */
|
||||||
|
#define PWM_LOAD_MODE_CENTER (PWM_CTL0_CTRLD0_Msk) /*!< PWM center load mode \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Synchronize Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_SYNC_OUT_FROM_SYNCIN_SWSYNC (0UL) /*!< Synchronize source from SYNC_IN or SWSYNC \hideinitializer */
|
||||||
|
#define PWM_SYNC_OUT_FROM_COUNT_TO_ZERO (1UL) /*!< Synchronize source from counter equal to 0 \hideinitializer */
|
||||||
|
#define PWM_SYNC_OUT_FROM_COUNT_TO_COMPARATOR (2UL) /*!< Synchronize source from counter equal to CMPDAT1, CMPDAT3, CMPDAT5 \hideinitializer */
|
||||||
|
#define PWM_SYNC_OUT_DISABLE (3UL) /*!< SYNC_OUT will not be generated \hideinitializer */
|
||||||
|
#define PWM_PHS_DIR_DECREMENT (0UL) /*!< PWM counter count decrement \hideinitializer */
|
||||||
|
#define PWM_PHS_DIR_INCREMENT (1UL) /*!< PWM counter count increment \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Noise Filter Clock Divide Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_NF_CLK_DIV_1 (0UL) /*!< Noise filter clock is HCLK divide by 1 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_2 (1UL) /*!< Noise filter clock is HCLK divide by 2 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_4 (2UL) /*!< Noise filter clock is HCLK divide by 4 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_8 (3UL) /*!< Noise filter clock is HCLK divide by 8 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_16 (4UL) /*!< Noise filter clock is HCLK divide by 16 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_32 (5UL) /*!< Noise filter clock is HCLK divide by 32 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_64 (6UL) /*!< Noise filter clock is HCLK divide by 64 \hideinitializer */
|
||||||
|
#define PWM_NF_CLK_DIV_128 (7UL) /*!< Noise filter clock is HCLK divide by 128 \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Clock Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define PWM_CLKSRC_PWM_CLK (0UL) /*!< PWM Clock source selects to PWM0_CLK or PWM1_CLK \hideinitializer */
|
||||||
|
#define PWM_CLKSRC_TIMER0 (1UL) /*!< PWM Clock source selects to TIMER0 overflow \hideinitializer */
|
||||||
|
#define PWM_CLKSRC_TIMER1 (2UL) /*!< PWM Clock source selects to TIMER1 overflow \hideinitializer */
|
||||||
|
#define PWM_CLKSRC_TIMER2 (3UL) /*!< PWM Clock source selects to TIMER2 overflow \hideinitializer */
|
||||||
|
#define PWM_CLKSRC_TIMER3 (4UL) /*!< PWM Clock source selects to TIMER3 overflow \hideinitializer */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PWM_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup PWM_EXPORTED_FUNCTIONS PWM Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enable complementary mode
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable complementary mode of PWM module.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 | (0x7ul<<PWM_CTL1_OUTMODE0_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disable complementary mode, and enable independent mode.
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable complementary mode of PWM module.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL1 = (pwm)->CTL1 & ~(0x7ul<<PWM_CTL1_OUTMODE0_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enable group mode
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable group mode of PWM module.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 | PWM_CTL0_GROUPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disable group mode
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable group mode of PWM module.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL0 = (pwm)->CTL0 & ~PWM_CTL0_GROUPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable timer synchronous start counting function of specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @param[in] u32SyncSrc Synchronous start source selection, valid values are:
|
||||||
|
* - \ref PWM_SSCTL_SSRC_PWM0
|
||||||
|
* - \ref PWM_SSCTL_SSRC_PWM1
|
||||||
|
* - \ref PWM_SSCTL_SSRC_BPWM0
|
||||||
|
* - \ref PWM_SSCTL_SSRC_BPWM1
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable timer synchronous start counting function of specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_ENABLE_TIMER_SYNC(pwm, u32ChannelMask, u32SyncSrc) ((pwm)->SSCTL = ((pwm)->SSCTL & ~PWM_SSCTL_SSRC_Msk) | (u32SyncSrc) | (u32ChannelMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable timer synchronous start counting function of specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to disable timer synchronous start counting function of specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_DISABLE_TIMER_SYNC(pwm, u32ChannelMask) \
|
||||||
|
do{ \
|
||||||
|
int i;\
|
||||||
|
for(i = 0U; i < 6U; i++) { \
|
||||||
|
if((u32ChannelMask) & (1UL << i)) \
|
||||||
|
(pwm)->SSCTL &= ~(1UL << i); \
|
||||||
|
} \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enable PWM counter synchronous start counting function.
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to make selected PWM0 and PWM1 channel(s) start counting at the same time.
|
||||||
|
* To configure synchronous start counting channel(s) by PWM_ENABLE_TIMER_SYNC() and PWM_DISABLE_TIMER_SYNC().
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_TRIGGER_SYNC_START(pwm) ((pwm)->SSTRG = PWM_SSTRG_CNTSEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enable output inverter of specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to enable output inverter of specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->POLCTL = (u32ChannelMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get captured rising data
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to get captured rising data of specified channel.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->RCAPDAT0) + ((u32ChannelNum) << 1U)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get captured falling data
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to get captured falling data of specified channel.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->FCAPDAT0) + ((u32ChannelNum) << 1U)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro mask output logic to high or low
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @param[in] u32LevelMask Output logic to high or low
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to mask output logic to high or low of specified channel(s).
|
||||||
|
* @note If u32ChannelMask parameter is 0, then mask function will be disabled.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) \
|
||||||
|
{ \
|
||||||
|
(pwm)->MSKEN = (u32ChannelMask); \
|
||||||
|
(pwm)->MSK = (u32LevelMask); \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the prescaler of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the prescaler of specified channel.
|
||||||
|
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
|
||||||
|
* The clock of PWM counter is divided by (u32Prescaler + 1).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1U)) = (u32Prescaler))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get the prescaler of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @return Return Clock prescaler of specified channel. Valid values are between 0 ~ 0xFFF
|
||||||
|
* @details This macro is used to get the prescaler of specified channel.
|
||||||
|
* @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, channel 1 will also be affected.
|
||||||
|
* The clock of PWM counter is divided by (u32Prescaler + 1).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_GET_PRESCALER(pwm, u32ChannelNum) (*(__IO uint32_t *) (&((pwm)->CLKPSC0_1) + ((u32ChannelNum) >> 1U)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the comparator of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32CMR Comparator of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the comparator of specified channel.
|
||||||
|
* @note This new setting will take effect on next PWM period.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)]= (u32CMR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get the comparator of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @return Return the comparator of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @details This macro is used to get the comparator of specified channel.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_GET_CMR(pwm, u32ChannelNum) ((pwm)->CMPDAT[(u32ChannelNum)])
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the free trigger comparator of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32FTCMR Free trigger comparator of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the free trigger comparator of specified channel.
|
||||||
|
* @note This new setting will take effect on next PWM period.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_FTCMR(pwm, u32ChannelNum, u32FTCMR) (*(__IO uint32_t *) (&((pwm)->FTCMPDAT0_1) + ((u32ChannelNum) >> 1U)) = (u32FTCMR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the period of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the period of specified channel.
|
||||||
|
* @note This new setting will take effect on next PWM period.
|
||||||
|
* @note PWM counter will stop if period length set to 0.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro get the period of the selected channel
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @return Return the period of specified channel. Valid values are between 0~0xFFFF
|
||||||
|
* @details This macro is used to get the period of specified channel.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_GET_CNR(pwm, u32ChannelNum) ((pwm)->PERIOD[(u32ChannelNum)])
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro set the PWM aligned type
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @param[in] u32AlignedType PWM aligned type, valid values are:
|
||||||
|
* - \ref PWM_EDGE_ALIGNED
|
||||||
|
* - \ref PWM_CENTER_ALIGNED
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set the PWM aligned type of specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \
|
||||||
|
do{ \
|
||||||
|
int i; \
|
||||||
|
for(i = 0U; i < 6U; i++) { \
|
||||||
|
if((u32ChannelMask) & (1U << i)) \
|
||||||
|
(pwm)->CTL1 = (((pwm)->CTL1 & ~(3UL << (i << 1U))) | ((u32AlignedType) << (i << 1U))); \
|
||||||
|
} \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set load window of window loading mode for specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set load window of window loading mode for specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_LOAD_WINDOW(pwm, u32ChannelMask) ((pwm)->LOAD |= (u32ChannelMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger synchronous event from specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are 0, 2, 4
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to trigger synchronous event from specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_TRIGGER_SYNC(pwm, u32ChannelNum) ((pwm)->SWSYNC |= (1U << ((u32ChannelNum) >> 1U)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear counter of specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to clear counter of specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_CLR_COUNTER(pwm, u32ChannelMask) ((pwm)->CNTCLR |= (u32ChannelMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set output level at zero, compare up, period(center) and compare down of specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 1...
|
||||||
|
* @param[in] u32ZeroLevel output level at zero point, valid values are:
|
||||||
|
* - \ref PWM_OUTPUT_NOTHING
|
||||||
|
* - \ref PWM_OUTPUT_LOW
|
||||||
|
* - \ref PWM_OUTPUT_HIGH
|
||||||
|
* - \ref PWM_OUTPUT_TOGGLE
|
||||||
|
* @param[in] u32CmpUpLevel output level at compare up point, valid values are:
|
||||||
|
* - \ref PWM_OUTPUT_NOTHING
|
||||||
|
* - \ref PWM_OUTPUT_LOW
|
||||||
|
* - \ref PWM_OUTPUT_HIGH
|
||||||
|
* - \ref PWM_OUTPUT_TOGGLE
|
||||||
|
* @param[in] u32PeriodLevel output level at period(center) point, valid values are:
|
||||||
|
* - \ref PWM_OUTPUT_NOTHING
|
||||||
|
* - \ref PWM_OUTPUT_LOW
|
||||||
|
* - \ref PWM_OUTPUT_HIGH
|
||||||
|
* - \ref PWM_OUTPUT_TOGGLE
|
||||||
|
* @param[in] u32CmpDownLevel output level at compare down point, valid values are:
|
||||||
|
* - \ref PWM_OUTPUT_NOTHING
|
||||||
|
* - \ref PWM_OUTPUT_LOW
|
||||||
|
* - \ref PWM_OUTPUT_HIGH
|
||||||
|
* - \ref PWM_OUTPUT_TOGGLE
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to Set output level at zero, compare up, period(center) and compare down of specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_OUTPUT_LEVEL(pwm, u32ChannelMask, u32ZeroLevel, u32CmpUpLevel, u32PeriodLevel, u32CmpDownLevel) \
|
||||||
|
do{ \
|
||||||
|
int i; \
|
||||||
|
for(i = 0U; i < 6U; i++) { \
|
||||||
|
if((u32ChannelMask) & (1 << i)) { \
|
||||||
|
(pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (i << 1))) | ((u32ZeroLevel) << (i << 1U))); \
|
||||||
|
(pwm)->WGCTL0 = (((pwm)->WGCTL0 & ~(3UL << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1U)))) | ((u32PeriodLevel) << (PWM_WGCTL0_PRDPCTL0_Pos + (i << 1U)))); \
|
||||||
|
(pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (i << 1U))) | ((u32CmpUpLevel) << (i << 1U))); \
|
||||||
|
(pwm)->WGCTL1 = (((pwm)->WGCTL1 & ~(3UL << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1U)))) | ((u32CmpDownLevel) << (PWM_WGCTL1_CMPDCTL0_Pos + (i << 1U)))); \
|
||||||
|
} \
|
||||||
|
} \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger brake event from specified channel(s)
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel
|
||||||
|
* Bit 0 represents channel 0, bit 1 represents channel 2 and bit 2 represents channel 4
|
||||||
|
* @param[in] u32BrakeType Type of brake trigger.
|
||||||
|
* - \ref PWM_FB_EDGE
|
||||||
|
* - \ref PWM_FB_LEVEL
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to trigger brake event from specified channel(s).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_TRIGGER_BRAKE(pwm, u32ChannelMask, u32BrakeType) ((pwm)->SWBRK |= ((u32ChannelMask) << (u32BrakeType)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Dead zone clock source
|
||||||
|
* @param[in] pwm The pointer of the specified PWM module
|
||||||
|
* @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5
|
||||||
|
* @param[in] u32AfterPrescaler Dead zone clock source is from prescaler output. Valid values are TRUE (after prescaler) or FALSE (before prescaler).
|
||||||
|
* @return None
|
||||||
|
* @details This macro is used to set Dead zone clock source. Every two channels share the same setting.
|
||||||
|
* @note The write-protection function should be disabled before using this function.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define PWM_SET_DEADZONE_CLK_SRC(pwm, u32ChannelNum, u32AfterPrescaler) \
|
||||||
|
(*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1U)) = (*(__IO uint32_t *) (&((pwm)->DTCTL0_1) + ((u32ChannelNum) >> 1U)) & ~PWM_DTCTL0_1_DTCKSEL_Msk) | \
|
||||||
|
((u32AfterPrescaler) << PWM_DTCTL0_1_DTCKSEL_Pos))
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Define PWM functions prototype */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
uint32_t PWM_ConfigCaptureChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge);
|
||||||
|
uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Frequency, uint32_t u32DutyCycle);
|
||||||
|
void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||||
|
void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||||
|
uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||||
|
void PWM_DisableDACTrigger(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition);
|
||||||
|
uint32_t PWM_GetDACTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableFaultBrake(PWM_T *pwm, uint32_t u32ChannelMask, uint32_t u32LevelMask, uint32_t u32BrakeSource);
|
||||||
|
void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_EnablePDMA(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32RisingFirst, uint32_t u32Mode);
|
||||||
|
void PWM_DisablePDMA(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration);
|
||||||
|
void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||||
|
void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||||
|
void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge);
|
||||||
|
uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType);
|
||||||
|
void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||||
|
void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||||
|
void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||||
|
uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource);
|
||||||
|
void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType);
|
||||||
|
void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_DisableZeroInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t PWM_GetZeroIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableAcc(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntFlagCnt, uint32_t u32IntAccSrc);
|
||||||
|
void PWM_DisableAcc(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_DisableAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t PWM_GetAccInt(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
uint32_t PWM_GetFTDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_EnableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||||
|
void PWM_DisableLoadMode(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32LoadMode);
|
||||||
|
void PWM_ConfigSyncPhase(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32SyncSrc, uint32_t u32Direction, uint32_t u32StartPhase);
|
||||||
|
void PWM_EnableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_DisableSyncPhase(PWM_T *pwm, uint32_t u32ChannelMask);
|
||||||
|
void PWM_EnableSyncNoiseFilter(PWM_T *pwm, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
|
||||||
|
void PWM_DisableSyncNoiseFilter(PWM_T *pwm);
|
||||||
|
void PWM_EnableSyncPinInverse(PWM_T *pwm);
|
||||||
|
void PWM_DisableSyncPinInverse(PWM_T *pwm);
|
||||||
|
void PWM_SetClockSource(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32ClkSrcSel);
|
||||||
|
void PWM_EnableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32ClkCnt, uint32_t u32ClkDivSel);
|
||||||
|
void PWM_DisableBrakeNoiseFilter(PWM_T *pwm, uint32_t u32BrakePinNum);
|
||||||
|
void PWM_EnableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
|
||||||
|
void PWM_DisableBrakePinInverse(PWM_T *pwm, uint32_t u32BrakePinNum);
|
||||||
|
void PWM_SetBrakePinSource(PWM_T *pwm, uint32_t u32BrakePinNum, uint32_t u32SelAnotherModule);
|
||||||
|
void PWM_SetLeadingEdgeBlanking(PWM_T *pwm, uint32_t u32TrigSrcSel, uint32_t u32TrigTyp, uint32_t u32BlankingCnt, uint32_t u32BlankingEnable);
|
||||||
|
uint32_t PWM_GetWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
void PWM_ClearWrapAroundFlag(PWM_T *pwm, uint32_t u32ChannelNum);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PWM_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group PWM_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__PWM_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,138 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file qei.c
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 2 $
|
||||||
|
* $Date: 16/09/01 9:33a $
|
||||||
|
* @brief Quadrature Encoder Interface (QEI) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup QEI_Driver QEI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Close QEI function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This function reset QEI configuration and stop QEI counting.
|
||||||
|
*/
|
||||||
|
void QEI_Close(QEI_T* qei)
|
||||||
|
{
|
||||||
|
/* Reset QEI configuration */
|
||||||
|
qei->CTL = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI interrupt
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32IntSel Interrupt type selection.
|
||||||
|
* - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
|
||||||
|
* - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
|
||||||
|
* - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
|
||||||
|
* - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
|
||||||
|
* @return None
|
||||||
|
* @details This function disable QEI specified interrupt.
|
||||||
|
*/
|
||||||
|
void QEI_DisableInt(QEI_T* qei, uint32_t u32IntSel)
|
||||||
|
{
|
||||||
|
/* Disable QEI specified interrupt */
|
||||||
|
QEI_DISABLE_INT(qei, u32IntSel);
|
||||||
|
|
||||||
|
/* Disable NVIC QEI IRQ */
|
||||||
|
if(qei == QEI0)
|
||||||
|
NVIC_DisableIRQ(QEI0_IRQn);
|
||||||
|
else
|
||||||
|
NVIC_DisableIRQ(QEI1_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI interrupt
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32IntSel Interrupt type selection.
|
||||||
|
* - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
|
||||||
|
* - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
|
||||||
|
* - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
|
||||||
|
* - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
|
||||||
|
* @return None
|
||||||
|
* @details This function enable QEI specified interrupt.
|
||||||
|
*/
|
||||||
|
void QEI_EnableInt(QEI_T* qei, uint32_t u32IntSel)
|
||||||
|
{
|
||||||
|
/* Enable QEI specified interrupt */
|
||||||
|
QEI_ENABLE_INT(qei, u32IntSel);
|
||||||
|
|
||||||
|
/* Enable NVIC QEI IRQ */
|
||||||
|
if(qei == QEI0)
|
||||||
|
NVIC_EnableIRQ(QEI0_IRQn);
|
||||||
|
else
|
||||||
|
NVIC_EnableIRQ(QEI1_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Open QEI in specified mode and enable input
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Mode QEI counting mode.
|
||||||
|
* - \ref QEI_CTL_X4_FREE_COUNTING_MODE
|
||||||
|
* - \ref QEI_CTL_X2_FREE_COUNTING_MODE
|
||||||
|
* - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
|
||||||
|
* - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
|
||||||
|
* @param[in] u32Value The counter maximum value in compare-counting mode.
|
||||||
|
* @return None
|
||||||
|
* @details This function set QEI in specified mode and enable input.
|
||||||
|
*/
|
||||||
|
void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value)
|
||||||
|
{
|
||||||
|
/* Set QEI function configuration */
|
||||||
|
/* Set QEI counting mode */
|
||||||
|
/* Enable IDX, QEA and QEB input to QEI controller */
|
||||||
|
qei->CTL = (qei->CTL & (~QEI_CTL_MODE_Msk)) | ((u32Mode) | QEI_CTL_CHAEN_Msk | QEI_CTL_CHBEN_Msk | QEI_CTL_IDXEN_Msk);
|
||||||
|
|
||||||
|
/* Set QEI maximum count value in in compare-counting mode */
|
||||||
|
qei->CNTMAX = u32Value;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start QEI function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This function enable QEI function and start QEI counting.
|
||||||
|
*/
|
||||||
|
void QEI_Start(QEI_T* qei)
|
||||||
|
{
|
||||||
|
/* Enable QEI controller function */
|
||||||
|
qei->CTL |= QEI_CTL_QEIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop QEI function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This function disable QEI function and stop QEI counting.
|
||||||
|
*/
|
||||||
|
void QEI_Stop(QEI_T* qei)
|
||||||
|
{
|
||||||
|
/* Disable QEI controller function */
|
||||||
|
qei->CTL &= (~QEI_CTL_QEIEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group QEI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,363 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file qei.h
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/08/05 4:52p $
|
||||||
|
* @brief Quadrature Encoder Interface (QEI) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2014 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __QEI_H__
|
||||||
|
#define __QEI_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup QEI_Driver QEI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup QEI_EXPORTED_CONSTANTS QEI Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* QEI counting mode selection constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define QEI_CTL_X4_FREE_COUNTING_MODE (0x0<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 free-counting mode */
|
||||||
|
#define QEI_CTL_X2_FREE_COUNTING_MODE (0x1<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 free-counting mode */
|
||||||
|
#define QEI_CTL_X4_COMPARE_COUNTING_MODE (0x2<<QEI_CTL_MODE_Pos) /*!< QEI operate in X4 compare-counting mode */
|
||||||
|
#define QEI_CTL_X2_COMPARE_COUNTING_MODE (0x3<<QEI_CTL_MODE_Pos) /*!< QEI operate in X2 compare-counting mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* QEI noise filter clock pre-divide selection constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define QEI_CTL_NFCLKSEL_QEI_CLK_DIV1 (0x0<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK */
|
||||||
|
#define QEI_CTL_NFCLKSEL_QEI_CLK_DIV2 (0x1<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/2 */
|
||||||
|
#define QEI_CTL_NFCLKSEL_QEI_CLK_DIV4 (0x2<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/4 */
|
||||||
|
#define QEI_CTL_NFCLKSEL_QEI_CLK_DIV16 (0x3<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 */
|
||||||
|
#define QEI_CTL_NFCLKSEL_QEI_CLK_DIV32 (0x4<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 */
|
||||||
|
#define QEI_CTL_NFCLKSEL_QEI_CLK_DIV64 (0x5<<QEI_CTL_NFCLKSEL_Pos) /*!< The sampling frequency of the noise filter is QEI_CLK/16 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group QEI_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup QEI_EXPORTED_FUNCTIONS QEI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear QEI interrupt flag
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32IntSel Interrupt type selection.
|
||||||
|
* - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag
|
||||||
|
* - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag
|
||||||
|
* - \ref QEI_STATUS_CMPF_Msk : Compare-match flag
|
||||||
|
* - \ref QEI_STATUS_IDXF_Msk : Index detected flag
|
||||||
|
* @return None
|
||||||
|
* @details This macro clear QEI specified interrupt flag.
|
||||||
|
*/
|
||||||
|
#define QEI_CLR_INT_FLAG(qei, u32IntSel) ((qei)->STATUS = (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI compare function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable QEI counter compare function.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_CNT_CMP(qei) ((qei)->CTL &= (~QEI_CTL_CMPEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI compare function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro enable QEI counter compare function.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_CNT_CMP(qei) ((qei)->CTL |= QEI_CTL_CMPEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI index latch function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable QEI index trigger counter latch function.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_INDEX_LATCH(qei) ((qei)->CTL &= (~QEI_CTL_IDXLATEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI index latch function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro enable QEI index trigger counter latch function.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_INDEX_LATCH(qei) ((qei)->CTL |= QEI_CTL_IDXLATEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI index reload function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable QEI index trigger counter reload function.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_INDEX_RELOAD(qei) ((qei)->CTL &= (~QEI_CTL_IDXRLDEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI index reload function
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro enable QEI index trigger counter reload function.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_INDEX_RELOAD(qei) ((qei)->CTL |= QEI_CTL_IDXRLDEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI input
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32InputType Input signal type.
|
||||||
|
* - \ref QEI_CTL_CHAEN_Msk : QEA input
|
||||||
|
* - \ref QEI_CTL_CHAEN_Msk : QEB input
|
||||||
|
* - \ref QEI_CTL_IDXEN_Msk : IDX input
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable specified QEI signal input.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_INPUT(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI input
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32InputType Input signal type .
|
||||||
|
* - \ref QEI_CTL_CHAEN_Msk : QEA input
|
||||||
|
* - \ref QEI_CTL_CHBEN_Msk : QEB input
|
||||||
|
* - \ref QEI_CTL_IDXEN_Msk : IDX input
|
||||||
|
* @return None
|
||||||
|
* @details This macro enable specified QEI signal input.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_INPUT(qei, u32InputType) ((qei)->CTL |= (u32InputType))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable inverted input polarity
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32InputType Input signal type .
|
||||||
|
* - \ref QEI_CTL_CHAINV_Msk : QEA Input
|
||||||
|
* - \ref QEI_CTL_CHBINV_Msk : QEB Input
|
||||||
|
* - \ref QEI_CTL_IDXINV_Msk : IDX Input
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable specified QEI signal inverted input polarity.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL &= ~(u32InputType))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable inverted input polarity
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32InputType Input signal type.
|
||||||
|
* - \ref QEI_CTL_CHAINV_Msk : QEA Input
|
||||||
|
* - \ref QEI_CTL_CHBINV_Msk : QEB Input
|
||||||
|
* - \ref QEI_CTL_IDXINV_Msk : IDX Input
|
||||||
|
* @return None
|
||||||
|
* @details This macro inverse specified QEI signal input polarity.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_INPUT_INV(qei, u32InputType) ((qei)->CTL |= (u32InputType))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI interrupt
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32IntSel Interrupt type selection.
|
||||||
|
* - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
|
||||||
|
* - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
|
||||||
|
* - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
|
||||||
|
* - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable specified QEI interrupt.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_INT(qei, u32IntSel) ((qei)->CTL &= ~(u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI interrupt
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32IntSel Interrupt type selection.
|
||||||
|
* - \ref QEI_CTL_DIRIEN_Msk : Direction change interrupt
|
||||||
|
* - \ref QEI_CTL_OVUNIEN_Msk : Counter overflow or underflow interrupt
|
||||||
|
* - \ref QEI_CTL_CMPIEN_Msk : Compare-match interrupt
|
||||||
|
* - \ref QEI_CTL_IDXIEN_Msk : Index detected interrupt
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable specified QEI interrupt.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_INT(qei, u32IntSel) ((qei)->CTL |= (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI noise filter
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro disable QEI noise filter function.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_NOISE_FILTER(qei) ((qei)->CTL |= QEI_CTL_NFDIS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI noise filter
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32ClkSel The sampling frequency of the noise filter clock.
|
||||||
|
* - \ref QEI_CTL_NFCLKSEL_QEI_CLK_DIV1
|
||||||
|
* - \ref QEI_CTL_NFCLKSEL_QEI_CLK_DIV2
|
||||||
|
* - \ref QEI_CTL_NFCLKSEL_QEI_CLK_DIV4
|
||||||
|
* - \ref QEI_CTL_NFCLKSEL_QEI_CLK_DIV16
|
||||||
|
* - \ref QEI_CTL_NFCLKSEL_QEI_CLK_DIV32
|
||||||
|
* - \ref QEI_CTL_NFCLKSEL_QEI_CLK_DIV64
|
||||||
|
* @return None
|
||||||
|
* @details This macro enable QEI noise filter function and select noise filter clock.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_NOISE_FILTER(qei, u32ClkSel) ((qei)->CTL = ((qei)->CTL & (~(QEI_CTL_NFDIS_Msk|QEI_CTL_NFCLKSEL_Msk))) | (u32ClkSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get QEI counter value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return QEI pulse counter register value.
|
||||||
|
* @details This macro get QEI pulse counter value.
|
||||||
|
*/
|
||||||
|
#define QEI_GET_CNT_VALUE(qei) ((qei)->CNT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get QEI counting direction
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @retval 0 QEI counter is in down-counting.
|
||||||
|
* @retval 1 QEI counter is in up-counting.
|
||||||
|
* @details This macro get QEI counting direction.
|
||||||
|
*/
|
||||||
|
#define QEI_GET_DIR(qei) (((qei)->STATUS & (QEI_STATUS_DIRF_Msk))?1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get QEI counter hold value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return QEI pulse counter hold register value.
|
||||||
|
* @details This macro get QEI pulse counter hold value, which is updated with counter value in hold counter value control.
|
||||||
|
*/
|
||||||
|
#define QEI_GET_HOLD_VALUE(qei) ((qei)->CNTHOLD)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get QEI counter index latch value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return QEI pulse counter index latch value
|
||||||
|
* @details This macro get QEI pulse counter index latch value, which is updated with counter value when the index is detected.
|
||||||
|
*/
|
||||||
|
#define QEI_GET_INDEX_LATCH_VALUE(qei) ((qei)->CNTLATCH)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set QEI counter index latch value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @return QEI pulse counter index latch value
|
||||||
|
* @details This macro set QEI pulse counter index latch value, which is updated with counter value when the index is detected.
|
||||||
|
*/
|
||||||
|
#define QEI_SET_INDEX_LATCH_VALUE(qei,u32Val) ((qei)->CNTLATCH=u32Val)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get QEI interrupt flag status
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32IntSel Interrupt type selection.
|
||||||
|
* - \ref QEI_STATUS_DIRF_Msk : Counting direction flag
|
||||||
|
* - \ref QEI_STATUS_DIRCHGF_Msk : Direction change flag
|
||||||
|
* - \ref QEI_STATUS_OVUNF_Msk : Counter overflow or underflow flag
|
||||||
|
* - \ref QEI_STATUS_CMPF_Msk : Compare-match flag
|
||||||
|
* - \ref QEI_STATUS_IDXF_Msk : Index detected flag
|
||||||
|
* @retval 0 QEI specified interrupt flag is not set.
|
||||||
|
* @retval 1 QEI specified interrupt flag is set.
|
||||||
|
* @details This macro get QEI specified interrupt flag status.
|
||||||
|
*/
|
||||||
|
#define QEI_GET_INT_FLAG(qei, u32IntSel) (((qei)->STATUS & (u32IntSel))?1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set QEI counter compare value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Value The counter compare value.
|
||||||
|
* @return None
|
||||||
|
* @details This macro set QEI pulse counter compare value.
|
||||||
|
*/
|
||||||
|
#define QEI_SET_CNT_CMP(qei, u32Value) ((qei)->CNTCMP = (u32Value))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set QEI counter value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Value The counter compare value.
|
||||||
|
* @return None
|
||||||
|
* @details This macro set QEI pulse counter compare value.
|
||||||
|
*/
|
||||||
|
#define QEI_SET_CNT_VALUE(qei, u32Value) ((qei)->CNT = (u32Value))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable QEI counter hold mode
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Type The triggered type.
|
||||||
|
* - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control
|
||||||
|
* - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0
|
||||||
|
* - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1
|
||||||
|
* - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2
|
||||||
|
* - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3
|
||||||
|
* @return None
|
||||||
|
* @details This macro set QEI counter hold mode.
|
||||||
|
*/
|
||||||
|
#define QEI_ENABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL |= (u32Type))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable QEI counter hold mode
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Type The triggered type.
|
||||||
|
* - \ref QEI_CTL_HOLDCNT_Msk : Hold QEI_CNT control
|
||||||
|
* - \ref QEI_CTL_HOLDTMR0_Msk : Hold QEI_CNT by Timer0
|
||||||
|
* - \ref QEI_CTL_HOLDTMR1_Msk : Hold QEI_CNT by Timer1
|
||||||
|
* - \ref QEI_CTL_HOLDTMR2_Msk : Hold QEI_CNT by Timer2
|
||||||
|
* - \ref QEI_CTL_HOLDTMR3_Msk : Hold QEI_CNT by Timer3
|
||||||
|
* @return None
|
||||||
|
* @details This macro set QEI counter hold mode.
|
||||||
|
*/
|
||||||
|
#define QEI_DISABLE_HOLD_TRG_SRC(qei, u32Type) ((qei)->CTL &= ~(u32Type))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set QEI maximum count value
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Value The counter maximum value.
|
||||||
|
* @return QEI maximum count value
|
||||||
|
* @details This macro set QEI maximum count value.
|
||||||
|
*/
|
||||||
|
#define QEI_SET_CNT_MAX(qei, u32Value) ((qei)->CNTMAX = (u32Value))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set QEI counting mode
|
||||||
|
* @param[in] qei The pointer of the specified QEI module.
|
||||||
|
* @param[in] u32Mode QEI counting mode.
|
||||||
|
* - \ref QEI_CTL_X4_FREE_COUNTING_MODE
|
||||||
|
* - \ref QEI_CTL_X2_FREE_COUNTING_MODE
|
||||||
|
* - \ref QEI_CTL_X4_COMPARE_COUNTING_MODE
|
||||||
|
* - \ref QEI_CTL_X2_COMPARE_COUNTING_MODE
|
||||||
|
* @return None
|
||||||
|
* @details This macro set QEI counting mode.
|
||||||
|
*/
|
||||||
|
#define QEI_SET_CNT_MODE(qei, u32Mode) ((qei)->CTL = ((qei)->CTL & (~QEI_CTL_MODE_Msk)) | (u32Mode))
|
||||||
|
|
||||||
|
|
||||||
|
void QEI_Close(QEI_T* qei);
|
||||||
|
void QEI_DisableInt(QEI_T* qei, uint32_t u32eIntSel);
|
||||||
|
void QEI_EnableInt(QEI_T* qei, uint32_t u32eIntSel);
|
||||||
|
void QEI_Open(QEI_T* qei, uint32_t u32Mode, uint32_t u32Value);
|
||||||
|
void QEI_Start(QEI_T* qei);
|
||||||
|
void QEI_Stop(QEI_T* qei);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group QEI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group QEI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__QEI_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2014 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,428 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file rtc.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Real Time Clock(RTC) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __RTC_H__
|
||||||
|
#define __RTC_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC_Driver RTC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup RTC_EXPORTED_CONSTANTS RTC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* RTC Initial Keyword Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define RTC_INIT_KEY 0xA5EB1357UL /*!< RTC Initiation Key to make RTC leaving reset state */
|
||||||
|
#define RTC_WRITE_KEY 0x0000A965UL /*!< RTC Register Access Enable Key to enable RTC read/write accessible and kept 1024 RTC clock */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* RTC Time Attribute Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define RTC_CLOCK_12 0 /*!< RTC as 12-hour time scale with AM and PM indication */
|
||||||
|
#define RTC_CLOCK_24 1 /*!< RTC as 24-hour time scale */
|
||||||
|
#define RTC_AM 1 /*!< RTC as AM indication */
|
||||||
|
#define RTC_PM 2 /*!< RTC as PM indication */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* RTC Tick Period Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define RTC_TICK_1_SEC 0x0UL /*!< RTC time tick period is 1 second */
|
||||||
|
#define RTC_TICK_1_2_SEC 0x1UL /*!< RTC time tick period is 1/2 second */
|
||||||
|
#define RTC_TICK_1_4_SEC 0x2UL /*!< RTC time tick period is 1/4 second */
|
||||||
|
#define RTC_TICK_1_8_SEC 0x3UL /*!< RTC time tick period is 1/8 second */
|
||||||
|
#define RTC_TICK_1_16_SEC 0x4UL /*!< RTC time tick period is 1/16 second */
|
||||||
|
#define RTC_TICK_1_32_SEC 0x5UL /*!< RTC time tick period is 1/32 second */
|
||||||
|
#define RTC_TICK_1_64_SEC 0x6UL /*!< RTC time tick period is 1/64 second */
|
||||||
|
#define RTC_TICK_1_128_SEC 0x7UL /*!< RTC time tick period is 1/128 second */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* RTC Day of Week Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define RTC_SUNDAY 0x0UL /*!< Day of the Week is Sunday */
|
||||||
|
#define RTC_MONDAY 0x1UL /*!< Day of the Week is Monday */
|
||||||
|
#define RTC_TUESDAY 0x2UL /*!< Day of the Week is Tuesday */
|
||||||
|
#define RTC_WEDNESDAY 0x3UL /*!< Day of the Week is Wednesday */
|
||||||
|
#define RTC_THURSDAY 0x4UL /*!< Day of the Week is Thursday */
|
||||||
|
#define RTC_FRIDAY 0x5UL /*!< Day of the Week is Friday */
|
||||||
|
#define RTC_SATURDAY 0x6UL /*!< Day of the Week is Saturday */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* RTC Miscellaneous Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define RTC_YEAR2000 2000 /*!< RTC Reference for compute year data */
|
||||||
|
|
||||||
|
#define RTC_TAMPER0_SELECT (0x1 << 0) /*!< Select Tamper 0 */
|
||||||
|
#define RTC_TAMPER1_SELECT (0x1 << 1) /*!< Select Tamper 1 */
|
||||||
|
#define RTC_TAMPER2_SELECT (0x1 << 2) /*!< Select Tamper 2 */
|
||||||
|
#define RTC_TAMPER3_SELECT (0x1 << 3) /*!< Select Tamper 3 */
|
||||||
|
#define RTC_TAMPER4_SELECT (0x1 << 4) /*!< Select Tamper 4 */
|
||||||
|
#define RTC_TAMPER5_SELECT (0x1 << 5) /*!< Select Tamper 5 */
|
||||||
|
#define MAX_TAMPER_PIN_NUM 6 /*!< Tamper Pin number */
|
||||||
|
|
||||||
|
#define RTC_TAMPER_HIGH_LEVEL_DETECT 1 /*!< Tamper pin detect voltage level is high */
|
||||||
|
#define RTC_TAMPER_LOW_LEVEL_DETECT 0 /*!< Tamper pin detect voltage level is low */
|
||||||
|
|
||||||
|
#define RTC_TAMPER_DEBOUNCE_ENABLE 1 /*!< Enable RTC tamper pin de-bounce function */
|
||||||
|
#define RTC_TAMPER_DEBOUNCE_DISABLE 0 /*!< Disable RTC tamper pin de-bounce function */
|
||||||
|
|
||||||
|
#define RTC_PAIR0_SELECT (0x1 << 0) /*!< Select Pair 0 */
|
||||||
|
#define RTC_PAIR1_SELECT (0x1 << 1) /*!< Select Pair 1 */
|
||||||
|
#define RTC_PAIR2_SELECT (0x1 << 2) /*!< Select Pair 2 */
|
||||||
|
#define MAX_PAIR_NUM 3 /*!< Pair number */
|
||||||
|
|
||||||
|
#define RTC_2POW10_CLK (0x0 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 RTC clock cycles */
|
||||||
|
#define RTC_2POW11_CLK (0x1 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 2 RTC clock cycles */
|
||||||
|
#define RTC_2POW12_CLK (0x2 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 4 RTC clock cycles */
|
||||||
|
#define RTC_2POW13_CLK (0x3 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 6 RTC clock cycles */
|
||||||
|
#define RTC_2POW14_CLK (0x4 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 8 RTC clock cycles */
|
||||||
|
#define RTC_2POW15_CLK (0x5 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 16 RTC clock cycles */
|
||||||
|
#define RTC_2POW16_CLK (0x6 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 32 RTC clock cycles */
|
||||||
|
#define RTC_2POW17_CLK (0x7 << RTC_TAMPCTL_DYNRATE_Pos) /*!< 1024 x 64 RTC clock cycles */
|
||||||
|
|
||||||
|
#define REF_RANDOM_PATTERN 0x0 /*!< The new reference pattern is generated by random number generator when the reference pattern run out */
|
||||||
|
#define REF_PREVIOUS_PATTERN 0x1 /*!< The new reference pattern is repeated previous random value when the reference pattern run out */
|
||||||
|
#define REF_SEED 0x3 /*!< The new reference pattern is repeated from SEED (RTC_TAMPSEED[31:0]) when the reference pattern run out */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group RTC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup RTC_EXPORTED_STRUCTS RTC Exported Structs
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @details RTC define Time Data Struct
|
||||||
|
*/
|
||||||
|
typedef struct
|
||||||
|
{
|
||||||
|
uint32_t u32Year; /*!< Year value */
|
||||||
|
uint32_t u32Month; /*!< Month value */
|
||||||
|
uint32_t u32Day; /*!< Day value */
|
||||||
|
uint32_t u32DayOfWeek; /*!< Day of week value */
|
||||||
|
uint32_t u32Hour; /*!< Hour value */
|
||||||
|
uint32_t u32Minute; /*!< Minute value */
|
||||||
|
uint32_t u32Second; /*!< Second value */
|
||||||
|
uint32_t u32TimeScale; /*!< 12-Hour, 24-Hour */
|
||||||
|
uint32_t u32AmPm; /*!< Only Time Scale select 12-hr used */
|
||||||
|
} S_RTC_TIME_DATA_T;
|
||||||
|
|
||||||
|
/*@}*/ /* end of group RTC_EXPORTED_STRUCTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup RTC_EXPORTED_FUNCTIONS RTC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Indicate is Leap Year or not
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 This year is not a leap year
|
||||||
|
* @retval 1 This year is a leap year
|
||||||
|
*
|
||||||
|
* @details According to current date, return this year is leap year or not.
|
||||||
|
*/
|
||||||
|
#define RTC_IS_LEAP_YEAR() (RTC->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
|
||||||
|
/**
|
||||||
|
* @brief Indicate is Leap Year or not Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_IS_LEAP_YEAR_NS() (RTC_NS->LEAPYEAR & RTC_LEAPYEAR_LEAPYEAR_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear RTC Alarm Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear RTC alarm interrupt flag.
|
||||||
|
*/
|
||||||
|
#define RTC_CLEAR_ALARM_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_ALMIF_Msk)
|
||||||
|
/**
|
||||||
|
* @brief Clear RTC Alarm Interrupt Flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_CLEAR_ALARM_INT_FLAG_NS() (RTC_NS->INTSTS = RTC_INTSTS_ALMIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear RTC Tick Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear RTC tick interrupt flag.
|
||||||
|
*/
|
||||||
|
#define RTC_CLEAR_TICK_INT_FLAG() (RTC->INTSTS = RTC_INTSTS_TICKIF_Msk)
|
||||||
|
/**
|
||||||
|
* @brief Clear RTC Tick Interrupt Flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_CLEAR_TICK_INT_FLAG_NS() (RTC_NS->INTSTS = RTC_INTSTS_TICKIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear RTC Tamper Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param u32TamperFlag Tamper interrupt flag. It consists of: \n
|
||||||
|
* - \ref RTC_INTSTS_TAMP0IF_Msk \n
|
||||||
|
* - \ref RTC_INTSTS_TAMP1IF_Msk \n
|
||||||
|
* - \ref RTC_INTSTS_TAMP2IF_Msk \n
|
||||||
|
* - \ref RTC_INTSTS_TAMP3IF_Msk \n
|
||||||
|
* - \ref RTC_INTSTS_TAMP4IF_Msk \n
|
||||||
|
* - \ref RTC_INTSTS_TAMP5IF_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear RTC tamper pin interrupt flag.
|
||||||
|
*/
|
||||||
|
#define RTC_CLEAR_TAMPER_INT_FLAG(u32TamperFlag) (RTC->INTSTS = (u32TamperFlag))
|
||||||
|
/**
|
||||||
|
* @brief Clear RTC Tamper Interrupt Flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_CLEAR_TAMPER_INT_FLAG_NS(u32TamperFlag) (RTC_NS->INTSTS = (u32TamperFlag))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Alarm Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 RTC alarm interrupt did not occur
|
||||||
|
* @retval 1 RTC alarm interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates RTC alarm interrupt occurred or not.
|
||||||
|
*/
|
||||||
|
#define RTC_GET_ALARM_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Alarm Interrupt Flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_GET_ALARM_INT_FLAG_NS() ((RTC_NS->INTSTS & RTC_INTSTS_ALMIF_Msk)? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Time Tick Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 RTC time tick interrupt did not occur
|
||||||
|
* @retval 1 RTC time tick interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates RTC time tick interrupt occurred or not.
|
||||||
|
*/
|
||||||
|
#define RTC_GET_TICK_INT_FLAG() ((RTC->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Time Tick Interrupt Flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_GET_TICK_INT_FLAG_NS() ((RTC_NS->INTSTS & RTC_INTSTS_TICKIF_Msk)? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Tamper Interrupt Status
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 RTC tamper event interrupt did not occur
|
||||||
|
* @retval 1 RTC tamper event interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates RTC tamper event occurred or not.
|
||||||
|
*/
|
||||||
|
#define RTC_GET_TAMPER_INT_STATUS() ((RTC->INTSTS & (0x3F00))? 1:0)
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Tamper Interrupt Status Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_GET_TAMPER_INT_STATUS_NS() ((RTC_NS->INTSTS & (0x3F00))? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Tamper Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval RTC_INTSTS_TAMP0IF_Msk Tamper 0 interrupt flag is generated
|
||||||
|
* @retval RTC_INTSTS_TAMP1IF_Msk Tamper 1 interrupt flag is generated
|
||||||
|
* @retval RTC_INTSTS_TAMP2IF_Msk Tamper 2 interrupt flag is generated
|
||||||
|
* @retval RTC_INTSTS_TAMP3IF_Msk Tamper 3 interrupt flag is generated
|
||||||
|
* @retval RTC_INTSTS_TAMP4IF_Msk Tamper 4 interrupt flag is generated
|
||||||
|
* @retval RTC_INTSTS_TAMP5IF_Msk Tamper 5 interrupt flag is generated
|
||||||
|
*
|
||||||
|
* @details This macro indicates RTC tamper interrupt flags.
|
||||||
|
*/
|
||||||
|
#define RTC_GET_TAMPER_INT_FLAG() ((RTC->INTSTS & (0x3F00)))
|
||||||
|
/**
|
||||||
|
* @brief Get RTC Tamper Interrupt Flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_GET_TAMPER_INT_FLAG_NS() ((RTC_NS->INTSTS & (0x3F00)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable RTC Tick Wake-up Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable RTC tick interrupt wake-up function.
|
||||||
|
*/
|
||||||
|
#define RTC_ENABLE_TICK_WAKEUP() (RTC->INTEN |= RTC_INTEN_TICKIEN_Msk);
|
||||||
|
/**
|
||||||
|
* @brief Enable RTC Tick Wake-up Function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_ENABLE_TICK_WAKEUP_NS() (RTC_NS->INTEN |= RTC_INTEN_TICKIEN_Msk);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable RTC Tick Wake-up Function
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable RTC tick interrupt wake-up function.
|
||||||
|
*/
|
||||||
|
#define RTC_DISABLE_TICK_WAKEUP() (RTC->INTEN &= ~RTC_INTEN_TICKIEN_Msk);
|
||||||
|
/**
|
||||||
|
* @brief Disable RTC Tick Wake-up Function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_DISABLE_TICK_WAKEUP_NS() (RTC_NS->INTEN &= ~RTC_INTEN_TICKIEN_Msk);
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read Spare Register
|
||||||
|
*
|
||||||
|
* @param[in] u32RegNum The spare register number, 0~19.
|
||||||
|
*
|
||||||
|
* @return Spare register content
|
||||||
|
*
|
||||||
|
* @details Read the specify spare register content.
|
||||||
|
* @note The returned value is valid only when RWENF (RTC_RWEN[16]) bit is set. \n
|
||||||
|
* And its controlled by writing 0xA965 to RTC_RWEN[15:0](RTC Access Enable Register).
|
||||||
|
*/
|
||||||
|
#define RTC_READ_SPARE_REGISTER(u32RegNum) (RTC->SPR[(u32RegNum)])
|
||||||
|
/**
|
||||||
|
* @brief Read Spare Register Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_READ_SPARE_REGISTER_NS(u32RegNum) (RTC_NS->SPR[(u32RegNum)])
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write Spare Register
|
||||||
|
*
|
||||||
|
* @param[in] u32RegNum The spare register number, 0~19.
|
||||||
|
* @param[in] u32RegValue The spare register value.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Write specify data to spare register.
|
||||||
|
* @note This macro is effect only when RWENF (RTC_RWEN[16]) bit is set. \n
|
||||||
|
* And its controlled by writing 0xA965 to RTC_RWEN[15:0](RTC Access Enable Register).
|
||||||
|
*/
|
||||||
|
#define RTC_WRITE_SPARE_REGISTER(u32RegNum, u32RegValue) (RTC->SPR[(u32RegNum)] = (u32RegValue))
|
||||||
|
/**
|
||||||
|
* @brief Write Spare Register Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define RTC_WRITE_SPARE_REGISTER_NS(u32RegNum, u32RegValue) (RTC_NS->SPR[(u32RegNum)] = (u32RegValue))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait RTC Access Enable
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the maximum RTC read/write accessible time.
|
||||||
|
*/
|
||||||
|
static __INLINE void RTC_WaitAccessEnable(void)
|
||||||
|
{
|
||||||
|
/* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
|
||||||
|
RTC->RWEN = 0x0; // clear RWENF immediately
|
||||||
|
while(RTC->RWEN & RTC_RWEN_RWENF_Msk);
|
||||||
|
|
||||||
|
/* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
|
||||||
|
RTC->RWEN = RTC_WRITE_KEY;
|
||||||
|
while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0);
|
||||||
|
}
|
||||||
|
/**
|
||||||
|
* @brief Wait RTC Access Enable API for Non-Secure
|
||||||
|
*/
|
||||||
|
static __INLINE void RTC_WaitAccessEnable_NS(void)
|
||||||
|
{
|
||||||
|
/* To wait RWENF bit is cleared and enable RWENF bit (Access Enable bit) again */
|
||||||
|
RTC_NS->RWEN = 0x0; // clear RWENF immediately
|
||||||
|
while(RTC_NS->RWEN & RTC_RWEN_RWENF_Msk);
|
||||||
|
|
||||||
|
/* To wait RWENF bit is set and user can access the protected-register of RTC from now on */
|
||||||
|
RTC_NS->RWEN = RTC_WRITE_KEY;
|
||||||
|
while((RTC_NS->RWEN & RTC_RWEN_RWENF_Msk) == 0x0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void RTC_Open(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_Close(void);
|
||||||
|
void RTC_32KCalibration(int32_t i32FrequencyX10000);
|
||||||
|
void RTC_GetDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_GetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_SetDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_SetAlarmDateAndTime(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_SetDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
|
||||||
|
void RTC_SetTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||||
|
void RTC_SetAlarmDate(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
|
||||||
|
void RTC_SetAlarmTime(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||||
|
void RTC_SetAlarmDateMask(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
|
||||||
|
void RTC_SetAlarmTimeMask(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
|
||||||
|
uint32_t RTC_GetDayOfWeek(void);
|
||||||
|
void RTC_SetTickPeriod(uint32_t u32TickSelection);
|
||||||
|
void RTC_EnableInt(uint32_t u32IntFlagMask);
|
||||||
|
void RTC_DisableInt(uint32_t u32IntFlagMask);
|
||||||
|
void RTC_EnableSpareAccess(void);
|
||||||
|
void RTC_DisableSpareRegister(void);
|
||||||
|
void RTC_StaticTamperEnable(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
|
||||||
|
void RTC_StaticTamperDisable(uint32_t u32TamperSelect);
|
||||||
|
void RTC_DynamicTamperEnable(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
|
||||||
|
void RTC_DynamicTamperDisable(uint32_t u32PairSel);
|
||||||
|
void RTC_DynamicTamperConfig(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
|
||||||
|
|
||||||
|
void RTC_Open_NS(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_Close_NS(void);
|
||||||
|
void RTC_32KCalibration_NS(int32_t i32FrequencyX10000);
|
||||||
|
void RTC_GetDateAndTime_NS(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_GetAlarmDateAndTime_NS(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_SetDateAndTime_NS(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_SetAlarmDateAndTime_NS(S_RTC_TIME_DATA_T *sPt);
|
||||||
|
void RTC_SetDate_NS(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day, uint32_t u32DayOfWeek);
|
||||||
|
void RTC_SetTime_NS(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||||
|
void RTC_SetAlarmDate_NS(uint32_t u32Year, uint32_t u32Month, uint32_t u32Day);
|
||||||
|
void RTC_SetAlarmTime_NS(uint32_t u32Hour, uint32_t u32Minute, uint32_t u32Second, uint32_t u32TimeMode, uint32_t u32AmPm);
|
||||||
|
void RTC_SetAlarmDateMask_NS(uint8_t u8IsTenYMsk, uint8_t u8IsYMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenDMsk, uint8_t u8IsDMsk);
|
||||||
|
void RTC_SetAlarmTimeMaskv(uint8_t u8IsTenHMsk, uint8_t u8IsHMsk, uint8_t u8IsTenMMsk, uint8_t u8IsMMsk, uint8_t u8IsTenSMsk, uint8_t u8IsSMsk);
|
||||||
|
uint32_t RTC_GetDayOfWeek_NS(void);
|
||||||
|
void RTC_SetTickPeriod_NS(uint32_t u32TickSelection);
|
||||||
|
void RTC_EnableInt_NS(uint32_t u32IntFlagMask);
|
||||||
|
void RTC_DisableInt_NS(uint32_t u32IntFlagMask);
|
||||||
|
void RTC_EnableSpareAccess_NS(void);
|
||||||
|
void RTC_DisableSpareRegister_NS(void);
|
||||||
|
void RTC_StaticTamperEnable_NS(uint32_t u32TamperSelect, uint32_t u32DetecLevel, uint32_t u32DebounceEn);
|
||||||
|
void RTC_StaticTamperDisable_NS(uint32_t u32TamperSelect);
|
||||||
|
void RTC_DynamicTamperEnable_NS(uint32_t u32PairSel, uint32_t u32DebounceEn, uint32_t u32Pair1Source, uint32_t u32Pair2Source);
|
||||||
|
void RTC_DynamicTamperDisable_NS(uint32_t u32PairSel);
|
||||||
|
void RTC_DynamicTamperConfig_NS(uint32_t u32ChangeRate, uint32_t u32SeedReload, uint32_t u32RefPattern, uint32_t u32Seed);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group RTC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group RTC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __RTC_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,451 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file sc.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Smart Card(SC) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/* Below are variables used locally by SC driver and does not want to parse by doxygen unless HIDDEN_SYMBOLS is defined */
|
||||||
|
/** @cond HIDDEN_SYMBOLS */
|
||||||
|
static uint32_t u32CardStateIgnore[SC_INTERFACE_NUM] = {0UL, 0UL, 0UL};
|
||||||
|
|
||||||
|
/** @endcond HIDDEN_SYMBOLS */
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SC_Driver SC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Smartcard Slot Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval TRUE Card insert
|
||||||
|
* @retval FALSE Card remove
|
||||||
|
*
|
||||||
|
* @details This function is used to check if specified smartcard slot is presented.
|
||||||
|
*/
|
||||||
|
uint32_t SC_IsCardInserted(SC_T *sc)
|
||||||
|
{
|
||||||
|
uint32_t ret;
|
||||||
|
|
||||||
|
/* put conditions into two variable to remove IAR compilation warning */
|
||||||
|
uint32_t cond1 = ((sc->STATUS & SC_STATUS_CDPINSTS_Msk) >> SC_STATUS_CDPINSTS_Pos);
|
||||||
|
uint32_t cond2 = ((sc->CTL & SC_CTL_CDLV_Msk) >> SC_CTL_CDLV_Pos);
|
||||||
|
|
||||||
|
if(((sc == SC0) || (sc == SC0_NS)) && (u32CardStateIgnore[0] == 1UL))
|
||||||
|
{
|
||||||
|
ret = (uint32_t)TRUE;
|
||||||
|
}
|
||||||
|
else if(((sc == SC1) || (sc == SC1_NS)) && (u32CardStateIgnore[1] == 1UL))
|
||||||
|
{
|
||||||
|
ret = (uint32_t)TRUE;
|
||||||
|
}
|
||||||
|
else if(((sc == SC2) || (sc == SC2_NS)) && (u32CardStateIgnore[2] == 1UL))
|
||||||
|
{
|
||||||
|
ret = (uint32_t)TRUE;
|
||||||
|
}
|
||||||
|
else if(cond1 != cond2)
|
||||||
|
{
|
||||||
|
ret = (uint32_t)FALSE;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
ret = (uint32_t)TRUE;
|
||||||
|
}
|
||||||
|
|
||||||
|
return ret;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* @brief Reset the Tx/Rx FIFO
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function reset both transmit and receive FIFO of specified smartcard module.
|
||||||
|
*/
|
||||||
|
void SC_ClearFIFO(SC_T *sc)
|
||||||
|
{
|
||||||
|
while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified Smartcard
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details SC will force all transition to IDLE state.
|
||||||
|
*/
|
||||||
|
void SC_Close(SC_T *sc)
|
||||||
|
{
|
||||||
|
sc->INTEN = 0UL;
|
||||||
|
while(sc->PINCTL & SC_PINCTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->PINCTL = 0UL;
|
||||||
|
sc->ALTCTL = 0UL;
|
||||||
|
while(sc->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->CTL = 0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialized Smartcard
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32CD Card detect polarity, select the SC_CD pin state which indicates card insert. Could be:
|
||||||
|
* -\ref SC_PIN_STATE_HIGH
|
||||||
|
* -\ref SC_PIN_STATE_LOW
|
||||||
|
* -\ref SC_PIN_STATE_IGNORE, no card detect pin, always assumes card present.
|
||||||
|
* @param[in] u32PWR Power on polarity, select the SC_PWR pin state which could set smartcard VCC to high level. Could be:
|
||||||
|
* -\ref SC_PIN_STATE_HIGH
|
||||||
|
* -\ref SC_PIN_STATE_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Initialization process configures smartcard and enables engine clock.
|
||||||
|
*/
|
||||||
|
void SC_Open(SC_T *sc, uint32_t u32CD, uint32_t u32PWR)
|
||||||
|
{
|
||||||
|
uint32_t u32Reg = 0UL, u32Intf;
|
||||||
|
|
||||||
|
if((sc == SC0) || (sc == SC0_NS))
|
||||||
|
{
|
||||||
|
u32Intf = 0UL;
|
||||||
|
}
|
||||||
|
else if((sc == SC1) || (sc == SC1_NS))
|
||||||
|
{
|
||||||
|
u32Intf = 1UL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Intf = 2UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32CD != SC_PIN_STATE_IGNORE)
|
||||||
|
{
|
||||||
|
u32Reg = u32CD ? 0UL : SC_CTL_CDLV_Msk;
|
||||||
|
u32CardStateIgnore[u32Intf] = 0UL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32CardStateIgnore[u32Intf] = 1UL;
|
||||||
|
}
|
||||||
|
sc->PINCTL = u32PWR ? 0UL : SC_PINCTL_PWRINV_Msk;
|
||||||
|
while(sc->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->CTL = SC_CTL_SCEN_Msk | u32Reg;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset specified Smartcard
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Reset the Tx/Rx FIFO, clock and initial default parameter.
|
||||||
|
*/
|
||||||
|
void SC_ResetReader(SC_T *sc)
|
||||||
|
{
|
||||||
|
uint32_t u32Intf;
|
||||||
|
|
||||||
|
if((sc == SC0) || (sc == SC0_NS))
|
||||||
|
{
|
||||||
|
u32Intf = 0UL;
|
||||||
|
}
|
||||||
|
else if((sc == SC1) || (sc == SC1_NS))
|
||||||
|
{
|
||||||
|
u32Intf = 1UL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Intf = 2UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Reset FIFO, enable auto de-activation while card removal */
|
||||||
|
sc->ALTCTL |= (SC_ALTCTL_TXRST_Msk | SC_ALTCTL_RXRST_Msk | SC_ALTCTL_ADACEN_Msk);
|
||||||
|
/* Set Rx trigger level to 1 character, longest card detect debounce period, disable error retry (EMV ATR does not use error retry) */
|
||||||
|
while(sc->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->CTL &= ~(SC_CTL_RXTRGLV_Msk |
|
||||||
|
SC_CTL_CDDBSEL_Msk |
|
||||||
|
SC_CTL_TXRTY_Msk |
|
||||||
|
SC_CTL_TXRTYEN_Msk |
|
||||||
|
SC_CTL_RXRTY_Msk |
|
||||||
|
SC_CTL_RXRTYEN_Msk);
|
||||||
|
while(sc->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
/* Enable auto convention, and all three smartcard internal timers */
|
||||||
|
sc->CTL |= SC_CTL_AUTOCEN_Msk | SC_CTL_TMRSEL_Msk;
|
||||||
|
/* Disable Rx timeout */
|
||||||
|
sc->RXTOUT = 0UL;
|
||||||
|
/* 372 clocks per ETU by default */
|
||||||
|
sc->ETUCTL = 371UL;
|
||||||
|
|
||||||
|
/* Enable necessary interrupt for smartcard operation */
|
||||||
|
if(u32CardStateIgnore[u32Intf]) /* Do not enable card detect interrupt if card present state ignore */
|
||||||
|
{
|
||||||
|
sc->INTEN = (SC_INTEN_RDAIEN_Msk |
|
||||||
|
SC_INTEN_TERRIEN_Msk |
|
||||||
|
SC_INTEN_TMR0IEN_Msk |
|
||||||
|
SC_INTEN_TMR1IEN_Msk |
|
||||||
|
SC_INTEN_TMR2IEN_Msk |
|
||||||
|
SC_INTEN_BGTIEN_Msk |
|
||||||
|
SC_INTEN_ACERRIEN_Msk);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
sc->INTEN = (SC_INTEN_RDAIEN_Msk |
|
||||||
|
SC_INTEN_TERRIEN_Msk |
|
||||||
|
SC_INTEN_TMR0IEN_Msk |
|
||||||
|
SC_INTEN_TMR1IEN_Msk |
|
||||||
|
SC_INTEN_TMR2IEN_Msk |
|
||||||
|
SC_INTEN_BGTIEN_Msk |
|
||||||
|
SC_INTEN_ACERRIEN_Msk |
|
||||||
|
SC_INTEN_CDIEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Block Guard Time
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32BGT Block guard time using ETU as unit, valid range are between 1 ~ 32.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to configure block guard time (BGT) of specified smartcard module.
|
||||||
|
*/
|
||||||
|
void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT)
|
||||||
|
{
|
||||||
|
sc->CTL = (sc->CTL & ~SC_CTL_BGT_Msk) | ((u32BGT - 1UL) << SC_CTL_BGT_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Character Guard Time
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32CGT Character guard time using ETU as unit, valid range are between 11 ~ 267.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to configure character guard time (CGT) of specified smartcard module.
|
||||||
|
* @note Before using this API, user should set the correct stop bit length first.
|
||||||
|
*/
|
||||||
|
void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT)
|
||||||
|
{
|
||||||
|
/* CGT is "START bit" + "8-bits" + "Parity bit" + "STOP bit(s)" + "EGT counts" */
|
||||||
|
u32CGT -= sc->CTL & SC_CTL_NSB_Msk ? 11UL : 12UL;
|
||||||
|
sc->EGT = u32CGT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop all Timer Counting
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function stop all smartcard timer of specified smartcard module.
|
||||||
|
* @note This function stop the timers within smartcard module, \b not timer module.
|
||||||
|
*/
|
||||||
|
void SC_StopAllTimer(SC_T *sc)
|
||||||
|
{
|
||||||
|
while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->ALTCTL &= ~(SC_ALTCTL_CNTEN0_Msk | SC_ALTCTL_CNTEN1_Msk | SC_ALTCTL_CNTEN2_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure and Start specified Timer
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32TimerCh Specify time channel to start. Valid values are 0, 1, 2.
|
||||||
|
* @param[in] u32Mode Timer operating mode, valid values are:
|
||||||
|
* - \ref SC_TMR_MODE_0
|
||||||
|
* - \ref SC_TMR_MODE_1
|
||||||
|
* - \ref SC_TMR_MODE_2
|
||||||
|
* - \ref SC_TMR_MODE_3
|
||||||
|
* - \ref SC_TMR_MODE_4
|
||||||
|
* - \ref SC_TMR_MODE_5
|
||||||
|
* - \ref SC_TMR_MODE_6
|
||||||
|
* - \ref SC_TMR_MODE_7
|
||||||
|
* - \ref SC_TMR_MODE_8
|
||||||
|
* - \ref SC_TMR_MODE_F
|
||||||
|
* @param[in] u32ETUCount Timer timeout duration, ETU based. For timer 0, valid range are between 1 ~ 0x1000000 ETUs.
|
||||||
|
* For timer 1 and timer 2, valid range are between 1 ~ 0x100 ETUs.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable Timer starting, counter will count when condition match.
|
||||||
|
* @note This function start the timer within smartcard module, \b not timer module.
|
||||||
|
* @note Depend on the timer operating mode, timer may not start counting immediately.
|
||||||
|
*/
|
||||||
|
void SC_StartTimer(SC_T *sc, uint32_t u32TimerCh, uint32_t u32Mode, uint32_t u32ETUCount)
|
||||||
|
{
|
||||||
|
uint32_t reg = u32Mode | (SC_TMRCTL0_CNT_Msk & (u32ETUCount - 1UL));
|
||||||
|
while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
if(u32TimerCh == 0UL)
|
||||||
|
{
|
||||||
|
while(sc->TMRCTL0 & SC_TMRCTL0_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->TMRCTL0 = reg;
|
||||||
|
sc->ALTCTL |= SC_ALTCTL_CNTEN0_Msk;
|
||||||
|
}
|
||||||
|
else if(u32TimerCh == 1UL)
|
||||||
|
{
|
||||||
|
while(sc->TMRCTL1 & SC_TMRCTL1_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->TMRCTL1 = reg;
|
||||||
|
sc->ALTCTL |= SC_ALTCTL_CNTEN1_Msk;
|
||||||
|
}
|
||||||
|
else /* timer 2 */
|
||||||
|
{
|
||||||
|
while(sc->TMRCTL2 & SC_TMRCTL2_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
sc->TMRCTL2 = reg;
|
||||||
|
sc->ALTCTL |= SC_ALTCTL_CNTEN2_Msk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop specified Timer Counting
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32TimerCh Specify timer channel to stop. Valid values are 0, 1, 2.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function stop a smartcard timer of specified smartcard module.
|
||||||
|
* @note This function stop the timer within smartcard module, \b not timer module.
|
||||||
|
*/
|
||||||
|
void SC_StopTimer(SC_T *sc, uint32_t u32TimerCh)
|
||||||
|
{
|
||||||
|
while(sc->ALTCTL & SC_ALTCTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
if(u32TimerCh == 0UL) // timer 0
|
||||||
|
sc->ALTCTL &= ~SC_ALTCTL_CNTEN0_Msk;
|
||||||
|
else if(u32TimerCh == 1UL) // timer 1
|
||||||
|
sc->ALTCTL &= ~SC_ALTCTL_CNTEN1_Msk;
|
||||||
|
else // timer 2
|
||||||
|
sc->ALTCTL &= ~SC_ALTCTL_CNTEN2_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified Smartcard Clock Frequency
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return Smartcard frequency in kHZ
|
||||||
|
*
|
||||||
|
* @details This function is used to get specified smartcard module clock frequency in kHz.
|
||||||
|
*/
|
||||||
|
uint32_t SC_GetInterfaceClock(SC_T *sc)
|
||||||
|
{
|
||||||
|
uint32_t u32ClkSrc, u32Num, u32Clk, u32Div;
|
||||||
|
|
||||||
|
/* Get smartcard module clock source and divider */
|
||||||
|
if(sc == SC0)
|
||||||
|
{
|
||||||
|
u32Num = 0UL;
|
||||||
|
u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);
|
||||||
|
u32Div = CLK_GetModuleClockDivider(SC0_MODULE);
|
||||||
|
}
|
||||||
|
else if(sc == SC1)
|
||||||
|
{
|
||||||
|
u32Num = 1UL;
|
||||||
|
u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE);
|
||||||
|
u32Div = CLK_GetModuleClockDivider(SC1_MODULE);
|
||||||
|
}
|
||||||
|
else if(sc == SC2)
|
||||||
|
{
|
||||||
|
u32Num = 2UL;
|
||||||
|
u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE);
|
||||||
|
u32Div = CLK_GetModuleClockDivider(SC2_MODULE);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get smartcard module clock */
|
||||||
|
if(u32ClkSrc == 0UL)
|
||||||
|
{
|
||||||
|
u32Clk = __HXT;
|
||||||
|
}
|
||||||
|
else if(u32ClkSrc == 1UL)
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPLLClockFreq();
|
||||||
|
}
|
||||||
|
else if(u32ClkSrc == 2UL)
|
||||||
|
{
|
||||||
|
if(u32Num == 1UL)
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Clk = __HIRC;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32Clk /= (u32Div + 1UL) * 1000UL;
|
||||||
|
|
||||||
|
return u32Clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,318 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file sc.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Smart Card(SC) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __SC_H__
|
||||||
|
#define __SC_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SC_Driver SC Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SC_EXPORTED_CONSTANTS SC Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define SC_INTERFACE_NUM (3ul) /*!< Smartcard interface numbers \hideinitializer */
|
||||||
|
#define SC_PIN_STATE_HIGH (1ul) /*!< Smartcard pin status high \hideinitializer */
|
||||||
|
#define SC_PIN_STATE_LOW (0ul) /*!< Smartcard pin status low \hideinitializer */
|
||||||
|
#define SC_PIN_STATE_IGNORE (0xFFFFFFFFul) /*!< Ignore pin status \hideinitializer */
|
||||||
|
#define SC_CLK_ON (1ul) /*!< Smartcard clock on \hideinitializer */
|
||||||
|
#define SC_CLK_OFF (0ul) /*!< Smartcard clock off \hideinitializer */
|
||||||
|
|
||||||
|
#define SC_TMR_MODE_0 (0ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 0, down count \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_1 (1ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 1, down count, start after detect start bit \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_2 (2ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 2, down count, start after receive start bit \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_3 (3ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 3, down count, use for activation, only timer 0 support this mode \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_4 (4ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 4, down count with reload after timeout \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_5 (5ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 5, down count, start after detect start bit, reload after timeout \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_6 (6ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 6, down count, start after receive start bit, reload after timeout \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_7 (7ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 7, down count, start and reload after detect start bit \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_8 (8ul << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 8, up count \hideinitializer */
|
||||||
|
#define SC_TMR_MODE_F (0xF << SC_TMRCTL0_OPMODE_Pos) /*!<Timer Operation Mode 15, down count, reload after detect start bit \hideinitializer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SC_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SC_EXPORTED_FUNCTIONS SC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Smartcard Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Mask Interrupt mask to be enabled. A combination of
|
||||||
|
* - \ref SC_INTEN_ACERRIEN_Msk
|
||||||
|
* - \ref SC_INTEN_RXTOIEN_Msk
|
||||||
|
* - \ref SC_INTEN_INITIEN_Msk
|
||||||
|
* - \ref SC_INTEN_CDIEN_Msk
|
||||||
|
* - \ref SC_INTEN_BGTIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TMR2IEN_Msk
|
||||||
|
* - \ref SC_INTEN_TMR1IEN_Msk
|
||||||
|
* - \ref SC_INTEN_TMR0IEN_Msk
|
||||||
|
* - \ref SC_INTEN_TERRIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TBEIEN_Msk
|
||||||
|
* - \ref SC_INTEN_RDAIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to enable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
|
||||||
|
* Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
|
||||||
|
* Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Smartcard Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Mask Interrupt mask to be disabled. A combination of
|
||||||
|
* - \ref SC_INTEN_ACERRIEN_Msk
|
||||||
|
* - \ref SC_INTEN_RXTOIEN_Msk
|
||||||
|
* - \ref SC_INTEN_INITIEN_Msk
|
||||||
|
* - \ref SC_INTEN_CDIEN_Msk
|
||||||
|
* - \ref SC_INTEN_BGTIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TMR2IEN_Msk
|
||||||
|
* - \ref SC_INTEN_TMR1IEN_Msk
|
||||||
|
* - \ref SC_INTEN_TMR0IEN_Msk
|
||||||
|
* - \ref SC_INTEN_TERRIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TBEIEN_Msk
|
||||||
|
* - \ref SC_INTEN_RDAIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to disable Auto-convention error interrupt, Receiver buffer time-out interrupt, Initial end interrupt,
|
||||||
|
* Card detect interrupt, Block guard time interrupt, Timer2 interrupt, Timer1 interrupt, Timer0 interrupt,
|
||||||
|
* Transfer error interrupt, Transmit buffer empty interrupt or Receive data reach trigger level interrupt.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Smartcard Power Pin State
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32State Set pin state of power pin, valid parameters are:
|
||||||
|
* - \ref SC_PIN_STATE_HIGH
|
||||||
|
* - \ref SC_PIN_STATE_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details User can set PWREN (SC_PINCTL[0]) and PWRINV (SC_PINCTL[11]) to decide SC_PWR pin is in high or low level.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_SET_VCC_PIN(sc, u32State) \
|
||||||
|
do {\
|
||||||
|
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
|
||||||
|
if(u32State)\
|
||||||
|
(sc)->PINCTL |= SC_PINCTL_PWREN_Msk;\
|
||||||
|
else\
|
||||||
|
(sc)->PINCTL &= ~SC_PINCTL_PWREN_Msk;\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Smartcard Clock Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32OnOff Set clock on or off for selected smartcard module, valid values are:
|
||||||
|
* - \ref SC_CLK_ON
|
||||||
|
* - \ref SC_CLK_OFF
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details User can set CLKKEEP (SC_PINCTL[6]) to decide SC_CLK pin always keeps free running or not.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_SET_CLK_PIN(sc, u32OnOff)\
|
||||||
|
do {\
|
||||||
|
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
|
||||||
|
if(u32OnOff)\
|
||||||
|
(sc)->PINCTL |= SC_PINCTL_CLKKEEP_Msk;\
|
||||||
|
else\
|
||||||
|
(sc)->PINCTL &= ~(SC_PINCTL_CLKKEEP_Msk);\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Smartcard I/O Pin State
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32State Set pin state of I/O pin, valid parameters are:
|
||||||
|
* - \ref SC_PIN_STATE_HIGH
|
||||||
|
* - \ref SC_PIN_STATE_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details User can set SCDATA (SC_PINCTL[9]) to decide SC_DATA pin to high or low.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_SET_IO_PIN(sc, u32State)\
|
||||||
|
do {\
|
||||||
|
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
|
||||||
|
if(u32State)\
|
||||||
|
(sc)->PINCTL |= SC_PINCTL_SCDATA_Msk;\
|
||||||
|
else\
|
||||||
|
(sc)->PINCTL &= ~SC_PINCTL_SCDATA_Msk;\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Smartcard Reset Pin State
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32State Set pin state of reset pin, valid parameters are:
|
||||||
|
* - \ref SC_PIN_STATE_HIGH
|
||||||
|
* - \ref SC_PIN_STATE_LOW
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details User can set SCRST (SC_PINCTL[1]) to decide SC_RST pin to high or low.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_SET_RST_PIN(sc, u32State)\
|
||||||
|
do {\
|
||||||
|
while((sc)->PINCTL & SC_PINCTL_SYNC_Msk);\
|
||||||
|
if(u32State)\
|
||||||
|
(sc)->PINCTL |= SC_PINCTL_RSTEN_Msk;\
|
||||||
|
else\
|
||||||
|
(sc)->PINCTL &= ~SC_PINCTL_RSTEN_Msk;\
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read One Byte Data
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return One byte read from receive FIFO
|
||||||
|
*
|
||||||
|
* @details By reading DAT register, the SC will return an 8-bit received data.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_READ(sc) ((char)((sc)->DAT))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write One Byte Data
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u8Data Data to write to transmit FIFO.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details By writing data to DAT register, the SC will send out an 8-bit data.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Smartcard Stop Bit Length
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Len Stop bit length, ether 1 or 2.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Stop bit length must be 1 for T = 1 protocol and 2 for T = 0 protocol.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SC_SET_STOP_BIT_LEN(sc, u32Len) ((sc)->CTL = ((sc)->CTL & ~SC_CTL_NSB_Msk) | (((u32Len) == 1)? SC_CTL_NSB_Msk : 0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Tx Error Retry Count
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Count The number of Tx error retry count, between 0~8 and 0 means disable Tx error retry function.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable/disable transmitter retry function when parity error has occurred, and set error retry count.
|
||||||
|
* @note Set error retry count to 0 will disable Tx error retry function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void SC_SetTxRetry(SC_T *sc, uint32_t u32Count)
|
||||||
|
{
|
||||||
|
while((sc)->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
/* Retry count must set while enable bit disabled, so disable it first */
|
||||||
|
(sc)->CTL &= ~(SC_CTL_TXRTY_Msk | SC_CTL_TXRTYEN_Msk);
|
||||||
|
|
||||||
|
if((u32Count) != 0UL)
|
||||||
|
{
|
||||||
|
while((sc)->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
(sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_TXRTY_Pos) | SC_CTL_TXRTYEN_Msk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Rx Error Retry Count
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Count The number of Rx error retry count, between 0~8 and 0 means disable Rx error retry function.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable/disable receiver retry function when parity error has occurred, and set error retry count.
|
||||||
|
* @note Set error retry count to 0 will disable Rx error retry function.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void SC_SetRxRetry(SC_T *sc, uint32_t u32Count)
|
||||||
|
{
|
||||||
|
while((sc)->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
/* Retry count must set while enable bit disabled, so disable it first */
|
||||||
|
(sc)->CTL &= ~(SC_CTL_RXRTY_Msk | SC_CTL_RXRTYEN_Msk);
|
||||||
|
|
||||||
|
if((u32Count) != 0UL)
|
||||||
|
{
|
||||||
|
while((sc)->CTL & SC_CTL_SYNC_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
(sc)->CTL |= (((u32Count) - 1UL) << SC_CTL_RXRTY_Pos) | SC_CTL_RXRTYEN_Msk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t SC_IsCardInserted(SC_T *sc);
|
||||||
|
void SC_ClearFIFO(SC_T *sc);
|
||||||
|
void SC_Close(SC_T *sc);
|
||||||
|
void SC_Open(SC_T *sc, uint32_t u32CardDet, uint32_t u32PWR);
|
||||||
|
void SC_ResetReader(SC_T *sc);
|
||||||
|
void SC_SetBlockGuardTime(SC_T *sc, uint32_t u32BGT);
|
||||||
|
void SC_SetCharGuardTime(SC_T *sc, uint32_t u32CGT);
|
||||||
|
void SC_StopAllTimer(SC_T *sc);
|
||||||
|
void SC_StartTimer(SC_T *sc, uint32_t u32TimerNum, uint32_t u32Mode, uint32_t u32ETUCount);
|
||||||
|
void SC_StopTimer(SC_T *sc, uint32_t u32TimerNum);
|
||||||
|
uint32_t SC_GetInterfaceClock(SC_T *sc);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SC_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SC_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__SC_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,364 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file scu.h
|
||||||
|
* @version V1.00
|
||||||
|
* @brief Secure Configuration Unit Driver Header
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __SCU_H__
|
||||||
|
#define __SCU_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SCU_Driver SCU Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SCU_EXPORTED_CONSTANTS SCU Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @details Non-secure Attribution Definition.
|
||||||
|
*/
|
||||||
|
typedef enum NSATTR
|
||||||
|
{
|
||||||
|
/****** PNNSET0 **********************************************************************************/
|
||||||
|
USBH_Attr = 9,
|
||||||
|
SDH0_Attr = 13,
|
||||||
|
EBI_Attr = 16,
|
||||||
|
PDMA1_Attr = 24,
|
||||||
|
|
||||||
|
/****** PNNSET1 **********************************************************************************/
|
||||||
|
CRC_Attr = 32 + 17,
|
||||||
|
CRPT_Attr = 32 + 18,
|
||||||
|
|
||||||
|
/****** PNNSET2 **********************************************************************************/
|
||||||
|
RTC_Attr = 64 + 1,
|
||||||
|
EADC_Attr = 64 + 3,
|
||||||
|
ACMP01_Attr = 64 + 5,
|
||||||
|
DAC_Attr = 64 + 7,
|
||||||
|
I2S0_Attr = 64 + 8,
|
||||||
|
OTG_Attr = 64 + 13,
|
||||||
|
TMR23_Attr = 64 + 17,
|
||||||
|
PWM0_Attr = 64 + 24,
|
||||||
|
PWM1_Attr = 64 + 25,
|
||||||
|
BPWM0_Attr = 64 + 26,
|
||||||
|
BPWM1_Attr = 64 + 27,
|
||||||
|
/****** PNNSET3 **********************************************************************************/
|
||||||
|
SPI0_Attr = 96 + 0,
|
||||||
|
SPI1_Attr = 96 + 1,
|
||||||
|
SPI2_Attr = 96 + 2,
|
||||||
|
SPI3_Attr = 96 + 3,
|
||||||
|
SPI4_Attr = 96 + 4,
|
||||||
|
SPI5_Attr = 96 + 5,
|
||||||
|
UART0_Attr = 96 + 16,
|
||||||
|
UART1_Attr = 96 + 17,
|
||||||
|
UART2_Attr = 96 + 18,
|
||||||
|
UART3_Attr = 96 + 19,
|
||||||
|
UART4_Attr = 96 + 20,
|
||||||
|
UART5_Attr = 96 + 21,
|
||||||
|
/****** PNNSET4 **********************************************************************************/
|
||||||
|
I2C0_Attr = 128 + 0,
|
||||||
|
I2C1_Attr = 128 + 1,
|
||||||
|
I2C2_Attr = 128 + 2,
|
||||||
|
SC0_Attr = 128 + 16,
|
||||||
|
SC1_Attr = 128 + 17,
|
||||||
|
SC2_Attr = 128 + 18,
|
||||||
|
|
||||||
|
|
||||||
|
/****** PNNSET5 **********************************************************************************/
|
||||||
|
CAN0_Attr = 160 + 0,
|
||||||
|
QEI0_Attr = 160 + 16,
|
||||||
|
QEI1_Attr = 160 + 17,
|
||||||
|
ECAP0_Attr = 160 + 20,
|
||||||
|
ECAP1_Attr = 160 + 21,
|
||||||
|
DSRC_Attr = 160 + 23,
|
||||||
|
|
||||||
|
/****** PNNSET6 **********************************************************************************/
|
||||||
|
USBD_Attr = 192 + 0,
|
||||||
|
USCI0_Attr = 192 + 16,
|
||||||
|
USCI1_Attr = 192 + 17
|
||||||
|
|
||||||
|
|
||||||
|
} NSATTR_T;
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCU_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set peripheral non-secure attribution
|
||||||
|
*
|
||||||
|
* @param[in] module The module which needs to set to non-secure.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set a peripheral to be non-secure peripheral.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SCU_SET_PNSSET(nsattr) { SCU->PNSSET[(nsattr)/32] |= (1 << ((nsattr) & 0x1ful)); }
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get peripheral secure/non-secure attribution
|
||||||
|
*
|
||||||
|
* @param[in] module The peripheral which needs to get its secure/non-secure attribution.
|
||||||
|
*
|
||||||
|
* @return The secure/non-secure attribution of specified peripheral.
|
||||||
|
* @retval 0 The peripheral is secure
|
||||||
|
* @retval 1 The peripheral is non-secure
|
||||||
|
*
|
||||||
|
* @details This macro gets the peripheral secure/non-secure attribution.
|
||||||
|
*/
|
||||||
|
#define SCU_GET_PNSSET(nsattr) ((SCU->PNSSET[(nsattr)/32] >> ((nsattr) & 0x1ful)) & 1ul)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set secure/non-secure attribution of specified GPIO ports
|
||||||
|
*
|
||||||
|
* @param[in] mask The port mask of each GPIO port
|
||||||
|
* - \ref SCU_IONSSET_PA_Msk
|
||||||
|
* - \ref SCU_IONSSET_PB_Msk
|
||||||
|
* - \ref SCU_IONSSET_PC_Msk
|
||||||
|
* - \ref SCU_IONSSET_PD_Msk
|
||||||
|
* - \ref SCU_IONSSET_PE_Msk
|
||||||
|
* - \ref SCU_IONSSET_PF_Msk
|
||||||
|
* - \ref SCU_IONSSET_PG_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro gets the peripheral secure/non-secure attribution.
|
||||||
|
*/
|
||||||
|
#define SCU_SET_IONSSET(mask) (SCU->IONSSET |= (mask))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get secure/non-secure attribution of specified GPIO ports
|
||||||
|
*
|
||||||
|
* @param[in] mask The port mask of each GPIO port
|
||||||
|
* - \ref SCU_IONSSET_PA_Msk
|
||||||
|
* - \ref SCU_IONSSET_PB_Msk
|
||||||
|
* - \ref SCU_IONSSET_PC_Msk
|
||||||
|
* - \ref SCU_IONSSET_PD_Msk
|
||||||
|
* - \ref SCU_IONSSET_PE_Msk
|
||||||
|
* - \ref SCU_IONSSET_PF_Msk
|
||||||
|
* - \ref SCU_IONSSET_PG_Msk
|
||||||
|
*
|
||||||
|
* @return The secure/non-secure attribution of specified peripheral.
|
||||||
|
* @retval 0 The specified IO port is secure
|
||||||
|
* @retval 1 The specified IO port is non-secure
|
||||||
|
*
|
||||||
|
* @details This macro gets GPIO port secure/non-secure attribution.
|
||||||
|
*/
|
||||||
|
#define SCU_GET_IONSSET(port) ((SCU->IONSSET&(port))?1:0)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable sercure violation interrupts
|
||||||
|
*
|
||||||
|
* @param[in] mask The mask of each secure violation interrupt source
|
||||||
|
* - \ref SCU_SVIOIEN_APB0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_APB1IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_GPIOIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_EBIIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_USBHIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_CRCIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SDH0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_PDMA0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_PDMA1IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SRAM0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SRAM1IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_FMCIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_FLASHIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SCUIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SYSIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_CRPTIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable secure violation interrupt of SCU.
|
||||||
|
* The secure violation interrupt could be used to detect attack of secure elements.
|
||||||
|
*/
|
||||||
|
#define SCU_ENABLE_INT(int_mask) (SCU->SVIOIEN |= (int_mask))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable sercure violation interrupts
|
||||||
|
*
|
||||||
|
* @param[in] mask The mask of each secure violation interrupt source
|
||||||
|
* - \ref SCU_SVIOIEN_APB0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_APB1IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_GPIOIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_EBIIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_USBHIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_CRCIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SDH0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_PDMA0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_PDMA1IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SRAM0IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SRAM1IEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_FMCIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_FLASHIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SCUIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_SYSIEN_Msk
|
||||||
|
* - \ref SCU_SVIOIEN_CRPTIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable secure violation interrupt of SCU.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SCU_DISABLE_INT(int_mask) (SCU->SVIOIEN &= (~(int_mask)))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get secure violation interrupt status
|
||||||
|
*
|
||||||
|
* @param mask The interrupt flag mask bit
|
||||||
|
*
|
||||||
|
* @return The value of SCU_SVINTSTS register
|
||||||
|
*
|
||||||
|
* @details Return interrupt flag of SCU_SVINTSTS register.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SCU_GET_INT_FLAG(mask) (SCU->SVINTSTS&(mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear secure violation interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] flag The combination of the specified interrupt flags.
|
||||||
|
* Each bit corresponds to a interrupt source.
|
||||||
|
* This parameter decides which interrupt flags will be cleared.
|
||||||
|
* - \ref SCU_SVINTSTS_APB0IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_APB1IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_GPIOIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_EBIIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_USBHIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_CRCIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_SDH0IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_PDMA0IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_PDMA1IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_SRAM0IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_SRAM1IF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_FMCIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_FLASHIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_SCUIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_SYSIF_Msk
|
||||||
|
* - \ref SCU_SVINTSTS_CRPTIF_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear SCU related interrupt flags specified by flag parameter.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SCU_CLR_INT_FLAG(flag) (SCU->SVINTSTS = (flag))
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Control the behavior of non-secure monitor when CPU is in idle state.
|
||||||
|
*
|
||||||
|
* @param[in] opt Option for behavior control of non-secure monitor when CPU in idle.
|
||||||
|
* - true The counter keeps counting when CPU is in idle.
|
||||||
|
- false The counter will stop when CPU is in idle.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To control non-secure monitor counter when CPU is in idle.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SCU_NSM_IDLE_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_IDLEON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_IDLEON_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Control the behavior of non-secure monitor when CPU is in debug state.
|
||||||
|
*
|
||||||
|
* @param[in] opt Option for behavior control of non-secure monitor when CPU in debug.
|
||||||
|
* - true The counter keeps counting when CPU is in debug.
|
||||||
|
- false The counter will stop when CPU is in debug.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To control non-secure monitor counter when CPU is in debug.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define SCU_NSM_DBG_ON(opt) ((opt)?(SCU->NSMCTL |= SCU_NSMCTL_DBGON_Msk):(SCU->NSMCTL &= ~SCU_NSMCTL_DBGON_Msk))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Config non-secure monitor to detect timeout in non-secure state.
|
||||||
|
*
|
||||||
|
* @param[in] u32Ticks A specified period for timeout in non-secure state
|
||||||
|
* @param[in] u32Prescale A pre-scale divider to non-secure monitor clock
|
||||||
|
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to configure non-secure monitor. If the CPU state stay in non-secure state for
|
||||||
|
* a specified period. The non-secure monitor will timeout and assert an interrupt. Otherwise, the
|
||||||
|
* non-secure monitor will auto clear whenever returning to secure state. This could be used to avoid
|
||||||
|
* CPU state in non-secure state too long time for security purpose. User must enable SCU_IRQn if interrupt
|
||||||
|
* is necessary.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void SCU_NSMConfig(uint32_t u32Ticks, uint32_t u32Prescale)
|
||||||
|
{
|
||||||
|
|
||||||
|
SCU->NSMLOAD = u32Ticks;
|
||||||
|
SCU->NSMVAL = 0ul;
|
||||||
|
SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | (u32Prescale & 0xfful);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Config non-secure monitor to be a timer.
|
||||||
|
*
|
||||||
|
* @param[in] u32Ticks A specified period for timer interrupt.
|
||||||
|
* @param[in] u32Prescale A pre-scale divider to timer clock source.
|
||||||
|
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to configure non-secure monitor as a timer. In other words, the timer counter
|
||||||
|
* keeps counting even CPU is in secure state.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void SCU_TimerConfig(uint32_t u32Ticks, uint32_t u32Prescale)
|
||||||
|
{
|
||||||
|
|
||||||
|
SCU->NSMLOAD = u32Ticks;
|
||||||
|
SCU->NSMVAL = 0ul;
|
||||||
|
SCU->NSMCTL = SCU_NSMCTL_AUTORLD_Msk | SCU_NSMCTL_NSMIEN_Msk | SCU_NSMCTL_TMRMOD_Msk | (u32Prescale & 0xfful);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCU_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCU_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __SCU_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,266 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file scuart.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Smart Card UART(SCUART) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SCUART_Driver SCUART Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Smartcard UART Function
|
||||||
|
*
|
||||||
|
* @param sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable Smartcard interface UART mode.
|
||||||
|
*/
|
||||||
|
void SCUART_Close(SC_T* sc)
|
||||||
|
{
|
||||||
|
sc->INTEN = 0UL;
|
||||||
|
sc->UARTCTL = 0UL;
|
||||||
|
sc->CTL = 0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/** @cond HIDDEN_SYMBOLS */
|
||||||
|
/**
|
||||||
|
* @brief Get Smartcard Clock Frequency
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return Module clock of specified SC port.
|
||||||
|
*/
|
||||||
|
static uint32_t SCUART_GetClock(SC_T *sc)
|
||||||
|
{
|
||||||
|
uint32_t u32ClkSrc, u32Num, u32Clk, u32Div;
|
||||||
|
|
||||||
|
/* Get smartcard module clock source and divider */
|
||||||
|
if(sc == SC0)
|
||||||
|
{
|
||||||
|
u32Num = 0UL;
|
||||||
|
u32ClkSrc = CLK_GetModuleClockSource(SC0_MODULE);
|
||||||
|
u32Div = CLK_GetModuleClockDivider(SC0_MODULE);
|
||||||
|
}
|
||||||
|
else if(sc == SC1)
|
||||||
|
{
|
||||||
|
u32Num = 1UL;
|
||||||
|
u32ClkSrc = CLK_GetModuleClockSource(SC1_MODULE);
|
||||||
|
u32Div = CLK_GetModuleClockDivider(SC1_MODULE);
|
||||||
|
}
|
||||||
|
else if(sc == SC2)
|
||||||
|
{
|
||||||
|
u32Num = 2UL;
|
||||||
|
u32ClkSrc = CLK_GetModuleClockSource(SC2_MODULE);
|
||||||
|
u32Div = CLK_GetModuleClockDivider(SC2_MODULE);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get smartcard module clock */
|
||||||
|
if(u32ClkSrc == 0UL)
|
||||||
|
{
|
||||||
|
u32Clk = __HXT;
|
||||||
|
}
|
||||||
|
else if(u32ClkSrc == 1UL)
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPLLClockFreq();
|
||||||
|
}
|
||||||
|
else if(u32ClkSrc == 2UL)
|
||||||
|
{
|
||||||
|
if(u32Num == 1UL)
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Clk = __HIRC;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32Clk /= (u32Div + 1UL);
|
||||||
|
|
||||||
|
return u32Clk;
|
||||||
|
}
|
||||||
|
/** @endcond HIDDEN_SYMBOLS */
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Smartcard UART Function
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Baudrate Target baudrate of smartcard UART module.
|
||||||
|
*
|
||||||
|
* @return Actual baudrate of smartcard UART mode
|
||||||
|
*
|
||||||
|
* @details This function use to enable smartcard module UART mode and set baudrate.
|
||||||
|
*
|
||||||
|
* @note This function configures character width to 8 bits, 1 stop bit, and no parity.
|
||||||
|
* And can use \ref SCUART_SetLineConfig function to update these settings.
|
||||||
|
* The baudrate clock source comes from SC_CLK/SC_DIV, where SC_CLK is controlled
|
||||||
|
* by SCxSEL in CLKSEL3 register, SC_DIV is controlled by SCxDIV in CLKDIV1
|
||||||
|
* register. Since the baudrate divider is 12-bit wide and must be larger than 4,
|
||||||
|
* (clock source / baudrate) must be larger or equal to 5 and smaller or equal to
|
||||||
|
* 4096. Otherwise this function cannot configure SCUART to work with target baudrate.
|
||||||
|
*/
|
||||||
|
uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate)
|
||||||
|
{
|
||||||
|
uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
|
||||||
|
|
||||||
|
/* Calculate divider for target baudrate */
|
||||||
|
u32Div = (u32Clk + (u32Baudrate >> 1) - 1UL) / u32Baudrate - 1UL;
|
||||||
|
|
||||||
|
sc->CTL = SC_CTL_SCEN_Msk | SC_CTL_NSB_Msk; // Enable smartcard interface and stop bit = 1
|
||||||
|
sc->UARTCTL = SCUART_CHAR_LEN_8 | SCUART_PARITY_NONE | SC_UARTCTL_UARTEN_Msk; // Enable UART mode, disable parity and 8 bit per character
|
||||||
|
sc->ETUCTL = u32Div;
|
||||||
|
|
||||||
|
return(u32Clk / (u32Div + 1UL));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read SC UART Data
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] pu8RxBuf The buffer to store receive the data.
|
||||||
|
* @param[in] u32ReadBytes Number of data to receive.
|
||||||
|
*
|
||||||
|
* @return Actual character number reads to buffer
|
||||||
|
*
|
||||||
|
* @details The function is used to read data from Rx FIFO.
|
||||||
|
*
|
||||||
|
* @note This function does not block and return immediately if there's no data available.
|
||||||
|
*/
|
||||||
|
uint32_t SCUART_Read(SC_T* sc, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
|
||||||
|
{
|
||||||
|
uint32_t u32Count;
|
||||||
|
|
||||||
|
for(u32Count = 0UL; u32Count < u32ReadBytes; u32Count++)
|
||||||
|
{
|
||||||
|
if(SCUART_GET_RX_EMPTY(sc)) /* no data available */
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
pu8RxBuf[u32Count] = (uint8_t)SCUART_READ(sc); /* get data from FIFO */
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Count;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SC UART Line Setting
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Baudrate Target baudrate of smartcard UART mode. If this value is 0, SC UART baudrate will not change.
|
||||||
|
* @param[in] u32DataWidth The data length, could be:
|
||||||
|
* - \ref SCUART_CHAR_LEN_5
|
||||||
|
* - \ref SCUART_CHAR_LEN_6
|
||||||
|
* - \ref SCUART_CHAR_LEN_7
|
||||||
|
* - \ref SCUART_CHAR_LEN_8
|
||||||
|
* @param[in] u32Parity The parity setting, could be:
|
||||||
|
* - \ref SCUART_PARITY_NONE
|
||||||
|
* - \ref SCUART_PARITY_ODD
|
||||||
|
* - \ref SCUART_PARITY_EVEN
|
||||||
|
* @param[in] u32StopBits The stop bit length, could be:
|
||||||
|
* - \ref SCUART_STOP_BIT_1
|
||||||
|
* - \ref SCUART_STOP_BIT_2
|
||||||
|
*
|
||||||
|
* @return Actual baudrate of smartcard UART mode
|
||||||
|
*
|
||||||
|
* @details SC UART function is operated in SC UART line setting.
|
||||||
|
*/
|
||||||
|
uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits)
|
||||||
|
{
|
||||||
|
uint32_t u32Clk = SCUART_GetClock(sc), u32Div;
|
||||||
|
|
||||||
|
if(u32Baudrate == 0)
|
||||||
|
{
|
||||||
|
/* Keep original baudrate setting */
|
||||||
|
u32Div = sc->ETUCTL & SC_ETUCTL_ETURDIV_Msk;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
/* Calculate divider for target baudrate */
|
||||||
|
u32Div = ((u32Clk + (u32Baudrate >> 1) - 1) / u32Baudrate) - 1;
|
||||||
|
sc->ETUCTL = u32Div;
|
||||||
|
}
|
||||||
|
|
||||||
|
sc->CTL = u32StopBits | SC_CTL_SCEN_Msk; // Set stop bit
|
||||||
|
sc->UARTCTL = u32Parity | u32DataWidth | SC_UARTCTL_UARTEN_Msk; // Set character width and parity
|
||||||
|
|
||||||
|
return (u32Clk / (u32Div + 1));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Receive Time-out Count
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32TOC Rx time-out counter, using baudrate as counter unit. Valid range are 0~0x1FF,
|
||||||
|
* set this value to 0 will disable time-out counter.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The time-out counter resets and starts counting whenever the Rx buffer received a
|
||||||
|
* new data word. Once the counter decrease to 1 and no new data is received or CPU
|
||||||
|
* does not read any data from FIFO, a receiver time-out interrupt will be generated.
|
||||||
|
*/
|
||||||
|
void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC)
|
||||||
|
{
|
||||||
|
sc->RXTOUT = u32TOC;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write SC UART Data
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] pu8TxBuf The buffer containing data to send to transmit FIFO.
|
||||||
|
* @param[in] u32WriteBytes Number of data to transmit.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to write data into Tx FIFO to send data out.
|
||||||
|
*
|
||||||
|
* @note This function blocks until all data write into FIFO.
|
||||||
|
*/
|
||||||
|
void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes)
|
||||||
|
{
|
||||||
|
uint32_t u32Count;
|
||||||
|
|
||||||
|
for(u32Count = 0UL; u32Count != u32WriteBytes; u32Count++)
|
||||||
|
{
|
||||||
|
/* Wait 'til FIFO not full */
|
||||||
|
while(SCUART_GET_TX_FULL(sc))
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
/* Write 1 byte to FIFO */
|
||||||
|
sc->DAT = pu8TxBuf[u32Count]; // Write 1 byte to FIFO
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCUART_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,345 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file scuart.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Smart Card UART(SCUART) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __SCUART_H__
|
||||||
|
#define __SCUART_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SCUART_Driver SCUART Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SCUART_EXPORTED_CONSTANTS SCUART Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define SCUART_CHAR_LEN_5 (0x3UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 5 bits \hideinitializer */
|
||||||
|
#define SCUART_CHAR_LEN_6 (0x2UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 6 bits \hideinitializer */
|
||||||
|
#define SCUART_CHAR_LEN_7 (0x1UL << SC_UARTCTL_WLS_Pos) /*!< Set SCUART word length to 7 bits \hideinitializer */
|
||||||
|
#define SCUART_CHAR_LEN_8 (0UL) /*!< Set SCUART word length to 8 bits \hideinitializer */
|
||||||
|
|
||||||
|
#define SCUART_PARITY_NONE (SC_UARTCTL_PBOFF_Msk) /*!< Set SCUART transfer with no parity \hideinitializer */
|
||||||
|
#define SCUART_PARITY_ODD (SC_UARTCTL_OPE_Msk) /*!< Set SCUART transfer with odd parity \hideinitializer */
|
||||||
|
#define SCUART_PARITY_EVEN (0UL) /*!< Set SCUART transfer with even parity \hideinitializer */
|
||||||
|
|
||||||
|
#define SCUART_STOP_BIT_1 (SC_CTL_NSB_Msk) /*!< Set SCUART transfer with one stop bit \hideinitializer */
|
||||||
|
#define SCUART_STOP_BIT_2 (0UL) /*!< Set SCUART transfer with two stop bits \hideinitializer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCUART_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SCUART_EXPORTED_FUNCTIONS SCUART Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/* Tx Macros */
|
||||||
|
/**
|
||||||
|
* @brief Write Data to Tx Data Register
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u8Data Data byte to transmit.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details By writing data to DAT register, the SC will send out an 8-bit data.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_WRITE(sc, u8Data) ((sc)->DAT = (u8Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Tx FIFO Empty Flag Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Transmit FIFO is not empty
|
||||||
|
* @retval SC_STATUS_TXEMPTY_Msk Transmit FIFO is empty
|
||||||
|
*
|
||||||
|
* @details When the last byte of Tx buffer has been transferred to Transmitter Shift Register, hardware sets TXEMPTY (SC_STATUS[9]) high.
|
||||||
|
* It will be cleared when writing data into DAT (SC_DAT[7:0]).
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_GET_TX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Tx FIFO Full Flag Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Transmit FIFO is not full
|
||||||
|
* @retval SC_STATUS_TXFULL_Msk Transmit FIFO is full
|
||||||
|
*
|
||||||
|
* @details TXFULL (SC_STATUS[10]) is set when Tx buffer counts equals to 4, otherwise is cleared by hardware.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_GET_TX_FULL(sc) ((sc)->STATUS & SC_STATUS_TXFULL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait specified Smartcard port Transmission Complete
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details TXACT (SC_STATUS[31]) is cleared automatically when Tx transfer is finished or the last byte transmission has completed.
|
||||||
|
*
|
||||||
|
* @note This macro blocks until transmit complete.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_WAIT_TX_EMPTY(sc) while((sc)->STATUS & SC_STATUS_TXACT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Tx FIFO Full Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Transmit FIFO is not full
|
||||||
|
* @retval 1 Transmit FIFO is full
|
||||||
|
*
|
||||||
|
* @details TXFULL (SC_STATUS[10]) indicates Tx buffer full or not.
|
||||||
|
* This bit is set when Tx buffer counts equals to 4, otherwise is cleared by hardware.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_IS_TX_FULL(sc) (((sc)->STATUS & SC_STATUS_TXFULL_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Tx Transmit Complete Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Transmit is not complete
|
||||||
|
* @retval 1 Transmit complete
|
||||||
|
*
|
||||||
|
* @details TXACT (SC_STATUS[31]) indicates Tx Transmit is complete or not.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_IS_TX_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 0 : 1)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Tx FIFO Empty Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Transmit FIFO is not empty
|
||||||
|
* @retval 1 Transmit FIFO is empty
|
||||||
|
*
|
||||||
|
* @details TXEMPTY (SC_STATUS[9]) is set by hardware when the last byte of Tx buffer has been transferred to Transmitter Shift Register.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_IS_TX_FIFO_EMPTY(sc) (((sc)->STATUS & SC_STATUS_TXEMPTY_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check specified Smartcard port Transmission Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Transmit is completed
|
||||||
|
* @retval 1 Transmit is active
|
||||||
|
*
|
||||||
|
* @details TXACT (SC_STATUS[31]) is set by hardware when Tx transfer is in active and the STOP bit of the last byte has been transmitted.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_IS_TX_ACTIVE(sc) (((sc)->STATUS & SC_STATUS_TXACT_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
|
||||||
|
/* RX Macros */
|
||||||
|
/**
|
||||||
|
* @brief Read Rx Data Register
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @return The oldest data byte in RX FIFO
|
||||||
|
*
|
||||||
|
* @details By reading DAT register, the SC will return an 8-bit received data.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_READ(sc) ((sc)->DAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Rx FIFO Empty Flag Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Receive FIFO is not empty
|
||||||
|
* @retval SC_STATUS_RXEMPTY_Msk Receive FIFO is empty
|
||||||
|
*
|
||||||
|
* @details When the last byte of Rx buffer has been read by CPU, hardware sets RXEMPTY (SC_STATUS[1]) high.
|
||||||
|
* It will be cleared when SC receives any new data.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_GET_RX_EMPTY(sc) ((sc)->STATUS & SC_STATUS_RXEMPTY_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Rx FIFO Full Flag Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Receive FIFO is not full
|
||||||
|
* @retval SC_STATUS_TXFULL_Msk Receive FIFO is full
|
||||||
|
*
|
||||||
|
* @details RXFULL (SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_GET_RX_FULL(sc) ((sc)->STATUS & SC_STATUS_RXFULL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Rx FIFO Reach FIFO Trigger Level Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 The number of bytes in Rx FIFO is less than trigger level.
|
||||||
|
* @retval 1 The number of bytes in Rx FIFO equals or larger than trigger level.
|
||||||
|
*
|
||||||
|
* @details RDAIF (SC_INTSTS[0]) is used for received data reaching trigger level RXTRGLV (SC_CTL[7:6]) interrupt status flag.
|
||||||
|
*
|
||||||
|
* @note If receive trigger level is \b not 1 byte, this macro return 0 does not necessary indicates there is no data in FIFO.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_IS_RX_READY(sc) (((sc)->INTSTS & SC_INTSTS_RDAIF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check Rx FIFO Full Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval 0 Receive FIFO is not full
|
||||||
|
* @retval 1 Receive FIFO is full
|
||||||
|
*
|
||||||
|
* @details RXFULLF( SC_STATUS[2]) is set when Rx buffer counts equals to 4, otherwise it is cleared by hardware.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_IS_RX_FULL(sc) (((sc)->STATUS & SC_STATUS_RXFULL_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
|
||||||
|
/* Interrupt Macros */
|
||||||
|
/**
|
||||||
|
* @brief Enable specified SCUART Interrupt Function
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Mask Interrupt masks to enable, a combination of following bits.
|
||||||
|
* - \ref SC_INTEN_RXTOIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TERRIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TBEIEN_Msk
|
||||||
|
* - \ref SC_INTEN_RDAIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to enable receiver buffer time-out interrupt, transfer error interrupt,
|
||||||
|
* transmit buffer empty interrupt or receive data reach trigger level interrupt.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_ENABLE_INT(sc, u32Mask) ((sc)->INTEN |= (u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified SCUART Interrupt Function
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Mask Interrupt masks to disable, a combination of following bits.
|
||||||
|
* - \ref SC_INTEN_RXTOIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TERRIEN_Msk
|
||||||
|
* - \ref SC_INTEN_TBEIEN_Msk
|
||||||
|
* - \ref SC_INTEN_RDAIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to disable receiver buffer time-out interrupt, transfer error interrupt,
|
||||||
|
* transmit buffer empty interrupt or receive data reach trigger level interrupt.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_DISABLE_INT(sc, u32Mask) ((sc)->INTEN &= ~(u32Mask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified SCUART Interrupt Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Type Interrupt status to check, could be one of following value:
|
||||||
|
* - \ref SC_INTSTS_RBTOIF_Msk
|
||||||
|
* - \ref SC_INTSTS_TERRIF_Msk
|
||||||
|
* - \ref SC_INTSTS_TBEIF_Msk
|
||||||
|
* - \ref SC_INTSTS_RDAIF_Msk
|
||||||
|
*
|
||||||
|
* @retval 0 Specified interrupt does not happened.
|
||||||
|
* @retval 1 Specified interrupt happened.
|
||||||
|
*
|
||||||
|
* @details The macro is used to get receiver buffer time-out interrupt status, transfer error interrupt status,
|
||||||
|
* transmit buffer empty interrupt status or receive data reach interrupt status.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_GET_INT_FLAG(sc, u32Type) (((sc)->INTSTS & (u32Type))? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified SCUART Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Type Interrupt flag to clear, could be the combination of following values:
|
||||||
|
* - \ref SC_INTSTS_TERRIF_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to clear transfer error interrupt flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_CLR_INT_FLAG(sc, u32Type) ((sc)->INTSTS = (u32Type))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get SCUART Receiver Error Flag Status
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
*
|
||||||
|
* @retval SC_STATUS_PEF_Msk Rx parity error
|
||||||
|
* @retval SC_STATUS_FEF_Msk Rx frame error
|
||||||
|
* @retval SC_STATUS_BEF_Msk Rx break error
|
||||||
|
*
|
||||||
|
* @details The macro is used to get receiver parity error status, frame error status or break error status.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_GET_ERR_FLAG(sc) ((sc)->STATUS & (SC_STATUS_PEF_Msk | SC_STATUS_FEF_Msk | SC_STATUS_BEF_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified Receiver Error Flag
|
||||||
|
*
|
||||||
|
* @param[in] sc The pointer of smartcard module.
|
||||||
|
* @param[in] u32Mask Receiver error flag to clear, combination following values:
|
||||||
|
* - \ref SC_STATUS_PEF_Msk
|
||||||
|
* - \ref SC_STATUS_FEF_Msk
|
||||||
|
* - \ref SC_STATUS_BEF_Msk
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The macro is used to clear receiver parity error flag, frame error flag or break error flag.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SCUART_CLR_ERR_FLAG(sc, u32Mask) ((sc)->STATUS = (u32Mask))
|
||||||
|
|
||||||
|
void SCUART_Close(SC_T* sc);
|
||||||
|
uint32_t SCUART_Open(SC_T* sc, uint32_t u32Baudrate);
|
||||||
|
uint32_t SCUART_Read(SC_T* sc, uint8_t pu8RxBuf[], uint32_t u32ReadBytes);
|
||||||
|
uint32_t SCUART_SetLineConfig(SC_T* sc, uint32_t u32Baudrate, uint32_t u32DataWidth, uint32_t u32Parity, uint32_t u32StopBits);
|
||||||
|
void SCUART_SetTimeoutCnt(SC_T* sc, uint32_t u32TOC);
|
||||||
|
void SCUART_Write(SC_T* sc, uint8_t pu8TxBuf[], uint32_t u32WriteBytes);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCUART_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SCUART_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__SCUART_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,196 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file sdh.h
|
||||||
|
* @version V1.00
|
||||||
|
* @brief M2351 SDH driver header file
|
||||||
|
*
|
||||||
|
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include <stdio.h>
|
||||||
|
|
||||||
|
#ifndef __SDH_H__
|
||||||
|
#define __SDH_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SDH_Driver SDH Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SDH_EXPORTED_CONSTANTS SDH Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SDH_ERR_ID 0xFFFF0100UL
|
||||||
|
|
||||||
|
#define SDH_TIMEOUT (SDH_ERR_ID|0x01UL)
|
||||||
|
#define SDH_NO_MEMORY (SDH_ERR_ID|0x02UL)
|
||||||
|
|
||||||
|
//-- function return value
|
||||||
|
#define Successful 0U
|
||||||
|
#define Fail 1U
|
||||||
|
|
||||||
|
//--- define type of SD card or MMC
|
||||||
|
#define SDH_TYPE_UNKNOWN 0U
|
||||||
|
#define SDH_TYPE_SD_HIGH 1U
|
||||||
|
#define SDH_TYPE_SD_LOW 2U
|
||||||
|
#define SDH_TYPE_MMC 3U
|
||||||
|
#define SDH_TYPE_EMMC 4U
|
||||||
|
|
||||||
|
/* SD error */
|
||||||
|
#define SDH_NO_SD_CARD (SDH_ERR_ID|0x10UL)
|
||||||
|
#define SDH_ERR_DEVICE (SDH_ERR_ID|0x11UL)
|
||||||
|
#define SDH_INIT_TIMEOUT (SDH_ERR_ID|0x12UL)
|
||||||
|
#define SDH_SELECT_ERROR (SDH_ERR_ID|0x13UL)
|
||||||
|
#define SDH_WRITE_PROTECT (SDH_ERR_ID|0x14UL)
|
||||||
|
#define SDH_INIT_ERROR (SDH_ERR_ID|0x15UL)
|
||||||
|
#define SDH_CRC7_ERROR (SDH_ERR_ID|0x16UL)
|
||||||
|
#define SDH_CRC16_ERROR (SDH_ERR_ID|0x17UL)
|
||||||
|
#define SDH_CRC_ERROR (SDH_ERR_ID|0x18UL)
|
||||||
|
#define SDH_CMD8_ERROR (SDH_ERR_ID|0x19UL)
|
||||||
|
|
||||||
|
#define MMC_FREQ 20000 /*!< output 20MHz to MMC \hideinitializer */
|
||||||
|
#define SD_FREQ 25000 /*!< output 25MHz to SD \hideinitializer */
|
||||||
|
#define SDHC_FREQ 50000 /*!< output 50MHz to SDH \hideinitializer */
|
||||||
|
|
||||||
|
#define CardDetect_From_GPIO (1 << 8) /*!< Card detection pin is GPIO \hideinitializer */
|
||||||
|
#define CardDetect_From_DAT3 (1 << 9) /*!< Card detection pin is DAT3 \hideinitializer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SDH_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
/** @addtogroup SDH_EXPORTED_TYPEDEF SDH Exported Type Defines
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
typedef struct SDH_info_t
|
||||||
|
{
|
||||||
|
unsigned int CardType; /*!< SDHC, SD, or MMC */
|
||||||
|
unsigned int RCA; /*!< relative card address */
|
||||||
|
unsigned char IsCardInsert; /*!< card insert state */
|
||||||
|
unsigned int totalSectorN; /*!< total sector number */
|
||||||
|
unsigned int diskSize; /*!< disk size in Kbytes */
|
||||||
|
int sectorSize; /*!< sector size in bytes */
|
||||||
|
} SDH_INFO_T;
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SDH_EXPORTED_TYPEDEF */
|
||||||
|
|
||||||
|
/// @cond HIDDEN_SYMBOLS
|
||||||
|
extern SDH_INFO_T SD0;
|
||||||
|
/// @endcond HIDDEN_SYMBOLS
|
||||||
|
|
||||||
|
/** @addtogroup SDH_EXPORTED_FUNCTIONS SDH Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified interrupt.
|
||||||
|
*
|
||||||
|
* @param[in] sdh The pointer of the specified SDH module.
|
||||||
|
* @param[in] u32IntMask Interrupt type mask:
|
||||||
|
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
|
||||||
|
* \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
|
||||||
|
* \ref SDH_INTEN_WKIEN_Msk
|
||||||
|
*
|
||||||
|
* @return None.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SDH_ENABLE_INT(sdh, u32IntMask) (sdh->INTEN |= (u32IntMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified interrupt.
|
||||||
|
*
|
||||||
|
* @param[in] sdh The pointer of the specified SDH module.
|
||||||
|
* @param[in] u32IntMask Interrupt type mask:
|
||||||
|
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk /
|
||||||
|
* \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC0_Msk /
|
||||||
|
* \ref SDH_INTEN_CDSRC1_Msk
|
||||||
|
*
|
||||||
|
* @return None.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SDH_DISABLE_INT(sdh, u32IntMask) (sdh->INTEN &= ~(u32IntMask))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified interrupt flag/status.
|
||||||
|
*
|
||||||
|
* @param[in] sdh The pointer of the specified SDH module.
|
||||||
|
* @param[in] u32IntMask Interrupt type mask:
|
||||||
|
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
|
||||||
|
* \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /
|
||||||
|
* \ref SDH_INTSTS_CDIF0_Msk / \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_RTOIF_Msk /
|
||||||
|
* \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS0_Msk / \ref SDH_INTSTS_CDSTS1_Msk /
|
||||||
|
* \ref SDH_INTSTS_DAT1STS_Msk
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* @return 0 = The specified interrupt is not happened.
|
||||||
|
* 1 = The specified interrupt is happened.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SDH_GET_INT_FLAG(sdh, u32IntMask) ((sdh->INTSTS & (u32IntMask))?1:0)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified interrupt flag/status.
|
||||||
|
*
|
||||||
|
* @param[in] sdh The pointer of the specified SDH module.
|
||||||
|
* @param[in] u32IntMask Interrupt type mask:
|
||||||
|
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF0_Msk /
|
||||||
|
* \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
|
||||||
|
*
|
||||||
|
*
|
||||||
|
* @return None.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SDH_CLR_INT_FLAG(sdh, u32IntMask) (sdh->INTSTS = u32IntMask)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check SD Card inserted or removed.
|
||||||
|
*
|
||||||
|
* @param[in] sdh The pointer of the specified SDH module.
|
||||||
|
*
|
||||||
|
* @return 1: Card inserted.
|
||||||
|
* 0: Card removed.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SDH_IS_CARD_PRESENT(sdh) ((sdh == SDH0)? SD0.IsCardInsert : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get SD Card capacity.
|
||||||
|
*
|
||||||
|
* @param[in] sdh The pointer of the specified SDH module.
|
||||||
|
*
|
||||||
|
* @return SD Card capacity. (unit: KByte)
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SDH_GET_CARD_CAPACITY(sdh) ((sdh == SDH0)? SD0.diskSize : 0)
|
||||||
|
|
||||||
|
|
||||||
|
void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
|
||||||
|
uint32_t SDH_Probe(SDH_T *sdh);
|
||||||
|
uint32_t SDH_Read(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
|
||||||
|
uint32_t SDH_Write(SDH_T *sdh, uint8_t *pu8BufAddr, uint32_t u32StartSec, uint32_t u32SecCount);
|
||||||
|
|
||||||
|
unsigned int SDH_CardDetection(SDH_T *sdh);
|
||||||
|
void SDH_Open_Disk(SDH_T *sdh, unsigned int u32CardDetSrc);
|
||||||
|
void SDH_Close_Disk(SDH_T *sdh);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SDH_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SDH_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //end of __SDH_H__
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,621 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file spi.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series SPI driver header file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __SPI_H__
|
||||||
|
#define __SPI_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_Driver SPI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI_EXPORTED_CONSTANTS SPI Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI_MODE_0 (SPI_CTL_TXNEG_Msk) /*!< CLKPOL=0; RXNEG=0; TXNEG=1 */
|
||||||
|
#define SPI_MODE_1 (SPI_CTL_RXNEG_Msk) /*!< CLKPOL=0; RXNEG=1; TXNEG=0 */
|
||||||
|
#define SPI_MODE_2 (SPI_CTL_CLKPOL_Msk | SPI_CTL_RXNEG_Msk) /*!< CLKPOL=1; RXNEG=1; TXNEG=0 */
|
||||||
|
#define SPI_MODE_3 (SPI_CTL_CLKPOL_Msk | SPI_CTL_TXNEG_Msk) /*!< CLKPOL=1; RXNEG=0; TXNEG=1 */
|
||||||
|
|
||||||
|
#define SPI_SLAVE (SPI_CTL_SLAVE_Msk) /*!< Set as slave */
|
||||||
|
#define SPI_MASTER (0x0) /*!< Set as master */
|
||||||
|
|
||||||
|
#define SPI_SS (SPI_SSCTL_SS_Msk) /*!< Set SS */
|
||||||
|
#define SPI_SS_ACTIVE_HIGH (SPI_SSCTL_SSACTPOL_Msk) /*!< SS active high */
|
||||||
|
#define SPI_SS_ACTIVE_LOW (0x0) /*!< SS active low */
|
||||||
|
|
||||||
|
/* SPI Interrupt Mask */
|
||||||
|
#define SPI_UNIT_INT_MASK (0x001) /*!< Unit transfer interrupt mask */
|
||||||
|
#define SPI_SSACT_INT_MASK (0x002) /*!< Slave selection signal active interrupt mask */
|
||||||
|
#define SPI_SSINACT_INT_MASK (0x004) /*!< Slave selection signal inactive interrupt mask */
|
||||||
|
#define SPI_SLVUR_INT_MASK (0x008) /*!< Slave under run interrupt mask */
|
||||||
|
#define SPI_SLVBE_INT_MASK (0x010) /*!< Slave bit count error interrupt mask */
|
||||||
|
#define SPI_SLVTO_INT_MASK (0x020) /*!< Slave Mode Time-out interrupt mask */
|
||||||
|
#define SPI_TXUF_INT_MASK (0x040) /*!< Slave TX underflow interrupt mask */
|
||||||
|
#define SPI_FIFO_TXTH_INT_MASK (0x080) /*!< FIFO TX threshold interrupt mask */
|
||||||
|
#define SPI_FIFO_RXTH_INT_MASK (0x100) /*!< FIFO RX threshold interrupt mask */
|
||||||
|
#define SPI_FIFO_RXOV_INT_MASK (0x200) /*!< FIFO RX overrun interrupt mask */
|
||||||
|
#define SPI_FIFO_RXTO_INT_MASK (0x400) /*!< FIFO RX time-out interrupt mask */
|
||||||
|
|
||||||
|
/* SPI Status Mask */
|
||||||
|
#define SPI_BUSY_MASK (0x01) /*!< Busy status mask */
|
||||||
|
#define SPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
|
||||||
|
#define SPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
|
||||||
|
#define SPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
|
||||||
|
#define SPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
|
||||||
|
#define SPI_TXRX_RESET_MASK (0x20) /*!< TX or RX reset status mask */
|
||||||
|
#define SPI_SPIEN_STS_MASK (0x40) /*!< SPIEN status mask */
|
||||||
|
#define SPI_SSLINE_STS_MASK (0x80) /*!< SPIx_SS line status mask */
|
||||||
|
|
||||||
|
|
||||||
|
/* I2S Data Width */
|
||||||
|
#define SPII2S_DATABIT_8 (0 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 8-bit */
|
||||||
|
#define SPII2S_DATABIT_16 (1 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 16-bit */
|
||||||
|
#define SPII2S_DATABIT_24 (2 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 24-bit */
|
||||||
|
#define SPII2S_DATABIT_32 (3 << SPI_I2SCTL_WDWIDTH_Pos) /*!< I2S data width is 32-bit */
|
||||||
|
|
||||||
|
/* I2S Audio Format */
|
||||||
|
#define SPII2S_MONO SPI_I2SCTL_MONO_Msk /*!< Monaural channel */
|
||||||
|
#define SPII2S_STEREO 0 /*!< Stereo channel */
|
||||||
|
|
||||||
|
/* I2S Data Format */
|
||||||
|
#define SPII2S_FORMAT_I2S (0<<SPI_I2SCTL_FORMAT_Pos) /*!< I2S data format */
|
||||||
|
#define SPII2S_FORMAT_MSB (1<<SPI_I2SCTL_FORMAT_Pos) /*!< MSB justified data format */
|
||||||
|
#define SPII2S_FORMAT_PCMA (2<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode A data format */
|
||||||
|
#define SPII2S_FORMAT_PCMB (3<<SPI_I2SCTL_FORMAT_Pos) /*!< PCM mode B data format */
|
||||||
|
|
||||||
|
/* I2S Operation mode */
|
||||||
|
#define SPII2S_MODE_SLAVE SPI_I2SCTL_SLAVE_Msk /*!< As slave mode */
|
||||||
|
#define SPII2S_MODE_MASTER 0 /*!< As master mode */
|
||||||
|
|
||||||
|
/* I2S TX FIFO Threshold */
|
||||||
|
#define SPII2S_FIFO_TX_LEVEL_WORD_0 0 /*!< TX threshold is 0 word */
|
||||||
|
#define SPII2S_FIFO_TX_LEVEL_WORD_1 (1 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 1 word */
|
||||||
|
#define SPII2S_FIFO_TX_LEVEL_WORD_2 (2 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 2 words */
|
||||||
|
#define SPII2S_FIFO_TX_LEVEL_WORD_3 (3 << SPI_FIFOCTL_TXTH_Pos) /*!< TX threshold is 3 words */
|
||||||
|
/* I2S RX FIFO Threshold */
|
||||||
|
#define SPII2S_FIFO_RX_LEVEL_WORD_1 0 /*!< RX threshold is 1 word */
|
||||||
|
#define SPII2S_FIFO_RX_LEVEL_WORD_2 (1 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 2 words */
|
||||||
|
#define SPII2S_FIFO_RX_LEVEL_WORD_3 (2 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 3 words */
|
||||||
|
#define SPII2S_FIFO_RX_LEVEL_WORD_4 (3 << SPI_FIFOCTL_RXTH_Pos) /*!< RX threshold is 4 words */
|
||||||
|
|
||||||
|
/* I2S Record Channel */
|
||||||
|
#define SPII2S_MONO_RIGHT 0 /*!< Record mono right channel */
|
||||||
|
#define SPII2S_MONO_LEFT SPI_I2SCTL_RXLCH_Msk /*!< Record mono left channel */
|
||||||
|
|
||||||
|
/* I2S Channel */
|
||||||
|
#define SPII2S_RIGHT 0 /*!< Select right channel */
|
||||||
|
#define SPII2S_LEFT 1 /*!< Select left channel */
|
||||||
|
|
||||||
|
/* I2S Interrupt Mask */
|
||||||
|
#define SPII2S_FIFO_TXTH_INT_MASK (0x01) /*!< TX FIFO threshold interrupt mask */
|
||||||
|
#define SPII2S_FIFO_RXTH_INT_MASK (0x02) /*!< RX FIFO threshold interrupt mask */
|
||||||
|
#define SPII2S_FIFO_RXOV_INT_MASK (0x04) /*!< RX FIFO overrun interrupt mask */
|
||||||
|
#define SPII2S_FIFO_RXTO_INT_MASK (0x08) /*!< RX FIFO time-out interrupt mask */
|
||||||
|
#define SPII2S_TXUF_INT_MASK (0x10) /*!< TX FIFO underflow interrupt mask */
|
||||||
|
#define SPII2S_RIGHT_ZC_INT_MASK (0x20) /*!< Right channel zero cross interrupt mask */
|
||||||
|
#define SPII2S_LEFT_ZC_INT_MASK (0x40) /*!< Left channel zero cross interrupt mask */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SPI_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SPI_EXPORTED_FUNCTIONS SPI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the unit transfer interrupt flag.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Write 1 to UNITIF bit of SPI_STATUS register to clear the unit transfer interrupt flag.
|
||||||
|
*/
|
||||||
|
#define SPI_CLR_UNIT_TRANS_INT_FLAG(spi) ((spi)->STATUS = SPI_STATUS_UNITIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable 2-bit Transfer mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear TWOBIT bit of SPI_CTL register to disable 2-bit Transfer mode.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_2BIT_MODE(spi) ((spi)->CTL &= ~SPI_CTL_TWOBIT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Slave 3-wire mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear SLV3WIRE bit of SPI_SSCTL register to disable Slave 3-wire mode.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_3WIRE_MODE(spi) ((spi)->SSCTL &= ~SPI_SSCTL_SLV3WIRE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Dual I/O mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear DUALIOEN bit of SPI_CTL register to disable Dual I/O mode.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_DUAL_MODE(spi) ((spi)->CTL &= ~SPI_CTL_DUALIOEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Quad I/O mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear QUADIOEN bit of SPI_CTL register to disable Quad I/O mode.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_QUAD_MODE(spi) ((spi)->CTL &= ~SPI_CTL_QUADIOEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable 2-bit Transfer mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set TWOBIT bit of SPI_CTL register to enable 2-bit Transfer mode.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_2BIT_MODE(spi) ((spi)->CTL |= SPI_CTL_TWOBIT_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Slave 3-wire mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set SLV3WIRE bit of SPI_SSCTL register to enable Slave 3-wire mode.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_3WIRE_MODE(spi) ((spi)->SSCTL |= SPI_SSCTL_SLV3WIRE_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Dual input mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear QDIODIR bit and set DUALIOEN bit of SPI_CTL register to enable Dual input mode.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_DUAL_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_DATDIR_Msk)) | SPI_CTL_DUALIOEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Dual output mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set QDIODIR bit and DUALIOEN bit of SPI_CTL register to enable Dual output mode.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_DUAL_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_DATDIR_Msk | SPI_CTL_DUALIOEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Quad input mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear QDIODIR bit and set QUADIOEN bit of SPI_CTL register to enable Quad input mode.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_QUAD_INPUT_MODE(spi) ((spi)->CTL = ((spi)->CTL & (~SPI_CTL_DATDIR_Msk)) | SPI_CTL_QUADIOEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Quad output mode.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set QDIODIR bit and QUADIOEN bit of SPI_CTL register to enable Quad output mode.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_QUAD_OUTPUT_MODE(spi) ((spi)->CTL |= (SPI_CTL_DATDIR_Msk | SPI_CTL_QUADIOEN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger RX PDMA function.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set RXPDMAEN bit of SPI_PDMACTL register to enable RX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define SPI_TRIGGER_RX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger TX PDMA function.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set TXPDMAEN bit of SPI_PDMACTL register to enable TX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define SPI_TRIGGER_TX_PDMA(spi) ((spi)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable RX PDMA transfer.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear RXPDMAEN bit of SPI_PDMACTL register to disable RX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_RX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable TX PDMA transfer.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear TXPDMAEN bit of SPI_PDMACTL register to disable TX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_TX_PDMA(spi) ( (spi)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the count of available data in RX FIFO.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return The count of available data in RX FIFO.
|
||||||
|
* @details Read RXCNT (SPI_STATUS[27:24]) to get the count of available data in RX FIFO.
|
||||||
|
*/
|
||||||
|
#define SPI_GET_RX_FIFO_COUNT(spi) (((spi)->STATUS & SPI_STATUS_RXCNT_Msk) >> SPI_STATUS_RXCNT_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the RX FIFO empty flag.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @retval 0 RX FIFO is not empty.
|
||||||
|
* @retval 1 RX FIFO is empty.
|
||||||
|
* @details Read RXEMPTY bit of SPI_STATUS register to get the RX FIFO empty flag.
|
||||||
|
*/
|
||||||
|
#define SPI_GET_RX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_RXEMPTY_Msk)>>SPI_STATUS_RXEMPTY_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the TX FIFO empty flag.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @retval 0 TX FIFO is not empty.
|
||||||
|
* @retval 1 TX FIFO is empty.
|
||||||
|
* @details Read TXEMPTY bit of SPI_STATUS register to get the TX FIFO empty flag.
|
||||||
|
*/
|
||||||
|
#define SPI_GET_TX_FIFO_EMPTY_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXEMPTY_Msk)>>SPI_STATUS_TXEMPTY_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the TX FIFO full flag.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @retval 0 TX FIFO is not full.
|
||||||
|
* @retval 1 TX FIFO is full.
|
||||||
|
* @details Read TXFULL bit of SPI_STATUS register to get the TX FIFO full flag.
|
||||||
|
*/
|
||||||
|
#define SPI_GET_TX_FIFO_FULL_FLAG(spi) (((spi)->STATUS & SPI_STATUS_TXFULL_Msk)>>SPI_STATUS_TXFULL_Pos)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the datum read from RX register.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return Data in RX register.
|
||||||
|
* @details Read SPI_RX register to get the received datum.
|
||||||
|
*/
|
||||||
|
#define SPI_READ_RX(spi) ((spi)->RX)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write datum to TX register.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @param[in] u32TxData The datum which user attempt to transfer through SPI bus.
|
||||||
|
* @return None.
|
||||||
|
* @details Write u32TxData to SPI_TX register.
|
||||||
|
*/
|
||||||
|
#define SPI_WRITE_TX(spi, u32TxData) ((spi)->TX = (u32TxData))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SPIx_SS pin to high state.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set SPIx_SS pin to high state.
|
||||||
|
*/
|
||||||
|
#define SPI_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~SPI_SSCTL_AUTOSS_Msk)) | (SPI_SSCTL_SSACTPOL_Msk | SPI_SSCTL_SS_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SPIx_SS pin to low state.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set SPIx_SS pin to low state.
|
||||||
|
*/
|
||||||
|
#define SPI_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & (~(SPI_SSCTL_AUTOSS_Msk | SPI_SSCTL_SSACTPOL_Msk))) | SPI_SSCTL_SS_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Byte Reorder function.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Enable Byte Reorder function. The suspend interval depends on the setting of SUSPITV (SPI_CTL[7:4]).
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE_BYTE_REORDER(spi) ((spi)->CTL |= SPI_CTL_REORDER_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Byte Reorder function.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear REORDER bit field of SPI_CTL register to disable Byte Reorder function.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE_BYTE_REORDER(spi) ((spi)->CTL &= ~SPI_CTL_REORDER_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the length of suspend interval.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @param[in] u32SuspCycle Decides the length of suspend interval. It could be 0 ~ 15.
|
||||||
|
* @return None.
|
||||||
|
* @details Set the length of suspend interval according to u32SuspCycle.
|
||||||
|
* The length of suspend interval is ((u32SuspCycle + 0.5) * the length of one SPI bus clock cycle).
|
||||||
|
*/
|
||||||
|
#define SPI_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI_CTL_SUSPITV_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the SPI transfer sequence with LSB first.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set LSB bit of SPI_CTL register to set the SPI transfer sequence with LSB first.
|
||||||
|
*/
|
||||||
|
#define SPI_SET_LSB_FIRST(spi) ((spi)->CTL |= SPI_CTL_LSB_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the SPI transfer sequence with MSB first.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear LSB bit of SPI_CTL register to set the SPI transfer sequence with MSB first.
|
||||||
|
*/
|
||||||
|
#define SPI_SET_MSB_FIRST(spi) ((spi)->CTL &= ~SPI_CTL_LSB_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the data width of a SPI transaction.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @param[in] u32Width The bit width of one transaction.
|
||||||
|
* @return None.
|
||||||
|
* @details The data width can be 8 ~ 32 bits.
|
||||||
|
*/
|
||||||
|
#define SPI_SET_DATA_WIDTH(spi, u32Width) ((spi)->CTL = ((spi)->CTL & ~SPI_CTL_DWIDTH_Msk) | (((u32Width)&0x1F) << SPI_CTL_DWIDTH_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the SPI busy state.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @retval 0 SPI controller is not busy.
|
||||||
|
* @retval 1 SPI controller is busy.
|
||||||
|
* @details This macro will return the busy state of SPI controller.
|
||||||
|
*/
|
||||||
|
#define SPI_IS_BUSY(spi) ( ((spi)->STATUS & SPI_STATUS_BUSY_Msk)>>SPI_STATUS_BUSY_Pos )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SPI controller.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set SPIEN (SPI_CTL[0]) to enable SPI controller.
|
||||||
|
*/
|
||||||
|
#define SPI_ENABLE(spi) ((spi)->CTL |= SPI_CTL_SPIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SPI controller.
|
||||||
|
* @param[in] spi The pointer of the specified SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear SPIEN (SPI_CTL[0]) to disable SPI controller.
|
||||||
|
*/
|
||||||
|
#define SPI_DISABLE(spi) ((spi)->CTL &= ~SPI_CTL_SPIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable zero cross detection function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
|
||||||
|
* - \ref SPII2S_RIGHT
|
||||||
|
* - \ref SPII2S_LEFT
|
||||||
|
* @return None
|
||||||
|
* @details This function will set RZCEN or LZCEN bit of SPI_I2SCTL register to enable zero cross detection function.
|
||||||
|
*/
|
||||||
|
static __INLINE void SPII2S_ENABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
|
||||||
|
{
|
||||||
|
if(u32ChMask == SPII2S_RIGHT)
|
||||||
|
i2s->I2SCTL |= SPI_I2SCTL_RZCEN_Msk;
|
||||||
|
else
|
||||||
|
i2s->I2SCTL |= SPI_I2SCTL_LZCEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable zero cross detection function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32ChMask The mask for left or right channel. Valid values are:
|
||||||
|
* - \ref SPII2S_RIGHT
|
||||||
|
* - \ref SPII2S_LEFT
|
||||||
|
* @return None
|
||||||
|
* @details This function will clear RZCEN or LZCEN bit of SPI_I2SCTL register to disable zero cross detection function.
|
||||||
|
*/
|
||||||
|
static __INLINE void SPII2S_DISABLE_TX_ZCD(SPI_T *i2s, uint32_t u32ChMask)
|
||||||
|
{
|
||||||
|
if(u32ChMask == SPII2S_RIGHT)
|
||||||
|
i2s->I2SCTL &= ~SPI_I2SCTL_RZCEN_Msk;
|
||||||
|
else
|
||||||
|
i2s->I2SCTL &= ~SPI_I2SCTL_LZCEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S TX DMA function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set TXPDMAEN bit of SPI_PDMACTL register to transmit data with PDMA.
|
||||||
|
*/
|
||||||
|
#define SPII2S_ENABLE_TXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S TX DMA function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear TXPDMAEN bit of SPI_PDMACTL register to disable TX DMA function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_DISABLE_TXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S RX DMA function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set RXPDMAEN bit of SPI_PDMACTL register to receive data with PDMA.
|
||||||
|
*/
|
||||||
|
#define SPII2S_ENABLE_RXDMA(i2s) ( (i2s)->PDMACTL |= SPI_PDMACTL_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S RX DMA function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear RXPDMAEN bit of SPI_PDMACTL register to disable RX DMA function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_DISABLE_RXDMA(i2s) ( (i2s)->PDMACTL &= ~SPI_PDMACTL_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S TX function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set TXEN bit of SPI_I2SCTL register to enable I2S TX function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_ENABLE_TX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_TXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S TX function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear TXEN bit of SPI_I2SCTL register to disable I2S TX function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_DISABLE_TX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_TXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable I2S RX function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set RXEN bit of SPI_I2SCTL register to enable I2S RX function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_ENABLE_RX(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_RXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable I2S RX function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear RXEN bit of SPI_I2SCTL register to disable I2S RX function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_DISABLE_RX(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_RXEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable TX Mute function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will set MUTE bit of SPI_I2SCTL register to enable I2S TX mute function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_ENABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL |= SPI_I2SCTL_MUTE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable TX Mute function.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear MUTE bit of SPI_I2SCTL register to disable I2S TX mute function.
|
||||||
|
*/
|
||||||
|
#define SPII2S_DISABLE_TX_MUTE(i2s) ( (i2s)->I2SCTL &= ~SPI_I2SCTL_MUTE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear TX FIFO.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear TX FIFO. The internal TX FIFO pointer will be reset to FIFO start point.
|
||||||
|
*/
|
||||||
|
#define SPII2S_CLR_TX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_TXFBCLR_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear RX FIFO.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear RX FIFO. The internal RX FIFO pointer will be reset to FIFO start point.
|
||||||
|
*/
|
||||||
|
#define SPII2S_CLR_RX_FIFO(i2s) ( (i2s)->FIFOCTL |= SPI_FIFOCTL_RXFBCLR_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function sets the recording source channel when mono mode is used.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32Ch left or right channel. Valid values are:
|
||||||
|
* - \ref SPII2S_MONO_LEFT
|
||||||
|
* - \ref SPII2S_MONO_RIGHT
|
||||||
|
* @return None
|
||||||
|
* @details This function selects the recording source channel of monaural mode.
|
||||||
|
*/
|
||||||
|
static __INLINE void SPII2S_SET_MONO_RX_CHANNEL(SPI_T *i2s, uint32_t u32Ch)
|
||||||
|
{
|
||||||
|
u32Ch == SPII2S_MONO_LEFT ?
|
||||||
|
(i2s->I2SCTL |= SPI_I2SCTL_RXLCH_Msk) :
|
||||||
|
(i2s->I2SCTL &= ~SPI_I2SCTL_RXLCH_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write data to I2S TX FIFO.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32Data The value written to TX FIFO.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will write a value to TX FIFO.
|
||||||
|
*/
|
||||||
|
#define SPII2S_WRITE_TX_FIFO(i2s, u32Data) ( (i2s)->TX = (u32Data) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read RX FIFO.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return The value read from RX FIFO.
|
||||||
|
* @details This function will return a value read from RX FIFO.
|
||||||
|
*/
|
||||||
|
#define SPII2S_READ_RX_FIFO(i2s) ( (i2s)->RX )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the interrupt flag.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32Mask The mask value for all interrupt flags.
|
||||||
|
* @return The interrupt flags specified by the u32mask parameter.
|
||||||
|
* @details This macro will return the combination interrupt flags of SPI_I2SSTS register. The flags are specified by the u32mask parameter.
|
||||||
|
*/
|
||||||
|
#define SPII2S_GET_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS & (u32Mask) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the interrupt flag.
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @param[in] u32Mask The mask value for all interrupt flags.
|
||||||
|
* @return None
|
||||||
|
* @details This macro will clear the interrupt flags specified by the u32mask parameter.
|
||||||
|
* @note Except TX and RX FIFO threshold interrupt flags, the other interrupt flags can be cleared by writing 1 to itself.
|
||||||
|
*/
|
||||||
|
#define SPII2S_CLR_INT_FLAG(i2s, u32Mask) ( (i2s)->I2SSTS = (u32Mask) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get transmit FIFO level
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return TX FIFO level
|
||||||
|
* @details This macro will return the number of available words in TX FIFO.
|
||||||
|
*/
|
||||||
|
#define SPII2S_GET_TX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_TXCNT_Msk) >> SPI_I2SSTS_TXCNT_Pos )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get receive FIFO level
|
||||||
|
* @param[in] i2s The pointer of the specified I2S module.
|
||||||
|
* @return RX FIFO level
|
||||||
|
* @details This macro will return the number of available words in RX FIFO.
|
||||||
|
*/
|
||||||
|
#define SPII2S_GET_RX_FIFO_LEVEL(i2s) ( ((i2s)->I2SSTS & SPI_I2SSTS_RXCNT_Msk) >> SPI_I2SSTS_RXCNT_Pos )
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/* Function prototype declaration */
|
||||||
|
uint32_t SPI_Open(SPI_T *spi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||||
|
void SPI_Close(SPI_T *spi);
|
||||||
|
void SPI_ClearRxFIFO(SPI_T *spi);
|
||||||
|
void SPI_ClearTxFIFO(SPI_T *spi);
|
||||||
|
void SPI_DisableAutoSS(SPI_T *spi);
|
||||||
|
void SPI_EnableAutoSS(SPI_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||||
|
uint32_t SPI_SetBusClock(SPI_T *spi, uint32_t u32BusClock);
|
||||||
|
void SPI_SetFIFO(SPI_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||||
|
uint32_t SPI_GetBusClock(SPI_T *spi);
|
||||||
|
void SPI_EnableInt(SPI_T *spi, uint32_t u32Mask);
|
||||||
|
void SPI_DisableInt(SPI_T *spi, uint32_t u32Mask);
|
||||||
|
uint32_t SPI_GetIntFlag(SPI_T *spi, uint32_t u32Mask);
|
||||||
|
void SPI_ClearIntFlag(SPI_T *spi, uint32_t u32Mask);
|
||||||
|
uint32_t SPI_GetStatus(SPI_T *spi, uint32_t u32Mask);
|
||||||
|
|
||||||
|
uint32_t SPII2S_Open(SPI_T *i2s, uint32_t u32MasterSlave, uint32_t u32SampleRate, uint32_t u32WordWidth, uint32_t u32Channels, uint32_t u32DataFormat);
|
||||||
|
void SPII2S_Close(SPI_T *i2s);
|
||||||
|
void SPII2S_EnableInt(SPI_T *i2s, uint32_t u32Mask);
|
||||||
|
void SPII2S_DisableInt(SPI_T *i2s, uint32_t u32Mask);
|
||||||
|
uint32_t SPII2S_EnableMCLK(SPI_T *i2s, uint32_t u32BusClock);
|
||||||
|
void SPII2S_DisableMCLK(SPI_T *i2s);
|
||||||
|
void SPII2S_SetFIFO(SPI_T *i2s, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SPI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SPI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__SPI_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,376 @@
|
||||||
|
/****************************************************************************//**
|
||||||
|
* @file spi5.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 SPI5 driver source file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI5_Driver SPI5 Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SPI5_EXPORTED_FUNCTIONS SPI5 Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function make SPI5 module be ready to transfer.
|
||||||
|
* By default, the SPI5 transfer sequence is MSB first and
|
||||||
|
* the automatic slave select function is disabled. In
|
||||||
|
* Slave mode, the u32BusClock must be NULL and the SPI5 clock
|
||||||
|
* divider setting will be 0.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32MasterSlave decides the SPI5 module is operating in master mode or in slave mode. Valid values are:
|
||||||
|
* - \ref SPI5_MASTER
|
||||||
|
* - \ref SPI5_SLAVE
|
||||||
|
* @param[in] u32SPI5Mode decides the transfer timing. Valid values are:
|
||||||
|
* - \ref SPI5_MODE_0
|
||||||
|
* - \ref SPI5_MODE_1
|
||||||
|
* - \ref SPI5_MODE_2
|
||||||
|
* - \ref SPI5_MODE_3
|
||||||
|
* @param[in] u32DataWidth decides the data width of a SPI5 transaction.
|
||||||
|
* @param[in] u32BusClock is the expected frequency of SPI5 bus clock in Hz.
|
||||||
|
* @return Actual frequency of SPI5 peripheral clock.
|
||||||
|
*/
|
||||||
|
uint32_t SPI5_Open(SPI5_T *spi,
|
||||||
|
uint32_t u32MasterSlave,
|
||||||
|
uint32_t u32SPI5Mode,
|
||||||
|
uint32_t u32DataWidth,
|
||||||
|
uint32_t u32BusClock)
|
||||||
|
{
|
||||||
|
if (!(__PC() & (1 << 28)))
|
||||||
|
{
|
||||||
|
if(u32DataWidth == 32)
|
||||||
|
u32DataWidth = 0;
|
||||||
|
|
||||||
|
spi->CTL = u32MasterSlave | (u32DataWidth << SPI5_CTL_DWIDTH_Pos) | (u32SPI5Mode);
|
||||||
|
|
||||||
|
return (SPI5_SetBusClock(spi, u32BusClock));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset SPI5 module and disable SPI5 peripheral clock.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_Close(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
if (!(__PC() & (1 << 28)))
|
||||||
|
{
|
||||||
|
/* Reset SPI5 */
|
||||||
|
if((uint32_t)spi == SPI5_BASE && (CLK->APBCLK1 & CLK_APBCLK1_SPI5CKEN_Msk))
|
||||||
|
{
|
||||||
|
CLK->APBCLK1 &= ~CLK_APBCLK1_SPI5CKEN_Msk;
|
||||||
|
SYS->IPRST2 |= SYS_IPRST2_SPI5RST_Msk;
|
||||||
|
SYS->IPRST2 &= ~SYS_IPRST2_SPI5RST_Msk;
|
||||||
|
CLK->APBCLK1 |= CLK_APBCLK1_SPI5CKEN_Msk;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear RX FIFO buffer.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_ClearRxFIFO(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
spi->FIFOCTL |= SPI5_FIFOCTL_RXFBCLR_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear TX FIFO buffer.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_ClearTxFIFO(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
spi->FIFOCTL |= SPI5_FIFOCTL_TXFBCLR_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the automatic slave select function.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_DisableAutoSS(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
spi->SSCTL &= ~SPI5_SSCTL_AUTOSS_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the automatic slave select function. Only available in Master mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32SSPinMask specifies slave select pins. (SPI5_SS)
|
||||||
|
* @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
|
||||||
|
* - \ref SPI5_SS0_ACTIVE_HIGH
|
||||||
|
* - \ref SPI5_SS0_ACTIVE_LOW
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_EnableAutoSS(SPI5_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
|
||||||
|
{
|
||||||
|
spi->SSCTL = (spi->SSCTL & ~(SPI5_SSCTL_SSACTPOL_Msk | SPI5_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI5_SSCTL_AUTOSS_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the SPI5 bus clock. Only available in Master mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32BusClock is the expected frequency of SPI5 bus clock.
|
||||||
|
* @return Actual frequency of SPI5 peripheral clock.
|
||||||
|
*/
|
||||||
|
uint32_t SPI5_SetBusClock(SPI5_T *spi, uint32_t u32BusClock)
|
||||||
|
{
|
||||||
|
if (!(__PC() & (1 << 28)))
|
||||||
|
{
|
||||||
|
uint32_t u32ClkSrc, u32HCLKFreq;
|
||||||
|
uint32_t u32Div;
|
||||||
|
|
||||||
|
/* Get system clock frequency */
|
||||||
|
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||||
|
|
||||||
|
if(u32BusClock >= u32HCLKFreq)
|
||||||
|
{
|
||||||
|
/* Select PCLK as the clock source of SPI5 */
|
||||||
|
if(spi == SPI5)
|
||||||
|
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI5SEL_Msk)) | CLK_CLKSEL2_SPI5SEL_PCLK1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Check clock source of SPI5 */
|
||||||
|
if((spi == SPI5) || (spi == SPI5_NS))
|
||||||
|
{
|
||||||
|
if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_HXT)
|
||||||
|
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||||
|
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PLL)
|
||||||
|
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||||
|
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PCLK1)
|
||||||
|
{
|
||||||
|
/* Clock source is PCLK1 */
|
||||||
|
if(CLK_GetPCLK1Freq() == u32HCLKFreq >> 1)
|
||||||
|
u32ClkSrc = (u32HCLKFreq / 2);
|
||||||
|
else
|
||||||
|
u32ClkSrc = u32HCLKFreq;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
u32ClkSrc = __HIRC; /* Clock source is HIRC */
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32BusClock >= u32HCLKFreq)
|
||||||
|
{
|
||||||
|
/* Set DIVIDER = 0 */
|
||||||
|
spi->CLKDIV = 0;
|
||||||
|
/* Return master peripheral clock rate */
|
||||||
|
return u32ClkSrc;
|
||||||
|
}
|
||||||
|
else if(u32BusClock >= u32ClkSrc)
|
||||||
|
{
|
||||||
|
/* Set DIVIDER = 0 */
|
||||||
|
spi->CLKDIV = 0;
|
||||||
|
/* Return master peripheral clock rate */
|
||||||
|
return u32ClkSrc;
|
||||||
|
}
|
||||||
|
else if(u32BusClock == 0)
|
||||||
|
{
|
||||||
|
/* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
|
||||||
|
spi->CLKDIV |= SPI5_CLKDIV_DIVIDER_Msk;
|
||||||
|
/* Return master peripheral clock rate */
|
||||||
|
return (u32ClkSrc / (0xFF + 1));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Div = (((u32ClkSrc * 10) / u32BusClock + 5) / 10) - 1; /* Round to the nearest integer */
|
||||||
|
if(u32Div > 0xFF)
|
||||||
|
{
|
||||||
|
u32Div = 0xFF;
|
||||||
|
spi->CLKDIV |= SPI5_CLKDIV_DIVIDER_Msk;
|
||||||
|
/* Return master peripheral clock rate */
|
||||||
|
return (u32ClkSrc / (0xFF + 1));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
spi->CLKDIV = (spi->CLKDIV & (~SPI5_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI5_CLKDIV_DIVIDER_Pos);
|
||||||
|
/* Return master peripheral clock rate */
|
||||||
|
return (u32ClkSrc / (u32Div + 1));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FIFO mode with user-specified TX FIFO threshold and RX FIFO threshold configurations.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32TxThreshold decides the TX FIFO threshold.
|
||||||
|
* @param[in] u32RxThreshold decides the RX FIFO threshold.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_EnableFIFO(SPI5_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
|
||||||
|
{
|
||||||
|
spi->FIFOCTL = ((spi->FIFOCTL & ~(SPI5_FIFOCTL_TXTH_Msk | SPI5_FIFOCTL_RXTH_Msk)) |
|
||||||
|
(u32TxThreshold << SPI5_FIFOCTL_TXTH_Pos) |
|
||||||
|
(u32RxThreshold << SPI5_FIFOCTL_RXTH_Pos));
|
||||||
|
|
||||||
|
spi->CTL |= SPI5_CTL_FIFOM_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable FIFO mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_DisableFIFO(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
spi->CTL &= ~SPI5_CTL_FIFOM_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the actual frequency of SPI5 bus clock. Only available in Master mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return Actual SPI5 bus clock frequency.
|
||||||
|
*/
|
||||||
|
uint32_t SPI5_GetBusClock(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
uint32_t u32Div;
|
||||||
|
uint32_t u32ClkSrc, u32HCLKFreq;
|
||||||
|
|
||||||
|
/* Get DIVIDER setting */
|
||||||
|
u32Div = (spi->CLKDIV & SPI5_CLKDIV_DIVIDER_Msk) >> SPI5_CLKDIV_DIVIDER_Pos;
|
||||||
|
|
||||||
|
/* Get system clock frequency */
|
||||||
|
u32HCLKFreq = CLK_GetHCLKFreq();
|
||||||
|
|
||||||
|
/* Check clock source of SPI5 */
|
||||||
|
if((spi == SPI5) || (spi == SPI5_NS))
|
||||||
|
{
|
||||||
|
if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_HXT)
|
||||||
|
u32ClkSrc = __HXT; /* Clock source is HXT */
|
||||||
|
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PLL)
|
||||||
|
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
|
||||||
|
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PCLK1)
|
||||||
|
{
|
||||||
|
/* Clock source is PCLK1 */
|
||||||
|
if(CLK_GetPCLK1Freq() == u32HCLKFreq >> 1)
|
||||||
|
u32ClkSrc = (u32HCLKFreq / 2);
|
||||||
|
else
|
||||||
|
u32ClkSrc = u32HCLKFreq;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
u32ClkSrc = __HIRC; /* Clock source is HIRC */
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Return SPI bus clock rate */
|
||||||
|
return (u32ClkSrc / (u32Div + 1));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable FIFO related interrupts specified by u32Mask parameter.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32Mask is the combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt bit.
|
||||||
|
* This parameter decides which interrupts will be enabled. Valid values are:
|
||||||
|
* - \ref SPI5_IE_MASK
|
||||||
|
* - \ref SPI5_SSTAIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_TXTHIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_RXTHIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_RXOVIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_TIMEOUIEN_MASK
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_EnableInt(SPI5_T *spi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
if((u32Mask & SPI5_IE_MASK) == SPI5_IE_MASK)
|
||||||
|
spi->CTL |= SPI5_CTL_UNITIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_SSTAIEN_MASK) == SPI5_SSTAIEN_MASK)
|
||||||
|
spi->SSCTL |= SPI5_SSCTL_SSTAIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_TXTHIEN_MASK) == SPI5_FIFO_TXTHIEN_MASK)
|
||||||
|
spi->FIFOCTL |= SPI5_FIFOCTL_TXTHIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_RXTHIEN_MASK) == SPI5_FIFO_RXTHIEN_MASK)
|
||||||
|
spi->FIFOCTL |= SPI5_FIFOCTL_RXTHIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_RXOVIEN_MASK) == SPI5_FIFO_RXOVIEN_MASK)
|
||||||
|
spi->FIFOCTL |= SPI5_FIFOCTL_RXOVIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_TIMEOUIEN_MASK) == SPI5_FIFO_TIMEOUIEN_MASK)
|
||||||
|
spi->FIFOCTL |= SPI5_FIFOCTL_RXTOIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable FIFO related interrupts specified by u32Mask parameter.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32Mask is the combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt bit.
|
||||||
|
* This parameter decides which interrupts will be enabled. Valid values are:
|
||||||
|
* - \ref SPI5_IE_MASK
|
||||||
|
* - \ref SPI5_SSTAIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_TXTHIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_RXTHIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_RXOVIEN_MASK
|
||||||
|
* - \ref SPI5_FIFO_TIMEOUIEN_MASK
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_DisableInt(SPI5_T *spi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
if((u32Mask & SPI5_IE_MASK) == SPI5_IE_MASK)
|
||||||
|
spi->CTL &= ~SPI5_CTL_UNITIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_SSTAIEN_MASK) == SPI5_SSTAIEN_MASK)
|
||||||
|
spi->SSCTL &= ~SPI5_SSCTL_SSTAIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_TXTHIEN_MASK) == SPI5_FIFO_TXTHIEN_MASK)
|
||||||
|
spi->FIFOCTL &= ~SPI5_FIFOCTL_TXTHIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_RXTHIEN_MASK) == SPI5_FIFO_RXTHIEN_MASK)
|
||||||
|
spi->FIFOCTL &= ~SPI5_FIFOCTL_RXTHIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_RXOVIEN_MASK) == SPI5_FIFO_RXOVIEN_MASK)
|
||||||
|
spi->FIFOCTL &= ~SPI5_FIFOCTL_RXOVIEN_Msk;
|
||||||
|
|
||||||
|
if((u32Mask & SPI5_FIFO_TIMEOUIEN_MASK) == SPI5_FIFO_TIMEOUIEN_MASK)
|
||||||
|
spi->FIFOCTL &= ~SPI5_FIFOCTL_RXTOIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable wake-up function.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_EnableWakeup(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
spi->CTL |= SPI5_CTL_WKCLKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable wake-up function.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
*/
|
||||||
|
void SPI5_DisableWakeup(SPI5_T *spi)
|
||||||
|
{
|
||||||
|
spi->CTL &= ~SPI5_CTL_WKCLKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SPI5_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SPI5_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,304 @@
|
||||||
|
/****************************************************************************//**
|
||||||
|
* @file spi5.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series SPI5 driver header file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __SPI5_H__
|
||||||
|
#define __SPI5_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SPI5_Driver SPI5 Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SPI5_EXPORTED_CONSTANTS SPI5 Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define SPI5_MODE_0 (SPI5_CTL_TXNEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
|
||||||
|
#define SPI5_MODE_1 (SPI5_CTL_RXNEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
|
||||||
|
#define SPI5_MODE_2 (SPI5_CTL_CLKPOL_Msk | SPI5_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
|
||||||
|
#define SPI5_MODE_3 (SPI5_CTL_CLKPOL_Msk | SPI5_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
|
||||||
|
|
||||||
|
#define SPI5_SLAVE (SPI5_CTL_SLAVE_Msk) /*!< Set as slave */
|
||||||
|
#define SPI5_MASTER (0x0) /*!< Set as master */
|
||||||
|
|
||||||
|
#define SPI5_SS (0x1) /*!< Set SS */
|
||||||
|
#define SPI5_SS_ACTIVE_HIGH (SPI5_SSCTL_SSACTPOL_Msk) /*!< SS active high */
|
||||||
|
#define SPI5_SS_ACTIVE_LOW (0x0) /*!< SS active low */
|
||||||
|
|
||||||
|
#define SPI5_IE_MASK (0x01) /*!< Interrupt enable mask */
|
||||||
|
#define SPI5_SSTAIEN_MASK (0x04) /*!< Slave 3-Wire mode start interrupt enable mask */
|
||||||
|
#define SPI5_FIFO_TXTHIEN_MASK (0x08) /*!< FIFO TX interrupt mask */
|
||||||
|
#define SPI5_FIFO_RXTHIEN_MASK (0x10) /*!< FIFO RX interrupt mask */
|
||||||
|
#define SPI5_FIFO_RXOVIEN_MASK (0x20) /*!< FIFO RX overrun interrupt mask */
|
||||||
|
#define SPI5_FIFO_TIMEOUIEN_MASK (0x40) /*!< FIFO timeout interrupt mask */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group M2351_SPI5_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup M2351_SPI5_EXPORTED_FUNCTIONS SPI5 Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Abort the current transfer in slave 3-wire mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSCTL |= SPI5_SSCTL_SLVABORT_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the slave 3-wire mode start interrupt flag.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI5_STATUS_SLVSTAIF_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the unit transfer interrupt flag.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI5_STATUS_UNITIF_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable slave 3-wire mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI5_SSCTL_SLV3WIRE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable slave 3-wire mode.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI5_SSCTL_SLV3WIRE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the count of available data in RX FIFO.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return The count of available data in RX FIFO.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI5_STATUS_RXCNT_Msk) >> SPI5_STATUS_RXCNT_Pos) & 0xf )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the RX FIFO empty flag.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return RX FIFO flag
|
||||||
|
* @retval 0 RX FIFO is not empty
|
||||||
|
* @retval 1 RX FIFO is empty
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI5_STATUS_RXEMPTY_Msk) == SPI5_STATUS_RXEMPTY_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the TX FIFO empty flag.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return TX FIFO flag
|
||||||
|
* @retval 0 TX FIFO is not empty
|
||||||
|
* @retval 1 TX FIFO is empty
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI5_STATUS_TXEMPTY_Msk) == SPI5_STATUS_TXEMPTY_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the TX FIFO full flag.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return TX FIFO flag
|
||||||
|
* @retval 0 TX FIFO is not full
|
||||||
|
* @retval 1 TX FIFO is full
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI5_STATUS_TXFULL_Msk) == SPI5_STATUS_TXFULL_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the datum read from RX FIFO.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return Data in RX register.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_READ_RX(spi) ((spi)->RX)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write datum to TX register.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32TxData is the datum which user attempt to transfer through SPI5 bus.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_WRITE_TX(spi, u32TxData) ( (spi)->TX = u32TxData )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SPI5_SS pin to high state.
|
||||||
|
* @param[in] spi The pointer of the specified SPI5 module.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set SPI5_SS pin to high state. Only available in Master mode.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_SET_SS_HIGH(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI5_SSCTL_AUTOSS_Msk|SPI5_SSCTL_SSACTPOL_Msk|SPI5_SS)))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SPI5_SS pin to low state.
|
||||||
|
* @param[in] spi The pointer of the specified SPI5 module.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set SPI5_SS pin to low state. Only available in Master mode.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_SET_SS_LOW(spi) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI5_SSCTL_AUTOSS_Msk|SPI5_SSCTL_SSACTPOL_Msk|SPI5_SS)) | SPI5_SS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set SPI5_SS pin to high or low state.
|
||||||
|
* @param[in] spi The pointer of the specified SPI5 module.
|
||||||
|
* @param[in] ss 0 = Set SPI5_SS to low. 1 = Set SPI5_SS to high.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set SPI5_SS pin to specified high/low state.
|
||||||
|
* Only available in Master mode.
|
||||||
|
*/
|
||||||
|
#define SPI5_SET_SS_LEVEL(spi, ss) ((spi)->SSCTL = ((spi)->SSCTL & ~(SPI5_SSCTL_AUTOSS_Msk|SPI5_SSCTL_SSACTPOL_Msk|SPI5_SSCTL_SS_Msk)) | ((ss)^1))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable byte reorder function.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI5_CTL_REORDER_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable byte reorder function.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI5_CTL_REORDER_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the length of suspend interval.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32SuspCycle decides the length of suspend interval.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI5_CTL_SUSPITV_Msk) | (u32SuspCycle << SPI5_CTL_SUSPITV_Pos) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the SPI5 transfer sequence with LSB first.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI5_CTL_LSB_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the SPI5 transfer sequence with MSB first.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI5_CTL_LSB_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the data width of a SPI5 transaction.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @param[in] u32Width is the data width (from 8-32 bits).
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
static __INLINE void SPI5_SET_DATA_WIDTH(SPI5_T *spi, uint32_t u32Width)
|
||||||
|
{
|
||||||
|
if(u32Width == 32)
|
||||||
|
u32Width = 0;
|
||||||
|
|
||||||
|
spi->CTL = (spi->CTL & ~SPI5_CTL_DWIDTH_Msk) | (u32Width << SPI5_CTL_DWIDTH_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the SPI5 busy state.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return SPI5 busy status
|
||||||
|
* @retval 0 SPI5 module is not busy
|
||||||
|
* @retval 1 SPI5 module is busy
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_IS_BUSY(spi) ( ((spi)->CTL & SPI5_CTL_GOBUSY_Msk) == SPI5_CTL_GOBUSY_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the GOBUSY bit to trigger SPI5 transfer.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_TRIGGER(spi) ( (spi)->CTL |= SPI5_CTL_GOBUSY_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger RX PDMA transfer.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI5_PDMACTL_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger TX PDMA transfer.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return none
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI5_PDMACTL_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the status register value.
|
||||||
|
* @param[in] spi is the base address of SPI5 module.
|
||||||
|
* @return status value.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define SPI5_GET_STATUS(spi) ((spi)->STATUS)
|
||||||
|
|
||||||
|
uint32_t SPI5_Open(SPI5_T *spi, uint32_t u32MasterSlave, uint32_t u32SPI5Mode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||||
|
void SPI5_Close(SPI5_T *spi);
|
||||||
|
void SPI5_ClearRxFIFO(SPI5_T *spi);
|
||||||
|
void SPI5_ClearTxFIFO(SPI5_T *spi);
|
||||||
|
void SPI5_DisableAutoSS(SPI5_T *spi);
|
||||||
|
void SPI5_EnableAutoSS(SPI5_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||||
|
uint32_t SPI5_SetBusClock(SPI5_T *spi, uint32_t u32BusClock);
|
||||||
|
void SPI5_EnableFIFO(SPI5_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
|
||||||
|
void SPI5_DisableFIFO(SPI5_T *spi);
|
||||||
|
uint32_t SPI5_GetBusClock(SPI5_T *spi);
|
||||||
|
void SPI5_EnableInt(SPI5_T *spi, uint32_t u32Mask);
|
||||||
|
void SPI5_DisableInt(SPI5_T *spi, uint32_t u32Mask);
|
||||||
|
void SPI5_EnableWakeup(SPI5_T *spi);
|
||||||
|
void SPI5_DisableWakeup(SPI5_T *spi);
|
||||||
|
/*@}*/ /* end of group SPI5_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SPI5_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__SPI5_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,227 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file sys.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series System Manager (SYS) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup SYS_Driver SYS Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup SYS_EXPORTED_FUNCTIONS SYS Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear reset source
|
||||||
|
* @param[in] u32Src is system reset source. Including :
|
||||||
|
* - \ref SYS_RSTSTS_CPULKRF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_CPURF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_MCURF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_BODRF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_LVRF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_WDTRF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_PINRF_Msk
|
||||||
|
* - \ref SYS_RSTSTS_PORF_Msk
|
||||||
|
* @return None
|
||||||
|
* @details This function clear the selected system reset source.
|
||||||
|
*/
|
||||||
|
void SYS_ClearResetSrc(uint32_t u32Src)
|
||||||
|
{
|
||||||
|
SYS->RSTSTS = u32Src;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Brown-out detector output status
|
||||||
|
* @param None
|
||||||
|
* @retval 0 System voltage is higher than BODVL setting or BODEN is 0.
|
||||||
|
* @retval 1 System voltage is lower than BODVL setting.
|
||||||
|
* @details This function get Brown-out detector output status.
|
||||||
|
*/
|
||||||
|
uint32_t SYS_GetBODStatus(void)
|
||||||
|
{
|
||||||
|
return ((SYS->BODCTL & SYS_BODCTL_BODOUT_Msk) >> SYS_BODCTL_BODOUT_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get reset status register value
|
||||||
|
* @param None
|
||||||
|
* @return Reset source
|
||||||
|
* @details This function get the system reset status register value.
|
||||||
|
*/
|
||||||
|
uint32_t SYS_GetResetSrc(void)
|
||||||
|
{
|
||||||
|
return (SYS->RSTSTS);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check if register is locked nor not
|
||||||
|
* @param None
|
||||||
|
* @retval 0 Write-protection function is disabled.
|
||||||
|
* 1 Write-protection function is enabled.
|
||||||
|
* @details This function check register write-protection bit setting.
|
||||||
|
*/
|
||||||
|
uint32_t SYS_IsRegLocked(void)
|
||||||
|
{
|
||||||
|
return !(SYS->REGLCTL & 0x1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get product ID
|
||||||
|
* @param None
|
||||||
|
* @return Product ID
|
||||||
|
* @details This function get product ID.
|
||||||
|
*/
|
||||||
|
uint32_t SYS_ReadPDID(void)
|
||||||
|
{
|
||||||
|
return SYS->PDID;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset chip with chip reset
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This function reset chip with chip reset.
|
||||||
|
* The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void SYS_ResetChip(void)
|
||||||
|
{
|
||||||
|
SYS->IPRST0 |= SYS_IPRST0_CHIPRST_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset chip with CPU reset
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This function reset CPU with CPU reset.
|
||||||
|
* The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void SYS_ResetCPU(void)
|
||||||
|
{
|
||||||
|
SYS->IPRST0 |= SYS_IPRST0_CPURST_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset selected module
|
||||||
|
* @param[in] u32ModuleIndex is module index. Including :
|
||||||
|
* - \ref PDMA0_RST
|
||||||
|
* - \ref PDMA1_RST
|
||||||
|
* - \ref EBI_RST
|
||||||
|
* - \ref USBH_RST
|
||||||
|
* - \ref SDH0_RST
|
||||||
|
* - \ref CRC_RST
|
||||||
|
* - \ref CRPT_RST
|
||||||
|
* - \ref GPIO_RST
|
||||||
|
* - \ref TMR0_RST
|
||||||
|
* - \ref TMR1_RST
|
||||||
|
* - \ref TMR2_RST
|
||||||
|
* - \ref TMR3_RST
|
||||||
|
* - \ref ACMP01_RST
|
||||||
|
* - \ref I2C0_RST
|
||||||
|
* - \ref I2C1_RST
|
||||||
|
* - \ref I2C2_RST
|
||||||
|
* - \ref SPI0_RST
|
||||||
|
* - \ref SPI1_RST
|
||||||
|
* - \ref SPI2_RST
|
||||||
|
* - \ref SPI3_RST
|
||||||
|
* - \ref SPI4_RST
|
||||||
|
* - \ref SPI5_RST
|
||||||
|
* - \ref UART0_RST
|
||||||
|
* - \ref UART1_RST
|
||||||
|
* - \ref UART2_RST
|
||||||
|
* - \ref UART3_RST
|
||||||
|
* - \ref UART4_RST
|
||||||
|
* - \ref UART5_RST
|
||||||
|
* - \ref DSRC_RST
|
||||||
|
* - \ref CAN0_RST
|
||||||
|
* - \ref OTG_RST
|
||||||
|
* - \ref USBD_RST
|
||||||
|
* - \ref EADC_RST
|
||||||
|
* - \ref I2S0_RST
|
||||||
|
* - \ref TRNG_RST
|
||||||
|
* - \ref SC0_RST
|
||||||
|
* - \ref SC1_RST
|
||||||
|
* - \ref SC2_RST
|
||||||
|
* - \ref USCI0_RST
|
||||||
|
* - \ref USCI1_RST
|
||||||
|
* - \ref DAC_RST
|
||||||
|
* - \ref PWM0_RST
|
||||||
|
* - \ref PWM1_RST
|
||||||
|
* - \ref BPWM0_RST
|
||||||
|
* - \ref BPWM1_RST
|
||||||
|
* - \ref QEI0_RST
|
||||||
|
* - \ref QEI1_RST
|
||||||
|
* - \ref ECAP0_RST
|
||||||
|
* - \ref ECAP1_RST
|
||||||
|
* @return None
|
||||||
|
* @details This function reset selected module.
|
||||||
|
*/
|
||||||
|
void SYS_ResetModule(uint32_t u32ModuleIndex)
|
||||||
|
{
|
||||||
|
/* Generate reset signal to the corresponding module */
|
||||||
|
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) |= 1 << (u32ModuleIndex & 0x00ffffff);
|
||||||
|
|
||||||
|
/* Release corresponding module from reset state */
|
||||||
|
*(volatile uint32_t *)((uint32_t)&SYS->IPRST0 + (u32ModuleIndex >> 24)) &= ~(1 << (u32ModuleIndex & 0x00ffffff));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable and configure Brown-out detector function
|
||||||
|
* @param[in] i32Mode is reset or interrupt mode. Including :
|
||||||
|
* - \ref SYS_BODCTL_BOD_RST_EN
|
||||||
|
* - \ref SYS_BODCTL_BOD_INTERRUPT_EN
|
||||||
|
* @param[in] u32BODLevel is Brown-out voltage level. Including :
|
||||||
|
* - \ref SYS_BODCTL_BODVL_1_6V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_1_8V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_2_0V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_2_2V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_2_4V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_2_6V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_2_8V
|
||||||
|
* - \ref SYS_BODCTL_BODVL_3_0V
|
||||||
|
* @return None
|
||||||
|
* @details This function configure Brown-out detector reset or interrupt mode, enable Brown-out function and set Brown-out voltage level.
|
||||||
|
* The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void SYS_EnableBOD(int32_t i32Mode, uint32_t u32BODLevel)
|
||||||
|
{
|
||||||
|
/* Enable Brown-out Detector function */
|
||||||
|
SYS->BODCTL |= SYS_BODCTL_BODEN_Msk;
|
||||||
|
|
||||||
|
/* Enable Brown-out interrupt or reset function */
|
||||||
|
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODRSTEN_Msk) | i32Mode;
|
||||||
|
|
||||||
|
/* Select Brown-out Detector threshold voltage */
|
||||||
|
SYS->BODCTL = (SYS->BODCTL & ~SYS_BODCTL_BODVL_Msk) | u32BODLevel;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Brown-out detector function
|
||||||
|
* @param None
|
||||||
|
* @return None
|
||||||
|
* @details This function disable Brown-out detector function.
|
||||||
|
* The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void SYS_DisableBOD(void)
|
||||||
|
{
|
||||||
|
SYS->BODCTL &= ~SYS_BODCTL_BODEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SYS_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group SYS_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,409 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file timer.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Timer Controller(Timer) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_Driver TIMER Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Open Timer with Operate Mode and Frequency
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Mode Operation mode. Possible options are
|
||||||
|
* - \ref TIMER_ONESHOT_MODE
|
||||||
|
* - \ref TIMER_PERIODIC_MODE
|
||||||
|
* - \ref TIMER_TOGGLE_MODE
|
||||||
|
* - \ref TIMER_CONTINUOUS_MODE
|
||||||
|
* @param[in] u32Freq Target working frequency
|
||||||
|
*
|
||||||
|
* @return Real timer working frequency
|
||||||
|
*
|
||||||
|
* @details This API is used to configure timer to operate in specified mode and frequency.
|
||||||
|
* If timer cannot work in target frequency, a closest frequency will be chose and returned.
|
||||||
|
* @note After calling this API, Timer is \b NOT running yet. But could start timer running be calling
|
||||||
|
* \ref TIMER_Start macro or program registers directly.
|
||||||
|
*/
|
||||||
|
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq)
|
||||||
|
{
|
||||||
|
uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||||||
|
uint32_t u32Cmpr = 0UL, u32Prescale = 0UL;
|
||||||
|
|
||||||
|
/* Fastest possible timer working freq is (u32Clk / 2). While cmpr = 2, prescaler = 0. */
|
||||||
|
if(u32Freq > (u32Clk / 2UL))
|
||||||
|
{
|
||||||
|
u32Cmpr = 2UL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(u32Clk > 64000000UL)
|
||||||
|
{
|
||||||
|
u32Prescale = 7UL; /* real prescaler value is 8 */
|
||||||
|
u32Clk >>= 3;
|
||||||
|
}
|
||||||
|
else if(u32Clk > 32000000UL)
|
||||||
|
{
|
||||||
|
u32Prescale = 3UL; /* real prescaler value is 4 */
|
||||||
|
u32Clk >>= 2;
|
||||||
|
}
|
||||||
|
else if(u32Clk > 16000000UL)
|
||||||
|
{
|
||||||
|
u32Prescale = 1UL; /* real prescaler value is 2 */
|
||||||
|
u32Clk >>= 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
u32Cmpr = u32Clk / u32Freq;
|
||||||
|
}
|
||||||
|
|
||||||
|
timer->CTL = u32Mode | u32Prescale;
|
||||||
|
timer->CMP = u32Cmpr;
|
||||||
|
|
||||||
|
return(u32Clk / (u32Cmpr * (u32Prescale + 1UL)));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop Timer Counting
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This API stops timer counting and disable all timer interrupt function.
|
||||||
|
*/
|
||||||
|
void TIMER_Close(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL = 0UL;
|
||||||
|
timer->EXTCTL = 0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Create a specify Delay Time
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Usec Delay period in micro seconds. Valid values are between 100~1000000 (100 micro second ~ 1 second).
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This API is used to create a delay loop for u32usec micro seconds by using timer one-shot mode.
|
||||||
|
* @note This API overwrites the register setting of the timer used to count the delay time.
|
||||||
|
* @note This API use polling mode. So there is no need to enable interrupt for the timer module used to generate delay.
|
||||||
|
*/
|
||||||
|
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec)
|
||||||
|
{
|
||||||
|
uint32_t u32Clk = TIMER_GetModuleClock(timer);
|
||||||
|
uint32_t u32Prescale = 0UL, delay = (SystemCoreClock / u32Clk) + 1UL;
|
||||||
|
uint32_t u32Cmpr, u32NsecPerTick;
|
||||||
|
|
||||||
|
// Clear current timer configuration/
|
||||||
|
timer->CTL = 0UL;
|
||||||
|
timer->EXTCTL = 0UL;
|
||||||
|
|
||||||
|
if(u32Clk <= 1000000UL) /* min delay is 1000 us if timer clock source is <= 1 MHz */
|
||||||
|
{
|
||||||
|
if(u32Usec < 1000UL)
|
||||||
|
{
|
||||||
|
u32Usec = 1000UL;
|
||||||
|
}
|
||||||
|
if(u32Usec > 1000000UL)
|
||||||
|
{
|
||||||
|
u32Usec = 1000000UL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(u32Usec < 100UL)
|
||||||
|
{
|
||||||
|
u32Usec = 100UL;
|
||||||
|
}
|
||||||
|
if(u32Usec > 1000000UL)
|
||||||
|
{
|
||||||
|
u32Usec = 1000000UL;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32Clk <= 1000000)
|
||||||
|
{
|
||||||
|
u32Prescale = 0;
|
||||||
|
u32NsecPerTick = 1000000000 / u32Clk;
|
||||||
|
u32Cmpr = (u32Usec * 1000) / u32NsecPerTick;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
if(u32Clk > 64000000UL)
|
||||||
|
{
|
||||||
|
u32Prescale = 7UL; /* real prescaler value is 8 */
|
||||||
|
u32Clk >>= 3;
|
||||||
|
}
|
||||||
|
else if(u32Clk > 32000000UL)
|
||||||
|
{
|
||||||
|
u32Prescale = 3UL; /* real prescaler value is 4 */
|
||||||
|
u32Clk >>= 2;
|
||||||
|
}
|
||||||
|
else if(u32Clk > 16000000UL)
|
||||||
|
{
|
||||||
|
u32Prescale = 1UL; /* real prescaler value is 2 */
|
||||||
|
u32Clk >>= 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32Usec < 250UL)
|
||||||
|
{
|
||||||
|
u32Cmpr = (u32Usec * u32Clk) / 1000000UL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32NsecPerTick = 1000000000UL / u32Clk;
|
||||||
|
u32Cmpr = (u32Usec * 1000UL) / u32NsecPerTick;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
timer->CMP = u32Cmpr;
|
||||||
|
timer->CTL = TIMER_CTL_CNTEN_Msk | TIMER_ONESHOT_MODE | u32Prescale;
|
||||||
|
|
||||||
|
// When system clock is faster than timer clock, it is possible timer active bit cannot set in time while we check it.
|
||||||
|
// And the while loop below return immediately, so put a tiny delay here allowing timer start counting and raise active flag.
|
||||||
|
for(; delay > 0UL; delay--)
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
|
||||||
|
while(timer->CTL & TIMER_CTL_ACTSTS_Msk)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Timer Capture Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32CapMode Timer capture mode. Could be
|
||||||
|
* - \ref TIMER_CAPTURE_FREE_COUNTING_MODE
|
||||||
|
* - \ref TIMER_CAPTURE_COUNTER_RESET_MODE
|
||||||
|
* @param[in] u32Edge Timer capture trigger edge. Possible values are
|
||||||
|
* - \ref TIMER_CAPTURE_EVENT_FALLING
|
||||||
|
* - \ref TIMER_CAPTURE_EVENT_RISING
|
||||||
|
* - \ref TIMER_CAPTURE_EVENT_FALLING_RISING
|
||||||
|
* - \ref TIMER_CAPTURE_EVENT_RISING_FALLING
|
||||||
|
* - \ref TIMER_CAPTURE_EVENT_GET_LOW_PERIOD
|
||||||
|
* - \ref TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This API is used to enable timer capture function with specify capture trigger edge \n
|
||||||
|
* to get current counter value or reset counter value to 0.
|
||||||
|
* @note Timer frequency should be configured separately by using \ref TIMER_Open API, or program registers directly.
|
||||||
|
*/
|
||||||
|
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge)
|
||||||
|
{
|
||||||
|
timer->EXTCTL = (timer->EXTCTL & ~(TIMER_EXTCTL_CAPFUNCS_Msk | TIMER_EXTCTL_CAPEDGE_Msk)) |
|
||||||
|
u32CapMode | u32Edge | TIMER_EXTCTL_CAPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Timer Capture Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This API is used to disable the timer capture function.
|
||||||
|
*/
|
||||||
|
void TIMER_DisableCapture(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Timer Counter Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Edge Detection edge of counter pin. Could be ether
|
||||||
|
* - \ref TIMER_COUNTER_EVENT_FALLING, or
|
||||||
|
* - \ref TIMER_COUNTER_EVENT_RISING
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the timer counter function with specify detection edge.
|
||||||
|
* @note Timer compare value should be configured separately by using \ref TIMER_SET_CMP_VALUE macro or program registers directly.
|
||||||
|
* @note While using event counter function, \ref TIMER_TOGGLE_MODE cannot set as timer operation mode.
|
||||||
|
*/
|
||||||
|
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge)
|
||||||
|
{
|
||||||
|
timer->EXTCTL = (timer->EXTCTL & ~TIMER_EXTCTL_CNTPHASE_Msk) | u32Edge;
|
||||||
|
timer->CTL |= TIMER_CTL_EXTCNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Timer Counter Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This API is used to disable the timer event counter function.
|
||||||
|
*/
|
||||||
|
void TIMER_DisableEventCounter(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL &= ~TIMER_CTL_EXTCNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Timer Clock Frequency
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return Timer clock frequency
|
||||||
|
*
|
||||||
|
* @details This API is used to get the timer clock frequency.
|
||||||
|
* @note This API cannot return correct clock rate if timer source is from external clock input.
|
||||||
|
*/
|
||||||
|
uint32_t TIMER_GetModuleClock(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
uint32_t u32Src, u32Clk;
|
||||||
|
const uint32_t au32Clk[] = {__HXT, __LXT, 0UL, 0UL, 0UL, __LIRC, 0UL, __HIRC};
|
||||||
|
|
||||||
|
if(timer == TIMER0)
|
||||||
|
{
|
||||||
|
u32Src = CLK_GetModuleClockSource(TMR0_MODULE);
|
||||||
|
}
|
||||||
|
else if(timer == TIMER1)
|
||||||
|
{
|
||||||
|
u32Src = CLK_GetModuleClockSource(TMR1_MODULE);
|
||||||
|
}
|
||||||
|
else if((timer == TIMER2) || (timer == TIMER2_NS))
|
||||||
|
{
|
||||||
|
u32Src = CLK_GetModuleClockSource(TMR2_MODULE);
|
||||||
|
}
|
||||||
|
else /* Timer 3 */
|
||||||
|
{
|
||||||
|
u32Src = CLK_GetModuleClockSource(TMR3_MODULE);
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32Src == 2UL)
|
||||||
|
{
|
||||||
|
if((timer == TIMER0) || (timer == TIMER1))
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Clk = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Clk = au32Clk[u32Src];
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Clk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Timer Frequency Counter Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32DropCount This parameter has no effect in this BSP
|
||||||
|
* @param[in] u32Timeout This parameter has no effect in this BSP
|
||||||
|
* @param[in] u32EnableInt Enable interrupt assertion after capture complete or not. Valid values are TRUE and FALSE
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the Timer frequency counter function for
|
||||||
|
* calculate input event frequency. After enable this function, a pair of timers,
|
||||||
|
* TIMER0 and TIMER1, or TIMER2 and TIMER3 will be configured for this function.
|
||||||
|
* The mode used to calculate input event frequency is mentioned as
|
||||||
|
* "Inter Timer Trigger Mode" in Technical Reference Manual.
|
||||||
|
*/
|
||||||
|
void TIMER_EnableFreqCounter(TIMER_T *timer,
|
||||||
|
uint32_t u32DropCount,
|
||||||
|
uint32_t u32Timeout,
|
||||||
|
uint32_t u32EnableInt)
|
||||||
|
{
|
||||||
|
TIMER_T *t; /* store the timer base to configure compare value */
|
||||||
|
|
||||||
|
if(timer == TIMER0)
|
||||||
|
t = TIMER1;
|
||||||
|
else if(timer == TIMER2)
|
||||||
|
t = TIMER3;
|
||||||
|
else if(timer == TIMER2_NS)
|
||||||
|
t = TIMER3_NS;
|
||||||
|
else
|
||||||
|
return ;
|
||||||
|
|
||||||
|
t->CMP = 0xFFFFFFUL;
|
||||||
|
t->EXTCTL = u32EnableInt ? TIMER_EXTCTL_CAPIEN_Msk : 0;
|
||||||
|
timer->CTL = TIMER_CTL_INTRGEN_Msk | TIMER_CTL_CNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Timer Frequency Counter Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @brief This function is used to disable the Timer frequency counter function.
|
||||||
|
*/
|
||||||
|
void TIMER_DisableFreqCounter(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL &= ~TIMER_CTL_INTRGEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Modules Trigger Source
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Src Selects the interrupt source to trigger other modules. Could be:
|
||||||
|
* - \ref TIMER_TRGSRC_TIMEOUT_EVENT
|
||||||
|
* - \ref TIMER_TRGSRC_CAPTURE_EVENT
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @brief This function is used to select the interrupt source used to trigger other modules.
|
||||||
|
*/
|
||||||
|
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src)
|
||||||
|
{
|
||||||
|
timer->TRGCTL = (timer->TRGCTL & ~TIMER_TRGCTL_TRGSSEL_Msk) | u32Src;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Target Modules to Trigger by Timer Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Mask The mask of modules (PWM, EADC, DAC and PDMA) trigger by timer. Is the combination of
|
||||||
|
* - \ref TIMER_TRG_TO_PWM,
|
||||||
|
* - \ref TIMER_TRG_TO_EADC,
|
||||||
|
* - \ref TIMER_TRG_TO_DAC and
|
||||||
|
* - \ref TIMER_TRG_TO_PDMA
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to set PWM, EADC, DAC and PDMA module trigger by timer interrupt event.
|
||||||
|
*/
|
||||||
|
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
timer->TRGCTL = (timer->TRGCTL & ~(TIMER_TRGCTL_TRGPWM_Msk | TIMER_TRGCTL_TRGDAC_Msk | TIMER_TRGCTL_TRGEADC_Msk | TIMER_TRGCTL_TRGPDMA_Msk)) | u32Mask;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,478 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file timer.h
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 2 $
|
||||||
|
* $Date: 16/07/29 3:12p $
|
||||||
|
* @brief Timer Controller(Timer) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __TIMER_H__
|
||||||
|
#define __TIMER_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_Driver TIMER Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_EXPORTED_CONSTANTS TIMER Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* TIMER Operation Mode, External Counter and Capture Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TIMER_ONESHOT_MODE (0UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in one-shot mode */
|
||||||
|
#define TIMER_PERIODIC_MODE (1UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in periodic mode */
|
||||||
|
#define TIMER_TOGGLE_MODE (2UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in toggle-output mode */
|
||||||
|
#define TIMER_CONTINUOUS_MODE (3UL << TIMER_CTL_OPMODE_Pos) /*!< Timer working in continuous counting mode */
|
||||||
|
#define TIMER_TOUT_PIN_FROM_TM (0UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx pin */
|
||||||
|
#define TIMER_TOUT_PIN_FROM_TM_EXT (1UL << TIMER_CTL_TGLPINSEL_Pos) /*!< Timer toggle-output pin is from Tx_EXT pin */
|
||||||
|
|
||||||
|
#define TIMER_COUNTER_EVENT_FALLING (0UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on falling edge detection */
|
||||||
|
#define TIMER_COUNTER_EVENT_RISING (1UL << TIMER_EXTCTL_CNTPHASE_Pos) /*!< Counter increase on rising edge detection */
|
||||||
|
#define TIMER_CAPTURE_FREE_COUNTING_MODE (0UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to get timer counter value */
|
||||||
|
#define TIMER_CAPTURE_COUNTER_RESET_MODE (1UL << TIMER_EXTCTL_CAPFUNCS_Pos) /*!< Timer capture event to reset timer counter */
|
||||||
|
|
||||||
|
#define TIMER_CAPTURE_EVENT_FALLING (0UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Falling edge detection to trigger capture event */
|
||||||
|
#define TIMER_CAPTURE_EVENT_RISING (1UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Rising edge detection to trigger capture event */
|
||||||
|
#define TIMER_CAPTURE_EVENT_FALLING_RISING (2UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both falling and rising edge detection to trigger capture event, and first event at falling edge */
|
||||||
|
#define TIMER_CAPTURE_EVENT_RISING_FALLING (3UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< Both rising and falling edge detection to trigger capture event, and first event at rising edge */
|
||||||
|
#define TIMER_CAPTURE_EVENT_GET_LOW_PERIOD (6UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at falling edge, follows are at at rising edge */
|
||||||
|
#define TIMER_CAPTURE_EVENT_GET_HIGH_PERIOD (7UL << TIMER_EXTCTL_CAPEDGE_Pos) /*!< First capture event is at rising edge, follows are at at falling edge */
|
||||||
|
|
||||||
|
#define TIMER_TRGSRC_TIMEOUT_EVENT (0UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer time-out event */
|
||||||
|
#define TIMER_TRGSRC_CAPTURE_EVENT (1UL << TIMER_TRGCTL_TRGSSEL_Pos) /*!< Select internal trigger source from timer capture event */
|
||||||
|
#define TIMER_TRG_TO_PWM (TIMER_TRGCTL_TRGPWM_Msk) /*!< Each timer event as PWM counter clock source */
|
||||||
|
#define TIMER_TRG_TO_EADC (TIMER_TRGCTL_TRGEADC_Msk) /*!< Each timer event to start ADC conversion */
|
||||||
|
#define TIMER_TRG_TO_DAC (TIMER_TRGCTL_TRGDAC_Msk) /*!< Each timer event to start DAC conversion */
|
||||||
|
#define TIMER_TRG_TO_PDMA (TIMER_TRGCTL_TRGPDMA_Msk) /*!< Each timer event to trigger PDMA transfer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_EXPORTED_FUNCTIONS TIMER Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Timer Compared Value
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Value Timer compare value. Valid values are between 2 to 0xFFFFFF.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set timer compared value to adjust timer time-out interval.
|
||||||
|
* @note 1. Never write 0x0 or 0x1 in this field, or the core will run into unknown state. \n
|
||||||
|
* 2. If update timer compared value in continuous counting mode, timer counter value will keep counting continuously. \n
|
||||||
|
* But if timer is operating at other modes, the timer up counter will restart counting and start from 0.
|
||||||
|
*/
|
||||||
|
#define TIMER_SET_CMP_VALUE(timer, u32Value) ((timer)->CMP = (u32Value))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Timer Prescale Value
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Value Timer prescale value. Valid values are between 0 to 0xFF.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set timer prescale value and timer source clock will be divided by (prescale + 1) \n
|
||||||
|
* before it is fed into timer.
|
||||||
|
*/
|
||||||
|
#define TIMER_SET_PRESCALE_VALUE(timer, u32Value) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_PSC_Msk) | (u32Value))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check specify Timer Status
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Timer 24-bit up counter is inactive
|
||||||
|
* @retval 1 Timer 24-bit up counter is active
|
||||||
|
*
|
||||||
|
* @details This macro is used to check if specify Timer counter is inactive or active.
|
||||||
|
*/
|
||||||
|
#define TIMER_IS_ACTIVE(timer) (((timer)->CTL & TIMER_CTL_ACTSTS_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select Toggle-output Pin
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32ToutSel Toggle-output pin selection, valid values are:
|
||||||
|
* - \ref TIMER_TOUT_PIN_FROM_TM
|
||||||
|
* - \ref TIMER_TOUT_PIN_FROM_TM_EXT
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to select timer toggle-output pin is output on TMx or TMx_EXT pin.
|
||||||
|
*/
|
||||||
|
#define TIMER_SELECT_TOUT_PIN(timer, u32ToutSel) ((timer)->CTL = ((timer)->CTL & ~TIMER_CTL_TGLPINSEL_Msk) | (u32ToutSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start Timer Counting
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to start Timer counting.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_Start(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL |= TIMER_CTL_CNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop Timer Counting
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to stop/suspend Timer counting.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_Stop(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL &= ~TIMER_CTL_CNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Timer Interrupt Wake-up Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the timer interrupt wake-up function and interrupt source could be time-out interrupt, \n
|
||||||
|
* counter event interrupt or capture trigger interrupt.
|
||||||
|
* @note To wake the system from Power-down mode, timer clock source must be ether LXT or LIRC.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_EnableWakeup(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL |= TIMER_CTL_WKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Timer Wake-up Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable the timer interrupt wake-up function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_DisableWakeup(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL &= ~TIMER_CTL_WKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start Timer Capture Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to start Timer capture function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_StartCapture(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL |= TIMER_EXTCTL_CAPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop Timer Capture Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to stop Timer capture function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_StopCapture(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL &= ~TIMER_EXTCTL_CAPEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Capture Pin De-bounce
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the detect de-bounce function of capture pin.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_EnableCaptureDebounce(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL |= TIMER_EXTCTL_CAPDBEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Capture Pin De-bounce
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable the detect de-bounce function of capture pin.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_DisableCaptureDebounce(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL &= ~TIMER_EXTCTL_CAPDBEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Counter Pin De-bounce
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the detect de-bounce function of counter pin.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_EnableEventCounterDebounce(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL |= TIMER_EXTCTL_CNTDBEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Counter Pin De-bounce
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable the detect de-bounce function of counter pin.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_DisableEventCounterDebounce(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL &= ~TIMER_EXTCTL_CNTDBEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Timer Time-out Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the timer time-out interrupt function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_EnableInt(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL |= TIMER_CTL_INTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Timer Time-out Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable the timer time-out interrupt function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_DisableInt(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CTL &= ~TIMER_CTL_INTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Capture Trigger Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable the timer capture trigger interrupt function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_EnableCaptureInt(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL |= TIMER_EXTCTL_CAPIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Capture Trigger Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable the timer capture trigger interrupt function.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_DisableCaptureInt(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EXTCTL &= ~TIMER_EXTCTL_CAPIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Timer Time-out Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Timer time-out interrupt did not occur
|
||||||
|
* @retval 1 Timer time-out interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This function indicates timer time-out interrupt occurred or not.
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t TIMER_GetIntFlag(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
return ((timer->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1UL : 0UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Timer Time-out Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function clears timer time-out interrupt flag to 0.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_ClearIntFlag(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->INTSTS = TIMER_INTSTS_TIF_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Timer Capture Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Timer capture interrupt did not occur
|
||||||
|
* @retval 1 Timer capture interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This function indicates timer capture trigger interrupt occurred or not.
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t TIMER_GetCaptureIntFlag(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
return timer->EINTSTS;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Timer Capture Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function clears timer capture trigger interrupt flag to 0.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_ClearCaptureIntFlag(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->EINTSTS = TIMER_EINTSTS_CAPIF_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Timer Wake-up Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Timer does not cause CPU wake-up
|
||||||
|
* @retval 1 Timer interrupt event cause CPU wake-up
|
||||||
|
*
|
||||||
|
* @details This function indicates timer interrupt event has waked up system or not.
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t TIMER_GetWakeupFlag(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
return (timer->INTSTS & TIMER_INTSTS_TWKF_Msk ? 1UL : 0UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Timer Wake-up Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function clears the timer wake-up system flag to 0.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_ClearWakeupFlag(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->INTSTS = TIMER_INTSTS_TWKF_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Capture value
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return 24-bit Capture Value
|
||||||
|
*
|
||||||
|
* @details This function reports the current 24-bit timer capture value.
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t TIMER_GetCaptureData(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
return timer->CAP;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Counter value
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return 24-bit Counter Value
|
||||||
|
*
|
||||||
|
* @details This function reports the current 24-bit timer counter value.
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t TIMER_GetCounter(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
return timer->CNT;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset Counter
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to reset current counter value and internal prescale counter value.
|
||||||
|
*/
|
||||||
|
static __INLINE void TIMER_ResetCounter(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->CNT = 0UL;
|
||||||
|
while(timer->CNT)
|
||||||
|
{
|
||||||
|
;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t TIMER_Open(TIMER_T *timer, uint32_t u32Mode, uint32_t u32Freq);
|
||||||
|
void TIMER_Close(TIMER_T *timer);
|
||||||
|
void TIMER_Delay(TIMER_T *timer, uint32_t u32Usec);
|
||||||
|
void TIMER_EnableCapture(TIMER_T *timer, uint32_t u32CapMode, uint32_t u32Edge);
|
||||||
|
void TIMER_DisableCapture(TIMER_T *timer);
|
||||||
|
void TIMER_EnableEventCounter(TIMER_T *timer, uint32_t u32Edge);
|
||||||
|
void TIMER_DisableEventCounter(TIMER_T *timer);
|
||||||
|
uint32_t TIMER_GetModuleClock(TIMER_T *timer);
|
||||||
|
void TIMER_EnableFreqCounter(TIMER_T *timer, uint32_t u32DropCount, uint32_t u32Timeout, uint32_t u32EnableInt);
|
||||||
|
void TIMER_DisableFreqCounter(TIMER_T *timer);
|
||||||
|
void TIMER_SetTriggerSource(TIMER_T *timer, uint32_t u32Src);
|
||||||
|
void TIMER_SetTriggerTarget(TIMER_T *timer, uint32_t u32Mask);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __TIMER_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,451 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file timer.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Timer PWM Controller(Timer PWM) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set PWM Counter Clock Source
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32CntClkSrc PWM counter clock source, could be one of following source
|
||||||
|
* - \ref TPWM_CNTR_CLKSRC_TMR_CLK
|
||||||
|
* - \ref TPWM_CNTR_CLKSRC_TIMER0_INT
|
||||||
|
* - \ref TPWM_CNTR_CLKSRC_TIMER1_INT
|
||||||
|
* - \ref TPWM_CNTR_CLKSRC_TIMER2_INT
|
||||||
|
* - \ref TPWM_CNTR_CLKSRC_TIMER3_INT
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to set PWM counter clock source.
|
||||||
|
*/
|
||||||
|
void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc)
|
||||||
|
{
|
||||||
|
(timer)->PWMCLKSRC = ((timer)->PWMCLKSRC & ~TIMER_PWMCLKSRC_CLKSRC_Msk) | u32CntClkSrc;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure PWM Output Frequency and Duty Cycle
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Frequency Target generator frequency.
|
||||||
|
* @param[in] u32DutyCycle Target generator duty cycle percentage. Valid range are between 0~100. 10 means 10%, 20 means 20%...
|
||||||
|
*
|
||||||
|
* @return Nearest frequency clock in nano second
|
||||||
|
*
|
||||||
|
* @details This API is used to configure PWM output frequency and duty cycle in up count type and auto-reload operation mode.
|
||||||
|
* @note This API is only available if Timer PWM counter clock source is from TMRx_CLK.
|
||||||
|
*/
|
||||||
|
uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle)
|
||||||
|
{
|
||||||
|
uint32_t u32PWMClockFreq, u32TargetFreq;
|
||||||
|
uint32_t u32Prescaler = 0x1000UL, u32Period, u32CMP;
|
||||||
|
|
||||||
|
if((timer == TIMER0) || (timer == TIMER1))
|
||||||
|
{
|
||||||
|
u32PWMClockFreq = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32PWMClockFreq = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Calculate u16PERIOD and u16PSC */
|
||||||
|
for(u32Prescaler = 1UL; u32Prescaler <= 0x1000UL; u32Prescaler++)
|
||||||
|
{
|
||||||
|
u32Period = (u32PWMClockFreq / u32Prescaler) / u32Frequency;
|
||||||
|
|
||||||
|
/* If target u32Period is larger than 0x10000, need to use a larger prescaler */
|
||||||
|
if(u32Period <= 0x10000UL)
|
||||||
|
{
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
/* Store return value here 'cos we're gonna change u32Prescaler & u32Period to the real value to fill into register */
|
||||||
|
u32TargetFreq = (u32PWMClockFreq / u32Prescaler) / u32Period;
|
||||||
|
|
||||||
|
/* Set PWM to up count type */
|
||||||
|
timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | (TPWM_UP_COUNT << TIMER_PWMCTL_CNTTYPE_Pos);
|
||||||
|
|
||||||
|
/* Set PWM to auto-reload mode */
|
||||||
|
timer->PWMCTL = (timer->PWMCTL & ~TIMER_PWMCTL_CNTMODE_Msk) | (TPWM_AUTO_RELOAD_MODE << TIMER_PWMCTL_CNTMODE_Pos);
|
||||||
|
|
||||||
|
/* Convert to real register value */
|
||||||
|
TPWM_SET_PRESCALER(timer, (u32Prescaler - 1UL));
|
||||||
|
|
||||||
|
TPWM_SET_PERIOD(timer, (u32Period - 1UL));
|
||||||
|
if(u32DutyCycle)
|
||||||
|
{
|
||||||
|
u32CMP = (u32DutyCycle * u32Period) / 100UL;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32CMP = 0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
TPWM_SET_CMPDAT(timer, u32CMP);
|
||||||
|
|
||||||
|
return (u32TargetFreq);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Dead-Time Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable Dead-Time function and counter source is the same as Timer PWM clock source.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount)
|
||||||
|
{
|
||||||
|
timer->PWMDTCTL = TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Dead-Time Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32DTCount Dead-Time duration in PWM clock count, valid values are between 0x0~0xFFF, but 0x0 means there is no Dead-Time insertion.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable Dead-Time function and counter source is the Timer PWM clock source with prescale.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount)
|
||||||
|
{
|
||||||
|
timer->PWMDTCTL = TIMER_PWMDTCTL_DTCKSEL_Msk | TIMER_PWMDTCTL_DTEN_Msk | u32DTCount;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Dead-Time Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable Dead-time of selected channel.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_DisableDeadTime(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMDTCTL = 0x0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable PWM Counter
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable PWM generator and start counter counting.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableCounter(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable PWM Generator
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable PWM counter immediately by clear CNTEN (TIMERx_PWMCTL[0]) bit.
|
||||||
|
*/
|
||||||
|
void TPWM_DisableCounter(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMCTL &= ~TIMER_PWMCTL_CNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Trigger EADC
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32Condition The condition to trigger EADC. It could be one of following conditions:
|
||||||
|
* - \ref TPWM_TRIGGER_EADC_AT_ZERO_POINT
|
||||||
|
* - \ref TPWM_TRIGGER_EADC_AT_PERIOD_POINT
|
||||||
|
* - \ref TPWM_TRIGGER_EADC_AT_ZERO_OR_PERIOD_POINT
|
||||||
|
* - \ref TPWM_TRIGGER_EADC_AT_COMPARE_UP_COUNT_POINT
|
||||||
|
* - \ref TPWM_TRIGGER_EADC_AT_COMPARE_DOWN_COUNT_POINT
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable specified counter compare event to trigger EADC.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableTriggerEADC(TIMER_T *timer, uint32_t u32Condition)
|
||||||
|
{
|
||||||
|
timer->PWMEADCTS = TIMER_PWMEADCTS_TRGEN_Msk | (u32Condition << TIMER_PWMEADCTS_TRGSEL_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Trigger EADC
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable counter compare event to trigger EADC.
|
||||||
|
*/
|
||||||
|
void TPWM_DisableTriggerEADC(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMEADCTS = 0x0UL;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Fault Brake Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32CH0Level PWMx_CH0 output level while fault brake event occurs. Valid value is one of following setting
|
||||||
|
* - \ref TPWM_OUTPUT_TOGGLE
|
||||||
|
* - \ref TPWM_OUTPUT_NOTHING
|
||||||
|
* - \ref TPWM_OUTPUT_LOW
|
||||||
|
* - \ref TPWM_OUTPUT_HIGH
|
||||||
|
* @param[in] u32CH1Level PWMx_CH1 output level while fault brake event occurs. Valid value is one of following setting
|
||||||
|
* - \ref TPWM_OUTPUT_TOGGLE
|
||||||
|
* - \ref TPWM_OUTPUT_NOTHING
|
||||||
|
* - \ref TPWM_OUTPUT_LOW
|
||||||
|
* - \ref TPWM_OUTPUT_HIGH
|
||||||
|
* @param[in] u32BrakeSource Fault brake source, combination of following source
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP0
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_ACMP1
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_BKPIN
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_CSS
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_BOD
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_COR
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_EDGE_SYS_RAM
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP0
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_ACMP1
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_BKPIN
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_COR
|
||||||
|
* - \ref TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable fault brake function.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource)
|
||||||
|
{
|
||||||
|
timer->PWMFAILBRK |= ((u32BrakeSource >> 16) & 0xFUL);
|
||||||
|
timer->PWMBRKCTL |= (u32BrakeSource & 0xFFFFUL) | (u32CH0Level << TIMER_PWMBRKCTL_BRKAEVEN_Pos) | (u32CH1Level << TIMER_PWMBRKCTL_BRKAODD_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Fault Brake Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32IntSource Interrupt source, could be one of following source
|
||||||
|
* - \ref TPWM_BRAKE_EDGE
|
||||||
|
* - \ref TPWM_BRAKE_LEVEL
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable fault brake interrupt.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
|
||||||
|
{
|
||||||
|
timer->PWMINTEN1 |= u32IntSource;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Fault Brake Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32IntSource Interrupt source, could be one of following source
|
||||||
|
* - \ref TPWM_BRAKE_EDGE
|
||||||
|
* - \ref TPWM_BRAKE_LEVEL
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable fault brake interrupt.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource)
|
||||||
|
{
|
||||||
|
timer->PWMINTEN1 &= ~u32IntSource;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Indicate Fault Brake Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32IntSource Interrupt source, could be one of following source
|
||||||
|
* - \ref TPWM_BRAKE_EDGE
|
||||||
|
* - \ref TPWM_BRAKE_LEVEL
|
||||||
|
*
|
||||||
|
* @return Fault brake interrupt flag of specified source
|
||||||
|
* @retval 0 Fault brake interrupt did not occurred
|
||||||
|
* @retval 1 Fault brake interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This function is used to indicate fault brake interrupt flag occurred or not of selected source.
|
||||||
|
*/
|
||||||
|
uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
|
||||||
|
{
|
||||||
|
return ((timer->PWMINTSTS1 & (0x3UL << u32IntSource)) ? 1UL : 0UL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Fault Brake Interrupt Flags
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32IntSource Interrupt source, could be one of following source
|
||||||
|
* - \ref TPWM_BRAKE_EDGE
|
||||||
|
* - \ref TPWM_BRAKE_LEVEL
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to clear fault brake interrupt flags of selected source.
|
||||||
|
* @note The register write-protection function should be disabled before using this function.
|
||||||
|
*/
|
||||||
|
void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource)
|
||||||
|
{
|
||||||
|
timer->PWMINTSTS1 = (0x3UL << u32IntSource);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable load mode of selected channel
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32LoadMode Timer PWM counter loading mode, could be one of following mode
|
||||||
|
* - \ref TPWM_LOAD_MODE_PERIOD
|
||||||
|
* - \ref TPWM_LOAD_MODE_IMMEDIATE
|
||||||
|
* - \ref TPWM_LOAD_MODE_CENTER
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable load mode of selected channel.
|
||||||
|
* @note The default loading mode is period loading mode.
|
||||||
|
*/
|
||||||
|
void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode)
|
||||||
|
{
|
||||||
|
timer->PWMCTL = (timer->PWMCTL & ~(TIMER_PWMCTL_IMMLDEN_Msk | TIMER_PWMCTL_CTRLD_Msk)) | u32LoadMode;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Brake Pin Noise Filter Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32BrakePinSrc The external brake pin source, could be one of following source
|
||||||
|
* - \ref TPWM_TM_BRAKE0
|
||||||
|
* - \ref TPWM_TM_BRAKE1
|
||||||
|
* - \ref TPWM_TM_BRAKE2
|
||||||
|
* - \ref TPWM_TM_BRAKE3
|
||||||
|
* @param[in] u32DebounceCnt This value controls the real debounce sample time.
|
||||||
|
* The target debounce sample time is (debounce sample clock period) * (u32DebounceCnt).
|
||||||
|
* @param[in] u32ClkSrcSel Brake pin detector debounce clock source, could be one of following source
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_1
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_2
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_4
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_8
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_16
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_32
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_64
|
||||||
|
* - \ref TPWM_BKP_DBCLK_PCLK_DIV_128
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable external brake pin detector noise filter function.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel)
|
||||||
|
{
|
||||||
|
timer->PWMBNF = (timer->PWMBNF & ~(TIMER_PWMBNF_BKPINSRC_Msk | TIMER_PWMBNF_BRKFCNT_Msk | TIMER_PWMBNF_BRKNFSEL_Msk)) |
|
||||||
|
(u32BrakePinSrc << TIMER_PWMBNF_BKPINSRC_Pos) |
|
||||||
|
(u32DebounceCnt << TIMER_PWMBNF_BRKFCNT_Pos) |
|
||||||
|
(u32ClkSrcSel << TIMER_PWMBNF_BRKNFSEL_Pos) | TIMER_PWMBNF_BRKNFEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Brake Pin Noise Filter Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable external brake pin detector noise filter function.
|
||||||
|
*/
|
||||||
|
void TPWM_DisableBrakePinDebounce(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMBNF &= ~TIMER_PWMBNF_BRKNFEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Brake Pin Inverse
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to enable PWM brake pin inverse function.
|
||||||
|
*/
|
||||||
|
void TPWM_EnableBrakePinInverse(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Brake Pin Inverse
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to disable PWM brake pin inverse function.
|
||||||
|
*/
|
||||||
|
void TPWM_DisableBrakePinInverse(TIMER_T *timer)
|
||||||
|
{
|
||||||
|
timer->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Brake Pin Source
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] u32BrakePinNum Brake pin selection. One of the following:
|
||||||
|
* - \ref TPWM_TM_BRAKE0
|
||||||
|
* - \ref TPWM_TM_BRAKE1
|
||||||
|
* - \ref TPWM_TM_BRAKE2
|
||||||
|
* - \ref TPWM_TM_BRAKE3
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to set PWM brake pin source.
|
||||||
|
*/
|
||||||
|
void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum)
|
||||||
|
{
|
||||||
|
timer->PWMBNF = (((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | (u32BrakePinNum << TIMER_PWMBNF_BKPINSRC_Pos));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_PWM_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,709 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file timer.h
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 2 $
|
||||||
|
* $Date: 16/07/29 3:12p $
|
||||||
|
* @brief Timer PWM Controller(Timer PWM) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __TIMER_PWM_H__
|
||||||
|
#define __TIMER_PWM_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_PWM_Driver TIMER PWM Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_PWM_EXPORTED_CONSTANTS TIMER PWM Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Output Channel Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_CH0 (BIT0) /*!< Indicate PWMx_CH0 */
|
||||||
|
#define TPWM_CH1 (BIT1) /*!< Indicate PWMx_CH1 */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Counter Type Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_UP_COUNT (0UL) /*!< Up count type */
|
||||||
|
#define TPWM_DOWN_COUNT (1UL) /*!< Down count type */
|
||||||
|
#define TPWM_UP_DOWN_COUNT (2UL) /*!< Up-Down count type */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Counter Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_AUTO_RELOAD_MODE (0UL) /*!< Auto-reload mode */
|
||||||
|
#define TPWM_ONE_SHOT_MODE (1UL) /*!< One-shot mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Output Level Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_OUTPUT_TOGGLE (0UL) /*!< Timer PWM output toggle */
|
||||||
|
#define TPWM_OUTPUT_NOTHING (1UL) /*!< Timer PWM output nothing */
|
||||||
|
#define TPWM_OUTPUT_LOW (2UL) /*!< Timer PWM output low */
|
||||||
|
#define TPWM_OUTPUT_HIGH (3UL) /*!< Timer PWM output high */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Trigger EADC Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_TRIGGER_EADC_AT_ZERO_POINT (0UL) /*!< Timer PWM trigger EADC while counter zero point event occurred */
|
||||||
|
#define TPWM_TRIGGER_EADC_AT_PERIOD_POINT (1UL) /*!< Timer PWM trigger EADC while counter period point event occurred */
|
||||||
|
#define TPWM_TRIGGER_EADC_AT_ZERO_OR_PERIOD_POINT (2UL) /*!< Timer PWM trigger EADC while counter zero or period point event occurred */
|
||||||
|
#define TPWM_TRIGGER_EADC_AT_COMPARE_UP_COUNT_POINT (3UL) /*!< Timer PWM trigger EADC while counter up count compare point event occurred */
|
||||||
|
#define TPWM_TRIGGER_EADC_AT_COMPARE_DOWN_COUNT_POINT (4UL) /*!< Timer PWM trigger EADC while counter down count compare point event occurred */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Brake Control Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_ACMP0 (TIMER_PWMBRKCTL_CPO0EBEN_Msk) /*!< Comparator 0 as edge-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_ACMP1 (TIMER_PWMBRKCTL_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_BKPIN (TIMER_PWMBRKCTL_BRKPEEN_Msk) /*!< Brake pin as edge-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_SYS_CSS (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_SYS_BOD (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_SYS_COR (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as edge-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_EDGE_SYS_RAM (TIMER_PWMBRKCTL_SYSEBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
|
||||||
|
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_ACMP0 (TIMER_PWMBRKCTL_CPO0LBEN_Msk) /*!< Comparator 0 as level-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_ACMP1 (TIMER_PWMBRKCTL_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_BKPIN (TIMER_PWMBRKCTL_BRKPLEN_Msk) /*!< Brake pin as level-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_SYS_CSS (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CSSBRKEN_Msk << 16)) /*!< System fail condition: clock security system detection as level-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_SYS_BOD (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_BODBRKEN_Msk << 16)) /*!< System fail condition: brown-out detection as level-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_SYS_COR (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_CORBRKEN_Msk << 16)) /*!< System fail condition: core lockup detection as level-detect fault brake source */
|
||||||
|
#define TPWM_BRAKE_SOURCE_LEVEL_SYS_RAM (TIMER_PWMBRKCTL_SYSLBEN_Msk | (TIMER_PWMFAILBRK_RAMBRKEN_Msk << 16)) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
|
||||||
|
|
||||||
|
#define TPWM_BRAKE_EDGE (TIMER_PWMSWBRK_BRKETRG_Msk) /*!< Edge-detect fault brake */
|
||||||
|
#define TPWM_BRAKE_LEVEL (TIMER_PWMSWBRK_BRKLTRG_Msk) /*!< Level-detect fault brake */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Load Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_LOAD_MODE_PERIOD (0UL) /*!< Timer PWM period load mode \hideinitializer */
|
||||||
|
#define TPWM_LOAD_MODE_IMMEDIATE (TIMER_PWMCTL_IMMLDEN_Msk) /*!< Timer PWM immediately load mode \hideinitializer */
|
||||||
|
#define TPWM_LOAD_MODE_CENTER (TIMER_PWMCTL_CTRLD_Msk) /*!< Timer PWM center load mode \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Brake Pin De-bounce Clock Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_1 (0UL) /*!< De-bounce clock is PCLK divide by 1 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_2 (1UL) /*!< De-bounce clock is PCLK divide by 2 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_4 (2UL) /*!< De-bounce clock is PCLK divide by 4 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_8 (3UL) /*!< De-bounce clock is PCLK divide by 8 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_16 (4UL) /*!< De-bounce clock is PCLK divide by 16 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_32 (5UL) /*!< De-bounce clock is PCLK divide by 32 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_64 (6UL) /*!< De-bounce clock is PCLK divide by 64 \hideinitializer */
|
||||||
|
#define TPWM_BKP_DBCLK_PCLK_DIV_128 (7UL) /*!< De-bounce clock is PCLK divide by 128 \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Brake Pin Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_TM_BRAKE0 (0UL) /*!< Brake pin source comes from TM_BRAKE0 \hideinitializer */
|
||||||
|
#define TPWM_TM_BRAKE1 (1UL) /*!< Brake pin source comes from TM_BRAKE1 \hideinitializer */
|
||||||
|
#define TPWM_TM_BRAKE2 (2UL) /*!< Brake pin source comes from TM_BRAKE2 \hideinitializer */
|
||||||
|
#define TPWM_TM_BRAKE3 (3UL) /*!< Brake pin source comes from TM_BRAKE3 \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Counter Clock Source Select Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_CNTR_CLKSRC_TMR_CLK (0UL) /*!< Timer PWM Clock source selects to TMR_CLK \hideinitializer */
|
||||||
|
#define TPWM_CNTR_CLKSRC_TIMER0_INT (1UL) /*!< Timer PWM Clock source selects to TIMER0 interrupt event \hideinitializer */
|
||||||
|
#define TPWM_CNTR_CLKSRC_TIMER1_INT (2UL) /*!< Timer PWM Clock source selects to TIMER1 interrupt event \hideinitializer */
|
||||||
|
#define TPWM_CNTR_CLKSRC_TIMER2_INT (3UL) /*!< Timer PWM Clock source selects to TIMER2 interrupt event \hideinitializer */
|
||||||
|
#define TPWM_CNTR_CLKSRC_TIMER3_INT (4UL) /*!< Timer PWM Clock source selects to TIMER3 interrupt event \hideinitializer */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Counter Synchronous Mode Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define TPWM_CNTR_SYNC_DISABLE (0UL) /*!< Disable TIMER PWM synchronous function \hideinitializer */
|
||||||
|
#define TPWM_CNTR_SYNC_START_BY_TIMER0 ((0<<TIMER_PWMSCTL_SYNCSRC_Pos) | (1<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous start by TIMER0 PWM \hideinitializer */
|
||||||
|
#define TPWM_CNTR_SYNC_CLEAR_BY_TIMER0 ((0<<TIMER_PWMSCTL_SYNCSRC_Pos) | (3<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous clear by TIMER0 PWM \hideinitializer */
|
||||||
|
#define TPWM_CNTR_SYNC_START_BY_TIMER2 ((1<<TIMER_PWMSCTL_SYNCSRC_Pos) | (1<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous start by TIMER2 PWM \hideinitializer */
|
||||||
|
#define TPWM_CNTR_SYNC_CLEAR_BY_TIMER2 ((1<<TIMER_PWMSCTL_SYNCSRC_Pos) | (3<<TIMER_PWMSCTL_SYNCMODE_Pos)) /*!< PWM counter synchronous clear by TIMER2 PWM \hideinitializer */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_PWM_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup TIMER_PWM_EXPORTED_FUNCTIONS TIMER PWM Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable PWM Counter Mode
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable specified Timer channel as PWM counter mode, then timer counter mode is invalid.
|
||||||
|
* @note All registers about time counter function will be cleared to 0 and timer clock source will be changed to PCLKx automatically after executing this macro.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_PWM_MODE(timer) ((timer)->ALTCTL = (1 << TIMER_ALTCTL_FUNCSEL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable PWM Counter Mode
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable specified Timer channel as PWM counter mode, then timer counter mode is available.
|
||||||
|
* @note All registers about PWM counter function will be cleared to 0 after executing this macro.
|
||||||
|
*/
|
||||||
|
#define TPWM_DISABLE_PWM_MODE(timer) ((timer)->ALTCTL = (0 << TIMER_ALTCTL_FUNCSEL_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Independent Mode
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable independent mode of TIMER PWM module and complementary mode will be disabled.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_INDEPENDENT_MODE(timer) ((timer)->PWMCTL &= ~(1 << TIMER_PWMCTL_OUTMODE_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Complementary Mode
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable complementary mode of Timer PWM module and independent mode will be disabled.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_COMPLEMENTARY_MODE(timer) ((timer)->PWMCTL |= (1 << TIMER_PWMCTL_OUTMODE_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Counter Type
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] type Timer PWM count type, could be one of the following type
|
||||||
|
* - \ref TPWM_UP_COUNT
|
||||||
|
* - \ref TPWM_DOWN_COUNT
|
||||||
|
* - \ref TPWM_UP_DOWN_COUNT
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set Timer PWM counter type.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_COUNTER_TYPE(timer, type) ((timer)->PWMCTL = ((timer)->PWMCTL & ~TIMER_PWMCTL_CNTTYPE_Msk) | ((type) << TIMER_PWMCTL_CNTTYPE_Pos))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Start PWM Counter
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable PWM generator and start counter counting.
|
||||||
|
*/
|
||||||
|
#define TPWM_START_COUNTER(timer) ((timer)->PWMCTL |= TIMER_PWMCTL_CNTEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop PWM Counter
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to stop PWM counter after current period is completed.
|
||||||
|
*/
|
||||||
|
#define TPWM_STOP_COUNTER(timer) ((timer)->PWMPERIOD = 0x0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Counter Clock Prescaler
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] prescaler Clock prescaler of specified channel. Valid values are between 0x0~0xFFF.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set the prescaler of specified TIMER PWM.
|
||||||
|
* @note If prescaler is 0, then there is no scaling in counter clock source.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_PRESCALER(timer, prescaler) ((timer)->PWMCLKPSC = (prescaler))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Counter Clock Prescaler
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return Target prescaler setting, CLKPSC (TIMERx_PWMCLKPSC[11:0])
|
||||||
|
*
|
||||||
|
* @details Get the prescaler setting, the target counter clock divider is (CLKPSC + 1).
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_PRESCALER(timer) ((timer)->PWMCLKPSC)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Couner Period
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] period Period of specified channel. Valid values are between 0x0~0xFFFF.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set the period of specified TIMER PWM.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_PERIOD(timer, period) ((timer)->PWMPERIOD = (period))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Couner Period
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return Target period setting, PERIOD (TIMERx_PWMPERIOD[15:0])
|
||||||
|
*
|
||||||
|
* @details This macro is used to get the period of specified TIMER PWM.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_PERIOD(timer) ((timer)->PWMPERIOD)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Comparator Value
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] cmp Comparator of specified channel. Valid values are between 0x0~0xFFFF.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set the comparator value of specified TIMER PWM.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_CMPDAT(timer, cmp) ((timer)->PWMCMPDAT = (cmp))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Comparator Value
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return Target comparator setting, CMPDAT (TIMERx_PWMCMPDAT[15:0])
|
||||||
|
*
|
||||||
|
* @details This macro is used to get the comparator value of specified TIMER PWM.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_CMPDAT(timer) ((timer)->PWMCMPDAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Counter
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear counter of specified TIMER PWM.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_COUNTER(timer) ((timer)->PWMCNTCLR = TIMER_PWMCNTCLR_CNTCLR_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Software Trigger Brake Event
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] type Type of brake trigger. Valid values are:
|
||||||
|
* - \ref TPWM_BRAKE_EDGE
|
||||||
|
* - \ref TPWM_BRAKE_LEVEL
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to trigger brake event by writing PWMSWBRK register.
|
||||||
|
*/
|
||||||
|
#define TPWM_SW_TRIGGER_BRAKE(timer, type) ((timer)->PWMSWBRK = (type))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Output Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] ch Enable specified channel output function. Valid values are:
|
||||||
|
* - \ref TPWM_CH0
|
||||||
|
* - \ref TPWM_CH1
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable output function of specified output pins.
|
||||||
|
* @note If the corresponding bit in u32ChMask parameter is 0, then output function will be disabled in this channel.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_OUTPUT(timer, ch) ((timer)->PWMPOEN = (ch))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Output Inverse
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] ch Set specified channel output is inversed or not. Valid values are:
|
||||||
|
* - \ref TPWM_CH0
|
||||||
|
* - \ref TPWM_CH1
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable output inverse of specified output pins.
|
||||||
|
* @note If u32ChMask parameter is 0, then output inverse function will be disabled.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_OUTPUT_INVERSE(timer, ch) ((timer)->PWMPOLCTL = (ch))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Output Function
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] ch Enable specified channel output mask function. Valid values are:
|
||||||
|
* - \ref TPWM_CH0
|
||||||
|
* - \ref TPWM_CH1
|
||||||
|
*
|
||||||
|
* @param[in] level Output to high or low on specified mask channel.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable output function of specified output pins.
|
||||||
|
* @note If u32ChMask parameter is 0, then output mask function will be disabled.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_MASK_OUTPUT(timer, ch, level) \
|
||||||
|
{ \
|
||||||
|
(timer)->PWMMSKEN = (ch); \
|
||||||
|
(timer)->PWMMSK = (level); \
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Counter Synchronous Mode
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @param[in] mode Synchronous mode. Possible options are:
|
||||||
|
* - \ref TPWM_CNTR_SYNC_DISABLE
|
||||||
|
* - \ref TPWM_CNTR_SYNC_START_BY_TIMER0
|
||||||
|
* - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER0
|
||||||
|
* - \ref TPWM_CNTR_SYNC_START_BY_TIMER2
|
||||||
|
* - \ref TPWM_CNTR_SYNC_CLEAR_BY_TIMER2
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set counter synchronous mode of specified Timer PWM module.
|
||||||
|
* @note Only support all PWM counters are synchronous by TIMER0 PWM or TIMER0~1 PWM counter synchronous by TIMER0 PWM and
|
||||||
|
* TIMER2~3 PWM counter synchronous by TIMER2 PWM.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_COUNTER_SYNC_MODE(timer, mode) ((timer)->PWMSCTL = (mode))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger Counter Synchronous
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to trigger synchronous event by specified TIMER PWM.
|
||||||
|
* @note 1. This macro is only available for TIMER0 PWM and TIMER2 PWM. \n
|
||||||
|
* 2. STRGEN (PWMSTRG[0]) is write only and always read as 0.
|
||||||
|
*/
|
||||||
|
#define TPWM_TRIGGER_COUNTER_SYNC(timer) ((timer)->PWMSTRG = TIMER_PWMSTRG_STRGEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Zero Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable the zero event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_ZIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Zero Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable the zero event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_DISABLE_ZERO_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_ZIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Zero Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Zero event interrupt did not occur
|
||||||
|
* @retval 1 Zero event interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates zero event occurred or not.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_ZERO_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_ZIF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Zero Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears zero event interrupt flag.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_ZERO_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_ZIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Period Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable the period event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_PIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Period Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable the period event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_DISABLE_PERIOD_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_PIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Period Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Period event interrupt did not occur
|
||||||
|
* @retval 1 Period event interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates period event occurred or not.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_PERIOD_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_PIF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Period Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears period event interrupt flag.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_PERIOD_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_PIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Compare Up Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable the compare up event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPUIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Compare Up Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable the compare up event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_DISABLE_CMP_UP_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPUIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Compare Up Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Compare up event interrupt did not occur
|
||||||
|
* @retval 1 Compare up event interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates compare up event occurred or not.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_CMP_UP_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPUIF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Compare Up Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears compare up event interrupt flag.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_CMP_UP_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPUIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable Compare Down Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to enable the compare down event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_ENABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 |= TIMER_PWMINTEN0_CMPDIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable Compare Down Event Interrupt
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to disable the compare down event interrupt function.
|
||||||
|
*/
|
||||||
|
#define TPWM_DISABLE_CMP_DOWN_INT(timer) ((timer)->PWMINTEN0 &= ~TIMER_PWMINTEN0_CMPDIEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Compare Down Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Compare down event interrupt did not occur
|
||||||
|
* @retval 1 Compare down event interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates compare down event occurred or not.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_CMP_DOWN_INT_FLAG(timer) (((timer)->PWMINTSTS0 & TIMER_PWMINTSTS0_CMPDIF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Compare Down Event Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears compare down event interrupt flag.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_CMP_DOWN_INT_FLAG(timer) ((timer)->PWMINTSTS0 = TIMER_PWMINTSTS0_CMPDIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Counter Reach Maximum Count Status
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Timer PWM counter never counts to maximum value
|
||||||
|
* @retval 1 Timer PWM counter counts to maximum value, 0xFFFF
|
||||||
|
*
|
||||||
|
* @details This macro indicates Timer PWM counter has count to 0xFFFF or not.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_REACH_MAX_CNT_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_CNTMAXF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Counter Reach Maximum Count Status
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears reach maximum count status.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_REACH_MAX_CNT_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_CNTMAXF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Trigger EADC Status
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @retval 0 Trigger EADC start conversion is not occur
|
||||||
|
* @retval 1 Specified counter compare event has trigger ADC start conversion
|
||||||
|
*
|
||||||
|
* @details This macro is used to indicate PWM counter compare event has triggered EADC start conversion.
|
||||||
|
*/
|
||||||
|
#define TPWM_GET_TRG_EADC_STATUS(timer) (((timer)->PWMSTATUS & TIMER_PWMSTATUS_EADCTRGF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Trigger EADC Status
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear PWM counter compare event trigger EADC status.
|
||||||
|
*/
|
||||||
|
#define TPWM_CLEAR_TRG_EADC_STATUS(timer) ((timer)->PWMSTATUS = TIMER_PWMSTATUS_EADCTRGF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Brake Event at Brake Pin High or Low-to-High
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
|
||||||
|
* @note The default brake pin detection is high level or from low to high.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_BRAKE_PIN_HIGH_DETECT(timer) ((timer)->PWMBNF &= ~TIMER_PWMBNF_BRKPINV_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Brake Event at Brake Pin Low or High-to-Low
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set detect brake event when external brake pin at low level or transfer from high to low.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_BRAKE_PIN_LOW_DETECT(timer) ((timer)->PWMBNF |= TIMER_PWMBNF_BRKPINV_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set External Brake Pin Source
|
||||||
|
*
|
||||||
|
* @param[in] timer The pointer of the specified Timer module. It could be TIMER0, TIMER1, TIMER2, TIMER3.
|
||||||
|
* @param[in] pin The external brake pin source, could be one of following source
|
||||||
|
* - \ref TPWM_TM_BRAKE0
|
||||||
|
* - \ref TPWM_TM_BRAKE1
|
||||||
|
* - \ref TPWM_TM_BRAKE2
|
||||||
|
* - \ref TPWM_TM_BRAKE3
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to set detect brake event when external brake pin at high level or transfer from low to high.
|
||||||
|
*/
|
||||||
|
#define TPWM_SET_BRAKE_PIN_SOURCE(timer, pin) ((timer)->PWMBNF = ((timer)->PWMBNF & ~TIMER_PWMBNF_BKPINSRC_Msk) | ((pin)<<TIMER_PWMBNF_BKPINSRC_Pos))
|
||||||
|
|
||||||
|
|
||||||
|
void TPWM_SetCounterClockSource(TIMER_T *timer, uint32_t u32CntClkSrc);
|
||||||
|
uint32_t TPWM_ConfigOutputFreqAndDuty(TIMER_T *timer, uint32_t u32Frequency, uint32_t u32DutyCycle);
|
||||||
|
void TPWM_EnableDeadTime(TIMER_T *timer, uint32_t u32DTCount);
|
||||||
|
void TPWM_EnableDeadTimeWithPrescale(TIMER_T *timer, uint32_t u32DTCount);
|
||||||
|
void TPWM_DisableDeadTime(TIMER_T *timer);
|
||||||
|
void TPWM_EnableCounter(TIMER_T *timer);
|
||||||
|
void TPWM_DisableCounter(TIMER_T *timer);
|
||||||
|
void TPWM_EnableTriggerEADC(TIMER_T *timer, uint32_t u32Condition);
|
||||||
|
void TPWM_DisableTriggerEADC(TIMER_T *timer);
|
||||||
|
void TPWM_EnableFaultBrake(TIMER_T *timer, uint32_t u32CH0Level, uint32_t u32CH1Level, uint32_t u32BrakeSource);
|
||||||
|
void TPWM_EnableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource);
|
||||||
|
void TPWM_DisableFaultBrakeInt(TIMER_T *timer, uint32_t u32IntSource);
|
||||||
|
uint32_t TPWM_GetFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource);
|
||||||
|
void TPWM_ClearFaultBrakeIntFlag(TIMER_T *timer, uint32_t u32IntSource);
|
||||||
|
void TPWM_SetLoadMode(TIMER_T *timer, uint32_t u32LoadMode);
|
||||||
|
void TPWM_EnableBrakePinDebounce(TIMER_T *timer, uint32_t u32BrakePinSrc, uint32_t u32DebounceCnt, uint32_t u32ClkSrcSel);
|
||||||
|
void TPWM_DisableBrakePinDebounce(TIMER_T *timer);
|
||||||
|
void TPWM_EnableBrakePinInverse(TIMER_T *timer);
|
||||||
|
void TPWM_DisableBrakePinInverse(TIMER_T *timer);
|
||||||
|
void TPWM_SetBrakePinSource(TIMER_T *timer, uint32_t u32BrakePinNum);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_PWM_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group TIMER_PWM_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __TIMER_PWM_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,600 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file uart.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series UART Interface Controller (UART) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup UART_Driver UART Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear UART specified interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32InterruptFlag The specified interrupt of UART module.
|
||||||
|
* - \ref UART_INTSTS_LININT_Msk : LIN Bus interrupt
|
||||||
|
* - \ref UART_INTSTS_WKINT_Msk : Wake-up interrupt
|
||||||
|
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error interrupt
|
||||||
|
* - \ref UART_INTSTS_MODEMINT_Msk : MODEM Status Interrupt
|
||||||
|
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to clear UART specified interrupt flag.
|
||||||
|
*/
|
||||||
|
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(u32InterruptFlag & UART_INTSTS_RLSINT_Msk) /* Clear Receive Line Status Interrupt */
|
||||||
|
uart->FIFOSTS = UART_FIFOSTS_BIF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_FEF_Msk | UART_FIFOSTS_ADDRDETF_Msk;
|
||||||
|
|
||||||
|
if(u32InterruptFlag & UART_INTSTS_MODEMINT_Msk) /* Clear MODEM Status Interrupt */
|
||||||
|
uart->MODEMSTS |= UART_MODEMSTS_CTSDETF_Msk;
|
||||||
|
|
||||||
|
if(u32InterruptFlag & UART_INTSTS_BUFERRINT_Msk) /* Clear Buffer Error Interrupt */
|
||||||
|
uart->FIFOSTS = UART_FIFOSTS_RXOVIF_Msk | UART_FIFOSTS_TXOVIF_Msk;
|
||||||
|
|
||||||
|
if(u32InterruptFlag & UART_INTSTS_WKINT_Msk) /* Clear Wake-up Interrupt */
|
||||||
|
uart->WKSTS = uart->WKSTS;
|
||||||
|
|
||||||
|
if(u32InterruptFlag & UART_INTSTS_LININT_Msk) /* Clear LIN Bus Interrupt */
|
||||||
|
{
|
||||||
|
uart->INTSTS = UART_INTSTS_LINIF_Msk;
|
||||||
|
uart->LINSTS = uart->LINSTS;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable UART interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable UART interrupt.
|
||||||
|
*/
|
||||||
|
void UART_Close(UART_T* uart)
|
||||||
|
{
|
||||||
|
uart->INTEN = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable UART auto flow control function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable UART auto flow control.
|
||||||
|
*/
|
||||||
|
void UART_DisableFlowCtrl(UART_T* uart)
|
||||||
|
{
|
||||||
|
uart->INTEN &= ~(UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable UART specified interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32InterruptFlag The specified interrupt of UART module.
|
||||||
|
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt
|
||||||
|
* - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt
|
||||||
|
* - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt
|
||||||
|
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||||
|
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||||
|
* - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt
|
||||||
|
* - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt
|
||||||
|
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt
|
||||||
|
* - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt
|
||||||
|
* - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable UART specified interrupt and disable NVIC UART IRQ.
|
||||||
|
*/
|
||||||
|
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag)
|
||||||
|
{
|
||||||
|
/* Disable UART specified interrupt */
|
||||||
|
UART_DISABLE_INT(uart, u32InterruptFlag);
|
||||||
|
|
||||||
|
/* Disable NVIC UART IRQ */
|
||||||
|
if(uart == UART0)
|
||||||
|
NVIC_DisableIRQ(UART0_IRQn);
|
||||||
|
else if(uart == UART1)
|
||||||
|
NVIC_DisableIRQ(UART1_IRQn);
|
||||||
|
else if(uart == UART2)
|
||||||
|
NVIC_DisableIRQ(UART2_IRQn);
|
||||||
|
else if(uart == UART3)
|
||||||
|
NVIC_DisableIRQ(UART3_IRQn);
|
||||||
|
else if(uart == UART2)
|
||||||
|
NVIC_DisableIRQ(UART4_IRQn);
|
||||||
|
else
|
||||||
|
NVIC_DisableIRQ(UART5_IRQn);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable UART auto flow control function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to Enable UART auto flow control.
|
||||||
|
*/
|
||||||
|
/**
|
||||||
|
* @brief Enable UART auto flow control function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to Enable UART auto flow control.
|
||||||
|
*/
|
||||||
|
void UART_EnableFlowCtrl(UART_T* uart)
|
||||||
|
{
|
||||||
|
/* Set RTS pin output is low level active */
|
||||||
|
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
|
||||||
|
|
||||||
|
/* Set CTS pin input is low level active */
|
||||||
|
uart->MODEMSTS |= UART_MODEMSTS_CTSACTLV_Msk;
|
||||||
|
|
||||||
|
/* Set RTS and CTS auto flow control enable */
|
||||||
|
uart->INTEN |= UART_INTEN_ATORTSEN_Msk | UART_INTEN_ATOCTSEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable UART specified interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32InterruptFlag The specified interrupt of UART module:
|
||||||
|
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt
|
||||||
|
* - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt
|
||||||
|
* - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt
|
||||||
|
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||||
|
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||||
|
* - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt
|
||||||
|
* - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt
|
||||||
|
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt
|
||||||
|
* - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt
|
||||||
|
* - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to enable UART specified interrupt and enable NVIC UART IRQ.
|
||||||
|
*/
|
||||||
|
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Enable UART specified interrupt */
|
||||||
|
UART_ENABLE_INT(uart, u32InterruptFlag);
|
||||||
|
|
||||||
|
/* Enable NVIC UART IRQ */
|
||||||
|
if(uart == UART0)
|
||||||
|
NVIC_EnableIRQ(UART0_IRQn);
|
||||||
|
else if(uart == UART1)
|
||||||
|
NVIC_EnableIRQ(UART1_IRQn);
|
||||||
|
else if(uart == UART2)
|
||||||
|
NVIC_EnableIRQ(UART2_IRQn);
|
||||||
|
else if(uart == UART3)
|
||||||
|
NVIC_EnableIRQ(UART3_IRQn);
|
||||||
|
else if(uart == UART4)
|
||||||
|
NVIC_EnableIRQ(UART4_IRQn);
|
||||||
|
else
|
||||||
|
NVIC_EnableIRQ(UART5_IRQn);
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Open and set UART function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32baudrate The baudrate of UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function use to enable UART function and set baud-rate.
|
||||||
|
*/
|
||||||
|
void UART_Open(UART_T* uart, uint32_t u32baudrate)
|
||||||
|
{
|
||||||
|
uint8_t u8UartClkSrcSel, u8UartClkDivNum;
|
||||||
|
uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
|
||||||
|
uint32_t u32Baud_Div = 0;
|
||||||
|
|
||||||
|
/* Get UART clock source selection and UART clock divider number */
|
||||||
|
switch((uint32_t)uart)
|
||||||
|
{
|
||||||
|
case UART0_BASE:
|
||||||
|
case UART0_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
|
||||||
|
break;
|
||||||
|
case UART1_BASE:
|
||||||
|
case UART1_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
|
||||||
|
break;
|
||||||
|
case UART2_BASE:
|
||||||
|
case UART2_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
|
||||||
|
break;
|
||||||
|
case UART3_BASE:
|
||||||
|
case UART3_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
|
||||||
|
break;
|
||||||
|
case UART4_BASE:
|
||||||
|
case UART4_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
|
||||||
|
break;
|
||||||
|
case UART5_BASE:
|
||||||
|
case UART5_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Select UART function */
|
||||||
|
uart->FUNCSEL = UART_FUNCSEL_UART;
|
||||||
|
|
||||||
|
/* Set UART line configuration */
|
||||||
|
uart->LINE = UART_WORD_LEN_8 | UART_PARITY_NONE | UART_STOP_BIT_1;
|
||||||
|
|
||||||
|
/* Set UART Rx and RTS trigger level */
|
||||||
|
uart->FIFO &= ~(UART_FIFO_RFITL_Msk | UART_FIFO_RTSTRGLV_Msk);
|
||||||
|
|
||||||
|
/* Get PLL clock frequency if UART clock source selection is PLL */
|
||||||
|
if(u8UartClkSrcSel == 1)
|
||||||
|
u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
|
||||||
|
|
||||||
|
/* Set UART baud rate */
|
||||||
|
if(u32baudrate != 0)
|
||||||
|
{
|
||||||
|
u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
|
||||||
|
|
||||||
|
if(u32Baud_Div > 0xFFFF)
|
||||||
|
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
|
||||||
|
else
|
||||||
|
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read UART data
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] pu8RxBuf The buffer to receive the data of receive FIFO.
|
||||||
|
* @param[in] u32ReadBytes The the read bytes number of data.
|
||||||
|
*
|
||||||
|
* @return u32Count Receive byte count
|
||||||
|
*
|
||||||
|
* @details The function is used to read Rx data from RX FIFO and the data will be stored in pu8RxBuf.
|
||||||
|
*/
|
||||||
|
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
|
||||||
|
{
|
||||||
|
uint32_t u32Count, u32delayno;
|
||||||
|
|
||||||
|
for(u32Count = 0; u32Count < u32ReadBytes; u32Count++)
|
||||||
|
{
|
||||||
|
u32delayno = 0;
|
||||||
|
|
||||||
|
while(uart->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk) /* Check RX empty => failed */
|
||||||
|
{
|
||||||
|
u32delayno++;
|
||||||
|
if(u32delayno >= 0x40000000)
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
pu8RxBuf[u32Count] = uart->DAT; /* Get Data from UART RX */
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Count;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set UART line configuration
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32baudrate The register value of baudrate of UART module.
|
||||||
|
* If u32baudrate = 0, UART baudrate will not change.
|
||||||
|
* @param[in] u32data_width The data length of UART module.
|
||||||
|
* - \ref UART_WORD_LEN_5
|
||||||
|
* - \ref UART_WORD_LEN_6
|
||||||
|
* - \ref UART_WORD_LEN_7
|
||||||
|
* - \ref UART_WORD_LEN_8
|
||||||
|
* @param[in] u32parity The parity setting (none/odd/even/mark/space) of UART module.
|
||||||
|
* - \ref UART_PARITY_NONE
|
||||||
|
* - \ref UART_PARITY_ODD
|
||||||
|
* - \ref UART_PARITY_EVEN
|
||||||
|
* - \ref UART_PARITY_MARK
|
||||||
|
* - \ref UART_PARITY_SPACE
|
||||||
|
* @param[in] u32stop_bits The stop bit length (1/1.5/2 bit) of UART module.
|
||||||
|
* - \ref UART_STOP_BIT_1
|
||||||
|
* - \ref UART_STOP_BIT_1_5
|
||||||
|
* - \ref UART_STOP_BIT_2
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function use to config UART line setting.
|
||||||
|
*/
|
||||||
|
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
|
||||||
|
{
|
||||||
|
uint8_t u8UartClkSrcSel, u8UartClkDivNum;
|
||||||
|
uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
|
||||||
|
uint32_t u32Baud_Div = 0;
|
||||||
|
|
||||||
|
/* Get UART clock source selection and UART clock divider number */
|
||||||
|
switch((uint32_t)uart)
|
||||||
|
{
|
||||||
|
case UART0_BASE:
|
||||||
|
case UART0_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
|
||||||
|
break;
|
||||||
|
case UART1_BASE:
|
||||||
|
case UART1_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
|
||||||
|
break;
|
||||||
|
case UART2_BASE:
|
||||||
|
case UART2_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
|
||||||
|
break;
|
||||||
|
case UART3_BASE:
|
||||||
|
case UART3_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
|
||||||
|
break;
|
||||||
|
case UART4_BASE:
|
||||||
|
case UART4_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
|
||||||
|
break;
|
||||||
|
case UART5_BASE:
|
||||||
|
case UART5_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get PLL clock frequency if UART clock source selection is PLL */
|
||||||
|
if(u8UartClkSrcSel == 1)
|
||||||
|
u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
|
||||||
|
|
||||||
|
/* Set UART baud rate */
|
||||||
|
if(u32baudrate != 0)
|
||||||
|
{
|
||||||
|
u32Baud_Div = UART_BAUD_MODE2_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate);
|
||||||
|
|
||||||
|
if(u32Baud_Div > 0xFFFF)
|
||||||
|
uart->BAUD = (UART_BAUD_MODE0 | UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32baudrate));
|
||||||
|
else
|
||||||
|
uart->BAUD = (UART_BAUD_MODE2 | u32Baud_Div);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set UART line configuration */
|
||||||
|
uart->LINE = u32data_width | u32parity | u32stop_bits;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set Rx timeout count
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32TOC Rx timeout counter.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function use to set Rx timeout count.
|
||||||
|
*/
|
||||||
|
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC)
|
||||||
|
{
|
||||||
|
/* Set time-out interrupt comparator */
|
||||||
|
uart->TOUT = (uart->TOUT & ~UART_TOUT_TOIC_Msk) | (u32TOC);
|
||||||
|
|
||||||
|
/* Set time-out counter enable */
|
||||||
|
uart->INTEN |= UART_INTEN_TOCNTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select and configure IrDA function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32Buadrate The baudrate of UART module.
|
||||||
|
* @param[in] u32Direction The direction of UART module in IrDA mode:
|
||||||
|
* - \ref UART_IRDA_TXEN
|
||||||
|
* - \ref UART_IRDA_RXEN
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to configure IrDA relative settings. It consists of TX or RX mode and baudrate.
|
||||||
|
*/
|
||||||
|
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction)
|
||||||
|
{
|
||||||
|
uint8_t u8UartClkSrcSel, u8UartClkDivNum;
|
||||||
|
uint32_t u32ClkTbl[4] = {__HXT, 0, __LXT, __HIRC};
|
||||||
|
uint32_t u32Baud_Div;
|
||||||
|
|
||||||
|
/* Select IrDA function mode */
|
||||||
|
uart->FUNCSEL = UART_FUNCSEL_IrDA;
|
||||||
|
|
||||||
|
/* Get UART clock source selection and UART clock divider number */
|
||||||
|
switch((uint32_t)uart)
|
||||||
|
{
|
||||||
|
case UART0_BASE:
|
||||||
|
case UART0_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART0_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART0_MODULE);
|
||||||
|
break;
|
||||||
|
case UART1_BASE:
|
||||||
|
case UART1_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART1_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART1_MODULE);
|
||||||
|
break;
|
||||||
|
case UART2_BASE:
|
||||||
|
case UART2_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART2_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART2_MODULE);
|
||||||
|
break;
|
||||||
|
case UART3_BASE:
|
||||||
|
case UART3_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART3_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART3_MODULE);
|
||||||
|
break;
|
||||||
|
case UART4_BASE:
|
||||||
|
case UART4_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART4_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART4_MODULE);
|
||||||
|
break;
|
||||||
|
case UART5_BASE:
|
||||||
|
case UART5_BASE+NS_OFFSET:
|
||||||
|
u8UartClkSrcSel = CLK_GetModuleClockSource(UART5_MODULE);
|
||||||
|
u8UartClkDivNum = CLK_GetModuleClockDivider(UART5_MODULE);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Get PLL clock frequency if UART clock source selection is PLL */
|
||||||
|
if(u8UartClkSrcSel == 1)
|
||||||
|
u32ClkTbl[u8UartClkSrcSel] = CLK_GetPLLClockFreq();
|
||||||
|
|
||||||
|
/* Set UART IrDA baud rate in mode 0 */
|
||||||
|
if(u32Buadrate != 0)
|
||||||
|
{
|
||||||
|
u32Baud_Div = UART_BAUD_MODE0_DIVIDER((u32ClkTbl[u8UartClkSrcSel]) / (u8UartClkDivNum + 1), u32Buadrate);
|
||||||
|
|
||||||
|
if(u32Baud_Div < 0xFFFF)
|
||||||
|
uart->BAUD = (UART_BAUD_MODE0 | u32Baud_Div);
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Configure IrDA relative settings */
|
||||||
|
if(u32Direction == UART_IRDA_RXEN)
|
||||||
|
{
|
||||||
|
uart->IRDA |= UART_IRDA_RXINV_Msk; //Rx signal is inverse
|
||||||
|
uart->IRDA &= ~UART_IRDA_TXEN_Msk;
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
uart->IRDA &= ~UART_IRDA_TXINV_Msk; //Tx signal is not inverse
|
||||||
|
uart->IRDA |= UART_IRDA_TXEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select and configure RS485 function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32Mode The operation mode(NMM/AUD/AAD).
|
||||||
|
* - \ref UART_ALTCTL_RS485NMM_Msk
|
||||||
|
* - \ref UART_ALTCTL_RS485AUD_Msk
|
||||||
|
* - \ref UART_ALTCTL_RS485AAD_Msk
|
||||||
|
* @param[in] u32Addr The RS485 address.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to set RS485 relative setting.
|
||||||
|
*/
|
||||||
|
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr)
|
||||||
|
{
|
||||||
|
/* Select UART RS485 function mode */
|
||||||
|
uart->FUNCSEL = UART_FUNCSEL_RS485;
|
||||||
|
|
||||||
|
/* Set RS585 configuration */
|
||||||
|
uart->ALTCTL &= ~(UART_ALTCTL_RS485NMM_Msk | UART_ALTCTL_RS485AUD_Msk | UART_ALTCTL_RS485AAD_Msk | UART_ALTCTL_ADDRMV_Msk);
|
||||||
|
uart->ALTCTL |= (u32Mode | (u32Addr << UART_ALTCTL_ADDRMV_Pos));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Select and configure LIN function
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] u32Mode The LIN direction :
|
||||||
|
* - \ref UART_ALTCTL_LINTXEN_Msk
|
||||||
|
* - \ref UART_ALTCTL_LINRXEN_Msk
|
||||||
|
* @param[in] u32BreakLength The breakfield length.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to set LIN relative setting.
|
||||||
|
*/
|
||||||
|
void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength)
|
||||||
|
{
|
||||||
|
/* Select LIN function mode */
|
||||||
|
uart->FUNCSEL = UART_FUNCSEL_LIN;
|
||||||
|
|
||||||
|
/* Select LIN function setting : Tx enable, Rx enable and break field length */
|
||||||
|
uart->ALTCTL &= ~(UART_ALTCTL_LINTXEN_Msk | UART_ALTCTL_LINRXEN_Msk | UART_ALTCTL_BRKFL_Msk);
|
||||||
|
uart->ALTCTL |= (u32Mode | (u32BreakLength << UART_ALTCTL_BRKFL_Pos));
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write UART data
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module.
|
||||||
|
* @param[in] pu8TxBuf The buffer to send the data to UART transmission FIFO.
|
||||||
|
* @param[out] u32WriteBytes The byte number of data.
|
||||||
|
*
|
||||||
|
* @return u32Count transfer byte count
|
||||||
|
*
|
||||||
|
* @details The function is to write data into TX buffer to transmit data by UART.
|
||||||
|
*/
|
||||||
|
uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
|
||||||
|
{
|
||||||
|
uint32_t u32Count, u32delayno;
|
||||||
|
|
||||||
|
for(u32Count = 0; u32Count != u32WriteBytes; u32Count++)
|
||||||
|
{
|
||||||
|
u32delayno = 0;
|
||||||
|
while((uart->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) == 0) /* Wait Tx empty and Time-out manner */
|
||||||
|
{
|
||||||
|
u32delayno++;
|
||||||
|
if(u32delayno >= 0x40000000)
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
uart->DAT = pu8TxBuf[u32Count]; /* Send UART Data from buffer */
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Count;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group UART_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,465 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file UART.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series UART Interface Controller (UART) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __UART_H__
|
||||||
|
#define __UART_H__
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup UART_Driver UART Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup UART_EXPORTED_CONSTANTS UART Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART FIFO size constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART0_FIFO_SIZE 16 /*!< UART0 supports separated receive/transmit 16/16 bytes entry FIFO */
|
||||||
|
#define UART1_FIFO_SIZE 16 /*!< UART1 supports separated receive/transmit 16/16 bytes entry FIFO */
|
||||||
|
#define UART2_FIFO_SIZE 16 /*!< UART2 supports separated receive/transmit 16/16 bytes entry FIFO */
|
||||||
|
#define UART3_FIFO_SIZE 16 /*!< UART3 supports separated receive/transmit 16/16 bytes entry FIFO */
|
||||||
|
#define UART4_FIFO_SIZE 16 /*!< UART4 supports separated receive/transmit 16/16 bytes entry FIFO */
|
||||||
|
#define UART5_FIFO_SIZE 16 /*!< UART5 supports separated receive/transmit 16/16 bytes entry FIFO */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART_FIFO constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_FIFO_RFITL_1BYTE (0x0 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 1 byte */
|
||||||
|
#define UART_FIFO_RFITL_4BYTES (0x1 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 4 bytes */
|
||||||
|
#define UART_FIFO_RFITL_8BYTES (0x2 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 8 bytes */
|
||||||
|
#define UART_FIFO_RFITL_14BYTES (0x3 << UART_FIFO_RFITL_Pos) /*!< UART_FIFO setting to set RX FIFO Trigger Level to 14 bytes */
|
||||||
|
|
||||||
|
#define UART_FIFO_RTSTRGLV_1BYTE (0x0 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 1 byte */
|
||||||
|
#define UART_FIFO_RTSTRGLV_4BYTES (0x1 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 4 bytes */
|
||||||
|
#define UART_FIFO_RTSTRGLV_8BYTES (0x2 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 8 bytes */
|
||||||
|
#define UART_FIFO_RTSTRGLV_14BYTES (0x3 << UART_FIFO_RTSTRGLV_Pos) /*!< UART_FIFO setting to set RTS Trigger Level to 14 bytes */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART_LINE constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_WORD_LEN_5 (0) /*!< UART_LINE setting to set UART word length to 5 bits */
|
||||||
|
#define UART_WORD_LEN_6 (1) /*!< UART_LINE setting to set UART word length to 6 bits */
|
||||||
|
#define UART_WORD_LEN_7 (2) /*!< UART_LINE setting to set UART word length to 7 bits */
|
||||||
|
#define UART_WORD_LEN_8 (3) /*!< UART_LINE setting to set UART word length to 8 bits */
|
||||||
|
|
||||||
|
#define UART_PARITY_NONE (0x0 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as no parity */
|
||||||
|
#define UART_PARITY_ODD (0x1 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as odd parity */
|
||||||
|
#define UART_PARITY_EVEN (0x3 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to set UART as even parity */
|
||||||
|
#define UART_PARITY_MARK (0x5 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
|
||||||
|
#define UART_PARITY_SPACE (0x7 << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
|
||||||
|
|
||||||
|
#define UART_STOP_BIT_1 (0x0 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
|
||||||
|
#define UART_STOP_BIT_1_5 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
|
||||||
|
#define UART_STOP_BIT_2 (0x1 << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART RTS ACTIVE LEVEL constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_RTS_IS_LOW_LEV_ACTIVE (0x1 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is Low Level Active */
|
||||||
|
#define UART_RTS_IS_HIGH_LEV_ACTIVE (0x0 << UART_MODEM_RTSACTLV_Pos) /*!< Set RTS is High Level Active */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART_IRDA constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_IRDA_TXEN (0x1 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Tx mode */
|
||||||
|
#define UART_IRDA_RXEN (0x0 << UART_IRDA_TXEN_Pos) /*!< Set IrDA function Rx mode */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART_FUNCSEL constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_FUNCSEL_UART (0x0 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
|
||||||
|
#define UART_FUNCSEL_LIN (0x1 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */
|
||||||
|
#define UART_FUNCSEL_IrDA (0x2 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
|
||||||
|
#define UART_FUNCSEL_RS485 (0x3 << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART_LINCTL constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_LINCTL_BRKFL(x) (((x)-1) << UART_LINCTL_BRKFL_Pos) /*!< UART_LINCTL setting to set LIN Break Field Length, x = 10 ~ 15, default value is 12 */
|
||||||
|
#define UART_LINCTL_BSL(x) (((x)-1) << UART_LINCTL_BSL_Pos) /*!< UART_LINCTL setting to set LIN Break/Sync Delimiter Length, x = 1 ~ 4 */
|
||||||
|
#define UART_LINCTL_HSEL_BREAK (0x0UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field */
|
||||||
|
#define UART_LINCTL_HSEL_BREAK_SYNC (0x1UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field and sync field */
|
||||||
|
#define UART_LINCTL_HSEL_BREAK_SYNC_ID (0x2UL << UART_LINCTL_HSEL_Pos) /*!< UART_LINCTL setting to set LIN Header Select to break field, sync field and ID field*/
|
||||||
|
#define UART_LINCTL_PID(x) ((x) << UART_LINCTL_PID_Pos) /*!< UART_LINCTL setting to set LIN PID value */
|
||||||
|
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UART BAUDRATE MODE constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UART_BAUD_MODE0 (0) /*!< Set UART Baudrate Mode is Mode0 */
|
||||||
|
#define UART_BAUD_MODE2 (UART_BAUD_BAUDM1_Msk | UART_BAUD_BAUDM0_Msk) /*!< Set UART Baudrate Mode is Mode2 */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group UART_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup UART_EXPORTED_FUNCTIONS UART Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Calculate UART baudrate mode0 divider
|
||||||
|
*
|
||||||
|
* @param[in] u32SrcFreq UART clock frequency
|
||||||
|
* @param[in] u32BaudRate Baudrate of UART module
|
||||||
|
*
|
||||||
|
* @return UART baudrate mode0 divider
|
||||||
|
*
|
||||||
|
* @details This macro calculate UART baudrate mode0 divider.
|
||||||
|
*/
|
||||||
|
#define UART_BAUD_MODE0_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)*8)) / (u32BaudRate) >> 4)-2)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Calculate UART baudrate mode2 divider
|
||||||
|
*
|
||||||
|
* @param[in] u32SrcFreq UART clock frequency
|
||||||
|
* @param[in] u32BaudRate Baudrate of UART module
|
||||||
|
*
|
||||||
|
* @return UART baudrate mode2 divider
|
||||||
|
*
|
||||||
|
* @details This macro calculate UART baudrate mode2 divider.
|
||||||
|
*/
|
||||||
|
#define UART_BAUD_MODE2_DIVIDER(u32SrcFreq, u32BaudRate) ((((u32SrcFreq) + ((u32BaudRate)/2)) / (u32BaudRate))-2)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write UART data
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
* @param[in] u8Data Data byte to transmit.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro write Data to Tx data register.
|
||||||
|
*/
|
||||||
|
#define UART_WRITE(uart, u8Data) ((uart)->DAT = (u8Data))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read UART data
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @return The oldest data byte in RX FIFO.
|
||||||
|
*
|
||||||
|
* @details This macro read Rx data register.
|
||||||
|
*/
|
||||||
|
#define UART_READ(uart) ((uart)->DAT)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Tx empty
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Tx FIFO is not empty
|
||||||
|
* @retval >=1 Tx FIFO is empty
|
||||||
|
*
|
||||||
|
* @details This macro get Transmitter FIFO empty register value.
|
||||||
|
*/
|
||||||
|
#define UART_GET_TX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTY_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Rx empty
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Rx FIFO is not empty
|
||||||
|
* @retval >=1 Rx FIFO is empty
|
||||||
|
*
|
||||||
|
* @details This macro get Receiver FIFO empty register value.
|
||||||
|
*/
|
||||||
|
#define UART_GET_RX_EMPTY(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXEMPTY_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check specified uart port transmission is over.
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Tx transmission is not over
|
||||||
|
* @retval 1 Tx transmission is over
|
||||||
|
*
|
||||||
|
* @details This macro return Transmitter Empty Flag register bit value.
|
||||||
|
* It indicates if specified uart port transmission is over nor not.
|
||||||
|
*/
|
||||||
|
#define UART_IS_TX_EMPTY(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait specified uart port transmission is over
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro wait specified uart port transmission is over.
|
||||||
|
*/
|
||||||
|
#define UART_WAIT_TX_EMPTY(uart) while(!((((uart)->FIFOSTS) & UART_FIFOSTS_TXEMPTYF_Msk) >> UART_FIFOSTS_TXEMPTYF_Pos))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check RX is ready or not
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 The number of bytes in the RX FIFO is less than the RFITL
|
||||||
|
* @retval 1 The number of bytes in the RX FIFO equals or larger than RFITL
|
||||||
|
*
|
||||||
|
* @details This macro check receive data available interrupt flag is set or not.
|
||||||
|
*/
|
||||||
|
#define UART_IS_RX_READY(uart) (((uart)->INTSTS & UART_INTSTS_RDAIF_Msk)>>UART_INTSTS_RDAIF_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check TX FIFO is full or not
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 1 TX FIFO is full
|
||||||
|
* @retval 0 TX FIFO is not full
|
||||||
|
*
|
||||||
|
* @details This macro check TX FIFO is full or not.
|
||||||
|
*/
|
||||||
|
#define UART_IS_TX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)>>UART_FIFOSTS_TXFULL_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check RX FIFO is full or not
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 1 RX FIFO is full
|
||||||
|
* @retval 0 RX FIFO is not full
|
||||||
|
*
|
||||||
|
* @details This macro check RX FIFO is full or not.
|
||||||
|
*/
|
||||||
|
#define UART_IS_RX_FULL(uart) (((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)>>UART_FIFOSTS_RXFULL_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Tx full register value
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Tx FIFO is not full.
|
||||||
|
* @retval >=1 Tx FIFO is full.
|
||||||
|
*
|
||||||
|
* @details This macro get Tx full register value.
|
||||||
|
*/
|
||||||
|
#define UART_GET_TX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_TXFULL_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Rx full register value
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Rx FIFO is not full.
|
||||||
|
* @retval >=1 Rx FIFO is full.
|
||||||
|
*
|
||||||
|
* @details This macro get Rx full register value.
|
||||||
|
*/
|
||||||
|
#define UART_GET_RX_FULL(uart) ((uart)->FIFOSTS & UART_FIFOSTS_RXFULL_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified UART interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
* @param[in] u32eIntSel Interrupt type select
|
||||||
|
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter empty interrupt
|
||||||
|
* - \ref UART_INTEN_ABRIEN_Msk : Auto baud rate interrupt
|
||||||
|
* - \ref UART_INTEN_LINIEN_Msk : Lin bus interrupt
|
||||||
|
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||||
|
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||||
|
* - \ref UART_INTEN_RXTOIEN_Msk : Rx time-out interrupt
|
||||||
|
* - \ref UART_INTEN_MODEMIEN_Msk : Modem interrupt
|
||||||
|
* - \ref UART_INTEN_RLSIEN_Msk : Rx Line status interrupt
|
||||||
|
* - \ref UART_INTEN_THREIEN_Msk : Tx empty interrupt
|
||||||
|
* - \ref UART_INTEN_RDAIEN_Msk : Rx ready interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro enable specified UART interrupt.
|
||||||
|
*/
|
||||||
|
#define UART_ENABLE_INT(uart, u32eIntSel) ((uart)->INTEN |= (u32eIntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified UART interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
* @param[in] u32eIntSel Interrupt type select
|
||||||
|
* - \ref UART_INTEN_TXENDIEN_Msk : Transmitter Empty Interrupt
|
||||||
|
* - \ref UART_INTEN_ABRIEN_Msk : Auto-baud Rate Interrupt
|
||||||
|
* - \ref UART_INTEN_LINIEN_Msk : Lin Bus interrupt
|
||||||
|
* - \ref UART_INTEN_WKIEN_Msk : Wake-up interrupt
|
||||||
|
* - \ref UART_INTEN_BUFERRIEN_Msk : Buffer Error interrupt
|
||||||
|
* - \ref UART_INTEN_RXTOIEN_Msk : Rx Time-out Interrupt
|
||||||
|
* - \ref UART_INTEN_MODEMIEN_Msk : MODEM Status Interrupt
|
||||||
|
* - \ref UART_INTEN_RLSIEN_Msk : Receive Line Status Interrupt
|
||||||
|
* - \ref UART_INTEN_THREIEN_Msk : Transmit Holding Register Empty Interrupt
|
||||||
|
* - \ref UART_INTEN_RDAIEN_Msk : Receive Data Available Interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro enable specified UART interrupt.
|
||||||
|
*/
|
||||||
|
#define UART_DISABLE_INT(uart, u32eIntSel) ((uart)->INTEN &= ~ (u32eIntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get specified interrupt flag/status
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
* @param[in] u32eIntTypeFlag Interrupt Type Flag, should be
|
||||||
|
* - \ref UART_INTSTS_HWBUFEINT_Msk : PDMA Mode Buffer Error Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_HWTOINT_Msk : PDMA Mode Rx Time-out Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_HWMODINT_Msk : PDMA Mode MODEM Status Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_HWRLSINT_Msk : PDMA Mode Receive Line Status Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_HWBUFEIF_Msk : PDMA Mode Buffer Error Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_HWTOIF_Msk : PDMA Mode Time-out Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_HWMODIF_Msk : PDMA Mode MODEM Status Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_HWRLSIF_Msk : PDMA Mode Receive Line Status Flag
|
||||||
|
* - \ref UART_INTSTS_ABRINT_Msk : Auto-baud Rate Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_TXENDINT_Msk : Transmitter Empty Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_LININT_Msk : LIN Bus Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_WKINT_Msk : Wake-up Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_BUFERRINT_Msk : Buffer Error Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_RXTOINT_Msk : Rx Time-out Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_MODEMINT_Msk : Modem Status Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_RLSINT_Msk : Receive Line Status Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_THREINT_Msk : Transmit Holding Register Empty Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_RDAINT_Msk : Receive Data Available Interrupt Indicator
|
||||||
|
* - \ref UART_INTSTS_TXENDIF_Msk : Transmitter Empty Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_LINIF_Msk : LIN Bus Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_WKIF_Msk : Wake-up Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_BUFERRIF_Msk : Buffer Error Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_RXTOIF_Msk : Rx Time-out Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_MODEMIF_Msk : MODEM Status Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_RLSIF_Msk : Receive Line Status Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_THREIF_Msk : Transmit Holding Register Empty Interrupt Flag
|
||||||
|
* - \ref UART_INTSTS_RDAIF_Msk : Receive Data Available Interrupt Flag
|
||||||
|
*
|
||||||
|
* @retval 0 The specified interrupt is not happened.
|
||||||
|
* 1 The specified interrupt is happened.
|
||||||
|
*
|
||||||
|
* @details This macro get specified interrupt flag or interrupt indicator status.
|
||||||
|
*/
|
||||||
|
#define UART_GET_INT_FLAG(uart,u32eIntTypeFlag) (((uart)->INTSTS & (u32eIntTypeFlag))?1:0)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set RTS pin to low
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro set RTS pin to low.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void UART_CLEAR_RTS(UART_T* uart)
|
||||||
|
{
|
||||||
|
uart->MODEM |= UART_MODEM_RTSACTLV_Msk;
|
||||||
|
uart->MODEM &= ~UART_MODEM_RTS_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set RTS pin to high
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro set RTS pin to high.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void UART_SET_RTS(UART_T* uart)
|
||||||
|
{
|
||||||
|
uart->MODEM |= UART_MODEM_RTSACTLV_Msk | UART_MODEM_RTS_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear RS-485 Address Byte Detection Flag
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clear RS-485 address byte detection flag.
|
||||||
|
*/
|
||||||
|
#define UART_RS485_CLEAR_ADDR_FLAG(uart) ((uart)->FIFOSTS = UART_FIFOSTS_ADDRDETF_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get RS-485 Address Byte Detection Flag
|
||||||
|
*
|
||||||
|
* @param[in] uart The pointer of the specified UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Receiver detects a data that is not an address bit.
|
||||||
|
* @retval 1 Receiver detects a data that is an address bit.
|
||||||
|
*
|
||||||
|
* @details This macro get RS-485 address byte detection flag.
|
||||||
|
*/
|
||||||
|
#define UART_RS485_GET_ADDR_FLAG(uart) (((uart)->FIFOSTS & UART_FIFOSTS_ADDRDETF_Msk) >> UART_FIFOSTS_ADDRDETF_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
void UART_ClearIntFlag(UART_T* uart , uint32_t u32InterruptFlag);
|
||||||
|
void UART_Close(UART_T* uart);
|
||||||
|
void UART_DisableFlowCtrl(UART_T* uart);
|
||||||
|
void UART_DisableInt(UART_T* uart, uint32_t u32InterruptFlag);
|
||||||
|
void UART_EnableFlowCtrl(UART_T* uart);
|
||||||
|
void UART_EnableInt(UART_T* uart, uint32_t u32InterruptFlag);
|
||||||
|
void UART_Open(UART_T* uart, uint32_t u32baudrate);
|
||||||
|
uint32_t UART_Read(UART_T* uart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
|
||||||
|
void UART_SetLine_Config(UART_T* uart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
||||||
|
void UART_SetTimeoutCnt(UART_T* uart, uint32_t u32TOC);
|
||||||
|
void UART_SelectIrDAMode(UART_T* uart, uint32_t u32Buadrate, uint32_t u32Direction);
|
||||||
|
void UART_SelectRS485Mode(UART_T* uart, uint32_t u32Mode, uint32_t u32Addr);
|
||||||
|
void UART_SelectLINMode(UART_T* uart, uint32_t u32Mode, uint32_t u32BreakLength);
|
||||||
|
uint32_t UART_Write(UART_T* uart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group UART_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group UART_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__UART_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,893 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file usbd.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series USB driver header file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __USBD_H__
|
||||||
|
#define __USBD_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USBD_Driver USBD Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USBD_EXPORTED_STRUCTS USBD Exported Structs
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
typedef struct s_usbd_info
|
||||||
|
{
|
||||||
|
const uint8_t *gu8DevDesc; /*!< Pointer for USB Device Descriptor */
|
||||||
|
const uint8_t *gu8ConfigDesc; /*!< Pointer for USB Configuration Descriptor */
|
||||||
|
const uint8_t **gu8StringDesc; /*!< Pointer for USB String Descriptor pointers */
|
||||||
|
const uint8_t **gu8HidReportDesc; /*!< Pointer for USB HID Report Descriptor */
|
||||||
|
const uint8_t *gu8BosDesc;
|
||||||
|
const uint32_t *gu32HidReportSize; /*!< Pointer for HID Report descriptor Size */
|
||||||
|
const uint32_t *gu32ConfigHidDescIdx; /*!< Pointer for HID Descriptor start index */
|
||||||
|
|
||||||
|
} S_USBD_INFO_T;
|
||||||
|
|
||||||
|
extern const S_USBD_INFO_T gsInfo;
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USBD_EXPORTED_STRUCTS */
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup USBD_EXPORTED_CONSTANTS USBD Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
#define USBD_BUF_BASE (USBD_BASE+0x100)
|
||||||
|
#define USBD_BUF_BASE_NS (USBD_BASE+NS_OFFSET+0x100)
|
||||||
|
#define USBD_MAX_EP 12
|
||||||
|
|
||||||
|
#define EP0 0 /*!< Endpoint 0 */
|
||||||
|
#define EP1 1 /*!< Endpoint 1 */
|
||||||
|
#define EP2 2 /*!< Endpoint 2 */
|
||||||
|
#define EP3 3 /*!< Endpoint 3 */
|
||||||
|
#define EP4 4 /*!< Endpoint 4 */
|
||||||
|
#define EP5 5 /*!< Endpoint 5 */
|
||||||
|
#define EP6 6 /*!< Endpoint 6 */
|
||||||
|
#define EP7 7 /*!< Endpoint 7 */
|
||||||
|
#define EP8 8 /*!< Endpoint 8 */
|
||||||
|
#define EP9 9 /*!< Endpoint 9 */
|
||||||
|
#define EP10 10 /*!< Endpoint 10 */
|
||||||
|
#define EP11 11 /*!< Endpoint 11 */
|
||||||
|
|
||||||
|
|
||||||
|
/*!<USB Request Type */
|
||||||
|
#define REQ_STANDARD 0x00
|
||||||
|
#define REQ_CLASS 0x20
|
||||||
|
#define REQ_VENDOR 0x40
|
||||||
|
|
||||||
|
/*!<USB Standard Request */
|
||||||
|
#define GET_STATUS 0x00
|
||||||
|
#define CLEAR_FEATURE 0x01
|
||||||
|
#define SET_FEATURE 0x03
|
||||||
|
#define SET_ADDRESS 0x05
|
||||||
|
#define GET_DESCRIPTOR 0x06
|
||||||
|
#define SET_DESCRIPTOR 0x07
|
||||||
|
#define GET_CONFIGURATION 0x08
|
||||||
|
#define SET_CONFIGURATION 0x09
|
||||||
|
#define GET_INTERFACE 0x0A
|
||||||
|
#define SET_INTERFACE 0x0B
|
||||||
|
#define SYNC_FRAME 0x0C
|
||||||
|
|
||||||
|
/*!<USB Descriptor Type */
|
||||||
|
#define DESC_DEVICE 0x01
|
||||||
|
#define DESC_CONFIG 0x02
|
||||||
|
#define DESC_STRING 0x03
|
||||||
|
#define DESC_INTERFACE 0x04
|
||||||
|
#define DESC_ENDPOINT 0x05
|
||||||
|
#define DESC_QUALIFIER 0x06
|
||||||
|
#define DESC_OTHERSPEED 0x07
|
||||||
|
#define DESC_IFPOWER 0x08
|
||||||
|
#define DESC_OTG 0x09
|
||||||
|
#define DESC_BOS 0x0F
|
||||||
|
#define DESC_CAPABILITY 0x10
|
||||||
|
|
||||||
|
/*!<USB Device Capability Type */
|
||||||
|
#define CAP_WIRELESS 0x01
|
||||||
|
#define CAP_USB20_EXT 0x02
|
||||||
|
|
||||||
|
/*!<USB HID Descriptor Type */
|
||||||
|
#define DESC_HID 0x21
|
||||||
|
#define DESC_HID_RPT 0x22
|
||||||
|
|
||||||
|
/*!<USB Descriptor Length */
|
||||||
|
#define LEN_DEVICE 18
|
||||||
|
#define LEN_QUALIFIER 10
|
||||||
|
#define LEN_CONFIG 9
|
||||||
|
#define LEN_INTERFACE 9
|
||||||
|
#define LEN_ENDPOINT 7
|
||||||
|
#define LEN_OTG 5
|
||||||
|
#define LEN_BOS 5
|
||||||
|
#define LEN_HID 9
|
||||||
|
#define LEN_CCID 0x36
|
||||||
|
#define LEN_BOSCAP 7
|
||||||
|
|
||||||
|
/*!<USB Endpoint Type */
|
||||||
|
#define EP_ISO 0x01
|
||||||
|
#define EP_BULK 0x02
|
||||||
|
#define EP_INT 0x03
|
||||||
|
|
||||||
|
#define EP_INPUT 0x80
|
||||||
|
#define EP_OUTPUT 0x00
|
||||||
|
|
||||||
|
/*!<USB Feature Selector */
|
||||||
|
#define FEATURE_DEVICE_REMOTE_WAKEUP 0x01
|
||||||
|
#define FEATURE_ENDPOINT_HALT 0x00
|
||||||
|
|
||||||
|
/******************************************************************************/
|
||||||
|
/* USB Specific Macros */
|
||||||
|
/******************************************************************************/
|
||||||
|
|
||||||
|
#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable */
|
||||||
|
#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 */
|
||||||
|
|
||||||
|
#define USBD_BYTEM USBD_ATTR_BYTEM_Msk
|
||||||
|
#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable */
|
||||||
|
#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable */
|
||||||
|
#define USBD_RWAKEUP USBD_ATTR_RWAKEUP_Msk
|
||||||
|
#define USBD_PHY_EN USBD_ATTR_PHYEN_Msk /*!< PHY Enable */
|
||||||
|
|
||||||
|
#define USBD_INT_BUS USBD_INTEN_BUSIEN_Msk /*!< USB Bus Event Interrupt */
|
||||||
|
#define USBD_INT_USB USBD_INTEN_USBIEN_Msk /*!< USB Event Interrupt */
|
||||||
|
#define USBD_INT_FLDET USBD_INTEN_VBDETIEN_Msk /*!< USB VBUS Detection Interrupt */
|
||||||
|
#define USBD_INT_WAKEUP (USBD_INTEN_NEVWKIEN_Msk | USBD_INTEN_WKEN_Msk) /*!< USB No-Event-Wake-Up Interrupt */
|
||||||
|
|
||||||
|
#define USBD_INTSTS_WAKEUP USBD_INTSTS_NEVWKIF_Msk /*!< USB No-Event-Wake-Up Interrupt Status */
|
||||||
|
#define USBD_INTSTS_FLDET USBD_INTSTS_VBDETIF_Msk /*!< USB Float Detect Interrupt Status */
|
||||||
|
#define USBD_INTSTS_BUS USBD_INTSTS_BUSIF_Msk /*!< USB Bus Event Interrupt Status */
|
||||||
|
#define USBD_INTSTS_USB USBD_INTSTS_USBIF_Msk /*!< USB Event Interrupt Status */
|
||||||
|
#define USBD_INTSTS_SETUP USBD_INTSTS_SETUP_Msk /*!< USB Setup Event */
|
||||||
|
#define USBD_INTSTS_EP0 USBD_INTSTS_EPEVT0_Msk /*!< USB Endpoint 0 Event */
|
||||||
|
#define USBD_INTSTS_EP1 USBD_INTSTS_EPEVT1_Msk /*!< USB Endpoint 1 Event */
|
||||||
|
#define USBD_INTSTS_EP2 USBD_INTSTS_EPEVT2_Msk /*!< USB Endpoint 2 Event */
|
||||||
|
#define USBD_INTSTS_EP3 USBD_INTSTS_EPEVT3_Msk /*!< USB Endpoint 3 Event */
|
||||||
|
#define USBD_INTSTS_EP4 USBD_INTSTS_EPEVT4_Msk /*!< USB Endpoint 4 Event */
|
||||||
|
#define USBD_INTSTS_EP5 USBD_INTSTS_EPEVT5_Msk /*!< USB Endpoint 5 Event */
|
||||||
|
#define USBD_INTSTS_EP6 USBD_INTSTS_EPEVT6_Msk /*!< USB Endpoint 6 Event */
|
||||||
|
#define USBD_INTSTS_EP7 USBD_INTSTS_EPEVT7_Msk /*!< USB Endpoint 7 Event */
|
||||||
|
#define USBD_INTSTS_EP8 USBD_INTSTS_EPEVT8_Msk /*!< USB Endpoint 8 Event */
|
||||||
|
#define USBD_INTSTS_EP9 USBD_INTSTS_EPEVT9_Msk /*!< USB Endpoint 9 Event */
|
||||||
|
#define USBD_INTSTS_EP10 USBD_INTSTS_EPEVT10_Msk /*!< USB Endpoint 10 Event */
|
||||||
|
#define USBD_INTSTS_EP11 USBD_INTSTS_EPEVT11_Msk /*!< USB Endpoint 11 Event */
|
||||||
|
|
||||||
|
#define USBD_STATE_USBRST USBD_ATTR_USBRST_Msk /*!< USB Bus Reset */
|
||||||
|
#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend */
|
||||||
|
#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume */
|
||||||
|
#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout */
|
||||||
|
|
||||||
|
#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall */
|
||||||
|
#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */
|
||||||
|
|
||||||
|
#define USBD_CFG_EPMODE_DISABLE (0ul << USBD_CFG_STATE_Pos)/*!< Endpoint Disable */
|
||||||
|
#define USBD_CFG_EPMODE_OUT (1ul << USBD_CFG_STATE_Pos)/*!< Out Endpoint */
|
||||||
|
#define USBD_CFG_EPMODE_IN (2ul << USBD_CFG_STATE_Pos)/*!< In Endpoint */
|
||||||
|
#define USBD_CFG_TYPE_ISO (1ul << USBD_CFG_ISOCH_Pos)/*!< Isochronous */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USBD_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup USBD_EXPORTED_FUNCTIONS USBD Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Compare two input numbers and return maximum one.
|
||||||
|
*
|
||||||
|
* @param[in] a First number to be compared.
|
||||||
|
* @param[in] b Second number to be compared.
|
||||||
|
*
|
||||||
|
* @return Maximum value between a and b.
|
||||||
|
*
|
||||||
|
* @details If a > b, then return a. Otherwise, return b.
|
||||||
|
*/
|
||||||
|
#define USBD_Maximum(a,b) ((a)>(b) ? (a) : (b))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Compare two input numbers and return minimum one
|
||||||
|
*
|
||||||
|
* @param[in] a First number to be compared
|
||||||
|
* @param[in] b Second number to be compared
|
||||||
|
*
|
||||||
|
* @return Minimum value between a and b
|
||||||
|
*
|
||||||
|
* @details If a < b, then return a. Otherwise, return b.
|
||||||
|
*/
|
||||||
|
#define USBD_Minimum(a,b) ((a)<(b) ? (a) : (b))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USB
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To set USB ATTR control register to enable USB and PHY.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_ENABLE_USB() ((uint32_t)(USBD->ATTR |= 0x7D0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USB Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_ENABLE_USB_NS() ((uint32_t)(USBD_NS->ATTR |= 0x7D0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USB
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To set USB ATTR control register to disable USB.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_DISABLE_USB() ((uint32_t)(USBD->ATTR &= ~USBD_USB_EN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USB Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_DISABLE_USB_NS() ((uint32_t)(USBD_NS->ATTR &= ~USBD_USB_EN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USB PHY
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To set USB ATTR control register to enable USB PHY.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_ENABLE_PHY() ((uint32_t)(USBD->ATTR |= USBD_PHY_EN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USB PHY Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_ENABLE_PHY_NS() ((uint32_t)(USBD_NS->ATTR |= USBD_PHY_EN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USB PHY
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To set USB ATTR control register to disable USB PHY.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_DISABLE_PHY() ((uint32_t)(USBD->ATTR &= ~USBD_PHY_EN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USB PHY Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_DISABLE_PHY_NS() ((uint32_t)(USBD_NS->ATTR &= ~USBD_PHY_EN))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SE0. Force USB PHY transceiver to drive SE0.
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set DRVSE0 bit of USB_DRVSE0 register to enable software-disconnect function. Force USB PHY transceiver to drive SE0 to bus.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_SE0() ((uint32_t)(USBD->SE0 |= USBD_DRVSE0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable SE0 Macro for Non-Secure. Force USB PHY transceiver to drive SE0.
|
||||||
|
*/
|
||||||
|
#define USBD_SET_SE0_NS() ((uint32_t)(USBD_NS->SE0 |= USBD_DRVSE0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SE0
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear DRVSE0 bit of USB_DRVSE0 register to disable software-disconnect function.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_CLR_SE0() ((uint32_t)(USBD->SE0 &= ~USBD_DRVSE0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable SE0 Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_CLR_SE0_NS() ((uint32_t)(USBD_NS->SE0 &= ~USBD_DRVSE0))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB device address
|
||||||
|
*
|
||||||
|
* @param[in] addr The USB device address.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Write USB device address to USB_FADDR register.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_ADDR(addr) (USBD->FADDR = (addr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB device address Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_SET_ADDR_NS(addr) (USBD_NS->FADDR = (addr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB device address
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return USB device address
|
||||||
|
*
|
||||||
|
* @details Read USB_FADDR register to get USB device address.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_ADDR() ((uint32_t)(USBD->FADDR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB device address Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_ADDR_NS() ((uint32_t)(USBD_NS->FADDR))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USB interrupt function
|
||||||
|
*
|
||||||
|
* @param[in] intr The combination of the specified interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt enable bit.
|
||||||
|
* This parameter decides which interrupts will be enabled.
|
||||||
|
* (USBD_INT_WAKEUP, USBD_INT_FLDET, USBD_INT_USB, USBD_INT_BUS)
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Enable USB related interrupt functions specified by intr parameter.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_ENABLE_INT(intr) (USBD->INTEN |= (intr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USB interrupt function Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_ENABLE_INT_NS(intr) (USBD_NS->INTEN |= (intr))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get interrupt status
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return The value of USB_INTSTS register
|
||||||
|
*
|
||||||
|
* @details Return all interrupt flags of USB_INTSTS register.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_INT_FLAG() ((uint32_t)(USBD->INTSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get interrupt status Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_INT_FLAG_NS() ((uint32_t)(USBD_NS->INTSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USB interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] flag The combination of the specified interrupt flags.
|
||||||
|
* Each bit corresponds to a interrupt source.
|
||||||
|
* This parameter decides which interrupt flags will be cleared.
|
||||||
|
* (USBD_INTSTS_WAKEUP, USBD_INTSTS_FLDET, USBD_INTSTS_BUS, USBD_INTSTS_USB)
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear USB related interrupt flags specified by flag parameter.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_CLR_INT_FLAG(flag) (USBD->INTSTS = (flag))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USB interrupt flag Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_CLR_INT_FLAG_NS(flag) (USBD_NS->INTSTS = (flag))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get endpoint status
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return The value of USB_EPSTS register.
|
||||||
|
*
|
||||||
|
* @details Return all endpoint status.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_EP_FLAG() ((uint32_t)(USBD->EPSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get endpoint status Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_EP_FLAG_NS() ((uint32_t)(USBD_NS->EPSTS))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB bus state
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return The value of USB_ATTR[3:0].
|
||||||
|
* Bit 0 indicates USB bus reset status.
|
||||||
|
* Bit 1 indicates USB bus suspend status.
|
||||||
|
* Bit 2 indicates USB bus resume status.
|
||||||
|
* Bit 3 indicates USB bus time-out status.
|
||||||
|
*
|
||||||
|
* @details Return USB_ATTR[3:0] for USB bus events.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_BUS_STATE() ((uint32_t)(USBD->ATTR & 0xf))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB bus state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_BUS_STATE_NS() ((uint32_t)(USBD_NS->ATTR & 0xf))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check cable connection state
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 USB cable is not attached.
|
||||||
|
* @retval 1 USB cable is attached.
|
||||||
|
*
|
||||||
|
* @details Check the connection state by FLDET bit of USB_FLDET register.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_IS_ATTACHED() ((uint32_t)(USBD->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check cable connection state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_IS_ATTACHED_NS() ((uint32_t)(USBD_NS->VBUSDET & USBD_VBUSDET_VBUSDET_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop USB transaction of the specified endpoint ID
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Write 1 to CLRRDY bit of USB_CFGPx register to stop USB transaction of the specified endpoint ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_STOP_TRANSACTION(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop USB transaction of the specified endpoint ID Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_STOP_TRANSACTION_NS(ep) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_CLRRDY_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB DATA1 PID for the specified endpoint ID
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set DSQ_SYNC bit of USB_CFGx register to specify the DATA1 PID for the following IN token transaction.
|
||||||
|
* Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_DATA1(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB DATA1 PID for the specified endpoint ID Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_SET_DATA1_NS(ep) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) |= USBD_CFG_DSQSYNC_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB DATA0 PID for the specified endpoint ID
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear DSQ_SYNC bit of USB_CFGx register to specify the DATA0 PID for the following IN token transaction.
|
||||||
|
* Base on this setting, hardware will toggle PID between DATA0 and DATA1 automatically for IN token transactions.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_DATA0(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB DATA0 PID for the specified endpoint ID Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_SET_DATA0_NS(ep) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) &= (~USBD_CFG_DSQSYNC_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB payload size (IN data)
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @param[in] size The transfer length.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro will write the transfer length to USB_MXPLDx register for IN data transaction.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_PAYLOAD_LEN(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB payload size (IN data) Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_SET_PAYLOAD_LEN_NS(ep, size) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))) = (size))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB payload size (OUT data)
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return The value of USB_MXPLDx register.
|
||||||
|
*
|
||||||
|
* @details Get the data length of OUT data transaction by reading USB_MXPLDx register.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_PAYLOAD_LEN(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].MXPLD + (uint32_t)((ep) << 4))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB payload size (OUT data) Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_PAYLOAD_LEN_NS(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].MXPLD + (uint32_t)((ep) << 4))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure endpoint
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @param[in] config The USB configuration.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro will write config parameter to USB_CFGx register of specified endpoint ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_CONFIG_EP(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Configure endpoint Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_CONFIG_EP_NS(ep, config) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFG + (uint32_t)((ep) << 4))) = (config))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB endpoint buffer
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @param[in] offset The SRAM offset.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro will set the SRAM offset for the specified endpoint ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_EP_BUF_ADDR(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB endpoint buffer Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_SET_EP_BUF_ADDR_NS(ep, offset) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))) = (offset))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the offset of the specified USB endpoint buffer
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return The offset of the specified endpoint buffer.
|
||||||
|
*
|
||||||
|
* @details This macro will return the SRAM offset of the specified endpoint ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_EP_BUF_ADDR(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the offset of the specified USB endpoint buffer Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_EP_BUF_ADDR_NS(ep) ((uint32_t)*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].BUFSEG + (uint32_t)((ep) << 4))))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB endpoint stall state
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set USB endpoint stall state for the specified endpoint ID. Endpoint will respond STALL token automatically.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_SET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB endpoint stall state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_SET_EP_STALL_NS(ep) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) |= USBD_CFGP_SSTALL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USB endpoint stall state
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear USB endpoint stall state for the specified endpoint ID. Endpoint will respond ACK/NAK token.
|
||||||
|
*/
|
||||||
|
#define USBD_CLR_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USB endpoint stall state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_CLR_EP_STALL_NS(ep) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) &= ~USBD_CFGP_SSTALL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB endpoint stall state
|
||||||
|
*
|
||||||
|
* @param[in] ep The USB endpoint ID. M2351 Series supports 12 hardware endpoint ID. This parameter could be 0 ~ 11.
|
||||||
|
*
|
||||||
|
* @retval 0 USB endpoint is not stalled.
|
||||||
|
* @retval Others USB endpoint is stalled.
|
||||||
|
*
|
||||||
|
* @details Get USB endpoint stall state of the specified endpoint ID.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
#define USBD_GET_EP_STALL(ep) (*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB endpoint stall state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
#define USBD_GET_EP_STALL_NS(ep) (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief To support byte access between USB SRAM and system SRAM
|
||||||
|
*
|
||||||
|
* @param[in] dest Destination pointer.
|
||||||
|
*
|
||||||
|
* @param[in] src Source pointer.
|
||||||
|
*
|
||||||
|
* @param[in] size Byte count.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will copy the number of data specified by size and src parameters to the address specified by dest parameter.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE void USBD_MemCopy(uint8_t *dest, uint8_t *src, int32_t size)
|
||||||
|
{
|
||||||
|
while(size--) *dest++ = *src++;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB endpoint stall state
|
||||||
|
*
|
||||||
|
* @param[in] epnum USB endpoint number
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set USB endpoint stall state. Endpoint will respond STALL token automatically.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE void USBD_SetStall(uint8_t epnum)
|
||||||
|
{
|
||||||
|
uint32_t u32CfgAddr;
|
||||||
|
uint32_t u32Cfg;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i = 0; i < USBD_MAX_EP; i++)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
if((u32Cfg & 0xf) == epnum)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USB endpoint stall state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
static __INLINE void USBD_SetStall_NS(uint8_t epnum)
|
||||||
|
{
|
||||||
|
uint32_t u32CfgAddr;
|
||||||
|
uint32_t u32Cfg;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i = 0; i < USBD_MAX_EP; i++)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD_NS->EP[0].CFG; /* USBD_CFG0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
if((u32Cfg & 0xf) == epnum)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD_NS->EP[0].CFGP; /* USBD_CFGP0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg | USBD_CFGP_SSTALL);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USB endpoint stall state
|
||||||
|
*
|
||||||
|
* @param[in] epnum USB endpoint number
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear USB endpoint stall state. Endpoint will respond ACK/NAK token.
|
||||||
|
*/
|
||||||
|
static __INLINE void USBD_ClearStall(uint8_t epnum)
|
||||||
|
{
|
||||||
|
uint32_t u32CfgAddr;
|
||||||
|
uint32_t u32Cfg;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i = 0; i < USBD_MAX_EP; i++)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
if((u32Cfg & 0xf) == epnum)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USB endpoint stall state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
static __INLINE void USBD_ClearStall_NS(uint8_t epnum)
|
||||||
|
{
|
||||||
|
uint32_t u32CfgAddr;
|
||||||
|
uint32_t u32Cfg;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i = 0; i < USBD_MAX_EP; i++)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD_NS->EP[0].CFG; /* USBD_CFG0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
if((u32Cfg & 0xf) == epnum)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD_NS->EP[0].CFGP; /* USBD_CFGP0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
*((__IO uint32_t *)(u32CfgAddr)) = (u32Cfg & ~USBD_CFGP_SSTALL);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB endpoint stall state
|
||||||
|
*
|
||||||
|
* @param[in] epnum USB endpoint number
|
||||||
|
*
|
||||||
|
* @retval 0 USB endpoint is not stalled.
|
||||||
|
* @retval Others USB endpoint is stalled.
|
||||||
|
*
|
||||||
|
* @details Get USB endpoint stall state.
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t USBD_GetStall(uint8_t epnum)
|
||||||
|
{
|
||||||
|
uint32_t u32CfgAddr;
|
||||||
|
uint32_t u32Cfg;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i = 0; i < USBD_MAX_EP; i++)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFG; /* USBD_CFG0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
if((u32Cfg & 0xf) == epnum)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD->EP[0].CFGP; /* USBD_CFGP0 */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USB endpoint stall state Macro for Non-Secure
|
||||||
|
*/
|
||||||
|
static __INLINE uint32_t USBD_GetStall_NS(uint8_t epnum)
|
||||||
|
{
|
||||||
|
uint32_t u32CfgAddr;
|
||||||
|
uint32_t u32Cfg;
|
||||||
|
int i;
|
||||||
|
|
||||||
|
for(i = 0; i < USBD_MAX_EP; i++)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD_NS->EP[0].CFG; /* USBD_CFG0 */
|
||||||
|
u32Cfg = *((__IO uint32_t *)(u32CfgAddr));
|
||||||
|
|
||||||
|
if((u32Cfg & 0xf) == epnum)
|
||||||
|
{
|
||||||
|
u32CfgAddr = (uint32_t)(i << 4) + (uint32_t)&USBD_NS->EP[0].CFGP; /* USBD_CFGP0 */
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
|
||||||
|
}
|
||||||
|
|
||||||
|
extern volatile uint8_t g_usbd_RemoteWakeupEn;
|
||||||
|
|
||||||
|
|
||||||
|
typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
|
||||||
|
typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declaration for USB class request callback handler */
|
||||||
|
typedef void (*SET_INTERFACE_REQ)(void); /*!< Functional pointer type declaration for USB set interface request callback handler */
|
||||||
|
typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
|
||||||
|
|
||||||
|
|
||||||
|
/*--------------------------------------------------------------------*/
|
||||||
|
void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
|
||||||
|
void USBD_Start(void);
|
||||||
|
void USBD_GetSetupPacket(uint8_t *buf);
|
||||||
|
void USBD_ProcessSetupPacket(void);
|
||||||
|
void USBD_StandardRequest(void);
|
||||||
|
void USBD_PrepareCtrlIn(uint8_t *pu8Buf, uint32_t u32Size);
|
||||||
|
void USBD_CtrlIn(void);
|
||||||
|
void USBD_PrepareCtrlOut(uint8_t *pu8Buf, uint32_t u32Size);
|
||||||
|
void USBD_CtrlOut(void);
|
||||||
|
void USBD_SwReset(void);
|
||||||
|
void USBD_SetVendorRequest(VENDOR_REQ pfnVendorReq);
|
||||||
|
void USBD_SetConfigCallback(SET_CONFIG_CB pfnSetConfigCallback);
|
||||||
|
void USBD_LockEpStall(uint32_t u32EpBitmap);
|
||||||
|
|
||||||
|
void USBD_Open_NS(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
|
||||||
|
void USBD_Start_NS(void);
|
||||||
|
void USBD_ProcessSetupPacket_NS(void);
|
||||||
|
void USBD_StandardRequest_NS(void);
|
||||||
|
void USBD_PrepareCtrlIn_NS(uint8_t *pu8Buf, uint32_t u32Size);
|
||||||
|
void USBD_CtrlIn_NS(void);
|
||||||
|
void USBD_PrepareCtrlOut_NS(uint8_t *pu8Buf, uint32_t u32Size);
|
||||||
|
void USBD_CtrlOut_NS(void);
|
||||||
|
void USBD_SwReset_NS(void);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USBD_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USBD_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__USBD_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,320 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file USCI_I2C.h
|
||||||
|
* @version V3.0
|
||||||
|
* $Revision: 1 $
|
||||||
|
* $Date: 16/07/07 7:50p $
|
||||||
|
* @brief M2351 series USCI I2C(UI2C) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __USCI_I2C_H__
|
||||||
|
#define __USCI_I2C_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_I2C_Driver USCI_I2C Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_I2C_EXPORTED_CONSTANTS USCI_I2C Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI_I2C master event definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
enum UI2C_MASTER_EVENT
|
||||||
|
{
|
||||||
|
MASTER_SEND_ADDRESS = 10, /*!< Master send address to Slave */
|
||||||
|
MASTER_SEND_H_WR_ADDRESS, /*!< Master send High address to Slave */
|
||||||
|
MASTER_SEND_H_RD_ADDRESS, /*!< Master send address to Slave (Read ADDR) */
|
||||||
|
MASTER_SEND_L_ADDRESS, /*!< Master send Low address to Slave */
|
||||||
|
MASTER_SEND_DATA, /*!< Master Send Data to Slave */
|
||||||
|
MASTER_SEND_REPEAT_START, /*!< Master send repeat start to Slave */
|
||||||
|
MASTER_READ_DATA, /*!< Master Get Data from Slave */
|
||||||
|
MASTER_STOP, /*!< Master send stop to Slave */
|
||||||
|
MASTER_SEND_START /*!< Master send start to Slave */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI_I2C slave event definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
enum UI2C_SLAVE_EVENT
|
||||||
|
{
|
||||||
|
SLAVE_ADDRESS_ACK = 100, /*!< Slave send address ACK */
|
||||||
|
SLAVE_H_WR_ADDRESS_ACK, /*!< Slave send High address ACK */
|
||||||
|
SLAVE_L_WR_ADDRESS_ACK, /*!< Slave send Low address ACK */
|
||||||
|
SLAVE_GET_DATA, /*!< Slave Get Data from Master (Write CMD) */
|
||||||
|
SLAVE_SEND_DATA, /*!< Slave Send Data to Master (Read CMD) */
|
||||||
|
SLAVE_H_RD_ADDRESS_ACK, /*!< Slave send High address ACK */
|
||||||
|
SLAVE_L_RD_ADDRESS_ACK /*!< Slave send Low address ACK */
|
||||||
|
};
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI_CTL constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UI2C_CTL_PTRG 0x20UL /*!< USCI_CTL setting for I2C control bits. It would set PTRG bit */
|
||||||
|
#define UI2C_CTL_STA 0x08UL /*!< USCI_CTL setting for I2C control bits. It would set STA bit */
|
||||||
|
#define UI2C_CTL_STO 0x04UL /*!< USCI_CTL setting for I2C control bits. It would set STO bit */
|
||||||
|
#define UI2C_CTL_AA 0x02UL /*!< USCI_CTL setting for I2C control bits. It would set AA bit */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI_I2C GCMode constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UI2C_GCMODE_ENABLE (1) /*!< Enable USCI_I2C GC Mode */
|
||||||
|
#define UI2C_GCMODE_DISABLE (0) /*!< Disable USCI_I2C GC Mode */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI_I2C Wakeup Mode constant definitions. */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UI2C_DATA_TOGGLE_WK (0x0 << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according data toggle */
|
||||||
|
#define UI2C_ADDR_MATCH_WK (0x1 << UI2C_WKCTL_WKADDREN_Pos) /*!< Wakeup according address match */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI_I2C interrupt mask definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UI2C_TO_INT_MASK (0x001) /*!< Time-out interrupt mask */
|
||||||
|
#define UI2C_STAR_INT_MASK (0x002) /*!< Start condition received interrupt mask */
|
||||||
|
#define UI2C_STOR_INT_MASK (0x004) /*!< Stop condition received interrupt mask */
|
||||||
|
#define UI2C_NACK_INT_MASK (0x008) /*!< Non-acknowledge interrupt mask */
|
||||||
|
#define UI2C_ARBLO_INT_MASK (0x010) /*!< Arbitration lost interrupt mask */
|
||||||
|
#define UI2C_ERR_INT_MASK (0x020) /*!< Error interrupt mask */
|
||||||
|
#define UI2C_ACK_INT_MASK (0x040) /*!< Acknowledge interrupt mask */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_I2C_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup USCI_I2C_EXPORTED_FUNCTIONS USCI_I2C Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro sets the USCI_I2C protocol control register at one time
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
* @param[in] u8Ctrl Set the register value of USCI_I2C control register.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set UI2C_PROTCTL register to control USCI_I2C bus conditions of START, STOP, SI, ACK.
|
||||||
|
*/
|
||||||
|
#define UI2C_SET_CONTROL_REG(ui2c, u8Ctrl) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | u8Ctrl)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro only set START bit to protocol control register of USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the USCI_I2C bus START condition in UI2C_PROTCTL register.
|
||||||
|
*/
|
||||||
|
#define UI2C_START(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~UI2C_PROTCTL_PTRG_Msk) | UI2C_PROTCTL_STA_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro only set STOP bit to the control register of USCI_I2C module
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set the USCI_I2C bus STOP condition in UI2C_PROTCTL register.
|
||||||
|
*/
|
||||||
|
#define UI2C_STOP(ui2c) ((ui2c)->PROTCTL = ((ui2c)->PROTCTL & ~0x2E) | (UI2C_PROTCTL_PTRG_Msk | UI2C_PROTCTL_STO_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro returns the data stored in data register of USCI_I2C module
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return Data
|
||||||
|
*
|
||||||
|
* @details Read a byte data value of UI2C_RXDAT register from USCI_I2C bus
|
||||||
|
*/
|
||||||
|
#define UI2C_GET_DATA(ui2c) ((ui2c)->RXDAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro writes the data to data register of USCI_I2C module
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
* @param[in] u8Data The data which will be written to data register of USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Write a byte data value of UI2C_TXDAT register, then sends address or data to USCI I2C bus
|
||||||
|
*/
|
||||||
|
#define UI2C_SET_DATA(ui2c, u8Data) ((ui2c)->TXDAT = (u8Data))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro returns time-out flag
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @retval 0 USCI_I2C bus time-out is not happened
|
||||||
|
* @retval 1 USCI_I2C bus time-out is happened
|
||||||
|
*
|
||||||
|
* @details USCI_I2C bus occurs time-out event, the time-out flag will be set. If not occurs time-out event, this bit is cleared.
|
||||||
|
*/
|
||||||
|
#define UI2C_GET_TIMEOUT_FLAG(ui2c) (((ui2c)->PROTSTS & UI2C_PROTSTS_TOIF_Msk) == UI2C_PROTSTS_TOIF_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro returns wake-up flag
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @retval 0 Chip is not woken-up from power-down mode
|
||||||
|
* @retval 1 Chip is woken-up from power-down mode
|
||||||
|
*
|
||||||
|
* @details USCI_I2C controller wake-up flag will be set when USCI_I2C bus occurs wake-up from deep-sleep.
|
||||||
|
*/
|
||||||
|
#define UI2C_GET_WAKEUP_FLAG(ui2c) (((ui2c)->WKSTS & UI2C_WKSTS_WKF_Msk) == UI2C_WKSTS_WKF_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro is used to clear USCI_I2C wake-up flag
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details If USCI_I2C wake-up flag is set, use this macro to clear it.
|
||||||
|
*/
|
||||||
|
#define UI2C_CLR_WAKEUP_FLAG(ui2c) ((ui2c)->WKSTS = UI2C_WKSTS_WKF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables the USCI_I2C 10-bit address mode
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The UI2C_I2C is 7-bit address mode, when disable USCI_I2C 10-bit address match function.
|
||||||
|
*/
|
||||||
|
#define UI2C_DISABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL &= ~(UI2C_PROTCTL_ADDR10EN_Msk))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables the 10-bit address mode
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To enable USCI_I2C 10-bit address match function.
|
||||||
|
*/
|
||||||
|
#define UI2C_ENABLE_10BIT_ADDR_MODE(ui2c) ((ui2c)->PROTCTL |= UI2C_PROTCTL_ADDR10EN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro gets USCI_I2C protocol interrupt flag or bus status
|
||||||
|
*
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
*
|
||||||
|
* @return A word data of USCI_I2C_PROTSTS register
|
||||||
|
*
|
||||||
|
* @details Read a word data of USCI_I2C PROTSTS register to get USCI_I2C bus Interrupt flags or status.
|
||||||
|
*/
|
||||||
|
#define UI2C_GET_PROT_STATUS(ui2c) ((ui2c)->PROTSTS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro clears specified protocol interrupt flag
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||||
|
* - \ref UI2C_PROTSTS_ACKIF_Msk
|
||||||
|
* - \ref UI2C_PROTSTS_ERRIF_Msk
|
||||||
|
* - \ref UI2C_PROTSTS_ARBLOIF_Msk
|
||||||
|
* - \ref UI2C_PROTSTS_NACKIF_Msk
|
||||||
|
* - \ref UI2C_PROTSTS_STORIF_Msk
|
||||||
|
* - \ref UI2C_PROTSTS_STARIF_Msk
|
||||||
|
* - \ref UI2C_PROTSTS_TOIF_Msk
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details To clear interrupt flag when USCI_I2C occurs interrupt and set interrupt flag.
|
||||||
|
*/
|
||||||
|
#define UI2C_CLR_PROT_INT_FLAG(ui2c,u32IntTypeFlag) ((ui2c)->PROTSTS = (u32IntTypeFlag))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro enables specified protocol interrupt
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref UI2C_PROTIEN_ACKIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_ERRIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_ARBLOIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_NACKIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_STORIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_STARIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_TOIEN_Msk
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Set specified USCI_I2C protocol interrupt bits to enable interrupt function.
|
||||||
|
*/
|
||||||
|
#define UI2C_ENABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN |= (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This macro disables specified protocol interrupt
|
||||||
|
* @param[in] ui2c The pointer of the specified USCI_I2C module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref UI2C_PROTIEN_ACKIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_ERRIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_ARBLOIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_NACKIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_STORIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_STARIEN_Msk
|
||||||
|
* - \ref UI2C_PROTIEN_TOIEN_Msk
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details Clear specified USCI_I2C protocol interrupt bits to disable interrupt funtion.
|
||||||
|
*/
|
||||||
|
#define UI2C_DISABLE_PROT_INT(ui2c, u32IntSel) ((ui2c)->PROTIEN &= ~ (u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t UI2C_Open(UI2C_T *ui2c, uint32_t u32BusClock);
|
||||||
|
void UI2C_Close(UI2C_T *ui2c);
|
||||||
|
void UI2C_ClearTimeoutFlag(UI2C_T *ui2c);
|
||||||
|
void UI2C_Trigger(UI2C_T *ui2c, uint8_t u8Start, uint8_t u8Stop, uint8_t u8Ptrg, uint8_t u8Ack);
|
||||||
|
void UI2C_DisableInt(UI2C_T *ui2c, uint32_t u32Mask);
|
||||||
|
void UI2C_EnableInt(UI2C_T *ui2c, uint32_t u32Mask);
|
||||||
|
uint32_t UI2C_GetBusClockFreq(UI2C_T *ui2c);
|
||||||
|
uint32_t UI2C_SetBusClockFreq(UI2C_T *ui2c, uint32_t u32BusClock);
|
||||||
|
uint32_t UI2C_GetIntFlag(UI2C_T *ui2c, uint32_t u32Mask);
|
||||||
|
void UI2C_ClearIntFlag(UI2C_T* ui2c , uint32_t u32Mask);
|
||||||
|
uint32_t UI2C_GetData(UI2C_T *ui2c);
|
||||||
|
void UI2C_SetData(UI2C_T *ui2c, uint8_t u8Data);
|
||||||
|
void UI2C_SetSlaveAddr(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddr, uint8_t u8GCMode);
|
||||||
|
void UI2C_SetSlaveAddrMask(UI2C_T *ui2c, uint8_t u8SlaveNo, uint16_t u16SlaveAddrMask);
|
||||||
|
void UI2C_EnableTimeout(UI2C_T *ui2c, uint32_t u32TimeoutCnt);
|
||||||
|
void UI2C_DisableTimeout(UI2C_T *ui2c);
|
||||||
|
void UI2C_EnableWakeup(UI2C_T *ui2c, uint8_t u8WakeupMode);
|
||||||
|
void UI2C_DisableWakeup(UI2C_T *ui2c);
|
||||||
|
uint8_t UI2C_WriteByte(UI2C_T *ui2c, uint8_t u8SlaveAddr, const uint8_t data);
|
||||||
|
uint32_t UI2C_WriteMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, const uint8_t *data, uint32_t u32wLen);
|
||||||
|
uint8_t UI2C_WriteByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t data);
|
||||||
|
uint32_t UI2C_WriteMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, const uint8_t *data, uint32_t u32wLen);
|
||||||
|
uint8_t UI2C_WriteByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t data);
|
||||||
|
uint32_t UI2C_WriteMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, const uint8_t *data, uint32_t u32wLen);
|
||||||
|
uint8_t UI2C_ReadByte(UI2C_T *ui2c, uint8_t u8SlaveAddr);
|
||||||
|
uint32_t UI2C_ReadMultiBytes(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||||
|
uint8_t UI2C_ReadByteOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
|
||||||
|
uint32_t UI2C_ReadMultiBytesOneReg(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||||
|
uint8_t UI2C_ReadByteTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
|
||||||
|
uint32_t UI2C_ReadMultiBytesTwoRegs(UI2C_T *ui2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t *rdata, uint32_t u32rLen);
|
||||||
|
/*@}*/ /* end of group USCI_I2C_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_I2C_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__USCI_I2C_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,526 @@
|
||||||
|
/****************************************************************************//**
|
||||||
|
* @file usci_spi.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series USCI_SPI driver source file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief This function make USCI_SPI module be ready to transfer.
|
||||||
|
* By default, the USCI_SPI transfer sequence is MSB first, the slave selection
|
||||||
|
* signal is active low and the automatic slave select function is disabled. In
|
||||||
|
* Slave mode, the u32BusClock must be NULL and the USCI_SPI clock
|
||||||
|
* divider setting will be 0.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32MasterSlave Decide the USCI_SPI module is operating in master mode or in slave mode. Valid values are:
|
||||||
|
* - \ref USPI_SLAVE
|
||||||
|
* - \ref USPI_MASTER
|
||||||
|
* @param[in] u32SPIMode Decide the transfer timing. Valid values are:
|
||||||
|
* - \ref USPI_MODE_0
|
||||||
|
* - \ref USPI_MODE_1
|
||||||
|
* - \ref USPI_MODE_2
|
||||||
|
* - \ref USPI_MODE_3
|
||||||
|
* @param[in] u32DataWidth The data width of a USCI_SPI transaction.
|
||||||
|
* @param[in] u32BusClock The expected frequency of USCI_SPI bus clock in Hz.
|
||||||
|
* @return Actual frequency of USCI_SPI peripheral clock.
|
||||||
|
*/
|
||||||
|
uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock)
|
||||||
|
{
|
||||||
|
uint32_t u32ClkDiv = 0;
|
||||||
|
uint32_t u32Pclk;
|
||||||
|
|
||||||
|
if((uspi == USPI0) || (uspi == USPI0_NS))
|
||||||
|
{
|
||||||
|
u32Pclk = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Pclk = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
|
||||||
|
if(u32BusClock != 0)
|
||||||
|
u32ClkDiv = (uint32_t)((((((u32Pclk / 2) * 10) / (u32BusClock)) + 5) / 10) - 1); /* Compute proper divider for USCI_SPI clock */
|
||||||
|
|
||||||
|
/* Enable USCI_SPI protocol */
|
||||||
|
uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
|
||||||
|
uspi->CTL = 1 << USPI_CTL_FUNMODE_Pos;
|
||||||
|
|
||||||
|
/* Data format configuration */
|
||||||
|
if(u32DataWidth == 16)
|
||||||
|
u32DataWidth = 0;
|
||||||
|
uspi->LINECTL &= ~USPI_LINECTL_DWIDTH_Msk;
|
||||||
|
uspi->LINECTL |= (u32DataWidth << USPI_LINECTL_DWIDTH_Pos);
|
||||||
|
|
||||||
|
/* MSB data format */
|
||||||
|
uspi->LINECTL &= ~USPI_LINECTL_LSB_Msk;
|
||||||
|
|
||||||
|
/* Set slave selection signal active low */
|
||||||
|
if(u32MasterSlave == USPI_MASTER)
|
||||||
|
uspi->LINECTL |= USPI_LINECTL_CTLOINV_Msk;
|
||||||
|
else
|
||||||
|
uspi->CTLIN0 |= USPI_CTLIN0_ININV_Msk;
|
||||||
|
|
||||||
|
/* Set operating mode and transfer timing */
|
||||||
|
uspi->PROTCTL &= ~(USPI_PROTCTL_SCLKMODE_Msk | USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SLAVE_Msk);
|
||||||
|
uspi->PROTCTL |= (u32MasterSlave | u32SPIMode);
|
||||||
|
|
||||||
|
/* Set USCI_SPI bus clock */
|
||||||
|
uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
|
||||||
|
uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
|
||||||
|
uspi->PROTCTL |= USPI_PROTCTL_PROTEN_Msk;
|
||||||
|
|
||||||
|
if(u32BusClock != 0)
|
||||||
|
return (u32Pclk / ((u32ClkDiv + 1) << 1));
|
||||||
|
else
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USCI_SPI function mode.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_Close(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uspi->CTL &= ~USPI_CTL_FUNMODE_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Rx buffer.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_ClearRxBuf(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uspi->BUFCTL |= USPI_BUFCTL_RXCLR_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear Tx buffer.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_ClearTxBuf(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uspi->BUFCTL |= USPI_BUFCTL_TXCLR_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable the automatic slave select function.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_DisableAutoSS(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uspi->PROTCTL &= ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable the automatic slave select function. Only available in Master mode.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32SSPinMask This parameter is not used.
|
||||||
|
* @param[in] u32ActiveLevel The active level of slave select signal. Valid values are:
|
||||||
|
* - \ref USPI_SS_ACTIVE_HIGH
|
||||||
|
* - \ref USPI_SS_ACTIVE_LOW
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
|
||||||
|
{
|
||||||
|
uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_CTLOINV_Msk) | u32ActiveLevel;
|
||||||
|
uspi->PROTCTL |= USPI_PROTCTL_AUTOSS_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the USCI_SPI bus clock. Only available in Master mode.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32BusClock The expected frequency of USCI_SPI bus clock.
|
||||||
|
* @return Actual frequency of USCI_SPI peripheral clock.
|
||||||
|
*/
|
||||||
|
uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock)
|
||||||
|
{
|
||||||
|
uint32_t u32ClkDiv;
|
||||||
|
uint32_t u32Pclk;
|
||||||
|
|
||||||
|
if((uspi == USPI0) || (uspi == USPI0_NS))
|
||||||
|
{
|
||||||
|
u32Pclk = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Pclk = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
|
||||||
|
if(uspi == USPI0)
|
||||||
|
{
|
||||||
|
u32Pclk = CLK_GetPCLK0Freq();
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32Pclk = CLK_GetPCLK1Freq();
|
||||||
|
}
|
||||||
|
|
||||||
|
u32ClkDiv = (uint32_t)((((((u32Pclk / 2) * 10) / (u32BusClock)) + 5) / 10) - 1); /* Compute proper divider for USCI_SPI clock */
|
||||||
|
|
||||||
|
/* Set USCI_SPI bus clock */
|
||||||
|
uspi->BRGEN &= ~USPI_BRGEN_CLKDIV_Msk;
|
||||||
|
uspi->BRGEN |= (u32ClkDiv << USPI_BRGEN_CLKDIV_Pos);
|
||||||
|
|
||||||
|
return (u32Pclk / ((u32ClkDiv + 1) << 1));
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the actual frequency of USCI_SPI bus clock. Only available in Master mode.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return Actual USCI_SPI bus clock frequency.
|
||||||
|
*/
|
||||||
|
uint32_t USPI_GetBusClock(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uint32_t u32ClkDiv;
|
||||||
|
|
||||||
|
u32ClkDiv = (uspi->BRGEN & USPI_BRGEN_CLKDIV_Msk) >> USPI_BRGEN_CLKDIV_Pos;
|
||||||
|
|
||||||
|
if((uspi == USPI0) || (uspi == USPI0_NS))
|
||||||
|
{
|
||||||
|
return ( CLK_GetPCLK0Freq() / ((u32ClkDiv+1)<<1) );
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return ( CLK_GetPCLK1Freq() / ((u32ClkDiv+1)<<1) );
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable related interrupts specified by u32Mask parameter.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt bit.
|
||||||
|
* This parameter decides which interrupts will be enabled. Valid values are:
|
||||||
|
* - \ref USPI_SSINACT_INT_MASK
|
||||||
|
* - \ref USPI_SSACT_INT_MASK
|
||||||
|
* - \ref USPI_SLVTO_INT_MASK
|
||||||
|
* - \ref USPI_SLVBE_INT_MASK
|
||||||
|
* - \ref USPI_TXUDR_INT_MASK
|
||||||
|
* - \ref USPI_RXOV_INT_MASK
|
||||||
|
* - \ref USPI_TXST_INT_MASK
|
||||||
|
* - \ref USPI_TXEND_INT_MASK
|
||||||
|
* - \ref USPI_RXST_INT_MASK
|
||||||
|
* - \ref USPI_RXEND_INT_MASK
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
/* Enable slave selection signal inactive interrupt flag */
|
||||||
|
if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
|
||||||
|
uspi->PROTIEN |= USPI_PROTIEN_SSINAIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable slave selection signal active interrupt flag */
|
||||||
|
if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
|
||||||
|
uspi->PROTIEN |= USPI_PROTIEN_SSACTIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable slave time-out interrupt flag */
|
||||||
|
if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
|
||||||
|
uspi->PROTIEN |= USPI_PROTIEN_SLVTOIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable slave bit count error interrupt flag */
|
||||||
|
if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
|
||||||
|
uspi->PROTIEN |= USPI_PROTIEN_SLVBEIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable TX under run interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
|
||||||
|
uspi->BUFCTL |= USPI_BUFCTL_TXUDRIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable RX overrun interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
|
||||||
|
uspi->BUFCTL |= USPI_BUFCTL_RXOVIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable TX start interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
|
||||||
|
uspi->INTEN |= USPI_INTEN_TXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable TX end interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
|
||||||
|
uspi->INTEN |= USPI_INTEN_TXENDIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable RX start interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
|
||||||
|
uspi->INTEN |= USPI_INTEN_RXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable RX end interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
|
||||||
|
uspi->INTEN |= USPI_INTEN_RXENDIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable related interrupts specified by u32Mask parameter.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt bit.
|
||||||
|
* This parameter decides which interrupts will be disabled. Valid values are:
|
||||||
|
* - \ref USPI_SSINACT_INT_MASK
|
||||||
|
* - \ref USPI_SSACT_INT_MASK
|
||||||
|
* - \ref USPI_SLVTO_INT_MASK
|
||||||
|
* - \ref USPI_SLVBE_INT_MASK
|
||||||
|
* - \ref USPI_TXUDR_INT_MASK
|
||||||
|
* - \ref USPI_RXOV_INT_MASK
|
||||||
|
* - \ref USPI_TXST_INT_MASK
|
||||||
|
* - \ref USPI_TXEND_INT_MASK
|
||||||
|
* - \ref USPI_RXST_INT_MASK
|
||||||
|
* - \ref USPI_RXEND_INT_MASK
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
/* Disable slave selection signal inactive interrupt flag */
|
||||||
|
if((u32Mask & USPI_SSINACT_INT_MASK) == USPI_SSINACT_INT_MASK)
|
||||||
|
uspi->PROTIEN &= ~USPI_PROTIEN_SSINAIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable slave selection signal active interrupt flag */
|
||||||
|
if((u32Mask & USPI_SSACT_INT_MASK) == USPI_SSACT_INT_MASK)
|
||||||
|
uspi->PROTIEN &= ~USPI_PROTIEN_SSACTIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable slave time-out interrupt flag */
|
||||||
|
if((u32Mask & USPI_SLVTO_INT_MASK) == USPI_SLVTO_INT_MASK)
|
||||||
|
uspi->PROTIEN &= ~USPI_PROTIEN_SLVTOIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable slave bit count error interrupt flag */
|
||||||
|
if((u32Mask & USPI_SLVBE_INT_MASK) == USPI_SLVBE_INT_MASK)
|
||||||
|
uspi->PROTIEN &= ~USPI_PROTIEN_SLVBEIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable TX under run interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXUDR_INT_MASK) == USPI_TXUDR_INT_MASK)
|
||||||
|
uspi->BUFCTL &= ~USPI_BUFCTL_TXUDRIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable RX overrun interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXOV_INT_MASK) == USPI_RXOV_INT_MASK)
|
||||||
|
uspi->BUFCTL &= ~USPI_BUFCTL_RXOVIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable TX start interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXST_INT_MASK) == USPI_TXST_INT_MASK)
|
||||||
|
uspi->INTEN &= ~USPI_INTEN_TXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable TX end interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXEND_INT_MASK) == USPI_TXEND_INT_MASK)
|
||||||
|
uspi->INTEN &= ~USPI_INTEN_TXENDIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable RX start interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXST_INT_MASK) == USPI_RXST_INT_MASK)
|
||||||
|
uspi->INTEN &= ~USPI_INTEN_RXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable RX end interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXEND_INT_MASK) == USPI_RXEND_INT_MASK)
|
||||||
|
uspi->INTEN &= ~USPI_INTEN_RXENDIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get interrupt flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||||
|
* Each bit corresponds to a interrupt source.
|
||||||
|
* This parameter decides which interrupt flags will be read. It is combination of:
|
||||||
|
* - \ref USPI_SSINACT_INT_MASK
|
||||||
|
* - \ref USPI_SSACT_INT_MASK
|
||||||
|
* - \ref USPI_SLVTO_INT_MASK
|
||||||
|
* - \ref USPI_SLVBE_INT_MASK
|
||||||
|
* - \ref USPI_TXUDR_INT_MASK
|
||||||
|
* - \ref USPI_RXOV_INT_MASK
|
||||||
|
* - \ref USPI_TXST_INT_MASK
|
||||||
|
* - \ref USPI_TXEND_INT_MASK
|
||||||
|
* - \ref USPI_RXST_INT_MASK
|
||||||
|
* - \ref USPI_RXEND_INT_MASK
|
||||||
|
* @return Interrupt flags of selected sources.
|
||||||
|
*/
|
||||||
|
uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
uint32_t u32IntFlag = 0;
|
||||||
|
|
||||||
|
/* Check slave selection signal inactive interrupt flag */
|
||||||
|
if((u32Mask & USPI_SSINACT_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_SSINAIF_Msk))
|
||||||
|
u32IntFlag |= USPI_SSINACT_INT_MASK;
|
||||||
|
|
||||||
|
/* Check slave selection signal active interrupt flag */
|
||||||
|
if((u32Mask & USPI_SSACT_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_SSACTIF_Msk))
|
||||||
|
u32IntFlag |= USPI_SSACT_INT_MASK;
|
||||||
|
|
||||||
|
/* Check slave time-out interrupt flag */
|
||||||
|
if((u32Mask & USPI_SLVTO_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_SLVTOIF_Msk))
|
||||||
|
u32IntFlag |= USPI_SLVTO_INT_MASK;
|
||||||
|
|
||||||
|
/* Check slave bit count error interrupt flag */
|
||||||
|
if((u32Mask & USPI_SLVBE_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_SLVBEIF_Msk))
|
||||||
|
u32IntFlag |= USPI_SLVBE_INT_MASK;
|
||||||
|
|
||||||
|
/* Check TX under run interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXUDR_INT_MASK) && (uspi->BUFSTS & USPI_BUFSTS_TXUDRIF_Msk))
|
||||||
|
u32IntFlag |= USPI_TXUDR_INT_MASK;
|
||||||
|
|
||||||
|
/* Check RX overrun interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXOV_INT_MASK) && (uspi->BUFSTS & USPI_BUFSTS_RXOVIF_Msk))
|
||||||
|
u32IntFlag |= USPI_RXOV_INT_MASK;
|
||||||
|
|
||||||
|
/* Check TX start interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXST_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_TXSTIF_Msk))
|
||||||
|
u32IntFlag |= USPI_TXST_INT_MASK;
|
||||||
|
|
||||||
|
/* Check TX end interrupt flag */
|
||||||
|
if((u32Mask & USPI_TXEND_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_TXENDIF_Msk))
|
||||||
|
u32IntFlag |= USPI_TXEND_INT_MASK;
|
||||||
|
|
||||||
|
/* Check RX start interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXST_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_RXSTIF_Msk))
|
||||||
|
u32IntFlag |= USPI_RXST_INT_MASK;
|
||||||
|
|
||||||
|
/* Check RX end interrupt flag */
|
||||||
|
if((u32Mask & USPI_RXEND_INT_MASK) && (uspi->PROTSTS & USPI_PROTSTS_RXENDIF_Msk))
|
||||||
|
u32IntFlag |= USPI_RXEND_INT_MASK;
|
||||||
|
|
||||||
|
return u32IntFlag;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear interrupt flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||||
|
* Each bit corresponds to a interrupt source.
|
||||||
|
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
|
||||||
|
* - \ref USPI_SSINACT_INT_MASK
|
||||||
|
* - \ref USPI_SSACT_INT_MASK
|
||||||
|
* - \ref USPI_SLVTO_INT_MASK
|
||||||
|
* - \ref USPI_SLVBE_INT_MASK
|
||||||
|
* - \ref USPI_TXUDR_INT_MASK
|
||||||
|
* - \ref USPI_RXOV_INT_MASK
|
||||||
|
* - \ref USPI_TXST_INT_MASK
|
||||||
|
* - \ref USPI_TXEND_INT_MASK
|
||||||
|
* - \ref USPI_RXST_INT_MASK
|
||||||
|
* - \ref USPI_RXEND_INT_MASK
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
/* Clear slave selection signal inactive interrupt flag */
|
||||||
|
if(u32Mask & USPI_SSINACT_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_SSINAIF_Msk;
|
||||||
|
|
||||||
|
/* Clear slave selection signal active interrupt flag */
|
||||||
|
if(u32Mask & USPI_SSACT_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_SSACTIF_Msk;
|
||||||
|
|
||||||
|
/* Clear slave time-out interrupt flag */
|
||||||
|
if(u32Mask & USPI_SLVTO_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_SLVTOIF_Msk;
|
||||||
|
|
||||||
|
/* Clear slave bit count error interrupt flag */
|
||||||
|
if(u32Mask & USPI_SLVBE_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_SLVBEIF_Msk;
|
||||||
|
|
||||||
|
/* Clear TX under run interrupt flag */
|
||||||
|
if(u32Mask & USPI_TXUDR_INT_MASK)
|
||||||
|
uspi->BUFSTS = USPI_BUFSTS_TXUDRIF_Msk;
|
||||||
|
|
||||||
|
/* Clear RX overrun interrupt flag */
|
||||||
|
if(u32Mask & USPI_RXOV_INT_MASK)
|
||||||
|
uspi->BUFSTS = USPI_BUFSTS_RXOVIF_Msk;
|
||||||
|
|
||||||
|
/* Clear TX start interrupt flag */
|
||||||
|
if(u32Mask & USPI_TXST_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_TXSTIF_Msk;
|
||||||
|
|
||||||
|
/* Clear TX end interrupt flag */
|
||||||
|
if(u32Mask & USPI_TXEND_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_TXENDIF_Msk;
|
||||||
|
|
||||||
|
/* Clear RX start interrupt flag */
|
||||||
|
if(u32Mask & USPI_RXST_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_RXSTIF_Msk;
|
||||||
|
|
||||||
|
/* Clear RX end interrupt flag */
|
||||||
|
if(u32Mask & USPI_RXEND_INT_MASK)
|
||||||
|
uspi->PROTSTS = USPI_PROTSTS_RXENDIF_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USCI_SPI status.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32Mask The combination of all related sources.
|
||||||
|
* Each bit corresponds to a source.
|
||||||
|
* This parameter decides which flags will be read. It is combination of:
|
||||||
|
* - \ref USPI_BUSY_MASK
|
||||||
|
* - \ref USPI_RX_EMPTY_MASK
|
||||||
|
* - \ref USPI_RX_FULL_MASK
|
||||||
|
* - \ref USPI_TX_EMPTY_MASK
|
||||||
|
* - \ref USPI_TX_FULL_MASK
|
||||||
|
* - \ref USPI_SSLINE_STS_MASK
|
||||||
|
* @return Flags of selected sources.
|
||||||
|
*/
|
||||||
|
uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
uint32_t u32Flag = 0;
|
||||||
|
|
||||||
|
/* Check busy status */
|
||||||
|
if((u32Mask & USPI_BUSY_MASK) && (uspi->PROTSTS & USPI_PROTSTS_BUSY_Msk))
|
||||||
|
u32Flag |= USPI_BUSY_MASK;
|
||||||
|
|
||||||
|
/* Check RX empty flag */
|
||||||
|
if((u32Mask & USPI_RX_EMPTY_MASK) && (uspi->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk))
|
||||||
|
u32Flag |= USPI_RX_EMPTY_MASK;
|
||||||
|
|
||||||
|
/* Check RX full flag */
|
||||||
|
if((u32Mask & USPI_RX_FULL_MASK) && (uspi->BUFSTS & USPI_BUFSTS_RXFULL_Msk))
|
||||||
|
u32Flag |= USPI_RX_FULL_MASK;
|
||||||
|
|
||||||
|
/* Check TX empty flag */
|
||||||
|
if((u32Mask & USPI_TX_EMPTY_MASK) && (uspi->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk))
|
||||||
|
u32Flag |= USPI_TX_EMPTY_MASK;
|
||||||
|
|
||||||
|
/* Check TX full flag */
|
||||||
|
if((u32Mask & USPI_TX_FULL_MASK) && (uspi->BUFSTS & USPI_BUFSTS_TXFULL_Msk))
|
||||||
|
u32Flag |= USPI_TX_FULL_MASK;
|
||||||
|
|
||||||
|
/* Check USCI_SPI_SS line status */
|
||||||
|
if((u32Mask & USPI_SSLINE_STS_MASK) && (uspi->PROTSTS & USPI_PROTSTS_SSLINE_Msk))
|
||||||
|
u32Flag |= USPI_SSLINE_STS_MASK;
|
||||||
|
|
||||||
|
return u32Flag;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USCI_SPI Wake-up Function.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_EnableWakeup(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uspi->WKCTL |= USPI_WKCTL_WKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USCI_SPI Wake-up Function.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
*/
|
||||||
|
void USPI_DisableWakeup(USPI_T *uspi)
|
||||||
|
{
|
||||||
|
uspi->WKCTL &= ~USPI_WKCTL_WKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_SPI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,404 @@
|
||||||
|
/****************************************************************************//**
|
||||||
|
* @file usci_spi.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series USCI_SPI driver header file
|
||||||
|
*
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __USCI_SPI_H__
|
||||||
|
#define __USCI_SPI_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_SPI_Driver USCI_SPI Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_SPI_EXPORTED_CONSTANTS USCI_SPI Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
#define USPI_MODE_0 (0x0 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with falling edge and receive with rising edge */
|
||||||
|
#define USPI_MODE_1 (0x1 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle low; data transmit with rising edge and receive with falling edge */
|
||||||
|
#define USPI_MODE_2 (0x2 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with rising edge and receive with falling edge */
|
||||||
|
#define USPI_MODE_3 (0x3 << USPI_PROTCTL_SCLKMODE_Pos) /*!< SCLK idle high; data transmit with falling edge and receive with rising edge */
|
||||||
|
|
||||||
|
#define USPI_SLAVE (USPI_PROTCTL_SLAVE_Msk) /*!< Set as slave */
|
||||||
|
#define USPI_MASTER (0x0) /*!< Set as master */
|
||||||
|
|
||||||
|
#define USPI_SS (USPI_PROTCTL_SS_Msk) /*!< Set SS */
|
||||||
|
#define USPI_SS_ACTIVE_HIGH (0x0) /*!< SS active high */
|
||||||
|
#define USPI_SS_ACTIVE_LOW (USPI_LINECTL_CTLOINV_Msk) /*!< SS active low */
|
||||||
|
|
||||||
|
/* USCI_SPI Interrupt Mask */
|
||||||
|
#define USPI_SSINACT_INT_MASK (0x001) /*!< Slave Slave Inactive interrupt mask */
|
||||||
|
#define USPI_SSACT_INT_MASK (0x002) /*!< Slave Slave Active interrupt mask */
|
||||||
|
#define USPI_SLVTO_INT_MASK (0x004) /*!< Slave Mode Time-out interrupt mask */
|
||||||
|
#define USPI_SLVBE_INT_MASK (0x008) /*!< Slave Mode Bit Count Error interrupt mask */
|
||||||
|
#define USPI_TXUDR_INT_MASK (0x010) /*!< Slave Transmit Under Run interrupt mask */
|
||||||
|
#define USPI_RXOV_INT_MASK (0x020) /*!< Receive Buffer Overrun interrupt mask */
|
||||||
|
#define USPI_TXST_INT_MASK (0x040) /*!< Transmit Start interrupt mask */
|
||||||
|
#define USPI_TXEND_INT_MASK (0x080) /*!< Transmit End interrupt mask */
|
||||||
|
#define USPI_RXST_INT_MASK (0x100) /*!< Receive Start interrupt mask */
|
||||||
|
#define USPI_RXEND_INT_MASK (0x200) /*!< Receive End interrupt mask */
|
||||||
|
|
||||||
|
/* USCI_SPI Status Mask */
|
||||||
|
#define USPI_BUSY_MASK (0x01) /*!< Busy status mask */
|
||||||
|
#define USPI_RX_EMPTY_MASK (0x02) /*!< RX empty status mask */
|
||||||
|
#define USPI_RX_FULL_MASK (0x04) /*!< RX full status mask */
|
||||||
|
#define USPI_TX_EMPTY_MASK (0x08) /*!< TX empty status mask */
|
||||||
|
#define USPI_TX_FULL_MASK (0x10) /*!< TX full status mask */
|
||||||
|
#define USPI_SSLINE_STS_MASK (0x20) /*!< USCI_SPI_SS line status mask */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_SPI_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup USCI_SPI_EXPORTED_FUNCTIONS USCI_SPI Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable slave 3-wire mode.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_DISABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL &= ~USPI_PROTCTL_SLV3WIRE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable slave 3-wire mode.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_ENABLE_3WIRE_MODE(uspi) ( (uspi)->PROTCTL |= USPI_PROTCTL_SLV3WIRE_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the Rx buffer empty flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return Rx buffer flag
|
||||||
|
* @retval 0: Rx buffer is not empty
|
||||||
|
* @retval 1: Rx buffer is empty
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_GET_RX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_RXEMPTY_Msk) == USPI_BUFSTS_RXEMPTY_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the Tx buffer empty flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return Tx buffer flag
|
||||||
|
* @retval 0: Tx buffer is not empty
|
||||||
|
* @retval 1: Tx buffer is empty
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_GET_TX_EMPTY_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXEMPTY_Msk) == USPI_BUFSTS_TXEMPTY_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the Tx buffer full flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return Tx buffer flag
|
||||||
|
* @retval 0: Tx buffer is not full
|
||||||
|
* @retval 1: Tx buffer is full
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_GET_TX_FULL_FLAG(uspi) ( ((uspi)->BUFSTS & USPI_BUFSTS_TXFULL_Msk) == USPI_BUFSTS_TXFULL_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the datum read from RX register.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return data in Rx register
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_READ_RX(uspi) ((uspi)->RXDAT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write datum to TX register.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32TxData The datum which user attempt to transfer through USCI_SPI bus.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_WRITE_TX(uspi, u32TxData) ( (uspi)->TXDAT = u32TxData )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USCI_SPI_SS pin to high state.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set USCI_SPI_SS pin to high state. Only available in Master mode.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_SET_SS_HIGH(uspi) \
|
||||||
|
do{ \
|
||||||
|
(uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
|
||||||
|
(uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USCI_SPI_SS pin to low state.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Disable automatic slave selection function and set USCI_SPI_SS pin to low state. Only available in Master mode.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_SET_SS_LOW(uspi) \
|
||||||
|
do{ \
|
||||||
|
(uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \
|
||||||
|
(uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
|
||||||
|
}while(0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the length of suspend interval.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32SuspCycle Decide the length of suspend interval.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_SET_SUSPEND_CYCLE(uspi, u32SuspCycle) ( (uspi)->PROTCTL = ((uspi)->PROTCTL & ~USPI_PROTCTL_SUSPITV_Msk) | (u32SuspCycle << USPI_PROTCTL_SUSPITV_Pos) )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the USCI_SPI transfer sequence with LSB first.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_SET_LSB_FIRST(uspi) ( (uspi)->LINECTL |= USPI_LINECTL_LSB_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the USCI_SPI transfer sequence with MSB first.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_SET_MSB_FIRST(uspi) ( (uspi)->LINECTL &= ~USPI_LINECTL_LSB_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set the data width of a USCI_SPI transaction.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32Width The data width
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
static __INLINE void USPI_SET_DATA_WIDTH(USPI_T *uspi, uint32_t u32Width)
|
||||||
|
{
|
||||||
|
if(u32Width == 16)
|
||||||
|
u32Width = 0;
|
||||||
|
|
||||||
|
uspi->LINECTL = (uspi->LINECTL & ~USPI_LINECTL_DWIDTH_Msk) | (u32Width << USPI_LINECTL_DWIDTH_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the USCI_SPI busy state.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return USCI_SPI busy status
|
||||||
|
* @retval 0: USCI_SPI module is not busy
|
||||||
|
* @retval 1: USCI_SPI module is busy
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_IS_BUSY(uspi) ( ((uspi)->PROTSTS & USPI_PROTSTS_BUSY_Msk) == USPI_PROTSTS_BUSY_Msk ? 1:0 )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get the USCI_SPI wakeup flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return Wakeup status.
|
||||||
|
* @retval 0 Flag is not set.
|
||||||
|
* @retval 1 Flag is set.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_GET_WAKEUP_FLAG(uspi) ( ((uspi)->WKSTS & USPI_WKSTS_WKF_Msk) == USPI_WKSTS_WKF_Msk ? 1:0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear the USCI_SPI wakeup flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_CLR_WAKEUP_FLAG(uspi) ( (uspi)->WKSTS |= USPI_WKSTS_WKF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get protocol interrupt flag/status.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return The interrupt flag/status of protocol status register.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_GET_PROT_STATUS(uspi) ( (uspi)->PROTSTS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified protocol interrupt flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||||
|
* - \ref USPI_PROTSTS_SSACTIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_SSINAIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_SLVBEIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_SLVTOIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_RXENDIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_RXSTIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_TXENDIF_Msk
|
||||||
|
* - \ref USPI_PROTSTS_TXSTIF_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_CLR_PROT_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->PROTSTS = u32IntTypeFlag)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get buffer interrupt flag/status.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return The interrupt flag/status of buffer status register.
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_GET_BUF_STATUS(uspi) ( (uspi)->BUFSTS)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified buffer interrupt flag.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||||
|
* - \ref USPI_BUFSTS_TXUDRIF_Msk
|
||||||
|
* - \ref USPI_BUFSTS_RXOVIF_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_CLR_BUF_INT_FLAG(uspi,u32IntTypeFlag) ( (uspi)->BUFSTS = u32IntTypeFlag)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified protocol interrupt.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref USPI_PROTIEN_SLVBEIEN_Msk
|
||||||
|
* - \ref USPI_PROTIEN_SLVTOIEN_Msk
|
||||||
|
* - \ref USPI_PROTIEN_SSACTIEN_Msk
|
||||||
|
* - \ref USPI_PROTIEN_SSINAIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_ENABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN |= (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified protocol interrupt.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref USPI_PROTIEN_SLVBEIEN_Msk
|
||||||
|
* - \ref USPI_PROTIEN_SLVTOIEN_Msk
|
||||||
|
* - \ref USPI_PROTIEN_SSACTIEN_Msk
|
||||||
|
* - \ref USPI_PROTIEN_SSINAIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_DISABLE_PROT_INT(uspi, u32IntSel) ((uspi)->PROTIEN &= ~ (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified buffer interrupt.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref USPI_BUFCTL_RXOVIEN_Msk
|
||||||
|
* - \ref USPI_BUFCTL_TXUDRIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_ENABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL |= (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified buffer interrupt.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref USPI_BUFCTL_RXOVIEN_Msk
|
||||||
|
* - \ref USPI_BUFCTL_TXUDRIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_DISABLE_BUF_INT(uspi, u32IntSel) ((uspi)->BUFCTL &= ~ (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified transfer interrupt.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref USPI_INTEN_RXENDIEN_Msk
|
||||||
|
* - \ref USPI_INTEN_RXSTIEN_Msk
|
||||||
|
* - \ref USPI_INTEN_TXENDIEN_Msk
|
||||||
|
* - \ref USPI_INTEN_TXSTIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_ENABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN |= (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified transfer interrupt.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @param[in] u32IntSel Interrupt Type, should be
|
||||||
|
* - \ref USPI_INTEN_RXENDIEN_Msk
|
||||||
|
* - \ref USPI_INTEN_RXSTIEN_Msk
|
||||||
|
* - \ref USPI_INTEN_TXENDIEN_Msk
|
||||||
|
* - \ref USPI_INTEN_TXSTIEN_Msk
|
||||||
|
* @return None
|
||||||
|
* \hideinitializer
|
||||||
|
*/
|
||||||
|
#define USPI_DISABLE_TRANS_INT(uspi, u32IntSel) ((uspi)->INTEN &= ~ (u32IntSel))
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger RX PDMA function.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set RXPDMAEN bit of USPI_PDMACTL register to enable RX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define USPI_TRIGGER_RX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_RXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Trigger TX PDMA function.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Set TXPDMAEN bit of USPI_PDMACTL register to enable TX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define USPI_TRIGGER_TX_PDMA(uspi) ((uspi)->PDMACTL |= USPI_PDMACTL_TXPDMAEN_Msk|USPI_PDMACTL_PDMAEN_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable RX PDMA transfer.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear RXPDMAEN bit of USPI_PDMACTL register to disable RX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define USPI_DISABLE_RX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_RXPDMAEN_Msk )
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable TX PDMA transfer.
|
||||||
|
* @param[in] uspi The pointer of the specified USCI_SPI module.
|
||||||
|
* @return None.
|
||||||
|
* @details Clear TXPDMAEN bit of USPI_PDMACTL register to disable TX PDMA transfer function.
|
||||||
|
*/
|
||||||
|
#define USPI_DISABLE_TX_PDMA(uspi) ( (uspi)->PDMACTL &= ~USPI_PDMACTL_TXPDMAEN_Msk )
|
||||||
|
|
||||||
|
uint32_t USPI_Open(USPI_T *uspi, uint32_t u32MasterSlave, uint32_t u32SPIMode, uint32_t u32DataWidth, uint32_t u32BusClock);
|
||||||
|
void USPI_Close(USPI_T *uspi);
|
||||||
|
void USPI_ClearRxBuf(USPI_T *uspi);
|
||||||
|
void USPI_ClearTxBuf(USPI_T *uspi);
|
||||||
|
void USPI_DisableAutoSS(USPI_T *uspi);
|
||||||
|
void USPI_EnableAutoSS(USPI_T *uspi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
|
||||||
|
uint32_t USPI_SetBusClock(USPI_T *uspi, uint32_t u32BusClock);
|
||||||
|
uint32_t USPI_GetBusClock(USPI_T *uspi);
|
||||||
|
void USPI_EnableInt(USPI_T *uspi, uint32_t u32Mask);
|
||||||
|
void USPI_DisableInt(USPI_T *uspi, uint32_t u32Mask);
|
||||||
|
uint32_t USPI_GetIntFlag(USPI_T *uspi, uint32_t u32Mask);
|
||||||
|
void USPI_ClearIntFlag(USPI_T *uspi, uint32_t u32Mask);
|
||||||
|
uint32_t USPI_GetStatus(USPI_T *uspi, uint32_t u32Mask);
|
||||||
|
void USPI_EnableWakeup(USPI_T *uspi);
|
||||||
|
void USPI_DisableWakeup(USPI_T *uspi);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_SPI_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_SPI_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__USCI_SPI_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,561 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file usci_uart.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series USCI UART (UUART) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#include <stdio.h>
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_UART_Driver USCI_UART Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear USCI_UART specified interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||||
|
* Each bit corresponds to a interrupt source.
|
||||||
|
* This parameter decides which interrupt flags will be cleared. It could be the combination of:
|
||||||
|
* - \ref UUART_ABR_INT_MASK
|
||||||
|
* - \ref UUART_RLS_INT_MASK
|
||||||
|
* - \ref UUART_BUF_RXOV_INT_MASK
|
||||||
|
* - \ref UUART_TXST_INT_MASK
|
||||||
|
* - \ref UUART_TXEND_INT_MASK
|
||||||
|
* - \ref UUART_RXST_INT_MASK
|
||||||
|
* - \ref UUART_RXEND_INT_MASK
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to clear USCI_UART related interrupt flags specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
|
||||||
|
void UUART_ClearIntFlag(UUART_T* uuart , uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
|
||||||
|
if(u32Mask & UUART_ABR_INT_MASK) /* Clear Auto-baud Rate Interrupt */
|
||||||
|
uuart->PROTSTS = UUART_PROTSTS_ABRDETIF_Msk;
|
||||||
|
|
||||||
|
if(u32Mask & UUART_RLS_INT_MASK) /* Clear Receive Line Status Interrupt */
|
||||||
|
uuart->PROTSTS = (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk);
|
||||||
|
|
||||||
|
if(u32Mask & UUART_BUF_RXOV_INT_MASK) /* Clear Receive Buffer Over-run Error Interrupt */
|
||||||
|
uuart->BUFSTS = UUART_BUFSTS_RXOVIF_Msk;
|
||||||
|
|
||||||
|
if(u32Mask & UUART_TXST_INT_MASK) /* Clear Transmit Start Interrupt */
|
||||||
|
uuart->PROTSTS = UUART_PROTSTS_TXSTIF_Msk;
|
||||||
|
|
||||||
|
if(u32Mask & UUART_TXEND_INT_MASK) /* Clear Transmit End Interrupt */
|
||||||
|
uuart->PROTSTS = UUART_PROTSTS_TXENDIF_Msk;
|
||||||
|
|
||||||
|
if(u32Mask & UUART_RXST_INT_MASK) /* Clear Receive Start Interrupt */
|
||||||
|
uuart->PROTSTS = UUART_PROTSTS_RXSTIF_Msk;
|
||||||
|
|
||||||
|
if(u32Mask & UUART_RXEND_INT_MASK) /* Clear Receive End Interrupt */
|
||||||
|
uuart->PROTSTS = UUART_PROTSTS_RXENDIF_Msk;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get USCI_UART specified interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt sources.
|
||||||
|
* Each bit corresponds to a interrupt source.
|
||||||
|
* This parameter decides which interrupt flags will be read. It is combination of:
|
||||||
|
* - \ref UUART_ABR_INT_MASK
|
||||||
|
* - \ref UUART_RLS_INT_MASK
|
||||||
|
* - \ref UUART_BUF_RXOV_INT_MASK
|
||||||
|
* - \ref UUART_TXST_INT_MASK
|
||||||
|
* - \ref UUART_TXEND_INT_MASK
|
||||||
|
* - \ref UUART_RXST_INT_MASK
|
||||||
|
* - \ref UUART_RXEND_INT_MASK
|
||||||
|
*
|
||||||
|
* @return Interrupt flags of selected sources.
|
||||||
|
*
|
||||||
|
* @details The function is used to get USCI_UART related interrupt flags specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
|
||||||
|
uint32_t UUART_GetIntFlag(UUART_T* uuart , uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
uint32_t u32IntFlag = 0;
|
||||||
|
|
||||||
|
/* Check Auto-baud Rate Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_ABR_INT_MASK) && (uuart->PROTSTS & UUART_PROTSTS_ABRDETIF_Msk))
|
||||||
|
u32IntFlag |= UUART_ABR_INT_MASK;
|
||||||
|
|
||||||
|
/* Check Receive Line Status Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_RLS_INT_MASK) && (uuart->PROTSTS & (UUART_PROTSTS_BREAK_Msk | UUART_PROTSTS_FRMERR_Msk | UUART_PROTSTS_PARITYERR_Msk)))
|
||||||
|
u32IntFlag |= UUART_RLS_INT_MASK;
|
||||||
|
|
||||||
|
/* Check Receive Buffer Over-run Error Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_BUF_RXOV_INT_MASK) && (uuart->BUFSTS & UUART_BUFSTS_RXOVIF_Msk))
|
||||||
|
u32IntFlag |= UUART_BUF_RXOV_INT_MASK;
|
||||||
|
|
||||||
|
/* Check Transmit Start Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_TXST_INT_MASK) && (uuart->PROTSTS & UUART_PROTSTS_TXSTIF_Msk))
|
||||||
|
u32IntFlag |= UUART_TXST_INT_MASK;
|
||||||
|
|
||||||
|
/* Check Transmit End Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_TXEND_INT_MASK) && (uuart->PROTSTS & UUART_PROTSTS_TXENDIF_Msk))
|
||||||
|
u32IntFlag |= UUART_TXEND_INT_MASK;
|
||||||
|
|
||||||
|
/* Check Receive Start Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_RXST_INT_MASK) && (uuart->PROTSTS & UUART_PROTSTS_RXSTIF_Msk))
|
||||||
|
u32IntFlag |= UUART_RXST_INT_MASK;
|
||||||
|
|
||||||
|
/* Check Receive End Interrupt Flag */
|
||||||
|
if((u32Mask & UUART_RXEND_INT_MASK) && (uuart->PROTSTS & UUART_PROTSTS_RXENDIF_Msk))
|
||||||
|
u32IntFlag |= UUART_RXEND_INT_MASK;
|
||||||
|
|
||||||
|
return u32IntFlag;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USCI_UART function mode
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable USCI_UART function mode.
|
||||||
|
*/
|
||||||
|
void UUART_Close(UUART_T* uuart)
|
||||||
|
{
|
||||||
|
uuart->CTL = 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable interrupt function.
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt enable bit.
|
||||||
|
* This parameter decides which interrupts will be disabled. It is combination of:
|
||||||
|
* - \ref UUART_ABR_INT_MASK
|
||||||
|
* - \ref UUART_RLS_INT_MASK
|
||||||
|
* - \ref UUART_BUF_RXOV_INT_MASK
|
||||||
|
* - \ref UUART_TXST_INT_MASK
|
||||||
|
* - \ref UUART_TXEND_INT_MASK
|
||||||
|
* - \ref UUART_RXST_INT_MASK
|
||||||
|
* - \ref UUART_RXEND_INT_MASK
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disabled USCI_UART related interrupts specified by u32Mask parameter.
|
||||||
|
*/
|
||||||
|
void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
|
||||||
|
/* Disable Auto-baud rate interrupt flag */
|
||||||
|
if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
|
||||||
|
uuart->PROTIEN &= ~UUART_PROTIEN_ABRIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable receive line status interrupt flag */
|
||||||
|
if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
|
||||||
|
uuart->PROTIEN &= ~UUART_PROTIEN_RLSIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable RX overrun interrupt flag */
|
||||||
|
if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
|
||||||
|
uuart->BUFCTL &= ~UUART_BUFCTL_RXOVIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable TX start interrupt flag */
|
||||||
|
if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
|
||||||
|
uuart->INTEN &= ~UUART_INTEN_TXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable TX end interrupt flag */
|
||||||
|
if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
|
||||||
|
uuart->INTEN &= ~UUART_INTEN_TXENDIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable RX start interrupt flag */
|
||||||
|
if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
|
||||||
|
uuart->INTEN &= ~UUART_INTEN_RXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Disable RX end interrupt flag */
|
||||||
|
if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
|
||||||
|
uuart->INTEN &= ~UUART_INTEN_RXENDIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable interrupt function.
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32Mask The combination of all related interrupt enable bits.
|
||||||
|
* Each bit corresponds to a interrupt enable bit.
|
||||||
|
* This parameter decides which interrupts will be enabled. It is combination of:
|
||||||
|
* - \ref UUART_ABR_INT_MASK
|
||||||
|
* - \ref UUART_RLS_INT_MASK
|
||||||
|
* - \ref UUART_BUF_RXOV_INT_MASK
|
||||||
|
* - \ref UUART_TXST_INT_MASK
|
||||||
|
* - \ref UUART_TXEND_INT_MASK
|
||||||
|
* - \ref UUART_RXST_INT_MASK
|
||||||
|
* - \ref UUART_RXEND_INT_MASK
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to enable USCI_UART related interrupts specified by u32Mask parameter..
|
||||||
|
*/
|
||||||
|
void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask)
|
||||||
|
{
|
||||||
|
/* Enable Auto-baud rate interrupt flag */
|
||||||
|
if((u32Mask & UUART_ABR_INT_MASK) == UUART_ABR_INT_MASK)
|
||||||
|
uuart->PROTIEN |= UUART_PROTIEN_ABRIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable receive line status interrupt flag */
|
||||||
|
if((u32Mask & UUART_RLS_INT_MASK) == UUART_RLS_INT_MASK)
|
||||||
|
uuart->PROTIEN |= UUART_PROTIEN_RLSIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable RX overrun interrupt flag */
|
||||||
|
if((u32Mask & UUART_BUF_RXOV_INT_MASK) == UUART_BUF_RXOV_INT_MASK)
|
||||||
|
uuart->BUFCTL |= UUART_BUFCTL_RXOVIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable TX start interrupt flag */
|
||||||
|
if((u32Mask & UUART_TXST_INT_MASK) == UUART_TXST_INT_MASK)
|
||||||
|
uuart->INTEN |= UUART_INTEN_TXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable TX end interrupt flag */
|
||||||
|
if((u32Mask & UUART_TXEND_INT_MASK) == UUART_TXEND_INT_MASK)
|
||||||
|
uuart->INTEN |= UUART_INTEN_TXENDIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable RX start interrupt flag */
|
||||||
|
if((u32Mask & UUART_RXST_INT_MASK) == UUART_RXST_INT_MASK)
|
||||||
|
uuart->INTEN |= UUART_INTEN_RXSTIEN_Msk;
|
||||||
|
|
||||||
|
/* Enable RX end interrupt flag */
|
||||||
|
if((u32Mask & UUART_RXEND_INT_MASK) == UUART_RXEND_INT_MASK)
|
||||||
|
uuart->INTEN |= UUART_INTEN_RXENDIEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Open and set USCI_UART function
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32baudrate The baud rate of USCI_UART module.
|
||||||
|
*
|
||||||
|
* @return Real baud rate of USCI_UART module.
|
||||||
|
*
|
||||||
|
* @details This function use to enable USCI_UART function and set baud-rate.
|
||||||
|
*/
|
||||||
|
uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate)
|
||||||
|
{
|
||||||
|
uint32_t u32PCLKFreq, u32PDSClk, u32PDSCnt, u32DSCnt, u32ClkDiv;
|
||||||
|
uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
|
||||||
|
|
||||||
|
/* Get PCLK frequency */
|
||||||
|
if( (uuart == UUART0) || (uuart == UUART0_NS) )
|
||||||
|
u32PDSClk = u32PCLKFreq = CLK_GetPCLK0Freq();
|
||||||
|
else
|
||||||
|
u32PDSClk = u32PCLKFreq = CLK_GetPCLK1Freq();
|
||||||
|
|
||||||
|
for(u32PDSCnt = 1; u32PDSCnt <= 0x04; u32PDSCnt++) //PDSCNT could be 0~0x3
|
||||||
|
{
|
||||||
|
u32PDSClk = u32PCLKFreq / u32PDSCnt;
|
||||||
|
|
||||||
|
if(u32PDSClk > (36000000))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Find best solution */
|
||||||
|
u32Min = (uint32_t) - 1;
|
||||||
|
u32MinDSCnt = 0;
|
||||||
|
u32MinClkDiv = 0;
|
||||||
|
for(u32DSCnt = 6; u32DSCnt <= 0x10; u32DSCnt++) //DSCNT could be 0x5~0xF
|
||||||
|
{
|
||||||
|
for(u32ClkDiv = 1; u32ClkDiv <= 0x400; u32ClkDiv++) //CLKDIV could be 0~0x3FF
|
||||||
|
{
|
||||||
|
|
||||||
|
u32Tmp = u32PDSClk / u32DSCnt / u32ClkDiv;
|
||||||
|
|
||||||
|
u32Tmp2 = (u32Tmp > u32baudrate) ? u32Tmp - u32baudrate : u32baudrate - u32Tmp;
|
||||||
|
|
||||||
|
if(u32Tmp2 < u32Min)
|
||||||
|
{
|
||||||
|
u32Min = u32Tmp2;
|
||||||
|
u32MinDSCnt = u32DSCnt;
|
||||||
|
u32MinClkDiv = u32ClkDiv;
|
||||||
|
|
||||||
|
/* Break when get good results */
|
||||||
|
if(u32Min == 0)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Enable USCI_UART protocol */
|
||||||
|
uuart->CTL &= ~UUART_CTL_FUNMODE_Msk;
|
||||||
|
uuart->CTL = 2 << UUART_CTL_FUNMODE_Pos;
|
||||||
|
|
||||||
|
/* Set USCI_UART line configuration */
|
||||||
|
uuart->LINECTL = UUART_WORD_LEN_8 | UUART_LINECTL_LSB_Msk;
|
||||||
|
uuart->DATIN0 = (2 << UUART_DATIN0_EDGEDET_Pos); //Set falling edge detection
|
||||||
|
|
||||||
|
/* Set USCI_UART baud rate */
|
||||||
|
uuart->BRGEN = ((u32MinClkDiv - 1) << UUART_BRGEN_CLKDIV_Pos) |
|
||||||
|
((u32MinDSCnt - 1) << UUART_BRGEN_DSCNT_Pos) |
|
||||||
|
((u32PDSCnt - 1) << UUART_BRGEN_PDSCNT_Pos);
|
||||||
|
|
||||||
|
uuart->PROTCTL |= UUART_PROTCTL_PROTEN_Msk;
|
||||||
|
|
||||||
|
return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read USCI_UART data
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] pu8RxBuf The buffer to receive the data of receive buffer.
|
||||||
|
* @param[in] u32ReadBytes The read bytes number of data.
|
||||||
|
*
|
||||||
|
* @return Receive byte count
|
||||||
|
*
|
||||||
|
* @details The function is used to read Rx data from RX buffer and the data will be stored in pu8RxBuf.
|
||||||
|
*/
|
||||||
|
uint32_t UUART_Read(UUART_T* uuart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes)
|
||||||
|
{
|
||||||
|
uint32_t u32Count, u32delayno;
|
||||||
|
|
||||||
|
for(u32Count = 0; u32Count < u32ReadBytes; u32Count++)
|
||||||
|
{
|
||||||
|
u32delayno = 0;
|
||||||
|
|
||||||
|
while(uuart->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) /* Check RX empty => failed */
|
||||||
|
{
|
||||||
|
u32delayno++;
|
||||||
|
if(u32delayno >= 0x40000000)
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
pu8RxBuf[u32Count] = uuart->RXDAT; /* Get Data from USCI RX */
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Count;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Set USCI_UART line configuration
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32baudrate The register value of baud rate of USCI_UART module.
|
||||||
|
* If u32baudrate = 0, USCI_UART baud rate will not change.
|
||||||
|
* @param[in] u32data_width The data length of USCI_UART module.
|
||||||
|
* - \ref UUART_WORD_LEN_6
|
||||||
|
* - \ref UUART_WORD_LEN_7
|
||||||
|
* - \ref UUART_WORD_LEN_8
|
||||||
|
* - \ref UUART_WORD_LEN_9
|
||||||
|
* @param[in] u32parity The parity setting (none/odd/even) of USCI_UART module.
|
||||||
|
* - \ref UUART_PARITY_NONE
|
||||||
|
* - \ref UUART_PARITY_ODD
|
||||||
|
* - \ref UUART_PARITY_EVEN
|
||||||
|
* @param[in] u32stop_bits The stop bit length (1/2 bit) of USCI_UART module.
|
||||||
|
* - \ref UUART_STOP_BIT_1
|
||||||
|
* - \ref UUART_STOP_BIT_2
|
||||||
|
*
|
||||||
|
* @return Real baud rate of USCI_UART module.
|
||||||
|
*
|
||||||
|
* @details This function use to config USCI_UART line setting.
|
||||||
|
*/
|
||||||
|
uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits)
|
||||||
|
{
|
||||||
|
uint32_t u32PCLKFreq, u32PDSClk, u32PDSCnt, u32DSCnt, u32ClkDiv;
|
||||||
|
uint32_t u32Tmp, u32Tmp2, u32Min, u32MinClkDiv, u32MinDSCnt;
|
||||||
|
|
||||||
|
/* Get PCLK frequency */
|
||||||
|
if(uuart == UUART0)
|
||||||
|
u32PDSClk = u32PCLKFreq = CLK_GetPCLK0Freq();
|
||||||
|
else
|
||||||
|
u32PDSClk = u32PCLKFreq = CLK_GetPCLK1Freq();
|
||||||
|
|
||||||
|
if(u32baudrate != 0)
|
||||||
|
{
|
||||||
|
for(u32PDSCnt = 1; u32PDSCnt <= 0x04; u32PDSCnt++) //PDSCNT could be 0~0x3
|
||||||
|
{
|
||||||
|
u32PDSClk = u32PCLKFreq / u32PDSCnt;
|
||||||
|
|
||||||
|
if(u32PDSClk > (36000000))
|
||||||
|
continue;
|
||||||
|
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Find best solution */
|
||||||
|
u32Min = (uint32_t) - 1;
|
||||||
|
u32MinDSCnt = 0;
|
||||||
|
u32MinClkDiv = 0;
|
||||||
|
for(u32DSCnt = 6; u32DSCnt <= 0x10; u32DSCnt++) //DSCNT could be 0x5~0xF
|
||||||
|
{
|
||||||
|
for(u32ClkDiv = 1; u32ClkDiv <= 0x400; u32ClkDiv++) //CLKDIV could be 0~0x3FF
|
||||||
|
{
|
||||||
|
u32Tmp = u32PDSClk / u32DSCnt / u32ClkDiv;
|
||||||
|
|
||||||
|
u32Tmp2 = (u32Tmp > u32baudrate) ? u32Tmp - u32baudrate : u32baudrate - u32Tmp;
|
||||||
|
|
||||||
|
if(u32Tmp2 < u32Min)
|
||||||
|
{
|
||||||
|
u32Min = u32Tmp2;
|
||||||
|
u32MinDSCnt = u32DSCnt;
|
||||||
|
u32MinClkDiv = u32ClkDiv;
|
||||||
|
|
||||||
|
/* Break when get good results */
|
||||||
|
if(u32Min == 0)
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set USCI_UART baud rate */
|
||||||
|
uuart->BRGEN = ((u32MinClkDiv - 1) << UUART_BRGEN_CLKDIV_Pos) |
|
||||||
|
((u32MinDSCnt - 1) << UUART_BRGEN_DSCNT_Pos) |
|
||||||
|
((u32PDSCnt - 1) << UUART_BRGEN_PDSCNT_Pos);
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
u32PDSCnt = ((uuart->BRGEN & UUART_BRGEN_PDSCNT_Msk) >> UUART_BRGEN_PDSCNT_Pos) + 1;
|
||||||
|
u32MinDSCnt = ((uuart->BRGEN & UUART_BRGEN_DSCNT_Msk) >> UUART_BRGEN_DSCNT_Pos) + 1;
|
||||||
|
u32MinClkDiv = ((uuart->BRGEN & UUART_BRGEN_CLKDIV_Msk) >> UUART_BRGEN_CLKDIV_Pos) + 1;
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Set USCI_UART line configuration */
|
||||||
|
uuart->LINECTL = (uuart->LINECTL & ~UUART_LINECTL_DWIDTH_Msk) | u32data_width;
|
||||||
|
uuart->PROTCTL = (uuart->PROTCTL & ~(UUART_PROTCTL_STICKEN_Msk | UUART_PROTCTL_EVENPARITY_Msk |
|
||||||
|
UUART_PROTCTL_PARITYEN_Msk)) | u32parity;
|
||||||
|
uuart->PROTCTL = (uuart->PROTCTL & ~UUART_PROTCTL_STOPB_Msk) | u32stop_bits;
|
||||||
|
|
||||||
|
return (u32PCLKFreq / u32PDSCnt / u32MinDSCnt / u32MinClkDiv);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write USCI_UART data
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] pu8TxBuf The buffer to send the data to USCI transmission buffer.
|
||||||
|
* @param[out] u32WriteBytes The byte number of data.
|
||||||
|
*
|
||||||
|
* @return Transfer byte count
|
||||||
|
*
|
||||||
|
* @details The function is to write data into TX buffer to transmit data by USCI_UART.
|
||||||
|
*/
|
||||||
|
uint32_t UUART_Write(UUART_T* uuart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes)
|
||||||
|
{
|
||||||
|
uint32_t u32Count, u32delayno;
|
||||||
|
|
||||||
|
for(u32Count = 0; u32Count != u32WriteBytes; u32Count++)
|
||||||
|
{
|
||||||
|
u32delayno = 0;
|
||||||
|
while((uuart->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) == 0) /* Wait Tx empty */
|
||||||
|
{
|
||||||
|
u32delayno++;
|
||||||
|
if(u32delayno >= 0x40000000)
|
||||||
|
return FALSE;
|
||||||
|
}
|
||||||
|
uuart->TXDAT = pu8TxBuf[u32Count]; /* Send USCI_UART Data to buffer */
|
||||||
|
}
|
||||||
|
|
||||||
|
return u32Count;
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USCI_UART Wake-up Function
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
* @param[in] u32WakeupMode The wakeup mode of USCI_UART module.
|
||||||
|
* - \ref UUART_PROTCTL_DATWKEN_Msk : Data wake-up Mode
|
||||||
|
* - \ref UUART_PROTCTL_CTSWKEN_Msk : nCTS wake-up Mode
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to enable Wake-up function of USCI_UART.
|
||||||
|
*/
|
||||||
|
void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode)
|
||||||
|
{
|
||||||
|
uuart->PROTCTL |= u32WakeupMode;
|
||||||
|
uuart->WKCTL |= UUART_WKCTL_WKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USCI_UART Wake-up Function
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable Wake-up function of USCI_UART.
|
||||||
|
*/
|
||||||
|
void UUART_DisableWakeup(UUART_T* uuart)
|
||||||
|
{
|
||||||
|
uuart->PROTCTL &= ~(UUART_PROTCTL_DATWKEN_Msk | UUART_PROTCTL_CTSWKEN_Msk);
|
||||||
|
uuart->WKCTL &= ~UUART_WKCTL_WKEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable USCI_UART auto flow control
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to enable USCI_UART auto flow control.
|
||||||
|
*/
|
||||||
|
void UUART_EnableFlowCtrl(UUART_T* uuart)
|
||||||
|
{
|
||||||
|
/* Set RTS signal is low level active */
|
||||||
|
uuart->LINECTL &= ~UUART_LINECTL_CTLOINV_Msk;
|
||||||
|
|
||||||
|
/* Set CTS signal is low level active */
|
||||||
|
uuart->CTLIN0 &= ~UUART_CTLIN0_ININV_Msk;
|
||||||
|
|
||||||
|
/* Enable CTS and RTS auto flow control function */
|
||||||
|
uuart->PROTCTL |= UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable USCI_UART auto flow control
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function is used to disable USCI_UART auto flow control.
|
||||||
|
*/
|
||||||
|
void UUART_DisableFlowCtrl(UUART_T* uuart)
|
||||||
|
{
|
||||||
|
/* Disable CTS and RTS auto flow control function */
|
||||||
|
uuart->PROTCTL &= ~(UUART_PROTCTL_RTSAUTOEN_Msk | UUART_PROTCTL_CTSAUTOEN_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_UART_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,417 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file usci_uart.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief M2351 series USCI UART (UUART) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __USCI_UART_H__
|
||||||
|
#define __USCI_UART_H__
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_UART_Driver USCI_UART Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup USCI_UART_EXPORTED_CONSTANTS USCI_UART Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UUART_LINECTL constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UUART_WORD_LEN_6 (6 << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 6 bits */
|
||||||
|
#define UUART_WORD_LEN_7 (7 << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 7 bits */
|
||||||
|
#define UUART_WORD_LEN_8 (8 << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 8 bits */
|
||||||
|
#define UUART_WORD_LEN_9 (9 << UUART_LINECTL_DWIDTH_Pos) /*!< UUART_LINECTL setting to set UART word length to 9 bits */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* UUART_PROTCTL constants definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UUART_PARITY_NONE (0x0 << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as no parity */
|
||||||
|
#define UUART_PARITY_ODD (0x1 << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as odd parity */
|
||||||
|
#define UUART_PARITY_EVEN (0x3 << UUART_PROTCTL_PARITYEN_Pos) /*!< UUART_PROTCTL setting to set UART as even parity */
|
||||||
|
|
||||||
|
#define UUART_STOP_BIT_1 (0x0) /*!< UUART_PROTCTL setting for one stop bit */
|
||||||
|
#define UUART_STOP_BIT_2 (0x1) /*!< UUART_PROTCTL setting for two stop bit */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* USCI UART interrupt mask definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define UUART_ABR_INT_MASK (0x002) /*!< Auto-baud rate interrupt mask */
|
||||||
|
#define UUART_RLS_INT_MASK (0x004) /*!< Receive line status interrupt mask */
|
||||||
|
#define UUART_BUF_RXOV_INT_MASK (0x008) /*!< Buffer RX overrun interrupt mask */
|
||||||
|
#define UUART_TXST_INT_MASK (0x010) /*!< TX start interrupt mask */
|
||||||
|
#define UUART_TXEND_INT_MASK (0x020) /*!< Tx end interrupt mask */
|
||||||
|
#define UUART_RXST_INT_MASK (0x040) /*!< RX start interrupt mask */
|
||||||
|
#define UUART_RXEND_INT_MASK (0x080) /*!< RX end interrupt mask */
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_UART_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup USCI_UART_EXPORTED_FUNCTIONS USCI_UART Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Write USCI_UART data
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u8Data Data byte to transmit.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro write Data to Tx data register.
|
||||||
|
*/
|
||||||
|
#define UUART_WRITE(uuart, u8Data) ((uuart)->TXDAT = (u8Data))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Read USCI_UART data
|
||||||
|
*
|
||||||
|
* @param[in] usci The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @return The oldest data byte in RX buffer.
|
||||||
|
*
|
||||||
|
* @details This macro read Rx data register.
|
||||||
|
*/
|
||||||
|
#define UUART_READ(uuart) ((uuart)->RXDAT)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Tx empty
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Tx buffer is not empty
|
||||||
|
* @retval >=1 Tx buffer is empty
|
||||||
|
*
|
||||||
|
* @details This macro get Transmitter buffer empty register value.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_TX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Rx empty
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Rx buffer is not empty
|
||||||
|
* @retval >=1 Rx buffer is empty
|
||||||
|
*
|
||||||
|
* @details This macro get Receiver buffer empty register value.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_RX_EMPTY(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check specified usci_uart port transmission is over.
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Tx transmission is not over
|
||||||
|
* @retval 1 Tx transmission is over
|
||||||
|
*
|
||||||
|
* @details This macro return Transmitter Empty Flag register bit value. \n
|
||||||
|
* It indicates if specified usci_uart port transmission is over nor not.
|
||||||
|
*/
|
||||||
|
#define UUART_IS_TX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check specified usci_uart port receiver is empty.
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Rx receiver is not empty
|
||||||
|
* @retval 1 Rx receiver is empty
|
||||||
|
*
|
||||||
|
* @details This macro return Receive Empty Flag register bit value. \n
|
||||||
|
* It indicates if specified usci_uart port receiver is empty nor not.
|
||||||
|
*/
|
||||||
|
#define UUART_IS_RX_EMPTY(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXEMPTY_Msk) >> UUART_BUFSTS_RXEMPTY_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Wait specified usci_uart port transmission is over
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro wait specified usci_uart port transmission is over.
|
||||||
|
*/
|
||||||
|
#define UUART_WAIT_TX_EMPTY(uuart) while(!((((uuart)->BUFSTS) & UUART_BUFSTS_TXEMPTY_Msk) >> UUART_BUFSTS_TXEMPTY_Pos))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check TX buffer is full or not
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 1 TX buffer is full
|
||||||
|
* @retval 0 TX buffer is not full
|
||||||
|
*
|
||||||
|
* @details This macro check TX buffer is full or not.
|
||||||
|
*/
|
||||||
|
#define UUART_IS_TX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)>>UUART_BUFSTS_TXFULL_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Check RX buffer is full or not
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 1 RX buffer is full
|
||||||
|
* @retval 0 RX buffer is not full
|
||||||
|
*
|
||||||
|
* @details This macro check RX buffer is full or not.
|
||||||
|
*/
|
||||||
|
#define UUART_IS_RX_FULL(uuart) (((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)>>UUART_BUFSTS_RXFULL_Pos)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Tx full register value
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Tx buffer is not full.
|
||||||
|
* @retval >=1 Tx buffer is full.
|
||||||
|
*
|
||||||
|
* @details This macro get Tx full register value.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_TX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_TXFULL_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get Rx full register value
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Rx buffer is not full.
|
||||||
|
* @retval >=1 Rx buffer is full.
|
||||||
|
*
|
||||||
|
* @details This macro get Rx full register value.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_RX_FULL(uuart) ((uuart)->BUFSTS & UUART_BUFSTS_RXFULL_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified USCI_UART protocol interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntSel Interrupt type select
|
||||||
|
* - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
|
||||||
|
* - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro enable specified USCI_UART protocol interrupt.
|
||||||
|
*/
|
||||||
|
#define UUART_ENABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN |= (u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified USCI_UART protocol interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntSel Interrupt type select
|
||||||
|
* - \ref UUART_PROTIEN_RLSIEN_Msk : Rx Line status interrupt
|
||||||
|
* - \ref UUART_PROTIEN_ABRIEN_Msk : Auto-baud rate interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro disable specified USCI_UART protocol interrupt.
|
||||||
|
*/
|
||||||
|
#define UUART_DISABLE_PROT_INT(uuart, u32IntSel) ((uuart)->PROTIEN &= ~(u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified USCI_UART buffer interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntSel Interrupt type select
|
||||||
|
* - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro enable specified USCI_UART buffer interrupt.
|
||||||
|
*/
|
||||||
|
#define UUART_ENABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL |= (u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified USCI_UART buffer interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntSel Interrupt type select
|
||||||
|
* - \ref UUART_BUFCTL_RXOVIEN_Msk : Receive buffer overrun error interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro disable specified USCI_UART buffer interrupt.
|
||||||
|
*/
|
||||||
|
#define UUART_DISABLE_BUF_INT(uuart, u32IntSel) ((uuart)->BUFCTL &= ~ (u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable specified USCI_UART transfer interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntSel Interrupt type select
|
||||||
|
* - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
|
||||||
|
* - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
|
||||||
|
* - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
|
||||||
|
* - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro enable specified USCI_UART transfer interrupt.
|
||||||
|
*/
|
||||||
|
#define UUART_ENABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN |= (u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable specified USCI_UART transfer interrupt
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntSel Interrupt type select
|
||||||
|
* - \ref UUART_INTEN_RXENDIEN_Msk : Receive end interrupt
|
||||||
|
* - \ref UUART_INTEN_RXSTIEN_Msk : Receive start interrupt
|
||||||
|
* - \ref UUART_INTEN_TXENDIEN_Msk : Transmit end interrupt
|
||||||
|
* - \ref UUART_INTEN_TXSTIEN_Msk : Transmit start interrupt
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro disable specified USCI_UART transfer interrupt.
|
||||||
|
*/
|
||||||
|
#define UUART_DISABLE_TRANS_INT(uuart, u32IntSel) ((uuart)->INTEN &= ~(u32IntSel))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get protocol interrupt flag/status
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @return The interrupt flag/status of protocol status register.
|
||||||
|
*
|
||||||
|
* @details This macro get protocol status register value.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_PROT_STATUS(uuart) ((uuart)->PROTSTS)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified protocol interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||||
|
* - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator
|
||||||
|
* - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag
|
||||||
|
* - \ref UUART_PROTSTS_BRKDETIF_Msk : LIN Break Detected Interrupt Flag
|
||||||
|
* - \ref UUART_PROTSTS_BREAK_Msk : Break Flag
|
||||||
|
* - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag
|
||||||
|
* - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag
|
||||||
|
* - \ref UUART_PROTSTS_RXENDIF_Msk : Receive End Interrupt Flag
|
||||||
|
* - \ref UUART_PROTSTS_RXSTIF_Msk : Receive Start Interrupt Flag
|
||||||
|
* - \ref UUART_PROTSTS_TXENDIF_Msk : Transmit End Interrupt Flag
|
||||||
|
* - \ref UUART_PROTSTS_TXSTIF_Msk : Transmit Start Interrupt Flag
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clear specified protocol interrupt flag.
|
||||||
|
*/
|
||||||
|
#define UUART_CLR_PROT_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->PROTSTS = (u32IntTypeFlag))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get transmit/receive buffer interrupt flag/status
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @return The interrupt flag/status of buffer status register.
|
||||||
|
*
|
||||||
|
* @details This macro get buffer status register value.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_BUF_STATUS(uuart) ((uuart)->BUFSTS)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear specified buffer interrupt flag
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be
|
||||||
|
* - \ref UUART_BUFSTS_RXOVIF_Msk : Receive Buffer Over-run Error Interrupt Indicator
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clear specified buffer interrupt flag.
|
||||||
|
*/
|
||||||
|
#define UUART_CLR_BUF_INT_FLAG(uuart,u32IntTypeFlag) ((uuart)->BUFSTS = (u32IntTypeFlag))
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get wakeup flag
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @retval 0 Chip did not wake up from power-down mode.
|
||||||
|
* @retval 1 Chip waked up from power-down mode.
|
||||||
|
*
|
||||||
|
* @details This macro get wakeup flag.
|
||||||
|
*/
|
||||||
|
#define UUART_GET_WAKEUP_FLAG(uuart) ((uuart)->WKSTS & UUART_WKSTS_WKF_Msk ? 1: 0 )
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear wakeup flag
|
||||||
|
*
|
||||||
|
* @param[in] uuart The pointer of the specified USCI_UART module
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clear wakeup flag.
|
||||||
|
*/
|
||||||
|
#define UUART_CLR_WAKEUP_FLAG(uuart) ((uuart)->WKSTS = UUART_WKSTS_WKF_Msk)
|
||||||
|
|
||||||
|
|
||||||
|
void UUART_ClearIntFlag(UUART_T* uuart, uint32_t u32Mask);
|
||||||
|
uint32_t UUART_GetIntFlag(UUART_T* uuart, uint32_t u32Mask);
|
||||||
|
void UUART_Close(UUART_T* uuart);
|
||||||
|
void UUART_DisableInt(UUART_T* uuart, uint32_t u32Mask);
|
||||||
|
void UUART_EnableInt(UUART_T* uuart, uint32_t u32Mask);
|
||||||
|
uint32_t UUART_Open(UUART_T* uuart, uint32_t u32baudrate);
|
||||||
|
uint32_t UUART_Read(UUART_T* uuart, uint8_t *pu8RxBuf, uint32_t u32ReadBytes);
|
||||||
|
uint32_t UUART_SetLine_Config(UUART_T* uuart, uint32_t u32baudrate, uint32_t u32data_width, uint32_t u32parity, uint32_t u32stop_bits);
|
||||||
|
uint32_t UUART_Write(UUART_T* uuart, uint8_t *pu8TxBuf, uint32_t u32WriteBytes);
|
||||||
|
void UUART_EnableWakeup(UUART_T* uuart, uint32_t u32WakeupMode);
|
||||||
|
void UUART_DisableWakeup(UUART_T* uuart);
|
||||||
|
void UUART_EnableFlowCtrl(UUART_T* uuart);
|
||||||
|
void UUART_DisableFlowCtrl(UUART_T* uuart);
|
||||||
|
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_UART_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group USCI_UART_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__USCI_UART_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,69 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file wdt.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Watchdog Timer(WDT) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WDT_Driver WDT Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Initialize WDT and start counting
|
||||||
|
*
|
||||||
|
* @param[in] u32TimeoutInterval Time-out interval period of WDT module. Valid values are:
|
||||||
|
* - \ref WDT_TIMEOUT_2POW4
|
||||||
|
* - \ref WDT_TIMEOUT_2POW6
|
||||||
|
* - \ref WDT_TIMEOUT_2POW8
|
||||||
|
* - \ref WDT_TIMEOUT_2POW10
|
||||||
|
* - \ref WDT_TIMEOUT_2POW12
|
||||||
|
* - \ref WDT_TIMEOUT_2POW14
|
||||||
|
* - \ref WDT_TIMEOUT_2POW16
|
||||||
|
* - \ref WDT_TIMEOUT_2POW18
|
||||||
|
* @param[in] u32ResetDelay Configure WDT time-out reset delay period. Valid values are:
|
||||||
|
* - \ref WDT_RESET_DELAY_1026CLK
|
||||||
|
* - \ref WDT_RESET_DELAY_130CLK
|
||||||
|
* - \ref WDT_RESET_DELAY_18CLK
|
||||||
|
* - \ref WDT_RESET_DELAY_3CLK
|
||||||
|
* @param[in] u32EnableReset Enable WDT time-out reset system function. Valid values are TRUE and FALSE.
|
||||||
|
* @param[in] u32EnableWakeup Enable WDT time-out wake-up system function. Valid values are TRUE and FALSE.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function makes WDT module start counting with different time-out interval, reset delay period and choose to \n
|
||||||
|
* enable or disable WDT time-out reset system or wake-up system.
|
||||||
|
* @note Please make sure that Register Write-Protection Function has been disabled before using this function.
|
||||||
|
*/
|
||||||
|
void WDT_Open(uint32_t u32TimeoutInterval,
|
||||||
|
uint32_t u32ResetDelay,
|
||||||
|
uint32_t u32EnableReset,
|
||||||
|
uint32_t u32EnableWakeup)
|
||||||
|
{
|
||||||
|
WDT->ALTCTL = u32ResetDelay;
|
||||||
|
|
||||||
|
WDT->CTL = u32TimeoutInterval | WDT_CTL_WDTEN_Msk |
|
||||||
|
(u32EnableReset << WDT_CTL_RSTEN_Pos) |
|
||||||
|
(u32EnableWakeup << WDT_CTL_WKEN_Pos);
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WDT_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,203 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file wdt.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Watchdog Timer(WDT) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __WDT_H__
|
||||||
|
#define __WDT_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WDT_Driver WDT Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WDT_EXPORTED_CONSTANTS WDT Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* WDT Time-out Interval Period Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define WDT_TIMEOUT_2POW4 (0UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^4 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW6 (1UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^6 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW8 (2UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^8 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW10 (3UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^10 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW12 (4UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^12 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW14 (5UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^14 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW16 (6UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^16 * WDT clocks */
|
||||||
|
#define WDT_TIMEOUT_2POW18 (7UL << WDT_CTL_TOUTSEL_Pos) /*!< Setting WDT time-out interval to 2^18 * WDT clocks */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* WDT Reset Delay Period Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define WDT_RESET_DELAY_1026CLK (0UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 1026 * WDT clocks */
|
||||||
|
#define WDT_RESET_DELAY_130CLK (1UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 130 * WDT clocks */
|
||||||
|
#define WDT_RESET_DELAY_18CLK (2UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 18 * WDT clocks */
|
||||||
|
#define WDT_RESET_DELAY_3CLK (3UL << WDT_ALTCTL_RSTDSEL_Pos) /*!< Setting WDT reset delay period to 3 * WDT clocks */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* WDT Free Reset Counter Keyword Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define WDT_RESET_COUNTER_KEYWORD (0x00005AA5) /*!< Fill this value to WDT_RSTCNT register to free reset WDT counter */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WDT_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup WDT_EXPORTED_FUNCTIONS WDT Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear WDT Reset System Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears WDT time-out reset system flag.
|
||||||
|
*/
|
||||||
|
#define WDT_CLEAR_RESET_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_RSTF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear WDT Time-out Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears WDT time-out interrupt flag.
|
||||||
|
*/
|
||||||
|
#define WDT_CLEAR_TIMEOUT_INT_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_WKF_Msk)) | WDT_CTL_IF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear WDT Wake-up Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro clears WDT time-out wake-up system flag.
|
||||||
|
*/
|
||||||
|
#define WDT_CLEAR_TIMEOUT_WAKEUP_FLAG() (WDT->CTL = (WDT->CTL & ~(WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk)) | WDT_CTL_WKF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get WDT Time-out Reset Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 WDT time-out reset system did not occur
|
||||||
|
* @retval 1 WDT time-out reset system occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates system has been reset by WDT time-out reset or not.
|
||||||
|
*/
|
||||||
|
#define WDT_GET_RESET_FLAG() ((WDT->CTL & WDT_CTL_RSTF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get WDT Time-out Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 WDT time-out interrupt did not occur
|
||||||
|
* @retval 1 WDT time-out interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro indicates WDT time-out interrupt occurred or not.
|
||||||
|
*/
|
||||||
|
#define WDT_GET_TIMEOUT_INT_FLAG() ((WDT->CTL & WDT_CTL_IF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get WDT Time-out Wake-up Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 WDT time-out interrupt does not cause CPU wake-up
|
||||||
|
* @retval 1 WDT time-out interrupt event cause CPU wake-up
|
||||||
|
*
|
||||||
|
* @details This macro indicates WDT time-out interrupt event has waked up system or not.
|
||||||
|
*/
|
||||||
|
#define WDT_GET_TIMEOUT_WAKEUP_FLAG() ((WDT->CTL & WDT_CTL_WKF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reset WDT Counter
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to reset the internal 18-bit WDT up counter value.
|
||||||
|
* @note If WDT is activated and time-out reset system function is enabled also, user should \n
|
||||||
|
* reset the 18-bit WDT up counter value to avoid generate WDT time-out reset signal to \n
|
||||||
|
* reset system before the WDT time-out reset delay period expires.
|
||||||
|
*/
|
||||||
|
#define WDT_RESET_COUNTER() (WDT->RSTCNT = WDT_RESET_COUNTER_KEYWORD)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Stop WDT Counting
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will stop WDT counting and disable WDT module.
|
||||||
|
*/
|
||||||
|
static __INLINE void WDT_Close(void)
|
||||||
|
{
|
||||||
|
WDT->CTL = 0;
|
||||||
|
while(WDT->CTL & WDT_CTL_SYNC_Msk); // Wait disable WDTEN bit completed, it needs 2 * WDT_CLK.
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Enable WDT Time-out Interrupt
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will enable the WDT time-out interrupt function.
|
||||||
|
*/
|
||||||
|
static __INLINE void WDT_EnableInt(void)
|
||||||
|
{
|
||||||
|
WDT->CTL |= WDT_CTL_INTEN_Msk;
|
||||||
|
while(WDT->CTL & WDT_CTL_SYNC_Msk); // Wait enable WDTEN bit completed, it needs 2 * WDT_CLK.
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Disable WDT Time-out Interrupt
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function will disable the WDT time-out interrupt function.
|
||||||
|
*/
|
||||||
|
static __INLINE void WDT_DisableInt(void)
|
||||||
|
{
|
||||||
|
// Do not touch another write 1 clear bits
|
||||||
|
WDT->CTL &= ~(WDT_CTL_INTEN_Msk | WDT_CTL_RSTF_Msk | WDT_CTL_IF_Msk | WDT_CTL_WKF_Msk);
|
||||||
|
}
|
||||||
|
|
||||||
|
void WDT_Open(uint32_t u32TimeoutInterval, uint32_t u32ResetDelay, uint32_t u32EnableReset, uint32_t u32EnableWakeup);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WDT_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WDT_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif //__WDT_H__
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,69 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file wwdt.c
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Window Watchdog Timer(WWDT) driver source file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDT_Driver WWDT Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Open WWDT function to start counting
|
||||||
|
*
|
||||||
|
* @param[in] u32PreScale Prescale period for the WWDT counter period. Valid values are:
|
||||||
|
* - \ref WWDT_PRESCALER_1
|
||||||
|
* - \ref WWDT_PRESCALER_2
|
||||||
|
* - \ref WWDT_PRESCALER_4
|
||||||
|
* - \ref WWDT_PRESCALER_8
|
||||||
|
* - \ref WWDT_PRESCALER_16
|
||||||
|
* - \ref WWDT_PRESCALER_32
|
||||||
|
* - \ref WWDT_PRESCALER_64
|
||||||
|
* - \ref WWDT_PRESCALER_128
|
||||||
|
* - \ref WWDT_PRESCALER_192
|
||||||
|
* - \ref WWDT_PRESCALER_256
|
||||||
|
* - \ref WWDT_PRESCALER_384
|
||||||
|
* - \ref WWDT_PRESCALER_512
|
||||||
|
* - \ref WWDT_PRESCALER_768
|
||||||
|
* - \ref WWDT_PRESCALER_1024
|
||||||
|
* - \ref WWDT_PRESCALER_1536
|
||||||
|
* - \ref WWDT_PRESCALER_2048
|
||||||
|
* @param[in] u32CmpValue Setting the window compared value. Valid values are between 0x0 to 0x3F.
|
||||||
|
* @param[in] u32EnableInt Enable WWDT interrupt function. Valid values are TRUE and FALSE.
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function make WWDT module start counting with different counter period and compared window value.
|
||||||
|
* @note Application can call this function only once after boot up.
|
||||||
|
*/
|
||||||
|
void WWDT_Open(uint32_t u32PreScale,
|
||||||
|
uint32_t u32CmpValue,
|
||||||
|
uint32_t u32EnableInt)
|
||||||
|
{
|
||||||
|
WWDT->CTL = u32PreScale |
|
||||||
|
(u32CmpValue << WWDT_CTL_CMPDAT_Pos) |
|
||||||
|
((u32EnableInt == TRUE) ? WWDT_CTL_INTEN_Msk : 0) |
|
||||||
|
WWDT_CTL_WWDTEN_Msk;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WWDT_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
||||||
|
|
@ -0,0 +1,146 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file wwdt.h
|
||||||
|
* @version V3.00
|
||||||
|
* @brief Window Watchdog Timet(WWDT) driver header file
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
#ifndef __WWDT_H__
|
||||||
|
#define __WWDT_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C"
|
||||||
|
{
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup Standard_Driver Standard Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDT_Driver WWDT Driver
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/** @addtogroup WWDT_EXPORTED_CONSTANTS WWDT Exported Constants
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* WWDT Prescale Period Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define WWDT_PRESCALER_1 (0 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_2 (1 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_4 (2 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 4 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_8 (3 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 8 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_16 (4 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 16 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_32 (5 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 32 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_64 (6 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 64 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_128 (7 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 128 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_192 (8 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 192 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_256 (9 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 256 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_384 (10 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 384 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_512 (11 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 512 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_768 (12 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 768 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_1024 (13 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1024 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_1536 (14 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 1536 * (64*WWDT_CLK) */
|
||||||
|
#define WWDT_PRESCALER_2048 (15 << WWDT_CTL_PSCSEL_Pos) /*!< Select max time-out period to 2048 * (64*WWDT_CLK) */
|
||||||
|
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* WWDT Reload Counter Keyword Constant Definitions */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#define WWDT_RELOAD_WORD (0x00005AA5) /*!< Fill this value to WWDT_RLDCNT register to reload WWDT counter */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WWDT_EXPORTED_CONSTANTS */
|
||||||
|
|
||||||
|
|
||||||
|
/** @addtogroup WWDT_EXPORTED_FUNCTIONS WWDT Exported Functions
|
||||||
|
@{
|
||||||
|
*/
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear WWDT Reset System Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear WWDT time-out reset system flag.
|
||||||
|
*/
|
||||||
|
#define WWDT_CLEAR_RESET_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTRF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Clear WWDT Compared Match Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to clear WWDT compared match interrupt flag.
|
||||||
|
*/
|
||||||
|
#define WWDT_CLEAR_INT_FLAG() (WWDT->STATUS = WWDT_STATUS_WWDTIF_Msk)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get WWDT Reset System Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 WWDT time-out reset system did not occur
|
||||||
|
* @retval 1 WWDT time-out reset system occurred
|
||||||
|
*
|
||||||
|
* @details This macro is used to indicate system has been reset by WWDT time-out reset or not.
|
||||||
|
*/
|
||||||
|
#define WWDT_GET_RESET_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTRF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get WWDT Compared Match Interrupt Flag
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @retval 0 WWDT compare match interrupt did not occur
|
||||||
|
* @retval 1 WWDT compare match interrupt occurred
|
||||||
|
*
|
||||||
|
* @details This macro is used to indicate WWDT counter value matches CMPDAT value or not.
|
||||||
|
*/
|
||||||
|
#define WWDT_GET_INT_FLAG() ((WWDT->STATUS & WWDT_STATUS_WWDTIF_Msk)? 1 : 0)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Get WWDT Counter
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return WWDT Counter Value
|
||||||
|
*
|
||||||
|
* @details This macro reflects the current WWDT counter value.
|
||||||
|
*/
|
||||||
|
#define WWDT_GET_COUNTER() (WWDT->CNT)
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Reload WWDT Counter
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This macro is used to reload the WWDT counter value to 0x3F.
|
||||||
|
* @note User can only write WWDT_RLDCNT register to reload WWDT counter value when current WWDT counter value \n
|
||||||
|
* between 0 and CMPDAT value. If user writes WWDT_RLDCNT when current WWDT counter value is larger than CMPDAT, \n
|
||||||
|
* WWDT reset signal will generate immediately to reset system.
|
||||||
|
*/
|
||||||
|
#define WWDT_RELOAD_COUNTER() (WWDT->RLDCNT = WWDT_RELOAD_WORD)
|
||||||
|
|
||||||
|
void WWDT_Open(uint32_t u32PreScale, uint32_t u32CmpValue, uint32_t u32EnableInt);
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WWDT_EXPORTED_FUNCTIONS */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group WWDT_Driver */
|
||||||
|
|
||||||
|
/*@}*/ /* end of group Standard_Driver */
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __WWDT_H__ */
|
||||||
|
|
||||||
|
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
|
||||||
|
LR_IROM1 0x00000000 {
|
||||||
|
ER_IROM1 0x00000000 { ; load address = execution address
|
||||||
|
*(RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
|
||||||
|
; uvisor-lib.a (+RW +ZI)
|
||||||
|
;}
|
||||||
|
|
||||||
|
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
|
||||||
|
}
|
||||||
|
|
||||||
|
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102)) { ; Reserve for vectors
|
||||||
|
}
|
||||||
|
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x18000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM
|
||||||
|
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20018000) ; 96 KB SRAM
|
||||||
|
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
/* mbed Microcontroller Library - stackheap
|
||||||
|
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* Setup a fixed single stack/heap memory model,
|
||||||
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
|
||||||
|
extern char Image$$ARM_LIB_HEAP$$Base[];
|
||||||
|
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
|
||||||
|
r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,27 @@
|
||||||
|
|
||||||
|
LR_IROM1 0x00000000 {
|
||||||
|
ER_IROM1 0x00000000 { ; load address = execution address
|
||||||
|
*(RESET, +First)
|
||||||
|
*(InRoot$$Sections)
|
||||||
|
.ANY (+RO)
|
||||||
|
}
|
||||||
|
|
||||||
|
;UVISOR AlignExpr(+0, 16) { ; 16 byte-aligned
|
||||||
|
; uvisor-lib.a (+RW +ZI)
|
||||||
|
;}
|
||||||
|
|
||||||
|
ARM_LIB_STACK 0x20000000 EMPTY 0x800 {
|
||||||
|
}
|
||||||
|
|
||||||
|
ER_IRAMVEC 0x20000800 EMPTY (4*(16 + 102)) { ; Reserve for vectors
|
||||||
|
}
|
||||||
|
RW_IRAM1 AlignExpr(+0, 16) { ; 16 byte-aligned
|
||||||
|
.ANY (+RW +ZI)
|
||||||
|
}
|
||||||
|
|
||||||
|
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (0x20000000 + 0x18000 - AlignExpr(ImageLimit(RW_IRAM1), 16)) {
|
||||||
|
}
|
||||||
|
}
|
||||||
|
ScatterAssert(LoadLimit(LR_IROM1) <= 0x00080000) ; 512 KB APROM
|
||||||
|
ScatterAssert(ImageLimit(ARM_LIB_HEAP) <= 0x20018000) ; 96 KB SRAM
|
||||||
|
|
||||||
|
|
@ -0,0 +1,28 @@
|
||||||
|
/* mbed Microcontroller Library - stackheap
|
||||||
|
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
|
||||||
|
*
|
||||||
|
* Setup a fixed single stack/heap memory model,
|
||||||
|
* between the top of the RW/ZI region and the stackpointer
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#include <rt_misc.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
|
||||||
|
extern char Image$$ARM_LIB_STACK$$ZI$$Limit[];
|
||||||
|
extern char Image$$ARM_LIB_HEAP$$Base[];
|
||||||
|
extern char Image$$ARM_LIB_HEAP$$ZI$$Limit[];
|
||||||
|
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
|
||||||
|
|
||||||
|
struct __initial_stackheap r;
|
||||||
|
r.heap_base = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
|
||||||
|
r.heap_limit = (uint32_t)Image$$ARM_LIB_HEAP$$ZI$$Limit;
|
||||||
|
return r;
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,255 @@
|
||||||
|
/*
|
||||||
|
* Nuvoton M2351 GCC linker script file
|
||||||
|
*/
|
||||||
|
|
||||||
|
StackSize = 0x800;
|
||||||
|
|
||||||
|
MEMORY
|
||||||
|
{
|
||||||
|
VECTORS (rx) : ORIGIN = 0x00000000, LENGTH = 0x00000400
|
||||||
|
FLASH (rx) : ORIGIN = 0x00000400, LENGTH = 0x00080000 - 0x00000400
|
||||||
|
RAM_INTERN (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 - 0x00000000
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Must match cmsis_nvic.h
|
||||||
|
*/
|
||||||
|
__vector_size = 4 * (16 + 102);
|
||||||
|
|
||||||
|
|
||||||
|
/* Linker script to place sections and symbol values. Should be used together
|
||||||
|
* with other linker script that defines memory regions FLASH and RAM.
|
||||||
|
* It references following symbols, which must be defined in code:
|
||||||
|
* Reset_Handler : Entry of reset handler
|
||||||
|
*
|
||||||
|
* It defines following symbols, which code can use without definition:
|
||||||
|
* __exidx_start
|
||||||
|
* __exidx_end
|
||||||
|
* __etext
|
||||||
|
* __data_start__
|
||||||
|
* __preinit_array_start
|
||||||
|
* __preinit_array_end
|
||||||
|
* __init_array_start
|
||||||
|
* __init_array_end
|
||||||
|
* __fini_array_start
|
||||||
|
* __fini_array_end
|
||||||
|
* __data_end__
|
||||||
|
* __bss_start__
|
||||||
|
* __bss_end__
|
||||||
|
* __end__
|
||||||
|
* end
|
||||||
|
* __HeapLimit
|
||||||
|
* __StackLimit
|
||||||
|
* __StackTop
|
||||||
|
* __stack
|
||||||
|
*/
|
||||||
|
ENTRY(Reset_Handler)
|
||||||
|
|
||||||
|
SECTIONS
|
||||||
|
{
|
||||||
|
.isr_vector :
|
||||||
|
{
|
||||||
|
__vector_table = .;
|
||||||
|
KEEP(*(.vector_table))
|
||||||
|
. = ALIGN(4);
|
||||||
|
} > VECTORS
|
||||||
|
|
||||||
|
/* ensure that uvisor bss is at the beginning of memory */
|
||||||
|
.uvisor.bss (NOLOAD):
|
||||||
|
{
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_bss_start = .;
|
||||||
|
|
||||||
|
/* protected uvisor main bss */
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_bss_main_start = .;
|
||||||
|
KEEP(*(.keep.uvisor.bss.main))
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_bss_main_end = .;
|
||||||
|
|
||||||
|
/* protected uvisor secure boxes bss */
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_bss_boxes_start = .;
|
||||||
|
KEEP(*(.keep.uvisor.bss.boxes))
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_bss_boxes_end = .;
|
||||||
|
|
||||||
|
/* Ensure log2(size) alignment of the uvisor region, to ensure that the region can be effectively protected by the MPU. */
|
||||||
|
. = ALIGN(1 << LOG2CEIL(__uvisor_bss_boxes_end - __uvisor_bss_start));
|
||||||
|
__uvisor_bss_end = .;
|
||||||
|
} > RAM_INTERN
|
||||||
|
|
||||||
|
.text :
|
||||||
|
{
|
||||||
|
/* uVisor code and data */
|
||||||
|
. = ALIGN(4);
|
||||||
|
__uvisor_main_start = .;
|
||||||
|
*(.uvisor.main)
|
||||||
|
__uvisor_main_end = .;
|
||||||
|
|
||||||
|
*(.text*)
|
||||||
|
|
||||||
|
KEEP(*(.init))
|
||||||
|
KEEP(*(.fini))
|
||||||
|
|
||||||
|
/* .ctors */
|
||||||
|
*crtbegin.o(.ctors)
|
||||||
|
*crtbegin?.o(.ctors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
|
||||||
|
*(SORT(.ctors.*))
|
||||||
|
*(.ctors)
|
||||||
|
|
||||||
|
/* .dtors */
|
||||||
|
*crtbegin.o(.dtors)
|
||||||
|
*crtbegin?.o(.dtors)
|
||||||
|
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
|
||||||
|
*(SORT(.dtors.*))
|
||||||
|
*(.dtors)
|
||||||
|
|
||||||
|
*(.rodata*)
|
||||||
|
|
||||||
|
KEEP(*(.eh_frame*))
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
.ARM.extab :
|
||||||
|
{
|
||||||
|
*(.ARM.extab* .gnu.linkonce.armextab.*)
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
.ARM.exidx :
|
||||||
|
{
|
||||||
|
__exidx_start = .;
|
||||||
|
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
|
||||||
|
__exidx_end = .;
|
||||||
|
} > FLASH
|
||||||
|
|
||||||
|
/* .stack section doesn't contains any symbols. It is only
|
||||||
|
* used for linker to reserve space for the main stack section
|
||||||
|
* WARNING: .stack should come immediately after the last secure memory
|
||||||
|
* section. This provides stack overflow detection. */
|
||||||
|
.stack (NOLOAD):
|
||||||
|
{
|
||||||
|
__StackLimit = .;
|
||||||
|
*(.stack*);
|
||||||
|
. += StackSize - (. - __StackLimit);
|
||||||
|
} > RAM_INTERN
|
||||||
|
|
||||||
|
/* Set stack top to end of RAM, and stack limit move down by
|
||||||
|
* size of stack_dummy section */
|
||||||
|
__StackTop = ADDR(.stack) + SIZEOF(.stack);
|
||||||
|
__StackLimit = ADDR(.stack);
|
||||||
|
PROVIDE(__stack = __StackTop);
|
||||||
|
|
||||||
|
/* Relocate vector table in SRAM */
|
||||||
|
.isr_vector.reloc (NOLOAD) :
|
||||||
|
{
|
||||||
|
. = ALIGN(1 << LOG2CEIL(__vector_size));
|
||||||
|
PROVIDE(__start_vector_table__ = .);
|
||||||
|
. += __vector_size;
|
||||||
|
PROVIDE(__end_vector_table__ = .);
|
||||||
|
} > RAM_INTERN
|
||||||
|
|
||||||
|
.data :
|
||||||
|
{
|
||||||
|
PROVIDE( __etext = LOADADDR(.data) );
|
||||||
|
|
||||||
|
__data_start__ = .;
|
||||||
|
*(vtable)
|
||||||
|
*(.data*)
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* preinit data */
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_start = .);
|
||||||
|
KEEP(*(.preinit_array))
|
||||||
|
PROVIDE_HIDDEN (__preinit_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* init data */
|
||||||
|
PROVIDE_HIDDEN (__init_array_start = .);
|
||||||
|
KEEP(*(SORT(.init_array.*)))
|
||||||
|
KEEP(*(.init_array))
|
||||||
|
PROVIDE_HIDDEN (__init_array_end = .);
|
||||||
|
|
||||||
|
. = ALIGN(4);
|
||||||
|
/* finit data */
|
||||||
|
PROVIDE_HIDDEN (__fini_array_start = .);
|
||||||
|
KEEP(*(SORT(.fini_array.*)))
|
||||||
|
KEEP(*(.fini_array))
|
||||||
|
PROVIDE_HIDDEN (__fini_array_end = .);
|
||||||
|
|
||||||
|
/* All data end */
|
||||||
|
. = ALIGN(32);
|
||||||
|
__data_end__ = .;
|
||||||
|
|
||||||
|
} >RAM_INTERN AT>FLASH
|
||||||
|
|
||||||
|
/* uvisor configuration data */
|
||||||
|
.uvisor.secure :
|
||||||
|
{
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_secure_start = .;
|
||||||
|
|
||||||
|
/* uvisor secure boxes configuration tables */
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_cfgtbl_start = .;
|
||||||
|
KEEP(*(.keep.uvisor.cfgtbl))
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_cfgtbl_end = .;
|
||||||
|
|
||||||
|
/* pointers to uvisor secure boxes configuration tables */
|
||||||
|
/* note: no further alignment here, we need to have the exact list of pointers */
|
||||||
|
__uvisor_cfgtbl_ptr_start = .;
|
||||||
|
KEEP(*(.keep.uvisor.cfgtbl_ptr_first))
|
||||||
|
KEEP(*(.keep.uvisor.cfgtbl_ptr))
|
||||||
|
__uvisor_cfgtbl_ptr_end = .;
|
||||||
|
|
||||||
|
/* the following symbols are kept for backward compatibility and will be soon
|
||||||
|
* deprecated; applications actively using uVisor (__uvisor_mode == UVISOR_ENABLED)
|
||||||
|
* will need to use uVisor 0.8.x or above, or the security assertions will halt the
|
||||||
|
* system */
|
||||||
|
/************************/
|
||||||
|
__uvisor_data_src = .;
|
||||||
|
__uvisor_data_start = .;
|
||||||
|
__uvisor_data_end = .;
|
||||||
|
/************************/
|
||||||
|
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uvisor_secure_end = .;
|
||||||
|
} >FLASH
|
||||||
|
|
||||||
|
.uninitialized (NOLOAD):
|
||||||
|
{
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uninitialized_start = .;
|
||||||
|
*(.uninitialized)
|
||||||
|
KEEP(*(.keep.uninitialized))
|
||||||
|
. = ALIGN(32);
|
||||||
|
__uninitialized_end = .;
|
||||||
|
} > RAM_INTERN
|
||||||
|
|
||||||
|
.bss (NOLOAD):
|
||||||
|
{
|
||||||
|
__bss_start__ = .;
|
||||||
|
*(.bss*)
|
||||||
|
*(COMMON)
|
||||||
|
__bss_end__ = .;
|
||||||
|
} > RAM_INTERN
|
||||||
|
|
||||||
|
.heap (NOLOAD):
|
||||||
|
{
|
||||||
|
__end__ = .;
|
||||||
|
end = __end__;
|
||||||
|
*(.heap*);
|
||||||
|
. += (ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN) - .);
|
||||||
|
__HeapLimit = .;
|
||||||
|
} > RAM_INTERN
|
||||||
|
PROVIDE(__heap_size = SIZEOF(.heap));
|
||||||
|
PROVIDE(__mbed_sbrk_start = ADDR(.heap));
|
||||||
|
PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
|
||||||
|
|
||||||
|
/* Provide physical memory boundaries for uVisor. */
|
||||||
|
__uvisor_flash_start = ORIGIN(VECTORS);
|
||||||
|
__uvisor_flash_end = ORIGIN(FLASH) + LENGTH(FLASH);
|
||||||
|
__uvisor_sram_start = ORIGIN(RAM_INTERN);
|
||||||
|
__uvisor_sram_end = ORIGIN(RAM_INTERN) + LENGTH(RAM_INTERN);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,40 @@
|
||||||
|
/******************************************************************************
|
||||||
|
* @file startup_NUC472_442.c
|
||||||
|
* @version V0.10
|
||||||
|
* $Revision: 11 $
|
||||||
|
* $Date: 15/09/02 10:02a $
|
||||||
|
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for NUC472/442 MCU
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*****************************************************************************/
|
||||||
|
|
||||||
|
#include "M2351.h"
|
||||||
|
#include <errno.h>
|
||||||
|
#include "nu_miscutil.h"
|
||||||
|
|
||||||
|
extern uint32_t __mbed_sbrk_start;
|
||||||
|
extern uint32_t __mbed_krbs_start;
|
||||||
|
|
||||||
|
#define NU_HEAP_ALIGN 4
|
||||||
|
|
||||||
|
/**
|
||||||
|
* The default implementation of _sbrk() (in common/retarget.cpp) for GCC_ARM requires one-region model (heap and stack share one region), which doesn't
|
||||||
|
* fit two-region model (heap and stack are two distinct regions), for example, NUMAKER-PFM-NUC472 locates heap on external SRAM. Define __wrap__sbrk() to
|
||||||
|
* override the default _sbrk(). It is expected to get called through gcc hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
|
||||||
|
*/
|
||||||
|
void *__wrap__sbrk(int incr)
|
||||||
|
{
|
||||||
|
static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
|
||||||
|
uint32_t heap_ind_old = NU_ALIGN_UP(heap_ind, NU_HEAP_ALIGN);
|
||||||
|
uint32_t heap_ind_new = NU_ALIGN_UP(heap_ind_old + incr, NU_HEAP_ALIGN);
|
||||||
|
|
||||||
|
if (heap_ind_new > &__mbed_krbs_start) {
|
||||||
|
errno = ENOMEM;
|
||||||
|
return (void *) -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
heap_ind = heap_ind_new;
|
||||||
|
|
||||||
|
return (void *) heap_ind_old;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,36 @@
|
||||||
|
/*###ICF### Section handled by ICF editor, don't touch! ****/
|
||||||
|
/*-Editor annotation file-*/
|
||||||
|
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
|
||||||
|
/*-Specials-*/
|
||||||
|
define symbol __ICFEDIT_intvec_start__ = 0x00000000;
|
||||||
|
/*-Memory Regions-*/
|
||||||
|
define symbol __ICFEDIT_region_ROM_start__ = 0x00000000;
|
||||||
|
define symbol __ICFEDIT_region_ROM_end__ = 0x00080000 - 1;
|
||||||
|
define symbol __ICFEDIT_region_IRAM_start__ = 0x20000000;
|
||||||
|
define symbol __ICFEDIT_region_IRAM_end__ = 0x20018000 - 1;
|
||||||
|
/*-Sizes-*/
|
||||||
|
define symbol __ICFEDIT_size_cstack__ = 0x800;
|
||||||
|
define symbol __ICFEDIT_size_heap__ = 0x4000;
|
||||||
|
/**** End of ICF editor section. ###ICF###*/
|
||||||
|
|
||||||
|
|
||||||
|
define memory mem with size = 4G;
|
||||||
|
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
|
||||||
|
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
|
||||||
|
|
||||||
|
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
|
||||||
|
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
|
||||||
|
/* NOTE: Vector table base requires to be aligned to the power of vector table size. Give a safe value here. */
|
||||||
|
define block IRAMVEC with alignment = 1024, size = 4 * (16 + 102) { };
|
||||||
|
|
||||||
|
|
||||||
|
initialize by copy { readwrite };
|
||||||
|
do not initialize { section .noinit };
|
||||||
|
|
||||||
|
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
|
||||||
|
|
||||||
|
place in ROM_region { readonly };
|
||||||
|
place at start of IRAM_region { block CSTACK };
|
||||||
|
place in IRAM_region { block IRAMVEC };
|
||||||
|
place in IRAM_region { readwrite };
|
||||||
|
place in IRAM_region { block HEAP };
|
||||||
|
|
@ -0,0 +1,33 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2017 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_CMSIS_H
|
||||||
|
#define MBED_CMSIS_H
|
||||||
|
|
||||||
|
#include "M2351.h"
|
||||||
|
#include "cmsis_nvic.h"
|
||||||
|
|
||||||
|
// Support linker-generated symbol as start of relocated vector table.
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
extern uint32_t Image$$ER_IRAMVEC$$ZI$$Base;
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
extern uint32_t __start_vector_table__;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,312 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2017 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_CMSIS_NVIC_H
|
||||||
|
#define MBED_CMSIS_NVIC_H
|
||||||
|
|
||||||
|
#include "cmsis.h"
|
||||||
|
|
||||||
|
#define NVIC_USER_IRQ_OFFSET 16
|
||||||
|
#define NVIC_USER_IRQ_NUMBER 102
|
||||||
|
#define NVIC_NUM_VECTORS (NVIC_USER_IRQ_OFFSET + NVIC_USER_IRQ_NUMBER)
|
||||||
|
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &Image$$ER_IRAMVEC$$ZI$$Base)
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
# pragma section = "IRAMVEC"
|
||||||
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) __section_begin("IRAMVEC"))
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
# define NVIC_RAM_VECTOR_ADDRESS ((uint32_t) &__start_vector_table__)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Interrupt Priorities are WORD accessible only under ARMv6M */
|
||||||
|
/* The following MACROS handle generation of the register offset and byte masks */
|
||||||
|
#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
|
||||||
|
#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
|
||||||
|
#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Enable Interrupt
|
||||||
|
\details Enables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Enable status
|
||||||
|
\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt is not enabled.
|
||||||
|
\return 1 Interrupt is enabled.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetEnableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Disable Interrupt
|
||||||
|
\details Disables a device specific interrupt in the NVIC interrupt controller.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||||
|
__DSB();
|
||||||
|
__ISB();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Pending Interrupt
|
||||||
|
\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not pending.
|
||||||
|
\return 1 Interrupt status is pending.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Pending Interrupt
|
||||||
|
\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Clear Pending Interrupt
|
||||||
|
\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Active Interrupt
|
||||||
|
\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
|
||||||
|
\param [in] IRQn Device specific interrupt number.
|
||||||
|
\return 0 Interrupt status is not active.
|
||||||
|
\return 1 Interrupt status is active.
|
||||||
|
\note IRQn must not be negative.
|
||||||
|
*/
|
||||||
|
#ifdef ARM_V8M
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return(0U);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Priority
|
||||||
|
\details Sets the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\param [in] priority Priority to set.
|
||||||
|
\note The priority cannot be set for every processor exception.
|
||||||
|
*/
|
||||||
|
#ifdef ARM_V8M
|
||||||
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
__STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
|
||||||
|
{
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
|
||||||
|
(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Priority
|
||||||
|
\details Reads the priority of a device specific interrupt or a processor exception.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Interrupt Priority.
|
||||||
|
Value is aligned automatically to the implemented priority bits of the microcontroller.
|
||||||
|
*/
|
||||||
|
#ifdef ARM_V8M
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#else
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
|
||||||
|
if ((int32_t)(IRQn) >= 0)
|
||||||
|
{
|
||||||
|
return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
else
|
||||||
|
{
|
||||||
|
return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
/**
|
||||||
|
\brief Set Interrupt Vector
|
||||||
|
\details Sets an interrupt vector in SRAM based interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
VTOR must been relocated to SRAM before.
|
||||||
|
If VTOR is not present address 0 must be mapped to SRAM.
|
||||||
|
\param [in] IRQn Interrupt number
|
||||||
|
\param [in] vector Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
|
||||||
|
{
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
#else
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
#endif
|
||||||
|
vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief Get Interrupt Vector
|
||||||
|
\details Reads an interrupt vector from interrupt vector table.
|
||||||
|
The interrupt number can be positive to specify a device specific interrupt,
|
||||||
|
or negative to specify a processor exception.
|
||||||
|
\param [in] IRQn Interrupt number.
|
||||||
|
\return Address of interrupt handler function
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE uint32_t NVIC_GetVector(IRQn_Type IRQn)
|
||||||
|
{
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
uint32_t *vectors = (uint32_t *)SCB->VTOR;
|
||||||
|
#else
|
||||||
|
uint32_t *vectors = (uint32_t *)0x0U;
|
||||||
|
#endif
|
||||||
|
return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
\brief System Reset
|
||||||
|
\details Initiates a system reset request to reset the MCU.
|
||||||
|
*/
|
||||||
|
__STATIC_INLINE void NVIC_SystemReset(void)
|
||||||
|
{
|
||||||
|
__DSB(); /* Ensure all outstanding memory accesses included
|
||||||
|
buffered write are completed before reset */
|
||||||
|
SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
|
||||||
|
SCB_AIRCR_SYSRESETREQ_Msk);
|
||||||
|
__DSB(); /* Ensure completion of memory access */
|
||||||
|
|
||||||
|
for(;;) /* wait until reset */
|
||||||
|
{
|
||||||
|
__NOP();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,410 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file startup_M2351.c
|
||||||
|
* @version V2.00
|
||||||
|
* $Revision: 9 $
|
||||||
|
* $Date: 16/08/27 12:33p $
|
||||||
|
* @brief Startup Source File
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
/* Suppress warning messages */
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
// Suppress warning message: extended constant initialiser used
|
||||||
|
#pragma diag_suppress 1296
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Macro Definitions */
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
#define WEAK __attribute__ ((weak))
|
||||||
|
#define ALIAS(f) __attribute__ ((weak, alias(#f)))
|
||||||
|
|
||||||
|
#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
|
||||||
|
void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
|
||||||
|
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
//#define STRINGIFY(x) #x
|
||||||
|
//#define _STRINGIFY(x) STRINGIFY(x)
|
||||||
|
#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
|
||||||
|
void FUN(void); \
|
||||||
|
_Pragma(_STRINGIFY(_WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)))
|
||||||
|
#define _WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) weak __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS)
|
||||||
|
#define __WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) FUN##=##FUN_ALIAS
|
||||||
|
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
#define WEAK __attribute__ ((weak))
|
||||||
|
#define ALIAS(f) __attribute__ ((weak, alias(#f)))
|
||||||
|
|
||||||
|
#define WEAK_ALIAS_FUNC(FUN, FUN_ALIAS) \
|
||||||
|
void FUN(void) __attribute__ ((weak, alias(#FUN_ALIAS)));
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
/* Initialize segments */
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
extern uint32_t Image$$ARM_LIB_STACK$$ZI$$Limit;
|
||||||
|
extern void __main(void);
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
void __iar_program_start(void);
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
extern uint32_t __StackTop;
|
||||||
|
extern uint32_t __etext;
|
||||||
|
extern uint32_t __data_start__;
|
||||||
|
extern uint32_t __data_end__;
|
||||||
|
extern uint32_t __bss_start__;
|
||||||
|
extern uint32_t __bss_end__;
|
||||||
|
|
||||||
|
extern void uvisor_init(void);
|
||||||
|
//#if defined(TOOLCHAIN_GCC_ARM)
|
||||||
|
//extern void _start(void);
|
||||||
|
//#endif
|
||||||
|
extern void software_init_hook(void) __attribute__((weak));
|
||||||
|
extern void __libc_init_array(void);
|
||||||
|
extern int main(void);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Default empty handler */
|
||||||
|
void Default_Handler(void);
|
||||||
|
|
||||||
|
/* Reset handler */
|
||||||
|
void Reset_Handler(void);
|
||||||
|
|
||||||
|
/* Cortex-M0+ core handlers */
|
||||||
|
WEAK_ALIAS_FUNC(NMI_Handler, Default_Handler)
|
||||||
|
WEAK_ALIAS_FUNC(HardFault_Handler, Default_Handler)
|
||||||
|
WEAK_ALIAS_FUNC(SVC_Handler, Default_Handler)
|
||||||
|
|
||||||
|
WEAK_ALIAS_FUNC(PendSV_Handler, Default_Handler)
|
||||||
|
WEAK_ALIAS_FUNC(SysTick_Handler, Default_Handler)
|
||||||
|
|
||||||
|
/* Peripherals handlers */
|
||||||
|
WEAK_ALIAS_FUNC(BOD_IRQHandler, Default_Handler) // 0: Brown Out detection
|
||||||
|
WEAK_ALIAS_FUNC(IRC_IRQHandler, Default_Handler) // 1: Internal RC
|
||||||
|
WEAK_ALIAS_FUNC(PWRWU_IRQHandler, Default_Handler) // 2: Power down wake up
|
||||||
|
WEAK_ALIAS_FUNC(SRAM_IRQHandler, Default_Handler) // 3: SRAM
|
||||||
|
WEAK_ALIAS_FUNC(CLKFAIL_IRQHandler, Default_Handler) // 4: Clock detection fail
|
||||||
|
// 5: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(RTC_IRQHandler, Default_Handler) // 6: Real Time Clock
|
||||||
|
WEAK_ALIAS_FUNC(TAMPER_IRQHandler, Default_Handler) // 7: Tamper detection
|
||||||
|
WEAK_ALIAS_FUNC(WDT_IRQHandler, Default_Handler) // 8: Watchdog timer
|
||||||
|
WEAK_ALIAS_FUNC(WWDT_IRQHandler, Default_Handler) // 9: Window watchdog timer
|
||||||
|
WEAK_ALIAS_FUNC(EINT0_IRQHandler, Default_Handler) // 10: External Input 0
|
||||||
|
WEAK_ALIAS_FUNC(EINT1_IRQHandler, Default_Handler) // 11: External Input 1
|
||||||
|
WEAK_ALIAS_FUNC(EINT2_IRQHandler, Default_Handler) // 12: External Input 2
|
||||||
|
WEAK_ALIAS_FUNC(EINT3_IRQHandler, Default_Handler) // 13: External Input 3
|
||||||
|
WEAK_ALIAS_FUNC(EINT4_IRQHandler, Default_Handler) // 14: External Input 4
|
||||||
|
WEAK_ALIAS_FUNC(EINT5_IRQHandler, Default_Handler) // 15: External Input 5
|
||||||
|
WEAK_ALIAS_FUNC(GPA_IRQHandler, Default_Handler) // 16: GPIO Port A
|
||||||
|
WEAK_ALIAS_FUNC(GPB_IRQHandler, Default_Handler) // 17: GPIO Port B
|
||||||
|
WEAK_ALIAS_FUNC(GPC_IRQHandler, Default_Handler) // 18: GPIO Port C
|
||||||
|
WEAK_ALIAS_FUNC(GPD_IRQHandler, Default_Handler) // 19: GPIO Port D
|
||||||
|
WEAK_ALIAS_FUNC(GPE_IRQHandler, Default_Handler) // 20: GPIO Port E
|
||||||
|
WEAK_ALIAS_FUNC(GPF_IRQHandler, Default_Handler) // 21: GPIO Port F
|
||||||
|
WEAK_ALIAS_FUNC(SPI0_IRQHandler, Default_Handler) // 22: SPI0
|
||||||
|
WEAK_ALIAS_FUNC(SPI1_IRQHandler, Default_Handler) // 23: SPI1
|
||||||
|
WEAK_ALIAS_FUNC(BRAKE0_IRQHandler, Default_Handler) // 24:
|
||||||
|
WEAK_ALIAS_FUNC(PWM0_P0_IRQHandler, Default_Handler) // 25:
|
||||||
|
WEAK_ALIAS_FUNC(PWM0_P1_IRQHandler, Default_Handler) // 26:
|
||||||
|
WEAK_ALIAS_FUNC(PWM0_P2_IRQHandler, Default_Handler) // 27:
|
||||||
|
WEAK_ALIAS_FUNC(BRAKE1_IRQHandler, Default_Handler) // 28:
|
||||||
|
WEAK_ALIAS_FUNC(PWM1_P0_IRQHandler, Default_Handler) // 29:
|
||||||
|
WEAK_ALIAS_FUNC(PWM1_P1_IRQHandler, Default_Handler) // 30:
|
||||||
|
WEAK_ALIAS_FUNC(PWM1_P2_IRQHandler, Default_Handler) // 31:
|
||||||
|
WEAK_ALIAS_FUNC(TMR0_IRQHandler, Default_Handler) // 32: Timer 0
|
||||||
|
WEAK_ALIAS_FUNC(TMR1_IRQHandler, Default_Handler) // 33: Timer 1
|
||||||
|
WEAK_ALIAS_FUNC(TMR2_IRQHandler, Default_Handler) // 34: Timer 2
|
||||||
|
WEAK_ALIAS_FUNC(TMR3_IRQHandler, Default_Handler) // 35: Timer 3
|
||||||
|
WEAK_ALIAS_FUNC(UART0_IRQHandler, Default_Handler) // 36: UART0
|
||||||
|
WEAK_ALIAS_FUNC(UART1_IRQHandler, Default_Handler) // 37: UART1
|
||||||
|
WEAK_ALIAS_FUNC(I2C0_IRQHandler, Default_Handler) // 38: I2C0
|
||||||
|
WEAK_ALIAS_FUNC(I2C1_IRQHandler, Default_Handler) // 39: I2C1
|
||||||
|
WEAK_ALIAS_FUNC(PDMA0_IRQHandler, Default_Handler) // 40: Peripheral DMA
|
||||||
|
WEAK_ALIAS_FUNC(DAC_IRQHandler, Default_Handler) // 41: DAC
|
||||||
|
WEAK_ALIAS_FUNC(EADC0_IRQHandler, Default_Handler) // 42: ADC0 interrupt source 0
|
||||||
|
WEAK_ALIAS_FUNC(EADC1_IRQHandler, Default_Handler) // 43: ADC0 interrupt source 1
|
||||||
|
WEAK_ALIAS_FUNC(ACMP01_IRQHandler, Default_Handler) // 44: ACMP0 and ACMP1
|
||||||
|
// 45: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(EADC2_IRQHandler, Default_Handler) // 46: ADC0 interrupt source 2
|
||||||
|
WEAK_ALIAS_FUNC(EADC3_IRQHandler, Default_Handler) // 47: ADC0 interrupt source 3
|
||||||
|
WEAK_ALIAS_FUNC(UART2_IRQHandler, Default_Handler) // 48: UART2
|
||||||
|
WEAK_ALIAS_FUNC(UART3_IRQHandler, Default_Handler) // 49: UART3
|
||||||
|
// 50: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(SPI2_IRQHandler, Default_Handler) // 51: SPI2
|
||||||
|
WEAK_ALIAS_FUNC(SPI3_IRQHandler, Default_Handler) // 52: SPI3
|
||||||
|
WEAK_ALIAS_FUNC(USBD_IRQHandler, Default_Handler) // 53: USB device
|
||||||
|
WEAK_ALIAS_FUNC(USBH_IRQHandler, Default_Handler) // 54: USB host
|
||||||
|
WEAK_ALIAS_FUNC(USBOTG_IRQHandler, Default_Handler) // 55: USB OTG
|
||||||
|
WEAK_ALIAS_FUNC(CAN0_IRQHandler, Default_Handler) // 56: CAN0
|
||||||
|
// 57: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(SC0_IRQHandler, Default_Handler) // 58:
|
||||||
|
WEAK_ALIAS_FUNC(SC1_IRQHandler, Default_Handler) // 59:
|
||||||
|
WEAK_ALIAS_FUNC(SC2_IRQHandler, Default_Handler) // 60:
|
||||||
|
// 61:
|
||||||
|
WEAK_ALIAS_FUNC(SPI4_IRQHandler, Default_Handler) // 62:
|
||||||
|
// 63: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(SDH0_IRQHandler, Default_Handler) // 64:
|
||||||
|
// 65 ~67: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(I2S0_IRQHandler, Default_Handler) // 68:
|
||||||
|
// 69: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(OPA0_IRQHandler, Default_Handler) // 70:
|
||||||
|
WEAK_ALIAS_FUNC(CRPT_IRQHandler, Default_Handler) // 71:
|
||||||
|
WEAK_ALIAS_FUNC(GPG_IRQHandler, Default_Handler) // 72:
|
||||||
|
// 73: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(UART4_IRQHandler, Default_Handler) // 74:
|
||||||
|
WEAK_ALIAS_FUNC(UART5_IRQHandler, Default_Handler) // 75:
|
||||||
|
WEAK_ALIAS_FUNC(USCI0_IRQHandler, Default_Handler) // 76:
|
||||||
|
WEAK_ALIAS_FUNC(USCI1_IRQHandler, Default_Handler) // 77:
|
||||||
|
WEAK_ALIAS_FUNC(BPWM0_IRQHandler, Default_Handler) // 78:
|
||||||
|
WEAK_ALIAS_FUNC(BPWM1_IRQHandler, Default_Handler) // 79:
|
||||||
|
// 80~81: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(I2C2_IRQHandler, Default_Handler) // 82:
|
||||||
|
// 83: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(QEI0_IRQHandler, Default_Handler) // 84:
|
||||||
|
WEAK_ALIAS_FUNC(QEI1_IRQHandler, Default_Handler) // 85:
|
||||||
|
WEAK_ALIAS_FUNC(ECAP0_IRQHandler, Default_Handler) // 86:
|
||||||
|
WEAK_ALIAS_FUNC(ECAP1_IRQHandler, Default_Handler) // 87:
|
||||||
|
// 88~89: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(SDH1_IRQHandler, Default_Handler) // 90:
|
||||||
|
// 91~95: Reserved
|
||||||
|
WEAK_ALIAS_FUNC(SPI5_IRQHandler, Default_Handler) // 96:
|
||||||
|
WEAK_ALIAS_FUNC(DSRC_IRQHandler, Default_Handler) // 97:
|
||||||
|
WEAK_ALIAS_FUNC(PDMA1_IRQHandler, Default_Handler) // 98:
|
||||||
|
WEAK_ALIAS_FUNC(SCU_IRQHandler, Default_Handler) // 99:
|
||||||
|
WEAK_ALIAS_FUNC(LCD_IRQHandler, Default_Handler) // 100:
|
||||||
|
WEAK_ALIAS_FUNC(TRNG_IRQHandler, Default_Handler) // 101:
|
||||||
|
|
||||||
|
|
||||||
|
/* Vector table */
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
__attribute__ ((section("RESET")))
|
||||||
|
const uint32_t __vector_handlers[] = {
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
extern uint32_t CSTACK$$Limit;
|
||||||
|
const uint32_t __vector_table[] @ ".intvec" = {
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
__attribute__ ((section(".vector_table")))
|
||||||
|
const uint32_t __vector_handlers[] = {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Configure Initial Stack Pointer, using linker-generated symbols */
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
(uint32_t) &Image$$ARM_LIB_STACK$$ZI$$Limit,
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
//(uint32_t) __sfe("CSTACK"),
|
||||||
|
(uint32_t) &CSTACK$$Limit,
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
(uint32_t) &__StackTop,
|
||||||
|
#endif
|
||||||
|
|
||||||
|
(uint32_t) Reset_Handler, // Reset Handler
|
||||||
|
(uint32_t) NMI_Handler, // NMI Handler
|
||||||
|
(uint32_t) HardFault_Handler, // Hard Fault Handler
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
(uint32_t) SVC_Handler, // SVCall Handler
|
||||||
|
0, // Reserved
|
||||||
|
0, // Reserved
|
||||||
|
(uint32_t) PendSV_Handler, // PendSV Handler
|
||||||
|
(uint32_t) SysTick_Handler, // SysTick Handler
|
||||||
|
|
||||||
|
/* External Interrupts */
|
||||||
|
(uint32_t) BOD_IRQHandler, // 0: Brown Out detection
|
||||||
|
(uint32_t) IRC_IRQHandler, // 1: Internal RC
|
||||||
|
(uint32_t) PWRWU_IRQHandler, // 2: Power down wake up
|
||||||
|
(uint32_t) SRAM_IRQHandler, // 3:
|
||||||
|
(uint32_t) CLKFAIL_IRQHandler, // 4: Clock detection fail
|
||||||
|
(uint32_t) Default_Handler, // 5: Reserved
|
||||||
|
(uint32_t) RTC_IRQHandler, // 6: Real Time Clock
|
||||||
|
(uint32_t) TAMPER_IRQHandler, // 7: Tamper detection
|
||||||
|
(uint32_t) WDT_IRQHandler, // 8: Watchdog timer
|
||||||
|
(uint32_t) WWDT_IRQHandler, // 9: Window watchdog timer
|
||||||
|
(uint32_t) EINT0_IRQHandler, // 10: External Input 0
|
||||||
|
(uint32_t) EINT1_IRQHandler, // 11: External Input 1
|
||||||
|
(uint32_t) EINT2_IRQHandler, // 12: External Input 2
|
||||||
|
(uint32_t) EINT3_IRQHandler, // 13: External Input 3
|
||||||
|
(uint32_t) EINT4_IRQHandler, // 14: External Input 4
|
||||||
|
(uint32_t) EINT5_IRQHandler, // 15: External Input 5
|
||||||
|
(uint32_t) GPA_IRQHandler, // 16: GPIO Port A
|
||||||
|
(uint32_t) GPB_IRQHandler, // 17: GPIO Port B
|
||||||
|
(uint32_t) GPC_IRQHandler, // 18: GPIO Port C
|
||||||
|
(uint32_t) GPD_IRQHandler, // 19: GPIO Port D
|
||||||
|
(uint32_t) GPE_IRQHandler, // 20: GPIO Port E
|
||||||
|
(uint32_t) GPF_IRQHandler, // 21: GPIO Port F
|
||||||
|
(uint32_t) SPI0_IRQHandler, // 22: SPI0
|
||||||
|
(uint32_t) SPI1_IRQHandler, // 23: SPI1
|
||||||
|
(uint32_t) BRAKE0_IRQHandler, // 24:
|
||||||
|
(uint32_t) PWM0_P0_IRQHandler, // 25:
|
||||||
|
(uint32_t) PWM0_P1_IRQHandler, // 26:
|
||||||
|
(uint32_t) PWM0_P2_IRQHandler, // 27:
|
||||||
|
(uint32_t) BRAKE1_IRQHandler, // 28:
|
||||||
|
(uint32_t) PWM1_P0_IRQHandler, // 29:
|
||||||
|
(uint32_t) PWM1_P1_IRQHandler, // 30:
|
||||||
|
(uint32_t) PWM1_P2_IRQHandler, // 31:
|
||||||
|
(uint32_t) TMR0_IRQHandler, // 32: Timer 0
|
||||||
|
(uint32_t) TMR1_IRQHandler, // 33: Timer 1
|
||||||
|
(uint32_t) TMR2_IRQHandler, // 34: Timer 2
|
||||||
|
(uint32_t) TMR3_IRQHandler, // 35: Timer 3
|
||||||
|
(uint32_t) UART0_IRQHandler, // 36: UART0
|
||||||
|
(uint32_t) UART1_IRQHandler, // 37: UART1
|
||||||
|
(uint32_t) I2C0_IRQHandler, // 38: I2C0
|
||||||
|
(uint32_t) I2C1_IRQHandler, // 39: I2C1
|
||||||
|
(uint32_t) PDMA0_IRQHandler, // 40: Peripheral DMA
|
||||||
|
(uint32_t) DAC_IRQHandler, // 41: DAC
|
||||||
|
(uint32_t) EADC0_IRQHandler, // 42: ADC0 interrupt source 0
|
||||||
|
(uint32_t) EADC1_IRQHandler, // 43: ADC0 interrupt source 1
|
||||||
|
(uint32_t) ACMP01_IRQHandler, // 44: ACMP0 and ACMP1
|
||||||
|
(uint32_t) Default_Handler, // 45: Reserved
|
||||||
|
(uint32_t) EADC2_IRQHandler, // 46: ADC0 interrupt source 2
|
||||||
|
(uint32_t) EADC3_IRQHandler, // 47: ADC0 interrupt source 3
|
||||||
|
(uint32_t) UART2_IRQHandler, // 48: UART2
|
||||||
|
(uint32_t) UART3_IRQHandler, // 49: UART3
|
||||||
|
(uint32_t) Default_Handler, // 50: Reserved
|
||||||
|
(uint32_t) SPI2_IRQHandler, // 51: SPI2
|
||||||
|
(uint32_t) Default_Handler, // 52: Reserved
|
||||||
|
(uint32_t) USBD_IRQHandler, // 53: USB device
|
||||||
|
(uint32_t) USBH_IRQHandler, // 54: USB host
|
||||||
|
(uint32_t) USBOTG_IRQHandler, // 55: USB OTG
|
||||||
|
(uint32_t) CAN0_IRQHandler, // 56: CAN0
|
||||||
|
(uint32_t) Default_Handler, // 57: Reserved
|
||||||
|
(uint32_t) SC0_IRQHandler, // 58:
|
||||||
|
(uint32_t) SC1_IRQHandler, // 59:
|
||||||
|
(uint32_t) SC2_IRQHandler, // 60:
|
||||||
|
(uint32_t) Default_Handler, // 61: Reserved.
|
||||||
|
(uint32_t) SPI4_IRQHandler, // 62:
|
||||||
|
(uint32_t) Default_Handler, // 63:
|
||||||
|
(uint32_t) SDH0_IRQHandler, // 64:
|
||||||
|
(uint32_t) Default_Handler, // 65:
|
||||||
|
(uint32_t) Default_Handler, // 66:
|
||||||
|
(uint32_t) Default_Handler, // 67:
|
||||||
|
(uint32_t) I2S0_IRQHandler, // 68:
|
||||||
|
(uint32_t) Default_Handler, // 69:
|
||||||
|
(uint32_t) OPA0_IRQHandler, // 70:
|
||||||
|
(uint32_t) CRPT_IRQHandler, // 71:
|
||||||
|
(uint32_t) GPG_IRQHandler, // 72:
|
||||||
|
(uint32_t) Default_Handler, // 73:
|
||||||
|
(uint32_t) UART4_IRQHandler, // 74:
|
||||||
|
(uint32_t) UART5_IRQHandler, // 75:
|
||||||
|
(uint32_t) USCI0_IRQHandler, // 76:
|
||||||
|
(uint32_t) USCI1_IRQHandler, // 77:
|
||||||
|
(uint32_t) BPWM0_IRQHandler, // 78:
|
||||||
|
(uint32_t) BPWM1_IRQHandler, // 79:
|
||||||
|
(uint32_t) Default_Handler, // 80:
|
||||||
|
(uint32_t) Default_Handler, // 81:
|
||||||
|
(uint32_t) I2C2_IRQHandler, // 82:
|
||||||
|
(uint32_t) Default_Handler, // 83:
|
||||||
|
(uint32_t) QEI0_IRQHandler, // 84:
|
||||||
|
(uint32_t) QEI1_IRQHandler, // 85:
|
||||||
|
(uint32_t) ECAP0_IRQHandler, // 86:
|
||||||
|
(uint32_t) ECAP1_IRQHandler, // 87:
|
||||||
|
(uint32_t) Default_Handler, // 88:
|
||||||
|
(uint32_t) Default_Handler, // 89:
|
||||||
|
(uint32_t) SDH1_IRQHandler, // 90:
|
||||||
|
(uint32_t) Default_Handler, // 91:
|
||||||
|
(uint32_t) Default_Handler, // 92:
|
||||||
|
(uint32_t) Default_Handler, // 93:
|
||||||
|
(uint32_t) Default_Handler, // 94:
|
||||||
|
(uint32_t) Default_Handler, // 95:
|
||||||
|
(uint32_t) SPI5_IRQHandler, // 96:
|
||||||
|
(uint32_t) DSRC_IRQHandler, // 97:
|
||||||
|
(uint32_t) PDMA1_IRQHandler, // 98:
|
||||||
|
(uint32_t) SCU_IRQHandler, // 99:
|
||||||
|
(uint32_t) LCD_IRQHandler, // 100:
|
||||||
|
(uint32_t) TRNG_IRQHandler, // 101:
|
||||||
|
};
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief This is the code that gets called on processor reset.
|
||||||
|
*/
|
||||||
|
void Reset_Handler(void)
|
||||||
|
{
|
||||||
|
/* Disable register write-protection function */
|
||||||
|
SYS_UnlockReg();
|
||||||
|
|
||||||
|
/* Disable Power-on Reset function */
|
||||||
|
SYS_DISABLE_POR();
|
||||||
|
|
||||||
|
/* Enable register write-protection function */
|
||||||
|
SYS_LockReg();
|
||||||
|
|
||||||
|
/**
|
||||||
|
* SystemInit() must be called at the very start.
|
||||||
|
*/
|
||||||
|
SystemInit();
|
||||||
|
|
||||||
|
#if defined(__CC_ARM)
|
||||||
|
__main();
|
||||||
|
|
||||||
|
#elif defined(__ICCARM__)
|
||||||
|
__iar_program_start();
|
||||||
|
|
||||||
|
#elif defined(__GNUC__)
|
||||||
|
uint32_t *src_ind = (uint32_t *) &__etext;
|
||||||
|
uint32_t *dst_ind = (uint32_t *) &__data_start__;
|
||||||
|
uint32_t *dst_end = (uint32_t *) &__data_end__;
|
||||||
|
|
||||||
|
/* Move .data section from ROM to RAM */
|
||||||
|
if (src_ind != dst_ind) {
|
||||||
|
for (; dst_ind < dst_end;) {
|
||||||
|
*dst_ind ++ = *src_ind ++;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
/* Initialize .bss section to zero */
|
||||||
|
dst_ind = (uint32_t *) &__bss_start__;
|
||||||
|
dst_end = (uint32_t *) &__bss_end__;
|
||||||
|
if (dst_ind != dst_end) {
|
||||||
|
for (; dst_ind < dst_end;) {
|
||||||
|
*dst_ind ++ = 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
//uvisor_init();
|
||||||
|
|
||||||
|
if (software_init_hook) {
|
||||||
|
/**
|
||||||
|
* Give control to the RTOS via software_init_hook() which will also call __libc_init_array().
|
||||||
|
* Assume software_init_hook() is defined in libraries/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h.
|
||||||
|
*/
|
||||||
|
software_init_hook();
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
__libc_init_array();
|
||||||
|
main();
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/* Infinite loop */
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* \brief Default interrupt handler for unused IRQs.
|
||||||
|
*/
|
||||||
|
void Default_Handler(void)
|
||||||
|
{
|
||||||
|
while (1);
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
uint32_t GetPC(void)
|
||||||
|
{
|
||||||
|
uint32_t val=0;
|
||||||
|
__asm {
|
||||||
|
MOV R0, #0 // dumy
|
||||||
|
//MOV R0, LR // Except R0~R12, SP/LR/PC cannot be read or directly modified in inline assembly code
|
||||||
|
MOV val, R0
|
||||||
|
}
|
||||||
|
return val;
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,111 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file system_M2351.c
|
||||||
|
* @version V2.00
|
||||||
|
* $Revision: 6 $
|
||||||
|
* $Date: 16/12/02 2:01p $
|
||||||
|
* @brief System Setting Source File
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
//#include <arm_cmse.h>
|
||||||
|
#include <stdio.h>
|
||||||
|
#include <stdint.h>
|
||||||
|
#include "M2351.h"
|
||||||
|
|
||||||
|
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||||
|
#include "partition_M2351.h"
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
extern void *__vector_handlers; /* see startup file */
|
||||||
|
extern uint32_t GetPC(void); /* Get current program counter(PC) */
|
||||||
|
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Clock Variable definitions
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
uint32_t SystemCoreClock = __HSI; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
uint32_t CyclesPerUs = (__HSI / 1000000); /*!< Cycles per micro second */
|
||||||
|
uint32_t PllClock = __HSI; /*!< PLL Output Clock Frequency */
|
||||||
|
const uint32_t gau32ClkSrcTbl[] = {__HXT, __LXT, NULL, __LIRC, NULL, NULL, NULL, __HIRC};
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Update the Variable SystemCoreClock
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to update the variable SystemCoreClock
|
||||||
|
* and must be called whenever the core clock is changed.
|
||||||
|
*/
|
||||||
|
void SystemCoreClockUpdate(void)
|
||||||
|
{
|
||||||
|
/* Update PLL Clock */
|
||||||
|
PllClock = CLK_GetPLLClockFreq();
|
||||||
|
|
||||||
|
/* Update System Core Clock */
|
||||||
|
SystemCoreClock = CLK_GetCPUFreq();
|
||||||
|
|
||||||
|
/* Update Cycles per micro second */
|
||||||
|
CyclesPerUs = (SystemCoreClock + 500000) / 1000000;
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System Initialization
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The necessary initialization of system. Global variables are forbidden here.
|
||||||
|
*/
|
||||||
|
void SystemInit(void)
|
||||||
|
{
|
||||||
|
|
||||||
|
#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
|
||||||
|
SCB->VTOR = (uint32_t) &__vector_handlers;
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
|
||||||
|
TZ_SAU_Setup();
|
||||||
|
SCU_Setup();
|
||||||
|
FMC_NSBA_Setup();
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifdef INIT_SYSCLK_AT_BOOTING
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
|
||||||
|
#if USE_ASSERT
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Assert Error Message
|
||||||
|
*
|
||||||
|
* @param[in] file the source file name
|
||||||
|
* @param[in] line line number
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The function prints the source file name and line number where
|
||||||
|
* the ASSERT_PARAM() error occurs, and then stops in an infinite loop.
|
||||||
|
*/
|
||||||
|
void AssertError(uint8_t * file, uint32_t line)
|
||||||
|
{
|
||||||
|
|
||||||
|
printf("[%s] line %d : wrong parameters.\r\n", file, line);
|
||||||
|
|
||||||
|
/* Infinite loop */
|
||||||
|
while(1) ;
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
|
@ -0,0 +1,100 @@
|
||||||
|
/**************************************************************************//**
|
||||||
|
* @file system_M2351.h
|
||||||
|
* @version V3.00
|
||||||
|
* $Revision: 3 $
|
||||||
|
* $Date: 16/07/26 11:17a $
|
||||||
|
* @brief System Setting Header File
|
||||||
|
*
|
||||||
|
* @note
|
||||||
|
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
|
||||||
|
*
|
||||||
|
******************************************************************************/
|
||||||
|
#ifndef __SYSTEM_M2351_H__
|
||||||
|
#define __SYSTEM_M2351_H__
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
/* Macro Definition */
|
||||||
|
/*---------------------------------------------------------------------------------------------------------*/
|
||||||
|
#ifndef DEBUG_PORT
|
||||||
|
# define DEBUG_PORT UART5 /*!< Select Debug Port which is used for retarget.c to output debug message to UART */
|
||||||
|
#endif
|
||||||
|
|
||||||
|
/**
|
||||||
|
*
|
||||||
|
* @details This is used to enable PLL to speed up booting at startup. Remove it will cause system using
|
||||||
|
* default clock source (External crystal or internal 22.1184MHz IRC).
|
||||||
|
* Enable this option will cause system booting in 72MHz(By XTAL) or 71.8848MHz(By IRC22M) according to
|
||||||
|
* user configuration setting in CONFIG0
|
||||||
|
*
|
||||||
|
*/
|
||||||
|
//#define INIT_SYSCLK_AT_BOOTING
|
||||||
|
|
||||||
|
/*----------------------------------------------------------------------------
|
||||||
|
Define SYSCLK
|
||||||
|
*----------------------------------------------------------------------------*/
|
||||||
|
#define __HXT (12000000UL) /*!< External Crystal Clock Frequency */
|
||||||
|
#define __LIRC (10000UL) /*!< Internal 10K RC Oscillator Frequency */
|
||||||
|
#define __HIRC (12000000UL) /*!< Internal 12M RC Oscillator Frequency */
|
||||||
|
#define __LXT (32768UL) /*!< External Crystal Clock Frequency 32.768KHz */
|
||||||
|
#define __HSI (48000000UL) /*!< PLL Output Clock Frequency */
|
||||||
|
|
||||||
|
|
||||||
|
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
|
||||||
|
extern uint32_t CyclesPerUs; /*!< Cycles per micro second */
|
||||||
|
extern uint32_t PllClock; /*!< PLL Output Clock Frequency */
|
||||||
|
extern uint32_t __PC(void); /*!< Return the current program counter value */
|
||||||
|
|
||||||
|
#if USE_ASSERT
|
||||||
|
/**
|
||||||
|
* @brief Assert Function
|
||||||
|
*
|
||||||
|
* @param[in] expr Expression to be evaluated
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details If the expression is false, an error message will be printed out
|
||||||
|
* from debug port (UART0 or UART1).
|
||||||
|
*/
|
||||||
|
#define ASSERT_PARAM(expr) { if (!(expr)) { AssertError((uint8_t*)__FILE__, __LINE__); } }
|
||||||
|
|
||||||
|
void AssertError(uint8_t* file, uint32_t line);
|
||||||
|
#else
|
||||||
|
#define ASSERT_PARAM(expr)
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#define assert_param(expr) ASSERT_PARAM(expr)
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief System Initialization
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details The necessary initialization of system.
|
||||||
|
*/
|
||||||
|
extern void SystemInit(void);
|
||||||
|
|
||||||
|
|
||||||
|
/**
|
||||||
|
* @brief Update the Variable SystemCoreClock
|
||||||
|
*
|
||||||
|
* @param None
|
||||||
|
*
|
||||||
|
* @return None
|
||||||
|
*
|
||||||
|
* @details This function is used to update the variable SystemCoreClock
|
||||||
|
* and must be called whenever the core clock is changed.
|
||||||
|
*/
|
||||||
|
extern void SystemCoreClockUpdate(void);
|
||||||
|
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif /* __SYSTEM_M2351_H__ */
|
||||||
|
|
@ -0,0 +1,86 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2015-2017 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gpio_api.h"
|
||||||
|
#include "mbed_assert.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "mbed_error.h"
|
||||||
|
#include "PeripheralPins.h"
|
||||||
|
|
||||||
|
uint32_t gpio_set(PinName pin)
|
||||||
|
{
|
||||||
|
if (pin == (PinName) NC) {
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
|
||||||
|
|
||||||
|
#if 1
|
||||||
|
pin_function(pin, 0 << NU_MFP_POS(pin_index));
|
||||||
|
#else
|
||||||
|
pinmap_pinout(pin, PinMap_GPIO);
|
||||||
|
#endif
|
||||||
|
|
||||||
|
return (uint32_t)(1 << pin_index); // Return the pin mask
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_init(gpio_t *obj, PinName pin)
|
||||||
|
{
|
||||||
|
obj->pin = pin;
|
||||||
|
|
||||||
|
if (obj->pin == (PinName) NC) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
obj->mask = gpio_set(pin);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_mode(gpio_t *obj, PinMode mode)
|
||||||
|
{
|
||||||
|
if (obj->pin == (PinName) NC) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
pin_mode(obj->pin, mode);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_dir(gpio_t *obj, PinDirection direction)
|
||||||
|
{
|
||||||
|
if (obj->pin == (PinName) NC) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
|
||||||
|
|
||||||
|
uint32_t mode_intern = GPIO_MODE_INPUT;
|
||||||
|
|
||||||
|
switch (direction) {
|
||||||
|
case PIN_INPUT:
|
||||||
|
mode_intern = GPIO_MODE_INPUT;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case PIN_OUTPUT:
|
||||||
|
mode_intern = GPIO_MODE_OUTPUT;
|
||||||
|
break;
|
||||||
|
|
||||||
|
default:
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
|
||||||
|
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,257 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "gpio_irq_api.h"
|
||||||
|
|
||||||
|
#if DEVICE_INTERRUPTIN
|
||||||
|
|
||||||
|
#include "gpio_api.h"
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "PeripheralPins.h"
|
||||||
|
#include "mbed_error.h"
|
||||||
|
#include "nu_bitutil.h"
|
||||||
|
|
||||||
|
#define NU_MAX_PIN_PER_PORT 16
|
||||||
|
|
||||||
|
struct nu_gpio_irq_var {
|
||||||
|
gpio_irq_t * obj_arr[NU_MAX_PIN_PER_PORT];
|
||||||
|
IRQn_Type irq_n;
|
||||||
|
void (*vec)(void);
|
||||||
|
};
|
||||||
|
|
||||||
|
static void gpio_irq_0_vec(void);
|
||||||
|
static void gpio_irq_1_vec(void);
|
||||||
|
static void gpio_irq_2_vec(void);
|
||||||
|
static void gpio_irq_3_vec(void);
|
||||||
|
static void gpio_irq_4_vec(void);
|
||||||
|
static void gpio_irq_5_vec(void);
|
||||||
|
static void gpio_irq_6_vec(void);
|
||||||
|
static void gpio_irq(struct nu_gpio_irq_var *var);
|
||||||
|
|
||||||
|
//EINT0_IRQn
|
||||||
|
static struct nu_gpio_irq_var gpio_irq_var_arr[] = {
|
||||||
|
{{NULL}, GPA_IRQn, gpio_irq_0_vec},
|
||||||
|
{{NULL}, GPB_IRQn, gpio_irq_1_vec},
|
||||||
|
{{NULL}, GPC_IRQn, gpio_irq_2_vec},
|
||||||
|
{{NULL}, GPD_IRQn, gpio_irq_3_vec},
|
||||||
|
{{NULL}, GPE_IRQn, gpio_irq_4_vec},
|
||||||
|
{{NULL}, GPF_IRQn, gpio_irq_5_vec},
|
||||||
|
{{NULL}, GPG_IRQn, gpio_irq_6_vec}
|
||||||
|
};
|
||||||
|
|
||||||
|
#define NU_MAX_PORT (sizeof (gpio_irq_var_arr) / sizeof (gpio_irq_var_arr[0]))
|
||||||
|
|
||||||
|
#ifndef MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||||
|
#define MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_ENABLE 0
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
|
||||||
|
#define MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_ENABLE_LIST NC
|
||||||
|
#endif
|
||||||
|
static PinName gpio_irq_debounce_arr[] = {
|
||||||
|
MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_ENABLE_LIST
|
||||||
|
};
|
||||||
|
|
||||||
|
#ifndef MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE
|
||||||
|
#define MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE GPIO_DBCTL_DBCLKSRC_LIRC
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#ifndef MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE
|
||||||
|
#define MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE GPIO_DBCTL_DBCLKSEL_16
|
||||||
|
#endif
|
||||||
|
|
||||||
|
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
|
||||||
|
{
|
||||||
|
if (pin == NC) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(pin);
|
||||||
|
if (pin_index >= NU_MAX_PIN_PER_PORT || port_index >= NU_MAX_PORT) {
|
||||||
|
return -1;
|
||||||
|
}
|
||||||
|
|
||||||
|
obj->pin = pin;
|
||||||
|
obj->irq_handler = (uint32_t) handler;
|
||||||
|
obj->irq_id = id;
|
||||||
|
|
||||||
|
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
|
||||||
|
//gpio_set(pin);
|
||||||
|
|
||||||
|
{
|
||||||
|
#if MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_ENABLE
|
||||||
|
// Suppress compiler warning
|
||||||
|
(void) gpio_irq_debounce_arr;
|
||||||
|
|
||||||
|
// Configure de-bounce clock source and sampling cycle time
|
||||||
|
GPIO_SET_DEBOUNCE_TIME(gpio_base, MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
|
||||||
|
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||||
|
#else
|
||||||
|
// Enable de-bounce if the pin is in the de-bounce enable list
|
||||||
|
|
||||||
|
// De-bounce defaults to disabled.
|
||||||
|
GPIO_DISABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||||
|
|
||||||
|
PinName *debounce_pos = gpio_irq_debounce_arr;
|
||||||
|
PinName *debounce_end = gpio_irq_debounce_arr + sizeof (gpio_irq_debounce_arr) / sizeof (gpio_irq_debounce_arr[0]);
|
||||||
|
for (; debounce_pos != debounce_end && *debounce_pos != NC; debounce_pos ++) {
|
||||||
|
uint32_t pin_index_debunce = NU_PINNAME_TO_PIN(*debounce_pos);
|
||||||
|
uint32_t port_index_debounce = NU_PINNAME_TO_PORT(*debounce_pos);
|
||||||
|
|
||||||
|
if (pin_index == pin_index_debunce &&
|
||||||
|
port_index == port_index_debounce) {
|
||||||
|
// Configure de-bounce clock source and sampling cycle time
|
||||||
|
GPIO_SET_DEBOUNCE_TIME(gpio_base, MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_CLOCK_SOURCE, MBED_CONF_M2351_GPIO_IRQ_DEBOUNCE_SAMPLE_RATE);
|
||||||
|
GPIO_ENABLE_DEBOUNCE(gpio_base, 1 << pin_index);
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
}
|
||||||
|
|
||||||
|
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
|
||||||
|
|
||||||
|
var->obj_arr[pin_index] = obj;
|
||||||
|
|
||||||
|
// NOTE: InterruptIn requires IRQ enabled by default.
|
||||||
|
gpio_irq_enable(obj);
|
||||||
|
|
||||||
|
return 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_irq_free(gpio_irq_t *obj)
|
||||||
|
{
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
|
||||||
|
|
||||||
|
NVIC_DisableIRQ(var->irq_n);
|
||||||
|
NU_PORT_BASE(port_index)->INTEN = 0;
|
||||||
|
|
||||||
|
MBED_ASSERT(pin_index < NU_MAX_PIN_PER_PORT);
|
||||||
|
var->obj_arr[pin_index] = NULL;
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
|
||||||
|
{
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
|
||||||
|
|
||||||
|
switch (event) {
|
||||||
|
case IRQ_RISE:
|
||||||
|
if (enable) {
|
||||||
|
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_RISING);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
gpio_base->INTEN &= ~(GPIO_INT_RISING << pin_index);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
|
||||||
|
case IRQ_FALL:
|
||||||
|
if (enable) {
|
||||||
|
GPIO_EnableInt(gpio_base, pin_index, GPIO_INT_FALLING);
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
gpio_base->INTEN &= ~(GPIO_INT_FALLING << pin_index);
|
||||||
|
}
|
||||||
|
break;
|
||||||
|
default:
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_irq_enable(gpio_irq_t *obj)
|
||||||
|
{
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
|
||||||
|
|
||||||
|
NVIC_SetVector(var->irq_n, (uint32_t) var->vec);
|
||||||
|
NVIC_EnableIRQ(var->irq_n);
|
||||||
|
}
|
||||||
|
|
||||||
|
void gpio_irq_disable(gpio_irq_t *obj)
|
||||||
|
{
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
struct nu_gpio_irq_var *var = gpio_irq_var_arr + port_index;
|
||||||
|
|
||||||
|
NVIC_DisableIRQ(var->irq_n);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gpio_irq_0_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 0);
|
||||||
|
}
|
||||||
|
static void gpio_irq_1_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 1);
|
||||||
|
}
|
||||||
|
static void gpio_irq_2_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 2);
|
||||||
|
}
|
||||||
|
static void gpio_irq_3_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 3);
|
||||||
|
}
|
||||||
|
static void gpio_irq_4_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 4);
|
||||||
|
}
|
||||||
|
static void gpio_irq_5_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 5);
|
||||||
|
}
|
||||||
|
static void gpio_irq_6_vec(void)
|
||||||
|
{
|
||||||
|
gpio_irq(gpio_irq_var_arr + 6);
|
||||||
|
}
|
||||||
|
|
||||||
|
static void gpio_irq(struct nu_gpio_irq_var *var)
|
||||||
|
{
|
||||||
|
uint32_t port_index = var->irq_n - GPA_IRQn;
|
||||||
|
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
|
||||||
|
|
||||||
|
uint32_t intsrc = gpio_base->INTSRC;
|
||||||
|
uint32_t inten = gpio_base->INTEN;
|
||||||
|
while (intsrc) {
|
||||||
|
int pin_index = nu_ctz(intsrc);
|
||||||
|
gpio_irq_t *obj = var->obj_arr[pin_index];
|
||||||
|
if (inten & (GPIO_INT_RISING << pin_index)) {
|
||||||
|
if (GPIO_PIN_DATA(port_index, pin_index)) {
|
||||||
|
if (obj->irq_handler) {
|
||||||
|
((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_RISE);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
if (inten & (GPIO_INT_FALLING << pin_index)) {
|
||||||
|
if (! GPIO_PIN_DATA(port_index, pin_index)) {
|
||||||
|
if (obj->irq_handler) {
|
||||||
|
((gpio_irq_handler) obj->irq_handler)(obj->irq_id, IRQ_FALL);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
intsrc &= ~(1 << pin_index);
|
||||||
|
}
|
||||||
|
// Clear all interrupt flags
|
||||||
|
gpio_base->INTSRC = gpio_base->INTSRC;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,57 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MBED_GPIO_OBJECT_H
|
||||||
|
#define MBED_GPIO_OBJECT_H
|
||||||
|
|
||||||
|
#include "mbed_assert.h"
|
||||||
|
#include "cmsis.h"
|
||||||
|
#include "PortNames.h"
|
||||||
|
#include "PeripheralNames.h"
|
||||||
|
#include "PinNames.h"
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
extern "C" {
|
||||||
|
#endif
|
||||||
|
|
||||||
|
typedef struct {
|
||||||
|
PinName pin;
|
||||||
|
uint32_t mask;
|
||||||
|
} gpio_t;
|
||||||
|
|
||||||
|
static inline void gpio_write(gpio_t *obj, int value)
|
||||||
|
{
|
||||||
|
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
|
||||||
|
GPIO_PIN_DATA(port_index, pin_index) = value ? 1 : 0;
|
||||||
|
}
|
||||||
|
|
||||||
|
static inline int gpio_read(gpio_t *obj)
|
||||||
|
{
|
||||||
|
MBED_ASSERT(obj->pin != (PinName)NC);
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(obj->pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(obj->pin);
|
||||||
|
|
||||||
|
return (GPIO_PIN_DATA(port_index, pin_index) ? 1 : 0);
|
||||||
|
}
|
||||||
|
|
||||||
|
#ifdef __cplusplus
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,231 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "lp_ticker_api.h"
|
||||||
|
|
||||||
|
#if DEVICE_LOWPOWERTIMER
|
||||||
|
|
||||||
|
#include "sleep_api.h"
|
||||||
|
#include "nu_modutil.h"
|
||||||
|
#include "nu_miscutil.h"
|
||||||
|
#include "mbed_critical.h"
|
||||||
|
|
||||||
|
// lp_ticker tick = us = timestamp
|
||||||
|
#define US_PER_TICK (1)
|
||||||
|
#define US_PER_SEC (1000 * 1000)
|
||||||
|
|
||||||
|
#define US_PER_TMR2_INT (US_PER_SEC * 10) // 10 second per interrupt
|
||||||
|
#define TMR2_CLK_PER_SEC (__LXT)
|
||||||
|
#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC)) // CMPDAT for 10 second
|
||||||
|
#define TMR3_CLK_PER_SEC (__LXT)
|
||||||
|
|
||||||
|
static void tmr2_vec(void);
|
||||||
|
static void tmr3_vec(void);
|
||||||
|
static void lp_ticker_arm_cd(void);
|
||||||
|
|
||||||
|
static int lp_ticker_inited = 0;
|
||||||
|
static volatile uint32_t counter_major = 0;
|
||||||
|
static volatile uint32_t cd_major_minor_clks = 0;
|
||||||
|
static volatile uint32_t cd_minor_clks = 0;
|
||||||
|
static volatile uint32_t wakeup_tick = (uint32_t) -1;
|
||||||
|
|
||||||
|
// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
|
||||||
|
// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
|
||||||
|
static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
|
||||||
|
static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
|
||||||
|
|
||||||
|
#define TMR_CMP_MIN 2
|
||||||
|
#define TMR_CMP_MAX 0xFFFFFFu
|
||||||
|
|
||||||
|
void lp_ticker_init(void)
|
||||||
|
{
|
||||||
|
if (lp_ticker_inited) {
|
||||||
|
return;
|
||||||
|
}
|
||||||
|
lp_ticker_inited = 1;
|
||||||
|
|
||||||
|
counter_major = 0;
|
||||||
|
cd_major_minor_clks = 0;
|
||||||
|
cd_minor_clks = 0;
|
||||||
|
wakeup_tick = (uint32_t) -1;
|
||||||
|
|
||||||
|
// Reset module
|
||||||
|
SYS_ResetModule(timer2_modinit.rsetidx);
|
||||||
|
SYS_ResetModule(timer3_modinit.rsetidx);
|
||||||
|
|
||||||
|
// Select IP clock source
|
||||||
|
CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
|
||||||
|
CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
|
||||||
|
// Enable IP clock
|
||||||
|
CLK_EnableModuleClock(timer2_modinit.clkidx);
|
||||||
|
CLK_EnableModuleClock(timer3_modinit.clkidx);
|
||||||
|
|
||||||
|
// Configure clock
|
||||||
|
uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
|
||||||
|
uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
|
||||||
|
MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
|
||||||
|
MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
|
||||||
|
uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
|
||||||
|
MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
|
||||||
|
// Continuous mode
|
||||||
|
// NOTE: TIMER_CNT is updated continuously by default.
|
||||||
|
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2;
|
||||||
|
((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
|
||||||
|
|
||||||
|
// Set vector
|
||||||
|
NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
|
||||||
|
NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
|
||||||
|
|
||||||
|
NVIC_EnableIRQ(timer2_modinit.irq_n);
|
||||||
|
NVIC_EnableIRQ(timer3_modinit.irq_n);
|
||||||
|
|
||||||
|
TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
|
||||||
|
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
|
||||||
|
|
||||||
|
// NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
|
||||||
|
// timer is not running.
|
||||||
|
|
||||||
|
// Start timer
|
||||||
|
TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
|
||||||
|
|
||||||
|
// Schedule wakeup to match semantics of lp_ticker_get_compare_match()
|
||||||
|
lp_ticker_set_interrupt(wakeup_tick);
|
||||||
|
}
|
||||||
|
|
||||||
|
timestamp_t lp_ticker_read()
|
||||||
|
{
|
||||||
|
if (! lp_ticker_inited) {
|
||||||
|
lp_ticker_init();
|
||||||
|
}
|
||||||
|
|
||||||
|
TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
|
||||||
|
|
||||||
|
do {
|
||||||
|
uint64_t major_minor_clks;
|
||||||
|
uint32_t minor_clks;
|
||||||
|
|
||||||
|
// NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
|
||||||
|
// NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
|
||||||
|
do {
|
||||||
|
core_util_critical_section_enter();
|
||||||
|
|
||||||
|
// NOTE: Order of reading minor_us/carry here is significant.
|
||||||
|
minor_clks = TIMER_GetCounter(timer2_base);
|
||||||
|
uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
|
||||||
|
// When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
|
||||||
|
if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
|
||||||
|
major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
|
||||||
|
}
|
||||||
|
|
||||||
|
core_util_critical_section_exit();
|
||||||
|
}
|
||||||
|
while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
|
||||||
|
|
||||||
|
// Add power-down compensation
|
||||||
|
return ((uint64_t) major_minor_clks * US_PER_SEC / TMR3_CLK_PER_SEC / US_PER_TICK);
|
||||||
|
}
|
||||||
|
while (0);
|
||||||
|
}
|
||||||
|
|
||||||
|
void lp_ticker_set_interrupt(timestamp_t timestamp)
|
||||||
|
{
|
||||||
|
uint32_t now = lp_ticker_read();
|
||||||
|
wakeup_tick = timestamp;
|
||||||
|
|
||||||
|
TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
|
||||||
|
/**
|
||||||
|
* NOTE: Scheduled alarm may go off incorrectly due to wrap around.
|
||||||
|
* Conditions in which delta is negative:
|
||||||
|
* 1. Wrap around
|
||||||
|
* 2. Newly scheduled alarm is behind now
|
||||||
|
*/
|
||||||
|
//int delta = (timestamp > now) ? (timestamp - now) : (uint32_t) ((uint64_t) timestamp + 0xFFFFFFFFu - now);
|
||||||
|
int delta = (int) (timestamp - now);
|
||||||
|
|
||||||
|
if (delta > 0) {
|
||||||
|
cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
|
||||||
|
lp_ticker_arm_cd();
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
cd_major_minor_clks = cd_minor_clks = 0;
|
||||||
|
/**
|
||||||
|
* This event was in the past. Set the interrupt as pending, but don't process it here.
|
||||||
|
* This prevents a recurive loop under heavy load which can lead to a stack overflow.
|
||||||
|
*/
|
||||||
|
NVIC_SetPendingIRQ(timer3_modinit.irq_n);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void lp_ticker_disable_interrupt(void)
|
||||||
|
{
|
||||||
|
TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
}
|
||||||
|
|
||||||
|
void lp_ticker_clear_interrupt(void)
|
||||||
|
{
|
||||||
|
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
}
|
||||||
|
|
||||||
|
static void tmr2_vec(void)
|
||||||
|
{
|
||||||
|
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
|
||||||
|
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
|
||||||
|
counter_major ++;
|
||||||
|
}
|
||||||
|
|
||||||
|
static void tmr3_vec(void)
|
||||||
|
{
|
||||||
|
TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
|
||||||
|
cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
|
||||||
|
if (cd_major_minor_clks == 0) {
|
||||||
|
// NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
|
||||||
|
lp_ticker_irq_handler();
|
||||||
|
}
|
||||||
|
else {
|
||||||
|
lp_ticker_arm_cd();
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
static void lp_ticker_arm_cd(void)
|
||||||
|
{
|
||||||
|
TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
|
||||||
|
|
||||||
|
timer3_base->CNT = 0;
|
||||||
|
while (timer3_base->CNT & TIMER_CNT_RSTACT_Msk);
|
||||||
|
// One-shot mode, Clock = 32 KHz
|
||||||
|
uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
|
||||||
|
MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
|
||||||
|
MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
|
||||||
|
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480/M2351. In M451/M480/M2351, TIMER_CNT is updated continuously by default.
|
||||||
|
timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
|
||||||
|
timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
|
||||||
|
|
||||||
|
cd_minor_clks = cd_major_minor_clks;
|
||||||
|
cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
|
||||||
|
timer3_base->CMP = cd_minor_clks;
|
||||||
|
|
||||||
|
TIMER_EnableInt(timer3_base);
|
||||||
|
TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
|
||||||
|
TIMER_Start(timer3_base);
|
||||||
|
}
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,83 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "mbed_assert.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "PortNames.h"
|
||||||
|
#include "mbed_error.h"
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Configure pin multi-function
|
||||||
|
*/
|
||||||
|
void pin_function(PinName pin, int data)
|
||||||
|
{
|
||||||
|
MBED_ASSERT(pin != (PinName)NC);
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(pin);
|
||||||
|
__IO uint32_t *GPx_MFPx = ((__IO uint32_t *) &SYS->GPA_MFPL) + port_index * 2 + (pin_index / 8);
|
||||||
|
//uint32_t MFP_Pos = NU_MFP_POS(pin_index);
|
||||||
|
uint32_t MFP_Msk = NU_MFP_MSK(pin_index);
|
||||||
|
|
||||||
|
// E.g.: SYS->GPA_MFPL = (SYS->GPA_MFPL & (~SYS_GPA_MFPL_PA0MFP_Msk) ) | SYS_GPA_MFPL_PA0MFP_SC0_CD ;
|
||||||
|
*GPx_MFPx = (*GPx_MFPx & (~MFP_Msk)) | data;
|
||||||
|
|
||||||
|
// [TODO] Disconnect JTAG-DP + SW-DP signals.
|
||||||
|
// Warning: Need to reconnect under reset
|
||||||
|
//if ((pin == PA_13) || (pin == PA_14)) {
|
||||||
|
//
|
||||||
|
//}
|
||||||
|
//if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
|
||||||
|
//
|
||||||
|
//}
|
||||||
|
}
|
||||||
|
|
||||||
|
/**
|
||||||
|
* Configure pin pull-up/pull-down
|
||||||
|
*/
|
||||||
|
void pin_mode(PinName pin, PinMode mode)
|
||||||
|
{
|
||||||
|
MBED_ASSERT(pin != (PinName)NC);
|
||||||
|
uint32_t pin_index = NU_PINNAME_TO_PIN(pin);
|
||||||
|
uint32_t port_index = NU_PINNAME_TO_PORT(pin);
|
||||||
|
GPIO_T *gpio_base = NU_PORT_BASE(port_index);
|
||||||
|
|
||||||
|
uint32_t mode_intern = GPIO_MODE_INPUT;
|
||||||
|
|
||||||
|
switch (mode) {
|
||||||
|
case PullUp:
|
||||||
|
mode_intern = GPIO_MODE_INPUT;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case PullDown:
|
||||||
|
case PullNone:
|
||||||
|
// NOTE: Not support
|
||||||
|
return;
|
||||||
|
|
||||||
|
case PushPull:
|
||||||
|
mode_intern = GPIO_MODE_OUTPUT;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case OpenDrain:
|
||||||
|
mode_intern = GPIO_MODE_OPEN_DRAIN;
|
||||||
|
break;
|
||||||
|
|
||||||
|
case Quasi:
|
||||||
|
mode_intern = GPIO_MODE_QUASI;
|
||||||
|
break;
|
||||||
|
}
|
||||||
|
|
||||||
|
GPIO_SetMode(gpio_base, 1 << pin_index, mode_intern);
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,99 @@
|
||||||
|
/* mbed Microcontroller Library
|
||||||
|
* Copyright (c) 2017-2018 Nuvoton
|
||||||
|
*
|
||||||
|
* Licensed under the Apache License, Version 2.0 (the "License");
|
||||||
|
* you may not use this file except in compliance with the License.
|
||||||
|
* You may obtain a copy of the License at
|
||||||
|
*
|
||||||
|
* http://www.apache.org/licenses/LICENSE-2.0
|
||||||
|
*
|
||||||
|
* Unless required by applicable law or agreed to in writing, software
|
||||||
|
* distributed under the License is distributed on an "AS IS" BASIS,
|
||||||
|
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||||
|
* See the License for the specific language governing permissions and
|
||||||
|
* limitations under the License.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include "port_api.h"
|
||||||
|
#include "gpio_api.h"
|
||||||
|
#include "pinmap.h"
|
||||||
|
#include "mbed_error.h"
|
||||||
|
|
||||||
|
#if DEVICE_PORTIN || DEVICE_PORTOUT || DEVICE_PORTINOUT
|
||||||
|
|
||||||
|
PinName port_pin(PortName port, int pin_n)
|
||||||
|
{
|
||||||
|
return (PinName) NU_PORT_N_PIN_TO_PINNAME(port, pin_n);
|
||||||
|
}
|
||||||
|
|
||||||
|
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
|
||||||
|
{
|
||||||
|
obj->port = port;
|
||||||
|
obj->mask = mask;
|
||||||
|
obj->direction = dir;
|
||||||
|
|
||||||
|
uint32_t i;
|
||||||
|
obj->direction = dir;
|
||||||
|
for (i = 0; i < GPIO_PIN_MAX; i++) {
|
||||||
|
if (obj->mask & (1 << i)) {
|
||||||
|
gpio_set(port_pin(port, i));
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
port_dir(obj, dir);
|
||||||
|
}
|
||||||
|
|
||||||
|
void port_dir(port_t *obj, PinDirection dir)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
obj->direction = dir;
|
||||||
|
for (i = 0; i < GPIO_PIN_MAX; i++) {
|
||||||
|
if (obj->mask & (1 << i)) {
|
||||||
|
if (dir == PIN_OUTPUT) {
|
||||||
|
GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_OUTPUT);
|
||||||
|
} else { // PIN_INPUT
|
||||||
|
GPIO_SetMode(NU_PORT_BASE(obj->port), 1 << i, GPIO_MODE_INPUT);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void port_mode(port_t *obj, PinMode mode)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
|
||||||
|
for (i = 0; i < GPIO_PIN_MAX; i++) {
|
||||||
|
if (obj->mask & (1 << i)) {
|
||||||
|
pin_mode(port_pin(obj->port, i), mode);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
void port_write(port_t *obj, int value)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
uint32_t port_index = obj->port;
|
||||||
|
|
||||||
|
for (i = 0; i < GPIO_PIN_MAX; i++) {
|
||||||
|
if (obj->mask & (1 << i)) {
|
||||||
|
GPIO_PIN_DATA(port_index, i) = (value & obj->mask) ? 1 : 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
int port_read(port_t *obj)
|
||||||
|
{
|
||||||
|
uint32_t i;
|
||||||
|
uint32_t port_index = obj->port;
|
||||||
|
int value = 0;
|
||||||
|
|
||||||
|
for (i = 0; i < GPIO_PIN_MAX; i++) {
|
||||||
|
if (obj->mask & (1 << i)) {
|
||||||
|
value = value | (GPIO_PIN_DATA(port_index, i) << i);
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
return value;
|
||||||
|
}
|
||||||
|
|
||||||
|
#endif
|
||||||
Some files were not shown because too many files have changed in this diff Show More
Loading…
Reference in New Issue