From 948d1a301356f541ce45d8a468e198c9ccd694f3 Mon Sep 17 00:00:00 2001 From: Maciej Bocianski Date: Fri, 3 Aug 2018 09:54:47 +0200 Subject: [PATCH] hal-qspi test: code refactoring --- .../qspi/flash_configs/MX25R6435F_config.h | 16 +++++-- TESTS/mbed_hal/qspi/main.cpp | 44 ++++++++----------- TESTS/mbed_hal/qspi/qspi_test_utils.cpp | 27 ++++++------ 3 files changed, 46 insertions(+), 41 deletions(-) diff --git a/TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h b/TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h index ce426064c8..6cd588d487 100644 --- a/TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h +++ b/TESTS/mbed_hal/qspi/flash_configs/MX25R6435F_config.h @@ -108,10 +108,15 @@ // single quad enable flag for both dual and quad mode -#define QUAD_ENABLE_IMPLEMENTATION() \ +#define QUAD_ENABLE() \ \ uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \ \ + if (write_enable(qspi) != QSPI_STATUS_OK) { \ + return QSPI_STATUS_ERROR; \ + } \ + WAIT_FOR(WRSR_MAX_TIME, qspi); \ + \ reg_data[0] = STATUS_BIT_QE; \ qspi.cmd.build(QSPI_CMD_WRSR); \ \ @@ -132,10 +137,15 @@ -#define QUAD_DISABLE_IMPLEMENTATION() \ +#define QUAD_DISABLE() \ \ uint8_t reg_data[QSPI_STATUS_REG_SIZE]; \ \ + if (write_enable(qspi) != QSPI_STATUS_OK) { \ + return QSPI_STATUS_ERROR; \ + } \ + WAIT_FOR(WRSR_MAX_TIME, qspi); \ + \ reg_data[0] = 0; \ qspi.cmd.build(QSPI_CMD_WRSR); \ \ @@ -156,7 +166,7 @@ -#define FAST_MODE_ENABLE_IMPLEMENTATION() \ +#define FAST_MODE_ENABLE() \ \ qspi_status_t ret; \ const int32_t reg_size = QSPI_STATUS_REG_SIZE + QSPI_CONFIG_REG_0_SIZE; \ diff --git a/TESTS/mbed_hal/qspi/main.cpp b/TESTS/mbed_hal/qspi/main.cpp index 0ef44ee797..cdcfd34899 100644 --- a/TESTS/mbed_hal/qspi/main.cpp +++ b/TESTS/mbed_hal/qspi/main.cpp @@ -71,11 +71,11 @@ uint8_t rx_buf[DATA_SIZE_1024]; static void log_data(const char *str, uint8_t *data, uint32_t size) { - printf("%s: ", str); + utest_printf("%s: ", str); for (uint32_t j = 0; j < size; j++) { - printf("%02X ", data[j]); + utest_printf("%02X ", data[j]); } - printf("\r\n"); + utest_printf("\r\n"); } @@ -171,19 +171,19 @@ static void _qspi_write_read_test(Qspi &qspi, qspi_bus_width_t write_inst_width, if (tx_buf[i] != rx_buf[i]) { log_data("tx data", tx_buf, data_size); log_data("rx data", rx_buf, data_size); - printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time); + utest_printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time); TEST_ASSERT_EQUAL(tx_buf[i], rx_buf[i]); } } #ifdef QSPI_TEST_LOG_FLASH_TIME - printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time); + utest_printf("erase/write/read time: %d/%d/%d [us]\r\n", erase_time, write_time, read_time); #endif #ifdef QSPI_TEST_LOG_DATA log_data("tx data", tx_buf, data_size); log_data("rx data", rx_buf, data_size); - printf("rx/tx data match\r\n"); + utest_printf("rx/tx data match\r\n"); #endif } } @@ -222,9 +222,6 @@ void qspi_write_read_test(void) if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) || is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) { - ret = write_enable(qspi); - TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); - WAIT_FOR(WRSR_MAX_TIME, qspi); ret = dual_enable(qspi); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); WAIT_FOR(WRSR_MAX_TIME, qspi); @@ -232,9 +229,6 @@ void qspi_write_read_test(void) if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) || is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) { - ret = write_enable(qspi); - TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); - WAIT_FOR(WRSR_MAX_TIME, qspi); ret = quad_enable(qspi); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); WAIT_FOR(WRSR_MAX_TIME, qspi); @@ -248,10 +242,13 @@ void qspi_write_read_test(void) WAIT_FOR(WRSR_MAX_TIME, qspi); #ifdef QSPI_TEST_LOG_FLASH_STATUS - printf("Status "); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi); - printf("Config 0 "); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi); + utest_printf("Status\r\n"); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi); + utest_printf("Config 0\r\n"); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi); #ifdef CONFIG_REG1 - printf("Config 1 "); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi); + utest_printf("Config 1\r\n"); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi); +#endif +#ifdef CONFIG_REG2 + utest_printf("Config 2\r\n"); log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi); #endif #endif @@ -265,9 +262,6 @@ void qspi_write_read_test(void) if (is_dual_cmd(write_inst_width, write_addr_width, write_data_width) || is_dual_cmd(read_inst_width, read_addr_width, read_data_width)) { - ret = write_enable(qspi); - TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); - WAIT_FOR(WRSR_MAX_TIME, qspi); ret = dual_disable(qspi); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); WAIT_FOR(WRSR_MAX_TIME, qspi); @@ -275,9 +269,6 @@ void qspi_write_read_test(void) if (is_quad_cmd(write_inst_width, write_addr_width, write_data_width) || is_quad_cmd(read_inst_width, read_addr_width, read_data_width)) { - ret = write_enable(qspi); - TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); - WAIT_FOR(WRSR_MAX_TIME, qspi); ret = quad_disable(qspi); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); WAIT_FOR(WRSR_MAX_TIME, qspi); @@ -321,10 +312,13 @@ void qspi_init_free_test(void) flash_init(qspi); #ifdef QSPI_TEST_LOG_FLASH_STATUS - printf("Status "); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi); - printf("Config 0 "); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi); + utest_printf("Status\r\n"); log_register(STATUS_REG, QSPI_STATUS_REG_SIZE, qspi); + utest_printf("Config 0\r\n"); log_register(CONFIG_REG0, QSPI_CONFIG_REG_0_SIZE, qspi); #ifdef CONFIG_REG1 - printf("Config 1 "); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi); + utest_printf("Config 1\r\n"); log_register(CONFIG_REG1, QSPI_CONFIG_REG_1_SIZE, qspi); +#endif +#ifdef CONFIG_REG2 + utest_printf("Config 2\r\n"); log_register(CONFIG_REG2, QSPI_CONFIG_REG_2_SIZE, qspi); #endif #endif @@ -375,7 +369,7 @@ void qspi_frequency_test(void) void qspi_memory_id_test() { - printf("*** %s memory config loaded ***\r\n", QSPI_FLASH_CHIP_STRING); + utest_printf("*** %s memory config loaded ***\r\n", QSPI_FLASH_CHIP_STRING); } diff --git a/TESTS/mbed_hal/qspi/qspi_test_utils.cpp b/TESTS/mbed_hal/qspi/qspi_test_utils.cpp index 8339d38edb..76d7a9fd48 100644 --- a/TESTS/mbed_hal/qspi/qspi_test_utils.cpp +++ b/TESTS/mbed_hal/qspi/qspi_test_utils.cpp @@ -14,6 +14,7 @@ * limitations under the License. */ +#include "utest/utest.h" #include "hal/qspi_api.h" #include "qspi_test_utils.h" @@ -166,12 +167,12 @@ void log_register(uint32_t cmd, uint32_t reg_size, Qspi &qspi) ret = read_register(cmd, reg, reg_size, qspi); TEST_ASSERT_EQUAL(QSPI_STATUS_OK, ret); - for (int j = 0; j < reg_size; j++) { - printf("register byte %d data: ", j); + for (uint32_t j = 0; j < reg_size; j++) { + utest_printf("register byte %u data: ", j); for(int i = 0; i < 8; i++) { - printf("%s ", ((reg[j] & (1 << i)) & 0xFF) == 0 ? "0" : "1"); + utest_printf("%s ", ((reg[j] & (1 << i)) & 0xFF) == 0 ? "0" : "1"); } - printf("\r\n"); + utest_printf("\r\n"); } } @@ -183,36 +184,36 @@ qspi_status_t erase(uint32_t erase_cmd, uint32_t flash_addr, Qspi &qspi) qspi_status_t dual_enable(Qspi &qspi) { -#ifdef DUAL_ENABLE_IMPLEMENTATION - DUAL_ENABLE_IMPLEMENTATION(); +#ifdef DUAL_ENABLE + DUAL_ENABLE(); #else - QUAD_ENABLE_IMPLEMENTATION(); + QUAD_ENABLE(); #endif } qspi_status_t dual_disable(Qspi &qspi) { -#ifdef DUAL_DISABLE_IMPLEMENTATION - DUAL_DISABLE_IMPLEMENTATION(); +#ifdef DUAL_DISABLE + DUAL_DISABLE(); #else - QUAD_DISABLE_IMPLEMENTATION(); + QUAD_DISABLE(); #endif } qspi_status_t quad_enable(Qspi &qspi) { - QUAD_ENABLE_IMPLEMENTATION(); + QUAD_ENABLE(); } qspi_status_t quad_disable(Qspi &qspi) { - QUAD_DISABLE_IMPLEMENTATION(); + QUAD_DISABLE(); } qspi_status_t fast_mode_enable(Qspi &qspi) { - FAST_MODE_ENABLE_IMPLEMENTATION(); + FAST_MODE_ENABLE(); } bool is_dual_cmd(qspi_bus_width_t inst_width, qspi_bus_width_t addr_width, qspi_bus_width_t data_width)