Refine M487 USBD code and build M263A successfully

pull/12176/head
cyliangtw 2019-11-18 20:05:49 +08:00
parent 9b721bf327
commit 93fbef2cde
2 changed files with 32 additions and 28 deletions

View File

@ -20,16 +20,13 @@
static USBPhyHw *instance;
//#undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD
//#define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 1 /* USB 1.1 Only */
#if defined (TARGET_M451)
#undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD
#define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 0 /* USB 1.1 Only */
#elif defined (TARGET_M2351)
#elif defined (TARGET_M2351) || defined(TARGET_M261)
#undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD
#define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 0 /* USB 1.1 Only */
#define USBD_SET_ADDRESS 0x05ul
#elif defined (TARGET_NANO100)
#undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD
#define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 0 /* USB 1.1 Only */
@ -38,8 +35,7 @@ static USBPhyHw *instance;
#undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD
#define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 1 /* USB 2.0 Only */
#endif
#undef MBED_CONF_TARGET_USB_DEVICE_HSUSBD
#define MBED_CONF_TARGET_USB_DEVICE_HSUSBD 0 /* USB 1.1 Only */
void chip_config(void)
{
#if defined(TARGET_M451)
@ -83,7 +79,7 @@ void chip_config(void)
CLK_EnableModuleClock(HSUSBD_MODULE);
#endif
#elif defined (TARGET_M2351)
#elif defined (TARGET_M2351) || defined(TARGET_M261)
/* Select USBD */
SYS->USBPHY = (SYS->USBPHY & ~SYS_USBPHY_USBROLE_Msk) | SYS_USBPHY_OTGPHYEN_Msk | SYS_USBPHY_SBO_Msk;
@ -92,7 +88,7 @@ void chip_config(void)
CLK_EnableModuleClock(USBD_MODULE);
/* Select IP clock source */
CLK_SetModuleClock(UART0_MODULE, CLK_CLKSEL1_UART0SEL_HIRC, CLK_CLKDIV0_UART0(1));
CLK_SetModuleClock(USBD_MODULE, CLK_CLKSEL0_USBSEL_HIRC48, CLK_CLKDIV0_USB(1));
/* USBD multi-function pins for VBUS, D+, D-, and ID pins */
SYS->GPA_MFPH &= ~(SYS_GPA_MFPH_PA12MFP_Msk | SYS_GPA_MFPH_PA13MFP_Msk | SYS_GPA_MFPH_PA14MFP_Msk | SYS_GPA_MFPH_PA15MFP_Msk);
@ -126,7 +122,12 @@ void chip_config(void)
#define HW_TO_DESC(endpoint) (endpoint|(((endpoint&1)?0x0:0x80)))
/* Global variables for Control Pipe */
#if defined(TARGET_M261)
extern uint8_t g_USBD_au8SetupPacket[]; /*!< Setup packet buffer */
uint8_t* g_usbd_SetupPacket=g_USBD_au8SetupPacket;
#else
extern uint8_t g_usbd_SetupPacket[]; /*!< Setup packet buffer */
#endif
static volatile uint32_t s_ep_compl = 0;
static volatile uint32_t s_ep_buf_ind = 8;
static volatile uint32_t s_ep0_max_packet_size = 8;
@ -671,9 +672,12 @@ void USBPhyHw::process()
USBD_CLR_INT_FLAG(USBD_INTSTS_EP0);
/* control IN */
events->ep0_in();
/* In ACK for Set address */
#if defined(TARGET_M480) || defined(TARGET_M451)
if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == USBD_SET_ADDRESS))
#else
if((g_usbd_SetupPacket[0] == REQ_STANDARD) && (g_usbd_SetupPacket[1] == SET_ADDRESS))
#endif
{
if((USBD_GET_ADDR() != s_usb_addr) && (USBD_GET_ADDR() == 0))
{
@ -704,7 +708,7 @@ void USBPhyHw::process()
ep_status = (USBD->EPSTS >> (ep_hw_index * 4) + 8) & 0x7;
else
ep_status = (USBD->EPSTS2 >> ((ep_hw_index - 4) * 4)) & 0x7;
#elif defined(TARGET_M480) || defined(TARGET_M2351)
#elif defined(TARGET_M480) || defined(TARGET_M2351) || defined(TARGET_M261)
if(ep_hw_index < 8)
ep_status = (USBD->EPSTS0 >> (ep_hw_index * 4)) & 0x7;
else

View File

@ -25,7 +25,7 @@
#define NUMBER_OF_LOGICAL_ENDPOINTS (12)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#endif
#elif defined (TARGET_M2351)
#elif defined (TARGET_M2351) || defined(TARGET_M261)
#define NUMBER_OF_LOGICAL_ENDPOINTS (12)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS)
#elif defined (TARGET_NANO100)