mirror of https://github.com/ARMmbed/mbed-os.git
K64F: Updated the SYSMPU SDK driver
This is required to setup the MPU for ENET bus master accesses Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>pull/6847/head
Mahesh Mahadevan
Kevin Bracey
parent
de72090d26
commit
93f8cfed05
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@ -8275,252 +8275,6 @@ typedef struct {
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*/ /* end of group MCM_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- MPU Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
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* @{
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*/
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/** MPU - Register Layout Typedef */
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typedef struct {
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__IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
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uint8_t RESERVED_0[12];
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struct { /* offset: 0x10, array step: 0x8 */
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__I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
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__I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
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} SP[5];
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uint8_t RESERVED_1[968];
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__IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
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uint8_t RESERVED_2[832];
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__IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
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} MPU_Type;
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/* ----------------------------------------------------------------------------
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-- MPU Register Masks
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup MPU_Register_Masks MPU Register Masks
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* @{
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*/
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/*! @name CESR - Control/Error Status Register */
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#define MPU_CESR_VLD_MASK (0x1U)
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#define MPU_CESR_VLD_SHIFT (0U)
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#define MPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_VLD_SHIFT)) & MPU_CESR_VLD_MASK)
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#define MPU_CESR_NRGD_MASK (0xF00U)
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#define MPU_CESR_NRGD_SHIFT (8U)
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#define MPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
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#define MPU_CESR_NSP_MASK (0xF000U)
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#define MPU_CESR_NSP_SHIFT (12U)
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#define MPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
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#define MPU_CESR_HRL_MASK (0xF0000U)
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#define MPU_CESR_HRL_SHIFT (16U)
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#define MPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
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#define MPU_CESR_SPERR_MASK (0xF8000000U)
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#define MPU_CESR_SPERR_SHIFT (27U)
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#define MPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
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/*! @name EAR - Error Address Register, slave port n */
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#define MPU_EAR_EADDR_MASK (0xFFFFFFFFU)
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#define MPU_EAR_EADDR_SHIFT (0U)
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#define MPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EAR_EADDR_SHIFT)) & MPU_EAR_EADDR_MASK)
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/* The count of MPU_EAR */
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#define MPU_EAR_COUNT (5U)
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/*! @name EDR - Error Detail Register, slave port n */
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#define MPU_EDR_ERW_MASK (0x1U)
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#define MPU_EDR_ERW_SHIFT (0U)
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#define MPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_ERW_SHIFT)) & MPU_EDR_ERW_MASK)
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#define MPU_EDR_EATTR_MASK (0xEU)
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#define MPU_EDR_EATTR_SHIFT (1U)
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#define MPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
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#define MPU_EDR_EMN_MASK (0xF0U)
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#define MPU_EDR_EMN_SHIFT (4U)
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#define MPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
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#define MPU_EDR_EPID_MASK (0xFF00U)
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#define MPU_EDR_EPID_SHIFT (8U)
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#define MPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
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#define MPU_EDR_EACD_MASK (0xFFFF0000U)
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#define MPU_EDR_EACD_SHIFT (16U)
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#define MPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
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/* The count of MPU_EDR */
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#define MPU_EDR_COUNT (5U)
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/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
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#define MPU_WORD_VLD_MASK (0x1U)
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#define MPU_WORD_VLD_SHIFT (0U)
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#define MPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_VLD_SHIFT)) & MPU_WORD_VLD_MASK)
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#define MPU_WORD_M0UM_MASK (0x7U)
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#define MPU_WORD_M0UM_SHIFT (0U)
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#define MPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
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#define MPU_WORD_M0SM_MASK (0x18U)
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#define MPU_WORD_M0SM_SHIFT (3U)
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#define MPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
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#define MPU_WORD_M0PE_MASK (0x20U)
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#define MPU_WORD_M0PE_SHIFT (5U)
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#define MPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0PE_SHIFT)) & MPU_WORD_M0PE_MASK)
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#define MPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
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#define MPU_WORD_ENDADDR_SHIFT (5U)
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#define MPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
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#define MPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
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#define MPU_WORD_SRTADDR_SHIFT (5U)
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#define MPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
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#define MPU_WORD_M1UM_MASK (0x1C0U)
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#define MPU_WORD_M1UM_SHIFT (6U)
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#define MPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
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#define MPU_WORD_M1SM_MASK (0x600U)
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#define MPU_WORD_M1SM_SHIFT (9U)
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#define MPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
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#define MPU_WORD_M1PE_MASK (0x800U)
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#define MPU_WORD_M1PE_SHIFT (11U)
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#define MPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1PE_SHIFT)) & MPU_WORD_M1PE_MASK)
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#define MPU_WORD_M2UM_MASK (0x7000U)
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#define MPU_WORD_M2UM_SHIFT (12U)
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#define MPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
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#define MPU_WORD_M2SM_MASK (0x18000U)
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#define MPU_WORD_M2SM_SHIFT (15U)
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#define MPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
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#define MPU_WORD_PIDMASK_MASK (0xFF0000U)
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#define MPU_WORD_PIDMASK_SHIFT (16U)
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#define MPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
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#define MPU_WORD_M2PE_MASK (0x20000U)
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#define MPU_WORD_M2PE_SHIFT (17U)
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#define MPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2PE_SHIFT)) & MPU_WORD_M2PE_MASK)
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#define MPU_WORD_M3UM_MASK (0x1C0000U)
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#define MPU_WORD_M3UM_SHIFT (18U)
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#define MPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
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#define MPU_WORD_M3SM_MASK (0x600000U)
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#define MPU_WORD_M3SM_SHIFT (21U)
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#define MPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
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#define MPU_WORD_M3PE_MASK (0x800000U)
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#define MPU_WORD_M3PE_SHIFT (23U)
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#define MPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3PE_SHIFT)) & MPU_WORD_M3PE_MASK)
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#define MPU_WORD_PID_MASK (0xFF000000U)
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#define MPU_WORD_PID_SHIFT (24U)
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#define MPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
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#define MPU_WORD_M4WE_MASK (0x1000000U)
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#define MPU_WORD_M4WE_SHIFT (24U)
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#define MPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4WE_SHIFT)) & MPU_WORD_M4WE_MASK)
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#define MPU_WORD_M4RE_MASK (0x2000000U)
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#define MPU_WORD_M4RE_SHIFT (25U)
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#define MPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M4RE_SHIFT)) & MPU_WORD_M4RE_MASK)
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#define MPU_WORD_M5WE_MASK (0x4000000U)
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#define MPU_WORD_M5WE_SHIFT (26U)
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#define MPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5WE_SHIFT)) & MPU_WORD_M5WE_MASK)
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#define MPU_WORD_M5RE_MASK (0x8000000U)
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#define MPU_WORD_M5RE_SHIFT (27U)
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#define MPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M5RE_SHIFT)) & MPU_WORD_M5RE_MASK)
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#define MPU_WORD_M6WE_MASK (0x10000000U)
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#define MPU_WORD_M6WE_SHIFT (28U)
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#define MPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6WE_SHIFT)) & MPU_WORD_M6WE_MASK)
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#define MPU_WORD_M6RE_MASK (0x20000000U)
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#define MPU_WORD_M6RE_SHIFT (29U)
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#define MPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M6RE_SHIFT)) & MPU_WORD_M6RE_MASK)
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#define MPU_WORD_M7WE_MASK (0x40000000U)
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#define MPU_WORD_M7WE_SHIFT (30U)
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#define MPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7WE_SHIFT)) & MPU_WORD_M7WE_MASK)
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#define MPU_WORD_M7RE_MASK (0x80000000U)
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#define MPU_WORD_M7RE_SHIFT (31U)
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#define MPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M7RE_SHIFT)) & MPU_WORD_M7RE_MASK)
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/* The count of MPU_WORD */
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#define MPU_WORD_COUNT (12U)
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/* The count of MPU_WORD */
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#define MPU_WORD_COUNT2 (4U)
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/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
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#define MPU_RGDAAC_M0UM_MASK (0x7U)
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#define MPU_RGDAAC_M0UM_SHIFT (0U)
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#define MPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
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#define MPU_RGDAAC_M0SM_MASK (0x18U)
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#define MPU_RGDAAC_M0SM_SHIFT (3U)
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#define MPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
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#define MPU_RGDAAC_M0PE_MASK (0x20U)
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#define MPU_RGDAAC_M0PE_SHIFT (5U)
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#define MPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0PE_SHIFT)) & MPU_RGDAAC_M0PE_MASK)
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#define MPU_RGDAAC_M1UM_MASK (0x1C0U)
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#define MPU_RGDAAC_M1UM_SHIFT (6U)
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#define MPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
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#define MPU_RGDAAC_M1SM_MASK (0x600U)
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#define MPU_RGDAAC_M1SM_SHIFT (9U)
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#define MPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
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#define MPU_RGDAAC_M1PE_MASK (0x800U)
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#define MPU_RGDAAC_M1PE_SHIFT (11U)
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#define MPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1PE_SHIFT)) & MPU_RGDAAC_M1PE_MASK)
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#define MPU_RGDAAC_M2UM_MASK (0x7000U)
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#define MPU_RGDAAC_M2UM_SHIFT (12U)
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#define MPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
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#define MPU_RGDAAC_M2SM_MASK (0x18000U)
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#define MPU_RGDAAC_M2SM_SHIFT (15U)
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#define MPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
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#define MPU_RGDAAC_M2PE_MASK (0x20000U)
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#define MPU_RGDAAC_M2PE_SHIFT (17U)
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#define MPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2PE_SHIFT)) & MPU_RGDAAC_M2PE_MASK)
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#define MPU_RGDAAC_M3UM_MASK (0x1C0000U)
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#define MPU_RGDAAC_M3UM_SHIFT (18U)
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#define MPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
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#define MPU_RGDAAC_M3SM_MASK (0x600000U)
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#define MPU_RGDAAC_M3SM_SHIFT (21U)
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#define MPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
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#define MPU_RGDAAC_M3PE_MASK (0x800000U)
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#define MPU_RGDAAC_M3PE_SHIFT (23U)
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#define MPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3PE_SHIFT)) & MPU_RGDAAC_M3PE_MASK)
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#define MPU_RGDAAC_M4WE_MASK (0x1000000U)
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#define MPU_RGDAAC_M4WE_SHIFT (24U)
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#define MPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4WE_SHIFT)) & MPU_RGDAAC_M4WE_MASK)
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#define MPU_RGDAAC_M4RE_MASK (0x2000000U)
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#define MPU_RGDAAC_M4RE_SHIFT (25U)
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#define MPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M4RE_SHIFT)) & MPU_RGDAAC_M4RE_MASK)
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#define MPU_RGDAAC_M5WE_MASK (0x4000000U)
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#define MPU_RGDAAC_M5WE_SHIFT (26U)
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#define MPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5WE_SHIFT)) & MPU_RGDAAC_M5WE_MASK)
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#define MPU_RGDAAC_M5RE_MASK (0x8000000U)
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#define MPU_RGDAAC_M5RE_SHIFT (27U)
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#define MPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M5RE_SHIFT)) & MPU_RGDAAC_M5RE_MASK)
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#define MPU_RGDAAC_M6WE_MASK (0x10000000U)
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#define MPU_RGDAAC_M6WE_SHIFT (28U)
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#define MPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6WE_SHIFT)) & MPU_RGDAAC_M6WE_MASK)
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#define MPU_RGDAAC_M6RE_MASK (0x20000000U)
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#define MPU_RGDAAC_M6RE_SHIFT (29U)
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#define MPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M6RE_SHIFT)) & MPU_RGDAAC_M6RE_MASK)
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#define MPU_RGDAAC_M7WE_MASK (0x40000000U)
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#define MPU_RGDAAC_M7WE_SHIFT (30U)
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#define MPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7WE_SHIFT)) & MPU_RGDAAC_M7WE_MASK)
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#define MPU_RGDAAC_M7RE_MASK (0x80000000U)
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#define MPU_RGDAAC_M7RE_SHIFT (31U)
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#define MPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M7RE_SHIFT)) & MPU_RGDAAC_M7RE_MASK)
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/* The count of MPU_RGDAAC */
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#define MPU_RGDAAC_COUNT (12U)
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/*!
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* @}
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*/ /* end of group MPU_Register_Masks */
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/* MPU - Peripheral instance base addresses */
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/** Peripheral MPU base address */
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#define MPU_BASE (0x4000D000u)
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/** Peripheral MPU base pointer */
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#define MPU ((MPU_Type *)MPU_BASE)
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/** Array initializer of MPU peripheral base addresses */
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#define MPU_BASE_ADDRS { MPU_BASE }
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/** Array initializer of MPU peripheral base pointers */
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#define MPU_BASE_PTRS { MPU }
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/*!
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* @}
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*/ /* end of group MPU_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- NV Peripheral Access Layer
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---------------------------------------------------------------------------- */
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@ -11285,6 +11039,252 @@ typedef struct {
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*/ /* end of group SPI_Peripheral_Access_Layer */
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/* ----------------------------------------------------------------------------
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-- SYSMPU Peripheral Access Layer
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---------------------------------------------------------------------------- */
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/*!
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* @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
|
||||
* @{
|
||||
*/
|
||||
|
||||
/** SYSMPU - Register Layout Typedef */
|
||||
typedef struct {
|
||||
__IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
|
||||
uint8_t RESERVED_0[12];
|
||||
struct { /* offset: 0x10, array step: 0x8 */
|
||||
__I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
|
||||
__I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
|
||||
} SP[5];
|
||||
uint8_t RESERVED_1[968];
|
||||
__IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
|
||||
uint8_t RESERVED_2[832];
|
||||
__IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
|
||||
} SYSMPU_Type;
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- SYSMPU Register Masks
|
||||
---------------------------------------------------------------------------- */
|
||||
|
||||
/*!
|
||||
* @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*! @name CESR - Control/Error Status Register */
|
||||
#define SYSMPU_CESR_VLD_MASK (0x1U)
|
||||
#define SYSMPU_CESR_VLD_SHIFT (0U)
|
||||
#define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
|
||||
#define SYSMPU_CESR_NRGD_MASK (0xF00U)
|
||||
#define SYSMPU_CESR_NRGD_SHIFT (8U)
|
||||
#define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
|
||||
#define SYSMPU_CESR_NSP_MASK (0xF000U)
|
||||
#define SYSMPU_CESR_NSP_SHIFT (12U)
|
||||
#define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
|
||||
#define SYSMPU_CESR_HRL_MASK (0xF0000U)
|
||||
#define SYSMPU_CESR_HRL_SHIFT (16U)
|
||||
#define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
|
||||
#define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
|
||||
#define SYSMPU_CESR_SPERR_SHIFT (27U)
|
||||
#define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
|
||||
|
||||
/*! @name EAR - Error Address Register, slave port n */
|
||||
#define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
|
||||
#define SYSMPU_EAR_EADDR_SHIFT (0U)
|
||||
#define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
|
||||
|
||||
/* The count of SYSMPU_EAR */
|
||||
#define SYSMPU_EAR_COUNT (5U)
|
||||
|
||||
/*! @name EDR - Error Detail Register, slave port n */
|
||||
#define SYSMPU_EDR_ERW_MASK (0x1U)
|
||||
#define SYSMPU_EDR_ERW_SHIFT (0U)
|
||||
#define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
|
||||
#define SYSMPU_EDR_EATTR_MASK (0xEU)
|
||||
#define SYSMPU_EDR_EATTR_SHIFT (1U)
|
||||
#define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
|
||||
#define SYSMPU_EDR_EMN_MASK (0xF0U)
|
||||
#define SYSMPU_EDR_EMN_SHIFT (4U)
|
||||
#define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
|
||||
#define SYSMPU_EDR_EPID_MASK (0xFF00U)
|
||||
#define SYSMPU_EDR_EPID_SHIFT (8U)
|
||||
#define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
|
||||
#define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
|
||||
#define SYSMPU_EDR_EACD_SHIFT (16U)
|
||||
#define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
|
||||
|
||||
/* The count of SYSMPU_EDR */
|
||||
#define SYSMPU_EDR_COUNT (5U)
|
||||
|
||||
/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
|
||||
#define SYSMPU_WORD_VLD_MASK (0x1U)
|
||||
#define SYSMPU_WORD_VLD_SHIFT (0U)
|
||||
#define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
|
||||
#define SYSMPU_WORD_M0UM_MASK (0x7U)
|
||||
#define SYSMPU_WORD_M0UM_SHIFT (0U)
|
||||
#define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
|
||||
#define SYSMPU_WORD_M0SM_MASK (0x18U)
|
||||
#define SYSMPU_WORD_M0SM_SHIFT (3U)
|
||||
#define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
|
||||
#define SYSMPU_WORD_M0PE_MASK (0x20U)
|
||||
#define SYSMPU_WORD_M0PE_SHIFT (5U)
|
||||
#define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
|
||||
#define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
|
||||
#define SYSMPU_WORD_ENDADDR_SHIFT (5U)
|
||||
#define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
|
||||
#define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
|
||||
#define SYSMPU_WORD_SRTADDR_SHIFT (5U)
|
||||
#define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
|
||||
#define SYSMPU_WORD_M1UM_MASK (0x1C0U)
|
||||
#define SYSMPU_WORD_M1UM_SHIFT (6U)
|
||||
#define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
|
||||
#define SYSMPU_WORD_M1SM_MASK (0x600U)
|
||||
#define SYSMPU_WORD_M1SM_SHIFT (9U)
|
||||
#define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
|
||||
#define SYSMPU_WORD_M1PE_MASK (0x800U)
|
||||
#define SYSMPU_WORD_M1PE_SHIFT (11U)
|
||||
#define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
|
||||
#define SYSMPU_WORD_M2UM_MASK (0x7000U)
|
||||
#define SYSMPU_WORD_M2UM_SHIFT (12U)
|
||||
#define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
|
||||
#define SYSMPU_WORD_M2SM_MASK (0x18000U)
|
||||
#define SYSMPU_WORD_M2SM_SHIFT (15U)
|
||||
#define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
|
||||
#define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
|
||||
#define SYSMPU_WORD_PIDMASK_SHIFT (16U)
|
||||
#define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
|
||||
#define SYSMPU_WORD_M2PE_MASK (0x20000U)
|
||||
#define SYSMPU_WORD_M2PE_SHIFT (17U)
|
||||
#define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
|
||||
#define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
|
||||
#define SYSMPU_WORD_M3UM_SHIFT (18U)
|
||||
#define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
|
||||
#define SYSMPU_WORD_M3SM_MASK (0x600000U)
|
||||
#define SYSMPU_WORD_M3SM_SHIFT (21U)
|
||||
#define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
|
||||
#define SYSMPU_WORD_M3PE_MASK (0x800000U)
|
||||
#define SYSMPU_WORD_M3PE_SHIFT (23U)
|
||||
#define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
|
||||
#define SYSMPU_WORD_PID_MASK (0xFF000000U)
|
||||
#define SYSMPU_WORD_PID_SHIFT (24U)
|
||||
#define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
|
||||
#define SYSMPU_WORD_M4WE_MASK (0x1000000U)
|
||||
#define SYSMPU_WORD_M4WE_SHIFT (24U)
|
||||
#define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
|
||||
#define SYSMPU_WORD_M4RE_MASK (0x2000000U)
|
||||
#define SYSMPU_WORD_M4RE_SHIFT (25U)
|
||||
#define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
|
||||
#define SYSMPU_WORD_M5WE_MASK (0x4000000U)
|
||||
#define SYSMPU_WORD_M5WE_SHIFT (26U)
|
||||
#define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
|
||||
#define SYSMPU_WORD_M5RE_MASK (0x8000000U)
|
||||
#define SYSMPU_WORD_M5RE_SHIFT (27U)
|
||||
#define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
|
||||
#define SYSMPU_WORD_M6WE_MASK (0x10000000U)
|
||||
#define SYSMPU_WORD_M6WE_SHIFT (28U)
|
||||
#define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
|
||||
#define SYSMPU_WORD_M6RE_MASK (0x20000000U)
|
||||
#define SYSMPU_WORD_M6RE_SHIFT (29U)
|
||||
#define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
|
||||
#define SYSMPU_WORD_M7WE_MASK (0x40000000U)
|
||||
#define SYSMPU_WORD_M7WE_SHIFT (30U)
|
||||
#define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
|
||||
#define SYSMPU_WORD_M7RE_MASK (0x80000000U)
|
||||
#define SYSMPU_WORD_M7RE_SHIFT (31U)
|
||||
#define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
|
||||
|
||||
/* The count of SYSMPU_WORD */
|
||||
#define SYSMPU_WORD_COUNT (12U)
|
||||
|
||||
/* The count of SYSMPU_WORD */
|
||||
#define SYSMPU_WORD_COUNT2 (4U)
|
||||
|
||||
/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
|
||||
#define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
|
||||
#define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
|
||||
#define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
|
||||
#define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
|
||||
#define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
|
||||
#define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
|
||||
#define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
|
||||
#define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
|
||||
#define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
|
||||
#define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
|
||||
#define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
|
||||
#define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
|
||||
#define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
|
||||
#define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
|
||||
#define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
|
||||
#define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
|
||||
#define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
|
||||
#define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
|
||||
#define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
|
||||
#define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
|
||||
#define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
|
||||
#define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
|
||||
#define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
|
||||
#define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
|
||||
#define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
|
||||
#define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
|
||||
#define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
|
||||
#define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
|
||||
#define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
|
||||
#define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
|
||||
#define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
|
||||
#define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
|
||||
#define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
|
||||
#define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
|
||||
#define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
|
||||
#define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
|
||||
#define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
|
||||
#define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
|
||||
#define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
|
||||
#define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
|
||||
#define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
|
||||
#define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
|
||||
#define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
|
||||
#define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
|
||||
#define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
|
||||
#define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
|
||||
#define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
|
||||
#define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
|
||||
#define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
|
||||
#define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
|
||||
#define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
|
||||
#define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
|
||||
#define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
|
||||
#define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
|
||||
#define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
|
||||
#define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
|
||||
#define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
|
||||
#define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
|
||||
#define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
|
||||
#define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
|
||||
|
||||
/* The count of SYSMPU_RGDAAC */
|
||||
#define SYSMPU_RGDAAC_COUNT (12U)
|
||||
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/ /* end of group SYSMPU_Register_Masks */
|
||||
|
||||
|
||||
/* SYSMPU - Peripheral instance base addresses */
|
||||
/** Peripheral SYSMPU base address */
|
||||
#define SYSMPU_BASE (0x4000D000u)
|
||||
/** Peripheral SYSMPU base pointer */
|
||||
#define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
|
||||
/** Array initializer of SYSMPU peripheral base addresses */
|
||||
#define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
|
||||
/** Array initializer of SYSMPU peripheral base pointers */
|
||||
#define SYSMPU_BASE_PTRS { SYSMPU }
|
||||
|
||||
/*!
|
||||
* @}
|
||||
*/ /* end of group SYSMPU_Peripheral_Access_Layer */
|
||||
|
||||
|
||||
/* ----------------------------------------------------------------------------
|
||||
-- UART Peripheral Access Layer
|
||||
---------------------------------------------------------------------------- */
|
||||
|
|
|
|||
|
|
@ -230,8 +230,8 @@
|
|||
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
|
||||
/* @brief MMDVSQ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
|
||||
/* @brief MPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MPU_COUNT (1)
|
||||
/* @brief SYSMPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
|
||||
/* @brief MSCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
|
||||
/* @brief MSCM availability on the SoC. */
|
||||
|
|
@ -477,8 +477,8 @@
|
|||
#define FSL_FEATURE_SOC_MMAU_COUNT (0)
|
||||
/* @brief MMDVSQ availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0)
|
||||
/* @brief MPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MPU_COUNT (1)
|
||||
/* @brief SYSMPU availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_SYSMPU_COUNT (1)
|
||||
/* @brief MSCAN availability on the SoC. */
|
||||
#define FSL_FEATURE_SOC_MSCAN_COUNT (0)
|
||||
/* @brief MSCM availability on the SoC. */
|
||||
|
|
@ -1499,21 +1499,6 @@
|
|||
/* @brief Reset clock mode is BLPI. */
|
||||
#define FSL_FEATURE_MCG_RESET_IS_BLPI (0)
|
||||
|
||||
/* MPU module features */
|
||||
|
||||
/* @brief Specifies number of descriptors available. */
|
||||
#define FSL_FEATURE_MPU_DESCRIPTOR_COUNT (12)
|
||||
/* @brief Has process identifier support. */
|
||||
#define FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER (1)
|
||||
/* @brief Total number of MPU master. */
|
||||
#define FSL_FEATURE_MPU_MASTER_COUNT (8)
|
||||
/* @brief Total number of MPU master with privileged rights */
|
||||
#define FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT (4)
|
||||
/* @brief Max index of used MPU master. */
|
||||
#define FSL_FEATURE_MPU_MASTER_MAX_INDEX (5)
|
||||
/* @brief Has master 4 or 5 or 6 or 7. */
|
||||
#define FSL_FEATURE_MPU_HAS_MASTER_4_7 (1)
|
||||
|
||||
/* interrupt module features */
|
||||
|
||||
/* @brief Lowest interrupt request number. */
|
||||
|
|
@ -2009,6 +1994,17 @@
|
|||
((x) == DSPI1 ? (0) : \
|
||||
((x) == DSPI2 ? (0) : (-1))))
|
||||
|
||||
/* SYSMPU module features */
|
||||
|
||||
/* @brief Specifies number of descriptors available. */
|
||||
#define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12)
|
||||
/* @brief Has process identifier support. */
|
||||
#define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1)
|
||||
/* @brief Total number of MPU slave. */
|
||||
#define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5)
|
||||
/* @brief Total number of MPU master. */
|
||||
#define FSL_FEATURE_SYSMPU_MASTER_COUNT (6)
|
||||
|
||||
/* SysTick module features */
|
||||
|
||||
/* @brief Systick has external reference clock. */
|
||||
|
|
|
|||
|
|
@ -237,9 +237,9 @@ extern uint32_t g_xtal32Freq;
|
|||
}
|
||||
|
||||
/*! @brief Clock ip name array for MPU. */
|
||||
#define MPU_CLOCKS \
|
||||
#define SYSMPU_CLOCKS \
|
||||
{ \
|
||||
kCLOCK_Mpu0 \
|
||||
kCLOCK_Sysmpu0 \
|
||||
}
|
||||
|
||||
/*! @brief Clock ip name array for VREF. */
|
||||
|
|
@ -445,7 +445,7 @@ typedef enum _clock_ip_name
|
|||
|
||||
kCLOCK_Flexbus0 = CLK_GATE_DEFINE(0x1040U, 0U),
|
||||
kCLOCK_Dma0 = CLK_GATE_DEFINE(0x1040U, 1U),
|
||||
kCLOCK_Mpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
|
||||
kCLOCK_Sysmpu0 = CLK_GATE_DEFINE(0x1040U, 2U),
|
||||
} clock_ip_name_t;
|
||||
|
||||
/*!@brief SIM configuration structure for clock setting. */
|
||||
|
|
|
|||
|
|
@ -1,247 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_mpu.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
const clock_ip_name_t g_mpuClock[FSL_FEATURE_SOC_MPU_COUNT] = MPU_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Codes
|
||||
******************************************************************************/
|
||||
|
||||
void MPU_Init(MPU_Type *base, const mpu_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint8_t count;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Un-gate MPU clock */
|
||||
CLOCK_EnableClock(g_mpuClock[0]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Initializes the regions. */
|
||||
for (count = 1; count < FSL_FEATURE_MPU_DESCRIPTOR_COUNT; count++)
|
||||
{
|
||||
base->WORD[count][3] = 0; /* VLD/VID+PID. */
|
||||
base->WORD[count][0] = 0; /* Start address. */
|
||||
base->WORD[count][1] = 0; /* End address. */
|
||||
base->WORD[count][2] = 0; /* Access rights. */
|
||||
base->RGDAAC[count] = 0; /* Alternate access rights. */
|
||||
}
|
||||
|
||||
/* MPU configure. */
|
||||
while (config)
|
||||
{
|
||||
MPU_SetRegionConfig(base, &(config->regionConfig));
|
||||
config = config->next;
|
||||
}
|
||||
/* Enable MPU. */
|
||||
MPU_Enable(base, true);
|
||||
}
|
||||
|
||||
void MPU_Deinit(MPU_Type *base)
|
||||
{
|
||||
/* Disable MPU. */
|
||||
MPU_Enable(base, false);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Gate the clock. */
|
||||
CLOCK_DisableClock(g_mpuClock[0]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform)
|
||||
{
|
||||
assert(hardwareInform);
|
||||
|
||||
uint32_t cesReg = base->CESR;
|
||||
|
||||
hardwareInform->hardwareRevisionLevel = (cesReg & MPU_CESR_HRL_MASK) >> MPU_CESR_HRL_SHIFT;
|
||||
hardwareInform->slavePortsNumbers = (cesReg & MPU_CESR_NSP_MASK) >> MPU_CESR_NSP_SHIFT;
|
||||
hardwareInform->regionsNumbers = (mpu_region_total_num_t)((cesReg & MPU_CESR_NRGD_MASK) >> MPU_CESR_NRGD_SHIFT);
|
||||
}
|
||||
|
||||
void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig)
|
||||
{
|
||||
assert(regionConfig);
|
||||
assert(regionConfig->regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
|
||||
|
||||
uint32_t wordReg = 0;
|
||||
uint8_t msPortNum;
|
||||
uint8_t regNumber = regionConfig->regionNum;
|
||||
|
||||
/* The start and end address of the region descriptor. */
|
||||
base->WORD[regNumber][0] = regionConfig->startAddress;
|
||||
base->WORD[regNumber][1] = regionConfig->endAddress;
|
||||
|
||||
/* Set the privilege rights for master 0 ~ master 3. */
|
||||
for (msPortNum = 0; msPortNum <= MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX; msPortNum++)
|
||||
{
|
||||
wordReg |= MPU_REGION_RWXRIGHTS_MASTER(
|
||||
msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) |
|
||||
(uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights));
|
||||
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
wordReg |=
|
||||
MPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable);
|
||||
#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
|
||||
}
|
||||
|
||||
/* Set the normal read write rights for master 4 ~ master 7. */
|
||||
for (msPortNum = FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT; msPortNum < FSL_FEATURE_MPU_MASTER_COUNT;
|
||||
msPortNum++)
|
||||
{
|
||||
wordReg |= MPU_REGION_RWRIGHTS_MASTER(msPortNum,
|
||||
((uint32_t)regionConfig->accessRights2[msPortNum - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT].readEnable << 1U |
|
||||
(uint32_t)regionConfig->accessRights2[msPortNum - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT].writeEnable));
|
||||
}
|
||||
|
||||
/* Set region descriptor access rights. */
|
||||
base->WORD[regNumber][2] = wordReg;
|
||||
|
||||
wordReg = MPU_WORD_VLD(1);
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
wordReg |= MPU_WORD_PID(regionConfig->processIdentifier) | MPU_WORD_PIDMASK(regionConfig->processIdMask);
|
||||
#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
|
||||
|
||||
base->WORD[regNumber][3] = wordReg;
|
||||
}
|
||||
|
||||
void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
|
||||
|
||||
base->WORD[regionNum][0] = startAddr;
|
||||
base->WORD[regionNum][1] = endAddr;
|
||||
}
|
||||
|
||||
void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const mpu_rwxrights_master_access_control_t *accessRights)
|
||||
{
|
||||
assert(accessRights);
|
||||
assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
|
||||
assert(masterNum <= MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX);
|
||||
|
||||
uint32_t mask = MPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum);
|
||||
uint32_t right = base->RGDAAC[regionNum];
|
||||
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
mask |= MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum);
|
||||
#endif
|
||||
|
||||
/* Build rights control value. */
|
||||
right &= ~mask;
|
||||
right |= MPU_REGION_RWXRIGHTS_MASTER(
|
||||
masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
right |= MPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
|
||||
#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
|
||||
|
||||
/* Set low master region access rights. */
|
||||
base->RGDAAC[regionNum] = right;
|
||||
}
|
||||
|
||||
#if FSL_FEATURE_MPU_HAS_MASTER_4_7
|
||||
void MPU_SetRegionRwMasterAccessRights(MPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const mpu_rwrights_master_access_control_t *accessRights)
|
||||
{
|
||||
assert(accessRights);
|
||||
assert(regionNum < FSL_FEATURE_MPU_DESCRIPTOR_COUNT);
|
||||
assert(masterNum > MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX);
|
||||
assert(masterNum <= FSL_FEATURE_MPU_MASTER_MAX_INDEX);
|
||||
|
||||
uint32_t mask = MPU_REGION_RWRIGHTS_MASTER_MASK(masterNum);
|
||||
uint32_t right = base->RGDAAC[regionNum];
|
||||
|
||||
/* Build rights control value. */
|
||||
right &= ~mask;
|
||||
right |=
|
||||
MPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
|
||||
/* Set low master region access rights. */
|
||||
base->RGDAAC[regionNum] = right;
|
||||
}
|
||||
#endif /* FSL_FEATURE_MPU_HAS_MASTER_4_7 */
|
||||
|
||||
bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum)
|
||||
{
|
||||
uint8_t sperr;
|
||||
|
||||
sperr = ((base->CESR & MPU_CESR_SPERR_MASK) >> MPU_CESR_SPERR_SHIFT) & (0x1U << (MPU_SLAVE_PORT_NUM - slaveNum));
|
||||
|
||||
return (sperr != 0) ? true : false;
|
||||
}
|
||||
|
||||
void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform)
|
||||
{
|
||||
assert(errInform);
|
||||
|
||||
uint16_t value;
|
||||
uint32_t cesReg;
|
||||
|
||||
/* Error address. */
|
||||
errInform->address = base->SP[slaveNum].EAR;
|
||||
|
||||
/* Error detail information. */
|
||||
value = (base->SP[slaveNum].EDR & MPU_EDR_EACD_MASK) >> MPU_EDR_EACD_SHIFT;
|
||||
if (!value)
|
||||
{
|
||||
errInform->accessControl = kMPU_NoRegionHit;
|
||||
}
|
||||
else if (!(value & (uint16_t)(value - 1)))
|
||||
{
|
||||
errInform->accessControl = kMPU_NoneOverlappRegion;
|
||||
}
|
||||
else
|
||||
{
|
||||
errInform->accessControl = kMPU_OverlappRegion;
|
||||
}
|
||||
|
||||
value = base->SP[slaveNum].EDR;
|
||||
errInform->master = (uint32_t)((value & MPU_EDR_EMN_MASK) >> MPU_EDR_EMN_SHIFT);
|
||||
errInform->attributes = (mpu_err_attributes_t)((value & MPU_EDR_EATTR_MASK) >> MPU_EDR_EATTR_SHIFT);
|
||||
errInform->accessType = (mpu_err_access_type_t)((value & MPU_EDR_ERW_MASK) >> MPU_EDR_ERW_SHIFT);
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
errInform->processorIdentification = (uint8_t)((value & MPU_EDR_EPID_MASK) >> MPU_EDR_EPID_SHIFT);
|
||||
#endif
|
||||
|
||||
/* Clears error slave port bit. */
|
||||
cesReg = (base->CESR & ~MPU_CESR_SPERR_MASK) | ((0x1U << slaveNum) << MPU_CESR_SPERR_SHIFT);
|
||||
base->CESR = cesReg;
|
||||
}
|
||||
|
|
@ -1,427 +0,0 @@
|
|||
/*
|
||||
* Copyright (c) 2015, Freescale Semiconductor, Inc.
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of Freescale Semiconductor, Inc. nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_MPU_H_
|
||||
#define _FSL_MPU_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup mpu
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief MPU driver version 2.1.0. */
|
||||
#define FSL_MPU_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief MPU the bit shift for masters with privilege rights: read write and execute. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
|
||||
|
||||
/*! @brief MPU masters with read, write and execute rights bit mask. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
|
||||
|
||||
/*! @brief MPU masters with read, write and execute rights bit width. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
|
||||
|
||||
/*! @brief MPU masters with read, write and execute rights priority setting. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER(n, x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_MASK(n))
|
||||
|
||||
/*! @brief MPU masters with read, write and execute rights process enable bit shift. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + MPU_REGION_RWXRIGHTS_MASTER_WIDTH)
|
||||
|
||||
/*! @brief MPU masters with read, write and execute rights process enable bit mask. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
|
||||
|
||||
/*! @brief MPU masters with read, write and execute rights process enable setting. */
|
||||
#define MPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & MPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
|
||||
|
||||
/*! @brief MPU masters with normal read write permission bit shift. */
|
||||
#define MPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT) * 2 + 24)
|
||||
|
||||
/*! @brief MPU masters with normal read write rights bit mask. */
|
||||
#define MPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
|
||||
|
||||
/*! @brief MPU masters with normal read write rights priority setting. */
|
||||
#define MPU_REGION_RWRIGHTS_MASTER(n, x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << MPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & MPU_REGION_RWRIGHTS_MASTER_MASK(n))
|
||||
|
||||
/*! @brief the Slave port numbers. */
|
||||
#define MPU_SLAVE_PORT_NUM (4u)
|
||||
/*! @brief define the maximum index of master with privileged rights. */
|
||||
#define MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX (3)
|
||||
|
||||
/*! @brief Describes the number of MPU regions. */
|
||||
typedef enum _mpu_region_total_num
|
||||
{
|
||||
kMPU_8Regions = 0x0U, /*!< MPU supports 8 regions. */
|
||||
kMPU_12Regions = 0x1U, /*!< MPU supports 12 regions. */
|
||||
kMPU_16Regions = 0x2U /*!< MPU supports 16 regions. */
|
||||
} mpu_region_total_num_t;
|
||||
|
||||
/*! @brief MPU slave port number. */
|
||||
typedef enum _mpu_slave
|
||||
{
|
||||
kMPU_Slave0 = 0U, /*!< MPU slave port 0. */
|
||||
kMPU_Slave1 = 1U, /*!< MPU slave port 1. */
|
||||
kMPU_Slave2 = 2U, /*!< MPU slave port 2. */
|
||||
kMPU_Slave3 = 3U, /*!< MPU slave port 3. */
|
||||
kMPU_Slave4 = 4U /*!< MPU slave port 4. */
|
||||
} mpu_slave_t;
|
||||
|
||||
/*! @brief MPU error access control detail. */
|
||||
typedef enum _mpu_err_access_control
|
||||
{
|
||||
kMPU_NoRegionHit = 0U, /*!< No region hit error. */
|
||||
kMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
|
||||
kMPU_OverlappRegion = 2U /*!< Access overlapping region error. */
|
||||
} mpu_err_access_control_t;
|
||||
|
||||
/*! @brief MPU error access type. */
|
||||
typedef enum _mpu_err_access_type
|
||||
{
|
||||
kMPU_ErrTypeRead = 0U, /*!< MPU error access type --- read. */
|
||||
kMPU_ErrTypeWrite = 1U /*!< MPU error access type --- write. */
|
||||
} mpu_err_access_type_t;
|
||||
|
||||
/*! @brief MPU access error attributes.*/
|
||||
typedef enum _mpu_err_attributes
|
||||
{
|
||||
kMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */
|
||||
kMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */
|
||||
kMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
|
||||
kMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */
|
||||
} mpu_err_attributes_t;
|
||||
|
||||
/*! @brief MPU access rights in supervisor mode for bus master 0 ~ 3. */
|
||||
typedef enum _mpu_supervisor_access_rights
|
||||
{
|
||||
kMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
|
||||
kMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */
|
||||
kMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */
|
||||
kMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */
|
||||
} mpu_supervisor_access_rights_t;
|
||||
|
||||
/*! @brief MPU access rights in user mode for bus master 0 ~ 3. */
|
||||
typedef enum _mpu_user_access_rights
|
||||
{
|
||||
kMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */
|
||||
kMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */
|
||||
kMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */
|
||||
kMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */
|
||||
kMPU_UserRead = 4U, /*!< Read is allowed in user mode. */
|
||||
kMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */
|
||||
kMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */
|
||||
kMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
|
||||
} mpu_user_access_rights_t;
|
||||
|
||||
/*! @brief MPU hardware basic information. */
|
||||
typedef struct _mpu_hardware_info
|
||||
{
|
||||
uint8_t hardwareRevisionLevel; /*!< Specifies the MPU's hardware and definition reversion level. */
|
||||
uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to MPU. */
|
||||
mpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
|
||||
} mpu_hardware_info_t;
|
||||
|
||||
/*! @brief MPU detail error access information. */
|
||||
typedef struct _mpu_access_err_info
|
||||
{
|
||||
uint32_t master; /*!< Access error master. */
|
||||
mpu_err_attributes_t attributes; /*!< Access error attributes. */
|
||||
mpu_err_access_type_t accessType; /*!< Access error type. */
|
||||
mpu_err_access_control_t accessControl; /*!< Access error control. */
|
||||
uint32_t address; /*!< Access error address. */
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
uint8_t processorIdentification; /*!< Access error processor identification. */
|
||||
#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
|
||||
} mpu_access_err_info_t;
|
||||
|
||||
/*! @brief MPU read/write/execute rights control for bus master 0 ~ 3. */
|
||||
typedef struct _mpu_rwxrights_master_access_control
|
||||
{
|
||||
mpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
|
||||
mpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
bool processIdentifierEnable; /*!< Enables or disables process identifier. */
|
||||
#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
|
||||
} mpu_rwxrights_master_access_control_t;
|
||||
|
||||
/*! @brief MPU read/write access control for bus master 4 ~ 7. */
|
||||
typedef struct _mpu_rwrights_master_access_control
|
||||
{
|
||||
bool writeEnable; /*!< Enables or disables write permission. */
|
||||
bool readEnable; /*!< Enables or disables read permission. */
|
||||
} mpu_rwrights_master_access_control_t;
|
||||
|
||||
/*!
|
||||
* @brief MPU region configuration structure.
|
||||
*
|
||||
* This structure is used to configure the regionNum region.
|
||||
* The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
|
||||
* 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
|
||||
* are used to configure the high master 4 ~ 7 with the normal read write permission.
|
||||
* The master port assignment is the chip configuration. Normally, the core is the
|
||||
* master 0, debugger is the master 1.
|
||||
* Note that the MPU assigns a priority scheme where the debugger is treated as the highest
|
||||
* priority master followed by the core and then all the remaining masters.
|
||||
* MPU protection does not allow writes from the core to affect the "regionNum 0" start
|
||||
* and end address nor the permissions associated with the debugger. It can only write
|
||||
* the permission fields associated with the other masters. This protection guarantees that
|
||||
* the debugger always has access to the entire address space and those rights can't
|
||||
* be changed by the core or any other bus master. Prepare
|
||||
* the region configuration when regionNum is 0.
|
||||
*/
|
||||
typedef struct _mpu_region_config
|
||||
{
|
||||
uint32_t regionNum; /*!< MPU region number, range form 0 ~ FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1. */
|
||||
uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by MPU. The actual
|
||||
start address is 0-modulo-32 byte address. */
|
||||
uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU. The actual end
|
||||
address is 31-modulo-32 byte address. */
|
||||
mpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
|
||||
mpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */
|
||||
#if FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER
|
||||
uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
|
||||
uint8_t
|
||||
processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
|
||||
#endif /* FSL_FEATURE_MPU_HAS_PROCESS_IDENTIFIER */
|
||||
} mpu_region_config_t;
|
||||
|
||||
/*!
|
||||
* @brief The configuration structure for the MPU initialization.
|
||||
*
|
||||
* This structure is used when calling the MPU_Init function.
|
||||
*/
|
||||
typedef struct _mpu_config
|
||||
{
|
||||
mpu_region_config_t regionConfig; /*!< Region access permission. */
|
||||
struct _mpu_config *next; /*!< Pointer to the next structure. */
|
||||
} mpu_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the MPU with the user configuration structure.
|
||||
*
|
||||
* This function configures the MPU module with the user-defined configuration.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param config The pointer to the configuration structure.
|
||||
*/
|
||||
void MPU_Init(MPU_Type *base, const mpu_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the MPU regions.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
*/
|
||||
void MPU_Deinit(MPU_Type *base);
|
||||
|
||||
/* @}*/
|
||||
|
||||
/*!
|
||||
* @name Basic Control Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the MPU globally.
|
||||
*
|
||||
* Call this API to enable or disable the MPU module.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param enable True enable MPU, false disable MPU.
|
||||
*/
|
||||
static inline void MPU_Enable(MPU_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Enable the MPU globally. */
|
||||
base->CESR |= MPU_CESR_VLD_MASK;
|
||||
}
|
||||
else
|
||||
{ /* Disable the MPU globally. */
|
||||
base->CESR &= ~MPU_CESR_VLD_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the MPU for a special region.
|
||||
*
|
||||
* When MPU is enabled, call this API to disable an unused region
|
||||
* of an enabled MPU. Call this API to minimize the power dissipation.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param number MPU region number.
|
||||
* @param enable True enable the special region MPU, false disable the special region MPU.
|
||||
*/
|
||||
static inline void MPU_RegionEnable(MPU_Type *base, uint32_t number, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Enable the #number region MPU. */
|
||||
base->WORD[number][3] |= MPU_WORD_VLD_MASK;
|
||||
}
|
||||
else
|
||||
{ /* Disable the #number region MPU. */
|
||||
base->WORD[number][3] &= ~MPU_WORD_VLD_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the MPU basic hardware information.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param hardwareInform The pointer to the MPU hardware information structure. See "mpu_hardware_info_t".
|
||||
*/
|
||||
void MPU_GetHardwareInfo(MPU_Type *base, mpu_hardware_info_t *hardwareInform);
|
||||
|
||||
/*!
|
||||
* @brief Sets the MPU region.
|
||||
*
|
||||
* Note: Due to the MPU protection, the region number 0 does not allow writes from
|
||||
* core to affect the start and end address nor the permissions associated with
|
||||
* the debugger. It can only write the permission fields associated
|
||||
* with the other masters.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param regionConfig The pointer to the MPU user configuration structure. See "mpu_region_config_t".
|
||||
*/
|
||||
void MPU_SetRegionConfig(MPU_Type *base, const mpu_region_config_t *regionConfig);
|
||||
|
||||
/*!
|
||||
* @brief Sets the region start and end address.
|
||||
*
|
||||
* Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by MPU.
|
||||
* The actual start address by MPU is 0-modulo-32 byte address.
|
||||
* Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by MPU.
|
||||
* The end address used by the MPU is 31-modulo-32 byte address.
|
||||
* Note: Due to the MPU protection, the startAddr and endAddr can't be
|
||||
* changed by the core when regionNum is 0.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param regionNum MPU region number. The range is from 0 to
|
||||
* FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
|
||||
* @param startAddr Region start address.
|
||||
* @param endAddr Region end address.
|
||||
*/
|
||||
void MPU_SetRegionAddr(MPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
|
||||
|
||||
/*!
|
||||
* @brief Sets the MPU region access rights for masters with read, write, and execute rights.
|
||||
* The MPU access rights depend on two board classifications of bus masters.
|
||||
* The privilege rights masters and the normal rights masters.
|
||||
* The privilege rights masters have the read, write, and execute access rights.
|
||||
* Except the normal read and write rights, the execute rights are also
|
||||
* allowed for these masters. The privilege rights masters normally range from
|
||||
* bus masters 0 - 3. However, the maximum master number is device-specific.
|
||||
* See the "MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
|
||||
* The normal rights masters access rights control see
|
||||
* "MPU_SetRegionRwMasterAccessRights()".
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param regionNum MPU region number. Should range from 0 to
|
||||
* FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
|
||||
* @param masterNum MPU bus master number. Should range from 0 to
|
||||
* MPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
|
||||
* @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwxrights_master_access_control_t".
|
||||
*/
|
||||
void MPU_SetRegionRwxMasterAccessRights(MPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const mpu_rwxrights_master_access_control_t *accessRights);
|
||||
#if FSL_FEATURE_MPU_HAS_MASTER_4_7
|
||||
/*!
|
||||
* @brief Sets the MPU region access rights for masters with read and write rights.
|
||||
* The MPU access rights depend on two board classifications of bus masters.
|
||||
* The privilege rights masters and the normal rights masters.
|
||||
* The normal rights masters only have the read and write access permissions.
|
||||
* The privilege rights access control see "MPU_SetRegionRwxMasterAccessRights".
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param regionNum MPU region number. The range is from 0 to
|
||||
* FSL_FEATURE_MPU_DESCRIPTOR_COUNT - 1.
|
||||
* @param masterNum MPU bus master number. Should range from FSL_FEATURE_MPU_PRIVILEGED_RIGHTS_MASTER_COUNT
|
||||
* to ~ FSL_FEATURE_MPU_MASTER_MAX_INDEX.
|
||||
* @param accessRights The pointer to the MPU access rights configuration. See "mpu_rwrights_master_access_control_t".
|
||||
*/
|
||||
void MPU_SetRegionRwMasterAccessRights(MPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const mpu_rwrights_master_access_control_t *accessRights);
|
||||
#endif /* FSL_FEATURE_MPU_HAS_MASTER_4_7 */
|
||||
/*!
|
||||
* @brief Gets the numbers of slave ports where errors occur.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param slaveNum MPU slave port number.
|
||||
* @return The slave ports error status.
|
||||
* true - error happens in this slave port.
|
||||
* false - error didn't happen in this slave port.
|
||||
*/
|
||||
bool MPU_GetSlavePortErrorStatus(MPU_Type *base, mpu_slave_t slaveNum);
|
||||
|
||||
/*!
|
||||
* @brief Gets the MPU detailed error access information.
|
||||
*
|
||||
* @param base MPU peripheral base address.
|
||||
* @param slaveNum MPU slave port number.
|
||||
* @param errInform The pointer to the MPU access error information. See "mpu_access_err_info_t".
|
||||
*/
|
||||
void MPU_GetDetailErrorAccessInfo(MPU_Type *base, mpu_slave_t slaveNum, mpu_access_err_info_t *errInform);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_MPU_H_ */
|
||||
|
|
@ -0,0 +1,249 @@
|
|||
/*
|
||||
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
#include "fsl_sysmpu.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* Variables
|
||||
******************************************************************************/
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
const clock_ip_name_t g_sysmpuClock[FSL_FEATURE_SOC_SYSMPU_COUNT] = SYSMPU_CLOCKS;
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/*******************************************************************************
|
||||
* Codes
|
||||
******************************************************************************/
|
||||
|
||||
void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config)
|
||||
{
|
||||
assert(config);
|
||||
uint8_t count;
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Un-gate SYSMPU clock */
|
||||
CLOCK_EnableClock(g_sysmpuClock[0]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
|
||||
/* Initializes the regions. */
|
||||
for (count = 1; count < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT; count++)
|
||||
{
|
||||
base->WORD[count][3] = 0; /* VLD/VID+PID. */
|
||||
base->WORD[count][0] = 0; /* Start address. */
|
||||
base->WORD[count][1] = 0; /* End address. */
|
||||
base->WORD[count][2] = 0; /* Access rights. */
|
||||
base->RGDAAC[count] = 0; /* Alternate access rights. */
|
||||
}
|
||||
|
||||
/* SYSMPU configure. */
|
||||
while (config)
|
||||
{
|
||||
SYSMPU_SetRegionConfig(base, &(config->regionConfig));
|
||||
config = config->next;
|
||||
}
|
||||
/* Enable SYSMPU. */
|
||||
SYSMPU_Enable(base, true);
|
||||
}
|
||||
|
||||
void SYSMPU_Deinit(SYSMPU_Type *base)
|
||||
{
|
||||
/* Disable SYSMPU. */
|
||||
SYSMPU_Enable(base, false);
|
||||
|
||||
#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
|
||||
/* Gate the clock. */
|
||||
CLOCK_DisableClock(g_sysmpuClock[0]);
|
||||
#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
|
||||
}
|
||||
|
||||
void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform)
|
||||
{
|
||||
assert(hardwareInform);
|
||||
|
||||
uint32_t cesReg = base->CESR;
|
||||
|
||||
hardwareInform->hardwareRevisionLevel = (cesReg & SYSMPU_CESR_HRL_MASK) >> SYSMPU_CESR_HRL_SHIFT;
|
||||
hardwareInform->slavePortsNumbers = (cesReg & SYSMPU_CESR_NSP_MASK) >> SYSMPU_CESR_NSP_SHIFT;
|
||||
hardwareInform->regionsNumbers = (sysmpu_region_total_num_t)((cesReg & SYSMPU_CESR_NRGD_MASK) >> SYSMPU_CESR_NRGD_SHIFT);
|
||||
}
|
||||
|
||||
void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig)
|
||||
{
|
||||
assert(regionConfig);
|
||||
assert(regionConfig->regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
|
||||
|
||||
uint32_t wordReg = 0;
|
||||
uint8_t msPortNum;
|
||||
uint8_t regNumber = regionConfig->regionNum;
|
||||
|
||||
/* The start and end address of the region descriptor. */
|
||||
base->WORD[regNumber][0] = regionConfig->startAddress;
|
||||
base->WORD[regNumber][1] = regionConfig->endAddress;
|
||||
|
||||
/* Set the privilege rights for master 0 ~ master 3. */
|
||||
for (msPortNum = 0; msPortNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum++)
|
||||
{
|
||||
wordReg |= SYSMPU_REGION_RWXRIGHTS_MASTER(
|
||||
msPortNum, (((uint32_t)regionConfig->accessRights1[msPortNum].superAccessRights << 3U) |
|
||||
(uint32_t)regionConfig->accessRights1[msPortNum].userAccessRights));
|
||||
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
wordReg |=
|
||||
SYSMPU_REGION_RWXRIGHTS_MASTER_PE(msPortNum, regionConfig->accessRights1[msPortNum].processIdentifierEnable);
|
||||
#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
|
||||
}
|
||||
|
||||
#if FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT
|
||||
/* Set the normal read write rights for master 4 ~ master 7. */
|
||||
for (msPortNum = SYSMPU_MASTER_RWATTRIBUTE_START_PORT; msPortNum < FSL_FEATURE_SYSMPU_MASTER_COUNT;
|
||||
msPortNum++)
|
||||
{
|
||||
wordReg |= SYSMPU_REGION_RWRIGHTS_MASTER(msPortNum,
|
||||
((uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].readEnable << 1U |
|
||||
(uint32_t)regionConfig->accessRights2[msPortNum - SYSMPU_MASTER_RWATTRIBUTE_START_PORT].writeEnable));
|
||||
}
|
||||
#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > SYSMPU_MASTER_RWATTRIBUTE_START_PORT */
|
||||
|
||||
/* Set region descriptor access rights. */
|
||||
base->WORD[regNumber][2] = wordReg;
|
||||
|
||||
wordReg = SYSMPU_WORD_VLD(1);
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
wordReg |= SYSMPU_WORD_PID(regionConfig->processIdentifier) | SYSMPU_WORD_PIDMASK(regionConfig->processIdMask);
|
||||
#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
|
||||
|
||||
base->WORD[regNumber][3] = wordReg;
|
||||
}
|
||||
|
||||
void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr)
|
||||
{
|
||||
assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
|
||||
|
||||
base->WORD[regionNum][0] = startAddr;
|
||||
base->WORD[regionNum][1] = endAddr;
|
||||
}
|
||||
|
||||
void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const sysmpu_rwxrights_master_access_control_t *accessRights)
|
||||
{
|
||||
assert(accessRights);
|
||||
assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
|
||||
assert(masterNum < SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
|
||||
|
||||
uint32_t mask = SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(masterNum);
|
||||
uint32_t right = base->RGDAAC[regionNum];
|
||||
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
mask |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(masterNum);
|
||||
#endif
|
||||
|
||||
/* Build rights control value. */
|
||||
right &= ~mask;
|
||||
right |= SYSMPU_REGION_RWXRIGHTS_MASTER(
|
||||
masterNum, ((uint32_t)(accessRights->superAccessRights << 3U) | accessRights->userAccessRights));
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
right |= SYSMPU_REGION_RWXRIGHTS_MASTER_PE(masterNum, accessRights->processIdentifierEnable);
|
||||
#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
|
||||
|
||||
/* Set low master region access rights. */
|
||||
base->RGDAAC[regionNum] = right;
|
||||
}
|
||||
|
||||
#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
|
||||
void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const sysmpu_rwrights_master_access_control_t *accessRights)
|
||||
{
|
||||
assert(accessRights);
|
||||
assert(regionNum < FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT);
|
||||
assert(masterNum >= SYSMPU_MASTER_RWATTRIBUTE_START_PORT);
|
||||
assert(masterNum <= (FSL_FEATURE_SYSMPU_MASTER_COUNT - 1));
|
||||
|
||||
uint32_t mask = SYSMPU_REGION_RWRIGHTS_MASTER_MASK(masterNum);
|
||||
uint32_t right = base->RGDAAC[regionNum];
|
||||
|
||||
/* Build rights control value. */
|
||||
right &= ~mask;
|
||||
right |=
|
||||
SYSMPU_REGION_RWRIGHTS_MASTER(masterNum, (((uint32_t)accessRights->readEnable << 1U) | accessRights->writeEnable));
|
||||
/* Set low master region access rights. */
|
||||
base->RGDAAC[regionNum] = right;
|
||||
}
|
||||
#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
|
||||
|
||||
bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum)
|
||||
{
|
||||
uint8_t sperr;
|
||||
|
||||
sperr = ((base->CESR & SYSMPU_CESR_SPERR_MASK) >> SYSMPU_CESR_SPERR_SHIFT) & (0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1));
|
||||
|
||||
return (sperr != 0) ? true : false;
|
||||
}
|
||||
|
||||
void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform)
|
||||
{
|
||||
assert(errInform);
|
||||
|
||||
uint16_t value;
|
||||
uint32_t cesReg;
|
||||
|
||||
/* Error address. */
|
||||
errInform->address = base->SP[slaveNum].EAR;
|
||||
|
||||
/* Error detail information. */
|
||||
value = (base->SP[slaveNum].EDR & SYSMPU_EDR_EACD_MASK) >> SYSMPU_EDR_EACD_SHIFT;
|
||||
if (!value)
|
||||
{
|
||||
errInform->accessControl = kSYSMPU_NoRegionHit;
|
||||
}
|
||||
else if (!(value & (uint16_t)(value - 1)))
|
||||
{
|
||||
errInform->accessControl = kSYSMPU_NoneOverlappRegion;
|
||||
}
|
||||
else
|
||||
{
|
||||
errInform->accessControl = kSYSMPU_OverlappRegion;
|
||||
}
|
||||
|
||||
value = base->SP[slaveNum].EDR;
|
||||
errInform->master = (uint32_t)((value & SYSMPU_EDR_EMN_MASK) >> SYSMPU_EDR_EMN_SHIFT);
|
||||
errInform->attributes = (sysmpu_err_attributes_t)((value & SYSMPU_EDR_EATTR_MASK) >> SYSMPU_EDR_EATTR_SHIFT);
|
||||
errInform->accessType = (sysmpu_err_access_type_t)((value & SYSMPU_EDR_ERW_MASK) >> SYSMPU_EDR_ERW_SHIFT);
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
errInform->processorIdentification = (uint8_t)((value & SYSMPU_EDR_EPID_MASK) >> SYSMPU_EDR_EPID_SHIFT);
|
||||
#endif
|
||||
|
||||
/* Clears error slave port bit. */
|
||||
cesReg = (base->CESR & ~SYSMPU_CESR_SPERR_MASK) | ((0x1U << (FSL_FEATURE_SYSMPU_SLAVE_COUNT - slaveNum - 1)) << SYSMPU_CESR_SPERR_SHIFT);
|
||||
base->CESR = cesReg;
|
||||
}
|
||||
|
|
@ -0,0 +1,435 @@
|
|||
/*
|
||||
* Copyright (c) 2015 - 2016, Freescale Semiconductor, Inc.
|
||||
* Copyright 2016-2017 NXP
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without modification,
|
||||
* are permitted provided that the following conditions are met:
|
||||
*
|
||||
* o Redistributions of source code must retain the above copyright notice, this list
|
||||
* of conditions and the following disclaimer.
|
||||
*
|
||||
* o Redistributions in binary form must reproduce the above copyright notice, this
|
||||
* list of conditions and the following disclaimer in the documentation and/or
|
||||
* other materials provided with the distribution.
|
||||
*
|
||||
* o Neither the name of the copyright holder nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from this
|
||||
* software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
|
||||
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
|
||||
* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
#ifndef _FSL_SYSMPU_H_
|
||||
#define _FSL_SYSMPU_H_
|
||||
|
||||
#include "fsl_common.h"
|
||||
|
||||
/*!
|
||||
* @addtogroup sysmpu
|
||||
* @{
|
||||
*/
|
||||
|
||||
|
||||
/*******************************************************************************
|
||||
* Definitions
|
||||
******************************************************************************/
|
||||
|
||||
/*! @name Driver version */
|
||||
/*@{*/
|
||||
/*! @brief SYSMPU driver version 2.2.0. */
|
||||
#define FSL_SYSMPU_DRIVER_VERSION (MAKE_VERSION(2, 2, 0))
|
||||
/*@}*/
|
||||
|
||||
/*! @brief define the start master port with read and write attributes. */
|
||||
#define SYSMPU_MASTER_RWATTRIBUTE_START_PORT (4)
|
||||
|
||||
/*! @brief SYSMPU the bit shift for masters with privilege rights: read write and execute. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n) (n * 6)
|
||||
|
||||
/*! @brief SYSMPU masters with read, write and execute rights bit mask. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n) (0x1Fu << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))
|
||||
|
||||
/*! @brief SYSMPU masters with read, write and execute rights bit width. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH 5
|
||||
|
||||
/*! @brief SYSMPU masters with read, write and execute rights priority setting. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER(n, x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_MASK(n))
|
||||
|
||||
/*! @brief SYSMPU masters with read, write and execute rights process enable bit shift. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n) (n * 6 + SYSMPU_REGION_RWXRIGHTS_MASTER_WIDTH)
|
||||
|
||||
/*! @brief SYSMPU masters with read, write and execute rights process enable bit mask. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n) (0x1u << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))
|
||||
|
||||
/*! @brief SYSMPU masters with read, write and execute rights process enable setting. */
|
||||
#define SYSMPU_REGION_RWXRIGHTS_MASTER_PE(n, x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWXRIGHTS_MASTER_PE_SHIFT(n))) & SYSMPU_REGION_RWXRIGHTS_MASTER_PE_MASK(n))
|
||||
|
||||
/*! @brief SYSMPU masters with normal read write permission bit shift. */
|
||||
#define SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n) ((n - SYSMPU_MASTER_RWATTRIBUTE_START_PORT) * 2 + 24)
|
||||
|
||||
/*! @brief SYSMPU masters with normal read write rights bit mask. */
|
||||
#define SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n) (0x3u << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))
|
||||
|
||||
/*! @brief SYSMPU masters with normal read write rights priority setting. */
|
||||
#define SYSMPU_REGION_RWRIGHTS_MASTER(n, x) \
|
||||
(((uint32_t)(((uint32_t)(x)) << SYSMPU_REGION_RWRIGHTS_MASTER_SHIFT(n))) & SYSMPU_REGION_RWRIGHTS_MASTER_MASK(n))
|
||||
|
||||
|
||||
/*! @brief Describes the number of SYSMPU regions. */
|
||||
typedef enum _sysmpu_region_total_num
|
||||
{
|
||||
kSYSMPU_8Regions = 0x0U, /*!< SYSMPU supports 8 regions. */
|
||||
kSYSMPU_12Regions = 0x1U, /*!< SYSMPU supports 12 regions. */
|
||||
kSYSMPU_16Regions = 0x2U /*!< SYSMPU supports 16 regions. */
|
||||
} sysmpu_region_total_num_t;
|
||||
|
||||
/*! @brief SYSMPU slave port number. */
|
||||
typedef enum _sysmpu_slave
|
||||
{
|
||||
kSYSMPU_Slave0 = 0U, /*!< SYSMPU slave port 0. */
|
||||
kSYSMPU_Slave1 = 1U, /*!< SYSMPU slave port 1. */
|
||||
kSYSMPU_Slave2 = 2U, /*!< SYSMPU slave port 2. */
|
||||
kSYSMPU_Slave3 = 3U, /*!< SYSMPU slave port 3. */
|
||||
kSYSMPU_Slave4 = 4U, /*!< SYSMPU slave port 4. */
|
||||
#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 5
|
||||
kSYSMPU_Slave5 = 5U, /*!< SYSMPU slave port 5. */
|
||||
#endif
|
||||
#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 6
|
||||
kSYSMPU_Slave6 = 6U, /*!< SYSMPU slave port 6. */
|
||||
#endif
|
||||
#if FSL_FEATURE_SYSMPU_SLAVE_COUNT > 7
|
||||
kSYSMPU_Slave7 = 7U, /*!< SYSMPU slave port 7. */
|
||||
#endif
|
||||
} sysmpu_slave_t;
|
||||
|
||||
/*! @brief SYSMPU error access control detail. */
|
||||
typedef enum _sysmpu_err_access_control
|
||||
{
|
||||
kSYSMPU_NoRegionHit = 0U, /*!< No region hit error. */
|
||||
kSYSMPU_NoneOverlappRegion = 1U, /*!< Access single region error. */
|
||||
kSYSMPU_OverlappRegion = 2U /*!< Access overlapping region error. */
|
||||
} sysmpu_err_access_control_t;
|
||||
|
||||
/*! @brief SYSMPU error access type. */
|
||||
typedef enum _sysmpu_err_access_type
|
||||
{
|
||||
kSYSMPU_ErrTypeRead = 0U, /*!< SYSMPU error access type --- read. */
|
||||
kSYSMPU_ErrTypeWrite = 1U /*!< SYSMPU error access type --- write. */
|
||||
} sysmpu_err_access_type_t;
|
||||
|
||||
/*! @brief SYSMPU access error attributes.*/
|
||||
typedef enum _sysmpu_err_attributes
|
||||
{
|
||||
kSYSMPU_InstructionAccessInUserMode = 0U, /*!< Access instruction error in user mode. */
|
||||
kSYSMPU_DataAccessInUserMode = 1U, /*!< Access data error in user mode. */
|
||||
kSYSMPU_InstructionAccessInSupervisorMode = 2U, /*!< Access instruction error in supervisor mode. */
|
||||
kSYSMPU_DataAccessInSupervisorMode = 3U /*!< Access data error in supervisor mode. */
|
||||
} sysmpu_err_attributes_t;
|
||||
|
||||
/*! @brief SYSMPU access rights in supervisor mode for bus master 0 ~ 3. */
|
||||
typedef enum _sysmpu_supervisor_access_rights
|
||||
{
|
||||
kSYSMPU_SupervisorReadWriteExecute = 0U, /*!< Read write and execute operations are allowed in supervisor mode. */
|
||||
kSYSMPU_SupervisorReadExecute = 1U, /*!< Read and execute operations are allowed in supervisor mode. */
|
||||
kSYSMPU_SupervisorReadWrite = 2U, /*!< Read write operations are allowed in supervisor mode. */
|
||||
kSYSMPU_SupervisorEqualToUsermode = 3U /*!< Access permission equal to user mode. */
|
||||
} sysmpu_supervisor_access_rights_t;
|
||||
|
||||
/*! @brief SYSMPU access rights in user mode for bus master 0 ~ 3. */
|
||||
typedef enum _sysmpu_user_access_rights
|
||||
{
|
||||
kSYSMPU_UserNoAccessRights = 0U, /*!< No access allowed in user mode. */
|
||||
kSYSMPU_UserExecute = 1U, /*!< Execute operation is allowed in user mode. */
|
||||
kSYSMPU_UserWrite = 2U, /*!< Write operation is allowed in user mode. */
|
||||
kSYSMPU_UserWriteExecute = 3U, /*!< Write and execute operations are allowed in user mode. */
|
||||
kSYSMPU_UserRead = 4U, /*!< Read is allowed in user mode. */
|
||||
kSYSMPU_UserReadExecute = 5U, /*!< Read and execute operations are allowed in user mode. */
|
||||
kSYSMPU_UserReadWrite = 6U, /*!< Read and write operations are allowed in user mode. */
|
||||
kSYSMPU_UserReadWriteExecute = 7U /*!< Read write and execute operations are allowed in user mode. */
|
||||
} sysmpu_user_access_rights_t;
|
||||
|
||||
/*! @brief SYSMPU hardware basic information. */
|
||||
typedef struct _sysmpu_hardware_info
|
||||
{
|
||||
uint8_t hardwareRevisionLevel; /*!< Specifies the SYSMPU's hardware and definition reversion level. */
|
||||
uint8_t slavePortsNumbers; /*!< Specifies the number of slave ports connected to SYSMPU. */
|
||||
sysmpu_region_total_num_t regionsNumbers; /*!< Indicates the number of region descriptors implemented. */
|
||||
} sysmpu_hardware_info_t;
|
||||
|
||||
/*! @brief SYSMPU detail error access information. */
|
||||
typedef struct _sysmpu_access_err_info
|
||||
{
|
||||
uint32_t master; /*!< Access error master. */
|
||||
sysmpu_err_attributes_t attributes; /*!< Access error attributes. */
|
||||
sysmpu_err_access_type_t accessType; /*!< Access error type. */
|
||||
sysmpu_err_access_control_t accessControl; /*!< Access error control. */
|
||||
uint32_t address; /*!< Access error address. */
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
uint8_t processorIdentification; /*!< Access error processor identification. */
|
||||
#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
|
||||
} sysmpu_access_err_info_t;
|
||||
|
||||
/*! @brief SYSMPU read/write/execute rights control for bus master 0 ~ 3. */
|
||||
typedef struct _sysmpu_rwxrights_master_access_control
|
||||
{
|
||||
sysmpu_supervisor_access_rights_t superAccessRights; /*!< Master access rights in supervisor mode. */
|
||||
sysmpu_user_access_rights_t userAccessRights; /*!< Master access rights in user mode. */
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
bool processIdentifierEnable; /*!< Enables or disables process identifier. */
|
||||
#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
|
||||
} sysmpu_rwxrights_master_access_control_t;
|
||||
|
||||
/*! @brief SYSMPU read/write access control for bus master 4 ~ 7. */
|
||||
typedef struct _sysmpu_rwrights_master_access_control
|
||||
{
|
||||
bool writeEnable; /*!< Enables or disables write permission. */
|
||||
bool readEnable; /*!< Enables or disables read permission. */
|
||||
} sysmpu_rwrights_master_access_control_t;
|
||||
|
||||
/*!
|
||||
* @brief SYSMPU region configuration structure.
|
||||
*
|
||||
* This structure is used to configure the regionNum region.
|
||||
* The accessRights1[0] ~ accessRights1[3] are used to configure the bus master
|
||||
* 0 ~ 3 with the privilege rights setting. The accessRights2[0] ~ accessRights2[3]
|
||||
* are used to configure the high master 4 ~ 7 with the normal read write permission.
|
||||
* The master port assignment is the chip configuration. Normally, the core is the
|
||||
* master 0, debugger is the master 1.
|
||||
* Note that the SYSMPU assigns a priority scheme where the debugger is treated as the highest
|
||||
* priority master followed by the core and then all the remaining masters.
|
||||
* SYSMPU protection does not allow writes from the core to affect the "regionNum 0" start
|
||||
* and end address nor the permissions associated with the debugger. It can only write
|
||||
* the permission fields associated with the other masters. This protection guarantees that
|
||||
* the debugger always has access to the entire address space and those rights can't
|
||||
* be changed by the core or any other bus master. Prepare
|
||||
* the region configuration when regionNum is 0.
|
||||
*/
|
||||
typedef struct _sysmpu_region_config
|
||||
{
|
||||
uint32_t regionNum; /*!< SYSMPU region number, range form 0 ~ FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1. */
|
||||
uint32_t startAddress; /*!< Memory region start address. Note: bit0 ~ bit4 always be marked as 0 by SYSMPU. The actual
|
||||
start address is 0-modulo-32 byte address. */
|
||||
uint32_t endAddress; /*!< Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU. The actual end
|
||||
address is 31-modulo-32 byte address. */
|
||||
sysmpu_rwxrights_master_access_control_t accessRights1[4]; /*!< Masters with read, write and execute rights setting. */
|
||||
sysmpu_rwrights_master_access_control_t accessRights2[4]; /*!< Masters with normal read write rights setting. */
|
||||
#if FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER
|
||||
uint8_t processIdentifier; /*!< Process identifier used when "processIdentifierEnable" set with true. */
|
||||
uint8_t
|
||||
processIdMask; /*!< Process identifier mask. The setting bit will ignore the same bit in process identifier. */
|
||||
#endif /* FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER */
|
||||
} sysmpu_region_config_t;
|
||||
|
||||
/*!
|
||||
* @brief The configuration structure for the SYSMPU initialization.
|
||||
*
|
||||
* This structure is used when calling the SYSMPU_Init function.
|
||||
*/
|
||||
typedef struct _sysmpu_config
|
||||
{
|
||||
sysmpu_region_config_t regionConfig; /*!< Region access permission. */
|
||||
struct _sysmpu_config *next; /*!< Pointer to the next structure. */
|
||||
} sysmpu_config_t;
|
||||
|
||||
/*******************************************************************************
|
||||
* API
|
||||
******************************************************************************/
|
||||
|
||||
#if defined(__cplusplus)
|
||||
extern "C" {
|
||||
#endif /* _cplusplus */
|
||||
|
||||
/*!
|
||||
* @name Initialization and deinitialization
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Initializes the SYSMPU with the user configuration structure.
|
||||
*
|
||||
* This function configures the SYSMPU module with the user-defined configuration.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param config The pointer to the configuration structure.
|
||||
*/
|
||||
void SYSMPU_Init(SYSMPU_Type *base, const sysmpu_config_t *config);
|
||||
|
||||
/*!
|
||||
* @brief Deinitializes the SYSMPU regions.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
*/
|
||||
void SYSMPU_Deinit(SYSMPU_Type *base);
|
||||
|
||||
/* @}*/
|
||||
|
||||
/*!
|
||||
* @name Basic Control Operations
|
||||
* @{
|
||||
*/
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the SYSMPU globally.
|
||||
*
|
||||
* Call this API to enable or disable the SYSMPU module.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param enable True enable SYSMPU, false disable SYSMPU.
|
||||
*/
|
||||
static inline void SYSMPU_Enable(SYSMPU_Type *base, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Enable the SYSMPU globally. */
|
||||
base->CESR |= SYSMPU_CESR_VLD_MASK;
|
||||
}
|
||||
else
|
||||
{ /* Disable the SYSMPU globally. */
|
||||
base->CESR &= ~SYSMPU_CESR_VLD_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Enables/disables the SYSMPU for a special region.
|
||||
*
|
||||
* When SYSMPU is enabled, call this API to disable an unused region
|
||||
* of an enabled SYSMPU. Call this API to minimize the power dissipation.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param number SYSMPU region number.
|
||||
* @param enable True enable the special region SYSMPU, false disable the special region SYSMPU.
|
||||
*/
|
||||
static inline void SYSMPU_RegionEnable(SYSMPU_Type *base, uint32_t number, bool enable)
|
||||
{
|
||||
if (enable)
|
||||
{
|
||||
/* Enable the #number region SYSMPU. */
|
||||
base->WORD[number][3] |= SYSMPU_WORD_VLD_MASK;
|
||||
}
|
||||
else
|
||||
{ /* Disable the #number region SYSMPU. */
|
||||
base->WORD[number][3] &= ~SYSMPU_WORD_VLD_MASK;
|
||||
}
|
||||
}
|
||||
|
||||
/*!
|
||||
* @brief Gets the SYSMPU basic hardware information.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param hardwareInform The pointer to the SYSMPU hardware information structure. See "sysmpu_hardware_info_t".
|
||||
*/
|
||||
void SYSMPU_GetHardwareInfo(SYSMPU_Type *base, sysmpu_hardware_info_t *hardwareInform);
|
||||
|
||||
/*!
|
||||
* @brief Sets the SYSMPU region.
|
||||
*
|
||||
* Note: Due to the SYSMPU protection, the region number 0 does not allow writes from
|
||||
* core to affect the start and end address nor the permissions associated with
|
||||
* the debugger. It can only write the permission fields associated
|
||||
* with the other masters.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param regionConfig The pointer to the SYSMPU user configuration structure. See "sysmpu_region_config_t".
|
||||
*/
|
||||
void SYSMPU_SetRegionConfig(SYSMPU_Type *base, const sysmpu_region_config_t *regionConfig);
|
||||
|
||||
/*!
|
||||
* @brief Sets the region start and end address.
|
||||
*
|
||||
* Memory region start address. Note: bit0 ~ bit4 is always marked as 0 by SYSMPU.
|
||||
* The actual start address by SYSMPU is 0-modulo-32 byte address.
|
||||
* Memory region end address. Note: bit0 ~ bit4 always be marked as 1 by SYSMPU.
|
||||
* The end address used by the SYSMPU is 31-modulo-32 byte address.
|
||||
* Note: Due to the SYSMPU protection, the startAddr and endAddr can't be
|
||||
* changed by the core when regionNum is 0.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param regionNum SYSMPU region number. The range is from 0 to
|
||||
* FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
|
||||
* @param startAddr Region start address.
|
||||
* @param endAddr Region end address.
|
||||
*/
|
||||
void SYSMPU_SetRegionAddr(SYSMPU_Type *base, uint32_t regionNum, uint32_t startAddr, uint32_t endAddr);
|
||||
|
||||
/*!
|
||||
* @brief Sets the SYSMPU region access rights for masters with read, write, and execute rights.
|
||||
* The SYSMPU access rights depend on two board classifications of bus masters.
|
||||
* The privilege rights masters and the normal rights masters.
|
||||
* The privilege rights masters have the read, write, and execute access rights.
|
||||
* Except the normal read and write rights, the execute rights are also
|
||||
* allowed for these masters. The privilege rights masters normally range from
|
||||
* bus masters 0 - 3. However, the maximum master number is device-specific.
|
||||
* See the "SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX".
|
||||
* The normal rights masters access rights control see
|
||||
* "SYSMPU_SetRegionRwMasterAccessRights()".
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param regionNum SYSMPU region number. Should range from 0 to
|
||||
* FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
|
||||
* @param masterNum SYSMPU bus master number. Should range from 0 to
|
||||
* SYSMPU_PRIVILEGED_RIGHTS_MASTER_MAX_INDEX.
|
||||
* @param accessRights The pointer to the SYSMPU access rights configuration. See "sysmpu_rwxrights_master_access_control_t".
|
||||
*/
|
||||
void SYSMPU_SetRegionRwxMasterAccessRights(SYSMPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const sysmpu_rwxrights_master_access_control_t *accessRights);
|
||||
#if FSL_FEATURE_SYSMPU_MASTER_COUNT > 4
|
||||
/*!
|
||||
* @brief Sets the SYSMPU region access rights for masters with read and write rights.
|
||||
* The SYSMPU access rights depend on two board classifications of bus masters.
|
||||
* The privilege rights masters and the normal rights masters.
|
||||
* The normal rights masters only have the read and write access permissions.
|
||||
* The privilege rights access control see "SYSMPU_SetRegionRwxMasterAccessRights".
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param regionNum SYSMPU region number. The range is from 0 to
|
||||
* FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT - 1.
|
||||
* @param masterNum SYSMPU bus master number. Should range from SYSMPU_MASTER_RWATTRIBUTE_START_PORT
|
||||
* to ~ FSL_FEATURE_SYSMPU_MASTER_COUNT - 1.
|
||||
* @param accessRights The pointer to the SYSMPU access rights configuration. See "sysmpu_rwrights_master_access_control_t".
|
||||
*/
|
||||
void SYSMPU_SetRegionRwMasterAccessRights(SYSMPU_Type *base,
|
||||
uint32_t regionNum,
|
||||
uint32_t masterNum,
|
||||
const sysmpu_rwrights_master_access_control_t *accessRights);
|
||||
#endif /* FSL_FEATURE_SYSMPU_MASTER_COUNT > 4 */
|
||||
/*!
|
||||
* @brief Gets the numbers of slave ports where errors occur.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param slaveNum SYSMPU slave port number.
|
||||
* @return The slave ports error status.
|
||||
* true - error happens in this slave port.
|
||||
* false - error didn't happen in this slave port.
|
||||
*/
|
||||
bool SYSMPU_GetSlavePortErrorStatus(SYSMPU_Type *base, sysmpu_slave_t slaveNum);
|
||||
|
||||
/*!
|
||||
* @brief Gets the SYSMPU detailed error access information.
|
||||
*
|
||||
* @param base SYSMPU peripheral base address.
|
||||
* @param slaveNum SYSMPU slave port number.
|
||||
* @param errInform The pointer to the SYSMPU access error information. See "sysmpu_access_err_info_t".
|
||||
*/
|
||||
void SYSMPU_GetDetailErrorAccessInfo(SYSMPU_Type *base, sysmpu_slave_t slaveNum, sysmpu_access_err_info_t *errInform);
|
||||
|
||||
/* @} */
|
||||
|
||||
#if defined(__cplusplus)
|
||||
}
|
||||
#endif
|
||||
|
||||
/*! @}*/
|
||||
|
||||
#endif /* _FSL_SYSMPU_H_ */
|
||||
Loading…
Reference in New Issue