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Merge pull request #3062 from jamike/TARGET_STM_USBDEVICE_FS 

TARGET_STM :USB device FS
pull/3180/merge
Martin Kojtal 2016-11-29 18:07:11 +01:00 committed by GitHub
parent 754bd24301 a34e0937fb
commit 93c08f340a
35 changed files with 1201 additions and 135 deletions
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6
features/unsupported/USBDevice/USBAudio/USBAudio.cpp
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@ -313,7 +313,8 @@ void USBAudio::USBCallback_requestCompleted(uint8_t * buf, uint32_t length) {
switch (transfer->setup.bRequest) {
case REQUEST_SET_CUR:
mute = data & 0xff;
updateVol.call();
if (updateVol)
updateVol.call();
break;
default:
break;
@ -324,7 +325,8 @@ void USBAudio::USBCallback_requestCompleted(uint8_t * buf, uint32_t length) {
case REQUEST_SET_CUR:
volCur = data;
volume = (float)volCur/(float)volMax;
updateVol.call();
if (updateVol)
updateVol.call();
break;
default:
break;

325
features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM32.cpp Normal file
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@ -0,0 +1,325 @@
/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if (defined (USB_STM_HAL) && defined(TARGET_STM32F4)) \
|| defined(TARGET_STM32F2) || defined (TARGET_STM32F7) || defined (TARGET_STM32F3) || defined (TARGET_STM32L4)
#include "USBHAL.h"
#include "pinmap.h"
/* mbed endpoint definition to hal definition */
#define EP_ADDR(ep) (((ep) >> 1)|((ep) & 1) << 7)
/* from hal definition to mbed definition */
#define ADDR_EPIN(ep) (((ep) << 1) | 1)
#define ADDR_EPOUT(ep) (((ep) << 1))
/* id to detect if rx buffer is used or not */
#include "USBHAL_STM_TARGET.h"
/* this call at device reception completion on a Out Enpoint */
void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
uint8_t endpoint = ADDR_EPOUT(epnum);
priv->epComplete[endpoint] = 1;
/* -2 endpoint 0 In out are not in call back list */
if (epnum) {
bool (USBHAL::*func)(void) = priv->epCallback[endpoint-2];
(obj->*func)();
} else {
void (USBHAL::*func)(void) = priv->ep0_out;
(obj->*func)();
}
}
/* this is call at device transmission completion on In endpoint */
void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
uint8_t endpoint = ADDR_EPIN(epnum);
priv->epComplete[endpoint] = 1;
/* -2 endpoint 0 In out are not in call back list */
if (epnum) {
bool (USBHAL::*func)(void) = priv->epCallback[endpoint-2];
(obj->*func)();
} else {
void (USBHAL::*func)(void) = priv->ep0_in;
(obj->*func)();
}
}
/* This is call at device set up reception */
void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
void (USBHAL::*func)(void)=priv->ep0_setup;
void (USBHAL::*func1)(void)=priv->ep0_read;
(obj->*func)();
(obj->*func1)();
}
void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->suspend_change;
(obj->*func)(1);
}
void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->suspend_change;
(obj->*func)(0);
}
void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->connect_change;
(obj->*func)(1);
}
void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
void (USBHAL::*func)(unsigned int suspended) = priv->connect_change;
(obj->*func)(0);
}
void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
unsigned int i;
for(i=0;i<hpcd->Init.dev_endpoints;i++) {
priv->epComplete[2*i]=0;
HAL_PCD_EP_Close(hpcd,EP_ADDR(2*i));
HAL_PCD_EP_Flush(hpcd,EP_ADDR(2*i));
priv->epComplete[2*i+1]=0;
HAL_PCD_EP_Close(hpcd,EP_ADDR(2*i+1));
HAL_PCD_EP_Flush(hpcd,EP_ADDR(2*i+1));
}
void (USBHAL::*func)(void)=priv->bus_reset;
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) = priv->ep_realise;
(obj->*func)();
(obj->*ep_realise)(EP0IN, MAX_PACKET_SIZE_EP0,0);
(obj->*ep_realise)(EP0OUT, MAX_PACKET_SIZE_EP0,0);
}
/* hal pcd handler , used for STM32 HAL PCD Layer */
uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
return 0;
}
USBHAL::~USBHAL(void) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_PCD_DeInit(&hpcd);
delete HALPriv;
}
void USBHAL::connect(void) {
NVIC_EnableIRQ(USBHAL_IRQn);
}
void USBHAL::disconnect(void) {
NVIC_DisableIRQ(USBHAL_IRQn);
}
void USBHAL::configureDevice(void) {
// Not needed
}
void USBHAL::unconfigureDevice(void) {
// Not needed
}
void USBHAL::setAddress(uint8_t address) {
HAL_PCD_SetAddress(&hpcd, address);
EP0write(0, 0);
}
bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) {
uint32_t epIndex = EP_ADDR(endpoint);
uint32_t type;
uint32_t len;
HAL_StatusTypeDef ret;
switch (endpoint) {
case EP0IN:
case EP0OUT:
type = 0;
break;
case EPISO_IN:
case EPISO_OUT:
type = 1;
break;
case EPBULK_IN:
case EPBULK_OUT:
type = 2;
break;
case EPINT_IN:
case EPINT_OUT:
type = 3;
break;
}
if (maxPacket > MAXTRANSFER_SIZE) return false;
if (epIndex & 0x80) {
len = HAL_PCDEx_GetTxFiFo(&hpcd,epIndex & 0x7f);
MBED_ASSERT(len >= maxPacket);
}
ret = HAL_PCD_EP_Open(&hpcd, epIndex, maxPacket, type);
MBED_ASSERT(ret!=HAL_BUSY);
return (ret == HAL_OK) ? true:false;
}
// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) {
memcpy(buffer, hpcd.Setup, MAX_PACKET_SIZE_SETUP);
memset(hpcd.Setup,0,MAX_PACKET_SIZE_SETUP);
}
void USBHAL::EP0readStage(void) {
}
void USBHAL::EP0read(void) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t epIndex = EP_ADDR(EP0OUT);
uint8_t *pBuf = (uint8_t *)HALPriv->pBufRx0;
HAL_StatusTypeDef ret;
HALPriv->epComplete[EP0OUT] = 2;
ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, MAX_PACKET_SIZE_EP0 );
MBED_ASSERT(ret!=HAL_BUSY);
}
uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)hpcd.pData;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, 0);
HALPriv->epComplete[EP0OUT] = 0;
if (length) {
uint8_t *buff = (uint8_t *)HALPriv->pBufRx0;
memcpy(buffer, buff, length);
}
return length;
}
void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
/* check that endpoint maximum size is not exceeding TX fifo */
MBED_ASSERT(hpcd.IN_ep[0].maxpacket >= size);
endpointWrite(EP0IN, buffer, size);
}
void USBHAL::EP0getWriteResult(void) {
}
void USBHAL::EP0stall(void) {
stallEndpoint(EP0IN);
}
EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t* pBuf = (uint8_t *)HALPriv->pBufRx;
HAL_StatusTypeDef ret;
// clean reception end flag before requesting reception
HALPriv->epComplete[endpoint] = 2;
ret = HAL_PCD_EP_Receive(&hpcd, epIndex, pBuf, maximumSize);
MBED_ASSERT(ret!=HAL_BUSY);
return EP_PENDING;
}
EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint]==0) {
/* no reception possible !!! */
bytesRead = 0;
return EP_COMPLETED;
}else if ((HALPriv->epComplete[endpoint]!=1))
return EP_PENDING;
uint32_t epIndex = EP_ADDR(endpoint);
uint8_t *buff = (uint8_t *)HALPriv->pBufRx;
uint32_t length = (uint32_t) HAL_PCD_EP_GetRxCount(&hpcd, epIndex);
memcpy(buffer, buff, length);
*bytesRead = length;
HALPriv->epComplete[endpoint]= 0;
return EP_COMPLETED;
}
EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
uint32_t epIndex = EP_ADDR(endpoint);
HAL_StatusTypeDef ret;
// clean transmission end flag before requesting transmission
HALPriv->epComplete[endpoint] = 2;
ret = HAL_PCD_EP_Transmit(&hpcd, epIndex, data, size);
MBED_ASSERT(ret!=HAL_BUSY);
// update the status
if (ret != HAL_OK) return EP_INVALID;
// fix me return is too simple
return EP_PENDING;
}
EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
if (HALPriv->epComplete[endpoint] == 1)
return EP_COMPLETED;
return EP_PENDING;
}
void USBHAL::stallEndpoint(uint8_t endpoint) {
USBHAL_Private_t *HALPriv = (USBHAL_Private_t *)(hpcd.pData);
HAL_StatusTypeDef ret;
HALPriv->epComplete[endpoint] = 0;
ret = HAL_PCD_EP_SetStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret!=HAL_BUSY);
}
void USBHAL::unstallEndpoint(uint8_t endpoint) {
HAL_StatusTypeDef ret;
ret = HAL_PCD_EP_ClrStall(&hpcd, EP_ADDR(endpoint));
MBED_ASSERT(ret!=HAL_BUSY);
}
bool USBHAL::getEndpointStallState(uint8_t endpoint) {
return false;
}
void USBHAL::remoteWakeup(void) {
}
void USBHAL::_usbisr(void) {
instance->usbisr();
}
void USBHAL::usbisr(void) {
HAL_PCD_IRQHandler(&instance->hpcd);
}
#endif

128
features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM32F303ZE.h Normal file
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@ -0,0 +1,128 @@
/* Copyright (c) 2016 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef USBHAL_STM32F303ZE_H
#define USBHAL_STM32F303ZE_H
#define USBHAL_IRQn USB_LP_CAN_RX0_IRQn
/* must be multiple of 4 bytes */
#define NB_ENDPOINT 8
#define MAXTRANSFER_SIZE 0x200
#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
#if (FIFO_USB_RAM_SIZE > 0x500)
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
void (USBHAL::*sof)(int frame);
void (USBHAL::*connect_change)(unsigned int connected);
void (USBHAL::*suspend_change)(unsigned int suspended);
void (USBHAL::*ep0_setup)(void);
void (USBHAL::*ep0_in)(void);
void (USBHAL::*ep0_out)(void);
void (USBHAL::*ep0_read)(void);
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
bool (USBHAL::*epCallback[6])(void);
uint8_t epComplete[2*NB_ENDPOINT];
/* memorize dummy buffer used for reception */
uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
gpio_t usb_switch;
}USBHAL_Private_t;
uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
{
return 1024;
}
void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state){
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
gpio_write(&(priv->usb_switch),state);
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
uint32_t sofnum = (hpcd->Instance->FNR) & USB_FNR_FN;
void (USBHAL::*func)(int frame) = priv->sof;
/* fix me call with same frame number */
(obj->*func)(sofnum);
}
USBHAL * USBHAL::instance;
USBHAL::USBHAL(void) {
/* init parameter */
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
hpcd.Instance = USB;
/* initialized Init to zero (constructor does not zero initialized the
* area */
/* initialized all field of init including 0 field */
/* constructor does not fill with zero */
memset(&hpcd.Init, 0, sizeof(hpcd.Init));
hpcd.Init.dev_endpoints = NB_ENDPOINT;
hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd.Init.Sof_enable = 1;
hpcd.Init.speed = PCD_SPEED_FULL;
/* pass instance for usage inside call back */
HALPriv->inst = this;
HALPriv->bus_reset = &USBHAL::busReset;
HALPriv->suspend_change = &USBHAL::suspendStateChanged;
HALPriv->connect_change = &USBHAL::connectStateChanged;
HALPriv->sof = &USBHAL::SOF;
HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
HALPriv->ep_realise = &USBHAL::realiseEndpoint;
HALPriv->ep0_in = &USBHAL::EP0in;
HALPriv->ep0_out = &USBHAL::EP0out;
HALPriv->ep0_read = &USBHAL::EP0read;
hpcd.pData = (void*)HALPriv;
HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
instance = this;
__HAL_RCC_GPIOA_CLK_ENABLE();
/* Configure USB DM pin. This is optional, and maintained only for user guidance. */
pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_USB));
pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF14_USB));
__HAL_RCC_GPIOG_CLK_ENABLE();
gpio_init_out(&HALPriv->usb_switch,PG_6);
/* Enable USB Clock */
__HAL_RCC_USB_CLK_ENABLE();
/* Enable SYSCFG Clock */
__HAL_RCC_SYSCFG_CLK_ENABLE();
hpcd.State = HAL_PCD_STATE_RESET;
HAL_PCD_Init(&hpcd);
/* hardcoded size of FIFO according definition*/
HAL_PCDEx_PMAConfig(&hpcd , 0x00 , PCD_SNG_BUF, 0x30);
HAL_PCDEx_PMAConfig(&hpcd , 0x80 , PCD_SNG_BUF, 0x70);
#if 1
HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_DBL_BUF, 0x018000b0);
#else
HAL_PCDEx_PMAConfig(&hpcd , 0x3, PCD_SNG_BUF, 0x180);
#endif
HAL_PCDEx_PMAConfig(&hpcd , 0x83, PCD_SNG_BUF, 0xb0);
NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
NVIC_SetPriority(USBHAL_IRQn, 1);
HAL_PCD_Start(&hpcd);
}
#endif

145
features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM32L476VG.h Normal file
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@ -0,0 +1,145 @@
/* Copyright (c) 2016 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef USBHAL_STM32L476VG
#define USBHAL_STM32L476VG
#define USBHAL_IRQn OTG_FS_IRQn
#define NB_ENDPOINT 4
/* must be multiple of 4 bytes */
#define MAXTRANSFER_SIZE 0x200
#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
#if (FIFO_USB_RAM_SIZE > 0x500)
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
void (USBHAL::*sof)(int frame);
void (USBHAL::*connect_change)(unsigned int connected);
void (USBHAL::*suspend_change)(unsigned int suspended);
void (USBHAL::*ep0_setup)(void);
void (USBHAL::*ep0_in)(void);
void (USBHAL::*ep0_out)(void);
void (USBHAL::*ep0_read)(void);
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
uint8_t epComplete[8];
/* memorize dummy buffer used for reception */
uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
}USBHAL_Private_t;
uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
{
uint32_t len;
if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
else
len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
return len*4;
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd) {
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
void (USBHAL::*func)(int frame) = priv->sof;
/* fix me call with same frame number */
(obj->*func)(sofnum);
}
USBHAL * USBHAL::instance;
USBHAL::USBHAL(void) {
/* init parameter */
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
/* initialized all field of init including 0 field */
/* constructor does not fill with zero */
hpcd.Instance = USB_OTG_FS;
/* initialized all field of init including 0 field */
/* constructor does not fill with zero */
memset(&hpcd.Init, 0, sizeof(hpcd.Init));
hpcd.Init.dev_endpoints = NB_ENDPOINT;
hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd.Init.Sof_enable = 1;
hpcd.Init.speed = PCD_SPEED_FULL;
/* pass instance for usage inside call back */
HALPriv->inst = this;
HALPriv->bus_reset = &USBHAL::busReset;
HALPriv->suspend_change = &USBHAL::suspendStateChanged;
HALPriv->connect_change = &USBHAL::connectStateChanged;
HALPriv->sof = &USBHAL::SOF;
HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
HALPriv->ep_realise = &USBHAL::realiseEndpoint;
HALPriv->ep0_in = &USBHAL::EP0in;
HALPriv->ep0_out = &USBHAL::EP0out;
HALPriv->ep0_read = &USBHAL::EP0read;
hpcd.pData = (void*)HALPriv;
HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
instance = this;
__HAL_RCC_PWR_CLK_ENABLE();
HAL_PWREx_EnableVddUSB();
/* Configure USB VBUS GPIO */
__HAL_RCC_GPIOC_CLK_ENABLE();
/* Configure USB FS GPIOs */
__HAL_RCC_GPIOA_CLK_ENABLE();
/* Configure DM DP Pins */
pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
/* Configure VBUS Pin */
pin_function(PC_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
hpcd.State = HAL_PCD_STATE_RESET;
HAL_PCD_Init(&hpcd);
/* 1.25kbytes */
/* min value 16 (= 16 x 4 bytes) */
/* max value 256 (= 1K bytes ) */
/* maximum sum is 0x140 */
HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
/* bulk/int 64 bytes in FS */
HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
/* bulk/int bytes in FS */
HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4));
HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
/* ISOchronous */
HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
NVIC_SetVector(USBHAL_IRQn,(uint32_t)&_usbisr);
NVIC_SetPriority( USBHAL_IRQn, 1);
HAL_PCD_Start(&hpcd);
}
#endif

133
features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM_144_64pins.h Normal file
View File

@ -0,0 +1,133 @@
/* Copyright (c) 2016 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifndef USBHAL_STM32_144_64
#define USBHAL_STM32_144_64
#define USBHAL_IRQn OTG_FS_IRQn
/* must be multiple of 4 bytes */
#define NB_ENDPOINT 4
#define MAXTRANSFER_SIZE 0x200
#define FIFO_USB_RAM_SIZE (MAXTRANSFER_SIZE+MAX_PACKET_SIZE_EP0+MAX_PACKET_SIZE_EP1+MAX_PACKET_SIZE_EP2+MAX_PACKET_SIZE_EP3)
#if (FIFO_USB_RAM_SIZE > 0x500)
#error "FIFO dimensioning incorrect"
#endif
typedef struct
{
USBHAL *inst;
void (USBHAL::*bus_reset)(void);
void (USBHAL::*sof)(int frame);
void (USBHAL::*connect_change)(unsigned int connected);
void (USBHAL::*suspend_change)(unsigned int suspended);
void (USBHAL::*ep0_setup)(void);
void (USBHAL::*ep0_in)(void);
void (USBHAL::*ep0_out)(void);
void (USBHAL::*ep0_read)(void);
bool (USBHAL::*ep_realise)(uint8_t endpoint, uint32_t maxPacket, uint32_t flags);
bool (USBHAL::*epCallback[2*NB_ENDPOINT-2])(void);
/* memorize dummy buffer used for reception */
uint32_t pBufRx[MAXTRANSFER_SIZE>>2];
uint32_t pBufRx0[MAX_PACKET_SIZE_EP0>>2];
uint8_t epComplete[2*NB_ENDPOINT];
}USBHAL_Private_t;
uint32_t HAL_PCDEx_GetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo)
{
uint32_t len;
if (fifo == 0) len = hpcd->Instance->DIEPTXF0_HNPTXFSIZ>>16;
else
len = hpcd->Instance->DIEPTXF[fifo - 1] >> 16;
return len*4;
}
void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
USBHAL_Private_t *priv=((USBHAL_Private_t *)(hpcd->pData));
USBHAL *obj= priv->inst;
USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
uint32_t sofnum = (USBx_DEVICE->DSTS & USB_OTG_DSTS_FNSOF) >> 8;
void (USBHAL::*func)(int frame) = priv->sof;
/* fix me call with same frame number */
(obj->*func)(sofnum);
}
USBHAL * USBHAL::instance;
USBHAL::USBHAL(void) {
/* init parameter */
USBHAL_Private_t *HALPriv = new(USBHAL_Private_t);
hpcd.Instance = USB_OTG_FS;
memset(&hpcd.Init, 0, sizeof(hpcd.Init));
hpcd.Init.dev_endpoints = NB_ENDPOINT;
hpcd.Init.ep0_mps = MAX_PACKET_SIZE_EP0;
hpcd.Init.phy_itface = PCD_PHY_EMBEDDED;
hpcd.Init.Sof_enable = 1;
hpcd.Init.speed = PCD_SPEED_FULL;
//hpcd.Init.vbus_sensing_enable = 0;
//hpcd.Init.lpm_enable = 0;
/* pass instance for usage inside call back */
HALPriv->inst = this;
HALPriv->bus_reset = &USBHAL::busReset;
HALPriv->suspend_change = &USBHAL::suspendStateChanged;
HALPriv->connect_change = &USBHAL::connectStateChanged;
HALPriv->sof = &USBHAL::SOF;
HALPriv->ep0_setup = &USBHAL::EP0setupCallback;
HALPriv->ep_realise = &USBHAL::realiseEndpoint;
HALPriv->ep0_in = &USBHAL::EP0in;
HALPriv->ep0_out = &USBHAL::EP0out;
HALPriv->ep0_read = &USBHAL::EP0read;
hpcd.pData = (void*)HALPriv;
HALPriv->epCallback[0] = &USBHAL::EP1_OUT_callback;
HALPriv->epCallback[1] = &USBHAL::EP1_IN_callback;
HALPriv->epCallback[2] = &USBHAL::EP2_OUT_callback;
HALPriv->epCallback[3] = &USBHAL::EP2_IN_callback;
HALPriv->epCallback[4] = &USBHAL::EP3_OUT_callback;
HALPriv->epCallback[5] = &USBHAL::EP3_IN_callback;
instance = this;
// Enable power and clocking
/* board 144 pin all similar */
__HAL_RCC_GPIOA_CLK_ENABLE();
pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, GPIO_AF10_OTG_FS));
pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
__HAL_RCC_USB_OTG_FS_CLK_ENABLE();
__HAL_RCC_SYSCFG_CLK_ENABLE();
hpcd.State = HAL_PCD_STATE_RESET;
HAL_PCD_Init(&hpcd);
/* 1.25kbytes */
/* min value 16 (= 16 x 4 bytes) */
/* max value 256 (= 1K bytes ) */
/* maximum sum is 0x140 */
HAL_PCDEx_SetRxFiFo(&hpcd, (MAXTRANSFER_SIZE/4));
/* bulk/int 64 bytes in FS */
HAL_PCDEx_SetTxFiFo(&hpcd, 0, (MAX_PACKET_SIZE_EP0/4)+1);
/* bulk/int bytes in FS */
HAL_PCDEx_SetTxFiFo(&hpcd, 1, (MAX_PACKET_SIZE_EP1/4));
HAL_PCDEx_SetTxFiFo(&hpcd, 2, (MAX_PACKET_SIZE_EP2/4));
/* ISOchronous */
HAL_PCDEx_SetTxFiFo(&hpcd, 3, (MAX_PACKET_SIZE_EP3/4));
NVIC_SetVector(USBHAL_IRQn, (uint32_t)&_usbisr);
NVIC_SetPriority(USBHAL_IRQn, 1);
HAL_PCD_Start(&hpcd);
}
#endif

28
features/unsupported/USBDevice/USBDevice/TARGET_STM/USBHAL_STM_TARGET.h Normal file
View File

@ -0,0 +1,28 @@
/* Copyright (c) 2016 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#ifdef TARGET_STM32F303ZE
#include "USBHAL_STM32F303ZE.h"
#endif
#if defined(TARGET_STM32F429ZI) || defined(TARGET_STM32F446ZE) || defined(TARGET_STM32F207ZG) \
|| defined(TARGET_STM32F767ZI) || defined (TARGET_STM32F746ZG) || defined(TARGET_STM32F411RE) \
|| defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE)
#include "USBHAL_STM_144_64pins.h"
#endif
#ifdef TARGET_STM32L476VG
#include "USBHAL_STM32L476VG.h"
#endif

4
features/unsupported/USBDevice/USBDevice/USBEndpoints.h
View File

@ -43,8 +43,10 @@ typedef enum {
#include "USBEndpoints_LPC11U.h"
#elif defined(TARGET_KL25Z) | defined(TARGET_KL26Z) | defined(TARGET_KL27Z) | defined(TARGET_KL43Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D50M) | defined(TARGET_K64F) | defined(TARGET_K22F) | defined(TARGET_TEENSY3_1)
#include "USBEndpoints_KL25Z.h"
#elif defined (TARGET_STM32F4)
#elif !defined(USB_STM_HAL) && defined(TARGET_STM32F4)
#include "USBEndpoints_STM32F4.h"
#elif defined (TARGET_STM32F4) || defined (TARGET_STM32F2) || defined (TARGET_STM32F7) || defined (TARGET_STM32F3) || defined(TARGET_STM32L4)
#include "USBEndpoints_STM32.h"
#elif defined (TARGET_RZ_A1H) || defined (TARGET_VK_RZ_A1H)
#include "USBEndpoints_RZ_A1H.h"
#elif defined(TARGET_Maxim)

67
features/unsupported/USBDevice/USBDevice/USBEndpoints_STM32.h Normal file
View File

@ -0,0 +1,67 @@
/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#define NUMBER_OF_LOGICAL_ENDPOINTS (4)
#define NUMBER_OF_PHYSICAL_ENDPOINTS (NUMBER_OF_LOGICAL_ENDPOINTS * 2)
/* Define physical endpoint numbers */
/* Endpoint No. Type(s) MaxPacket DoubleBuffer */
/* ---------------- ------------ ---------- --- */
#define EP0OUT (0) /* Control 64 No */
#define EP0IN (1) /* Control 64 No */
#define EP1OUT (2) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP1IN (3) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP2OUT (4) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP2IN (5) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP3OUT (6) /* Int/Bulk/Iso 64/64/1023 Yes */
#define EP3IN (7) /* Int/Bulk/Iso 64/64/1023 Yes */
/* Maximum Packet sizes */
#define MAX_PACKET_SIZE_SETUP (48)
#define MAX_PACKET_SIZE_EP0 (64)
#define MAX_PACKET_SIZE_EP1 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP2 (64) /* Int/Bulk */
#define MAX_PACKET_SIZE_EP3 (200) /* Int/Bulk/iso (44100 stereo 16 bits) */
#define MAX_PACKET_SIZE_EP1_ISO (1023) /* Isochronous */
#define MAX_PACKET_SIZE_EP2_ISO (1023) /* Isochronous */
#define MAX_PACKET_SIZE_EP3_ISO (1023) /* Isochronous */
/* Generic endpoints - intended to be portable accross devices */
/* and be suitable for simple USB devices. */
/* Bulk endpoint */
#define EPBULK_OUT (EP2OUT)
#define EPBULK_IN (EP2IN)
#define EPBULK_OUT_callback EP2_OUT_callback
#define EPBULK_IN_callback EP2_IN_callback
/* Interrupt endpoint */
#define EPINT_OUT (EP1OUT)
#define EPINT_IN (EP1IN)
#define EPINT_OUT_callback EP1_OUT_callback
#define EPINT_IN_callback EP1_IN_callback
/* Isochronous endpoint */
#define EPISO_OUT (EP3OUT)
#define EPISO_IN (EP3IN)
#define EPISO_OUT_callback EP3_OUT_callback
#define EPISO_IN_callback EP3_IN_callback
#define MAX_PACKET_SIZE_EPBULK (MAX_PACKET_SIZE_EP2)
#define MAX_PACKET_SIZE_EPINT (MAX_PACKET_SIZE_EP1)
#define MAX_PACKET_SIZE_EPISO (MAX_PACKET_SIZE_EP3_ISO)

10
features/unsupported/USBDevice/USBDevice/USBHAL.h
View File

@ -109,11 +109,13 @@ private:
static USBHAL * instance;
#if defined(TARGET_LPC11UXX) || defined(TARGET_LPC11U6X) || defined(TARGET_LPC1347) || defined(TARGET_LPC1549)
bool (USBHAL::*epCallback[10 - 2])(void);
#elif defined(TARGET_STM32F4)
bool (USBHAL::*epCallback[8 - 2])(void);
bool (USBHAL::*epCallback[10 - 2])(void);
#elif defined(TARGET_STM32F4) && !defined(USB_STM_HAL)
bool (USBHAL::*epCallback[8 - 2])(void);
#elif defined(TARGET_STM32F4) || defined(TARGET_STM32F3) || defined (TARGET_STM32F2)|| defined(TARGET_STM32L4) || defined(TARGET_STM32F7)
PCD_HandleTypeDef hpcd;
#else
bool (USBHAL::*epCallback[32 - 2])(void);
bool (USBHAL::*epCallback[32 - 2])(void);
#endif

2
features/unsupported/USBDevice/USBDevice/USBHAL_STM32F4.cpp
View File

@ -16,7 +16,7 @@
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/
#if defined(TARGET_STM32F4)
#if defined(TARGET_STM32F4) && !defined(USB_STM_HAL)
#include "USBHAL.h"
#include "USBRegs_STM32.h"

5
features/unsupported/USBDevice/USBSerial/USBSerial.cpp
View File

@ -56,8 +56,9 @@ bool USBSerial::EPBULK_OUT_callback() {
buf.queue(c[i]);
}
//call a potential handler
rx.call();
//call a potential handlenr
if (rx)
rx.call();
return true;
}

21
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_def.h
View File

@ -123,6 +123,27 @@ typedef enum
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
#if defined ( __GNUC__ )
#ifndef __weak

43
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pcd.c
View File

@ -144,12 +144,18 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if(hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
hpcd->EPLock[i].Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
}
hpcd->State = HAL_PCD_STATE_BUSY;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@ -393,7 +399,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@ -973,8 +979,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7FU) == 0U )
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
@ -983,7 +989,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1024,7 +1030,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7FU) == 0U )
{
@ -1035,8 +1041,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1064,13 +1070,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7FU) == 0U)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1098,9 +1104,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPClearStall(hpcd->Instance , ep);
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1113,7 +1119,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x80U) == 0x80U)
{
@ -1124,8 +1130,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1247,8 +1253,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
if(len <= 0U)
{
fifoemptymsk = 0x1U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
}
return HAL_OK;

5
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_pcd.h
View File

@ -75,6 +75,10 @@ typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
typedef struct
{
HAL_LockTypeDef Lock;
} PCD_EPLockDef;
/**
* @brief PCD Handle Structure definition
*/
@ -85,6 +89,7 @@ typedef struct
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
PCD_EPLockDef EPLock[15];
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
void *pData; /*!< Pointer to upper stack Handler */

4
targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_ll_usb.c
View File

@ -590,7 +590,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num);
}
}
}
@ -708,7 +708,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num));
}
}

21
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h
View File

@ -122,6 +122,27 @@ typedef enum
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
#if defined ( __GNUC__ )
#ifndef __weak

5
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.c
View File

@ -156,7 +156,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
hpcd->EPLock[i].Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
}
@ -185,8 +186,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->OUT_ep[i].maxpacket = 0;
hpcd->OUT_ep[i].xfer_buff = 0;
hpcd->OUT_ep[i].xfer_len = 0;
}
/* Init Device */
/*CNTR_FRES = 1*/
hpcd->Instance->CNTR = USB_CNTR_FRES;

6
targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_pcd.h
View File

@ -171,6 +171,11 @@ typedef struct
typedef USB_TypeDef PCD_TypeDef;
typedef struct
{
HAL_LockTypeDef Lock;
} PCD_EPLockDef;
/**
* @brief PCD Handle Structure definition
*/
@ -182,6 +187,7 @@ typedef struct
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
PCD_EPLockDef EPLock[15];
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
void *pData; /*!< Pointer to upper stack Handler */

22
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h
View File

@ -122,6 +122,28 @@ typedef enum
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
#endif /* USE_RTOS */
#if defined ( __GNUC__ )

58
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c
View File

@ -148,11 +148,17 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if(hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
hpcd->EPLock[i].Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
}
hpcd->State = HAL_PCD_STATE_BUSY;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@ -190,7 +196,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->Instance->DIEPTXF[i] = 0U;
}
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
@ -296,10 +301,10 @@ __weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
//__HAL_LOCK(hpcd);
USB_DevConnect (hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
__HAL_UNLOCK(hpcd);
//__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -310,11 +315,11 @@ HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
__HAL_LOCK(hpcd);
//__HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
USB_DevDisconnect(hpcd->Instance);
__HAL_UNLOCK(hpcd);
//__HAL_UNLOCK(hpcd);
return HAL_OK;
}
@ -421,7 +426,8 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK,fifoemptymsk);
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@ -440,7 +446,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
/* prepare to rx more setup packets */
USB_EP0_OutStart(hpcd->Instance, 1U, (uint8_t *)hpcd->Setup);
}
}
}
}
if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
@ -968,9 +974,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint
ep->data_pid_start = 0U;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_ActivateEndpoint(hpcd->Instance , ep);
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return ret;
}
@ -997,9 +1003,9 @@ HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->is_in = (0x80U & ep_addr) != 0U;
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_DeactivateEndpoint(hpcd->Instance , ep);
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return HAL_OK;
}
@ -1030,7 +1036,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
if ((ep_addr & 0x7FU) == 0U)
{
@ -1040,7 +1046,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return HAL_OK;
}
@ -1081,7 +1087,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
if ((ep_addr & 0x7FU) == 0U)
{
@ -1092,7 +1098,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return HAL_OK;
}
@ -1121,13 +1127,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7FU) == 0U)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return HAL_OK;
}
@ -1155,9 +1161,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->num = ep_addr & 0x7FU;
ep->is_in = ((ep_addr & 0x80U) == 0x80U);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_EPClearStall(hpcd->Instance , ep);
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return HAL_OK;
}
@ -1170,8 +1176,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
if ((ep_addr & 0x80U) == 0x80U)
{
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
@ -1181,7 +1186,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
return HAL_OK;
}
@ -1304,8 +1309,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
if(len <= 0U)
{
fifoemptymsk = 0x1U << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
}
return HAL_OK;

11
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h
View File

@ -92,14 +92,21 @@ typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
/**
* @brief PCD Handle Structure definition
*/
*/
typedef struct
{
HAL_LockTypeDef Lock;
} PCD_EPLockDef;
typedef struct
{
PCD_TypeDef *Instance; /*!< Register base address */
PCD_InitTypeDef Init; /*!< PCD required parameters */
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
PCD_EPLockDef EPLock[15]; /*!< PCD endpoint peripheral status */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
#ifdef USB_OTG_GLPMCFG_LPMEN

4
targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c
View File

@ -607,7 +607,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
USBx_DEVICE->DIEPEMPMSK |= 1U << ep->num;
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << ep->num);
}
}
}
@ -725,7 +725,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << (ep->num));
}
}

22
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h
View File

@ -122,6 +122,28 @@ typedef enum
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
#if defined ( __GNUC__ )
#ifndef __weak

37
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c
View File

@ -145,6 +145,16 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
if(hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
hpcd->EPLock[i].Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
}
hpcd->State = HAL_PCD_STATE_BUSY;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
@ -186,7 +196,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->Instance->DIEPTXF[i] = 0;
}
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
@ -406,7 +415,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1 << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@ -1014,7 +1023,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7F) == 0 )
{
@ -1024,7 +1033,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1065,7 +1074,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->dma_addr = (uint32_t)pBuf;
}
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7F) == 0 )
{
@ -1076,8 +1085,8 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1105,13 +1114,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7F) == 0)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1139,9 +1148,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPClearStall(hpcd->Instance , ep);
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1154,7 +1163,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x80) == 0x80)
{
@ -1165,7 +1174,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1288,7 +1297,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
if(len <= 0)
{
fifoemptymsk = 0x1 << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
}

6
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h
View File

@ -83,7 +83,10 @@ typedef enum
typedef USB_OTG_GlobalTypeDef PCD_TypeDef;
typedef USB_OTG_CfgTypeDef PCD_InitTypeDef;
typedef USB_OTG_EPTypeDef PCD_EPTypeDef ;
typedef struct
{
HAL_LockTypeDef Lock;
} PCD_EPLockDef;
/**
* @brief PCD Handle Structure definition
*/
@ -94,6 +97,7 @@ typedef struct
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
PCD_EPLockDef EPLock[15];
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */

4
targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c
View File

@ -594,7 +594,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num);
}
}
}
@ -712,7 +712,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num));
}
}

2
targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld
View File

@ -140,7 +140,7 @@ SECTIONS
.stack_dummy (COPY):
{
*(.stack*)
} > SRAM2
} > SRAM1
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */

8
targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device/TOOLCHAIN_IAR/stm32l476xx.icf
View File

@ -19,8 +19,8 @@ define region SRAM2_region = mem:[from __region_SRAM2_start__ to __region_SRAM2_
define region SRAM1_region = mem:[from __region_SRAM1_start__ to __region_SRAM1_end__];
/* Stack 1/8 and Heap 1/4 of RAM */
define symbol __size_cstack__ = 0x4000;
define symbol __size_heap__ = 0x8000;
define symbol __size_cstack__ = 0x8000;
define symbol __size_heap__ = 0xa000;
define block CSTACK with alignment = 8, size = __size_cstack__ { };
define block HEAP with alignment = 8, size = __size_heap__ { };
define block STACKHEAP with fixed order { block HEAP, block CSTACK };
@ -31,5 +31,5 @@ do not initialize { section .noinit };
place at address mem:__intvec_start__ { readonly section .intvec };
place in ROM_region { readonly };
place in SRAM2_region { readwrite };
place in SRAM1_region { block STACKHEAP };
place in SRAM1_region { readwrite, block STACKHEAP };
place in SRAM2_region { };

38
targets/TARGET_STM/TARGET_STM32L4/TARGET_DISCO_L476VG/device/system_stm32l4xx.c
View File

@ -530,7 +530,8 @@ uint8_t SetSysClock_PLL_MSI(void)
{
RCC_ClkInitTypeDef RCC_ClkInitStruct = {0};
RCC_OscInitTypeDef RCC_OscInitStruct = {0};
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
// Enable LSE Oscillator to automatically calibrate the MSI clock
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE; // No PLL update
@ -538,32 +539,39 @@ uint8_t SetSysClock_PLL_MSI(void)
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
RCC->CR |= RCC_CR_MSIPLLEN; // Enable MSI PLL-mode
}
// Enable MSI oscillator and activate PLL with MSI as source
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
HAL_RCCEx_DisableLSECSS();
/* Enable MSI Oscillator and activate PLL with MSI as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_MSI | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI; // 4 MHz
RCC_OscInitStruct.PLL.PLLM = 1; // VCO input clock = 4 MHz (4 MHz / 1)
RCC_OscInitStruct.PLL.PLLN = 40; // VCO output clock = 160 MHz (4 MHz * 40)
RCC_OscInitStruct.PLL.PLLP = 7; // PLLSAI3 clock = 22.86 MHz (160 MHz / 7)
RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock (PLL48M1) = 40 MHz (160 MHz / 4) --> Not good for USB
RCC_OscInitStruct.PLL.PLLR = 2; // PLL clock = 80 MHz (160 MHz / 2)
RCC_OscInitStruct.HSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_11;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_MSI;
RCC_OscInitStruct.PLL.PLLM = 6;
RCC_OscInitStruct.PLL.PLLN = 40;
RCC_OscInitStruct.PLL.PLLP = 7;
RCC_OscInitStruct.PLL.PLLQ = 4;
RCC_OscInitStruct.PLL.PLLR = 4;
if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
{
return 0; // FAIL
}
/* Enable MSI Auto-calibration through LSE */
HAL_RCCEx_EnableMSIPLLMode();
/* Select MSI output as USB clock source */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_MSI;
HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
// Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 80 MHz
RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 80 MHz
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 80 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 80 MHz
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; // 80 MHz
if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_4) != HAL_OK)
{
return 0; // FAIL

22
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_def.h
View File

@ -124,6 +124,28 @@ typedef enum
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0)
#endif /* USE_RTOS */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
static inline void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) | mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
static inline void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
{
uint32_t newValue;
do {
newValue = (uint32_t)__LDREXW((volatile unsigned long *)ptr) &~mask;
} while (__STREXW(newValue,(volatile unsigned long*) ptr));
}
#if defined ( __GNUC__ )
#ifndef __weak

29
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.c
View File

@ -157,7 +157,8 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
{
/* Allocate lock resource and initialize it */
hpcd->Lock = HAL_UNLOCKED;
for (index = 0; index < hpcd->Init.dev_endpoints ; index++)
hpcd->EPLock[index].Lock = HAL_UNLOCKED;
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
}
@ -198,7 +199,6 @@ HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
hpcd->OUT_ep[index].xfer_buff = 0;
hpcd->OUT_ep[index].xfer_len = 0;
}
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
@ -426,7 +426,7 @@ void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1 << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@ -1141,7 +1141,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
ep->is_in = 0;
ep->num = ep_addr & 0x7F;
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7F) == 0 )
{
@ -1151,7 +1151,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, u
{
USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1187,7 +1187,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
ep->is_in = 1;
ep->num = ep_addr & 0x7F;
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x7F) == 0 )
{
@ -1198,7 +1198,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr,
USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1226,13 +1226,13 @@ HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7F) == 0)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1260,9 +1260,9 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
USB_EPClearStall(hpcd->Instance , ep);
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1275,8 +1275,7 @@ HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
__HAL_LOCK(hpcd);
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
if ((ep_addr & 0x80) == 0x80)
{
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
@ -1286,7 +1285,7 @@ HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
USB_FlushRxFifo(hpcd->Instance);
}
__HAL_UNLOCK(hpcd);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
return HAL_OK;
}
@ -1398,7 +1397,7 @@ static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t
if(len <= 0)
{
fifoemptymsk = 0x1 << epnum;
USBx_DEVICE->DIEPEMPMSK &= ~fifoemptymsk;
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
}

5
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_hal_pcd.h
View File

@ -118,6 +118,10 @@ typedef USB_TypeDef PCD_TypeDef;
typedef USB_CfgTypeDef PCD_InitTypeDef;
typedef USB_EPTypeDef PCD_EPTypeDef;
#endif /* USB */
typedef struct
{
HAL_LockTypeDef Lock;
} PCD_EPLockDef;
/**
* @brief PCD Handle Structure definition
@ -130,6 +134,7 @@ typedef struct
PCD_EPTypeDef IN_ep[15]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[15]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
PCD_EPLockDef EPLock[15];
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12]; /*!< Setup packet buffer */
PCD_LPM_StateTypeDef LPM_State; /*!< LPM State */

4
targets/TARGET_STM/TARGET_STM32L4/device/stm32l4xx_ll_usb.c
View File

@ -571,7 +571,7 @@ HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDe
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num);
}
}
@ -677,7 +677,7 @@ HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeD
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << (ep->num));
}
/* EP enable, IN data in FIFO */

10
targets/targets.json
View File

@ -802,7 +802,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"detect_code": ["0720"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USB_STM_HAL"],
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name": "STM32F401RE"
@ -828,7 +828,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"detect_code": ["0740"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USB_STM_HAL"],
"device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name": "STM32F411RE"
@ -855,7 +855,7 @@
"extra_labels": ["STM", "STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "F429_F439"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"progen": {"target": "nucleo-f429zi"},
"macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2"],
"macros": ["RTC_LSI=1", "TRANSACTION_QUEUE_SIZE_SPI=2", "USB_STM_HAL"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES", "TRNG"],
"detect_code": ["0796"],
"features": ["LWIP"],
@ -898,7 +898,7 @@
"supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
"inherits": ["Target"],
"detect_code": ["0778"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USB_STM_HAL"],
"device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "ERROR_RED", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"release_versions": ["2", "5"],
"device_name" : "STM32F446ZE"
@ -1132,7 +1132,7 @@
"core": "Cortex-M4F",
"extra_labels": ["STM", "STM32F4", "STM32F407", "STM32F407VG"],
"supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2"],
"macros": ["TRANSACTION_QUEUE_SIZE_SPI=2", "USB_STM_HAL"],
"device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
"device_name": "STM32F407VG"
},

96
tools/build_travis.py
View File

@ -45,25 +45,25 @@ build_list = (
{ "target": "NUCLEO_F072RB", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F091RC", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F103RB", "toolchains": "GCC_ARM", "libs": ["rtos", "fat"] },
{ "target": "NUCLEO_F207ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F207ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_F302R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F303K8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F303RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F303ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F303ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_F334R8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F401RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_F410RB", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F411RE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_L432KC", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "NUCLEO_L476RG", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "NUCLEO_L011K4", "toolchains": "GCC_ARM", "libs": ["dsp"] },
{ "target": "NUCLEO_L031K6", "toolchains": "GCC_ARM", "libs": ["dsp"] },
{ "target": "NUCLEO_L073RZ", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "NUCLEO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_F446RE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "NUCLEO_F446ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "NUCLEO_F746ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F767ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "NUCLEO_F446ZE", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_F746ZG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "NUCLEO_F767ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "MOTE_L152RC", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
@ -77,7 +77,7 @@ build_list = (
{ "target": "DISCO_F051R8", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "DISCO_F334C8", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "DISCO_F401VC", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "DISCO_F407VG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "DISCO_F407VG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
{ "target": "DISCO_F429ZI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "DISCO_F469NI", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "fat"] },
{ "target": "DISCO_F746NG", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
@ -124,7 +124,8 @@ build_list = (
{ "target": "SAMD21J18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "SAMD21G18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
{ "target": "SAML21J18A", "toolchains": "GCC_ARM", "libs": ["dsp", "fat"] },
)
{ "target": "DISCO_L476VG", "toolchains": "GCC_ARM", "libs": ["dsp", "rtos", "usb", "fat"] },
)
################################################################################
# Configure example test building (linking against external mbed SDK libraries liek fat or rtos)
@ -162,8 +163,79 @@ linking_list = [
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
}
]
},
{"target": "NUCLEO_F446ZE",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F401RE",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F411RE",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F429ZI",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F207ZG",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F746ZG",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F767ZI",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "DISCO_F407VG",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "NUCLEO_F303ZE",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
},
{"target": "DISCO_L476VG",
"toolchains": "GCC_ARM",
"tests": {"" : ["MBED_2", "MBED_10", "MBED_11", "MBED_16"],
"rtos" : ["RTOS_1", "RTOS_2", "RTOS_3"],
"usb" : ["USB_1", "USB_2" ,"USB_3"],
}
}
]
################################################################################