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clk freq header file 

- HAL clock improvement
pull/144/head
0xc0170 2014-01-14 17:51:09 +01:00
parent 4e5993e7ee
commit 937430a130
7 changed files with 169 additions and 15 deletions
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17
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/analogin_api.c
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@ -18,6 +18,7 @@
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "clk_freqs.h"
static const PinMap PinMap_ADC[] = {
{PTC2, ADC0_SE4b, 0},
@ -33,6 +34,8 @@ static const PinMap PinMap_ADC[] = {
{NC, NC, 0}
};
#define MAX_FADC 6000000
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
if (obj->adc == (ADCName)NC)
@ -43,13 +46,23 @@ void analogin_init(analogin_t *obj, PinName pin) {
uint32_t port = (uint32_t)pin >> PORT_SHIFT;
SIM->SCGC5 |= 1 << (SIM_SCGC5_PORTA_SHIFT + port);
// bus clk
uint32_t PCLK = bus_frequency();
uint32_t clkdiv;
for (clkdiv = 0; clkdiv < 4; clkdiv++) {
if ((PCLK >> clkdiv) <= MAX_FADC)
break;
}
if (clkdiv == 4) //Set max div
clkdiv = 0x7;
ADC0->SC1[1] = ADC_SC1_ADCH(obj->adc);
ADC0->CFG1 = ADC_CFG1_ADLPC_MASK // Low-Power Configuration
| ADC_CFG1_ADIV(3) // Clock Divide Select: (Input Clock)/8
| ADC_CFG1_ADIV(clkdiv & 0x3) // Clock Divide Select
| ADC_CFG1_ADLSMP_MASK // Long Sample Time
| ADC_CFG1_MODE(3) // (16)bits Resolution
| ADC_CFG1_ADICLK(1); // Input Clock: (Bus Clock)/2
| ADC_CFG1_ADICLK(clkdiv >> 2); // Input Clock
ADC0->CFG2 = ADC_CFG2_MUXSEL_MASK // ADxxb or ADxxa channels
| ADC_CFG2_ADACKEN_MASK // Asynchronous Clock Output Enable

97
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/clk_freqs.h Normal file
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@ -0,0 +1,97 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef CLK_FREQS_H
#define CLK_FREQS_H
#ifdef __cplusplus
extern "C" {
#endif
/*!
* \brief Get the peripheral bus clock frequency
* \return Bus frequency
*/
static inline uint32_t bus_frequency(void) {
return SystemCoreClock / (((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV4_MASK) >> SIM_CLKDIV1_OUTDIV4_SHIFT) + 1);
}
/*!
* \brief Get external oscillator (crystal) frequency
* \return External osc frequency
*/
static uint32_t extosc_frequency(void) {
uint32_t MCGClock = SystemCoreClock * (1u + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT));
if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(2)) //MCG clock = external reference clock
return MCGClock;
if ((MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0)) { //PLL/FLL is selected
uint32_t divider, multiplier;
if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x0u) { //FLL is selected
if ((MCG->S & MCG_S_IREFST_MASK) == 0x0u) { //FLL uses external reference
divider = (uint8_t)(1u << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
if ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x0u)
divider <<= 5u;
/* Select correct multiplier to calculate the MCG output clock */
switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
case 0x0u:
multiplier = 640u;
break;
case 0x20u:
multiplier = 1280u;
break;
case 0x40u:
multiplier = 1920u;
break;
case 0x60u:
multiplier = 2560u;
break;
case 0x80u:
multiplier = 732u;
break;
case 0xA0u:
multiplier = 1464u;
break;
case 0xC0u:
multiplier = 2197u;
break;
case 0xE0u:
default:
multiplier = 2929u;
break;
}
return MCGClock * divider / multiplier;
}
} else { //PLL is selected
divider = (1u + (MCG->C5 & MCG_C5_PRDIV0_MASK));
multiplier = ((MCG->C6 & MCG_C6_VDIV0_MASK) + 24u);
return MCGClock * divider / multiplier;
}
}
//In all other cases either there is no crystal or we cannot determine it
//For example when the FLL is running on the internal reference, and there is also an
//external crystal. However these are unlikely situations
return 0;
}
#ifdef __cplusplus
}
#endif
#endif

3
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/i2c_api.c
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@ -18,6 +18,7 @@
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "clk_freqs.h"
static const PinMap PinMap_I2C_SDA[] = {
{PTB1, I2C_0, 2},
@ -185,7 +186,7 @@ void i2c_frequency(i2c_t *obj, int hz) {
uint32_t ref = 0;
uint8_t i, j;
// bus clk
uint32_t PCLK = SystemCoreClock/2;
uint32_t PCLK = bus_frequency();
uint32_t pulse = PCLK / (hz * 2);
// we look for the values that minimize the error

19
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/pwmout_api.c
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@ -48,7 +48,7 @@ static const PinMap PinMap_PWM[] = {
{NC , NC , 0}
};
#define PWM_CLOCK_MHZ (0.75) // (48)MHz / 64 = (0.75)MHz
static float pwm_clock = 0;
void pwmout_init(pwmout_t* obj, PinName pin) {
// determine the channel
@ -56,6 +56,17 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
if (pwm == (PWMName)NC)
error("PwmOut pin mapping failed");
uint32_t clkdiv = 0;
float clkval = SystemCoreClock / 1000000.0f;
while (clkval > 1) {
clkdiv++;
clkval /= 2.0;
if (clkdiv == 7)
break;
}
pwm_clock = clkval;
unsigned int port = (unsigned int)pin >> PORT_SHIFT;
unsigned int ftm_n = (pwm >> TPM_SHIFT);
unsigned int ch_n = (pwm & 0xFF);
@ -65,7 +76,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
FTM_Type *ftm = (FTM_Type *)(FTM0_BASE + 0x1000 * ftm_n);
ftm->CONF |= FTM_CONF_BDMMODE(3);
ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(6); // (48)MHz / 64 = (0.75)MHz
ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(clkdiv); // (clock)MHz / clkdiv ~= (0.75)MHz
ftm->CONTROLS[ch_n].CnSC = (FTM_CnSC_MSB_MASK | FTM_CnSC_ELSB_MASK); /* No Interrupts; High True pulses on Edge Aligned PWM */
obj->CnV = &ftm->CONTROLS[ch_n].CnV;
@ -108,7 +119,7 @@ void pwmout_period_ms(pwmout_t* obj, int ms) {
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
float dc = pwmout_read(obj);
*obj->MOD = PWM_CLOCK_MHZ * us;
*obj->MOD = (uint32_t)(pwm_clock * (float)us);
pwmout_write(obj, dc);
}
@ -121,5 +132,5 @@ void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
*obj->CnV = PWM_CLOCK_MHZ * us;
*obj->CnV = (uint32_t)(pwm_clock * (float)us);
}

2
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/serial_api.c
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@ -53,7 +53,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
obj->uart = (UART_Type *)uart;
// enable clk
switch (uart) {
case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK | (1<<SIM_SOPT5_UART0TXSRC_SHIFT);
case UART_0: SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_MASK;
SIM->SCGC5 |= SIM_SCGC5_PORTA_MASK; SIM->SCGC4 |= SIM_SCGC4_UART0_MASK; break;
case UART_1: SIM->SCGC5 |= SIM_SCGC5_PORTC_MASK; SIM->SCGC4 |= SIM_SCGC4_UART1_MASK; break;
case UART_2: SIM->SCGC5 |= SIM_SCGC5_PORTD_MASK; SIM->SCGC4 |= SIM_SCGC4_UART2_MASK; break;

3
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/spi_api.c
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@ -20,6 +20,7 @@
#include "cmsis.h"
#include "pinmap.h"
#include "error.h"
#include "clk_freqs.h"
static const PinMap PinMap_SPI_SCLK[] = {
{PTC5, SPI_0, 2},
@ -125,7 +126,7 @@ void spi_frequency(spi_t *obj, int hz) {
uint32_t ref_prescaler = 0;
// bus clk
uint32_t PCLK = SystemCoreClock;
uint32_t PCLK = bus_frequency();
uint32_t divisor = 2;
uint32_t prescaler;

43
libraries/mbed/targets/hal/TARGET_Freescale/TARGET_K20D5M/us_ticker.c
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@ -16,11 +16,14 @@
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "clk_freqs.h"
static void pit_init(void);
static void lptmr_init(void);
static int us_ticker_inited = 0;
static uint32_t pit_ldval = 0;
void us_ticker_init(void) {
if (us_ticker_inited)
@ -35,7 +38,7 @@ static uint32_t pit_us_ticker_counter = 0;
void pit0_isr(void) {
pit_us_ticker_counter++;
PIT->CHANNEL[0].LDVAL = 48; // 1us
PIT->CHANNEL[0].LDVAL = pit_ldval; // 1us
PIT->CHANNEL[0].TFLG = 1;
}
@ -46,7 +49,9 @@ static void pit_init(void) {
SIM->SCGC6 |= SIM_SCGC6_PIT_MASK; // Clock PIT
PIT->MCR = 0; // Enable PIT
PIT->CHANNEL[0].LDVAL = 48; // 1us
pit_ldval = bus_frequency() / 1000000;
PIT->CHANNEL[0].LDVAL = pit_ldval; // 1us
PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TIE_MASK;
PIT->CHANNEL[0].TCTRL |= PIT_TCTRL_TEN_MASK; // Start timer 1
@ -82,10 +87,36 @@ static void lptmr_init(void) {
NVIC_EnableIRQ(LPTimer_IRQn);
/* Clock at (1)MHz -> (1)tick/us */
OSC0->CR |= OSC_CR_ERCLKEN_MASK;
LPTMR0->PSR = 0;
LPTMR0->PSR |= LPTMR_PSR_PCS(3); // OSCERCLK -> 8MHz
LPTMR0->PSR |= LPTMR_PSR_PRESCALE(2); // divide by 8
/* Check if the external oscillator can be divided to 1MHz */
uint32_t extosc = extosc_frequency();
if (extosc != 0) { //If external oscillator found
OSC0->CR |= OSC_CR_ERCLKEN_MASK;
if (extosc % 1000000u == 0) { //If it is a multiple if 1MHz
extosc /= 1000000;
if (extosc == 1) { //1MHz, set timerprescaler in bypass mode
LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PBYP_MASK;
return;
} else { //See if we can divide it to 1MHz
uint32_t divider = 0;
extosc >>= 1;
while (1) {
if (extosc == 1) {
LPTMR0->PSR = LPTMR_PSR_PCS(3) | LPTMR_PSR_PRESCALE(divider);
return;
}
if (extosc % 2 != 0) //If we can't divide by two anymore
break;
divider++;
extosc >>= 1;
}
}
}
}
//No suitable external oscillator clock -> Use fast internal oscillator (4MHz)
MCG->C1 |= MCG_C1_IRCLKEN_MASK;
MCG->C2 |= MCG_C2_IRCS_MASK;
LPTMR0->PSR = LPTMR_PSR_PCS(0) | LPTMR_PSR_PRESCALE(1);
}
void us_ticker_disable_interrupt(void) {