diff --git a/hal/targets/cmsis/core_caFunc.h b/hal/targets/cmsis/core_caFunc.h
index 9c1a37536a..190a2ba1a0 100644
--- a/hal/targets/cmsis/core_caFunc.h
+++ b/hal/targets/cmsis/core_caFunc.h
@@ -811,6 +811,15 @@ __asm(
 __STATIC_INLINE void __v7_inv_dcache_all(void) {
     __v7_all_cache(0);
 }
+/** \brief  Clean and Invalidate D$ by MVA
+
+    DCCIMVAC. Data cache clean and invalidate by MVA to PoC
+ */
+__STATIC_INLINE void __v7_clean_inv_dcache_mva(void *va) {
+    __MCR(15, 0, (uint32_t)va, 7, 14, 1);
+    __DMB();
+}
+
 #include "core_ca_mmu.h"
 
 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
diff --git a/hal/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c b/hal/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
index 0cb924904d..e312a058c9 100644
--- a/hal/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
+++ b/hal/targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c
@@ -524,7 +524,11 @@ static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
         }
         serial_rx_abort_asynch(obj);
         
+#if defined ( __ICCARM__ )
+        was_masked = __disable_irq_iar();
+#else
         was_masked = __disable_irq();
+#endif /* __ICCARM__ */
         if (obj->serial.uart->SCFSR & 0x93) {
             err_read = obj->serial.uart->SCFSR;
             obj->serial.uart->SCFSR = (err_read & ~0x93);