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Remove Atmel targets

pull/12775/head
MarceloSalazar 2020-04-07 23:17:19 +01:00
parent c0f7670c6f
commit 92d8838296
662 changed files with 0 additions and 242117 deletions
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35
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB,
#if defined(TARGET_SAMR21G18A)
PortC,
#endif
PortMax
} PortName;
#ifdef __cplusplus
}
#endif
#endif

13
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis.h
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in samd21j18a specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "samd21.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21/device/cmsis_nvic.h
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
#endif

150
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
typedef enum {
ADC_0 = 0x0ul,
ADC_1 = 0x1ul,
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum {
DAC_0 = 0x42004800UL
} DACName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_3
// Default peripherals
#define MBED_SPI0 PA18, PA16, PA19, PA17
#define MBED_UART0 PA04, PA05
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA08, PA09
#define MBED_ANALOGOUT0 PA02
#define MBED_ANALOGIN0 PA03
#define MBED_ANALOGIN1 PA08
#define MBED_ANALOGIN2 PB09
#define MBED_ANALOGIN3 PA04
#define MBED_ANALOGIN4 PA05
#define MBED_ANALOGIN5 PA06
#define MBED_ANALOGIN7 PA07
#define MBED_PWMOUT0 PA18
#define MBED_PWMOUT1 PA19
#ifdef __cplusplus
}
#endif
#endif

244
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PA02, ADC_0, 1},
{PA03, ADC_1, 1},
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PA02, DAC_0, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA00, SERCOM1_PAD0, 3},
{PA01, SERCOM1_PAD1, 3},
{PA04, SERCOM0_PAD0, 3},
{PA05, SERCOM0_PAD1, 3},
{PA06, SERCOM0_PAD2, 3},
{PA07, SERCOM0_PAD3, 3},
{PA08, SERCOM0_PAD0, 2},
{PA09, SERCOM0_PAD1, 2},
{PA10, SERCOM0_PAD2, 2},
{PA11, SERCOM0_PAD3, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA17, SERCOM1_PAD1, 2},
{PA18, SERCOM1_PAD2, 2},
{PA19, SERCOM1_PAD3, 2},
{PA20, SERCOM3_PAD2, 3},
{PA21, SERCOM3_PAD3, 3},
{PA22, SERCOM3_PAD0, 2},
{PA23, SERCOM3_PAD1, 2},
{PA24, SERCOM3_PAD2, 2},
{PA25, SERCOM3_PAD3, 2},
{PA30, SERCOM1_PAD2, 3},
{PA31, SERCOM1_PAD3, 3},
{PB02, SERCOM5_PAD0, 3},
{PB03, SERCOM5_PAD1, 3},
{PB08, SERCOM4_PAD0, 3},
{PB09, SERCOM4_PAD1, 3},
{PB10, SERCOM4_PAD2, 3},
{PB11, SERCOM4_PAD3, 3},
{PB22, SERCOM5_PAD2, 3},
{PB23, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA10, SERCOM2_PAD2, 3},
{PA11, SERCOM2_PAD3, 3},
{PA12, SERCOM4_PAD0, 3},
{PA13, SERCOM4_PAD1, 3},
{PA14, SERCOM4_PAD2, 3},
{PA15, SERCOM4_PAD3, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA20, SERCOM5_PAD2, 2},
{PA21, SERCOM5_PAD3, 2},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA24, SERCOM5_PAD2, 3},
{PA25, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA00, PWM_2, 4},
{PA01, PWM_2, 4},
{PA04, PWM_0, 4},
{PA05, PWM_0, 4},
{PA06, PWM_1, 4},
{PA07, PWM_1, 4},
{PA08, PWM_1, 5},
{PA09, PWM_1, 5},
{PA10, PWM_1, 4},
{PA11, PWM_1, 4},
{PA12, PWM_2, 4},
{PA13, PWM_2, 4},
{PA14, PWM_0, 5},
{PA15, PWM_0, 5},
{PA16, PWM_2, 4},
{PA17, PWM_2, 4},
{PA18, PWM_0, 5},
{PA19, PWM_0, 5},
{PA20, PWM_0, 5},
{PA21, PWM_0, 5},
{PA22, PWM_0, 5},
{PA23, PWM_0, 5},
{PA24, PWM_1, 5},
{PA25, PWM_1, 5},
{PA30, PWM_1, 4},
{PA31, PWM_1, 4},
{PB10, PWM_0, 5},
{PB11, PWM_0, 5},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA18, EXTINT_2, 0},
{PA02, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA03, EXTINT_3, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA21, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PA28, EXTINT_8, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA10, EXTINT_10, 0},
{PA30, EXTINT_10, 0},
{PB10, EXTINT_10, 0},
{PA11, EXTINT_11, 0},
{PA31, EXTINT_11, 0},
{PB11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PA14, EXTINT_14, 0},
{PA15, EXTINT_15, 0},
{PA27, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA00, PWM_2, 0},
{PA01, PWM_2, 1},
{PA04, PWM_0, 0},
{PA05, PWM_0, 1},
{PA06, PWM_1, 0},
{PA07, PWM_1, 1},
{PA08, PWM_1, 2},
{PA09, PWM_1, 3},
{PA10, PWM_1, 0},
{PA11, PWM_1, 1},
{PA12, PWM_2, 0},
{PA13, PWM_2, 1},
{PA14, PWM_0, 4},
{PA15, PWM_0, 5},
{PA16, PWM_2, 0},
{PA17, PWM_2, 1},
{PA18, PWM_0, 2},
{PA19, PWM_0, 3},
{PA20, PWM_0, 6},
{PA21, PWM_0, 7},
{PA22, PWM_0, 4},
{PA23, PWM_0, 5},
{PA24, PWM_1, 2},
{PA25, PWM_1, 3},
{PA30, PWM_1, 0},
{PA31, PWM_1, 1},
{PB10, PWM_0, 4},
{PB11, PWM_0, 5},
/* Not connected */
{NC , NC , NC}
};

40
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PeripheralPins.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

95
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA02 = 2,
PA03 = 3,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA28 = 28,
PA30 = 30,
PA31 = 31,
PB02 = 34,
PB03 = 35,
PB08 = 40,
PB09 = 41,
PB10 = 42,
PB11 = 43,
PB22 = 54,
PB23 = 55,
USBTX = PB10,
USBRX = PB11,
LED1 = PA23,
LED2 = PA23,
LED3 = PA23,
LED4 = PA23,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

32
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/mbed_overrides.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

530
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/SAMW25_XPLAINED_PRO/samw25_xplained_pro.h
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/**
* \file
*
* \brief SAM W25 Xplained Pro board definition
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#ifndef SAMW25_XPLAINED_PRO_H_INCLUDED
#define SAMW25_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samd21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMW25_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PA23
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PB23
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PB23A_EIC_EXTINT7
#define SW0_EIC_MUX MUX_PA23A_EIC_EXTINT7
#define SW0_EIC_PINMUX PINMUX_PA23A_EIC_EXTINT7
#define SW0_EIC_LINE 7
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM_MODULE TCC0
#define LED_0_PWM_CHANNEL 0
#define LED_0_PWM_OUTPUT 0
#define LED_0_PWM_PIN PIN_PA23F_TCC0_WO5
#define LED_0_PWM_MUX MUX_PA23F_TCC0_WO5
#define LED_0_PWM_PINMUX PINMUX_PA23F_TCC0_WO5
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PA02
#define EXT1_PIN_4 PIN_PA03
#define EXT1_PIN_5 PIN_PB02
#define EXT1_PIN_6 PIN_PB03
#define EXT1_PIN_7 PIN_PA10
#define EXT1_PIN_8 PIN_PA11
#define EXT1_PIN_9 PIN_PA20
#define EXT1_PIN_10 PIN_PA21
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB11
#define EXT1_PIN_14 PIN_PB10
#define EXT1_PIN_15 PIN_PA17
#define EXT1_PIN_16 PIN_PA18
#define EXT1_PIN_17 PIN_PA16
#define EXT1_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 0
#define EXT1_ADC_0_PIN PIN_PA02B_ADC_AIN0
#define EXT1_ADC_0_MUX MUX_PA02B_ADC_AIN0
#define EXT1_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
#define EXT1_ADC_1_CHANNEL 1
#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TCC0
#define EXT1_PWM_0_CHANNEL 2
#define EXT1_PWM_0_PIN PIN_PA10F_TCC0_WO2
#define EXT1_PWM_0_MUX MUX_PA10F_TCC0_WO2
#define EXT1_PWM_0_PINMUX PINMUX_PA10F_TCC0_WO2
#define EXT1_PWM_1_CHANNEL 3
#define EXT1_PWM_1_PIN PIN_PA11F_TCC0_WO3
#define EXT1_PWM_1_MUX MUX_PA11F_TCC0_WO3
#define EXT1_PWM_1_PINMUX PINMUX_PA11F_TCC0_WO3
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PA20A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PA20A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PA20A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM0
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM1
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PA04
#define EXT3_PIN_4 PIN_PA05
#define EXT3_PIN_5 PIN_PB22
#define EXT3_PIN_6 PIN_PB23
#define EXT3_PIN_7 PIN_PA22
#define EXT3_PIN_8 PIN_PA23
#define EXT3_PIN_9 PIN_PA06
#define EXT3_PIN_10 0
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PA01
#define EXT3_PIN_14 PIN_PA00
#define EXT3_PIN_15 PIN_PA07
#define EXT3_PIN_16 PIN_PA18
#define EXT3_PIN_17 PIN_PA16
#define EXT3_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 4
#define EXT3_ADC_0_PIN PIN_PA04B_ADC_AIN4
#define EXT3_ADC_0_MUX MUX_PA04B_ADC_AIN4
#define EXT3_ADC_0_PINMUX PINMUX_PA04B_ADC_AIN4
#define EXT3_ADC_1_CHANNEL 5
#define EXT3_ADC_1_PIN PIN_PA05B_ADC_AIN5
#define EXT3_ADC_1_MUX MUX_PA05B_ADC_AIN5
#define EXT3_ADC_1_PINMUX PINMUX_PA05B_ADC_AIN5
/** @} */
/** \name Extension header #3 PWM definitions
* @{
*/
#define EXT3_PWM_MODULE TC4
#define EXT3_PWM_0_CHANNEL 0
#define EXT3_PWM_0_PIN PIN_PA22E_TC4_WO0
#define EXT3_PWM_0_MUX MUX_PA22E_TC4_WO0
#define EXT3_PWM_0_PINMUX PINMUX_PA22E_TC4_WO0
#define EXT3_PWM_1_CHANNEL 1
#define EXT3_PWM_1_PIN PIN_PA23E_TC4_WO1
#define EXT3_PWM_1_MUX MUX_PA23E_TC4_WO1
#define EXT3_PWM_1_PINMUX PINMUX_PA23E_TC4_WO1
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 6
#define EXT3_IRQ_PIN PIN_PA06A_EIC_EXTINT6
#define EXT3_IRQ_MUX MUX_PA06A_EIC_EXTINT6
#define EXT3_IRQ_PINMUX PINMUX_PA06A_EIC_EXTINT6
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM0
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM1
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_PA00D_SERCOM1_PAD0
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_PA01D_SERCOM1_PAD1
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM1
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA07 */
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA05
#define USB_VBUS_EIC_LINE 5
#define USB_VBUS_EIC_MUX MUX_PA05A_EIC_EXTINT5
#define USB_VBUS_EIC_PINMUX PINMUX_PA05A_EIC_EXTINT5
#define USB_ID_PIN PIN_PA04
#define USB_ID_EIC_LINE 4
#define USB_ID_EIC_MUX MUX_PA04A_EIC_EXTINT4
#define USB_ID_EIC_PINMUX PINMUX_PA04A_EIC_EXTINT4
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PB22
#define EDBG_GPIO1_PIN PIN_PB23
#define EDBG_GPIO2_PIN PIN_PA22
#define EDBG_GPIO3_PIN PIN_PA24
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM0
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08C_SERCOM0_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09C_SERCOM0_PAD1
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM1
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED /* PA_06 */
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM4
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
/** @} */
/** @} */
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI EXT1_SPI_MODULE
#define AT86RFX_RST_PIN EXT1_PIN_7
#define AT86RFX_MISC_PIN EXT1_PIN_12
#define AT86RFX_IRQ_PIN EXT1_PIN_9
#define AT86RFX_SLP_PIN EXT1_PIN_10
#define AT86RFX_SPI_CS EXT1_PIN_15
#define AT86RFX_SPI_MOSI EXT1_PIN_16
#define AT86RFX_SPI_MISO EXT1_PIN_17
#define AT86RFX_SPI_SCK EXT1_PIN_18
#define AT86RFX_CSD EXT1_PIN_5
#define AT86RFX_CPS EXT1_PIN_8
#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ()
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ()
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ()
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION()
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION()
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
#ifdef __cplusplus
}
#endif
#endif /* SAMW25_XPLAINED_PRO_H_INCLUDED */

115
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/analogout_api.c
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@ -1,115 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "dac.h"
struct dac_module dac_instance;
extern uint8_t g_sys_init;
#define MAX_VAL_10BIT 0x03FF
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t pos_input;
pos_input = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(pos_input != NC);
obj->dac = DAC_0;
dac_get_config_defaults(&config_dac);
dac_init(&dac_instance, (Dac *)DAC_0, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan);
dac_chan_enable(&dac_instance, DAC_CHANNEL_0);
dac_enable(&dac_instance);
}
void analogout_free(dac_t *obj)
{
MBED_ASSERT(obj);
struct system_pinmux_config pin_conf;
dac_disable(&dac_instance);
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
pin_conf.powersave = false;
pin_conf.mux_position = SYSTEM_PINMUX_GPIO;
system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/
}
void analogout_write(dac_t *obj, float value)
{
MBED_ASSERT(obj);
uint16_t count_val = 0;
if (value < 0.0f) {
count_val = 0;
} else if (value > 1.0f) {
count_val = MAX_VAL_10BIT;
} else {
count_val = (uint16_t)(value * (float)MAX_VAL_10BIT);
}
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
MBED_ASSERT(obj);
uint16_t count_val;
count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
static uint32_t data_reg_read(dac_t *obj)
{
Dac *const dac_module = (Dac *)obj->dac;
return (uint32_t)dac_module->DATA.reg;
}
float analogout_read(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return data_val/(float)MAX_VAL_10BIT;
}
uint16_t analogout_read_u16(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/SAMD21G18A.sct
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@ -1,50 +0,0 @@
#! armcc -E
;SAMD21G18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMD21G18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
#define VECTOR_SIZE 0xB8
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/SAMD21G18A.sct
View File

@ -1,27 +0,0 @@
#! armcc -E
;SAMD21G18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAMD21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S
View File

@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/samd21g18a.ld
View File

@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(ram) + LENGTH(ram);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

158
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c
View File

@ -1,158 +0,0 @@
#include "samd21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */ // expected to be done by MBED OS
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

173
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_IAR/startup_samd21.c
View File

@ -1,173 +0,0 @@
#include "samd21.h"
void __iar_program_start(void);
int __low_level_init(void);
void Dummy_Handler(void);
void Reset_Handler(void);
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}
/* Cortex-M0+ core handlers */
void NMI_Handler ( void );
void HardFault_Handler ( void );
void SVC_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void PM_Handler ( void );
void SYSCTRL_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void USB_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void TC5_Handler ( void );
void TC6_Handler ( void );
void TC7_Handler ( void );
void ADC_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void PTC_Handler ( void );
void I2S_Handler ( void );
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak PM_Handler = Dummy_Handler
#pragma weak SYSCTRL_Handler = Dummy_Handler
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#pragma weak USB_Handler = Dummy_Handler
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#pragma weak SERCOM4_Handler = Dummy_Handler
#pragma weak SERCOM5_Handler = Dummy_Handler
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC3_Handler = Dummy_Handler
#pragma weak TC4_Handler = Dummy_Handler
#pragma weak TC5_Handler = Dummy_Handler
#pragma weak TC6_Handler = Dummy_Handler
#pragma weak TC7_Handler = Dummy_Handler
#pragma weak ADC_Handler = Dummy_Handler
#pragma weak AC_Handler = Dummy_Handler
#pragma weak DAC_Handler = Dummy_Handler
#pragma weak PTC_Handler = Dummy_Handler
#pragma weak I2S_Handler = Dummy_Handler
/* Exception Table */
#pragma language=extended
#pragma segment="CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
//! [startup_vector_table]
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
//! [startup_vector_table]
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__iar_program_start();
}

158
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
typedef enum {
ADC_0 = 0x0ul,
ADC_1 = 0x1ul,
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_8 = 0x8ul,
ADC_9 = 0x8ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_12 = 0xCul,
ADC_13 = 0xDul,
ADC_14 = 0xEul,
ADC_15 = 0xFul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum {
DAC_0 = 0x42004800UL
} DACName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_3
// Default peripherals
#define MBED_SPI0 PA18, PA16, PA19, PA17
#define MBED_UART0 PA04, PA05
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA08, PA09
#define MBED_ANALOGOUT0 PA02
#define MBED_ANALOGIN0 PA03
#define MBED_ANALOGIN1 PA08
#define MBED_ANALOGIN2 PB09
#define MBED_ANALOGIN3 PA04
#define MBED_ANALOGIN4 PA05
#define MBED_ANALOGIN5 PA06
#define MBED_ANALOGIN7 PA07
#define MBED_ANALOGIN8 PB00
#define MBED_ANALOGIN9 PB01
#define MBED_PWMOUT0 PA18
#define MBED_PWMOUT1 PA19
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PA02, ADC_0, 1},
{PA03, ADC_1, 1},
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB00, ADC_8, 1},
{PB01, ADC_9, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PB04, ADC_12, 1},
{PB05, ADC_13, 1},
{PB06, ADC_14, 1},
{PB07, ADC_15, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PA02, DAC_0, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA00, SERCOM1_PAD0, 3},
{PA01, SERCOM1_PAD1, 3},
{PA04, SERCOM0_PAD0, 3},
{PA05, SERCOM0_PAD1, 3},
{PA06, SERCOM0_PAD2, 3},
{PA07, SERCOM0_PAD3, 3},
{PA08, SERCOM0_PAD0, 2},
{PA09, SERCOM0_PAD1, 2},
{PA10, SERCOM0_PAD2, 2},
{PA11, SERCOM0_PAD3, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA17, SERCOM1_PAD1, 2},
{PA18, SERCOM1_PAD2, 2},
{PA19, SERCOM1_PAD3, 2},
{PA20, SERCOM3_PAD2, 3},
{PA21, SERCOM3_PAD3, 3},
{PA22, SERCOM3_PAD0, 2},
{PA23, SERCOM3_PAD1, 2},
{PA24, SERCOM3_PAD2, 2},
{PA25, SERCOM3_PAD3, 2},
{PA30, SERCOM1_PAD2, 3},
{PA31, SERCOM1_PAD3, 3},
{PB00, SERCOM5_PAD2, 3},
{PB01, SERCOM5_PAD3, 3},
{PB02, SERCOM5_PAD0, 3},
{PB03, SERCOM5_PAD1, 3},
{PB08, SERCOM4_PAD0, 3},
{PB09, SERCOM4_PAD1, 3},
{PB10, SERCOM4_PAD2, 3},
{PB11, SERCOM4_PAD3, 3},
{PB12, SERCOM4_PAD0, 2},
{PB13, SERCOM4_PAD1, 2},
{PB14, SERCOM4_PAD2, 2},
{PB15, SERCOM4_PAD3, 2},
{PB16, SERCOM5_PAD0, 2},
{PB17, SERCOM5_PAD1, 2},
{PB22, SERCOM5_PAD2, 3},
{PB23, SERCOM5_PAD3, 3},
{PB30, SERCOM5_PAD0, 3},
{PB31, SERCOM5_PAD1, 3},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA10, SERCOM2_PAD2, 3},
{PA11, SERCOM2_PAD3, 3},
{PA12, SERCOM4_PAD0, 3},
{PA13, SERCOM4_PAD1, 3},
{PA14, SERCOM4_PAD2, 3},
{PA15, SERCOM4_PAD3, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA20, SERCOM5_PAD2, 2},
{PA21, SERCOM5_PAD3, 2},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA24, SERCOM5_PAD2, 3},
{PA25, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA00, PWM_2, 4},
{PA01, PWM_2, 4},
{PA04, PWM_0, 4},
{PA05, PWM_0, 4},
{PA06, PWM_1, 4},
{PA07, PWM_1, 4},
{PA08, PWM_1, 5},
{PA09, PWM_1, 5},
{PA10, PWM_1, 4},
{PA11, PWM_1, 4},
{PA12, PWM_2, 4},
{PA13, PWM_2, 4},
{PA14, PWM_0, 5},
{PA15, PWM_0, 5},
{PA16, PWM_2, 4},
{PA17, PWM_2, 4},
{PA18, PWM_0, 5},
{PA19, PWM_0, 5},
{PA20, PWM_0, 5},
{PA21, PWM_0, 5},
{PA22, PWM_0, 5},
{PA23, PWM_0, 5},
{PA24, PWM_1, 5},
{PA25, PWM_1, 5},
{PA30, PWM_1, 4},
{PA31, PWM_1, 4},
{PB10, PWM_0, 5},
{PB11, PWM_0, 5},
{PB12, PWM_0, 5},
{PB13, PWM_0, 5},
{PB16, PWM_0, 5},
{PB17, PWM_0, 5},
{PB30, PWM_1, 5},
{PB31, PWM_1, 5},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PB00, EXTINT_0, 0},
{PB16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PB01, EXTINT_1, 0},
{PB17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA18, EXTINT_2, 0},
{PA02, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA03, EXTINT_3, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PB04, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA21, EXTINT_5, 0},
{PB05, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB06, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB07, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PA28, EXTINT_8, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA10, EXTINT_10, 0},
{PA30, EXTINT_10, 0},
{PB10, EXTINT_10, 0},
{PA11, EXTINT_11, 0},
{PA31, EXTINT_11, 0},
{PB11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PB12, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PB13, EXTINT_13, 0},
{PB14, EXTINT_14, 0},
{PB30, EXTINT_14, 0},
{PA14, EXTINT_14, 0},
{PA15, EXTINT_15, 0},
{PA27, EXTINT_15, 0},
{PB15, EXTINT_15, 0},
{PB31, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA00, PWM_2, 0},
{PA01, PWM_2, 1},
{PA04, PWM_0, 0},
{PA05, PWM_0, 1},
{PA06, PWM_1, 0},
{PA07, PWM_1, 1},
{PA08, PWM_1, 2},
{PA09, PWM_1, 3},
{PA10, PWM_1, 0},
{PA11, PWM_1, 1},
{PA12, PWM_2, 0},
{PA13, PWM_2, 1},
{PA14, PWM_0, 4},
{PA15, PWM_0, 5},
{PA16, PWM_2, 0},
{PA17, PWM_2, 1},
{PA18, PWM_0, 2},
{PA19, PWM_0, 3},
{PA20, PWM_0, 6},
{PA21, PWM_0, 7},
{PA22, PWM_0, 4},
{PA23, PWM_0, 5},
{PA24, PWM_1, 2},
{PA25, PWM_1, 3},
{PA30, PWM_1, 0},
{PA31, PWM_1, 1},
{PB10, PWM_0, 4},
{PB11, PWM_0, 5},
{PB12, PWM_0, 6},
{PB13, PWM_0, 7},
{PB16, PWM_0, 4},
{PB17, PWM_0, 5},
{PB30, PWM_1, 2},
{PB31, PWM_1, 3},
/* Not connected */
{NC , NC , NC}
};

40
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PeripheralPins.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA02 = 2,
PA03 = 3,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA28 = 28,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB01 = 33,
PB02 = 34,
PB03 = 35,
PB04 = 36,
PB05 = 37,
PB06 = 38,
PB07 = 39,
PB08 = 40,
PB09 = 41,
PB10 = 42,
PB11 = 43,
PB12 = 44,
PB13 = 45,
PB14 = 46,
PB15 = 47,
PB16 = 48,
PB17 = 49,
PB22 = 54,
PB23 = 55,
PB30 = 62,
PB31 = 63,
USBTX = PA22,
USBRX = PA23,
LED1 = PB30,
LED2 = PB30,
LED3 = PB30,
LED4 = PB30,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

32
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/mbed_overrides.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

662
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/SAMD21_XPLAINED_PRO/samd21_xplained_pro.h
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#ifndef SAMD21_XPLAINED_PRO_H_INCLUDED
#define SAMD21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samd21_xplained_pro_group SAM D21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samd21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMD21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PB30
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA15
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA15A_EIC_EXTINT15
#define SW0_EIC_MUX MUX_PA15A_EIC_EXTINT15
#define SW0_EIC_PINMUX PINMUX_PA15A_EIC_EXTINT15
#define SW0_EIC_LINE 15
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 0
#define LED_0_PWM4CTRL_OUTPUT 0
#define LED_0_PWM4CTRL_PIN PIN_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_MUX MUX_PB30E_TCC0_WO0
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB30E_TCC0_WO0
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Serialflash definitions
*
* On board Serialflash definitions.
*
* @{ */
#define SERIALFLASH_SPI_MODULE SERCOM5
#define SERIALFLASH_SPI_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define SERIALFLASH_SPI_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define SERIALFLASH_SPI_PINMUX_PAD1 PINMUX_UNUSED
#define SERIALFLASH_SPI_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define SERIALFLASH_SPI_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define SERIALFLASH_SPI_CS PIN_PA13
/** @} */
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PB00
#define EXT1_PIN_4 PIN_PB01
#define EXT1_PIN_5 PIN_PB06
#define EXT1_PIN_6 PIN_PB07
#define EXT1_PIN_7 PIN_PB02
#define EXT1_PIN_8 PIN_PB03
#define EXT1_PIN_9 PIN_PB04
#define EXT1_PIN_10 PIN_PB05
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB09
#define EXT1_PIN_14 PIN_PB08
#define EXT1_PIN_15 PIN_PA05
#define EXT1_PIN_16 PIN_PA06
#define EXT1_PIN_17 PIN_PA04
#define EXT1_PIN_18 PIN_PA07
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 8
#define EXT1_ADC_0_PIN PIN_PB00B_ADC_AIN8
#define EXT1_ADC_0_MUX MUX_PB00B_ADC_AIN8
#define EXT1_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
#define EXT1_ADC_1_CHANNEL 9
#define EXT1_ADC_1_PIN PIN_PB01B_ADC_AIN9
#define EXT1_ADC_1_MUX MUX_PB01B_ADC_AIN9
#define EXT1_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC6
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PB02E_TC6_WO0
#define EXT1_PWM_0_MUX MUX_PB02E_TC6_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC6_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PB03E_TC6_WO1
#define EXT1_PWM_1_MUX MUX_PB03E_TC6_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC6_WO1
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM2
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM0
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #2 pin definitions
* @{
*/
#define EXT2_PIN_3 PIN_PA10
#define EXT2_PIN_4 PIN_PA11
#define EXT2_PIN_5 PIN_PA20
#define EXT2_PIN_6 PIN_PA21
#define EXT2_PIN_7 PIN_PB12
#define EXT2_PIN_8 PIN_PB13
#define EXT2_PIN_9 PIN_PB14
#define EXT2_PIN_10 PIN_PB15
#define EXT2_PIN_11 PIN_PA08
#define EXT2_PIN_12 PIN_PA09
#define EXT2_PIN_13 PIN_PB11
#define EXT2_PIN_14 PIN_PB10
#define EXT2_PIN_15 PIN_PA17
#define EXT2_PIN_16 PIN_PA18
#define EXT2_PIN_17 PIN_PA16
#define EXT2_PIN_18 PIN_PA19
/** @} */
/** \name Extension header #2 pin definitions by function
* @{
*/
#define EXT2_PIN_ADC_0 EXT2_PIN_3
#define EXT2_PIN_ADC_1 EXT2_PIN_4
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
#define EXT2_PIN_PWM_0 EXT2_PIN_7
#define EXT2_PIN_PWM_1 EXT2_PIN_8
#define EXT2_PIN_IRQ EXT2_PIN_9
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
#define EXT2_PIN_UART_RX EXT2_PIN_13
#define EXT2_PIN_UART_TX EXT2_PIN_14
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
/** @} */
/** \name Extension header #2 ADC definitions
* @{
*/
#define EXT2_ADC_MODULE ADC
#define EXT2_ADC_0_CHANNEL 18
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
#define EXT2_ADC_1_CHANNEL 19
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
/** @} */
/** \name Extension header #2 PWM definitions
* @{
*/
#define EXT2_PWM_MODULE TC4
#define EXT2_PWM_0_CHANNEL 0
#define EXT2_PWM_0_PIN PIN_PB12E_TC4_WO0
#define EXT2_PWM_0_MUX MUX_PB12E_TC4_WO0
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC4_WO0
#define EXT2_PWM_1_CHANNEL 1
#define EXT2_PWM_1_PIN PIN_PB13E_TC4_WO1
#define EXT2_PWM_1_MUX MUX_PB13E_TC4_WO1
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC4_WO1
/** @} */
/** \name Extension header #2 PWM for Control definitions
* @{
*/
#define EXT2_PWM4CTRL_MODULE TCC0
#define EXT2_PWM4CTRL_0_CHANNEL 2
#define EXT2_PWM4CTRL_0_OUTPUT 6
#define EXT2_PWM4CTRL_0_PIN PIN_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_MUX MUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_0_PINMUX PINMUX_PB12F_TCC0_WO6
#define EXT2_PWM4CTRL_1_CHANNEL 3
#define EXT2_PWM4CTRL_1_OUTPUT 7
#define EXT2_PWM4CTRL_1_PIN PIN_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_MUX MUX_PB13F_TCC0_WO7
#define EXT2_PWM4CTRL_1_PINMUX PINMUX_PB13F_TCC0_WO7
/** @} */
/** \name Extension header #2 IRQ/External interrupt definitions
* @{
*/
#define EXT2_IRQ_MODULE EIC
#define EXT2_IRQ_INPUT 14
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #2 UART definitions
* @{
*/
#define EXT2_UART_MODULE SERCOM4
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_PB12C_SERCOM4_PAD0
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_PB13C_SERCOM4_PAD1
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #2 SPI definitions
* @{
*/
#define EXT2_SPI_MODULE SERCOM1
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PA02
#define EXT3_PIN_4 PIN_PA03
#define EXT3_PIN_5 PIN_PB30
#define EXT3_PIN_6 PIN_PA15
#define EXT3_PIN_7 PIN_PA12
#define EXT3_PIN_8 PIN_PA13
#define EXT3_PIN_9 PIN_PA28
#define EXT3_PIN_10 PIN_PA27
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PB11
#define EXT3_PIN_14 PIN_PB10
#define EXT3_PIN_15 PIN_PB17
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB16
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 0
#define EXT3_ADC_0_PIN PIN_PA02B_ADC_AIN0
#define EXT3_ADC_0_MUX MUX_PA02B_ADC_AIN0
#define EXT3_ADC_0_PINMUX PINMUX_PA02B_ADC_AIN0
#define EXT3_ADC_1_CHANNEL 1
#define EXT3_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT3_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT3_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #3 PWM for Control definitions
* @{
*/
#define EXT3_PWM4CTRL_MODULE TCC2
#define EXT3_PWM4CTRL_0_CHANNEL 0
#define EXT3_PWM4CTRL_0_OUTPUT 0
#define EXT3_PWM4CTRL_0_PIN PIN_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_MUX MUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_0_PINMUX PINMUX_PA12E_TCC2_WO0
#define EXT3_PWM4CTRL_1_CHANNEL 1
#define EXT3_PWM4CTRL_1_OUTPUT 1
#define EXT3_PWM4CTRL_1_PIN PIN_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_MUX MUX_PA13E_TCC2_WO1
#define EXT3_PWM4CTRL_1_PINMUX PINMUX_PA13E_TCC2_WO1
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 8
#define EXT3_IRQ_PIN PIN_PA28A_EIC_EXTINT8
#define EXT3_IRQ_MUX MUX_PA28A_EIC_EXTINT8
#define EXT3_IRQ_PINMUX PINMUX_PA28A_EIC_EXTINT8
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM2
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM4
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PB10D_SERCOM4_PAD2
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PB11D_SERCOM4_PAD3
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA14
#define USB_VBUS_EIC_LINE 14
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
#define USB_ID_PIN PIN_PA03
#define USB_ID_EIC_LINE 3
#define USB_ID_EIC_MUX MUX_PA03A_EIC_EXTINT3
#define USB_ID_EIC_PINMUX PINMUX_PA03A_EIC_EXTINT3
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PA27
#define EDBG_GPIO1_PIN PIN_PA28
#define EDBG_GPIO2_PIN PIN_PA20
#define EDBG_GPIO3_PIN PIN_PA21
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM2
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM3
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
/** @} */
/** @} */
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI EXT1_SPI_MODULE
#define AT86RFX_RST_PIN EXT1_PIN_7
#define AT86RFX_MISC_PIN EXT1_PIN_12
#define AT86RFX_IRQ_PIN EXT1_PIN_9
#define AT86RFX_SLP_PIN EXT1_PIN_10
#define AT86RFX_SPI_CS EXT1_PIN_15
#define AT86RFX_SPI_MOSI EXT1_PIN_16
#define AT86RFX_SPI_MISO EXT1_PIN_17
#define AT86RFX_SPI_SCK EXT1_PIN_18
#define AT86RFX_CSD EXT1_PIN_5
#define AT86RFX_CPS EXT1_PIN_8
#define AT86RFX_SPI_SERCOM_MUX_SETTING EXT1_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 EXT1_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 EXT1_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 EXT1_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN EXT1_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX EXT1_IRQ_PINMUX
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ() \
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ() \
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION() \
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAMD21_XPLAINED_PRO_H_INCLUDED */

115
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/analogout_api.c
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@ -1,115 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "dac.h"
struct dac_module dac_instance;
extern uint8_t g_sys_init;
#define MAX_VAL_10BIT 0x03FF
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t pos_input;
pos_input = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(pos_input != NC);
obj->dac = DAC_0;
dac_get_config_defaults(&config_dac);
dac_init(&dac_instance, (Dac *)DAC_0, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&dac_instance, DAC_CHANNEL_0, &config_dac_chan);
dac_chan_enable(&dac_instance, DAC_CHANNEL_0);
dac_enable(&dac_instance);
}
void analogout_free(dac_t *obj)
{
MBED_ASSERT(obj);
struct system_pinmux_config pin_conf;
dac_disable(&dac_instance);
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
pin_conf.powersave = false;
pin_conf.mux_position = SYSTEM_PINMUX_GPIO;
system_pinmux_pin_set_config(PA02, &pin_conf); /*PA02 is the only DAC pin available*/
}
void analogout_write(dac_t *obj, float value)
{
MBED_ASSERT(obj);
uint16_t count_val = 0;
if (value < 0.0f) {
count_val = 0;
} else if (value > 1.0f) {
count_val = MAX_VAL_10BIT;
} else {
count_val = (uint16_t)(value * (float)MAX_VAL_10BIT);
}
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
MBED_ASSERT(obj);
uint16_t count_val;
count_val = (uint16_t)((value * (float)MAX_VAL_10BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/
dac_chan_write(&dac_instance, DAC_CHANNEL_0, count_val);
}
static uint32_t data_reg_read(dac_t *obj)
{
Dac *const dac_module = (Dac *)obj->dac;
return (uint32_t)dac_module->DATA.reg;
}
float analogout_read(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return data_val/(float)MAX_VAL_10BIT;
}
uint16_t analogout_read_u16(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return (uint16_t)((data_val / (float)MAX_VAL_10BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/SAMD21J18A.sct
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@ -1,50 +0,0 @@
#! armcc -E
;SAMD21J18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMD21J18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
#define VECTOR_SIZE 0xB8
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/SAMD21J18A.sct
View File

@ -1,27 +0,0 @@
#! armcc -E
;SAMD21J18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAMD21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

190
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S
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@ -1,190 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMD21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMD21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/samd21j18a.ld
View File

@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

158
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_GCC_ARM/startup_samd21.c
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#include "samd21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */ // expected to be done by MBED OS
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

173
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_IAR/startup_samd21.c
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#include "samd21.h"
void __iar_program_start(void);
int __low_level_init(void);
void Dummy_Handler(void);
void Reset_Handler(void);
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}
/* Cortex-M0+ core handlers */
void NMI_Handler ( void );
void HardFault_Handler ( void );
void SVC_Handler ( void );
void PendSV_Handler ( void );
void SysTick_Handler ( void );
/* Peripherals handlers */
void PM_Handler ( void );
void SYSCTRL_Handler ( void );
void WDT_Handler ( void );
void RTC_Handler ( void );
void EIC_Handler ( void );
void NVMCTRL_Handler ( void );
void DMAC_Handler ( void );
void USB_Handler ( void );
void EVSYS_Handler ( void );
void SERCOM0_Handler ( void );
void SERCOM1_Handler ( void );
void SERCOM2_Handler ( void );
void SERCOM3_Handler ( void );
void SERCOM4_Handler ( void );
void SERCOM5_Handler ( void );
void TCC0_Handler ( void );
void TCC1_Handler ( void );
void TCC2_Handler ( void );
void TC3_Handler ( void );
void TC4_Handler ( void );
void TC5_Handler ( void );
void TC6_Handler ( void );
void TC7_Handler ( void );
void ADC_Handler ( void );
void AC_Handler ( void );
void DAC_Handler ( void );
void PTC_Handler ( void );
void I2S_Handler ( void );
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak PM_Handler = Dummy_Handler
#pragma weak SYSCTRL_Handler = Dummy_Handler
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#pragma weak USB_Handler = Dummy_Handler
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#pragma weak SERCOM4_Handler = Dummy_Handler
#pragma weak SERCOM5_Handler = Dummy_Handler
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC3_Handler = Dummy_Handler
#pragma weak TC4_Handler = Dummy_Handler
#pragma weak TC5_Handler = Dummy_Handler
#pragma weak TC6_Handler = Dummy_Handler
#pragma weak TC7_Handler = Dummy_Handler
#pragma weak ADC_Handler = Dummy_Handler
#pragma weak AC_Handler = Dummy_Handler
#pragma weak DAC_Handler = Dummy_Handler
#pragma weak PTC_Handler = Dummy_Handler
#pragma weak I2S_Handler = Dummy_Handler
/* Exception Table */
#pragma language=extended
#pragma segment="CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
//! [startup_vector_table]
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
(void*) USB_Handler, /* 7 Universal Serial Bus */
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
(void*) ADC_Handler, /* 23 Analog Digital Converter */
(void*) AC_Handler, /* 24 Analog Comparators */
(void*) DAC_Handler, /* 25 Digital Analog Converter */
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
//! [startup_vector_table]
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
__iar_program_start();
}

13
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis.h
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in samr21j18a specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "saml21.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21/device/cmsis_nvic.h
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 29) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
#endif

161
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000000UL, // Base address of SERCOM0
UART_1 = (int)0x42000400UL, // Base address of SERCOM1
UART_2 = (int)0x42000800UL, // Base address of SERCOM2
UART_3 = (int)0x42000C00UL, // Base address of SERCOM3
UART_4 = (int)0x42001000UL, // Base address of SERCOM4
UART_5 = (int)0x43000400UL // Base address of SERCOM5
} UARTName;
typedef enum {
ADC_0 = 0x0ul,
ADC_1 = 0x1ul,
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_8 = 0x8ul,
ADC_9 = 0x9ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_12 = 0xCul,
ADC_13 = 0xDul,
ADC_14 = 0xEul,
ADC_15 = 0xFul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum {
DAC_0 = 0x42003000UL
} DACName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42001400UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42001800UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42001C00UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
struct dac_pin_channel {
PinName pin;
DACName dac;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_3
// Default peripherals
#define MBED_SPI0 PA06, PA04, PA07, PA05
#define MBED_UART0 PB08, PB09
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA08, PA09
#define MBED_ANALOGIN0 PB05
#define MBED_ANALOGIN1 PA03
#define MBED_ANALOGIN2 PA06
#define MBED_ANALOGIN3 PA07
#define MBED_ANALOGIN4 PB02
#define MBED_ANALOGIN5 PB03
#define MBED_ANALOGIN7 PA08
#define MBED_ANALOGIN8 PA09
#define MBED_PWMOUT0 PB12
#define MBED_PWMOUT1 PB13
#ifdef __cplusplus
}
#endif
#endif

313
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PA02, ADC_0, 1},
{PA03, ADC_1, 1},
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB00, ADC_8, 1},
{PB01, ADC_9, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PB04, ADC_12, 1},
{PB05, ADC_13, 1},
{PB06, ADC_14, 1},
{PB07, ADC_15, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************DAC***************/
const PinMap PinMap_DAC[] = {
{PA02, DAC_0, 1},
{PA05, DAC_0, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA04, SERCOM0_PAD0, 3},
{PA08, SERCOM0_PAD0, 2},
{PA05, SERCOM0_PAD1, 3},
{PA09, SERCOM0_PAD1, 2},
{PA06, SERCOM0_PAD2, 3},
{PA10, SERCOM0_PAD2, 2},
{PA07, SERCOM0_PAD3, 3},
{PA11, SERCOM0_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA00, SERCOM1_PAD0, 3},
{PA17, SERCOM1_PAD1, 2},
{PA01, SERCOM1_PAD1, 3},
{PA30, SERCOM1_PAD2, 3},
{PA18, SERCOM1_PAD2, 2},
{PA31, SERCOM1_PAD3, 3},
{PA19, SERCOM1_PAD3, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA22, SERCOM3_PAD0, 2},
{PA27, SERCOM3_PAD0, 5},
{PA23, SERCOM3_PAD1, 2},
{PA20, SERCOM3_PAD2, 3},
{PA24, SERCOM3_PAD2, 2},
{PA21, SERCOM3_PAD3, 3},
{PA25, SERCOM3_PAD3, 2},
{PB08, SERCOM4_PAD0, 3},
{PB12, SERCOM4_PAD0, 2},
{PB09, SERCOM4_PAD1, 3},
{PB13, SERCOM4_PAD1, 2},
{PB31, SERCOM4_PAD1, 5},
{PB10, SERCOM4_PAD2, 3},
{PB14, SERCOM4_PAD2, 2},
{PB30, SERCOM4_PAD2, 5},
{PB11, SERCOM4_PAD3, 3},
{PB15, SERCOM4_PAD3, 2},
{PB02, SERCOM5_PAD0, 3},
{PB16, SERCOM5_PAD0, 2},
{PB03, SERCOM5_PAD1, 3},
{PB17, SERCOM5_PAD1, 2},
{PB00, SERCOM5_PAD2, 3},
{PB22, SERCOM5_PAD2, 3},
{PB01, SERCOM5_PAD3, 3},
{PB23, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA10, SERCOM2_PAD2, 3},
{PA11, SERCOM2_PAD3, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA12, SERCOM4_PAD0, 3},
{PA13, SERCOM4_PAD1, 3},
{PA14, SERCOM4_PAD2, 3},
{PA15, SERCOM4_PAD3, 3},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA20, SERCOM5_PAD2, 2},
{PA24, SERCOM5_PAD2, 3},
{PA21, SERCOM5_PAD3, 2},
{PA25, SERCOM5_PAD3, 3},
{PB31, SERCOM5_PAD1, 3},
{PB30, SERCOM5_PAD0, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA04, PWM_0, 4},
{PA08, PWM_0, 4},
{PB30, PWM_0, 4},
{PA16, PWM_0, 5},
{PA05, PWM_0, 4},
{PA09, PWM_0, 4},
{PB31, PWM_0, 4},
{PA17, PWM_2, 4},
{PA10, PWM_0, 5},
{PA18, PWM_0, 5},
{PA11, PWM_0, 5},
{PA19, PWM_0, 5},
{PA22, PWM_0, 5},
{PB10, PWM_0, 5},
{PB16, PWM_0, 5},
{PA14, PWM_0, 5},
{PA15, PWM_0, 5},
{PA23, PWM_0, 5},
{PB11, PWM_0, 5},
{PB17, PWM_0, 5},
{PA12, PWM_0, 5},
{PA16, PWM_0, 5},
{PA20, PWM_0, 5},
{PB12, PWM_0, 5},
{PA13, PWM_0, 5},
{PA17, PWM_0, 5},
{PA21, PWM_0, 5},
{PB13, PWM_0, 5},
{PA06, PWM_1, 4},
{PA10, PWM_1, 4},
{PA30, PWM_1, 4},
{PA07, PWM_1, 4},
{PA11, PWM_1, 4},
{PA31, PWM_1, 4},
{PA08, PWM_1, 5},
{PA24, PWM_1, 5},
{PB30, PWM_1, 5},
{PA09, PWM_1, 5},
{PA25, PWM_1, 5},
{PB31, PWM_1, 5},
{PA12, PWM_2, 4},
{PA16, PWM_2, 4},
{PA00, PWM_2, 4},
{PA13, PWM_2, 4},
{PA17, PWM_2, 4},
{PA01, PWM_2, 4},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PB00, EXTINT_0, 0},
{PB16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PB01, EXTINT_1, 0},
{PB17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA02, EXTINT_2, 0},
{PA18, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA03, EXTINT_3, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PB04, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA21, EXTINT_5, 0},
{PB05, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB06, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB07, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA10, EXTINT_10, 0},
{PA30, EXTINT_10, 0},
{PB10, EXTINT_10, 0},
{PA11, EXTINT_11, 0},
{PA31, EXTINT_11, 0},
{PB11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PB12, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PB13, EXTINT_13, 0},
{PB14, EXTINT_14, 0},
{PB30, EXTINT_14, 0},
{PA14, EXTINT_14, 0},
{PA27, EXTINT_15, 0},
{PB15, EXTINT_15, 0},
{PB31, EXTINT_15, 0},
{PA15, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA04, PWM_0, 0},
{PA08, PWM_0, 0},
{PB30, PWM_0, 0},
{PA16, PWM_0, 6},
{PA05, PWM_0, 1},
{PA09, PWM_0, 1},
{PB31, PWM_0, 1},
{PA17, PWM_0, 1},
{PA10, PWM_0, 2},
{PA18, PWM_0, 2},
{PA11, PWM_0, 3},
{PA19, PWM_0, 3},
{PA22, PWM_0, 4},
{PB10, PWM_0, 4},
{PB16, PWM_0, 4},
{PA14, PWM_0, 4},
{PA15, PWM_0, 5},
{PA23, PWM_0, 5},
{PB11, PWM_0, 5},
{PB17, PWM_0, 5},
{PA12, PWM_0, 6},
{PA16, PWM_0, 6},
{PA20, PWM_0, 6},
{PB12, PWM_0, 6},
{PA13, PWM_0, 7},
{PA17, PWM_2, 1},
{PA21, PWM_0, 7},
{PB13, PWM_0, 7},
{PA06, PWM_1, 0},
{PA10, PWM_1, 0},
{PA30, PWM_1, 0},
{PA07, PWM_1, 1},
{PA11, PWM_1, 1},
{PA31, PWM_1, 1},
{PA08, PWM_1, 2},
{PA24, PWM_1, 2},
{PB30, PWM_1, 2},
{PA09, PWM_1, 3},
{PA25, PWM_1, 3},
{PB31, PWM_1, 3},
{PA12, PWM_2, 0},
{PA16, PWM_2, 0},
{PA00, PWM_2, 0},
{PA13, PWM_2, 1},
{PA17, PWM_2, 1},
{PA01, PWM_2, 1},
/* Not connected */
{NC , NC , NC}
};

40
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PeripheralPins.h
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@ -1,40 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2013 Nordic Semiconductor
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA02 = 2,
PA03 = 3,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA21 = 21,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB01 = 33,
PB02 = 34,
PB03 = 35,
PB04 = 36,
PB05 = 37,
PB06 = 38,
PB07 = 39,
PB08 = 40,
PB09 = 41,
PB10 = 42,
PB11 = 43,
PB12 = 44,
PB13 = 45,
PB14 = 46,
PB15 = 47,
PB16 = 48,
PB17 = 49,
PB22 = 54,
PB23 = 55,
PB30 = 62,
PB31 = 63,
USBTX = PA22,
USBRX = PA23,
LED1 = PB10,
LED2 = PB10,
LED3 = PB10,
LED4 = PB10,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

32
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/mbed_overrides.c
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@ -1,32 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

599
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/SAML21_XPLAINED_PRO/saml21_xplained_pro.h
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@ -1,599 +0,0 @@
/**
* \file
*
* \brief SAM L21 Xplained Pro board definition
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef SAML21_XPLAINED_PRO_H_INCLUDED
#define SAML21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup saml21_xplained_pro_group SAM L21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup saml21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAML21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PB10
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA02
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA02A_EIC_EXTINT2
#define SW0_EIC_MUX MUX_PA02A_EIC_EXTINT2
#define SW0_EIC_PINMUX PINMUX_PA02A_EIC_EXTINT2
#define SW0_EIC_LINE 2
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED0 LED0_PIN
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 0
#define LED_0_PWM4CTRL_OUTPUT 0
#define LED_0_PWM4CTRL_PIN PIN_PB10F_TCC0_WO4
#define LED_0_PWM4CTRL_MUX MUX_PB10F_TCC0_WO4
#define LED_0_PWM4CTRL_PINMUX PINMUX_PB10F_TCC0_WO4
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PB05
#define EXT1_PIN_4 PIN_PA03
#define EXT1_PIN_5 PIN_PB06
#define EXT1_PIN_6 PIN_PB07
#define EXT1_PIN_7 PIN_PA12
#define EXT1_PIN_8 PIN_PA13
#define EXT1_PIN_9 PIN_PB04
#define EXT1_PIN_10 PIN_PA02
#define EXT1_PIN_11 PIN_PA08
#define EXT1_PIN_12 PIN_PA09
#define EXT1_PIN_13 PIN_PB09
#define EXT1_PIN_14 PIN_PB08
#define EXT1_PIN_15 PIN_PA05
#define EXT1_PIN_16 PIN_PA06
#define EXT1_PIN_17 PIN_PA04
#define EXT1_PIN_18 PIN_PA07
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_IRQ EXT1_PIN_9
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_1 EXT1_PIN_10
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_13_CHANNEL 13
#define EXT1_ADC_13_PIN PIN_PB05B_ADC_AIN13
#define EXT1_ADC_13_MUX MUX_PB05B_ADC_AIN13
#define EXT1_ADC_13_PINMUX PINMUX_PB05B_ADC_AIN13
#define EXT1_ADC_1_CHANNEL 1
#define EXT1_ADC_1_PIN PIN_PA03B_ADC_AIN1
#define EXT1_ADC_1_MUX MUX_PA03B_ADC_AIN1
#define EXT1_ADC_1_PINMUX PINMUX_PA03B_ADC_AIN1
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC2
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PB02E_TC2_WO0
#define EXT1_PWM_0_MUX MUX_PB02E_TC2_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PB02E_TC2_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PB03E_TC2_WO1
#define EXT1_PWM_1_MUX MUX_PB03E_TC2_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PB03E_TC2_WO1
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 4
#define EXT1_IRQ_PIN PIN_PB04A_EIC_EXTINT4
#define EXT1_IRQ_MUX MUX_PB04A_EIC_EXTINT4
#define EXT1_IRQ_PINMUX PINMUX_PB04A_EIC_EXTINT4
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM2
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM4
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PB08D_SERCOM4_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PB09D_SERCOM4_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM4_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM4_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM0
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PA06D_SERCOM0_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PA07D_SERCOM0_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #2 pin definitions
* @{
*/
#define EXT2_PIN_3 PIN_PA10
#define EXT2_PIN_4 PIN_PA11
#define EXT2_PIN_5 PIN_PA20
#define EXT2_PIN_6 PIN_PA21
#define EXT2_PIN_7 PIN_PB12
#define EXT2_PIN_8 PIN_PB13
#define EXT2_PIN_9 PIN_PB14
#define EXT2_PIN_10 PIN_PB15
#define EXT2_PIN_11 PIN_PA08
#define EXT2_PIN_12 PIN_PA09
#define EXT2_PIN_13 PIN_PA19
#define EXT2_PIN_14 PIN_PA18
#define EXT2_PIN_15 PIN_PA17
#define EXT2_PIN_16 PIN_PB22
#define EXT2_PIN_17 PIN_PB16
#define EXT2_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #2 pin definitions by function
* @{
*/
#define EXT2_PIN_ADC_0 EXT2_PIN_3
#define EXT2_PIN_ADC_1 EXT2_PIN_4
#define EXT2_PIN_GPIO_0 EXT2_PIN_5
#define EXT2_PIN_GPIO_1 EXT2_PIN_6
#define EXT2_PIN_PWM_0 EXT2_PIN_7
#define EXT2_PIN_PWM_1 EXT2_PIN_8
#define EXT2_PIN_IRQ EXT2_PIN_9
#define EXT2_PIN_I2C_SDA EXT2_PIN_11
#define EXT2_PIN_I2C_SCL EXT2_PIN_12
#define EXT2_PIN_UART_RX EXT2_PIN_13
#define EXT2_PIN_UART_TX EXT2_PIN_14
#define EXT2_PIN_SPI_SS_1 EXT2_PIN_10
#define EXT2_PIN_SPI_SS_0 EXT2_PIN_15
#define EXT2_PIN_SPI_MOSI EXT2_PIN_16
#define EXT2_PIN_SPI_MISO EXT2_PIN_17
#define EXT2_PIN_SPI_SCK EXT2_PIN_18
/** @} */
/** \name Extension header #2 ADC definitions
* @{
*/
#define EXT2_ADC_MODULE ADC
#define EXT2_ADC_0_CHANNEL 18
#define EXT2_ADC_0_PIN PIN_PA10B_ADC_AIN18
#define EXT2_ADC_0_MUX MUX_PA10B_ADC_AIN18
#define EXT2_ADC_0_PINMUX PINMUX_PA10B_ADC_AIN18
#define EXT2_ADC_1_CHANNEL 19
#define EXT2_ADC_1_PIN PIN_PA11B_ADC_AIN19
#define EXT2_ADC_1_MUX MUX_PA11B_ADC_AIN19
#define EXT2_ADC_1_PINMUX PINMUX_PA11B_ADC_AIN19
/** @} */
/** \name Extension header #2 PWM definitions
* @{
*/
#define EXT2_PWM_MODULE TC0
#define EXT2_PWM_0_CHANNEL 0
#define EXT2_PWM_0_PIN PIN_PB12E_TC0_WO0
#define EXT2_PWM_0_MUX MUX_PB12E_TC0_WO0
#define EXT2_PWM_0_PINMUX PINMUX_PB12E_TC0_WO0
#define EXT2_PWM_1_CHANNEL 1
#define EXT2_PWM_1_PIN PIN_PB13E_TC0_WO1
#define EXT2_PWM_1_MUX MUX_PB13E_TC0_WO1
#define EXT2_PWM_1_PINMUX PINMUX_PB13E_TC0_WO1
/** @} */
/** \name Extension header #2 IRQ/External interrupt definitions
* @{
*/
#define EXT2_IRQ_MODULE EIC
#define EXT2_IRQ_INPUT 14
#define EXT2_IRQ_PIN PIN_PB14A_EIC_EXTINT14
#define EXT2_IRQ_MUX MUX_PB14A_EIC_EXTINT14
#define EXT2_IRQ_PINMUX PINMUX_PB14A_EIC_EXTINT14
/** @} */
/** \name Extension header #2 I2C definitions
* @{
*/
#define EXT2_I2C_MODULE SERCOM2
#define EXT2_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT2_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT2_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT2_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #2 UART definitions
* @{
*/
#define EXT2_UART_MODULE SERCOM1
#define EXT2_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT2_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT2_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT2_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT2_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT2_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #2 SPI definitions
* @{
*/
#define EXT2_SPI_MODULE SERCOM5
#define EXT2_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT2_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT2_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT2_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT2_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT2_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT2_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_3 PIN_PB00
#define EXT3_PIN_4 PIN_PB01
#define EXT3_PIN_5 PIN_PB30
#define EXT3_PIN_6 PIN_PA15
#define EXT3_PIN_7 PIN_PB10
#define EXT3_PIN_8 PIN_PB11
#define EXT3_PIN_9 PIN_PA16
#define EXT3_PIN_10 PIN_PA27
#define EXT3_PIN_11 PIN_PA08
#define EXT3_PIN_12 PIN_PA09
#define EXT3_PIN_13 PIN_PA19
#define EXT3_PIN_14 PIN_PA18
#define EXT3_PIN_15 PIN_PB17
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB16
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_ADC_0 EXT3_PIN_3
#define EXT3_PIN_ADC_1 EXT3_PIN_4
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_6
#define EXT3_PIN_PWM_0 EXT3_PIN_7
#define EXT3_PIN_PWM_1 EXT3_PIN_8
#define EXT3_PIN_IRQ EXT3_PIN_9
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_UART_RX EXT3_PIN_13
#define EXT3_PIN_UART_TX EXT3_PIN_14
#define EXT3_PIN_SPI_SS_1 EXT3_PIN_10
#define EXT3_PIN_SPI_SS_0 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 ADC definitions
* @{
*/
#define EXT3_ADC_MODULE ADC
#define EXT3_ADC_0_CHANNEL 8
#define EXT3_ADC_0_PIN PIN_PB00B_ADC_AIN8
#define EXT3_ADC_0_MUX MUX_PB00B_ADC_AIN8
#define EXT3_ADC_0_PINMUX PINMUX_PB00B_ADC_AIN8
#define EXT3_ADC_1_CHANNEL 9
#define EXT3_ADC_1_PIN PIN_PB01B_ADC_AIN9
#define EXT3_ADC_1_MUX MUX_PB01B_ADC_AIN9
#define EXT3_ADC_1_PINMUX PINMUX_PB01B_ADC_AIN9
/** @} */
/** \name Extension header #3 IRQ/External interrupt definitions
* @{
*/
#define EXT3_IRQ_MODULE EIC
#define EXT3_IRQ_INPUT 0
#define EXT3_IRQ_PIN PIN_PA16A_EIC_EXTINT0
#define EXT3_IRQ_MUX MUX_PA16A_EIC_EXTINT0
#define EXT3_IRQ_PINMUX PINMUX_PA16A_EIC_EXTINT0
/** @} */
/** \name Extension header #3 I2C definitions
* @{
*/
#define EXT3_I2C_MODULE SERCOM2
#define EXT3_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EXT3_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EXT3_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EXT3_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Extension header #3 UART definitions
* @{
*/
#define EXT3_UART_MODULE SERCOM1
#define EXT3_UART_SERCOM_MUX_SETTING USART_RX_3_TX_2_XCK_3
#define EXT3_UART_SERCOM_PINMUX_PAD0 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_UART_SERCOM_PINMUX_PAD2 PINMUX_PA18C_SERCOM1_PAD2
#define EXT3_UART_SERCOM_PINMUX_PAD3 PINMUX_PA19C_SERCOM1_PAD3
#define EXT3_UART_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT3_UART_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB17C_SERCOM5_PAD1
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM2
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA08D_SERCOM2_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA09D_SERCOM2_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM2_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM2_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB16C_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM3
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA22C_SERCOM3_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA23C_SERCOM3_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM3_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM3_DMAC_ID_RX
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA14
#define USB_VBUS_EIC_LINE 14
#define USB_VBUS_EIC_MUX MUX_PA14A_EIC_EXTINT14
#define USB_VBUS_EIC_PINMUX PINMUX_PA14A_EIC_EXTINT14
#define USB_ID_PIN PIN_PB02
#define USB_ID_EIC_LINE 2
#define USB_ID_EIC_MUX MUX_PB02A_EIC_EXTINT2
#define USB_ID_EIC_PINMUX PINMUX_PB02A_EIC_EXTINT2
/** @} */
/** \name CCL interface definitions
* @{
*/
#define CCL_LUT0_IN0_MUX MUX_PA04I_CCL_IN0
#define CCL_LUT0_IN1_MUX MUX_PA05I_CCL_IN1
#define CCL_LUT0_IN2_MUX MUX_PA06I_CCL_IN2
#define CCL_LUT0_OUT_MUX MUX_PA07I_CCL_OUT0
#define CCL_LUT0_IN0_PIN PIN_PA04I_CCL_IN0
#define CCL_LUT0_IN1_PIN PIN_PA05I_CCL_IN1
#define CCL_LUT0_IN2_PIN PIN_PA06I_CCL_IN2
#define CCL_LUT0_OUT_PIN PIN_PA07I_CCL_OUT0
#define CCL_LUT1_IN0_MUX MUX_PA08I_CCL_IN3
#define CCL_LUT1_IN1_MUX MUX_PA09I_CCL_IN4
#define CCL_LUT1_IN2_MUX MUX_PA10I_CCL_IN5
#define CCL_LUT1_OUT_MUX MUX_PA11I_CCL_OUT1
#define CCL_LUT1_IN0_PIN PIN_PA08I_CCL_IN3
#define CCL_LUT1_IN1_PIN PIN_PA09I_CCL_IN4
#define CCL_LUT1_IN2_PIN PIN_PA10I_CCL_IN5
#define CCL_LUT1_OUT_PIN PIN_PA11I_CCL_OUT1
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
/** @} */
#ifdef __cplusplus
}
#endif
#endif /* SAML21_XPLAINED_PRO_H_INCLUDED */

125
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/analogout_api.c
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@ -1,125 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "dac.h"
#if DEVICE_ANALOGOUT
extern uint8_t g_sys_init;
#define MAX_VAL_12BIT 0x0FFF /*12 Bit DAC for SAML21*/
void analogout_init(dac_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
struct dac_config config_dac;
struct dac_chan_config config_dac_chan;
uint32_t dacperipheral;
uint32_t ch_index;
dacperipheral = pinmap_find_peripheral(pin, PinMap_DAC);
MBED_ASSERT(dacperipheral != NC);
obj->pin = pin;
obj->dac = dacperipheral;
if (pin == PA02) {
ch_index = 0;
} else if (pin == PA05) {
ch_index = 1;
} else { /*Only 2 pins for DAC*/
return 0;
}
obj->channel = ch_index;
dac_get_config_defaults(&config_dac);
dac_init(&(obj->dac_instance), (Dac *)dacperipheral, &config_dac);
dac_chan_get_config_defaults(&config_dac_chan);
dac_chan_set_config(&(obj->dac_instance), ch_index, &config_dac_chan);
dac_chan_enable(&(obj->dac_instance), ch_index);
dac_enable(&(obj->dac_instance));
}
void analogout_free(dac_t *obj)
{
MBED_ASSERT(obj);
struct system_pinmux_config pin_conf;
dac_disable(&(obj->dac_instance));
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_UP;
pin_conf.powersave = false;
pin_conf.mux_position = SYSTEM_PINMUX_GPIO;
system_pinmux_pin_set_config(obj->pin, &pin_conf);
}
void analogout_write(dac_t *obj, float value)
{
MBED_ASSERT(obj);
uint16_t count_val = 0;
if (value < 0.0f) {
count_val = 0;
} else if (value > 1.0f) {
count_val = MAX_VAL_12BIT;
} else {
count_val = (uint16_t)(value * (float)MAX_VAL_12BIT);
}
dac_chan_write(&(obj->dac_instance), obj->channel, count_val);
}
void analogout_write_u16(dac_t *obj, uint16_t value)
{
MBED_ASSERT(obj);
uint16_t count_val;
count_val = (uint16_t)((value * (float)MAX_VAL_12BIT) / 0xFFFF); /*Normalization to the value 0xFFFF*/
dac_chan_write(&(obj->dac_instance), obj->channel, count_val);
}
static uint32_t data_reg_read(dac_t *obj)
{
Dac *const dac_module = (Dac *)obj->dac;
return (uint32_t)dac_module->DATA[obj->channel].reg;
}
float analogout_read(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return data_val/(float)MAX_VAL_12BIT;
}
uint16_t analogout_read_u16(dac_t *obj)
{
MBED_ASSERT(obj);
uint32_t data_val = data_reg_read(obj);
return (uint16_t)((data_val / (float)MAX_VAL_12BIT) * 0xFFFF); /*Normalization to the value 0xFFFF*/
}
const PinMap *analogout_pinmap()
{
return PinMap_DAC;
}
#endif // DEVICE_ANALOGOUT

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/SAML21J18A.sct
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#! armcc -E
;SAMD21J18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMD21J18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4 +0x4) 8-byte alignment
#define VECTOR_SIZE 0xB8
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

194
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S
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@ -1,194 +0,0 @@
;/**************************************************************************//**
; * @file startup_SAML21.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAML21 Device Series
; * @version V1.00
; * @date 10. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
;Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ;Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
DCD WDT_Handler ;1 Watchdog Timer
DCD RTC_Handler ;2 Real-Time Counter
DCD EIC_Handler ;3 External Interrupt Controller
DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller
DCD DMAC_Handler ;5 Direct Memory Access Controller
DCD USB_Handler ;6 Universal Serial Bus
DCD EVSYS_Handler ;7 Event System Interface
DCD SERCOM0_Handler ;8 Serial Communication Interface 0
DCD SERCOM1_Handler ;9 Serial Communication Interface 1
DCD SERCOM2_Handler ;10 Serial Communication Interface 2
DCD SERCOM3_Handler ;11 Serial Communication Interface 3
DCD SERCOM4_Handler ;12 Serial Communication Interface 4
DCD SERCOM5_Handler ;13 Serial Communication Interface 5
DCD TCC0_Handler ;14 Timer Counter Control 0
DCD TCC1_Handler ;15 Timer Counter Control 1
DCD TCC2_Handler ;16 Timer Counter Control 2
DCD TC0_Handler ;17 Basic Timer Counter 0
DCD TC1_Handler ;18 Basic Timer Counter 1
DCD TC2_Handler ;19 Basic Timer Counter 2
DCD TC3_Handler ;20 Basic Timer Counter 3
DCD TC4_Handler ;21 Basic Timer Counter 4
DCD ADC_Handler ;22 Analog Digital Converter
DCD AC_Handler ;23 Analog Comparators
DCD DAC_Handler ;24 Digital-to-Analog Converter
DCD PTC_Handler ;25 Peripheral Touch Controller
DCD AES_Handler ;26 Advanced Encryption Standard
DCD TRNG_Handler ;27 True Random Generator
DCD PICOP_Handler ;28 PicoProcessor
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SYSTEM_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT PICOP_Handler [WEAK]
SYSTEM_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
AES_Handler
TRNG_Handler
PICOP_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/SAML21J18A.sct
View File

@ -1,27 +0,0 @@
#! armcc -E
;SAML21J18A
;256KB FLASH (0x40000) @ 0x000000000
;32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAML21J18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 45 vectors * 4 bytes = (0xB4+0x4) 8-byte alignment
RW_IRAM1 (0x20000000+0xB8) (0x8000-0xB8-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

194
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S
View File

@ -1,194 +0,0 @@
;/**************************************************************************//**
; * @file startup_SAML21.s
; * @brief CMSIS Cortex-M4 Core Device Startup File for
; * Atmel SAML21 Device Series
; * @version V1.00
; * @date 10. February 2015
; *
; * @note
; * Copyright (C) 2015 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
;Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ;Reset Handler
DCD NMI_Handler ;NMI Handler
DCD HardFault_Handler ;Hard Fault Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD SVC_Handler ;SVCall Handler
DCD 0 ;Reserved
DCD 0 ;Reserved
DCD PendSV_Handler ;PendSV Handler
DCD SysTick_Handler ;SysTick Handler
;External Interrupts
DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator
DCD WDT_Handler ;1 Watchdog Timer
DCD RTC_Handler ;2 Real-Time Counter
DCD EIC_Handler ;3 External Interrupt Controller
DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller
DCD DMAC_Handler ;5 Direct Memory Access Controller
DCD USB_Handler ;6 Universal Serial Bus
DCD EVSYS_Handler ;7 Event System Interface
DCD SERCOM0_Handler ;8 Serial Communication Interface 0
DCD SERCOM1_Handler ;9 Serial Communication Interface 1
DCD SERCOM2_Handler ;10 Serial Communication Interface 2
DCD SERCOM3_Handler ;11 Serial Communication Interface 3
DCD SERCOM4_Handler ;12 Serial Communication Interface 4
DCD SERCOM5_Handler ;13 Serial Communication Interface 5
DCD TCC0_Handler ;14 Timer Counter Control 0
DCD TCC1_Handler ;15 Timer Counter Control 1
DCD TCC2_Handler ;16 Timer Counter Control 2
DCD TC0_Handler ;17 Basic Timer Counter 0
DCD TC1_Handler ;18 Basic Timer Counter 1
DCD TC2_Handler ;19 Basic Timer Counter 2
DCD TC3_Handler ;20 Basic Timer Counter 3
DCD TC4_Handler ;21 Basic Timer Counter 4
DCD ADC_Handler ;22 Analog Digital Converter
DCD AC_Handler ;23 Analog Comparators
DCD DAC_Handler ;24 Digital-to-Analog Converter
DCD PTC_Handler ;25 Peripheral Touch Controller
DCD AES_Handler ;26 Advanced Encryption Standard
DCD TRNG_Handler ;27 True Random Generator
DCD PICOP_Handler ;28 PicoProcessor
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
;Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
;Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SYSTEM_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC0_Handler [WEAK]
EXPORT TC1_Handler [WEAK]
EXPORT TC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT AES_Handler [WEAK]
EXPORT TRNG_Handler [WEAK]
EXPORT PICOP_Handler [WEAK]
SYSTEM_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC0_Handler
TC1_Handler
TC2_Handler
TC3_Handler
TC4_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
AES_Handler
TRNG_Handler
PICOP_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/saml21j18a.ld
View File

@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB8, LENGTH = 0x00008000 - 0xB8
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

281
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_GCC_ARM/startup_saml21.c
View File

@ -1,281 +0,0 @@
/**
* \file
*
* \brief gcc starttup file for SAML21
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "saml21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void SYSTEM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler"))); /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_USB
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_SERCOM4
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_SERCOM5
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_TC2
void TC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TC3
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef ID_ADC
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_AC
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_DAC
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PTC
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_AES
void AES_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_TRNG
void TRNG_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ID_PICOP
void PICOP_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
(void*) WDT_Handler, /* 1 Watchdog Timer */
(void*) RTC_Handler, /* 2 Real-Time Counter */
(void*) EIC_Handler, /* 3 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 5 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 6 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) EVSYS_Handler, /* 7 Event System Interface */
(void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) TCC0_Handler, /* 14 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 15 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 16 Timer Counter Control 2 */
(void*) TC0_Handler, /* 17 Basic Timer Counter 0 */
(void*) TC1_Handler, /* 18 Basic Timer Counter 1 */
#ifdef ID_TC2
(void*) TC2_Handler, /* 19 Basic Timer Counter 2 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_TC3
(void*) TC3_Handler, /* 20 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) TC4_Handler, /* 21 Basic Timer Counter 4 */
#ifdef ID_ADC
(void*) ADC_Handler, /* 22 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 23 Analog Comparators */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 24 Digital-to-Analog Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 25 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_AES
(void*) AES_Handler, /* 26 Advanced Encryption Standard */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_TRNG
(void*) TRNG_Handler, /* 27 True Random Generator */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ID_PICOP
(void*) PICOP_Handler /* 28 PicoProcessor */
#else
(void*) (0UL) /* Reserved */
#endif
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

261
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_IAR/startup_saml21.c
View File

@ -1,261 +0,0 @@
/**
* \file
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "saml21.h"
typedef void (*intfunc) (void);
typedef union {
intfunc __fun;
void * __ptr;
} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak SYSTEM_Handler = Dummy_Handler /* MCLK, OSCCTRL, OSC32KCTRL, PAC, PM, SUPC, TAL */
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#ifdef ID_USB
#pragma weak USB_Handler = Dummy_Handler
#endif
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#ifdef ID_SERCOM4
#pragma weak SERCOM4_Handler = Dummy_Handler
#endif
#ifdef ID_SERCOM5
#pragma weak SERCOM5_Handler = Dummy_Handler
#endif
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC0_Handler = Dummy_Handler
#pragma weak TC1_Handler = Dummy_Handler
#ifdef ID_TC2
#pragma weak TC2_Handler = Dummy_Handler
#endif
#ifdef ID_TC3
#pragma weak TC3_Handler = Dummy_Handler
#endif
#pragma weak TC4_Handler = Dummy_Handler
#ifdef ID_ADC
#pragma weak ADC_Handler = Dummy_Handler
#endif
#ifdef ID_AC
#pragma weak AC_Handler = Dummy_Handler
#endif
#ifdef ID_DAC
#pragma weak DAC_Handler = Dummy_Handler
#endif
#ifdef ID_PTC
#pragma weak PTC_Handler = Dummy_Handler
#endif
#ifdef ID_AES
#pragma weak AES_Handler = Dummy_Handler
#endif
#ifdef ID_TRNG
#pragma weak TRNG_Handler = Dummy_Handler
#endif
#ifdef ID_PICOP
#pragma weak PICOP_Handler = Dummy_Handler
#endif
/* Exception Table */
#pragma language = extended
#pragma segment = "CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) SYSTEM_Handler, /* 0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator */
(void*) WDT_Handler, /* 1 Watchdog Timer */
(void*) RTC_Handler, /* 2 Real-Time Counter */
(void*) EIC_Handler, /* 3 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 4 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 5 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 6 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) EVSYS_Handler, /* 7 Event System Interface */
(void*) SERCOM0_Handler, /* 8 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 9 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 10 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 11 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 12 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 13 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) TCC0_Handler, /* 14 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 15 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 16 Timer Counter Control 2 */
(void*) TC0_Handler, /* 17 Basic Timer Counter 0 */
(void*) TC1_Handler, /* 18 Basic Timer Counter 1 */
#ifdef ID_TC2
(void*) TC2_Handler, /* 19 Basic Timer Counter 2 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC3
(void*) TC3_Handler, /* 20 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) TC4_Handler, /* 21 Basic Timer Counter 4 */
#ifdef ID_ADC
(void*) ADC_Handler, /* 22 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 23 Analog Comparators */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 24 Digital-to-Analog Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 25 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AES
(void*) AES_Handler, /* 26 Advanced Encryption Standard */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TRNG
(void*) TRNG_Handler, /* 27 True Random Generator */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PICOP
(void*) PICOP_Handler /* 28 PicoProcessor */
#else
(void*) (0UL) /* Reserved*/
#endif
};
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
__iar_program_start();
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

13
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis.h
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/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in samr21j18a specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "samr21.h"
#include "cmsis_nvic.h"
#endif

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21/device/cmsis_nvic.h
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2011 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS (16 + 28) // CORE + MCU Peripherals
#define NVIC_RAM_VECTOR_ADDRESS 0x20000000 // Vectors positioned at start of RAM
#endif

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include <compiler.h>
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
#define _SERCOM_SPI_NAME(n, unused) \
SPI##n,
#define _SERCOM_PAD_NAME(n, pad) \
SERCOM##n##_PAD##pad = ((n & 0xF) | ((pad & 0xF) << 4)),
#define _SERCOM_I2C_NAME(n, unused) \
I2C##n,
typedef enum {
UART_0 = (int)0x42000800UL, // Base address of SERCOM0
UART_1 = (int)0x42000C00UL, // Base address of SERCOM1
UART_2 = (int)0x42001000UL, // Base address of SERCOM2
UART_3 = (int)0x42001400UL, // Base address of SERCOM3
UART_4 = (int)0x42001800UL, // Base address of SERCOM4
UART_5 = (int)0x42001C00UL // Base address of SERCOM5
} UARTName;
typedef enum { // for each input control mux 4,5,6,7,16,17,10,11 used in R21
ADC_2 = 0x2ul,
ADC_3 = 0x3ul,
ADC_4 = 0x4ul,
ADC_5 = 0x5ul,
ADC_6 = 0x6ul,
ADC_7 = 0x7ul,
ADC_8 = 0x8ul,
ADC_10 = 0xAul,
ADC_11 = 0xBul,
ADC_16 = 0x10ul,
ADC_17 = 0x11ul,
ADC_18 = 0x12ul,
ADC_19 = 0x13ul
} ADCName;
typedef enum { // for each channel
EXTINT_0 = 0,
EXTINT_1,
EXTINT_2,
EXTINT_3,
EXTINT_4,
EXTINT_5,
EXTINT_6,
EXTINT_7,
EXTINT_8,
EXTINT_9,
EXTINT_10,
EXTINT_11,
EXTINT_12,
EXTINT_13,
EXTINT_14,
EXTINT_15
} EXTINTName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_SPI_NAME, ~)
} SPIName;
typedef enum {
MREPEAT(SERCOM_INST_NUM, _SERCOM_I2C_NAME, ~)
} I2CName;
typedef enum {
/* Pad 0 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 0)
/* Pad 1 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 1)
/* Pad 2 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 2)
/* Pad 3 definitions */
MREPEAT(SERCOM_INST_NUM, _SERCOM_PAD_NAME, 3)
} SercomPadName;
typedef enum {
PWM_0 = (0x42002000UL), /**< \brief (TCC0) APB Base Address */
PWM_1 = (0x42002400UL), /**< \brief (TCC1) APB Base Address */
PWM_2 = (0x42002800UL), /**< \brief (TCC2) APB Base Address */
} PWMName;
struct pwm_pin_channel {
PinName pin;
PWMName pwm;
uint8_t channel_index;
};
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART_0
// Default peripherals
#define MBED_SPI0 PB22, PB02, PB23, PA14
#define MBED_UART0 PA04, PA05
#define MBED_UARTUSB USBTX, USBRX
#define MBED_I2C0 PA16, PA17
#define MBED_ANALOGIN0 PA04
#define MBED_ANALOGIN1 PA05
#define MBED_ANALOGIN2 PA06
#define MBED_ANALOGIN3 PA07
#define MBED_ANALOGIN4 PB02
#define MBED_ANALOGIN5 PB03
#define MBED_ANALOGIN7 PA08
#define MBED_ANALOGIN8 PA09
#define MBED_PWMOUT0 PA18
#define MBED_PWMOUT1 PA19
#ifdef __cplusplus
}
#endif
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************ADC***************/
const PinMap PinMap_ADC[] = {
{PB08, ADC_2, 1},
{PB09, ADC_3, 1},
{PA04, ADC_4, 1},
{PA05, ADC_5, 1},
{PA06, ADC_6, 1},
{PA07, ADC_7, 1},
{PB00, ADC_8, 1},
{PB02, ADC_10, 1},
{PB03, ADC_11, 1},
{PA08, ADC_16, 1},
{PA09, ADC_17, 1},
{PA10, ADC_18, 1},
{PA11, ADC_19, 1},
/* Not connected */
{NC , NC , NC}
};
/************SERCOM Pins***********/
const PinMap PinMap_SERCOM_PAD[] = {
{PA00, SERCOM1_PAD0, 3},
{PA01, SERCOM1_PAD1, 3},
{PA04, SERCOM0_PAD0, 3},
{PA05, SERCOM0_PAD1, 3},
{PA06, SERCOM0_PAD2, 3},
{PA07, SERCOM0_PAD3, 3},
{PA08, SERCOM0_PAD0, 2},
{PA09, SERCOM0_PAD1, 2},
{PA12, SERCOM2_PAD0, 2},
{PA13, SERCOM2_PAD1, 2},
{PA14, SERCOM2_PAD2, 2},
{PA15, SERCOM2_PAD3, 2},
{PA16, SERCOM1_PAD0, 2},
{PA17, SERCOM1_PAD1, 2},
{PA18, SERCOM1_PAD2, 2},
{PA19, SERCOM1_PAD3, 2},
{PA22, SERCOM3_PAD0, 2},
{PA23, SERCOM3_PAD1, 2},
{PA24, SERCOM3_PAD2, 2},
{PA25, SERCOM3_PAD3, 2},
{PA27, SERCOM3_PAD0, 5},
{PA28, SERCOM3_PAD1, 5},
{PA30, SERCOM1_PAD2, 3},
{PA31, SERCOM1_PAD3, 3},
{PB02, SERCOM5_PAD0, 3},
{PB03, SERCOM5_PAD1, 3},
{PB22, SERCOM5_PAD2, 3},
{PB23, SERCOM5_PAD3, 3},
{PB30, SERCOM4_PAD2, 5},
{PB31, SERCOM4_PAD1, 5},
{PC18, SERCOM4_PAD3, 5},
{PC19, SERCOM4_PAD0, 5},
/* Not connected */
{NC , NC , NC}
};
/*******SERCOM Pins extended*******/
const PinMap PinMap_SERCOM_PADEx[] = {
{PA08, SERCOM2_PAD0, 3},
{PA09, SERCOM2_PAD1, 3},
{PA16, SERCOM3_PAD0, 3},
{PA17, SERCOM3_PAD1, 3},
{PA18, SERCOM3_PAD2, 3},
{PA19, SERCOM3_PAD3, 3},
{PA22, SERCOM5_PAD0, 3},
{PA23, SERCOM5_PAD1, 3},
{PA24, SERCOM5_PAD2, 3},
{PA25, SERCOM5_PAD3, 3},
/* Not connected */
{NC , NC , NC}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{PA00, PWM_2, 4},
{PA01, PWM_2, 4},
{PA04, PWM_0, 4},
{PA05, PWM_0, 4},
{PA06, PWM_1, 4},
{PA07, PWM_1, 4},
{PA08, PWM_0, 4},
{PA09, PWM_0, 4},
{PA10, PWM_1, 4},
{PA11, PWM_1, 4},
{PA12, PWM_2, 4},
{PA13, PWM_2, 4},
{PA16, PWM_2, 4},
{PA17, PWM_2, 4},
{PA18, PWM_0, 5},
{PA19, PWM_0, 5},
{PA20, PWM_0, 5},
{PA22, PWM_0, 5},
{PA23, PWM_0, 5},
{PA24, PWM_1, 5},
{PA25, PWM_1, 5},
{PA30, PWM_1, 4},
{PA31, PWM_1, 4},
{PB16, PWM_0, 5},
{PB17, PWM_0, 5},
{PB30, PWM_0, 4},
{PB31, PWM_0, 4},
/* Not connected */
{NC , NC , NC}
};
/**********EXTINT*************/
const PinMap PinMap_EXTINT[] = {
{PA16, EXTINT_0, 0},
{PB00, EXTINT_0, 0},
{PB16, EXTINT_0, 0},
{PA00, EXTINT_0, 0},
{PA17, EXTINT_1, 0},
{PB17, EXTINT_1, 0},
{PA01, EXTINT_1, 0},
{PA18, EXTINT_2, 0},
{PB02, EXTINT_2, 0},
{PA19, EXTINT_3, 0},
{PB03, EXTINT_3, 0},
{PA04, EXTINT_4, 0},
{PA20, EXTINT_4, 0},
{PA05, EXTINT_5, 0},
{PA06, EXTINT_6, 0},
{PA22, EXTINT_6, 0},
{PB22, EXTINT_6, 0},
{PA07, EXTINT_7, 0},
{PA23, EXTINT_7, 0},
{PB23, EXTINT_7, 0},
{PA28, EXTINT_8, 0},
{PB08, EXTINT_8, 0},
{PA09, EXTINT_9, 0},
{PB09, EXTINT_9, 0},
{PA30, EXTINT_10, 0},
{PA10, EXTINT_10, 0},
{PA31, EXTINT_11, 0},
{PA11, EXTINT_11, 0},
{PA12, EXTINT_12, 0},
{PA24, EXTINT_12, 0},
{PA13, EXTINT_13, 0},
{PA25, EXTINT_13, 0},
{PB14, EXTINT_14, 0},
{PB30, EXTINT_14, 0},
{PA14, EXTINT_14, 0},
{PA15, EXTINT_15, 0},
{PA27, EXTINT_15, 0},
{PB15, EXTINT_15, 0},
{PB31, EXTINT_15, 0},
/* Not connected */
{NC , NC , NC}
};
const struct pwm_pin_channel pwn_pins[] = {
{PA00, PWM_2, 0},
{PA01, PWM_2, 1},
{PA04, PWM_0, 0},
{PA05, PWM_0, 1},
{PA06, PWM_1, 0},
{PA07, PWM_1, 1},
{PA08, PWM_0, 0},
{PA09, PWM_0, 1},
{PA10, PWM_1, 0},
{PA11, PWM_1, 1},
{PA12, PWM_2, 0},
{PA13, PWM_2, 1},
{PA16, PWM_2, 0},
{PA17, PWM_2, 1},
{PA18, PWM_0, 2},
{PA19, PWM_0, 3},
{PA20, PWM_0, 6},
{PA22, PWM_0, 4},
{PA23, PWM_0, 5},
{PA24, PWM_1, 2},
{PA25, PWM_1, 3},
{PA30, PWM_1, 0},
{PA31, PWM_1, 1},
{PB16, PWM_0, 4},
{PB17, PWM_0, 5},
{PB30, PWM_0, 0},
{PB31, PWM_0, 1},
/* Not connected */
{(PinName) NC ,(PWMName) NC ,(uint8_t) NC}
};

37
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PeripheralPins.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
/************ADC***************/
extern const PinMap PinMap_ADC[];
//*********SERCOM*************/
extern const PinMap PinMap_SERCOM_PAD[];
extern const PinMap PinMap_SERCOM_PADEx[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/**********EXTINT*************/
extern const PinMap PinMap_EXTINT[];
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT,
PIN_INPUT_OUTPUT //pin state can be set and read back
} PinDirection;
typedef enum {
PA00 = 0,
PA01 = 1,
PA04 = 4,
PA05 = 5,
PA06 = 6,
PA07 = 7,
PA08 = 8,
PA09 = 9,
PA10 = 10,
PA11 = 11,
PA12 = 12,
PA13 = 13,
PA14 = 14,
PA15 = 15,
PA16 = 16,
PA17 = 17,
PA18 = 18,
PA19 = 19,
PA20 = 20,
PA22 = 22,
PA23 = 23,
PA24 = 24,
PA25 = 25,
PA27 = 27,
PA28 = 28,
PA30 = 30,
PA31 = 31,
PB00 = 32,
PB02 = 34,
PB03 = 35,
PB08 = 40,
PB09 = 41,
PB14 = 46,
PB15 = 47,
PB16 = 48,
PB17 = 49,
PB22 = 54,
PB23 = 55,
PB30 = 62,
PB31 = 63,
PC16 = 80,
PC18 = 82,
PC19 = 83,
USBTX = PA04,
USBRX = PA05,
LED1 = PA19,
LED2 = PA19,
LED3 = PA19,
LED4 = PA19,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullUp = 1,
PullDown = 2,
PullDefault = PullUp
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

33
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/mbed_overrides.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "compiler.h"
#include "system.h"
uint8_t g_sys_init = 0;
//called before main - implement here if board needs it ortherwise, let
// the application override this if necessary
//TODO: To be implemented by adding system init and board init
void mbed_sdk_init()
{
if(g_sys_init == 0) {
g_sys_init = 1;
system_init();
}
}
/***************************************************************/

475
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/SAMR21_XPLAINED_PRO/samr21_xplained_pro.h
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#ifndef SAMR21_XPLAINED_PRO_H_INCLUDED
#define SAMR21_XPLAINED_PRO_H_INCLUDED
#include <conf_board.h>
#include <compiler.h>
#ifdef __cplusplus
extern "C" {
#endif
/**
* \ingroup group_common_boards
* \defgroup samr21_xplained_pro_group SAM R21 Xplained Pro board
*
* @{
*/
void system_board_init(void);
/**
* \defgroup samr21_xplained_pro_features_group Features
*
* Symbols that describe features and capabilities of the board.
*
* @{
*/
/** Name string macro */
#define BOARD_NAME "SAMR21_XPLAINED_PRO"
/** \name Resonator definitions
* @{ */
#define BOARD_FREQ_SLCK_XTAL (32768U)
#define BOARD_FREQ_SLCK_BYPASS (32768U)
#define BOARD_FREQ_MAINCK_XTAL 0 /* Not Mounted */
#define BOARD_FREQ_MAINCK_BYPASS 0 /* Not Mounted */
#define BOARD_MCK CHIP_FREQ_CPU_MAX
#define BOARD_OSC_STARTUP_US 15625
/** @} */
/** \name LED0 definitions
* @{ */
#define LED0_PIN PIN_PA19
#define LED0_ACTIVE false
#define LED0_INACTIVE !LED0_ACTIVE
#define LED0 LED0_PIN
/** @} */
/** \name SW0 definitions
* @{ */
#define SW0_PIN PIN_PA28
#define SW0_ACTIVE false
#define SW0_INACTIVE !SW0_ACTIVE
#define SW0_EIC_PIN PIN_PA28A_EIC_EXTINT8
#define SW0_EIC_MUX MUX_PA28A_EIC_EXTINT8
#define SW0_EIC_PINMUX PINMUX_PA28A_EIC_EXTINT8
#define SW0_EIC_LINE 8
/** @} */
/**
* \name LED #0 definitions
*
* Wrapper macros for LED0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define LED_0_NAME "LED0 (yellow)"
#define LED_0_PIN LED0_PIN
#define LED_0_ACTIVE LED0_ACTIVE
#define LED_0_INACTIVE LED0_INACTIVE
#define LED0_GPIO LED0_PIN
#define LED_0_PWM_MODULE TC3
#define LED_0_PWM_CHANNEL 1
#define LED_0_PWM_OUTPUT 1
#define LED_0_PWM_PIN PIN_PA19E_TC3_WO1
#define LED_0_PWM_MUX MUX_PA19E_TC3_WO1
#define LED_0_PWM_PINMUX PINMUX_PA19E_TC3_WO1
#define LED_0_PWM4CTRL_MODULE TCC0
#define LED_0_PWM4CTRL_CHANNEL 3
#define LED_0_PWM4CTRL_OUTPUT 3
#define LED_0_PWM4CTRL_PIN PIN_PA19F_TCC0_WO3
#define LED_0_PWM4CTRL_MUX MUX_PA19F_TCC0_WO3
#define LED_0_PWM4CTRL_PINMUX PINMUX_PA19F_TCC0_WO3
/** @} */
/** Number of on-board LEDs */
#define LED_COUNT 1
/**
* \name Button #0 definitions
*
* Wrapper macros for SW0, to ensure common naming across all Xplained Pro
* boards.
*
* @{ */
#define BUTTON_0_NAME "SW0"
#define BUTTON_0_PIN SW0_PIN
#define BUTTON_0_ACTIVE SW0_ACTIVE
#define BUTTON_0_INACTIVE SW0_INACTIVE
#define BUTTON_0_EIC_PIN SW0_EIC_PIN
#define BUTTON_0_EIC_MUX SW0_EIC_MUX
#define BUTTON_0_EIC_PINMUX SW0_EIC_PINMUX
#define BUTTON_0_EIC_LINE SW0_EIC_LINE
/** @} */
/** Number of on-board buttons */
#define BUTTON_COUNT 1
/** \name Extension header #1 pin definitions
* @{
*/
#define EXT1_PIN_3 PIN_PA06
#define EXT1_PIN_4 PIN_PA07
#define EXT1_PIN_5 PIN_PA13
#define EXT1_PIN_6 PIN_PA28
#define EXT1_PIN_7 PIN_PA18
#define EXT1_PIN_8 PIN_PA19
#define EXT1_PIN_9 PIN_PA22
#define EXT1_PIN_10 PIN_PA23
#define EXT1_PIN_11 PIN_PA16
#define EXT1_PIN_12 PIN_PA17
#define EXT1_PIN_13 PIN_PA05
#define EXT1_PIN_14 PIN_PA04
#define EXT1_PIN_15 PIN_PB03
#define EXT1_PIN_16 PIN_PB22
#define EXT1_PIN_17 PIN_PB02
#define EXT1_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #1 pin definitions by function
* @{
*/
#define EXT1_PIN_ADC_0 EXT1_PIN_3
#define EXT1_PIN_ADC_1 EXT1_PIN_4
#define EXT1_PIN_GPIO_0 EXT1_PIN_5
#define EXT1_PIN_GPIO_1 EXT1_PIN_6
#define EXT1_PIN_PWM_0 EXT1_PIN_7
#define EXT1_PIN_PWM_1 EXT1_PIN_8
#define EXT1_PIN_GPIO_3 EXT1_PIN_9
#define EXT1_PIN_GPIO_4 EXT1_PIN_10
#define EXT1_PIN_I2C_SDA EXT1_PIN_11
#define EXT1_PIN_I2C_SCL EXT1_PIN_12
#define EXT1_PIN_UART_RX EXT1_PIN_13
#define EXT1_PIN_UART_TX EXT1_PIN_14
#define EXT1_PIN_SPI_SS_0 EXT1_PIN_15
#define EXT1_PIN_SPI_MOSI EXT1_PIN_16
#define EXT1_PIN_SPI_MISO EXT1_PIN_17
#define EXT1_PIN_SPI_SCK EXT1_PIN_18
/** @} */
/** \name Extension header #1 ADC definitions
* @{
*/
#define EXT1_ADC_MODULE ADC
#define EXT1_ADC_0_CHANNEL 6
#define EXT1_ADC_0_PIN PIN_PA06B_ADC_AIN6
#define EXT1_ADC_0_MUX MUX_PA06B_ADC_AIN6
#define EXT1_ADC_0_PINMUX PINMUX_PA06B_ADC_AIN6
#define EXT1_ADC_1_CHANNEL 7
#define EXT1_ADC_1_PIN PIN_PA07B_ADC_AIN7
#define EXT1_ADC_1_MUX MUX_PA07B_ADC_AIN7
#define EXT1_ADC_1_PINMUX PINMUX_PA07B_ADC_AIN7
/** @} */
/** \name Extension header #1 PWM definitions
* @{
*/
#define EXT1_PWM_MODULE TC3
#define EXT1_PWM_0_CHANNEL 0
#define EXT1_PWM_0_PIN PIN_PA18E_TC3_WO0
#define EXT1_PWM_0_MUX MUX_PA18E_TC3_WO0
#define EXT1_PWM_0_PINMUX PINMUX_PA18E_TC3_WO0
#define EXT1_PWM_1_CHANNEL 1
#define EXT1_PWM_1_PIN PIN_PA19E_TC3_WO1
#define EXT1_PWM_1_MUX MUX_PA19E_TC3_WO1
#define EXT1_PWM_1_PINMUX PINMUX_PA19E_TC3_WO1
/** @} */
/** \name Extension header #1 PWM for Control definitions
* @{
*/
#define EXT1_PWM4CTRL_MODULE TCC0
#define EXT1_PWM4CTRL_0_CHANNEL 2
#define EXT1_PWM4CTRL_0_OUTPUT 2
#define EXT1_PWM4CTRL_0_PIN PIN_PA18F_TCC0_WO2
#define EXT1_PWM4CTRL_0_MUX MUX_PA18F_TCC0_WO2
#define EXT1_PWM4CTRL_0_PINMUX PINMUX_PA18F_TCC0_WO2
#define EXT1_PWM4CTRL_1_CHANNEL 3
#define EXT1_PWM4CTRL_1_OUTPUT 3
#define EXT1_PWM4CTRL_1_PIN PIN_PA19F_TCC0_WO3
#define EXT1_PWM4CTRL_1_MUX MUX_PA19F_TCC0_WO3
#define EXT1_PWM4CTRL_1_PINMUX PINMUX_PA19F_TCC0_WO3
/** @} */
/** \name Extension header #1 IRQ/External interrupt definitions
* @{
*/
#define EXT1_IRQ_MODULE EIC
#define EXT1_IRQ_INPUT 6
#define EXT1_IRQ_PIN PIN_PA22A_EIC_EXTINT6
#define EXT1_IRQ_MUX MUX_PA22A_EIC_EXTINT6
#define EXT1_IRQ_PINMUX PINMUX_PA22A_EIC_EXTINT6
/** @} */
/** \name Extension header #1 I2C definitions
* @{
*/
#define EXT1_I2C_MODULE SERCOM1
#define EXT1_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EXT1_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EXT1_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EXT1_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Extension header #1 UART definitions
* @{
*/
#define EXT1_UART_MODULE SERCOM0
#define EXT1_UART_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EXT1_UART_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EXT1_UART_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EXT1_UART_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EXT1_UART_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EXT1_UART_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EXT1_UART_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
/** \name Extension header #1 SPI definitions
* @{
*/
#define EXT1_SPI_MODULE SERCOM5
#define EXT1_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT1_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
#define EXT1_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB03D_SERCOM5_PAD1
#define EXT1_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT1_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT1_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT1_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 pin definitions
* @{
*/
#define EXT3_PIN_5 PIN_PA15
#define EXT3_PIN_10 PIN_PA08
#define EXT3_PIN_11 PIN_PA16
#define EXT3_PIN_12 PIN_PA17
#define EXT3_PIN_15 PIN_PA14
#define EXT3_PIN_16 PIN_PB22
#define EXT3_PIN_17 PIN_PB02
#define EXT3_PIN_18 PIN_PB23
/** @} */
/** \name Extension header #3 pin definitions by function
* @{
*/
#define EXT3_PIN_GPIO_0 EXT3_PIN_5
#define EXT3_PIN_GPIO_1 EXT3_PIN_10
#define EXT3_PIN_I2C_SDA EXT3_PIN_11
#define EXT3_PIN_I2C_SCL EXT3_PIN_12
#define EXT3_PIN_GPIO_2 EXT3_PIN_15
#define EXT3_PIN_SPI_MOSI EXT3_PIN_16
#define EXT3_PIN_SPI_MISO EXT3_PIN_17
#define EXT3_PIN_SPI_SCK EXT3_PIN_18
/** @} */
/** \name Extension header #3 SPI definitions
* @{
*/
#define EXT3_SPI_SLAVE_SELECT_PIN PIN_PA14
#define EXT3_SPI_MODULE SERCOM5
#define EXT3_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EXT3_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
#define EXT3_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EXT3_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EXT3_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EXT3_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EXT3_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Extension header #3 Dataflash
* @{
*/
#define EXT3_DATAFLASH_SPI_MODULE EXT3_SPI_MODULE
#define EXT3_DATAFLASH_SPI_MUX_SETTING EXT3_SPI_SERCOM_MUX_SETTING
#define EXT3_DATAFLASH_SPI_PINMUX_PAD0 EXT3_SPI_SERCOM_PINMUX_PAD0
#define EXT3_DATAFLASH_SPI_PINMUX_PAD1 EXT3_SPI_SERCOM_PINMUX_PAD1
#define EXT3_DATAFLASH_SPI_PINMUX_PAD2 EXT3_SPI_SERCOM_PINMUX_PAD2
#define EXT3_DATAFLASH_SPI_PINMUX_PAD3 EXT3_SPI_SERCOM_PINMUX_PAD3
/** @} */
/** \name USB definitions
* @{
*/
#define USB_ID
#define USB_TARGET_DP_PIN PIN_PA25G_USB_DP
#define USB_TARGET_DP_MUX MUX_PA25G_USB_DP
#define USB_TARGET_DP_PINMUX PINMUX_PA25G_USB_DP
#define USB_TARGET_DM_PIN PIN_PA24G_USB_DM
#define USB_TARGET_DM_MUX MUX_PA24G_USB_DM
#define USB_TARGET_DM_PINMUX PINMUX_PA24G_USB_DM
#define USB_VBUS_PIN PIN_PA07
#define USB_VBUS_EIC_LINE 7
#define USB_VBUS_EIC_MUX MUX_PA07A_EIC_EXTINT7
#define USB_VBUS_EIC_PINMUX PINMUX_PA07A_EIC_EXTINT7
/* USB ID pin is not connected */
//#define USB_ID_PIN -1
//#define USB_ID_EIC_LINE -1
//#define USB_ID_EIC_MUX -1
//#define USB_ID_EIC_PINMUX -1
/** @} */
/** \name Embedded debugger GPIO interface definitions
* @{
*/
#define EDBG_GPIO0_PIN PIN_PA08
#define EDBG_GPIO1_PIN PIN_PA09
#define EDBG_GPIO2_PIN PIN_PA12
#define EDBG_GPIO3_PIN PIN_PA14
/** @} */
/** \name Embedded debugger USART interface definitions
* @{
*/
#define EDBG_UART_MODULE -1 /* Not available on this board */
#define EDBG_UART_RX_PIN -1 /* Not available on this board */
#define EDBG_UART_RX_MUX -1 /* Not available on this board */
#define EDBG_UART_RX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_RX_SERCOM_PAD -1 /* Not available on this board */
#define EDBG_UART_TX_PIN -1 /* Not available on this board */
#define EDBG_UART_TX_MUX -1 /* Not available on this board */
#define EDBG_UART_TX_PINMUX -1 /* Not available on this board */
#define EDBG_UART_TX_SERCOM_PAD -1 /* Not available on this board */
/** @} */
/** \name Embedded debugger I2C interface definitions
* @{
*/
#define EDBG_I2C_MODULE SERCOM1
#define EDBG_I2C_SERCOM_PINMUX_PAD0 PINMUX_PA16C_SERCOM1_PAD0
#define EDBG_I2C_SERCOM_PINMUX_PAD1 PINMUX_PA17C_SERCOM1_PAD1
#define EDBG_I2C_SERCOM_DMAC_ID_TX SERCOM1_DMAC_ID_TX
#define EDBG_I2C_SERCOM_DMAC_ID_RX SERCOM1_DMAC_ID_RX
/** @} */
/** \name Embedded debugger SPI interface definitions
* @{
*/
#define EDBG_SPI_SLAVE_SELECT_PIN PIN_PA27
#define EDBG_SPI_MODULE SERCOM5
#define EDBG_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define EDBG_SPI_SERCOM_PINMUX_PAD0 PINMUX_PB02D_SERCOM5_PAD0
#define EDBG_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define EDBG_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB22D_SERCOM5_PAD2
#define EDBG_SPI_SERCOM_PINMUX_PAD3 PINMUX_PB23D_SERCOM5_PAD3
#define EDBG_SPI_SERCOM_DMAC_ID_TX SERCOM5_DMAC_ID_TX
#define EDBG_SPI_SERCOM_DMAC_ID_RX SERCOM5_DMAC_ID_RX
/** @} */
/** \name Embedded debugger CDC Gateway USART interface definitions
* @{
*/
#define EDBG_CDC_MODULE SERCOM0
#define EDBG_CDC_SERCOM_MUX_SETTING USART_RX_1_TX_0_XCK_1
#define EDBG_CDC_SERCOM_PINMUX_PAD0 PINMUX_PA04D_SERCOM0_PAD0
#define EDBG_CDC_SERCOM_PINMUX_PAD1 PINMUX_PA05D_SERCOM0_PAD1
#define EDBG_CDC_SERCOM_PINMUX_PAD2 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_PINMUX_PAD3 PINMUX_UNUSED
#define EDBG_CDC_SERCOM_DMAC_ID_TX SERCOM0_DMAC_ID_TX
#define EDBG_CDC_SERCOM_DMAC_ID_RX SERCOM0_DMAC_ID_RX
/** @} */
#define RF_SPI_MODULE SERCOM4
#define RF_SPI_SERCOM_MUX_SETTING SPI_SIGNAL_MUX_SETTING_E
#define RF_SPI_SERCOM_PINMUX_PAD0 PINMUX_PC19F_SERCOM4_PAD0
#define RF_SPI_SERCOM_PINMUX_PAD1 PINMUX_PB31D_SERCOM5_PAD1
#define RF_SPI_SERCOM_PINMUX_PAD2 PINMUX_PB30F_SERCOM4_PAD2
#define RF_SPI_SERCOM_PINMUX_PAD3 PINMUX_PC18F_SERCOM4_PAD3
#define RF_IRQ_MODULE EIC
#define RF_IRQ_INPUT 0
#define RF_IRQ_PIN PIN_PB00A_EIC_EXTINT0
#define RF_IRQ_MUX MUX_PB00A_EIC_EXTINT0
#define RF_IRQ_PINMUX PINMUX_PB00A_EIC_EXTINT0
/** \name 802.15.4 TRX Interface definitions
* @{
*/
#define AT86RFX_SPI SERCOM4
#define AT86RFX_RST_PIN PIN_PB15
#define AT86RFX_IRQ_PIN PIN_PB00
#define AT86RFX_SLP_PIN PIN_PA20
#define AT86RFX_SPI_CS PIN_PB31
#define AT86RFX_SPI_MOSI PIN_PB30
#define AT86RFX_SPI_MISO PIN_PC19
#define AT86RFX_SPI_SCK PIN_PC18
#define PIN_RFCTRL1 PIN_PA09
#define PIN_RFCTRL2 PIN_PA12
#define RFCTRL_CFG_ANT_DIV 4
#define AT86RFX_SPI_SERCOM_MUX_SETTING RF_SPI_SERCOM_MUX_SETTING
#define AT86RFX_SPI_SERCOM_PINMUX_PAD0 RF_SPI_SERCOM_PINMUX_PAD0
#define AT86RFX_SPI_SERCOM_PINMUX_PAD1 PINMUX_UNUSED
#define AT86RFX_SPI_SERCOM_PINMUX_PAD2 RF_SPI_SERCOM_PINMUX_PAD2
#define AT86RFX_SPI_SERCOM_PINMUX_PAD3 RF_SPI_SERCOM_PINMUX_PAD3
#define AT86RFX_IRQ_CHAN RF_IRQ_INPUT
#define AT86RFX_IRQ_PINMUX RF_IRQ_PINMUX
/** Enables the transceiver main interrupt. */
#define ENABLE_TRX_IRQ() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Disables the transceiver main interrupt. */
#define DISABLE_TRX_IRQ() \
extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/** Clears the transceiver main interrupt. */
#define CLEAR_TRX_IRQ() \
extint_chan_clear_detected(AT86RFX_IRQ_CHAN);
/*
* This macro saves the trx interrupt status and disables the trx interrupt.
*/
#define ENTER_TRX_REGION() \
{ extint_chan_disable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT)
/*
* This macro restores the transceiver interrupt status
*/
#define LEAVE_TRX_REGION() \
extint_chan_enable_callback(AT86RFX_IRQ_CHAN, EXTINT_CALLBACK_TYPE_DETECT); }
/** @} */
/**
* \brief Turns off the specified LEDs.
*
* \param led_gpio LED to turn off (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Off(led_gpio) port_pin_set_output_level(led_gpio,true)
/**
* \brief Turns on the specified LEDs.
*
* \param led_gpio LED to turn on (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_On(led_gpio) port_pin_set_output_level(led_gpio,false)
/**
* \brief Toggles the specified LEDs.
*
* \param led_gpio LED to toggle (LEDx_GPIO).
*
* \note The pins of the specified LEDs are set to GPIO output mode.
*/
#define LED_Toggle(led_gpio) port_pin_toggle_output_level(led_gpio)
#ifdef __cplusplus
}
#endif
#endif /* SAMR21_XPLAINED_PRO_H_INCLUDED */

38
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device.h
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@ -1,38 +0,0 @@
// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#include "objects.h"
#endif

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/SAMR21G18A.sct
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@ -1,50 +0,0 @@
#! armcc -E
;SAMR21G18A
; 256KB FLASH (0x40000) @ 0x000000000
#if !defined(MBED_APP_START)
#define MBED_APP_START 0x00000000
#endif
; SAMR21G18A: 256KB FLASH (0x40000)
#if !defined(MBED_APP_SIZE)
#define MBED_APP_SIZE 0x40000
#endif
; 32KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_RAM_START)
#define MBED_RAM_START 0x20000000
#endif
#if !defined(MBED_RAM_SIZE)
#define MBED_RAM_SIZE 0x8000
#endif
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
#define VECTOR_SIZE 0xB0
#define RAM_FIXED_SIZE (MBED_BOOT_STACK_SIZE+VECTOR_SIZE)
LR_IROM1 MBED_APP_START MBED_APP_SIZE { ; load region size_region
ER_IROM1 MBED_APP_START MBED_APP_SIZE { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 (MBED_RAM_START+VECTOR_SIZE) (MBED_RAM_SIZE-VECTOR_SIZE) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_HEAP AlignExpr(+0, 16) EMPTY (MBED_RAM_SIZE-RAM_FIXED_SIZE+MBED_RAM_START-AlignExpr(ImageLimit(RW_IRAM1), 16)) {
}
ARM_LIB_STACK (MBED_RAM_START+MBED_RAM_SIZE) EMPTY -MBED_BOOT_STACK_SIZE { ; stack
}
}

189
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S
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@ -1,189 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMR21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMR21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

27
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/SAMR21G18A.sct
View File

@ -1,27 +0,0 @@
#! armcc -E
;SAMR21G18A
;256KB FLASH (0x40000) @ 0x000000000
;2KB RAM (0x8000) @ 0x20000000
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
#define Stack_Size MBED_BOOT_STACK_SIZE
;SAMR21G18A: 256KB FLASH (0x40000) + 32KB RAM (0x8000)
LR_IROM1 0x00000000 0x40000 { ; load region size_region
ER_IROM1 0x00000000 0x40000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
; [RAM] Vector table dynamic copy: 44 vectors * 4 bytes = (0xB0) - alignment
RW_IRAM1 (0x20000000+0xB0) (0x8000-0xB0-Stack_Size) { ; RW data
.ANY (+RW +ZI)
}
ARM_LIB_STACK 0x20000000+0x8000 EMPTY -Stack_Size { ; Stack region growing down
}
}

189
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S
View File

@ -1,189 +0,0 @@
;/*****************************************************************************
; * @file startup_SAMR21.s
; * @brief CMSIS Cortex-M0+ Core Device Startup File for
; * Atmel SAMR21 Device Series
; * @version V1.00
; * @date 24. February 2014
; *
; * @note
; * Copyright (C) 2014 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PM_Handler ; 0 Power Manager
DCD SYSCTRL_Handler ; 1 System Control
DCD WDT_Handler ; 2 Watchdog Timer
DCD RTC_Handler ; 3 Real-Time Counter
DCD EIC_Handler ; 4 External Interrupt Controller
DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller
DCD DMAC_Handler ; 6 Direct Memory Access Controller
DCD USB_Handler ; 7 Universal Serial Bus
DCD EVSYS_Handler ; 8 Event System Interface
DCD SERCOM0_Handler ; 9 Serial Communication Interface 0
DCD SERCOM1_Handler ; 10 Serial Communication Interface 1
DCD SERCOM2_Handler ; 11 Serial Communication Interface 2
DCD SERCOM3_Handler ; 12 Serial Communication Interface 3
DCD SERCOM4_Handler ; 13 Serial Communication Interface 4
DCD SERCOM5_Handler ; 14 Serial Communication Interface 5
DCD TCC0_Handler ; 15 Timer Counter Control 0
DCD TCC1_Handler ; 16 Timer Counter Control 1
DCD TCC2_Handler ; 17 Timer Counter Control 2
DCD TC3_Handler ; 18 Basic Timer Counter 0
DCD TC4_Handler ; 19 Basic Timer Counter 1
DCD TC5_Handler ; 20 Basic Timer Counter 2
DCD TC6_Handler ; 21 Basic Timer Counter 3
DCD TC7_Handler ; 22 Basic Timer Counter 4
DCD ADC_Handler ; 23 Analog Digital Converter
DCD AC_Handler ; 24 Analog Comparators
DCD DAC_Handler ; 25 Digital Analog Converter
DCD PTC_Handler ; 26 Peripheral Touch Controller
DCD I2S_Handler ; 27 Inter-IC Sound Interface
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PM_Handler [WEAK]
EXPORT SYSCTRL_Handler [WEAK]
EXPORT WDT_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT EIC_Handler [WEAK]
EXPORT NVMCTRL_Handler [WEAK]
EXPORT DMAC_Handler [WEAK]
EXPORT USB_Handler [WEAK]
EXPORT EVSYS_Handler [WEAK]
EXPORT SERCOM0_Handler [WEAK]
EXPORT SERCOM1_Handler [WEAK]
EXPORT SERCOM2_Handler [WEAK]
EXPORT SERCOM3_Handler [WEAK]
EXPORT SERCOM4_Handler [WEAK]
EXPORT SERCOM5_Handler [WEAK]
EXPORT TCC0_Handler [WEAK]
EXPORT TCC1_Handler [WEAK]
EXPORT TCC2_Handler [WEAK]
EXPORT TC3_Handler [WEAK]
EXPORT TC4_Handler [WEAK]
EXPORT TC5_Handler [WEAK]
EXPORT TC6_Handler [WEAK]
EXPORT TC7_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT AC_Handler [WEAK]
EXPORT DAC_Handler [WEAK]
EXPORT PTC_Handler [WEAK]
EXPORT I2S_Handler [WEAK]
PM_Handler
SYSCTRL_Handler
WDT_Handler
RTC_Handler
EIC_Handler
NVMCTRL_Handler
DMAC_Handler
USB_Handler
EVSYS_Handler
SERCOM0_Handler
SERCOM1_Handler
SERCOM2_Handler
SERCOM3_Handler
SERCOM4_Handler
SERCOM5_Handler
TCC0_Handler
TCC1_Handler
TCC2_Handler
TC3_Handler
TC4_Handler
TC5_Handler
TC6_Handler
TC7_Handler
ADC_Handler
AC_Handler
DAC_Handler
PTC_Handler
I2S_Handler
B .
ENDP
ALIGN
END

127
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/samr21g18a.ld
View File

@ -1,127 +0,0 @@
OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
OUTPUT_ARCH(arm)
SEARCH_DIR(.)
#if !defined(MBED_BOOT_STACK_SIZE)
#define MBED_BOOT_STACK_SIZE 0x400
#endif
STACK_SIZE = MBED_BOOT_STACK_SIZE;
/* Memory Spaces Definitions */
MEMORY {
rom (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000
ram (rwx) : ORIGIN = 0x20000000 + 0xB0, LENGTH = 0x00008000 - 0xB0
}
/* Section Definitions */
SECTIONS {
.text :
{
. = ALIGN(8);
_sfixed = .;
KEEP(*(.vectors .vectors.*))
*(.text .text.* .gnu.linkonce.t.*)
*(.glue_7t) *(.glue_7)
*(.rodata .rodata* .gnu.linkonce.r.*)
*(.ARM.extab* .gnu.linkonce.armextab.*)
/* Support C constructors, and C destructors in both user code
and the C library. This also provides support for C++ code. */
. = ALIGN(8);
KEEP(*(.init))
. = ALIGN(8);
__preinit_array_start = .;
KEEP (*(.preinit_array))
__preinit_array_end = .;
. = ALIGN(8);
__init_array_start = .;
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
__init_array_end = .;
. = ALIGN(8);
KEEP (*crtbegin.o(.ctors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
KEEP (*(SORT(.ctors.*)))
KEEP (*crtend.o(.ctors))
. = ALIGN(8);
KEEP(*(.fini))
. = ALIGN(8);
__fini_array_start = .;
KEEP (*(.fini_array))
KEEP (*(SORT(.fini_array.*)))
__fini_array_end = .;
KEEP (*crtbegin.o(.dtors))
KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
KEEP (*(SORT(.dtors.*)))
KEEP (*crtend.o(.dtors))
. = ALIGN(8);
_efixed = .; /* End of text section */
} > rom
/* .ARM.exidx is sorted, so has to go in its own output section. */
PROVIDE_HIDDEN (__exidx_start = .);
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > rom
PROVIDE_HIDDEN (__exidx_end = .);
. = ALIGN(8);
_etext = .;
.relocate :
AT (_etext)
{
. = ALIGN(8);
_srelocate = .;
*(.ramfunc .ramfunc.*);
*(.data .data.*);
. = ALIGN(8);
_erelocate = .;
} > ram
/* .bss section which is used for uninitialized data */
.bss (NOLOAD) :
{
. = ALIGN(8);
_sbss = . ;
_szero = .;
*(.bss .bss.*)
*(COMMON)
. = ALIGN(8);
_ebss = . ;
_ezero = .;
} > ram
.heap (NOLOAD) :
{
. = ALIGN(8);
__end__ = . ;
. = ORIGIN(ram) + LENGTH(ram) - STACK_SIZE;
__HeapLimit = .;
} > ram
/* stack section */
.stack (NOLOAD):
{
. = ALIGN(8);
_sstack = .;
. = . + STACK_SIZE;
. = ALIGN(8);
_estack = .;
} > ram
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - STACK_SIZE;
. = ALIGN(8);
}

212
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_GCC_ARM/startup_samr21.c
View File

@ -1,212 +0,0 @@
#include "samr21.h"
/* Initialize segments */
extern uint32_t _sfixed;
extern uint32_t _efixed;
extern uint32_t _etext;
extern uint32_t _srelocate;
extern uint32_t _erelocate;
extern uint32_t _szero;
extern uint32_t _ezero;
extern uint32_t _sstack;
extern uint32_t _estack;
/** \cond DOXYGEN_SHOULD_SKIP_THIS */
int main(void);
/** \endcond */
void __libc_init_array(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
void NMI_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void HardFault_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SVC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void PendSV_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SysTick_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Peripherals handlers */
void PM_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SYSCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void WDT_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void RTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void EIC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void NVMCTRL_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void DMAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef USB_IRQn
void USB_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void EVSYS_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void SERCOM3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef SERCOM4_IRQn
void SERCOM4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef SERCOM5_IRQn
void SERCOM5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void TCC0_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC1_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TCC2_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC3_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC4_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
void TC5_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#ifdef TC6_IRQn
void TC6_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef TC7_IRQn
void TC7_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef ADC_IRQn
void ADC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef AC_IRQn
void AC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef DAC_IRQn
void DAC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
#ifdef PTC_IRQn
void PTC_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
#endif
void I2S_Handler ( void ) __attribute__ ((weak, alias("Dummy_Handler")));
/* Exception Table */
__attribute__ ((section(".vectors")))
const DeviceVectors exception_table = {
/* Configure Initial Stack Pointer, using linker-generated symbols */
(void*) (&_estack),
(void*) Reset_Handler,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef USB_IRQn
(void*) USB_Handler, /* 7 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef SERCOM4_IRQn
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef SERCOM5_IRQn
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef TC6_IRQn
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef TC7_IRQn
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef ADC_IRQn
(void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef AC_IRQn
(void*) AC_Handler, /* 24 Analog Comparators */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef DAC_IRQn
(void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
(void*) (0UL), /* Reserved */
#endif
#ifdef PTC_IRQn
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved */
#endif
(void*) I2S_Handler /* 27 Inter-IC Sound Interface */
};
/**
* \brief This is the code that gets called on processor reset.
* To initialize the device, and call the main() routine.
*/
void Reset_Handler(void)
{
uint32_t *pSrc, *pDest;
/* Initialize the relocate segment */
pSrc = &_etext;
pDest = &_srelocate;
if (pSrc != pDest) {
for (; pDest < &_erelocate;) {
*pDest++ = *pSrc++;
}
}
/* Clear the zero segment */
for (pDest = &_szero; pDest < &_ezero;) {
*pDest++ = 0;
}
/* Set the vector table base address */
pSrc = (uint32_t *) & _sfixed;
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
/* Initialize the C library */
__libc_init_array();
/* Branch to main function */
main();
/* Infinite loop */
while (1);
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

249
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_IAR/startup_samr21.c
View File

@ -1,249 +0,0 @@
/**
* \file
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
#include "samr21.h"
typedef void (*intfunc) (void);
typedef union {
intfunc __fun;
void * __ptr;
} intvec_elem;
void __iar_program_start(void);
int __low_level_init(void);
/* Default empty handler */
void Dummy_Handler(void);
/* Cortex-M0+ core handlers */
#pragma weak NMI_Handler = Dummy_Handler
#pragma weak HardFault_Handler = Dummy_Handler
#pragma weak SVC_Handler = Dummy_Handler
#pragma weak PendSV_Handler = Dummy_Handler
#pragma weak SysTick_Handler = Dummy_Handler
/* Peripherals handlers */
#pragma weak PM_Handler = Dummy_Handler
#pragma weak SYSCTRL_Handler = Dummy_Handler
#pragma weak WDT_Handler = Dummy_Handler
#pragma weak RTC_Handler = Dummy_Handler
#pragma weak EIC_Handler = Dummy_Handler
#pragma weak NVMCTRL_Handler = Dummy_Handler
#pragma weak DMAC_Handler = Dummy_Handler
#ifdef ID_USB
#pragma weak USB_Handler = Dummy_Handler
#endif
#pragma weak EVSYS_Handler = Dummy_Handler
#pragma weak SERCOM0_Handler = Dummy_Handler
#pragma weak SERCOM1_Handler = Dummy_Handler
#pragma weak SERCOM2_Handler = Dummy_Handler
#pragma weak SERCOM3_Handler = Dummy_Handler
#ifdef ID_SERCOM4
#pragma weak SERCOM4_Handler = Dummy_Handler
#endif
#ifdef ID_SERCOM5
#pragma weak SERCOM5_Handler = Dummy_Handler
#endif
#pragma weak TCC0_Handler = Dummy_Handler
#pragma weak TCC1_Handler = Dummy_Handler
#pragma weak TCC2_Handler = Dummy_Handler
#pragma weak TC3_Handler = Dummy_Handler
#pragma weak TC4_Handler = Dummy_Handler
#pragma weak TC5_Handler = Dummy_Handler
#ifdef ID_TC6
#pragma weak TC6_Handler = Dummy_Handler
#endif
#ifdef ID_TC7
#pragma weak TC7_Handler = Dummy_Handler
#endif
#ifdef ID_ADC
#pragma weak ADC_Handler = Dummy_Handler
#endif
#ifdef ID_AC
#pragma weak AC_Handler = Dummy_Handler
#endif
#ifdef ID_DAC
#pragma weak DAC_Handler = Dummy_Handler
#endif
#ifdef ID_PTC
#pragma weak PTC_Handler = Dummy_Handler
#endif
#pragma weak I2S_Handler = Dummy_Handler
/* Exception Table */
#pragma language = extended
#pragma segment = "CSTACK"
/* The name "__vector_table" has special meaning for C-SPY: */
/* it is where the SP start value is found, and the NVIC vector */
/* table register (VTOR) is initialized to this address if != 0 */
#pragma section = ".intvec"
#pragma location = ".intvec"
const DeviceVectors __vector_table[] = {
__sfe("CSTACK"),
(void*) __iar_program_start,
(void*) NMI_Handler,
(void*) HardFault_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) SVC_Handler,
(void*) (0UL), /* Reserved */
(void*) (0UL), /* Reserved */
(void*) PendSV_Handler,
(void*) SysTick_Handler,
/* Configurable interrupts */
(void*) PM_Handler, /* 0 Power Manager */
(void*) SYSCTRL_Handler, /* 1 System Control */
(void*) WDT_Handler, /* 2 Watchdog Timer */
(void*) RTC_Handler, /* 3 Real-Time Counter */
(void*) EIC_Handler, /* 4 External Interrupt Controller */
(void*) NVMCTRL_Handler, /* 5 Non-Volatile Memory Controller */
(void*) DMAC_Handler, /* 6 Direct Memory Access Controller */
#ifdef ID_USB
(void*) USB_Handler, /* 7 Universal Serial Bus */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) EVSYS_Handler, /* 8 Event System Interface */
(void*) SERCOM0_Handler, /* 9 Serial Communication Interface 0 */
(void*) SERCOM1_Handler, /* 10 Serial Communication Interface 1 */
(void*) SERCOM2_Handler, /* 11 Serial Communication Interface 2 */
(void*) SERCOM3_Handler, /* 12 Serial Communication Interface 3 */
#ifdef ID_SERCOM4
(void*) SERCOM4_Handler, /* 13 Serial Communication Interface 4 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_SERCOM5
(void*) SERCOM5_Handler, /* 14 Serial Communication Interface 5 */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) TCC0_Handler, /* 15 Timer Counter Control 0 */
(void*) TCC1_Handler, /* 16 Timer Counter Control 1 */
(void*) TCC2_Handler, /* 17 Timer Counter Control 2 */
(void*) TC3_Handler, /* 18 Basic Timer Counter 0 */
(void*) TC4_Handler, /* 19 Basic Timer Counter 1 */
(void*) TC5_Handler, /* 20 Basic Timer Counter 2 */
#ifdef ID_TC6
(void*) TC6_Handler, /* 21 Basic Timer Counter 3 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_TC7
(void*) TC7_Handler, /* 22 Basic Timer Counter 4 */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_ADC
(void*) ADC_Handler, /* 23 Analog Digital Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_AC
(void*) AC_Handler, /* 24 Analog Comparators */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_DAC
(void*) DAC_Handler, /* 25 Digital Analog Converter */
#else
(void*) (0UL), /* Reserved*/
#endif
#ifdef ID_PTC
(void*) PTC_Handler, /* 26 Peripheral Touch Controller */
#else
(void*) (0UL), /* Reserved*/
#endif
(void*) I2S_Handler, /* 27 Inter-IC Sound Interface */
(void*) (0UL), /* Reserved */
};
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
int __low_level_init(void)
{
uint32_t *pSrc = __section_begin(".intvec");
SCB->VTOR = ((uint32_t) pSrc & SCB_VTOR_TBLOFF_Msk);
return 1; /* if return 0, the data sections will not be initialized */
}
/**------------------------------------------------------------------------------
* This is the code that gets called on processor reset. To initialize the
* device.
*------------------------------------------------------------------------------*/
void Reset_Handler(void)
{
/* Change default QOS values to have the best performance and correct USB behaviour */
SBMATRIX->SFR[SBMATRIX_SLAVE_HMCRAMC0].reg = 2;
#if defined(ID_USB)
USB->DEVICE.QOSCTRL.bit.CQOS = 2;
USB->DEVICE.QOSCTRL.bit.DQOS = 2;
#endif
DMAC->QOSCTRL.bit.DQOS = 2;
DMAC->QOSCTRL.bit.FQOS = 2;
DMAC->QOSCTRL.bit.WRBQOS = 2;
/* Overwriting the default value of the NVMCTRL.CTRLB.MANW bit (errata reference 13134) */
NVMCTRL->CTRLB.bit.MANW = 1;
__iar_program_start();
}
/**
* \brief Default interrupt handler for unused IRQs.
*/
void Dummy_Handler(void)
{
while (1) {
}
}

231
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/analogin_api.c
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@ -1,231 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
#include "adc.h"
#include "status_codes.h"
extern uint8_t g_sys_init;
struct adc_module adc_instance;
void adc_configure_ain_pin(uint32_t pin)
{
#define PIN_INVALID_ADC_AIN 0xFFFFUL
/* Pinmapping table for AINxx -> GPIO pin number */
const uint32_t pinmapping[] = {
#if (SAMD20E | SAMD21E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20G | SAMD21G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20J | SAMD21J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif SAMR21E
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif SAMR21G
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD10C | SAMD11C)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DS | SAMD11DS)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DM | SAMD11DM)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAML21E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAML21G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAML21J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#else
# error ADC pin mappings are not defined for this device.
#endif
};
uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
if (pin <= ADC_EXTCHANNEL_MSB) {
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
struct system_pinmux_config config;
system_pinmux_get_config_defaults(&config);
/* Analog functions are all on MUX setting B */
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
config.mux_position = 1;
system_pinmux_pin_set_config(pin_map_result, &config);
}
}
void analogin_init(analogin_t *obj, PinName pin)
{
MBED_ASSERT(obj);
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
uint32_t pos_input;
static uint8_t init_flag = 0;
pos_input = pinmap_find_peripheral(pin, PinMap_ADC);
MBED_ASSERT(pos_input != (uint32_t)NC);
adc_get_config_defaults(&(obj->config_adc));
obj->config_adc.positive_input = (enum adc_positive_input)pos_input;
if (init_flag == 0) { // ADC init and enable to be done only once.
adc_init(&adc_instance, ADC, &(obj->config_adc));
adc_enable(&adc_instance);
init_flag = 1;
}
adc_configure_ain_pin(obj->config_adc.positive_input);
adc_configure_ain_pin(obj->config_adc.negative_input);
}
uint16_t analogin_read_u16(analogin_t *obj)
{
MBED_ASSERT(obj);
uint16_t result;
adc_set_positive_input(&adc_instance, obj->config_adc.positive_input);
adc_set_negative_input(&adc_instance, obj->config_adc.negative_input);
adc_start_conversion(&adc_instance);
do {
} while(adc_read(&(adc_instance), &result) == STATUS_BUSY); // 12 bit value
return (uint16_t)(((uint32_t)result * 0xFFFF) / 0x0FFF); // for normalizing to 16 bit value
}
float analogin_read(analogin_t *obj)
{
MBED_ASSERT(obj);
uint16_t value = analogin_read_u16(obj);
return (float)value * (1.0f / (float)0xFFFF);
}
const PinMap *analogin_pinmap()
{
return PinMap_ADC;
}

50
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_board.h
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@ -1,50 +0,0 @@
/**
* \file
*
* \brief SAM D21 Xplained Pro board configuration.
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
#endif /* CONF_BOARD_H_INCLUDED */

198
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_clocks.h
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/**
* \file
*
* \brief SAM D21 Clock configuration
*
* Copyright (C) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 0
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
# define CONF_CLOCK_OSC8M_ON_DEMAND true
# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY true
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND false
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY true
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT false
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE false
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND false
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768)
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 8)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 8)
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND false
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY true
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE true
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE true
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 (RTC) */
# define CONF_CLOCK_GCLK_2_ENABLE true
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY true
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_ULP32K
# define CONF_CLOCK_GCLK_2_PRESCALER 32
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

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/**
* \file
*
* \brief SAM D21 Direct Memory Access Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_DMA_H_INCLUDED
#define CONF_DMA_H_INCLUDED
# define CONF_MAX_USED_CHANNEL_NUM 1
#endif

51
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_extint.h
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/**
* \file
*
* \brief SAM D21 External Interrupt Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_EXTINT_H_INCLUDED
#define CONF_EXTINT_H_INCLUDED
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_spi.h
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/**
* \file
*
* \brief SAM D21 SPI configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_SPI_H_INCLUDED
# define CONF_SPI_H_INCLUDED
# define CONF_SPI_MASTER_ENABLE true
# define CONF_SPI_SLAVE_ENABLE false
# define CONF_SPI_TIMEOUT 10000
#endif /* CONF_SPI_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMD21/conf_test.h
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/**
* \file
*
* \brief SAM D21 Xplained Pro test configuration.
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_TEST_H_INCLUDED
#define CONF_TEST_H_INCLUDED
#define CONF_STDIO_USART EDBG_CDC_MODULE
#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING
#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0
#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1
#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2
#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3
#define CONF_STDIO_BAUDRATE 38400
#endif /* CONF_TEST_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_board.h
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/**
* \file
*
* \brief SAM L21 Xplained Pro board configuration.
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
#endif /* CONF_BOARD_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_clocks.h
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/**
* \file
*
* \brief SAM L21 Clock configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 0
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_LOW_POWER_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_BACKUP_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC16M configuration - Internal 16MHz oscillator */
# define CONF_CLOCK_OSC16M_FREQ_SEL SYSTEM_OSC16M_4M
# define CONF_CLOCK_OSC16M_ON_DEMAND true
# define CONF_CLOCK_OSC16M_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND true
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE false
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE false
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND false
# define CONF_CLOCK_DFLL_RUN_IN_STANDBY false
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR (48000000 / 32768)
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND true
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_PRESCALER SYSTEM_CLOCK_SOURCE_DPLL_DIV_1
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE false
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_XOSC32K
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
/* Configure GCLK generator 2 */
# define CONF_CLOCK_GCLK_2_ENABLE false
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_2_PRESCALER 1
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC16M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

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/**
* \file
*
* \brief SAM L21 Direct Memory Access Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_DMA_H_INCLUDED
#define CONF_DMA_H_INCLUDED
# define CONF_MAX_USED_CHANNEL_NUM 1
#endif

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_extint.h
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/**
* \file
*
* \brief SAM L21 External Interrupt Driver Configuration Header
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_EXTINT_H_INCLUDED
#define CONF_EXTINT_H_INCLUDED
# define EXTINT_CLOCK_SELECTION EXTINT_CLK_GCLK
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
#endif

56
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_spi.h
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/**
* \file
*
* \brief SAM L21 SPI configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_SPI_H_INCLUDED
# define CONF_SPI_H_INCLUDED
# define CONF_SPI_MASTER_ENABLE true
# define CONF_SPI_SLAVE_ENABLE false
# define CONF_SPI_TIMEOUT 10000
#endif /* CONF_SPI_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAML21/conf_test.h
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/**
* \file
*
* \brief SAM L21 Xplained Pro test configuration.
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_TEST_H_INCLUDED
#define CONF_TEST_H_INCLUDED
#define CONF_STDIO_USART EDBG_CDC_MODULE
#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING
#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0
#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1
#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2
#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3
#define CONF_STDIO_BAUDRATE 38400
#endif /* CONF_TEST_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_board.h
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/**
* \file
*
* \brief SAM R21 Xplained Pro board configuration.
*
* Copyright (c) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_BOARD_H_INCLUDED
#define CONF_BOARD_H_INCLUDED
#endif /* CONF_BOARD_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_clocks.h
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/**
* \file
*
* \brief SAM R21 Clock configuration
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <clock.h>
#ifndef CONF_CLOCKS_H_INCLUDED
# define CONF_CLOCKS_H_INCLUDED
/* System clock bus configuration */
# define CONF_CLOCK_CPU_CLOCK_FAILURE_DETECT false
# define CONF_CLOCK_FLASH_WAIT_STATES 0
# define CONF_CLOCK_CPU_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBA_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBB_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
# define CONF_CLOCK_APBC_DIVIDER SYSTEM_MAIN_CLOCK_DIV_1
/* SYSTEM_CLOCK_SOURCE_OSC8M configuration - Internal 8MHz oscillator */
# define CONF_CLOCK_OSC8M_PRESCALER SYSTEM_OSC8M_DIV_1
# define CONF_CLOCK_OSC8M_ON_DEMAND true
# define CONF_CLOCK_OSC8M_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC configuration - External clock/oscillator */
# define CONF_CLOCK_XOSC_ENABLE false
# define CONF_CLOCK_XOSC_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC_EXTERNAL_FREQUENCY 12000000UL
# define CONF_CLOCK_XOSC_STARTUP_TIME SYSTEM_XOSC_STARTUP_32768
# define CONF_CLOCK_XOSC_AUTO_GAIN_CONTROL true
# define CONF_CLOCK_XOSC_ON_DEMAND true
# define CONF_CLOCK_XOSC_RUN_IN_STANDBY false
/* SYSTEM_CLOCK_SOURCE_XOSC32K configuration - External 32KHz crystal/clock oscillator */
# define CONF_CLOCK_XOSC32K_ENABLE false
# define CONF_CLOCK_XOSC32K_EXTERNAL_CRYSTAL SYSTEM_CLOCK_EXTERNAL_CRYSTAL
# define CONF_CLOCK_XOSC32K_STARTUP_TIME SYSTEM_XOSC32K_STARTUP_65536
# define CONF_CLOCK_XOSC32K_AUTO_AMPLITUDE_CONTROL false
# define CONF_CLOCK_XOSC32K_ENABLE_1KHZ_OUPUT false
# define CONF_CLOCK_XOSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_XOSC32K_ON_DEMAND true
# define CONF_CLOCK_XOSC32K_RUN_IN_STANDBY false
//! [oscillator_settings]
/* SYSTEM_CLOCK_SOURCE_OSC32K configuration - Internal 32KHz oscillator */
# define CONF_CLOCK_OSC32K_ENABLE true
# define CONF_CLOCK_OSC32K_STARTUP_TIME SYSTEM_OSC32K_STARTUP_130
# define CONF_CLOCK_OSC32K_ENABLE_1KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ENABLE_32KHZ_OUTPUT true
# define CONF_CLOCK_OSC32K_ON_DEMAND true
# define CONF_CLOCK_OSC32K_RUN_IN_STANDBY false
//! [oscillator_settings]
/* SYSTEM_CLOCK_SOURCE_DFLL configuration - Digital Frequency Locked Loop */
# define CONF_CLOCK_DFLL_ENABLE false
# define CONF_CLOCK_DFLL_LOOP_MODE SYSTEM_CLOCK_DFLL_LOOP_MODE_OPEN
# define CONF_CLOCK_DFLL_ON_DEMAND false
/* DFLL open loop mode configuration */
# define CONF_CLOCK_DFLL_FINE_VALUE (0xff / 4)
/* DFLL closed loop mode configuration */
# define CONF_CLOCK_DFLL_SOURCE_GCLK_GENERATOR GCLK_GENERATOR_1
# define CONF_CLOCK_DFLL_MULTIPLY_FACTOR 6
# define CONF_CLOCK_DFLL_QUICK_LOCK true
# define CONF_CLOCK_DFLL_TRACK_AFTER_FINE_LOCK true
# define CONF_CLOCK_DFLL_KEEP_LOCK_ON_WAKEUP true
# define CONF_CLOCK_DFLL_ENABLE_CHILL_CYCLE true
# define CONF_CLOCK_DFLL_MAX_COARSE_STEP_SIZE (0x1f / 4)
# define CONF_CLOCK_DFLL_MAX_FINE_STEP_SIZE (0xff / 4)
/* SYSTEM_CLOCK_SOURCE_DPLL configuration - Digital Phase-Locked Loop */
# define CONF_CLOCK_DPLL_ENABLE false
# define CONF_CLOCK_DPLL_ON_DEMAND true
# define CONF_CLOCK_DPLL_RUN_IN_STANDBY false
# define CONF_CLOCK_DPLL_LOCK_BYPASS false
# define CONF_CLOCK_DPLL_WAKE_UP_FAST false
# define CONF_CLOCK_DPLL_LOW_POWER_ENABLE false
# define CONF_CLOCK_DPLL_LOCK_TIME SYSTEM_CLOCK_SOURCE_DPLL_LOCK_TIME_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_CLOCK SYSTEM_CLOCK_SOURCE_DPLL_REFERENCE_CLOCK_XOSC32K
# define CONF_CLOCK_DPLL_FILTER SYSTEM_CLOCK_SOURCE_DPLL_FILTER_DEFAULT
# define CONF_CLOCK_DPLL_REFERENCE_FREQUENCY 32768
# define CONF_CLOCK_DPLL_REFERENCE_DIVIDER 1
# define CONF_CLOCK_DPLL_OUTPUT_FREQUENCY 48000000
/* DPLL GCLK reference configuration */
# define CONF_CLOCK_DPLL_REFERENCE_GCLK_GENERATOR GCLK_GENERATOR_1
/* DPLL GCLK lock timer configuration */
# define CONF_CLOCK_DPLL_LOCK_GCLK_GENERATOR GCLK_GENERATOR_1
/* Set this to true to configure the GCLK when running clocks_init. If set to
* false, none of the GCLK generators will be configured in clocks_init(). */
# define CONF_CLOCK_CONFIGURE_GCLK true
/* Configure GCLK generator 0 (Main Clock) */
# define CONF_CLOCK_GCLK_0_ENABLE true
# define CONF_CLOCK_GCLK_0_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_0_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_0_PRESCALER 1
# define CONF_CLOCK_GCLK_0_OUTPUT_ENABLE false
/* Configure GCLK generator 1 */
# define CONF_CLOCK_GCLK_1_ENABLE false
# define CONF_CLOCK_GCLK_1_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_1_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_1_PRESCALER 1
# define CONF_CLOCK_GCLK_1_OUTPUT_ENABLE false
//! [gclk_settings]
/* Configure GCLK generator 2 (RTC) */
# define CONF_CLOCK_GCLK_2_ENABLE true
# define CONF_CLOCK_GCLK_2_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_2_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC32K
# define CONF_CLOCK_GCLK_2_PRESCALER 32
# define CONF_CLOCK_GCLK_2_OUTPUT_ENABLE false
//! [gclk_settings]
/* Configure GCLK generator 3 */
# define CONF_CLOCK_GCLK_3_ENABLE false
# define CONF_CLOCK_GCLK_3_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_3_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_3_PRESCALER 1
# define CONF_CLOCK_GCLK_3_OUTPUT_ENABLE false
/* Configure GCLK generator 4 */
# define CONF_CLOCK_GCLK_4_ENABLE false
# define CONF_CLOCK_GCLK_4_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_4_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_4_PRESCALER 1
# define CONF_CLOCK_GCLK_4_OUTPUT_ENABLE false
/* Configure GCLK generator 5 */
# define CONF_CLOCK_GCLK_5_ENABLE false
# define CONF_CLOCK_GCLK_5_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_5_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_5_PRESCALER 1
# define CONF_CLOCK_GCLK_5_OUTPUT_ENABLE false
/* Configure GCLK generator 6 */
# define CONF_CLOCK_GCLK_6_ENABLE false
# define CONF_CLOCK_GCLK_6_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_6_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_6_PRESCALER 1
# define CONF_CLOCK_GCLK_6_OUTPUT_ENABLE false
/* Configure GCLK generator 7 */
# define CONF_CLOCK_GCLK_7_ENABLE false
# define CONF_CLOCK_GCLK_7_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_7_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_7_PRESCALER 1
# define CONF_CLOCK_GCLK_7_OUTPUT_ENABLE false
/* Configure GCLK generator 8 */
# define CONF_CLOCK_GCLK_8_ENABLE false
# define CONF_CLOCK_GCLK_8_RUN_IN_STANDBY false
# define CONF_CLOCK_GCLK_8_CLOCK_SOURCE SYSTEM_CLOCK_SOURCE_OSC8M
# define CONF_CLOCK_GCLK_8_PRESCALER 1
# define CONF_CLOCK_GCLK_8_OUTPUT_ENABLE false
#endif /* CONF_CLOCKS_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_dma.h
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#ifndef CONF_DMA_H_INCLUDED
#define CONF_DMA_H_INCLUDED
# define CONF_MAX_USED_CHANNEL_NUM 1
#endif

6
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_extint.h
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#ifndef CONF_EXTINT_H_INCLUDED
#define CONF_EXTINT_H_INCLUDED
# define EXTINT_CLOCK_SOURCE GCLK_GENERATOR_0
#endif

9
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_spi.h
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#ifndef CONF_SPI_H_INCLUDED
# define CONF_SPI_H_INCLUDED
# define CONF_SPI_MASTER_ENABLE true
# define CONF_SPI_SLAVE_ENABLE false
# define CONF_SPI_TIMEOUT 10000
#endif /* CONF_SPI_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/config/TARGET_SAMR21/conf_test.h
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/**
* \file
*
* \brief SAM R21 Xplained Pro test configuration.
*
* Copyright (c) 2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef CONF_TEST_H_INCLUDED
#define CONF_TEST_H_INCLUDED
#define CONF_STDIO_USART EDBG_CDC_MODULE
#define CONF_STDIO_MUX_SETTING EDBG_CDC_SERCOM_MUX_SETTING
#define CONF_STDIO_PINMUX_PAD0 EDBG_CDC_SERCOM_PINMUX_PAD0
#define CONF_STDIO_PINMUX_PAD1 EDBG_CDC_SERCOM_PINMUX_PAD1
#define CONF_STDIO_PINMUX_PAD2 EDBG_CDC_SERCOM_PINMUX_PAD2
#define CONF_STDIO_PINMUX_PAD3 EDBG_CDC_SERCOM_PINMUX_PAD3
#define CONF_STDIO_BAUDRATE 38400
#endif /* CONF_TEST_H_INCLUDED */

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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "system.h"
#include "dma_api.h"
#include "dma_api_HAL.h"
#include <math.h>
#include "cmsis.h"
#include "pinmap.h"
/**
* \internal
* Structure redefinition, already defined in dma.c.
* Redefining as that definition is not available here
*/
struct _dma_module {
volatile bool _dma_init;
volatile uint32_t allocated_channels;
uint8_t free_channels;
};
extern struct _dma_module _dma_inst;
extern uint8_t g_sys_init;
static struct dma_instance_s dma_channels[CONF_MAX_USED_CHANNEL_NUM];
/**
* \internal
* Get resource index from channel id
*
* @param[in] channelid Valid DMA channel id
* @return index to DMA instance
*/
static uint8_t get_index_from_id(int channelid)
{
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
uint8_t i;
for (i=0; i<CONF_MAX_USED_CHANNEL_NUM; i++) {
if ((dma_channels[i].status & DMA_ALLOCATED)
&& (dma_channels[i].resource.channel_id == channelid)) {
break;
}
}
return i;
}
/**
* \internal
* Handler function for DMA callback
*
* @param[in] resource pointer to the resource
* @return void
*/
static void dma_handler(const struct dma_resource* const resource)
{
MBED_ASSERT(resource);
void (*callback_func)(void);
uint8_t channelid = resource->channel_id;
uint8_t channel_index;
channel_index = get_index_from_id(channelid);
if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
return;
}
callback_func = (void(*)(void))(dma_channels[channel_index].handler);
if (callback_func) {
callback_func();
}
}
/**
* \internal
* Configure a DMA channel for specified resource
*
* @param[in] channel_index index to the resource
* @return void
*/
static void configure_dma_resource(uint8_t channel_index)
{
/* Sanity check arguments */
MBED_ASSERT(channel_index < CONF_MAX_USED_CHANNEL_NUM);
enum status_code ret;
struct dma_resource_config config;
if (dma_channels[channel_index].status & DMA_ALLOCATED) {
return;
}
/* Get default configuration for DMA */
dma_get_config_defaults(&config);
/* Allocate a free channel */
ret = dma_allocate(&dma_channels[channel_index].resource, &config);
if (ret == STATUS_OK) {
dma_channels[channel_index].status = DMA_ALLOCATED;
}
}
/** Setup a DMA descriptor for specified resource
*
* @param[in] channel_index DMA channel id
* @param[in] src source address
* @param[in] src_inc_enable source address auto increment enable flag
* @param[in] desc destination address
* @param[in] desc_inc_enable destination address auto increment enable flag
* @param[in] length length of data to be transferred
* @param[in] beat_size beat size to be set
* @return void
*/
void dma_setup_transfer(uint8_t channelid, uint32_t src, bool src_inc_enable, uint32_t desc, bool desc_inc_enable, uint32_t length, uint8_t beat_size)
{
enum status_code result;
uint8_t channel_index;
struct dma_descriptor_config descriptor_config;
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
MBED_ASSERT(src);
MBED_ASSERT(desc);
channel_index = get_index_from_id(channelid);
dma_descriptor_get_config_defaults(&descriptor_config);
if (beat_size <= 8) {
descriptor_config.beat_size = DMA_BEAT_SIZE_BYTE;
} else if ((beat_size > 8) && (beat_size <= 16)) {
descriptor_config.beat_size = DMA_BEAT_SIZE_HWORD;
} else {
descriptor_config.beat_size = DMA_BEAT_SIZE_WORD;
}
descriptor_config.block_transfer_count = length;
descriptor_config.source_address = src;
descriptor_config.destination_address = desc;
/* Source address auto-increment is enabled by default */
if (!src_inc_enable) {
descriptor_config.src_increment_enable = false;
}
/* Destination address auto-increment is enabled by default */
if (!desc_inc_enable) {
descriptor_config.dst_increment_enable = false;
}
dma_descriptor_create(&dma_channels[channel_index].descriptor, &descriptor_config);
/* Add descriptor to resource */
if (dma_channels[channel_index].resource.descriptor == NULL) {
/* Multiple calls to this function without releasing already allocated channel is not handled now */
result = dma_add_descriptor(&dma_channels[channel_index].resource, &dma_channels[channel_index].descriptor);
if (result != STATUS_OK) {
dma_channels[channel_index].status |= DMA_ERROR;
}
}
}
/** Initialize the DMA
*
* Configures clock for DMAC
*/
void dma_init()
{
int i;
if (g_sys_init == 0) {
system_init();
g_sys_init = 1;
}
if (!_dma_inst._dma_init) {
for (i=0; i<CONF_MAX_USED_CHANNEL_NUM; i++) {
dma_channels[i].status = DMA_NOT_USED;
}
}
/* Do nothing for now. ASF does the clock init when allocating channel */
}
/** Allocates channel for DMA
*
* Allocates channel for DMA with specified capability
* @param[in] capabilities Capability of DMA channel
*/
int dma_channel_allocate(uint32_t capabilities)
{
uint8_t channel_index = 0;
for (channel_index=0; channel_index<CONF_MAX_USED_CHANNEL_NUM; channel_index++) {
if (dma_channels[channel_index].status == DMA_NOT_USED) {
break;
}
}
if (channel_index != CONF_MAX_USED_CHANNEL_NUM) {
configure_dma_resource(channel_index);
if (dma_channels[channel_index].status & DMA_ALLOCATED) {
return dma_channels[channel_index].resource.channel_id;
}
}
/* Couldn't find a channel. */
return DMA_ERROR_OUT_OF_CHANNELS;
}
/** Start DMA transfer
*
* Kick starts transfer in DMA channel with specified channel id
* @param[in] channelid Channel id of DMA channel
* @return zero if success otherwise non zero
*/
bool dma_start_transfer(int channelid)
{
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
uint8_t channel_index;
channel_index = get_index_from_id(channelid);
if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
/* Return invalid value for now */
return false;
}
if (!(dma_channels[channel_index].status & DMA_ALLOCATED)) {
/* DMA not allocated, return invalid value for now */
return false;
}
/* Start DMA transfer */
if (STATUS_OK != dma_start_transfer_job(&dma_channels[channel_index].resource)) {
/* Error in starting DMA transfer */
return false;
}
return true;
}
/** DMA channel busy check
*
* To check whether DMA channel is busy with a job or not
* @param[in] channelid Channel id of DMA channel
* @return non zero if busy otherwise zero
*/
bool dma_busy(int channelid)
{
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
uint8_t channel_index;
channel_index = get_index_from_id(channelid);
if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
/* This channel is not active! return zero for now */
//res = 0;
return 0;
}
return dma_is_busy(&dma_channels[channel_index].resource);
}
/** DMA channel transfer completion check
*
* To check whether DMA channel job is completed or not
* @param[in] channelid Channel id of DMA channel
* @return non zero if busy otherwise zero
*/
bool dma_is_transfer_complete(int channelid)
{
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
uint8_t channel_index;
channel_index = get_index_from_id(channelid);
if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
/* This channel is not active! return zero for now */
// res = 0;
return 0;
}
return (STATUS_OK == dma_get_job_status(&dma_channels[channel_index].resource));
}
/** Registers callback function for DMA
*
* Registers callback function for DMA for specified events
* @param[in] channelid Channel id of DMA channel
* @param[in] handler Callback function pointer
* @param[in] event Events mask
* @return void
*/
void dma_set_handler(int channelid, uint32_t handler, uint32_t event)
{
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
uint8_t channel_index;
channel_index = get_index_from_id(channelid);
if (channel_index >= CONF_MAX_USED_CHANNEL_NUM) {
/* Return for now */
return;
}
dma_channels[channel_index].handler = handler;
if (event & DMA_TRANSFER_ERROR) {
dma_register_callback(&dma_channels[channel_index].resource, (dma_callback_t)dma_handler, DMA_CALLBACK_TRANSFER_ERROR);
}
if (event & DMA_TRANSFER_COMPLETE) {
dma_register_callback(&dma_channels[channel_index].resource, (dma_callback_t)dma_handler, DMA_CALLBACK_TRANSFER_DONE);
}
/* Set interrupt vector if someone have removed it */
NVIC_SetVector(DMAC_IRQn, (uint32_t)DMAC_Handler);
/* Enable interrupt */
NVIC_EnableIRQ(DMAC_IRQn);
}
/** Frees an allocated DMA channel
*
* Frees an already allocated DMA channel with specified channel id
* @param[in] channelid Channel id of DMA channel to be disabled
* @return zero if success
*/
int dma_channel_free(int channelid)
{
/* Sanity check arguments */
MBED_ASSERT(channelid < CONF_MAX_USED_CHANNEL_NUM);
uint8_t channel_index;
channel_index = get_index_from_id(channelid);
if (STATUS_OK == dma_free(&dma_channels[channel_index].resource)) {
dma_channels[channel_index].status = DMA_NOT_USED;
dma_channels[channel_index].resource.descriptor = NULL;
return 0;
} else {
/* Return invalid value for now */
return -1;
}
}

106
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/dma_api_HAL.h
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@ -1,106 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef _DMA_API_HAL_H
#define _DMA_API_HAL_H
#ifdef __cplusplus
extern "C" {
#endif
#include <compiler.h>
#include "dma.h"
enum dma_status_flags {
DMA_NOT_USED = (uint32_t)1,
DMA_ALLOCATED = (DMA_NOT_USED << 1),
DMA_TEMPORARY = (DMA_NOT_USED << 2),
DMA_ERROR = (DMA_NOT_USED << 3),
};
/* No other capabilities supported now */
#define DMA_CAP_NONE 0
#define DMA_ADDRESS_INC_DISABLE 0
#define DMA_ADDRESS_INC_ENABLE 1
#define DMA_TRANSFER_ERROR ((uint32_t)1 << 1)
#define DMA_TRANSFER_COMPLETE ((uint32_t)1 << 2)
#define DMA_EVENT_ALL (DMA_TRANSFER_ERROR | DMA_TRANSFER_COMPLETE)
COMPILER_ALIGNED(16)
struct dma_instance_s {
struct dma_resource resource;
DmacDescriptor descriptor;
uint8_t status;
uint32_t events;
uint32_t handler;
};
/** Setup a DMA descriptor for specified resource
*
* @param[in] channel_index DMA channel id
* @param[in] src source address
* @param[in] src_inc_enable source address auto increment enable flag
* @param[in] desc destination address
* @param[in] desc_inc_enable destination address auto increment enable flag
* @param[in] length length of data to be transferred
* @param[in] beat_size beat size to be set
* @return void
*/
void dma_setup_transfer(uint8_t channelid, uint32_t src, bool src_inc_enable, uint32_t desc, bool desc_inc_enable, uint32_t length, uint8_t beat_size);
/** Start DMA transfer
*
* Kick starts transfer in DMA channel with specified channel id
* @param[in] channelid Channel id of DMA channel
* @return non zero if success otherwise zero
*/
bool dma_start_transfer(int channelid);
/** DMA channel busy check
*
* To check whether DMA channel is busy with a job or not
* @param[in] channelid Channel id of DMA channel
* @return non zero if busy otherwise zero
*/
bool dma_busy(int channelid);
/** DMA channel transfer completion check
*
* To check whether DMA channel job is completed or not
* @param[in] channelid Channel id of DMA channel
* @return non zero if busy otherwise zero
*/
bool dma_is_transfer_complete(int channelid);
/** Registers callback function for DMA
*
* Registers callback function for DMA for specified events
* @param[in] channelid Channel id of DMA channel
* @param[in] handler Callback function pointer
* @param[in] event Events mask
* @return void
*/
void dma_set_handler(int channelid, uint32_t handler, uint32_t event);
#ifdef __cplusplus
}
#endif
#endif /* _DMA_API_HAL_H */

704
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc.c
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@ -1,704 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Analog-to-Digital Converter Driver
*
* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "adc.h"
#if SAMD20
/* The Die revision D number */
#define REVISON_D_NUM 3
#endif
/**
* \brief Initializes an ADC configuration structure to defaults
*
* Initializes a given ADC configuration struct to a set of known default
* values. This function should be called on any new instance of the
* configuration struct before being modified by the user application.
*
* The default configuration is as follows:
* \li GCLK generator 0 (GCLK main) clock source
* \li 1V from internal bandgap reference
* \li Div 4 clock prescaler
* \li 12-bit resolution
* \li Window monitor disabled
* \li No gain
* \li Positive input on ADC PIN 0
* \li Negative input on ADC PIN 1
* \li Averaging disabled
* \li Oversampling disabled
* \li Right adjust data
* \li Single-ended mode
* \li Free running disabled
* \li All events (input and generation) disabled
* \li Sleep operation disabled
* \li No reference compensation
* \li No gain/offset correction
* \li No added sampling time
* \li Pin scan mode disabled
*
* \param[out] config Pointer to configuration struct to initialize to
* default values
*/
void adc_get_config_defaults(struct adc_config *const config)
{
Assert(config);
config->clock_source = GCLK_GENERATOR_0;
config->reference = ADC_REFERENCE_INT1V;
config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4;
config->resolution = ADC_RESOLUTION_12BIT;
config->window.window_mode = ADC_WINDOW_MODE_DISABLE;
config->window.window_upper_value = 0;
config->window.window_lower_value = 0;
config->gain_factor = ADC_GAIN_FACTOR_1X;
#if SAMR21
config->positive_input = ADC_POSITIVE_INPUT_PIN6 ;
#else
config->positive_input = ADC_POSITIVE_INPUT_PIN0 ;
#endif
config->negative_input = ADC_NEGATIVE_INPUT_GND ;
config->accumulate_samples = ADC_ACCUMULATE_DISABLE;
config->divide_result = ADC_DIVIDE_RESULT_DISABLE;
config->left_adjust = false;
config->differential_mode = false;
config->freerunning = false;
config->event_action = ADC_EVENT_ACTION_DISABLED;
config->run_in_standby = false;
config->reference_compensation_enable = false;
config->correction.correction_enable = false;
config->correction.gain_correction = ADC_GAINCORR_RESETVALUE;
config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE;
config->sample_length = 0;
config->pin_scan.offset_start_scan = 0;
config->pin_scan.inputs_to_scan = 0;
}
/**
* \brief Sets the ADC window mode
*
* Sets the ADC window mode to a given mode and value range.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] window_mode Window monitor mode to set
* \param[in] window_lower_value Lower window monitor threshold value
* \param[in] window_upper_value Upper window monitor threshold value
*/
void adc_set_window_mode(
struct adc_module *const module_inst,
const enum adc_window_mode window_mode,
const int16_t window_lower_value,
const int16_t window_upper_value)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set window mode */
adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set lower window monitor threshold value */
adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set upper window monitor threshold value */
adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
}
/**
* \internal Configure MUX settings for the analog pins
*
* This function will set the given ADC input pins
* to the analog function in the pinmux, giving
* the ADC access to the analog signal
*
* \param [in] pin AINxx pin to configure
*/
static inline void _adc_configure_ain_pin(uint32_t pin)
{
#define PIN_INVALID_ADC_AIN 0xFFFFUL
/* Pinmapping table for AINxx -> GPIO pin number */
const uint32_t pinmapping[] = {
#if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif SAMR21E
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif SAMR21G
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10C) || (SAMD11C)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DS) || (SAMD11DS)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DM) || (SAMD11DM)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#else
# error ADC pin mappings are not defined for this device.
#endif
};
uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
if (pin <= ADC_EXTCHANNEL_MSB) {
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
struct system_pinmux_config config;
system_pinmux_get_config_defaults(&config);
/* Analog functions are all on MUX setting B */
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
config.mux_position = 1;
system_pinmux_pin_set_config(pin_map_result, &config);
}
}
/**
* \internal Writes an ADC configuration to the hardware module
*
* Writes out a given ADC module configuration to the hardware module.
*
* \param[out] module_inst Pointer to the ADC software instance struct
* \param[in] config Pointer to configuration struct
*
* \return Status of the configuration procedure
* \retval STATUS_OK The configuration was successful
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
*/
static enum status_code _adc_set_config(
struct adc_module *const module_inst,
struct adc_config *const config)
{
uint8_t adjres = 0;
uint32_t resolution = ADC_RESOLUTION_16BIT;
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
#if SAMD20
uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos);
#endif
/* Get the hardware module pointer */
Adc *const adc_module = module_inst->hw;
/* Configure GCLK channel and enable clock */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = config->clock_source;
system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
system_gclk_chan_enable(ADC_GCLK_ID);
/* Setup pinmuxing for analog inputs */
if (config->pin_scan.inputs_to_scan != 0) {
uint8_t offset = config->pin_scan.offset_start_scan;
uint8_t start_pin =
offset +(uint8_t)config->positive_input;
uint8_t end_pin =
start_pin + config->pin_scan.inputs_to_scan;
while (start_pin < end_pin) {
_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
start_pin++;
offset++;
}
_adc_configure_ain_pin(config->negative_input);
} else {
_adc_configure_ain_pin(config->positive_input);
_adc_configure_ain_pin(config->negative_input);
}
/* Configure run in standby */
adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
/* Configure reference */
adc_module->REFCTRL.reg =
(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
(config->reference);
/* Set adjusting result and number of samples */
switch (config->resolution) {
case ADC_RESOLUTION_CUSTOM:
adjres = config->divide_result;
accumulate = config->accumulate_samples;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_13BIT:
/* Increase resolution by 1 bit */
adjres = ADC_DIVIDE_RESULT_2;
accumulate = ADC_ACCUMULATE_SAMPLES_4;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_14BIT:
/* Increase resolution by 2 bit */
adjres = ADC_DIVIDE_RESULT_4;
accumulate = ADC_ACCUMULATE_SAMPLES_16;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
#if SAMD20
/* See $35.1.8 for ADC errata of SAM D20.
The revisions before D have this issue.*/
case ADC_RESOLUTION_15BIT:
/* Increase resolution by 3 bit */
if(revision_num < REVISON_D_NUM) {
adjres = ADC_DIVIDE_RESULT_8;
} else {
adjres = ADC_DIVIDE_RESULT_2;
}
accumulate = ADC_ACCUMULATE_SAMPLES_64;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_16BIT:
if(revision_num < REVISON_D_NUM) {
/* Increase resolution by 4 bit */
adjres = ADC_DIVIDE_RESULT_16;
} else {
adjres = ADC_DIVIDE_RESULT_DISABLE;
}
accumulate = ADC_ACCUMULATE_SAMPLES_256;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
#else
case ADC_RESOLUTION_15BIT:
/* Increase resolution by 3 bit */
adjres = ADC_DIVIDE_RESULT_2;
accumulate = ADC_ACCUMULATE_SAMPLES_64;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_16BIT:
/* Increase resolution by 4 bit */
adjres = ADC_DIVIDE_RESULT_DISABLE;
accumulate = ADC_ACCUMULATE_SAMPLES_256;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
#endif
case ADC_RESOLUTION_8BIT:
/* 8-bit result register */
resolution = ADC_RESOLUTION_8BIT;
break;
case ADC_RESOLUTION_10BIT:
/* 10-bit result register */
resolution = ADC_RESOLUTION_10BIT;
break;
case ADC_RESOLUTION_12BIT:
/* 12-bit result register */
resolution = ADC_RESOLUTION_12BIT;
break;
default:
/* Unknown. Abort. */
return STATUS_ERR_INVALID_ARG;
}
adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
/* Check validity of sample length value */
if (config->sample_length > 63) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Configure sample length */
adc_module->SAMPCTRL.reg =
(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure CTRLB */
adc_module->CTRLB.reg =
config->clock_prescaler |
resolution |
(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
/* Check validity of window thresholds */
if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
switch (resolution) {
case ADC_RESOLUTION_8BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 127 ||
config->window.window_lower_value < -128 ||
config->window.window_upper_value > 127 ||
config->window.window_upper_value < -128)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 255 ||
config->window.window_upper_value > 255) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_10BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 511 ||
config->window.window_lower_value < -512 ||
config->window.window_upper_value > 511 ||
config->window.window_upper_value < -512)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 1023 ||
config->window.window_upper_value > 1023) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_12BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 2047 ||
config->window.window_lower_value < -2048 ||
config->window.window_upper_value > 2047 ||
config->window.window_upper_value < -2048)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 4095 ||
config->window.window_upper_value > 4095) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_16BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 32767 ||
config->window.window_lower_value < -32768 ||
config->window.window_upper_value > 32767 ||
config->window.window_upper_value < -32768)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 65535 ||
config->window.window_upper_value > 65535) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
}
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure window mode */
adc_module->WINCTRL.reg = config->window.window_mode;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure lower threshold */
adc_module->WINLT.reg =
config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure lower threshold */
adc_module->WINUT.reg = config->window.window_upper_value <<
ADC_WINUT_WINUT_Pos;
uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
if (inputs_to_scan > 0) {
/*
* Number of input sources included is the value written to INPUTSCAN
* plus 1.
*/
inputs_to_scan--;
}
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
/* Invalid number of input pins or input offset */
return STATUS_ERR_INVALID_ARG;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure pin scan mode and positive and negative input pins */
adc_module->INPUTCTRL.reg =
config->gain_factor |
(config->pin_scan.offset_start_scan <<
ADC_INPUTCTRL_INPUTOFFSET_Pos) |
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
config->negative_input |
config->positive_input;
/* Configure events */
adc_module->EVCTRL.reg = config->event_action;
/* Disable all interrupts */
adc_module->INTENCLR.reg =
(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
if (config->correction.correction_enable) {
/* Make sure gain_correction value is valid */
if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Set gain correction value */
adc_module->GAINCORR.reg = config->correction.gain_correction <<
ADC_GAINCORR_GAINCORR_Pos;
}
/* Make sure offset correction value is valid */
if (config->correction.offset_correction > 2047 ||
config->correction.offset_correction < -2048) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Set offset correction value */
adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
ADC_OFFSETCORR_OFFSETCORR_Pos;
}
}
/* Load in the fixed device ADC calibration constants */
adc_module->CALIB.reg =
ADC_CALIB_BIAS_CAL(
(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
) |
ADC_CALIB_LINEARITY_CAL(
(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
);
return STATUS_OK;
}
/**
* \brief Initializes the ADC channel sequence
*
* Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one
* automatically after a conversion done, causing the next conversion
* to be done with the positive input equal to MUXPOS + INPUTOFFSET,
* it is scanning continuously one by one even ADC channels are not continuous.
*
* Initializes the ADC channel sequence by the sequence of pin_array.
*
* \param[in] pin_array The array of the Mux selection for the positive ADC input
* \param[in] size The size of pin_array
*/
void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
{
for (int i = 0; i < size; i++) {
_adc_configure_ain_pin(pin_array[i]);
}
}
/**
* \brief Initializes the ADC
*
* Initializes the ADC device struct and the hardware module based on the
* given configuration struct values.
*
* \param[out] module_inst Pointer to the ADC software instance struct
* \param[in] hw Pointer to the ADC module instance
* \param[in] config Pointer to the configuration struct
*
* \return Status of the initialization procedure.
* \retval STATUS_OK The initialization was successful
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
* \retval STATUS_BUSY The module is busy with a reset operation
* \retval STATUS_ERR_DENIED The module is enabled
*/
enum status_code adc_init(
struct adc_module *const module_inst,
Adc *hw,
struct adc_config *config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(hw);
Assert(config);
/* Associate the software module instance with the hardware module */
module_inst->hw = hw;
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
/* We are in the middle of a reset. Abort. */
return STATUS_BUSY;
}
if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
/* Module must be disabled before initialization. Abort. */
return STATUS_ERR_DENIED;
}
/* Store the selected reference for later use */
module_inst->reference = config->reference;
/* Make sure bandgap is enabled if requested by the config */
if (module_inst->reference == ADC_REFERENCE_INT1V) {
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
}
#if ADC_CALLBACK_MODE == true
for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
module_inst->callback[i] = NULL;
};
module_inst->registered_callback_mask = 0;
module_inst->enabled_callback_mask = 0;
module_inst->remaining_conversions = 0;
module_inst->job_status = STATUS_OK;
_adc_instances[0] = module_inst;
if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
!config->freerunning) {
module_inst->software_trigger = true;
} else {
module_inst->software_trigger = false;
}
#endif
/* Write configuration to module */
return _adc_set_config(module_inst, config);
}

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMD21/adc_feature.h
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@ -1,728 +0,0 @@
/**
* \file
*
* \brief SAM ADC functionality
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef ADC_FEATURE_H_INCLUDED
#define ADC_FEATURE_H_INCLUDED
/**
* \addtogroup asfdoc_sam0_adc_group
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if ADC_CALLBACK_MODE == true
# include <system_interrupt.h>
#if !defined(__DOXYGEN__)
extern struct adc_module *_adc_instances[ADC_INST_NUM];
#endif
/** Forward definition of the device instance. */
struct adc_module;
/** Type of the callback functions. */
typedef void (*adc_callback_t)(struct adc_module *const module);
/**
* \brief ADC Callback enum
*
* Callback types for ADC callback driver.
*
*/
enum adc_callback {
/** Callback for buffer received. */
ADC_CALLBACK_READ_BUFFER,
/** Callback when window is hit. */
ADC_CALLBACK_WINDOW,
/** Callback for error. */
ADC_CALLBACK_ERROR,
# if !defined(__DOXYGEN__)
/** Number of available callbacks. */
ADC_CALLBACK_N,
# endif
};
#endif
/**
* \brief ADC reference voltage enum
*
* Enum for the possible reference voltages for the ADC.
*
*/
enum adc_reference {
/** 1.0V voltage reference. */
ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V,
/** 1/1.48V<SUB>CC</SUB> reference. */
ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V). */
ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
/** External reference A. */
ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
/** External reference B. */
ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
};
/**
* \brief ADC clock prescaler enum
*
* Enum for the possible clock prescaler values for the ADC.
*
*/
enum adc_clock_prescaler {
/** ADC clock division factor 4. */
ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
/** ADC clock division factor 8. */
ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
/** ADC clock division factor 16. */
ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
/** ADC clock division factor 32. */
ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
/** ADC clock division factor 64. */
ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
/** ADC clock division factor 128. */
ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
/** ADC clock division factor 256. */
ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
/** ADC clock division factor 512. */
ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
};
/**
* \brief ADC resolution enum
*
* Enum for the possible resolution values for the ADC.
*
*/
enum adc_resolution {
/** ADC 12-bit resolution. */
ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
/** ADC 16-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
/** ADC 10-bit resolution. */
ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
/** ADC 8-bit resolution. */
ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT,
/** ADC 13-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_13BIT,
/** ADC 14-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_14BIT,
/** ADC 15-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_15BIT,
/** ADC 16-bit result register for use with averaging. When using this mode
* the ADC result register will be set to 16-bit wide, and the number of
* samples to accumulate and the division factor is configured by the
* \ref adc_config.accumulate_samples and \ref adc_config.divide_result
* members in the configuration struct.
*/
ADC_RESOLUTION_CUSTOM,
};
/**
* \brief ADC window monitor mode enum
*
* Enum for the possible window monitor modes for the ADC.
*
*/
enum adc_window_mode {
/** No window mode. */
ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE,
/** RESULT > WINLT. */
ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1,
/** RESULT < WINUT. */
ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2,
/** WINLT < RESULT < WINUT. */
ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3,
/** !(WINLT < RESULT < WINUT). */
ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
};
/**
* \brief ADC gain factor selection enum
*
* Enum for the possible gain factor values for the ADC.
*
*/
enum adc_gain_factor {
/** 1x gain. */
ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X,
/** 2x gain. */
ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X,
/** 4x gain. */
ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X,
/** 8x gain. */
ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X,
/** 16x gain. */
ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X,
/** 1/2x gain. */
ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
};
/**
* \brief ADC event action enum
*
* Enum for the possible actions to take on an incoming event.
*
*/
enum adc_event_action {
/** Event action disabled. */
ADC_EVENT_ACTION_DISABLED = 0,
/** Flush ADC and start conversion. */
ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
/** Start conversion. */
ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
};
/**
* \brief ADC positive MUX input selection enum
*
* Enum for the possible positive MUX input selections for the ADC.
*
*/
enum adc_positive_input {
/** ADC0 pin. */
ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0,
/** ADC1 pin. */
ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1,
/** ADC2 pin. */
ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2,
/** ADC3 pin. */
ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3,
/** ADC4 pin. */
ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4,
/** ADC5 pin. */
ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5,
/** ADC6 pin. */
ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6,
/** ADC7 pin. */
ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7,
/** ADC8 pin. */
ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8,
/** ADC9 pin. */
ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9,
/** ADC10 pin. */
ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10,
/** ADC11 pin. */
ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11,
/** ADC12 pin. */
ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12,
/** ADC13 pin. */
ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13,
/** ADC14 pin. */
ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14,
/** ADC15 pin. */
ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15,
/** ADC16 pin. */
ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16,
/** ADC17 pin. */
ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17,
/** ADC18 pin. */
ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18,
/** ADC19 pin. */
ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19,
/** Temperature reference. */
ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
/** Bandgap voltage. */
ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
/** 1/4 scaled core supply. */
ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
/** 1/4 scaled I/O supply. */
ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
/** DAC input. */
ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
};
/**
* \brief ADC negative MUX input selection enum
*
* Enum for the possible negative MUX input selections for the ADC.
*
*/
enum adc_negative_input {
/** ADC0 pin. */
ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0,
/** ADC1 pin. */
ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1,
/** ADC2 pin. */
ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2,
/** ADC3 pin. */
ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3,
/** ADC4 pin. */
ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4,
/** ADC5 pin. */
ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5,
/** ADC6 pin. */
ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6,
/** ADC7 pin. */
ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7,
/** Internal ground. */
ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND,
/** I/O ground. */
ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND,
};
/**
* \brief ADC number of accumulated samples enum
*
* Enum for the possible numbers of ADC samples to accumulate.
* This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
* resolution setting is used.
*
*/
enum adc_accumulate_samples {
/** No averaging. */
ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
/** Average 2 samples. */
ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
/** Average 4 samples. */
ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
/** Average 8 samples. */
ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
/** Average 16 samples. */
ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
/** Average 32 samples. */
ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
/** Average 64 samples. */
ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
/** Average 128 samples. */
ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
/** Average 256 samples. */
ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
/** Average 512 samples. */
ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
/** Average 1024 samples. */
ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
};
/**
* \brief ADC possible dividers for the result register
*
* Enum for the possible division factors to use when accumulating
* multiple samples. To keep the same resolution for the averaged
* result and the actual input value, the division factor must
* be equal to the number of samples accumulated. This setting is only
* used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
*/
enum adc_divide_result {
/** Don't divide result register after accumulation. */
ADC_DIVIDE_RESULT_DISABLE = 0,
/** Divide result register by 2 after accumulation. */
ADC_DIVIDE_RESULT_2 = 1,
/** Divide result register by 4 after accumulation. */
ADC_DIVIDE_RESULT_4 = 2,
/** Divide result register by 8 after accumulation. */
ADC_DIVIDE_RESULT_8 = 3,
/** Divide result register by 16 after accumulation. */
ADC_DIVIDE_RESULT_16 = 4,
/** Divide result register by 32 after accumulation. */
ADC_DIVIDE_RESULT_32 = 5,
/** Divide result register by 64 after accumulation. */
ADC_DIVIDE_RESULT_64 = 6,
/** Divide result register by 128 after accumulation. */
ADC_DIVIDE_RESULT_128 = 7,
};
#if ADC_CALLBACK_MODE == true
/**
* Enum for the possible ADC interrupt flags.
*/
enum adc_interrupt_flag {
/** ADC result ready. */
ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
/** Window monitor match. */
ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
/** ADC result overwritten before read. */
ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
};
#endif
/**
* \brief ADC oversampling and decimation enum
*
* Enum for the possible numbers of bits resolution can be increased by when
* using oversampling and decimation.
*
*/
enum adc_oversampling_and_decimation {
/** Don't use oversampling and decimation mode. */
ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
/** 1 bit resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
/** 2 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
/** 3 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
/** 4 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_4BIT
};
/**
* \brief Window monitor configuration structure
*
* Window monitor configuration structure.
*/
struct adc_window_config {
/** Selected window mode. */
enum adc_window_mode window_mode;
/** Lower window value. */
int32_t window_lower_value;
/** Upper window value. */
int32_t window_upper_value;
};
/**
* \brief ADC event enable/disable structure.
*
* Event flags for the ADC module. This is used to enable and
* disable events via \ref adc_enable_events() and \ref adc_disable_events().
*/
struct adc_events {
/** Enable event generation on conversion done. */
bool generate_event_on_conversion_done;
/** Enable event generation on window monitor. */
bool generate_event_on_window_monitor;
};
/**
* \brief Gain and offset correction configuration structure
*
* Gain and offset correction configuration structure.
* Part of the \ref adc_config struct and will be initialized by
* \ref adc_get_config_defaults.
*/
struct adc_correction_config {
/**
* Enables correction for gain and offset based on values of gain_correction and
* offset_correction if set to true.
*/
bool correction_enable;
/**
* This value defines how the ADC conversion result is compensated for gain
* error before written to the result register. This is a fractional value,
* 1-bit integer plus an 11-bit fraction, therefore
* 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
* \c 0b010000000000 to \c 0b111111111111.
*/
uint16_t gain_correction;
/**
* This value defines how the ADC conversion result is compensated for
* offset error before written to the result register. This is a 12-bit
* value in two's complement format.
*/
int16_t offset_correction;
};
/**
* \brief Pin scan configuration structure
*
* Pin scan configuration structure. Part of the \ref adc_config struct and will
* be initialized by \ref adc_get_config_defaults.
*/
struct adc_pin_scan_config {
/**
* Offset (relative to selected positive input) of the first input pin to be
* used in pin scan mode.
*/
uint8_t offset_start_scan;
/**
* Number of input pins to scan in pin scan mode. A value below two will
* disable pin scan mode.
*/
uint8_t inputs_to_scan;
};
/**
* \brief ADC configuration structure
*
* Configuration structure for an ADC instance. This structure should be
* initialized by the \ref adc_get_config_defaults()
* function before being modified by the user application.
*/
struct adc_config {
/** GCLK generator used to clock the peripheral. */
enum gclk_generator clock_source;
/** Voltage reference. */
enum adc_reference reference;
/** Clock prescaler. */
enum adc_clock_prescaler clock_prescaler;
/** Result resolution. */
enum adc_resolution resolution;
/** Gain factor. */
enum adc_gain_factor gain_factor;
/** Positive MUX input. */
enum adc_positive_input positive_input;
/** Negative MUX input. For singled-ended conversion mode, the negative
* input must be connected to ground. This ground could be the internal
* GND, IOGND or an external ground connected to a pin. */
enum adc_negative_input negative_input;
/** Number of ADC samples to accumulate when using the
* \c ADC_RESOLUTION_CUSTOM mode.Note: if the result width increases,
* result resolution will be changed accordingly.
*/
enum adc_accumulate_samples accumulate_samples;
/** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */
enum adc_divide_result divide_result;
/** Left adjusted result. */
bool left_adjust;
/** Enables differential mode if true.
* if false, ADC will run in singled-ended mode. */
bool differential_mode;
/** Enables free running mode if true. */
bool freerunning;
/** Enables ADC in standby sleep mode if true. */
bool run_in_standby;
/**
* Enables reference buffer offset compensation if true.
* This will increase the accuracy of the gain stage, but decreases the input
* impedance; therefore the startup time of the reference must be increased.
*/
bool reference_compensation_enable;
/**
* This value (0-63) control the ADC sampling time in number of half ADC
* prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
* controlling the ADC input impedance. Sampling time is set according to
* the formula:
* Sample time = (sample_length+1) * (ADCclk / 2).
*/
uint8_t sample_length;
/** Window monitor configuration structure. */
struct adc_window_config window;
/** Gain and offset correction configuration structure. */
struct adc_correction_config correction;
/** Event action to take on incoming event. */
enum adc_event_action event_action;
/** Pin scan configuration structure. */
struct adc_pin_scan_config pin_scan;
};
/**
* \brief ADC software device instance structure.
*
* ADC software instance structure, used to retain software state information
* of an associated hardware module instance.
*
* \note The fields of this structure should not be altered by the user
* application; they are reserved for module-internal use only.
*/
struct adc_module {
#if !defined(__DOXYGEN__)
/** Pointer to ADC hardware module. */
Adc *hw;
/** Keep reference configuration so we know when enable is called. */
enum adc_reference reference;
# if ADC_CALLBACK_MODE == true
/** Array to store callback functions. */
adc_callback_t callback[ADC_CALLBACK_N];
/** Pointer to buffer used for ADC results. */
volatile uint16_t *job_buffer;
/** Remaining number of conversions in current job. */
volatile uint16_t remaining_conversions;
/** Bit mask for callbacks registered. */
uint8_t registered_callback_mask;
/** Bit mask for callbacks enabled. */
uint8_t enabled_callback_mask;
/** Holds the status of the ongoing or last conversion job. */
volatile enum status_code job_status;
/** If software triggering is needed. */
bool software_trigger;
# endif
#endif
};
#if !defined(__DOXYGEN__)
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus. This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \param[in] module_inst Pointer to the ADC software instance struct
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true if the module synchronization is ongoing
* \retval false if the module has completed synchronization
*/
static inline bool adc_is_syncing(
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
return true;
}
return false;
}
#endif
/**
* \name ADC Gain and Pin Scan Mode
* @{
*/
/**
* \brief Sets ADC gain factor
*
* Sets the ADC gain factor to a specified gain setting.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] gain_factor Gain factor value to set
*/
static inline void adc_set_gain(
struct adc_module *const module_inst,
const enum adc_gain_factor gain_factor)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set new gain factor */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
(gain_factor);
}
/**
* \brief Sets the ADC pin scan mode
*
* Configures the pin scan mode of the ADC module. In pin scan mode, the first
* conversion will start at the configured positive input + start_offset. When
* a conversion is done, a conversion will start on the next input, until
* \c inputs_to_scan number of conversions are made.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] inputs_to_scan Number of input pins to perform a conversion on
* (must be two or more)
* \param[in] start_offset Offset of first pin to scan (relative to
* configured positive input)
*
* \return Status of the pin scan configuration set request.
*
* \retval STATUS_OK Pin scan mode has been set successfully
* \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has
* an invalid value
*/
static inline enum status_code adc_set_pin_scan_mode(
struct adc_module *const module_inst,
uint8_t inputs_to_scan,
const uint8_t start_offset)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
if (inputs_to_scan > 0) {
/*
* Number of input sources included is the value written to INPUTSCAN
* plus 1.
*/
inputs_to_scan--;
}
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
/* Invalid number of input pins */
return STATUS_ERR_INVALID_ARG;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set pin scan mode */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg &
~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
(start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
return STATUS_OK;
}
/**
* \brief Disables pin scan mode
*
* Disables pin scan mode. The next conversion will be made on only one pin
* (the configured positive input pin).
*
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline void adc_disable_pin_scan_mode(
struct adc_module *const module_inst)
{
/* Disable pin scan mode */
adc_set_pin_scan_mode(module_inst, 0, 0);
}
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* ADC_FEATURE_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc.c
View File

@ -1,769 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Analog-to-Digital Converter Driver
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "adc.h"
#if (ADC_INST_NUM > 1) || (SAMC20)
# define _ADC_GCLK_ID(n,unused) TPASTE3(ADC,n,_GCLK_ID),
# define _ADC_APBCMASK(n,unused) TPASTE2(MCLK_APBCMASK_ADC,n),
# define _ADC_FUSES_BIASCOMP_ADDR(n,unused) TPASTE3(ADC,n,_FUSES_BIASCOMP_ADDR),
# define _ADC_FUSES_BIASCOMP_Pos(n,unused) TPASTE3(ADC,n,_FUSES_BIASCOMP_Pos),
# define _ADC_FUSES_BIASREFBUF_ADDR(n,unused) TPASTE3(ADC,n,_FUSES_BIASREFBUF_ADDR),
# define _ADC_FUSES_BIASREFBUF_Pos(n,unused) TPASTE3(ADC,n,_FUSES_BIASREFBUF_Pos),
# define _ADC_EXTCHANNEL_MSB(n,unused) TPASTE3(ADC,n,_EXTCHANNEL_MSB),
# define ADC_GCLK_ID MREPEAT(ADC_INST_NUM, _ADC_GCLK_ID, 0)
# define ADC_APBCMASKS MREPEAT(ADC_INST_NUM, _ADC_APBCMASK, 0)
# define ADC_FUSES_BIASCOMP_ADDR MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_ADDR, 0)
# define ADC_FUSES_BIASCOMP_Pos MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASCOMP_Pos, 0)
# define ADC_FUSES_BIASREFBUF_ADDR MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_ADDR, 0)
# define ADC_FUSES_BIASREFBUF_Pos MREPEAT(ADC_INST_NUM, _ADC_FUSES_BIASREFBUF_Pos, 0)
# define ADC_EXTCHANNEL_MSB MREPEAT(ADC_INST_NUM, _ADC_EXTCHANNEL_MSB, 0)
#endif
/* List of ADC GCLK IDs */
const uint8_t _adc_gclk_ids[ADC_INST_NUM] = { ADC_GCLK_ID };
/* List of ADC APB Masks */
#if (SAML21)
const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { MCLK_APBDMASK_ADC };
#else
const uint32_t _adc_apbcmasks[ADC_INST_NUM] = { ADC_APBCMASKS };
#endif
/* List of Number of external channels of ADC modules. */
const uint32_t _adc_extchannel_msb[ADC_INST_NUM] = { ADC_EXTCHANNEL_MSB };
/* List of address of comparator scaling of ADC modules. */
const uint32_t _adc_biascomp_addr[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_ADDR };
/* List of address of bias reference buffer scaling of ADC modules. */
const uint32_t _adc_biasrefbuf_addr[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_ADDR };
/* List of offset of comparator scaling of ADC modules. */
const uint8_t _adc_biascomp_pos[ADC_INST_NUM] = { ADC_FUSES_BIASCOMP_Pos };
/* List of offset of bias reference buffer scaling of ADC modules. */
const uint8_t _adc_biasrefbuf_pos[ADC_INST_NUM] = { ADC_FUSES_BIASREFBUF_Pos };
/**
* \internal Find the index of given ADC module instance.
*
* \param[in] ADC module instance pointer.
*
* \return Index of the given ADC module instance.
*/
uint8_t _adc_get_inst_index(
Adc *const hw)
{
/* List of available ADC modules. */
Adc *const adc_modules[ADC_INST_NUM] = ADC_INSTS;
/* Find index for ADC instance. */
for (uint32_t i = 0; i < ADC_INST_NUM; i++) {
if (hw == adc_modules[i]) {
return i;
}
}
/* Invalid data given. */
Assert(false);
return 0;
}
/**
* \brief Initializes an ADC configuration structure to defaults.
*
* Initializes a given ADC configuration struct to a set of known default
* values. This function should be called on any new instance of the
* configuration struct before being modified by the user application.
*
* The default configuration is as follows:
* \li GCLK generator 0 (GCLK main) clock source
* \li Internal bandgap reference
* \li Div 2 clock prescaler
* \li 12-bit resolution
* \li Window monitor disabled
* \li Positive input on ADC PIN 1
* \li Negative input on Internal ground
* \li Averaging disabled
* \li Oversampling disabled
* \li Right adjust data
* \li Single-ended mode
* \li Free running disabled
* \li All events (input and generation) disabled
* \li ADC run in standby disabled
* \li ADC On demand disabled
* \li No sampling time compensation
* \li Disable the positive input sequense
* \li No reference compensation
* \li No gain/offset correction
* \li No added sampling time
*
* \param[out] config Pointer to configuration struct to initialize to
* default values
*/
void adc_get_config_defaults(struct adc_config *const config)
{
Assert(config);
config->clock_source = GCLK_GENERATOR_0;
config->reference = ADC_REFERENCE_INTREF;
config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV2;
config->resolution = ADC_RESOLUTION_12BIT;
config->window.window_mode = ADC_WINDOW_MODE_DISABLE;
config->window.window_upper_value = 0;
config->window.window_lower_value = 0;
config->positive_input = ADC_POSITIVE_INPUT_PIN1;
config->negative_input = ADC_NEGATIVE_INPUT_GND;
config->accumulate_samples = ADC_ACCUMULATE_DISABLE;
config->divide_result = ADC_DIVIDE_RESULT_DISABLE;
config->left_adjust = false;
config->differential_mode = false;
config->freerunning = false;
config->event_action = ADC_EVENT_ACTION_DISABLED;
config->run_in_standby = false;
config->on_demand = false;
config->sampling_time_compensation_enable = false;
config->positive_input_sequence_mask_enable = 0;
config->reference_compensation_enable = false;
config->correction.correction_enable = false;
config->correction.gain_correction = ADC_GAINCORR_RESETVALUE;
config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE;
config->sample_length = 0;
}
/**
* \brief Sets the ADC window mode.
*
* Sets the ADC window mode to a given mode and value range.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] window_mode Window monitor mode to set
* \param[in] window_lower_value Lower window monitor threshold value
* \param[in] window_upper_value Upper window monitor threshold value
*/
void adc_set_window_mode(
struct adc_module *const module_inst,
const enum adc_window_mode window_mode,
const int16_t window_lower_value,
const int16_t window_upper_value)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set window mode */
adc_module->CTRLC.reg = window_mode;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set lower window monitor threshold value */
adc_module->WINLT.reg = window_lower_value;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set upper window monitor threshold value */
adc_module->WINUT.reg = window_upper_value;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
}
/**
* \internal Configure MUX settings for the analog pins.
*
* This function will set the given ADC input pins
* to the analog function in the pin mux, giving
* the ADC access to the analog signal.
*
* \param [in] index Index of the ADC module instance.
* \param [in] pin AINxx pin to configure
*/
static inline void _adc_configure_ain_pin(uint8_t index, uint32_t pin)
{
#define PIN_INVALID_ADC_AIN 0xFFFFUL
/* Pinmapping table for AINxx -> GPIO pin number */
#if (SAML21)
const uint32_t pinmapping[] = {
# if (SAML21E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
# elif (SAML21G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
# elif (SAML21J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
# else
# error ADC pin mappings are not defined for this device.
# endif
};
#elif (SAMC20)
const uint32_t pinmapping[] = {
# if (SAMC20E)
PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5,
PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7,
PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9,
PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
# elif (SAMC20G)
PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1,
PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3,
PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5,
PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7,
PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9,
PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
# elif (SAMC20J)
PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1,
PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3,
PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5,
PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7,
PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9,
PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
# else
# error ADC pin mappings are not defined for this device.
# endif
};
#elif (SAMC21)
const uint32_t *pinmapping = NULL;;
const uint32_t pinmapping0[] = {
# if (SAMC21E)
PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5,
PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7,
PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9,
PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
# elif (SAMC21G)
PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1,
PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3,
PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5,
PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7,
PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9,
PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
# elif (SAMC21J)
PIN_PA02B_ADC0_AIN0, PIN_PA03B_ADC0_AIN1,
PIN_PB08B_ADC0_AIN2, PIN_PB09B_ADC0_AIN3,
PIN_PA04B_ADC0_AIN4, PIN_PA05B_ADC0_AIN5,
PIN_PA06B_ADC0_AIN6, PIN_PA07B_ADC0_AIN7,
PIN_PA08B_ADC0_AIN8, PIN_PA09B_ADC0_AIN9,
PIN_PA10B_ADC0_AIN10, PIN_PA11B_ADC0_AIN11,
# else
# error ADC pin mappings are not defined for this device.
# endif
};
const uint32_t pinmapping1[] = {
# if (SAMC21E)
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
# elif (SAMC21G)
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC1_AIN2, PIN_PB03B_ADC1_AIN3,
PIN_PB08B_ADC1_AIN4, PIN_PB09B_ADC1_AIN5,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
# elif (SAMC21J)
PIN_PB00B_ADC1_AIN0, PIN_PB01B_ADC1_AIN1,
PIN_PB02B_ADC1_AIN2, PIN_PB03B_ADC1_AIN3,
PIN_PB08B_ADC1_AIN4, PIN_PB09B_ADC1_AIN5,
PIN_PB04B_ADC1_AIN6, PIN_PB05B_ADC1_AIN7,
PIN_PB06B_ADC1_AIN8, PIN_PB07B_ADC1_AIN9,
PIN_PA08B_ADC1_AIN10, PIN_PA09B_ADC1_AIN11,
# else
# error ADC pin mappings are not defined for this device.
# endif
};
switch(index) {
case 0:
pinmapping = pinmapping0;
break;
case 1:
pinmapping = pinmapping1;
break;
default:
break;
}
Assert(pinmapping);
#endif
uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
if (pin <= _adc_extchannel_msb[index]) {
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
struct system_pinmux_config config;
system_pinmux_get_config_defaults(&config);
/* Analog functions are all on MUX setting B */
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
config.mux_position = 1;
system_pinmux_pin_set_config(pin_map_result, &config);
}
}
/**
* \internal Writes an ADC configuration to the hardware module.
*
* Writes out a given ADC module configuration to the hardware module.
*
* \param[in] index Index of the ADC module instance
* \param[out] module_inst Pointer to the ADC software instance struct
* \param[in] config Pointer to configuration struct
*
* \return Status of the configuration procedure.
* \retval STATUS_OK The configuration was successful
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
*/
static enum status_code _adc_set_config(
uint8_t index,
struct adc_module *const module_inst,
struct adc_config *const config)
{
uint8_t adjres = 0;
uint32_t resolution = ADC_RESOLUTION_16BIT;
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
/* Get the hardware module pointer */
Adc *const adc_module = module_inst->hw;
/* Configure GCLK channel and enable clock */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = config->clock_source;
system_gclk_chan_set_config(_adc_gclk_ids[index], &gclk_chan_conf);
system_gclk_chan_enable(_adc_gclk_ids[index]);
/* Setup pinmuxing for analog inputs */
_adc_configure_ain_pin(index, config->positive_input);
_adc_configure_ain_pin(index, config->negative_input);
/* Set pinmux for positive input sequence*/
for(uint8_t i=0; i <= _adc_extchannel_msb[index]; i++) {
if(config->positive_input_sequence_mask_enable & (1 << i)) {
_adc_configure_ain_pin(index, i);
}
}
/* Configure run in standby and on demand */
adc_module->CTRLA.reg = ((config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos)
| (config->on_demand << ADC_CTRLA_ONDEMAND_Pos)) ;
/* Configure reference */
adc_module->REFCTRL.reg =
(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos)
| (config->reference);
/* Set adjusting result and number of samples */
switch (config->resolution) {
case ADC_RESOLUTION_CUSTOM:
adjres = config->divide_result;
accumulate = config->accumulate_samples;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_13BIT:
/* Increase resolution by 1 bit */
adjres = ADC_DIVIDE_RESULT_2;
accumulate = ADC_ACCUMULATE_SAMPLES_4;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_14BIT:
/* Increase resolution by 2 bit */
adjres = ADC_DIVIDE_RESULT_4;
accumulate = ADC_ACCUMULATE_SAMPLES_16;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_15BIT:
/* Increase resolution by 3 bit */
adjres = ADC_DIVIDE_RESULT_2;
accumulate = ADC_ACCUMULATE_SAMPLES_64;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_16BIT:
/* Increase resolution by 4 bit */
adjres = ADC_DIVIDE_RESULT_DISABLE;
accumulate = ADC_ACCUMULATE_SAMPLES_256;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_8BIT:
/* 8-bit result register */
resolution = ADC_RESOLUTION_8BIT;
break;
case ADC_RESOLUTION_10BIT:
/* 10-bit result register */
resolution = ADC_RESOLUTION_10BIT;
break;
case ADC_RESOLUTION_12BIT:
/* 12-bit result register */
resolution = ADC_RESOLUTION_12BIT;
break;
default:
/* Unknown. Abort. */
return STATUS_ERR_INVALID_ARG;
}
adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Check validity of sample length value */
if (config->sample_length > 63) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Configure sample length */
adc_module->SAMPCTRL.reg =
(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos)
| (config->sampling_time_compensation_enable << ADC_SAMPCTRL_OFFCOMP_Pos);
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure CTRLB */
adc_module->CTRLB.reg =
config->clock_prescaler;
adc_module->CTRLC.reg =
resolution |
(config->correction.correction_enable << ADC_CTRLC_CORREN_Pos) |
(config->freerunning << ADC_CTRLC_FREERUN_Pos) |
(config->left_adjust << ADC_CTRLC_LEFTADJ_Pos) |
(config->differential_mode << ADC_CTRLC_DIFFMODE_Pos);
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Check validity of window thresholds */
if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
switch (resolution) {
case ADC_RESOLUTION_8BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 127 ||
config->window.window_lower_value < -128 ||
config->window.window_upper_value > 127 ||
config->window.window_upper_value < -128)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 255 ||
config->window.window_upper_value > 255) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_10BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 511 ||
config->window.window_lower_value < -512 ||
config->window.window_upper_value > 511 ||
config->window.window_upper_value < -512)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 1023 ||
config->window.window_upper_value > 1023) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_12BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 2047 ||
config->window.window_lower_value < -2048 ||
config->window.window_upper_value > 2047 ||
config->window.window_upper_value < -2048)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 4095 ||
config->window.window_upper_value > 4095) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_16BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 32767 ||
config->window.window_lower_value < -32768 ||
config->window.window_upper_value > 32767 ||
config->window.window_upper_value < -32768)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 65535 ||
config->window.window_upper_value > 65535) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
}
}
/* Configure window mode */
adc_module->CTRLC.reg |= config->window.window_mode;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure lower threshold */
adc_module->WINLT.reg =
config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure lower threshold */
adc_module->WINUT.reg = config->window.window_upper_value <<
ADC_WINUT_WINUT_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure pin scan mode and positive and negative input pins */
adc_module->INPUTCTRL.reg =
config->negative_input |
config->positive_input;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure events */
adc_module->EVCTRL.reg = config->event_action;
/* Disable all interrupts */
adc_module->INTENCLR.reg =
(1 << ADC_INTENCLR_WINMON_Pos) |(1 << ADC_INTENCLR_OVERRUN_Pos)
| (1 << ADC_INTENCLR_RESRDY_Pos);
if (config->correction.correction_enable) {
/* Make sure gain_correction value is valid */
if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Set gain correction value */
adc_module->GAINCORR.reg = config->correction.gain_correction <<
ADC_GAINCORR_GAINCORR_Pos;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Make sure offset correction value is valid */
if (config->correction.offset_correction > 2047 ||
config->correction.offset_correction < -2048) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Set offset correction value */
adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
ADC_OFFSETCORR_OFFSETCORR_Pos;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
}
/* Load in the fixed device ADC calibration constants */
adc_module->CALIB.reg =
ADC_CALIB_BIASREFBUF(
(*(uint32_t *)_adc_biasrefbuf_addr[index] >> _adc_biasrefbuf_pos[index])
) |
ADC_CALIB_BIASCOMP(
(*(uint32_t *)_adc_biascomp_addr[index] >> _adc_biascomp_pos[index])
);
return STATUS_OK;
}
/**
* \brief Initializes the ADC.
*
* Initializes the ADC device struct and the hardware module based on the
* given configuration struct values.
*
* \param[out] module_inst Pointer to the ADC software instance struct
* \param[in] hw Pointer to the ADC module instance
* \param[in] config Pointer to the configuration struct
*
* \return Status of the initialization procedure.
* \retval STATUS_OK The initialization was successful
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
* \retval STATUS_BUSY The module is busy with a reset operation
* \retval STATUS_ERR_DENIED The module is enabled
*/
enum status_code adc_init(
struct adc_module *const module_inst,
Adc *hw,
struct adc_config *config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(hw);
Assert(config);
/* Temporary variable to hold ADC instance number */
uint8_t instance = _adc_get_inst_index(hw);
/* Associate the software module instance with the hardware module */
module_inst->hw = hw;
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, _adc_apbcmasks[instance]);
if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
/* We are in the middle of a reset. Abort. */
return STATUS_BUSY;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
/* Module must be disabled before initialization. Abort. */
return STATUS_ERR_DENIED;
}
/* Store the selected reference for later use */
module_inst->reference = config->reference;
/* Make sure the voltage reference is enabled if requested by the config */
if (module_inst->reference == ADC_REFERENCE_INTREF) {
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
}
#if ADC_CALLBACK_MODE == true
for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
module_inst->callback[i] = NULL;
};
module_inst->registered_callback_mask = 0;
module_inst->enabled_callback_mask = 0;
module_inst->remaining_conversions = 0;
module_inst->job_status = STATUS_OK;
_adc_instances[instance] = module_inst;
if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
!config->freerunning) {
module_inst->software_trigger = true;
} else {
module_inst->software_trigger = false;
}
#endif
/* Write configuration to module */
return _adc_set_config(instance, module_inst, config);
}

726
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAML21/adc_feature.h
View File

@ -1,726 +0,0 @@
/**
* \file
*
* \brief SAM ADC functionality
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef ADC_FEATURE_H_INCLUDED
#define ADC_FEATURE_H_INCLUDED
/**
* \addtogroup asfdoc_sam0_adc_group
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
/*@{*/
#if (SAMC20) || (SAMC21) || defined(__DOXYGEN__)
/** Output Driver Strength Selection feature support. */
# define FEATURE_ADC_SUPPORT_MASTER_SLAVE
#endif
/*@}*/
#if ADC_CALLBACK_MODE == true
# include <system_interrupt.h>
#if !defined(__DOXYGEN__)
extern struct adc_module *_adc_instances[ADC_INST_NUM];
#endif
/** Forward definition of the device instance. */
struct adc_module;
/** Type of the callback functions. */
typedef void (*adc_callback_t)(struct adc_module *const module);
/**
* \brief ADC callback enum.
*
* Callback types for ADC callback driver.
*
*/
enum adc_callback {
/** Callback for buffer received */
ADC_CALLBACK_READ_BUFFER,
/** Callback when window is hit */
ADC_CALLBACK_WINDOW,
/** Callback for error */
ADC_CALLBACK_ERROR,
# if !defined(__DOXYGEN__)
/** Number of available callbacks */
ADC_CALLBACK_N,
# endif
};
#endif
/**
* \brief ADC reference voltage enum.
*
* Enum for the possible reference voltages for the ADC.
*
*/
enum adc_reference {
/** Internal Bandgap Reference */
ADC_REFERENCE_INTREF = ADC_REFCTRL_REFSEL_INTREF,
/** 1/1.48V<SUB>CC</SUB> reference */
ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V) */
ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
/** External reference A */
ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
#if (SAML21)
/** External reference B. */
ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
#endif
#if (SAMC20) || (SAMC21)
/** DAC. */
ADC_REFERENCE_DAC = ADC_REFCTRL_REFSEL_DAC,
#endif
/** VDDANA. */
ADC_REFERENCE_INTVCC2 = ADC_REFCTRL_REFSEL_INTVCC2,
};
/**
* \brief ADC clock prescaler enum.
*
* Enum for the possible clock prescaler values for the ADC.
*
*/
enum adc_clock_prescaler {
/** ADC clock division factor 2 */
ADC_CLOCK_PRESCALER_DIV2 = ADC_CTRLB_PRESCALER_DIV2,
/** ADC clock division factor 4 */
ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
/** ADC clock division factor 8 */
ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
/** ADC clock division factor 16 */
ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
/** ADC clock division factor 32 */
ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
/** ADC clock division factor 64 */
ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
/** ADC clock division factor 128 */
ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
/** ADC clock division factor 256 */
ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
};
/**
* \brief ADC resolution enum.
*
* Enum for the possible resolution values for the ADC.
*
*/
enum adc_resolution {
/** ADC 12-bit resolution */
ADC_RESOLUTION_12BIT = ADC_CTRLC_RESSEL_12BIT,
/** ADC 16-bit resolution using oversampling and decimation */
ADC_RESOLUTION_16BIT = ADC_CTRLC_RESSEL_16BIT,
/** ADC 10-bit resolution */
ADC_RESOLUTION_10BIT = ADC_CTRLC_RESSEL_10BIT,
/** ADC 8-bit resolution */
ADC_RESOLUTION_8BIT = ADC_CTRLC_RESSEL_8BIT,
/** ADC 13-bit resolution using oversampling and decimation */
ADC_RESOLUTION_13BIT,
/** ADC 14-bit resolution using oversampling and decimation */
ADC_RESOLUTION_14BIT,
/** ADC 15-bit resolution using oversampling and decimation */
ADC_RESOLUTION_15BIT,
/** ADC 16-bit result register for use with averaging. When using this mode
* the ADC result register will be set to 16-bit wide, and the number of
* samples to accumulate and the division factor is configured by the
* \ref adc_config.accumulate_samples and \ref adc_config.divide_result
* members in the configuration struct.
*/
ADC_RESOLUTION_CUSTOM,
};
/**
* \brief ADC window monitor mode enum.
*
* Enum for the possible window monitor modes for the ADC.
*
*/
enum adc_window_mode {
/** No window mode */
ADC_WINDOW_MODE_DISABLE = ADC_CTRLC_WINMODE_DISABLE,
/** RESULT > WINLT */
ADC_WINDOW_MODE_ABOVE_LOWER = ADC_CTRLC_WINMODE_MODE1,
/** RESULT < WINUT */
ADC_WINDOW_MODE_BELOW_UPPER = ADC_CTRLC_WINMODE_MODE2,
/** WINLT < RESULT < WINUT */
ADC_WINDOW_MODE_BETWEEN = ADC_CTRLC_WINMODE_MODE3,
/** !(WINLT < RESULT < WINUT) */
ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_CTRLC_WINMODE_MODE4,
};
/**
* \brief ADC event action enum.
*
* Enum for the possible actions to take on an incoming event.
*
*/
enum adc_event_action {
/** Event action disabled */
ADC_EVENT_ACTION_DISABLED = 0,
/** Flush ADC and start conversion */
ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_FLUSHEI,
/** Start conversion */
ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
};
/**
* \brief ADC positive MUX input selection enum.
*
* Enum for the possible positive MUX input selections for the ADC.
*
*/
enum adc_positive_input {
/** ADC0 pin */
ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_AIN0,
/** ADC1 pin */
ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_AIN1,
/** ADC2 pin */
ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_AIN2,
/** ADC3 pin */
ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_AIN3,
/** ADC4 pin */
ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_AIN4,
/** ADC5 pin */
ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_AIN5,
/** ADC6 pin */
ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_AIN6,
/** ADC7 pin */
ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_AIN7,
/** ADC8 pin */
ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_AIN8,
/** ADC9 pin */
ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_AIN9,
/** ADC10 pin */
ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_AIN10,
/** ADC11 pin */
ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_AIN11,
#if !(SAMC20) && !(SAMC21)
/** ADC12 pin. */
ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_AIN12,
/** ADC13 pin */
ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_AIN13,
/** ADC14 pin */
ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_AIN14,
/** ADC15 pin */
ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_AIN15,
/** ADC16 pin */
ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_AIN16,
/** ADC17 pin */
ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_AIN17,
/** ADC18 pin */
ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_AIN18,
/** ADC19 pin */
ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_AIN19,
/** ADC20 pin */
ADC_POSITIVE_INPUT_PIN20 = ADC_INPUTCTRL_MUXPOS_AIN20,
/** ADC21 pin */
ADC_POSITIVE_INPUT_PIN21 = ADC_INPUTCTRL_MUXPOS_AIN21,
/** ADC22 pin */
ADC_POSITIVE_INPUT_PIN22 = ADC_INPUTCTRL_MUXPOS_AIN22,
/** ADC23 pin */
ADC_POSITIVE_INPUT_PIN23 = ADC_INPUTCTRL_MUXPOS_AIN23,
/** Temperature reference */
ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
#endif
/** Bandgap voltage. */
ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
/** 1/4 scaled core supply */
ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
/** 1/4 scaled I/O supply */
ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
/** DAC input */
ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
#if !(SAMC20) && !(SAMC21)
/** SCALEDVBAT. */
ADC_POSITIVE_INPUT_SCALEDVBAT = ADC_INPUTCTRL_MUXPOS_SCALEDVBAT,
/** OPAMP01 */
ADC_POSITIVE_INPUT_OPAMP01 = ADC_INPUTCTRL_MUXPOS_OPAMP01,
/** OPAMP02 */
ADC_POSITIVE_INPUT_OPAMP2 = ADC_INPUTCTRL_MUXPOS_OPAMP2,
#endif
};
/**
* \brief ADC negative MUX input selection enum.
*
* Enum for the possible negative MUX input selections for the ADC.
*
*/
enum adc_negative_input {
/** ADC0 pin */
ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_AIN0,
/** ADC1 pin */
ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_AIN1,
/** ADC2 pin */
ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_AIN2,
/** ADC3 pin */
ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_AIN3,
/** ADC4 pin */
ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_AIN4,
/** ADC5 pin */
ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_AIN5,
#if !(SAMC20) && !(SAMC21)
/** ADC6 pin. */
ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_AIN6,
/** ADC7 pin */
ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_AIN7,
#endif
/** Internal ground. */
ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG(0x18u),
};
/**
* \brief ADC number of accumulated samples enum.
*
* Enum for the possible numbers of ADC samples to accumulate.
* This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
* resolution setting is used.
*
*/
enum adc_accumulate_samples {
/** No averaging */
ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
/** Average 2 samples */
ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
/** Average 4 samples */
ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
/** Average 8 samples */
ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
/** Average 16 samples */
ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
/** Average 32 samples */
ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
/** Average 64 samples */
ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
/** Average 128 samples */
ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
/** Average 256 samples */
ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
/** Average 512 samples */
ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
/** Average 1024 samples */
ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
};
/**
* \brief ADC possible dividers for the result register.
*
* Enum for the possible division factors to use when accumulating
* multiple samples. To keep the same resolution for the averaged
* result and the actual input value, the division factor must
* be equal to the number of samples accumulated. This setting is only
* used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
*/
enum adc_divide_result {
/** Don't divide result register after accumulation */
ADC_DIVIDE_RESULT_DISABLE = 0,
/** Divide result register by 2 after accumulation */
ADC_DIVIDE_RESULT_2 = 1,
/** Divide result register by 4 after accumulation */
ADC_DIVIDE_RESULT_4 = 2,
/** Divide result register by 8 after accumulation */
ADC_DIVIDE_RESULT_8 = 3,
/** Divide result register by 16 after accumulation */
ADC_DIVIDE_RESULT_16 = 4,
/** Divide result register by 32 after accumulation */
ADC_DIVIDE_RESULT_32 = 5,
/** Divide result register by 64 after accumulation */
ADC_DIVIDE_RESULT_64 = 6,
/** Divide result register by 128 after accumulation */
ADC_DIVIDE_RESULT_128 = 7,
};
#if ADC_CALLBACK_MODE == true
/**
* Enum for the possible ADC interrupt flags.
*/
enum adc_interrupt_flag {
/** ADC result ready */
ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
/** Window monitor match */
ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
/** ADC result overwritten before read */
ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
};
#endif
/**
* \brief ADC oversampling and decimation enum.
*
* Enum for the possible numbers of bits resolution can be increased by when
* using oversampling and decimation.
*
*/
enum adc_oversampling_and_decimation {
/** Don't use oversampling and decimation mode */
ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
/** 1 bit resolution increase */
ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
/** 2 bits resolution increase */
ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
/** 3 bits resolution increase */
ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
/** 4 bits resolution increase */
ADC_OVERSAMPLING_AND_DECIMATION_4BIT
};
#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
/**
* Enum for the trigger selection in dual mode.
*/
enum adc_dual_mode_trigger_selection {
/** Start event or software trigger will start a conversion on both ADCs. */
ADC_DUAL_MODE_BOTH = ADC_CTRLC_DUALSEL_BOTH,
/** START event or software trigger will alternatingly start a conversion on ADC0 and ADC1. */
ADC_DUAL_MODE_INTERLEAVE = ADC_CTRLC_DUALSEL_INTERLEAVE,
};
#endif
/**
* \brief Window monitor configuration structure.
*
* Window monitor configuration structure.
*/
struct adc_window_config {
/** Selected window mode */
enum adc_window_mode window_mode;
/** Lower window value */
int32_t window_lower_value;
/** Upper window value */
int32_t window_upper_value;
};
/**
* \brief ADC event enable/disable structure.
*
* Event flags for the ADC module. This is used to enable and
* disable events via \ref adc_enable_events() and \ref adc_disable_events().
*/
struct adc_events {
/** Enable event generation on conversion done */
bool generate_event_on_conversion_done;
/** Enable event generation on window monitor */
bool generate_event_on_window_monitor;
};
/**
* \brief Gain and offset correction configuration structure.
*
* Gain and offset correction configuration structure.
* Part of the \ref adc_config struct and will be initialized by
* \ref adc_get_config_defaults.
*/
struct adc_correction_config {
/**
* Enables correction for gain and offset based on values of gain_correction and
* offset_correction if set to true
*/
bool correction_enable;
/**
* This value defines how the ADC conversion result is compensated for gain
* error before written to the result register. This is a fractional value,
* 1-bit integer plus an 11-bit fraction, therefore
* 1/2 ¡Ü gain_correction < 2. Valid \c gain_correction values ranges from
* \c 0b010000000000 to \c 0b111111111111.
*/
uint16_t gain_correction;
/**
* This value defines how the ADC conversion result is compensated for
* offset error before written to the result register. This is a 12-bit
* value in two's complement format.
*/
int16_t offset_correction;
};
/**
* \brief ADC configuration structure.
*
* Configuration structure for an ADC instance. This structure should be
* initialized by the \ref adc_get_config_defaults()
* function before being modified by the user application.
*/
struct adc_config {
/** GCLK generator used to clock the peripheral */
enum gclk_generator clock_source;
/** Voltage reference */
enum adc_reference reference;
/** Clock prescaler */
enum adc_clock_prescaler clock_prescaler;
/** Result resolution */
enum adc_resolution resolution;
/** Positive MUX input */
enum adc_positive_input positive_input;
/** Negative MUX input */
enum adc_negative_input negative_input;
/** Number of ADC samples to accumulate when using the
* \c ADC_RESOLUTION_CUSTOM mode
*/
enum adc_accumulate_samples accumulate_samples;
/** Division ration when using the ADC_RESOLUTION_CUSTOM mode */
enum adc_divide_result divide_result;
/** Left adjusted result */
bool left_adjust;
/** Enables differential mode if true */
bool differential_mode;
/** Enables free running mode if true */
bool freerunning;
/** ADC run in standby control */
bool run_in_standby;
/** ADC On demand control */
bool on_demand;
/**
* Enables sampling period offset compensation if true
*/
bool sampling_time_compensation_enable;
/**
* Positive input enabled mask for conversion sequence.
* The sequence start from the lowest input, and go to the next enabled input
* automatically when the conversion is done. If no bits are set the
* sequence is disabled.
*/
uint32_t positive_input_sequence_mask_enable;
/**
* Enables reference buffer offset compensation if true.
* This will increase the accuracy of the gain stage, but decreases the input
* impedance; therefore the startup time of the reference must be increased.
*/
bool reference_compensation_enable;
/**
* This value (0-63) control the ADC sampling time in number of half ADC
* prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
* controlling the ADC input impedance. Sampling time is set according to
* the formula:
* Sample time = (sample_length+1) * (ADCclk / 2).
*/
uint8_t sample_length;
/** Window monitor configuration structure */
struct adc_window_config window;
/** Gain and offset correction configuration structure */
struct adc_correction_config correction;
/** Event action to take on incoming event */
enum adc_event_action event_action;
};
/**
* \brief ADC software device instance structure.
*
* ADC software instance structure, used to retain software state information
* of an associated hardware module instance.
*
* \note The fields of this structure should not be altered by the user
* application; they are reserved for module-internal use only.
*/
struct adc_module {
#if !defined(__DOXYGEN__)
/** Pointer to ADC hardware module */
Adc *hw;
/** Keep reference configuration so we know when enable is called */
enum adc_reference reference;
# if ADC_CALLBACK_MODE == true
/** Array to store callback functions */
adc_callback_t callback[ADC_CALLBACK_N];
/** Pointer to buffer used for ADC results */
volatile uint16_t *job_buffer;
/** Remaining number of conversions in current job */
volatile uint16_t remaining_conversions;
/** Bit mask for callbacks registered */
uint8_t registered_callback_mask;
/** Bit mask for callbacks enabled */
uint8_t enabled_callback_mask;
/** Holds the status of the ongoing or last conversion job */
volatile enum status_code job_status;
/** If software triggering is needed */
bool software_trigger;
# endif
#endif
};
#if !defined(__DOXYGEN__)
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus. This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \param[in] module_inst Pointer to the ADC software instance struct
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true if the module synchronization is ongoing
* \retval false if the module has completed synchronization
*/
static inline bool adc_is_syncing(
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
if (adc_module->SYNCBUSY.reg) {
return true;
}
return false;
}
#endif
/**
* \name Positive Input Sequence
* @{
*/
/**
* \brief Enable positive input sequence mask for conversion.
*
* The sequence start from the lowest input, and go to the next enabled input
* automatically when the conversion is done. If no bits are set the
* sequence is disabled.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] eanble_seq_mask Sequence mask
*/
static inline void adc_enable_positive_input_sequence(
struct adc_module *const module_inst,
uint32_t positive_input_sequence_mask_enable)
{
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
adc_module->SEQCTRL.reg = positive_input_sequence_mask_enable;
}
/**
* \brief Disable positive input in the sequence.
*
* Disable positive input in the sequence.
*
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline void adc_disable_positive_input_sequence(
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
adc_module->SEQCTRL.reg = 0;
}
/**
* \brief Get ADC sequence status.
*
* Check if a sequence is done and get last conversion done in the sequence.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[out] is_sequence_busy Sequence busy status
* \param[out] sequence_state This value identifies the last conversion
* done in the sequence
*/
static inline void adc_get_sequence_status(
struct adc_module *const module_inst,
bool * is_sequence_busy,
uint8_t *sequence_state)
{
/* Sanity check arguments */
Assert(module_inst);
uint8_t temp = false;
Adc *const adc_module = module_inst->hw;
temp = adc_module->SEQSTATUS.reg;
if(temp & ADC_SEQSTATUS_SEQBUSY) {
*is_sequence_busy = true;
}
*sequence_state = temp & ADC_SEQSTATUS_SEQSTATE_Msk;
}
/** @} */
#ifdef FEATURE_ADC_SUPPORT_MASTER_SLAVE
/**
* \brief Set ADC master and slave mode.
*
* Enable ADC module Master-Slave Operation and select dual mode trigger.
*
* \param[in] master_inst Pointer to the master ADC software instance struct
* \param[in] slave_inst Pointer to the slave ADC software instance struct
* \param[in] dualsel Dual mode trigger selection
*
*/
static inline void adc_set_master_slave_mode(
struct adc_module *const master_inst,
struct adc_module *const slave_inst,
enum adc_dual_mode_trigger_selection dualsel)
{
/* Sanity check arguments */
Assert(master_inst);
Assert(slave_inst);
slave_inst->hw->CTRLA.reg |= ADC_CTRLA_SLAVEEN;
master_inst->hw->CTRLC.reg |= dualsel;
};
#endif
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* ADC_FEATURE_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc.c
View File

@ -1,704 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Analog-to-Digital Converter Driver
*
* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "adc.h"
#if SAMD20
/* The Die revision D number */
#define REVISON_D_NUM 3
#endif
/**
* \brief Initializes an ADC configuration structure to defaults
*
* Initializes a given ADC configuration struct to a set of known default
* values. This function should be called on any new instance of the
* configuration struct before being modified by the user application.
*
* The default configuration is as follows:
* \li GCLK generator 0 (GCLK main) clock source
* \li 1V from internal bandgap reference
* \li Div 4 clock prescaler
* \li 12-bit resolution
* \li Window monitor disabled
* \li No gain
* \li Positive input on ADC PIN 0
* \li Negative input on ADC PIN 1
* \li Averaging disabled
* \li Oversampling disabled
* \li Right adjust data
* \li Single-ended mode
* \li Free running disabled
* \li All events (input and generation) disabled
* \li Sleep operation disabled
* \li No reference compensation
* \li No gain/offset correction
* \li No added sampling time
* \li Pin scan mode disabled
*
* \param[out] config Pointer to configuration struct to initialize to
* default values
*/
void adc_get_config_defaults(struct adc_config *const config)
{
Assert(config);
config->clock_source = GCLK_GENERATOR_0;
config->reference = ADC_REFERENCE_INT1V;
config->clock_prescaler = ADC_CLOCK_PRESCALER_DIV4;
config->resolution = ADC_RESOLUTION_12BIT;
config->window.window_mode = ADC_WINDOW_MODE_DISABLE;
config->window.window_upper_value = 0;
config->window.window_lower_value = 0;
config->gain_factor = ADC_GAIN_FACTOR_1X;
#if SAMR21
config->positive_input = ADC_POSITIVE_INPUT_PIN6 ;
#else
config->positive_input = ADC_POSITIVE_INPUT_PIN0 ;
#endif
config->negative_input = ADC_NEGATIVE_INPUT_GND ;
config->accumulate_samples = ADC_ACCUMULATE_DISABLE;
config->divide_result = ADC_DIVIDE_RESULT_DISABLE;
config->left_adjust = false;
config->differential_mode = false;
config->freerunning = false;
config->event_action = ADC_EVENT_ACTION_DISABLED;
config->run_in_standby = false;
config->reference_compensation_enable = false;
config->correction.correction_enable = false;
config->correction.gain_correction = ADC_GAINCORR_RESETVALUE;
config->correction.offset_correction = ADC_OFFSETCORR_RESETVALUE;
config->sample_length = 0;
config->pin_scan.offset_start_scan = 0;
config->pin_scan.inputs_to_scan = 0;
}
/**
* \brief Sets the ADC window mode
*
* Sets the ADC window mode to a given mode and value range.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] window_mode Window monitor mode to set
* \param[in] window_lower_value Lower window monitor threshold value
* \param[in] window_upper_value Upper window monitor threshold value
*/
void adc_set_window_mode(
struct adc_module *const module_inst,
const enum adc_window_mode window_mode,
const int16_t window_lower_value,
const int16_t window_upper_value)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set window mode */
adc_module->WINCTRL.reg = window_mode << ADC_WINCTRL_WINMODE_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set lower window monitor threshold value */
adc_module->WINLT.reg = window_lower_value << ADC_WINLT_WINLT_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set upper window monitor threshold value */
adc_module->WINUT.reg = window_upper_value << ADC_WINUT_WINUT_Pos;
}
/**
* \internal Configure MUX settings for the analog pins
*
* This function will set the given ADC input pins
* to the analog function in the pinmux, giving
* the ADC access to the analog signal
*
* \param [in] pin AINxx pin to configure
*/
static inline void _adc_configure_ain_pin(uint32_t pin)
{
#define PIN_INVALID_ADC_AIN 0xFFFFUL
/* Pinmapping table for AINxx -> GPIO pin number */
const uint32_t pinmapping[] = {
#if (SAMD20E) || (SAMD21E)|| (SAMDA1E)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20G) || (SAMD21G)|| (SAMDA1G)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif (SAMD20J) || (SAMD21J)|| (SAMDA1J)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PB08B_ADC_AIN2, PIN_PB09B_ADC_AIN3,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_PB00B_ADC_AIN8, PIN_PB01B_ADC_AIN9,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_PB04B_ADC_AIN12, PIN_PB05B_ADC_AIN13,
PIN_PB06B_ADC_AIN14, PIN_PB07B_ADC_AIN15,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_PA10B_ADC_AIN18, PIN_PA11B_ADC_AIN19,
#elif SAMR21E
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif SAMR21G
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN4, PIN_PA05B_ADC_AIN5,
PIN_PA06B_ADC_AIN6, PIN_PA07B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PB02B_ADC_AIN10, PIN_PB03B_ADC_AIN11,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA08B_ADC_AIN16, PIN_PA09B_ADC_AIN17,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10C) || (SAMD11C)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DS) || (SAMD11DS)
PIN_PA02B_ADC_AIN0, PIN_INVALID_ADC_AIN,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#elif (SAMD10DM) || (SAMD11DM)
PIN_PA02B_ADC_AIN0, PIN_PA03B_ADC_AIN1,
PIN_PA04B_ADC_AIN2, PIN_PA05B_ADC_AIN3,
PIN_PA06B_ADC_AIN4, PIN_PA07B_ADC_AIN5,
PIN_PA14B_ADC_AIN6, PIN_PA15B_ADC_AIN7,
PIN_PA10B_ADC_AIN8, PIN_PA11B_ADC_AIN9,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
PIN_INVALID_ADC_AIN, PIN_INVALID_ADC_AIN,
#else
# error ADC pin mappings are not defined for this device.
#endif
};
uint32_t pin_map_result = PIN_INVALID_ADC_AIN;
if (pin <= ADC_EXTCHANNEL_MSB) {
pin_map_result = pinmapping[pin >> ADC_INPUTCTRL_MUXPOS_Pos];
Assert(pin_map_result != PIN_INVALID_ADC_AIN);
struct system_pinmux_config config;
system_pinmux_get_config_defaults(&config);
/* Analog functions are all on MUX setting B */
config.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
config.mux_position = 1;
system_pinmux_pin_set_config(pin_map_result, &config);
}
}
/**
* \internal Writes an ADC configuration to the hardware module
*
* Writes out a given ADC module configuration to the hardware module.
*
* \param[out] module_inst Pointer to the ADC software instance struct
* \param[in] config Pointer to configuration struct
*
* \return Status of the configuration procedure
* \retval STATUS_OK The configuration was successful
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
*/
static enum status_code _adc_set_config(
struct adc_module *const module_inst,
struct adc_config *const config)
{
uint8_t adjres = 0;
uint32_t resolution = ADC_RESOLUTION_16BIT;
enum adc_accumulate_samples accumulate = ADC_ACCUMULATE_DISABLE;
#if SAMD20
uint8_t revision_num = ((REG_DSU_DID & DSU_DID_DIE_Msk) >> DSU_DID_DIE_Pos);
#endif
/* Get the hardware module pointer */
Adc *const adc_module = module_inst->hw;
/* Configure GCLK channel and enable clock */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = config->clock_source;
system_gclk_chan_set_config(ADC_GCLK_ID, &gclk_chan_conf);
system_gclk_chan_enable(ADC_GCLK_ID);
/* Setup pinmuxing for analog inputs */
if (config->pin_scan.inputs_to_scan != 0) {
uint8_t offset = config->pin_scan.offset_start_scan;
uint8_t start_pin =
offset +(uint8_t)config->positive_input;
uint8_t end_pin =
start_pin + config->pin_scan.inputs_to_scan;
while (start_pin < end_pin) {
_adc_configure_ain_pin((offset % 16)+(uint8_t)config->positive_input);
start_pin++;
offset++;
}
_adc_configure_ain_pin(config->negative_input);
} else {
_adc_configure_ain_pin(config->positive_input);
_adc_configure_ain_pin(config->negative_input);
}
/* Configure run in standby */
adc_module->CTRLA.reg = (config->run_in_standby << ADC_CTRLA_RUNSTDBY_Pos);
/* Configure reference */
adc_module->REFCTRL.reg =
(config->reference_compensation_enable << ADC_REFCTRL_REFCOMP_Pos) |
(config->reference);
/* Set adjusting result and number of samples */
switch (config->resolution) {
case ADC_RESOLUTION_CUSTOM:
adjres = config->divide_result;
accumulate = config->accumulate_samples;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_13BIT:
/* Increase resolution by 1 bit */
adjres = ADC_DIVIDE_RESULT_2;
accumulate = ADC_ACCUMULATE_SAMPLES_4;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_14BIT:
/* Increase resolution by 2 bit */
adjres = ADC_DIVIDE_RESULT_4;
accumulate = ADC_ACCUMULATE_SAMPLES_16;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
#if SAMD20
/* See $35.1.8 for ADC errata of SAM D20.
The revisions before D have this issue.*/
case ADC_RESOLUTION_15BIT:
/* Increase resolution by 3 bit */
if(revision_num < REVISON_D_NUM) {
adjres = ADC_DIVIDE_RESULT_8;
} else {
adjres = ADC_DIVIDE_RESULT_2;
}
accumulate = ADC_ACCUMULATE_SAMPLES_64;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_16BIT:
if(revision_num < REVISON_D_NUM) {
/* Increase resolution by 4 bit */
adjres = ADC_DIVIDE_RESULT_16;
} else {
adjres = ADC_DIVIDE_RESULT_DISABLE;
}
accumulate = ADC_ACCUMULATE_SAMPLES_256;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
#else
case ADC_RESOLUTION_15BIT:
/* Increase resolution by 3 bit */
adjres = ADC_DIVIDE_RESULT_2;
accumulate = ADC_ACCUMULATE_SAMPLES_64;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
case ADC_RESOLUTION_16BIT:
/* Increase resolution by 4 bit */
adjres = ADC_DIVIDE_RESULT_DISABLE;
accumulate = ADC_ACCUMULATE_SAMPLES_256;
/* 16-bit result register */
resolution = ADC_RESOLUTION_16BIT;
break;
#endif
case ADC_RESOLUTION_8BIT:
/* 8-bit result register */
resolution = ADC_RESOLUTION_8BIT;
break;
case ADC_RESOLUTION_10BIT:
/* 10-bit result register */
resolution = ADC_RESOLUTION_10BIT;
break;
case ADC_RESOLUTION_12BIT:
/* 12-bit result register */
resolution = ADC_RESOLUTION_12BIT;
break;
default:
/* Unknown. Abort. */
return STATUS_ERR_INVALID_ARG;
}
adc_module->AVGCTRL.reg = ADC_AVGCTRL_ADJRES(adjres) | accumulate;
/* Check validity of sample length value */
if (config->sample_length > 63) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Configure sample length */
adc_module->SAMPCTRL.reg =
(config->sample_length << ADC_SAMPCTRL_SAMPLEN_Pos);
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure CTRLB */
adc_module->CTRLB.reg =
config->clock_prescaler |
resolution |
(config->correction.correction_enable << ADC_CTRLB_CORREN_Pos) |
(config->freerunning << ADC_CTRLB_FREERUN_Pos) |
(config->left_adjust << ADC_CTRLB_LEFTADJ_Pos) |
(config->differential_mode << ADC_CTRLB_DIFFMODE_Pos);
/* Check validity of window thresholds */
if (config->window.window_mode != ADC_WINDOW_MODE_DISABLE) {
switch (resolution) {
case ADC_RESOLUTION_8BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 127 ||
config->window.window_lower_value < -128 ||
config->window.window_upper_value > 127 ||
config->window.window_upper_value < -128)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 255 ||
config->window.window_upper_value > 255) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_10BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 511 ||
config->window.window_lower_value < -512 ||
config->window.window_upper_value > 511 ||
config->window.window_upper_value < -512)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 1023 ||
config->window.window_upper_value > 1023) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_12BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 2047 ||
config->window.window_lower_value < -2048 ||
config->window.window_upper_value > 2047 ||
config->window.window_upper_value < -2048)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 4095 ||
config->window.window_upper_value > 4095) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
case ADC_RESOLUTION_16BIT:
if (config->differential_mode &&
(config->window.window_lower_value > 32767 ||
config->window.window_lower_value < -32768 ||
config->window.window_upper_value > 32767 ||
config->window.window_upper_value < -32768)) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
} else if (config->window.window_lower_value > 65535 ||
config->window.window_upper_value > 65535) {
/* Invalid value */
return STATUS_ERR_INVALID_ARG;
}
break;
}
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure window mode */
adc_module->WINCTRL.reg = config->window.window_mode;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure lower threshold */
adc_module->WINLT.reg =
config->window.window_lower_value << ADC_WINLT_WINLT_Pos;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure lower threshold */
adc_module->WINUT.reg = config->window.window_upper_value <<
ADC_WINUT_WINUT_Pos;
uint8_t inputs_to_scan = config->pin_scan.inputs_to_scan;
if (inputs_to_scan > 0) {
/*
* Number of input sources included is the value written to INPUTSCAN
* plus 1.
*/
inputs_to_scan--;
}
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
config->pin_scan.offset_start_scan > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
/* Invalid number of input pins or input offset */
return STATUS_ERR_INVALID_ARG;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Configure pin scan mode and positive and negative input pins */
adc_module->INPUTCTRL.reg =
config->gain_factor |
(config->pin_scan.offset_start_scan <<
ADC_INPUTCTRL_INPUTOFFSET_Pos) |
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos) |
config->negative_input |
config->positive_input;
/* Configure events */
adc_module->EVCTRL.reg = config->event_action;
/* Disable all interrupts */
adc_module->INTENCLR.reg =
(1 << ADC_INTENCLR_SYNCRDY_Pos) | (1 << ADC_INTENCLR_WINMON_Pos) |
(1 << ADC_INTENCLR_OVERRUN_Pos) | (1 << ADC_INTENCLR_RESRDY_Pos);
if (config->correction.correction_enable) {
/* Make sure gain_correction value is valid */
if (config->correction.gain_correction > ADC_GAINCORR_GAINCORR_Msk) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Set gain correction value */
adc_module->GAINCORR.reg = config->correction.gain_correction <<
ADC_GAINCORR_GAINCORR_Pos;
}
/* Make sure offset correction value is valid */
if (config->correction.offset_correction > 2047 ||
config->correction.offset_correction < -2048) {
return STATUS_ERR_INVALID_ARG;
} else {
/* Set offset correction value */
adc_module->OFFSETCORR.reg = config->correction.offset_correction <<
ADC_OFFSETCORR_OFFSETCORR_Pos;
}
}
/* Load in the fixed device ADC calibration constants */
adc_module->CALIB.reg =
ADC_CALIB_BIAS_CAL(
(*(uint32_t *)ADC_FUSES_BIASCAL_ADDR >> ADC_FUSES_BIASCAL_Pos)
) |
ADC_CALIB_LINEARITY_CAL(
(*(uint64_t *)ADC_FUSES_LINEARITY_0_ADDR >> ADC_FUSES_LINEARITY_0_Pos)
);
return STATUS_OK;
}
/**
* \brief Initializes the ADC channel sequence
*
* Like SAMD and SAMR21 the INPUTOFFSET register will be incremented one
* automatically after a conversion done, causing the next conversion
* to be done with the positive input equal to MUXPOS + INPUTOFFSET,
* it is scanning continuously one by one even ADC channels are not continuous.
*
* Initializes the ADC channel sequence by the sequence of pin_array.
*
* \param[in] pin_array The array of the Mux selection for the positive ADC input
* \param[in] size The size of pin_array
*/
void adc_regular_ain_channel(uint32_t *pin_array, uint8_t size)
{
for (int i = 0; i < size; i++) {
_adc_configure_ain_pin(pin_array[i]);
}
}
/**
* \brief Initializes the ADC
*
* Initializes the ADC device struct and the hardware module based on the
* given configuration struct values.
*
* \param[out] module_inst Pointer to the ADC software instance struct
* \param[in] hw Pointer to the ADC module instance
* \param[in] config Pointer to the configuration struct
*
* \return Status of the initialization procedure.
* \retval STATUS_OK The initialization was successful
* \retval STATUS_ERR_INVALID_ARG Invalid argument(s) were provided
* \retval STATUS_BUSY The module is busy with a reset operation
* \retval STATUS_ERR_DENIED The module is enabled
*/
enum status_code adc_init(
struct adc_module *const module_inst,
Adc *hw,
struct adc_config *config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(hw);
Assert(config);
/* Associate the software module instance with the hardware module */
module_inst->hw = hw;
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_ADC);
if (hw->CTRLA.reg & ADC_CTRLA_SWRST) {
/* We are in the middle of a reset. Abort. */
return STATUS_BUSY;
}
if (hw->CTRLA.reg & ADC_CTRLA_ENABLE) {
/* Module must be disabled before initialization. Abort. */
return STATUS_ERR_DENIED;
}
/* Store the selected reference for later use */
module_inst->reference = config->reference;
/* Make sure bandgap is enabled if requested by the config */
if (module_inst->reference == ADC_REFERENCE_INT1V) {
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
}
#if ADC_CALLBACK_MODE == true
for (uint8_t i = 0; i < ADC_CALLBACK_N; i++) {
module_inst->callback[i] = NULL;
};
module_inst->registered_callback_mask = 0;
module_inst->enabled_callback_mask = 0;
module_inst->remaining_conversions = 0;
module_inst->job_status = STATUS_OK;
_adc_instances[0] = module_inst;
if (config->event_action == ADC_EVENT_ACTION_DISABLED &&
!config->freerunning) {
module_inst->software_trigger = true;
} else {
module_inst->software_trigger = false;
}
#endif
/* Write configuration to module */
return _adc_set_config(module_inst, config);
}

728
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/TARGET_SAMR21/adc_feature.h
View File

@ -1,728 +0,0 @@
/**
* \file
*
* \brief SAM ADC functionality
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef ADC_FEATURE_H_INCLUDED
#define ADC_FEATURE_H_INCLUDED
/**
* \addtogroup asfdoc_sam0_adc_group
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#if ADC_CALLBACK_MODE == true
# include <system_interrupt.h>
#if !defined(__DOXYGEN__)
extern struct adc_module *_adc_instances[ADC_INST_NUM];
#endif
/** Forward definition of the device instance. */
struct adc_module;
/** Type of the callback functions. */
typedef void (*adc_callback_t)(struct adc_module *const module);
/**
* \brief ADC Callback enum
*
* Callback types for ADC callback driver.
*
*/
enum adc_callback {
/** Callback for buffer received. */
ADC_CALLBACK_READ_BUFFER,
/** Callback when window is hit. */
ADC_CALLBACK_WINDOW,
/** Callback for error. */
ADC_CALLBACK_ERROR,
# if !defined(__DOXYGEN__)
/** Number of available callbacks. */
ADC_CALLBACK_N,
# endif
};
#endif
/**
* \brief ADC reference voltage enum
*
* Enum for the possible reference voltages for the ADC.
*
*/
enum adc_reference {
/** 1.0V voltage reference. */
ADC_REFERENCE_INT1V = ADC_REFCTRL_REFSEL_INT1V,
/** 1/1.48V<SUB>CC</SUB> reference. */
ADC_REFERENCE_INTVCC0 = ADC_REFCTRL_REFSEL_INTVCC0,
/** 1/2V<SUB>CC</SUB> (only for internal V<SUB>CC</SUB> > 2.1V). */
ADC_REFERENCE_INTVCC1 = ADC_REFCTRL_REFSEL_INTVCC1,
/** External reference A. */
ADC_REFERENCE_AREFA = ADC_REFCTRL_REFSEL_AREFA,
/** External reference B. */
ADC_REFERENCE_AREFB = ADC_REFCTRL_REFSEL_AREFB,
};
/**
* \brief ADC clock prescaler enum
*
* Enum for the possible clock prescaler values for the ADC.
*
*/
enum adc_clock_prescaler {
/** ADC clock division factor 4. */
ADC_CLOCK_PRESCALER_DIV4 = ADC_CTRLB_PRESCALER_DIV4,
/** ADC clock division factor 8. */
ADC_CLOCK_PRESCALER_DIV8 = ADC_CTRLB_PRESCALER_DIV8,
/** ADC clock division factor 16. */
ADC_CLOCK_PRESCALER_DIV16 = ADC_CTRLB_PRESCALER_DIV16,
/** ADC clock division factor 32. */
ADC_CLOCK_PRESCALER_DIV32 = ADC_CTRLB_PRESCALER_DIV32,
/** ADC clock division factor 64. */
ADC_CLOCK_PRESCALER_DIV64 = ADC_CTRLB_PRESCALER_DIV64,
/** ADC clock division factor 128. */
ADC_CLOCK_PRESCALER_DIV128 = ADC_CTRLB_PRESCALER_DIV128,
/** ADC clock division factor 256. */
ADC_CLOCK_PRESCALER_DIV256 = ADC_CTRLB_PRESCALER_DIV256,
/** ADC clock division factor 512. */
ADC_CLOCK_PRESCALER_DIV512 = ADC_CTRLB_PRESCALER_DIV512,
};
/**
* \brief ADC resolution enum
*
* Enum for the possible resolution values for the ADC.
*
*/
enum adc_resolution {
/** ADC 12-bit resolution. */
ADC_RESOLUTION_12BIT = ADC_CTRLB_RESSEL_12BIT,
/** ADC 16-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_16BIT = ADC_CTRLB_RESSEL_16BIT,
/** ADC 10-bit resolution. */
ADC_RESOLUTION_10BIT = ADC_CTRLB_RESSEL_10BIT,
/** ADC 8-bit resolution. */
ADC_RESOLUTION_8BIT = ADC_CTRLB_RESSEL_8BIT,
/** ADC 13-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_13BIT,
/** ADC 14-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_14BIT,
/** ADC 15-bit resolution using oversampling and decimation. */
ADC_RESOLUTION_15BIT,
/** ADC 16-bit result register for use with averaging. When using this mode
* the ADC result register will be set to 16-bit wide, and the number of
* samples to accumulate and the division factor is configured by the
* \ref adc_config.accumulate_samples and \ref adc_config.divide_result
* members in the configuration struct.
*/
ADC_RESOLUTION_CUSTOM,
};
/**
* \brief ADC window monitor mode enum
*
* Enum for the possible window monitor modes for the ADC.
*
*/
enum adc_window_mode {
/** No window mode. */
ADC_WINDOW_MODE_DISABLE = ADC_WINCTRL_WINMODE_DISABLE,
/** RESULT > WINLT. */
ADC_WINDOW_MODE_ABOVE_LOWER = ADC_WINCTRL_WINMODE_MODE1,
/** RESULT < WINUT. */
ADC_WINDOW_MODE_BELOW_UPPER = ADC_WINCTRL_WINMODE_MODE2,
/** WINLT < RESULT < WINUT. */
ADC_WINDOW_MODE_BETWEEN = ADC_WINCTRL_WINMODE_MODE3,
/** !(WINLT < RESULT < WINUT). */
ADC_WINDOW_MODE_BETWEEN_INVERTED = ADC_WINCTRL_WINMODE_MODE4,
};
/**
* \brief ADC gain factor selection enum
*
* Enum for the possible gain factor values for the ADC.
*
*/
enum adc_gain_factor {
/** 1x gain. */
ADC_GAIN_FACTOR_1X = ADC_INPUTCTRL_GAIN_1X,
/** 2x gain. */
ADC_GAIN_FACTOR_2X = ADC_INPUTCTRL_GAIN_2X,
/** 4x gain. */
ADC_GAIN_FACTOR_4X = ADC_INPUTCTRL_GAIN_4X,
/** 8x gain. */
ADC_GAIN_FACTOR_8X = ADC_INPUTCTRL_GAIN_8X,
/** 16x gain. */
ADC_GAIN_FACTOR_16X = ADC_INPUTCTRL_GAIN_16X,
/** 1/2x gain. */
ADC_GAIN_FACTOR_DIV2 = ADC_INPUTCTRL_GAIN_DIV2,
};
/**
* \brief ADC event action enum
*
* Enum for the possible actions to take on an incoming event.
*
*/
enum adc_event_action {
/** Event action disabled. */
ADC_EVENT_ACTION_DISABLED = 0,
/** Flush ADC and start conversion. */
ADC_EVENT_ACTION_FLUSH_START_CONV = ADC_EVCTRL_SYNCEI,
/** Start conversion. */
ADC_EVENT_ACTION_START_CONV = ADC_EVCTRL_STARTEI,
};
/**
* \brief ADC positive MUX input selection enum
*
* Enum for the possible positive MUX input selections for the ADC.
*
*/
enum adc_positive_input {
/** ADC0 pin. */
ADC_POSITIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXPOS_PIN0,
/** ADC1 pin. */
ADC_POSITIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXPOS_PIN1,
/** ADC2 pin. */
ADC_POSITIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXPOS_PIN2,
/** ADC3 pin. */
ADC_POSITIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXPOS_PIN3,
/** ADC4 pin. */
ADC_POSITIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXPOS_PIN4,
/** ADC5 pin. */
ADC_POSITIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXPOS_PIN5,
/** ADC6 pin. */
ADC_POSITIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXPOS_PIN6,
/** ADC7 pin. */
ADC_POSITIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXPOS_PIN7,
/** ADC8 pin. */
ADC_POSITIVE_INPUT_PIN8 = ADC_INPUTCTRL_MUXPOS_PIN8,
/** ADC9 pin. */
ADC_POSITIVE_INPUT_PIN9 = ADC_INPUTCTRL_MUXPOS_PIN9,
/** ADC10 pin. */
ADC_POSITIVE_INPUT_PIN10 = ADC_INPUTCTRL_MUXPOS_PIN10,
/** ADC11 pin. */
ADC_POSITIVE_INPUT_PIN11 = ADC_INPUTCTRL_MUXPOS_PIN11,
/** ADC12 pin. */
ADC_POSITIVE_INPUT_PIN12 = ADC_INPUTCTRL_MUXPOS_PIN12,
/** ADC13 pin. */
ADC_POSITIVE_INPUT_PIN13 = ADC_INPUTCTRL_MUXPOS_PIN13,
/** ADC14 pin. */
ADC_POSITIVE_INPUT_PIN14 = ADC_INPUTCTRL_MUXPOS_PIN14,
/** ADC15 pin. */
ADC_POSITIVE_INPUT_PIN15 = ADC_INPUTCTRL_MUXPOS_PIN15,
/** ADC16 pin. */
ADC_POSITIVE_INPUT_PIN16 = ADC_INPUTCTRL_MUXPOS_PIN16,
/** ADC17 pin. */
ADC_POSITIVE_INPUT_PIN17 = ADC_INPUTCTRL_MUXPOS_PIN17,
/** ADC18 pin. */
ADC_POSITIVE_INPUT_PIN18 = ADC_INPUTCTRL_MUXPOS_PIN18,
/** ADC19 pin. */
ADC_POSITIVE_INPUT_PIN19 = ADC_INPUTCTRL_MUXPOS_PIN19,
/** Temperature reference. */
ADC_POSITIVE_INPUT_TEMP = ADC_INPUTCTRL_MUXPOS_TEMP,
/** Bandgap voltage. */
ADC_POSITIVE_INPUT_BANDGAP = ADC_INPUTCTRL_MUXPOS_BANDGAP,
/** 1/4 scaled core supply. */
ADC_POSITIVE_INPUT_SCALEDCOREVCC = ADC_INPUTCTRL_MUXPOS_SCALEDCOREVCC,
/** 1/4 scaled I/O supply. */
ADC_POSITIVE_INPUT_SCALEDIOVCC = ADC_INPUTCTRL_MUXPOS_SCALEDIOVCC,
/** DAC input. */
ADC_POSITIVE_INPUT_DAC = ADC_INPUTCTRL_MUXPOS_DAC,
};
/**
* \brief ADC negative MUX input selection enum
*
* Enum for the possible negative MUX input selections for the ADC.
*
*/
enum adc_negative_input {
/** ADC0 pin. */
ADC_NEGATIVE_INPUT_PIN0 = ADC_INPUTCTRL_MUXNEG_PIN0,
/** ADC1 pin. */
ADC_NEGATIVE_INPUT_PIN1 = ADC_INPUTCTRL_MUXNEG_PIN1,
/** ADC2 pin. */
ADC_NEGATIVE_INPUT_PIN2 = ADC_INPUTCTRL_MUXNEG_PIN2,
/** ADC3 pin. */
ADC_NEGATIVE_INPUT_PIN3 = ADC_INPUTCTRL_MUXNEG_PIN3,
/** ADC4 pin. */
ADC_NEGATIVE_INPUT_PIN4 = ADC_INPUTCTRL_MUXNEG_PIN4,
/** ADC5 pin. */
ADC_NEGATIVE_INPUT_PIN5 = ADC_INPUTCTRL_MUXNEG_PIN5,
/** ADC6 pin. */
ADC_NEGATIVE_INPUT_PIN6 = ADC_INPUTCTRL_MUXNEG_PIN6,
/** ADC7 pin. */
ADC_NEGATIVE_INPUT_PIN7 = ADC_INPUTCTRL_MUXNEG_PIN7,
/** Internal ground. */
ADC_NEGATIVE_INPUT_GND = ADC_INPUTCTRL_MUXNEG_GND,
/** I/O ground. */
ADC_NEGATIVE_INPUT_IOGND = ADC_INPUTCTRL_MUXNEG_IOGND,
};
/**
* \brief ADC number of accumulated samples enum
*
* Enum for the possible numbers of ADC samples to accumulate.
* This setting is only used when the \ref ADC_RESOLUTION_CUSTOM
* resolution setting is used.
*
*/
enum adc_accumulate_samples {
/** No averaging. */
ADC_ACCUMULATE_DISABLE = ADC_AVGCTRL_SAMPLENUM_1,
/** Average 2 samples. */
ADC_ACCUMULATE_SAMPLES_2 = ADC_AVGCTRL_SAMPLENUM_2,
/** Average 4 samples. */
ADC_ACCUMULATE_SAMPLES_4 = ADC_AVGCTRL_SAMPLENUM_4,
/** Average 8 samples. */
ADC_ACCUMULATE_SAMPLES_8 = ADC_AVGCTRL_SAMPLENUM_8,
/** Average 16 samples. */
ADC_ACCUMULATE_SAMPLES_16 = ADC_AVGCTRL_SAMPLENUM_16,
/** Average 32 samples. */
ADC_ACCUMULATE_SAMPLES_32 = ADC_AVGCTRL_SAMPLENUM_32,
/** Average 64 samples. */
ADC_ACCUMULATE_SAMPLES_64 = ADC_AVGCTRL_SAMPLENUM_64,
/** Average 128 samples. */
ADC_ACCUMULATE_SAMPLES_128 = ADC_AVGCTRL_SAMPLENUM_128,
/** Average 256 samples. */
ADC_ACCUMULATE_SAMPLES_256 = ADC_AVGCTRL_SAMPLENUM_256,
/** Average 512 samples. */
ADC_ACCUMULATE_SAMPLES_512 = ADC_AVGCTRL_SAMPLENUM_512,
/** Average 1024 samples. */
ADC_ACCUMULATE_SAMPLES_1024 = ADC_AVGCTRL_SAMPLENUM_1024,
};
/**
* \brief ADC possible dividers for the result register
*
* Enum for the possible division factors to use when accumulating
* multiple samples. To keep the same resolution for the averaged
* result and the actual input value, the division factor must
* be equal to the number of samples accumulated. This setting is only
* used when the \ref ADC_RESOLUTION_CUSTOM resolution setting is used.
*/
enum adc_divide_result {
/** Don't divide result register after accumulation. */
ADC_DIVIDE_RESULT_DISABLE = 0,
/** Divide result register by 2 after accumulation. */
ADC_DIVIDE_RESULT_2 = 1,
/** Divide result register by 4 after accumulation. */
ADC_DIVIDE_RESULT_4 = 2,
/** Divide result register by 8 after accumulation. */
ADC_DIVIDE_RESULT_8 = 3,
/** Divide result register by 16 after accumulation. */
ADC_DIVIDE_RESULT_16 = 4,
/** Divide result register by 32 after accumulation. */
ADC_DIVIDE_RESULT_32 = 5,
/** Divide result register by 64 after accumulation. */
ADC_DIVIDE_RESULT_64 = 6,
/** Divide result register by 128 after accumulation. */
ADC_DIVIDE_RESULT_128 = 7,
};
#if ADC_CALLBACK_MODE == true
/**
* Enum for the possible ADC interrupt flags.
*/
enum adc_interrupt_flag {
/** ADC result ready. */
ADC_INTERRUPT_RESULT_READY = ADC_INTFLAG_RESRDY,
/** Window monitor match. */
ADC_INTERRUPT_WINDOW = ADC_INTFLAG_WINMON,
/** ADC result overwritten before read. */
ADC_INTERRUPT_OVERRUN = ADC_INTFLAG_OVERRUN,
};
#endif
/**
* \brief ADC oversampling and decimation enum
*
* Enum for the possible numbers of bits resolution can be increased by when
* using oversampling and decimation.
*
*/
enum adc_oversampling_and_decimation {
/** Don't use oversampling and decimation mode. */
ADC_OVERSAMPLING_AND_DECIMATION_DISABLE = 0,
/** 1 bit resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_1BIT,
/** 2 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_2BIT,
/** 3 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_3BIT,
/** 4 bits resolution increase. */
ADC_OVERSAMPLING_AND_DECIMATION_4BIT
};
/**
* \brief Window monitor configuration structure
*
* Window monitor configuration structure.
*/
struct adc_window_config {
/** Selected window mode. */
enum adc_window_mode window_mode;
/** Lower window value. */
int32_t window_lower_value;
/** Upper window value. */
int32_t window_upper_value;
};
/**
* \brief ADC event enable/disable structure.
*
* Event flags for the ADC module. This is used to enable and
* disable events via \ref adc_enable_events() and \ref adc_disable_events().
*/
struct adc_events {
/** Enable event generation on conversion done. */
bool generate_event_on_conversion_done;
/** Enable event generation on window monitor. */
bool generate_event_on_window_monitor;
};
/**
* \brief Gain and offset correction configuration structure
*
* Gain and offset correction configuration structure.
* Part of the \ref adc_config struct and will be initialized by
* \ref adc_get_config_defaults.
*/
struct adc_correction_config {
/**
* Enables correction for gain and offset based on values of gain_correction and
* offset_correction if set to true.
*/
bool correction_enable;
/**
* This value defines how the ADC conversion result is compensated for gain
* error before written to the result register. This is a fractional value,
* 1-bit integer plus an 11-bit fraction, therefore
* 1/2 <= gain_correction < 2. Valid \c gain_correction values ranges from
* \c 0b010000000000 to \c 0b111111111111.
*/
uint16_t gain_correction;
/**
* This value defines how the ADC conversion result is compensated for
* offset error before written to the result register. This is a 12-bit
* value in two's complement format.
*/
int16_t offset_correction;
};
/**
* \brief Pin scan configuration structure
*
* Pin scan configuration structure. Part of the \ref adc_config struct and will
* be initialized by \ref adc_get_config_defaults.
*/
struct adc_pin_scan_config {
/**
* Offset (relative to selected positive input) of the first input pin to be
* used in pin scan mode.
*/
uint8_t offset_start_scan;
/**
* Number of input pins to scan in pin scan mode. A value below two will
* disable pin scan mode.
*/
uint8_t inputs_to_scan;
};
/**
* \brief ADC configuration structure
*
* Configuration structure for an ADC instance. This structure should be
* initialized by the \ref adc_get_config_defaults()
* function before being modified by the user application.
*/
struct adc_config {
/** GCLK generator used to clock the peripheral. */
enum gclk_generator clock_source;
/** Voltage reference. */
enum adc_reference reference;
/** Clock prescaler. */
enum adc_clock_prescaler clock_prescaler;
/** Result resolution. */
enum adc_resolution resolution;
/** Gain factor. */
enum adc_gain_factor gain_factor;
/** Positive MUX input. */
enum adc_positive_input positive_input;
/** Negative MUX input. For singled-ended conversion mode, the negative
* input must be connected to ground. This ground could be the internal
* GND, IOGND or an external ground connected to a pin. */
enum adc_negative_input negative_input;
/** Number of ADC samples to accumulate when using the
* \c ADC_RESOLUTION_CUSTOM mode.Note: if the result width increases,
* result resolution will be changed accordingly.
*/
enum adc_accumulate_samples accumulate_samples;
/** Division ration when using the ADC_RESOLUTION_CUSTOM mode. */
enum adc_divide_result divide_result;
/** Left adjusted result. */
bool left_adjust;
/** Enables differential mode if true.
* if false, ADC will run in singled-ended mode. */
bool differential_mode;
/** Enables free running mode if true. */
bool freerunning;
/** Enables ADC in standby sleep mode if true. */
bool run_in_standby;
/**
* Enables reference buffer offset compensation if true.
* This will increase the accuracy of the gain stage, but decreases the input
* impedance; therefore the startup time of the reference must be increased.
*/
bool reference_compensation_enable;
/**
* This value (0-63) control the ADC sampling time in number of half ADC
* prescaled clock cycles (depends of \c ADC_PRESCALER value), thus
* controlling the ADC input impedance. Sampling time is set according to
* the formula:
* Sample time = (sample_length+1) * (ADCclk / 2).
*/
uint8_t sample_length;
/** Window monitor configuration structure. */
struct adc_window_config window;
/** Gain and offset correction configuration structure. */
struct adc_correction_config correction;
/** Event action to take on incoming event. */
enum adc_event_action event_action;
/** Pin scan configuration structure. */
struct adc_pin_scan_config pin_scan;
};
/**
* \brief ADC software device instance structure.
*
* ADC software instance structure, used to retain software state information
* of an associated hardware module instance.
*
* \note The fields of this structure should not be altered by the user
* application; they are reserved for module-internal use only.
*/
struct adc_module {
#if !defined(__DOXYGEN__)
/** Pointer to ADC hardware module. */
Adc *hw;
/** Keep reference configuration so we know when enable is called. */
enum adc_reference reference;
# if ADC_CALLBACK_MODE == true
/** Array to store callback functions. */
adc_callback_t callback[ADC_CALLBACK_N];
/** Pointer to buffer used for ADC results. */
volatile uint16_t *job_buffer;
/** Remaining number of conversions in current job. */
volatile uint16_t remaining_conversions;
/** Bit mask for callbacks registered. */
uint8_t registered_callback_mask;
/** Bit mask for callbacks enabled. */
uint8_t enabled_callback_mask;
/** Holds the status of the ongoing or last conversion job. */
volatile enum status_code job_status;
/** If software triggering is needed. */
bool software_trigger;
# endif
#endif
};
#if !defined(__DOXYGEN__)
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus. This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \param[in] module_inst Pointer to the ADC software instance struct
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true if the module synchronization is ongoing
* \retval false if the module has completed synchronization
*/
static inline bool adc_is_syncing(
struct adc_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Adc *const adc_module = module_inst->hw;
if (adc_module->STATUS.reg & ADC_STATUS_SYNCBUSY) {
return true;
}
return false;
}
#endif
/**
* \name ADC Gain and Pin Scan Mode
* @{
*/
/**
* \brief Sets ADC gain factor
*
* Sets the ADC gain factor to a specified gain setting.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] gain_factor Gain factor value to set
*/
static inline void adc_set_gain(
struct adc_module *const module_inst,
const enum adc_gain_factor gain_factor)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set new gain factor */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg & ~ADC_INPUTCTRL_GAIN_Msk) |
(gain_factor);
}
/**
* \brief Sets the ADC pin scan mode
*
* Configures the pin scan mode of the ADC module. In pin scan mode, the first
* conversion will start at the configured positive input + start_offset. When
* a conversion is done, a conversion will start on the next input, until
* \c inputs_to_scan number of conversions are made.
*
* \param[in] module_inst Pointer to the ADC software instance struct
* \param[in] inputs_to_scan Number of input pins to perform a conversion on
* (must be two or more)
* \param[in] start_offset Offset of first pin to scan (relative to
* configured positive input)
*
* \return Status of the pin scan configuration set request.
*
* \retval STATUS_OK Pin scan mode has been set successfully
* \retval STATUS_ERR_INVALID_ARG Number of input pins to scan or offset has
* an invalid value
*/
static inline enum status_code adc_set_pin_scan_mode(
struct adc_module *const module_inst,
uint8_t inputs_to_scan,
const uint8_t start_offset)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Adc *const adc_module = module_inst->hw;
if (inputs_to_scan > 0) {
/*
* Number of input sources included is the value written to INPUTSCAN
* plus 1.
*/
inputs_to_scan--;
}
if (inputs_to_scan > (ADC_INPUTCTRL_INPUTSCAN_Msk >> ADC_INPUTCTRL_INPUTSCAN_Pos) ||
start_offset > (ADC_INPUTCTRL_INPUTOFFSET_Msk >> ADC_INPUTCTRL_INPUTOFFSET_Pos)) {
/* Invalid number of input pins */
return STATUS_ERR_INVALID_ARG;
}
while (adc_is_syncing(module_inst)) {
/* Wait for synchronization */
}
/* Set pin scan mode */
adc_module->INPUTCTRL.reg =
(adc_module->INPUTCTRL.reg &
~(ADC_INPUTCTRL_INPUTSCAN_Msk | ADC_INPUTCTRL_INPUTOFFSET_Msk)) |
(start_offset << ADC_INPUTCTRL_INPUTOFFSET_Pos) |
(inputs_to_scan << ADC_INPUTCTRL_INPUTSCAN_Pos);
return STATUS_OK;
}
/**
* \brief Disables pin scan mode
*
* Disables pin scan mode. The next conversion will be made on only one pin
* (the configured positive input pin).
*
* \param[in] module_inst Pointer to the ADC software instance struct
*/
static inline void adc_disable_pin_scan_mode(
struct adc_module *const module_inst)
{
/* Disable pin scan mode */
adc_set_pin_scan_mode(module_inst, 0, 0);
}
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* ADC_FEATURE_H_INCLUDED */

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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/adc/adc.h
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targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac.c
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/**
* \file
*
* \brief SAM Peripheral Digital-to-Analog Converter Driver
*
* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "dac.h"
#include <system.h>
#include <pinmux.h>
/**
* \internal Writes a DAC configuration to the hardware module.
*
* Writes out a given configuration to the hardware module.
*
* \param[out] module_inst Pointer to the DAC software instance struct
* \param[in] config Pointer to the configuration struct
*
*/
static void _dac_set_config(
struct dac_module *const module_inst,
struct dac_config *const config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(config);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
/* Set selected DAC output to be enabled when enabling the module */
module_inst->output = config->output;
module_inst->start_on_event = false;
uint32_t new_ctrla = 0;
uint32_t new_ctrlb = 0;
/* Enable DAC in standby sleep mode if configured */
if (config->run_in_standby) {
new_ctrla |= DAC_CTRLA_RUNSTDBY;
}
/* Set reference voltage */
new_ctrlb |= config->reference;
/* Left adjust data if configured */
if (config->left_adjust) {
new_ctrlb |= DAC_CTRLB_LEFTADJ;
}
#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
/* Bypass DATABUF write protection if configured */
if (config->databuf_protection_bypass) {
new_ctrlb |= DAC_CTRLB_BDWP;
}
#endif
/* Voltage pump disable if configured */
if (config->voltage_pump_disable) {
new_ctrlb |= DAC_CTRLB_VPD;
}
/* Apply the new configuration to the hardware module */
dac_module->CTRLA.reg = new_ctrla;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
dac_module->CTRLB.reg = new_ctrlb;
}
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus, This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \param[in] dev_inst Pointer to the DAC software instance struct
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true If the module synchronization is ongoing
* \retval false If the module has completed synchronization
*/
bool dac_is_syncing(
struct dac_module *const dev_inst)
{
/* Sanity check arguments */
Assert(dev_inst);
Dac *const dac_module = dev_inst->hw;
#if (SAMC21)
if (dac_module->SYNCBUSY.reg) {
#else
if (dac_module->STATUS.reg & DAC_STATUS_SYNCBUSY) {
#endif
return true;
}
return false;
}
/**
* \brief Initializes a DAC configuration structure to defaults.
*
* Initializes a given DAC configuration structure to a set of
* known default values. This function should be called on any new
* instance of the configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li 1V from internal bandgap reference
* \li Drive the DAC output to the VOUT pin
* \li Right adjust data
* \li GCLK generator 0 (GCLK main) clock source
* \li The output buffer is disabled when the chip enters STANDBY sleep
* mode
*
* \param[out] config Configuration structure to initialize to default values
*/
void dac_get_config_defaults(
struct dac_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->reference = DAC_REFERENCE_INT1V;
config->output = DAC_OUTPUT_EXTERNAL;
config->left_adjust = false;
#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
config->databuf_protection_bypass = false;
#endif
config->voltage_pump_disable = false;
config->clock_source = GCLK_GENERATOR_0;
config->run_in_standby = false;
#if (SAMC21)
config->dither_mode = false;
#endif
}
/**
* \brief Initialize the DAC device struct.
*
* Use this function to initialize the Digital to Analog Converter. Resets the
* underlying hardware module and configures it.
*
* \note The DAC channel must be configured separately.
*
* \param[out] module_inst Pointer to the DAC software instance struct
* \param[in] module Pointer to the DAC module instance
* \param[in] config Pointer to the config struct, created by the user
* application
*
* \return Status of initialization.
* \retval STATUS_OK Module initiated correctly
* \retval STATUS_ERR_DENIED If module is enabled
* \retval STATUS_BUSY If module is busy resetting
*/
enum status_code dac_init(
struct dac_module *const module_inst,
Dac *const module,
struct dac_config *const config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module);
Assert(config);
/* Initialize device instance */
module_inst->hw = module;
/* Turn on the digital interface clock */
#if (SAMC21)
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
#else
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, PM_APBCMASK_DAC);
#endif
/* Check if module is enabled. */
if (module->CTRLA.reg & DAC_CTRLA_ENABLE) {
return STATUS_ERR_DENIED;
}
/* Check if reset is in progress. */
if (module->CTRLA.reg & DAC_CTRLA_SWRST) {
return STATUS_BUSY;
}
/* Configure GCLK channel and enable clock */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = config->clock_source;
system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
system_gclk_chan_enable(DAC_GCLK_ID);
/* MUX the DAC VOUT pin */
struct system_pinmux_config pin_conf;
system_pinmux_get_config_defaults(&pin_conf);
/* Set up the DAC VOUT pin */
pin_conf.mux_position = MUX_PA02B_DAC_VOUT;
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT, &pin_conf);
/* Write configuration to module */
_dac_set_config(module_inst, config);
/* Store reference selection for later use */
module_inst->reference = config->reference;
#if DAC_CALLBACK_MODE == true
for (uint8_t i = 0; i < DAC_CALLBACK_N; i++) {
module_inst->callback[i] = NULL;
};
_dac_instances[0] = module_inst;
#endif
return STATUS_OK;
}
/**
* \brief Resets the DAC module.
*
* This function will reset the DAC module to its power on default values and
* disable it.
*
* \param[in] module_inst Pointer to the DAC software instance struct
*/
void dac_reset(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
/* Software reset the module */
dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
}
/**
* \brief Enable the DAC module.
*
* Enables the DAC interface and the selected output. If any internal reference
* is selected it will be enabled.
*
* \param[in] module_inst Pointer to the DAC software instance struct
*
*/
void dac_enable(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
/* Enable selected output */
dac_module->CTRLB.reg |= module_inst->output;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
/* Enable the module */
dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
/* Enable internal bandgap reference if selected in the configuration */
if (module_inst->reference == DAC_REFERENCE_INT1V) {
#if (SAMC21)
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
}
if(dac_module->CTRLA.reg & DAC_CTRLA_ENABLE) {
while(! (dac_module->STATUS.reg & DAC_STATUS_READY)) {
};
}
#else
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_BANDGAP);
}
#endif
}
/**
* \brief Disable the DAC module.
*
* Disables the DAC interface and the output buffer.
*
* \param[in] module_inst Pointer to the DAC software instance struct
*
*/
void dac_disable(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
/* Wait until the synchronization is complete */
while (dac_is_syncing(module_inst)) {
};
/* Disable DAC */
dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
}
/**
* \brief Enables a DAC event input or output.
*
* Enables one or more input or output events to or from the DAC module. See
* \ref dac_events "here" for a list of events this module supports.
*
* \note Events cannot be altered while the module is enabled.
*
* \param[in] module_inst Software instance for the DAC peripheral
* \param[in] events Struct containing flags of events to enable
*/
void dac_enable_events(
struct dac_module *const module_inst,
struct dac_events *const events)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
Dac *const dac_module = module_inst->hw;
uint32_t event_mask = 0;
#if(SAMC21)
/* Configure Enable Inversion of input event */
if (events->generate_event_on_chan_falling_edge) {
event_mask |= DAC_EVCTRL_INVEI;
}
#endif
/* Configure Buffer Empty event */
if (events->generate_event_on_buffer_empty) {
event_mask |= DAC_EVCTRL_EMPTYEO;
}
/* Configure Conversion Start event */
if (events->on_event_start_conversion) {
event_mask |= DAC_EVCTRL_STARTEI;
module_inst->start_on_event = true;
}
dac_module->EVCTRL.reg |= event_mask;
}
/**
* \brief Disables a DAC event input or output.
*
* Disables one or more input or output events to or from the DAC module. See
* \ref dac_events "here" for a list of events this module supports.
*
* \note Events cannot be altered while the module is enabled.
*
* \param[in] module_inst Software instance for the DAC peripheral
* \param[in] events Struct containing flags of events to disable
*/
void dac_disable_events(
struct dac_module *const module_inst,
struct dac_events *const events)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
Dac *const dac_module = module_inst->hw;
uint32_t event_mask = 0;
/* Configure Buffer Empty event */
if (events->generate_event_on_buffer_empty) {
event_mask |= DAC_EVCTRL_EMPTYEO;
}
/* Configure Conversion Start event */
if (events->on_event_start_conversion) {
event_mask |= DAC_EVCTRL_STARTEI;
module_inst->start_on_event = false;
}
dac_module->EVCTRL.reg &= ~event_mask;
}
/**
* \brief Initializes a DAC channel configuration structure to defaults.
*
* Initializes a given DAC channel configuration structure to a set of
* known default values. This function should be called on any new
* instance of the configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li Start Conversion Event Input enabled
* \li Start Data Buffer Empty Event Output disabled
*
* \param[out] config Configuration structure to initialize to default values
*/
void dac_chan_get_config_defaults(
struct dac_chan_config *const config)
{
/* Sanity check arguments */
Assert(config);
}
/**
* \brief Writes a DAC channel configuration to the hardware module.
*
* Writes a given channel configuration to the hardware module.
*
* \note The DAC device instance structure must be initialized before calling
* this function.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to configure
* \param[in] config Pointer to the configuration struct
*
*/
void dac_chan_set_config(
struct dac_module *const module_inst,
const enum dac_channel channel,
struct dac_chan_config *const config)
{
/* No channel support yet */
UNUSED(channel);
}
/**
* \brief Enable a DAC channel.
*
* Enables the selected DAC channel.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to enable
*
*/
void dac_chan_enable(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* No channel support yet */
UNUSED(channel);
}
/**
* \brief Disable a DAC channel.
*
* Disables the selected DAC channel.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to disable
*
*/
void dac_chan_disable(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* No channel support yet */
UNUSED(channel);
}
/**
* \brief Enable the output buffer.
*
* Enables the output buffer and drives the DAC output to the VOUT pin.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel DAC channel to alter
*/
void dac_chan_enable_output_buffer(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* No channel support yet */
UNUSED(channel);
Dac *const dac_module = module_inst->hw;
/* Enable output buffer */
dac_module->CTRLB.reg |= DAC_OUTPUT_EXTERNAL;
}
/**
* \brief Disable the output buffer.
*
* Disables the output buffer.
*
* \note The output buffer(s) should be disabled when a channel's output is not
* currently needed, as it will draw current even if the system is in
* sleep mode.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel DAC channel to alter
*/
void dac_chan_disable_output_buffer(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* Sanity check arguments*/
Assert(module_inst);
Assert(module_inst->hw);
/* No channel support yet */
UNUSED(channel);
Dac *const dac_module = module_inst->hw;
/* Disable output buffer */
dac_module->CTRLB.reg &= ~DAC_OUTPUT_EXTERNAL;
}
/**
* \brief Write to the DAC.
*
* This function writes to the DATA or DATABUF register.
* If the conversion is not event-triggered, the data will be written to
* the DATA register and the conversion will start.
* If the conversion is event-triggered, the data will be written to DATABUF
* and transferred to the DATA register and converted when a Start Conversion
* Event is issued.
* Conversion data must be right or left adjusted according to configuration
* settings.
* \note To be event triggered, the enable_start_on_event must be
* enabled in the configuration.
*
* \param[in] module_inst Pointer to the DAC software device struct
* \param[in] channel DAC channel to write to
* \param[in] data Conversion data
*
* \return Status of the operation.
* \retval STATUS_OK If the data was written
*/
enum status_code dac_chan_write(
struct dac_module *const module_inst,
enum dac_channel channel,
const uint16_t data)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* No channel support yet */
UNUSED(channel);
Dac *const dac_module = module_inst->hw;
/* Wait until the synchronization is complete */
while (dac_is_syncing(module_inst)) {
};
if (module_inst->start_on_event) {
/* Write the new value to the buffered DAC data register */
dac_module->DATABUF.reg = data;
} else {
/* Write the new value to the DAC data register */
dac_module->DATA.reg = data;
}
return STATUS_OK;
}
/**
* \brief Write to the DAC.
*
* This function converts a specific number of digital data.
* The conversion should be event-triggered, the data will be written to DATABUF
* and transferred to the DATA register and converted when a Start Conversion
* Event is issued.
* Conversion data must be right or left adjusted according to configuration
* settings.
* \note To be event triggered, the enable_start_on_event must be
* enabled in the configuration.
*
* \param[in] module_inst Pointer to the DAC software device struct
* \param[in] channel DAC channel to write to
* \param[in] buffer Pointer to the digital data write buffer to be converted
* \param[in] length Length of the write buffer
*
* \return Status of the operation.
* \retval STATUS_OK If the data was written or no data conversion required
* \retval STATUS_ERR_UNSUPPORTED_DEV The DAC is not configured as using event trigger
* \retval STATUS_BUSY The DAC is busy to convert
*/
enum status_code dac_chan_write_buffer_wait(
struct dac_module *const module_inst,
enum dac_channel channel,
uint16_t *buffer,
uint32_t length)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
/* No channel support yet */
UNUSED(channel);
Dac *const dac_module = module_inst->hw;
/* Wait until the synchronization is complete */
while (dac_is_syncing(module_inst)) {
};
/* Zero length request */
if (length == 0) {
/* No data to be converted */
return STATUS_OK;
}
#if DAC_CALLBACK_MODE == true
/* Check if busy */
if (module_inst->job_status == STATUS_BUSY) {
return STATUS_BUSY;
}
#endif
/* Only support event triggered conversion */
if (module_inst->start_on_event == false) {
return STATUS_ERR_UNSUPPORTED_DEV;
}
/* Blocks while buffer is being transferred */
while (length--) {
/* Convert one data */
dac_chan_write(module_inst, channel, buffer[length]);
/* Wait until Transmit is complete or timeout */
for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) {
if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY) {
break;
} else if (i == DAC_TIMEOUT) {
return STATUS_ERR_TIMEOUT;
}
}
}
return STATUS_OK;
}
/**
* \brief Retrieves the current module status
*
* Checks the status of the module and returns it as a bitmask of status
* flags.
*
* \param[in] module_inst Pointer to the DAC software device struct
*
* \return Bitmask of status flags.
*
* \retval DAC_STATUS_CHANNEL_0_EMPTY Data has been transferred from DATABUF
* to DATA by a start conversion event
* and DATABUF is ready for new data
* \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred
* when DATABUF is empty
*
*/
uint32_t dac_get_status(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
uint8_t intflags = dac_module->INTFLAG.reg;
uint32_t status_flags = 0;
if (intflags & DAC_INTFLAG_EMPTY) {
status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
}
if (intflags & DAC_INTFLAG_UNDERRUN) {
status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
}
return status_flags;
}
/**
* \brief Clears a module status flag
*
* Clears the given status flag of the module.
*
* \param[in] module_inst Pointer to the DAC software device struct
* \param[in] status_flags Bit mask of status flags to clear
*
*/
void dac_clear_status(
struct dac_module *const module_inst,
uint32_t status_flags)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
uint32_t intflags = 0;
if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) {
intflags |= DAC_INTFLAG_EMPTY;
}
if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) {
intflags |= DAC_INTFLAG_UNDERRUN;
}
dac_module->INTFLAG.reg = intflags;
}

635
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAMD21/dac_feature.h
View File

@ -1,635 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Digital-to-Analog Converter Driver
*
* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef DAC_FEATURE_H_INCLUDED
#define DAC_FEATURE_H_INCLUDED
/**
* \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog Driver (DAC)
*
* This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the conversion of
* digital values to analog voltage. The following driver API modes are covered
* by this manual:
*
* - Polled APIs
* \if DAC_CALLBACK_MODE
* - Callback APIs
* \endif
*
* The following peripherals are used by this module:
* - DAC (Digital-to-Analog Converter)
*
* The following devices can use this module:
* - Atmel | SMART SAM D20/D21
* - Atmel | SMART SAM D10/D11
* - Atmel | SMART SAM DA0/DA1
* - Atmel | SMART SAM C21
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_dac_prerequisites
* - \ref asfdoc_sam0_dac_module_overview
* - \ref asfdoc_sam0_dac_special_considerations
* - \ref asfdoc_sam0_dac_extra_info
* - \ref asfdoc_sam0_dac_examples
* - \ref asfdoc_sam0_dac_api_overview
*
*
* \section asfdoc_sam0_dac_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_dac_module_overview Module Overview
*
* The Digital-to-Analog converter converts a digital value to analog voltage.
* The SAM DAC module has one channel with 10-bit resolution,
* and is capable of converting up to 350k samples per second (ksps).
*
* A common use of DAC is to generate audio signals by connecting the DAC
* output to a speaker, or to generate a reference voltage; either for an
* external circuit or an internal peripheral such as the Analog Comparator.
*
* After being set up, the DAC will convert new digital values written to the
* conversion data register (DATA) to an analog value either on the VOUT pin of
* the device, or internally for use as an input to the AC, ADC, and other analog
* modules.
*
* Writing the DATA register will start a new conversion. It is also possible
* to trigger the conversion from the event system.
*
* A simplified block diagram of the DAC can be seen in
* \ref asfdoc_sam0_dac_module_block_diagram "the figure below".
*
* \anchor asfdoc_sam0_dac_module_block_diagram
* \image html dac_block_diagram.svg "DAC Block Diagram"
*
* \subsection asfdoc_sam0_dac_conversion_range Conversion Range
* The conversion range is between GND and the selected voltage reference.
* Available voltage references are:
* \li AVCC voltage reference
* \li Internal 1V reference (INT1V)
* \li External voltage reference (AREF)
*
* \note Internal references will be enabled by the driver, but not disabled.
* Any reference not used by the application should be disabled by the application.
*
* The output voltage from a DAC channel is given as:
* \f[
* V_{OUT} = \frac{DATA}{0x3FF} \times VREF
* \f]
*
* \subsection asfdoc_sam0_dac_conversion Conversion
* The digital value written to the conversion data register (DATA) will be
* converted to an analog value.
* Writing the DATA register will start a new conversion.
* It is also possible to write the conversion data to the DATABUF register,
* the writing of the DATA register can then be triggered from the event
* system, which will load the value from DATABUF to DATA.
*
* \subsection asfdoc_sam0_dac_analog_output Analog Output
* The analog output value can be output to either the VOUT pin or internally,
* but not both at the same time.
*
* \subsubsection asfdoc_sam0_dac_analog_output_external External Output
* The output buffer must be enabled in order to drive the DAC output to the
* VOUT pin. Due to the output buffer, the DAC has high drive strength, and is
* capable of driving both resistive and capacitive loads, as well as loads
* which combine both.
*
* \subsubsection asfdoc_sam0_dac_analog_output_internal Internal Output
* The analog value can be internally available for use as input to the
* AC or ADC modules.
*
* \subsection asfdoc_sam0_dac_events Events
* Events generation and event actions are configurable in the DAC.
* The DAC has one event line input and one event output: <i>Start Conversion</i>
* and <i>Data Buffer Empty</i>.
*
* If the Start Conversion input event is enabled in the module configuration,
* an incoming event will load data from the data buffer to the data register
* and start a new conversion. This method synchronizes conversions with
* external events (such as those from a timer module) and ensures regular and
* fixed conversion intervals.
*
* If the Data Buffer Empty output event is enabled in the module configuration,
* events will be generated when the DAC data buffer register becomes empty and
* new data can be loaded to the buffer.
*
* \note The connection of events between modules requires the use of the
* \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
* to route output event of one module to the the input event of another.
* For more information on event routing, refer to the event driver
* documentation.
*
* \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values
* The 10-bit input value to the DAC is contained in a 16-bit register. This
* can be configured to be either left or right adjusted. In
* \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are
* shown, and the position of the most (MSB) and the least (LSB) significant bits
* are indicated. The unused bits should always be written to zero.
*
* \anchor asfdoc_sam0_dac_module_adj_modes
* \dot
* digraph {
* subgraph cluster_right {
* msbl [label="MSB", shape=none, group="msbl"];
* lsbl [label="LSB", shape=none];
* node [shape=none];
* color="white";
* reg_left [label=<
* <table cellspacing="0" cellpadding="2" width="100%">
* <tr>
* <td port="msb">15</td>
* <td>14</td>
* <td>13</td>
* <td>12</td>
* <td>11</td>
* <td>10</td>
* <td>9</td>
* <td>8</td>
* <td>7</td>
* <td port="lsb">6</td>
* <td>5</td>
* <td>4</td>
* <td>3</td>
* <td>2</td>
* <td>1</td>
* <td>0</td>
* </tr>
* <tr>
* <td COLSPAN="10"> DATA[9:0] </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* </tr>
* </table>
* >];
* msbl -> reg_left:msb:n;
* lsbl -> reg_left:lsb;
* label ="Left adjusted.\n";
* }
* subgraph cluster_left {
* rankdir=TB;
* msb [label="MSB", shape=none];
* lsb [label="LSB", shape=none];
* color="white";
* node [shape=none];
* reg_right [label=<
* <table cellspacing="0" cellpadding="2">
* <tr>
* <td>15</td>
* <td>14</td>
* <td>13</td>
* <td>12</td>
* <td>11</td>
* <td>10</td>
* <td port="msb">9</td>
* <td>8</td>
* <td>7</td>
* <td>6</td>
* <td>5</td>
* <td>4</td>
* <td>3</td>
* <td>2</td>
* <td>1</td>
* <td port="lsb">0</td>
* </tr>
* <tr>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td COLSPAN="10"> DATA[9:0] </td>
* </tr>
* </table>
* >];
* msb -> reg_right:msb;
* lsb -> reg_right:lsb:n;
* label = "Right adjusted.\n";
* graph [shape=none];
* }
* }
* \enddot
*
* \subsection asfdoc_sam0_dac_clk_sources Clock Sources
* The clock for the DAC interface (CLK_DAC) is generated by the Power Manager.
* This clock is turned on by default, and can be enabled and disabled in the
* Power Manager.
*
* Additionally, an asynchronous clock source (GCLK_DAC) is required.
* These clocks are normally disabled by default. The selected clock source
* must be enabled in the Power Manager before it can be used by the DAC.
* The DAC core operates asynchronously from the user interface and
* peripheral bus. As a consequence, the DAC needs two clock cycles of both
* CLK_DAC and GCLK_DAC to synchronize the values written to some of the
* control and data registers.
* The oscillator source for the GCLK_DAC clock is selected in the System
* Control Interface (SCIF).
*
* \section asfdoc_sam0_dac_special_considerations Special Considerations
*
* \subsection asfdoc_sam0_dac_special_considerations_output_buffer Output Driver
* The DAC can only do conversions in Active or Idle modes. However, if the
* output buffer is enabled it will draw current even if the system is in
* sleep mode. Therefore, always make sure that the output buffer is not
* enabled when it is not needed, to ensure minimum power consumption.
*
* \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time
* DAC conversion time is approximately 2.85µs. The user must ensure that new
* data is not written to the DAC before the last conversion is complete.
* Conversions should be triggered by a periodic event from a Timer/Counter or
* another peripheral.
*
*
* \section asfdoc_sam0_dac_extra_info Extra Information
*
* For extra information, see \ref asfdoc_sam0_dac_extra. This includes:
* - \ref asfdoc_sam0_dac_extra_acronyms
* - \ref asfdoc_sam0_dac_extra_dependencies
* - \ref asfdoc_sam0_dac_extra_errata
* - \ref asfdoc_sam0_dac_extra_history
*
*
* \section asfdoc_sam0_dac_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_dac_exqsg.
*
*
* \section asfdoc_sam0_dac_api_overview API Overview
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <compiler.h>
#include <clock.h>
#include <gclk.h>
/**
* \name DAC Status Flags
*
* DAC status flags, returned by \ref dac_get_status() and cleared by
* \ref dac_clear_status().
* @{
*/
/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF
* to DATA by a start conversion event and DATABUF is ready for new data.
*/
#define DAC_STATUS_CHANNEL_0_EMPTY (1UL << 0)
/** Under-run Channel 0 - Set when a start conversion event occurs when
* DATABUF is empty.
*/
#define DAC_STATUS_CHANNEL_0_UNDERRUN (1UL << 1)
/** @} */
/**
* \brief DAC reference voltage enum.
*
* Enum for the possible reference voltages for the DAC.
*/
enum dac_reference {
/** 1V from the internal band-gap reference.*/
DAC_REFERENCE_INT1V = DAC_CTRLB_REFSEL(0),
/** Analog V<SUB>CC</SUB> as reference. */
DAC_REFERENCE_AVCC = DAC_CTRLB_REFSEL(1),
/** External reference on AREF. */
DAC_REFERENCE_AREF = DAC_CTRLB_REFSEL(2),
};
/**
* \brief DAC output selection enum.
*
* Enum for the DAC output selection.
*/
enum dac_output {
/** DAC output to VOUT pin */
DAC_OUTPUT_EXTERNAL = DAC_CTRLB_EOEN,
/** DAC output as internal reference */
DAC_OUTPUT_INTERNAL = DAC_CTRLB_IOEN,
/** No output */
DAC_OUTPUT_NONE = 0,
};
/**
* \brief DAC channel selection enum.
*
* Enum for the DAC channel selection.
*/
enum dac_channel {
/** DAC output channel 0. */
DAC_CHANNEL_0,
};
/**
* \brief DAC software device instance structure.
*
* DAC software instance structure, used to retain software state information
* of an associated hardware module instance.
*
* \note The fields of this structure should not be altered by the user
* application; they are reserved for module-internal use only.
*/
struct dac_module {
#if !defined(__DOXYGEN__)
/** DAC hardware module. */
Dac *hw;
/** DAC output selection. */
enum dac_output output;
/** Reference selection. */
enum dac_reference reference;
/** DAC event selection. */
bool start_on_event;
# if DAC_CALLBACK_MODE == true
/** Pointer to buffer used for ADC results. */
volatile uint16_t *job_buffer;
/** Remaining number of conversions in current job. */
volatile uint16_t remaining_conversions;
/** Transferred number of conversions in current job. */
volatile uint16_t transferred_conversions;
/** DAC callback enable. */
bool callback_enable[DAC_CALLBACK_N];
/** DAC registered callback functions. */
dac_callback_t callback[DAC_CALLBACK_N];
/** Holds the status of the ongoing or last conversion job. */
volatile enum status_code job_status;
# endif
#endif
};
/**
* \brief DAC configuration structure.
*
* Configuration structure for a DAC instance. This structure should be
* initialized by the \ref dac_get_config_defaults()
* function before being modified by the user application.
*/
struct dac_config {
/** Reference voltage. */
enum dac_reference reference;
/** Select DAC output. */
enum dac_output output;
/** Left adjusted data. */
bool left_adjust;
/** GCLK generator used to clock the peripheral. */
enum gclk_generator clock_source;
#ifdef FEATURE_DAC_DATABUF_WRITE_PROTECTION
/** Bypass DATABUF write protection. */
bool databuf_protection_bypass;
#endif
/** Voltage pump disable. */
bool voltage_pump_disable;
/**
* The DAC behaves as in normal mode when the chip enters STANDBY sleep
* mode.
*/
bool run_in_standby;
#if (SAMC21)
/** Dither mode enable data. */
bool dither_mode;
#endif
};
/**
* \brief DAC event enable/disable structure.
*
* Event flags for the DAC module. This is used to enable and
* disable events via \ref dac_enable_events() and \ref dac_disable_events().
*/
struct dac_events {
/** Start a new DAC conversion. */
bool on_event_start_conversion;
/** Enable event generation on data buffer empty. */
bool generate_event_on_buffer_empty;
#if (SAMC21)
/** Enable the falling edge of the input event for DAC1. */
bool generate_event_on_chan_falling_edge;
#endif
};
/**
* \brief DAC channel configuration structure
*
* Configuration for a DAC channel. This structure should be initialized by the
* \ref dac_chan_get_config_defaults() function before being modified by the
* user application.
*/
struct dac_chan_config {
#if !defined(__DOXYGEN__)
/** Dummy value to ensure the struct has at least one member. */
uint8_t _dummy;
#endif
};
/**
* \name Configuration and Initialization (Channel)
* @{
*/
void dac_chan_enable_output_buffer(
struct dac_module *const dev_inst,
const enum dac_channel channel);
void dac_chan_disable_output_buffer(
struct dac_module *const dev_inst,
const enum dac_channel channel);
/** @} */
/** @} */
/**
* \page asfdoc_sam0_dac_extra Extra Information for DAC Driver
*
* \section asfdoc_sam0_dac_extra_acronyms Acronyms
* The table below presents the acronyms used in this module:
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>ADC</td>
* <td>Analog-to-Digital Converter</td>
* </tr>
* <tr>
* <td>AC</td>
* <td>Analog Comparator</td>
* </tr>
* <tr>
* <td>DAC</td>
* <td>Digital-to-Analog Converter</td>
* </tr>
* <tr>
* <td>LSB</td>
* <td>Least Significant Bit</td>
* </tr>
* <tr>
* <td>MSB</td>
* <td>Most Significant Bit</td>
* </tr>
* <tr>
* <td>DMA</td>
* <td>Direct Memory Access</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_dac_extra_dependencies Dependencies
* This driver has the following dependencies:
*
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
*
*
* \section asfdoc_sam0_dac_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_dac_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Add configuration for using 14-bit hardware dithering (SAMC21 support)</td>
* </tr>
* <tr>
* <td>Added new configuration parameters \c databuf_protection_bypass,
* \c voltage_pump_disable. Added new callback functions
* \c dac_chan_write_buffer_wait,
* \c dac_chan_write_buffer_job, \c dac_chan_write_job,
* \c dac_get_job_status, \c dac_abort_job and new callback type
* \c DAC_CALLBACK_TRANSFER_COMPLETE for DAC conversion job</td>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_dac_exqsg Examples for DAC Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that a QSG can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_dac_basic_use_case
* \if DAC_CALLBACK_MODE
* - \subpage asfdoc_sam0_dac_basic_use_case_callback
* \endif
* \if DAC_DMA_USE_MODE_SELECTION
* - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma
* \endif
*
* \if DAC_DMA_USE_MODE_SELECTION
* \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC
* For this examples, see
* \ref asfdoc_sam0_adc_dma_use_case
* \endif
*
* \page asfdoc_sam0_dac_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>42110E</td>
* <td>06/2015</td>
* <td>Add SAMC21 and SAMDAx support</td>
* </tr>
* <tr>
* <td>42110D</td>
* <td>12/2014</td>
* <td>Add SAMD10/D11 support</td>
* </tr>
* <tr>
* <td>42110C</td>
* <td>01/2014</td>
* <td>Add SAMD21 support</td>
* </tr>
* <tr>
* <td>42110B</td>
* <td>06/2013</td>
* <td>Added additional documentation on the event system. Corrected
* documentation typos.</td>
* </tr>
* <tr>
* <td>42110A</td>
* <td>06/2013</td>
* <td>Initial document release</td>
* </tr>
* </table>
*/
#ifdef __cplusplus
}
#endif
#endif /* DAC_FEATURE_H_INCLUDED */

790
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac.c
View File

@ -1,790 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Digital-to-Analog Converter Driver
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include "dac.h"
#include <system.h>
#include <pinmux.h>
/**
* \internal Writes a DAC configuration to the hardware module.
*
* Writes out a given configuration to the hardware module.
*
* \param[out] module_inst Pointer to the DAC software instance struct
* \param[in] config Pointer to the configuration struct
*
*/
static void _dac_set_config(
struct dac_module *const module_inst,
struct dac_config *const config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(config);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
/* Set selected DAC start on event to be disable when enabling the module */
module_inst->start_on_event[DAC_CHANNEL_0] = false;
module_inst->start_on_event[DAC_CHANNEL_1] = false;
uint32_t new_ctrlb = 0;
/* Enable DAC in differential mode if configured */
if (config->differential_mode) {
new_ctrlb |= DAC_CTRLB_DIFF;
}
/* Set reference voltage */
new_ctrlb |= config->reference;
/* Apply the new configuration to the hardware module */
dac_module->CTRLB.reg = new_ctrlb;
}
/**
* \brief Determines if the hardware module(s) are currently synchronizing to the bus.
*
* Checks to see if the underlying hardware peripheral module(s) are currently
* synchronizing across multiple clock domains to the hardware bus. This
* function can be used to delay further operations on a module until such time
* that it is ready, to prevent blocking delays for synchronization in the
* user application.
*
* \param[in] dev_inst Pointer to the DAC software instance struct
*
* \return Synchronization status of the underlying hardware module(s).
*
* \retval true If the module synchronization is ongoing
* \retval false If the module has completed synchronization
*/
bool dac_is_syncing(
struct dac_module *const dev_inst)
{
/* Sanity check arguments */
Assert(dev_inst);
Dac *const dac_module = dev_inst->hw;
if (dac_module->SYNCBUSY.reg) {
return true;
}
return false;
}
/**
* \brief Initializes a DAC configuration structure to defaults.
*
* Initializes a given DAC configuration structure to a set of
* known default values. This function should be called on any new
* instance of the configuration structures before being modified by the
* user application.
*
* The default configuration is as follows:
* \li 1V from internal bandgap reference
* \li Drive the DAC output to the VOUT pin
* \li Right adjust data
* \li GCLK generator 0 (GCLK main) clock source
* \li The output buffer is disabled when the chip enters STANDBY sleep
* mode
*
* \param[out] config Configuration structure to initialize to default values
*/
void dac_get_config_defaults(
struct dac_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Default configuration values */
config->differential_mode = false;
config->reference = DAC_REFERENCE_INTREF;
config->clock_source = GCLK_GENERATOR_0;
}
/**
* \brief Initialize the DAC device struct.
*
* Use this function to initialize the Digital to Analog Converter. Resets the
* underlying hardware module and configures it.
*
* \note The DAC channel must be configured separately.
*
* \param[out] module_inst Pointer to the DAC software instance struct
* \param[in] module Pointer to the DAC module instance
* \param[in] config Pointer to the config struct, created by the user
* application
*
* \return Status of initialization.
* \retval STATUS_OK Module initiated correctly
* \retval STATUS_ERR_DENIED If module is enabled
* \retval STATUS_BUSY If module is busy resetting
*/
enum status_code dac_init(
struct dac_module *const module_inst,
Dac *const module,
struct dac_config *const config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module);
Assert(config);
/* Initialize device instance */
module_inst->hw = module;
/* Turn on the digital interface clock */
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBC, MCLK_APBCMASK_DAC);
/* Check if module is enabled. */
if (module->CTRLA.reg & DAC_CTRLA_ENABLE) {
return STATUS_ERR_DENIED;
}
/* Check if reset is in progress. */
if (module->CTRLA.reg & DAC_CTRLA_SWRST) {
return STATUS_BUSY;
}
/* Configure GCLK channel and enable clock */
struct system_gclk_chan_config gclk_chan_conf;
system_gclk_chan_get_config_defaults(&gclk_chan_conf);
gclk_chan_conf.source_generator = config->clock_source;
system_gclk_chan_set_config(DAC_GCLK_ID, &gclk_chan_conf);
system_gclk_chan_enable(DAC_GCLK_ID);
/* Write configuration to module */
_dac_set_config(module_inst, config);
/* Store reference selection for later use */
module_inst->reference = config->reference;
#if DAC_CALLBACK_MODE == true
for (uint8_t i = 0; i < DAC_CHANNEL_N; i++) {
for (uint8_t j = 0; j < DAC_CALLBACK_N; j++) {
module_inst->callback[i][j] = NULL;
}
};
_dac_instances[0] = module_inst;
#endif
return STATUS_OK;
}
/**
* \brief Resets the DAC module.
*
* This function will reset the DAC module to its power on default values and
* disable it.
*
* \param[in] module_inst Pointer to the DAC software instance struct
*/
void dac_reset(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
/* Software reset the module */
dac_module->CTRLA.reg |= DAC_CTRLA_SWRST;
}
/**
* \brief Enable the DAC module.
*
* Enables the DAC interface and the selected output. If any internal reference
* is selected it will be enabled.
*
* \param[in] module_inst Pointer to the DAC software instance struct
*
*/
void dac_enable(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
/* Enable the module */
dac_module->CTRLA.reg |= DAC_CTRLA_ENABLE;
/* Enable internal bandgap reference if selected in the configuration */
if (module_inst->reference == DAC_REFERENCE_INTREF) {
system_voltage_reference_enable(SYSTEM_VOLTAGE_REFERENCE_OUTPUT);
}
if(dac_module->DACCTRL[DAC_CHANNEL_0].reg & DAC_DACCTRL_ENABLE) {
while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_0 + 1))) {
};
} else if(dac_module->DACCTRL[DAC_CHANNEL_1].reg & DAC_DACCTRL_ENABLE) {
while(! (dac_module->STATUS.reg & DAC_STATUS_READY(DAC_CHANNEL_1 + 1))) {
};
}
}
/**
* \brief Disable the DAC module.
*
* Disables the DAC interface and the output buffer.
*
* \param[in] module_inst Pointer to the DAC software instance struct
*
*/
void dac_disable(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
/* Disable DAC */
dac_module->CTRLA.reg &= ~DAC_CTRLA_ENABLE;
}
/**
* \brief Enables a DAC event input or output.
*
* Enables one or more input or output events to or from the DAC module. See
* \ref dac_events "Struct dac_events" for a list of events this module supports.
*
* \note Events cannot be altered while the module is enabled.
*
* \param[in] module_inst Software instance for the DAC peripheral
* \param[in] events Struct containing flags of events to enable
*/
void dac_enable_events(
struct dac_module *const module_inst,
struct dac_events *const events)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
Dac *const dac_module = module_inst->hw;
uint32_t event_mask = 0;
/* Configure Enable Inversion of input event */
if (events->generate_event_on_chan0_falling_edge) {
event_mask |= DAC_EVCTRL_INVEI0;
}
/* Configure Enable Inversion of input event */
if (events->generate_event_on_chan1_falling_edge) {
event_mask |= DAC_EVCTRL_INVEI1;
}
/* Configure Buffer Empty event */
if (events->generate_event_on_chan0_buffer_empty) {
event_mask |= DAC_EVCTRL_EMPTYEO0;
}
/* Configure Buffer Empty event */
if (events->generate_event_on_chan1_buffer_empty) {
event_mask |= DAC_EVCTRL_EMPTYEO1;
}
/* Configure Conversion Start event */
if (events->on_event_chan0_start_conversion) {
event_mask |= DAC_EVCTRL_STARTEI0;
module_inst->start_on_event[DAC_CHANNEL_0] = true;
}
/* Configure Conversion Start event */
if (events->on_event_chan1_start_conversion) {
event_mask |= DAC_EVCTRL_STARTEI1;
module_inst->start_on_event[DAC_CHANNEL_1] = true;
}
dac_module->EVCTRL.reg |= event_mask;
}
/**
* \brief Disables a DAC event input or output.
*
* Disables one or more input or output events to or from the DAC module. See
* \ref dac_events "Struct dac_events" for a list of events this module supports.
*
* \note Events cannot be altered while the module is enabled.
*
* \param[in] module_inst Software instance for the DAC peripheral
* \param[in] events Struct containing flags of events to disable
*/
void dac_disable_events(
struct dac_module *const module_inst,
struct dac_events *const events)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(events);
Dac *const dac_module = module_inst->hw;
uint32_t event_mask = 0;
/* Configure Buffer Empty event */
if (events->on_event_chan0_start_conversion) {
event_mask |= DAC_EVCTRL_EMPTYEO0;
}
/* Configure Buffer Empty event */
if (events->on_event_chan1_start_conversion) {
event_mask |= DAC_EVCTRL_EMPTYEO1;
}
/* Configure Conversion Start event */
if (events->generate_event_on_chan0_buffer_empty) {
event_mask |= DAC_EVCTRL_STARTEI0;
module_inst->start_on_event[DAC_CHANNEL_0] = false;
}
/* Configure Conversion Start event */
if (events->generate_event_on_chan0_buffer_empty) {
event_mask |= DAC_EVCTRL_STARTEI1;
module_inst->start_on_event[DAC_CHANNEL_1] = false;
}
dac_module->EVCTRL.reg &= ~event_mask;
}
void dac_chan_get_config_defaults(
struct dac_chan_config *const config)
{
/* Sanity check arguments */
Assert(config);
/* Dac channel default configuration values */
config->left_adjust = false;
config->current = DAC_CURRENT_12M;
config->run_in_standby = false;
config->dither_mode = false;
config->refresh_period = 1;
}
/**
* \brief Writes a DAC channel configuration to the hardware module.
*
* Writes out a given channel configuration to the hardware module.
*
* \note The DAC device instance structure must be initialized before calling
* this function.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to configure
* \param[in] config Pointer to the configuration struct
*
*/
void dac_chan_set_config(
struct dac_module *const module_inst,
const enum dac_channel channel,
struct dac_chan_config *const config)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Assert(config);
/* MUX the DAC VOUT pin */
struct system_pinmux_config pin_conf;
system_pinmux_get_config_defaults(&pin_conf);
pin_conf.direction = SYSTEM_PINMUX_PIN_DIR_INPUT;
pin_conf.input_pull = SYSTEM_PINMUX_PIN_PULL_NONE;
if(channel == DAC_CHANNEL_0) {
/* Set up the DAC VOUT0 pin */
pin_conf.mux_position = MUX_PA02B_DAC_VOUT0;
system_pinmux_pin_set_config(PIN_PA02B_DAC_VOUT0, &pin_conf);
} else if(channel == DAC_CHANNEL_1) {
/* Set up the DAC VOUT1 pin */
pin_conf.mux_position = MUX_PA05B_DAC_VOUT1;
system_pinmux_pin_set_config(PIN_PA05B_DAC_VOUT1, &pin_conf);
}
Dac *const dac_module = module_inst->hw;
uint32_t new_dacctrl = 0;
/* Left adjust data if configured */
if (config->left_adjust) {
new_dacctrl |= DAC_DACCTRL_LEFTADJ;
}
/* Set current control */
new_dacctrl |= config->current;
/* Enable DAC in standby sleep mode if configured */
if (config->run_in_standby) {
new_dacctrl |= DAC_DACCTRL_RUNSTDBY;
}
/* Voltage pump disable if configured */
if (config->dither_mode) {
new_dacctrl |= DAC_DACCTRL_DITHER;
}
new_dacctrl |= DAC_DACCTRL_REFRESH(config->refresh_period);
/* Apply the new configuration to the hardware module */
dac_module->DACCTRL[channel].reg = new_dacctrl;
}
/**
* \brief Enable a DAC channel.
*
* Enables the selected DAC channel.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to enable
*
*/
void dac_chan_enable(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
/* Enable the module */
dac_module->DACCTRL[channel].reg |= DAC_DACCTRL_ENABLE;
}
/**
* \brief Disable a DAC channel.
*
* Disables the selected DAC channel.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to disable
*
*/
void dac_chan_disable(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
/* Enable the module */
dac_module->DACCTRL[channel].reg &= ~DAC_DACCTRL_ENABLE;
}
/**
* \brief Write to the DAC.
*
* This function writes to the DATA or DATABUF register.
* If the conversion is not event-triggered, the data will be written to
* the DATA register and the conversion will start.
* If the conversion is event-triggered, the data will be written to DATABUF
* and transferred to the DATA register and converted when a Start Conversion
* Event is issued.
* Conversion data must be right or left adjusted according to configuration
* settings.
* \note To be event triggered, the enable_start_on_event must be
* enabled in the configuration.
*
* \param[in] module_inst Pointer to the DAC software device struct
* \param[in] channel DAC channel to write to
* \param[in] data Conversion data
*
* \return Status of the operation.
* \retval STATUS_OK If the data was written
*/
enum status_code dac_chan_write(
struct dac_module *const module_inst,
enum dac_channel channel,
const uint16_t data)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
if (module_inst->start_on_event[channel]) {
/* Write the new value to the buffered DAC data register */
dac_module->DATABUF[channel].reg = data;
} else {
/* Write the new value to the DAC data register */
dac_module->DATA[channel].reg = data;
}
return STATUS_OK;
}
/**
* \brief Write to the DAC.
*
* This function converts a specific number of digital data.
* The conversion should be event-triggered, the data will be written to DATABUF
* and transferred to the DATA register and converted when a Start Conversion
* Event is issued.
* Conversion data must be right or left adjusted according to configuration
* settings.
* \note To be event triggered, the enable_start_on_event must be
* enabled in the configuration.
*
* \param[in] module_inst Pointer to the DAC software device struct
* \param[in] channel DAC channel to write to
* \param[in] buffer Pointer to the digital data write buffer to be converted
* \param[in] length Length of the write buffer
*
* \return Status of the operation.
* \retval STATUS_OK If the data was written or no data conversion required
* \retval STATUS_ERR_UNSUPPORTED_DEV The DAC is not configured as using event trigger
* \retval STATUS_BUSY The DAC is busy and can not do the conversion
*/
enum status_code dac_chan_write_buffer_wait(
struct dac_module *const module_inst,
enum dac_channel channel,
uint16_t *buffer,
uint32_t length)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
while (dac_is_syncing(module_inst)) {
/* Wait until the synchronization is complete */
}
/* Zero length request */
if (length == 0) {
/* No data to be converted */
return STATUS_OK;
}
#if DAC_CALLBACK_MODE == true
/* Check if busy */
if (module_inst->job_status[channel] == STATUS_BUSY) {
return STATUS_BUSY;
}
#endif
/* Only support event triggered conversion */
if (module_inst->start_on_event[channel] == false) {
return STATUS_ERR_UNSUPPORTED_DEV;
}
/* Blocks while buffer is being transferred */
while (length--) {
/* Convert one data */
dac_chan_write(module_inst, channel, buffer[length]);
/* Wait until Transmit is complete or timeout */
for (uint32_t i = 0; i <= DAC_TIMEOUT; i++) {
if(channel == DAC_CHANNEL_0) {
if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY0) {
break;
} else if (i == DAC_TIMEOUT) {
return STATUS_ERR_TIMEOUT;
}
} else if(channel == DAC_CHANNEL_1) {
if (dac_module->INTFLAG.reg & DAC_INTFLAG_EMPTY1) {
break;
} else if (i == DAC_TIMEOUT) {
return STATUS_ERR_TIMEOUT;
}
}
}
}
return STATUS_OK;
}
/**
* \brief Retrieves the status of DAC channel end of conversion.
*
* Checks if the conversion is completed or not and returns boolean flag
* of status.
*
* \param[in] module_inst Pointer to the DAC software instance struct
* \param[in] channel Channel to disable
*
* \retval true Conversion is complete, VOUT is stable
* \retval false No conversion completed since last load of DATA
*/
bool dac_chan_is_end_of_conversion(
struct dac_module *const module_inst,
enum dac_channel channel)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
if(dac_module->STATUS.reg & DAC_STATUS_EOC(channel + 1)) {
return true;
} else {
return false;
}
}
/**
* \brief Retrieves the current module status.
*
* Checks the status of the module and returns it as a bitmask of status
* flags.
*
* \param[in] module_inst Pointer to the DAC software device struct
*
* \return Bitmask of status flags.
*
* \retval DAC_STATUS_CHANNEL_0_EMPTY Data has been transferred from DATABUF
* to DATA by a start conversion event
* and DATABUF is ready for new data
* \retval DAC_STATUS_CHANNEL_0_UNDERRUN A start conversion event has occurred
* when DATABUF is empty
*
*/
uint32_t dac_get_status(
struct dac_module *const module_inst)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
uint8_t intflags = dac_module->INTFLAG.reg;
uint32_t status_flags = 0;
if (intflags & DAC_INTFLAG_EMPTY0) {
status_flags |= DAC_STATUS_CHANNEL_0_EMPTY;
}
if (intflags & DAC_INTFLAG_EMPTY1) {
status_flags |= DAC_STATUS_CHANNEL_1_EMPTY;
}
if (intflags & DAC_INTFLAG_UNDERRUN0) {
status_flags |= DAC_STATUS_CHANNEL_0_UNDERRUN;
}
if (intflags & DAC_INTFLAG_UNDERRUN1) {
status_flags |= DAC_STATUS_CHANNEL_1_UNDERRUN;
}
return status_flags;
}
/**
* \brief Clears a module status flag.
*
* Clears the given status flag of the module.
*
* \param[in] module_inst Pointer to the DAC software device struct
* \param[in] status_flags Bit mask of status flags to clear
*
*/
void dac_clear_status(
struct dac_module *const module_inst,
uint32_t status_flags)
{
/* Sanity check arguments */
Assert(module_inst);
Assert(module_inst->hw);
Dac *const dac_module = module_inst->hw;
uint32_t intflags = 0;
if (status_flags & DAC_STATUS_CHANNEL_0_EMPTY) {
intflags |= DAC_INTFLAG_EMPTY0;
}
if (status_flags & DAC_STATUS_CHANNEL_1_EMPTY) {
intflags |= DAC_INTFLAG_EMPTY1;
}
if (status_flags & DAC_STATUS_CHANNEL_0_UNDERRUN) {
intflags |= DAC_INTFLAG_UNDERRUN0;
}
if (status_flags & DAC_STATUS_CHANNEL_1_UNDERRUN) {
intflags |= DAC_INTFLAG_UNDERRUN1;
}
dac_module->INTFLAG.reg = intflags;
}

611
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/TARGET_SAML21/dac_feature.h
View File

@ -1,611 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Digital-to-Analog Converter Driver
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef DAC_FEATURE_H_INCLUDED
#define DAC_FEATURE_H_INCLUDED
/**
* \defgroup asfdoc_sam0_dac_group SAM Digital-to-Analog (DAC) Driver
*
* This driver for Atmel&reg; | SMART ARM&reg;-based microcontrollers provides an interface for the conversion of
* digital values to analog voltage. The following driver API modes are covered
* by this manual:
*
* - Polled APIs
* \if DAC_CALLBACK_MODE
* - Callback APIs
* \endif
*
* The following peripheral is used by this module:
* - DAC (Digital-to-Analog Converter)
*
* The following devices can use this module:
* - Atmel | SMART SAM L21
*
* The outline of this documentation is as follows:
* - \ref asfdoc_sam0_dac_prerequisites
* - \ref asfdoc_sam0_dac_module_overview
* - \ref asfdoc_sam0_dac_special_considerations
* - \ref asfdoc_sam0_dac_extra_info
* - \ref asfdoc_sam0_dac_examples
* - \ref asfdoc_sam0_dac_api_overview
*
*
* \section asfdoc_sam0_dac_prerequisites Prerequisites
*
* There are no prerequisites for this module.
*
*
* \section asfdoc_sam0_dac_module_overview Module Overview
*
* The Digital-to-Analog converter converts a digital value to an analog voltage.
* The DAC Controller can operate as two independent DACs or as a single DAC
* in differential mode. Each DAC has a 12-bit resolution and it is capable of
* converting up to 1M samples per second (Msps).
*
* A common use of DAC is to generate audio signals by connecting the DAC
* output to a speaker, or to generate a reference voltage; either for an
* external circuit or an internal peripheral such as the Analog Comparator.
*
* After being set up, the DAC will convert new digital values written to the
* conversion data register (DATA0 or DATA1) to an analog value either on the
* DAC output (VOUT0 or VOUT1) pin of the device, or internally for use as an
* input to the AC, ADC, and other analog modules.
*
* Writing the DATA register will start a new conversion. It is also possible
* to trigger the conversion from the event system.
*
* A simplified block diagram of the DAC can be seen in
* \ref asfdoc_sam0_dac_module_block_diagram "the figure below".
*
* \anchor asfdoc_sam0_dac_module_block_diagram
* \image html dac_block_diagram_saml.svg "DAC Block Diagram"
*
* \subsection asfdoc_sam0_dac_conversion_range Conversion Range
* The conversion range is between GND and the selected voltage reference.
* Available voltage references are:
* \li Voltage supply (VDDANA)
* \li Internal bandgap reference (INTREF)
* \li Unbuffered External voltage reference (VREFPU)
* \li Buffered External voltage reference (VREFPB)
*
* \note Internal references will be enabled by the driver, but not disabled.
* Any reference not used by the application should be disabled by the application.
*
* The output voltage from a DAC channel is given as:
* \f[
* V_{OUTx} = \frac{DATAx}{0x3FF} \times VREF
* \f]
* The differential output voltage is given as:
* \f[
* V_{OUT} = \frac{DATA0}{0x1FF} \times VREF = (V_{OUT0}-V_{OUT1})
* \f]
*
* \subsection asfdoc_sam0_dac_conversion Conversion
* The conversion digital value written to the DATA register will be converted
* to an analog value. Writing the DATA register will start a new conversion.
* It is also possible to write the conversion value to the DATABUF register,
* the writing of the DATA register can then be triggered from the event
* system, which will load the value from DATABUF to DATA.
*
* \subsection asfdoc_sam0_dac_analog_output Analog Output
* The analog output value can be output to the VOUTx converted by DACx, and
* each data conversion can be started independently.
*
* In differential mode, DAC0 and DAC1 are operating synchronously to convert
* value. VOUT0 is the positive output and VOUT1 the negative output.
*
* VOUT0 signal is internally connected so that it can be used as input for
* AC, ADC, or OPAMP modules when DAC0 is enabled.
* \note The pin VOUT0 will be dedicated to internal input and cannot be
* configured as alternate function.
*
* \subsection asfdoc_sam0_dac_events Events
* Events generation and event actions are configurable in the DAC.
* The DAC has one event line input and one event output: <i>Start Conversion</i>
* and <i>Data Buffer Empty</i>.
*
* If the Start Conversion input event is enabled in the module configuration,
* an incoming event will load data from the data buffer to the data register
* and start a new conversion. This method synchronizes conversions with
* external events (such as those from a timer module) and ensures regular and
* fixed conversion intervals.
*
* If the Data Buffer Empty output event is enabled in the module configuration,
* events will be generated when the DAC data buffer register becomes empty and
* new data can be loaded to the buffer.
*
* \note The connection of events between modules requires the use of the
* \ref asfdoc_sam0_events_group "SAM Event System Driver (EVENTS)"
* to route output event of one module to the the input event of another.
* For more information on event routing, refer to the event driver
* documentation.
*
* \subsection asfdoc_sam0_dac_data_adjust Left and Right Adjusted Values
* The 12-bit input value to the DAC is contained in a 16-bit register. This
* can be configured to be either left or right adjusted. In
* \ref asfdoc_sam0_dac_module_adj_modes "the figure below" both options are
* shown, and the position of the most (MSB) and the least (LSB) significant bits
* are indicated. The unused bits should always be written to zero.
*
* \anchor asfdoc_sam0_dac_module_adj_modes
* \dot
* digraph {
* subgraph cluster_right {
* msbl [label="MSB", shape=none, group="msbl"];
* lsbl [label="LSB", shape=none];
* node [shape=none];
* color="white";
* reg_left [label=<
* <table cellspacing="0" cellpadding="2" width="100%">
* <tr>
* <td port="msb">15</td>
* <td>14</td>
* <td>13</td>
* <td>12</td>
* <td>11</td>
* <td>10</td>
* <td>9</td>
* <td>8</td>
* <td>7</td>
* <td>6</td>
* <td>5</td>
* <td port="lsb">4</td>
* <td>3</td>
* <td>2</td>
* <td>1</td>
* <td>0</td>
* </tr>
* <tr>
* <td COLSPAN="12"> DATA[11:0] </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* <td BGCOLOR="lightgray"> </td>
* </tr>
* </table>
* >];
* msbl -> reg_left:msb:n;
* lsbl -> reg_left:lsb;
* label ="Left adjusted.\n";
* }
* subgraph cluster_left {
* rankdir=TB;
* msb [label="MSB", shape=none];
* lsb [label="LSB", shape=none];
* color="white";
* node [shape=none];
* reg_right [label=<
* <table cellspacing="0" cellpadding="2">
* <tr>
* <td>15</td>
* <td>14</td>
* <td>13</td>
* <td>12</td>
* <td port="msb">11</td>
* <td>10</td>
* <td>9</td>
* <td>8</td>
* <td>7</td>
* <td>6</td>
* <td>5</td>
* <td>4</td>
* <td>3</td>
* <td>2</td>
* <td>1</td>
* <td port="lsb">0</td>
* </tr>
* <tr>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td BGCOLOR="lightgray"></td>
* <td COLSPAN="12"> DATA[11:0] </td>
* </tr>
* </table>
* >];
* msb -> reg_right:msb;
* lsb -> reg_right:lsb:n;
* label = "Right adjusted.\n";
* graph [shape=none];
* }
* }
* \enddot
*
* \subsection asfdoc_sam0_dac_clk_sources Clock Sources
* The clock for the DAC interface (CLK_DAC) is generated by the Power Manager.
* This clock is turned on by default, and can be enabled and disabled in the
* Power Manager.
*
* Additionally, an asynchronous clock source (GCLK_DAC) is required.
* These clocks are normally disabled by default. The selected clock source
* must be enabled in the Power Manager before it can be used by the DAC.
* The DAC core operates asynchronously from the user interface and
* peripheral bus. As a consequence, the DAC needs two clock cycles of both
* CLK_DAC and GCLK_DAC to synchronize the values written to some of the
* control and data registers.
* The oscillator source for the GCLK_DAC clock is selected in the Supply
* Control Interface (SUPC).
*
* \section asfdoc_sam0_dac_special_considerations Special Considerations
*
* \subsection asfdoc_sam0_dac_special_considerations_sleep Sleep Mode
* The DAC can do conversions in Active or Idle modes, and will continue the
* conversions in standby sleep mode if the RUNSTDBY bit in the DACCTRLx
* register is set. Otherwise, the DACx will stop conversions.
*
* If DACx conversion is stopped in standby sleep mode, DACx is disabled to
* reduce power consumption. When exiting standby sleep mode, DACx is enabled
* therefore startup time is required before starting a new conversion.
*
* \subsection asfdoc_sam0_dac_special_considerations_conversion_time Conversion Time
* DAC conversion time is approximately 2.85µs. The user must ensure that new
* data is not written to the DAC before the last conversion is complete.
* Conversions should be triggered by a periodic event from a Timer/Counter or
* another peripheral.
*
*
* \section asfdoc_sam0_dac_extra_info Extra Information
*
* For extra information, see \ref asfdoc_sam0_dac_extra. This includes:
* - \ref asfdoc_sam0_dac_extra_acronyms
* - \ref asfdoc_sam0_dac_extra_dependencies
* - \ref asfdoc_sam0_dac_extra_errata
* - \ref asfdoc_sam0_dac_extra_history
*
*
* \section asfdoc_sam0_dac_examples Examples
*
* For a list of examples related to this driver, see
* \ref asfdoc_sam0_dac_exqsg.
*
*
* \section asfdoc_sam0_dac_api_overview API Overview
* @{
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <compiler.h>
#include <clock.h>
#include <gclk.h>
/**
* \name DAC Status Flags
*
* DAC status flags, returned by \ref dac_get_status() and cleared by
* \ref dac_clear_status().
* @{
*/
/** Data Buffer Empty Channel 0 - Set when data is transferred from DATABUF
* to DATA by a start conversion event and DATABUF is ready for new data.
*/
#define DAC_STATUS_CHANNEL_0_EMPTY (1UL << 0)
/** Data Buffer Empty Channel 1 - Set when data is transferred from DATABUF
* to DATA by a start conversion event and DATABUF is ready for new data.
*/
#define DAC_STATUS_CHANNEL_1_EMPTY (1UL << 1)
/** Underrun Channel 0 - Set when a start conversion event occurs when
* DATABUF is empty.
*/
#define DAC_STATUS_CHANNEL_0_UNDERRUN (1UL << 2)
/** Underrun Channel 1 - Set when a start conversion event occurs when
* DATABUF is empty.
*/
#define DAC_STATUS_CHANNEL_1_UNDERRUN (1UL << 3)
/** @} */
/**
* \brief DAC reference voltage enum.
*
* Enum for the possible reference voltages for the DAC.
*/
enum dac_reference {
/** Unbuffered external voltage reference */
DAC_REFERENCE_VREFPU = DAC_CTRLB_REFSEL(0),
/** Analog VCC as reference */
DAC_REFERENCE_VDDANA = DAC_CTRLB_REFSEL(1),
/** Buffered external voltage reference */
DAC_REFERENCE_VREFPB = DAC_CTRLB_REFSEL(2),
/** Internal bandgap reference */
DAC_REFERENCE_INTREF = DAC_CTRLB_REFSEL(3),
};
/**
* \brief DAC current control enum.
*
* Enum for the current in output buffer according the conversion rate.
*/
enum dac_current_ctrl {
/** 1MHz < GCLK_DAC < 12MHz */
DAC_CURRENT_12M = DAC_DACCTRL_CCTRL(0),
/** 100KHz < GCLK_DAC < 1MHz */
DAC_CURRENT_1M = DAC_DACCTRL_CCTRL(1),
/** 10KHz < GCLK_DAC < 100KHz */
DAC_CURRENT_100K = DAC_DACCTRL_CCTRL(2),
/** GCLK_DAC < 10KHz */
DAC_CURRENT_10K = DAC_DACCTRL_CCTRL(3),
};
/**
* \brief DAC channel selection enum.
*
* Enum for the DAC channel selection.
*/
enum dac_channel {
/** DAC output channel 0 */
DAC_CHANNEL_0,
/** DAC output channel 1 */
DAC_CHANNEL_1,
#if !defined(__DOXYGEN__)
DAC_CHANNEL_N,
#endif
};
/**
* \brief DAC software device instance structure.
*
* DAC software instance structure, used to retain software state information
* of an associated hardware module instance.
*
* \note The fields of this structure should not be altered by the user
* application; they are reserved for module-internal use only.
*/
struct dac_module {
#if !defined(__DOXYGEN__)
/** DAC hardware module */
Dac *hw;
/** Reference selection */
enum dac_reference reference;
/** DAC event selection */
bool start_on_event[DAC_CHANNEL_N];
# if DAC_CALLBACK_MODE == true
/** Pointer to buffer used for ADC results */
volatile uint16_t *job_buffer[DAC_CHANNEL_N];
/** Remaining number of conversions in current job */
volatile uint16_t remaining_conversions[DAC_CHANNEL_N];
/** Transferred number of conversions in current job */
volatile uint16_t transferred_conversions[DAC_CHANNEL_N];
/** DAC callback enable */
bool callback_enable[DAC_CHANNEL_N][DAC_CALLBACK_N];
/** DAC registered callback functions */
dac_callback_t callback[DAC_CHANNEL_N][DAC_CALLBACK_N];
/** Holds the status of the ongoing or last conversion job */
volatile enum status_code job_status[DAC_CHANNEL_N];
# endif
#endif
};
/**
* \brief DAC configuration structure.
*
* Configuration structure for a DAC instance. This structure should be
* initialized by the \ref dac_get_config_defaults()
* function before being modified by the user application.
*/
struct dac_config {
/** Differential mode enable data */
bool differential_mode;
/** Reference voltage */
enum dac_reference reference;
/** GCLK generator used to clock the peripheral */
enum gclk_generator clock_source;
};
/**
* \brief DAC channel configuration structure.
*
* Configuration for a DAC channel. This structure should be initialized by the
* \ref dac_chan_get_config_defaults() function before being modified by the
* user application.
*/
struct dac_chan_config {
/** Left adjusted data */
bool left_adjust;
/** Current control data */
enum dac_current_ctrl current;
/**
* The DAC behaves as in normal mode when the chip enters STANDBY sleep
* mode
*/
bool run_in_standby;
/** Dither mode enable data */
bool dither_mode;
/**
* The DAC conversion refreshed periodically when used to generate a static
* voltage
*/
uint8_t refresh_period;
};
/**
* \brief DAC event enable/disable structure.
*
* Event flags for the DAC module. This is used to enable and
* disable events via \ref dac_enable_events() and \ref dac_disable_events().
*/
struct dac_events {
/** Start a new DAC0 conversion */
bool on_event_chan0_start_conversion;
/** Start a new DAC1 conversion */
bool on_event_chan1_start_conversion;
/** Enable event generation on DAC0 data buffer empty */
bool generate_event_on_chan0_buffer_empty;
/** Enable event generation on DAC1 data buffer empty */
bool generate_event_on_chan1_buffer_empty;
/** Enable the falling edge of the input event for DAC0 */
bool generate_event_on_chan0_falling_edge;
/** Enable the falling edge of the input event for DAC1 */
bool generate_event_on_chan1_falling_edge;
};
/**
* \name Status Management (Channel)
* @{
*/
bool dac_chan_is_end_of_conversion(
struct dac_module *const module_inst,
enum dac_channel channel);
/** @} */
/** @} */
/**
* \page asfdoc_sam0_dac_extra Extra Information for DAC Driver
*
* \section asfdoc_sam0_dac_extra_acronyms Acronyms
* The table below presents the acronyms used in this module:
*
* <table>
* <tr>
* <th>Acronym</th>
* <th>Description</th>
* </tr>
* <tr>
* <td>ADC</td>
* <td>Analog-to-Digital Converter</td>
* </tr>
* <tr>
* <td>AC</td>
* <td>Analog Comparator</td>
* </tr>
* <tr>
* <td>DAC</td>
* <td>Digital-to-Analog Converter</td>
* </tr>
* <tr>
* <td>LSB</td>
* <td>Least Significant Bit</td>
* </tr>
* <tr>
* <td>MSB</td>
* <td>Most Significant Bit</td>
* </tr>
* <tr>
* <td>DMA</td>
* <td>Direct Memory Access</td>
* </tr>
* </table>
*
*
* \section asfdoc_sam0_dac_extra_dependencies Dependencies
* This driver has the following dependency:
*
* - \ref asfdoc_sam0_system_pinmux_group "System Pin Multiplexer Driver"
*
*
* \section asfdoc_sam0_dac_extra_errata Errata
* There are no errata related to this driver.
*
*
* \section asfdoc_sam0_dac_extra_history Module History
* An overview of the module history is presented in the table below, with
* details on the enhancements and fixes made to the module since its first
* release. The current version of this corresponds to the newest version in
* the table.
*
* <table>
* <tr>
* <th>Changelog</th>
* </tr>
* <tr>
* <td>Initial Release</td>
* </tr>
* </table>
*/
/**
* \page asfdoc_sam0_dac_exqsg Examples for DAC Driver
*
* This is a list of the available Quick Start guides (QSGs) and example
* applications for \ref asfdoc_sam0_dac_group. QSGs are simple examples with
* step-by-step instructions to configure and use this driver in a selection of
* use cases. Note that a QSG can be compiled as a standalone application or be
* added to the user application.
*
* - \subpage asfdoc_sam0_dac_basic_use_case
* \if DAC_CALLBACK_MODE
* - \subpage asfdoc_sam0_dac_basic_use_case_callback
* \endif
* \if DAC_DMA_USE_MODE_SELECTION
* - \subpage asfdoc_sam0_adc_dma_use_case_dac_in_dma
* \endif
*
* \if DAC_DMA_USE_MODE_SELECTION
* \page asfdoc_sam0_adc_dma_use_case_dac_in_dma Quick Start Guide for Using DMA with ADC/DAC
* For this examples, see
* \ref asfdoc_sam0_adc_dma_use_case
* \endif
*
* \page asfdoc_sam0_dac_document_revision_history Document Revision History
*
* <table>
* <tr>
* <th>Doc. Rev.</td>
* <th>Date</td>
* <th>Comments</td>
* </tr>
* <tr>
* <td>42450A</td>
* <td>07/2015</td>
* <td>Initial document release</td>
* </tr>
* </table>
*/
#ifdef __cplusplus
}
#endif
#endif /* DAC_FEATURE_H_INCLUDED */

207
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dac/dac.h
View File

@ -1,207 +0,0 @@
/**
* \file
*
* \brief SAM Peripheral Digital-to-Analog Converter Driver
*
* Copyright (C) 2012-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#ifndef DAC_H_INCLUDED
#define DAC_H_INCLUDED
#ifdef __cplusplus
extern "C" {
#endif
#include <compiler.h>
#include <clock.h>
#include <gclk.h>
/**
* \addtogroup asfdoc_sam0_dac_group
*
* @{
*/
/**
* Define DAC features set according to different device families.
* @{
*/
#if (SAMD21 || SAMD10 || SAMD11 || SAMDA1)
# define FEATURE_DAC_DATABUF_WRITE_PROTECTION
#endif
/**@}*/
#ifndef DAC_TIMEOUT
# define DAC_TIMEOUT 0xFFFF
#endif
#if DAC_CALLBACK_MODE == true
# include <system_interrupt.h>
/** Forward definition of the device instance. */
struct dac_module;
#if !defined(__DOXYGEN__)
extern struct dac_module *_dac_instances[DAC_INST_NUM];
#endif
/** Type definition for a DAC module callback function. */
typedef void (*dac_callback_t)(uint8_t channel);
/** Enum for the possible callback types for the DAC module. */
enum dac_callback {
/** Callback type for when a DAC channel data empty condition occurs
* (requires event triggered mode) */
DAC_CALLBACK_DATA_EMPTY,
/** Callback type for when a DAC channel data underrun condition occurs
* (requires event triggered mode) */
DAC_CALLBACK_DATA_UNDERRUN,
/** Callback type for when a DAC channel write buffer job complete (requires
* event triggered mode) */
DAC_CALLBACK_TRANSFER_COMPLETE,
#if !defined(__DOXYGEN__)
DAC_CALLBACK_N,
#endif
};
#endif
#include <dac_feature.h>
/**
* \name Configuration and Initialization
* @{
*/
bool dac_is_syncing(
struct dac_module *const dev_inst);
void dac_get_config_defaults(
struct dac_config *const config);
enum status_code dac_init(
struct dac_module *const dev_inst,
Dac *const module,
struct dac_config *const config);
void dac_reset(
struct dac_module *const dev_inst);
void dac_enable(
struct dac_module *const dev_inst);
void dac_disable(
struct dac_module *const dev_inst);
void dac_enable_events(
struct dac_module *const module_inst,
struct dac_events *const events);
void dac_disable_events(
struct dac_module *const module_inst,
struct dac_events *const events);
/** @} */
/**
* \name Configuration and Initialization (Channel)
* @{
*/
void dac_chan_get_config_defaults(
struct dac_chan_config *const config);
void dac_chan_set_config(
struct dac_module *const dev_inst,
const enum dac_channel channel,
struct dac_chan_config *const config);
void dac_chan_enable(
struct dac_module *const dev_inst,
enum dac_channel channel);
void dac_chan_disable(
struct dac_module *const dev_inst,
enum dac_channel channel);
/** @} */
/**
* \name Channel Data Management
* @{
*/
enum status_code dac_chan_write(
struct dac_module *const dev_inst,
enum dac_channel channel,
const uint16_t data);
enum status_code dac_chan_write_buffer_wait(
struct dac_module *const module_inst,
enum dac_channel channel,
uint16_t *buffer,
uint32_t length);
/** @} */
/**
* \name Status Management
* @{
*/
uint32_t dac_get_status(
struct dac_module *const module_inst);
void dac_clear_status(
struct dac_module *const module_inst,
uint32_t status_flags);
/** @} */
#ifdef __cplusplus
}
#endif
/** @} */
#endif /* DAC_H_INCLUDED */

654
targets/TARGET_Atmel/TARGET_SAM_CortexM0P/drivers/dma/dma.c
View File

@ -1,654 +0,0 @@
/*
* \file
*
* \brief SAM Direct Memory Access Controller Driver
*
* Copyright (C) 2014-2015 Atmel Corporation. All rights reserved.
*
* \asf_license_start
*
* \page License
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
*
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* 3. The name of Atmel may not be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* 4. This software may only be redistributed and used in connection with an
* Atmel microcontroller product.
*
* THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
* EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*
* \asf_license_stop
*
*/
/*
* Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a>
*/
#include <string.h>
#include "dma.h"
#include "clock.h"
#include "system_interrupt.h"
struct _dma_module {
volatile bool _dma_init;
volatile uint32_t allocated_channels;
uint8_t free_channels;
};
struct _dma_module _dma_inst = {
._dma_init = false,
.allocated_channels = 0,
.free_channels = CONF_MAX_USED_CHANNEL_NUM,
};
/** Maximum retry counter for resuming a job transfer. */
#define MAX_JOB_RESUME_COUNT 10000
/** DMA channel mask. */
#define DMA_CHANNEL_MASK (0x1f)
COMPILER_ALIGNED(16)
DmacDescriptor descriptor_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
/** Initial write back memory section. */
COMPILER_ALIGNED(16)
static DmacDescriptor _write_back_section[CONF_MAX_USED_CHANNEL_NUM] SECTION_DMAC_DESCRIPTOR;
/** Internal DMA resource pool. */
static struct dma_resource* _dma_active_resource[CONF_MAX_USED_CHANNEL_NUM];
/* DMA channel interrup flag. */
uint8_t g_chan_interrupt_flag[CONF_MAX_USED_CHANNEL_NUM]= {0};
/**
* \brief Find a free channel for a DMA resource.
*
* Find a channel for the requested DMA resource.
*
* \return Status of channel allocation.
* \retval DMA_INVALID_CHANNEL No channel available
* \retval count Allocated channel for the DMA resource
*/
static uint8_t _dma_find_first_free_channel_and_allocate(void)
{
uint8_t count;
uint32_t tmp;
bool allocated = false;
system_interrupt_enter_critical_section();
tmp = _dma_inst.allocated_channels;
for (count = 0; count < CONF_MAX_USED_CHANNEL_NUM; ++count) {
if (!(tmp & 0x00000001)) {
/* If free channel found, set as allocated and return
*number */
_dma_inst.allocated_channels |= 1 << count;
_dma_inst.free_channels--;
allocated = true;
break;
}
tmp = tmp >> 1;
}
system_interrupt_leave_critical_section();
if (!allocated) {
return DMA_INVALID_CHANNEL;
} else {
return count;
}
}
/**
* \brief Release an allocated DMA channel.
*
* \param[in] channel Channel id to be released
*
*/
static void _dma_release_channel(uint8_t channel)
{
_dma_inst.allocated_channels &= ~(1 << channel);
_dma_inst.free_channels++;
}
/**
* \brief Configure the DMA resource.
*
* \param[in] dma_resource Pointer to a DMA resource instance
* \param[out] resource_config Configurations of the DMA resource
*
*/
static void _dma_set_config(struct dma_resource *resource,
struct dma_resource_config *resource_config)
{
Assert(resource);
Assert(resource_config);
uint32_t temp_CHCTRLB_reg;
system_interrupt_enter_critical_section();
/** Select the DMA channel and clear software trigger */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->SWTRIGCTRL.reg &= (uint32_t)(~(1 << resource->channel_id));
temp_CHCTRLB_reg = DMAC_CHCTRLB_LVL(resource_config->priority) | \
DMAC_CHCTRLB_TRIGSRC(resource_config->peripheral_trigger) | \
DMAC_CHCTRLB_TRIGACT(resource_config->trigger_action);
if(resource_config->event_config.input_action) {
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVIE | DMAC_CHCTRLB_EVACT(
resource_config->event_config.input_action);
}
/** Enable event output, the event output selection is configured in
* each transfer descriptor */
if (resource_config->event_config.event_output_enable) {
temp_CHCTRLB_reg |= DMAC_CHCTRLB_EVOE;
}
/* Write config to CTRLB register */
DMAC->CHCTRLB.reg = temp_CHCTRLB_reg;
system_interrupt_leave_critical_section();
}
/**
* \brief DMA interrupt service routine.
*
*/
void DMAC_Handler( void )
{
uint8_t active_channel;
struct dma_resource *resource;
uint8_t isr;
uint32_t write_size;
uint32_t total_size;
system_interrupt_enter_critical_section();
/* Get Pending channel */
active_channel = DMAC->INTPEND.reg & DMAC_INTPEND_ID_Msk;
Assert(_dma_active_resource[active_channel]);
/* Get active DMA resource based on channel */
resource = _dma_active_resource[active_channel];
/* Select the active channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
isr = DMAC->CHINTFLAG.reg;
/* Calculate block transfer size of the DMA transfer */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
resource->transfered_size = total_size - write_size;
/* DMA channel interrupt handler */
if (isr & DMAC_CHINTENCLR_TERR) {
/* Clear transfer error flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TERR;
/* Set I/O ERROR status */
resource->job_status = STATUS_ERR_IO;
/* Execute the callback function */
if ((resource->callback_enable & (1<<DMA_CALLBACK_TRANSFER_ERROR)) &&
(resource->callback[DMA_CALLBACK_TRANSFER_ERROR])) {
resource->callback[DMA_CALLBACK_TRANSFER_ERROR](resource);
}
} else if (isr & DMAC_CHINTENCLR_TCMPL) {
/* Clear the transfer complete flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_TCMPL;
/* Set job status */
resource->job_status = STATUS_OK;
/* Execute the callback function */
if ((resource->callback_enable & (1 << DMA_CALLBACK_TRANSFER_DONE)) &&
(resource->callback[DMA_CALLBACK_TRANSFER_DONE])) {
resource->callback[DMA_CALLBACK_TRANSFER_DONE](resource);
}
} else if (isr & DMAC_CHINTENCLR_SUSP) {
/* Clear channel suspend flag */
DMAC->CHINTFLAG.reg = DMAC_CHINTENCLR_SUSP;
/* Set job status */
resource->job_status = STATUS_SUSPEND;
/* Execute the callback function */
if ((resource->callback_enable & (1 << DMA_CALLBACK_CHANNEL_SUSPEND)) &&
(resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND])) {
resource->callback[DMA_CALLBACK_CHANNEL_SUSPEND](resource);
}
}
system_interrupt_leave_critical_section();
}
/**
* \brief Initializes config with predefined default values.
*
* This function will initialize a given DMA configuration structure to
* a set of known default values. This function should be called on
* any new instance of the configuration structure before being
* modified by the user application.
*
* The default configuration is as follows:
* \li Software trigger is used as the transfer trigger
* \li Priority level 0
* \li Only software/event trigger
* \li Requires a trigger for each transaction
* \li No event input /output
* \li DMA channel is disabled during sleep mode (if has the feature)
* \param[out] config Pointer to the configuration
*
*/
void dma_get_config_defaults(struct dma_resource_config *config)
{
Assert(config);
/* Set as priority 0 */
config->priority = DMA_PRIORITY_LEVEL_0;
/* Only software/event trigger */
config->peripheral_trigger = 0;
/* Transaction trigger */
config->trigger_action = DMA_TRIGGER_ACTON_TRANSACTION;
/* Event configurations, no event input/output */
config->event_config.input_action = DMA_EVENT_INPUT_NOACT;
config->event_config.event_output_enable = false;
#ifdef FEATURE_DMA_CHANNEL_STANDBY
config->run_in_standby = false;
#endif
}
/**
* \brief Allocate a DMA with configurations.
*
* This function will allocate a proper channel for a DMA transfer request.
*
* \param[in,out] dma_resource Pointer to a DMA resource instance
* \param[in] transfer_config Configurations of the DMA transfer
*
* \return Status of the allocation procedure.
*
* \retval STATUS_OK The DMA resource was allocated successfully
* \retval STATUS_ERR_NOT_FOUND DMA resource allocation failed
*/
enum status_code dma_allocate(struct dma_resource *resource,
struct dma_resource_config *config)
{
uint8_t new_channel;
Assert(resource);
system_interrupt_enter_critical_section();
if (!_dma_inst._dma_init) {
/* Initialize clocks for DMA */
#if (SAML21) || (SAMC20) || (SAMC21)
system_ahb_clock_set_mask(MCLK_AHBMASK_DMAC);
#else
system_ahb_clock_set_mask(PM_AHBMASK_DMAC);
system_apb_clock_set_mask(SYSTEM_CLOCK_APB_APBB,
PM_APBBMASK_DMAC);
#endif
/* Perform a software reset before enable DMA controller */
DMAC->CTRL.reg &= ~DMAC_CTRL_DMAENABLE;
DMAC->CTRL.reg = DMAC_CTRL_SWRST;
/* Setup descriptor base address and write back section base
* address */
DMAC->BASEADDR.reg = (uint32_t)descriptor_section;
DMAC->WRBADDR.reg = (uint32_t)_write_back_section;
/* Enable all priority level at the same time */
DMAC->CTRL.reg = DMAC_CTRL_DMAENABLE | DMAC_CTRL_LVLEN(0xf);
_dma_inst._dma_init = true;
}
/* Find the proper channel */
new_channel = _dma_find_first_free_channel_and_allocate();
/* If no channel available, return not found */
if (new_channel == DMA_INVALID_CHANNEL) {
system_interrupt_leave_critical_section();
return STATUS_ERR_NOT_FOUND;
}
/* Set the channel */
resource->channel_id = new_channel;
/** Perform a reset for the allocated channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLA.reg &= ~DMAC_CHCTRLA_ENABLE;
DMAC->CHCTRLA.reg = DMAC_CHCTRLA_SWRST;
#ifdef FEATURE_DMA_CHANNEL_STANDBY
if(config->run_in_standby) {
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_RUNSTDBY;
}
#endif
/** Configure the DMA control,channel registers and descriptors here */
_dma_set_config(resource, config);
resource->descriptor = NULL;
/* Log the DMA resource into the internal DMA resource pool */
_dma_active_resource[resource->channel_id] = resource;
system_interrupt_leave_critical_section();
return STATUS_OK;
}
/**
* \brief Free an allocated DMA resource.
*
* This function will free an allocated DMA resource.
*
* \param[in,out] resource Pointer to the DMA resource
*
* \return Status of the free procedure.
*
* \retval STATUS_OK The DMA resource was freed successfully
* \retval STATUS_BUSY The DMA resource was busy and can't be freed
* \retval STATUS_ERR_NOT_INITIALIZED DMA resource was not initialized
*/
enum status_code dma_free(struct dma_resource *resource)
{
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
/* Check if channel is busy */
if (dma_is_busy(resource)) {
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if DMA resource was not allocated */
if (!(_dma_inst.allocated_channels & (1 << resource->channel_id))) {
system_interrupt_leave_critical_section();
return STATUS_ERR_NOT_INITIALIZED;
}
/* Release the DMA resource */
_dma_release_channel(resource->channel_id);
/* Reset the item in the DMA resource pool */
_dma_active_resource[resource->channel_id] = NULL;
system_interrupt_leave_critical_section();
return STATUS_OK;
}
/**
* \brief Start a DMA transfer.
*
* This function will start a DMA transfer through an allocated DMA resource.
*
* \param[in,out] resource Pointer to the DMA resource
*
* \return Status of the transfer start procedure.
*
* \retval STATUS_OK The transfer was started successfully
* \retval STATUS_BUSY The DMA resource was busy and the transfer was not started
* \retval STATUS_ERR_INVALID_ARG Transfer size is 0 and transfer was not started
*/
enum status_code dma_start_transfer_job(struct dma_resource *resource)
{
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
/* Check if resource was busy */
if (resource->job_status == STATUS_BUSY) {
system_interrupt_leave_critical_section();
return STATUS_BUSY;
}
/* Check if transfer size is valid */
if (resource->descriptor->BTCNT.reg == 0) {
system_interrupt_leave_critical_section();
return STATUS_ERR_INVALID_ARG;
}
/* Enable DMA interrupt */
system_interrupt_enable(SYSTEM_INTERRUPT_MODULE_DMA);
/* Set the interrupt flag */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHINTENSET.reg = (DMAC_CHINTENSET_MASK & g_chan_interrupt_flag[resource->channel_id]);
/* Set job status */
resource->job_status = STATUS_BUSY;
/* Set channel x descriptor 0 to the descriptor base address */
memcpy(&descriptor_section[resource->channel_id], resource->descriptor,
sizeof(DmacDescriptor));
/* Enable the transfer channel */
DMAC->CHCTRLA.reg |= DMAC_CHCTRLA_ENABLE;
system_interrupt_leave_critical_section();
return STATUS_OK;
}
/**
* \brief Abort a DMA transfer.
*
* This function will abort a DMA transfer. The DMA channel used for the DMA
* resource will be disabled.
* The block transfer count will be also calculated and written to the DMA
* resource structure.
*
* \note The DMA resource will not be freed after calling this function.
* The function \ref dma_free() can be used to free an allocated resource.
*
* \param[in,out] resource Pointer to the DMA resource
*
*/
void dma_abort_job(struct dma_resource *resource)
{
uint32_t write_size;
uint32_t total_size;
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLA.reg = 0;
system_interrupt_leave_critical_section();
/* Get transferred size */
total_size = descriptor_section[resource->channel_id].BTCNT.reg;
write_size = _write_back_section[resource->channel_id].BTCNT.reg;
resource->transfered_size = total_size - write_size;
resource->job_status = STATUS_ABORTED;
}
/**
* \brief Suspend a DMA transfer.
*
* This function will request to suspend the transfer of the DMA resource.
* The channel is kept enabled, can receive transfer triggers (the transfer
* pending bit will be set), but will be removed from the arbitration scheme.
* The channel operation can be resumed by calling \ref dma_resume_job().
*
* \note This function sets the command to suspend the DMA channel
* associated with a DMA resource. The channel suspend interrupt flag
* indicates whether the transfer is truly suspended.
*
* \param[in] resource Pointer to the DMA resource
*
*/
void dma_suspend_job(struct dma_resource *resource)
{
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
system_interrupt_enter_critical_section();
/* Select the channel */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
/* Send the suspend request */
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_SUSPEND;
system_interrupt_leave_critical_section();
}
/**
* \brief Resume a suspended DMA transfer.
*
* This function try to resume a suspended transfer of a DMA resource.
*
* \param[in] resource Pointer to the DMA resource
*
*/
void dma_resume_job(struct dma_resource *resource)
{
uint32_t bitmap_channel;
uint32_t count = 0;
Assert(resource);
Assert(resource->channel_id != DMA_INVALID_CHANNEL);
/* Get bitmap of the allocated DMA channel */
bitmap_channel = (1 << resource->channel_id);
/* Check if channel was suspended */
if (resource->job_status != STATUS_SUSPEND) {
return;
}
system_interrupt_enter_critical_section();
/* Send resume request */
DMAC->CHID.reg = DMAC_CHID_ID(resource->channel_id);
DMAC->CHCTRLB.reg |= DMAC_CHCTRLB_CMD_RESUME;
system_interrupt_leave_critical_section();
/* Check if transfer job resumed */
for (count = 0; count < MAX_JOB_RESUME_COUNT; count++) {
if ((DMAC->BUSYCH.reg & bitmap_channel) == bitmap_channel) {
break;
}
}
if (count < MAX_JOB_RESUME_COUNT) {
/* Job resumed */
resource->job_status = STATUS_BUSY;
} else {
/* Job resume timeout */
resource->job_status = STATUS_ERR_TIMEOUT;
}
}
/**
* \brief Create a DMA transfer descriptor with configurations.
*
* This function will set the transfer configurations to the DMA transfer
* descriptor.
*
* \param[in] descriptor Pointer to the DMA transfer descriptor
* \param[in] config Pointer to the descriptor configuration structure
*
*/
void dma_descriptor_create(DmacDescriptor* descriptor,
struct dma_descriptor_config *config)
{
/* Set block transfer control */
descriptor->BTCTRL.bit.VALID = config->descriptor_valid;
descriptor->BTCTRL.bit.EVOSEL = config->event_output_selection;
descriptor->BTCTRL.bit.BLOCKACT = config->block_action;
descriptor->BTCTRL.bit.BEATSIZE = config->beat_size;
descriptor->BTCTRL.bit.SRCINC = config->src_increment_enable;
descriptor->BTCTRL.bit.DSTINC = config->dst_increment_enable;
descriptor->BTCTRL.bit.STEPSEL = config->step_selection;
descriptor->BTCTRL.bit.STEPSIZE = config->step_size;
/* Set transfer size, source address and destination address */
descriptor->BTCNT.reg = config->block_transfer_count;
descriptor->SRCADDR.reg = config->source_address;
descriptor->DSTADDR.reg = config->destination_address;
/* Set next transfer descriptor address */
descriptor->DESCADDR.reg = config->next_descriptor_address;
}
/**
* \brief Add a DMA transfer descriptor to a DMA resource.
*
* This function will add a DMA transfer descriptor to a DMA resource.
* If there was a transfer descriptor already allocated to the DMA resource,
* the descriptor will be linked to the next descriptor address.
*
* \param[in] resource Pointer to the DMA resource
* \param[in] descriptor Pointer to the transfer descriptor
*
* \retval STATUS_OK The descriptor is added to the DMA resource
* \retval STATUS_BUSY The DMA resource was busy and the descriptor is not added
*/
enum status_code dma_add_descriptor(struct dma_resource *resource,
DmacDescriptor* descriptor)
{
DmacDescriptor* desc = resource->descriptor;
if (resource->job_status == STATUS_BUSY) {
return STATUS_BUSY;
}
/* Look up for an empty space for the descriptor */
if (desc == NULL) {
resource->descriptor = descriptor;
} else {
/* Looking for end of descriptor link */
while(desc->DESCADDR.reg != 0) {
desc = (DmacDescriptor*)(desc->DESCADDR.reg);
}
/* Set to the end of descriptor list */
desc->DESCADDR.reg = (uint32_t)descriptor;
}
return STATUS_OK;
}

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