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Merge pull request #1121 from Wiznet/master 

Add WIZwiki-W7500
pull/1154/head
Martin Kojtal 2015-06-03 08:54:53 +01:00
parent e775613c6b 86a6703ef5
commit 927c31ab84
49 changed files with 8511 additions and 1 deletions
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15
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/W7500.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00020000 { ; load region size_region
ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00004000 { ; RW data
.ANY (+RW +ZI)
}
}

213
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/startup_W7500x.s Normal file
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;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000400
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500)
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SSP0_Handler [WEAK]
EXPORT SSP1_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT UART2_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT PORT0_Handler [WEAK]
EXPORT PORT1_Handler [WEAK]
EXPORT PORT2_Handler [WEAK]
EXPORT PORT3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT DUALTIMER0_Handler [WEAK]
EXPORT DUALTIMER1_Handler [WEAK]
EXPORT PWM0_Handler [WEAK]
EXPORT PWM1_Handler [WEAK]
EXPORT PWM2_Handler [WEAK]
EXPORT PWM3_Handler [WEAK]
EXPORT PWM4_Handler [WEAK]
EXPORT PWM5_Handler [WEAK]
EXPORT PWM6_Handler [WEAK]
EXPORT PWM7_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT WZTOE_Handler [WEAK]
EXPORT EXTI_Handler [WEAK]
SSP0_Handler
SSP1_Handler
UART0_Handler
UART1_Handler
UART2_Handler
I2C0_Handler
I2C1_Handler
PORT0_Handler
PORT1_Handler
PORT2_Handler
PORT3_Handler
DMA_Handler
DUALTIMER0_Handler
DUALTIMER1_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PWM5_Handler
PWM6_Handler
PWM7_Handler
RTC_Handler
ADC_Handler
WZTOE_Handler
EXTI_Handler
B .
ENDP
ALIGN
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
END

31
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_MICRO/sys.cpp Normal file
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/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

15
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/W7500.sct Normal file
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; *************************************************************
; *** Scatter-Loading Description File generated by uVision ***
; *************************************************************
LR_IROM1 0x00000000 0x00020000 { ; load region size_region
ER_IROM1 0x00000000 0x00020000 { ; load address = execution address
*.o (RESET, +First)
*(InRoot$$Sections)
.ANY (+RO)
}
RW_IRAM1 0x20000000 0x00004000 { ; RW data
.ANY (+RW +ZI)
}
}

186
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/startup_W7500x.s Normal file
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;/**************************************************************************//**
; * @file startup_CMSDK_CM0.s
; * @brief CMSIS Cortex-M0 Core Device Startup File for
; * Device CMSDK_CM0
; * @version V3.01
; * @date 06. March 2012
; * @modify 29. April 2014 by WIZnet ; added WZTOE_HANDLER
; * @note
; * Copyright (C) 2012 ARM Limited. All rights reserved.
; *
; * @par
; * ARM Limited (ARM) is supplying this software for use with Cortex-M
; * processor based microcontrollers. This file can be freely distributed
; * within development tools that are supporting such ARM based processors.
; *
; * @par
; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
; *
; ******************************************************************************/
;/*
;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
;*/
__initial_sp EQU 0x20004000 ; Top of RAM (16 KB for WIZwiki_W7500)
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD SSP0_Handler ; 16+ 0: SSP 0 Handler
DCD SSP1_Handler ; 16+ 1: SSP 1 Handler
DCD UART0_Handler ; 16+ 2: UART 0 Handler
DCD UART1_Handler ; 16+ 3: UART 1 Handler
DCD UART2_Handler ; 16+ 4: UART 2 Handler
DCD I2C0_Handler ; 16+ 5: I2C 0 Handler
DCD I2C1_Handler ; 16+ 6: I2C 1 Handler
DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler
DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler
DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler
DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler
DCD DMA_Handler ; 16+11: DMA Combined Handler
DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler
DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler
DCD PWM0_Handler ; 16+14: PWM0 Handler
DCD PWM1_Handler ; 16+15: PWM1 Handler
DCD PWM2_Handler ; 16+16: PWM2 Handler
DCD PWM3_Handler ; 16+17: PWM3 Handler
DCD PWM4_Handler ; 16+18: PWM4 Handler
DCD PWM5_Handler ; 16+19: PWM5 Handler
DCD PWM6_Handler ; 16+20: PWM6 Handler
DCD PWM7_Handler ; 16+21: PWM7 Handler
DCD RTC_Handler ; 16+22: RTC Handler
DCD ADC_Handler ; 16+23: ADC Handler
DCD WZTOE_Handler ; 16+24: WZTOE_Handler
DCD EXTI_Handler ; 16+25: EXTI_Handler
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT SystemInit
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT SSP0_Handler [WEAK]
EXPORT SSP1_Handler [WEAK]
EXPORT UART0_Handler [WEAK]
EXPORT UART1_Handler [WEAK]
EXPORT UART2_Handler [WEAK]
EXPORT I2C0_Handler [WEAK]
EXPORT I2C1_Handler [WEAK]
EXPORT PORT0_Handler [WEAK]
EXPORT PORT1_Handler [WEAK]
EXPORT PORT2_Handler [WEAK]
EXPORT PORT3_Handler [WEAK]
EXPORT DMA_Handler [WEAK]
EXPORT DUALTIMER0_Handler [WEAK]
EXPORT DUALTIMER1_Handler [WEAK]
EXPORT PWM0_Handler [WEAK]
EXPORT PWM1_Handler [WEAK]
EXPORT PWM2_Handler [WEAK]
EXPORT PWM3_Handler [WEAK]
EXPORT PWM4_Handler [WEAK]
EXPORT PWM5_Handler [WEAK]
EXPORT PWM6_Handler [WEAK]
EXPORT PWM7_Handler [WEAK]
EXPORT RTC_Handler [WEAK]
EXPORT ADC_Handler [WEAK]
EXPORT WZTOE_Handler [WEAK]
EXPORT EXTI_Handler [WEAK]
SSP0_Handler
SSP1_Handler
UART0_Handler
UART1_Handler
UART2_Handler
I2C0_Handler
I2C1_Handler
PORT0_Handler
PORT1_Handler
PORT2_Handler
PORT3_Handler
DMA_Handler
DUALTIMER0_Handler
DUALTIMER1_Handler
PWM0_Handler
PWM1_Handler
PWM2_Handler
PWM3_Handler
PWM4_Handler
PWM5_Handler
PWM6_Handler
PWM7_Handler
RTC_Handler
ADC_Handler
WZTOE_Handler
EXTI_Handler
B .
ENDP
ALIGN
END

31
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_ARM_STD/sys.cpp Normal file
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/* mbed Microcontroller Library - stackheap
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*/
#ifdef __cplusplus
extern "C" {
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$RW_IRAM1$$ZI$$Limit[];
extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
uint32_t sp_limit = __current_sp();
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

152
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/W7500.ld Normal file
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/* Linker script to configure memory regions. */
MEMORY
{
FLASH (rx) : ORIGIN = 0x0, LENGTH = 0x20000 /* 128K */
RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x4000 /* 16K */
}
/* Library configurations */
GROUP(libgcc.a libc.a libm.a libnosys.a)
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
KEEP(*(.isr_vector))
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
*(.rodata*)
KEEP(*(.eh_frame*))
} > FLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > FLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > FLASH
__exidx_end = .;
__etext = .;
.data : AT (__etext)
{
__data_start__ = .;
*(vtable)
*(.data*)
. = ALIGN(4);
/* preinit data */
PROVIDE_HIDDEN (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE_HIDDEN (__preinit_array_end = .);
. = ALIGN(4);
/* init data */
PROVIDE_HIDDEN (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE_HIDDEN (__init_array_end = .);
. = ALIGN(4);
/* finit data */
PROVIDE_HIDDEN (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE_HIDDEN (__fini_array_end = .);
KEEP(*(.jcr*))
. = ALIGN(4);
/* All data end */
__data_end__ = .;
} > RAM
.bss :
{
. = ALIGN(4);
__bss_start__ = .;
*(.bss*)
*(COMMON)
. = ALIGN(4);
__bss_end__ = .;
} > RAM
.heap (COPY):
{
__end__ = .;
end = __end__;
*(.heap*)
__HeapLimit = .;
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}

259
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/TOOLCHAIN_GCC_ARM/startup_W7500.s Normal file
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/* File: startup_W7500.s
* Purpose: startup file for Cortex-M0 devices. Should use with
* GCC for ARM Embedded Processors
* Version: V1.4
* Date: 20 Dezember 2012
*
*/
/* Copyright (c) 2011 - 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
.syntax unified
.arch armv6-m
.section .stack
.align 3
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .stack
.align 3
#ifdef __STACK_SIZE
.equ Stack_Size, __STACK_SIZE
#else
.equ Stack_Size, 0x200
#endif
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space Stack_Size
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.section .heap
.align 3
#ifdef __HEAP_SIZE
.equ Heap_Size, __HEAP_SIZE
#else
.equ Heap_Size, 0
#endif
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.if Heap_Size
.space Heap_Size
.endif
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
/* Vector Table */
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long __StackTop /* Top of Stack */
.long Reset_Handler /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long 0 /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
.long SSP0_Handler /* 16+ 0: SSP 0 Handler */
.long SSP1_Handler /* 16+ 1: SSP 1 Handler */
.long UART0_Handler /* 16+ 2: UART 0 Handler */
.long UART1_Handler /* 16+ 3: UART 1 Handler */
.long UART2_Handler /* 16+ 4: UART 2 Handler */
.long I2C0_Handler /* 16+ 5: I2C 0 Handler */
.long I2C1_Handler /* 16+ 6: I2C 1 Handler */
.long PORT0_Handler /* 16+ 7: GPIO Port 0 Combined Handler */
.long PORT1_Handler /* 16+ 8: GPIO Port 1 Combined Handler */
.long PORT2_Handler /* 16+ 9: GPIO Port 2 Combined Handler */
.long PORT3_Handler /* 16+10: GPIO Port 3 Combined Handler */
.long DMA_Handler /* 16+11: DMA Combined Handler */
.long DUALTIMER0_Handler /* 16+12: Dual timer 0 handler */
.long DUALTIMER1_Handler /* 16+ 13: Dual timer 1 Handler */
.long PWM0_Handler /* 16+ 14: PWM0 Handler */
.long PWM1_Handler /* 16+ 15: PWM1 Handler */
.long PWM2_Handler /* 16+ 16: PWM2 Handler */
.long PWM3_Handler /* 16+ 17: PWM3 Handler */
.long PWM4_Handler /* 16+ 18: PWM4 Handler */
.long PWM5_Handler /* 16+ 19: PWM5 Handler */
.long PWM6_Handler /* 16+ 20: PWM6 Handler */
.long PWM7_Handler /* 16+ 21: PWM7 Handler */
.long RTC_Handler /* 16+ 22: RTC Handler */
.long ADC_Handler /* 16+ 23: ADC Handler */
.long WZTOE_Handler /* 16+ 24: WZTOE Handler */
.long EXTI_Handler /* 16+ 25: EXTI Handler */
.size __isr_vector, . - __isr_vector
/* Reset Handler */
.text
.thumb
.thumb_func
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* Loop to copy data from read only memory to RAM. The ranges
* of copy from/to are specified by following symbols evaluated in
* linker script.
* __etext: End of code section, i.e., begin of data sections to copy from.
* __data_start__/__data_end__: RAM address range that data should be
* copied to. Both must be aligned to 4 bytes boundary. */
ldr r1, =__etext
ldr r2, =__data_start__
ldr r3, =__data_end__
subs r3, r2
ble .LC1
.LC0:
subs r3, #4
ldr r0, [r1, r3]
str r0, [r2, r3]
bgt .LC0
.LC1:
#ifdef __STARTUP_CLEAR_BSS
/* This part of work usually is done in C library startup code. Otherwise,
* define this macro to enable it in this startup.
*
* Loop to zero out BSS section, which uses following symbols
* in linker script:
* __bss_start__: start of BSS section. Must align to 4
* __bss_end__: end of BSS section. Must align to 4
*/
ldr r1, =__bss_start__
ldr r2, =__bss_end__
subs r2, r1
ble .LC3
movs r0, 0
.LC2:
str r0, [r1, r2]
subs r2, 4
bge .LC2
.LC3:
#endif /* __STARTUP_CLEAR_BSS */
/*bl _start*/
bl main
.pool
.size Reset_Handler, . - Reset_Handler
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
/* System Exception Handlers */
def_default_handler NMI_Handler
def_default_handler HardFault_Handler
def_default_handler MemManage_Handler
def_default_handler BusFault_Handler
def_default_handler UsageFault_Handler
def_default_handler SVC_Handler
def_default_handler DebugMon_Handler
def_default_handler PendSV_Handler
def_default_handler SysTick_Handler
/* IRQ Handlers */
def_default_handler SSP0_Handler
def_default_handler SSP1_Handler
def_default_handler UART0_Handler
def_default_handler UART1_Handler
def_default_handler UART2_Handler
def_default_handler I2C0_Handler
def_default_handler I2C1_Handler
def_default_handler PORT0_Handler
def_default_handler PORT1_Handler
def_default_handler PORT2_Handler
def_default_handler PORT3_Handler
def_default_handler DMA_Handler
def_default_handler DUALTIMER0_Handler
def_default_handler DUALTIMER1_Handler
def_default_handler PWM0_Handler
def_default_handler PWM1_Handler
def_default_handler PWM2_Handler
def_default_handler PWM3_Handler
def_default_handler PWM4_Handler
def_default_handler PWM5_Handler
def_default_handler PWM6_Handler
def_default_handler PWM7_Handler
def_default_handler RTC_Handler
def_default_handler ADC_Handler
def_default_handler WZTOE_Handler
def_default_handler EXTI_Handler
/*
def_default_handler Default_Handler
.weak DEF_IRQHandler
.set DEF_IRQHandler, Default_Handler
*/
.end

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/* mbed Microcontroller Library
* A generic CMSIS include header
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "W7500x.h"
#include "cmsis_nvic.h"
#endif

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis_nvic.h"
#define NVIC_RAM_VECTOR_ADDRESS (0x20000000) // Vectors positioned at start of RAM
#define NVIC_FLASH_VECTOR_ADDRESS (0x00000000) // Initial vector position in flash
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
static volatile uint32_t *vectors = (uint32_t *)NVIC_RAM_VECTOR_ADDRESS;
vectors[IRQn + 16] = vector;
}
uint32_t NVIC_GetVector(IRQn_Type IRQn) {
uint32_t *vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
// Return the vector
return vectors[IRQn + 16];
}

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/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2014, STMicroelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_CMSIS_NVIC_H
#define MBED_CMSIS_NVIC_H
#define NVIC_NUM_VECTORS 41
#define NVIC_USER_IRQ_OFFSET 16
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
uint32_t NVIC_GetVector(IRQn_Type IRQn);
#ifdef __cplusplus
}
#endif
#endif

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/**************************************************************************//**
* @file system_CMSDK_CM0.c
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
* Device CMSDK
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include "system_W7500x.h"
/*----------------------------------------------------------------------------
DEFINES
*----------------------------------------------------------------------------*/
//#define SYSCLK_EXTERN_OSC
/*----------------------------------------------------------------------------
Clock Variable definitions
*----------------------------------------------------------------------------*/
uint32_t SystemFrequency = 0; /*!< System Clock Frequency (Core Clock) */
uint32_t SystemCoreClock = 0; /*!< Processor Clock Frequency */
/*----------------------------------------------------------------------------
Clock functions
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
{
uint8_t M,N,OD;
#ifdef SYSCLK_EXTERN_OSC
CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
#else
CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
#endif
OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
N = (CRG->PLL_FCR >> 8 ) & 0x3F;
M = (CRG->PLL_FCR >> 16) & 0x3F;
#ifdef SYSCLK_EXTERN_OSC
SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
#else
SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
#endif
}
uint32_t GetSystemClock()
{
return SystemCoreClock;
}
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System.
*/
void SystemInit (void)
{
uint8_t M,N,OD;
(*((volatile uint32_t *)(W7500x_TRIM_BGT))) = (*((volatile uint32_t *)(W7500x_INFO_BGT)));
(*((volatile uint32_t *)(W7500x_TRIM_OSC))) = (*((volatile uint32_t *)(W7500x_INFO_OSC)));
// Set PLL input frequency
#ifdef SYSCLK_EXTERN_OSC
CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
#else
CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
#endif
OD = (1 << (CRG->PLL_FCR & 0x01)) * (1 << ((CRG->PLL_FCR & 0x02) >> 1));
N = (CRG->PLL_FCR >> 8 ) & 0x3F;
M = (CRG->PLL_FCR >> 16) & 0x3F;
#ifdef SYSCLK_EXTERN_OSC
SystemCoreClock = EXTERN_XTAL * M / N * 1 / OD;
#else
SystemCoreClock = INTERN_XTAL * M / N * 1 / OD;
#endif
}

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/**************************************************************************//**
* @file system_W7500x.h
* @brief CMSIS Cortex-M# Device Peripheral Access Layer Header File for
* Device W7500x
* @version V3.10
* @date 23. November 2012
*
* @note
*
******************************************************************************/
/* Copyright (c) 2012 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef SYSTEM_W7500x_H /* ToDo: replace '<Device>' with your device name */
#define SYSTEM_W7500x_H
#ifdef __cplusplus
extern "C" {
#endif
#include "W7500x.h"
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
extern uint32_t GetSystemClock(void); /*!< Get System Clock Frequency */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/*----------------------------------------------------------------------------
Define clocks
*----------------------------------------------------------------------------*/
#define EXTERN_XTAL (8000000UL) /* External Oscillator Frequency */
#define INTERN_XTAL (8000000UL) /* Internal Oscillator Frequency */
#ifdef __cplusplus
}
#endif
#endif /* SYSTEM_W7500x_H */

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#include "W7500x.h"
void ADC_PowerDownEnable (FunctionalState NewState)
{
if (NewState != DISABLE) ADC->ADC_CTR = ADC_CTR_PWD_PD;
else ADC->ADC_CTR = ADC_CTR_PWD_NRMOP;
}
void ADC_ChannelSelect (ADC_CH num)
{
assert_param(IS_ADC_CH_NUM(num));
ADC->ADC_CHSEL = num;
}
void ADC_Start (void)
{
ADC->ADC_START = ADC_START_START;
}
uint16_t ADC_ReadData (void)
{
return ((uint16_t)ADC->ADC_DATA);
}
void ADC_InterruptMask (FunctionalState NewState)
{
if (NewState != DISABLE) ADC->ADC_INT = ADC_INT_MASK_ENA;
else ADC->ADC_INT = ADC_INT_MASK_DIS;
}
uint8_t ADC_IsInterrupt (void)
{
return (((uint8_t)ADC->ADC_INT && 0x01ul));
}
void ADC_InterruptClear (void)
{
ADC->ADC_INT = ADC_INTCLEAR;
}
void ADC_Init (void)
{
// ADC_CLK on
ADC_PowerDownEnable(DISABLE);
//ADC_ChannelSelect(num);
}
void ADC_DeInit (void)
{
// ADC_CLK off
ADC_PowerDownEnable(ENABLE);
ADC_InterruptMask(DISABLE);
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the ADC
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_ADC_H
#define __W7500X_ADC_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
typedef enum { ADC_CH0 = 0,
ADC_CH1 = 1,
ADC_CH2 = 2,
ADC_CH3 = 3,
ADC_CH4 = 4,
ADC_CH5 = 5,
ADC_CH6 = 6,
ADC_CH7 = 7,
ADC_CH15 = 15} ADC_CH;
#define IS_ADC_CH_NUM(NUM) (((NUM) == ADC_CH0) || \
((NUM) == ADC_CH1) || \
((NUM) == ADC_CH2) || \
((NUM) == ADC_CH3) || \
((NUM) == ADC_CH4) || \
((NUM) == ADC_CH5) || \
((NUM) == ADC_CH6) || \
((NUM) == ADC_CH7) || \
((NUM) == ADC_CH15))
void ADC_Init(void);
void ADC_DeInit(void);
void ADC_PowerDownEnable (FunctionalState NewState);
void ADC_ChannelSelect (ADC_CH num);
void ADC_Start (void);
uint16_t ADC_ReadData (void);
void ADC_InterruptMask (FunctionalState NewState);
uint8_t ADC_IsInterrupt (void);
void ADC_InterruptClear (void);
#ifdef __cplusplus
}
#endif
#endif //__W7500X_ADC_H

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#include "W7500x_gpio.h"
#include "W7500x_exti.h"
#include "W7500x_pwm.h"
#include "W7500x_uart.h"
#include "W7500x_i2c.h"
#include "W7500x_adc.h"
#include "system_W7500x.h"
#ifdef USE_FULL_ASSERT
#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__,__LINE__))
#else
#define assert_param(expr) ((void)0)
#endif /* USE_FULL_ASSERT */

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#include "W7500x_crg.h"
void CRG_DeInit(void)
{
//To Do
}
void CRG_OSC_PowerDownEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->OSC_PDR = CRG_OSC_PDR_PD;
else CRG->OSC_PDR = CRG_OSC_PDR_NRMLOP;
}
void CRG_PLL_PowerDownEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->PLL_PDR = CRG_PLL_PDR_PD;
else CRG->PLL_PDR = CRG_PLL_PDR_NRMLOP;
}
void CRG_PLL_OutputEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->PLL_OER = CRG_PLL_OER_EN;
else CRG->PLL_OER = CRG_PLL_OER_DIS;
}
void CRG_PLL_BypassEnable(FunctionalState NewState)
{
if(NewState != DISABLE) CRG->PLL_BPR = CRG_PLL_BPR_EN;
else CRG->PLL_BPR = CRG_PLL_BPR_DIS;
}
void CRG_PLL_InputFrequencySelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_PLL_SRC(src));
if( src == CRG_RCLK ) CRG->PLL_IFSR = CRG_PLL_IFSR_RCLK;
else CRG->PLL_IFSR = CRG_PLL_IFSR_OCLK;
}
void CRG_FCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_FCLK_SRC(src));
if ( src == CRG_RCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_RCLK;
else if ( src == CRG_OCLK ) CRG->FCLK_SSR = CRG_FCLK_SSR_OCLK;
else CRG->FCLK_SSR = CRG_FCLK_SSR_MCLK;
}
void CRG_FCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_FCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV4;
else CRG->FCLK_PVSR = CRG_FCLK_PVSR_DIV8;
}
void CRG_SSPCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_SSPCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_RCLK;
else CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_OCLK;
}
void CRG_SSPCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_SSPCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV4;
else CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV8;
}
void CRG_ADCCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_ADCCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_RCLK;
else CRG->ADCCLK_SSR = CRG_ADCCLK_SSR_OCLK;
}
void CRG_ADCCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_ADCCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV4;
else CRG->ADCCLK_PVSR = CRG_ADCCLK_PVSR_DIV8;
}
void CRG_TIMERCLK_SourceSelect(CRG_TIMER num, CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_TIMERCLK_NUM(num));
assert_param(IS_CRG_TIMERCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_DIS);
else if ( src == CRG_MCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_MCLK);
else if ( src == CRG_RCLK ) CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_RCLK);
else CRG_SET_TIMERCLK_SSR(num,CRG_TIMERCLK_SSR_OCLK);
}
void CRG_TIMERCLK_SetPrescale(CRG_TIMER num, CRG_PREDIV prediv)
{
assert_param(IS_CRG_TIMERCLK_NUM(num));
assert_param(IS_CRG_TIMERCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV1);
else if ( prediv == CRG_PREDIV2 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV2);
else if ( prediv == CRG_PREDIV4 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV4);
else if ( prediv == CRG_PREDIV8 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV8);
else if ( prediv == CRG_PREDIV16 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV16);
else if ( prediv == CRG_PREDIV32 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV32);
else if ( prediv == CRG_PREDIV64 ) CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV64);
else CRG_SET_TIMERCLK_PREDIV(num,CRG_TIMERCLK_PVSR_DIV128);
}
void CRG_PWMCLK_SourceSelect(CRG_PWM num, CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_PWMCLK_NUM(num));
assert_param(IS_CRG_PWMCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_DIS);
else if ( src == CRG_MCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_MCLK);
else if ( src == CRG_RCLK ) CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_RCLK);
else CRG_SET_PWMCLK_SSR(num,CRG_PWMCLK_SSR_OCLK);
}
void CRG_PWMCLK_SetPrescale(CRG_PWM num, CRG_PREDIV prediv)
{
assert_param(IS_CRG_PWMCLK_NUM(num));
assert_param(IS_CRG_PWMCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV1);
else if ( prediv == CRG_PREDIV2 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV2);
else if ( prediv == CRG_PREDIV4 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV4);
else if ( prediv == CRG_PREDIV8 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV8);
else if ( prediv == CRG_PREDIV16 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV16);
else if ( prediv == CRG_PREDIV32 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV32);
else if ( prediv == CRG_PREDIV64 ) CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV64);
else CRG_SET_PWMCLK_PREDIV(num,CRG_PWMCLK_PVSR_DIV128);
}
void CRG_RTC_HS_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_RTC_HS_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_RCLK;
else CRG->RTC_HS_SSR = CRG_RTC_HS_SSR_OCLK;
if ( src != CRG_CLK_DIS ) CRG_RTC_SourceSelect(CRG_CLK_HIGH);
}
void CRG_RTC_HS_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_RTC_HS_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV4;
else if ( prediv == CRG_PREDIV8 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV8;
else if ( prediv == CRG_PREDIV16 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV16;
else if ( prediv == CRG_PREDIV32 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV32;
else if ( prediv == CRG_PREDIV64 ) CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV64;
else CRG->RTC_HS_PVSR = CRG_RTC_HS_PVSR_DIV128;
}
void CRG_RTC_SourceSelect(CRG_CLK_LOW_SOURCE src)
{
assert_param(IS_CRG_RTC_LOW_SRC(src));
if (src == CRG_CLK_LOW)
{
CRG_RTC_HS_SourceSelect(CRG_CLK_DIS);
CRG->RTC_SSR = CRG_RTC_SSR_LW;
}
else
{
CRG->RTC_SSR = CRG_RTC_SSR_HS;
}
}
void CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_WDOGCLK_HS_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_RCLK;
else CRG->WDOGCLK_HS_SSR = CRG_WDOGCLK_HS_SSR_OCLK;
if ( src != CRG_CLK_DIS ) CRG_WDOGCLK_SourceSelect(CRG_CLK_HIGH);
}
void CRG_WDOGCLK_HS_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_WDOGCLK_HS_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV4;
else if ( prediv == CRG_PREDIV8 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV8;
else if ( prediv == CRG_PREDIV16 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV16;
else if ( prediv == CRG_PREDIV32 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV32;
else if ( prediv == CRG_PREDIV64 ) CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV64;
else CRG->WDOGCLK_HS_PVSR = CRG_WDOGCLK_HS_PVSR_DIV128;
}
void CRG_WDOGCLK_SourceSelect(CRG_CLK_LOW_SOURCE src)
{
assert_param(IS_CRG_WDOGCLK_LOW_SRC(src));
if (src == CRG_CLK_LOW)
{
CRG_WDOGCLK_HS_SourceSelect(CRG_CLK_DIS);
CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_LW;
}
else
{
CRG->WDOGCLK_SSR = CRG_WDOGCLK_SSR_HS;
}
}
void CRG_UARTCLK_SourceSelect(CRG_CLK_SOURCE src)
{
assert_param(IS_CRG_UARTCLK_SRC(src));
if ( src == CRG_CLK_DIS ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_DIS;
else if ( src == CRG_MCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_MCLK;
else if ( src == CRG_RCLK ) CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK;
else CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_OCLK;
}
void CRG_UARTCLK_SetPrescale(CRG_PREDIV prediv)
{
assert_param(IS_CRG_UARTCLK_PREDIV(prediv));
if ( prediv == CRG_PREDIV1 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV1;
else if ( prediv == CRG_PREDIV2 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV2;
else if ( prediv == CRG_PREDIV4 ) CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV4;
else CRG->UARTCLK_PVSR = CRG_UARTCLK_PVSR_DIV8;
}
void CRG_MII_Enable(FunctionalState rx_clk, FunctionalState tx_clk)
{
assert_param(IS_FUNCTIONAL_STATE(rx_clk));
assert_param(IS_FUNCTIONAL_STATE(tx_clk));
if ( rx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_RXCLK;
else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_RXCLK);
if ( tx_clk != DISABLE ) CRG->MIICLK_ECR |= CRG_MIICLK_ECR_EN_TXCLK;
else CRG->MIICLK_ECR &= ~(CRG_MIICLK_ECR_EN_TXCLK);
}
void CRG_SetMonitoringClock(uint32_t value)
{
assert_param(IS_CRG_MONCLK_SSR(value));
CRG->MONCLK_SSR = value;
}
uint32_t CRG_GetMonitoringClock(void)
{
return (uint8_t)CRG->MONCLK_SSR;
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the Clock Reset Generator
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_CRG_H
#define __W7500X_CRG_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
// It will be in W7500x_crg.h
typedef enum { CRG_CLK_DIS = 0, CRG_MCLK, CRG_RCLK, CRG_OCLK } CRG_CLK_SOURCE;
typedef enum { CRG_CLK_HIGH = 0, CRG_CLK_LOW } CRG_CLK_LOW_SOURCE;
typedef enum { CRG_PREDIV1 = 0, CRG_PREDIV2, CRG_PREDIV4, CRG_PREDIV8, CRG_PREDIV16, \
CRG_PREDIV32, CRG_PREDIV64, CRG_PREDIV128 } CRG_PREDIV;
typedef enum { CRG_TIMER0 = 0, CRG_TIMER1 } CRG_TIMER;
typedef enum { CRG_PWM0 = 0, CRG_PWM1, CRG_PWM2, CRG_PWM3, CRG_PWM4, CRG_PWM5, CRG_PWM6, CRG_PWM7 } CRG_PWM;
#define IS_CRG_PLL_SRC(SRC) (((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
#define IS_CRG_FCLK_SRC(SRC) (((SRC) == CRG_MCLK) || ((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
#define CRG_CLK_SRC_DEFAULT(SRC) (((SRC) == CRG_CLK_DIS) || ((SRC) == CRG_MCLK) || \
((SRC) == CRG_RCLK) || ((SRC) == CRG_OCLK))
#define CRG_CLK_SRC_LOW(SRC) (((SRC) == CRG_CLK_HIGH) || ((SRC) == CRG_CLK_LOW))
#define CRG_CLK_PREDIV_DEFAULT(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8))
#define CRG_CLK_PREDIV_ADVANCE(DIV) (((DIV) == CRG_PREDIV1) || ((DIV) == CRG_PREDIV2) || \
((DIV) == CRG_PREDIV4) || ((DIV) == CRG_PREDIV8) || \
((DIV) == CRG_PREDIV16) || ((DIV) == CRG_PREDIV32) || \
((DIV) == CRG_PREDIV64) || ((DIV) == CRG_PREDIV128))
#define IS_CRG_FCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_SSPCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_SSPCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_ADCCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_ADCCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_TIMERCLK_NUM(NUM) (((NUM) == CRG_TIMER0) || ((NUM) == CRG_TIMER1))
#define IS_CRG_TIMERCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_TIMERCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define CRG_SET_TIMERCLK_SSR(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->TIMER0CLK_SSR) + (0x10ul * NUM)) = VALUE)
#define CRG_SET_TIMERCLK_PREDIV(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->TIMER0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
//#define CRG_SET_TIMERCLK_SSR(num,value) CRG->TIMER##num##CLK_SSR = value
//#define CRG_SET_TIMERCLK_PREDIV(num,value) CRG->TIMER##num##CLK_PVSR = value
#define IS_CRG_PWMCLK_NUM(NUM) (((NUM) == CRG_PWM0) || ((NUM) == CRG_PWM1) || \
((NUM) == CRG_PWM2) || ((NUM) == CRG_PWM3) || \
((NUM) == CRG_PWM4) || ((NUM) == CRG_PWM5) || \
((NUM) == CRG_PWM6) || ((NUM) == CRG_PWM7) )
#define IS_CRG_PWMCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_PWMCLK_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define CRG_SET_PWMCLK_SSR(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->PWM0CLK_SSR) + (0x10ul * NUM)) = VALUE)
#define CRG_SET_PWMCLK_PREDIV(NUM,VALUE) \
(*((volatile uint32_t *)(CRG->PWM0CLK_PVSR) + (0x10ul * NUM)) = VALUE)
//#define CRG_SET_PWMCLK_SSR(num,value) CRG->PWM##num##CLK_SSR = value
//#define CRG_SET_PWMCLK_PREDIV(num,value) CRG->PWM##num##CLK_PVSR = value
#define IS_CRG_RTC_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_RTC_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define IS_CRG_RTC_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
#define IS_CRG_WDOGCLK_HS_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_WDOGCLK_HS_PREDIV(DIV) CRG_CLK_PREDIV_ADVANCE(DIV)
#define IS_CRG_WDOGCLK_LOW_SRC(SRC) CRG_CLK_SRC_LOW(SRC)
#define IS_CRG_UARTCLK_SRC(SRC) CRG_CLK_SRC_DEFAULT(SRC)
#define IS_CRG_UARTCLK_PREDIV(DIV) CRG_CLK_PREDIV_DEFAULT(DIV)
#define IS_CRG_MONCLK_SSR(value) (((value) >= 0x00ul) || ((value) <= 0x13ul))
void CRG_DeInit(void);
void CRG_OSC_PowerDownEnable (FunctionalState NewState);
void CRG_PLL_PowerDownEnable (FunctionalState NewState);
void CRG_PLL_OutputEnable (FunctionalState NewState);
void CRG_PLL_BypassEnable (FunctionalState NewState);
void CRG_PLL_InputFrequencySelect (CRG_CLK_SOURCE src);
void CRG_FCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_FCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_SSPCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_SSPCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_ADCCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_ADCCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_TIMERCLK_SourceSelect (CRG_TIMER num, CRG_CLK_SOURCE src);
void CRG_TIMERCLK_SetPrescale (CRG_TIMER num, CRG_PREDIV prediv);
void CRG_PWMCLK_SourceSelect (CRG_PWM num, CRG_CLK_SOURCE src);
void CRG_PWMCLK_SetPrescale (CRG_PWM num, CRG_PREDIV prediv);
void CRG_RTC_HS_SourceSelect (CRG_CLK_SOURCE src);
void CRG_RTC_HS_SetPrescale (CRG_PREDIV prediv);
void CRG_RTC_SourceSelect (CRG_CLK_LOW_SOURCE src);
void CRG_WDOGCLK_HS_SourceSelect (CRG_CLK_SOURCE src);
void CRG_WDOGCLK_HS_SetPrescale (CRG_PREDIV prediv);
void CRG_WDOGCLK_SourceSelect (CRG_CLK_LOW_SOURCE src);
void CRG_UARTCLK_SourceSelect (CRG_CLK_SOURCE src);
void CRG_UARTCLK_SetPrescale (CRG_PREDIV prediv);
void CRG_MII_Enable (FunctionalState rx_clk, FunctionalState tx_clk);
void CRG_SetMonitoringClock (uint32_t value);
uint32_t CRG_GetMonitoringClock (void);
#ifdef __cplusplus
}
#endif
#endif

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#include "W7500x.h"
/**
* @brief Deinitializes the EXTI peripheral registers to their default reset values.
* @param None
* @retval None
*/
void EXTI_DeInit(void)
{
uint32_t i, loop =16;
for(i=0; i<loop; i++)
{
EXTI_PA->Port[i] = 0x00;
EXTI_PB->Port[i] = 0x00;
EXTI_PC->Port[i] = 0x00;
}
for(i=0; i<5; i++)
{
EXTI_PD->Port[i] = 0x00;
}
}
/**
* @brief Initializes the EXTI peripheral according to the specified
* parameters in the EXTI_InitStruct.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
* that contains the configuration information for the EXTI peripheral.
* @retval None
*/
void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(pinpos = 0x00; pinpos < loop; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (EXTI_InitStruct->EXTI_Line) & pos;
if(currentpin == pos)
{
px_exti->Port[pinpos] |= EXTI_Px_INTEN_ENABLE;
if(EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising)
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
else
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
}
}
}
void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity )
{
uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(pinpos = 0x00; pinpos < loop; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = GPIO_Pin & pos;
if(currentpin == pos)
{
if(Polarity == EXTI_Trigger_Rising)
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_RISING_EDGE;
else
px_exti->Port[pinpos] |= EXTI_Px_INTPOR_FALLING_EDGE;
}
}
}
/**
* @brief Fills each EXTI_InitStruct member with its reset value.
* @param EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
* be initialized.
* @retval None
*/
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
{
EXTI_InitStruct->EXTI_Line = 0xFF;
EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
}
uint16_t EXTI_Px_GetEXTEN(PAD_Type Px)
{
uint32_t i, loop = 16;
uint16_t ret=0;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(i = 0x00; i < loop; i++)
{
ret |= (((px_exti->Port[i]&0x2)>>1)<<i);
}
return ret;
}
uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px)
{
uint32_t i, loop = 16;
uint16_t ret=0;
P_Port_Def *px_exti;
assert_param(IS_PAD_TYPE(Px));
if (Px == PAD_PA) px_exti = EXTI_PA;
else if (Px == PAD_PB) px_exti = EXTI_PB;
else if (Px == PAD_PC) px_exti = EXTI_PC;
else
{
px_exti = (P_Port_Def*)EXTI_PD;
loop = 5;
}
for(i = 0x00; i < loop; i++)
{
ret |= ((px_exti->Port[i]&0x1)<<i);
}
return ret;
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_EXTI_H
#define __W7500X_EXTI_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
/**
* @brief EXTI mode enumeration
*/
typedef enum
{
EXTI_Mode_Disable = 0x00,
EXTI_Mode_Interrupt = 0x02
}EXTIMode_TypeDef;
#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Rising) || \
((MODE) == EXTI_Mode_Interrupt))
/**
* @brief EXTI Trigger enumeration
*/
typedef enum
{
EXTI_Trigger_Rising = 0x00,
EXTI_Trigger_Falling = 0x01
}EXTITrigger_TypeDef;
#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
((TRIGGER) == EXTI_Trigger_Falling))
/**
* @brief EXTI Init Structure definition
*/
typedef struct
{
uint32_t EXTI_Line; /*!< Specifies the EXTI lines to be enabled or disabled.
This parameter can be any combination of @ref EXTI_Lines */
EXTIMode_TypeDef EXTI_Mode; /*!< Specifies the mode for the EXTI lines.This parameter can be a value of @ref EXTIMode_TypeDef */
EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
This parameter can be a value of @ref EXTIMode_TypeDef */
}EXTI_InitTypeDef;
/**
* @}
*/
void EXTI_DeInit(void);
void EXTI_Init(PAD_Type Px, EXTI_InitTypeDef* EXTI_InitStruct);
void EXTI_Polarity_Set(PAD_Type Px, uint16_t GPIO_Pin, uint16_t Polarity );
void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
uint32_t EXTI_GetEXTIConfig(PAD_Type Px, uint16_t GPIO_Pin);
uint16_t EXTI_Px_GetEXTEN(PAD_Type Px);
uint16_t EXTI_Px_GetEXTINTPOL(PAD_Type Px);
#ifdef __cplusplus
}
#endif
#endif //__W7500X_EXTI_H

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#include "W7500x.h"
void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx)
{
uint32_t i, loop =16;
P_Port_Def *px_pcr;
P_Port_Def *px_afsr;
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
/* DeInit GPIOx Registers */
GPIOx->DATA = 0x0000;
GPIOx->DATAOUT = 0x0000;
//GPIOx->OUTENSET = 0x0000;
GPIOx->OUTENCLR = 0xFFFF;
//GPIOx->INTENSET = 0x0000;
GPIOx->INTENCLR = 0xFFFF;
//GPIOx->INTTYPESET = 0x0000;
GPIOx->INTTYPECLR = 0xFFFF;
//GPIOx->INTPOLSET = 0x0000;
GPIOx->INTPOLCLR = 0xFFFF;
/* DeInit GPIOx
* Pad Control Register
* Pad Extern interrupt Enable Register
* Pad Alternate Function Select Register
*/
if (GPIOx == GPIOA)
{
px_pcr = PA_PCR;
px_afsr = PA_AFSR;
}
else if (GPIOx == GPIOB)
{
px_pcr = PB_PCR;
px_afsr = PB_AFSR;
}
else if (GPIOx == GPIOC)
{
px_pcr = PC_PCR;
px_afsr = PC_AFSR;
}
else // if (GPIOx == GPIOD)
{
px_pcr = (P_Port_Def*)PD_PCR;
px_afsr = (P_Port_Def*)PD_AFSR;
loop = 5;
}
for(i=0; i<loop; i++)
{
px_pcr->Port[i] = 0x60;
px_afsr->Port[i] = PAD_AF0;
}
}
void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
{
uint32_t pinpos = 0x00, pos = 0x00, currentpin = 0x00, loop = 16;
P_Port_Def *px_pcr;
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
// assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
if (GPIOx == GPIOA) px_pcr = PA_PCR;
else if (GPIOx == GPIOB) px_pcr = PB_PCR;
else if (GPIOx == GPIOC) px_pcr = PC_PCR;
else
{
px_pcr = (P_Port_Def*)PD_PCR;
loop = 5;
}
for(pinpos = 0x00; pinpos < loop; pinpos++)
{
pos = ((uint32_t)0x01) << pinpos;
currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
if(currentpin == pos)
{
if(GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT)
{
GPIOx->OUTENSET |= pos;
}
else // GPIO_Mode_In
{
GPIOx->OUTENCLR = pos;
}
// Configure pull-up pull-down bits
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_PUPD_UP)
{
px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
px_pcr->Port[pinpos] |= Px_PCR_PUPD_UP;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_PUPD_UP | Px_PCR_PUPD_DOWN);
px_pcr->Port[pinpos] |= Px_PCR_PUPD_DOWN;
}
// Configure Driving stregnth selections bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_DS_HIGH)
{
px_pcr->Port[pinpos] |= Px_PCR_DS_HIGH;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_DS_HIGH);
}
// Configure Open Drain selections bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_OD)
{
px_pcr->Port[pinpos] |= Px_PCR_OD;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_OD);
}
// Configure Input buffer enable selection bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_IE)
{
px_pcr->Port[pinpos] |= Px_PCR_IE;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_IE);
}
// Configure input type (CMOS input or Summit trigger input) select bit
if(GPIO_InitStruct->GPIO_Pad & Px_PCR_CS_SUMMIT)
{
px_pcr->Port[pinpos] |= Px_PCR_CS_SUMMIT;
}
else
{
px_pcr->Port[pinpos] &= ~(Px_PCR_CS_SUMMIT);
}
}
}
}
void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
{
GPIO_InitStruct->GPIO_Pin = GPIO_Pin_All;
GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
GPIO_InitStruct->GPIO_Pad = (GPIOPad_TypeDef)(GPIO_PuPd_UP);
}
uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if((GPIOx->DATA & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
return ((uint16_t)GPIOx->DATA);
}
uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
uint8_t bitstatus = 0x00;
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
if((GPIOx->DATAOUT & GPIO_Pin) != (uint32_t)Bit_RESET)
{
bitstatus = (uint8_t)Bit_SET;
}
else
{
bitstatus = (uint8_t)Bit_RESET;
}
return bitstatus;
}
uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
{
/* Check the parameters */
assert_param(IS_GPIO_ALLPERIPH(GPIOx));
return ((uint16_t)GPIOx->DATAOUT);
}
void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
(GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = GPIO_Pin;
(GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = GPIO_Pin;
}
void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GPIO_PIN(GPIO_Pin));
(GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = ~(GPIO_Pin);
(GPIOx->UB_MASKED[(uint8_t)(GPIO_Pin>>8)]) = ~(GPIO_Pin);
}
void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
assert_param(IS_GPIO_BIT_ACTION(BitVal));
(GPIOx->LB_MASKED[(uint8_t)(GPIO_Pin)]) = BitVal;
(GPIOx->UB_MASKED[(uint8_t)((GPIO_Pin)>>8)]) = BitVal;
}
void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
{
/* Check the parameters */
assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
GPIOx->DATAOUT = PortVal;
}
void HAL_PAD_AFConfig(PAD_Type Px, uint16_t GPIO_Pin, PAD_AF_TypeDef P_AF)
{
int i;
uint16_t idx =0x1;
assert_param(IS_PAD_Type(Px));
for(i=0;i<16;i++)
{
if(GPIO_Pin & (idx<<i))
{
if(Px == PAD_PA)
{
assert_param(IS_PA_NUM(i));
PA_AFSR->Port[i] &= ~(0x03ul);
PA_AFSR->Port[i] |= P_AF;
}
else if(Px == PAD_PB)
{
assert_param(IS_PB_NUM(i));
PB_AFSR->Port[i] &= ~(0x03ul);
PB_AFSR->Port[i] |= P_AF;
}
else if(Px == PAD_PC)
{
assert_param(IS_PC_NUM(i));
PC_AFSR->Port[i] &= ~(0x03ul);
PC_AFSR->Port[i] |= P_AF;
}
else
{
assert_param(IS_PD_NUM(i));
PD_AFSR->Port[i] &= ~(0x03ul);
PD_AFSR->Port[i] |= P_AF;
}
}
}
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the GPIO
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_HAL_GPIO_H
#define __W7500X_HAL_GPIO_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
#define GPIO_Pin_0 (uint16_t)(0x01 << 0) // Pin 0 Selected
#define GPIO_Pin_1 (uint16_t)(0x01 << 1) // Pin 1 Selected
#define GPIO_Pin_2 (uint16_t)(0x01 << 2) // Pin 2 Selected
#define GPIO_Pin_3 (uint16_t)(0x01 << 3) // Pin 3 Selected
#define GPIO_Pin_4 (uint16_t)(0x01 << 4) // Pin 4 Selected
#define GPIO_Pin_5 (uint16_t)(0x01 << 5) // Pin 5 Selected
#define GPIO_Pin_6 (uint16_t)(0x01 << 6) // Pin 6 Selected
#define GPIO_Pin_7 (uint16_t)(0x01 << 7) // Pin 7 Selected
#define GPIO_Pin_8 (uint16_t)(0x01 << 8) // Pin 8 Selected
#define GPIO_Pin_9 (uint16_t)(0x01 << 9) // Pin 9 Selected
#define GPIO_Pin_10 (uint16_t)(0x01 << 10) // Pin 10 Selected
#define GPIO_Pin_11 (uint16_t)(0x01 << 11) // Pin 11 Selected
#define GPIO_Pin_12 (uint16_t)(0x01 << 12) // Pin 12 Selected
#define GPIO_Pin_13 (uint16_t)(0x01 << 13) // Pin 13 Selected
#define GPIO_Pin_14 (uint16_t)(0x01 << 14) // Pin 14 Selected
#define GPIO_Pin_15 (uint16_t)(0x01 << 15) // Pin 15 Selected
#define GPIO_Pin_All (uint16_t)(0xFFFF) // All pins Selected
#define IS_GPIO_PIN(PIN) ((PIN) != (uint16_t)0x00)
#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || ((PIN) == GPIO_Pin_1) || \
(((PIN) == GPIO_Pin_2) || ((PIN) == GPIO_Pin_3) || \
(((PIN) == GPIO_Pin_4) || ((PIN) == GPIO_Pin_5) || \
(((PIN) == GPIO_Pin_6) || ((PIN) == GPIO_Pin_7) || \
(((PIN) == GPIO_Pin_8) || ((PIN) == GPIO_Pin_9) || \
(((PIN) == GPIO_Pin_10) || ((PIN) == GPIO_Pin_11) || \
(((PIN) == GPIO_Pin_12) || ((PIN) == GPIO_Pin_13) || \
(((PIN) == GPIO_Pin_14) || ((PIN) == GPIO_Pin_15) )
#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || ((PERIPH) == GPIOB) || \
((PERIPH) == GPIOC) || ((PERIPH) == GPIOD) )
typedef enum
{
GPIO_Mode_IN = 0x00, /*!< GPIO Input Mode */
GPIO_Mode_OUT = 0x01, /*!< GPIO Output Mode */
GPIO_Mode_AF = 0x02 /*!< GPIO Alternate function Mode */
}GPIOMode_TypeDef;
typedef enum
{
GPIO_NO_PUPD = 0x0ul,
GPIO_PuPd_UP = Px_PCR_PUPD_UP,
GPIO_PuPd_DOWN = Px_PCR_PUPD_DOWN,
GPIO_OD = Px_PCR_OD,
}GPIOPad_TypeDef;
typedef struct
{
uint32_t GPIO_Pin;
GPIOMode_TypeDef GPIO_Mode;
GPIOPad_TypeDef GPIO_Pad;
}GPIO_InitTypeDef;
typedef enum
{
Bit_RESET = 0,
Bit_SET
}BitAction;
typedef enum
{
PAD_PA = 0,
PAD_PB,
PAD_PC,
PAD_PD
}PAD_Type;
typedef enum
{
PAD_AF0 = Px_AFSR_AF0,
PAD_AF1 = Px_AFSR_AF1,
PAD_AF2 = Px_AFSR_AF2,
PAD_AF3 = Px_AFSR_AF3
}PAD_AF_TypeDef;
#define IS_PAD_TYPE(Px) (((Px) == PAD_PA) || ((Px) == PAD_PB) \
((Px) == PAD_PC) || ((Px) == PAD_PD))
#define IS_PA_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
#define IS_PB_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
#define IS_PC_NUM(NUM) (((NUM)>=0) && ((NUM)<16))
#define IS_PD_NUM(NUM) (((NUM)>=0) && ((NUM)< 5))
#define IS_PAD_AF(AF) (((AF) == PAD_AF0) || ((AF) == PAD_AF1) || \
((AF) == PAD_AF2) || ((AF) == PAD_AF3))
#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION_ == Bit_RESET) || (ACTION) ==Bit_SET))
void HAL_GPIO_DeInit(GPIO_TypeDef* GPIOx);
void HAL_GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
void HAL_GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
uint8_t HAL_GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint8_t HAL_GPIO_ReadInputData(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint8_t HAL_GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
uint16_t HAL_GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
void HAL_GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
void HAL_GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
void HAL_GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
void HAL_PAD_AFConfig(PAD_Type Px, uint16_t Pnum, PAD_AF_TypeDef P_AF);
#ifdef __cplusplus
}
#endif
#endif // __W7500X_HAL_GPIO_H

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#include "W7500x.h"
/** @defgroup I2C_Private_Functions
* @{
*/
/**
* @brief Initializes the I2Cx peripheral according to the specified
* parameters in the I2C_InitStruct.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_InitStruct: pointer to a I2C_InitTypeDef structure that
* contains the configuration information for the specified I2C peripheral.
* @retval None
*/
void I2C_Delay(uint32_t nCount)
{
for(; nCount != 0; nCount--);
}
uint32_t I2C_Init(I2C_TypeDef* I2Cx, I2C_ConfigStruct conf)
{
uint32_t mode;
uint8_t prescale;
uint16_t timeout;
uint16_t slave_address;
mode = conf.mode;
slave_address = conf.slave_address;
if(mode == I2C_Master)
{
prescale = conf.master.prescale;
timeout = conf.master.timeout;
I2C_CoreEn(I2Cx,ENABLE);
I2C_MasterSlave(I2Cx,ENABLE);
I2C_Prescale(I2Cx,prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz
I2C_TimeoutSet(I2Cx,timeout); // 0xFFFF
I2C_CoreEn(I2Cx,DISABLE);
}
else if(conf.mode == I2C_Slave)
{
I2C_AcknowledgeConfig(I2Cx,ENABLE);
I2C_SetSlavAddress(I2Cx,slave_address);
}
else
return ERROR;
I2C_AcknowledgeConfig(I2Cx,ENABLE);
return SUCCESS;
}
void I2C_DeInit(I2C_TypeDef* I2Cx)
{
I2C_InterRst(I2Cx,ENABLE);
I2C_CoreEn(I2Cx, ENABLE);
I2C_InterRst(I2Cx,DISABLE);
I2C_CoreEn(I2Cx, DISABLE);
}
ErrorStatus I2C_Start(I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr)
{
ErrorStatus ret;
I2C_GenerateSTART(I2Cx,ENABLE);
I2C_SendSlaveAddress(I2Cx,slave_address,(I2C_CTR)ctr);
I2C_GenerateSTART(I2Cx,DISABLE);
ret=I2C_CheckEvent(I2Cx,I2C_ACKR);
return ret;
}
void I2C_Stop(I2C_TypeDef* I2Cx)
{
I2C_GenerateSTOP(I2Cx,ENABLE);
I2C_GenerateSTOP(I2Cx,DISABLE);
}
void I2C_Reset(I2C_TypeDef* I2Cx)
{
I2C_CoreEn(I2Cx,ENABLE);
// Maybe, it needs a little delay
I2C_CoreEn(I2Cx,DISABLE);
}
void I2C_SendData(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> TXR = (uint16_t)Data;
}
int8_t I2C_SendDataAck(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> TXR = (uint16_t)Data;
if(I2C_CheckEvent(I2Cx,I2C_ACKR) == ERROR)
{
return ERROR;
}
return SUCCESS;
}
int I2C_ReceiveData(I2C_TypeDef* I2Cx, int last)
{
if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR )
return -1;
if(last)
{
I2C_AcknowledgeConfig(I2Cx,DISABLE);
if( I2C_CheckEvent(I2Cx,I2C_ACKT) == ERROR )
return -1;
I2C_Stop(I2Cx);
}
return (uint8_t)I2Cx -> RXR;
}
int I2C_Burst_Read(I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop)
{
int recv_cnt;
if( I2C_Start(I2Cx,address,I2C_READ_SA7) == ERROR){
return -1;
}
for(recv_cnt=0;recv_cnt<length;recv_cnt++)
{
}
return recv_cnt;
}
int I2C_Burst_Write(I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop)
{
int cnt;
if( I2C_Start(I2Cx,address,I2C_WRITE_SA7) == ERROR)
{
return -1;
}
for(cnt=0;cnt<length;cnt++)
{
if( I2C_SendDataAck(I2Cx,data[cnt]) == ERROR )
{
I2C_Stop(I2Cx);
return -1;
}
}
// If not repeated start, send stop
if(stop)
{
I2C_Stop(I2Cx);
}
return length;
}
/**
* @brief Generates I2Cx communication START condition.
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C START condition generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_STA;
else I2Cx->CMDR = I2C_CMDR_STA;
}
/**
* @brief Generates I2Cx communication STOP condition.
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C STOP condition generation.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_STO;
else I2Cx->CMDR = I2C_CMDR_STO;
}
/**
* @brief Enables or disables the specified I2C acknowledge feature.
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C Acknowledgement.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx -> CMDR = I2C_CMDR_ACK;
else I2Cx -> CMDR = I2C_CMDR_ACK;
}
/**
* @brief Generates I2Cx communication REGenerateSTART condition
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C Acknowledgement.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_RESTART(I2C_TypeDef * I2Cx, FunctionalState NewState)
{
if(NewState != DISABLE) I2Cx->CMDR = I2C_CMDR_RESTA;
else I2Cx->CMDR = I2C_CMDR_RESTA;
}
/**
* @brief Enable or disable the specified I2C Core_en feature
* @param I2Cx: where x can be 0 or 1 to select the I2C peripheral.
* @param NewState: NewState of the I2C Acknowledgement.
* This parameter can be: ENABLE or DISABLE.
* @retval None.
*/
void I2C_CoreEn(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control*/
if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_COREEN;
else I2Cx -> CTR = I2C_CTR_COREEN;
}
void I2C_InterEn(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control Interrupt Enable*/
if(NewState != DISABLE) I2Cx -> CTR = I2C_CTR_INTEREN;
else I2Cx -> CTR = I2C_CTR_INTEREN;
}
void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control MasterSlave select*/
if(NewState == ENABLE)
{
if( (I2Cx->CTR & I2C_CTR_MODE) != I2C_CTR_MODE )
{
I2Cx->CTR = I2C_CTR_MODE;
}
}
else // DISABLE
{
if( (I2Cx->CTR & I2C_CTR_MODE) == I2C_CTR_MODE )
{
I2Cx->CTR = I2C_CTR_MODE;
}
}
}
void I2C_ControlRW(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control Read(receive)*/
if(NewState == ENABLE)
{
if( (I2Cx->CTR & I2C_CTR_CTRRWN) != I2C_CTR_CTRRWN )
{
I2Cx->CTR = I2C_CTR_CTRRWN;
}
}
else // DISABLE
{
if( (I2Cx->CTR & I2C_CTR_CTRRWN) == I2C_CTR_CTRRWN )
{
I2Cx->CTR = I2C_CTR_CTRRWN;
}
}
}
void I2C_ControlEn(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control*/
if(NewState == ENABLE)
{
if( (I2Cx->CTR & I2C_CTR_CTEN) != I2C_CTR_CTEN )
{
I2Cx->CTR = I2C_CTR_CTEN;
}
}
else // DISABLE
{
if( (I2Cx->CTR & I2C_CTR_CTEN) == I2C_CTR_CTEN )
{
I2Cx->CTR = I2C_CTR_CTEN;
}
}
}
void I2C_InterRst(I2C_TypeDef* I2Cx,FunctionalState NewState)
{
/*Control*/
if(NewState == ENABLE)
{
if( (I2Cx->ISCR & I2C_ISCR_RST) != I2C_ISCR_RST )
{
I2Cx->ISCR = I2C_ISCR_RST;
}
}
else // DISABLE
{
if( (I2Cx->ISCR & I2C_ISCR_RST) == I2C_ISCR_RST )
{
I2Cx->ISCR = I2C_ISCR_RST;
}
}
}
void I2C_Prescale(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> PRER = (uint16_t)Data;
}
void I2C_TimeoutSet(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> TSR = (uint16_t)Data;
}
void I2C_SetSlavAddress(I2C_TypeDef* I2Cx,uint16_t Data)
{
I2Cx -> SADDR = (uint16_t)Data;
}
uint8_t I2C_StatusRead(I2C_TypeDef* I2Cx)
{
return (uint8_t)I2Cx -> SR;
}
ErrorStatus WaitEvent(I2C_TypeDef* I2Cx, uint32_t flag, FlagStatus status)
{
int Timeout=0,loopcnt=0;
Timeout = I2Cx->TSR;
if(status == SET)
{
for(loopcnt=Timeout; loopcnt>0; loopcnt--)
{
if( ((I2Cx->SR) & flag) == flag )
return SUCCESS;
}
}
else
{
for(loopcnt=Timeout; loopcnt>0; loopcnt--)
{
if( ((I2Cx->SR) & flag) != flag )
return SUCCESS;
}
}
return ERROR;
}
/**
* @brief Checks whether the specified I2C flag is set or not.
* @param I2Cx: where x can be 1 or 2 to select the I2C peripheral.
* @param I2C_EVENT: specifies the event to be checked.
*/
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr)
{
switch(sr)
{
case(I2C_ACKR):
if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR;
if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR;
break;
case(I2C_ACKT ):
if( WaitEvent(I2Cx, I2C_SR_ACKT, SET) == ERROR) return ERROR;
if( WaitEvent(I2Cx, I2C_SR_ACKT, RESET) == ERROR) return ERROR;
break;
case(I2C_OACKR):
if( WaitEvent(I2Cx, I2C_SR_ACKR, SET) == ERROR) return ERROR;
break;
case(I2C_SACKR ):
if( WaitEvent(I2Cx, I2C_SR_ACKR, RESET) == ERROR) return ERROR;
break;
case(I2C_BT ):
if( WaitEvent(I2Cx, I2C_SR_BT, RESET) == ERROR) return ERROR;
break;
default:
return ERROR;
}
return SUCCESS;
}
/*
void I2C_MasterInit(I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr)
{
switch(Ctr)
{
case(I2C_WRITE_SA7): //000
case(I2C_READ_SA7): //001
I2C_CoreEn(I2Cx,ENABLE);
break;
case(I2C_WRITE_SA10): //010
case(I2C_READ_SA10): //011
I2C_CoreEn(I2Cx,ENABLE);
I2C_SlaveAddressLength(I2Cx,ENABLE);
break;
case(I2C_CTRWRITE_SA7): //100
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlEn(I2Cx,ENABLE);
break;
case(I2C_CTRREAD_SA7): //101
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlRW(I2Cx,ENABLE);
I2C_ControlEn(I2Cx,ENABLE);
break;
case(I2C_CTRWRITE_SA10): //110
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlRW(I2Cx,DISABLE);
I2C_ControlEn(I2Cx,ENABLE);
I2C_SlaveAddressLength(I2Cx,ENABLE);
break;
case(I2C_CTRREAD_SA10): //111
I2C_CoreEn(I2Cx,ENABLE);
I2C_ControlRW(I2Cx,ENABLE);
I2C_ControlEn(I2Cx,ENABLE);
I2C_SlaveAddressLength(I2Cx,ENABLE);
break;
default:
return;
}
I2C_MasterSlave(I2Cx,ENABLE);
I2C_MasterSlave(I2Cx,DISABLE);
I2C_MasterSlave(I2Cx,ENABLE);
I2C_Prescale(I2Cx,Prescale); // 0x61 //When PLL clk is 20MHz and Prescale value set 0x61, SCL is 100KHz
I2C_TimeoutSet(I2Cx,Timeout); // 0xFFFF
#if defined(I2C_INT)
I2C_CoreEn(I2Cx,DISABLE);
I2C_InterEn(I2Cx,ENABLE);
#else
I2C_CoreEn(I2Cx,DISABLE);
#endif
}
void I2C_SlaveInit(I2C_TypeDef * I2Cx, FunctionalState NewState,uint16_t data)
{
if(NewState != DISABLE)
{
I2C_SlaveAddressLength(I2Cx,ENABLE);
}
else
I2C_AcknowledgeConfig(I2Cx,ENABLE);
I2C_SetSlavAddress(I2Cx,data);
}
*/
void I2C_SendSlaveAddress(I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr)
{
switch(Ctr)
{
case(I2C_READ_SA7):
I2C_SendData(I2Cx,SlaveAddress|I2C_READ);
break;
case(I2C_WRITE_SA7):
I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE);
break;
// case(I2C_READ_SA10):
// I2C_SendData(I2Cx,SlaveAddress|I2C_READ);
// break;
//
// case(I2C_WRITE_SA10):
// I2C_SendData(I2Cx,SlaveAddress|I2C_WRITE);
// break;
case(I2C_CTRWRITE_SA7):
case(I2C_CTRREAD_SA7):
// case(I2C_CTRWRITE_SA10):
// case(I2C_CTRREAD_SA10):
I2C_SendData(I2Cx,SlaveAddress);
break;
default:
return;
}
}
int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr)
{
I2C_RESTART(I2Cx,ENABLE);
I2C_SendSlaveAddress(I2Cx,SlaveAddress,Ctr);
if((I2C_CheckEvent(I2Cx,I2C_OACKR)) == ERROR )
{
return 0;
}
I2C_RESTART(I2Cx,DISABLE);
if((I2C_CheckEvent(I2Cx,I2C_SACKR)) == ERROR)
{
return 0;
}
return 1;
}
/**
* @brief Reads the specified I2C register and returns its value.
* @param I2C_Register: specifies the register to read.
* This parameter can be one of the following values:
* @arg I2C_Register_CR1: CR1 register.
* @arg I2C_Register_CR2: CR2 register.
* @arg I2C_Register_OAR1: OAR1 register.
* @arg I2C_Register_OAR2: OAR2 register.
* @arg I2C_Register_DR: DR register.
* @arg I2C_Register_SR1: SR1 register.
* @arg I2C_Register_SR2: SR2 register.
* @arg I2C_Register_CCR: CCR register.
* @arg I2C_Register_TRISE: TRISE register.
* @retval The value of the read register.
*/
uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
{
__IO uint32_t tmp = 0;
tmp = (uint32_t) I2Cx;
tmp += I2C_Register;
/* Return the selected register value */
return (*(__IO uint16_t *) tmp);
}

231
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_i2c.h Normal file
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#include "W7500x.h"
/**
* @defgroup I2C_Public_Types I2X Public Types
*/
typedef enum
{
I2C_WRITE_SA7=0,
I2C_READ_SA7,
//I2C_WRITE_SA10,
//I2C_READ_SA10,
I2C_CTRWRITE_SA7,
I2C_CTRREAD_SA7,
//I2C_CTRWRITE_SA10,
//I2C_CTRREAD_SA10,
} I2C_CTR;
typedef enum
{
I2C_ACKR=0,
I2C_ACKT,
I2C_OACKR,
I2C_SACKR,
I2C_BT,
} I2C_SR;
typedef enum
{
INT_ACKR=-1,
INT_ACKT=-2,
INT_NACKR=-3,
INT_NACKT=-4,
INT_BT=-5,
} I2C_ERROR;
/**
*@
*/
/** @defgroup I2C_registers
* @{
*/
#define I2C_Register_PRER ((uint8_t)0x00)
#define I2C_Register_CTR ((uint8_t)0x04)
#define I2C_Register_CMDR ((uint8_t)0x08)
#define I2C_Register_SR ((uint8_t)0x0C)
#define I2C_Register_TSR ((uint8_t)0x10)
#define I2C_Register_SADDR ((uint8_t)0x14)
#define I2C_Register_TXR ((uint8_t)0x18)
#define I2C_Register_RXR ((uint8_t)0x1C)
#define I2C_Register_ISR ((uint8_t)0x20)
#define I2C_Register_ISCR ((uint8_t)0x24)
#define I2C_Register_ISMR ((uint8_t)0x28)
#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_PRER) || \
((REGISTER) == I2C_Register_CTR) || \
((REGISTER) == I2C_Register_CMDR) || \
((REGISTER) == I2C_Register_SR) || \
((REGISTER) == I2C_Register_TSR) || \
((REGISTER) == I2C_Register_SADDR) || \
((REGISTER) == I2C_Register_TXR) || \
((REGISTER) == I2C_Register_RXR) || \
((REGISTER) == I2C_Register_ISR)|| \
((REGISTER) == I2C_Register_ISCR)| \
((REGISTER) == I2C_Register_ISMR))
/**
* @}
*/
/** @addtogroup Peripheral_registers_structures
* @{
*/
/**
* @}
*/
/**
* @brief I2C Interrput Status Register Mask flags
*/
//------------------------------------------------
// I2C_ISMR_BIT
//------------------------------------------------
/**
* @}
*/
/** @defgroup I2C_Private_Defines
* @{
*/
/* I2C COREEN mask */
#define I2C_CTR_COREEN_DIS ((uint16_t)0xFF7F)
/* I2C INTEREN mask */
#define I2C_CTR_INTEREN_DIS ((uint16_t)0xFFBF)
/* I2C MODE(M/SN) mask */
#define I2C_CTR_MODE_SLAVE ((uint16_t)0xFFDF)
/* I2C ADDR10(10/7N) mask */
#define I2C_CTR_ADDR10_7BIT ((uint16_t)0xFFEF)
/* I2C CTRRWN(R/WN) mask */
#define I2C_CTR_CTRRWN_DIS ((uint16_t)0xFFF7)
/* I2C CTREN mask */
#define I2C_CTR_CTEN_DIS ((uint16_t)0xFFFB)
/* I2C START mask */
#define I2C_CMDR_START_DIS ((uint16_t)0xFF7F)
/* I2C STOP mask */
#define I2C_CMDR_STOP_DIS ((uint16_t)0xFFBF)
/* I2C ACK mask */
#define I2C_CMDR_ACK_NAK ((uint16_t)0xFFDF)
/* I2C RESTART mask */
#define I2C_CMDR_RESTA_DIS ((uint16_t)0xFFEF)
/* I2C INTERRUPT RESET mask */
#define I2C_ISCR_RST_DIS ((uint16_t)0xFFFE)
/**
* @}
*/
#define I2C_WRITE 0
#define I2C_READ 1
#define I2C_RWSEL(NewState) (((NewState) == I2C_WRITE)|| \
((NewState) == I2C_READ))
#define I2C_Ack_Enable (0x01ul << 5)
#define I2C_Ack_Disable (0x00ul << 5)
#define IS_I2C_ACK_NewState(NewState) (((NewState) == I2C_Ack_Enable) || \
((NewState) == I2C_Ack_Disable))
#define I2C_MASTER_MODE (0x01ul << 5 ) // 0x20
#define I2C_SLAVE_MODE (0x00ul << 5 ) // 0x20
#define IS_I2C_MODE(MODE) ((MODE) == I2C_MASTER_MODE)|| \
(MODE) == I2C_SLAVE_MODE))
#define I2C_CTR_MODE (0x01ul << 5 ) // 0x20
#define SLAVE_ADDR10 0x208
typedef enum
{
I2C_Master = I2C_MASTER_MODE,
I2C_Slave = I2C_SLAVE_MODE
}I2C_MODE;
typedef struct
{
uint8_t prescale;
uint16_t timeout;
I2C_CTR control;
}I2C_MasterConfStruct;
typedef struct
{
uint32_t mode;
uint16_t slave_address; // only on slave mode
I2C_MasterConfStruct master;
}I2C_ConfigStruct;
/** @defgroup I2C_Exported_Functions
* @{
*/
uint32_t I2C_Init (I2C_TypeDef* I2Cx, I2C_ConfigStruct conf);
void setFrequency (I2C_TypeDef* I2Cx, uint8_t prescale);
void I2C_DeInit (I2C_TypeDef* I2Cx);
ErrorStatus I2C_Start (I2C_TypeDef* I2Cx, uint16_t slave_address, I2C_CTR ctr);
void I2C_Stop (I2C_TypeDef* I2Cx);
void I2C_Reset (I2C_TypeDef* I2Cx);
void I2C_SendData (I2C_TypeDef* I2Cx,uint16_t Data);
int8_t I2C_SendDataAck (I2C_TypeDef* I2Cx,uint16_t Data);
int I2C_ReceiveData (I2C_TypeDef* I2Cx, int last);
int I2C_Burst_Read (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop);
int I2C_Burst_Write (I2C_TypeDef* I2Cx, uint16_t address, uint8_t *data, int length, int stop);
void I2C_Delay (uint32_t nCount);
void I2C_GenerateSTART (I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_GenerateSTOP (I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_AcknowledgeConfig (I2C_TypeDef* I2Cx, FunctionalState NewState);
void I2C_RESTART (I2C_TypeDef * I2Cx, FunctionalState NewState);
void I2C_CoreEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_InterEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_MasterSlave(I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_ControlRW (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_ControlEn (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_InterRst (I2C_TypeDef* I2Cx,FunctionalState NewState);
void I2C_Prescale (I2C_TypeDef* I2Cx,uint16_t Data);
void I2C_TimeoutSet (I2C_TypeDef* I2Cx,uint16_t Data);
void I2C_SetSlavAddress (I2C_TypeDef* I2Cx,uint16_t Data);
uint8_t I2C_StatusRead (I2C_TypeDef* I2Cx);
ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx,I2C_SR sr);
void I2C_MasterInit (I2C_TypeDef * I2Cx,uint8_t Prescale,uint16_t Timeout,I2C_CTR Ctr);
void I2C_SlaveInit (I2C_TypeDef * I2Cx,FunctionalState NewState, uint16_t data);
void I2C_SendSlaveAddress (I2C_TypeDef* I2Cx, uint8_t SlaveAddress,I2C_CTR Ctr);
int8_t I2C_Restart_Structure(I2C_TypeDef * I2Cx,uint32_t SlaveAddress,I2C_CTR Ctr);
uint16_t I2C_ReadRegister (I2C_TypeDef* I2Cx, uint8_t I2C_Register);
/**
* @}
*/

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Includes -------------------------------------------*/
#include "W7500x.h"
void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn)
{
if( PWM_CHn == PWM_CH0 )
{
PWM->IER &= PWM_IER_IE0_Disable; ///< Interrupt enable register
PWM->SSR &= PWM_SSR_SS0_Stop; ///< Start Stop register
PWM->PSR &= PWM_PSR_PS0_Restart; ///< Pause register
PWM_CH0->IER = 0; ///< Interrupt enable register
PWM_CH0->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH0->PR = 0; ///< Prescale register
PWM_CH0->MR = 0; ///< Match register
PWM_CH0->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH0->UDMR = 0; ///< Up Dowm mode register
PWM_CH0->TCMR = 0; ///< Timer Counter mode register
PWM_CH0->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH0->CMR = 0; ///< Capture mode register
PWM_CH0->PDMR = 0; ///< Periodic Mode register
PWM_CH0->DZER = 0; ///< Dead Zone Enable register
PWM_CH0->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH1 )
{
PWM->IER &= PWM_IER_IE1_Disable; ///< Reset Interrupt enable register
PWM->SSR &= PWM_SSR_SS1_Stop; ///< Reset Start Stop register
PWM->PSR &= PWM_PSR_PS1_Restart; ///< Reset Pause register
PWM_CH1->IER = 0; ///< Interrupt enable register
PWM_CH1->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH1->PR = 0; ///< Prescale register
PWM_CH1->MR = 0; ///< Match register
PWM_CH1->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH1->UDMR = 0; ///< Up Dowm mode register
PWM_CH1->TCMR = 0; ///< Timer Counter mode register
PWM_CH1->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH1->CMR = 0; ///< Capture mode register
PWM_CH1->PDMR = 0; ///< Periodic Mode register
PWM_CH1->DZER = 0; ///< Dead Zone Enable register
PWM_CH1->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH2)
{
PWM->IER &= PWM_IER_IE2_Disable; ///< Interrupt enable register
PWM->SSR &= PWM_SSR_SS2_Stop; ///< Start Stop register
PWM->PSR &= PWM_PSR_PS2_Restart; ///< Pause register
PWM_CH2->IER = 0; ///< Interrupt enable register
PWM_CH2->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH2->PR = 0; ///< Prescale register
PWM_CH2->MR = 0; ///< Match register
PWM_CH2->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH2->UDMR = 0; ///< Up Dowm mode register
PWM_CH2->TCMR = 0; ///< Timer Counter mode register
PWM_CH2->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH2->CMR = 0; ///< Capture mode register
PWM_CH2->PDMR = 0; ///< Periodic Mode register
PWM_CH2->DZER = 0; ///< Dead Zone Enable register
PWM_CH2->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH3 )
{
PWM->IER &= PWM_IER_IE3_Disable; ///< Interrupt enable register
PWM->SSR &= PWM_SSR_SS3_Stop; ///< Start Stop register
PWM->PSR &= PWM_PSR_PS3_Restart; ///< Pause register
PWM_CH3->IER = 0; ///< Interrupt enable register
PWM_CH3->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH3->MR = 0; ///< Match register
PWM_CH3->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH3->UDMR = 0; ///< Up Dowm mode register
PWM_CH3->TCMR = 0; ///< Timer Counter mode register
PWM_CH3->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH3->CMR = 0; ///< Capture mode register
PWM_CH3->PDMR = 0; ///< Periodic Mode register
PWM_CH3->DZER = 0; ///< Dead Zone Enable register
PWM_CH3->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH4 )
{
PWM->SSR &= PWM_IER_IE4_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS4_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS4_Restart; ///< Interrupt enable register
PWM_CH4->IER = 0; ///< Interrupt enable register
PWM_CH4->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH4->PR = 0; ///< Prescale register
PWM_CH4->MR = 0; ///< Match register
PWM_CH4->LR = 0xFFFF; ///< Limit register
PWM_CH4->UDMR = 0; ///< Up Dowm mode register
PWM_CH4->TCMR = 0; ///< Timer Counter mode register
PWM_CH4->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH4->CMR = 0; ///< Capture mode register
PWM_CH4->PDMR = 0; ///< Periodic Mode register
PWM_CH4->DZER = 0; ///< Dead Zone Enable register
PWM_CH4->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH5 )
{
PWM->SSR &= PWM_IER_IE5_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS5_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS5_Restart; ///< Interrupt enable register
PWM_CH5->IER = 0; ///< Interrupt enable register
PWM_CH5->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH5->PR = 0; ///< Prescale register
PWM_CH5->MR = 0; ///< Match register
PWM_CH5->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH5->UDMR = 0; ///< Up Dowm mode register
PWM_CH5->TCMR = 0; ///< Timer Counter mode register
PWM_CH5->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH5->CMR = 0; ///< Capture mode register
PWM_CH5->PDMR = 0; ///< Periodic Mode register
PWM_CH5->DZER = 0; ///< Dead Zone Enable register
PWM_CH5->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH6 )
{
PWM->SSR &= PWM_IER_IE6_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS6_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS6_Restart; ///< Interrupt enable register
PWM_CH6->IER = 0; ///< Interrupt enable register
PWM_CH6->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH6->PR = 0; ///< Prescale register
PWM_CH6->MR = 0; ///< Match register
PWM_CH6->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH6->UDMR = 0; ///< Up Dowm mode register
PWM_CH6->TCMR = 0; ///< Timer Counter mode register
PWM_CH6->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH6->CMR = 0; ///< Capture mode register
PWM_CH6->PDMR = 0; ///< Periodic Mode register
PWM_CH6->DZER = 0; ///< Dead Zone Enable register
PWM_CH6->DZCR = 0; ///< Dead Zone Counter register
}
else if( PWM_CHn == PWM_CH7 )
{
PWM->SSR &= PWM_IER_IE7_Disable; ///< Start Stop register
PWM->PSR &= PWM_SSR_SS7_Stop; ///< Pause register
PWM->IER &= PWM_PSR_PS7_Restart; ///< Interrupt enable register
PWM_CH7->IER = 0; ///< Interrupt enable register
PWM_CH7->ICR = PWM_CHn_ICR_MatchInterruptClear |
PWM_CHn_ICR_OverflowInterruptClear |
PWM_CHn_ICR_CaptureInterruptClear; ///< Interrupt clear register
PWM_CH7->PR = 0; ///< Prescale register
PWM_CH7->MR = 0; ///< Match register
PWM_CH7->LR = 0xFFFFFFFF; ///< Limit register
PWM_CH7->UDMR = 0; ///< Up Dowm mode register
PWM_CH7->TCMR = 0; ///< Timer Counter mode register
PWM_CH7->PEEER = 0; ///< PWM output Enable and External input Enable register
PWM_CH7->CMR = 0; ///< Capture mode register
PWM_CH7->PDMR = 0; ///< Periodic Mode register
PWM_CH7->DZER = 0; ///< Dead Zone Enable register
PWM_CH7->DZCR = 0; ///< Dead Zone Counter register
}
}
void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct) //complet
{
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Prescale register value */
PWM_CHn->PR = PWM_TimerModeInitStruct->PWM_CHn_PR;
/* Set Match register value */
PWM_CHn->MR = PWM_TimerModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_TimerModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_TimerModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_TimerModeInitStruct->PWM_CHn_PDMR;
}
void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_PR_FILTER(PWM_CaptureModeInitStruct->PWM_CHn_PR));
assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_MR));
assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_CaptureModeInitStruct->PWM_CHn_LR));
assert_param(IS_PWM_CHn_UDMR(PWM_CaptureModeInitStruct->PWM_CHn_UDMR));
assert_param(IS_PWM_CHn_PDMR(PWM_CaptureModeInitStruct->PWM_CHn_PDMR));
assert_param(IS_PWM_CHn_CMR(PWM_CaptureModeInitStruct->PWM_CHn_CMR));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Prescale register value */
PWM_CHn->PR = PWM_CaptureModeInitStruct->PWM_CHn_PR;
/* Set Match register value */
PWM_CHn->MR = PWM_CaptureModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_CaptureModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_CaptureModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_CaptureModeInitStruct->PWM_CHn_PDMR;
/* Select Capture mode */
PWM_CHn->CMR = PWM_CaptureModeInitStruct->PWM_CHn_CMR;
/* External input enable */
PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
}
void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Match register value */
PWM_CHn->MR = PWM_CounterModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_CounterModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_CounterModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_CounterModeInitStruct->PWM_CHn_PDMR;
/* Select Counter mode */
PWM_CHn->TCMR = PWM_CounterModeInitStruct->PWM_CHn_TCMR;
/* Enable external input */
PWM_CHn->PEEER = PWM_CHn_PEEER_ExtEnable;
}
void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_PR_FILTER(PWM_DeadzoneModeInitStruct->PWM_CHn_PR));
assert_param(IS_PWM_MR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_MR));
assert_param(IS_PWM_LR_FILTER(PWM_CHn, PWM_DeadzoneModeInitStruct->PWM_CHn_LR));
assert_param(IS_PWM_CHn_UDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR));
assert_param(IS_PWM_CHn_PDMR(PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR));
assert_param(IS_PWM_Deadznoe(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/* Select Timer/Counter mode as Timer mode */
PWM_CHn->TCMR = PWM_CHn_TCMR_TimerMode;
/* Set Prescale register value */
PWM_CHn->PR = PWM_DeadzoneModeInitStruct->PWM_CHn_PR;
/* Set Match register value */
PWM_CHn->MR = PWM_DeadzoneModeInitStruct->PWM_CHn_MR;
/* Set Limit register value */
PWM_CHn->LR = PWM_DeadzoneModeInitStruct->PWM_CHn_LR;
/* Select Up-down mode */
PWM_CHn->UDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_UDMR;
/* Select Periodic mode */
PWM_CHn->PDMR = PWM_DeadzoneModeInitStruct->PWM_CHn_PDMR;
/* Enable Dead Zone generation */
PWM_CHn->DZER = PWM_CHn_DZER_Enable;
/* Set Dead Zone Counter */
PWM_CHn->DZCR = PWM_DeadzoneModeInitStruct->PWM_CHn_DZCR;
}
void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable ) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_Output(outputEnDisable));
if( PWM_CHn->DZER )
assert_param(IS_PWM_Deadznoe(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
/*Config PWM output and External input */
PWM_CHn->PEEER = outputEnDisable;
}
void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn)
{
PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_PWMEnable);
}
void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn)
{
PWM_CtrlPWMOutput(PWM_CHn, PWM_CHn_PEEER_Disable);
}
void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
if(state == ENABLE)
{
if(PWM_CHn == PWM_CH0) {
PWM->IER |= PWM_IER_IE0_Enable;
}
else if(PWM_CHn == PWM_CH1) {
PWM->IER |= PWM_IER_IE1_Enable;
}
else if(PWM_CHn == PWM_CH2) {
PWM->IER |= PWM_IER_IE2_Enable;
}
else if(PWM_CHn == PWM_CH3) {
PWM->IER |= PWM_IER_IE3_Enable;
}
else if(PWM_CHn == PWM_CH4) {
PWM->IER |= PWM_IER_IE4_Enable;
}
else if(PWM_CHn == PWM_CH5) {
PWM->IER |= PWM_IER_IE5_Enable;
}
else if(PWM_CHn == PWM_CH6) {
PWM->IER |= PWM_IER_IE6_Enable;
}
else if(PWM_CHn == PWM_CH7) {
PWM->IER |= PWM_IER_IE7_Enable;
}
}
else
{
if(PWM_CHn == PWM_CH0) {
PWM->IER &= PWM_IER_IE0_Disable;
}
else if(PWM_CHn == PWM_CH1) {
PWM->IER &= PWM_IER_IE1_Disable;
}
else if(PWM_CHn == PWM_CH2) {
PWM->IER &= PWM_IER_IE2_Disable;
}
else if(PWM_CHn == PWM_CH3) {
PWM->IER &= PWM_IER_IE3_Disable;
}
else if(PWM_CHn == PWM_CH4) {
PWM->IER &= PWM_IER_IE4_Disable;
}
else if(PWM_CHn == PWM_CH5) {
PWM->IER &= PWM_IER_IE5_Disable;
}
else if(PWM_CHn == PWM_CH6) {
PWM->IER &= PWM_IER_IE6_Disable;
}
else if(PWM_CHn == PWM_CH7) {
PWM->IER &= PWM_IER_IE7_Disable;
}
}
}
FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn)
{
FlagStatus ret_val = RESET;
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
if(PWM_CHn == PWM_CH0) {
ret_val = (FlagStatus)((PWM->IER & 0x01) >> 0);
}
else if(PWM_CHn == PWM_CH1) {
ret_val = (FlagStatus)((PWM->IER & 0x02) >> 1);
}
else if(PWM_CHn == PWM_CH2) {
ret_val = (FlagStatus)((PWM->IER & 0x04) >> 2);
}
else if(PWM_CHn == PWM_CH3) {
ret_val = (FlagStatus)((PWM->IER & 0x08) >> 3);
}
else if(PWM_CHn == PWM_CH4) {
ret_val = (FlagStatus)((PWM->IER & 0x10) >> 4);
}
else if(PWM_CHn == PWM_CH5) {
ret_val = (FlagStatus)((PWM->IER & 0x20) >> 5);
}
else if(PWM_CHn == PWM_CH6) {
ret_val = (FlagStatus)((PWM->IER & 0x40) >> 6);
}
else if(PWM_CHn == PWM_CH7) {
ret_val = (FlagStatus)((PWM->IER & 0x80) >> 7);
}
return ret_val;
}
void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_IER(PWM_CHn_IER));
/* Stop PWM_CHn */
PWM_CHn_Stop(PWM_CHn);
if(state == ENABLE)
PWM_CHn->IER |= PWM_CHn_IER;
else
PWM_CHn->IER &= ~PWM_CHn_IER;
}
uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->IER;
}
uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->IR;
}
void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR)
{
/* Check the parameters */
PWM_CHn->ICR = PWM_CHn_ICR;
}
void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Set Start Stop register */
if(PWM_CHn == PWM_CH0) {
PWM->SSR |= PWM_SSR_SS0_Start;
}
else if(PWM_CHn == PWM_CH1) {
PWM->SSR |= PWM_SSR_SS1_Start;
}
else if(PWM_CHn == PWM_CH2) {
PWM->SSR |= PWM_SSR_SS2_Start;
}
else if(PWM_CHn == PWM_CH3) {
PWM->SSR |= PWM_SSR_SS3_Start;
}
else if(PWM_CHn == PWM_CH4) {
PWM->SSR |= PWM_SSR_SS4_Start;
}
else if(PWM_CHn == PWM_CH5) {
PWM->SSR |= PWM_SSR_SS5_Start;
}
else if(PWM_CHn == PWM_CH6) {
PWM->SSR |= PWM_SSR_SS6_Start;
}
else if(PWM_CHn == PWM_CH7) {
PWM->SSR |= PWM_SSR_SS7_Start;
}
}
void PWM_Multi_Start(uint32_t ssr_bit_flag) //complete
{
/* Set Start Stop register */
PWM->SSR |= ssr_bit_flag;
}
void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Reset Start Stop register */
if(PWM_CHn == PWM_CH0) {
PWM->SSR &= PWM_SSR_SS0_Stop;
}
else if(PWM_CHn == PWM_CH1) {
PWM->SSR &= PWM_SSR_SS1_Stop;
}
else if(PWM_CHn == PWM_CH2) {
PWM->SSR &= PWM_SSR_SS2_Stop;
}
else if(PWM_CHn == PWM_CH3) {
PWM->SSR &= PWM_SSR_SS3_Stop;
}
else if(PWM_CHn == PWM_CH4) {
PWM->SSR &= PWM_SSR_SS4_Stop;
}
else if(PWM_CHn == PWM_CH5) {
PWM->SSR &= PWM_SSR_SS5_Stop;
}
else if(PWM_CHn == PWM_CH6) {
PWM->SSR &= PWM_SSR_SS6_Stop;
}
else if(PWM_CHn == PWM_CH7) {
PWM->SSR &= PWM_SSR_SS7_Stop;
}
}
void PWM_Multi_Stop(uint32_t ssr_bit_flag) //complete
{
/* Reset Start Stop register */
PWM->SSR &= ~ssr_bit_flag;
}
void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn)
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Set Pause register */
if(PWM_CHn == PWM_CH0) {
PWM->PSR |= PWM_PSR_PS0_Pause;
}
else if(PWM_CHn == PWM_CH1) {
PWM->PSR |= PWM_PSR_PS1_Pause;
}
else if(PWM_CHn == PWM_CH2) {
PWM->PSR |= PWM_PSR_PS2_Pause;
}
else if(PWM_CHn == PWM_CH3) {
PWM->PSR |= PWM_PSR_PS3_Pause;
}
else if(PWM_CHn == PWM_CH4) {
PWM->PSR |= PWM_PSR_PS4_Pause;
}
else if(PWM_CHn == PWM_CH5) {
PWM->PSR |= PWM_PSR_PS5_Pause;
}
else if(PWM_CHn == PWM_CH6) {
PWM->PSR |= PWM_PSR_PS6_Pause;
}
else if(PWM_CHn == PWM_CH7) {
PWM->PSR |= PWM_PSR_PS7_Pause;
}
}
void PWM_Multi_Pause(uint32_t psr_bit_flag)
{
PWM->PSR |= psr_bit_flag;
}
void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn)
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
/* Reset Pause register */
if(PWM_CHn == PWM_CH0) {
PWM->PSR &= PWM_PSR_PS0_Restart;
}
else if(PWM_CHn == PWM_CH1) {
PWM->PSR &= PWM_PSR_PS1_Restart;
}
else if(PWM_CHn == PWM_CH2) {
PWM->PSR &= PWM_PSR_PS2_Restart;
}
else if(PWM_CHn == PWM_CH3) {
PWM->PSR &= PWM_PSR_PS3_Restart;
}
else if(PWM_CHn == PWM_CH4) {
PWM->PSR &= PWM_PSR_PS4_Restart;
}
else if(PWM_CHn == PWM_CH5) {
PWM->PSR &= PWM_PSR_PS5_Restart;
}
else if(PWM_CHn == PWM_CH6) {
PWM->PSR &= PWM_PSR_PS6_Restart;
}
else if(PWM_CHn == PWM_CH7) {
PWM->PSR &= PWM_PSR_PS7_Restart;
}
}
void PWM_Multi_Restart(uint32_t psr_bit_flag)
{
PWM->PSR &= ~psr_bit_flag;
}
uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->TCR;
}
uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PCR;
}
uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PR;
}
void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_PR_FILTER(PR));
PWM_CHn->PR = PR;
}
uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->MR;
}
void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
PWM_CHn->MR = MR;
}
uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->LR;
}
void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
PWM_CHn->LR = LR;
}
uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->UDMR;
}
void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_UDMR(UDMR));
PWM_CHn->UDMR = UDMR;
}
uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->TCMR;
}
void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_TCMR(TCMR));
PWM_CHn->TCMR = TCMR;
}
uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PEEER;
}
void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_PEEER(PEEER));
PWM_CHn->PEEER = PEEER;
}
uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->CMR;
}
void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_CMR(CMR));
PWM_CHn->CMR = CMR;
}
uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn)
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->CR;
}
uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->PDMR;
}
void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_PDMR(PDMR));
PWM_CHn->PDMR = PDMR;
}
uint32_t PWM_CHn_GetDZER(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->DZER;
}
void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_DZER(DZER));
PWM_CHn->DZER = DZER;
}
uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
return PWM_CHn->DZCR;
}
void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR) //complete
{
/* Check the parameters */
assert_param(IS_PWM_ALL_CH(PWM_CHn));
assert_param(IS_PWM_CHn_DZCR_FILTER(DZCR));
PWM_CHn->DZCR = DZCR;
}
void PWM_CH0_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH0_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH0_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH0, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH1_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH1_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH1_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH1, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH2_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH2_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH2_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH2, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH3_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH3_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH3_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH3, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH4_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH4_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH4_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH4, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH5_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH5_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH5_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH5, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH6_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH6_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH6_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH6, PWM_CHn_ICR_CaptureInterruptClear);
}
void PWM_CH7_ClearMatchInt(void)
{
PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_MatchInterruptClear);
}
void PWM_CH7_ClearOverflowInt(void)
{
PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_OverflowInterruptClear);
}
void PWM_CH7_ClearCaptureInt(void)
{
PWM_CHn_ClearInt(PWM_CH7, PWM_CHn_ICR_CaptureInterruptClear);
}

289
libraries/mbed/targets/cmsis/TARGET_WIZNET/TARGET_W7500x/W7500x_pwm.h Normal file
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@ -0,0 +1,289 @@
/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_PWM_H
#define __W7500X_PWM_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
/**********************************************************************************************/
/**********************************************************************************************/
// This structure and define must be in W7500x.h
/**********************************************************************************************/
/**********************************************************************************************/
typedef struct
{
uint32_t PWM_CHn_PEEER;
}PWM_CtrlPWMOutputTypeDef;
typedef struct
{
uint32_t PWM_CHn_PR;
uint32_t PWM_CHn_MR;
uint32_t PWM_CHn_LR;
uint32_t PWM_CHn_UDMR;
uint32_t PWM_CHn_PDMR;
uint32_t PWM_CHn_DZCR;
}PWM_DeadzoneModeInitTypDef;
#define IS_PWM_ALL_CH(CHn) ((CHn == PWM_CH0) || \
(CHn == PWM_CH1) || \
(CHn == PWM_CH2) || \
(CHn == PWM_CH3) || \
(CHn == PWM_CH4) || \
(CHn == PWM_CH5) || \
(CHn == PWM_CH6) || \
(CHn == PWM_CH7))
#define PWM_IER_IE0_Enable (0x1ul << 0)
#define PWM_IER_IE1_Enable (0x1ul << 1)
#define PWM_IER_IE2_Enable (0x1ul << 2)
#define PWM_IER_IE3_Enable (0x1ul << 3)
#define PWM_IER_IE4_Enable (0x1ul << 4)
#define PWM_IER_IE5_Enable (0x1ul << 5)
#define PWM_IER_IE6_Enable (0x1ul << 6)
#define PWM_IER_IE7_Enable (0x1ul << 7)
#define PWM_IER_IE0_Disable ~PWM_IER_IE0_Enable
#define PWM_IER_IE1_Disable ~PWM_IER_IE1_Enable
#define PWM_IER_IE2_Disable ~PWM_IER_IE2_Enable
#define PWM_IER_IE3_Disable ~PWM_IER_IE3_Enable
#define PWM_IER_IE4_Disable ~PWM_IER_IE4_Enable
#define PWM_IER_IE5_Disable ~PWM_IER_IE5_Enable
#define PWM_IER_IE6_Disable ~PWM_IER_IE6_Enable
#define PWM_IER_IE7_Disable ~PWM_IER_IE7_Enable
#define PWM_SSR_SS0_Start (0x1ul << 0)
#define PWM_SSR_SS1_Start (0x1ul << 1)
#define PWM_SSR_SS2_Start (0x1ul << 2)
#define PWM_SSR_SS3_Start (0x1ul << 3)
#define PWM_SSR_SS4_Start (0x1ul << 4)
#define PWM_SSR_SS5_Start (0x1ul << 5)
#define PWM_SSR_SS6_Start (0x1ul << 6)
#define PWM_SSR_SS7_Start (0x1ul << 7)
#define PWM_SSR_SS0_Stop ~PWM_SSR_SS0_Start
#define PWM_SSR_SS1_Stop ~PWM_SSR_SS1_Start
#define PWM_SSR_SS2_Stop ~PWM_SSR_SS2_Start
#define PWM_SSR_SS3_Stop ~PWM_SSR_SS3_Start
#define PWM_SSR_SS4_Stop ~PWM_SSR_SS4_Start
#define PWM_SSR_SS5_Stop ~PWM_SSR_SS5_Start
#define PWM_SSR_SS6_Stop ~PWM_SSR_SS6_Start
#define PWM_SSR_SS7_Stop ~PWM_SSR_SS7_Start
#define IS_SSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
#define PWM_PSR_PS0_Pause (0x1ul << 0)
#define PWM_PSR_PS1_Pause (0x1ul << 1)
#define PWM_PSR_PS2_Pause (0x1ul << 2)
#define PWM_PSR_PS3_Pause (0x1ul << 3)
#define PWM_PSR_PS4_Pause (0x1ul << 4)
#define PWM_PSR_PS5_Pause (0x1ul << 5)
#define PWM_PSR_PS6_Pause (0x1ul << 6)
#define PWM_PSR_PS7_Pause (0x1ul << 7)
#define PWM_PSR_PS0_Restart ~PWM_PSR_PS0_Pause
#define PWM_PSR_PS1_Restart ~PWM_PSR_PS1_Pause
#define PWM_PSR_PS2_Restart ~PWM_PSR_PS2_Pause
#define PWM_PSR_PS3_Restart ~PWM_PSR_PS3_Pause
#define PWM_PSR_PS4_Restart ~PWM_PSR_PS4_Pause
#define PWM_PSR_PS5_Restart ~PWM_PSR_PS5_Pause
#define PWM_PSR_PS6_Restart ~PWM_PSR_PS6_Pause
#define PWM_PSR_PS7_Restart ~PWM_PSR_PS7_Pause
#define IS_PWM_PSR_BIT_FLAG(FLAG) (FLAG <= 0xFF)
#define PWM_CHn_IER_MIE (0x1ul << 0) ///< Match Interrupt Enable
#define PWM_CHn_IER_OIE (0x1ul << 1) ///< Overflow Interrupt Enable
#define PWM_CHn_IER_CIE (0x1ul << 2) ///< Capture Interrupt Enable
#define IS_PWM_CHn_IER(FLAG) (FLAG <= 0x7)
#define PWM_CHn_IER_MI_Msk (0x1ul << 0) ///< Match Interrupt Enable Mask
#define PWM_CHn_IER_OI_Msk (0x1ul << 1) ///< Overflow Interrupt Enable Mask
#define PWM_CHn_IER_CI_Msk (0x1ul << 2) ///< Capture Interrupt Enable Mask
#define PWM_CHn_ICR_MatchInterruptClear (0x1ul << 0)
#define PWM_CHn_ICR_OverflowInterruptClear (0x1ul << 1)
#define PWM_CHn_ICR_CaptureInterruptClear (0x1ul << 2)
#define IS_PWM_CHn_IntClearFlag(FLAG) FLAG <= 0x7
/*
#define IS_PWM_STOP(CHn) (((CHn == PWM_CH0) && (PWM->SSR & PWM_SSR_SS0)) || \
((CHn == PWM_CH1) && (PWM->SSR & PWM_SSR_SS1)) || \
((CHn == PWM_CH2) && (PWM->SSR & PWM_SSR_SS2)) || \
((CHn == PWM_CH3) && (PWM->SSR & PWM_SSR_SS3)) || \
((CHn == PWM_CH4) && (PWM->SSR & PWM_SSR_SS4)) || \
((CHn == PWM_CH5) && (PWM->SSR & PWM_SSR_SS5)) || \
((CHn == PWM_CH6) && (PWM->SSR & PWM_SSR_SS6)) || \
((CHn == PWM_CH7) && (PWM->SSR & PWM_SSR_SS7)))
*/
#define IS_PWM_PR_FILTER(MAXVAL) (MAXVAL <= 0x1F)
#define PWM_CHn_UDMR_UpCount (0x0ul)
#define PWM_CHn_UDMR_DownCount (0x1ul)
#define IS_PWM_CHn_UDMR(MODE) ((MODE == PWM_CHn_UDMR_UpCount) || \
(MODE == PWM_CHn_UDMR_DownCount))
#define PWM_CHn_TCMR_TimerMode (0x0ul)
#define PWM_CHn_TCMR_RisingCounterMode (0x1ul)
#define PWM_CHn_TCMR_FallingCounterMode (0x2ul)
#define PWM_CHn_TCMR_BothCounterMode (0x3ul)
#define IS_PWM_CHn_TCMR(MODE) ((MODE == PWM_CHn_TCMR_RisingCounterMode) || \
(MODE == PWM_CHn_TCMR_FallingCounterMode) || \
(MODE == PWM_CHn_TCMR_BothCounterMode))
#define PWM_CHn_PEEER_Disable (0x0ul)
#define PWM_CHn_PEEER_ExtEnable (0x1ul)
#define PWM_CHn_PEEER_PWMEnable (0x2ul)
#define IS_PWM_CHn_PEEER(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
(ENABLE == PWM_CHn_PEEER_ExtEnable) || \
(ENABLE == PWM_CHn_PEEER_PWMEnable))
#define IS_PWM_Output(ENABLE) ((ENABLE == PWM_CHn_PEEER_Disable) || \
(ENABLE == PWM_CHn_PEEER_PWMEnable))
#define PWM_CHn_CMR_RisingEdge 0x0ul
#define PWM_CHn_CMR_FallingEdge 0x1ul
#define IS_PWM_CHn_CMR(MODE) ((MODE == PWM_CHn_CMR_RisingEdge) || \
(MODE == PWM_CHn_CMR_FallingEdge))
#define PWM_CHn_PDMR_Oneshot (0x0ul)
#define PWM_CHn_PDMR_Periodic (0x1ul)
#define IS_PWM_CHn_PDMR(MODE) ((MODE == PWM_CHn_PDMR_Periodic) || \
(MODE == PWM_CHn_PDMR_Oneshot))
#define PWM_CHn_DZER_Enable (0x1ul)
#define PWM_CHn_DZER_Disable (0x0ul)
#define PWM_CHn_DZER(ENABLE) ((ENABLE == PWM_CHn_DZER_Enable) || \
(ENABLE == PWM_CHn_DZER_Disable))
#define IS_PWM_Deadznoe(CHn) (((CHn == PWM_CH0) && (PWM_CH1->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH1) && (PWM_CH0->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH2) && (PWM_CH3->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH3) && (PWM_CH2->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH4) && (PWM_CH5->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH5) && (PWM_CH4->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH6) && (PWM_CH7->DZER == PWM_CHn_DZER_Disable)) || \
((CHn == PWM_CH7) && (PWM_CH6->DZER == PWM_CHn_DZER_Disable)))
#define IS_PWM_CHn_DZCR_FILTER(MAXVAL) (MAXVAL <= 0x3FF)
void PWM_DeInit(PWM_CHn_TypeDef* PWM_CHn);
void PWM_TimerModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_TimerModeInitTypeDef* PWM_TimerModeInitStruct);
void PWM_CaptureModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CaptureModeInitTypeDef* PWM_CaptureModeInitStruct);
void PWM_CounterModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_CounterModeInitTypeDef* PWM_CounterModeInitStruct);
void PWM_DeadzoneModeInit(PWM_CHn_TypeDef* PWM_CHn, PWM_DeadzoneModeInitTypDef* PWM_DeadzoneModeInitStruct);
void PWM_CtrlPWMOutput(PWM_CHn_TypeDef* PWM_CHn, uint32_t outputEnDisable );
void PWM_CtrlPWMOutputEnable(PWM_CHn_TypeDef* PWM_CHn) ;
void PWM_CtrlPWMOutputDisable(PWM_CHn_TypeDef* PWM_CHn) ;
void PWM_IntConfig(PWM_CHn_TypeDef* PWM_CHn, FunctionalState state);
FlagStatus PWM_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_IntConfig(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_IER, FunctionalState state);
void PWM_CHn_Start(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Start(uint32_t ssr_bit_flag);
void PWM_CHn_Stop(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Stop(uint32_t ssr_bit_flag);
void PWM_CHn_Pause(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Pause(uint32_t psr_bit_flag);
void PWM_CHn_Restart(PWM_CHn_TypeDef* PWM_CHn);
void PWM_Multi_Restart(uint32_t psr_bit_flag);
uint32_t PWM_CHn_GetIntEnableStatus(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetIntFlagStatus(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_ClearInt(PWM_CHn_TypeDef* PWM_CHn, uint32_t PWM_CHn_ICR);
uint32_t PWM_CHn_GetTCR(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetPCR(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetPR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetPR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PR);
uint32_t PWM_CHn_GetMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t MR);
uint32_t PWM_CHn_GetLR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetLR(PWM_CHn_TypeDef* PWM_CHn, uint32_t LR);
uint32_t PWM_CHn_GetUDMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetUDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t UDMR);
uint32_t PWM_CHn_GetTCMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetTCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t TCMR);
uint32_t PWM_CHn_GetPEEER(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetPEEER(PWM_CHn_TypeDef* PWM_CHn, uint32_t PEEER);
uint32_t PWM_CHn_GetCMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetCMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t CMR);
uint32_t PWM_CHn_GetCR(PWM_CHn_TypeDef* PWM_CHn);
uint32_t PWM_CHn_GetPDMR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetPDMR(PWM_CHn_TypeDef* PWM_CHn, uint32_t PDMR);
void PWM_CHn_SetDZER(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZER);
uint32_t PWM_CHn_GetDZCR(PWM_CHn_TypeDef* PWM_CHn);
void PWM_CHn_SetDZCR(PWM_CHn_TypeDef* PWM_CHn, uint32_t DZCR);
void PWM_CH0_ClearMatchInt(void);
void PWM_CH0_ClearOverflowInt(void);
void PWM_CH0_ClearCaptureInt(void);
void PWM_CH1_ClearMatchInt(void);
void PWM_CH1_ClearOverflowInt(void);
void PWM_CH1_ClearCaptureInt(void);
void PWM_CH2_ClearMatchInt(void);
void PWM_CH2_ClearOverflowInt(void);
void PWM_CH2_ClearCaptureInt(void);
void PWM_CH3_ClearMatchInt(void);
void PWM_CH3_ClearOverflowInt(void);
void PWM_CH3_ClearCaptureInt(void);
void PWM_CH4_ClearMatchInt(void);
void PWM_CH4_ClearOverflowInt(void);
void PWM_CH4_ClearCaptureInt(void);
void PWM_CH5_ClearMatchInt(void);
void PWM_CH5_ClearOverflowInt(void);
void PWM_CH5_ClearCaptureInt(void);
void PWM_CH6_ClearMatchInt(void);
void PWM_CH6_ClearOverflowInt(void);
void PWM_CH6_ClearCaptureInt(void);
void PWM_CH7_ClearMatchInt(void);
void PWM_CH7_ClearOverflowInt(void);
void PWM_CH7_ClearCaptureInt(void);
void PWM0_Handler(void);
void PWM1_Handler(void);
void PWM2_Handler(void);
void PWM3_Handler(void);
void PWM4_Handler(void);
void PWM5_Handler(void);
void PWM6_Handler(void);
void PWM7_Handler(void);
//Temporary macro=======
#define PWM_CH(N) ((PWM_CHn_TypeDef *) (W7500x_PWM_BASE + (N * 0x100UL)))
//======================
#ifdef __cplusplus
}
#endif
#endif //__W7500X_PWM_H

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/**
******************************************************************************
* @file W7500x_uart.c
* @author
* @version
* @date
* @brief
******************************************************************************
* @attention
*
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
void UART_StructInit(UART_InitTypeDef* UART_InitStruct)
{
/* UART_InitStruct members default value */
UART_InitStruct->UART_BaudRate = 115200;
UART_InitStruct->UART_WordLength = UART_WordLength_8b ;
UART_InitStruct->UART_StopBits = UART_StopBits_1;
UART_InitStruct->UART_Parity = UART_Parity_No ;
UART_InitStruct->UART_Mode = UART_Mode_Rx | UART_Mode_Tx;
UART_InitStruct->UART_HardwareFlowControl = UART_HardwareFlowControl_None ;
}
void UART_DeInit(UART_TypeDef *UARTx)
{
}
uint32_t UART_Init(UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct)
{
float baud_divisor;
uint32_t tmpreg=0x00, uartclock=0x00;
uint32_t integer_baud = 0x00, fractional_baud = 0x00;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_WORD_LENGTH(UART_InitStruct->UART_WordLength));
assert_param(IS_UART_PARITY(UART_InitStruct->UART_Parity));
assert_param(IS_UART_STOPBITS(UART_InitStruct->UART_StopBits));
assert_param(IS_UART_HARDWARE_FLOW_CONTROL(UART_InitStruct->UART_HardwareFlowControl));
assert_param(IS_UART_MODE(UART_InitStruct->UART_Mode));
UARTx->CR &= ~(UART_CR_UARTEN);
// Set baudrate
CRG->UARTCLK_SSR = CRG_UARTCLK_SSR_RCLK; // Set UART Clock using internal Oscilator ( 8MHz )
uartclock = (8000000UL) / (1 << CRG->UARTCLK_PVSR);
baud_divisor = ((float)uartclock / (16 * UART_InitStruct->UART_BaudRate));
integer_baud = (uint32_t)baud_divisor;
fractional_baud = (uint32_t)((baud_divisor - integer_baud) * 64 + 0.5);
UARTx->IBRD = integer_baud;
UARTx->FBRD = fractional_baud;
tmpreg = UARTx->LCR_H;
tmpreg &= ~(0x00EE);
tmpreg |= (UART_InitStruct->UART_WordLength | UART_InitStruct->UART_StopBits | UART_InitStruct->UART_Parity);
UARTx->LCR_H |= tmpreg;
tmpreg = UARTx->CR;
tmpreg &= ~(UART_CR_CTSEn | UART_CR_RTSEn | UART_CR_RXE | UART_CR_TXE | UART_CR_UARTEN);
tmpreg |= (UART_InitStruct->UART_Mode | UART_InitStruct->UART_HardwareFlowControl);
UARTx->CR |= tmpreg;
UARTx->CR |= UART_CR_UARTEN;
return 0;
}
void UART_SendData(UART_TypeDef* UARTx, uint16_t Data)
{
assert_param(IS_UART_01_PERIPH(UARTx));
UARTx->DR = Data;
}
uint16_t UART_ReceiveData(UART_TypeDef* UARTx)
{
assert_param(IS_UART_01_PERIPH(UARTx));
return (uint16_t)(UARTx->DR);
}
void UART_SendBreak(UART_TypeDef* UARTx)
{
assert_param(IS_UART_01_PERIPH(UARTx));
UARTx->LCR_H |= UART_LCR_H_BRK;
}
FlagStatus UART_GetRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
{
FlagStatus bitstatus = RESET;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
if( (UARTx->STATUS.RSR & UART_RECV_STATUS) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void UART_ClearRecvStatus(UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS)
{
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_RECV_STATUS(UART_RECV_STATUS));
UARTx->STATUS.ECR = (uint16_t)UART_RECV_STATUS;
}
FlagStatus UART_GetFlagStatus(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
FlagStatus bitstatus = RESET;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_FLAG(UART_FLAG));
if ((UARTx->FR & UART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
/*
void UART_ClearFlag(UART_TypeDef* UARTx, uint16_t UART_FLAG)
{
}
*/
void UART_ITConfig(UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState)
{
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
if ( NewState != DISABLE )
{
UARTx->IMSC |= UART_IT;
}
else
{
UARTx->ICR |= UART_IT;
}
}
ITStatus UART_GetITStatus(UART_TypeDef* UARTx, uint16_t UART_IT)
{
ITStatus bitstatus = RESET;
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
if ((UARTx->MIS & UART_IT) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void UART_ClearITPendingBit(UART_TypeDef* UARTx, uint16_t UART_IT)
{
assert_param(IS_UART_01_PERIPH(UARTx));
assert_param(IS_UART_IT_FLAG(UART_IT));
UARTx->ICR |= UART_IT;
}
void S_UART_DeInit()
{
}
uint32_t S_UART_Init(uint32_t baud)
{
uint32_t tmpreg=0x00;
uint32_t uartclock = 0x00, integer_baud = 0x00;
assert_param(IS_UART_MODE(S_UART_InitStruct->UART_Mode));
if(CRG->FCLK_SSR == CRG_FCLK_SSR_RCLK)
{
uartclock = INTERN_XTAL;
}
else if(CRG->FCLK_SSR == CRG_FCLK_SSR_OCLK)
{
uartclock = EXTERN_XTAL;
}
else
{
uartclock = GetSystemClock();
}
integer_baud = (uint32_t)(uartclock / baud);
UART2->BAUDDIV = integer_baud;
tmpreg = UART2->CTRL;
tmpreg &= ~(S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
tmpreg |= (S_UART_CTRL_RX_EN | S_UART_CTRL_TX_EN);
UART2->CTRL = tmpreg;
return 0;
}
void S_UART_SendData(uint16_t Data)
{
while(UART2->STATE & S_UART_STATE_TX_BUF_FULL);
UART2->DATA = Data;
}
uint16_t S_UART_ReceiveData()
{
return (uint16_t)(UART2->DATA);
}
FlagStatus S_UART_GetFlagStatus(uint16_t S_UART_FLAG)
{
FlagStatus bitstatus = RESET;
assert_param(IS_S_UART_FLAG(S_UART_FLAG));
if ((UART2->STATE & S_UART_FLAG) != (uint16_t)RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void S_UART_ITConfig(uint16_t S_UART_IT, FunctionalState NewState)
{
assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
if ( NewState != DISABLE )
{
UART2->CTRL |= S_UART_IT;
}
else
{
UART2->CTRL &= ~(S_UART_IT);
}
}
ITStatus S_UART_GetITStatus(uint16_t S_UART_IT)
{
ITStatus bitstatus = RESET;
assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
if ((UART2->INT.STATUS & (S_UART_IT >> 2)) != (uint16_t) RESET)
{
bitstatus = SET;
}
else
{
bitstatus = RESET;
}
return bitstatus;
}
void S_UART_ClearITPendingBit(uint16_t S_UART_IT)
{
assert_param(IS_S_UART_IT_FLAG(S_UART_IT));
UART2->INT.CLEAR |= (S_UART_IT >> 2);
}
/**************************************************/
// It will be moved to application board's driver */
/**************************************************/
uint8_t UartPutc(UART_TypeDef* UARTx, uint8_t ch)
{
UART_SendData(UARTx,ch);
while(UARTx->FR & UART_FR_BUSY);
return (ch);
}
void UartPuts(UART_TypeDef* UARTx, uint8_t *str)
{
uint8_t ch;
do{
ch = *str;
if(ch != (uint8_t)0x0)
{
UartPutc(UARTx, ch);
}
*str++;
}while(ch != 0);
}
uint8_t UartGetc(UART_TypeDef* UARTx)
{
while(UARTx->FR & UART_FR_RXFE);
return (UARTx->DR & 0xFF);
}
uint8_t S_UartPutc(uint8_t ch)
{
S_UART_SendData(ch);
return (ch);
}
void S_UartPuts(uint8_t *str)
{
uint8_t ch;
do{
ch = *str;
if(ch != (uint8_t)0x0)
{
S_UART_SendData(ch);
}
*str++;
}while(ch != 0);
}
uint8_t S_UartGetc()
{
while( (UART2->STATE & S_UART_STATE_RX_BUF_FULL) == 0 );
return (uint8_t)S_UART_ReceiveData();
}

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/**
******************************************************************************
* @file
* @author
* @version
* @date
* @brief This file contains all the functions prototypes for the UART
* firmware library.
******************************************************************************
*
******************************************************************************
*/
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __W7500X_UART_H
#define __W7500X_UART_H
#ifdef __cplusplus
extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
#include "W7500x.h"
/**
* @brief UART Init Structure definition
*/
typedef struct
{
uint32_t UART_BaudRate;
uint16_t UART_WordLength;
uint16_t UART_StopBits;
uint16_t UART_Parity;
uint16_t UART_Mode;
uint16_t UART_HardwareFlowControl;
} UART_InitTypeDef;
/**
* @}
*/
/** @defgroup UART_Exported_Constants
* @{
*/
#define IS_UART_01_PERIPH(PERIPH) (((PERIPH) == UART0) || ((PERIPH) == UART1))
#define IS_UART_2_PERIPH(PERIPH) ((PERIPH) == UART2)
/**
* @}
*/
/** @addtogroup UART_Word_Length
* @{
*/
#define UART_WordLength_8b ((uint16_t)UART_LCR_H_WLEN(3))
#define UART_WordLength_7b ((uint16_t)UART_LCR_H_WLEN(2))
#define UART_WordLength_6b ((uint16_t)UART_LCR_H_WLEN(1))
#define UART_WordLength_5b ((uint16_t)UART_LCR_H_WLEN(0))
#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WordLength_8b) || \
((LENGTH) == UART_WordLength_7b) || \
((LENGTH) == UART_WordLength_6b) || \
((LENGTH) == UART_WordLength_5b) )
/**
* @}
*/
/** @addtogroup UART_Parity
* @{
*/
#define UART_Parity_No ((uint16_t)0x0000)
#define UART_Parity_Even ((uint16_t)(UART_LCR_H_PEN | UART_LCR_H_EPS))
#define UART_Parity_Odd ((uint16_t)(UART_LCR_H_PEN))
#define IS_UART_PARITY(PARITY) (((PARITY) == UART_Parity_No) || \
((PARITY) == UART_Parity_Even) || \
((PARITY) == UART_Parity_Odd))
/**
* @}
*/
/** @addtogroup UART_Stop_Bits
* @{
*/
#define UART_StopBits_1 ((uint16_t)0x0000)
#define UART_StopBits_2 ((uint16_t)(UART_LCR_H_STP2))
#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_StopBits_1) || \
((STOPBITS) == UART_StopBits_2))
/**
* @}
*/
/** @addtogroup UART_Mode
* @{
*/
#define UART_Mode_Rx ((uint16_t)(UART_CR_RXE))
#define UART_Mode_Tx ((uint16_t)(UART_CR_TXE))
#define IS_UART_MODE(MODE) (((MODE) == UART_Mode_Rx) || \
((MODE) == UART_Mode_Tx))
/**
* @}
*/
/** @addtogroup UART_Hardware_Flow_Control
* @{
*/
#define UART_HardwareFlowControl_None ((uint16_t)0x0000)
#define UART_HardwareFlowControl_RTS ((uint16_t)UART_CR_RTSEn)
#define UART_HardwareFlowControl_CTS ((uint16_t)UART_CR_CTSEn)
#define UART_HardwareFlowControl_RTS_CTS ((uint16_t)(UART_CR_RTSEn | UART_CR_CTSEn))
#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL) \
(((CONTROL) == UART_HardwareFlowControl_None) || \
((CONTROL) == UART_HardwareFlowControl_RTS) || \
((CONTROL) == UART_HardwareFlowControl_CTS) || \
((CONTROL) == UART_HardwareFlowControl_RTS_CTS))
/**
* @}
*/
/** @addtogroup UART_Receive Status
* @{
*/
#define UART_RECV_STATUS_OE ((uint16_t)0x01UL << 3) /*!< Overrun error */
#define UART_RECV_STATUS_BE ((uint16_t)0x01UL << 2) /*!< Break error */
#define UART_RECV_STATUS_PE ((uint16_t)0x01UL << 1) /*!< Parity error */
#define UART_RECV_STATUS_FE ((uint16_t)0x01UL << 0) /*!< Framing error */
#define IS_UART_RECV_STATUS(FLAG) (((FLAG) == UART_RECV_STATUS_OE) || ((FLAG) == UART_RECV_STATUS_BE) || \
((FLAG) == UART_RECV_STATUS_PE) || ((FLAG) == UART_RECV_STATUS_FE))
/**
* @}
*/
/** @addtogroup UART_Flags
* @{
*/
#define UART_FLAG_RI ((uint16_t)0x01UL << 8) /*!< Ring indicator */
#define UART_FLAG_TXFE ((uint16_t)0x01UL << 7) /*!< Transmit FIFO empty */
#define UART_FLAG_RXFF ((uint16_t)0x01UL << 6) /*!< Receive FIFO full */
#define UART_FLAG_TXFF ((uint16_t)0x01UL << 5) /*!< Transmit FIFO full */
#define UART_FLAG_RXFE ((uint16_t)0x01UL << 4) /*!< Receive FIFO empty */
#define UART_FLAG_BUSY ((uint16_t)0x01UL << 3) /*!< UART busy */
#define UART_FLAG_DCD ((uint16_t)0x01UL << 2) /*!< Data carrier detect */
#define UART_FLAG_DSR ((uint16_t)0x01UL << 1) /*!< Data set ready */
#define UART_FLAG_CTS ((uint16_t)0x01UL << 0) /*!< Clear to send */
#define IS_UART_FLAG(FLAG) (((FLAG) == UART_FLAG_RI) || ((FLAG) == UART_FLAG_TXFE) || \
((FLAG) == UART_FLAG_RXFF) || ((FLAG) == UART_FLAG_TXFF) || \
((FLAG) == UART_FLAG_RXFE) || ((FLAG) == UART_FLAG_BUSY) || \
((FLAG) == UART_FLAG_DCD) || ((FLAG) == UART_FLAG_DSR) || \
((FLAG) == UART_FLAG_CTS))
/**
* @}
*/
/** @addtogroup UART_IT_Flags
* @{
*/
#define UART_IT_FLAG_OEI ((uint16_t)0x01UL << 10) /*!< Overrun error interrupt */
#define UART_IT_FLAG_BEI ((uint16_t)0x01UL << 9) /*!< Break error interrupt */
#define UART_IT_FLAG_PEI ((uint16_t)0x01UL << 8) /*!< Parity error interrupt */
#define UART_IT_FLAG_FEI ((uint16_t)0x01UL << 7) /*!< Framing error interrupt */
#define UART_IT_FLAG_RTI ((uint16_t)0x01UL << 6) /*!< Receive timeout interrupt */
#define UART_IT_FLAG_TXI ((uint16_t)0x01UL << 5) /*!< Transmit interrupt */
#define UART_IT_FLAG_RXI ((uint16_t)0x01UL << 4) /*!< Receive interrupt */
#define UART_IT_FLAG_DSRMI ((uint16_t)0x01UL << 3) /*!< UARTDSR modem interrupt */
#define UART_IT_FLAG_DCDMI ((uint16_t)0x01UL << 2) /*!< UARTDCD modem interrupt */
#define UART_IT_FLAG_CTSMI ((uint16_t)0x01UL << 1) /*!< UARTCTS modem interrupt */
#define UART_IT_FLAG_RIMI ((uint16_t)0x01UL << 0) /*!< UARTRI modem interrupt */
#define IS_UART_IT_FLAG(FLAG) (((FLAG) == UART_IT_FLAG_OEI) || ((FLAG) == UART_IT_FLAG_BEI) || \
((FLAG) == UART_IT_FLAG_PEI) || ((FLAG) == UART_IT_FLAG_FEI) || \
((FLAG) == UART_IT_FLAG_RTI) || ((FLAG) == UART_IT_FLAG_TXI) || \
((FLAG) == UART_IT_FLAG_RXI) || ((FLAG) == UART_IT_FLAG_DSRMI) || \
((FLAG) == UART_IT_FLAG_DCDMI)|| ((FLAG) == UART_IT_FLAG_CTSMI) || \
((FLAG) == UART_IT_FLAG_RIMI))
/**
* @}
*/
/** @addtogroup UART_FIFO_Level Select
* @{
*/
#define UART_IFLS_RXIFLSEL7_8 ((uint16_t)(UART_IFLS_RXIFLSEL(4)))
#define UART_IFLS_RXIFLSEL3_4 ((uint16_t)(UART_IFLS_RXIFLSEL(3)))
#define UART_IFLS_RXIFLSEL1_2 ((uint16_t)(UART_IFLS_RXIFLSEL(2)))
#define UART_IFLS_RXIFLSEL1_4 ((uint16_t)(UART_IFLS_RXIFLSEL(1)))
#define UART_IFLS_RXIFLSEL1_8 ((uint16_t)(UART_IFLS_RXIFLSEL(0)))
#define UART_IFLS_TXIFLSEL7_8 ((uint16_t)(UART_IFLS_TXIFLSEL(4)))
#define UART_IFLS_TXIFLSEL3_4 ((uint16_t)(UART_IFLS_TXIFLSEL(3)))
#define UART_IFLS_TXIFLSEL1_2 ((uint16_t)(UART_IFLS_TXIFLSEL(2)))
#define UART_IFLS_TXIFLSEL1_4 ((uint16_t)(UART_IFLS_TXIFLSEL(1)))
#define UART_IFLS_TXIFLSEL1_8 ((uint16_t)(UART_IFLS_TXIFLSEL(0)))
#define IS_UART_FIFO_Level(FLAG) (((FLAG) == UART_IFLS_RXIFLSEL7_8) || ((FLAG) == UART_IFLS_RXIFLSEL3_4)|| \
((FLAG) == UART_IFLS_RXIFLSEL1_2)|| ((FLAG) == UART_IFLS_RXIFLSEL1_4)|| ((FLAG) == UART_IFLS_RXIFLSEL1_8)||\
((FLAG) == UART_IFLS_TXIFLSEL7_8)|| ((FLAG) == UART_IFLS_TXIFLSEL3_4)|| \
((FLAG) == UART_IFLS_TXIFLSEL1_2)|| ((FLAG) == UART_IFLS_TXIFLSEL1_4)||((FLAG) == UART_IFLS_TXIFLSEL1_8))
/**
* @}
*/
/** @addtogroup S_UART_Flags
* @{
*/
#define S_UART_FLAG_RXO ((uint16_t)0x01UL << 3) /*!< RX buffer Overrun */
#define S_UART_FLAG_TXO ((uint16_t)0x01UL << 2) /*!< TX buffer Overrun */
#define S_UART_FLAG_RXF ((uint16_t)0x01UL << 1) /*!< RX buffer Full */
#define S_UART_FLAG_TXF ((uint16_t)0x01UL << 0) /*!< TX buffer Full */
#define IS_S_UART_FLAG(FLAG) (((FLAG) == S_UART_FLAG_RXO) || ((FLAG) == S_UART_FLAG_TXO) || \
((FLAG) == S_UART_FLAG_RXF) || ((FLAG) == S_UART_FLAG_TXF))
/**
* @}
*/
/** @addtogroup S_UART_IT_Flags
* @{
*/
#define S_UART_IT_FLAG_RXOI ((uint16_t)0x01UL << 5) /*!< RX overrun interrupt */
#define S_UART_IT_FLAG_TXOI ((uint16_t)0x01UL << 4) /*!< TX overrun interrupt */
#define S_UART_IT_FLAG_RXI ((uint16_t)0x01UL << 3) /*!< RX interrupt */
#define S_UART_IT_FLAG_TXI ((uint16_t)0x01UL << 2) /*!< TX interrupt */
#define IS_S_UART_IT_FLAG(FLAG) (((FLAG) == S_UART_IT_FLAG_RXOI) || ((FLAG) == S_UART_IT_FLAG_TXOI) || \
((FLAG) == S_UART_IT_FLAG_RXI) || ((FLAG) == S_UART_IT_FLAG_TXI))
/**
* @}
*/
void UART_StructInit (UART_InitTypeDef* UART_InitStruct);
uint32_t UART_Init (UART_TypeDef *UARTx, UART_InitTypeDef* UART_InitStruct);
void UART_SendData (UART_TypeDef* UARTx, uint16_t Data);
uint16_t UART_ReceiveData (UART_TypeDef* UARTx);
void UART_SendBreak (UART_TypeDef* UARTx);
void UART_ClearRecvStatus (UART_TypeDef* UARTx, uint16_t UART_RECV_STATUS);
FlagStatus UART_GetFlagStatus (UART_TypeDef* UARTx, uint16_t UART_FLAG);
void UART_ITConfig (UART_TypeDef* UARTx, uint16_t UART_IT, FunctionalState NewState);
ITStatus UART_GetITStatus (UART_TypeDef* UARTx, uint16_t UART_IT);
void UART_ClearITPendingBit (UART_TypeDef* UARTx, uint16_t UART_IT);
void S_UART_DeInit(void);
uint32_t S_UART_Init(uint32_t baud);
void S_UART_SendData(uint16_t Data);
uint16_t S_UART_ReceiveData(void);
uint8_t UartPutc (UART_TypeDef* UARTx, uint8_t ch);
void UartPuts (UART_TypeDef* UARTx, uint8_t *str);
uint8_t UartGetc (UART_TypeDef* UARTx);
uint8_t S_UartPutc(uint8_t ch);
void S_UartPuts(uint8_t *str);
uint8_t S_UartGetc(void);
#ifdef __cplusplus
}
#endif
#endif // __W7500X_UART_H

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
//*** ADC ***
extern const PinMap PinMap_ADC[];
//*** SERIAL ***
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
//*** I2C ***
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
//*** SPI ***
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SSEL[];
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
ADC_0 = (int)W7500x_ADC_BASE
} ADCName;
typedef enum {
UART_0 = (int)W7500x_UART0_BASE,
UART_1 = (int)W7500x_UART1_BASE
} UARTName;
#define STDIO_UART_TX PC_2
#define STDIO_UART_RX PC_3
#define STDIO_UART UART_1
typedef enum {
SPI_0 = (int)SSP0_BASE,
SPI_1 = (int)SSP1_BASE
} SPIName;
typedef enum {
I2C_0 = (int)I2C0_BASE,
I2C_1 = (int)I2C1_BASE
} I2CName;
typedef enum {
PWM_1 = 0
// PWM_1 = (int)TIM1_BASE,
// PWM_3 = (int)TIM3_BASE,
// PWM_14 = (int)TIM14_BASE,
// PWM_15 = (int)TIM15_BASE,
// PWM_16 = (int)TIM16_BASE,
// PWM_17 = (int)TIM17_BASE
} PWMName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "PeripheralPins.h"
#include "PeripheralNames.h"
#include "pinmap.h"
//*** ADC ***
const PinMap PinMap_ADC[] = {
{PC_15, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN0
{PC_14, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN1
{PC_13, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN2
{PC_12, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN3
{PC_11, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN4
{PC_10, ADC_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF3)}, // ADC0_IN5
{NC, NC, 0}
};
//*** SERIAL ***
const PinMap PinMap_UART_TX[] = {
{PA_14, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
{PC_2, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
{NC, NC, 0}
};
const PinMap PinMap_UART_RX[] = {
{PA_13, UART_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
{PC_3, UART_1, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_PULLUP, Px_AFSR_AF0)},
{NC, NC, 0}
};
//*** I2C ***
const PinMap PinMap_I2C_SDA[] = {
{PA_10, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{NC, NC, 0}
};
const PinMap PinMap_I2C_SCL[] = {
{PA_9, I2C_0, WIZ_PIN_DATA(WIZ_MODE_AF, WIZ_GPIO_NOPULL, Px_AFSR_AF0)},
{NC, NC, 0}
};
//*** SPI ***
const PinMap PinMap_SPI_SCLK[] = {
{PA_6 , SPI_0, 0},
{PB_1 , SPI_1, 0},
{PC_12, SPI_0, 3},
{PA_12, SPI_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{PA_8 , SPI_0, 0},
{PB_3 , SPI_1, 0},
{PC_10, SPI_0, 3},
{PA_14, SPI_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{PA_7 , SPI_0, 0},
{PB_2 , SPI_1, 0},
{PC_11, SPI_0, 3},
{PA_13, SPI_1, 3},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{PA_5 , SPI_0, 0},
{PB_0 , SPI_1, 0},
{PC_13, SPI_0, 3},
{PA_11, SPI_1, 3},
{NC , NC , 0}
};

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
// See W7500x_hal_gpio.h for values of MODE, PUPD and AFNUM
#define WIZ_PIN_DATA(MODE, PUPD, AFNUM) ((int)(((AFNUM) << 8) | ((PUPD) << 4) | ((MODE) << 0)))
#define WIZ_PIN_MODE(X) (((X) >> 0) & 0x0F)
#define WIZ_PIN_PUPD(X) (((X) >> 4) & 0x0F)
#define WIZ_PIN_AFNUM(X) (((X) >> 8) & 0x0F)
#define WIZ_MODE_INPUT (0)
#define WIZ_MODE_OUTPUT (1)
#define WIZ_MODE_AF (2)
#define WIZ_GPIO_NOPULL (0) /*!< No Pull-up or Pull-down activation */
#define WIZ_GPIO_PULLDOWN (1) /*!< Pull-down activation */
#define WIZ_GPIO_PULLUP (2) /*!< Pull-up activation */
#define WIZ_GPIO_OPEN_DRAIN (3) /*!< Open Drain activation */
#define WIZ_AFNUM(X)(((uint32_t)(X) >> 8) & 0xF) // AF number (0=AF0, 1=AF1, 2=AF2, 3=AF3)
#define WIZ_PORT(X) (((uint32_t)(X) >> 4) & 0xF) // port number (0=A, 1=B, 2=C, 3=D)
#define WIZ_PIN(X) ((uint32_t)(X) & 0xF) // pin number
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
typedef enum {
// W7500x Pin Names (AF[9:8] + PORT[5:4] + PIN[3:0])
PA_0 = 0x000,
PA_1 = 0x001,
PA_2 = 0x002,
PA_3 = 0x003,
PA_4 = 0x004,
PA_5 = 0x005,
PA_6 = 0x006,
PA_7 = 0x007,
PA_8 = 0x008,
PA_9 = 0x009,
PA_10 = 0x00A,
PA_11 = 0x00B,
PA_12 = 0x00C,
PA_13 = 0x00D,
PA_14 = 0x00E,
PA_15 = 0x00F,
PB_0 = 0x010, //SSEL1/SD_SEL
PB_1 = 0x011, //SCLK1/SD_CLK
PB_2 = 0x012, //MISO1/SD_MISO
PB_3 = 0x013, //MOSI1/SD_MOSI
PB_4 = 0x014,
PB_5 = 0x015,
PB_6 = 0x016,
PB_7 = 0x017,
PB_8 = 0x018,
PB_9 = 0x019,
PB_10 = 0x01A,
PB_11 = 0x01B,
PB_12 = 0x01C,
PB_13 = 0x01D,
PB_14 = 0x01E,
PB_15 = 0x01F,
PC_0 = 0x120, // 0xx:U_CTS1, 1xx:GPIOC_0, 2xx:PWM0
PC_1 = 0x121, // 0xx:U_RTS1, 1xx:GPIOC_1, 2xx:PWM1
PC_2 = 0x022,
PC_3 = 0x023,
PC_4 = 0x124, // 0xx:SDA1, 1xx:GPIOC_4, 2xx:PWM4
PC_5 = 0x025,
PC_6 = 0x026,
PC_7 = 0x027,
PC_8 = 0x128, // 0xx:PWM0, 1xx:GPIOC_8, 2xx:SCL0, 3xx:AIN7
PC_9 = 0x129, // 0xx:PWM1, 1xx:GPIOC_9, 2xx:SDA0, 3xx:AIN6
PC_10 = 0x32A, // 0xx:U_TXD2, 1xx:GPIOC_10, 2xx:PWM2, 3xx:AIN5
PC_11 = 0x32B, // 0xx:U_RXD2, 1xx:GPIOC_11, 2xx:PWM3, 3xx:AIN4
PC_12 = 0x32C, // 0xx:AIN3, 1xx:GPIOC_12, 2xx:SSEL0, 3xx:AIN3
PC_13 = 0x32D, // 0xx:AIN2, 1xx:GPIOC_13, 2xx:SCLK0, 3xx:AIN2
PC_14 = 0x32E, // 0xx:AIN1, 1xx:GPIOC_14, 2xx:MISO0, 3xx:AIN1
PC_15 = 0x32F, // 0xx:AIN0, 1xx:GPIOC_15, 2xx:MOSI0, 3xx:AIN0
PD_0 = 0x030,
PD_1 = 0x031,
PD_2 = 0x032,
PD_3 = 0x033,
PD_4 = 0x034,
// Arduino connector namings
A0 = PC_15, // AIN0
A1 = PC_14, // AIN1
A2 = PC_13, // AIN2
A3 = PC_12, // AIN3
A4 = PC_11, // AIN4
A5 = PC_10, // AIN5
D0 = PA_14, // U_TXD0
D1 = PA_13, // U_RXD0
D2 = PC_1, // GPIOC_1, EXTI
D3 = PC_0, // GPIOC_0, EXTI
D4 = PA_2, // GPIOA_2,
D5 = PA_1, // GPIOA_1,
D6 = PA_0, // GPIOA_0,
D7 = PC_6, // GPIOC_6, EXTI
D8 = PC_7, // GPIOC_7, EXTI
D9 = PC_4, // GPIOC_4, EXTI
D10 = PA_5, // SSEL0
D11 = PA_8, // MOSI0
D12 = PA_7, // MISO0
D13 = PA_6, // SCLK0
D14 = PA_10, // SDA0
D15 = PA_9, // SCL0
// Generic signals namings
LED_RED = PC_8,
LED_GREEN = PC_9,
LED_BLUE = PC_5,
LED1 = LED_RED,
LED2 = LED_GREEN,
LED3 = LED_BLUE,
LED4 = LED_BLUE,
// USER_BUTTON = PC_13,
SERIAL_TX = PC_2, // U_TXD1
SERIAL_RX = PC_3, // U_RXD1
USBTX = SERIAL_TX,
USBRX = SERIAL_RX,
I2C_SCL = PA_9, // SCL0
I2C_SDA = PA_10, // SDA0
SPI_MOSI = PA_8, // MISO0
SPI_MISO = PA_7, // MOSI0
SPI_SCK = PA_9, // SCL0
SPI_CS = PA_5, // SSEL0
SD_SEL = PB_0, // SSEL1
SD_CLK = PB_1, // SCL1
SD_MISO = PB_2, // MOSI1
SD_MOSI = PB_3, // MISO1
// PWM_OUT = PC_7,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullNone = 0,
PullDown = 1,
PullUp = 2,
OpenDrain = 3,
PullDefault = PullNone
} PinMode;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PortA = 0,
PortB = 1,
PortC = 2,
PortD = 3,
} PortName;
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
#define DEVICE_PORTIN 1
#define DEVICE_PORTOUT 1
#define DEVICE_PORTINOUT 1
#define DEVICE_INTERRUPTIN 1
#define DEVICE_ANALOGIN 1
#define DEVICE_ANALOGOUT 0 // Not present on this device
#define DEVICE_SERIAL 1
#define DEVICE_I2C 1
#define DEVICE_I2CSLAVE 0
#define DEVICE_SPI 1
#define DEVICE_SPISLAVE 1
#define DEVICE_RTC 0
#define DEVICE_PWMOUT 0
#define DEVICE_SLEEP 0
#define DEVICE_ETHERNET 0
//=======================================
#define DEVICE_SEMIHOST 0
#define DEVICE_LOCALFILESYSTEM 0
#define DEVICE_ID_LENGTH 24
#define DEVICE_DEBUG_AWARENESS 0
#define DEVICE_STDIO_MESSAGES 1
#define DEVICE_ERROR_RED 0
#include "objects.h"
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "PortNames.h"
#ifdef __cplusplus
extern "C" {
#endif
struct gpio_irq_s {
IRQn_Type irq_n;
uint32_t irq_index;
uint32_t event;
PinName pin;
};
struct port_s {
PortName port;
uint32_t mask;
PinDirection direction;
__IO uint32_t *reg_in;
__IO uint32_t *reg_out;
};
struct analogin_s {
ADCName adc;
PinName pin;
};
struct serial_s {
UARTName uart;
int index; // Used by irq
uint32_t baudrate;
uint32_t databits;
uint32_t stopbits;
uint32_t parity;
PinName pin_tx;
PinName pin_rx;
};
struct spi_s {
SSP_TypeDef *spi;
};
struct i2c_s {
I2CName i2c;
uint16_t ADDRESS;
uint16_t is_setAddress;
};
struct pwmout_s {
PWMName pwm;
PinName pin;
uint32_t period;
uint32_t pulse;
};
#include "gpio_object.h"
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#if DEVICE_ANALOGIN
#include "wait_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
ADC_TypeDef * AdcHandle;
static int adc_inited = 0;
void analogin_init(analogin_t *obj, PinName pin)
{
// Get the peripheral name from the pin and assign it to the object
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
// Configure GPIO
pinmap_pinout(pin, PinMap_ADC);
// Save pin number for the read function
obj->pin = pin;
// The ADC initialization is done once
if (adc_inited == 0) {
adc_inited = 1;
ADC_Init();
}
}
static inline uint16_t adc_read(analogin_t *obj)
{
ADC_CH adc_ch;
switch (obj->pin) {
case PC_15:
adc_ch = ADC_CH0;
break;
case PC_14:
adc_ch = ADC_CH1;
break;
case PC_13:
adc_ch = ADC_CH2;
break;
case PC_12:
adc_ch = ADC_CH3;
break;
case PC_11:
adc_ch = ADC_CH4;
break;
case PC_10:
adc_ch = ADC_CH5;
break;
default:
return 0;
}
ADC_ChannelSelect(adc_ch);
ADC_Start();
// Wait end of conversion and get value
while(ADC_IsInterrupt());
return ADC_ReadData();
}
uint16_t analogin_read_u16(analogin_t *obj)
{
uint16_t value = adc_read(obj);
// 12-bit to 16-bit conversion
return value;
}
float analogin_read(analogin_t *obj)
{
uint16_t value = adc_read(obj);
return (float)value * (1.0f / (float)0xFFF); // 12 bits range
}
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "gpio_api.h"
#include "pinmap.h"
extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx);
uint32_t gpio_set(PinName pin)
{
MBED_ASSERT(pin != (PinName)NC);
pin_function(pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0));
return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
}
void gpio_init(gpio_t *obj, PinName pin)
{
obj->pin = pin;
if (pin == (PinName)NC) {
return;
}
uint32_t port_index = WIZ_PORT(pin);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)Get_GPIO_BaseAddress(port_index);
// Fill GPIO object structure for future use
obj->mask = gpio_set(pin);
obj->reg_data_in = &gpio->DATA;
}
void gpio_mode(gpio_t *obj, PinMode mode)
{
pin_mode(obj->pin, mode);
}
void gpio_dir(gpio_t *obj, PinDirection direction)
{
MBED_ASSERT(obj->pin != (PinName)NC);
obj->direction = direction;
if (direction == PIN_OUTPUT) {
pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0));
} else { // PIN_INPUT
pin_function(obj->pin, WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0));
}
}

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifndef MBED_GPIO_OBJECT_H
#define MBED_GPIO_OBJECT_H
#include "mbed_assert.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef struct {
PinName pin;
uint32_t mask;
uint32_t direction;
__IO uint32_t *reg_data_in;
} gpio_t;
extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx);
static inline void gpio_write(gpio_t *obj, int value) {
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t port_index = WIZ_PORT(obj->pin);
uint32_t pin_index = WIZ_PIN(obj->pin);
uint32_t gpio_add = Get_GPIO_BaseAddress(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
if (value)
{
HAL_GPIO_SetBits(gpio,(0x01 << pin_index));
}
else
{
HAL_GPIO_ResetBits(gpio,(0x01 << pin_index));
}
}
static inline int gpio_read(gpio_t *obj) {
int ret;
MBED_ASSERT(obj->pin != (PinName)NC);
uint32_t port_index = WIZ_PORT(obj->pin);
uint32_t gpio_add = Get_GPIO_BaseAddress(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
if(obj->direction == PIN_OUTPUT)
{
ret = ( HAL_GPIO_ReadOutputData(gpio) & obj->mask ) ? 1 : 0;
}
else
{
ret = ((*obj->reg_data_in & obj->mask) ? 1 : 0);
}
return ret;
}
static inline int gpio_is_connected(const gpio_t *obj) {
return obj->pin != (PinName)NC;
}
#ifdef __cplusplus
}
#endif
#endif

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "i2c_api.h"
#if DEVICE_I2C
#include "cmsis.h"
#include "pinmap.h"
#include "PeripheralPins.h"
/* Timeout values for flags and events waiting loops. These timeouts are
not based on accurate values, they just guarantee that the application will
not remain stuck if the I2C communication is corrupted. */
#define FLAG_TIMEOUT ((int)0x1000)
#define LONG_TIMEOUT ((int)0xFFFF)
I2C_TypeDef * I2cHandle;
int i2c0_inited = 0;
int i2c1_inited = 0;
void i2c_init(i2c_t *obj, PinName sda, PinName scl)
{
// Determine the I2C to use
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT(obj->i2c != (I2CName)NC);
// Enable I2C1 clock and pinout if not done
if ((obj->i2c == I2C_0) && !i2c0_inited) {
i2c0_inited = 1;
// Configure I2C pins
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(sda, OpenDrain);
pin_mode(scl, OpenDrain);
}
// Enable I2C2 clock and pinout if not done
if ((obj->i2c == I2C_1) && !i2c1_inited) {
i2c1_inited = 1;
// Configure I2C pins
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
pin_mode(sda, OpenDrain);
pin_mode(scl, OpenDrain);
}
// Reset to clear pending flags if any
i2c_reset(obj);
// I2C configuration
i2c_frequency(obj, 100000); // 100 kHz per default
obj->is_setAddress = 0;
}
void i2c_frequency(i2c_t *obj, int hz)
{
MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
I2cHandle = (I2C_TypeDef *)(obj->i2c);
// wait before init
I2C_ConfigStruct conf;
conf.mode = I2C_Master;
conf.master.timeout = LONG_TIMEOUT;
// Common settings: I2C clock = 48 MHz, Analog filter = ON, Digital filter coefficient = 0
switch (hz) {
case 100000:
conf.master.prescale = 0x61; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
break;
case 400000:
break;
case 1000000:
break;
default:
break;
}
// I2C configuration
I2C_Init(I2cHandle, conf);
}
inline int i2c_start(i2c_t *obj)
{
obj->is_setAddress = 0;
return 0;
}
inline int i2c_stop(i2c_t *obj)
{
I2cHandle = (I2C_TypeDef *)(obj->i2c);
// Generate the STOP condition
I2C_Stop(I2cHandle);
I2C_Reset(I2cHandle);
obj->is_setAddress = 0;
return 0;
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
I2cHandle = (I2C_TypeDef *)(obj->i2c);
int count;
int value;
if(!obj->is_setAddress)
{
if( I2C_Start(I2cHandle, address, I2C_READ_SA7) == ERROR )
{
return -1;
}
obj->is_setAddress = 1;
obj->ADDRESS = address;
}
else
{
I2C_Restart_Structure(I2cHandle, address, I2C_READ_SA7);
obj->ADDRESS = address;
}
// Read all bytes
for (count = 0; count < (length-1); count++) {
if( (value = i2c_byte_read(obj, 0)) == -1) return value;
data[count] = (char)value;
}
if(stop){
if( (value = i2c_byte_read(obj, 1)) == -1) return value;
data[count] = (char)value;
}
else{
if( (value = i2c_byte_read(obj, 0)) == -1) return value;
data[count] = (char)value;
}
return count;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
{
I2cHandle = (I2C_TypeDef *)(obj->i2c);
int count;
if(!obj->is_setAddress)
{
if( I2C_Start(I2cHandle, address, I2C_WRITE_SA7) == ERROR )
{
return -1;
}
obj->is_setAddress = 1;
obj->ADDRESS = address;
}
else
{
I2C_Restart_Structure(I2cHandle, address, I2C_WRITE_SA7);
obj->ADDRESS = address;
}
for (count = 0; count < length; count++) {
i2c_byte_write(obj, data[count]);
}
// If not repeated start, send stop
if (stop) {
i2c_stop(obj);
}
return count;
}
int i2c_byte_read(i2c_t *obj, int last)
{
I2cHandle = (I2C_TypeDef *)(obj->i2c);
return I2C_ReceiveData(I2cHandle, last);
}
int i2c_byte_write(i2c_t *obj, int data)
{
I2cHandle = (I2C_TypeDef *)(obj->i2c);
return I2C_SendDataAck(I2cHandle,(uint8_t)data);
}
void i2c_reset(i2c_t *obj)
{
I2cHandle = (I2C_TypeDef *)(obj->i2c);
I2C_Reset(I2cHandle);
}
//#if DEVICE_I2CSLAVE
//
//void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
//{
// I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
// uint16_t tmpreg = 0;
//
// // disable
// i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN);
// // Get the old register value
// tmpreg = i2c->OAR1;
// // Reset address bits
// tmpreg &= 0xFC00;
// // Set new address
// tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
// // Store the new register value
// i2c->OAR1 = tmpreg;
// // enable
// i2c->OAR1 |= I2C_OAR1_OA1EN;
//}
//
//void i2c_slave_mode(i2c_t *obj, int enable_slave)
//{
// I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
// uint16_t tmpreg;
//
// // Get the old register value
// tmpreg = i2c->OAR1;
//
// // Enable / disable slave
// if (enable_slave == 1) {
// tmpreg |= I2C_OAR1_OA1EN;
// } else {
// tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN);
// }
//
// // Set new mode
// i2c->OAR1 = tmpreg;
//}
//
//// See I2CSlave.h
//#define NoData 0 // the slave has not been addressed
//#define ReadAddressed 1 // the master has requested a read from this slave (slave = transmitter)
//#define WriteGeneral 2 // the master is writing to all slave
//#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
//
//int i2c_slave_receive(i2c_t *obj)
//{
// I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
// int retValue = NoData;
//
// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
// if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1)
// retValue = ReadAddressed;
// else
// retValue = WriteAddressed;
//
// __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
// }
// }
//
// return (retValue);
//}
//
//int i2c_slave_read(i2c_t *obj, char *data, int length)
//{
// char size = 0;
//
// while (size < length) data[size++] = (char)i2c_byte_read(obj, 0);
//
// return size;
//}
//
//int i2c_slave_write(i2c_t *obj, const char *data, int length)
//{
// char size = 0;
// I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
//
// do {
// i2c_byte_write(obj, data[size]);
// size++;
// } while (size < length);
//
// return size;
//}
//
//
//#endif // DEVICE_I2CSLAVE
#endif // DEVICE_I2C

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "cmsis.h"
// This function is called after RAM initialization and before main.
void mbed_sdk_init()
{
// Update the SystemCoreClock variable.
SystemInit();
}

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "pinmap.h"
#include "PortNames.h"
// GPIO mode look-up table
// It have to same with PinMode index in "PinNames.h"
static const uint32_t gpio_pupd[4] = {
GPIO_NO_PUPD, // PullNone
GPIO_PuPd_DOWN, // PullDown
GPIO_PuPd_UP, // PullUp
GPIO_OD // OpenDrain
};
uint32_t Get_GPIO_BaseAddress(uint32_t port_idx)
{
uint32_t gpio_add = 0;
switch(port_idx) {
case PortA:
gpio_add = GPIOA_BASE;
break;
case PortB:
gpio_add = GPIOB_BASE;
break;
case PortC:
gpio_add = GPIOC_BASE;
break;
case PortD:
gpio_add = GPIOD_BASE;
break;
default:
error("Pinmap error: wrong port number.");
break;
}
return gpio_add;
}
/**
* Configure pin (input, output, alternate function or analog) + output speed + AF
*/
void pin_function(PinName pin, int data) {
MBED_ASSERT(pin != (PinName)NC);
// Get the pin informations
uint32_t mode = WIZ_PIN_MODE(data);
uint32_t pupd = WIZ_PIN_PUPD(data);
uint32_t afnum;
if( mode == WIZ_MODE_AF )
afnum = WIZ_PIN_AFNUM(data);
else
afnum = WIZ_AFNUM(pin);
uint32_t port_index = WIZ_PORT(pin);
uint32_t pin_index = WIZ_PIN(pin);
uint32_t gpio_add = Get_GPIO_BaseAddress(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
// Configure Alternate Function
// Warning: Must be done before the GPIO is initialized
switch (afnum) {
case 0:
HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF0);
break;
case 1:
HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF1);
break;
case 2:
HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF2);
break;
case 3:
HAL_PAD_AFConfig(port_index,(uint32_t)(1 << pin_index),Px_AFSR_AF3);
break;
default:
break;
}
if(mode == WIZ_MODE_AF)
return;
// Configure GPIO
GPIO_InitTypeDef GPIO_InitStructure;
GPIO_InitStructure.GPIO_Pin = (uint32_t)(1 << pin_index);
GPIO_InitStructure.GPIO_Mode = mode;
GPIO_InitStructure.GPIO_Pad = gpio_pupd[pupd];
HAL_GPIO_Init(gpio, &GPIO_InitStructure);
}
/**
* Configure pin pull-up/pull-down
*/
void pin_mode(PinName pin, PinMode pupd)
{
MBED_ASSERT(pin != (PinName)NC);
P_Port_Def *px_pcr;
uint32_t port_index = WIZ_PORT(pin);
switch(port_index) {
case PortA:
px_pcr = PA_PCR;
break;
case PortB:
px_pcr = PB_PCR;
break;
case PortC:
px_pcr = PC_PCR;
break;
case PortD:
px_pcr = (P_Port_Def*)PD_PCR;
break;
default:
error("Pinmap error: wrong port number.");
return;
}
px_pcr->Port[port_index] &= ~(Px_PCR_PUPD_DOWN|Px_PCR_PUPD_UP|Px_PCR_DS_HIGH| \
Px_PCR_OD | Px_PCR_IE | Px_PCR_CS_SUMMIT);
px_pcr->Port[port_index] |= gpio_pupd[pupd];
}

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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
#include "mbed_error.h"
#if DEVICE_PORTIN || DEVICE_PORTOUT
extern uint32_t Get_GPIO_BaseAddress(uint32_t port_idx);
//port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
PinName port_pin(PortName port, int pin_n)
{
int af_num = 0;
if( (port == 2) && ((pin_n == 0) || (pin_n == 1) || (pin_n == 4) || (pin_n == 8) || (pin_n == 9)) )
{
af_num = 1;
}
return (PinName)(pin_n + (port << 4) + (af_num << 8));
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
{
uint32_t port_index = (uint32_t)port;
// Enable GPIO clock
uint32_t gpio_add = Get_GPIO_BaseAddress(port_index);
GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
// Fill PORT object structure for future use
obj->port = port;
obj->mask = mask;
obj->direction = dir;
obj->reg_in = &gpio->DATA;
obj->reg_out = &gpio->DATAOUT;
port_dir(obj, dir);
}
void port_dir(port_t *obj, PinDirection dir)
{
uint32_t i;
obj->direction = dir;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
if (dir == PIN_OUTPUT) {
pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_OUTPUT, WIZ_GPIO_NOPULL, 0));
} else { // PIN_INPUT
pin_function(port_pin(obj->port, i), WIZ_PIN_DATA(WIZ_MODE_INPUT, WIZ_GPIO_NOPULL, 0));
}
}
}
}
void port_mode(port_t *obj, PinMode mode)
{
uint32_t i;
for (i = 0; i < 16; i++) { // Process all pins
if (obj->mask & (1 << i)) { // If the pin is used
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_write(port_t *obj, int value)
{
*obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
}
int port_read(port_t *obj)
{
if (obj->direction == PIN_OUTPUT) {
return (*obj->reg_out & obj->mask);
} else { // PIN_INPUT
return (*obj->reg_in & obj->mask);
}
}
#endif

310
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include "serial_api.h"
#if DEVICE_SERIAL
#include "cmsis.h"
#include "pinmap.h"
#include <string.h>
#include "PeripheralPins.h"
#define UART_NUM (2)
static uint32_t serial_irq_ids[UART_NUM] = {0, 0};
static uart_irq_handler irq_handler;
static UART_TypeDef *UART;
UART_InitTypeDef UART_InitStructure;
int stdio_uart_inited = 0;
serial_t stdio_uart;
static void init_uart(serial_t *obj)
{
UART = (UART_TypeDef *)(obj->uart);
UART_InitStructure.UART_BaudRate = obj->baudrate;
UART_InitStructure.UART_WordLength = obj->databits;
UART_InitStructure.UART_StopBits = obj->stopbits;
UART_InitStructure.UART_Parity = obj->parity;
UART_InitStructure.UART_HardwareFlowControl = UART_HardwareFlowControl_None;
if (obj->pin_rx == NC) {
UART_InitStructure.UART_Mode = UART_Mode_Tx;
} else if (obj->pin_tx == NC) {
UART_InitStructure.UART_Mode = UART_Mode_Rx;
} else {
UART_InitStructure.UART_Mode = (UART_Mode_Rx | UART_Mode_Tx);
}
UART_Init(UART,&UART_InitStructure);
}
void serial_init(serial_t *obj, PinName tx, PinName rx)
{
// Determine the UART to use (UART_1, UART_2, ...)
UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
// Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT(obj->uart != (UARTName)NC);
// Enable USART clock
if (obj->uart == UART_0) {
obj->index = 0;
}
if (obj->uart == UART_1) {
obj->index = 1;
}
// Configure the UART pins
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
if (tx != NC) {
pin_mode(tx, PullUp);
}
if (rx != NC) {
pin_mode(rx, PullUp);
}
// Configure UART
obj->baudrate = 9600;
obj->databits = UART_WordLength_8b;
obj->stopbits = UART_StopBits_1;
obj->parity = UART_Parity_No;
obj->pin_tx = tx;
obj->pin_rx = rx;
init_uart(obj);
// For stdio management
if (obj->uart == STDIO_UART) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj)
{
// Reset UART and disable clock
if (obj->uart == UART_0) {
}
if (obj->uart == UART_1) {
}
// Configure GPIOs
// pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
// pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
serial_irq_ids[obj->index] = 0;
}
void serial_baud(serial_t *obj, int baudrate)
{
obj->baudrate = baudrate;
init_uart(obj);
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
if (data_bits == 7) {
obj->databits = UART_WordLength_7b;
} else {
obj->databits = UART_WordLength_8b;
}
switch (parity) {
case ParityOdd:
case ParityForced0:
obj->parity = UART_Parity_Odd;
break;
case ParityEven:
case ParityForced1:
obj->parity = UART_Parity_Even;
break;
default: // ParityNone
obj->parity = UART_Parity_No;
break;
}
if (stop_bits == 2) {
obj->stopbits = UART_StopBits_2;
} else {
obj->stopbits = UART_StopBits_1;
}
init_uart(obj);
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static void uart_irq(UARTName name, int id)
{
UART = (UART_TypeDef *)name;
if (serial_irq_ids[id] != 0) {
if( UART_GetITStatus(UART,UART_IT_FLAG_TXI) != RESET ){
irq_handler(serial_irq_ids[id], TxIrq);
UART_ClearITPendingBit(UART,UART_IT_FLAG_TXI);
}
if( UART_GetITStatus(UART,UART_IT_FLAG_RXI) != RESET ){
irq_handler(serial_irq_ids[id], RxIrq);
}
}
}
#ifdef __cplusplus
extern "C"{
#endif
void UART0_Handler()
{
uart_irq(UART_0, 0);
}
void UART1_Handler()
{
uart_irq(UART_1, 1);
}
#ifdef __cplusplus
}
#endif
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
irq_handler = handler;
serial_irq_ids[obj->index] = id;
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
IRQn_Type irq_n = (IRQn_Type)0;
UART = (UART_TypeDef *)(obj->uart);
if (obj->uart == UART_0) {
irq_n = UART0_IRQn;
}
if (obj->uart == UART_1) {
irq_n = UART1_IRQn;
}
if (enable) {
if (irq == RxIrq) {
UART_ITConfig(UART,UART_IT_FLAG_RXI,ENABLE);
} else { // TxIrq
UART_ITConfig(UART,UART_IT_FLAG_TXI,ENABLE);
}
NVIC_ClearPendingIRQ(irq_n);
NVIC_EnableIRQ(irq_n);
} else { // disable
UART_ITConfig(UART,(UART_IT_FLAG_RXI|UART_IT_FLAG_TXI),DISABLE);
NVIC_DisableIRQ(irq_n);
}
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj)
{
UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
// while(!serial_readable(obj));
while(uart->FR & UART_FR_RXFE);
return (uart->DR & 0xFF);
}
void serial_putc(serial_t *obj, int c)
{
UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
uart->DR = (uint32_t)(c & (uint16_t)0xFF);
while(uart->FR & UART_FR_BUSY);
}
int serial_readable(serial_t *obj)
{
int status;
UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
// Check if data is received
status = ((uart->FR & UART_FR_RXFE) ? 0: 1);
return status;
}
int serial_writable(serial_t *obj)
{
int status;
UART_TypeDef *uart = (UART_TypeDef *)(obj->uart);
// Check if data is transmitted
status = ((uart->FR & UART_FR_BUSY) ? 0: 1);
return status;
}
void serial_clear(serial_t *obj)
{
// UartHandle.Instance = (USART_TypeDef *)(obj->uart);
// __HAL_UART_CLEAR_IT(&UartHandle, UART_FLAG_TC);
// __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
}
void serial_pinout_tx(PinName tx)
{
//pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj)
{
// [TODO]
}
void serial_break_clear(serial_t *obj)
{
// [TODO]
}
#endif

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libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/sleep.c Normal file
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/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "sleep_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
void sleep(void)
{
// To Do
}
void deepsleep(void)
{
// To Do
}

202
libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/spi_api.c Normal file
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@ -0,0 +1,202 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "mbed_assert.h"
#include <math.h>
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "PeripheralPins.h"
static inline int ssp_disable(spi_t *obj);
static inline int ssp_enable(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)obj->spi != NC);
// enable power and clocking
switch ((int)obj->spi) {
case SPI_0: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock
case SPI_1: CRG->SSPCLK_SSR = CRG_SSPCLK_SSR_MCLK; break;
}
// set default format and frequency
if (ssel == NC) {
spi_format(obj, 8, 0, 0); // 8 bits, mode 0, master
} else {
spi_format(obj, 8, 0, 1); // 8 bits, mode 0, slave
}
spi_frequency(obj, 1000000);
// enable the ssp channel
ssp_enable(obj);
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if (ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
ssp_disable(obj);
MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
// set it up
int DSS = bits - 1; // DSS (data select size)
int SPO = (polarity) ? 1 : 0; // SPO - clock out polarity
int SPH = (phase) ? 1 : 0; // SPH - clock out phase
int FRF = 0; // FRF (frame format) = SPI
uint32_t tmp = obj->spi->CR0;
tmp &= ~(0xFFFF);
tmp |= DSS << 0
| FRF << 4
| SPO << 6
| SPH << 7;
obj->spi->CR0 = tmp;
tmp = obj->spi->CR1;
tmp &= ~(0xD);
tmp |= 0 << 0 // LBM - loop back mode - off
| ((slave) ? 1 : 0) << 2 // MS - master slave mode, 1 = slave
| 0 << 3; // SOD - slave output disable - na
obj->spi->CR1 = tmp;
ssp_enable(obj);
}
void spi_frequency(spi_t *obj, int hz) {
ssp_disable(obj);
// setup the spi clock diveder to /1
switch ((int)obj->spi) {
case SPI_0:
CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
break;
case SPI_1:
CRG->SSPCLK_PVSR = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
break;
}
uint32_t HCLK = SystemCoreClock;
int prescaler;
for (prescaler = 2; prescaler <= 254; prescaler += 2) {
int prescale_hz = HCLK / prescaler;
// calculate the divider
int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
// check we can support the divider
if (divider < 256) {
// prescaler
obj->spi->CPSR = prescaler;
// divider
obj->spi->CR0 &= ~(0xFFFF << 8);
obj->spi->CR0 |= (divider - 1) << 8;
ssp_enable(obj);
return;
}
}
error("Couldn't setup requested SPI frequency");
}
static inline int ssp_disable(spi_t *obj) {
return obj->spi->CR1 &= ~(1 << 1);
}
static inline int ssp_enable(spi_t *obj) {
return obj->spi->CR1 |= (1 << 1);
}
static inline int ssp_readable(spi_t *obj) {
return obj->spi->SR & (1 << 2);
}
static inline int ssp_writeable(spi_t *obj) {
return obj->spi->SR & (1 << 1);
}
static inline void ssp_write(spi_t *obj, int value) {
while (!ssp_writeable(obj));
obj->spi->DR = value;
}
static inline int ssp_read(spi_t *obj) {
while (!ssp_readable(obj));
return obj->spi->DR;
}
static inline int ssp_busy(spi_t *obj) {
return (obj->spi->SR & (1 << 4)) ? (1) : (0);
}
int spi_master_write(spi_t *obj, int value) {
ssp_write(obj, value);
return ssp_read(obj);
}
int spi_slave_receive(spi_t *obj) {
return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj) {
return obj->spi->DR;
}
void spi_slave_write(spi_t *obj, int value) {
while (ssp_writeable(obj) == 0) ;
obj->spi->DR = value;
}
int spi_busy(spi_t *obj) {
return ssp_busy(obj);
}

137
libraries/mbed/targets/hal/TARGET_WIZNET/TARGET_W7500x/us_ticker.c Normal file
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@ -0,0 +1,137 @@
/* mbed Microcontroller Library
*******************************************************************************
* Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "system_W7500x.h"
// 32-bit timer selection
#define TIM_MST7 PWM_CH7
#define TIM_MST6 PWM_CH6
#define IRQn_PWM6 PWM6_IRQn
static PWM_TimerModeInitTypeDef TimMasterHandle_CH7;
static PWM_TimerModeInitTypeDef TimMasterHandle_CH6;
static int us_ticker_inited = 0;
#ifdef __cplusplus
extern "C"{
#endif
void PWM6_Handler(void)
{
uint32_t IntFlag = 0;
IntFlag = PWM_CHn_GetIntFlagStatus(TIM_MST6);
/* If overflow interrupt is occurred */
if( (IntFlag & PWM_CHn_IER_OI_Msk) != 0 )
{
/* Clear overflow interrupt */
PWM_CH6_ClearOverflowInt();
us_ticker_irq_handler();
}
}
#ifdef __cplusplus
}
#endif
void us_ticker_init(void)
{
if (us_ticker_inited) return;
us_ticker_inited = 1;
SystemCoreClockUpdate();
TimMasterHandle_CH7.PWM_CHn_PR = (GetSystemClock() / 1000000) -1;
TimMasterHandle_CH7.PWM_CHn_LR = 0xFFFFFFFF;
TimMasterHandle_CH7.PWM_CHn_PDMR = 1;
PWM_TimerModeInit(TIM_MST7, &TimMasterHandle_CH7);
PWM_CHn_Start(TIM_MST7);
}
uint32_t us_ticker_read()
{
if (!us_ticker_inited) us_ticker_init();
return (TIM_MST7->TCR);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
int32_t dev = 0;
if (!us_ticker_inited)
{
us_ticker_init();
}
dev = (int32_t)(timestamp - (us_ticker_read() + 150));
if(dev <= 0)
{
us_ticker_irq_handler();
return;
}
PWM_CHn_Stop(TIM_MST6);
SystemCoreClockUpdate();
TimMasterHandle_CH6.PWM_CHn_PR = (GetSystemClock() / 1000000) -1;
TimMasterHandle_CH6.PWM_CHn_LR = dev;
TimMasterHandle_CH6.PWM_CHn_UDMR = 0;
TimMasterHandle_CH6.PWM_CHn_PDMR = 0;
NVIC_EnableIRQ(IRQn_PWM6);
PWM_CHn_IntConfig(TIM_MST6, PWM_CHn_IER_OIE, ENABLE);
PWM_IntConfig(TIM_MST6, ENABLE);
PWM_TimerModeInit(TIM_MST6, &TimMasterHandle_CH6);
PWM_CHn_Start(TIM_MST6);
}
void us_ticker_disable_interrupt(void)
{
NVIC_DisableIRQ(IRQn_PWM6);
PWM_CHn_IntConfig(TIM_MST6, PWM_CHn_IER_OIE, DISABLE);
PWM_IntConfig(TIM_MST6, DISABLE);
}
void us_ticker_clear_interrupt(void)
{
PWM_CHn_ClearInt(TIM_MST6, PWM_CHn_IER_OIE);
}

2
workspace_tools/build_release.py
View File

@ -101,6 +101,8 @@ OFFICIAL_MBED_LIBRARY_BUILD = (
('EFM32WG_STK3800', ('ARM', 'GCC_ARM', 'uARM')),
('MAXWSNENV', ('ARM', 'GCC_ARM', 'IAR')),
('WIZwiki_W7500', ('ARM', 'uARM')),
)

16
workspace_tools/targets.py
View File

@ -69,8 +69,19 @@ class Target:
def init_hooks(self, hook, toolchain_name):
pass
##WIZnet
class WIZwiki_W7500(Target):
def __init__(self):
Target.__init__(self)
self.core = "Cortex-M0"
self.extra_labels = ['WIZNET', 'W7500x', 'WIZwiki_W7500']
self.supported_toolchains = ["uARM", "ARM"]
self.default_toolchain = "ARM"
self.supported_form_factors = ["ARDUINO"]
### NXP ###
# This class implements the post-link patching step needed by LPC targets
@ -1242,6 +1253,9 @@ class EFM32HG_STK3400(Target):
# Get a single instance for each target
TARGETS = [
### WIZnet ###
WIZwiki_W7500(),
### NXP ###
LPC11C24(),
LPC11U24(),