diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/CHANGELOG.md b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/CHANGELOG.md
new file mode 100644
index 0000000000..bb4dad9a4a
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/CHANGELOG.md
@@ -0,0 +1,344 @@
+# Change Log
+
+## [v2.5.3](https://github.com/ARMmbed/ble-nrf51822/tree/v2.5.3) (2016-02-16)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.5.2...v2.5.3)
+
+**Merged pull requests:**
+
+- Fix for compilation errors with S110 softdevice in btle.cpp [\#109](https://github.com/ARMmbed/ble-nrf51822/pull/109) ([ddavidebor](https://github.com/ddavidebor))
+
+## [v2.5.2](https://github.com/ARMmbed/ble-nrf51822/tree/v2.5.2) (2016-02-16)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.5.1...v2.5.2)
+
+**Merged pull requests:**
+
+- Sync develop against master [\#113](https://github.com/ARMmbed/ble-nrf51822/pull/113) ([pan-](https://github.com/pan-))
+- Fix incorrect handles of characteristics descriptors. [\#112](https://github.com/ARMmbed/ble-nrf51822/pull/112) ([pan-](https://github.com/pan-))
+
+## [v2.5.1](https://github.com/ARMmbed/ble-nrf51822/tree/v2.5.1) (2016-01-27)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.5.0...v2.5.1)
+
+**Merged pull requests:**
+
+- Remove Gap::state updates from this module [\#108](https://github.com/ARMmbed/ble-nrf51822/pull/108) ([andresag01](https://github.com/andresag01))
+- merge version  [\#106](https://github.com/ARMmbed/ble-nrf51822/pull/106) ([pan-](https://github.com/pan-))
+
+## [v2.5.0](https://github.com/ARMmbed/ble-nrf51822/tree/v2.5.0) (2016-01-12)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.4.1...v2.5.0)
+
+**Merged pull requests:**
+
+- Fix access to enum member [\#105](https://github.com/ARMmbed/ble-nrf51822/pull/105) ([pan-](https://github.com/pan-))
+- Hotfix dependency [\#104](https://github.com/ARMmbed/ble-nrf51822/pull/104) ([pan-](https://github.com/pan-))
+- Finish implementation of getAddressesFromBondTable [\#103](https://github.com/ARMmbed/ble-nrf51822/pull/103) ([andresag01](https://github.com/andresag01))
+
+## [v2.4.1](https://github.com/ARMmbed/ble-nrf51822/tree/v2.4.1) (2016-01-11)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.4.0...v2.4.1)
+
+**Merged pull requests:**
+
+- merge branch develop \(v2.4.0\) [\#100](https://github.com/ARMmbed/ble-nrf51822/pull/100) ([pan-](https://github.com/pan-))
+
+## [v2.4.0](https://github.com/ARMmbed/ble-nrf51822/tree/v2.4.0) (2016-01-10)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.3.1...v2.4.0)
+
+**Merged pull requests:**
+
+- Add implementation of experimental whitelisting API [\#99](https://github.com/ARMmbed/ble-nrf51822/pull/99) ([andresag01](https://github.com/andresag01))
+
+## [v2.3.1](https://github.com/ARMmbed/ble-nrf51822/tree/v2.3.1) (2016-01-07)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.3.0...v2.3.1)
+
+**Merged pull requests:**
+
+- Update yotta module dependencies [\#98](https://github.com/ARMmbed/ble-nrf51822/pull/98) ([pan-](https://github.com/pan-))
+
+## [v2.3.0](https://github.com/ARMmbed/ble-nrf51822/tree/v2.3.0) (2015-12-23)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.10...v2.3.0)
+
+**Merged pull requests:**
+
+- Implementation of Characteristic descriptor discovery [\#74](https://github.com/ARMmbed/ble-nrf51822/pull/74) ([pan-](https://github.com/pan-))
+
+## [v2.2.10](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.10) (2015-12-23)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.9...v2.2.10)
+
+**Fixed bugs:**
+
+- nRF5xn::init don't verify if errors have occurred during btle\_init [\#59](https://github.com/ARMmbed/ble-nrf51822/issues/59)
+
+**Closed issues:**
+
+- A call to shutdown does not clear the state of some components of BLE API [\#85](https://github.com/ARMmbed/ble-nrf51822/issues/85)
+- Memory allocation issue on the NRF51DK board. [\#76](https://github.com/ARMmbed/ble-nrf51822/issues/76)
+- Terrible handling of initLen / minLen and variable length characteristics. [\#56](https://github.com/ARMmbed/ble-nrf51822/issues/56)
+
+**Merged pull requests:**
+
+- Fix shutdown of Gap instance to avoid NULL refs [\#96](https://github.com/ARMmbed/ble-nrf51822/pull/96) ([andresag01](https://github.com/andresag01))
+- Add check for return code of ble\_init [\#95](https://github.com/ARMmbed/ble-nrf51822/pull/95) ([andresag01](https://github.com/andresag01))
+
+## [v2.2.9](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.9) (2015-12-18)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.8...v2.2.9)
+
+**Closed issues:**
+
+- Cannot open source input file "system\_nrf51.h" [\#52](https://github.com/ARMmbed/ble-nrf51822/issues/52)
+
+**Merged pull requests:**
+
+- Remove occurrence of deprecated appearance enum [\#92](https://github.com/ARMmbed/ble-nrf51822/pull/92) ([andresag01](https://github.com/andresag01))
+
+## [v2.2.8](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.8) (2015-12-16)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.7...v2.2.8)
+
+## [v2.2.7](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.7) (2015-12-15)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.6...v2.2.7)
+
+**Merged pull requests:**
+
+- Replace deprecated inclusions of mbed.h [\#89](https://github.com/ARMmbed/ble-nrf51822/pull/89) ([andresag01](https://github.com/andresag01))
+- Improve shutdown to clear BLE API and not just SD [\#87](https://github.com/ARMmbed/ble-nrf51822/pull/87) ([andresag01](https://github.com/andresag01))
+
+## [v2.2.6](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.6) (2015-12-15)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.5...v2.2.6)
+
+**Merged pull requests:**
+
+- follow the extraction of address related types from Gap.h into BLEProtocol.h [\#88](https://github.com/ARMmbed/ble-nrf51822/pull/88) ([rgrover](https://github.com/rgrover))
+
+## [v2.2.5](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.5) (2015-12-11)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.3...v2.2.5)
+
+**Merged pull requests:**
+
+- Added SecurityManager::setLinkSecurity call for elevating security settings on a particular connection. [\#86](https://github.com/ARMmbed/ble-nrf51822/pull/86) ([marcuschangarm](https://github.com/marcuschangarm))
+
+## [v2.2.3](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.3) (2015-12-10)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.2...v2.2.3)
+
+## [v2.2.2](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.2) (2015-12-08)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.1...v2.2.2)
+
+**Merged pull requests:**
+
+- Add -Wno-unused-function to supress-warnings.cmake [\#83](https://github.com/ARMmbed/ble-nrf51822/pull/83) ([andresag01](https://github.com/andresag01))
+
+## [v2.2.1](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.1) (2015-12-08)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.2.0...v2.2.1)
+
+**Merged pull requests:**
+
+- WIP: UUID endian change [\#82](https://github.com/ARMmbed/ble-nrf51822/pull/82) ([marcuschangarm](https://github.com/marcuschangarm))
+
+## [v2.2.0](https://github.com/ARMmbed/ble-nrf51822/tree/v2.2.0) (2015-12-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.1.4...v2.2.0)
+
+## [v2.1.4](https://github.com/ARMmbed/ble-nrf51822/tree/v2.1.4) (2015-12-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.1.3...v2.1.4)
+
+## [v2.1.3](https://github.com/ARMmbed/ble-nrf51822/tree/v2.1.3) (2015-12-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.1.2...v2.1.3)
+
+## [v2.1.2](https://github.com/ARMmbed/ble-nrf51822/tree/v2.1.2) (2015-12-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.1.1...v2.1.2)
+
+**Merged pull requests:**
+
+- Allow GattAttributes to have variable length [\#81](https://github.com/ARMmbed/ble-nrf51822/pull/81) ([andresag01](https://github.com/andresag01))
+
+## [v2.1.1](https://github.com/ARMmbed/ble-nrf51822/tree/v2.1.1) (2015-12-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.1.0...v2.1.1)
+
+**Merged pull requests:**
+
+- Fixed endianness bug in nRF5xServiceDiscovery::processDiscoverUUIDResponse so it is consistent with BLE API. [\#80](https://github.com/ARMmbed/ble-nrf51822/pull/80) ([marcuschangarm](https://github.com/marcuschangarm))
+- Fixed bug in nRF5xGap.setAddress where random adresses where not set properly. [\#79](https://github.com/ARMmbed/ble-nrf51822/pull/79) ([marcuschangarm](https://github.com/marcuschangarm))
+- Separate concept of minlen and len for BLE chars [\#78](https://github.com/ARMmbed/ble-nrf51822/pull/78) ([andresag01](https://github.com/andresag01))
+- Split nordic sdk into its own module [\#75](https://github.com/ARMmbed/ble-nrf51822/pull/75) ([LiyouZhou](https://github.com/LiyouZhou))
+
+## [v2.1.0](https://github.com/ARMmbed/ble-nrf51822/tree/v2.1.0) (2015-11-27)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.8...v2.1.0)
+
+**Merged pull requests:**
+
+- Update to sdk 8.1 [\#77](https://github.com/ARMmbed/ble-nrf51822/pull/77) ([LiyouZhou](https://github.com/LiyouZhou))
+
+## [v2.0.8](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.8) (2015-11-26)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.7...v2.0.8)
+
+## [v2.0.7](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.7) (2015-11-26)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.6...v2.0.7)
+
+**Closed issues:**
+
+- test2000 [\#72](https://github.com/ARMmbed/ble-nrf51822/issues/72)
+- test1000000 [\#71](https://github.com/ARMmbed/ble-nrf51822/issues/71)
+- test4 [\#70](https://github.com/ARMmbed/ble-nrf51822/issues/70)
+- test3 [\#69](https://github.com/ARMmbed/ble-nrf51822/issues/69)
+- test2 [\#68](https://github.com/ARMmbed/ble-nrf51822/issues/68)
+
+**Merged pull requests:**
+
+- use Extern c around \#include to use nordic sdk headers implemented in C [\#73](https://github.com/ARMmbed/ble-nrf51822/pull/73) ([LiyouZhou](https://github.com/LiyouZhou))
+
+## [v2.0.6](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.6) (2015-11-17)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.5...v2.0.6)
+
+**Closed issues:**
+
+- test [\#66](https://github.com/ARMmbed/ble-nrf51822/issues/66)
+
+**Merged pull requests:**
+
+- add Nordic's license agreement. [\#67](https://github.com/ARMmbed/ble-nrf51822/pull/67) ([rgrover](https://github.com/rgrover))
+
+## [v2.0.5](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.5) (2015-11-16)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.4...v2.0.5)
+
+**Merged pull requests:**
+
+- Post radio notification callback through minar [\#65](https://github.com/ARMmbed/ble-nrf51822/pull/65) ([andresag01](https://github.com/andresag01))
+
+## [v2.0.4](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.4) (2015-11-13)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.3...v2.0.4)
+
+**Merged pull requests:**
+
+- Fix assembly sequence to start bootloader in GCC [\#64](https://github.com/ARMmbed/ble-nrf51822/pull/64) ([andresag01](https://github.com/andresag01))
+
+## [v2.0.3](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.3) (2015-11-09)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.2...v2.0.3)
+
+**Merged pull requests:**
+
+- Added watchdog header file from Nordic SDK 8.1 [\#62](https://github.com/ARMmbed/ble-nrf51822/pull/62) ([marcuschangarm](https://github.com/marcuschangarm))
+
+## [v2.0.2](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.2) (2015-11-03)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/mbedos-release-15-11...v2.0.2)
+
+## [mbedos-release-15-11](https://github.com/ARMmbed/ble-nrf51822/tree/mbedos-release-15-11) (2015-11-03)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.1...mbedos-release-15-11)
+
+## [v2.0.1](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.1) (2015-11-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v2.0.0...v2.0.1)
+
+**Merged pull requests:**
+
+- Ensure that the initialization flags is set to false if the BLE stack is shutdown properly. [\#58](https://github.com/ARMmbed/ble-nrf51822/pull/58) ([pan-](https://github.com/pan-))
+
+## [v2.0.0](https://github.com/ARMmbed/ble-nrf51822/tree/v2.0.0) (2015-11-02)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v1.1.0...v2.0.0)
+
+**Closed issues:**
+
+- Nordic SDK and SoftDevice [\#57](https://github.com/ARMmbed/ble-nrf51822/issues/57)
+- shouldn't eab6631cb be merged into master? [\#54](https://github.com/ARMmbed/ble-nrf51822/issues/54)
+
+**Merged pull requests:**
+
+- Introduced changes for memory savings [\#55](https://github.com/ARMmbed/ble-nrf51822/pull/55) ([andresag01](https://github.com/andresag01))
+
+## [v1.1.0](https://github.com/ARMmbed/ble-nrf51822/tree/v1.1.0) (2015-10-28)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v1.0.0...v1.1.0)
+
+**Closed issues:**
+
+- target dependencies in module.json [\#50](https://github.com/ARMmbed/ble-nrf51822/issues/50)
+
+**Merged pull requests:**
+
+- When connecting, if no scanning parameters are passed, use values from Gap parent. [\#53](https://github.com/ARMmbed/ble-nrf51822/pull/53) ([marcuschangarm](https://github.com/marcuschangarm))
+
+## [v1.0.0](https://github.com/ARMmbed/ble-nrf51822/tree/v1.0.0) (2015-10-19)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/mbedos-techcon-oob2...v1.0.0)
+
+## [mbedos-techcon-oob2](https://github.com/ARMmbed/ble-nrf51822/tree/mbedos-techcon-oob2) (2015-10-19)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v0.4.8...mbedos-techcon-oob2)
+
+**Closed issues:**
+
+- rename the bootloader files with \_fota in the name? [\#51](https://github.com/ARMmbed/ble-nrf51822/issues/51)
+
+**Merged pull requests:**
+
+- Update S110 detection macros, again [\#49](https://github.com/ARMmbed/ble-nrf51822/pull/49) ([jpbrucker](https://github.com/jpbrucker))
+- Error check number of characteristics [\#48](https://github.com/ARMmbed/ble-nrf51822/pull/48) ([Timmmm](https://github.com/Timmmm))
+
+## [v0.4.8](https://github.com/ARMmbed/ble-nrf51822/tree/v0.4.8) (2015-09-25)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v0.4.7...v0.4.8)
+
+**Closed issues:**
+
+- Error real cause loss in nRF5xGattServer.cpp [\#44](https://github.com/ARMmbed/ble-nrf51822/issues/44)
+
+**Merged pull requests:**
+
+- rgrover patch fixed [\#47](https://github.com/ARMmbed/ble-nrf51822/pull/47) ([fabiencomte](https://github.com/fabiencomte))
+- Update S110 detection macros [\#43](https://github.com/ARMmbed/ble-nrf51822/pull/43) ([jpbrucker](https://github.com/jpbrucker))
+- remove some unnecessary include paths [\#42](https://github.com/ARMmbed/ble-nrf51822/pull/42) ([autopulated](https://github.com/autopulated))
+- Add FOTA bootloader image [\#41](https://github.com/ARMmbed/ble-nrf51822/pull/41) ([jpbrucker](https://github.com/jpbrucker))
+
+## [v0.4.7](https://github.com/ARMmbed/ble-nrf51822/tree/v0.4.7) (2015-08-13)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v0.4.6...v0.4.7)
+
+## [v0.4.6](https://github.com/ARMmbed/ble-nrf51822/tree/v0.4.6) (2015-08-11)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v0.4.5...v0.4.6)
+
+**Closed issues:**
+
+- remove duplication of global static variable BLE\_EVT\_BUFFER [\#39](https://github.com/ARMmbed/ble-nrf51822/issues/39)
+- clearScanResponse\(\)  [\#30](https://github.com/ARMmbed/ble-nrf51822/issues/30)
+- Debug builds fail due to missing bsp.h [\#11](https://github.com/ARMmbed/ble-nrf51822/issues/11)
+
+**Merged pull requests:**
+
+- Disable GattClient features when using S110 SoftDevice [\#38](https://github.com/ARMmbed/ble-nrf51822/pull/38) ([jpbrucker](https://github.com/jpbrucker))
+
+## [v0.4.5](https://github.com/ARMmbed/ble-nrf51822/tree/v0.4.5) (2015-08-10)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v0.4.4...v0.4.5)
+
+## [v0.4.4](https://github.com/ARMmbed/ble-nrf51822/tree/v0.4.4) (2015-08-07)
+[Full Changelog](https://github.com/ARMmbed/ble-nrf51822/compare/v0.4.3...v0.4.4)
+
+**Closed issues:**
+
+- nrf51822 hangs after calling sd\_flash\_page\_erase\(\) [\#35](https://github.com/ARMmbed/ble-nrf51822/issues/35)
+- nRF5xn::getVersion return \(Unknown\) with version 8 soft device [\#29](https://github.com/ARMmbed/ble-nrf51822/issues/29)
+
+**Merged pull requests:**
+
+- Changed Gap:: to GapAdvertisingParams:: because of change in BLE [\#34](https://github.com/ARMmbed/ble-nrf51822/pull/34) ([jslater8](https://github.com/jslater8))
+- Select the clock source dynamically on SoftDevice initialisation [\#32](https://github.com/ARMmbed/ble-nrf51822/pull/32) ([jpbrucker](https://github.com/jpbrucker))
+- Add S110 SoftDevice compatibility [\#28](https://github.com/ARMmbed/ble-nrf51822/pull/28) ([jpbrucker](https://github.com/jpbrucker))
+
+## [v0.4.3](https://github.com/ARMmbed/ble-nrf51822/tree/v0.4.3) (2015-07-22)
+**Closed issues:**
+
+- Target polling failed [\#24](https://github.com/ARMmbed/ble-nrf51822/issues/24)
+- support  handling of HVX Events \(notifications and indications\). [\#22](https://github.com/ARMmbed/ble-nrf51822/issues/22)
+- provide an implementation for GattServer::areUpdatesEnabled\(\) [\#21](https://github.com/ARMmbed/ble-nrf51822/issues/21)
+- getValueHandle\(\) returns characteristicIndex instead of attribute-handle [\#20](https://github.com/ARMmbed/ble-nrf51822/issues/20)
+- Clash With Definition And Enum Naming [\#16](https://github.com/ARMmbed/ble-nrf51822/issues/16)
+- Errors in GCC build [\#14](https://github.com/ARMmbed/ble-nrf51822/issues/14)
+- bring s110 support back [\#10](https://github.com/ARMmbed/ble-nrf51822/issues/10)
+- Allow adding a User Description descriptor to a GattCharacteristic. [\#9](https://github.com/ARMmbed/ble-nrf51822/issues/9)
+- device\_manager\_peripheral.c includes app\_trace.h [\#7](https://github.com/ARMmbed/ble-nrf51822/issues/7)
+- linking esb\_gcc.a \(nrf51822 enhanced shock burst\) with mbed [\#5](https://github.com/ARMmbed/ble-nrf51822/issues/5)
+- The app\_timer usage may conflict [\#2](https://github.com/ARMmbed/ble-nrf51822/issues/2)
+- Nordic License [\#1](https://github.com/ARMmbed/ble-nrf51822/issues/1)
+
+**Merged pull requests:**
+
+- Develop [\#25](https://github.com/ARMmbed/ble-nrf51822/pull/25) ([zoujixing](https://github.com/zoujixing))
+- Remove unnecessary 'compiler\_abstraction.h' to get rid of duplicate '… [\#23](https://github.com/ARMmbed/ble-nrf51822/pull/23) ([adfernandes](https://github.com/adfernandes))
+- restructure for minimal yotta compatibility [\#15](https://github.com/ARMmbed/ble-nrf51822/pull/15) ([autopulated](https://github.com/autopulated))
+- Fix various GCC compilation issues. [\#12](https://github.com/ARMmbed/ble-nrf51822/pull/12) ([adfernandes](https://github.com/adfernandes))
+- Fix for GCC lost in SDK v8.0 update [\#8](https://github.com/ARMmbed/ble-nrf51822/pull/8) ([rosterloh](https://github.com/rosterloh))
+- new target DELTA\_DFCM\_NNN40 with nrf51822 chip, config internal RC crystal. [\#6](https://github.com/ARMmbed/ble-nrf51822/pull/6) ([Marcomissyou](https://github.com/Marcomissyou))
+- Updated return value for nRF51GattServer::updateValue. Will now report w... [\#4](https://github.com/ARMmbed/ble-nrf51822/pull/4) ([marcuschangarm](https://github.com/marcuschangarm))
+- Added optional data and length fields to the return struct for authorize... [\#3](https://github.com/ARMmbed/ble-nrf51822/pull/3) ([marcuschangarm](https://github.com/marcuschangarm))
+
+
+
+\* *This Change Log was automatically generated by [github_changelog_generator](https://github.com/skywinder/Github-Changelog-Generator)*
\ No newline at end of file
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/LICENSE b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/LICENSE
new file mode 100644
index 0000000000..60744edab2
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/LICENSE
@@ -0,0 +1,6 @@
+This module contains softdevice which comes with The Nordic Softdevice License Agreement,
+a BSD-like licence for binary distributions, offered by Nordic for use in mbed. Some
+other files come from the mbed SDK, and are licensed under Apache-2.0. Unless
+specifically indicated otherwise in a file, files are licensed under the
+Apache 2.0 license, as can be found in: apache-2.0.txt. The Nordic Semiconductor Softdevice
+License Agreement can be found in softdevice_nrf51822_licence_agreement.txt.
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/apache-2.0.txt b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/apache-2.0.txt
new file mode 100644
index 0000000000..9327527edd
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/apache-2.0.txt
@@ -0,0 +1,13 @@
+Copyright (c) 2015 ARM Limited
+
+Licensed under the Apache License, Version 2.0 (the "License");
+you may not use this file except in compliance with the License.
+You may obtain a copy of the License at
+
+    http://www.apache.org/licenses/LICENSE-2.0
+
+Unless required by applicable law or agreed to in writing, software
+distributed under the License is distributed on an "AS IS" BASIS,
+WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+See the License for the specific language governing permissions and
+limitations under the License.
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/s110_nrf51822_8.0.0_bootloader.hex b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/s110_nrf51822_8.0.0_bootloader.hex
new file mode 100644
index 0000000000..c9c68846b9
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/s110_nrf51822_8.0.0_bootloader.hex
@@ -0,0 +1,463 @@
+:020000040003F7
+:20C00000983C002005DD030017DD030019DD03000000000000000000000000000000000057
+:20C0200000000000000000000000000069C1030000000000000000001DDD03001FDD0300D7
+:20C0400021DD030021DD030021DD030021DD030021DD03000000000021DD030021DD0300D9
+:20C0600021DD030021DD030021DD030021DD030021DD030021DD030021DD030021DD0300B8
+:20C0800021DD030057D8030021DD030021DD03006DD8030021DD03004DF4030021DD0300DD
+:20C0A00021DD030021DD03000000000000000000000000000000000000000000000000007E
+:20C0C00000F002F800F040F80CA030C8083824182D18A246671EAB4654465D46AC4201D18E
+:20C0E00000F032F87E460F3E0FCCB6460126334200D0FB1AA246AB463343184710370000C8
+:20C1000030370000103A02D378C878C1FAD8520701D330C830C101D504680C6070470000D3
+:20C120000023002400250026103A01D378C1FBD8520700D330C100D50B6070471FB5C04655
+:20C14000C0461FBD10B510BD03F0E3FA1146FFF7F5FF00F0D3F803F0FBFA03B4FFF7F2FF19
+:20C1600003BC03F0FFFA00000648704502D1EFF3098101E0EFF30881886902380078024A97
+:20C1800010470000FDFFFFFF39D50300401E00BF00BF00BF00BF00BF00BF00BF00BF00BF28
+:20C1A00000BF00BF00BFF1D170470000401E00BF00BF00BF00BF00BF00BF00BF00BF00BFB4
+:20C1C00000BF00BF00BFF1D170470000401E00BF00BF00BF00BF00BF00BF00BF00BF00BF94
+:20C1E00000BF00BF00BFF1D170470000056885F3088846680A4AEFF305839A42304602D183
+:20C20000084CA6463047074C064D0646064FF0B4034C034D024E024FF0B404480047000005
+:20C2200000000000FFFFFFFF00000021F9FFFFFF70B505460C46164602E00FCC0FC5103EEE
+:20C24000102EFAD2082E02D303CC03C5083E042E07D301CC01C5361F03E021782970641C63
+:20C260006D1C761EF9D270BD0A4610B50146664803F064F810BD10B502F078FC10BD10B5C6
+:20C28000624C86B01ECC03946C460EC4002807D0684618DF002803D00022114603F04EF864
+:20C2A0000F20800313DF002803D00022114603F045F8574B48225749092003F0A3F80028AB
+:20C2C00003D00022114603F039F800200490059001206946087404A860DF002803D0002251
+:20C2E000114603F02BF84C4803F0A8F8002803D00022114603F022F806B010BD08B547485A
+:20C30000C169B12943D0002445480F2140698903884204D000221146104603F00FF8012068
+:20C320000007006901218902884204D000221146104603F003F83B4800903B4B05220321A1
+:20C34000002001F0BAFA002803D00022114602F0F5FF00F067FC00F0AAFC012500281AD09D
+:20C3600000F0B4FC002803D00022114602F0E6FF20466840FFF783FF00F038F800F0CCFC74
+:20C3800000280ED00022114602F0D8FF09E001240021C161B8E720466840FFF770FF00F002
+:20C3A00025F803252D03002C04D1A86800F090FB002807D100F047FC002803D000221146D5
+:20C3C00002F0BCFFA86800F083FB002806D000F06EFC002802D1A86800F041FCBFF34F8F12
+:20C3E00013491248C860BFF34F8FFEE7094A10B548321421082002F00BFF002803D00022E2
+:20C40000114602F09BFF10BDEFBEADDE8CF703006BF30300342B002077C20300000500404D
+:20C4200000100010EFDC0300F42800200400FA0500ED00E070B5FC4C1E46A06815460229A3
+:20C4400002D0042916D108E0052813D1A369002B10D03246294604200BE002280AD1F348B0
+:20C46000406880470320A060A369002B02D0324629469847280003D00022114602F05EFF98
+:20C4800070BD4CB5E84E0120307005200195009400F058FB4CBD10B5E34C2078002801D057
+:20C4A000082010BD206901F0F4FA002803D00022114602F043FF0F2100228904206901F01E
+:20C4C000ABFA040003D00022114602F037FF204610BDD54910B5D448243141610221816012
+:20C4E000C168243002F059FD002803D00022114602F024FF10BDCC4910B5CB481C31416145
+:20C50000022181600320000380680F218903081A4108C5481C3002F040FD002803D000223D
+:20C52000114602F00BFF10BD704700B589B01822BF4902A8FFF77CFE06980799009001917A
+:20C5400002A80FC800F0FEFA09B000BD00B5B64987B049886A461181032109038968069146
+:20C56000B249012050394A6803928A680492C9680591069A0091019202A90EC900F0E2FA6E
+:20C58000002007B000BD30B5A84CA748503C89B02430E16802F001FD002803D00022114679
+:20C5A00002F0CCFEA048E2681C3041680023083002F0C3FC050012D1182102A802F0E6FFEA
+:20C5C00000209949029049886A469181E1680691079A0091019203A90EC900F0B3FA284601
+:20C5E00009B030BD00B5904987B049886A4611818E49032050394A6803928A680492C9683A
+:20C600000591069A0091019202A90EC900F09AFA0020B6E73EB5864A6B46183207CA07C3A4
+:20C62000814D00246C7029466C802431684602F068FC002801D0AC603EBD03207A4900038F
+:20C6400080682431486024390A46526ACA610F218903091A490840187349764A1C31486068
+:20C6600071480021103001F07BF9002803D00022114602F063FE0F2100228904286901F013
+:20C68000CBF9002803D00022114602F057FE01206C60A86000203EBD63498861704770B59A
+:20C6A000426862481468536891685038D26804604360C26081600078440701D5840705D130
+:20C6C0009C0703D18C0701D1940701D0062070BD5B189A18544D0F239B02EA60994213D81A
+:20C6E0005549564B514CC60709D08868181A90420AD3534820605348606053480FE08968F6
+:20C70000591A4908914201D20C2070BD4F4921604F496160800701D54E4800E04E48A0607B
+:20C72000A868012802D00826304670BDFFF7B3FE0600FAD12168E8688847F5E770B50500F7
+:20C7400004D0287A800703D0102070BD0E2070BD354CA068032805D0042801D0052803D0CB
+:20C76000082070BD0520A0606868E168860060688019884204D90020C04360600C2070BD5C
+:20C78000FFF789FE0028FAD1A96832466368606902F0D3FB0028F2D1616889196160E268EB
+:20C7A0009142ECD0092070BD10B51F4C08206168002900D010BDA1680429FBD11B4861786F
+:20C7C000403802F021FC002802D00021617010BD0521A16010BDF8B5134C0746A068032899
+:20C7E00004D0042804D008252846F8BD0420A0606068002801D00820F8BDFFF74CFE05000E
+:20C80000FAD17868860060788119402901D90920F8BD064AB968403A1018324602F057FE82
+:20C82000607880196070DFE7002800201C2D00209CF7030083C403000030000000C003006D
+:20C84000D3C403002BC503004DC50300F7C4030029C50300E5C5030087C5030010B5894CF1
+:20C86000A068052813D1E168606888420FD10620A060FFF710FE002808D16069E1684068FF
+:20C8800002F0FCFB002801D10721A16010BD082010BD10B57B488168072901D0082010BD63
+:20C8A000006901F0F6F8002803D00022114602F045FD75488068804710BD1CB506200195C2
+:20C8C000009400F03FF91CBDF8B51C4617460D46064600F0C1F8002817D001200003854215
+:20C8E00007D92346291B301B1A46FFF7EDFF00280BD13A462946304600F0B9F8002804D117
+:20C900003A462946304600F0A7F8F8BDF0B589B0684600F015FA049800282AD001210903F7
+:20C92000079A4018904226D9501A45081046049A0C468718024668001618001908900320DF
+:20C9400000038068049988420DD261190846042200F08DF800280CD121460422084600F073
+:20C9600086F8002805D1BA1B2B4630460899FFF7ABFF09B0F0BD049A079800F078F8F8E75C
+:20C9800000B58DB004A800F0DBF9099800280DD0089800280CD008990B984018019000219D
+:20C9A0000998009180080290684618DF0DB000BD0320000380680F218903091A4908ECE7FB
+:20C9C00000B58DB004A800F0BBF909980028EDD00F210898890300280CD0089A0B98019158
+:20C9E0008018029003220998009280080390684618DFDBE70320000380680A1A5208EEE7D2
+:20CA000030B591B0684600F09BF90498002814D001210903079A4018904214D9501A43087B
+:20CA20001046049A5C0082180019611803242403A468049DAC4202D20E2011B030BD121AB5
+:20CA4000FFF742FFF9E703200CAB07C3049880080F900CA818DFF0E71FB5032301909008B3
+:20CA6000039000930291684618DF04B010BD1FB5012301909008039000930291684618DF58
+:20CA8000F3E70000002800201C2D002010B5BB480368012B02D1022900D10160100003D099
+:20CAA0000022114602F04AFC10BD10B5B34C48DF002803D00022114602F040FC02F0FCFB82
+:20CAC0002068022803D0032801D00428EFD110BD38B50068401C19D00024684600F058F96F
+:20CAE00000980168012910D1818800290AD0C168032000038068002202F0CEFA0099898861
+:20CB0000814201D1012400E00024204638BD10B504469A482021001D02F0B9F9002803D00E
+:20CB20000022114602F00AFC9448002320222146001D02F01BF9002803D00022114602F053
+:20CB4000FDFB10BD0FB4F8B5684600F021F96846818B069D0122894CFF238948002D13D090
+:20CB6000012D17D0032D2BD00021022D37D02A46052D46D0042D4ED0062A01D10420206071
+:20CB8000F8BC08BC04B0184781800A9983600260C16010E08180099D089949190A9D49195D
+:20CBA000C160A52183600160089901610999856141610B99C16122607148FFF7A8FFDFE7B9
+:20CBC00000990B6803608B888380C968C160AA21816008990161099941610A990BE0009D60
+:20CBE0002E68A52E09D00660AE888680ED68C5600161836041618161DDE781800360C160C5
+:20CC0000F6E700F085F9002803D00022114602F095FB0320B3E781800360C1600099896807
+:20CC20008160C9E70EB557480090202001900120029002F001F8002804D150496846091D98
+:20CC400002F023F80EBD10B5FFF7E4FC002805D100F02FFB0446FFF728FF204610BD70B58A
+:20CC600011DF002803D00022114602F067FB464900200B68444C012180340A4682401A4206
+:20CC800004D0C506ED0E0A46AA402260401C2028F3D303242403A06813DF002803D000226F
+:20CCA000114602F04BFBA06802F0F2F970BD08B5684600F06DF800980168A52904D0806888
+:20CCC000AA2801D0002008BD012008BD10B5FFF797FE002803D1FFF773FE00281BD064209C
+:20CCE00001F0F2FDFFF712FE002803D00022114602F024FBFFF784FE002803D000221146DD
+:20CD000002F01CFBFFF73CFE040003D00022114602F014FB204610BD00B589B018221B49CA
+:20CD200002A8FFF785FA069807990090019102A80FC8FFF707FFFFF7B8FE002009B000BDB5
+:20CD400010B50E4988B0044600232022091D684602F04FF80098206068468088A08003983A
+:20CD6000E0600298A06004982061059860610698A0610798E06108B010BD00002C280020E6
+:20CD8000282D00208DCA030000E100E0C0F70300014901607047000000FC030008280CD0DC
+:20CDA00004DC002807D006280FD108E00B280AD00C280AD105E001207047022070470320C9
+:20CDC000704704207047042901D0062070470520704770B515460A46032823D0042820D1FF
+:20CDE000FE4C002906D0E088FD49884219D0132176DF10E0284602F0A3F9002803D00022F7
+:20CE0000114602F09BFAE069A8420AD101220321F44801F003F8002803D00022114602F051
+:20CE20008DFA70BD01211046FFF7B8FF02460121EEE7F0B5054608790E4685B081070CD07C
+:20CE400003221146284600F0E9FF002803D00022114602F073FA05B0F0BDE04900901831D9
+:20CE600002F047F9010011D1DC4CB168009AA06902F02DFB009802F097F9010006D1204647
+:20CE80006946183002F09CF9010003D0284600F0AFFAE0E704200190009880080290A06902
+:20CEA000039001A8FFF74AFC07000BD0092F10D0A06902F045F9010002D0284600F098FA04
+:20CEC0003946E3E73079616940186061A069E061C1E7307961694118616160780028BAD073
+:20CEE0006089401E0004000C6081B4D1284601F0E9F8002803D00022114602F01FFA20890D
+:20CF00006081A8E710B50022114602F017FA10BD10B5B24C01202070E088B149884208D01B
+:20CF2000132176DF002810D00022114602F006FA0BE0A078002808D074DF002803D0002282
+:20CF4000114602F0FBF90020A07001F034FC002803D00022114602F0F1F9002010BD70B5E1
+:20CF60000D68044601209D4A2B0002F002FC0A2B3043061320575C466012FFF76FFC0421FD
+:20CF8000FFF70CFF024604212EE00022114602F0D5F970BDFFF7BCFF002803D0002211468A
+:20CFA00002F0CCF9FFF775FC002808D170BDFFF7AFFF002803D00022114602F0BFF9FFF76D
+:20CFC0007CFC70BD106188680078107170BD02201061886800780128F8D1FFF7E5FB02213F
+:20CFE000FFF7DCFE02460221204600F017FF0028CBD170BD0320106170BD12692046012ACC
+:20D0000006D0022A07D0032AF6D1FFF712FF70BD00F001FA70BD00F03BFA70BD50708888D5
+:20D020001081508170BD00205070108170BD2046516901F010F8DAE710B5044669488EB0EB
+:20D0400081796846817068490180342101A802F09DFA022001900021684641728472012131
+:20D0600001820590002101A801F03FFA002803D00022114602F062F90EB010BDF0B5574C10
+:20D080008BB0A07800283AD156481821183802F07DFA2046534CC078183C00250126002875
+:20D0A00037D02746483700950195029510226946F81D039502F0DEF9002822D0F81D08909D
+:20D0C00009976846067509A804906846067708A806900420FFF7B0FF25700220207204A813
+:20D0E000E060282020823F486582183873DF002803D00022114602F021F9384886700BB045
+:20D10000F0BD0520FFF798FF2670676025722582E9E70620FFF790FF257065602572E0E7E2
+:20D1200070B52E4C01880022E588A6B017290AD01EDC11293FD008DC022977D0102902D123
+:20D140008088E080A27026B070BD264C303426461836132951D01429F5D1C289638D002106
+:20D160009A4200D1314600238088E21D82DF1BE0512970D00EDC18296CD01929E3D18079F5
+:20D180000028E0D1A270E068401EE0604FD0FFF775FFD8E7522976D05529D4D18079002871
+:20D1A000D1D11321284676DF0028CCD00022114602F0C4F8C7E78020694688803220E06054
+:20D1C000012301AA06A92846AADF002803D00022114602F0B3F82078002807E038280020A2
+:20D1E000FFFF0000602D00203015000001D1FFF745FF0020C043E080A5E70722C14910A839
+:20D2000002F065F91022E11D0CA802F060F91C22314612A802F05BF90CA80A9012A8099039
+:20D2200006ABB94A852128467FDFBDE70DE01822B64906A8FEF7FCFF0A980B9900900191F8
+:20D2400006A80FC8FFF77EFC7DE70021284667DFAAE700E017E0817900299AD0807A042885
+:20D2600003D0062801D0052893D1022909D0012069460872FF208330888102A92846A8DF82
+:20D2800092E70220F4E700F08DF88DE710B5044601F0C2FA9B482146303800F09AFE2046D3
+:20D2A000FFF73EFF10BD10B50022114602F046F810BD30B5944D87B00024203D2C7094483D
+:20D2C0002C6102F0B3F800286AD19248FFF7E4F901F000FF002863D18A4800F059F900288C
+:20D2E00001D10120E87011206946087207228AA102A87CDF002803D00022114602F01EF8B4
+:20D3000000940C2168460194018018214180FF2184809131C1807ADF002803D0002211469A
+:20D3200002F00CF804206946009408807C4801907C4802907348303800F00BFE002803D046
+:20D340000022114601F0FAFF1C21684602F01EF9754801900120800302900094032168468C
+:20D360000173C4810474714806900594684601F0FEF9002803D00022114601F0DFFF624910
+:20D38000E12208784008400010400C30DF22104008700720487010208870FFF76FFE0020A3
+:20D3A00007B030BD70B5584C614D203CE088A84201D1082070BDE178002914D05149012359
+:20D3C00008223431A9DF0028F4D12A460C21E088A7DF5849884204D0082802D0891C88420E
+:20D3E000E8D1002070BD00231A461946A9DF70BD10B50A46044603211046FFF7CFFC0246AE
+:20D400000321204600F00AFD002803D00022114601F094FF10BD30B5054687B000200090AF
+:20D4200001900290039038486A46203800791070364A0C3A1068926804906846069205900E
+:20D4400008790C2806D003221BE00022114601F075FFA5E78C68204600F049F80190201D5E
+:20D4600000F045F802902046083000F040F8039004A8FFF714F9002892D00121FFF78EFCB9
+:20D4800002460121284600F0C9FC0028DDD187E7FEB50446087982070ED08207920F042385
+:20D4A0009B1A0022154604E08E683554401CC0B2521C9A42F8D30871012000908868029048
+:20D4C0000879800801906846FFF785F900280DD00221FFF763FC02460221204600F09EFCB8
+:20D4E000002803D00022114601F028FFFEBD10B5044602F04DF80002E178000A09060843E0
+:20D5000010BD0000902D002058280020E4F703008DD20300D3CD0300446675546172670031
+:20D520005FCF0300A7D20300CD0C000005CF0300FFFF00000230000010B50C46002802D04D
+:20D540000120086010BD2168002911D01C48421A814212D03C2A0DD23C303C3101220B78B9
+:20D5600003701346491E401E521C3C2BF7D904E00E200BE03C2201F0AAFF00223C211048A9
+:20D5800001F08AFD0E49891E08800020206010BD70B5054600223C21094801F07DFD084C21
+:20D5A000A41E2188884201D00B2070BD3C220449284601F08CFF2088401C2080002070BD87
+:20D5C000823F00208307FF22DB0E9A408907090E994000280BDA0007000F08388308FA484C
+:20D5E0009B001B18D86990430843D86170478308F6489B001B1818689043084318607047AA
+:20D6000070B50124F24960040860F24940108860F04940398860F04D6C602F20FEF7B6FDAC
+:20D62000AC60EE4D00242F206C61FEF7AFFD2C7170BDF0B5E94F2821BC6841430D19396962
+:20D640004A1C09D028224A431619AB68B268934204D8D21AB26069623861F0BD0A4602E066
+:20D660000A46796A9B1B4E1C0BD028264E433719BE689E42F4D328264E433619B768FF1A1A
+:20D68000B760AB60696228214A4311194862F0BD70B5D24C2269A5681346114606E0814212
+:20D6A00007D00A46282671434919496A4E1CF6D170BD002EFCD08A420CD1282043435819EC
+:20D6C000406A2061401C05D1C34B01209860002363616071282041434819282381685A4310
+:20D6E000406A52195062421CE2D028225043401982685118816070BDF8B5B84C2569681CF9
+:20D7000035D0B748002640686169401A07023F0A19E028204543A0682A189068B84214D8D0
+:20D72000A3693F1A8619556A002B09D0116AD0699847002807D00022114601F0FFFD02E048
+:20D74000D169106A8847681CE3D1A178E078814206D1401CC0B2E070022801D10020E07079
+:20D760009E490006800D1C310E5000F0BAF9F8BDF8B50446994800270169009146785CE038
+:20D780009648F100C2688D1851E0601C07D0934A28209268604321468018446A24E0287854
+:20D7A000182141436A68401CC0B252182870A978884200D12F70894B516828209B6848434C
+:20D7C000C0181368012B34D1037E002B31D19368C360D368036113694361526902627F4A52
+:20D7E0005279002A00D0C7607C4BC2685B6996469C46D31A1A027B4B120A9A4202D20369C3
+:20D80000D21808E0724663469A1A12020369120A934202D99A1A826000E08760C76001222E
+:20D8200007610276921E42620846FFF702FF601CABD1287869788842A7D13046761EF6B202
+:20D8400000289DD1654801690098814201D00120F8BD0020F8BD644900200860486088607F
+:20D86000C860614940390860486045E7FEB50020C0435A4D02906869019068462E6900F07B
+:20D8800035F9074600F04FF90446002F08D002AA0199009800F08FF90298FFF769FF06E050
+:20D8A0000298FFF765FF002801D1002C02D0304600F0AAF900206871FEBDFFB59807002448
+:20D8C00081B01E4615460F4600280BD1002E09D0FFF796FE41490A9888610F703246002042
+:20D8E0008E6008E0072005B0F0BD28234343D4509B181C76401CB842F7DB28204743BB19C1
+:20D90000032048700F461846CB6019461830002218232E465E43D3005B181C705C709D708A
+:20D9200058603018521C032AF5DB0020C0433861BC70FC7001242D482405046003211420A9
+:20D94000FFF740FE224880380460254C0198A06003211120FFF736FE606878610020C2E71A
+:20D9600070B51E4CA568002D06D0002A06D0002804D00023247809E0082070BD072070BDBB
+:20D9800028265E43AE59002E04D05B1CA342F7DB042070BD282401265C432E516419E261BF
+:20D9A00061600360002070BD07494868C005C00D2CD010381CD50207120F083A9208920097
+:20D9C0005118C96919E0000000ED00E000E400E080E100E040130140001001406028002054
+:20D9E00000150140FFFF7F004011014080E200E08108B14A8900891809688007C00EC1400B
+:20DA00000806800F012803D0032803D0022070470020704701207047FEB50446A74817469E
+:20DA200082680D46002A0CD001788C4201D2052D01D20720FEBD2146282359435358012B7D
+:20DA400001D00820FEBD8818406801281DD00026FFF7AAFFC00099490190C9684018694684
+:20DA600000F018F9002812D0012144600160944949680830E2C091490198C9684118009877
+:20DA8000487000F02EF80020FEBD2E46E0E70420FEBDF8B5894D0446A868002809D0297844
+:20DAA0008C4201D30720F8BD282161434058012801D00820F8BDFFF777FFC600E86869465B
+:20DAC000301800F0E7F8002809D0022112C0E86831180098487000F004F80020F8BD04206B
+:20DAE000F8BD0120774900050860704710B5734900238A78CC78A24212D0521CD2B28A70D0
+:20DB0000022A00D18B708A786C4B92001C339A580260486910180002000A4861012010BDA3
+:20DB20000360002010BDF8B5644801690091457833E06248E900C0680E1834782AE01820A2
+:20DB400060437168641C0818B178E4B2A14200D100240168022902D003291BD113E0574A00
+:20DB600040682821926841438F18397E002911D0FFF78EFD002038760CE028277843C018B1
+:20DB80000276406A03E04D4900228B680869471CF3D108617078A042D1D128466D1EEDB2D0
+:20DBA0000028C6D1454801690098814201D00120F8BD0020F8BDF7B5404C0025A7682369E0
+:20DBC0001EE028215943C9198E68864202D9301A886017E0801B751900268E600E764E6946
+:20DBE0009C464B6AB646002E0AD0019E76193602360ACE6076460E6116684E626146116045
+:20DC0000591CDED12361FEBDF8B52C4801694A1C3DD028225143826889188E6828494C681F
+:20DC200047690079E11B0D022D0AED1C002815D10120254A00045060234A403A506021491D
+:20DC4000400080310860214908602149012008602F20FEF79BFA194901200871B54200D208
+:20DC60003546E81900021649000A4031086014494968001B091B0902090A0002C91C000A88
+:20DC8000814203D901200F4940040860F8BDFFF7B7FCF8BD42788378521C934200D10022C2
+:20DCA0000378934201D1002070470A6041684078182250430818704700E400E06028002090
+:20DCC0000015014000E200E04013014000E100E00010014010B50446082904D000221146F9
+:20DCE000104601F02BFB21686068884710BD1CB501910090024A0821684601F09DFA1CBD53
+:20DD0000D5DC03000A48026803210A4302600948804709480047FEE7FEE7FEE7FEE7FEE797
+:20DD2000FEE7000005480649064A074B70470000240500404DDD0300C1C003009830002007
+:20DD4000983C00209834002098340020F8B500F035F82B4E002804D02A4870602A49F01300
+:20DD600088612A480124018CC9B201290DD1818C09070AD1018D0906090F042905D1808D56
+:20DD80000006000F01D1224884600027B461214D6F60A8058460686800280ED1C820FEF790
+:20DDA00005FA1D487F1C8742F5D30020B06101208007846068680028FCD0F8BD1348018CB5
+:20DDC000C9B2012917D1818C090714D1018D09060A0F03D1828D1206120F0ED0090F0129C2
+:20DDE00003D1828D1206120F07D0032903D1808D0006000F01D0002070470120704700008E
+:20DE000000050040DFFF07C0006C0040C00F00F000060040000100408813000030B585B071
+:20DE2000002822D00388FE4CA34220D0FD4B1B78002B1CD0FB4B10255B1C1D7059700024C0
+:20DE400001259A70032269460A820094019402940394028A0A808D708C8004A902910393E7
+:20DE600000886946A6DF05B030BD0E20FBE70820F9E7F0B58BB0044602276846077300268B
+:20DE800009968784C68408A80A900D46A18A208809AAA5DF002804D0E16A00291AD08847BE
+:20DEA00018E06846008CC007C00F13D068460682208803A9A8DF002813D1A97E28461B30BA
+:20DEC00001220B0001F055FC09430F1B202224263E284300FF20FE3069460882208803A94D
+:20DEE000A8DF0BB0F0BD00960AE0062219E069460A71029022E0204690470020F1E700920D
+:20DF00002B8B022BF3D2F0E700971DE003201AE0042018E0052016E0298B032905D20322BE
+:20DF200008212046FFF77AFFDBE741780278080210436946888003D006200090A26ADAE784
+:20DF40000720FAE7092000906946A26AD3E70322E7E730B585B00D46040038D0002D36D0EC
+:20DF60006868002833D00020C043AF4B20800FCB049301AB07C3AD4869460880891C01A888
+:20DF800063DF002822D1221D69460120A0DF00281CD168468078A071204600F0CEF8002886
+:20DFA00014D1204600F055F900280FD12946204600F002F9002809D16868A062A868002804
+:20DFC00000D0E06297490120087000204BE70E2049E73EB5002828D0002926D0826A002ABE
+:20DFE00023D00A88102A21D0112A30D0502A1FD0512A1AD104460846891D0A78022A14D196
+:20E000004A88238A9A4210D1807A04280DD006280BD0052809D0891C2046FFF72AFF002860
+:20E0200003D0E16A002900D088473EBD898810E0CA8803899A42F8D1082200928A7F6B4605
+:20E040001A7120310291826A694690473EBD0021C94301803EBDF0B585B00A4605002DD00F
+:20E0600028886F4988422BD06E480078002827D06C4C1020641C2070072060700127A770F8
+:20E080000321684601820026E11C104600F04CF801466846008A0918684601820096019680
+:20E0A00002960396298A01808770868004A80394029028886946A6DF05B0F0BD0E20FBE7D3
+:20E0C0000820F9E7F0B585B00A46050028D028885349884226D053480078002822D0514C3B
+:20E0E0001120641C20700127684607820026611C104600F019F801466846008A0918684638
+:20E1000001820096019602960396298A01808770868004A80394029028886946A6DFCBE782
+:20E120000E20C9E70820C7E70870020A4A70020C8A70000EC8700420704730B58FB0054655
+:20E140001C21684601F022FA694608780421084369460870002401940394049405940694E6
+:20E16000A87908A9887031486946801C0884601C00070794000F0C77103048778A7FF920B4
+:20E180000240921CE7200240012002438A77142109A801F0FBF908A8099007A80A906946D3
+:20E1A0008C851420CC8508860D942B46A888083309AAA2DF0FB030BDF0B58FB00F4605465A
+:20E1C0001C21684601F0E2F968460178022631430170002401940394049405940694A97917
+:20E1E00008A8817011496846091D0184601C0107090F103168460794017700200146684618
+:20E200004177817FF9200140891CE72001400120014368468177142109A801F0B7F907E086
+:20E22000FFFF000088280020FCF703003015000008A8099007A80A9068468685C4850686B5
+:20E240000D972B46A888203309AA6946A2DF0FB0F0BD30B58FB005461C21684601F096F9FD
+:20E2600069460878082108431022104369460870002401940394049405940694A87908A962
+:20E280008870144869460884601C00070794000F0C7710304877887FF9210840801CF72123
+:20E2A000084010430121084369468877142109A801F06CF908A8099007A80A9069468C851A
+:20E2C0001720CC8508860D942B46A888103309AAA2DF6FE731150000FFB583B0074600207F
+:20E2E0000C9C8646267805463AE07868A90041180A88684682804988C1800022694601A8F7
+:20E3000065DF002810D1684601780598814226D17046002801D0002200E002222078891824
+:20E3200041181F2902D90C2007B0F0BD7146002908D1401CC0B2411C069B049A21701A54AF
+:20E3400001208646217806980A18694601A865DF0028E9D1694620780978401820706D1CC0
+:20E360003888A842C1DC7046002804D020780699801B401E88550020D6E7F8B51546069C10
+:20E380001E46074602220094FFF7A6FF002806D133461022294638460094FFF79DFFF8BD07
+:20E3A000F7B582B000260546167000681446002805D02846039900F0CAF8060008D168794D
+:20E3C00000281ED02078039F001D1F2802D90C2005B0F0BD684679DF0028F9D1217803226A
+:20E3E000481C20707A5421781922481C20707A542078C1196846008800F0A4F821784018A0
+:20E400002070A8790223002810D02078039A411C2170135420780399471C012227700A54E5
+:20E420002078AA79471C039927700A54A868002815D00021415620788C460246C01C03992E
+:20E440001F28C4D8501C20708B5422780A23501C20708B5420786246431C23700A54A8899B
+:20E46000002809D028460094062202210C30039BFFF783FF0600ABD1A88A002809D02846D9
+:20E480000094072203211430039BFFF776FF06009ED1A88B002809D0284600941522142137
+:20E4A0001C30039BFFF769FF060091D1686A002805D02246039900F07FF8060088D1A86A01
+:20E4C000002805D02246039900F0B5F8060084D13020405D002806D022462846039900F0F6
+:20E4E000DCF80600C7D1304672E770B50C4692B000216A46117007251171002809D0817927
+:20E5000049070CD502A9FFF74BFF002808D102AE00E00026002C0ED0A079002802D028469D
+:20E5200012B070BD01AA0AA92046FFF739FF0028F6D10AAA00E0002268460379017830463C
+:20E5400072DFEDE70870000A487002207047F8B514780746A01C15460E461F2803D83879BF
+:20E56000801C1F2801D90C20F8BD1D20001B80B26946864608803019801C7DDF0028F3D143
+:20E580003868022805D168460088704501D8092107E038790821002801D0704501D96846F6
+:20E5A0000088421C3255641CE2B2B1542978801C081828700020F8BDF8B50D461178064636
+:20E5C000881D14461F2801D90C20F8BD33880720062BFAD31927FF01BB4202D94D4A9342D6
+:20E5E000F3D17288062AF0D3BA4202D9494FBA42EBD1484FBB4203D0BA4201D09342E4D87E
+:20E60000481C052220706A5420781222411C21702A54207841193088FFF794FF21784018C5
+:20E62000C0B2207041197088FFF78CFF2178401820700020F8BD70B5054600790E46801CD6
+:20E640001446C0B21178821C8A181F2A01D90C2070BD0A46491C401C2170B0542078FF224A
+:20E66000411C21703254207881192888FFF76AFF21784018C0B22070AA88002A09D0A968AC
+:20E68000002908D0801900F022FF2078297940182070002070BD072070BDF7B582B0029894
+:20E6A0001446C06A0F46002832D0029800252030009028E00298C16A0C2068430E18217855
+:20E6C00030794A1CC01C2270785421781622481C20707A542078C1193088FFF733FF217873
+:20E6E0004018C0B22070B288002A09D0B16800290ED0C01900F0EBFE207831794018207087
+:20E700006D1C0098EDB2007CA842D3D800205FE607205DE6FFFF000038B56749674A48883D
+:20E7200090420FD04A78664C521CD2B24A70237B934208D3083175DF002803D0A1690029FF
+:20E7400000D0884738BD00254D70217C002907D03B2176DF002803D0A169002900D0884728
+:20E7600061690029EED068460095884738BD70B5054601461C225248FDF75AFD4E4C002647
+:20E7800026702968002907D00822A01800F09FFE204608307ADF02E0474808307BDF0028C1
+:20E7A00008D1401E608044486670464A0021001DFFF7D6F870BD10B53F484068FFF769F9D5
+:20E7C00010BDF8B53C48103000F069F800263A4D3B4C002806D06169002919D001200090EB
+:20E7E000684614E02878002804D0616900290FD00096F5E7687800280CD0A16800226868B8
+:20E80000FFF70AF9002803D0A169002900D088472E70F8BD6168F1E7F8B5294C028800276B
+:20E82000254DE689102A18D029464968112A21D0122A2DD0502A0FD1801D0288B2420BD1FF
+:20E84000028B022A08D1C27E837E10021843C007C00F13D0FFF7B5FFF8BD81886980014667
+:20E86000154808221631103000F031FE6F70002EF0D0F8BD0020C04368806F700846FFF7BB
+:20E8800008F90028F5D0A1690029F2D08847F8BD811D09480822103000F019FEDAE7418827
+:20E8A000054808300288914204D34088814201D8012070470020704790280020FFFF0000B6
+:20E8C000CC2D002019E7030031B5054C04E0401E00902046FDF77AFC00980028F7D138BDC6
+:20E8E000E703000018225043FE4A00218018017181604161012281610261C1607047FFB577
+:20E9000081B0F94C049B039A054626691A4303200092002E03D1002A0ED001222261276919
+:20E92000039A0126360792003B0000F022FF072707162940526127000222EFE770693269FC
+:20E9400092B25043326933691204920C9BB2594329DF002812D102210FE0084628DF00286A
+:20E960000CD10399002901D0032106E00499002916D12978042946D017E0216105B0F0BDAE
+:20E980007069326992B25043326993B24B4301461846039A29DF0028F0D10499002901D0F4
+:20E9A0000421EAE72978042920D00521E5E773693069366980B2434368681B189B18B6B2C7
+:20E9C0004E43301880181946049A29DF0028E9D0D4E7306980B24843696880188A08696902
+:20E9E00029DF0028CAD1009900290CD00621C4E77069316989B24843316989B200F0D9FD08
+:20EA000028DF0028BAD10721B7E7F8B5B54918230A780F205A435418241DB3492278266970
+:20EA2000CF68022A1BD001252D07042A2AD0052A5BD1286981B2304600F0BBFD0146A36877
+:20EA400028699A1980B24843101A820860681818861928694B1C80B25843801B34E0B8023C
+:20EA600062686169121A0918A3683018181801239B029A4202D2920829DF31E0FF220132BA
+:20EA800029DF2DE0E268974914205043F4314018001D0BC8B04203D160685943814218D02E
+:20EAA000022A16D0286981B2304600F082FD0146286980B24843301A820828694B1C80B208
+:20EAC000584363689B19C01A83082046FFF717FF06E0286981B2304600F06BFDC01928DFED
+:20EAE000002802D17F4901228A70F8BDF8B57D4C069E65780A2D1DD027787D19EDB20A2D5B
+:20EB000001D30A3DEDB218277D432D192871AA6103C9EE60AB6069612861A1780020002978
+:20EB200004D1FFF772FF112800D100206178491C6170F8BD0420F8BD38B5024669481823B1
+:20EB400001785943081803690179022B0AD014246343644CF434E4588368009383691030F7
+:20EB6000A04738BD604B14331C68F5E7F8B55D4B9978012914D100255B499D700A69082A77
+:20EB800005D002280FD003280AD10D2006E0022807D00D7000F025FA002801D0FFF7CCFF37
+:20EBA000F8BD0D61F6E74F48182403784E496343CC681818641C001DCC600378022B05D11F
+:20EBC0004668A102B14201D3012700E00027052B01D1072A03D00021042B02D003E00121C1
+:20EBE000FAE7072A03D00026042B02D007E00126FAE74068A302834201D3002A1AD0002000
+:20EC0000314301433943C5D0374E28463561FFF793FF344C2078FFF765FEF5606078401E1E
+:20EC200060702078401CC0B220700A28B2D30A382070AFE70120E3E770B500252A4C2948D3
+:20EC4000E56025610570457085702E463046FFF749FE761C0A2EF9D3012212076560516952
+:20EC600028461269491E92B25143E560A1601D49F4310D608D600D61CD601B4914310D6090
+:20EC8000888001212170206170BDF8B5164A044610780E46002830D0002C30D0002E2ED058
+:20ECA000206800282BD0012000076768016989B28F4228D8102F26D3A168002923D09568E2
+:20ECC000794343694A19006980B243439A421AD801200007006980B2814212D901200007E1
+:20ECE000006903E0E82D0020A828002080B2394600F05FFC002906D103E00820F8BD0E20B9
+:20ED0000F8BDB80701D00720F8BDBD49486801281CD00F461421BB4A21C641438E18756092
+:20ED2000236853506168B160A168F160A268616800235143012212075B1C14699BB2A4B214
+:20ED40008C4205D21469A4B2091B02E00420F8BD00211469A4B265191469A4B28C42EBD985
+:20ED6000BD60401C336178600020F8BDF8B50446A3481E46007815460F46002807D0002F3D
+:20ED800007D0002C05D02068002817D103E00820F8BD0E20F8BD9B48016800290ED0C268E3
+:20EDA000816840684A4310186268904206D9002D04D0A94202D3A819884201D90720F8BD90
+:20EDC000384600F008F9002811D0304600F003F900280CD0606800F0FEF8002807D02B4637
+:20EDE0003A46214602200096FFF780FEF8BD1020F8BDFFB5824881B000781F4616460D462B
+:20EE0000002808D0002D08D00198002805D02868002817D103E00820B0E50E20AEE5794C91
+:20EE2000206800280ED0E168A0686268414389186A68914206D9002E04D0B04202D3F119AD
+:20EE4000814201D9072099E5019800F0C4F800281BD0384600F0BFF8002816D0686800F025
+:20EE6000BAF8002811D068683246C119019800F02EFB00962868142148432458002203215B
+:20EE80002846019BA047002078E5102076E5F8B505465B480F460078002805D0002D05D012
+:20EEA0002868002821D103E00820F8BD0E20F8BD544C00262068002817D0A168E0684843CC
+:20EEC00061684118686881420FD900F084F800280DD0296814225143091968684A68896834
+:20EEE000801A00F066FB002903D00720F8BD1020F8BD3B460022294604200096FFF7F6FDB5
+:20EF0000F8BD3F4A1278002A0DD000280DD000290BD00268002A08D0394A14321368002B3E
+:20EF200005D004207047082070470E20704702230B600068106000207047F8B504463048AF
+:20EF40001E46007817460D46002807D0002D07D0002C05D0206802281BD103E00820F8BDC3
+:20EF60000E20F8BD264814300068002811D0084600F031F800280ED0304600F02CF800286C
+:20EF800009D03B462A46214602200096FFF7AEFDF8BD0720F8BD1020F8BD08B5184A1278C8
+:20EFA000002A05D0002805D00268022A11D103E0082008BD0E2008BD114A14321268002AD5
+:20EFC00007D00B460022014604200092FFF78EFD08BD072008BD800701D000207047012068
+:20EFE0007047084910B5F43949780020002906D0FFF70BFD002802D0112800D1002010BD48
+:20F00000A8280020DC2E002070B500250C290ED304464318008941000919581A0A38C2B2BD
+:20F020001748022A027002D30A318B4201D2092070BD144800F04BFA134914480A8882422E
+:20F0400002D02388934217D14988814202D06088884211D10D4A0323521E20891B03A842DE
+:20F060000AD9690009194989914203D09E896D1CB142F4D1002070BD0B2070BD00207047C6
+:20F08000C4280020F02E002080100010FFFF000010B5FDF7ABF810BD10B50446002A02D054
+:20F0A0001088002210E00A48FBE7030A00020343A05C584003061B0F43401803584083B2EB
+:20F0C0001806C00C5840521C8A42EED310BD0000FFFF00004B48002101704C484A4A026039
+:20F0E0008160C160016108224161426081610846704710B500291DD000220A60434A5368A8
+:20F10000002B1BD0202817D85B1E5360D0682423401CD060106914684343E3180B60012366
+:20F1200083409169401C19434007400F91611061002010BD0E2010BD0C2010BD042010BD8F
+:20F14000F0B5324A0646916800292BD057691020791A4907490F14680B4624254D436519D6
+:20F16000B54206D1012495698C4065400020956104E0491C4907490F8F42EED1491C4E07DC
+:20F18000760F956901210C469C402B4623420AD19368002B07D05B1E936053685B1C53609D
+:20F1A0003346F0E70420F0BD184A2423117C1268491E4907490F594320315050002070470B
+:20F1C00070B500281AD0002918D0104AD368002B16D05B1ED360936824265B1C936053692A
+:20F1E00015681C467343EE1820330660E858641C08606007400F5061002070BD0E2070BD84
+:20F20000042070BDC5280020FC2E00201C30002030B5CB0008339DB293070024002B01D0E6
+:20F22000072030BD3B4B9A605219DA605C701C7058809980002030BDF7B5364C0E466088D5
+:20F24000814237D8344F00F069F822786078A188884201DA401C00E00020C0B2904202D155
+:20F2600000F062F824E065786078884201DA401C00E00020607000F057F8BD4218D0A0688C
+:20F28000EF000299C151009900290CD0002E0AD0608832464543E068281800F018F9A068B3
+:20F2A0003818868002E00021381881800020FEBD0420FEBD0920FEBD0EB504E068468188A8
+:20F2C000029A0098904702AA01A9684600F003F80028F3D00EBD70B50E4B05241D785E786C
+:20F2E000AE4215D01D781C789E88B44201DA641C00E000241C705C88DE686C43A41904600F
+:20F300009B68E800C418A4880C80185800241060204670BDCC280020FFFF000072B606484F
+:20F320000168491C0160704703490868401E086000D162B670470000DC280020BFF34F8F11
+:20F3400003490248C860BFF34F8FFEE70400FA0500ED00E010B5002904D000221146104619
+:20F36000FFF7ECFF00F010F810BD10B50021024A0846FFF761FF10BD55F3030010B50846E6
+:20F380001146FCF771FF10BDF8B5384C2078002837D02069002807D00026E068002805D0FB
+:20F3A0000025002E04D013E00126F6E70125F8E7684651DF052806D0002806D000221146D2
+:20F3C000FFF7BCFF04E0012602E0216900988847002D12D1608869460880A06861DF0528FA
+:20F3E00006D0002806D000221146FFF7A7FF04E0012502E0E168A0688847002ED8D0002D15
+:20F40000CFD0F8BD70B5002901D08C0701D0072070BD164C0125A16062801549636010DF46
+:20F420000028F5D1257016202EDF70BD002803D00E49C860002070470E207047002803D0A8
+:20F440000A490861002070470E20704710B507484068002807D08047002803D0002211463E
+:20F46000FFF76CFF10BDFFF78FFF10BDE02800207DF30300034610B50B439B070FD1042A66
+:20F480000DD308C810C9121FA342F8D018BA21BA884201D9012010BD0020C04310BD002AAC
+:20F4A00003D0D30703D0521C07E0002010BD03780C78401C491C1B1B07D103780C78401C61
+:20F4C000491C1B1B01D1921EF1D1184610BDF8B5042A2CD3830712D00B78491C0370401C25
+:20F4E000521E83070BD00B78491C0370401C521E830704D00B78491C0370401C521E8B07F9
+:20F500009B0F05D0C91ADF002023DE1B08C90AE0FCF78EFEF8BD1D4608C9FD401C46B440B8
+:20F520002C4310C0121F042AF5D2F308C91A521EF0D40B78491C0370401C521EEAD40B78EC
+:20F54000491C0370401C521EE4D409780170F8BD01E004C0091F0429FBD28B0701D50280F7
+:20F56000801CC90700D00270704700290BD0C30702D00270401C491E022904D3830702D5EE
+:20F580000280801C891EE3E70022EEE70022DFE70378C2781946437812061B0219438378A2
+:20F5A000C0781B04194311430902090A000608437047002203098B422CD3030A8B4211D366
+:20F5C00000239C464EE003460B433CD4002243088B4231D303098B421CD3030A8B4201D39D
+:20F5E00094463FE0C3098B4201D3CB01C01A524183098B4201D38B01C01A524143098B422D
+:20F6000001D34B01C01A524103098B4201D30B01C01A5241C3088B4201D3CB00C01A524193
+:20F6200083088B4201D38B00C01A524143088B4201D34B00C01A5241411A00D201465241FB
+:20F64000104670475DE0CA0F00D04942031000D34042534000229C4603098B422DD3030A47
+:20F660008B4212D3FC22890112BA030A8B420CD3890192118B4208D3890192118B4204D305
+:20F6800089013AD0921100E08909C3098B4201D3CB01C01A524183098B4201D38B01C01A88
+:20F6A000524143098B4201D34B01C01A524103098B4201D30B01C01A5241C3088B4201D37F
+:20F6C000CB00C01A524183088B4201D38B00C01A5241D9D243088B4201D34B00C01A52417F
+:20F6E000411A00D20146634652415B10104601D34042002B00D54942704763465B1000D31A
+:20F70000404201B50020C046C04602BD704770477047754600F022F8AE460500694653469B
+:20F72000C008C000854618B020B5FEF7FBFA60BC00274908B6460026C0C5C0C5C0C5C0C525
+:20F74000C0C5C0C5C0C5C0C5403D49008D4670470446C046C0462046FCF7FFFC004870479C
+:20F760003830002001491820ABBEFEE726000200704730B47446641E2578641CAB4200D256
+:20F780001D46635D5B00E31830BC184702000000000000000000000000000000040000009F
+:20F7A000000000000000000000000000000000000000000035C4030000000000000000004D
+:20F7C000020000000000000000000000000000000000000000000000030000000000000024
+:20F7E0000000000005000000000000000000000000000000000000000000000023D1BCEA6A
+:20F800005F782315DEEF1212000000002CF8030000280020F400000004C1030020F90300A1
+:20F82000F4280020A413000020C103000000000000000000000000000000000000000000F1
+:20F840000000000000000000000000000000000000000000000000000000000000000000A8
+:20F8600000000000000000000000FFFF000000003200000000000000000000000000000058
+:20F88000000000000000000000000000000000000000000000000000000000000000000068
+:20F8A000000000000000000000000000000000000024F40000000000000000000000000030
+:20F8C000000000000000000000000000000000000000000000000000000000000000000028
+:20F8E000000000000000000000000000000000000000000000000000000000000000000008
+:20F900000000000000000000000000000000000000000000000000000000000000000000E7
+:20FC00000100000000000000FE0000000000000000000000000000000000000000000000E5
+:020000041000EA
+:0410140000C0030015
+:040000050003C0C173
+:00000001FF
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/s130_nrf51_1.0.0_bootloader.hex b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/s130_nrf51_1.0.0_bootloader.hex
new file mode 100644
index 0000000000..c9c68846b9
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/s130_nrf51_1.0.0_bootloader.hex
@@ -0,0 +1,463 @@
+:020000040003F7
+:20C00000983C002005DD030017DD030019DD03000000000000000000000000000000000057
+:20C0200000000000000000000000000069C1030000000000000000001DDD03001FDD0300D7
+:20C0400021DD030021DD030021DD030021DD030021DD03000000000021DD030021DD0300D9
+:20C0600021DD030021DD030021DD030021DD030021DD030021DD030021DD030021DD0300B8
+:20C0800021DD030057D8030021DD030021DD03006DD8030021DD03004DF4030021DD0300DD
+:20C0A00021DD030021DD03000000000000000000000000000000000000000000000000007E
+:20C0C00000F002F800F040F80CA030C8083824182D18A246671EAB4654465D46AC4201D18E
+:20C0E00000F032F87E460F3E0FCCB6460126334200D0FB1AA246AB463343184710370000C8
+:20C1000030370000103A02D378C878C1FAD8520701D330C830C101D504680C6070470000D3
+:20C120000023002400250026103A01D378C1FBD8520700D330C100D50B6070471FB5C04655
+:20C14000C0461FBD10B510BD03F0E3FA1146FFF7F5FF00F0D3F803F0FBFA03B4FFF7F2FF19
+:20C1600003BC03F0FFFA00000648704502D1EFF3098101E0EFF30881886902380078024A97
+:20C1800010470000FDFFFFFF39D50300401E00BF00BF00BF00BF00BF00BF00BF00BF00BF28
+:20C1A00000BF00BF00BFF1D170470000401E00BF00BF00BF00BF00BF00BF00BF00BF00BFB4
+:20C1C00000BF00BF00BFF1D170470000401E00BF00BF00BF00BF00BF00BF00BF00BF00BF94
+:20C1E00000BF00BF00BFF1D170470000056885F3088846680A4AEFF305839A42304602D183
+:20C20000084CA6463047074C064D0646064FF0B4034C034D024E024FF0B404480047000005
+:20C2200000000000FFFFFFFF00000021F9FFFFFF70B505460C46164602E00FCC0FC5103EEE
+:20C24000102EFAD2082E02D303CC03C5083E042E07D301CC01C5361F03E021782970641C63
+:20C260006D1C761EF9D270BD0A4610B50146664803F064F810BD10B502F078FC10BD10B5C6
+:20C28000624C86B01ECC03946C460EC4002807D0684618DF002803D00022114603F04EF864
+:20C2A0000F20800313DF002803D00022114603F045F8574B48225749092003F0A3F80028AB
+:20C2C00003D00022114603F039F800200490059001206946087404A860DF002803D0002251
+:20C2E000114603F02BF84C4803F0A8F8002803D00022114603F022F806B010BD08B547485A
+:20C30000C169B12943D0002445480F2140698903884204D000221146104603F00FF8012068
+:20C320000007006901218902884204D000221146104603F003F83B4800903B4B05220321A1
+:20C34000002001F0BAFA002803D00022114602F0F5FF00F067FC00F0AAFC012500281AD09D
+:20C3600000F0B4FC002803D00022114602F0E6FF20466840FFF783FF00F038F800F0CCFC74
+:20C3800000280ED00022114602F0D8FF09E001240021C161B8E720466840FFF770FF00F002
+:20C3A00025F803252D03002C04D1A86800F090FB002807D100F047FC002803D000221146D5
+:20C3C00002F0BCFFA86800F083FB002806D000F06EFC002802D1A86800F041FCBFF34F8F12
+:20C3E00013491248C860BFF34F8FFEE7094A10B548321421082002F00BFF002803D00022E2
+:20C40000114602F09BFF10BDEFBEADDE8CF703006BF30300342B002077C20300000500404D
+:20C4200000100010EFDC0300F42800200400FA0500ED00E070B5FC4C1E46A06815460229A3
+:20C4400002D0042916D108E0052813D1A369002B10D03246294604200BE002280AD1F348B0
+:20C46000406880470320A060A369002B02D0324629469847280003D00022114602F05EFF98
+:20C4800070BD4CB5E84E0120307005200195009400F058FB4CBD10B5E34C2078002801D057
+:20C4A000082010BD206901F0F4FA002803D00022114602F043FF0F2100228904206901F01E
+:20C4C000ABFA040003D00022114602F037FF204610BDD54910B5D448243141610221816012
+:20C4E000C168243002F059FD002803D00022114602F024FF10BDCC4910B5CB481C31416145
+:20C50000022181600320000380680F218903081A4108C5481C3002F040FD002803D000223D
+:20C52000114602F00BFF10BD704700B589B01822BF4902A8FFF77CFE06980799009001917A
+:20C5400002A80FC800F0FEFA09B000BD00B5B64987B049886A461181032109038968069146
+:20C56000B249012050394A6803928A680492C9680591069A0091019202A90EC900F0E2FA6E
+:20C58000002007B000BD30B5A84CA748503C89B02430E16802F001FD002803D00022114679
+:20C5A00002F0CCFEA048E2681C3041680023083002F0C3FC050012D1182102A802F0E6FFEA
+:20C5C00000209949029049886A469181E1680691079A0091019203A90EC900F0B3FA284601
+:20C5E00009B030BD00B5904987B049886A4611818E49032050394A6803928A680492C9683A
+:20C600000591069A0091019202A90EC900F09AFA0020B6E73EB5864A6B46183207CA07C3A4
+:20C62000814D00246C7029466C802431684602F068FC002801D0AC603EBD03207A4900038F
+:20C6400080682431486024390A46526ACA610F218903091A490840187349764A1C31486068
+:20C6600071480021103001F07BF9002803D00022114602F063FE0F2100228904286901F013
+:20C68000CBF9002803D00022114602F057FE01206C60A86000203EBD63498861704770B59A
+:20C6A000426862481468536891685038D26804604360C26081600078440701D5840705D130
+:20C6C0009C0703D18C0701D1940701D0062070BD5B189A18544D0F239B02EA60994213D81A
+:20C6E0005549564B514CC60709D08868181A90420AD3534820605348606053480FE08968F6
+:20C70000591A4908914201D20C2070BD4F4921604F496160800701D54E4800E04E48A0607B
+:20C72000A868012802D00826304670BDFFF7B3FE0600FAD12168E8688847F5E770B50500F7
+:20C7400004D0287A800703D0102070BD0E2070BD354CA068032805D0042801D0052803D0CB
+:20C76000082070BD0520A0606868E168860060688019884204D90020C04360600C2070BD5C
+:20C78000FFF789FE0028FAD1A96832466368606902F0D3FB0028F2D1616889196160E268EB
+:20C7A0009142ECD0092070BD10B51F4C08206168002900D010BDA1680429FBD11B4861786F
+:20C7C000403802F021FC002802D00021617010BD0521A16010BDF8B5134C0746A068032899
+:20C7E00004D0042804D008252846F8BD0420A0606068002801D00820F8BDFFF74CFE05000E
+:20C80000FAD17868860060788119402901D90920F8BD064AB968403A1018324602F057FE82
+:20C82000607880196070DFE7002800201C2D00209CF7030083C403000030000000C003006D
+:20C84000D3C403002BC503004DC50300F7C4030029C50300E5C5030087C5030010B5894CF1
+:20C86000A068052813D1E168606888420FD10620A060FFF710FE002808D16069E1684068FF
+:20C8800002F0FCFB002801D10721A16010BD082010BD10B57B488168072901D0082010BD63
+:20C8A000006901F0F6F8002803D00022114602F045FD75488068804710BD1CB506200195C2
+:20C8C000009400F03FF91CBDF8B51C4617460D46064600F0C1F8002817D001200003854215
+:20C8E00007D92346291B301B1A46FFF7EDFF00280BD13A462946304600F0B9F8002804D117
+:20C900003A462946304600F0A7F8F8BDF0B589B0684600F015FA049800282AD001210903F7
+:20C92000079A4018904226D9501A45081046049A0C468718024668001618001908900320DF
+:20C9400000038068049988420DD261190846042200F08DF800280CD121460422084600F073
+:20C9600086F8002805D1BA1B2B4630460899FFF7ABFF09B0F0BD049A079800F078F8F8E75C
+:20C9800000B58DB004A800F0DBF9099800280DD0089800280CD008990B984018019000219D
+:20C9A0000998009180080290684618DF0DB000BD0320000380680F218903091A4908ECE7FB
+:20C9C00000B58DB004A800F0BBF909980028EDD00F210898890300280CD0089A0B98019158
+:20C9E0008018029003220998009280080390684618DFDBE70320000380680A1A5208EEE7D2
+:20CA000030B591B0684600F09BF90498002814D001210903079A4018904214D9501A43087B
+:20CA20001046049A5C0082180019611803242403A468049DAC4202D20E2011B030BD121AB5
+:20CA4000FFF742FFF9E703200CAB07C3049880080F900CA818DFF0E71FB5032301909008B3
+:20CA6000039000930291684618DF04B010BD1FB5012301909008039000930291684618DF58
+:20CA8000F3E70000002800201C2D002010B5BB480368012B02D1022900D10160100003D099
+:20CAA0000022114602F04AFC10BD10B5B34C48DF002803D00022114602F040FC02F0FCFB82
+:20CAC0002068022803D0032801D00428EFD110BD38B50068401C19D00024684600F058F96F
+:20CAE00000980168012910D1818800290AD0C168032000038068002202F0CEFA0099898861
+:20CB0000814201D1012400E00024204638BD10B504469A482021001D02F0B9F9002803D00E
+:20CB20000022114602F00AFC9448002320222146001D02F01BF9002803D00022114602F053
+:20CB4000FDFB10BD0FB4F8B5684600F021F96846818B069D0122894CFF238948002D13D090
+:20CB6000012D17D0032D2BD00021022D37D02A46052D46D0042D4ED0062A01D10420206071
+:20CB8000F8BC08BC04B0184781800A9983600260C16010E08180099D089949190A9D49195D
+:20CBA000C160A52183600160089901610999856141610B99C16122607148FFF7A8FFDFE7B9
+:20CBC00000990B6803608B888380C968C160AA21816008990161099941610A990BE0009D60
+:20CBE0002E68A52E09D00660AE888680ED68C5600161836041618161DDE781800360C160C5
+:20CC0000F6E700F085F9002803D00022114602F095FB0320B3E781800360C1600099896807
+:20CC20008160C9E70EB557480090202001900120029002F001F8002804D150496846091D98
+:20CC400002F023F80EBD10B5FFF7E4FC002805D100F02FFB0446FFF728FF204610BD70B58A
+:20CC600011DF002803D00022114602F067FB464900200B68444C012180340A4682401A4206
+:20CC800004D0C506ED0E0A46AA402260401C2028F3D303242403A06813DF002803D000226F
+:20CCA000114602F04BFBA06802F0F2F970BD08B5684600F06DF800980168A52904D0806888
+:20CCC000AA2801D0002008BD012008BD10B5FFF797FE002803D1FFF773FE00281BD064209C
+:20CCE00001F0F2FDFFF712FE002803D00022114602F024FBFFF784FE002803D000221146DD
+:20CD000002F01CFBFFF73CFE040003D00022114602F014FB204610BD00B589B018221B49CA
+:20CD200002A8FFF785FA069807990090019102A80FC8FFF707FFFFF7B8FE002009B000BDB5
+:20CD400010B50E4988B0044600232022091D684602F04FF80098206068468088A08003983A
+:20CD6000E0600298A06004982061059860610698A0610798E06108B010BD00002C280020E6
+:20CD8000282D00208DCA030000E100E0C0F70300014901607047000000FC030008280CD0DC
+:20CDA00004DC002807D006280FD108E00B280AD00C280AD105E001207047022070470320C9
+:20CDC000704704207047042901D0062070470520704770B515460A46032823D0042820D1FF
+:20CDE000FE4C002906D0E088FD49884219D0132176DF10E0284602F0A3F9002803D00022F7
+:20CE0000114602F09BFAE069A8420AD101220321F44801F003F8002803D00022114602F051
+:20CE20008DFA70BD01211046FFF7B8FF02460121EEE7F0B5054608790E4685B081070CD07C
+:20CE400003221146284600F0E9FF002803D00022114602F073FA05B0F0BDE04900901831D9
+:20CE600002F047F9010011D1DC4CB168009AA06902F02DFB009802F097F9010006D1204647
+:20CE80006946183002F09CF9010003D0284600F0AFFAE0E704200190009880080290A06902
+:20CEA000039001A8FFF74AFC07000BD0092F10D0A06902F045F9010002D0284600F098FA04
+:20CEC0003946E3E73079616940186061A069E061C1E7307961694118616160780028BAD073
+:20CEE0006089401E0004000C6081B4D1284601F0E9F8002803D00022114602F01FFA20890D
+:20CF00006081A8E710B50022114602F017FA10BD10B5B24C01202070E088B149884208D01B
+:20CF2000132176DF002810D00022114602F006FA0BE0A078002808D074DF002803D0002282
+:20CF4000114602F0FBF90020A07001F034FC002803D00022114602F0F1F9002010BD70B5E1
+:20CF60000D68044601209D4A2B0002F002FC0A2B3043061320575C466012FFF76FFC0421FD
+:20CF8000FFF70CFF024604212EE00022114602F0D5F970BDFFF7BCFF002803D0002211468A
+:20CFA00002F0CCF9FFF775FC002808D170BDFFF7AFFF002803D00022114602F0BFF9FFF76D
+:20CFC0007CFC70BD106188680078107170BD02201061886800780128F8D1FFF7E5FB02213F
+:20CFE000FFF7DCFE02460221204600F017FF0028CBD170BD0320106170BD12692046012ACC
+:20D0000006D0022A07D0032AF6D1FFF712FF70BD00F001FA70BD00F03BFA70BD50708888D5
+:20D020001081508170BD00205070108170BD2046516901F010F8DAE710B5044669488EB0EB
+:20D0400081796846817068490180342101A802F09DFA022001900021684641728472012131
+:20D0600001820590002101A801F03FFA002803D00022114602F062F90EB010BDF0B5574C10
+:20D080008BB0A07800283AD156481821183802F07DFA2046534CC078183C00250126002875
+:20D0A00037D02746483700950195029510226946F81D039502F0DEF9002822D0F81D08909D
+:20D0C00009976846067509A804906846067708A806900420FFF7B0FF25700220207204A813
+:20D0E000E060282020823F486582183873DF002803D00022114602F021F9384886700BB045
+:20D10000F0BD0520FFF798FF2670676025722582E9E70620FFF790FF257065602572E0E7E2
+:20D1200070B52E4C01880022E588A6B017290AD01EDC11293FD008DC022977D0102902D123
+:20D140008088E080A27026B070BD264C303426461836132951D01429F5D1C289638D002106
+:20D160009A4200D1314600238088E21D82DF1BE0512970D00EDC18296CD01929E3D18079F5
+:20D180000028E0D1A270E068401EE0604FD0FFF775FFD8E7522976D05529D4D18079002871
+:20D1A000D1D11321284676DF0028CCD00022114602F0C4F8C7E78020694688803220E06054
+:20D1C000012301AA06A92846AADF002803D00022114602F0B3F82078002807E038280020A2
+:20D1E000FFFF0000602D00203015000001D1FFF745FF0020C043E080A5E70722C14910A839
+:20D2000002F065F91022E11D0CA802F060F91C22314612A802F05BF90CA80A9012A8099039
+:20D2200006ABB94A852128467FDFBDE70DE01822B64906A8FEF7FCFF0A980B9900900191F8
+:20D2400006A80FC8FFF77EFC7DE70021284667DFAAE700E017E0817900299AD0807A042885
+:20D2600003D0062801D0052893D1022909D0012069460872FF208330888102A92846A8DF82
+:20D2800092E70220F4E700F08DF88DE710B5044601F0C2FA9B482146303800F09AFE2046D3
+:20D2A000FFF73EFF10BD10B50022114602F046F810BD30B5944D87B00024203D2C7094483D
+:20D2C0002C6102F0B3F800286AD19248FFF7E4F901F000FF002863D18A4800F059F900288C
+:20D2E00001D10120E87011206946087207228AA102A87CDF002803D00022114602F01EF8B4
+:20D3000000940C2168460194018018214180FF2184809131C1807ADF002803D0002211469A
+:20D3200002F00CF804206946009408807C4801907C4802907348303800F00BFE002803D046
+:20D340000022114601F0FAFF1C21684602F01EF9754801900120800302900094032168468C
+:20D360000173C4810474714806900594684601F0FEF9002803D00022114601F0DFFF624910
+:20D38000E12208784008400010400C30DF22104008700720487010208870FFF76FFE0020A3
+:20D3A00007B030BD70B5584C614D203CE088A84201D1082070BDE178002914D05149012359
+:20D3C00008223431A9DF0028F4D12A460C21E088A7DF5849884204D0082802D0891C88420E
+:20D3E000E8D1002070BD00231A461946A9DF70BD10B50A46044603211046FFF7CFFC0246AE
+:20D400000321204600F00AFD002803D00022114601F094FF10BD30B5054687B000200090AF
+:20D4200001900290039038486A46203800791070364A0C3A1068926804906846069205900E
+:20D4400008790C2806D003221BE00022114601F075FFA5E78C68204600F049F80190201D5E
+:20D4600000F045F802902046083000F040F8039004A8FFF714F9002892D00121FFF78EFCB9
+:20D4800002460121284600F0C9FC0028DDD187E7FEB50446087982070ED08207920F042385
+:20D4A0009B1A0022154604E08E683554401CC0B2521C9A42F8D30871012000908868029048
+:20D4C0000879800801906846FFF785F900280DD00221FFF763FC02460221204600F09EFCB8
+:20D4E000002803D00022114601F028FFFEBD10B5044602F04DF80002E178000A09060843E0
+:20D5000010BD0000902D002058280020E4F703008DD20300D3CD0300446675546172670031
+:20D520005FCF0300A7D20300CD0C000005CF0300FFFF00000230000010B50C46002802D04D
+:20D540000120086010BD2168002911D01C48421A814212D03C2A0DD23C303C3101220B78B9
+:20D5600003701346491E401E521C3C2BF7D904E00E200BE03C2201F0AAFF00223C211048A9
+:20D5800001F08AFD0E49891E08800020206010BD70B5054600223C21094801F07DFD084C21
+:20D5A000A41E2188884201D00B2070BD3C220449284601F08CFF2088401C2080002070BD87
+:20D5C000823F00208307FF22DB0E9A408907090E994000280BDA0007000F08388308FA484C
+:20D5E0009B001B18D86990430843D86170478308F6489B001B1818689043084318607047AA
+:20D6000070B50124F24960040860F24940108860F04940398860F04D6C602F20FEF7B6FDAC
+:20D62000AC60EE4D00242F206C61FEF7AFFD2C7170BDF0B5E94F2821BC6841430D19396962
+:20D640004A1C09D028224A431619AB68B268934204D8D21AB26069623861F0BD0A4602E066
+:20D660000A46796A9B1B4E1C0BD028264E433719BE689E42F4D328264E433619B768FF1A1A
+:20D68000B760AB60696228214A4311194862F0BD70B5D24C2269A5681346114606E0814212
+:20D6A00007D00A46282671434919496A4E1CF6D170BD002EFCD08A420CD1282043435819EC
+:20D6C000406A2061401C05D1C34B01209860002363616071282041434819282381685A4310
+:20D6E000406A52195062421CE2D028225043401982685118816070BDF8B5B84C2569681CF9
+:20D7000035D0B748002640686169401A07023F0A19E028204543A0682A189068B84214D8D0
+:20D72000A3693F1A8619556A002B09D0116AD0699847002807D00022114601F0FFFD02E048
+:20D74000D169106A8847681CE3D1A178E078814206D1401CC0B2E070022801D10020E07079
+:20D760009E490006800D1C310E5000F0BAF9F8BDF8B50446994800270169009146785CE038
+:20D780009648F100C2688D1851E0601C07D0934A28209268604321468018446A24E0287854
+:20D7A000182141436A68401CC0B252182870A978884200D12F70894B516828209B6848434C
+:20D7C000C0181368012B34D1037E002B31D19368C360D368036113694361526902627F4A52
+:20D7E0005279002A00D0C7607C4BC2685B6996469C46D31A1A027B4B120A9A4202D20369C3
+:20D80000D21808E0724663469A1A12020369120A934202D99A1A826000E08760C76001222E
+:20D8200007610276921E42620846FFF702FF601CABD1287869788842A7D13046761EF6B202
+:20D8400000289DD1654801690098814201D00120F8BD0020F8BD644900200860486088607F
+:20D86000C860614940390860486045E7FEB50020C0435A4D02906869019068462E6900F07B
+:20D8800035F9074600F04FF90446002F08D002AA0199009800F08FF90298FFF769FF06E050
+:20D8A0000298FFF765FF002801D1002C02D0304600F0AAF900206871FEBDFFB59807002448
+:20D8C00081B01E4615460F4600280BD1002E09D0FFF796FE41490A9888610F703246002042
+:20D8E0008E6008E0072005B0F0BD28234343D4509B181C76401CB842F7DB28204743BB19C1
+:20D90000032048700F461846CB6019461830002218232E465E43D3005B181C705C709D708A
+:20D9200058603018521C032AF5DB0020C0433861BC70FC7001242D482405046003211420A9
+:20D94000FFF740FE224880380460254C0198A06003211120FFF736FE606878610020C2E71A
+:20D9600070B51E4CA568002D06D0002A06D0002804D00023247809E0082070BD072070BDBB
+:20D9800028265E43AE59002E04D05B1CA342F7DB042070BD282401265C432E516419E261BF
+:20D9A00061600360002070BD07494868C005C00D2CD010381CD50207120F083A9208920097
+:20D9C0005118C96919E0000000ED00E000E400E080E100E040130140001001406028002054
+:20D9E00000150140FFFF7F004011014080E200E08108B14A8900891809688007C00EC1400B
+:20DA00000806800F012803D0032803D0022070470020704701207047FEB50446A74817469E
+:20DA200082680D46002A0CD001788C4201D2052D01D20720FEBD2146282359435358012B7D
+:20DA400001D00820FEBD8818406801281DD00026FFF7AAFFC00099490190C9684018694684
+:20DA600000F018F9002812D0012144600160944949680830E2C091490198C9684118009877
+:20DA8000487000F02EF80020FEBD2E46E0E70420FEBDF8B5894D0446A868002809D0297844
+:20DAA0008C4201D30720F8BD282161434058012801D00820F8BDFFF777FFC600E86869465B
+:20DAC000301800F0E7F8002809D0022112C0E86831180098487000F004F80020F8BD04206B
+:20DAE000F8BD0120774900050860704710B5734900238A78CC78A24212D0521CD2B28A70D0
+:20DB0000022A00D18B708A786C4B92001C339A580260486910180002000A4861012010BDA3
+:20DB20000360002010BDF8B5644801690091457833E06248E900C0680E1834782AE01820A2
+:20DB400060437168641C0818B178E4B2A14200D100240168022902D003291BD113E0574A00
+:20DB600040682821926841438F18397E002911D0FFF78EFD002038760CE028277843C018B1
+:20DB80000276406A03E04D4900228B680869471CF3D108617078A042D1D128466D1EEDB2D0
+:20DBA0000028C6D1454801690098814201D00120F8BD0020F8BDF7B5404C0025A7682369E0
+:20DBC0001EE028215943C9198E68864202D9301A886017E0801B751900268E600E764E6946
+:20DBE0009C464B6AB646002E0AD0019E76193602360ACE6076460E6116684E626146116045
+:20DC0000591CDED12361FEBDF8B52C4801694A1C3DD028225143826889188E6828494C681F
+:20DC200047690079E11B0D022D0AED1C002815D10120254A00045060234A403A506021491D
+:20DC4000400080310860214908602149012008602F20FEF79BFA194901200871B54200D208
+:20DC60003546E81900021649000A4031086014494968001B091B0902090A0002C91C000A88
+:20DC8000814203D901200F4940040860F8BDFFF7B7FCF8BD42788378521C934200D10022C2
+:20DCA0000378934201D1002070470A6041684078182250430818704700E400E06028002090
+:20DCC0000015014000E200E04013014000E100E00010014010B50446082904D000221146F9
+:20DCE000104601F02BFB21686068884710BD1CB501910090024A0821684601F09DFA1CBD53
+:20DD0000D5DC03000A48026803210A4302600948804709480047FEE7FEE7FEE7FEE7FEE797
+:20DD2000FEE7000005480649064A074B70470000240500404DDD0300C1C003009830002007
+:20DD4000983C00209834002098340020F8B500F035F82B4E002804D02A4870602A49F01300
+:20DD600088612A480124018CC9B201290DD1818C09070AD1018D0906090F042905D1808D56
+:20DD80000006000F01D1224884600027B461214D6F60A8058460686800280ED1C820FEF790
+:20DDA00005FA1D487F1C8742F5D30020B06101208007846068680028FCD0F8BD1348018CB5
+:20DDC000C9B2012917D1818C090714D1018D09060A0F03D1828D1206120F0ED0090F0129C2
+:20DDE00003D1828D1206120F07D0032903D1808D0006000F01D0002070470120704700008E
+:20DE000000050040DFFF07C0006C0040C00F00F000060040000100408813000030B585B071
+:20DE2000002822D00388FE4CA34220D0FD4B1B78002B1CD0FB4B10255B1C1D7059700024C0
+:20DE400001259A70032269460A820094019402940394028A0A808D708C8004A902910393E7
+:20DE600000886946A6DF05B030BD0E20FBE70820F9E7F0B58BB0044602276846077300268B
+:20DE800009968784C68408A80A900D46A18A208809AAA5DF002804D0E16A00291AD08847BE
+:20DEA00018E06846008CC007C00F13D068460682208803A9A8DF002813D1A97E28461B30BA
+:20DEC00001220B0001F055FC09430F1B202224263E284300FF20FE3069460882208803A94D
+:20DEE000A8DF0BB0F0BD00960AE0062219E069460A71029022E0204690470020F1E700920D
+:20DF00002B8B022BF3D2F0E700971DE003201AE0042018E0052016E0298B032905D20322BE
+:20DF200008212046FFF77AFFDBE741780278080210436946888003D006200090A26ADAE784
+:20DF40000720FAE7092000906946A26AD3E70322E7E730B585B00D46040038D0002D36D0EC
+:20DF60006868002833D00020C043AF4B20800FCB049301AB07C3AD4869460880891C01A888
+:20DF800063DF002822D1221D69460120A0DF00281CD168468078A071204600F0CEF8002886
+:20DFA00014D1204600F055F900280FD12946204600F002F9002809D16868A062A868002804
+:20DFC00000D0E06297490120087000204BE70E2049E73EB5002828D0002926D0826A002ABE
+:20DFE00023D00A88102A21D0112A30D0502A1FD0512A1AD104460846891D0A78022A14D196
+:20E000004A88238A9A4210D1807A04280DD006280BD0052809D0891C2046FFF72AFF002860
+:20E0200003D0E16A002900D088473EBD898810E0CA8803899A42F8D1082200928A7F6B4605
+:20E040001A7120310291826A694690473EBD0021C94301803EBDF0B585B00A4605002DD00F
+:20E0600028886F4988422BD06E480078002827D06C4C1020641C2070072060700127A770F8
+:20E080000321684601820026E11C104600F04CF801466846008A0918684601820096019680
+:20E0A00002960396298A01808770868004A80394029028886946A6DF05B0F0BD0E20FBE7D3
+:20E0C0000820F9E7F0B585B00A46050028D028885349884226D053480078002822D0514C3B
+:20E0E0001120641C20700127684607820026611C104600F019F801466846008A0918684638
+:20E1000001820096019602960396298A01808770868004A80394029028886946A6DFCBE782
+:20E120000E20C9E70820C7E70870020A4A70020C8A70000EC8700420704730B58FB0054655
+:20E140001C21684601F022FA694608780421084369460870002401940394049405940694E6
+:20E16000A87908A9887031486946801C0884601C00070794000F0C77103048778A7FF920B4
+:20E180000240921CE7200240012002438A77142109A801F0FBF908A8099007A80A906946D3
+:20E1A0008C851420CC8508860D942B46A888083309AAA2DF0FB030BDF0B58FB00F4605465A
+:20E1C0001C21684601F0E2F968460178022631430170002401940394049405940694A97917
+:20E1E00008A8817011496846091D0184601C0107090F103168460794017700200146684618
+:20E200004177817FF9200140891CE72001400120014368468177142109A801F0B7F907E086
+:20E22000FFFF000088280020FCF703003015000008A8099007A80A9068468685C4850686B5
+:20E240000D972B46A888203309AA6946A2DF0FB0F0BD30B58FB005461C21684601F096F9FD
+:20E2600069460878082108431022104369460870002401940394049405940694A87908A962
+:20E280008870144869460884601C00070794000F0C7710304877887FF9210840801CF72123
+:20E2A000084010430121084369468877142109A801F06CF908A8099007A80A9069468C851A
+:20E2C0001720CC8508860D942B46A888103309AAA2DF6FE731150000FFB583B0074600207F
+:20E2E0000C9C8646267805463AE07868A90041180A88684682804988C1800022694601A8F7
+:20E3000065DF002810D1684601780598814226D17046002801D0002200E002222078891824
+:20E3200041181F2902D90C2007B0F0BD7146002908D1401CC0B2411C069B049A21701A54AF
+:20E3400001208646217806980A18694601A865DF0028E9D1694620780978401820706D1CC0
+:20E360003888A842C1DC7046002804D020780699801B401E88550020D6E7F8B51546069C10
+:20E380001E46074602220094FFF7A6FF002806D133461022294638460094FFF79DFFF8BD07
+:20E3A000F7B582B000260546167000681446002805D02846039900F0CAF8060008D168794D
+:20E3C00000281ED02078039F001D1F2802D90C2005B0F0BD684679DF0028F9D1217803226A
+:20E3E000481C20707A5421781922481C20707A542078C1196846008800F0A4F821784018A0
+:20E400002070A8790223002810D02078039A411C2170135420780399471C012227700A54E5
+:20E420002078AA79471C039927700A54A868002815D00021415620788C460246C01C03992E
+:20E440001F28C4D8501C20708B5422780A23501C20708B5420786246431C23700A54A8899B
+:20E46000002809D028460094062202210C30039BFFF783FF0600ABD1A88A002809D02846D9
+:20E480000094072203211430039BFFF776FF06009ED1A88B002809D0284600941522142137
+:20E4A0001C30039BFFF769FF060091D1686A002805D02246039900F07FF8060088D1A86A01
+:20E4C000002805D02246039900F0B5F8060084D13020405D002806D022462846039900F0F6
+:20E4E000DCF80600C7D1304672E770B50C4692B000216A46117007251171002809D0817927
+:20E5000049070CD502A9FFF74BFF002808D102AE00E00026002C0ED0A079002802D028469D
+:20E5200012B070BD01AA0AA92046FFF739FF0028F6D10AAA00E0002268460379017830463C
+:20E5400072DFEDE70870000A487002207047F8B514780746A01C15460E461F2803D83879BF
+:20E56000801C1F2801D90C20F8BD1D20001B80B26946864608803019801C7DDF0028F3D143
+:20E580003868022805D168460088704501D8092107E038790821002801D0704501D96846F6
+:20E5A0000088421C3255641CE2B2B1542978801C081828700020F8BDF8B50D461178064636
+:20E5C000881D14461F2801D90C20F8BD33880720062BFAD31927FF01BB4202D94D4A9342D6
+:20E5E000F3D17288062AF0D3BA4202D9494FBA42EBD1484FBB4203D0BA4201D09342E4D87E
+:20E60000481C052220706A5420781222411C21702A54207841193088FFF794FF21784018C5
+:20E62000C0B2207041197088FFF78CFF2178401820700020F8BD70B5054600790E46801CD6
+:20E640001446C0B21178821C8A181F2A01D90C2070BD0A46491C401C2170B0542078FF224A
+:20E66000411C21703254207881192888FFF76AFF21784018C0B22070AA88002A09D0A968AC
+:20E68000002908D0801900F022FF2078297940182070002070BD072070BDF7B582B0029894
+:20E6A0001446C06A0F46002832D0029800252030009028E00298C16A0C2068430E18217855
+:20E6C00030794A1CC01C2270785421781622481C20707A542078C1193088FFF733FF217873
+:20E6E0004018C0B22070B288002A09D0B16800290ED0C01900F0EBFE207831794018207087
+:20E700006D1C0098EDB2007CA842D3D800205FE607205DE6FFFF000038B56749674A48883D
+:20E7200090420FD04A78664C521CD2B24A70237B934208D3083175DF002803D0A1690029FF
+:20E7400000D0884738BD00254D70217C002907D03B2176DF002803D0A169002900D0884728
+:20E7600061690029EED068460095884738BD70B5054601461C225248FDF75AFD4E4C002647
+:20E7800026702968002907D00822A01800F09FFE204608307ADF02E0474808307BDF0028C1
+:20E7A00008D1401E608044486670464A0021001DFFF7D6F870BD10B53F484068FFF769F9D5
+:20E7C00010BDF8B53C48103000F069F800263A4D3B4C002806D06169002919D001200090EB
+:20E7E000684614E02878002804D0616900290FD00096F5E7687800280CD0A16800226868B8
+:20E80000FFF70AF9002803D0A169002900D088472E70F8BD6168F1E7F8B5294C028800276B
+:20E82000254DE689102A18D029464968112A21D0122A2DD0502A0FD1801D0288B2420BD1FF
+:20E84000028B022A08D1C27E837E10021843C007C00F13D0FFF7B5FFF8BD81886980014667
+:20E86000154808221631103000F031FE6F70002EF0D0F8BD0020C04368806F700846FFF7BB
+:20E8800008F90028F5D0A1690029F2D08847F8BD811D09480822103000F019FEDAE7418827
+:20E8A000054808300288914204D34088814201D8012070470020704790280020FFFF0000B6
+:20E8C000CC2D002019E7030031B5054C04E0401E00902046FDF77AFC00980028F7D138BDC6
+:20E8E000E703000018225043FE4A00218018017181604161012281610261C1607047FFB577
+:20E9000081B0F94C049B039A054626691A4303200092002E03D1002A0ED001222261276919
+:20E92000039A0126360792003B0000F022FF072707162940526127000222EFE770693269FC
+:20E9400092B25043326933691204920C9BB2594329DF002812D102210FE0084628DF00286A
+:20E960000CD10399002901D0032106E00499002916D12978042946D017E0216105B0F0BDAE
+:20E980007069326992B25043326993B24B4301461846039A29DF0028F0D10499002901D0F4
+:20E9A0000421EAE72978042920D00521E5E773693069366980B2434368681B189B18B6B2C7
+:20E9C0004E43301880181946049A29DF0028E9D0D4E7306980B24843696880188A08696902
+:20E9E00029DF0028CAD1009900290CD00621C4E77069316989B24843316989B200F0D9FD08
+:20EA000028DF0028BAD10721B7E7F8B5B54918230A780F205A435418241DB3492278266970
+:20EA2000CF68022A1BD001252D07042A2AD0052A5BD1286981B2304600F0BBFD0146A36877
+:20EA400028699A1980B24843101A820860681818861928694B1C80B25843801B34E0B8023C
+:20EA600062686169121A0918A3683018181801239B029A4202D2920829DF31E0FF220132BA
+:20EA800029DF2DE0E268974914205043F4314018001D0BC8B04203D160685943814218D02E
+:20EAA000022A16D0286981B2304600F082FD0146286980B24843301A820828694B1C80B208
+:20EAC000584363689B19C01A83082046FFF717FF06E0286981B2304600F06BFDC01928DFED
+:20EAE000002802D17F4901228A70F8BDF8B57D4C069E65780A2D1DD027787D19EDB20A2D5B
+:20EB000001D30A3DEDB218277D432D192871AA6103C9EE60AB6069612861A1780020002978
+:20EB200004D1FFF772FF112800D100206178491C6170F8BD0420F8BD38B5024669481823B1
+:20EB400001785943081803690179022B0AD014246343644CF434E4588368009383691030F7
+:20EB6000A04738BD604B14331C68F5E7F8B55D4B9978012914D100255B499D700A69082A77
+:20EB800005D002280FD003280AD10D2006E0022807D00D7000F025FA002801D0FFF7CCFF37
+:20EBA000F8BD0D61F6E74F48182403784E496343CC681818641C001DCC600378022B05D11F
+:20EBC0004668A102B14201D3012700E00027052B01D1072A03D00021042B02D003E00121C1
+:20EBE000FAE7072A03D00026042B02D007E00126FAE74068A302834201D3002A1AD0002000
+:20EC0000314301433943C5D0374E28463561FFF793FF344C2078FFF765FEF5606078401E1E
+:20EC200060702078401CC0B220700A28B2D30A382070AFE70120E3E770B500252A4C2948D3
+:20EC4000E56025610570457085702E463046FFF749FE761C0A2EF9D3012212076560516952
+:20EC600028461269491E92B25143E560A1601D49F4310D608D600D61CD601B4914310D6090
+:20EC8000888001212170206170BDF8B5164A044610780E46002830D0002C30D0002E2ED058
+:20ECA000206800282BD0012000076768016989B28F4228D8102F26D3A168002923D09568E2
+:20ECC000794343694A19006980B243439A421AD801200007006980B2814212D901200007E1
+:20ECE000006903E0E82D0020A828002080B2394600F05FFC002906D103E00820F8BD0E20B9
+:20ED0000F8BDB80701D00720F8BDBD49486801281CD00F461421BB4A21C641438E18756092
+:20ED2000236853506168B160A168F160A268616800235143012212075B1C14699BB2A4B214
+:20ED40008C4205D21469A4B2091B02E00420F8BD00211469A4B265191469A4B28C42EBD985
+:20ED6000BD60401C336178600020F8BDF8B50446A3481E46007815460F46002807D0002F3D
+:20ED800007D0002C05D02068002817D103E00820F8BD0E20F8BD9B48016800290ED0C268E3
+:20EDA000816840684A4310186268904206D9002D04D0A94202D3A819884201D90720F8BD90
+:20EDC000384600F008F9002811D0304600F003F900280CD0606800F0FEF8002807D02B4637
+:20EDE0003A46214602200096FFF780FEF8BD1020F8BDFFB5824881B000781F4616460D462B
+:20EE0000002808D0002D08D00198002805D02868002817D103E00820B0E50E20AEE5794C91
+:20EE2000206800280ED0E168A0686268414389186A68914206D9002E04D0B04202D3F119AD
+:20EE4000814201D9072099E5019800F0C4F800281BD0384600F0BFF8002816D0686800F025
+:20EE6000BAF8002811D068683246C119019800F02EFB00962868142148432458002203215B
+:20EE80002846019BA047002078E5102076E5F8B505465B480F460078002805D0002D05D012
+:20EEA0002868002821D103E00820F8BD0E20F8BD544C00262068002817D0A168E0684843CC
+:20EEC00061684118686881420FD900F084F800280DD0296814225143091968684A68896834
+:20EEE000801A00F066FB002903D00720F8BD1020F8BD3B460022294604200096FFF7F6FDB5
+:20EF0000F8BD3F4A1278002A0DD000280DD000290BD00268002A08D0394A14321368002B3E
+:20EF200005D004207047082070470E20704702230B600068106000207047F8B504463048AF
+:20EF40001E46007817460D46002807D0002D07D0002C05D0206802281BD103E00820F8BDC3
+:20EF60000E20F8BD264814300068002811D0084600F031F800280ED0304600F02CF800286C
+:20EF800009D03B462A46214602200096FFF7AEFDF8BD0720F8BD1020F8BD08B5184A1278C8
+:20EFA000002A05D0002805D00268022A11D103E0082008BD0E2008BD114A14321268002AD5
+:20EFC00007D00B460022014604200092FFF78EFD08BD072008BD800701D000207047012068
+:20EFE0007047084910B5F43949780020002906D0FFF70BFD002802D0112800D1002010BD48
+:20F00000A8280020DC2E002070B500250C290ED304464318008941000919581A0A38C2B2BD
+:20F020001748022A027002D30A318B4201D2092070BD144800F04BFA134914480A8882422E
+:20F0400002D02388934217D14988814202D06088884211D10D4A0323521E20891B03A842DE
+:20F060000AD9690009194989914203D09E896D1CB142F4D1002070BD0B2070BD00207047C6
+:20F08000C4280020F02E002080100010FFFF000010B5FDF7ABF810BD10B50446002A02D054
+:20F0A0001088002210E00A48FBE7030A00020343A05C584003061B0F43401803584083B2EB
+:20F0C0001806C00C5840521C8A42EED310BD0000FFFF00004B48002101704C484A4A026039
+:20F0E0008160C160016108224161426081610846704710B500291DD000220A60434A5368A8
+:20F10000002B1BD0202817D85B1E5360D0682423401CD060106914684343E3180B60012366
+:20F1200083409169401C19434007400F91611061002010BD0E2010BD0C2010BD042010BD8F
+:20F14000F0B5324A0646916800292BD057691020791A4907490F14680B4624254D436519D6
+:20F16000B54206D1012495698C4065400020956104E0491C4907490F8F42EED1491C4E07DC
+:20F18000760F956901210C469C402B4623420AD19368002B07D05B1E936053685B1C53609D
+:20F1A0003346F0E70420F0BD184A2423117C1268491E4907490F594320315050002070470B
+:20F1C00070B500281AD0002918D0104AD368002B16D05B1ED360936824265B1C936053692A
+:20F1E00015681C467343EE1820330660E858641C08606007400F5061002070BD0E2070BD84
+:20F20000042070BDC5280020FC2E00201C30002030B5CB0008339DB293070024002B01D0E6
+:20F22000072030BD3B4B9A605219DA605C701C7058809980002030BDF7B5364C0E466088D5
+:20F24000814237D8344F00F069F822786078A188884201DA401C00E00020C0B2904202D155
+:20F2600000F062F824E065786078884201DA401C00E00020607000F057F8BD4218D0A0688C
+:20F28000EF000299C151009900290CD0002E0AD0608832464543E068281800F018F9A068B3
+:20F2A0003818868002E00021381881800020FEBD0420FEBD0920FEBD0EB504E068468188A8
+:20F2C000029A0098904702AA01A9684600F003F80028F3D00EBD70B50E4B05241D785E786C
+:20F2E000AE4215D01D781C789E88B44201DA641C00E000241C705C88DE686C43A41904600F
+:20F300009B68E800C418A4880C80185800241060204670BDCC280020FFFF000072B606484F
+:20F320000168491C0160704703490868401E086000D162B670470000DC280020BFF34F8F11
+:20F3400003490248C860BFF34F8FFEE70400FA0500ED00E010B5002904D000221146104619
+:20F36000FFF7ECFF00F010F810BD10B50021024A0846FFF761FF10BD55F3030010B50846E6
+:20F380001146FCF771FF10BDF8B5384C2078002837D02069002807D00026E068002805D0FB
+:20F3A0000025002E04D013E00126F6E70125F8E7684651DF052806D0002806D000221146D2
+:20F3C000FFF7BCFF04E0012602E0216900988847002D12D1608869460880A06861DF0528FA
+:20F3E00006D0002806D000221146FFF7A7FF04E0012502E0E168A0688847002ED8D0002D15
+:20F40000CFD0F8BD70B5002901D08C0701D0072070BD164C0125A16062801549636010DF46
+:20F420000028F5D1257016202EDF70BD002803D00E49C860002070470E207047002803D0A8
+:20F440000A490861002070470E20704710B507484068002807D08047002803D0002211463E
+:20F46000FFF76CFF10BDFFF78FFF10BDE02800207DF30300034610B50B439B070FD1042A66
+:20F480000DD308C810C9121FA342F8D018BA21BA884201D9012010BD0020C04310BD002AAC
+:20F4A00003D0D30703D0521C07E0002010BD03780C78401C491C1B1B07D103780C78401C61
+:20F4C000491C1B1B01D1921EF1D1184610BDF8B5042A2CD3830712D00B78491C0370401C25
+:20F4E000521E83070BD00B78491C0370401C521E830704D00B78491C0370401C521E8B07F9
+:20F500009B0F05D0C91ADF002023DE1B08C90AE0FCF78EFEF8BD1D4608C9FD401C46B440B8
+:20F520002C4310C0121F042AF5D2F308C91A521EF0D40B78491C0370401C521EEAD40B78EC
+:20F54000491C0370401C521EE4D409780170F8BD01E004C0091F0429FBD28B0701D50280F7
+:20F56000801CC90700D00270704700290BD0C30702D00270401C491E022904D3830702D5EE
+:20F580000280801C891EE3E70022EEE70022DFE70378C2781946437812061B0219438378A2
+:20F5A000C0781B04194311430902090A000608437047002203098B422CD3030A8B4211D366
+:20F5C00000239C464EE003460B433CD4002243088B4231D303098B421CD3030A8B4201D39D
+:20F5E00094463FE0C3098B4201D3CB01C01A524183098B4201D38B01C01A524143098B422D
+:20F6000001D34B01C01A524103098B4201D30B01C01A5241C3088B4201D3CB00C01A524193
+:20F6200083088B4201D38B00C01A524143088B4201D34B00C01A5241411A00D201465241FB
+:20F64000104670475DE0CA0F00D04942031000D34042534000229C4603098B422DD3030A47
+:20F660008B4212D3FC22890112BA030A8B420CD3890192118B4208D3890192118B4204D305
+:20F6800089013AD0921100E08909C3098B4201D3CB01C01A524183098B4201D38B01C01A88
+:20F6A000524143098B4201D34B01C01A524103098B4201D30B01C01A5241C3088B4201D37F
+:20F6C000CB00C01A524183088B4201D38B00C01A5241D9D243088B4201D34B00C01A52417F
+:20F6E000411A00D20146634652415B10104601D34042002B00D54942704763465B1000D31A
+:20F70000404201B50020C046C04602BD704770477047754600F022F8AE460500694653469B
+:20F72000C008C000854618B020B5FEF7FBFA60BC00274908B6460026C0C5C0C5C0C5C0C525
+:20F74000C0C5C0C5C0C5C0C5403D49008D4670470446C046C0462046FCF7FFFC004870479C
+:20F760003830002001491820ABBEFEE726000200704730B47446641E2578641CAB4200D256
+:20F780001D46635D5B00E31830BC184702000000000000000000000000000000040000009F
+:20F7A000000000000000000000000000000000000000000035C4030000000000000000004D
+:20F7C000020000000000000000000000000000000000000000000000030000000000000024
+:20F7E0000000000005000000000000000000000000000000000000000000000023D1BCEA6A
+:20F800005F782315DEEF1212000000002CF8030000280020F400000004C1030020F90300A1
+:20F82000F4280020A413000020C103000000000000000000000000000000000000000000F1
+:20F840000000000000000000000000000000000000000000000000000000000000000000A8
+:20F8600000000000000000000000FFFF000000003200000000000000000000000000000058
+:20F88000000000000000000000000000000000000000000000000000000000000000000068
+:20F8A000000000000000000000000000000000000024F40000000000000000000000000030
+:20F8C000000000000000000000000000000000000000000000000000000000000000000028
+:20F8E000000000000000000000000000000000000000000000000000000000000000000008
+:20F900000000000000000000000000000000000000000000000000000000000000000000E7
+:20FC00000100000000000000FE0000000000000000000000000000000000000000000000E5
+:020000041000EA
+:0410140000C0030015
+:040000050003C0C173
+:00000001FF
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/softdevice_nrf51822_licence_agreement.txt b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/softdevice_nrf51822_licence_agreement.txt
new file mode 100644
index 0000000000..8e447f4c64
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/bootloader/softdevice_nrf51822_licence_agreement.txt
@@ -0,0 +1,30 @@
+/*
+ * S110/S120/S130 License Agreement
+ *
+ * Copyright (c) 2015, Nordic Semiconductor ASA, All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * • Redistributions must reproduce the above copyright notice and the following
+ *   disclaimer in the documentation and/or other materials provided with the
+ *   distribution.
+ * • Neither the name of the copyright holder nor the names of its contributors
+ *   may be used to endorse or promote products derived from this software
+ *   without specific prior written permission.
+ * • No reverse engineering, decompilation, or disassembly of this software is
+ *   permitted.
+ *
+ * DISCLAIMER.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * /
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/module.json b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/module.json
new file mode 100644
index 0000000000..b45b894f0e
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/module.json
@@ -0,0 +1,36 @@
+{
+  "name": "ble-nrf51822",
+  "version": "2.7.1",
+  "description": "Nordic stack and drivers for the mbed BLE API.",
+  "keywords": [
+    "Bluetooth",
+    "BLE",
+    "mbed",
+    "mbed-official"
+  ],
+  "author": "Rohit Grover",
+  "repository": {
+    "url": "git@github.com:ARMmbed/ble-nRF51822.git",
+    "type": "git"
+  },
+  "homepage": "https://developer.mbed.org/teams/Nordic-Semiconductor/",
+  "licenses": [
+    {
+      "url": "https://spdx.org/licenses/Apache-2.0",
+      "type": "Apache-2.0"
+    },
+    {
+      "type": "LicenseRef-softdevice_nrf51822_licence_agreement.txt"
+    }
+  ],
+  "dependencies": {
+    "ble": "^2.6.0",
+    "nrf51-sdk": "^2.4.0"
+  },
+  "extraIncludes": [
+    "source/btle",
+    "source/btle/custom",
+    "source/common"
+  ],
+  "targetDependencies": {}
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/softdevice_nrf51822_licence_agreement.txt b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/softdevice_nrf51822_licence_agreement.txt
new file mode 100644
index 0000000000..8e447f4c64
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/softdevice_nrf51822_licence_agreement.txt
@@ -0,0 +1,30 @@
+/*
+ * S110/S120/S130 License Agreement
+ *
+ * Copyright (c) 2015, Nordic Semiconductor ASA, All rights reserved.
+ *
+ * Redistribution. Redistribution and use in binary form, without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * • Redistributions must reproduce the above copyright notice and the following
+ *   disclaimer in the documentation and/or other materials provided with the
+ *   distribution.
+ * • Neither the name of the copyright holder nor the names of its contributors
+ *   may be used to endorse or promote products derived from this software
+ *   without specific prior written permission.
+ * • No reverse engineering, decompilation, or disassembly of this software is
+ *   permitted.
+ *
+ * DISCLAIMER.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * /
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp
new file mode 100644
index 0000000000..cbd8d33051
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.cpp
@@ -0,0 +1,278 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "common/common.h"
+#include "nordic_common.h"
+
+#include "btle.h"
+#include "btle_clock.h"
+
+#include "ble_flash.h"
+#include "ble_conn_params.h"
+
+#include "btle_gap.h"
+#include "btle_advertising.h"
+#include "custom/custom_helper.h"
+
+#include "ble/GapEvents.h"
+#include "nRF5xn.h"
+
+extern "C" {
+#include "pstorage.h"
+#include "device_manager.h"
+#include "softdevice_handler.h"
+#include "ble_stack_handler_types.h"
+}
+
+#include "nrf_ble_hci.h"
+#include "btle_discovery.h"
+
+#include "nRF5xGattClient.h"
+#include "nRF5xServiceDiscovery.h"
+#include "nRF5xCharacteristicDescriptorDiscoverer.h"
+
+bool isEventsSignaled = false;
+
+extern "C" void assert_nrf_callback(uint16_t line_num, const uint8_t *p_file_name);
+void            app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t *p_file_name);
+
+static void btle_handler(ble_evt_t *p_ble_evt);
+
+#if 0
+#define CENTRAL_LINK_COUNT    (YOTTA_CFG_NORDIC_BLE_CENTRAL_LINKS)  /**<number of central links used by the application. When changing this number remember to adjust the RAM settings */
+                                                                       /** If value for YOTTA_CFG_NORDIC_BLE_PERIPHERAL_LINKS was used, ram settings are adjusted by the yotta target module. */
+#define PERIPHERAL_LINK_COUNT (YOTTA_CFG_NORDIC_BLE_PERIPHERAL_LINKS)     /**<number of peripheral links used by the application. When changing this number remember to adjust the RAM settings*/
+                                                                       /** If value for YOTTA_CFG_NORDIC_BLE_CENTRAL_LINKS was used, ram settings are adjusted by the yotta target module. */
+#define GATTS_ATTR_TAB_SIZE (YOTTA_CFG_NORDIC_BLE_GATTS_ATTR_TAB_SIZE) /**< GATTS attribite table size. */
+                                                                       /** If value for YOTTA_CFG_NORDIC_BLE_GATTS_ATTR_TAB_SIZE was used, ram settings are adjusted by the yotta target module. */
+#else
+#define CENTRAL_LINK_COUNT    3  /**<number of central links used by the application. When changing this number remember to adjust the RAM settings */
+                                                                       /** If value for YOTTA_CFG_NORDIC_BLE_PERIPHERAL_LINKS was used, ram settings are adjusted by the yotta target module. */
+#define PERIPHERAL_LINK_COUNT 1     /**<number of peripheral links used by the application. When changing this number remember to adjust the RAM settings*/
+                                                                       /** If value for YOTTA_CFG_NORDIC_BLE_CENTRAL_LINKS was used, ram settings are adjusted by the yotta target module. */
+#define GATTS_ATTR_TAB_SIZE 0x600 /**< GATTS attribite table size. */
+                                                                       /** If value for YOTTA_CFG_NORDIC_BLE_GATTS_ATTR_TAB_SIZE was used, ram settings are adjusted by the yotta target module. */
+
+#endif
+
+static void sys_evt_dispatch(uint32_t sys_evt)
+{
+    pstorage_sys_event_handler(sys_evt);
+}
+
+/**
+ * This function is called in interrupt context to handle BLE events; i.e. pull
+ * system and user events out of the pending events-queue of the BLE stack. The
+ * BLE stack signals the availability of events by the triggering the SWI2
+ * interrupt, which forwards the handling to this function.
+ *
+ * The event processing loop is implemented in intern_softdevice_events_execute().
+ *
+ * This function will signal to the user code by calling signalEventsToProcess
+ * that their is events to process and BLE::processEvents should be called.
+ */
+static uint32_t signalEvent()
+{
+    if(isEventsSignaled == false) {
+        isEventsSignaled = true;
+        nRF5xn::Instance(BLE::DEFAULT_INSTANCE).signalEventsToProcess(BLE::DEFAULT_INSTANCE);
+    }
+    return NRF_SUCCESS;
+}
+
+error_t btle_init(void)
+{
+    nrf_clock_lf_cfg_t clockConfiguration;
+
+    // Configure the LF clock according to values provided by btle_clock.h.
+    // It is input from the chain of the yotta configuration system.
+    clockConfiguration.source        = LFCLK_CONF_SOURCE;
+    clockConfiguration.xtal_accuracy = LFCLK_CONF_ACCURACY;
+    clockConfiguration.rc_ctiv       = LFCLK_CONF_RC_CTIV;
+    clockConfiguration.rc_temp_ctiv  = LFCLK_CONF_RC_TEMP_CTIV;
+
+    SOFTDEVICE_HANDLER_INIT(&clockConfiguration, signalEvent);
+
+    // Enable BLE stack
+    /**
+     * Using this call, the application can select whether to include the
+     * Service Changed characteristic in the GATT Server. The default in all
+     * previous releases has been to include the Service Changed characteristic,
+     * but this affects how GATT clients behave. Specifically, it requires
+     * clients to subscribe to this attribute and not to cache attribute handles
+     * between connections unless the devices are bonded. If the application
+     * does not need to change the structure of the GATT server attributes at
+     * runtime this adds unnecessary complexity to the interaction with peer
+     * clients. If the SoftDevice is enabled with the Service Changed
+     * Characteristics turned off, then clients are allowed to cache attribute
+     * handles making applications simpler on both sides.
+     */
+    static const bool IS_SRVC_CHANGED_CHARACT_PRESENT = true;
+
+    ble_enable_params_t ble_enable_params;
+    uint32_t err_code = softdevice_enable_get_default_config(CENTRAL_LINK_COUNT,
+                                                    PERIPHERAL_LINK_COUNT,
+                                                    &ble_enable_params);
+
+    ble_enable_params.gatts_enable_params.attr_tab_size  = GATTS_ATTR_TAB_SIZE;
+    ble_enable_params.gatts_enable_params.service_changed  = IS_SRVC_CHANGED_CHARACT_PRESENT;
+    ble_enable_params.common_enable_params.vs_uuid_count = UUID_TABLE_MAX_ENTRIES;
+
+    if(err_code  != NRF_SUCCESS) {
+        return ERROR_INVALID_PARAM;
+    }
+
+    if (softdevice_enable(&ble_enable_params) != NRF_SUCCESS) {
+        return ERROR_INVALID_PARAM;
+    }
+
+    ble_gap_addr_t addr;
+    if (sd_ble_gap_address_get(&addr) != NRF_SUCCESS) {
+        return ERROR_INVALID_PARAM;
+    }
+    if (sd_ble_gap_address_set(BLE_GAP_ADDR_CYCLE_MODE_NONE, &addr) != NRF_SUCCESS) {
+        return ERROR_INVALID_PARAM;
+    }
+
+    ASSERT_STATUS( softdevice_ble_evt_handler_set(btle_handler));
+    ASSERT_STATUS( softdevice_sys_evt_handler_set(sys_evt_dispatch));
+
+    return btle_gap_init();
+}
+
+static void btle_handler(ble_evt_t *p_ble_evt)
+{
+    /* Library service handlers */
+#if SDK_CONN_PARAMS_MODULE_ENABLE
+    ble_conn_params_on_ble_evt(p_ble_evt);
+#endif
+
+    dm_ble_evt_handler(p_ble_evt);
+
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+    bleGattcEventHandler(p_ble_evt);
+#endif
+
+    nRF5xn               &ble             = nRF5xn::Instance(BLE::DEFAULT_INSTANCE);
+    nRF5xGap             &gap             = (nRF5xGap &) ble.getGap();
+    nRF5xGattServer      &gattServer      = (nRF5xGattServer &) ble.getGattServer();
+    nRF5xSecurityManager &securityManager = (nRF5xSecurityManager &) ble.getSecurityManager();
+
+    /* Custom event handler */
+    switch (p_ble_evt->header.evt_id) {
+        case BLE_GAP_EVT_CONNECTED: {
+            Gap::Handle_t handle = p_ble_evt->evt.gap_evt.conn_handle;
+#if defined(TARGET_MCU_NRF51_16K_S110) || defined(TARGET_MCU_NRF51_32K_S110)
+            /* Only peripheral role is supported by S110 */
+            Gap::Role_t role = Gap::PERIPHERAL;
+#else
+            Gap::Role_t role = static_cast<Gap::Role_t>(p_ble_evt->evt.gap_evt.params.connected.role);
+#endif
+            gap.setConnectionHandle(handle);
+            const Gap::ConnectionParams_t *params = reinterpret_cast<Gap::ConnectionParams_t *>(&(p_ble_evt->evt.gap_evt.params.connected.conn_params));
+            const ble_gap_addr_t *peer = &p_ble_evt->evt.gap_evt.params.connected.peer_addr;
+            const ble_gap_addr_t *own  = &p_ble_evt->evt.gap_evt.params.connected.own_addr;
+            gap.processConnectionEvent(handle,
+                                                           role,
+                                                           static_cast<BLEProtocol::AddressType_t>(peer->addr_type), peer->addr,
+                                                           static_cast<BLEProtocol::AddressType_t>(own->addr_type),  own->addr,
+                                                           params);
+            break;
+        }
+
+        case BLE_GAP_EVT_DISCONNECTED: {
+            Gap::Handle_t handle = p_ble_evt->evt.gap_evt.conn_handle;
+            // Since we are not in a connection and have not started advertising,
+            // store bonds
+            gap.setConnectionHandle (BLE_CONN_HANDLE_INVALID);
+
+            Gap::DisconnectionReason_t reason;
+            switch (p_ble_evt->evt.gap_evt.params.disconnected.reason) {
+                case BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION:
+                    reason = Gap::LOCAL_HOST_TERMINATED_CONNECTION;
+                    break;
+                case BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION:
+                    reason = Gap::REMOTE_USER_TERMINATED_CONNECTION;
+                    break;
+                case BLE_HCI_CONN_INTERVAL_UNACCEPTABLE:
+                    reason = Gap::CONN_INTERVAL_UNACCEPTABLE;
+                    break;
+                default:
+                    /* Please refer to the underlying transport library for an
+                     * interpretion of this reason's value. */
+                    reason = static_cast<Gap::DisconnectionReason_t>(p_ble_evt->evt.gap_evt.params.disconnected.reason);
+                    break;
+            }
+
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+            // Close all pending discoveries for this connection
+            nRF5xGattClient& gattClient = ble.getGattClient();
+            gattClient.characteristicDescriptorDiscoverer().terminate(handle, BLE_ERROR_INVALID_STATE);
+            gattClient.discovery().terminate(handle);
+#endif
+
+            gap.processDisconnectionEvent(handle, reason);
+            break;
+        }
+
+        case BLE_GAP_EVT_PASSKEY_DISPLAY:
+            securityManager.processPasskeyDisplayEvent(p_ble_evt->evt.gap_evt.conn_handle, p_ble_evt->evt.gap_evt.params.passkey_display.passkey);
+            break;
+
+        case BLE_GAP_EVT_TIMEOUT:
+            gap.processTimeoutEvent(static_cast<Gap::TimeoutSource_t>(p_ble_evt->evt.gap_evt.params.timeout.src));
+            break;
+
+        case BLE_GATTC_EVT_TIMEOUT:
+        case BLE_GATTS_EVT_TIMEOUT:
+            // Disconnect on GATT Server and Client timeout events.
+            // ASSERT_STATUS_RET_VOID (sd_ble_gap_disconnect(m_conn_handle,
+            // BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION));
+            break;
+
+        case BLE_GAP_EVT_ADV_REPORT: {
+            const ble_gap_evt_adv_report_t *advReport = &p_ble_evt->evt.gap_evt.params.adv_report;
+            gap.processAdvertisementReport(advReport->peer_addr.addr,
+                                           advReport->rssi,
+                                           advReport->scan_rsp,
+                                           static_cast<GapAdvertisingParams::AdvertisingType_t>(advReport->type),
+                                           advReport->dlen,
+                                           advReport->data);
+            break;
+        }
+
+        default:
+            break;
+    }
+
+    gattServer.hwCallback(p_ble_evt);
+}
+
+/*! @brief      Callback when an error occurs inside the SoftDevice */
+void assert_nrf_callback(uint16_t line_num, const uint8_t *p_file_name)
+{
+    ASSERT(false, (void) 0);
+}
+
+/*!
+    @brief      Handler for general errors above the SoftDevice layer.
+                Typically we can' recover from this so we do a reset.
+*/
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t *p_file_name)
+{
+    ASSERT_STATUS_RET_VOID( error_code );
+    NVIC_SystemReset();
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h
new file mode 100644
index 0000000000..2e6fe3d9f7
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle.h
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _BTLE_H_
+#define _BTLE_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "common/common.h"
+
+#include "ble_srv_common.h"
+#include "nrf_ble.h"
+
+error_t     btle_init(void);
+
+// flag indicating if events have been signaled or not
+// It is used by processEvents and signalEventsToProcess
+// signalEventsToProcess raise the flag and processEvents
+// clears it.
+extern bool isEventsSignaled;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // ifndef _BTLE_H_
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.cpp
new file mode 100644
index 0000000000..cdaf6a4a49
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.cpp
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "common/common.h"
+
+#include "ble_advdata.h"
+#include "btle.h"
+
+/**************************************************************************/
+/*!
+    @brief      Starts the advertising process
+
+    @returns
+*/
+/**************************************************************************/
+error_t btle_advertising_start(void)
+{
+    ble_gap_adv_params_t adv_para = {0};
+
+    /* Set the default advertising parameters */
+    adv_para.type        = BLE_GAP_ADV_TYPE_ADV_IND;
+    adv_para.p_peer_addr = NULL; /* Undirected advertising */
+    adv_para.fp          = BLE_GAP_ADV_FP_ANY;
+    adv_para.p_whitelist = NULL;
+    adv_para.interval    = (CFG_GAP_ADV_INTERVAL_MS * 8) / 5; /* Advertising
+                                                               * interval in
+                                                               * units of 0.625
+                                                               * ms */
+    adv_para.timeout     = CFG_GAP_ADV_TIMEOUT_S;
+
+    ASSERT_STATUS( sd_ble_gap_adv_start(&adv_para));
+
+    return ERROR_NONE;
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.h
new file mode 100644
index 0000000000..a215153ab5
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_advertising.h
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _BTLE_ADVERTISING_H_
+#define _BTLE_ADVERTISING_H_
+
+#include "common/common.h"
+
+error_t btle_advertising_start(void);
+
+#endif // ifndef _BTLE_ADVERTISING_H_
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_clock.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_clock.h
new file mode 100644
index 0000000000..6a6a530c3e
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_clock.h
@@ -0,0 +1,130 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef _BTLE_CLOCK_H_
+#define _BTLE_CLOCK_H_
+
+#include "nrf5x_lf_clk_helper.h"
+
+/**
+ * @brief Module that generates settings for the low-frequency (LF) clock configuration.
+ *
+ * This module provides macros that are generated from the mbed config system macros.
+ *
+ *
+ *
+ * As a result, this module provides the following: @n
+ * - literal value LFCLK_CONF_SOURCE @n
+ * - literal value LFCLK_CONF_ACCURACY @n
+ * - literal value LFCLK_CONF_RC_CTIV @n
+ * - literal value LFCLK_CONF_RC_TEMP_CTIV
+ */
+
+
+
+#include "nrf_sdm.h"
+
+#define DEFAULT_LFCLK_CONF_ACCURACY NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM
+
+#ifdef NRF52
+    #define MAX_LFCLK_CONF_RC_CTIV    32
+#else
+    #define MAX_LFCLK_CONF_RC_CTIV    64
+#endif
+
+#define MAX_LFCLK_CONF_RC_TEMP_CTIV   33
+
+#define DEFAULT_LFCLK_CONF_RC_CTIV 16     // Check temperature every 16 * 250ms.
+#define DEFAULT_LFCLK_CONF_RC_TEMP_CTIV 1 // Only calibrate if temperature has changed.
+
+
+#if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC
+    #define LFCLK_CONF_SOURCE       NRF_CLOCK_LF_SRC_RC
+    
+    #ifdef MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL
+        #define LFCLK_CONF_RC_CTIV MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL
+    #else
+        #define LFCLK_CONF_RC_CTIV DEFAULT_LFCLK_CONF_RC_CTIV
+    #endif
+    
+    #ifdef MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG
+        #define LFCLK_CONF_RC_TEMP_CTIV MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG
+    #else
+        #define LFCLK_CONF_RC_TEMP_CTIV DEFAULT_LFCLK_CONF_RC_TEMP_CTIV
+    #endif
+    
+    #if (LFCLK_CONF_RC_CTIV < 1) || (LFCLK_CONF_RC_CTIV > MAX_LFCLK_CONF_RC_CTIV)
+        #error Calibration timer interval out of range!
+    #endif
+    
+    #if (LFCLK_CONF_RC_TEMP_CTIV < 0 ) || (LFCLK_CONF_RC_TEMP_CTIV > 33)
+        #error Number/mode of LF RC calibration intervals out of range!
+    #endif
+    
+#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH
+    #define LFCLK_CONF_SOURCE       NRF_CLOCK_LF_SRC_SYNTH
+    #define LFCLK_CONF_RC_CTIV      0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+    #define LFCLK_CONF_RC_TEMP_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+    
+    #ifdef MBED_CONF_NORDIC_LF_CLOCK_HF_SYNTH_ACCURACY
+        #define LFCLK_CONF_ACCURACY MBED_CONF_NORDIC_LF_CLOCK_HF_SYNTH_ACCURACY
+    #endif
+    
+#else //  default is NRF_LF_SRC_SYNTH
+    #define LFCLK_CONF_SOURCE NRF_CLOCK_LF_SRC_XTAL
+    #define LFCLK_CONF_RC_CTIV      0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+    #define LFCLK_CONF_RC_TEMP_CTIV 0 // Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+    
+    #ifdef MBED_CONF_NORDIC_LF_CLOCK_XTAL_ACCURACY
+        #define LFCLK_CONF_ACCURACY MBED_CONF_NORDIC_LF_CLOCK_XTAL_ACCURACY
+    #endif
+
+#endif
+
+#ifndef LFCLK_CONF_ACCURACY
+    #define LFCLK_CONF_ACCURACY DEFAULT_LFCLK_CONF_ACCURACY
+#endif
+
+#if (LFCLK_CONF_ACCURACY > NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM) || (LFCLK_CONF_ACCURACY < NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM)
+    #error Low frequency clock accuracy out of range!
+#endif
+
+
+#endif //_BTLE_CLOCK_H_
+
+
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp
new file mode 100644
index 0000000000..e6fb30e613
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.cpp
@@ -0,0 +1,147 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nRF5xServiceDiscovery.h"
+#include "nRF5xCharacteristicDescriptorDiscoverer.h"
+#include "nRF5xGattClient.h"
+#include "nRF5xn.h"
+
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+void bleGattcEventHandler(const ble_evt_t *p_ble_evt)
+{
+    nRF5xn                &ble         = nRF5xn::Instance(BLE::DEFAULT_INSTANCE);
+    nRF5xGap              &gap         = (nRF5xGap &) ble.getGap();
+    nRF5xGattClient       &gattClient  = (nRF5xGattClient &) ble.getGattClient();
+    nRF5xServiceDiscovery &sdSingleton = gattClient.discovery();
+    nRF5xCharacteristicDescriptorDiscoverer &characteristicDescriptorDiscoverer =
+        gattClient.characteristicDescriptorDiscoverer();
+
+    switch (p_ble_evt->header.evt_id) {
+        case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP:
+            switch (p_ble_evt->evt.gattc_evt.gatt_status) {
+                case BLE_GATT_STATUS_SUCCESS:
+                    sdSingleton.setupDiscoveredServices(&p_ble_evt->evt.gattc_evt.params.prim_srvc_disc_rsp);
+                    break;
+
+                case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND:
+                default:
+                    sdSingleton.terminate();
+                    break;
+            }
+            break;
+
+        case BLE_GATTC_EVT_CHAR_DISC_RSP:
+            switch (p_ble_evt->evt.gattc_evt.gatt_status) {
+                case BLE_GATT_STATUS_SUCCESS:
+                    sdSingleton.setupDiscoveredCharacteristics(&p_ble_evt->evt.gattc_evt.params.char_disc_rsp);
+                    break;
+
+                case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND:
+                default:
+                    sdSingleton.terminateCharacteristicDiscovery(BLE_ERROR_NONE);
+                    break;
+            }
+            break;
+
+        case BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP:
+            if (sdSingleton.isActive()) {
+                sdSingleton.processDiscoverUUIDResponse(&p_ble_evt->evt.gattc_evt.params.char_val_by_uuid_read_rsp);
+            }
+            break;
+
+        case BLE_GATTC_EVT_READ_RSP: {
+                GattReadCallbackParams response = {
+                    .connHandle = p_ble_evt->evt.gattc_evt.conn_handle,
+                    .handle     = p_ble_evt->evt.gattc_evt.params.read_rsp.handle,
+                    .offset     = p_ble_evt->evt.gattc_evt.params.read_rsp.offset,
+                    .len        = p_ble_evt->evt.gattc_evt.params.read_rsp.len,
+                    .data       = p_ble_evt->evt.gattc_evt.params.read_rsp.data,
+                };
+                gattClient.processReadResponse(&response);
+            }
+            break;
+
+        case BLE_GATTC_EVT_WRITE_RSP: {
+                GattWriteCallbackParams response = {
+                    .connHandle = p_ble_evt->evt.gattc_evt.conn_handle,
+                    .handle     = p_ble_evt->evt.gattc_evt.params.write_rsp.handle,
+                    .writeOp    = (GattWriteCallbackParams::WriteOp_t)(p_ble_evt->evt.gattc_evt.params.write_rsp.write_op),
+                    .offset     = p_ble_evt->evt.gattc_evt.params.write_rsp.offset,
+                    .len        = p_ble_evt->evt.gattc_evt.params.write_rsp.len,
+                    .data       = p_ble_evt->evt.gattc_evt.params.write_rsp.data,
+                };
+                gattClient.processWriteResponse(&response);
+            }
+            break;
+
+        case BLE_GATTC_EVT_HVX: {
+                GattHVXCallbackParams params;
+                params.connHandle = p_ble_evt->evt.gattc_evt.conn_handle;
+                params.handle     = p_ble_evt->evt.gattc_evt.params.hvx.handle;
+                params.type       = static_cast<HVXType_t>(p_ble_evt->evt.gattc_evt.params.hvx.type);
+                params.len        = p_ble_evt->evt.gattc_evt.params.hvx.len;
+                params.data       = p_ble_evt->evt.gattc_evt.params.hvx.data;
+
+                gattClient.processHVXEvent(&params);
+            }
+            break;
+
+        case BLE_GATTC_EVT_DESC_DISC_RSP: {
+            uint16_t conn_handle = p_ble_evt->evt.gattc_evt.conn_handle;
+            uint16_t status = p_ble_evt->evt.gattc_evt.gatt_status;
+            const ble_gattc_evt_desc_disc_rsp_t& discovered_descriptors = p_ble_evt->evt.gattc_evt.params.desc_disc_rsp;
+
+            switch(status) {
+                case BLE_GATT_STATUS_SUCCESS:
+                    characteristicDescriptorDiscoverer.process(
+                        conn_handle,
+                        discovered_descriptors
+                    );
+                    break;
+                case BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND:
+                    // end of discovery
+                    characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_NONE);
+                    break;
+                default:
+                    characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_UNSPECIFIED);
+                    break;
+            }
+        }   break;
+
+        case BLE_GATTC_EVT_ATTR_INFO_DISC_RSP : {
+            uint16_t conn_handle = p_ble_evt->evt.gattc_evt.conn_handle;
+            uint16_t status = p_ble_evt->evt.gattc_evt.gatt_status;
+            const ble_gattc_evt_attr_info_disc_rsp_t& infos = p_ble_evt->evt.gattc_evt.params.attr_info_disc_rsp;
+
+            switch(status) {
+                case BLE_GATT_STATUS_SUCCESS:
+                    characteristicDescriptorDiscoverer.processAttributeInformation(
+                        conn_handle,
+                        infos
+                    );
+                    break;
+                default:
+                    characteristicDescriptorDiscoverer.terminate(conn_handle, BLE_ERROR_UNSPECIFIED);
+                    break;
+            }
+
+        } break;
+    }
+
+    sdSingleton.progressCharacteristicDiscovery();
+    sdSingleton.progressServiceDiscovery();
+}
+#endif
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h
new file mode 100644
index 0000000000..9b7613e782
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_discovery.h
@@ -0,0 +1,22 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _BTLE_DISCOVERY_H_
+#define _BTLE_DISCOVERY_H_
+
+void bleGattcEventHandler(const ble_evt_t *p_ble_evt);
+
+#endif /*_BTLE_DISCOVERY_H_*/
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp
new file mode 100644
index 0000000000..5dbc372135
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.cpp
@@ -0,0 +1,99 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "common/common.h"
+
+#include "nrf_ble_gap.h"
+#include "ble_conn_params.h"
+
+static inline uint32_t msec_to_1_25msec(uint32_t interval_ms) ATTR_ALWAYS_INLINE ATTR_CONST;
+#if SDK_CONN_PARAMS_MODULE_ENABLE
+static void   error_callback(uint32_t nrf_error);
+#endif // SDK_CONN_PARAMS_MODULE_ENABLE
+
+/**************************************************************************/
+/*!
+    @brief      Initialise GAP in the underlying SoftDevice
+
+    @returns
+*/
+/**************************************************************************/
+error_t btle_gap_init(void)
+{
+    ble_gap_conn_params_t gap_conn_params = {0};
+
+    gap_conn_params.min_conn_interval = msec_to_1_25msec(CFG_GAP_CONNECTION_MIN_INTERVAL_MS);  // in 1.25ms units
+    gap_conn_params.max_conn_interval = msec_to_1_25msec(CFG_GAP_CONNECTION_MAX_INTERVAL_MS);  // in 1.25ms unit
+    gap_conn_params.slave_latency     = CFG_GAP_CONNECTION_SLAVE_LATENCY;
+    gap_conn_params.conn_sup_timeout  = CFG_GAP_CONNECTION_SUPERVISION_TIMEOUT_MS / 10; // in 10ms unit
+
+    ble_gap_conn_sec_mode_t sec_mode;
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); // no security is needed
+
+    ASSERT_STATUS( sd_ble_gap_device_name_set(&sec_mode, (const uint8_t *) CFG_GAP_LOCAL_NAME, strlen(CFG_GAP_LOCAL_NAME)));
+    ASSERT_STATUS( sd_ble_gap_appearance_set(CFG_GAP_APPEARANCE));
+    ASSERT_STATUS( sd_ble_gap_ppcp_set(&gap_conn_params));
+    ASSERT_STATUS( sd_ble_gap_tx_power_set(CFG_BLE_TX_POWER_LEVEL));
+
+    /**
+     * Call to conn_params_init() is not necessary; and so is disabled by default.
+     * This API should be exposed to the user to be invoked when necessary.
+     */
+#if SDK_CONN_PARAMS_MODULE_ENABLE
+    /* Connection Parameters */
+    enum {
+        FIRST_UPDATE_DELAY = APP_TIMER_TICKS(5000, CFG_TIMER_PRESCALER),
+        NEXT_UPDATE_DELAY  = APP_TIMER_TICKS(5000, CFG_TIMER_PRESCALER),
+        MAX_UPDATE_COUNT   = 3
+    };
+
+    ble_conn_params_init_t cp_init = {0};
+
+    cp_init.p_conn_params                  = NULL;
+    cp_init.first_conn_params_update_delay = FIRST_UPDATE_DELAY;
+    cp_init.next_conn_params_update_delay  = NEXT_UPDATE_DELAY;
+    cp_init.max_conn_params_update_count   = MAX_UPDATE_COUNT;
+    cp_init.start_on_notify_cccd_handle    = BLE_GATT_HANDLE_INVALID;
+    cp_init.disconnect_on_fail             = true;
+    cp_init.evt_handler                    = NULL;
+    cp_init.error_handler                  = error_callback;
+
+    ASSERT_STATUS ( ble_conn_params_init(&cp_init));
+#endif // SDK_CONN_PARAMS_MODULE_ENABLE
+
+    return ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief      Converts msecs to an integer representing 1.25ms units
+
+    @param[in]  ms
+                The number of milliseconds to conver to 1.25ms units
+
+    @returns    The number of 1.25ms units in the supplied number of ms
+*/
+/**************************************************************************/
+static inline uint32_t msec_to_1_25msec(uint32_t interval_ms)
+{
+    return (interval_ms * 4) / 5;
+}
+
+#if SDK_CONN_PARAMS_MODULE_ENABLE
+static void error_callback(uint32_t nrf_error)
+{
+    ASSERT_STATUS_RET_VOID( nrf_error );
+}
+#endif // SDK_CONN_PARAMS_MODULE_ENABLE
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.h
new file mode 100644
index 0000000000..828da3cd78
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_gap.h
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _BTLE_GAP_H_
+#define _BTLE_GAP_H_
+
+#include "common/common.h"
+
+error_t btle_gap_init(void);
+
+#endif // ifndef _BTLE_GAP_H_
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.cpp
new file mode 100644
index 0000000000..e7f176cad3
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.cpp
@@ -0,0 +1,325 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "btle.h"
+
+#include "nRF5xn.h"
+
+extern "C" {
+#include "pstorage.h"
+#include "device_manager.h"
+#include "id_manager.h"
+}
+
+#include "btle_security.h"
+
+static dm_application_instance_t applicationInstance;
+static bool                      initialized = false;
+static ret_code_t dm_handler(dm_handle_t const *p_handle, dm_event_t const *p_event, ret_code_t event_result);
+
+// default security parameters. Avoid "holes" between member assigments in order to compile by gcc++11.
+static ble_gap_sec_params_t securityParameters = {
+    .bond          = true,         /**< Perform bonding. */
+    .mitm          = true,         /**< Man In The Middle protection required. */
+    .lesc          = false,        /**< Enable LE Secure Connection pairing. */
+    .keypress      = false,        /**< Enable generation of keypress notifications. */
+    .io_caps       = SecurityManager::IO_CAPS_NONE, /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */
+    .oob           = 0,            /**< Out Of Band data available. */
+    .min_key_size  = 16,           /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */
+    .max_key_size  = 16,           /**< Maximum encryption key size in octets between min_key_size and 16. */
+    .kdist_own  = {
+      .enc  = 0,                   /**< Long Term Key and Master Identification. */
+      .id   = 0,                   /**< Identity Resolving Key and Identity Address Information. */
+      .sign = 0,                   /**< Connection Signature Resolving Key. */
+      .link = 0                    /**< Derive the Link Key from the LTK. */
+    },                             /**< Key distribution bitmap: keys that the local device will distribute. */
+    .kdist_peer  = {
+      .enc  = 1,                   /**< Long Term Key and Master Identification. */
+      .id   = 1,                   /**< Identity Resolving Key and Identity Address Information. */
+      .sign = 1,                   /**< Connection Signature Resolving Key. */
+      .link = 0                    /**< Derive the Link Key from the LTK. */
+    }                              /**< Key distribution bitmap: keys that the peripheral device will distribute. */
+};
+
+bool
+btle_hasInitializedSecurity(void)
+{
+    return initialized;
+}
+
+ble_error_t
+btle_initializeSecurity(bool                                      enableBonding,
+                        bool                                      requireMITM,
+                        SecurityManager::SecurityIOCapabilities_t iocaps,
+                        const SecurityManager::Passkey_t          passkey)
+{
+    /* guard against multiple initializations */
+    if (initialized) {
+        return BLE_ERROR_NONE;
+    }
+
+    if (pstorage_init() != NRF_SUCCESS) {
+        return BLE_ERROR_UNSPECIFIED;
+    }
+
+    ret_code_t rc;
+    if (passkey) {
+        ble_opt_t opts;
+        opts.gap_opt.passkey.p_passkey = const_cast<uint8_t *>(passkey);
+        if ((rc = sd_ble_opt_set(BLE_GAP_OPT_PASSKEY, &opts)) != NRF_SUCCESS) {
+            switch (rc) {
+                case BLE_ERROR_INVALID_CONN_HANDLE:
+                case NRF_ERROR_INVALID_ADDR:
+                case NRF_ERROR_INVALID_PARAM:
+                default:
+                    return BLE_ERROR_INVALID_PARAM;
+                case NRF_ERROR_INVALID_STATE:
+                    return BLE_ERROR_INVALID_STATE;
+                case NRF_ERROR_BUSY:
+                    return BLE_STACK_BUSY;
+            }
+        }
+    }
+
+    dm_init_param_t dm_init_param = {
+        .clear_persistent_data = false /* Set to true in case the module should clear all persistent data. */
+    };
+    if (dm_init(&dm_init_param) != NRF_SUCCESS) {
+        return BLE_ERROR_UNSPECIFIED;
+    }
+
+    // update default security parameters with function call parameters
+    securityParameters.bond = enableBonding;
+    securityParameters.mitm = requireMITM;
+    securityParameters.io_caps = iocaps;
+
+    const dm_application_param_t dm_param = {
+        .evt_handler  = dm_handler,
+        .service_type = DM_PROTOCOL_CNTXT_GATT_CLI_ID,
+        .sec_param    = securityParameters
+    };
+
+    if ((rc = dm_register(&applicationInstance, &dm_param)) != NRF_SUCCESS) {
+        switch (rc) {
+            case NRF_ERROR_INVALID_STATE:
+                return BLE_ERROR_INVALID_STATE;
+            case NRF_ERROR_NO_MEM:
+                return BLE_ERROR_NO_MEM;
+            default:
+                return BLE_ERROR_UNSPECIFIED;
+        }
+    }
+
+    initialized = true;
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t
+btle_purgeAllBondingState(void)
+{
+    ret_code_t rc;
+    if ((rc = dm_device_delete_all(&applicationInstance)) == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    }
+
+    switch (rc) {
+        case NRF_ERROR_INVALID_STATE:
+            return BLE_ERROR_INVALID_STATE;
+        case NRF_ERROR_NO_MEM:
+            return BLE_ERROR_NO_MEM;
+        default:
+            return BLE_ERROR_UNSPECIFIED;
+    }
+}
+
+ble_error_t
+btle_getLinkSecurity(Gap::Handle_t connectionHandle, SecurityManager::LinkSecurityStatus_t *securityStatusP)
+{
+    ret_code_t rc;
+    dm_handle_t dmHandle = {
+        .appl_id = applicationInstance,
+    };
+    if ((rc = dm_handle_get(connectionHandle, &dmHandle)) != NRF_SUCCESS) {
+        if (rc == NRF_ERROR_NOT_FOUND) {
+            return BLE_ERROR_INVALID_PARAM;
+        } else {
+            return BLE_ERROR_UNSPECIFIED;
+        }
+    }
+
+    if ((rc = dm_security_status_req(&dmHandle, reinterpret_cast<dm_security_status_t *>(securityStatusP))) != NRF_SUCCESS) {
+        switch (rc) {
+            case NRF_ERROR_INVALID_STATE:
+                return BLE_ERROR_INVALID_STATE;
+            case NRF_ERROR_NO_MEM:
+                return BLE_ERROR_NO_MEM;
+            default:
+                return BLE_ERROR_UNSPECIFIED;
+        }
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t
+btle_setLinkSecurity(Gap::Handle_t connectionHandle, SecurityManager::SecurityMode_t securityMode)
+{
+    // use default and updated parameters as starting point
+    // and modify structure based on security mode.
+    ble_gap_sec_params_t params = securityParameters;
+
+    switch (securityMode) {
+        case SecurityManager::SECURITY_MODE_ENCRYPTION_OPEN_LINK:
+            /**< Require no protection, open link. */
+            securityParameters.bond = false;
+            securityParameters.mitm = false;
+            break;
+
+        case SecurityManager::SECURITY_MODE_ENCRYPTION_NO_MITM:
+            /**< Require encryption, but no MITM protection. */
+            securityParameters.bond = true;
+            securityParameters.mitm = false;
+            break;
+
+        // not yet implemented security modes
+        case SecurityManager::SECURITY_MODE_NO_ACCESS:
+        case SecurityManager::SECURITY_MODE_ENCRYPTION_WITH_MITM:
+            /**< Require encryption and MITM protection. */
+        case SecurityManager::SECURITY_MODE_SIGNED_NO_MITM:
+            /**< Require signing or encryption, but no MITM protection. */
+        case SecurityManager::SECURITY_MODE_SIGNED_WITH_MITM:
+            /**< Require signing or encryption, and MITM protection. */
+        default:
+            return BLE_ERROR_NOT_IMPLEMENTED;
+    }
+
+    // update security settings for given connection
+    uint32_t result = sd_ble_gap_authenticate(connectionHandle, &params);
+
+    if (result == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    } else {
+        return BLE_ERROR_UNSPECIFIED;
+    }
+}
+
+ret_code_t
+dm_handler(dm_handle_t const *p_handle, dm_event_t const *p_event, ret_code_t event_result)
+{
+    nRF5xn               &ble             = nRF5xn::Instance(BLE::DEFAULT_INSTANCE);
+    nRF5xSecurityManager &securityManager = (nRF5xSecurityManager &) ble.getSecurityManager();
+
+    switch (p_event->event_id) {
+        case DM_EVT_SECURITY_SETUP: /* started */ {
+            const ble_gap_sec_params_t *peerParams = &p_event->event_param.p_gap_param->params.sec_params_request.peer_params;
+            securityManager.processSecuritySetupInitiatedEvent(p_event->event_param.p_gap_param->conn_handle,
+                                                                                   peerParams->bond,
+                                                                                   peerParams->mitm,
+                                                                                   (SecurityManager::SecurityIOCapabilities_t)peerParams->io_caps);
+            break;
+        }
+        case DM_EVT_SECURITY_SETUP_COMPLETE:
+            securityManager.
+                processSecuritySetupCompletedEvent(p_event->event_param.p_gap_param->conn_handle,
+                                                   (SecurityManager::SecurityCompletionStatus_t)(p_event->event_param.p_gap_param->params.auth_status.auth_status));
+            break;
+        case DM_EVT_LINK_SECURED: {
+            unsigned securityMode                    = p_event->event_param.p_gap_param->params.conn_sec_update.conn_sec.sec_mode.sm;
+            unsigned level                           = p_event->event_param.p_gap_param->params.conn_sec_update.conn_sec.sec_mode.lv;
+            SecurityManager::SecurityMode_t resolvedSecurityMode = SecurityManager::SECURITY_MODE_NO_ACCESS;
+            switch (securityMode) {
+                case 1:
+                    switch (level) {
+                        case 1:
+                            resolvedSecurityMode = SecurityManager::SECURITY_MODE_ENCRYPTION_OPEN_LINK;
+                            break;
+                        case 2:
+                            resolvedSecurityMode = SecurityManager::SECURITY_MODE_ENCRYPTION_NO_MITM;
+                            break;
+                        case 3:
+                            resolvedSecurityMode = SecurityManager::SECURITY_MODE_ENCRYPTION_WITH_MITM;
+                            break;
+                    }
+                    break;
+                case 2:
+                    switch (level) {
+                        case 1:
+                            resolvedSecurityMode = SecurityManager::SECURITY_MODE_SIGNED_NO_MITM;
+                            break;
+                        case 2:
+                            resolvedSecurityMode = SecurityManager::SECURITY_MODE_SIGNED_WITH_MITM;
+                            break;
+                    }
+                    break;
+            }
+
+            securityManager.processLinkSecuredEvent(p_event->event_param.p_gap_param->conn_handle, resolvedSecurityMode);
+            break;
+        }
+        case DM_EVT_DEVICE_CONTEXT_STORED:
+            securityManager.processSecurityContextStoredEvent(p_event->event_param.p_gap_param->conn_handle);
+            break;
+        default:
+            break;
+    }
+
+    return NRF_SUCCESS;
+}
+
+ble_error_t
+btle_createWhitelistFromBondTable(ble_gap_whitelist_t *p_whitelist)
+{
+    if (!btle_hasInitializedSecurity()) {
+        return BLE_ERROR_INITIALIZATION_INCOMPLETE;
+    }
+    ret_code_t err = dm_whitelist_create(&applicationInstance, p_whitelist);
+    if (err == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    } else if (err == NRF_ERROR_NULL) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    } else {
+        return BLE_ERROR_INVALID_STATE;
+    }
+}
+
+
+bool
+btle_matchAddressAndIrk(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk)
+{
+    /*
+     * Use a helper function from the Nordic SDK to test whether the BLE
+     * address can be generated using the IRK.
+     */
+    return im_address_resolve(p_addr, p_irk);
+}
+
+void
+btle_generateResolvableAddress(const ble_gap_irk_t &irk, ble_gap_addr_t &address)
+{
+    /* Set type to resolvable */
+    address.addr_type = BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE;
+
+    /*
+     * Assign a random number to the most significant 3 bytes
+     * of the address.
+     */
+    address.addr[BLE_GAP_ADDR_LEN - 3] = 0x8E;
+    address.addr[BLE_GAP_ADDR_LEN - 2] = 0x4F;
+    address.addr[BLE_GAP_ADDR_LEN - 1] = 0x7C;
+
+    /* Calculate the hash and store it in the top half of the address */
+    ah(irk.irk, &address.addr[BLE_GAP_ADDR_LEN - 3], address.addr);
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h
new file mode 100644
index 0000000000..4f863975ab
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/btle_security.h
@@ -0,0 +1,128 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _BTLE_SECURITY_H_
+#define _BTLE_SECURITY_H_
+
+#include "ble/Gap.h"
+#include "ble/SecurityManager.h"
+
+/**
+ * Function to test whether the SecurityManager has been initialized.
+ * Possible by a call to @ref btle_initializeSecurity().
+ *
+ * @return True if the SecurityManager was previously initialized, false
+ *         otherwise.
+ */
+bool btle_hasInitializedSecurity(void);
+
+/**
+ * Enable Nordic's Device Manager, which brings in functionality from the
+ * stack's Security Manager. The Security Manager implements the actual
+ * cryptographic algorithms and protocol exchanges that allow two devices to
+ * securely exchange data and privately detect each other.
+ *
+ * @param[in]  enableBonding Allow for bonding.
+ * @param[in]  requireMITM   Require protection for man-in-the-middle attacks.
+ * @param[in]  iocaps        To specify IO capabilities of this peripheral,
+ *                           such as availability of a display or keyboard to
+ *                           support out-of-band exchanges of security data.
+ * @param[in]  passkey       To specify a static passkey.
+ *
+ * @return BLE_ERROR_NONE on success.
+ */
+ble_error_t btle_initializeSecurity(bool                                      enableBonding = true,
+                                    bool                                      requireMITM   = true,
+                                    SecurityManager::SecurityIOCapabilities_t iocaps        = SecurityManager::IO_CAPS_NONE,
+                                    const SecurityManager::Passkey_t          passkey       = NULL);
+
+/**
+ * Get the security status of a link.
+ *
+ * @param[in]  connectionHandle
+ *               Handle to identify the connection.
+ * @param[out] securityStatusP
+ *               security status.
+ *
+ * @return BLE_ERROR_NONE Or appropriate error code indicating reason for failure.
+ */
+ble_error_t btle_getLinkSecurity(Gap::Handle_t connectionHandle, SecurityManager::LinkSecurityStatus_t *securityStatusP);
+
+/**
+ * Set the security mode on a connection. Useful for elevating the security mode
+ * once certain conditions are met, e.g., a particular service is found.
+ *
+ * @param[in]  connectionHandle
+ *               Handle to identify the connection.
+ * @param[in]  securityMode
+ *               security mode.
+ *
+ * @return BLE_ERROR_NONE Or appropriate error code indicating reason for failure.
+ */
+ble_error_t btle_setLinkSecurity(Gap::Handle_t connectionHandle, SecurityManager::SecurityMode_t securityMode);
+
+/**
+ * Function for deleting all peer device context and all related bonding
+ * information from the database.
+ *
+ * @retval BLE_ERROR_NONE             On success, else an error code indicating reason for failure.
+ * @retval BLE_ERROR_INVALID_STATE    If the API is called without module initialization and/or
+ *                                    application registration.
+ */
+ble_error_t btle_purgeAllBondingState(void);
+
+/**
+ * Query the SoftDevice bond table to extract a whitelist containing the BLE
+ * addresses and IRKs of bonded devices.
+ *
+ * @param[in/out]  p_whitelist
+ *                  (on input) p_whitelist->addr_count and
+ *                  p_whitelist->irk_count specify the maximum number of
+ *                  addresses and IRKs added to the whitelist structure.
+ *                  (on output) *p_whitelist is a whitelist containing the
+ *                  addresses and IRKs of the bonded devices.
+ *
+ * @return BLE_ERROR_NONE Or appropriate error code indicating reason for failure.
+ */
+ble_error_t btle_createWhitelistFromBondTable(ble_gap_whitelist_t *p_whitelist);
+
+/**
+ * Function to test whether a BLE address is generated using an IRK.
+ *
+ * @param[in]   p_addr
+ *                  Pointer to a BLE address.
+ * @param[in]   p_irk
+ *                  Pointer to an IRK.
+ *
+ * @return True if p_addr can be generated using p_irk, false otherwise.
+ */
+bool btle_matchAddressAndIrk(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk);
+
+/**
+ * Function to generate a private resolvable BLE address.
+ *
+ * @param[out]  p_addr
+ *                  The output address.
+ * @param[in]   p_irk
+ *                  A reference to a IRK.
+ *
+ * @note This function does not generate a secure address since the prand number in the
+ *       resolvable address is not truly random. Therefore, the output of this function
+ *       is only meant to be used by the application internally but never exported.
+ */
+void btle_generateResolvableAddress(const ble_gap_irk_t &irk, ble_gap_addr_t &address);
+
+#endif /* _BTLE_SECURITY_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp
new file mode 100644
index 0000000000..2a8e600c0a
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.cpp
@@ -0,0 +1,364 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "custom_helper.h"
+
+/*
+ * The current version of the soft-device doesn't handle duplicate 128-bit UUIDs
+ * very  well. It is therefore necessary to filter away duplicates before
+ * passing long UUIDs to sd_ble_uuid_vs_add(). The following types and data
+ * structures involved in maintaining a local cache of 128-bit UUIDs.
+ */
+typedef struct {
+    UUID::LongUUIDBytes_t uuid;
+    uint8_t         type;
+} converted_uuid_table_entry_t;
+
+static unsigned uuidTableEntries = 0; /* current usage of the table */
+converted_uuid_table_entry_t convertedUUIDTable[UUID_TABLE_MAX_ENTRIES];
+
+void custom_reset_128bits_uuid_table() {
+    uuidTableEntries = 0;
+}
+
+/**
+ * lookup the cache of previously converted 128-bit UUIDs to find a type value.
+ * @param  uuid          base 128-bit UUID
+ * @param  recoveredType the type field of the 3-byte nRF's uuid.
+ * @return               true if a match is found.
+ */
+static bool
+lookupConvertedUUIDTable(const UUID::LongUUIDBytes_t uuid, uint8_t *recoveredType)
+{
+    unsigned i;
+    for (i = 0; i < uuidTableEntries; i++) {
+        unsigned byteIndex;
+        for (byteIndex = 0; byteIndex < UUID::LENGTH_OF_LONG_UUID; byteIndex++) {
+            /* Skip bytes 2 and 3, because they contain the shortUUID (16-bit) version of the
+             * long UUID; and we're comparing against the remainder. */
+            if ((byteIndex == 2) || (byteIndex == 3)) {
+                continue;
+            }
+
+            if (convertedUUIDTable[i].uuid[byteIndex] != uuid[byteIndex]) {
+                break;
+            }
+        }
+
+        if (byteIndex == UUID::LENGTH_OF_LONG_UUID) {
+            *recoveredType = convertedUUIDTable[i].type;
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static void
+addToConvertedUUIDTable(const UUID::LongUUIDBytes_t uuid, uint8_t type)
+{
+    if (uuidTableEntries == UUID_TABLE_MAX_ENTRIES) {
+        return; /* recovery needed; or at least the user should be warned about this fact.*/
+    }
+
+    memcpy(convertedUUIDTable[uuidTableEntries].uuid, uuid, UUID::LENGTH_OF_LONG_UUID);
+    convertedUUIDTable[uuidTableEntries].uuid[2] = 0;
+    convertedUUIDTable[uuidTableEntries].uuid[3] = 0;
+    convertedUUIDTable[uuidTableEntries].type    = type;
+    uuidTableEntries++;
+}
+
+/**
+ * The nRF transport has its own 3-byte representation of a UUID. If the user-
+ * specified UUID is 128-bits wide, then the UUID base needs to be added to the
+ * soft-device and converted to a 3-byte handle before being used further. This
+ * function is responsible for this translation of user-specified UUIDs into
+ * nRF's representation.
+ *
+ * @param[in]  uuid
+ *                 user-specified UUID
+ * @return nRF
+ *              3-byte UUID (containing a type and 16-bit UUID) representation
+ *              to be used with SVC calls.
+ */
+ble_uuid_t custom_convert_to_nordic_uuid(const UUID &uuid)
+{
+    ble_uuid_t nordicUUID;
+    nordicUUID.uuid = uuid.getShortUUID();
+    nordicUUID.type = BLE_UUID_TYPE_UNKNOWN; /* to be set below */
+
+    if (uuid.shortOrLong() == UUID::UUID_TYPE_SHORT) {
+        nordicUUID.type = BLE_UUID_TYPE_BLE;
+    } else {
+        if (!lookupConvertedUUIDTable(uuid.getBaseUUID(), &nordicUUID.type)) {
+            nordicUUID.type = custom_add_uuid_base(uuid.getBaseUUID());
+            addToConvertedUUIDTable(uuid.getBaseUUID(), nordicUUID.type);
+        }
+    }
+
+    return nordicUUID;
+}
+
+/**************************************************************************/
+/*!
+    @brief      Adds the base UUID to the custom service. All UUIDs used
+                by this service are based on this 128-bit UUID.
+
+    @note       This UUID needs to be added to the SoftDevice stack before
+                adding the service's primary service via
+                'sd_ble_gatts_service_add'
+
+    @param[in]  p_uuid_base   A pointer to the 128-bit UUID array (8*16)
+
+    @returns    The UUID type.
+                A return value of 0 should be considered an error.
+
+    @retval     0x00    BLE_UUID_TYPE_UNKNOWN
+    @retval     0x01    BLE_UUID_TYPE_BLE
+    @retval     0x02    BLE_UUID_TYPE_VENDOR_BEGIN
+
+    @section EXAMPLE
+    @code
+
+    // Take note that bytes 2/3 are blank since these are used to identify
+    // the primary service and individual characteristics
+    #define CFG_CUSTOM_UUID_BASE  "\x6E\x40\x00\x00\xB5\xA3\xF3\x93\xE0\xA9\xE5\x0E\x24\xDC\xCA\x9E"
+
+    uint8_t uuid_type = custom_add_uuid_base(CFG_CUSTOM_UUID_BASE);
+    ASSERT(uuid_type > 0, ERROR_NOT_FOUND);
+
+    // We can now safely add the primary service and any characteristics
+    // for our custom service ...
+
+    @endcode
+*/
+/**************************************************************************/
+uint8_t custom_add_uuid_base(uint8_t const *const p_uuid_base)
+{
+    ble_uuid128_t base_uuid;
+    uint8_t       uuid_type = 0;
+
+    for (unsigned i = 0; i < UUID::LENGTH_OF_LONG_UUID; i++) {
+        base_uuid.uuid128[i] = p_uuid_base[i];
+    }
+
+    ASSERT_INT( ERROR_NONE, sd_ble_uuid_vs_add( &base_uuid, &uuid_type ), 0);
+
+    return uuid_type;
+}
+
+/**************************************************************************/
+/*!
+
+*/
+/**************************************************************************/
+error_t custom_decode_uuid_base(uint8_t const *const p_uuid_base,
+                                ble_uuid_t          *p_uuid)
+{
+    UUID::LongUUIDBytes_t uuid_base_le;
+
+    for (uint8_t i = 0; i < UUID::LENGTH_OF_LONG_UUID; i++) {
+        uuid_base_le[i] = p_uuid_base[i];
+    }
+
+    ASSERT_STATUS( sd_ble_uuid_decode(UUID::LENGTH_OF_LONG_UUID, uuid_base_le, p_uuid));
+
+    return ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief      Adds a new characteristic to the custom service, assigning
+                properties, a UUID add-on value, etc.
+
+    @param[in]  service_handle
+    @param[in]  p_uuid            The 16-bit value to add to the base UUID
+                                  for this characteristic (normally >1
+                                  since 1 is typically used by the primary
+                                  service).
+    @param[in]  char_props        The characteristic properties, as
+                                  defined by ble_gatt_char_props_t
+    @param[in]  max_length        The maximum length of this characeristic
+    @param[in]  has_variable_len  Whether the characteristic data has
+                                  variable length.
+    @param[out] p_char_handle
+
+    @returns
+    @retval     ERROR_NONE        Everything executed normally
+*/
+/**************************************************************************/
+error_t custom_add_in_characteristic(uint16_t                  service_handle,
+                                     ble_uuid_t               *p_uuid,
+                                     uint8_t                   properties,
+                                     SecurityManager::SecurityMode_t       requiredSecurity,
+                                     uint8_t                  *p_data,
+                                     uint16_t                  length,
+                                     uint16_t                  max_length,
+                                     bool                      has_variable_len,
+                                     const uint8_t            *userDescriptionDescriptorValuePtr,
+                                     uint16_t                  userDescriptionDescriptorValueLen,
+                                     bool                      readAuthorization,
+                                     bool                      writeAuthorization,
+                                     ble_gatts_char_handles_t *p_char_handle)
+{
+    /* Characteristic metadata */
+    ble_gatts_attr_md_t   cccd_md;
+    ble_gatt_char_props_t char_props;
+
+    memcpy(&char_props, &properties, 1);
+
+    if (char_props.notify || char_props.indicate) {
+        /* Notification requires cccd */
+        memclr_( &cccd_md, sizeof(ble_gatts_attr_md_t));
+        cccd_md.vloc = BLE_GATTS_VLOC_STACK;
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm);
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.write_perm);
+    }
+
+    ble_gatts_char_md_t char_md = {0};
+
+    char_md.char_props = char_props;
+    char_md.p_cccd_md  =
+        (char_props.notify || char_props.indicate) ? &cccd_md : NULL;
+    if ((userDescriptionDescriptorValueLen > 0) && (userDescriptionDescriptorValuePtr != NULL)) {
+        char_md.p_char_user_desc        = const_cast<uint8_t *>(userDescriptionDescriptorValuePtr);
+        char_md.char_user_desc_max_size = userDescriptionDescriptorValueLen;
+        char_md.char_user_desc_size     = userDescriptionDescriptorValueLen;
+    }
+
+    /* Attribute declaration */
+    ble_gatts_attr_md_t attr_md = {0};
+
+    attr_md.rd_auth = readAuthorization;
+    attr_md.wr_auth = writeAuthorization;
+
+    attr_md.vloc = BLE_GATTS_VLOC_STACK;
+    /* Always set variable size */
+    attr_md.vlen = has_variable_len;
+
+    if (char_props.read || char_props.notify || char_props.indicate) {
+        switch (requiredSecurity) {
+            case SecurityManager::SECURITY_MODE_ENCRYPTION_OPEN_LINK :
+                BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_ENCRYPTION_NO_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(&attr_md.read_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_ENCRYPTION_WITH_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(&attr_md.read_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_SIGNED_NO_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(&attr_md.read_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_SIGNED_WITH_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(&attr_md.read_perm);
+                break;
+            default:
+                break;
+        };
+    }
+
+    if (char_props.write || char_props.write_wo_resp) {
+        switch (requiredSecurity) {
+            case SecurityManager::SECURITY_MODE_ENCRYPTION_OPEN_LINK :
+                BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_ENCRYPTION_NO_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(&attr_md.write_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_ENCRYPTION_WITH_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(&attr_md.write_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_SIGNED_NO_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(&attr_md.write_perm);
+                break;
+            case SecurityManager::SECURITY_MODE_SIGNED_WITH_MITM :
+                BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(&attr_md.write_perm);
+                break;
+            default:
+                break;
+        };
+    }
+
+    ble_gatts_attr_t attr_char_value = {0};
+
+    attr_char_value.p_uuid    = p_uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.init_len  = length;
+    attr_char_value.max_len   = max_length;
+    attr_char_value.p_value   = p_data;
+
+    ASSERT_STATUS ( sd_ble_gatts_characteristic_add(service_handle,
+                                                    &char_md,
+                                                    &attr_char_value,
+                                                    p_char_handle));
+
+    return ERROR_NONE;
+}
+
+
+
+/**************************************************************************/
+/*!
+    @brief      Adds a new descriptor to the custom service, assigning
+                value, a UUID add-on value, etc.
+
+    @param[in]  char_handle
+    @param[in]  p_uuid            The 16-bit value to add to the base UUID
+                                  for this descriptor (normally >1
+                                  since 1 is typically used by the primary
+                                  service).
+    @param[in]  max_length        The maximum length of this descriptor
+    @param[in]  has_variable_len  Whether the characteristic data has
+                                  variable length.
+
+    @returns
+    @retval     ERROR_NONE        Everything executed normally
+*/
+/**************************************************************************/
+error_t custom_add_in_descriptor(uint16_t    char_handle,
+                                 ble_uuid_t *p_uuid,
+                                 uint8_t    *p_data,
+                                 uint16_t    length,
+                                 uint16_t    max_length,
+                                 bool        has_variable_len,
+                                 uint16_t   *p_desc_handle)
+{
+    /* Descriptor metadata */
+    ble_gatts_attr_md_t   desc_md = {0};
+
+    desc_md.vloc = BLE_GATTS_VLOC_STACK;
+    /* Always set variable size */
+    desc_md.vlen = has_variable_len;
+
+    /* Make it readable and writable */
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&desc_md.read_perm);
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&desc_md.write_perm);
+
+    ble_gatts_attr_t attr_desc = {0};
+
+    attr_desc.p_uuid    = p_uuid;
+    attr_desc.p_attr_md = &desc_md;
+    attr_desc.init_len  = length;
+    attr_desc.max_len   = max_length;
+    attr_desc.p_value   = p_data;
+
+    ASSERT_STATUS ( sd_ble_gatts_descriptor_add(char_handle,
+                                                &attr_desc,
+                                                p_desc_handle));
+
+    return ERROR_NONE;
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h
new file mode 100644
index 0000000000..22a32907c1
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/btle/custom/custom_helper.h
@@ -0,0 +1,71 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _CUSTOM_HELPER_H_
+#define _CUSTOM_HELPER_H_
+
+#include "common/common.h"
+#include "nrf_ble.h"
+#include "ble/UUID.h"
+#include "ble/GattCharacteristic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define UUID_TABLE_MAX_ENTRIES  (4) /* This is the maximum number of 128-bit UUIDs with distinct bases that
+                                                   * we expect to be in use; increase this limit if needed. */
+
+/**
+ * Reset the table of 128bits uuids.
+ * This table is used to keep track of vendors uuids added to the softdevice.
+ * It is important to reset it before disabling the softdevice otherwise the
+ * next time the softdevice will be enabled, this table will not be synchronmized
+ * with the softdevice table.
+ */
+void custom_reset_128bits_uuid_table();
+uint8_t custom_add_uuid_base(uint8_t const *const p_uuid_base);
+error_t custom_decode_uuid(uint8_t const *const p_uuid_base,
+                           ble_uuid_t          *p_uuid);
+ble_uuid_t custom_convert_to_nordic_uuid(const UUID &uuid);
+
+error_t custom_add_in_characteristic(uint16_t                  service_handle,
+                                     ble_uuid_t               *p_uuid,
+                                     uint8_t                   properties,
+                                     SecurityManager::SecurityMode_t requiredSecurity,
+                                     uint8_t                  *p_data,
+                                     uint16_t                  length,
+                                     uint16_t                  max_length,
+                                     bool                      has_variable_len,
+                                     const uint8_t            *userDescriptionDescriptorValuePtr,
+                                     uint16_t                  userDescriptionDescriptorValueLen,
+                                     bool                      readAuthorization,
+                                     bool                      writeAuthorization,
+                                     ble_gatts_char_handles_t *p_char_handle);
+
+error_t custom_add_in_descriptor(uint16_t                      char_handle,
+                                     ble_uuid_t               *p_uuid,
+                                     uint8_t                  *p_data,
+                                     uint16_t                  length,
+                                     uint16_t                  max_length,
+                                     bool                      has_variable_len,
+                                     uint16_t                 *p_desc_handle);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // ifndef _CUSTOM_HELPER_H_
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/ansi_escape.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/ansi_escape.h
new file mode 100644
index 0000000000..392dedb44f
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/ansi_escape.h
@@ -0,0 +1,103 @@
+/**************************************************************************/
+/*!
+    @file     ansi_esc_code.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, hathach (tinyusb.org)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+    This file is part of the tinyusb stack.
+*/
+/**************************************************************************/
+
+/** \file
+ *  \brief TBD
+ *
+ *  \note TBD
+ */
+
+/** \ingroup TBD
+ *  \defgroup TBD
+ *  \brief TBD
+ *
+ *  @{
+ */
+
+#ifndef _ANSI_ESC_CODE_H_
+#define _ANSI_ESC_CODE_H_
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define CSI_CODE(seq)   "\33[" seq
+#define CSI_SGR(x)      CSI_CODE(#x) "m"
+
+//------------- Cursor movement -------------//
+#define ANSI_CURSOR_UP(n)        CSI_CODE(#n "A")
+#define ANSI_CURSOR_DOWN(n)      CSI_CODE(#n "B")
+#define ANSI_CURSOR_FORWARD(n)   CSI_CODE(#n "C")
+#define ANSI_CURSOR_BACKWARD(n)  CSI_CODE(#n "D")
+#define ANSI_CURSOR_LINE_DOWN(n) CSI_CODE(#n "E")
+#define ANSI_CURSOR_LINE_UP(n)   CSI_CODE(#n "F")
+#define ANSI_CURSOR_POSITION(n, m) CSI_CODE(#n ";" #m "H")
+
+#define ANSI_ERASE_SCREEN(n)     CSI_CODE(#n "J")
+#define ANSI_ERASE_LINE(n)       CSI_CODE(#n "K")
+
+/** text color */
+#define ANSI_TEXT_BLACK          CSI_SGR(30)
+#define ANSI_TEXT_RED            CSI_SGR(31)
+#define ANSI_TEXT_GREEN          CSI_SGR(32)
+#define ANSI_TEXT_YELLOW         CSI_SGR(33)
+#define ANSI_TEXT_BLUE           CSI_SGR(34)
+#define ANSI_TEXT_MAGENTA        CSI_SGR(35)
+#define ANSI_TEXT_CYAN           CSI_SGR(36)
+#define ANSI_TEXT_WHITE          CSI_SGR(37)
+#define ANSI_TEXT_DEFAULT        CSI_SGR(39)
+
+/** background color */
+#define ANSI_BG_BLACK            CSI_SGR(40)
+#define ANSI_BG_RED              CSI_SGR(41)
+#define ANSI_BG_GREEN            CSI_SGR(42)
+#define ANSI_BG_YELLOW           CSI_SGR(43)
+#define ANSI_BG_BLUE             CSI_SGR(44)
+#define ANSI_BG_MAGENTA          CSI_SGR(45)
+#define ANSI_BG_CYAN             CSI_SGR(46)
+#define ANSI_BG_WHITE            CSI_SGR(47)
+#define ANSI_BG_DEFAULT          CSI_SGR(49)
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _TUSB_ANSI_ESC_CODE_H_ */
+
+/** @} */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/assertion.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/assertion.h
new file mode 100644
index 0000000000..c0bd8c0d66
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/assertion.h
@@ -0,0 +1,198 @@
+/**************************************************************************/
+/*!
+    @file     assertion.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, K. Townsend (microBuilder.eu)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/**************************************************************************/
+
+/** \file
+ *  \brief TBD
+ *
+ *  \note TBD
+ */
+
+/** \ingroup TBD
+ *  \defgroup TBD
+ *  \brief TBD
+ *
+ *  @{
+ */
+
+#ifndef _ASSERTION_H_
+#define _ASSERTION_H_
+
+#include "projectconfig.h"
+
+#ifdef __cplusplus
+extern "C"
+{
+#endif
+
+static inline void debugger_breakpoint(void) ATTR_ALWAYS_INLINE;
+static inline void debugger_breakpoint(void)
+{
+#ifndef _TEST_
+  __asm("BKPT #0\n");
+#endif
+}
+
+//--------------------------------------------------------------------+
+// Compile-time Assert
+//--------------------------------------------------------------------+
+#if defined __COUNTER__ && __COUNTER__ != __COUNTER__
+  #define _ASSERT_COUNTER __COUNTER__
+#else
+  #define _ASSERT_COUNTER __LINE__
+#endif
+
+#define ASSERT_STATIC(const_expr, message) enum { XSTRING_CONCAT_(static_assert_, _ASSERT_COUNTER) = 1/(!!(const_expr)) }
+
+//--------------------------------------------------------------------+
+// Assert Helper
+//--------------------------------------------------------------------+
+//#ifndef _TEST_
+//  #define ASSERT_MESSAGE(format, ...) _PRINTF("Assert at %s: %s: %d: " format "\n", __BASE_FILE__, __PRETTY_FUNCTION__, __LINE__, __VA_ARGS__)
+//#else
+//  #define ASSERT_MESSAGE(format, ...) _PRINTF("%d:note: Assert " format "\n", __LINE__, __VA_ARGS__)
+//#endif
+
+#if CFG_DEBUG == 3
+  #define ASSERT_MESSAGE(format, ...) debugger_breakpoint()
+#elif CFG_DEBUG == 2
+  #define ASSERT_MESSAGE(format, ...) printf("Assert at %s: %s: %d: " format "\n", __BASE_FILE__, __PRETTY_FUNCTION__, __LINE__, __VA_ARGS__)
+#else
+  #define ASSERT_MESSAGE(format, ...)
+#endif
+
+#define ASSERT_ERROR_HANDLER(x, para)  \
+    return (x)
+
+#define ASSERT_DEFINE_WITH_HANDLER(error_handler, handler_para, setup_statement, condition, error, format, ...) \
+  do{\
+    setup_statement;\
+	  if (!(condition)) {\
+	    ASSERT_MESSAGE(format, __VA_ARGS__);\
+	    error_handler(error, handler_para);\
+	  }\
+	}while(0)
+
+#define ASSERT_DEFINE(...) ASSERT_DEFINE_WITH_HANDLER(ASSERT_ERROR_HANDLER, NULL, __VA_ARGS__)
+
+//--------------------------------------------------------------------+
+// error_t Status Assert TODO use ASSERT_DEFINE
+//--------------------------------------------------------------------+
+#define ASSERT_STATUS_MESSAGE(sts, message) \
+    ASSERT_DEFINE(error_t status = (error_t)(sts),\
+                  ERROR_NONE == status, status, "%s: %s", ErrorStr[status], message)
+
+#define ASSERT_STATUS(sts) \
+    ASSERT_DEFINE(error_t status = (error_t)(sts),\
+                  ERROR_NONE == status, status, "error = %d", status)
+
+#define ASSERT_STATUS_RET_VOID(sts) \
+    ASSERT_DEFINE(error_t status = (error_t)(sts),\
+                  ERROR_NONE == status, (void) 0, "error = %d", status)
+
+//--------------------------------------------------------------------+
+// Logical Assert
+//--------------------------------------------------------------------+
+#define ASSERT(...)                      ASSERT_TRUE(__VA_ARGS__)
+#define ASSERT_TRUE(condition  , error)  ASSERT_DEFINE( , (condition), error, "%s", "evaluated to false")
+#define ASSERT_FALSE(condition , error)  ASSERT_DEFINE( ,!(condition), error, "%s", "evaluated to true")
+
+//--------------------------------------------------------------------+
+// Pointer Assert
+//--------------------------------------------------------------------+
+#define ASSERT_PTR(...)                    ASSERT_PTR_NOT_NULL(__VA_ARGS__)
+#define ASSERT_PTR_NOT_NULL(pointer, error) ASSERT_DEFINE( , NULL != (pointer), error, "%s", "pointer is NULL")
+#define ASSERT_PTR_NULL(pointer, error)    ASSERT_DEFINE( , NULL == (pointer), error, "%s", "pointer is not NULL")
+
+//--------------------------------------------------------------------+
+// Integral Assert
+//--------------------------------------------------------------------+
+#define ASSERT_XXX_EQUAL(type_format, expected, actual, error) \
+    ASSERT_DEFINE(\
+                  uint32_t exp = (expected); uint32_t act = (actual),\
+                  exp==act,\
+                  error,\
+                  "expected " type_format ", actual " type_format, exp, act)
+
+#define ASSERT_XXX_WITHIN(type_format, lower, upper, actual, error) \
+    ASSERT_DEFINE(\
+                  uint32_t low = (lower); uint32_t up = (upper); uint32_t act = (actual),\
+                  (low <= act) && (act <= up),\
+                  error,\
+                  "expected within " type_format " - " type_format ", actual " type_format, low, up, act)
+
+//--------------------------------------------------------------------+
+// Integer Assert
+//--------------------------------------------------------------------+
+#define ASSERT_INT(...)        ASSERT_INT_EQUAL(__VA_ARGS__)
+#define ASSERT_INT_EQUAL(...)  ASSERT_XXX_EQUAL("%d", __VA_ARGS__)
+#define ASSERT_INT_WITHIN(...) ASSERT_XXX_WITHIN("%d", __VA_ARGS__)
+
+//--------------------------------------------------------------------+
+// Hex Assert
+//--------------------------------------------------------------------+
+#define ASSERT_HEX(...)        ASSERT_HEX_EQUAL(__VA_ARGS__)
+#define ASSERT_HEX_EQUAL(...)  ASSERT_XXX_EQUAL("0x%x", __VA_ARGS__)
+#define ASSERT_HEX_WITHIN(...) ASSERT_XXX_WITHIN("0x%x", __VA_ARGS__)
+
+//--------------------------------------------------------------------+
+// Bin Assert
+//--------------------------------------------------------------------+
+#define BIN8_PRINTF_PATTERN "%d%d%d%d%d%d%d%d"
+#define BIN8_PRINTF_CONVERT(byte)  \
+  ((byte) & 0x80 ? 1 : 0), \
+  ((byte) & 0x40 ? 1 : 0), \
+  ((byte) & 0x20 ? 1 : 0), \
+  ((byte) & 0x10 ? 1 : 0), \
+  ((byte) & 0x08 ? 1 : 0), \
+  ((byte) & 0x04 ? 1 : 0), \
+  ((byte) & 0x02 ? 1 : 0), \
+  ((byte) & 0x01 ? 1 : 0)
+
+#define ASSERT_BIN8(...)        ASSERT_BIN8_EQUAL(__VA_ARGS__)
+#define ASSERT_BIN8_EQUAL(expected, actual, error)\
+    ASSERT_DEFINE(\
+                  uint8_t exp = (expected); uint8_t act = (actual),\
+                  exp==act,\
+                  error,\
+                  "expected " BIN8_PRINTF_PATTERN ", actual " BIN8_PRINTF_PATTERN, BIN8_PRINTF_CONVERT(exp), BIN8_PRINTF_CONVERT(act) )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _ASSERTION_H_ */
+
+/** @} */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/binary.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/binary.h
new file mode 100644
index 0000000000..585787eb2f
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/binary.h
@@ -0,0 +1,96 @@
+/**************************************************************************/
+/*!
+    @file     binary.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, K. Townsend (microBuilder.eu)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/**************************************************************************/
+
+/** \ingroup TBD
+ *  \defgroup TBD
+ *  \brief TBD
+ *
+ *  @{
+ */
+
+#ifndef _BINARY_H_
+#define _BINARY_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/// n-th Bit
+#define BIT(n) (1 << (n))
+
+/// set n-th bit of x to 1
+#define BIT_SET(x, n) ( (x) | BIT(n) )
+
+/// clear n-th bit of x
+#define BIT_CLR(x, n) ( (x) & (~BIT(n)) )
+
+/// test n-th bit of x
+#define BIT_TEST(x, n) ( (x) & BIT(n) )
+
+#if defined(__GNUC__) && !defined(__CC_ARM) // keil does not support binary format
+
+#define BIN8(x)               ((uint8_t)  (0b##x))
+#define BIN16(b1, b2)         ((uint16_t) (0b##b1##b2))
+#define BIN32(b1, b2, b3, b4) ((uint32_t) (0b##b1##b2##b3##b4))
+
+#else
+
+//  internal macro of B8, B16, B32
+#define _B8__(x) (((x&0x0000000FUL)?1:0) \
+                +((x&0x000000F0UL)?2:0) \
+                +((x&0x00000F00UL)?4:0) \
+                +((x&0x0000F000UL)?8:0) \
+                +((x&0x000F0000UL)?16:0) \
+                +((x&0x00F00000UL)?32:0) \
+                +((x&0x0F000000UL)?64:0) \
+                +((x&0xF0000000UL)?128:0))
+
+#define BIN8(d) ((uint8_t) _B8__(0x##d##UL))
+#define BIN16(dmsb,dlsb) (((uint16_t)BIN8(dmsb)<<8) + BIN8(dlsb))
+#define BIN32(dmsb,db2,db3,dlsb) \
+            (((uint32_t)BIN8(dmsb)<<24) \
+            + ((uint32_t)BIN8(db2)<<16) \
+            + ((uint32_t)BIN8(db3)<<8) \
+            + BIN8(dlsb))
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BINARY_H_ */
+
+/** @} */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/ble_error.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/ble_error.h
new file mode 100644
index 0000000000..36deb33080
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/ble_error.h
@@ -0,0 +1,151 @@
+/**************************************************************************/
+/*!
+    @file     ble_error.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, K. Townsend (microBuilder.eu)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/**************************************************************************/
+
+/** \file
+ *  \brief Error Header
+ *
+ *  \note TBD
+ */
+
+/** \ingroup Group_Common
+ *  \defgroup Group_Error Error Codes
+ *  @{
+ */
+
+#ifndef _BLE_ERROR_H_
+#define _BLE_ERROR_H_
+
+#include "projectconfig.h"
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+typedef enum 
+{
+  /*=======================================================================
+    NORDIC GLOBAL ERRORS                                   0x0000 .. 0x00FF
+    -----------------------------------------------------------------------
+    Errors mapped from nrf_error.h
+    -----------------------------------------------------------------------*/
+    ERROR_NONE                                    = 0x0000 , ///< Successful command
+    ERROR_SVC_HANDLER_MISSING                     = 0x0001 , ///< SVC handler is missing
+    ERROR_SOFTDEVICE_NOT_ENABLED                  = 0x0002 , ///< SoftDevice has not been enabled
+    ERROR_INTERNAL                                = 0x0003 , ///< Internal Error
+    ERROR_NO_MEM                                  = 0x0004 , ///< No Memory for operation
+    ERROR_NOT_FOUND                               = 0x0005 , ///< Not found
+    ERROR_NOT_SUPPORTED                           = 0x0006 , ///< Not supported
+    ERROR_INVALID_PARAM                           = 0x0007 , ///< Invalid Parameter
+    ERROR_INVALID_STATE                           = 0x0008 , ///< Invalid state, operation disallowed in this state
+    ERROR_INVALID_LENGTH                          = 0x0009 , ///< Invalid Length
+    ERROR_INVALID_FLAGS                           = 0x000A , ///< Invalid Flags
+    ERROR_INVALID_DATA                            = 0x000B , ///< Invalid Data
+    ERROR_DATA_SIZE                               = 0x000C , ///< Data size exceeds limit
+    ERROR_TIMEOUT                                 = 0x000D , ///< Operation timed out
+    ERROR_NULL                                    = 0x000E , ///< Null Pointer
+    ERROR_FORBIDDEN                               = 0x000F , ///< Forbidden Operation
+    ERROR_INVALID_ADDR                            = 0x0010 , ///< Bad Memory Address
+    ERROR_BUSY                                    = 0x0011 , ///< Busy
+  /*=======================================================================*/
+
+  ERROR_INVALIDPARAMETER                        = 0x0100 , /**< An invalid parameter value was provided */
+  ERROR_I2C_XFER_FAILED                         = 0x0101 , /**< an failed attempt to make I2C transfer */
+
+  /*=======================================================================
+    SIMPLE BINARY PROTOCOL ERRORS                          0x0120 .. 0x013F
+    -----------------------------------------------------------------------
+    Errors relating to the simple binary protocol (/src//protocol)
+    -----------------------------------------------------------------------*/
+    ERROR_PROT_INVALIDMSGTYPE                   = 0x121,  /**< Unexpected msg type encountered */
+    ERROR_PROT_INVALIDCOMMANDID                 = 0x122,  /**< Unknown or out of range command ID */
+    ERROR_PROT_INVALIDPAYLOAD                   = 0x123,  /**< Message payload has a problem (invalid len, etc.) */
+  /*=======================================================================*/
+
+  //------------- based on Nordic SDM nrf_error_sdm.h -------------//
+  ERROR_SDM_LFCLK_SOURCE_UNKNOWN                = 0x1000 , ///< Unknown lfclk source
+  ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION   = 0x1001 , ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts)
+  ERROR_SDM_INCORRECT_CLENR0                    = 0x1002 , ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing)
+
+  //------------- based on Nordic SOC nrf_error_soc.h -------------//
+  /* Mutex Errors */
+  ERROR_SOC_MUTEX_ALREADY_TAKEN                 = 0x2000 ,  ///< Mutex already taken
+
+  /* NVIC errors */
+  ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE        = 0x2001 ,  ///< NVIC interrupt not available
+  ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED = 0x2002 ,  ///< NVIC interrupt priority not allowed
+  ERROR_SOC_NVIC_SHOULD_NOT_RETURN              = 0x2003 ,  ///< NVIC should not return
+
+  /* Power errors */
+  ERROR_SOC_POWER_MODE_UNKNOWN                  = 0x2004 ,  ///< Power mode unknown
+  ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN         = 0x2005 ,  ///< Power POF threshold unknown
+  ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN         = 0x2006 ,  ///< Power off should not return
+
+  /* Rand errors */
+  ERROR_SOC_RAND_NOT_ENOUGH_VALUES              = 0x2007 ,  ///< RAND not enough values
+
+  /* PPI errors */
+  ERROR_SOC_PPI_INVALID_CHANNEL                 = 0x2008 ,  ///< Invalid PPI Channel
+  ERROR_SOC_PPI_INVALID_GROUP                   = 0x2009 ,  ///< Invalid PPI Group
+
+  //------------- based on Nordic STK (ble) ble_err.h -------------//
+  ERROR_BLE_INVALID_CONN_HANDLE                 = 0x3001 , /**< Invalid connection handle. */
+  ERROR_BLE_INVALID_ATTR_HANDLE                 = 0x3002 , /**< Invalid attribute handle. */
+  ERROR_BLE_NO_TX_BUFFERS                       = 0x3003 , /**< Buffer capacity exceeded. */
+
+  // L2CAP
+  ERROR_BLE_L2CAP_CID_IN_USE                    = 0x3100 , /**< CID already in use. */
+
+  // GAP
+  ERROR_BLE_GAP_UUID_LIST_MISMATCH              = 0x3200 , /**< UUID list does not contain an integral number of UUIDs. */
+  ERROR_BLE_GAP_DISCOVERABLE_WITH_WHITELIST     = 0x3201 , /**< Use of Whitelist not permitted with discoverable advertising. */
+  ERROR_BLE_GAP_INVALID_BLE_ADDR                = 0x3202 , /**< The upper two bits of the address do not correspond to the specified address type. */
+
+  // GATTC
+  ERROR_BLE_GATTC_PROC_NOT_PERMITTED            = 0x3300 ,
+
+  // GATTS
+  ERROR_BLEGATTS_INVALID_ATTR_TYPE              = 0x3400 , /**< Invalid attribute type. */
+  ERROR_BLEGATTS_SYS_ATTR_MISSING               = 0x3401 , /**< System Attributes missing. */
+
+}error_t;
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _BLE_ERROR_H_ */
+
+ /**  @} */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/common.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/common.h
new file mode 100644
index 0000000000..6002c6dfb7
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/common.h
@@ -0,0 +1,236 @@
+/**************************************************************************/
+/*!
+    @file     common.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, K. Townsend (microBuilder.eu)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/**************************************************************************/
+
+/** \defgroup Group_Common Common Files
+ * @{
+ *
+ *  \defgroup Group_CommonH common.h
+ *
+ *  @{
+ */
+
+#ifndef _COMMON_H_
+#define _COMMON_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+//--------------------------------------------------------------------+
+// INCLUDES
+//--------------------------------------------------------------------+
+
+//------------- Standard Header -------------//
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include <string.h>
+#include <stdio.h>
+
+//------------- General Header -------------//
+#include "projectconfig.h"
+#include "compiler.h"
+#include "assertion.h"
+#include "binary.h"
+#include "ble_error.h"
+
+//------------- MCU header -------------//
+//#include "nrf.h"
+
+//--------------------------------------------------------------------+
+// TYPEDEFS
+//--------------------------------------------------------------------+
+typedef unsigned char byte_t;
+typedef float  float32_t;
+typedef double float64_t;
+
+//--------------------------------------------------------------------+
+// MACROS
+//--------------------------------------------------------------------+
+#define STRING_(x)  #x                             // stringify without expand
+#define XSTRING_(x) STRING_(x)                     // expand then stringify
+#define STRING_CONCAT_(a, b) a##b                  // concat without expand
+#define XSTRING_CONCAT_(a, b) STRING_CONCAT_(a, b) // expand then concat
+
+#define U16_HIGH_U8(u16) ((uint8_t) (((u16) >> 8) & 0x00ff))
+#define U16_LOW_U8(u16)  ((uint8_t) ((u16)       & 0x00ff))
+#define U16_TO_U8S_BE(u16)  U16_HIGH_U8(u16), U16_LOW_U8(u16)
+#define U16_TO_U8S_LE(u16)  U16_LOW_U8(u16), U16_HIGH_U8(u16)
+
+#define U32_B1_U8(u32) ((uint8_t) (((u32) >> 24) & 0x000000ff)) // MSB
+#define U32_B2_U8(u32) ((uint8_t) (((u32) >> 16) & 0x000000ff))
+#define U32_B3_U8(u32) ((uint8_t) (((u32) >>  8) & 0x000000ff))
+#define U32_B4_U8(u32) ((uint8_t) ((u32)        & 0x000000ff)) // LSB
+
+#define U32_TO_U8S_BE(u32) U32_B1_U8(u32), U32_B2_U8(u32), U32_B3_U8(u32), U32_B4_U8(u32)
+#define U32_TO_U8S_LE(u32) U32_B4_U8(u32), U32_B3_U8(u32), U32_B2_U8(u32), U32_B1_U8(u32)
+
+//--------------------------------------------------------------------+
+// INLINE FUNCTION
+//--------------------------------------------------------------------+
+#define memclr_(buffer, size)  memset(buffer, 0, size)
+
+//------------- Conversion -------------//
+/// form an uint32_t from 4 x uint8_t
+static inline uint32_t u32_from_u8(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t u32_from_u8(uint8_t b1, uint8_t b2, uint8_t b3, uint8_t b4)
+{
+  return (b1 << 24) + (b2 << 16) + (b3 << 8) + b4;
+}
+
+static inline uint8_t u16_high_u8(uint16_t u16) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint8_t u16_high_u8(uint16_t u16)
+{
+  return (uint8_t) ((u16 >> 8) & 0x00ff);
+}
+
+static inline uint8_t u16_low_u8(uint16_t u16) ATTR_CONST ATTR_ALWAYS_INLINE;
+static inline uint8_t u16_low_u8(uint16_t u16)
+{
+  return (uint8_t) (u16 & 0x00ff);
+}
+
+//------------- Min -------------//
+static inline uint8_t min8_of(uint8_t x, uint8_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint8_t min8_of(uint8_t x, uint8_t y)
+{
+  return (x < y) ? x : y;
+}
+
+static inline uint16_t min16_of(uint16_t x, uint16_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint16_t min16_of(uint16_t x, uint16_t y)
+{
+  return (x < y) ? x : y;
+}
+
+static inline uint32_t min32_of(uint32_t x, uint32_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t min32_of(uint32_t x, uint32_t y)
+{
+  return (x < y) ? x : y;
+}
+
+//------------- Max -------------//
+static inline uint32_t max32_of(uint32_t x, uint32_t y) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t max32_of(uint32_t x, uint32_t y)
+{
+  return (x > y) ? x : y;
+}
+
+//------------- Align -------------//
+static inline uint32_t align32 (uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t align32 (uint32_t value)
+{
+	return (value & 0xFFFFFFE0UL);
+}
+
+static inline uint32_t align16 (uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t align16 (uint32_t value)
+{
+	return (value & 0xFFFFFFF0UL);
+}
+
+static inline uint32_t align_n (uint32_t alignment, uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t align_n (uint32_t alignment, uint32_t value)
+{
+	return value & (~(alignment-1));
+}
+
+static inline uint32_t align4k (uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t align4k (uint32_t value)
+{
+	return (value & 0xFFFFF000UL);
+}
+
+static inline uint32_t offset4k(uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint32_t offset4k(uint32_t value)
+{
+	return (value & 0xFFFUL);
+}
+
+//------------- Mathematics -------------//
+/// inclusive range checking
+static inline bool is_in_range(uint32_t lower, uint32_t value, uint32_t upper) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline bool is_in_range(uint32_t lower, uint32_t value, uint32_t upper)
+{
+  return (lower <= value) && (value <= upper);
+}
+
+/// exclusive range checking
+static inline bool is_in_range_exclusive(uint32_t lower, uint32_t value, uint32_t upper) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline bool is_in_range_exclusive(uint32_t lower, uint32_t value, uint32_t upper)
+{
+  return (lower < value) && (value < upper);
+}
+
+static inline uint8_t log2_of(uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint8_t log2_of(uint32_t value)
+{
+  uint8_t result = 0; // log2 of a value is its MSB's position
+
+  while (value >>= 1)
+  {
+    result++;
+  }
+  return result;
+}
+
+// return the number of set bits in value
+static inline uint8_t cardinality_of(uint32_t value) ATTR_ALWAYS_INLINE ATTR_CONST;
+static inline uint8_t cardinality_of(uint32_t value)
+{
+  // Brian Kernighan's method goes through as many iterations as there are set bits. So if we have a 32-bit word with only
+  // the high bit set, then it will only go once through the loop
+  // Published in 1988, the C Programming Language 2nd Ed. (by Brian W. Kernighan and Dennis M. Ritchie)
+  // mentions this in exercise 2-9. On April 19, 2006 Don Knuth pointed out to me that this method
+  // "was first published by Peter Wegner in CACM 3 (1960), 322. (Also discovered independently by Derrick Lehmer and
+  // published in 1964 in a book edited by Beckenbach.)"
+  uint8_t count;
+  for (count = 0; value; count++)
+  {
+    value &= value - 1; // clear the least significant bit set
+  }
+
+  return count;
+}
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _COMMON_H_ */
+
+/**  @} */
+/**  @} */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/compiler.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/compiler.h
new file mode 100644
index 0000000000..5b04ac05d0
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/common/compiler.h
@@ -0,0 +1,160 @@
+/**************************************************************************/
+/*!
+    @file     compiler.h
+    @author   hathach (tinyusb.org)
+
+    @section LICENSE
+
+    Software License Agreement (BSD License)
+
+    Copyright (c) 2013, K. Townsend (microBuilder.eu)
+    All rights reserved.
+
+    Redistribution and use in source and binary forms, with or without
+    modification, are permitted provided that the following conditions are met:
+    1. Redistributions of source code must retain the above copyright
+    notice, this list of conditions and the following disclaimer.
+    2. Redistributions in binary form must reproduce the above copyright
+    notice, this list of conditions and the following disclaimer in the
+    documentation and/or other materials provided with the distribution.
+    3. Neither the name of the copyright holders nor the
+    names of its contributors may be used to endorse or promote products
+    derived from this software without specific prior written permission.
+
+    THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS ''AS IS'' AND ANY
+    EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+    WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+    DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER BE LIABLE FOR ANY
+    DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+    INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+    LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION HOWEVER CAUSED AND
+    ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+    INCLUDING NEGLIGENCE OR OTHERWISE ARISING IN ANY WAY OUT OF THE USE OF THIS
+    SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
+/**************************************************************************/
+
+/** \file
+ *  \brief GCC Header
+ */
+
+/** \ingroup Group_Compiler
+ *  \defgroup Group_GCC GNU GCC
+ *  @{
+ */
+
+#ifndef _COMPILER_GCC_H_
+#define _COMPILER_GCC_H_
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#include "projectconfig.h"
+
+//#ifndef __GNUC__
+//  #define ATTR_ALWAYS_INLINE
+//  #define ATTR_CONST
+//#else
+
+#ifdef _TEST_
+  #define ATTR_ALWAYS_INLINE
+  #define STATIC_
+  #define INLINE_
+#else
+  #define STATIC_ static
+  #define INLINE_ inline
+
+  #if CFG_DEBUG == 3
+    #define ATTR_ALWAYS_INLINE  // no inline for debug = 3
+  #endif
+#endif
+
+
+#ifdef __GNUC__
+
+#define ALIGN_OF(x)                __alignof__(x)
+
+/// Normally, the compiler places the objects it generates in sections like data or bss & function in text. Sometimes, however, you need additional sections, or you need certain particular variables to appear in special sections, for example to map to special hardware. The section attribute specifies that a variable (or function) lives in a particular section
+#define ATTR_SECTION(section)      __attribute__ ((#section))
+
+/// If this attribute is used on a function declaration and a call to such a function is not eliminated through dead code elimination or other optimizations, an error that includes message is diagnosed. This is useful for compile-time checking
+#define ATTR_ERROR(Message)        __attribute__ ((error(Message)))
+
+/// If this attribute is used on a function declaration and a call to such a function is not eliminated through dead code elimination or other optimizations, a warning that includes message is diagnosed. This is useful for compile-time checking
+#define ATTR_WARNING(Message)      __attribute__ ((warning(Message)))
+
+/**
+ *  \defgroup Group_VariableAttr Variable Attributes
+ *  @{
+ */
+
+/// This attribute specifies a minimum alignment for the variable or structure field, measured in bytes
+#define ATTR_ALIGNED(Bytes)        __attribute__ ((aligned(Bytes)))
+
+/// The packed attribute specifies that a variable or structure field should have the smallest possible alignment—one byte for a variable, and one bit for a field, unless you specify a larger value with the aligned attribute
+#define ATTR_PACKED                __attribute__ ((packed))
+
+#define ATTR_PREPACKED
+
+#define ATTR_PACKED_STRUCT(x)    x __attribute__ ((packed))
+/** @} */
+
+/**
+ *  \defgroup Group_FuncAttr Function Attributes
+ *  @{
+ */
+
+#ifndef ATTR_ALWAYS_INLINE
+/// Generally, functions are not inlined unless optimization is specified. For functions declared inline, this attribute inlines the function even if no optimization level is specified
+#define ATTR_ALWAYS_INLINE         __attribute__ ((always_inline))
+#endif
+
+/// The nonnull attribute specifies that some function parameters should be non-null pointers. f the compiler determines that a null pointer is passed in an argument slot marked as non-null, and the -Wnonnull option is enabled, a warning is issued. All pointer arguments are marked as non-null
+#define ATTR_NON_NULL              __attribute__ ((nonull))
+
+/// Many functions have no effects except the return value and their return value depends only on the parameters and/or global variables. Such a function can be subject to common subexpression elimination and loop optimization just as an arithmetic operator would be. These functions should be declared with the attribute pure
+#define ATTR_PURE                  __attribute__ ((pure))
+
+/// Many functions do not examine any values except their arguments, and have no effects except the return value. Basically this is just slightly more strict class than the pure attribute below, since function is not allowed to read global memory.
+/// Note that a function that has pointer arguments and examines the data pointed to must not be declared const. Likewise, a function that calls a non-const function usually must not be const. It does not make sense for a const function to return void
+#define ATTR_CONST                 __attribute__ ((const))
+
+/// The deprecated attribute results in a warning if the function is used anywhere in the source file. This is useful when identifying functions that are expected to be removed in a future version of a program. The warning also includes the location of the declaration of the deprecated function, to enable users to easily find further information about why the function is deprecated, or what they should do instead. Note that the warnings only occurs for uses
+#define ATTR_DEPRECATED            __attribute__ ((deprecated))
+
+/// Same as the deprecated attribute with optional message in the warning
+#define ATTR_DEPRECATED_MESS(mess) __attribute__ ((deprecated(mess)))
+
+/// The weak attribute causes the declaration to be emitted as a weak symbol rather than a global. This is primarily useful in defining library functions that can be overridden in user code
+#define ATTR_WEAK                  __attribute__ ((weak))
+
+/// The alias attribute causes the declaration to be emitted as an alias for another symbol, which must be specified
+#define ATTR_ALIAS(func)           __attribute__ ((alias(#func)))
+
+/// The weakref attribute marks a declaration as a weak reference. It is equivalent with weak + alias attribute, but require function is static
+#define ATTR_WEAKREF(func)         __attribute__ ((weakref(#func)))
+
+/// The warn_unused_result attribute causes a warning to be emitted if a caller of the function with this attribute does not use its return value. This is useful for functions where not checking the result is either a security problem or always a bug
+#define ATTR_WARN_UNUSED_RESULT    __attribute__ ((warn_unused_result))
+
+/// This attribute, attached to a function, means that code must be emitted for the function even if it appears that the function is not referenced. This is useful, for example, when the function is referenced only in inline assembly.
+#define ATTR_USED                  __attribute__ ((used))
+
+/// This attribute, attached to a function, means that the function is meant to be possibly unused. GCC does not produce a warning for this function.
+#define ATTR_UNUSED                __attribute__ ((unused))
+
+#elif defined (__ICCARM__) //IAR
+  #define ATTR_ALWAYS_INLINE // IAR dosn't provide such a syntax extension in function's prototypes.
+  #define ATTR_CONST         // IAR dosn't provide such a syntax extension in function's prototypes.
+#endif
+
+/** @} */
+
+#ifdef __cplusplus
+ }
+#endif
+
+#endif /* _COMPILER_GCC_H_ */
+
+/// @}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp
new file mode 100644
index 0000000000..a06de22ffd
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.cpp
@@ -0,0 +1,303 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "nRF5xCharacteristicDescriptorDiscoverer.h"
+#include "nrf_ble_err.h"
+#include "ble/DiscoveredCharacteristicDescriptor.h"
+
+nRF5xCharacteristicDescriptorDiscoverer::nRF5xCharacteristicDescriptorDiscoverer() :
+    discoveryRunning() {
+    // nothing to do
+}
+
+nRF5xCharacteristicDescriptorDiscoverer::~nRF5xCharacteristicDescriptorDiscoverer() {
+    // nothing to do
+}
+
+ble_error_t nRF5xCharacteristicDescriptorDiscoverer::launch(
+    const DiscoveredCharacteristic& characteristic,
+    const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback,
+    const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback
+) {
+    Gap::Handle_t connHandle = characteristic.getConnectionHandle();
+    // it is ok to deduce that the start handle for descriptors is after
+    // the characteristic declaration and the characteristic value declaration
+    // see BLUETOOTH SPECIFICATION Version 4.2 [Vol 3, Part G] (3.3)
+    Gap::Handle_t descriptorStartHandle = characteristic.getDeclHandle() + 2;
+    Gap::Handle_t descriptorEndHandle = characteristic.getLastHandle();
+
+    // check if there is any descriptor to discover
+    if (descriptorEndHandle < descriptorStartHandle) {
+        CharacteristicDescriptorDiscovery::TerminationCallbackParams_t termParams = {
+            characteristic,
+            BLE_ERROR_NONE
+        };
+        terminationCallback.call(&termParams);
+        return BLE_ERROR_NONE;
+    }
+
+    // check if we can run this discovery
+    if (isConnectionInUse(connHandle)) {
+        return BLE_STACK_BUSY;
+    }
+
+    // get a new discovery slot, if none are available, just return
+    Discovery* discovery = getAvailableDiscoverySlot();
+    if(discovery == NULL) {
+        return BLE_STACK_BUSY;
+    }
+
+    // try to launch the discovery
+    ble_error_t err = gattc_descriptors_discover(connHandle, descriptorStartHandle, descriptorEndHandle);
+    if(!err) {
+        // commit the new discovery to its slot
+        *discovery = Discovery(characteristic, discoveryCallback, terminationCallback);
+    }
+
+    return err;
+}
+
+bool nRF5xCharacteristicDescriptorDiscoverer::isActive(const DiscoveredCharacteristic& characteristic) const {
+    for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) {
+        if(discoveryRunning[i].getCharacteristic() == characteristic) {
+            return true;
+        }
+    }
+    return false;
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::requestTerminate(const DiscoveredCharacteristic& characteristic) {
+    Discovery* discovery = findRunningDiscovery(characteristic);
+    if(discovery) {
+        // call terminate anyway
+        terminate(discovery, BLE_ERROR_NONE);
+    }
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::process(uint16_t connectionHandle, const ble_gattc_evt_desc_disc_rsp_t& descriptors) {
+    Discovery* discovery = findRunningDiscovery(connectionHandle);
+    // the discovery has been removed
+    if(!discovery) {
+        return;
+    }
+
+    for (uint16_t i = 0; i < descriptors.count; ++i) {
+        const ble_gattc_desc_t& desc = descriptors.descs[i];
+        const ble_uuid_t& uuid = desc.uuid;
+
+        if (uuid.type == BLE_UUID_TYPE_BLE) {
+            discovery->process(
+                desc.handle, UUID(uuid.uuid)
+            );
+        } else {
+            // discover attribute infos of the descriptor
+            ble_error_t err = gattc_attr_info_discover(connectionHandle, desc.handle, desc.handle);
+            if (err) {
+                terminate(discovery, err);
+            }
+
+            return;
+        }
+    }
+
+    // prepare the next discovery request (if needed)
+    uint16_t startHandle = descriptors.descs[descriptors.count - 1].handle + 1;
+    uint16_t endHandle = discovery->getCharacteristic().getLastHandle();
+
+    if(startHandle > endHandle) {
+        terminate(discovery, BLE_ERROR_NONE);
+        return;
+    }
+
+    ble_error_t err = gattc_descriptors_discover(connectionHandle, startHandle, endHandle);
+    if(err) {
+        terminate(discovery, err);
+        return;
+    }
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::processAttributeInformation(
+    uint16_t connectionHandle, const ble_gattc_evt_attr_info_disc_rsp_t& infos) {
+    Discovery* discovery = findRunningDiscovery(connectionHandle);
+    // the discovery has been removed
+    if(!discovery) {
+        return;
+    }
+
+    // for all UUIDS found, process the discovery
+    for (uint16_t i = 0; i < infos.count; ++i) {
+        bool use_16bits_uuids = infos.format == BLE_GATTC_ATTR_INFO_FORMAT_16BIT;
+        const ble_gattc_attr_info_t& attr_info = infos.attr_info[i];
+        UUID uuid = use_16bits_uuids ? UUID(attr_info.info.uuid16.uuid) : UUID(attr_info.info.uuid128.uuid128,  UUID::LSB);
+        discovery->process(attr_info.handle, uuid);
+    }
+
+    // prepare the next round of descriptors discovery
+    uint16_t startHandle = infos.attr_info[infos.count - 1].handle + 1;
+    uint16_t endHandle = discovery->getCharacteristic().getLastHandle();
+
+    if(startHandle > endHandle) {
+        terminate(discovery, BLE_ERROR_NONE);
+        return;
+    }
+
+    ble_error_t err = gattc_descriptors_discover(connectionHandle, startHandle, endHandle);
+    if(err) {
+        terminate(discovery, err);
+        return;
+    }
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::terminate(uint16_t handle, ble_error_t err) {
+    Discovery* discovery = findRunningDiscovery(handle);
+    // the discovery has already been terminated
+    if(!discovery) {
+        return;
+    }
+
+    terminate(discovery, err);
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::terminate(Discovery* discovery, ble_error_t err) {
+    // temporary copy, user code can try to launch a new discovery in the onTerminate
+    // callback. So, this discovery should not appear in such case.
+    Discovery tmp = *discovery;
+    *discovery = Discovery();
+    tmp.terminate(err);
+}
+
+nRF5xCharacteristicDescriptorDiscoverer::Discovery*
+nRF5xCharacteristicDescriptorDiscoverer::findRunningDiscovery(const DiscoveredCharacteristic& characteristic) {
+    for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) {
+        if((discoveryRunning[i].getCharacteristic() == characteristic) &&
+           (discoveryRunning[i].isEmpty() == false)) {
+            return &discoveryRunning[i];
+        }
+    }
+    return NULL;
+}
+
+nRF5xCharacteristicDescriptorDiscoverer::Discovery*
+nRF5xCharacteristicDescriptorDiscoverer::findRunningDiscovery(uint16_t handle) {
+    for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) {
+        if((discoveryRunning[i].getCharacteristic().getConnectionHandle() == handle) &&
+           (discoveryRunning[i].isEmpty() == false)) {
+            return &discoveryRunning[i];
+        }
+    }
+    return NULL;
+}
+
+nRF5xCharacteristicDescriptorDiscoverer::Discovery*
+nRF5xCharacteristicDescriptorDiscoverer::getAvailableDiscoverySlot() {
+    for(size_t i = 0; i < MAXIMUM_CONCURRENT_CONNECTIONS_COUNT; ++i) {
+        if(discoveryRunning[i].isEmpty()) {
+            return &discoveryRunning[i];
+        }
+    }
+    return NULL;
+}
+
+bool nRF5xCharacteristicDescriptorDiscoverer::isConnectionInUse(uint16_t connHandle) {
+     return findRunningDiscovery(connHandle) != NULL;
+}
+
+ble_error_t nRF5xCharacteristicDescriptorDiscoverer::gattc_descriptors_discover(
+    uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle) {
+
+    ble_gattc_handle_range_t discoveryRange = {
+        start_handle,
+        end_handle
+    };
+    uint32_t err = sd_ble_gattc_descriptors_discover(connection_handle, &discoveryRange);
+
+    switch(err) {
+        case NRF_SUCCESS:
+            return BLE_ERROR_NONE;
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            return BLE_ERROR_INVALID_PARAM;
+        case NRF_ERROR_INVALID_ADDR:
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        case NRF_ERROR_BUSY:
+            return BLE_STACK_BUSY;
+        default:
+            return BLE_ERROR_UNSPECIFIED;
+    }
+}
+
+ble_error_t nRF5xCharacteristicDescriptorDiscoverer::gattc_attr_info_discover(
+    uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle) {
+    ble_gattc_handle_range_t handle_range = { start_handle, end_handle };
+    uint32_t err = sd_ble_gattc_attr_info_discover(connection_handle, &handle_range);
+
+    switch(err) {
+        case NRF_SUCCESS:
+            return BLE_ERROR_NONE;
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            return BLE_ERROR_INVALID_PARAM;
+        case NRF_ERROR_INVALID_ADDR:
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        case NRF_ERROR_BUSY:
+            return BLE_STACK_BUSY;
+        case NRF_ERROR_INVALID_STATE:
+            return BLE_ERROR_INVALID_STATE;
+        default:
+            return BLE_ERROR_UNSPECIFIED;
+    }
+}
+
+
+
+// implementation of nRF5xCharacteristicDescriptorDiscoverer::Discovery
+
+nRF5xCharacteristicDescriptorDiscoverer::Discovery::Discovery() :
+    characteristic(), onDiscovery(), onTerminate() {
+}
+
+nRF5xCharacteristicDescriptorDiscoverer::Discovery::Discovery(
+    const DiscoveredCharacteristic& c, const DiscoveryCallback_t& dCb, const TerminationCallback_t& tCb) :
+    characteristic(c), onDiscovery(dCb), onTerminate(tCb) {
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::Discovery::process(
+    GattAttribute::Handle_t handle, const UUID& uuid) {
+    CharacteristicDescriptorDiscovery::DiscoveryCallbackParams_t params = {
+        characteristic,
+        DiscoveredCharacteristicDescriptor(
+            characteristic.getGattClient(),
+            characteristic.getConnectionHandle(),
+            handle,
+            uuid
+        )
+    };
+    onDiscovery.call(&params);
+}
+
+void nRF5xCharacteristicDescriptorDiscoverer::Discovery::terminate(ble_error_t err) {
+    CharacteristicDescriptorDiscovery::TerminationCallbackParams_t params = {
+        characteristic,
+        err
+    };
+
+    onTerminate.call(&params);
+}
+
+bool nRF5xCharacteristicDescriptorDiscoverer::Discovery::isEmpty() const {
+    return *this == Discovery();
+}
+
+const DiscoveredCharacteristic& nRF5xCharacteristicDescriptorDiscoverer::Discovery::getCharacteristic() const {
+    return characteristic;
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h
new file mode 100644
index 0000000000..285a4a1288
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xCharacteristicDescriptorDiscoverer.h
@@ -0,0 +1,227 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__
+#define __NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__
+
+#include "ble/Gap.h"
+#include "ble/DiscoveredCharacteristic.h"
+#include "ble/CharacteristicDescriptorDiscovery.h"
+#include "ble/GattClient.h"
+#include "nrf_ble_gattc.h"
+
+/**
+ * @brief Manage the discovery of Characteristic descriptors
+ * @details is a bridge between BLE API and Nordic stack regarding Characteristic
+ * Descriptor discovery. The BLE API can launch, monitor and ask for termination
+ * of a discovery. The Nordic stack will provide new descriptors and indicate when
+ * the discovery is done.
+ */
+class nRF5xCharacteristicDescriptorDiscoverer
+{
+    typedef CharacteristicDescriptorDiscovery::DiscoveryCallback_t DiscoveryCallback_t;
+    typedef CharacteristicDescriptorDiscovery::TerminationCallback_t TerminationCallback_t;
+
+public:
+    /**
+     * @brief Construct a new characteristic descriptor discoverer.
+     */
+    nRF5xCharacteristicDescriptorDiscoverer();
+
+    /**
+     * @brief Destroy a characteristic descriptor discoverer.
+     */
+    ~nRF5xCharacteristicDescriptorDiscoverer();
+
+    /**
+     * Launch a new characteristic descriptor discovery for a given DiscoveredCharacteristic.
+     * @param characteristic The characteristic owning the descriptors to discover.
+     * @param discoveryCallback The callback called when a descriptor is discovered.
+     * @param terminationCallback The callback called when the discovery process end.
+     * @return BLE_ERROR_NONE if characteristic descriptor discovery is launched successfully;
+     *         else an appropriate error.
+     * @note: this will be called by BLE API side.
+     */
+    ble_error_t launch(
+        const DiscoveredCharacteristic& characteristic,
+        const DiscoveryCallback_t& discoveryCallback,
+        const TerminationCallback_t& terminationCallback
+    );
+
+    /**
+     * @brief indicate if a characteristic descriptor discovery is active for a
+     * given DiscoveredCharacteristic.
+     * @param characteristic The characteristic for whom the descriptor might be
+     * currently discovered.
+     * @return true if descriptors of characteristic are discovered, false otherwise.
+     * @note: this will be called by BLE API side.
+     */
+    bool isActive(const DiscoveredCharacteristic& characteristic) const;
+
+    /**
+     * @brief request the termination of characteristic descriptor discovery
+     * for a give DiscoveredCharacteristic
+     * @param characteristic The characteristic for whom the descriptor discovery
+     * should be stopped.
+     * @note: this will be called by BLE API side.
+     */
+    void requestTerminate(const DiscoveredCharacteristic& characteristic);
+
+    /**
+     * @brief process descriptors discovered from the Nordic stack.
+     * @param connectionHandle The connection handle upon which descriptors has been
+     * discovered.
+     * @param descriptors Discovered descriptors.
+     * @note This will be called by the Nordic stack.
+     */
+    void process(uint16_t connectionHandle, const ble_gattc_evt_desc_disc_rsp_t& descriptors);
+
+    /**
+     * @brief Called by the Nordic stack when the discovery is over.
+     * @param The connection handle upon which the discovery process is done.
+     * @param err An error if the termination is due to an error.
+     */
+    void terminate(uint16_t connectionHandle, ble_error_t err);
+
+    /**
+    * @brief process attribute informations from the Nordic stack.
+    * @param connectionHandle The connection handle upon which
+    * attribute informations has been fetch.
+    * @param infos Informations around attribute, in that case the
+    * 128bit UUID of a descriptor.
+    * @note This will be called by the Nordic stack.
+     */
+    void processAttributeInformation(uint16_t handle, const ble_gattc_evt_attr_info_disc_rsp_t& infos);
+
+private:
+    // protection against copy construction and assignment
+    nRF5xCharacteristicDescriptorDiscoverer(const nRF5xCharacteristicDescriptorDiscoverer&);
+    nRF5xCharacteristicDescriptorDiscoverer& operator=(const nRF5xCharacteristicDescriptorDiscoverer&);
+
+    /**
+     * @brief Discovery process, it store the DiscoveredCharacteristic, the
+     * discovery callback and the termination callback.
+     */
+    class Discovery {
+    public:
+        /**
+         * @brief Construct an empty discovery, such can be considerate as a not running discovery.
+         * @note #isEmpty function will return true
+         */
+        Discovery();
+
+        /**
+         * @brief Construct a valid discovery process.
+         *
+         * @param c the characteristic from whom descriptors will be discovered.
+         * @param dCb The discovery callback called each time a descriptor is discovered.
+         * @param tCb The termination callback called when the discovery terminate.
+         *
+         * @note #isEmpty function will return false
+         */
+        Discovery(const DiscoveredCharacteristic& c, const DiscoveryCallback_t& dCb, const TerminationCallback_t& tCb);
+
+        /**
+         * @brief Process the discovery of a descriptor.
+         *
+         * @param handle The attribute handle of the descriptor found
+         * @param uuid The UUID of the descriptor found.
+         */
+        void process(GattAttribute::Handle_t handle, const UUID& uuid);
+
+        /**
+         * @brief Terminate the discovery process.
+         *
+         * @param err Error associate with the termination
+         * @note after this call #isEmpty function will return true.
+         */
+        void terminate(ble_error_t err);
+
+        /**
+         * @brief check if the discovery process is empty or not. Empty discovery are
+         * not running.
+         *
+         * @detail Discovery are empty after:
+         *     - a default construction
+         *     - a copy construction form a default constructed
+         *     - an assignment from a default constructed Discovery
+         * @return true if the Discovery is empty and false otherwise.
+         */
+        bool isEmpty() const;
+
+        /**
+         * @brief return the characteristic from whom descriptors are discovered.
+         * @return the characteristic from whom descriptors are discovered.
+         */
+        const DiscoveredCharacteristic& getCharacteristic() const;
+
+        /**
+         * @brief equal to operator, test if two discovery process are equal
+         *
+         * @param lhs left hand side of the expression
+         * @param rhs right hand side of the expression
+         * @return true if lhs == rhs
+         */
+        friend bool operator==(const Discovery& lhs, const Discovery& rhs) {
+            return lhs.characteristic == rhs.characteristic &&
+                   lhs.onDiscovery == rhs.onDiscovery &&
+                   lhs.onTerminate == rhs.onTerminate;
+        }
+
+        /**
+         * @brief not equal to operator, test if two discovery process are not equal
+         *
+         * @param lhs left hand side of the expression
+         * @param rhs right hand side of the expression
+         * @return true if lhs != rhs
+         */
+        friend bool operator!=(const Discovery& lhs, const Discovery& rhs) {
+            return !(lhs == rhs);
+        }
+
+    private:
+        DiscoveredCharacteristic characteristic;
+        DiscoveryCallback_t onDiscovery;
+        TerminationCallback_t onTerminate;
+    };
+
+    // find a running discovery process
+    Discovery* findRunningDiscovery(const DiscoveredCharacteristic& characteristic);
+    Discovery* findRunningDiscovery(uint16_t handle);
+
+    // Called to terminate a discovery is over.
+    void terminate(Discovery* discovery, ble_error_t err);
+
+    // get one slot for a discovery process
+    Discovery* getAvailableDiscoverySlot();
+
+    // indicate if a connection is already running a discovery
+    bool isConnectionInUse(uint16_t connHandle);
+
+    // low level start of a discovery
+    static ble_error_t gattc_descriptors_discover(uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle);
+
+    // discovery of 128bits UUIDS
+    static ble_error_t gattc_attr_info_discover(uint16_t connection_handle, uint16_t start_handle, uint16_t end_handle);
+
+    // count of concurrent connections which can run a descriptor discovery process
+    static const size_t MAXIMUM_CONCURRENT_CONNECTIONS_COUNT = 3;
+
+    // array of running discoveries
+    Discovery discoveryRunning[MAXIMUM_CONCURRENT_CONNECTIONS_COUNT];
+};
+
+#endif /*__NRF_CHARACTERISTIC_DESCRIPTOR_DISCOVERY_H__*/
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp
new file mode 100644
index 0000000000..a228a624d2
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.cpp
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nRF5xDiscoveredCharacteristic.h"
+#include "nRF5xGattClient.h"
+#include "nrf_ble_gatt.h"
+
+void
+nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient         *gattcIn,
+                                     Gap::Handle_t            connectionHandleIn,
+                                     ble_gatt_char_props_t    propsIn,
+                                     GattAttribute::Handle_t  declHandleIn,
+                                     GattAttribute::Handle_t  valueHandleIn)
+{
+    gattc       = gattcIn;
+    connHandle  = connectionHandleIn;
+    declHandle  = declHandleIn;
+    valueHandle = valueHandleIn;
+
+    props._broadcast       = propsIn.broadcast;
+    props._read            = propsIn.read;
+    props._writeWoResp     = propsIn.write_wo_resp;
+    props._write           = propsIn.write;
+    props._notify          = propsIn.notify;
+    props._indicate        = propsIn.indicate;
+    props._authSignedWrite = propsIn.auth_signed_wr;
+}
+
+void
+nRF5xDiscoveredCharacteristic::setup(nRF5xGattClient         *gattcIn,
+                                      Gap::Handle_t            connectionHandleIn,
+                                     UUID::ShortUUIDBytes_t   uuidIn,
+                                     ble_gatt_char_props_t    propsIn,
+                                     GattAttribute::Handle_t  declHandleIn,
+                                     GattAttribute::Handle_t  valueHandleIn)
+{
+    gattc       = gattcIn;
+    connHandle  = connectionHandleIn;
+    uuid        = uuidIn;
+    declHandle  = declHandleIn;
+    valueHandle = valueHandleIn;
+
+    props._broadcast       = propsIn.broadcast;
+    props._read            = propsIn.read;
+    props._writeWoResp     = propsIn.write_wo_resp;
+    props._write           = propsIn.write;
+    props._notify          = propsIn.notify;
+    props._indicate        = propsIn.indicate;
+    props._authSignedWrite = propsIn.auth_signed_wr;
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h
new file mode 100644
index 0000000000..7b4bfc82c7
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xDiscoveredCharacteristic.h
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF_DISCOVERED_CHARACTERISTIC_H__
+#define __NRF_DISCOVERED_CHARACTERISTIC_H__
+
+#include "ble/DiscoveredCharacteristic.h"
+#include "nrf_ble_gatt.h"
+
+class nRF5xGattClient; /* forward declaration */
+
+class nRF5xDiscoveredCharacteristic : public DiscoveredCharacteristic {
+public:
+    void setup(nRF5xGattClient         *gattcIn,
+               Gap::Handle_t            connectionHandleIn,
+               ble_gatt_char_props_t    propsIn,
+               GattAttribute::Handle_t  declHandleIn,
+               GattAttribute::Handle_t  valueHandleIn);
+
+    void setup(nRF5xGattClient         *gattcIn,
+               Gap::Handle_t            connectionHandleIn,
+               UUID::ShortUUIDBytes_t   uuidIn,
+               ble_gatt_char_props_t    propsIn,
+               GattAttribute::Handle_t  declHandleIn,
+               GattAttribute::Handle_t  valueHandleIn);
+
+    void setLastHandle(GattAttribute::Handle_t last) {
+      lastHandle = last;
+    }
+};
+
+#endif /* __NRF_DISCOVERED_CHARACTERISTIC_H__ */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp
new file mode 100644
index 0000000000..a2f59dd4da
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.cpp
@@ -0,0 +1,947 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nRF5xn.h"
+#ifdef YOTTA_CFG_MBED_OS
+    #include "mbed-drivers/mbed.h"
+#else
+    #include "mbed.h"
+#endif
+#include "ble/BLE.h"
+
+#include "common/common.h"
+#include "ble_advdata.h"
+#include "nrf_ble_hci.h"
+
+void radioNotificationStaticCallback(bool param) {
+    nRF5xGap &gap = (nRF5xGap &) nRF5xn::Instance(BLE::DEFAULT_INSTANCE).getGap();
+    gap.processRadioNotificationEvent(param);
+}
+
+/**************************************************************************/
+/*!
+    @brief  Sets the advertising parameters and payload for the device
+
+    @param[in]  params
+                Basic advertising details, including the advertising
+                delay, timeout and how the device should be advertised
+    @params[in] advData
+                The primary advertising data payload
+    @params[in] scanResponse
+                The optional Scan Response payload if the advertising
+                type is set to \ref GapAdvertisingParams::ADV_SCANNABLE_UNDIRECTED
+                in \ref GapAdveritinngParams
+
+    @returns    \ref ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+
+    @retval     BLE_ERROR_BUFFER_OVERFLOW
+                The proposed action would cause a buffer overflow.  All
+                advertising payloads must be <= 31 bytes, for example.
+
+    @retval     BLE_ERROR_NOT_IMPLEMENTED
+                A feature was requested that is not yet supported in the
+                nRF51 firmware or hardware.
+
+    @retval     BLE_ERROR_PARAM_OUT_OF_RANGE
+                One of the proposed values is outside the valid range.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::setAdvertisingData(const GapAdvertisingData &advData, const GapAdvertisingData &scanResponse)
+{
+    /* Make sure we don't exceed the advertising payload length */
+    if (advData.getPayloadLen() > GAP_ADVERTISING_DATA_MAX_PAYLOAD) {
+        return BLE_ERROR_BUFFER_OVERFLOW;
+    }
+
+    /* Make sure we have a payload! */
+    if (advData.getPayloadLen() == 0) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* Check the scan response payload limits */
+    //if ((params.getAdvertisingType() == GapAdvertisingParams::ADV_SCANNABLE_UNDIRECTED))
+    //{
+    //    /* Check if we're within the upper limit */
+    //    if (advData.getPayloadLen() > GAP_ADVERTISING_DATA_MAX_PAYLOAD)
+    //    {
+    //        return BLE_ERROR_BUFFER_OVERFLOW;
+    //    }
+    //    /* Make sure we have a payload! */
+    //    if (advData.getPayloadLen() == 0)
+    //    {
+    //        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    //    }
+    //}
+
+    /* Send advertising data! */
+    ASSERT(ERROR_NONE ==
+           sd_ble_gap_adv_data_set(advData.getPayload(),
+                                   advData.getPayloadLen(),
+                                   scanResponse.getPayload(),
+                                   scanResponse.getPayloadLen()),
+           BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    /* Make sure the GAP Service appearance value is aligned with the
+     *appearance from GapAdvertisingData */
+    ASSERT(ERROR_NONE == sd_ble_gap_appearance_set(advData.getAppearance()),
+           BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    /* ToDo: Perform some checks on the payload, for example the Scan Response can't */
+    /* contains a flags AD type, etc. */
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Starts the BLE HW, initialising any services that were
+            added before this function was called.
+
+    @note   All services must be added before calling this function!
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::startAdvertising(const GapAdvertisingParams &params)
+{
+    /* Make sure we support the advertising type */
+    if (params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) {
+        /* ToDo: This requires a propery security implementation, etc. */
+        return BLE_ERROR_NOT_IMPLEMENTED;
+    }
+
+    /* Check interval range */
+    if (params.getAdvertisingType() == GapAdvertisingParams::ADV_NON_CONNECTABLE_UNDIRECTED) {
+        /* Min delay is slightly longer for unconnectable devices */
+        if ((params.getIntervalInADVUnits() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN_NONCON) ||
+            (params.getIntervalInADVUnits() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) {
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        }
+    } else {
+        if ((params.getIntervalInADVUnits() < GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MIN) ||
+            (params.getIntervalInADVUnits() > GapAdvertisingParams::GAP_ADV_PARAMS_INTERVAL_MAX)) {
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        }
+    }
+
+    /* Check timeout is zero for Connectable Directed */
+    if ((params.getAdvertisingType() == GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) && (params.getTimeout() != 0)) {
+        /* Timeout must be 0 with this type, although we'll never get here */
+        /* since this isn't implemented yet anyway */
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* Check timeout for other advertising types */
+    if ((params.getAdvertisingType() != GapAdvertisingParams::ADV_CONNECTABLE_DIRECTED) &&
+        (params.getTimeout() > GapAdvertisingParams::GAP_ADV_PARAMS_TIMEOUT_MAX)) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* Allocate the stack's whitelist statically */
+    ble_gap_whitelist_t  whitelist;
+    ble_gap_addr_t      *whitelistAddressPtrs[YOTTA_CFG_WHITELIST_MAX_SIZE];
+    ble_gap_irk_t       *whitelistIrkPtrs[YOTTA_CFG_IRK_TABLE_MAX_SIZE];
+    /* Initialize the whitelist */
+    whitelist.pp_addrs   = whitelistAddressPtrs;
+    whitelist.pp_irks    = whitelistIrkPtrs;
+    whitelist.addr_count = 0;
+    whitelist.irk_count  = 0;
+
+    /* Add missing IRKs to whitelist from the bond table held by the SoftDevice */
+    if (advertisingPolicyMode != Gap::ADV_POLICY_IGNORE_WHITELIST) {
+        ble_error_t error = generateStackWhitelist(whitelist);
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    }
+
+    /* Start Advertising */
+    ble_gap_adv_params_t adv_para = {0};
+
+    adv_para.type        = params.getAdvertisingType();
+    adv_para.p_peer_addr = NULL;                           // Undirected advertisement
+    adv_para.fp          = advertisingPolicyMode;
+    adv_para.p_whitelist = &whitelist;
+    adv_para.interval    = params.getIntervalInADVUnits(); // advertising interval (in units of 0.625 ms)
+    adv_para.timeout     = params.getTimeout();
+
+    uint32_t err = sd_ble_gap_adv_start(&adv_para);
+    switch(err) {
+        case ERROR_NONE:
+            return BLE_ERROR_NONE;
+        case NRF_ERROR_NO_MEM:
+            return BLE_ERROR_NO_MEM;
+        default:
+            return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+}
+
+/* Observer role is not supported by S110, return BLE_ERROR_NOT_IMPLEMENTED */
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+ble_error_t nRF5xGap::startRadioScan(const GapScanningParams &scanningParams)
+{
+    /* Allocate the stack's whitelist statically */
+    ble_gap_whitelist_t  whitelist;
+    ble_gap_addr_t      *whitelistAddressPtrs[YOTTA_CFG_WHITELIST_MAX_SIZE];
+    ble_gap_irk_t       *whitelistIrkPtrs[YOTTA_CFG_IRK_TABLE_MAX_SIZE];
+    /* Initialize the whitelist */
+    whitelist.pp_addrs   = whitelistAddressPtrs;
+    whitelist.pp_irks    = whitelistIrkPtrs;
+    whitelist.addr_count = 0;
+    whitelist.irk_count  = 0;
+
+    /* Add missing IRKs to whitelist from the bond table held by the SoftDevice */
+    if (scanningPolicyMode != Gap::SCAN_POLICY_IGNORE_WHITELIST) {
+        ble_error_t error = generateStackWhitelist(whitelist);
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    }
+    
+    ble_gap_scan_params_t scanParams;
+    
+    scanParams.active      = scanningParams.getActiveScanning(); /**< If 1, perform active scanning (scan requests). */
+    scanParams.selective   = scanningPolicyMode;    /**< If 1, ignore unknown devices (non whitelisted). */
+    scanParams.p_whitelist = &whitelist; /**< Pointer to whitelist, NULL if none is given. */
+    scanParams.interval    = scanningParams.getInterval();  /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+    scanParams.window      = scanningParams.getWindow();    /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+    scanParams.timeout     = scanningParams.getTimeout();   /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
+
+    if (sd_ble_gap_scan_start(&scanParams) != NRF_SUCCESS) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t nRF5xGap::stopScan(void) {
+    if (sd_ble_gap_scan_stop() == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    }
+
+    return BLE_STACK_BUSY;
+}
+#endif
+
+/**************************************************************************/
+/*!
+    @brief  Stops the BLE HW and disconnects from any devices
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::stopAdvertising(void)
+{
+    /* Stop Advertising */
+    ASSERT(ERROR_NONE == sd_ble_gap_adv_stop(), BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    state.advertising = 0;
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t nRF5xGap::connect(const Address_t             peerAddr,
+                              BLEProtocol::AddressType_t  peerAddrType,
+                              const ConnectionParams_t   *connectionParams,
+                              const GapScanningParams    *scanParamsIn)
+{
+    ble_gap_addr_t addr;
+    addr.addr_type = peerAddrType;
+    memcpy(addr.addr, peerAddr, Gap::ADDR_LEN);
+
+    ble_gap_conn_params_t connParams;
+    if (connectionParams != NULL) {
+        connParams.min_conn_interval = connectionParams->minConnectionInterval;
+        connParams.max_conn_interval = connectionParams->maxConnectionInterval;
+        connParams.slave_latency     = connectionParams->slaveLatency;
+        connParams.conn_sup_timeout  = connectionParams->connectionSupervisionTimeout;
+    } else {
+        connParams.min_conn_interval = 50;
+        connParams.max_conn_interval = 100;
+        connParams.slave_latency     = 0;
+        connParams.conn_sup_timeout  = 600;
+    }
+
+    /* Allocate the stack's whitelist statically */
+    ble_gap_whitelist_t  whitelist;
+    ble_gap_addr_t      *whitelistAddressPtrs[YOTTA_CFG_WHITELIST_MAX_SIZE];
+    ble_gap_irk_t       *whitelistIrkPtrs[YOTTA_CFG_IRK_TABLE_MAX_SIZE];
+    /* Initialize the whitelist */
+    whitelist.pp_addrs   = whitelistAddressPtrs;
+    whitelist.pp_irks    = whitelistIrkPtrs;
+    whitelist.addr_count = 0;
+    whitelist.irk_count  = 0;
+
+    /* Add missing IRKs to whitelist from the bond table held by the SoftDevice */
+    if (scanningPolicyMode != Gap::SCAN_POLICY_IGNORE_WHITELIST) {
+        ble_error_t error = generateStackWhitelist(whitelist);
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    }
+
+    ble_gap_scan_params_t scanParams;
+    scanParams.selective   = scanningPolicyMode;    /**< If 1, ignore unknown devices (non whitelisted). */
+    scanParams.p_whitelist = &whitelist; /**< Pointer to whitelist, NULL if none is given. */
+    if (scanParamsIn != NULL) {
+        scanParams.active      = scanParamsIn->getActiveScanning();   /**< If 1, perform active scanning (scan requests). */
+        scanParams.interval    = scanParamsIn->getInterval();         /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+        scanParams.window      = scanParamsIn->getWindow();           /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+        scanParams.timeout     = scanParamsIn->getTimeout();          /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
+    } else {
+        scanParams.active      = _scanningParams.getActiveScanning(); /**< If 1, perform active scanning (scan requests). */
+        scanParams.interval    = _scanningParams.getInterval();       /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+        scanParams.window      = _scanningParams.getWindow();         /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+        scanParams.timeout     = _scanningParams.getTimeout();        /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
+    }
+
+    uint32_t rc = sd_ble_gap_connect(&addr, &scanParams, &connParams);
+    if (rc == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    }
+    switch (rc) {
+        case NRF_ERROR_INVALID_ADDR:
+            return BLE_ERROR_INVALID_PARAM;
+        case NRF_ERROR_INVALID_PARAM:
+            return BLE_ERROR_INVALID_PARAM;
+        case NRF_ERROR_INVALID_STATE:
+            return BLE_ERROR_INVALID_STATE;
+        case BLE_ERROR_GAP_INVALID_BLE_ADDR:
+            return BLE_ERROR_INVALID_PARAM;
+        case NRF_ERROR_NO_MEM:
+            return BLE_ERROR_NO_MEM;
+        case NRF_ERROR_BUSY:
+            return BLE_STACK_BUSY;
+        default:
+        case BLE_ERROR_GAP_WHITELIST_IN_USE:
+            return BLE_ERROR_UNSPECIFIED;
+    }
+}
+
+ble_error_t nRF5xGap::disconnect(Handle_t connectionHandle, DisconnectionReason_t reason)
+{
+    uint8_t code = BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION;
+    switch (reason) {
+        case REMOTE_USER_TERMINATED_CONNECTION:
+            code = BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION;
+            break;
+        case CONN_INTERVAL_UNACCEPTABLE:
+            code = BLE_HCI_CONN_INTERVAL_UNACCEPTABLE;
+            break;
+        default:
+            break;
+    }
+
+    /* Disconnect if we are connected to a central device */
+    ASSERT_INT(ERROR_NONE, sd_ble_gap_disconnect(connectionHandle, code), BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    return BLE_ERROR_NONE;
+}
+
+/*!
+    @brief  Disconnects if we are connected to a central device
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+*/
+ble_error_t nRF5xGap::disconnect(DisconnectionReason_t reason)
+{
+    return disconnect(m_connectionHandle, reason);
+}
+
+ble_error_t nRF5xGap::getPreferredConnectionParams(ConnectionParams_t *params)
+{
+    ASSERT_INT(NRF_SUCCESS,
+        sd_ble_gap_ppcp_get(reinterpret_cast<ble_gap_conn_params_t *>(params)),
+        BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t nRF5xGap::setPreferredConnectionParams(const ConnectionParams_t *params)
+{
+    ASSERT_INT(NRF_SUCCESS,
+        sd_ble_gap_ppcp_set(reinterpret_cast<const ble_gap_conn_params_t *>(params)),
+        BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t nRF5xGap::updateConnectionParams(Handle_t handle, const ConnectionParams_t *newParams)
+{
+    uint32_t rc;
+
+    rc = sd_ble_gap_conn_param_update(handle, reinterpret_cast<ble_gap_conn_params_t *>(const_cast<ConnectionParams_t*>(newParams)));
+    if (rc == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    } else {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+}
+
+/**************************************************************************/
+/*!
+    @brief  Clear nRF5xGap's state.
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::reset(void)
+{
+    /* Clear all state that is from the parent, including private members */
+    if (Gap::reset() != BLE_ERROR_NONE) {
+        return BLE_ERROR_INVALID_STATE;
+    }
+
+    /* Clear derived class members */
+    m_connectionHandle = BLE_CONN_HANDLE_INVALID;
+
+    /* Set the whitelist policy filter modes to IGNORE_WHITELIST */
+    advertisingPolicyMode = Gap::ADV_POLICY_IGNORE_WHITELIST;
+    scanningPolicyMode    = Gap::SCAN_POLICY_IGNORE_WHITELIST;
+
+    /* Clear the internal whitelist */
+    whitelistAddressesSize = 0;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Sets the 16-bit connection handle
+*/
+/**************************************************************************/
+void nRF5xGap::setConnectionHandle(uint16_t con_handle)
+{
+    m_connectionHandle = con_handle;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Gets the 16-bit connection handle
+*/
+/**************************************************************************/
+uint16_t nRF5xGap::getConnectionHandle(void)
+{
+    return m_connectionHandle;
+}
+
+/**************************************************************************/
+/*!
+    @brief      Sets the BLE device address
+
+    @returns    ble_error_t
+
+    @section EXAMPLE
+
+    @code
+
+    uint8_t device_address[6] = { 0xca, 0xfe, 0xf0, 0xf0, 0xf0, 0xf0 };
+    nrf.getGap().setAddress(Gap::BLEProtocol::AddressType::RANDOM_STATIC, device_address);
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::setAddress(AddressType_t type, const Address_t address)
+{
+    uint8_t cycle_mode;
+    ble_gap_addr_t dev_addr;
+
+    /* When using Public or Static addresses, the cycle mode must be None.
+       When using Random Private addresses, the cycle mode must be Auto.
+       In auto mode, the given address is ignored.
+    */
+    if ((type == BLEProtocol::AddressType::PUBLIC) || (type == BLEProtocol::AddressType::RANDOM_STATIC))
+    {
+        cycle_mode = BLE_GAP_ADDR_CYCLE_MODE_NONE;
+        memcpy(dev_addr.addr, address, ADDR_LEN);
+    }
+    else if ((type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE) || (type == BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE))
+    {
+        cycle_mode = BLE_GAP_ADDR_CYCLE_MODE_AUTO;
+        // address is ignored when in auto mode
+    }
+    else
+    {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    dev_addr.addr_type = type;
+    ASSERT_INT(ERROR_NONE, sd_ble_gap_address_set(cycle_mode, &dev_addr), BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t nRF5xGap::getAddress(AddressType_t *typeP, Address_t address)
+{
+    ble_gap_addr_t dev_addr;
+    if (sd_ble_gap_address_get(&dev_addr) != NRF_SUCCESS) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    if (typeP != NULL) {
+        *typeP = static_cast<AddressType_t>(dev_addr.addr_type);
+    }
+    if (address != NULL) {
+        memcpy(address, dev_addr.addr, ADDR_LEN);
+    }
+    return BLE_ERROR_NONE;
+}
+
+ble_error_t nRF5xGap::setDeviceName(const uint8_t *deviceName)
+{
+    ble_gap_conn_sec_mode_t sec_mode;
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&sec_mode); // no security is needed
+
+    if (sd_ble_gap_device_name_set(&sec_mode, deviceName, strlen((const char *)deviceName)) == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    } else {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+}
+
+ble_error_t nRF5xGap::getDeviceName(uint8_t *deviceName, unsigned *lengthP)
+{
+    if (sd_ble_gap_device_name_get(deviceName, (uint16_t *)lengthP) == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    } else {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+}
+
+ble_error_t nRF5xGap::setAppearance(GapAdvertisingData::Appearance appearance)
+{
+    if (sd_ble_gap_appearance_set(appearance) == NRF_SUCCESS) {
+        return BLE_ERROR_NONE;
+    } else {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+}
+
+ble_error_t nRF5xGap::getAppearance(GapAdvertisingData::Appearance *appearanceP)
+{
+    if ((sd_ble_gap_appearance_get(reinterpret_cast<uint16_t *>(appearanceP)) == NRF_SUCCESS)) {
+        return BLE_ERROR_NONE;
+    } else {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+}
+
+/* (Valid values are -40, -20, -16, -12, -8, -4, 0, 4) */
+ble_error_t nRF5xGap::setTxPower(int8_t txPower)
+{
+    unsigned rc;
+    if ((rc = sd_ble_gap_tx_power_set(txPower)) != NRF_SUCCESS) {
+        switch (rc) {
+            case NRF_ERROR_BUSY:
+                return BLE_STACK_BUSY;
+            case NRF_ERROR_INVALID_PARAM:
+            default:
+                return BLE_ERROR_PARAM_OUT_OF_RANGE;
+        }
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+void nRF5xGap::getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP)
+{
+#if defined(NRF51)
+    static const int8_t permittedTxValues[] = {
+        -30, -20, -16, -12, -8, -4, 0, 4
+    };
+#elif defined(NRF52)
+    static const int8_t permittedTxValues[] = {
+        -40, -20, -16, -12, -8, -4, 0, 4
+    };
+#else
+#error permitted TX power values unknown for this SOC
+#endif
+
+    *valueArrayPP = permittedTxValues;
+    *countP = sizeof(permittedTxValues) / sizeof(int8_t);
+}
+
+/**************************************************************************/
+/*!
+    @brief  Get the capacity of the internal whitelist maintained by this
+            implementation.
+
+    @returns    The capacity of the internal whitelist.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+uint8_t nRF5xGap::getMaxWhitelistSize(void) const
+{
+    return YOTTA_CFG_WHITELIST_MAX_SIZE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Get a copy of the implementation's internal whitelist.
+
+    @param[out] whitelistOut
+                A \ref Gap::Whitelist_t structure containing a copy of the
+                addresses in the implemenetation's internal whitelist.
+
+    @returns    \ref ble_errror_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::getWhitelist(Gap::Whitelist_t &whitelistOut) const
+{
+    uint8_t i;
+    for (i = 0; i < whitelistAddressesSize && i < whitelistOut.capacity; ++i) {
+        memcpy(&whitelistOut.addresses[i], &whitelistAddresses[i], sizeof(BLEProtocol::Address_t));
+    }
+    whitelistOut.size = i;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Set the whitelist that will be used in the next call to
+            startAdvertising().
+
+    @param[in]  whitelistIn
+                A reference to a \ref Gap::Whitelist_t structure
+                representing a whitelist containing all the white listed
+                BLE addresses.
+
+    @returns    \ref ble_errror_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly.
+
+                BLE_ERROR_INVALID_PARAM
+                The supplied whitelist contains a private non-resolvable
+                address
+
+                BLE_ERROR_PARAM_OUT_OF_RANGE
+                The size of the supplied whitelist exceeds the maximum
+                capacity of the implementation's internal whitelist.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::setWhitelist(const Gap::Whitelist_t &whitelistIn)
+{
+    if (whitelistIn.size > getMaxWhitelistSize()) {
+        return BLE_ERROR_PARAM_OUT_OF_RANGE;
+    }
+
+    /* Test for invalid parameters before we change the internal state */
+    for (uint8_t i = 0; i < whitelistIn.size; ++i) {
+        if (whitelistIn.addresses[i].type == BLEProtocol::AddressType::RANDOM_PRIVATE_NON_RESOLVABLE) {
+            /* This is not allowed because it is completely meaningless */
+            return BLE_ERROR_INVALID_PARAM;
+        }
+    }
+
+    whitelistAddressesSize = 0;
+    for (uint8_t i = 0; i < whitelistIn.size; ++i) {
+        memcpy(&whitelistAddresses[whitelistAddressesSize], &whitelistIn.addresses[i], sizeof(BLEProtocol::Address_t));
+        whitelistAddressesSize++;
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Set the advertising policy filter mode that will be used in
+            the next call to startAdvertising().
+
+    @returns    \ref ble_errror_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly.
+
+                BLE_ERROR_NOT_IMPLEMENTED
+                This feature is currently note implemented.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::setAdvertisingPolicyMode(Gap::AdvertisingPolicyMode_t mode)
+{
+    advertisingPolicyMode = mode;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Set the scanning policy filter mode that will be used in
+            the next call to startAdvertising().
+
+    @returns    \ref ble_errror_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly.
+
+                BLE_ERROR_NOT_IMPLEMENTED
+                This feature is currently note implemented.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::setScanningPolicyMode(Gap::ScanningPolicyMode_t mode)
+{
+    scanningPolicyMode = mode;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Set the initiator policy filter mode that will be used in
+            the next call to startAdvertising()
+
+    @returns    \ref ble_errror_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly.
+
+                BLE_ERROR_NOT_IMPLEMENTED
+                This feature is currently note implemented.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::setInitiatorPolicyMode(Gap::InitiatorPolicyMode_t mode)
+{
+    return BLE_ERROR_NOT_IMPLEMENTED;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Get the current advertising policy filter mode.
+
+    @returns    The advertising policy filter mode.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+Gap::AdvertisingPolicyMode_t nRF5xGap::getAdvertisingPolicyMode(void) const
+{
+    return advertisingPolicyMode;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Get the current scanning policy filter mode.
+
+    @returns    The scanning policy filter mode.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+Gap::ScanningPolicyMode_t nRF5xGap::getScanningPolicyMode(void) const
+{
+    return scanningPolicyMode;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Get the current initiator policy filter mode.
+
+    @returns    The initiator policy filter mode.
+
+    @note   Currently initiator filtering using the whitelist is not
+            implemented in this module.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+Gap::InitiatorPolicyMode_t nRF5xGap::getInitiatorPolicyMode(void) const
+{
+    return Gap::INIT_POLICY_IGNORE_WHITELIST;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Helper function used to populate the ble_gap_whitelist_t that
+            will be used by the SoftDevice for filtering requests.
+
+    @returns    \ref ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+
+    @retval     BLE_ERROR_INVALID_STATE
+                The internal stack was not initialized correctly.
+
+    @note  Both the SecurityManager and Gap must initialize correctly for
+           this function to succeed.
+
+    @note  This function is needed because for the BLE API the whitelist
+           is just a collection of keys, but for the stack it also includes
+           the IRK table.
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGap::generateStackWhitelist(ble_gap_whitelist_t &whitelist)
+{
+    ble_gap_whitelist_t  whitelistFromBondTable;
+    ble_gap_addr_t      *addressPtr[1];
+    ble_gap_irk_t       *irkPtr[YOTTA_CFG_IRK_TABLE_MAX_SIZE];
+
+    nRF5xSecurityManager& securityManager = (nRF5xSecurityManager&) nRF5xn::Instance(0).getSecurityManager();
+
+    if (securityManager.hasInitialized()) {
+        /* We do not care about the addresses, set the count to 0 */
+        whitelistFromBondTable.addr_count = 0;
+        /* The Nordic SDK will return a failure if we set pp_addr to NULL */
+        whitelistFromBondTable.pp_addrs   = addressPtr;
+        /* We want all the IRKs we can get because we do not know which ones match the addresses */
+        whitelistFromBondTable.irk_count  = YOTTA_CFG_IRK_TABLE_MAX_SIZE;
+        whitelistFromBondTable.pp_irks    = irkPtr;
+
+        /* Use the security manager to get the IRKs from the bond table */
+        ble_error_t error = securityManager.createWhitelistFromBondTable(whitelistFromBondTable);
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    } else  {
+        /**
+         * If there is no security manager then we cannot access the bond table,
+         * so disable IRK matching
+         */
+        whitelistFromBondTable.addr_count = 0;
+        whitelistFromBondTable.irk_count  = 0;
+    }
+
+    /**
+     * For every private resolvable address in the local whitelist check if
+     * there is an IRK for said address in the bond table and add it to the
+     * local IRK list.
+     */
+    whitelist.irk_count  = 0;
+    whitelist.addr_count = 0;
+    for (uint8_t i = 0; i < whitelistAddressesSize; ++i) {
+        if (whitelistAddresses[i].addr_type == BLEProtocol::AddressType::RANDOM_PRIVATE_RESOLVABLE) {
+            /* Test if there is a matching IRK for this private resolvable address */
+            for (uint8_t j = 0; j < whitelistFromBondTable.irk_count; ++j) {
+                if (securityManager.matchAddressAndIrk(&whitelistAddresses[i], whitelistFromBondTable.pp_irks[j])) {
+                    /* Found the corresponding IRK, add it to our local whitelist */
+                    whitelist.pp_irks[whitelist.irk_count] = whitelistFromBondTable.pp_irks[j];
+                    whitelist.irk_count++;
+                    /* Make sure we do not look at this IRK again */
+                    if (j != whitelistFromBondTable.irk_count - 1) {
+                        /**
+                         * This is not the last IRK, so replace the pointer
+                         * with the last pointer in the array
+                         */
+                        whitelistFromBondTable.pp_irks[j] =
+                            whitelistFromBondTable.pp_irks[whitelistFromBondTable.irk_count - 1];
+                    }
+                    /**
+                     * If the IRK is the last pointer in the array simply
+                     * decrement the total IRK count
+                     */
+                    whitelistFromBondTable.irk_count--;
+                    break;
+                }
+            }
+        } else {
+            /* Include the address into the whitelist */
+            whitelist.pp_addrs[whitelist.addr_count] = &whitelistAddresses[i];
+            whitelist.addr_count++;
+        }
+    }
+
+    return BLE_ERROR_NONE;
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h
new file mode 100644
index 0000000000..adb80851dd
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGap.h
@@ -0,0 +1,247 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF5x_GAP_H__
+#define __NRF5x_GAP_H__
+
+#ifdef YOTTA_CFG_MBED_OS
+    #include "mbed-drivers/mbed.h"
+#else
+    #include "mbed.h"
+#endif
+#ifndef YOTTA_CFG_WHITELIST_MAX_SIZE
+    #define YOTTA_CFG_WHITELIST_MAX_SIZE BLE_GAP_WHITELIST_ADDR_MAX_COUNT
+#elif YOTTA_CFG_WHITELIST_MAX_SIZE > BLE_GAP_WHITELIST_ADDR_MAX_COUNT
+    #undef YOTTA_CFG_WHITELIST_MAX_SIZE
+    #define YOTTA_CFG_WHITELIST_MAX_SIZE BLE_GAP_WHITELIST_ADDR_MAX_COUNT
+#endif
+#ifndef YOTTA_CFG_IRK_TABLE_MAX_SIZE
+    #define YOTTA_CFG_IRK_TABLE_MAX_SIZE BLE_GAP_WHITELIST_IRK_MAX_COUNT
+#elif YOTTA_CFG_IRK_TABLE_MAX_SIZE > BLE_GAP_WHITELIST_IRK_MAX_COUNT
+    #undef YOTTA_CFG_IRK_TABLE_MAX_SIZE
+    #define YOTTA_CFG_IRK_TABLE_MAX_SIZE BLE_GAP_WHITELIST_IRK_MAX_COUNT
+#endif
+#include "ble/blecommon.h"
+#include "nrf_ble.h"
+#include "ble/GapAdvertisingParams.h"
+#include "ble/GapAdvertisingData.h"
+#include "ble/Gap.h"
+#include "ble/GapScanningParams.h"
+
+#include "nrf_soc.h"
+
+extern "C" {
+#include "ble_radio_notification.h"
+#include "app_util_platform.h"
+}
+
+#include "btle_security.h"
+
+void radioNotificationStaticCallback(bool param);
+
+/**************************************************************************/
+/*!
+    \brief
+
+*/
+/**************************************************************************/
+class nRF5xGap : public Gap
+{
+public:
+    /* Functions that must be implemented from Gap */
+    virtual ble_error_t setAddress(AddressType_t  type,  const Address_t address);
+    virtual ble_error_t getAddress(AddressType_t *typeP, Address_t address);
+    virtual ble_error_t setAdvertisingData(const GapAdvertisingData &, const GapAdvertisingData &);
+
+    virtual uint16_t    getMinAdvertisingInterval(void) const {return GapAdvertisingParams::ADVERTISEMENT_DURATION_UNITS_TO_MS(BLE_GAP_ADV_INTERVAL_MIN);}
+    virtual uint16_t    getMinNonConnectableAdvertisingInterval(void) const {return GapAdvertisingParams::ADVERTISEMENT_DURATION_UNITS_TO_MS(BLE_GAP_ADV_NONCON_INTERVAL_MIN);}
+    virtual uint16_t    getMaxAdvertisingInterval(void) const {return GapAdvertisingParams::ADVERTISEMENT_DURATION_UNITS_TO_MS(BLE_GAP_ADV_INTERVAL_MAX);}
+
+    virtual ble_error_t startAdvertising(const GapAdvertisingParams &);
+    virtual ble_error_t stopAdvertising(void);
+    virtual ble_error_t connect(const Address_t, BLEProtocol::AddressType_t peerAddrType, const ConnectionParams_t *connectionParams, const GapScanningParams *scanParams);
+    virtual ble_error_t disconnect(Handle_t connectionHandle, DisconnectionReason_t reason);
+    virtual ble_error_t disconnect(DisconnectionReason_t reason);
+
+    virtual ble_error_t setDeviceName(const uint8_t *deviceName);
+    virtual ble_error_t getDeviceName(uint8_t *deviceName, unsigned *lengthP);
+    virtual ble_error_t setAppearance(GapAdvertisingData::Appearance appearance);
+    virtual ble_error_t getAppearance(GapAdvertisingData::Appearance *appearanceP);
+
+    virtual ble_error_t setTxPower(int8_t txPower);
+    virtual void        getPermittedTxPowerValues(const int8_t **valueArrayPP, size_t *countP);
+
+    void     setConnectionHandle(uint16_t con_handle);
+    uint16_t getConnectionHandle(void);
+
+    virtual ble_error_t getPreferredConnectionParams(ConnectionParams_t *params);
+    virtual ble_error_t setPreferredConnectionParams(const ConnectionParams_t *params);
+    virtual ble_error_t updateConnectionParams(Handle_t handle, const ConnectionParams_t *params);
+
+    virtual ble_error_t reset(void);
+
+    /*
+     * The following functions are part of the whitelisting experimental API.
+     * Therefore, this functionality can change in the near future.
+     */
+    virtual uint8_t getMaxWhitelistSize(void) const;
+    virtual ble_error_t getWhitelist(Gap::Whitelist_t &whitelistOut) const;
+    virtual ble_error_t setWhitelist(const Gap::Whitelist_t &whitelistIn);
+
+    virtual ble_error_t setAdvertisingPolicyMode(AdvertisingPolicyMode_t mode);
+    virtual ble_error_t setScanningPolicyMode(ScanningPolicyMode_t mode);
+    virtual ble_error_t setInitiatorPolicyMode(InitiatorPolicyMode_t mode);
+    virtual Gap::AdvertisingPolicyMode_t getAdvertisingPolicyMode(void) const;
+    virtual Gap::ScanningPolicyMode_t getScanningPolicyMode(void) const;
+    virtual Gap::InitiatorPolicyMode_t getInitiatorPolicyMode(void) const;
+
+    virtual ble_error_t initRadioNotification(void) {
+        if (ble_radio_notification_init(APP_IRQ_PRIORITY_HIGH /*MID*/, NRF_RADIO_NOTIFICATION_DISTANCE_800US, radioNotificationStaticCallback) == NRF_SUCCESS) {
+            return BLE_ERROR_NONE;
+        }
+
+        return BLE_ERROR_UNSPECIFIED;
+    }
+
+/* Observer role is not supported by S110, return BLE_ERROR_NOT_IMPLEMENTED */
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+    virtual ble_error_t startRadioScan(const GapScanningParams &scanningParams);
+    virtual ble_error_t stopScan(void);
+#endif
+
+private:
+    /*
+     * Whitelisting API related structures and helper functions.
+     */
+
+    /* Policy modes set by the user. By default these are set to ignore the whitelist */
+    Gap::AdvertisingPolicyMode_t advertisingPolicyMode;
+    Gap::ScanningPolicyMode_t    scanningPolicyMode;
+
+    /* Internal representation of a whitelist */
+    uint8_t         whitelistAddressesSize;
+    ble_gap_addr_t  whitelistAddresses[YOTTA_CFG_WHITELIST_MAX_SIZE];
+
+    /*
+     * An internal function used to populate the ble_gap_whitelist_t that will be used by
+     * the SoftDevice for filtering requests. This function is needed because for the BLE
+     * API the whitelist is just a collection of keys, but for the stack it also includes
+     * the IRK table.
+     */
+    ble_error_t generateStackWhitelist(ble_gap_whitelist_t &whitelist);
+
+private:
+    bool    radioNotificationCallbackParam; /* parameter to be passed into the Timeout-generated radio notification callback. */
+    Timeout radioNotificationTimeout;
+
+    /*
+     * A helper function to post radio notification callbacks with low interrupt priority.
+     */
+    void postRadioNotificationCallback(void) {
+#ifdef YOTTA_CFG_MBED_OS
+        /*
+         * In mbed OS, all user-facing BLE events (interrupts) are posted to the
+         * MINAR scheduler to be executed as callbacks in thread mode. MINAR guards
+         * its critical sections from interrupts by acquiring CriticalSectionLock,
+         * which results in a call to sd_nvic_critical_region_enter(). Thus, it is
+         * safe to invoke MINAR APIs from interrupt context as long as those
+         * interrupts are blocked by sd_nvic_critical_region_enter().
+         *
+         * Radio notifications are a special case for the above. The Radio
+         * Notification IRQ is handled at a very high priority--higher than the
+         * level blocked by sd_nvic_critical_region_enter(). Thus Radio Notification
+         * events can preempt MINAR's critical sections. Using MINAR APIs (such as
+         * posting an event) directly in processRadioNotification() may result in a
+         * race condition ending in a hard-fault.
+         *
+         * The solution is to *not* call MINAR APIs directly from the Radio
+         * Notification handling; i.e. to do the bulk of RadioNotification
+         * processing at a reduced priority which respects MINAR's critical
+         * sections. Unfortunately, on a cortex-M0, there is no clean way to demote
+         * priority for the currently executing interrupt--we wouldn't want to
+         * demote the radio notification handling anyway because it is sensitive to
+         * timing, and the system expects to finish this handling very quickly. The
+         * workaround is to employ a Timeout to trigger
+         * postRadioNotificationCallback() after a very short delay (~0 us) and post
+         * the MINAR callback that context.
+         *
+         * !!!WARNING!!! Radio notifications are very time critical events. The
+         * current solution is expected to work under the assumption that
+         * postRadioNotificationCalback() will be executed BEFORE the next radio
+         * notification event is generated.
+         */
+        minar::Scheduler::postCallback(
+            mbed::util::FunctionPointer1<void, bool>(&radioNotificationCallback, &FunctionPointerWithContext<bool>::call).bind(radioNotificationCallbackParam)
+        );
+#else
+        /*
+         * In mbed classic, all user-facing BLE events execute callbacks in interrupt
+         * mode. Radio Notifications are a special case because its IRQ is handled at
+         * a very high priority. Thus Radio Notification events can preempt other
+         * operations that require interaction with the SoftDevice such as advertising
+         * payload updates and changing the Gap state. Therefore, executing a Radio
+         * Notification callback directly from processRadioNotification() may result
+         * in a race condition ending in a hard-fault.
+         *
+         * The solution is to *not* execute the Radio Notification callback directly
+         * from the Radio Notification handling; i.e. to do the bulk of the
+         * Radio Notification processing at a reduced priority. Unfortunately, on a
+         * cortex-M0, there is no clean way to demote priority for the currently
+         * executing interrupt--we wouldn't want to demote the radio notification
+         * handling anyway because it is sensitive to timing, and the system expects
+         * to finish this handling very quickly. The workaround is to employ a Timeout
+         * to trigger postRadioNotificationCallback() after a very short delay (~0 us)
+         * and execute the callback in that context.
+         *
+         * !!!WARNING!!! Radio notifications are very time critical events. The
+         * current solution is expected to work under the assumption that
+         * postRadioNotificationCalback() will be executed BEFORE the next radio
+         * notification event is generated.
+         */
+        radioNotificationCallback.call(radioNotificationCallbackParam);
+#endif /* #ifdef YOTTA_CFG_MBED_OS */
+    }
+
+    /**
+     * A helper function to process radio-notification events; to be called internally.
+     * @param param [description]
+     */
+    void processRadioNotificationEvent(bool param) {
+        radioNotificationCallbackParam = param;
+        radioNotificationTimeout.attach_us(this, &nRF5xGap::postRadioNotificationCallback, 0);
+    }
+    friend void radioNotificationStaticCallback(bool param); /* allow invocations of processRadioNotificationEvent() */
+
+private:
+    uint16_t m_connectionHandle;
+
+    /*
+     * Allow instantiation from nRF5xn when required.
+     */
+    friend class nRF5xn;
+
+    nRF5xGap() :
+        advertisingPolicyMode(Gap::ADV_POLICY_IGNORE_WHITELIST),
+        scanningPolicyMode(Gap::SCAN_POLICY_IGNORE_WHITELIST),
+        whitelistAddressesSize(0) {
+        m_connectionHandle = BLE_CONN_HANDLE_INVALID;
+    }
+
+    nRF5xGap(nRF5xGap const &);
+    void operator=(nRF5xGap const &);
+};
+
+#endif // ifndef __NRF5x_GAP_H__
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp
new file mode 100644
index 0000000000..e79e47afa2
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.cpp
@@ -0,0 +1,50 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nRF5xGattClient.h"
+
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+ble_error_t
+nRF5xGattClient::launchServiceDiscovery(Gap::Handle_t                               connectionHandle,
+                                        ServiceDiscovery::ServiceCallback_t         sc,
+                                        ServiceDiscovery::CharacteristicCallback_t  cc,
+                                        const UUID                                 &matchingServiceUUIDIn,
+                                        const UUID                                 &matchingCharacteristicUUIDIn)
+{
+    return _discovery.launch(connectionHandle, sc, cc, matchingServiceUUIDIn, matchingCharacteristicUUIDIn);
+}
+
+ble_error_t nRF5xGattClient::discoverCharacteristicDescriptors(
+    const DiscoveredCharacteristic& characteristic,
+    const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback,
+    const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback)
+{
+    return _characteristicDescriptorDiscoverer.launch(
+        characteristic, 
+        discoveryCallback, 
+        terminationCallback
+    );
+}
+
+bool nRF5xGattClient::isCharacteristicDescriptorsDiscoveryActive(const DiscoveredCharacteristic& characteristic) const {
+    return _characteristicDescriptorDiscoverer.isActive(characteristic);   
+}
+
+void nRF5xGattClient::terminateCharacteristicDescriptorsDiscovery(const DiscoveredCharacteristic& characteristic) { 
+    return _characteristicDescriptorDiscoverer.requestTerminate(characteristic);
+}
+
+#endif
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h
new file mode 100644
index 0000000000..5670d15b9d
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattClient.h
@@ -0,0 +1,218 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF51822_GATT_CLIENT_H__
+#define __NRF51822_GATT_CLIENT_H__
+
+#include "ble/GattClient.h"
+#include "nRF5xServiceDiscovery.h"
+#include "nRF5xCharacteristicDescriptorDiscoverer.h"
+
+class nRF5xGattClient : public GattClient
+{
+public:
+    /**
+     * When using S110, all Gatt client features will return
+     * BLE_ERROR_NOT_IMPLEMENTED
+     */
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+
+    /**
+     * Launch service discovery. Once launched, service discovery will remain
+     * active with callbacks being issued back into the application for matching
+     * services/characteristics. isActive() can be used to determine status; and
+     * a termination callback (if setup) will be invoked at the end. Service
+     * discovery can be terminated prematurely if needed using terminate().
+     *
+     * @param  connectionHandle
+     *           Handle for the connection with the peer.
+     * @param  sc
+     *           This is the application callback for matching service. Taken as
+     *           NULL by default. Note: service discovery may still be active
+     *           when this callback is issued; calling asynchronous BLE-stack
+     *           APIs from within this application callback might cause the
+     *           stack to abort service discovery. If this becomes an issue, it
+     *           may be better to make local copy of the discoveredService and
+     *           wait for service discovery to terminate before operating on the
+     *           service.
+     * @param  cc
+     *           This is the application callback for matching characteristic.
+     *           Taken as NULL by default. Note: service discovery may still be
+     *           active when this callback is issued; calling asynchronous
+     *           BLE-stack APIs from within this application callback might cause
+     *           the stack to abort service discovery. If this becomes an issue,
+     *           it may be better to make local copy of the discoveredCharacteristic
+     *           and wait for service discovery to terminate before operating on the
+     *           characteristic.
+     * @param  matchingServiceUUID
+     *           UUID based filter for specifying a service in which the application is
+     *           interested. By default it is set as the wildcard UUID_UNKNOWN,
+     *           in which case it matches all services. If characteristic-UUID
+     *           filter (below) is set to the wildcard value, then a service
+     *           callback will be invoked for the matching service (or for every
+     *           service if the service filter is a wildcard).
+     * @param  matchingCharacteristicUUIDIn
+     *           UUID based filter for specifying characteristic in which the application
+     *           is interested. By default it is set as the wildcard UUID_UKNOWN
+     *           to match against any characteristic. If both service-UUID
+     *           filter and characteristic-UUID filter are used with non- wildcard
+     *           values, then only a single characteristic callback is
+     *           invoked for the matching characteristic.
+     *
+     * @Note     Using wildcard values for both service-UUID and characteristic-
+     *           UUID will result in complete service discovery--callbacks being
+     *           called for every service and characteristic.
+     *
+     * @return
+     *           BLE_ERROR_NONE if service discovery is launched successfully; else an appropriate error.
+     */
+    virtual ble_error_t launchServiceDiscovery(Gap::Handle_t                               connectionHandle,
+                                               ServiceDiscovery::ServiceCallback_t         sc = NULL,
+                                               ServiceDiscovery::CharacteristicCallback_t  cc = NULL,
+                                               const UUID                                 &matchingServiceUUID = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN),
+                                               const UUID                                 &matchingCharacteristicUUIDIn = UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN));
+
+    virtual void onServiceDiscoveryTermination(ServiceDiscovery::TerminationCallback_t callback) {
+        _discovery.onTermination(callback);
+    }
+
+    /**
+     * Is service-discovery currently active?
+     */
+    virtual bool isServiceDiscoveryActive(void) const {
+        return _discovery.isActive();
+    }
+
+    /**
+     * Terminate an ongoing service-discovery. This should result in an
+     * invocation of the TerminationCallback if service-discovery is active.
+     */
+    virtual void terminateServiceDiscovery(void) {
+        _discovery.terminate();
+    }
+
+    /**
+     * @brief Implementation of GattClient::discoverCharacteristicDescriptors
+     * @see GattClient::discoverCharacteristicDescriptors
+     */
+    virtual ble_error_t discoverCharacteristicDescriptors(
+        const DiscoveredCharacteristic& characteristic,
+        const CharacteristicDescriptorDiscovery::DiscoveryCallback_t& discoveryCallback,
+        const CharacteristicDescriptorDiscovery::TerminationCallback_t& terminationCallback
+    );
+
+    /**
+     * @brief Implementation of GattClient::isCharacteristicDiscoveryActive
+     * @see GattClient::isCharacteristicDiscoveryActive
+     */
+    virtual bool isCharacteristicDescriptorsDiscoveryActive(const DiscoveredCharacteristic& characteristic) const;
+
+    /**
+     * @brief Implementation of GattClient::terminateCharacteristicDiscovery
+     * @see GattClient::terminateCharacteristicDiscovery
+     */
+    virtual void terminateCharacteristicDescriptorsDiscovery(const DiscoveredCharacteristic& characteristic);
+
+    virtual ble_error_t read(Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, uint16_t offset) const {
+        uint32_t rc = sd_ble_gattc_read(connHandle, attributeHandle, offset);
+        if (rc == NRF_SUCCESS) {
+            return BLE_ERROR_NONE;
+        }
+        switch (rc) {
+            case NRF_ERROR_BUSY:
+                return BLE_STACK_BUSY;
+            case BLE_ERROR_INVALID_CONN_HANDLE:
+            case NRF_ERROR_INVALID_STATE:
+            case NRF_ERROR_INVALID_ADDR:
+            default:
+                return BLE_ERROR_INVALID_STATE;
+        }
+    }
+
+    virtual ble_error_t write(GattClient::WriteOp_t cmd, Gap::Handle_t connHandle, GattAttribute::Handle_t attributeHandle, size_t length, const uint8_t *value) const {
+        ble_gattc_write_params_t writeParams;
+        writeParams.write_op = cmd;
+        writeParams.flags    = 0; /* this is inconsequential */
+        writeParams.handle   = attributeHandle;
+        writeParams.offset   = 0;
+        writeParams.len      = length;
+        writeParams.p_value  = const_cast<uint8_t *>(value);
+
+        uint32_t rc = sd_ble_gattc_write(connHandle, &writeParams);
+        if (rc == NRF_SUCCESS) {
+            return BLE_ERROR_NONE;
+        }
+        switch (rc) {
+            case NRF_ERROR_BUSY:
+                return BLE_STACK_BUSY;
+            case BLE_ERROR_NO_TX_PACKETS:
+                return BLE_ERROR_NO_MEM;
+            case BLE_ERROR_INVALID_CONN_HANDLE:
+            case NRF_ERROR_INVALID_STATE:
+            case NRF_ERROR_INVALID_ADDR:
+            default:
+                return BLE_ERROR_INVALID_STATE;
+        }
+    }
+
+    /**
+     * @brief  Clear nRF5xGattClient's state.
+     *
+     * @return
+     *           BLE_ERROR_NONE if successful.
+     */
+    virtual ble_error_t reset(void) {
+        /* Clear all state that is from the parent, including private members */
+        if (GattClient::reset() != BLE_ERROR_NONE) {
+            return BLE_ERROR_INVALID_STATE;
+        }
+
+        /* Clear derived class members */
+        _discovery.reset();
+
+        return BLE_ERROR_NONE;
+    }
+
+public:
+    /*
+     * Allow instantiation from nRF5xn when required.
+     */
+    friend class nRF5xn;
+
+    nRF5xGattClient() : _discovery(this) {
+        /* empty */
+    }
+
+    nRF5xServiceDiscovery& discovery() {
+        return _discovery;
+    }
+
+    nRF5xCharacteristicDescriptorDiscoverer& characteristicDescriptorDiscoverer() {
+        return _characteristicDescriptorDiscoverer;
+    }
+
+private:
+    nRF5xGattClient(const nRF5xGattClient &);
+    const nRF5xGattClient& operator=(const nRF5xGattClient &);
+
+private:
+    nRF5xServiceDiscovery _discovery;
+    nRF5xCharacteristicDescriptorDiscoverer _characteristicDescriptorDiscoverer;
+
+#endif // if !S110
+};
+
+#endif // ifndef __NRF51822_GATT_CLIENT_H__
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp
new file mode 100644
index 0000000000..4f4c562920
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.cpp
@@ -0,0 +1,543 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nRF5xGattServer.h"
+#ifdef YOTTA_CFG_MBED_OS
+    #include "mbed-drivers/mbed.h"
+#else
+    #include "mbed.h"
+#endif
+
+#include "common/common.h"
+#include "btle/custom/custom_helper.h"
+
+#include "nRF5xn.h"
+
+/**************************************************************************/
+/*!
+    @brief  Adds a new service to the GATT table on the peripheral
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+
+    @section EXAMPLE
+
+    @code
+
+    @endcode
+*/
+/**************************************************************************/
+ble_error_t nRF5xGattServer::addService(GattService &service)
+{
+    /* ToDo: Make sure this service UUID doesn't already exist (?) */
+    /* ToDo: Basic validation */
+
+    /* Add the service to the nRF51 */
+    ble_uuid_t nordicUUID;
+    nordicUUID = custom_convert_to_nordic_uuid(service.getUUID());
+
+    uint16_t serviceHandle;
+    ASSERT( ERROR_NONE ==
+            sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY,
+                                     &nordicUUID,
+                                     &serviceHandle),
+            BLE_ERROR_PARAM_OUT_OF_RANGE );
+    service.setHandle(serviceHandle);
+
+    /* Add characteristics to the service */
+    for (uint8_t i = 0; i < service.getCharacteristicCount(); i++) {
+        if (characteristicCount >= BLE_TOTAL_CHARACTERISTICS) {
+            return BLE_ERROR_NO_MEM;
+        }
+        GattCharacteristic *p_char = service.getCharacteristic(i);
+
+        /* Skip any incompletely defined, read-only characteristics. */
+        if ((p_char->getValueAttribute().getValuePtr() == NULL) &&
+            (p_char->getValueAttribute().getLength() == 0) &&
+            (p_char->getProperties() == GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_READ)) {
+            continue;
+        }
+
+        nordicUUID = custom_convert_to_nordic_uuid(p_char->getValueAttribute().getUUID());
+
+        /* The user-description descriptor is a special case which needs to be
+         * handled at the time of adding the characteristic. The following block
+         * is meant to discover its presence. */
+        const uint8_t *userDescriptionDescriptorValuePtr = NULL;
+        uint16_t userDescriptionDescriptorValueLen = 0;
+        for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) {
+            GattAttribute *p_desc = p_char->getDescriptor(j);
+            if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) {
+                userDescriptionDescriptorValuePtr = p_desc->getValuePtr();
+                userDescriptionDescriptorValueLen = p_desc->getLength();
+            }
+        }
+
+        ASSERT ( ERROR_NONE ==
+                 custom_add_in_characteristic(BLE_GATT_HANDLE_INVALID,
+                                              &nordicUUID,
+                                              p_char->getProperties(),
+                                              p_char->getRequiredSecurity(),
+                                              p_char->getValueAttribute().getValuePtr(),
+                                              p_char->getValueAttribute().getLength(),
+                                              p_char->getValueAttribute().getMaxLength(),
+                                              p_char->getValueAttribute().hasVariableLength(),
+                                              userDescriptionDescriptorValuePtr,
+                                              userDescriptionDescriptorValueLen,
+                                              p_char->isReadAuthorizationEnabled(),
+                                              p_char->isWriteAuthorizationEnabled(),
+                                              &nrfCharacteristicHandles[characteristicCount]),
+                 BLE_ERROR_PARAM_OUT_OF_RANGE );
+
+        /* Update the characteristic handle */
+        p_characteristics[characteristicCount] = p_char;
+        p_char->getValueAttribute().setHandle(nrfCharacteristicHandles[characteristicCount].value_handle);
+        characteristicCount++;
+
+        /* Add optional descriptors if any */
+        for (uint8_t j = 0; j < p_char->getDescriptorCount(); j++) {
+            if (descriptorCount >= BLE_TOTAL_DESCRIPTORS) {
+                return BLE_ERROR_NO_MEM;
+            }
+
+            GattAttribute *p_desc = p_char->getDescriptor(j);
+            /* skip the user-description-descriptor here; this has already been handled when adding the characteristic (above). */
+            if (p_desc->getUUID() == BLE_UUID_DESCRIPTOR_CHAR_USER_DESC) {
+                continue;
+            }
+
+            nordicUUID = custom_convert_to_nordic_uuid(p_desc->getUUID());
+
+            ASSERT(ERROR_NONE ==
+                   custom_add_in_descriptor(BLE_GATT_HANDLE_INVALID,
+                                            &nordicUUID,
+                                            p_desc->getValuePtr(),
+                                            p_desc->getLength(),
+                                            p_desc->getMaxLength(),
+                                            p_desc->hasVariableLength(),
+                                            &nrfDescriptorHandles[descriptorCount]),
+                BLE_ERROR_PARAM_OUT_OF_RANGE);
+
+            p_descriptors[descriptorCount] = p_desc;
+            p_desc->setHandle(nrfDescriptorHandles[descriptorCount]);
+            descriptorCount++;
+        }
+    }
+
+    serviceCount++;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Reads the value of a characteristic, based on the service
+            and characteristic index fields
+
+    @param[in]  attributeHandle
+                The handle of the GattCharacteristic to read from
+    @param[in]  buffer
+                Buffer to hold the the characteristic's value
+                (raw byte array in LSB format)
+    @param[in/out] len
+                input:  Length in bytes to be read.
+                output: Total length of attribute value upon successful return.
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+*/
+/**************************************************************************/
+ble_error_t nRF5xGattServer::read(GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP)
+{
+    return read(BLE_CONN_HANDLE_INVALID, attributeHandle, buffer, lengthP);
+}
+
+ble_error_t nRF5xGattServer::read(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP)
+{
+    ble_gatts_value_t value = {
+        .len     = *lengthP,
+        .offset  = 0,
+        .p_value = buffer,
+    };
+
+    ASSERT( ERROR_NONE ==
+            sd_ble_gatts_value_get(connectionHandle, attributeHandle, &value),
+            BLE_ERROR_PARAM_OUT_OF_RANGE);
+    *lengthP = value.len;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Updates the value of a characteristic, based on the service
+            and characteristic index fields
+
+    @param[in]  charHandle
+                The handle of the GattCharacteristic to write to
+    @param[in]  buffer
+                Data to use when updating the characteristic's value
+                (raw byte array in LSB format)
+    @param[in]  len
+                The number of bytes in buffer
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+*/
+/**************************************************************************/
+ble_error_t nRF5xGattServer::write(GattAttribute::Handle_t attributeHandle, const uint8_t buffer[], uint16_t len, bool localOnly)
+{
+    return write(BLE_CONN_HANDLE_INVALID, attributeHandle, buffer, len, localOnly);
+}
+
+ble_error_t nRF5xGattServer::write(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, const uint8_t buffer[], uint16_t len, bool localOnly)
+{
+    ble_error_t returnValue = BLE_ERROR_NONE;
+
+    ble_gatts_value_t value = {
+        .len     = len,
+        .offset  = 0,
+        .p_value = const_cast<uint8_t *>(buffer),
+    };
+
+    if (localOnly) {
+        /* Only update locally regardless of notify/indicate */
+        ASSERT_INT( ERROR_NONE,
+                    sd_ble_gatts_value_set(connectionHandle, attributeHandle, &value),
+                    BLE_ERROR_PARAM_OUT_OF_RANGE );
+        return BLE_ERROR_NONE;
+    }
+
+    int characteristicIndex = resolveValueHandleToCharIndex(attributeHandle);
+    if ((characteristicIndex != -1) &&
+        (p_characteristics[characteristicIndex]->getProperties() & (GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE | GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY))) {
+        /* HVX update for the characteristic value */
+        ble_gatts_hvx_params_t hvx_params;
+
+        hvx_params.handle = attributeHandle;
+        hvx_params.type   =
+            (p_characteristics[characteristicIndex]->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) ? BLE_GATT_HVX_NOTIFICATION : BLE_GATT_HVX_INDICATION;
+        hvx_params.offset = 0;
+        hvx_params.p_data = const_cast<uint8_t *>(buffer);
+        hvx_params.p_len  = &len;
+
+        if (connectionHandle == BLE_CONN_HANDLE_INVALID) { /* use the default connection handle if the caller hasn't specified a valid connectionHandle. */
+            nRF5xGap &gap = (nRF5xGap &) nRF5xn::Instance(BLE::DEFAULT_INSTANCE).getGap();
+            connectionHandle = gap.getConnectionHandle();
+        }
+        error_t error = (error_t) sd_ble_gatts_hvx(connectionHandle, &hvx_params);
+        if (error != ERROR_NONE) {
+            switch (error) {
+                case ERROR_BLE_NO_TX_BUFFERS: /*  Notifications consume application buffers. The return value can be used for resending notifications. */
+                case ERROR_BUSY:
+                    returnValue = BLE_STACK_BUSY;
+                    break;
+
+                case ERROR_INVALID_STATE:
+                case ERROR_BLEGATTS_SYS_ATTR_MISSING:
+                    returnValue = BLE_ERROR_INVALID_STATE;
+                    break;
+
+                default :
+                    ASSERT_INT( ERROR_NONE,
+                                sd_ble_gatts_value_set(connectionHandle, attributeHandle, &value),
+                                BLE_ERROR_PARAM_OUT_OF_RANGE );
+
+                    /* Notifications consume application buffers. The return value can
+                     * be used for resending notifications. */
+                    returnValue = BLE_STACK_BUSY;
+                    break;
+            }
+        }
+    } else {
+        uint32_t err = sd_ble_gatts_value_set(connectionHandle, attributeHandle, &value);
+        switch(err) {
+            case NRF_SUCCESS:
+                returnValue = BLE_ERROR_NONE;
+                break;
+            case NRF_ERROR_INVALID_ADDR:
+            case NRF_ERROR_INVALID_PARAM:
+                returnValue = BLE_ERROR_INVALID_PARAM;
+                break;
+            case NRF_ERROR_NOT_FOUND:
+            case NRF_ERROR_DATA_SIZE:
+            case BLE_ERROR_INVALID_CONN_HANDLE:
+            case BLE_ERROR_GATTS_INVALID_ATTR_TYPE:
+                returnValue = BLE_ERROR_PARAM_OUT_OF_RANGE;
+                break;
+            case NRF_ERROR_FORBIDDEN:
+                returnValue = BLE_ERROR_OPERATION_NOT_PERMITTED;
+                break;
+            default:
+                returnValue = BLE_ERROR_UNSPECIFIED;
+                break;
+        }
+    }
+
+    return returnValue;
+}
+
+ble_error_t nRF5xGattServer::areUpdatesEnabled(const GattCharacteristic &characteristic, bool *enabledP)
+{
+    /* Forward the call with the default connection handle. */
+    nRF5xGap &gap = (nRF5xGap &) nRF5xn::Instance(BLE::DEFAULT_INSTANCE).getGap();
+    return areUpdatesEnabled(gap.getConnectionHandle(), characteristic, enabledP);
+}
+
+ble_error_t nRF5xGattServer::areUpdatesEnabled(Gap::Handle_t connectionHandle, const GattCharacteristic &characteristic, bool *enabledP)
+{
+    int characteristicIndex = resolveValueHandleToCharIndex(characteristic.getValueHandle());
+    if (characteristicIndex == -1) {
+        return BLE_ERROR_INVALID_PARAM;
+    }
+
+    /* Read the cccd value from the GATT server. */
+    GattAttribute::Handle_t cccdHandle = nrfCharacteristicHandles[characteristicIndex].cccd_handle;
+    uint16_t cccdValue;
+    uint16_t length = sizeof(cccdValue);
+    ble_error_t rc = read(connectionHandle, cccdHandle, reinterpret_cast<uint8_t *>(&cccdValue), &length);
+    if (rc != BLE_ERROR_NONE) {
+        return rc;
+    }
+    if (length != sizeof(cccdValue)) {
+        return BLE_ERROR_INVALID_STATE;
+    }
+
+    /* Check for NOTFICATION or INDICATION in CCCD. */
+    if ((cccdValue & BLE_GATT_HVX_NOTIFICATION) || (cccdValue & BLE_GATT_HVX_INDICATION)) {
+        *enabledP = true;
+    }
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Clear nRF5xGattServer's state.
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+*/
+/**************************************************************************/
+ble_error_t nRF5xGattServer::reset(void)
+{
+    /* Clear all state that is from the parent, including private members */
+    if (GattServer::reset() != BLE_ERROR_NONE) {
+        return BLE_ERROR_INVALID_STATE;
+    }
+
+    /* Clear derived class members */
+    memset(p_characteristics,        0, sizeof(p_characteristics));
+    memset(p_descriptors,            0, sizeof(p_descriptors));
+    memset(nrfCharacteristicHandles, 0, sizeof(ble_gatts_char_handles_t));
+    memset(nrfDescriptorHandles,     0, sizeof(nrfDescriptorHandles));
+    descriptorCount = 0;
+
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Callback handler for events getting pushed up from the SD
+*/
+/**************************************************************************/
+void nRF5xGattServer::hwCallback(ble_evt_t *p_ble_evt)
+{
+    GattAttribute::Handle_t        handle_value;
+    GattServerEvents::gattEvent_t  eventType;
+    const ble_gatts_evt_t         *gattsEventP = &p_ble_evt->evt.gatts_evt;
+
+    switch (p_ble_evt->header.evt_id) {
+        case BLE_GATTS_EVT_WRITE: {
+                /* There are 2 use case here: Values being updated & CCCD (indicate/notify) enabled */
+
+                /* 1.) Handle CCCD changes */
+                handle_value = gattsEventP->params.write.handle;
+                int characteristicIndex = resolveCCCDHandleToCharIndex(handle_value);
+                if ((characteristicIndex != -1) &&
+                    (p_characteristics[characteristicIndex]->getProperties() &
+                        (GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE | GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY))) {
+
+                    uint16_t cccd_value = (gattsEventP->params.write.data[1] << 8) | gattsEventP->params.write.data[0]; /* Little Endian but M0 may be mis-aligned */
+
+                    if (((p_characteristics[characteristicIndex]->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_INDICATE) && (cccd_value & BLE_GATT_HVX_INDICATION)) ||
+                        ((p_characteristics[characteristicIndex]->getProperties() & GattCharacteristic::BLE_GATT_CHAR_PROPERTIES_NOTIFY) && (cccd_value & BLE_GATT_HVX_NOTIFICATION))) {
+                        eventType = GattServerEvents::GATT_EVENT_UPDATES_ENABLED;
+                    } else {
+                        eventType = GattServerEvents::GATT_EVENT_UPDATES_DISABLED;
+                    }
+
+                    handleEvent(eventType, p_characteristics[characteristicIndex]->getValueHandle());
+                    return;
+                }
+
+                /* 2.) Changes to the characteristic value will be handled with other events below */
+                eventType = GattServerEvents::GATT_EVENT_DATA_WRITTEN;
+            }
+            break;
+
+        case BLE_GATTS_EVT_HVC:
+            /* Indication confirmation received */
+            eventType    = GattServerEvents::GATT_EVENT_CONFIRMATION_RECEIVED;
+            handle_value = gattsEventP->params.hvc.handle;
+            break;
+
+        case BLE_EVT_TX_COMPLETE: {
+            handleDataSentEvent(p_ble_evt->evt.common_evt.params.tx_complete.count);
+            return;
+        }
+
+        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
+            sd_ble_gatts_sys_attr_set(gattsEventP->conn_handle, NULL, 0, 0);
+            return;
+
+        case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST:
+            switch (gattsEventP->params.authorize_request.type) {
+                case BLE_GATTS_AUTHORIZE_TYPE_READ:
+                    eventType    = GattServerEvents::GATT_EVENT_READ_AUTHORIZATION_REQ;
+                    handle_value = gattsEventP->params.authorize_request.request.read.handle;
+                    break;
+                case BLE_GATTS_AUTHORIZE_TYPE_WRITE:
+                    eventType    = GattServerEvents::GATT_EVENT_WRITE_AUTHORIZATION_REQ;
+                    handle_value = gattsEventP->params.authorize_request.request.write.handle;
+                    break;
+                default:
+                    return;
+            }
+            break;
+
+        default:
+            return;
+    }
+
+    int characteristicIndex = resolveValueHandleToCharIndex(handle_value);
+    if (characteristicIndex == -1) {
+        return;
+    }
+
+    /* Find index (charHandle) in the pool */
+    switch (eventType) {
+        case GattServerEvents::GATT_EVENT_DATA_WRITTEN: {
+            GattWriteCallbackParams cbParams = {
+                .connHandle = gattsEventP->conn_handle,
+                .handle     = handle_value,
+                .writeOp    = static_cast<GattWriteCallbackParams::WriteOp_t>(gattsEventP->params.write.op),
+                .offset     = gattsEventP->params.write.offset,
+                .len        = gattsEventP->params.write.len,
+                .data       = gattsEventP->params.write.data
+            };
+            handleDataWrittenEvent(&cbParams);
+            break;
+        }
+        case GattServerEvents::GATT_EVENT_WRITE_AUTHORIZATION_REQ: {
+            GattWriteAuthCallbackParams cbParams = {
+                .connHandle = gattsEventP->conn_handle,
+                .handle     = handle_value,
+                .offset     = gattsEventP->params.authorize_request.request.write.offset,
+                .len        = gattsEventP->params.authorize_request.request.write.len,
+                .data       = gattsEventP->params.authorize_request.request.write.data,
+                .authorizationReply = AUTH_CALLBACK_REPLY_SUCCESS /* the callback handler must leave this member
+                                                                   * set to AUTH_CALLBACK_REPLY_SUCCESS if the client
+                                                                   * request is to proceed. */
+            };
+            
+            ble_gatts_rw_authorize_reply_params_t reply = {
+                .type = BLE_GATTS_AUTHORIZE_TYPE_WRITE,
+                .params = {
+                    .write = {
+                        .gatt_status = p_characteristics[characteristicIndex]->authorizeWrite(&cbParams),
+                        .update = 1,
+                        .offset = cbParams.offset,
+                        .len = cbParams.len,
+                        .p_data = cbParams.data
+                    }
+                }
+            };
+            
+            if (reply.params.write.gatt_status != BLE_GATT_STATUS_SUCCESS)
+            {
+                reply.params.write.update = 0;
+            }
+            
+            sd_ble_gatts_rw_authorize_reply(gattsEventP->conn_handle, &reply);
+
+            /*
+             * If write-authorization is enabled for a characteristic,
+             * AUTHORIZATION_REQ event (if replied with true) is *not*
+             * followed by another DATA_WRITTEN event; so we still need
+             * to invoke handleDataWritten(), much the same as we would
+             * have done if write-authorization had not been enabled.
+             */
+            if (reply.params.write.gatt_status == BLE_GATT_STATUS_SUCCESS) {
+                GattWriteCallbackParams cbParams = {
+                    .connHandle = gattsEventP->conn_handle,
+                    .handle     = handle_value,
+                    .writeOp    = static_cast<GattWriteCallbackParams::WriteOp_t>(gattsEventP->params.authorize_request.request.write.op),
+                    .offset     = gattsEventP->params.authorize_request.request.write.offset,
+                    .len        = gattsEventP->params.authorize_request.request.write.len,
+                    .data       = gattsEventP->params.authorize_request.request.write.data,
+                };
+                handleDataWrittenEvent(&cbParams);
+            }
+            break;
+        }
+        case GattServerEvents::GATT_EVENT_READ_AUTHORIZATION_REQ: {
+            GattReadAuthCallbackParams cbParams = {
+                .connHandle         = gattsEventP->conn_handle,
+                .handle             = handle_value,
+                .offset             = gattsEventP->params.authorize_request.request.read.offset,
+                .len                = 0,
+                .data               = NULL,
+                .authorizationReply = AUTH_CALLBACK_REPLY_SUCCESS /* the callback handler must leave this member
+                                                                   * set to AUTH_CALLBACK_REPLY_SUCCESS if the client
+                                                                   * request is to proceed. */
+            };
+
+            ble_gatts_rw_authorize_reply_params_t reply = {
+                .type = BLE_GATTS_AUTHORIZE_TYPE_READ,
+                .params = {
+                    .read = {
+                        .gatt_status = p_characteristics[characteristicIndex]->authorizeRead(&cbParams)
+                    }
+                }
+            };
+
+            if (cbParams.authorizationReply == BLE_GATT_STATUS_SUCCESS) {
+                if (cbParams.data != NULL) {
+                    reply.params.read.update = 1;
+                    reply.params.read.offset = cbParams.offset;
+                    reply.params.read.len    = cbParams.len;
+                    reply.params.read.p_data = cbParams.data;
+                }
+            }
+
+            sd_ble_gatts_rw_authorize_reply(gattsEventP->conn_handle, &reply);
+            break;
+        }
+
+        default:
+            handleEvent(eventType, handle_value);
+            break;
+    }
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h
new file mode 100644
index 0000000000..1a1ad86d89
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xGattServer.h
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF51822_GATT_SERVER_H__
+#define __NRF51822_GATT_SERVER_H__
+
+#include <stddef.h>
+
+#include "ble/blecommon.h"
+#include "nrf_ble.h" /* nordic ble */
+#include "ble/Gap.h"
+#include "ble/GattServer.h"
+
+class nRF5xGattServer : public GattServer
+{
+public:
+    /* Functions that must be implemented from GattServer */
+    virtual ble_error_t addService(GattService &);
+    virtual ble_error_t read(GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP);
+    virtual ble_error_t read(Gap::Handle_t connectionHandle, GattAttribute::Handle_t attributeHandle, uint8_t buffer[], uint16_t *lengthP);
+    virtual ble_error_t write(GattAttribute::Handle_t, const uint8_t[], uint16_t, bool localOnly = false);
+    virtual ble_error_t write(Gap::Handle_t connectionHandle, GattAttribute::Handle_t, const uint8_t[], uint16_t, bool localOnly = false);
+    virtual ble_error_t areUpdatesEnabled(const GattCharacteristic &characteristic, bool *enabledP);
+    virtual ble_error_t areUpdatesEnabled(Gap::Handle_t connectionHandle, const GattCharacteristic &characteristic, bool *enabledP);
+    virtual ble_error_t reset(void);
+
+    /* nRF51 Functions */
+    void eventCallback(void);
+    void hwCallback(ble_evt_t *p_ble_evt);
+
+
+private:
+    const static unsigned BLE_TOTAL_CHARACTERISTICS = 20;
+    const static unsigned BLE_TOTAL_DESCRIPTORS     = 8;
+
+private:
+    /**
+     * resolve a value attribute to its owning characteristic.
+     * @param  valueHandle the value handle to be resolved.
+     * @return             characteristic index if a resolution is found, else -1.
+     */
+    int resolveValueHandleToCharIndex(GattAttribute::Handle_t valueHandle) const {
+        unsigned charIndex;
+        for (charIndex = 0; charIndex < characteristicCount; charIndex++) {
+            if (nrfCharacteristicHandles[charIndex].value_handle == valueHandle) {
+                return charIndex;
+            }
+        }
+
+        return -1;
+    }
+
+    /**
+     * resolve a CCCD attribute handle to its owning characteristic.
+     * @param  cccdHandle the CCCD handle to be resolved.
+     * @return             characteristic index if a resolution is found, else -1.
+     */
+    int resolveCCCDHandleToCharIndex(GattAttribute::Handle_t cccdHandle) const {
+        unsigned charIndex;
+        for (charIndex = 0; charIndex < characteristicCount; charIndex++) {
+            if (nrfCharacteristicHandles[charIndex].cccd_handle == cccdHandle) {
+                return charIndex;
+            }
+        }
+
+        return -1;
+    }
+
+private:
+    GattCharacteristic       *p_characteristics[BLE_TOTAL_CHARACTERISTICS];
+    ble_gatts_char_handles_t  nrfCharacteristicHandles[BLE_TOTAL_CHARACTERISTICS];
+    GattAttribute            *p_descriptors[BLE_TOTAL_DESCRIPTORS];
+    uint8_t                   descriptorCount;
+    uint16_t                  nrfDescriptorHandles[BLE_TOTAL_DESCRIPTORS];
+
+    /*
+     * Allow instantiation from nRF5xn when required.
+     */
+    friend class nRF5xn;
+
+    nRF5xGattServer() : GattServer(), p_characteristics(), nrfCharacteristicHandles(), p_descriptors(), descriptorCount(0), nrfDescriptorHandles() {
+        /* empty */
+    }
+
+private:
+    nRF5xGattServer(const nRF5xGattServer &);
+    const nRF5xGattServer& operator=(const nRF5xGattServer &);
+};
+
+#endif // ifndef __NRF51822_GATT_SERVER_H__
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h
new file mode 100644
index 0000000000..2fa7b05511
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xSecurityManager.h
@@ -0,0 +1,174 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF51822_SECURITY_MANAGER_H__
+#define __NRF51822_SECURITY_MANAGER_H__
+
+#include <stddef.h>
+
+#include "nRF5xGap.h"
+#include "ble/SecurityManager.h"
+#include "btle_security.h"
+
+class nRF5xSecurityManager : public SecurityManager
+{
+public:
+    /* Functions that must be implemented from SecurityManager */
+    virtual ble_error_t init(bool                     enableBonding,
+                             bool                     requireMITM,
+                             SecurityIOCapabilities_t iocaps,
+                             const Passkey_t          passkey) {
+        return btle_initializeSecurity(enableBonding, requireMITM, iocaps, passkey);
+    }
+
+    virtual ble_error_t getLinkSecurity(Gap::Handle_t connectionHandle, LinkSecurityStatus_t *securityStatusP) {
+        return btle_getLinkSecurity(connectionHandle, securityStatusP);
+    }
+
+    virtual ble_error_t setLinkSecurity(Gap::Handle_t connectionHandle, SecurityMode_t securityMode) {
+        return btle_setLinkSecurity(connectionHandle, securityMode);
+    }
+
+    virtual ble_error_t purgeAllBondingState(void) {
+        return btle_purgeAllBondingState();
+    }
+
+    /**
+     * @brief  Returns a list of addresses from peers in the stacks bond table.
+     *
+     * @param[in/out]   addresses
+     *                  (on input) @ref Gap::Whitelist_t structure where at
+     *                  most addresses.capacity addresses from bonded peers will
+     *                  be stored.
+     *                  (on output) A copy of the addresses from bonded peers.
+     *
+     * @return
+     *           BLE_ERROR_NONE if successful.
+     */
+    virtual ble_error_t getAddressesFromBondTable(Gap::Whitelist_t &addresses) const {
+        uint8_t i;
+
+        ble_gap_whitelist_t  whitelistFromBondTable;
+        ble_gap_addr_t      *addressPtr[YOTTA_CFG_WHITELIST_MAX_SIZE];
+        ble_gap_irk_t       *irkPtr[YOTTA_CFG_IRK_TABLE_MAX_SIZE];
+
+        /* Initialize the structure so that we get as many addreses as the whitelist can hold */
+        whitelistFromBondTable.addr_count = YOTTA_CFG_IRK_TABLE_MAX_SIZE;
+        whitelistFromBondTable.pp_addrs   = addressPtr;
+        whitelistFromBondTable.irk_count  = YOTTA_CFG_IRK_TABLE_MAX_SIZE;
+        whitelistFromBondTable.pp_irks    = irkPtr;
+
+        ble_error_t error = createWhitelistFromBondTable(whitelistFromBondTable);
+        if (error != BLE_ERROR_NONE) {
+            addresses.size = 0;
+            return error;
+        }
+
+        /* Put all the addresses in the structure */
+        for (i = 0; i < whitelistFromBondTable.addr_count; ++i) {
+            if (i >= addresses.capacity) {
+                /* Ran out of space in the output Gap::Whitelist_t */
+                addresses.size = i;
+                return BLE_ERROR_NONE;
+            }
+            memcpy(&addresses.addresses[i], whitelistFromBondTable.pp_addrs[i], sizeof(BLEProtocol::Address_t));
+        }
+
+        /* Update the current address count */
+        addresses.size = i;
+
+        /* The assumption here is that the underlying implementation of
+         * createWhitelistFromBondTable()  will not return the private resolvable
+         * addresses (which is the case in the SoftDevice). Rather it returns the
+         * IRKs, so we need to generate the private resolvable address by ourselves.
+         */
+        for (i = 0; i < whitelistFromBondTable.irk_count; ++i) {
+            if (i + addresses.size >= addresses.capacity) {
+                /* Ran out of space in the output Gap::Whitelist_t */
+                addresses.size += i;
+                return BLE_ERROR_NONE;
+            }
+            btle_generateResolvableAddress(
+                *whitelistFromBondTable.pp_irks[i],
+                (ble_gap_addr_t &) addresses.addresses[i + addresses.size]
+            );
+        }
+
+        /* Update the current address count */
+        addresses.size += i;
+
+        return BLE_ERROR_NONE;
+    }
+
+    /**
+     * @brief  Clear nRF5xSecurityManager's state.
+     *
+     * @return
+     *           BLE_ERROR_NONE if successful.
+     */
+    virtual ble_error_t reset(void)
+    {
+        if (SecurityManager::reset() != BLE_ERROR_NONE) {
+            return BLE_ERROR_INVALID_STATE;
+        }
+
+        return BLE_ERROR_NONE;
+    }
+
+    bool hasInitialized(void) const {
+        return btle_hasInitializedSecurity();
+    }
+
+public:
+    /*
+     * Allow instantiation from nRF5xn when required.
+     */
+    friend class nRF5xn;
+
+    nRF5xSecurityManager() {
+        /* empty */
+    }
+
+private:
+    nRF5xSecurityManager(const nRF5xSecurityManager &);
+    const nRF5xSecurityManager& operator=(const nRF5xSecurityManager &);
+
+    /*
+     * Expose an interface that allows us to query the SoftDevice bond table
+     * and extract a whitelist.
+     */
+    ble_error_t createWhitelistFromBondTable(ble_gap_whitelist_t &whitelistFromBondTable) const {
+        return btle_createWhitelistFromBondTable(&whitelistFromBondTable);
+    }
+
+    /*
+     * Given a BLE address and a IRK this function check whether the address
+     * can be generated from the IRK. To do so, this function uses the hash
+     * function and algorithm described in the Bluetooth low Energy
+     * Specification. Internally, Nordic SDK functions are used.
+     */
+    bool matchAddressAndIrk(ble_gap_addr_t *address, ble_gap_irk_t *irk) const {
+        return btle_matchAddressAndIrk(address, irk);
+    }
+
+    /*
+     * Give nRF5xGap access to createWhitelistFromBondTable() and
+     * matchAddressAndIrk()
+     */
+    friend class nRF5xGap;
+};
+
+#endif // ifndef __NRF51822_SECURITY_MANAGER_H__
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp
new file mode 100644
index 0000000000..4bd0da6dd7
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.cpp
@@ -0,0 +1,312 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "nRF5xServiceDiscovery.h"
+
+ble_error_t
+nRF5xServiceDiscovery::launchCharacteristicDiscovery(Gap::Handle_t connectionHandle,
+                                                     Gap::Handle_t startHandle,
+                                                     Gap::Handle_t endHandle)
+{
+    characteristicDiscoveryStarted(connectionHandle);
+
+    ble_gattc_handle_range_t handleRange = {
+        .start_handle = startHandle,
+        .end_handle   = endHandle
+    };
+    uint32_t rc = sd_ble_gattc_characteristics_discover(connectionHandle, &handleRange);
+    ble_error_t err = BLE_ERROR_NONE;
+
+    switch (rc) {
+        case NRF_SUCCESS:
+            err = BLE_ERROR_NONE;
+            break;
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+        case NRF_ERROR_INVALID_ADDR:
+            err = BLE_ERROR_INVALID_PARAM;
+            break;
+        case NRF_ERROR_BUSY:
+            err = BLE_STACK_BUSY;
+            break;
+        case NRF_ERROR_INVALID_STATE:
+            err = BLE_ERROR_INVALID_STATE;
+            break;
+        default:
+            err = BLE_ERROR_UNSPECIFIED;
+            break;
+    }
+
+    if (err) {
+        terminateCharacteristicDiscovery(err);
+    }
+    return err;
+}
+
+void
+nRF5xServiceDiscovery::setupDiscoveredServices(const ble_gattc_evt_prim_srvc_disc_rsp_t *response)
+{
+    serviceIndex = 0;
+    numServices  = response->count;
+
+    /* Account for the limitation on the number of discovered services we can handle at a time. */
+    if (numServices > BLE_DB_DISCOVERY_MAX_SRV) {
+        numServices = BLE_DB_DISCOVERY_MAX_SRV;
+    }
+
+    serviceUUIDDiscoveryQueue.reset();
+    for (unsigned i = 0; i < numServices; ++i) {
+        if (response->services[i].uuid.type == BLE_UUID_TYPE_UNKNOWN) {
+            serviceUUIDDiscoveryQueue.enqueue(i);
+            services[i].setup(response->services[i].handle_range.start_handle,
+                                         response->services[i].handle_range.end_handle);
+        } else {
+            services[i].setup(response->services[i].uuid.uuid,
+                                         response->services[i].handle_range.start_handle,
+                                         response->services[i].handle_range.end_handle);
+        }
+    }
+
+    /* Trigger discovery of service UUID if necessary. */
+    if (serviceUUIDDiscoveryQueue.getCount()) {
+        serviceUUIDDiscoveryQueue.triggerFirst();
+    }
+}
+
+void
+nRF5xServiceDiscovery::setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response)
+{
+    numCharacteristics  = response->count;
+
+    /* Account for the limitation on the number of discovered characteristics we can handle at a time. */
+    if (numCharacteristics > BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV) {
+        numCharacteristics = BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV;
+    }
+
+    charUUIDDiscoveryQueue.reset();
+    for (unsigned charIndex = 0; charIndex < numCharacteristics; charIndex++) {
+        if (response->chars[charIndex].uuid.type == BLE_UUID_TYPE_UNKNOWN) {
+            charUUIDDiscoveryQueue.enqueue(charIndex);
+            characteristics[charIndex].setup(gattc,
+                                             connHandle,
+                                             response->chars[charIndex].char_props,
+                                             response->chars[charIndex].handle_decl,
+                                             response->chars[charIndex].handle_value);
+        } else {
+            characteristics[charIndex].setup(gattc,
+                                             connHandle,
+                                             response->chars[charIndex].uuid.uuid,
+                                             response->chars[charIndex].char_props,
+                                             response->chars[charIndex].handle_decl,
+                                             response->chars[charIndex].handle_value);
+        }
+    }
+
+    /* Trigger discovery of char UUID if necessary. */
+    if (charUUIDDiscoveryQueue.getCount()) {
+        charUUIDDiscoveryQueue.triggerFirst();
+    }
+}
+
+void
+nRF5xServiceDiscovery::progressCharacteristicDiscovery(void)
+{
+    if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) {
+        return;
+    }
+
+    if ((discoveredCharacteristic != nRF5xDiscoveredCharacteristic()) && (numCharacteristics > 0)) {
+        discoveredCharacteristic.setLastHandle(characteristics[0].getDeclHandle() - 1);
+
+        if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) ||
+            ((matchingCharacteristicUUID == discoveredCharacteristic.getUUID()) &&
+             (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) {
+            if (characteristicCallback) {
+                characteristicCallback(&discoveredCharacteristic);
+            }
+        }
+    }
+
+    for (uint8_t i = 0; i < numCharacteristics; ++i) {
+        if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) {
+            return;
+        }
+
+        if (i == (numCharacteristics - 1)) {
+            discoveredCharacteristic = characteristics[i];
+            break;
+        } else {
+            characteristics[i].setLastHandle(characteristics[i + 1].getDeclHandle() - 1);
+        }
+
+        if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) ||
+            ((matchingCharacteristicUUID == characteristics[i].getUUID()) &&
+             (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) {
+            if (characteristicCallback) {
+                characteristicCallback(&characteristics[i]);
+            }
+        }
+    }
+
+    if (state != CHARACTERISTIC_DISCOVERY_ACTIVE) {
+        return;
+    }
+
+    Gap::Handle_t startHandle = (numCharacteristics > 0) ? characteristics[numCharacteristics - 1].getValueHandle() + 1 : SRV_DISC_END_HANDLE;
+    Gap::Handle_t endHandle   = services[serviceIndex].getEndHandle();
+    resetDiscoveredCharacteristics(); /* Note: resetDiscoveredCharacteristics() must come after fetching start and end Handles. */
+
+    if (startHandle < endHandle) {
+        ble_gattc_handle_range_t handleRange = {
+            .start_handle = startHandle,
+            .end_handle   = endHandle
+        };
+        if (sd_ble_gattc_characteristics_discover(connHandle, &handleRange) != NRF_SUCCESS) {
+            terminateCharacteristicDiscovery(BLE_ERROR_UNSPECIFIED);
+        }
+    } else {
+        terminateCharacteristicDiscovery(BLE_ERROR_NONE);
+    }
+}
+
+void
+nRF5xServiceDiscovery::progressServiceDiscovery(void)
+{
+    /* Iterate through the previously discovered services cached in services[]. */
+    while ((state == SERVICE_DISCOVERY_ACTIVE) && (serviceIndex < numServices)) {
+        if ((matchingServiceUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) ||
+            (matchingServiceUUID == services[serviceIndex].getUUID())) {
+
+            if (serviceCallback && (matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN))) {
+                serviceCallback(&services[serviceIndex]);
+            }
+
+            if ((state == SERVICE_DISCOVERY_ACTIVE) && characteristicCallback) {
+                launchCharacteristicDiscovery(connHandle, services[serviceIndex].getStartHandle(), services[serviceIndex].getEndHandle());
+            } else {
+                serviceIndex++;
+            }
+        } else {
+            serviceIndex++;
+        }
+    }
+
+    /* Relaunch discovery of new services beyond the last entry cached in services[]. */
+    if ((state == SERVICE_DISCOVERY_ACTIVE) && (numServices > 0) && (serviceIndex > 0)) {
+        /* Determine the ending handle of the last cached service. */
+        Gap::Handle_t endHandle = services[serviceIndex - 1].getEndHandle();
+        resetDiscoveredServices(); /* Note: resetDiscoveredServices() must come after fetching endHandle. */
+
+        if (endHandle == SRV_DISC_END_HANDLE) {
+            terminateServiceDiscovery();
+        } else {
+            // the next service is located after the last handle discovered
+            // Launch a new discovery from [endHandle + 1 : 0xFFFF]
+            if (sd_ble_gattc_primary_services_discover(connHandle, endHandle + 1, NULL) != NRF_SUCCESS) {
+                terminateServiceDiscovery();
+            }
+        }
+    }
+}
+
+void
+nRF5xServiceDiscovery::ServiceUUIDDiscoveryQueue::triggerFirst(void)
+{
+    while (numIndices) { /* loop until a call to char_value_by_uuid_read() succeeds or we run out of pending indices. */
+        parentDiscoveryObject->state = DISCOVER_SERVICE_UUIDS;
+
+        unsigned serviceIndex = getFirst();
+        ble_uuid_t uuid = {
+            .uuid = BLE_UUID_SERVICE_PRIMARY,
+            .type = BLE_UUID_TYPE_BLE,
+        };
+        ble_gattc_handle_range_t handleRange = {
+            .start_handle = parentDiscoveryObject->services[serviceIndex].getStartHandle(),
+            .end_handle   = parentDiscoveryObject->services[serviceIndex].getEndHandle(),
+        };
+        if (sd_ble_gattc_char_value_by_uuid_read(parentDiscoveryObject->connHandle, &uuid, &handleRange) == NRF_SUCCESS) {
+            return;
+        }
+
+        /* Skip this service if we fail to launch a read for its service-declaration
+         * attribute. Its UUID will remain INVALID, and it may not match any filters. */
+        dequeue();
+    }
+
+    /* Switch back to service discovery upon exhausting the service-indices pending UUID discovery. */
+    if (parentDiscoveryObject->state == DISCOVER_SERVICE_UUIDS) {
+        parentDiscoveryObject->state = SERVICE_DISCOVERY_ACTIVE;
+    }
+}
+
+void
+nRF5xServiceDiscovery::CharUUIDDiscoveryQueue::triggerFirst(void)
+{
+    while (numIndices) { /* loop until a call to char_value_by_uuid_read() succeeds or we run out of pending indices. */
+        parentDiscoveryObject->state = DISCOVER_CHARACTERISTIC_UUIDS;
+
+        unsigned charIndex = getFirst();
+        ble_uuid_t uuid = {
+            .uuid = BLE_UUID_CHARACTERISTIC,
+            .type = BLE_UUID_TYPE_BLE,
+        };
+        ble_gattc_handle_range_t handleRange = { };
+        handleRange.start_handle = parentDiscoveryObject->characteristics[charIndex].getDeclHandle();
+        handleRange.end_handle   = parentDiscoveryObject->characteristics[charIndex].getDeclHandle() + 1;
+        if (sd_ble_gattc_char_value_by_uuid_read(parentDiscoveryObject->connHandle, &uuid, &handleRange) == NRF_SUCCESS) {
+            return;
+        }
+
+        /* Skip this service if we fail to launch a read for its service-declaration
+         * attribute. Its UUID will remain INVALID, and it may not match any filters. */
+        dequeue();
+    }
+
+    /* Switch back to service discovery upon exhausting the service-indices pending UUID discovery. */
+    if (parentDiscoveryObject->state == DISCOVER_CHARACTERISTIC_UUIDS) {
+        parentDiscoveryObject->state = CHARACTERISTIC_DISCOVERY_ACTIVE;
+    }
+}
+
+void
+nRF5xServiceDiscovery::processDiscoverUUIDResponse(const ble_gattc_evt_char_val_by_uuid_read_rsp_t *response)
+{
+    if (state == DISCOVER_SERVICE_UUIDS) {
+        if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID)) {
+            UUID::LongUUIDBytes_t uuid;
+            memcpy(uuid, response->handle_value[0].p_value, UUID::LENGTH_OF_LONG_UUID);
+
+            unsigned serviceIndex = serviceUUIDDiscoveryQueue.dequeue();
+            services[serviceIndex].setupLongUUID(uuid, UUID::LSB);
+
+            serviceUUIDDiscoveryQueue.triggerFirst();
+        } else {
+            serviceUUIDDiscoveryQueue.dequeue();
+        }
+    } else if (state == DISCOVER_CHARACTERISTIC_UUIDS) {
+        if ((response->count == 1) && (response->value_len == UUID::LENGTH_OF_LONG_UUID + 1 /* props */ + 2 /* value handle */)) {
+            UUID::LongUUIDBytes_t uuid;
+
+            memcpy(uuid, &(response->handle_value[0].p_value[3]), UUID::LENGTH_OF_LONG_UUID);
+
+            unsigned charIndex = charUUIDDiscoveryQueue.dequeue();
+            characteristics[charIndex].setupLongUUID(uuid, UUID::LSB);
+
+            charUUIDDiscoveryQueue.triggerFirst();
+        } else {
+            charUUIDDiscoveryQueue.dequeue();
+        }
+    }
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h
new file mode 100644
index 0000000000..20bf505936
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xServiceDiscovery.h
@@ -0,0 +1,366 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF_SERVICE_DISCOVERY_H__
+#define __NRF_SERVICE_DISCOVERY_H__
+
+#include "ble/ServiceDiscovery.h"
+#include "ble/DiscoveredService.h"
+#include "nRF5xDiscoveredCharacteristic.h"
+
+#include "nrf_ble.h"
+#include "nrf_ble_gattc.h"
+
+class nRF5xGattClient; /* forward declaration */
+
+class nRF5xServiceDiscovery : public ServiceDiscovery
+{
+public:
+    static const uint16_t SRV_DISC_START_HANDLE             = 0x0001; /**< The start handle value used during service discovery. */
+    static const uint16_t SRV_DISC_END_HANDLE               = 0xFFFF; /**< The end handle value used during service discovery. */
+
+public:
+    static const unsigned BLE_DB_DISCOVERY_MAX_SRV          = 4;      /**< Maximum number of services we can retain information for after a single discovery. */
+    static const unsigned BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV = 4;      /**< Maximum number of characteristics per service we can retain information for. */
+
+public:
+    nRF5xServiceDiscovery(nRF5xGattClient *gattcIn) :
+        gattc(gattcIn),
+        serviceIndex(0),
+        numServices(0),
+        numCharacteristics(0),
+        state(INACTIVE),
+        services(),
+        characteristics(),
+        serviceUUIDDiscoveryQueue(this),
+        charUUIDDiscoveryQueue(this),
+        onTerminationCallback(NULL) {
+        /* empty */
+    }
+
+    virtual ble_error_t launch(Gap::Handle_t                               connectionHandle,
+                               ServiceDiscovery::ServiceCallback_t         sc,
+                               ServiceDiscovery::CharacteristicCallback_t  cc,
+                               const UUID                                 &matchingServiceUUIDIn,
+                               const UUID                                 &matchingCharacteristicUUIDIn)
+    {
+        if (isActive()) {
+            return BLE_ERROR_INVALID_STATE;
+        }
+
+        serviceCallback            = sc;
+        characteristicCallback     = cc;
+        matchingServiceUUID        = matchingServiceUUIDIn;
+        matchingCharacteristicUUID = matchingCharacteristicUUIDIn;
+
+        serviceDiscoveryStarted(connectionHandle);
+
+        uint32_t rc;
+        if ((rc = sd_ble_gattc_primary_services_discover(connectionHandle, SRV_DISC_START_HANDLE, NULL)) != NRF_SUCCESS) {
+            terminate();
+            switch (rc) {
+                case NRF_ERROR_INVALID_PARAM:
+                case BLE_ERROR_INVALID_CONN_HANDLE:
+                    return BLE_ERROR_INVALID_PARAM;
+                case NRF_ERROR_BUSY:
+                    return BLE_STACK_BUSY;
+                default:
+                case NRF_ERROR_INVALID_STATE:
+                    return BLE_ERROR_INVALID_STATE;
+            }
+        }
+
+        return BLE_ERROR_NONE;
+    }
+
+    virtual bool isActive(void) const {
+        return state != INACTIVE;
+    }
+
+    virtual void terminate(void) {
+        terminateServiceDiscovery();
+    }
+
+    void terminate(Gap::Handle_t connectionHandle) {
+        if(connHandle == connectionHandle) {
+            terminate();
+        }
+    }
+
+    virtual void onTermination(ServiceDiscovery::TerminationCallback_t callback) {
+        onTerminationCallback = callback;
+    }
+
+    /**
+     * @brief  Clear nRF5xServiceDiscovery's state.
+     *
+     * @return
+     *           BLE_ERROR_NONE if successful.
+     */
+    virtual ble_error_t reset(void) {
+        /* Clear all state that is from the parent, including private members */
+        if (ServiceDiscovery::reset() != BLE_ERROR_NONE) {
+            return BLE_ERROR_INVALID_STATE;
+        }
+
+        /* Clear derived class members */
+        serviceIndex = 0;
+        numServices = 0;
+        numCharacteristics = 0;
+
+        state = INACTIVE;
+
+        serviceUUIDDiscoveryQueue.reset();
+        charUUIDDiscoveryQueue.reset();
+
+        onTerminationCallback = NULL;
+
+        return BLE_ERROR_NONE;
+    }
+
+private:
+    ble_error_t launchCharacteristicDiscovery(Gap::Handle_t connectionHandle, Gap::Handle_t startHandle, Gap::Handle_t endHandle);
+
+private:
+    void setupDiscoveredServices(const ble_gattc_evt_prim_srvc_disc_rsp_t *response);
+    void setupDiscoveredCharacteristics(const ble_gattc_evt_char_disc_rsp_t *response);
+
+    void triggerServiceUUIDDiscovery(void);
+    void processDiscoverUUIDResponse(const ble_gattc_evt_char_val_by_uuid_read_rsp_t *response);
+    void removeFirstServiceNeedingUUIDDiscovery(void);
+
+    void terminateServiceDiscovery(void) {
+        discoveredCharacteristic = nRF5xDiscoveredCharacteristic();
+
+        bool wasActive = isActive();
+        state = INACTIVE;
+
+        if (wasActive && onTerminationCallback) {
+            onTerminationCallback(connHandle);
+        }
+    }
+
+    void terminateCharacteristicDiscovery(ble_error_t err) {
+        if (state == CHARACTERISTIC_DISCOVERY_ACTIVE) {
+            if(discoveredCharacteristic != nRF5xDiscoveredCharacteristic()) {
+               if(err == BLE_ERROR_NONE) {
+                    // fullfill the last characteristic
+                    discoveredCharacteristic.setLastHandle(services[serviceIndex].getEndHandle());
+
+                    if ((matchingCharacteristicUUID == UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)) ||
+                        ((matchingCharacteristicUUID == discoveredCharacteristic.getUUID()) &&
+                         (matchingServiceUUID != UUID::ShortUUIDBytes_t(BLE_UUID_UNKNOWN)))) {
+                        if (characteristicCallback) {
+                            characteristicCallback(&discoveredCharacteristic);
+                        }
+                    }
+               }
+               discoveredCharacteristic = nRF5xDiscoveredCharacteristic();
+            }
+
+            state = SERVICE_DISCOVERY_ACTIVE;
+        }
+        serviceIndex++; /* Progress service index to keep discovery alive. */
+    }
+
+private:
+    void resetDiscoveredServices(void) {
+        numServices  = 0;
+        serviceIndex = 0;
+    }
+
+    void resetDiscoveredCharacteristics(void) {
+        numCharacteristics  = 0;
+    }
+
+private:
+    void serviceDiscoveryStarted(Gap::Handle_t connectionHandle) {
+        connHandle = connectionHandle;
+        resetDiscoveredServices();
+        state = SERVICE_DISCOVERY_ACTIVE;
+    }
+
+private:
+    void characteristicDiscoveryStarted(Gap::Handle_t connectionHandle) {
+        connHandle = connectionHandle;
+        resetDiscoveredCharacteristics();
+        state = CHARACTERISTIC_DISCOVERY_ACTIVE;
+    }
+
+private:
+    /**
+     * A datatype to contain service-indices for which long UUIDs need to be
+     * discovered using read_val_by_uuid().
+     */
+    class ServiceUUIDDiscoveryQueue {
+    public:
+        ServiceUUIDDiscoveryQueue(nRF5xServiceDiscovery *parent) :
+            numIndices(0),
+            serviceIndices(),
+            parentDiscoveryObject(parent) {
+            /* empty */
+        }
+
+    public:
+        void reset(void) {
+            numIndices = 0;
+            for (unsigned i = 0; i < BLE_DB_DISCOVERY_MAX_SRV; i++) {
+                serviceIndices[i] = INVALID_INDEX;
+            }
+        }
+        void enqueue(int serviceIndex) {
+            serviceIndices[numIndices++] = serviceIndex;
+        }
+        int dequeue(void) {
+            if (numIndices == 0) {
+                return INVALID_INDEX;
+            }
+
+            unsigned valueToReturn = serviceIndices[0];
+            numIndices--;
+            for (unsigned i = 0; i < numIndices; i++) {
+                serviceIndices[i] = serviceIndices[i + 1];
+            }
+
+            return valueToReturn;
+        }
+        unsigned getFirst(void) const {
+            return serviceIndices[0];
+        }
+        size_t getCount(void) const {
+            return numIndices;
+        }
+
+        /**
+         * Trigger UUID discovery for the first of the enqueued ServiceIndices.
+         */
+        void triggerFirst(void);
+
+    private:
+        static const int INVALID_INDEX = -1;
+
+    private:
+        size_t numIndices;
+        int    serviceIndices[BLE_DB_DISCOVERY_MAX_SRV];
+
+        nRF5xServiceDiscovery *parentDiscoveryObject;
+    };
+    friend class ServiceUUIDDiscoveryQueue;
+
+    /**
+     * A datatype to contain characteristic-indices for which long UUIDs need to
+     * be discovered using read_val_by_uuid().
+     */
+    class CharUUIDDiscoveryQueue {
+    public:
+        CharUUIDDiscoveryQueue(nRF5xServiceDiscovery *parent) :
+            numIndices(0),
+            charIndices(),
+            parentDiscoveryObject(parent) {
+            /* empty */
+        }
+
+    public:
+        void reset(void) {
+            numIndices = 0;
+            for (unsigned i = 0; i < BLE_DB_DISCOVERY_MAX_SRV; i++) {
+                charIndices[i] = INVALID_INDEX;
+            }
+        }
+        void enqueue(int serviceIndex) {
+            charIndices[numIndices++] = serviceIndex;
+        }
+        int dequeue(void) {
+            if (numIndices == 0) {
+                return INVALID_INDEX;
+            }
+
+            unsigned valueToReturn = charIndices[0];
+            numIndices--;
+            for (unsigned i = 0; i < numIndices; i++) {
+                charIndices[i] = charIndices[i + 1];
+            }
+
+            return valueToReturn;
+        }
+        unsigned getFirst(void) const {
+            return charIndices[0];
+        }
+        size_t getCount(void) const {
+            return numIndices;
+        }
+
+        /**
+         * Trigger UUID discovery for the first of the enqueued charIndices.
+         */
+        void triggerFirst(void);
+
+    private:
+        static const int INVALID_INDEX = -1;
+
+    private:
+        size_t numIndices;
+        int    charIndices[BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV];
+
+        nRF5xServiceDiscovery *parentDiscoveryObject;
+    };
+    friend class CharUUIDDiscoveryQueue;
+
+private:
+    friend void bleGattcEventHandler(const ble_evt_t *p_ble_evt);
+    void progressCharacteristicDiscovery(void);
+    void progressServiceDiscovery(void);
+
+private:
+    nRF5xGattClient *gattc;
+
+private:
+    uint8_t  serviceIndex;        /**< Index of the current service being discovered. This is intended for internal use during service discovery.*/
+    uint8_t  numServices;         /**< Number of services at the peers GATT database.*/
+    uint8_t  numCharacteristics;  /**< Number of characteristics within the service.*/
+
+    enum State_t {
+        INACTIVE,
+        SERVICE_DISCOVERY_ACTIVE,
+        CHARACTERISTIC_DISCOVERY_ACTIVE,
+        DISCOVER_SERVICE_UUIDS,
+        DISCOVER_CHARACTERISTIC_UUIDS,
+    } state;
+
+    DiscoveredService           services[BLE_DB_DISCOVERY_MAX_SRV];  /**< Information related to the current service being discovered.
+                                                                      *  This is intended for internal use during service discovery. */
+    nRF5xDiscoveredCharacteristic characteristics[BLE_DB_DISCOVERY_MAX_CHAR_PER_SRV];
+
+    ServiceUUIDDiscoveryQueue   serviceUUIDDiscoveryQueue;
+    CharUUIDDiscoveryQueue      charUUIDDiscoveryQueue;
+
+    TerminationCallback_t       onTerminationCallback;
+
+    /*
+     * The currently discovered characteristic. Discovery of a characteristic
+     * is a two phase process.
+     * First, declaration handle is fetched, it provide the UUID, the value handle and
+     * the properties of a characteristic.
+     * Second, the next declaration handle is fetched, with its declaration handle, it is
+     * possible to compute the last handle of the discovered characteristic and fill the
+     * missing part of the object.
+     * If there is no remaining characteristic to discover, the last handle of the
+     * discovered characteristic will be set to the last handle of its enclosing service.
+     */
+    nRF5xDiscoveredCharacteristic discoveredCharacteristic;
+};
+
+#endif /*__NRF_SERVICE_DISCOVERY_H__*/
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp
new file mode 100644
index 0000000000..f09d8bfb37
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.cpp
@@ -0,0 +1,220 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifdef YOTTA_CFG_MBED_OS
+    #include "mbed-drivers/mbed.h"
+#else
+    #include "mbed.h"
+#endif
+#include "nRF5xn.h"
+#include "ble/blecommon.h"
+#include "nrf_soc.h"
+
+#include "btle/btle.h"
+#include "btle/custom/custom_helper.h"
+#include "nrf_delay.h"
+
+extern "C" {
+#include "softdevice_handler.h"
+}
+
+/**
+ * The singleton which represents the nRF51822 transport for the BLE.
+ */
+static nRF5xn deviceInstance;
+
+/**
+ * BLE-API requires an implementation of the following function in order to
+ * obtain its transport handle.
+ */
+BLEInstanceBase *
+createBLEInstance(void)
+{
+    return &nRF5xn::Instance(BLE::DEFAULT_INSTANCE);
+}
+
+nRF5xn& nRF5xn::Instance(BLE::InstanceID_t instanceId)
+{
+    return deviceInstance;
+}
+
+nRF5xn::nRF5xn(void) :
+    initialized(false),
+    instanceID(BLE::DEFAULT_INSTANCE),
+    gapInstance(),
+    gattServerInstance(NULL),
+    gattClientInstance(NULL),
+    securityManagerInstance(NULL)
+{
+}
+
+nRF5xn::~nRF5xn(void)
+{
+}
+
+const char *nRF5xn::getVersion(void)
+{
+    if (!initialized) {
+        return "INITIALIZATION_INCOMPLETE";
+    }
+
+    static char versionString[32];
+    static bool versionFetched = false;
+
+    if (!versionFetched) {
+        ble_version_t version;
+        if ((sd_ble_version_get(&version) == NRF_SUCCESS) && (version.company_id == 0x0059)) {
+            switch (version.version_number) {
+                case 0x07:
+                case 0x08:
+                    snprintf(versionString, sizeof(versionString), "Nordic BLE4.1 ver:%u fw:%04x", version.version_number, version.subversion_number);
+                    break;
+                default:
+                    snprintf(versionString, sizeof(versionString), "Nordic (spec unknown) ver:%u fw:%04x", version.version_number, version.subversion_number);
+                    break;
+            }
+            versionFetched = true;
+        } else {
+            strncpy(versionString, "unknown", sizeof(versionString));
+        }
+    }
+
+    return versionString;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Initialize the BLE stack.
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE if everything executed properly and
+                BLE_ERROR_ALREADY_INITIALIZED if the stack has already
+                been initialized (possibly through a call to nRF5xn::init()).
+                BLE_ERROR_INTERNAL_STACK_FAILURE is returned if initialization
+                of the internal stack (SoftDevice) failed.
+
+*/
+/**************************************************************************/
+ble_error_t nRF5xn::init(BLE::InstanceID_t instanceID, FunctionPointerWithContext<BLE::InitializationCompleteCallbackContext *> callback)
+{
+    if (initialized) {
+        BLE::InitializationCompleteCallbackContext context = {
+            BLE::Instance(instanceID),
+            BLE_ERROR_ALREADY_INITIALIZED
+        };
+        callback.call(&context);
+        return BLE_ERROR_ALREADY_INITIALIZED;
+    }
+
+    instanceID   = instanceID;
+
+    /* ToDo: Clear memory contents, reset the SD, etc. */
+    if (btle_init() != ERROR_NONE) {
+        return BLE_ERROR_INTERNAL_STACK_FAILURE;
+    }
+
+    initialized = true;
+    BLE::InitializationCompleteCallbackContext context = {
+        BLE::Instance(instanceID),
+        BLE_ERROR_NONE
+    };
+    callback.call(&context);
+    return BLE_ERROR_NONE;
+}
+
+/**************************************************************************/
+/*!
+    @brief  Purge the BLE stack of GATT and GAP state.
+
+    @returns    ble_error_t
+
+    @retval     BLE_ERROR_NONE
+                Everything executed properly
+
+    @note  When using S110, GattClient::shutdown() will not be called
+           since Gatt client features are not supported.
+*/
+/**************************************************************************/
+ble_error_t nRF5xn::shutdown(void)
+{
+    if (!initialized) {
+        return BLE_ERROR_INITIALIZATION_INCOMPLETE;
+    }
+
+    /*
+     * Shutdown the SoftDevice first. This is because we need to disable all
+     * interrupts. Otherwise if we clear the BLE API and glue code first there
+     * will be many NULL references and no config information which could lead
+     * to errors if the shutdown process is interrupted.
+     */
+    if (softdevice_handler_sd_disable() != NRF_SUCCESS) {
+        return BLE_STACK_BUSY;
+    }
+
+
+    /* Shutdown the BLE API and nRF51 glue code */
+    ble_error_t error;
+
+    if (gattServerInstance != NULL) {
+        error = gattServerInstance->reset();
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    }
+
+    if (securityManagerInstance != NULL) {
+        error = securityManagerInstance->reset();
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    }
+
+    /* S110 does not support BLE client features, nothing to reset. */
+#if !defined(TARGET_MCU_NRF51_16K_S110) && !defined(TARGET_MCU_NRF51_32K_S110)
+    if (gattClientInstance != NULL) {
+        error = gattClientInstance->reset();
+        if (error != BLE_ERROR_NONE) {
+            return error;
+        }
+    }
+#endif
+
+    /* Gap instance is always present */
+    error = gapInstance.reset();
+    if (error != BLE_ERROR_NONE) {
+        return error;
+    }
+
+    custom_reset_128bits_uuid_table();
+
+    initialized = false;
+    return BLE_ERROR_NONE;
+}
+
+void
+nRF5xn::waitForEvent(void)
+{
+    processEvents();
+    sd_app_evt_wait();
+}
+
+void nRF5xn::processEvents() {
+    if (isEventsSignaled) {
+        isEventsSignaled = false;
+        intern_softdevice_events_execute();
+    }
+}
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h
new file mode 100644
index 0000000000..33c7926e0d
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/nRF5xn.h
@@ -0,0 +1,184 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef __NRF51822_H__
+#define __NRF51822_H__
+
+#include "ble/BLE.h"
+#include "ble/blecommon.h"
+#include "ble/BLEInstanceBase.h"
+
+#include "nRF5xGap.h"
+#include "nRF5xGattServer.h"
+#include "nRF5xGattClient.h"
+#include "nRF5xSecurityManager.h"
+
+#include "btle.h"
+
+class nRF5xn : public BLEInstanceBase
+{
+public:
+    nRF5xn(void);
+    virtual ~nRF5xn(void);
+
+    virtual ble_error_t init(BLE::InstanceID_t instanceID, FunctionPointerWithContext<BLE::InitializationCompleteCallbackContext *> callback);
+    virtual bool        hasInitialized(void) const {
+        return initialized;
+    }
+    virtual ble_error_t shutdown(void);
+    virtual const char *getVersion(void);
+
+    /**
+     * Accessors to GAP. This function checks whether gapInstance points to an
+     * object. If if does not, then the gapInstance is updated to
+     * &_getInstance before returning.
+     *
+     * @return  A reference to GattServer.
+     *
+     * @note  Unlike the GattClient, GattServer and SecurityManager, Gap is
+     *        always needed in a BLE application. Therefore it is allocated
+     *        statically.
+     */
+    virtual Gap &getGap() {
+        return gapInstance;
+    };
+
+    /**
+     * Accessors to GATT Server. This function checks whether a GattServer
+     * object was previously instantiated. If such object does not exist, then
+     * it is created before returning.
+     *
+     * @return  A reference to GattServer.
+     */
+    virtual GattServer &getGattServer() {
+        if (gattServerInstance == NULL) {
+            gattServerInstance = new nRF5xGattServer();
+        }
+        return *gattServerInstance;
+    };
+
+    /**
+     * Accessors to GATT Client. This function checks whether a GattClient
+     * object was previously instantiated. If such object does not exist, then
+     * it is created before returning.
+     *
+     * @return  A reference to GattClient.
+     */
+    virtual nRF5xGattClient &getGattClient() {
+        if (gattClientInstance == NULL) {
+            gattClientInstance = new nRF5xGattClient();
+        }
+        return *gattClientInstance;
+    }
+
+    /**
+     * Accessors to Security Manager. This function checks whether a SecurityManager
+     * object was previously instantiated. If such object does not exist, then
+     * it is created before returning.
+     *
+     * @return  A reference to GattServer.
+     */
+    virtual nRF5xSecurityManager &getSecurityManager() {
+        if (securityManagerInstance == NULL) {
+            securityManagerInstance = new nRF5xSecurityManager();
+        }
+        return *securityManagerInstance;
+    }
+
+    /**
+     * Accessors to GAP. This function checks whether gapInstance points to an
+     * object. If if does not, then the gapInstance is updated to
+     * &_getInstance before returning.
+     *
+     * @return  A const reference to GattServer.
+     *
+     * @note  Unlike the GattClient, GattServer and SecurityManager, Gap is
+     *        always needed in a BLE application. Therefore it is allocated
+     *        statically.
+     *
+     * @note  The accessor is able to modify the object's state because the
+     *        internal pointer has been declared mutable.
+     */
+    virtual const nRF5xGap &getGap() const  {
+        return gapInstance;
+    };
+
+    /**
+     * Accessors to GATT Server. This function checks whether a GattServer
+     * object was previously instantiated. If such object does not exist, then
+     * it is created before returning.
+     *
+     * @return  A const reference to GattServer.
+     *
+     * @note  The accessor is able to modify the object's state because the
+     *        internal pointer has been declared mutable.
+     */
+    virtual const nRF5xGattServer &getGattServer() const {
+        if (gattServerInstance == NULL) {
+            gattServerInstance = new nRF5xGattServer();
+        }
+        return *gattServerInstance;
+    };
+
+    /**
+     * Accessors to Security Manager. This function checks whether a SecurityManager
+     * object was previously instantiated. If such object does not exist, then
+     * it is created before returning.
+     *
+     * @return  A const reference to GattServer.
+     *
+     * @note  The accessor is able to modify the object's state because the
+     *        internal pointer has been declared mutable.
+     */
+    virtual const nRF5xSecurityManager &getSecurityManager() const {
+        if (securityManagerInstance == NULL) {
+            securityManagerInstance = new nRF5xSecurityManager();
+        }
+        return *securityManagerInstance;
+    }
+
+    virtual void waitForEvent(void);
+
+    virtual void processEvents();
+
+public:
+    static nRF5xn& Instance(BLE::InstanceID_t instanceId);
+
+private:
+    bool              initialized;
+    BLE::InstanceID_t instanceID;
+
+private:
+    mutable nRF5xGap gapInstance; /**< Gap instance whose reference is returned from a call to
+                                   * getGap(). Unlike the GattClient, GattServer and
+                                   * SecurityManager, Gap is always needed in a BLE application. */
+
+private:
+    mutable nRF5xGattServer      *gattServerInstance;      /**< Pointer to the GattServer object instance.
+                                                            *   If NULL, then GattServer has not been initialized.
+                                                            *   The pointer has been declared as 'mutable' so that
+                                                            *   it can be assigned inside a 'const' function. */
+    mutable nRF5xGattClient      *gattClientInstance;      /**< Pointer to the GattClient object instance.
+                                                            *   If NULL, then GattClient has not been initialized.
+                                                            *   The pointer has been declared as 'mutable' so that
+                                                            *   it can be assigned inside a 'const' function. */
+    mutable nRF5xSecurityManager *securityManagerInstance; /**< Pointer to the SecurityManager object instance.
+                                                            *   If NULL, then SecurityManager has not been initialized.
+                                                            *   The pointer has been declared as 'mutable' so that
+                                                            *   it can be assigned inside a 'const' function. */
+};
+
+#endif
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/projectconfig.h b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/projectconfig.h
new file mode 100644
index 0000000000..15959850c4
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/projectconfig.h
@@ -0,0 +1,136 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef _PROJECTCONFIG_H_
+#define _PROJECTCONFIG_H_
+
+#include "ble/GapAdvertisingData.h"
+
+/*=========================================================================
+    MCU & BOARD SELCTION
+
+    CFG_BOARD is one of the value defined in board.h
+    -----------------------------------------------------------------------*/
+    #define CFG_BOARD                                  BOARD_PCA10001
+    #define CFG_MCU_STRING                             "nRF51822"
+/*=========================================================================*/
+
+
+/*=========================================================================
+    CODE BASE VERSION SETTINGS
+
+    Please do not modify this version number.  To set a version number
+    for your project or firmware, change the values in your 'boards/'
+    config file.
+    -----------------------------------------------------------------------*/
+    #define CFG_CODEBASE_VERSION_MAJOR                 0
+    #define CFG_CODEBASE_VERSION_MINOR                 1
+    #define CFG_CODEBASE_VERSION_REVISION              0
+/*=========================================================================*/
+
+
+/*=========================================================================
+    FIRMWARE VERSION SETTINGS
+    -----------------------------------------------------------------------*/
+    #define CFG_FIRMWARE_VERSION_MAJOR                 0
+    #define CFG_FIRMWARE_VERSION_MINOR                 0
+    #define CFG_FIRMWARE_VERSION_REVISION              0
+/*=========================================================================*/
+
+
+/*=========================================================================
+    DEBUG LEVEL
+    -----------------------------------------------------------------------
+
+    CFG_DEBUG                 Level 3: Full debug output, any failed assert
+                                       will produce a breakpoint for the
+                                       debugger
+                              Level 2: ATTR_ALWAYS_INLINE is null, ASSERT
+                                       has text
+                              Level 1: ATTR_ALWAYS_INLINE is an attribute,
+                                       ASSERT has no text
+                              Level 0: No debug information generated
+
+    -----------------------------------------------------------------------*/
+    #define CFG_DEBUG                                  (1)
+
+    #if (CFG_DEBUG > 3) || (CFG_DEBUG < 0)
+      #error "CFG_DEBUG must be a value between 0 (no debug) and 3"
+    #endif
+/*=========================================================================*/
+
+
+/*=========================================================================
+    GENERAL NRF51 PERIPHERAL SETTINGS
+    -----------------------------------------------------------------------
+
+    CFG_SCHEDULER_ENABLE      Set this to 'true' or 'false' depending on
+                              if you use the event scheduler or not
+
+    -----------------------------------------------------------------------*/
+    #define CFG_SCHEDULER_ENABLE                       false
+
+    /*------------------------------- GPIOTE ------------------------------*/
+    #define CFG_GPIOTE_MAX_USERS                       1                        /**< Maximum number of users of the GPIOTE handler. */
+
+    /*-------------------------------- TIMER ------------------------------*/
+    #define CFG_TIMER_PRESCALER                        0                        /**< Value of the RTC1 PRESCALER register. freq = (32768/(PRESCALER+1)) */
+    #define CFG_TIMER_MAX_INSTANCE                     1                        /**< Maximum number of simultaneously created timers. */
+    #define CFG_TIMER_OPERATION_QUEUE_SIZE             2                        /**< Size of timer operation queues. */
+/*=========================================================================*/
+
+
+/*=========================================================================
+    BTLE SETTINGS
+    -----------------------------------------------------------------------*/
+
+    #define CFG_BLE_TX_POWER_LEVEL                     0                        /**< in dBm (Valid values are -40, -20, -16, -12, -8, -4, 0, 4) */
+
+    /*---------------------------- BOND MANAGER ---------------------------*/
+    #define CFG_BLE_BOND_FLASH_PAGE_BOND               (BLE_FLASH_PAGE_END-1)   /**< Flash page used for bond manager bonding information.*/
+    #define CFG_BLE_BOND_FLASH_PAGE_SYS_ATTR           (BLE_FLASH_PAGE_END-3)   /**< Flash page used for bond manager system attribute information. TODO check if we can use BLE_FLASH_PAGE_END-2*/
+    #define CFG_BLE_BOND_DELETE_BUTTON_NUM             0                        /**< Button to press to delete bond details during init */
+
+    /*------------------------------ SECURITY -----------------------------*/
+    #define CFG_BLE_SEC_PARAM_MITM                     0                        /**< Man In The Middle protection not required. */
+    #define CFG_BLE_SEC_PARAM_IO_CAPABILITIES          BLE_GAP_IO_CAPS_NONE     /**< No I/O capabilities. */
+    #define CFG_BLE_SEC_PARAM_OOB                      0                        /**< Out Of Band data not available. */
+    #define CFG_BLE_SEC_PARAM_MIN_KEY_SIZE             7                        /**< Minimum encryption key size. */
+    #define CFG_BLE_SEC_PARAM_MAX_KEY_SIZE             16
+
+    /*--------------------------------- GAP -------------------------------*/
+    #define CFG_GAP_APPEARANCE                         GapAdvertisingData::GENERIC_TAG
+    #define CFG_GAP_LOCAL_NAME                         "nRF5x"
+
+    #define CFG_GAP_CONNECTION_MIN_INTERVAL_MS           50                     /**< Minimum acceptable connection interval */
+    #define CFG_GAP_CONNECTION_MAX_INTERVAL_MS          500                     /**< Maximum acceptable connection interval */
+    #define CFG_GAP_CONNECTION_SUPERVISION_TIMEOUT_MS  4000                     /**< Connection supervisory timeout */
+    #define CFG_GAP_CONNECTION_SLAVE_LATENCY           0                        /**< Slave Latency in number of connection events. */
+
+    #define CFG_GAP_ADV_INTERVAL_MS                    25                       /**< The advertising interval in miliseconds, should be multiply of 0.625 */
+    #define CFG_GAP_ADV_TIMEOUT_S                      180                      /**< The advertising timeout in units of seconds. */
+/*=========================================================================*/
+
+
+/*=========================================================================
+    VALIDATION
+    -----------------------------------------------------------------------*/
+    #if CFG_BLE_TX_POWER_LEVEL != -40 && CFG_BLE_TX_POWER_LEVEL != -20 && CFG_BLE_TX_POWER_LEVEL != -16 && CFG_BLE_TX_POWER_LEVEL != -12 && CFG_BLE_TX_POWER_LEVEL != -8  && CFG_BLE_TX_POWER_LEVEL != -4  && CFG_BLE_TX_POWER_LEVEL != 0   && CFG_BLE_TX_POWER_LEVEL != 4
+        #error "CFG_BLE_TX_POWER_LEVEL must be -40, -20, -16, -12, -8, -4, 0 or 4"
+    #endif
+/*=========================================================================*/
+
+#endif /* _PROJECTCONFIG_H_ */
diff --git a/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/supress-warnings.cmake b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/supress-warnings.cmake
new file mode 100644
index 0000000000..60061399da
--- /dev/null
+++ b/features/FEATURE_BLE/targets/TARGET_NORDIC/TARGET_NRF5/source/supress-warnings.cmake
@@ -0,0 +1,21 @@
+# Copyright 2015 ARM Limited
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#     http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+
+message("suppressing warnings from ble-nrf51822")
+
+if(CMAKE_C_COMPILER_ID STREQUAL "GNU")
+    set_target_properties(ble-nrf51822
+        PROPERTIES COMPILE_FLAGS "-Wno-sign-compare -Wno-unused-variable -Wno-unused-parameter -Wno-unused-function -Wno-missing-field-initializers"
+    )
+endif()
diff --git a/hal/targets.json b/hal/targets.json
index f7ba2eae69..30b1f250ed 100644
--- a/hal/targets.json
+++ b/hal/targets.json
@@ -1456,7 +1456,7 @@
         "extra_labels_add": ["DELTA_DFCM_NNN40"],
         "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
     },
-    "NRF51_DK": {
+    "NRF51_DK_LEGACY": {
         "supported_form_factors": ["ARDUINO"],
         "inherits": ["MCU_NRF51_32K"],
         "progen": {"target": "nrf51-dk"},
@@ -1837,6 +1837,119 @@
         "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
         "default_build": "standard"
     },
+    "MCU_NRF51_UNIFIED": {
+        "inherits": ["Target"],
+        "core": "Cortex-M0",
+        "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
+        "macros": [
+            "NRF51",
+            "TARGET_NRF51822",
+            "BLE_STACK_SUPPORT_REQD",
+            "SOFTDEVICE_PRESENT",
+            "S130",
+            "TARGET_MCU_NRF51822"
+        ],
+        "MERGE_BOOTLOADER": false,
+        "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
+        "public": false,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "",
+                "name": "s130_nrf51_2.0.0_softdevice.hex",
+                "offset": 110592
+            }
+        ],
+        "detect_code": ["1070"],
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "program_cycle_s": 6,
+        "default_build": "small",
+        "features": ["BLE"],
+        "config":{
+            "lf_clock_src": {
+                "value": "NRF_LF_SRC_XTAL",
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+            }
+        }
+    },
+    "MCU_NRF51_32K_UNIFIED": {
+        "inherits": ["MCU_NRF51_UNIFIED"],
+        "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
+        "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
+        "public": false
+    },
+    "NRF51_DK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF51_32K_UNIFIED"],
+        "progen": {"target": "nrf51-dk"},
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
+    },
+    "MCU_NRF52": {
+        "inherits": ["Target"],
+        "core": "Cortex-M4F",
+        "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"],
+        "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"],
+        "OUTPUT_EXT": "hex",
+        "is_disk_virtual": true,
+        "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
+        "public": false,
+        "detect_code": ["1101"],
+        "program_cycle_s": 6,
+        "MERGE_SOFT_DEVICE": true,
+        "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
+            {
+                "boot": "",
+                "name": "s132_nrf52_2.0.0_softdevice.hex",
+                "offset": 114688
+            }
+        ],
+        "post_binary_hook": {
+            "function": "MCU_NRF51Code.binary_hook",
+            "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
+        },
+        "MERGE_BOOTLOADER": false,
+        "features": ["BLE"],
+        "config":{
+            "lf_clock_src": {
+                "value": "NRF_LF_SRC_XTAL",
+                "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
+            }
+        },
+        "default_build": "small"
+    },
+    "NRF52_DK": {
+        "supported_form_factors": ["ARDUINO"],
+        "inherits": ["MCU_NRF52"],
+        "progen": {"target": "nrf52-dk"},
+        "macros_add": [
+            "BOARD_PCA10040",
+            "NRF52_PAN_12",
+            "NRF52_PAN_15",
+            "NRF52_PAN_58",
+            "NRF52_PAN_55",
+            "NRF52_PAN_54",
+            "NRF52_PAN_31",
+            "NRF52_PAN_30",
+            "NRF52_PAN_51",
+            "NRF52_PAN_36",
+            "NRF52_PAN_53",
+            "S132",
+            "CONFIG_GPIO_AS_PINRESET",
+            "BLE_STACK_SUPPORT_REQD",
+            "SWI_DISABLE0",
+            "NRF52_PAN_20",
+            "NRF52_PAN_64",
+            "NRF52_PAN_62",
+            "NRF52_PAN_63"
+        ],
+        "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"]
+    },
     "BLUEPILL_F103C8": {
         "core": "Cortex-M3",
         "default_toolchain": "GCC_ARM",
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S
new file mode 100644
index 0000000000..f57ccfe64b
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_16K/startup_nRF51822.S
@@ -0,0 +1,187 @@
+; mbed Microcontroller Library
+; Copyright (c) 2013 Nordic Semiconductor.
+;Licensed under the Apache License, Version 2.0 (the "License");
+;you may not use this file except in compliance with the License.
+;You may obtain a copy of the License at
+;http://www.apache.org/licenses/LICENSE-2.0
+;Unless required by applicable law or agreed to in writing, software
+;distributed under the License is distributed on an "AS IS" BASIS,
+;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;See the License for the specific language governing permissions and
+;limitations under the License.
+
+; Description message
+
+__initial_sp	EQU     0x20004000
+
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+                DCD      RADIO_IRQHandler ;RADIO
+                DCD      UART0_IRQHandler ;UART0
+                DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+                DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+                DCD      0 ;Reserved
+                DCD      GPIOTE_IRQHandler ;GPIOTE
+                DCD      ADC_IRQHandler ;ADC
+                DCD      TIMER0_IRQHandler ;TIMER0
+                DCD      TIMER1_IRQHandler ;TIMER1
+                DCD      TIMER2_IRQHandler ;TIMER2
+                DCD      RTC0_IRQHandler ;RTC0
+                DCD      TEMP_IRQHandler ;TEMP
+                DCD      RNG_IRQHandler ;RNG
+                DCD      ECB_IRQHandler ;ECB
+                DCD      CCM_AAR_IRQHandler ;CCM_AAR
+                DCD      WDT_IRQHandler ;WDT
+                DCD      RTC1_IRQHandler ;RTC1
+                DCD      QDEC_IRQHandler ;QDEC
+                DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+                DCD      SWI0_IRQHandler ;SWI0
+                DCD      SWI1_IRQHandler ;SWI1
+                DCD      SWI2_IRQHandler ;SWI2
+                DCD      SWI3_IRQHandler ;SWI3
+                DCD      SWI4_IRQHandler ;SWI4
+                DCD      SWI5_IRQHandler ;SWI5
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+NRF_POWER_RAMON_ADDRESS           EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk EQU   0xF         ; All RAM blocks on in onmode bit mask
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit				
+                IMPORT  __main
+                LDR     R0, =NRF_POWER_RAMON_ADDRESS
+                LDR     R2, [R0]
+                MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+                ORRS    R2, R2, R1
+                STR     R2, [R0]
+                LDR     R0, =SystemInit               
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   POWER_CLOCK_IRQHandler [WEAK]
+                EXPORT   RADIO_IRQHandler [WEAK]
+                EXPORT   UART0_IRQHandler [WEAK]
+                EXPORT   SPI0_TWI0_IRQHandler [WEAK]
+                EXPORT   SPI1_TWI1_IRQHandler [WEAK]
+                EXPORT   GPIOTE_IRQHandler [WEAK]
+                EXPORT   ADC_IRQHandler [WEAK]
+                EXPORT   TIMER0_IRQHandler [WEAK]
+                EXPORT   TIMER1_IRQHandler [WEAK]
+                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   RTC0_IRQHandler [WEAK]
+                EXPORT   TEMP_IRQHandler [WEAK]
+                EXPORT   RNG_IRQHandler [WEAK]
+                EXPORT   ECB_IRQHandler [WEAK]
+                EXPORT   CCM_AAR_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler [WEAK]
+                EXPORT   RTC1_IRQHandler [WEAK]
+                EXPORT   QDEC_IRQHandler [WEAK]
+                EXPORT   LPCOMP_COMP_IRQHandler [WEAK]
+                EXPORT   SWI0_IRQHandler [WEAK]
+                EXPORT   SWI1_IRQHandler [WEAK]
+                EXPORT   SWI2_IRQHandler [WEAK]
+                EXPORT   SWI3_IRQHandler [WEAK]
+                EXPORT   SWI4_IRQHandler [WEAK]
+                EXPORT   SWI5_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UART0_IRQHandler
+SPI0_TWI0_IRQHandler
+SPI1_TWI1_IRQHandler
+GPIOTE_IRQHandler
+ADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+LPCOMP_COMP_IRQHandler
+SWI0_IRQHandler
+SWI1_IRQHandler
+SWI2_IRQHandler
+SWI3_IRQHandler
+SWI4_IRQHandler
+SWI5_IRQHandler
+
+                B .
+                ENDP
+                ALIGN
+                END
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
new file mode 100644
index 0000000000..6396fd84fe
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/nRF51822.sct
@@ -0,0 +1,24 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000  {
+;  ER_IROM1 0x00000000 0x00040000  {
+;   *.o (RESET, +First)
+;   *(InRoot$$Sections)
+;   .ANY (+RO)
+;  }
+;  RW_IRAM1 0x20000000 0x00008000  {
+;   .ANY (+RW +ZI)
+;  }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x0001B000 0x0025000  {
+  ER_IROM1 0x0001B000 0x0025000  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20002ef8 0x5108  {
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S
new file mode 100644
index 0000000000..ea211543df
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NORDIC_32K/startup_nRF51822.S
@@ -0,0 +1,196 @@
+; mbed Microcontroller Library
+; Copyright (c) 2013 Nordic Semiconductor.
+;Licensed under the Apache License, Version 2.0 (the "License");
+;you may not use this file except in compliance with the License.
+;You may obtain a copy of the License at
+;http://www.apache.org/licenses/LICENSE-2.0
+;Unless required by applicable law or agreed to in writing, software
+;distributed under the License is distributed on an "AS IS" BASIS,
+;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+;See the License for the specific language governing permissions and
+;limitations under the License.
+
+; Description message
+
+__initial_sp	EQU     0x20008000
+
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler             ; Reset Handler
+                DCD     NMI_Handler               ; NMI Handler
+                DCD     HardFault_Handler         ; Hard Fault Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler               ; SVCall Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler            ; PendSV Handler
+                DCD     SysTick_Handler           ; SysTick Handler
+
+                ; External Interrupts
+                DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+                DCD      RADIO_IRQHandler ;RADIO
+                DCD      UART0_IRQHandler ;UART0
+                DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+                DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+                DCD      0 ;Reserved
+                DCD      GPIOTE_IRQHandler ;GPIOTE
+                DCD      ADC_IRQHandler ;ADC
+                DCD      TIMER0_IRQHandler ;TIMER0
+                DCD      TIMER1_IRQHandler ;TIMER1
+                DCD      TIMER2_IRQHandler ;TIMER2
+                DCD      RTC0_IRQHandler ;RTC0
+                DCD      TEMP_IRQHandler ;TEMP
+                DCD      RNG_IRQHandler ;RNG
+                DCD      ECB_IRQHandler ;ECB
+                DCD      CCM_AAR_IRQHandler ;CCM_AAR
+                DCD      WDT_IRQHandler ;WDT
+                DCD      RTC1_IRQHandler ;RTC1
+                DCD      QDEC_IRQHandler ;QDEC
+                DCD      LPCOMP_IRQHandler ;LPCOMP
+                DCD      SWI0_IRQHandler ;SWI0
+                DCD      SWI1_IRQHandler ;SWI1
+                DCD      SWI2_IRQHandler ;SWI2
+                DCD      SWI3_IRQHandler ;SWI3
+                DCD      SWI4_IRQHandler ;SWI4
+                DCD      SWI5_IRQHandler ;SWI5
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+                DCD      0 ;Reserved
+
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+NRF_POWER_RAMON_ADDRESS            EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMONB_ADDRESS           EQU   0x40000554  ; NRF_POWER->RAMONB address
+NRF_POWER_RAMONx_RAMxON_ONMODE_Msk EQU   0x3         ; All RAM blocks on in onmode bit mask
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                
+                MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+                
+                LDR     R0, =NRF_POWER_RAMON_ADDRESS
+                LDR     R2, [R0]
+                ORRS    R2, R2, R1
+                STR     R2, [R0]
+                
+                LDR     R0, =NRF_POWER_RAMONB_ADDRESS
+                LDR     R2, [R0]
+                ORRS    R2, R2, R1
+                STR     R2, [R0]
+                
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   POWER_CLOCK_IRQHandler [WEAK]
+                EXPORT   RADIO_IRQHandler [WEAK]
+                EXPORT   UART0_IRQHandler [WEAK]
+                EXPORT   SPI0_TWI0_IRQHandler [WEAK]
+                EXPORT   SPI1_TWI1_IRQHandler [WEAK]
+                EXPORT   GPIOTE_IRQHandler [WEAK]
+                EXPORT   ADC_IRQHandler [WEAK]
+                EXPORT   TIMER0_IRQHandler [WEAK]
+                EXPORT   TIMER1_IRQHandler [WEAK]
+                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   RTC0_IRQHandler [WEAK]
+                EXPORT   TEMP_IRQHandler [WEAK]
+                EXPORT   RNG_IRQHandler [WEAK]
+                EXPORT   ECB_IRQHandler [WEAK]
+                EXPORT   CCM_AAR_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler [WEAK]
+                EXPORT   RTC1_IRQHandler [WEAK]
+                EXPORT   QDEC_IRQHandler [WEAK]
+                EXPORT   LPCOMP_IRQHandler [WEAK]
+                EXPORT   SWI0_IRQHandler [WEAK]
+                EXPORT   SWI1_IRQHandler [WEAK]
+                EXPORT   SWI2_IRQHandler [WEAK]
+                EXPORT   SWI3_IRQHandler [WEAK]
+                EXPORT   SWI4_IRQHandler [WEAK]
+                EXPORT   SWI5_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UART0_IRQHandler
+SPI0_TWI0_IRQHandler
+SPI1_TWI1_IRQHandler
+GPIOTE_IRQHandler
+ADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+LPCOMP_IRQHandler
+SWI0_IRQHandler
+SWI1_IRQHandler
+SWI2_IRQHandler
+SWI3_IRQHandler
+SWI4_IRQHandler
+SWI5_IRQHandler
+
+                B .
+                ENDP
+                ALIGN
+                END
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
new file mode 100644
index 0000000000..94e85ccb7b
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S110/nRF51822.sct
@@ -0,0 +1,24 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000  {
+;  ER_IROM1 0x00000000 0x00040000  {
+;   *.o (RESET, +First)
+;   *(InRoot$$Sections)
+;   .ANY (+RO)
+;  }
+;  RW_IRAM1 0x20000000 0x00004000  {
+;   .ANY (+RW +ZI)
+;  }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x0001B000 0x0025000  {
+  ER_IROM1 0x0001B000 0x0025000  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20002ef8 0x1108  {
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
new file mode 100644
index 0000000000..94e85ccb7b
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/TARGET_MCU_NRF51_16K_S130/nRF51822.sct
@@ -0,0 +1,24 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000  {
+;  ER_IROM1 0x00000000 0x00040000  {
+;   *.o (RESET, +First)
+;   *(InRoot$$Sections)
+;   .ANY (+RO)
+;  }
+;  RW_IRAM1 0x20000000 0x00004000  {
+;   .ANY (+RW +ZI)
+;  }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x0001B000 0x0025000  {
+  ER_IROM1 0x0001B000 0x0025000  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20002ef8 0x1108  {
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/sys.cpp b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
new file mode 100644
index 0000000000..d2b7bcfa9f
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NORDIC_32K/NRF51822.ld
@@ -0,0 +1,162 @@
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0001B000, LENGTH = 0x25000
+  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0x5108
+}
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.Vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.jcr)
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+    __edata = .;
+
+    .fs_data :
+    {
+      PROVIDE(__start_fs_data = .);
+      KEEP(*(.fs_data))
+      PROVIDE(__stop_fs_data = .);
+    } > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (NOLOAD):
+	{
+		__end__ = .;
+		end = __end__;
+		__HeapBase = .;
+		*(.heap*)
+		. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (NOLOAD):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld
new file mode 100644
index 0000000000..d0ed81d84e
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S110/NRF51822.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x00018000, LENGTH = 0x28000
+  RAM (rwx) :  ORIGIN = 0x20002000, LENGTH = 0x2000
+}
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.Vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.jcr)
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (NOLOAD):
+	{
+		__end__ = .;
+		end = __end__;
+		__HeapBase = .;
+		*(.heap*)
+		. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (NOLOAD):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld
new file mode 100644
index 0000000000..237ab15985
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/TARGET_MCU_NRF51_16K_S130/NRF51822.ld
@@ -0,0 +1,153 @@
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x0001C000, LENGTH = 0x24000
+  RAM (rwx) :  ORIGIN = 0x20002800, LENGTH = 0x1800
+}
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with other linker script that defines memory regions FLASH and RAM.
+ * It references following symbols, which must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines following symbols, which code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+SECTIONS
+{
+	.text :
+	{
+		KEEP(*(.Vectors))
+		*(.text*)
+
+		KEEP(*(.init))
+		KEEP(*(.fini))
+
+		/* .ctors */
+		*crtbegin.o(.ctors)
+		*crtbegin?.o(.ctors)
+		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+		*(SORT(.ctors.*))
+		*(.ctors)
+
+		/* .dtors */
+ 		*crtbegin.o(.dtors)
+ 		*crtbegin?.o(.dtors)
+ 		*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+ 		*(SORT(.dtors.*))
+ 		*(.dtors)
+
+		*(.rodata*)
+
+		KEEP(*(.eh_frame*))
+	} > FLASH
+
+
+	.ARM.extab :
+	{
+		*(.ARM.extab* .gnu.linkonce.armextab.*)
+	} > FLASH
+
+	__exidx_start = .;
+	.ARM.exidx :
+	{
+		*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+	} > FLASH
+	__exidx_end = .;
+
+	__etext = .;
+
+	.data : AT (__etext)
+	{
+		__data_start__ = .;
+		*(vtable)
+		*(.data*)
+
+		. = ALIGN(4);
+		/* preinit data */
+		PROVIDE_HIDDEN (__preinit_array_start = .);
+		KEEP(*(.preinit_array))
+		PROVIDE_HIDDEN (__preinit_array_end = .);
+
+		. = ALIGN(4);
+		/* init data */
+		PROVIDE_HIDDEN (__init_array_start = .);
+		KEEP(*(SORT(.init_array.*)))
+		KEEP(*(.init_array))
+		PROVIDE_HIDDEN (__init_array_end = .);
+
+
+		. = ALIGN(4);
+		/* finit data */
+		PROVIDE_HIDDEN (__fini_array_start = .);
+		KEEP(*(SORT(.fini_array.*)))
+		KEEP(*(.fini_array))
+		PROVIDE_HIDDEN (__fini_array_end = .);
+
+		*(.jcr)
+		. = ALIGN(4);
+		/* All data end */
+		__data_end__ = .;
+
+	} > RAM
+
+	.bss :
+	{
+		. = ALIGN(4);
+		__bss_start__ = .;
+		*(.bss*)
+		*(COMMON)
+		. = ALIGN(4);
+		__bss_end__ = .;
+	} > RAM
+
+	.heap (NOLOAD):
+	{
+		__end__ = .;
+		end = __end__;
+		__HeapBase = .;
+		*(.heap*)
+		. = ORIGIN(RAM) + LENGTH(RAM) - Stack_Size;
+		__HeapLimit = .;
+	} > RAM
+
+	/* .stack_dummy section doesn't contains any symbols. It is only
+	 * used for linker to calculate size of stack sections, and assign
+	 * values to stack symbols later */
+	.stack_dummy (NOLOAD):
+	{
+		*(.stack*)
+	} > RAM
+
+	/* Set stack top to end of RAM, and stack limit move down by
+	 * size of stack_dummy section */
+	__StackTop = ORIGIN(RAM) + LENGTH(RAM);
+	__StackLimit = __StackTop - SIZEOF(.stack_dummy);
+	PROVIDE(__stack = __StackTop);
+
+	/* Check if data + heap + stack exceeds RAM limit */
+	ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/startup_NRF51822.S b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
new file mode 100644
index 0000000000..03f6daaf53
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_GCC_ARM/startup_NRF51822.S
@@ -0,0 +1,264 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+    .syntax unified
+    .arch armv6-m
+
+    .section .stack
+    .align 3
+#ifdef __STACK_SIZE
+    .equ    Stack_Size, __STACK_SIZE
+#else
+    .equ    Stack_Size, 2048
+#endif
+    .globl    Stack_Size
+    .globl    __StackTop
+    .globl    __StackLimit
+__StackLimit:
+    .space    Stack_Size
+    .size __StackLimit, . - __StackLimit
+__StackTop:
+    .size __StackTop, . - __StackTop
+
+    .section .heap
+    .align 3
+    .globl    __HeapBase
+    .globl    __HeapLimit
+
+    .section .Vectors
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long    __StackTop            /* Top of Stack */
+    .long   Reset_Handler               /* Reset Handler */
+    .long   NMI_Handler                 /* NMI Handler */
+    .long   HardFault_Handler           /* Hard Fault Handler */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   SVC_Handler                 /* SVCall Handler */
+    .long   0                           /* Reserved */
+    .long   0                           /* Reserved */
+    .long   PendSV_Handler              /* PendSV Handler */
+    .long   SysTick_Handler             /* SysTick Handler */
+
+  /* External Interrupts */
+    .long 	POWER_CLOCK_IRQHandler		 /*POWER_CLOCK */
+    .long 	RADIO_IRQHandler		 /*RADIO */
+    .long 	UART0_IRQHandler		 /*UART0 */
+    .long 	SPI0_TWI0_IRQHandler		 /*SPI0_TWI0 */
+    .long 	SPI1_TWI1_IRQHandler		 /*SPI1_TWI1 */
+    .long 	0		 /*Reserved */
+    .long 	GPIOTE_IRQHandler		 /*GPIOTE */
+    .long 	ADC_IRQHandler		 /*ADC */
+    .long 	TIMER0_IRQHandler		 /*TIMER0 */
+    .long 	TIMER1_IRQHandler		 /*TIMER1 */
+    .long 	TIMER2_IRQHandler		 /*TIMER2 */
+    .long 	RTC0_IRQHandler		 /*RTC0 */
+    .long 	TEMP_IRQHandler		 /*TEMP */
+    .long 	RNG_IRQHandler		 /*RNG */
+    .long 	ECB_IRQHandler		 /*ECB */
+    .long 	CCM_AAR_IRQHandler		 /*CCM_AAR */
+    .long 	WDT_IRQHandler		 /*WDT */
+    .long 	RTC1_IRQHandler		 /*RTC1 */
+    .long 	QDEC_IRQHandler		 /*QDEC */
+    .long 	LPCOMP_IRQHandler		 /*LPCOMP */
+    .long 	SWI0_IRQHandler		 /*SWI0 */
+    .long 	SWI1_IRQHandler		 /*SWI1 */
+    .long 	SWI2_IRQHandler		 /*SWI2 */
+    .long 	SWI3_IRQHandler		 /*SWI3 */
+    .long 	SWI4_IRQHandler		 /*SWI4 */
+    .long 	SWI5_IRQHandler		 /*SWI5 */
+    .long 	0		 /*Reserved */
+    .long 	0		 /*Reserved */
+    .long 	0		 /*Reserved */
+    .long 	0		 /*Reserved */
+    .long 	0		 /*Reserved */
+    .long 	0		 /*Reserved */
+
+
+    .size    __Vectors, . - __Vectors
+
+/* Reset Handler */
+
+    .equ    NRF_POWER_RAMON_ADDRESS,             0x40000524
+    .equ    NRF_POWER_RAMONB_ADDRESS,            0x40000554
+    .equ    NRF_POWER_RAMONx_RAMxON_ONMODE_Msk,  0x3  
+
+    .text
+    .thumb
+    .thumb_func
+    .align 1
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+
+    MOVS    R1, #NRF_POWER_RAMONx_RAMxON_ONMODE_Msk
+    LDR     R0, =NRF_POWER_RAMON_ADDRESS
+    LDR     R2, [R0]
+    ORRS    R2, R1
+    STR     R2, [R0]
+
+    LDR     R0, =NRF_POWER_RAMONB_ADDRESS
+    LDR     R2, [R0]
+    ORRS    R2, R1
+    STR     R2, [R0]
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0, =_start
+    BX      R0
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ  POWER_CLOCK_IRQHandler
+    IRQ  RADIO_IRQHandler
+    IRQ  UART0_IRQHandler
+    IRQ  SPI0_TWI0_IRQHandler
+    IRQ  SPI1_TWI1_IRQHandler
+    IRQ  GPIOTE_IRQHandler
+    IRQ  ADC_IRQHandler
+    IRQ  TIMER0_IRQHandler
+    IRQ  TIMER1_IRQHandler
+    IRQ  TIMER2_IRQHandler
+    IRQ  RTC0_IRQHandler
+    IRQ  TEMP_IRQHandler
+    IRQ  RNG_IRQHandler
+    IRQ  ECB_IRQHandler
+    IRQ  CCM_AAR_IRQHandler
+    IRQ  WDT_IRQHandler
+    IRQ  RTC1_IRQHandler
+    IRQ  QDEC_IRQHandler
+    IRQ  LPCOMP_IRQHandler
+    IRQ  SWI0_IRQHandler
+    IRQ  SWI1_IRQHandler
+    IRQ  SWI2_IRQHandler
+    IRQ  SWI3_IRQHandler
+    IRQ  SWI4_IRQHandler
+    IRQ  SWI5_IRQHandler
+
+
+  .end
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf
new file mode 100644
index 0000000000..e39581e3af
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/nRF51822_QFAA.icf
@@ -0,0 +1,43 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0001b000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0001b0c0;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20003FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x400;
+define symbol __ICFEDIT_size_heap__   = 0x900;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP,
+                        block CSTACK };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S
new file mode 100644
index 0000000000..b1e263009c
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_16K/startup_NRF51822_IAR.S
@@ -0,0 +1,237 @@
+;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
+;; The information contained herein is confidential property of Nordic
+;; Semiconductor ASA.Terms and conditions of usage are described in detail
+;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+;; Licensees are granted free, non-transferable use of the information. NO
+;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+;; the file.
+
+;; Description message
+
+        MODULE  ?cstartup
+
+        ;; Stack size default : 1024
+        ;; Heap size default : 2048
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+;__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+        DCD      RADIO_IRQHandler ;RADIO
+        DCD      UART0_IRQHandler ;UART0
+        DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+        DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+        DCD      0 ;Reserved
+        DCD      GPIOTE_IRQHandler ;GPIOTE
+        DCD      ADC_IRQHandler ;ADC
+        DCD      TIMER0_IRQHandler ;TIMER0
+        DCD      TIMER1_IRQHandler ;TIMER1
+        DCD      TIMER2_IRQHandler ;TIMER2
+        DCD      RTC0_IRQHandler ;RTC0
+        DCD      TEMP_IRQHandler ;TEMP
+        DCD      RNG_IRQHandler ;RNG
+        DCD      ECB_IRQHandler ;ECB
+        DCD      CCM_AAR_IRQHandler ;CCM_AAR
+        DCD      WDT_IRQHandler ;WDT
+        DCD      RTC1_IRQHandler ;RTC1
+        DCD      QDEC_IRQHandler ;QDEC
+        DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+        DCD      SWI0_IRQHandler ;SWI0
+        DCD      SWI1_IRQHandler ;SWI1
+        DCD      SWI2_IRQHandler ;SWI2
+        DCD      SWI3_IRQHandler ;SWI3
+        DCD      SWI4_IRQHandler ;SWI4
+        DCD      SWI5_IRQHandler ;SWI5
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+
+
+__Vectors_End
+__Vectors                           EQU   __vector_table
+__Vectors_Size                      EQU   __Vectors_End - __Vectors
+NRF_POWER_RAMON_ADDRESS             EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk   EQU   0xF         ; All RAM blocks on in onmode bit mask
+
+; Default handlers.
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =NRF_POWER_RAMON_ADDRESS
+        LDR     R2, [R0]
+        MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+        ORRS    R2, R2, R1
+        STR     R2, [R0]
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        ; Dummy exception handlers
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+       ; Dummy interrupt handlers
+
+        PUBWEAK  POWER_CLOCK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+        B .
+        PUBWEAK  RADIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+        B .
+        PUBWEAK  UART0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+        B .
+        PUBWEAK  SPI0_TWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_TWI0_IRQHandler
+        B .
+        PUBWEAK  SPI1_TWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_TWI1_IRQHandler
+        B .
+        PUBWEAK  GPIOTE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+        B .
+        PUBWEAK  ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+        B .
+        PUBWEAK  TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+        B .
+        PUBWEAK  TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+        B .
+        PUBWEAK  TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+        B .
+        PUBWEAK  RTC0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+        B .
+        PUBWEAK  TEMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+        B .
+        PUBWEAK  RNG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+        B .
+        PUBWEAK  ECB_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+        B .
+        PUBWEAK  CCM_AAR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+        B .
+        PUBWEAK  WDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+        B .
+        PUBWEAK  RTC1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+        B .
+        PUBWEAK  QDEC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+        B .
+        PUBWEAK  LPCOMP_COMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPCOMP_COMP_IRQHandler
+        B .
+        PUBWEAK  SWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_IRQHandler
+        B .
+        PUBWEAK  SWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_IRQHandler
+        B .
+        PUBWEAK  SWI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+        B .
+        PUBWEAK  SWI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+        B .
+        PUBWEAK  SWI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+        B .
+        PUBWEAK  SWI5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+        B .
+
+
+        END
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf
new file mode 100644
index 0000000000..c8a1541e55
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/nRF51822_QFAA.icf
@@ -0,0 +1,44 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x0001b000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x0001b0c0;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0003FFFF;
+define symbol __ICFEDIT_region_RAM_start__ = 0x20002ef8;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20007FFF;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__   = 0xc00;
+define symbol __ICFEDIT_size_heap__     = 0x1800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP,
+                        block CSTACK };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S
new file mode 100644
index 0000000000..c0a2b08eab
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TOOLCHAIN_IAR/TARGET_MCU_NORDIC_32K/startup_NRF51822_IAR.S
@@ -0,0 +1,237 @@
+;; Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
+;; The information contained herein is confidential property of Nordic
+;; Semiconductor ASA.Terms and conditions of usage are described in detail
+;; in NORDIC SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+;; Licensees are granted free, non-transferable use of the information. NO
+;; WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+;; the file.
+
+;; Description message
+
+        MODULE  ?cstartup
+
+        ;; Stack size default : 1024
+        ;; Heap size default : 2048
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     0
+        DCD     0
+        DCD     0
+;__vector_table_0x1c
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     0
+        DCD     SVC_Handler
+        DCD     0
+        DCD     0
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD      POWER_CLOCK_IRQHandler ;POWER_CLOCK
+        DCD      RADIO_IRQHandler ;RADIO
+        DCD      UART0_IRQHandler ;UART0
+        DCD      SPI0_TWI0_IRQHandler ;SPI0_TWI0
+        DCD      SPI1_TWI1_IRQHandler ;SPI1_TWI1
+        DCD      0 ;Reserved
+        DCD      GPIOTE_IRQHandler ;GPIOTE
+        DCD      ADC_IRQHandler ;ADC
+        DCD      TIMER0_IRQHandler ;TIMER0
+        DCD      TIMER1_IRQHandler ;TIMER1
+        DCD      TIMER2_IRQHandler ;TIMER2
+        DCD      RTC0_IRQHandler ;RTC0
+        DCD      TEMP_IRQHandler ;TEMP
+        DCD      RNG_IRQHandler ;RNG
+        DCD      ECB_IRQHandler ;ECB
+        DCD      CCM_AAR_IRQHandler ;CCM_AAR
+        DCD      WDT_IRQHandler ;WDT
+        DCD      RTC1_IRQHandler ;RTC1
+        DCD      QDEC_IRQHandler ;QDEC
+        DCD      LPCOMP_COMP_IRQHandler ;LPCOMP_COMP
+        DCD      SWI0_IRQHandler ;SWI0
+        DCD      SWI1_IRQHandler ;SWI1
+        DCD      SWI2_IRQHandler ;SWI2
+        DCD      SWI3_IRQHandler ;SWI3
+        DCD      SWI4_IRQHandler ;SWI4
+        DCD      SWI5_IRQHandler ;SWI5
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+        DCD      0 ;Reserved
+
+
+__Vectors_End
+__Vectors                           EQU   __vector_table
+__Vectors_Size                      EQU   __Vectors_End - __Vectors
+NRF_POWER_RAMON_ADDRESS             EQU   0x40000524  ; NRF_POWER->RAMON address
+NRF_POWER_RAMON_RAMxON_ONMODE_Msk   EQU   0xF         ; All RAM blocks on in onmode bit mask
+
+; Default handlers.
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER:NOROOT(2)
+Reset_Handler
+        LDR     R0, =NRF_POWER_RAMON_ADDRESS
+        LDR     R2, [R0]
+        MOVS    R1, #NRF_POWER_RAMON_RAMxON_ONMODE_Msk
+        ORRS    R2, R2, R1
+        STR     R2, [R0]
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        ; Dummy exception handlers
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SysTick_Handler
+        B .
+
+       ; Dummy interrupt handlers
+
+        PUBWEAK  POWER_CLOCK_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+POWER_CLOCK_IRQHandler
+        B .
+        PUBWEAK  RADIO_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RADIO_IRQHandler
+        B .
+        PUBWEAK  UART0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+UART0_IRQHandler
+        B .
+        PUBWEAK  SPI0_TWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI0_TWI0_IRQHandler
+        B .
+        PUBWEAK  SPI1_TWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SPI1_TWI1_IRQHandler
+        B .
+        PUBWEAK  GPIOTE_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+GPIOTE_IRQHandler
+        B .
+        PUBWEAK  ADC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ADC_IRQHandler
+        B .
+        PUBWEAK  TIMER0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER0_IRQHandler
+        B .
+        PUBWEAK  TIMER1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER1_IRQHandler
+        B .
+        PUBWEAK  TIMER2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TIMER2_IRQHandler
+        B .
+        PUBWEAK  RTC0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC0_IRQHandler
+        B .
+        PUBWEAK  TEMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+TEMP_IRQHandler
+        B .
+        PUBWEAK  RNG_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RNG_IRQHandler
+        B .
+        PUBWEAK  ECB_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+ECB_IRQHandler
+        B .
+        PUBWEAK  CCM_AAR_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+CCM_AAR_IRQHandler
+        B .
+        PUBWEAK  WDT_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+WDT_IRQHandler
+        B .
+        PUBWEAK  RTC1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+RTC1_IRQHandler
+        B .
+        PUBWEAK  QDEC_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+QDEC_IRQHandler
+        B .
+        PUBWEAK  LPCOMP_COMP_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+LPCOMP_COMP_IRQHandler
+        B .
+        PUBWEAK  SWI0_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI0_IRQHandler
+        B .
+        PUBWEAK  SWI1_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI1_IRQHandler
+        B .
+        PUBWEAK  SWI2_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI2_IRQHandler
+        B .
+        PUBWEAK  SWI3_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI3_IRQHandler
+        B .
+        PUBWEAK  SWI4_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI4_IRQHandler
+        B .
+        PUBWEAK  SWI5_IRQHandler
+        SECTION .text:CODE:REORDER:NOROOT(1)
+SWI5_IRQHandler
+        B .
+
+
+        END
\ No newline at end of file
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis.h
new file mode 100644
index 0000000000..b73fdadde8
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis.h
@@ -0,0 +1,13 @@
+/* mbed Microcontroller Library - CMSIS
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * A generic CMSIS include header, pulling in LPC407x_8x specifics
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "nrf.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis_nvic.c b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis_nvic.c
new file mode 100644
index 0000000000..5fe8d89d6f
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis_nvic.c
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+/* In the M0, there is no VTOR. In the LPC range such as the LPC11U,
+ * whilst the vector table may only be something like 48 entries (192 bytes, 0xC0), 
+ * the SYSMEMREMAP register actually remaps the memory from 0x10000000-0x100001FF 
+ * to adress 0x0-0x1FF. In this case, RAM can be addressed at both 0x10000000 and 0x0
+ * 
+ * If we just copy the vectors to RAM and switch the SYSMEMMAP, any accesses to FLASH
+ * above the vector table before 0x200 will actually go to RAM. So we need to provide 
+ * a solution where the compiler gets the right results based on the memory map
+ *
+ * Option 1 - We allocate and copy 0x200 of RAM rather than just the table
+ *  - const data and instructions before 0x200 will be copied to and fetched/exec from RAM
+ *  - RAM overhead: 0x200 - 0xC0 = 320 bytes, FLASH overhead: 0
+ * 
+ * Option 2 - We pad the flash to 0x200 to ensure the compiler doesn't allocate anything there  
+ *  - No flash accesses will go to ram, as there will be nothing there
+ *  - RAM only needs to be allocated for the vectors, as all other ram addresses are normal
+ *  - RAM overhead: 0, FLASH overhead: 320 bytes
+ *
+ * Option 2 is the one to go for, as RAM is the most valuable resource
+ */
+
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Location of vectors in RAM
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)       // Initial vector position in flash
+/*
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    uint32_t i;
+
+    // Copy and switch to dynamic vectors if the first time called
+    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = vectors;
+        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+        for (i=0; i<NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + 16] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    uint32_t *vectors = (uint32_t*)SCB->VTOR;
+    return vectors[IRQn + 16];
+}*/
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
+   // int i;
+    // Space for dynamic vectors, initialised to allocate in R/W
+    static volatile uint32_t* vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
+    /*
+    // Copy and switch to dynamic vectors if first time called
+    if((LPC_SYSCON->SYSMEMREMAP & 0x3) != 0x1) {     
+      uint32_t *old_vectors = (uint32_t *)0;         // FLASH vectors are at 0x0
+      for(i = 0; i < NVIC_NUM_VECTORS; i++) {    
+            vectors[i] = old_vectors[i];
+        }
+        LPC_SYSCON->SYSMEMREMAP = 0x1; // Remaps 0x0-0x1FF FLASH block to RAM block
+    }*/
+
+    // Set the vector 
+    vectors[IRQn + 16] = vector; 
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn) {
+    // We can always read vectors at 0x0, as the addresses are remapped
+    uint32_t *vectors = (uint32_t*)0; 
+
+    // Return the vector
+    return vectors[IRQn + 16];
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis_nvic.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis_nvic.h
new file mode 100644
index 0000000000..ab365b2a79
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/cmsis_nvic.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2011 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS      (16 + 32)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "nrf51.h"
+#include "cmsis.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/system_nrf51.c b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/system_nrf51.c
new file mode 100644
index 0000000000..ead48866be
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/system_nrf51.c
@@ -0,0 +1,171 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/* NOTE: Template files (including this one) are application specific and therefore expected to
+   be copied into the application project folder prior to its use! */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf51.h"
+#include "nrf5x_lf_clk_helper.h"
+
+/*lint ++flb "Enter library region" */
+
+
+#define __SYSTEM_CLOCK      (16000000UL)     /*!< nRF51 devices use a fixed System Clock Frequency of 16MHz */
+
+static bool is_manual_peripheral_setup_needed(void);
+static bool is_disabled_in_debug_needed(void);
+static bool is_peripheral_domain_setup_needed(void);
+
+
+#if defined ( __CC_ARM )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
+#elif defined ( __ICCARM__ )
+    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK;
+#elif defined   ( __GNUC__ )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = __SYSTEM_CLOCK;
+}
+
+void SystemInit(void)
+{
+    /* If desired, switch off the unused RAM to lower consumption by the use of RAMON register.
+       It can also be done in the application main() function. */
+
+    /* Prepare the peripherals for use as indicated by the PAN 26 "System: Manual setup is required
+       to enable the use of peripherals" found at Product Anomaly document for your device found at
+       https://www.nordicsemi.com/. The side effect of executing these instructions in the devices
+       that do not need it is that the new peripherals in the second generation devices (LPCOMP for
+       example) will not be available. */
+    if (is_manual_peripheral_setup_needed())
+    {
+        *(uint32_t volatile *)0x40000504 = 0xC007FFDF;
+        *(uint32_t volatile *)0x40006C18 = 0x00008000;
+    }
+
+    /* Disable PROTENSET registers under debug, as indicated by PAN 59 "MPU: Reset value of DISABLEINDEBUG
+       register is incorrect" found at Product Anomaly document for your device found at
+       https://www.nordicsemi.com/. There is no side effect of using these instruction if not needed. */
+    if (is_disabled_in_debug_needed())
+    {
+        NRF_MPU->DISABLEINDEBUG = MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos;
+    }
+
+    /* Execute the following code to eliminate excessive current in sleep mode with RAM retention in nRF51802 devices,
+       as indicated by PAN 76 "System: Excessive current in sleep mode with retention" found at Product Anomaly document
+       for your device found at https://www.nordicsemi.com/. */
+    if (is_peripheral_domain_setup_needed()){
+        if (*(uint32_t volatile *)0x4006EC00 != 1){
+            *(uint32_t volatile *)0x4006EC00 = 0x9375;
+            while (*(uint32_t volatile *)0x4006EC00 != 1){
+            }
+        }
+        *(uint32_t volatile *)0x4006EC14 = 0xC0;
+    }
+    
+    // Start the LF oscilator according to the mbed configuration (over the nrf5x_lf_clk_helper.h file)
+    NRF_CLOCK->LFCLKSRC             = (CLOCK_LFCLKSRC_SRC_TO_USE << CLOCK_LFCLKSRC_SRC_Pos);
+    NRF_CLOCK->EVENTS_LFCLKSTARTED  = 0;
+    NRF_CLOCK->TASKS_LFCLKSTART     = 1;
+
+    // Wait for the external oscillator to start up.
+    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
+        // Do nothing.
+    }
+}
+
+
+static bool is_manual_peripheral_setup_needed(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x00) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x10) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool is_disabled_in_debug_needed(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool is_peripheral_domain_setup_needed(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x1) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xA0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+        if ((((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0xD0) && (((*(uint32_t *)0xF0000FEC) & 0x000000F0) == 0x0))
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+/*lint --flb "Leave library region" */
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/system_nrf51.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/system_nrf51.h
new file mode 100644
index 0000000000..72398da0d7
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/system_nrf51.h
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SYSTEM_NRF51_H
+#define SYSTEM_NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF51_H */
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/nRF52832.sct b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/nRF52832.sct
new file mode 100644
index 0000000000..70df192ed2
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/nRF52832.sct
@@ -0,0 +1,24 @@
+;WITHOUT SOFTDEVICE:
+;LR_IROM1 0x00000000 0x00040000  {
+;  ER_IROM1 0x00000000 0x00040000  {
+;   *.o (RESET, +First)
+;   *(InRoot$$Sections)
+;   .ANY (+RO)
+;  }
+;  RW_IRAM1 0x20000000 0x00004000  {
+;   .ANY (+RW +ZI)
+;  }
+;}
+;
+;WITH SOFTDEVICE:
+
+LR_IROM1 0x1C000 0x0064000  {
+  ER_IROM1 0x1C000 0x0064000  {
+   *.o (RESET, +First)
+   *(InRoot$$Sections)
+   .ANY (+RO)
+  }
+  RW_IRAM1 0x20002EF8 0x0000D108  {
+   .ANY (+RW +ZI)
+  }
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/startup_nrf52832.s b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/startup_nrf52832.s
new file mode 100644
index 0000000000..dca7388684
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/startup_nrf52832.s
@@ -0,0 +1,443 @@
+;/* Copyright (c) 2012 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+__initial_sp	EQU     0x20008000
+
+                PRESERVE8
+                THUMB
+
+; Vector Table Mapped to Address 0 at Reset
+
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp              ; Top of Stack
+                DCD     Reset_Handler
+                DCD     NMI_Handler
+                DCD     HardFault_Handler
+                DCD     MemoryManagement_Handler
+                DCD     BusFault_Handler
+                DCD     UsageFault_Handler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     SVC_Handler
+                DCD     DebugMonitor_Handler
+                DCD     0                         ; Reserved
+                DCD     PendSV_Handler
+                DCD     SysTick_Handler
+
+                ; External Interrupts
+                DCD     POWER_CLOCK_IRQHandler
+                DCD     RADIO_IRQHandler
+                DCD     UARTE0_UART0_IRQHandler
+                DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+                DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+                DCD     NFCT_IRQHandler
+                DCD     GPIOTE_IRQHandler
+                DCD     SAADC_IRQHandler
+                DCD     TIMER0_IRQHandler
+                DCD     TIMER1_IRQHandler
+                DCD     TIMER2_IRQHandler
+                DCD     RTC0_IRQHandler
+                DCD     TEMP_IRQHandler
+                DCD     RNG_IRQHandler
+                DCD     ECB_IRQHandler
+                DCD     CCM_AAR_IRQHandler
+                DCD     WDT_IRQHandler
+                DCD     RTC1_IRQHandler
+                DCD     QDEC_IRQHandler
+                DCD     COMP_LPCOMP_IRQHandler
+                DCD     SWI0_EGU0_IRQHandler
+                DCD     SWI1_EGU1_IRQHandler
+                DCD     SWI2_EGU2_IRQHandler
+                DCD     SWI3_EGU3_IRQHandler
+                DCD     SWI4_EGU4_IRQHandler
+                DCD     SWI5_EGU5_IRQHandler
+                DCD     TIMER3_IRQHandler
+                DCD     TIMER4_IRQHandler
+                DCD     PWM0_IRQHandler
+                DCD     PDM_IRQHandler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     MWU_IRQHandler
+                DCD     PWM1_IRQHandler
+                DCD     PWM2_IRQHandler
+                DCD     SPIM2_SPIS2_SPI2_IRQHandler
+                DCD     RTC2_IRQHandler
+                DCD     I2S_IRQHandler
+                DCD     FPU_IRQHandler
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+                DCD     0                         ; Reserved
+
+__Vectors_End
+
+__Vectors_Size  EQU     __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset Handler
+
+
+Reset_Handler   PROC
+                EXPORT  Reset_Handler             [WEAK]
+                IMPORT  SystemInit
+                IMPORT  __main
+                
+                
+                LDR     R0, =SystemInit
+                BLX     R0
+                LDR     R0, =__main
+                BX      R0
+                ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler               [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler         [WEAK]
+                B       .
+                ENDP
+MemoryManagement_Handler\
+                PROC
+                EXPORT  MemoryManagement_Handler  [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler          [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler        [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler               [WEAK]
+                B       .
+                ENDP
+DebugMonitor_Handler\
+                PROC
+                EXPORT  DebugMonitor_Handler      [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler            [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler           [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT   POWER_CLOCK_IRQHandler [WEAK]
+                EXPORT   RADIO_IRQHandler [WEAK]
+                EXPORT   UARTE0_UART0_IRQHandler [WEAK]
+                EXPORT   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler [WEAK]
+                EXPORT   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler [WEAK]
+                EXPORT   NFCT_IRQHandler [WEAK]
+                EXPORT   GPIOTE_IRQHandler [WEAK]
+                EXPORT   SAADC_IRQHandler [WEAK]
+                EXPORT   TIMER0_IRQHandler [WEAK]
+                EXPORT   TIMER1_IRQHandler [WEAK]
+                EXPORT   TIMER2_IRQHandler [WEAK]
+                EXPORT   RTC0_IRQHandler [WEAK]
+                EXPORT   TEMP_IRQHandler [WEAK]
+                EXPORT   RNG_IRQHandler [WEAK]
+                EXPORT   ECB_IRQHandler [WEAK]
+                EXPORT   CCM_AAR_IRQHandler [WEAK]
+                EXPORT   WDT_IRQHandler [WEAK]
+                EXPORT   RTC1_IRQHandler [WEAK]
+                EXPORT   QDEC_IRQHandler [WEAK]
+                EXPORT   COMP_LPCOMP_IRQHandler [WEAK]
+                EXPORT   SWI0_EGU0_IRQHandler [WEAK]
+                EXPORT   SWI1_EGU1_IRQHandler [WEAK]
+                EXPORT   SWI2_EGU2_IRQHandler [WEAK]
+                EXPORT   SWI3_EGU3_IRQHandler [WEAK]
+                EXPORT   SWI4_EGU4_IRQHandler [WEAK]
+                EXPORT   SWI5_EGU5_IRQHandler [WEAK]
+                EXPORT   TIMER3_IRQHandler [WEAK]
+                EXPORT   TIMER4_IRQHandler [WEAK]
+                EXPORT   PWM0_IRQHandler [WEAK]
+                EXPORT   PDM_IRQHandler [WEAK]
+                EXPORT   MWU_IRQHandler [WEAK]
+                EXPORT   PWM1_IRQHandler [WEAK]
+                EXPORT   PWM2_IRQHandler [WEAK]
+                EXPORT   SPIM2_SPIS2_SPI2_IRQHandler [WEAK]
+                EXPORT   RTC2_IRQHandler [WEAK]
+                EXPORT   I2S_IRQHandler [WEAK]
+                EXPORT   FPU_IRQHandler [WEAK]
+POWER_CLOCK_IRQHandler
+RADIO_IRQHandler
+UARTE0_UART0_IRQHandler
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+NFCT_IRQHandler
+GPIOTE_IRQHandler
+SAADC_IRQHandler
+TIMER0_IRQHandler
+TIMER1_IRQHandler
+TIMER2_IRQHandler
+RTC0_IRQHandler
+TEMP_IRQHandler
+RNG_IRQHandler
+ECB_IRQHandler
+CCM_AAR_IRQHandler
+WDT_IRQHandler
+RTC1_IRQHandler
+QDEC_IRQHandler
+COMP_LPCOMP_IRQHandler
+SWI0_EGU0_IRQHandler
+SWI1_EGU1_IRQHandler
+SWI2_EGU2_IRQHandler
+SWI3_EGU3_IRQHandler
+SWI4_EGU4_IRQHandler
+SWI5_EGU5_IRQHandler
+TIMER3_IRQHandler
+TIMER4_IRQHandler
+PWM0_IRQHandler
+PDM_IRQHandler
+MWU_IRQHandler
+PWM1_IRQHandler
+PWM2_IRQHandler
+SPIM2_SPIS2_SPI2_IRQHandler
+RTC2_IRQHandler
+I2S_IRQHandler
+FPU_IRQHandler
+                B .
+                ENDP
+                ALIGN
+                END
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/sys.cpp b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/sys.cpp
new file mode 100644
index 0000000000..2f1024ace8
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_ARM_STD/sys.cpp
@@ -0,0 +1,31 @@
+/* mbed Microcontroller Library - stackheap
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ * 
+ * Setup a fixed single stack/heap memory model, 
+ *  between the top of the RW/ZI region and the stackpointer
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif 
+
+#include <rt_misc.h>
+#include <stdint.h>
+
+extern char Image$$RW_IRAM1$$ZI$$Limit[];
+
+extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
+    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
+    uint32_t sp_limit = __current_sp();
+
+    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
+
+    struct __initial_stackheap r;
+    r.heap_base = zi_limit;
+    r.heap_limit = sp_limit;
+    return r;
+}
+
+#ifdef __cplusplus
+}
+#endif 
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld
new file mode 100644
index 0000000000..e866a7e520
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/NRF52832.ld
@@ -0,0 +1,185 @@
+/*
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+/* Linker script to configure memory regions. */
+
+MEMORY
+{
+  FLASH (rx) : ORIGIN = 0x1C000, LENGTH = 0x64000
+  RAM (rwx) :  ORIGIN = 0x20002ef8, LENGTH = 0xd108
+}
+
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/* Linker script to place sections and symbol values. Should be used together
+ * with the other linker script that defines memory regions FLASH and RAM.
+ * It references the following symbols that must be defined in code:
+ *   Reset_Handler : Entry of reset handler
+ *
+ * It defines the following symbols that the code can use without definition:
+ *   __exidx_start
+ *   __exidx_end
+ *   __etext
+ *   __data_start__
+ *   __preinit_array_start
+ *   __preinit_array_end
+ *   __init_array_start
+ *   __init_array_end
+ *   __fini_array_start
+ *   __fini_array_end
+ *   __data_end__
+ *   __bss_start__
+ *   __bss_end__
+ *   __end__
+ *   end
+ *   __HeapLimit
+ *   __StackLimit
+ *   __StackTop
+ *   __stack
+ */
+ENTRY(Reset_Handler)
+
+
+SECTIONS
+{
+    .text :
+    {
+        KEEP(*(.Vectors))
+        *(.text*)
+
+        KEEP(*(.init))
+        KEEP(*(.fini))
+
+        /* .ctors */
+        *crtbegin.o(.ctors)
+        *crtbegin?.o(.ctors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
+        *(SORT(.ctors.*))
+        *(.ctors)
+
+        /* .dtors */
+        *crtbegin.o(.dtors)
+        *crtbegin?.o(.dtors)
+        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
+        *(SORT(.dtors.*))
+        *(.dtors)
+
+        *(.rodata*)
+
+        KEEP(*(.eh_frame*))
+    } > FLASH
+
+    .ARM.extab :
+    {
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        . = ALIGN(4);
+    } > FLASH
+
+    __exidx_start = .;
+    .ARM.exidx :
+    {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+        . = ALIGN(4);
+    } > FLASH
+    __exidx_end = .;
+
+    __etext = .;
+
+    .data : AT (__etext)
+    {
+        __data_start__ = .;
+        *(vtable)
+        *(.data*)
+
+        . = ALIGN(4);
+        /* preinit data */
+        PROVIDE_HIDDEN (__preinit_array_start = .);
+        KEEP(*(.preinit_array))
+        PROVIDE_HIDDEN (__preinit_array_end = .);
+
+        . = ALIGN(4);
+        /* init data */
+        PROVIDE_HIDDEN (__init_array_start = .);
+        KEEP(*(SORT(.init_array.*)))
+        KEEP(*(.init_array))
+        PROVIDE_HIDDEN (__init_array_end = .);
+
+
+        . = ALIGN(4);
+        /* finit data */
+        PROVIDE_HIDDEN (__fini_array_start = .);
+        KEEP(*(SORT(.fini_array.*)))
+        KEEP(*(.fini_array))
+        PROVIDE_HIDDEN (__fini_array_end = .);
+
+        *(.jcr)
+        . = ALIGN(4);
+        /* All data end */
+        __data_end__ = .;
+
+    } > RAM
+
+    __edata = .;
+
+    .fs_data :
+    {
+      PROVIDE(__start_fs_data = .);
+      KEEP(*(.fs_data))
+      PROVIDE(__stop_fs_data = .);
+    } > RAM
+
+    .bss :
+    {
+        . = ALIGN(4);
+        __bss_start__ = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4);
+        __bss_end__ = .;
+    } > RAM
+
+    .heap (NOLOAD):
+    {
+        __end__ = .;
+        end = __end__;
+        *(.heap*);
+
+        /* Expand the heap to reach the stack boundary. */
+        ASSERT(. <= (ORIGIN(RAM) + LENGTH(RAM) - 0x800), "heap region overflowed into stack");
+        . += (ORIGIN(RAM) + LENGTH(RAM) - 0x800) - .;
+    } > RAM
+    PROVIDE(__heap_start = ADDR(.heap));
+    PROVIDE(__heap_size = SIZEOF(.heap));
+    PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+    PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+
+    /* .stack_dummy section does not contain any symbols. It is only
+     * used for the linker script to calculate the size of stack sections
+     * and assign values to stack symbols later. */
+    .stack (NOLOAD):
+    {
+        __StackLimit = .;
+        *(.stack*)
+        . += (ORIGIN(RAM) + LENGTH(RAM) - .);
+    } > RAM
+
+    /* Set the stack top to the end of RAM and move down the stack limit by
+     * the size of the stack_dummy section. */
+    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
+    __StackLimit = __StackTop - SIZEOF(.stack);
+    PROVIDE(__stack = __StackTop);
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/startup_NRF52832.S b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/startup_NRF52832.S
new file mode 100644
index 0000000000..0d02b962e8
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_GCC_ARM/startup_NRF52832.S
@@ -0,0 +1,467 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/*
+NOTE: Template files (including this one) are application specific and therefore
+expected to be copied into the application project folder prior to its use!
+*/
+
+    .syntax unified
+    .arch armv7e-m
+
+    .section .Vectors
+    .align 2
+    .globl __Vectors
+__Vectors:
+    .long   __StackTop                  /* Top of Stack */
+    .long   Reset_Handler
+    .long   NMI_Handler
+    .long   HardFault_Handler
+    .long   MemoryManagement_Handler
+    .long   BusFault_Handler
+    .long   UsageFault_Handler
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   SVC_Handler
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   PendSV_Handler
+    .long   SysTick_Handler
+
+  /* External Interrupts */
+    .long   POWER_CLOCK_IRQHandler
+    .long   RADIO_IRQHandler
+    .long   UARTE0_UART0_IRQHandler
+    .long   SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+    .long   SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+    .long   NFCT_IRQHandler
+    .long   GPIOTE_IRQHandler
+    .long   SAADC_IRQHandler
+    .long   TIMER0_IRQHandler
+    .long   TIMER1_IRQHandler
+    .long   TIMER2_IRQHandler
+    .long   RTC0_IRQHandler
+    .long   TEMP_IRQHandler
+    .long   RNG_IRQHandler
+    .long   ECB_IRQHandler
+    .long   CCM_AAR_IRQHandler
+    .long   WDT_IRQHandler
+    .long   RTC1_IRQHandler
+    .long   QDEC_IRQHandler
+    .long   COMP_LPCOMP_IRQHandler
+    .long   SWI0_EGU0_IRQHandler
+    .long   SWI1_EGU1_IRQHandler
+    .long   SWI2_EGU2_IRQHandler
+    .long   SWI3_EGU3_IRQHandler
+    .long   SWI4_EGU4_IRQHandler
+    .long   SWI5_EGU5_IRQHandler
+    .long   TIMER3_IRQHandler
+    .long   TIMER4_IRQHandler
+    .long   PWM0_IRQHandler
+    .long   PDM_IRQHandler
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   MWU_IRQHandler
+    .long   PWM1_IRQHandler
+    .long   PWM2_IRQHandler
+    .long   SPIM2_SPIS2_SPI2_IRQHandler
+    .long   RTC2_IRQHandler
+    .long   I2S_IRQHandler
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+    .long   0                           /*Reserved */
+
+    .size    __Vectors, . - __Vectors
+
+/* Reset Handler */
+
+    .text
+    .thumb
+    .thumb_func
+    .align 1
+    .globl    Reset_Handler
+    .type    Reset_Handler, %function
+Reset_Handler:
+    .fnstart
+
+
+/*     Loop to copy data from read only memory to RAM. The ranges
+ *      of copy from/to are specified by following symbols evaluated in
+ *      linker script.
+ *      __etext: End of code section, i.e., begin of data sections to copy from.
+ *      __data_start__/__data_end__: RAM address range that data should be
+ *      copied to. Both must be aligned to 4 bytes boundary.  */
+
+    ldr    r1, =__etext
+    ldr    r2, =__data_start__
+    ldr    r3, =__data_end__
+
+    subs    r3, r2
+    ble     .LC0
+
+.LC1:
+    subs    r3, 4
+    ldr    r0, [r1,r3]
+    str    r0, [r2,r3]
+    bgt    .LC1
+.LC0:
+
+    LDR     R0, =SystemInit
+    BLX     R0
+    LDR     R0, =_start
+    BX      R0
+
+    .pool
+    .cantunwind
+    .fnend
+    .size   Reset_Handler,.-Reset_Handler
+
+    .section ".text"
+
+
+/* Dummy Exception Handlers (infinite loops which can be modified) */
+
+    .weak   NMI_Handler
+    .type   NMI_Handler, %function
+NMI_Handler:
+    B       .
+    .size   NMI_Handler, . - NMI_Handler
+
+
+    .weak   HardFault_Handler
+    .type   HardFault_Handler, %function
+HardFault_Handler:
+    B       .
+    .size   HardFault_Handler, . - HardFault_Handler
+
+
+    .weak   MemoryManagement_Handler
+    .type   MemoryManagement_Handler, %function
+MemoryManagement_Handler:
+    B       .
+    .size   MemoryManagement_Handler, . - MemoryManagement_Handler
+
+
+    .weak   BusFault_Handler
+    .type   BusFault_Handler, %function
+BusFault_Handler:
+    B       .
+    .size   BusFault_Handler, . - BusFault_Handler
+
+
+    .weak   UsageFault_Handler
+    .type   UsageFault_Handler, %function
+UsageFault_Handler:
+    B       .
+    .size   UsageFault_Handler, . - UsageFault_Handler
+
+
+    .weak   SVC_Handler
+    .type   SVC_Handler, %function
+SVC_Handler:
+    B       .
+    .size   SVC_Handler, . - SVC_Handler
+
+
+    .weak   PendSV_Handler
+    .type   PendSV_Handler, %function
+PendSV_Handler:
+    B       .
+    .size   PendSV_Handler, . - PendSV_Handler
+
+
+    .weak   SysTick_Handler
+    .type   SysTick_Handler, %function
+SysTick_Handler:
+    B       .
+    .size   SysTick_Handler, . - SysTick_Handler
+
+
+/* IRQ Handlers */
+
+    .globl  Default_Handler
+    .type   Default_Handler, %function
+Default_Handler:
+    B       .
+    .size   Default_Handler, . - Default_Handler
+
+    .macro  IRQ handler
+    .weak   \handler
+    .set    \handler, Default_Handler
+    .endm
+
+    IRQ  POWER_CLOCK_IRQHandler
+    IRQ  RADIO_IRQHandler
+    IRQ  UARTE0_UART0_IRQHandler
+    IRQ  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+    IRQ  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+    IRQ  NFCT_IRQHandler
+    IRQ  GPIOTE_IRQHandler
+    IRQ  SAADC_IRQHandler
+    IRQ  TIMER0_IRQHandler
+    IRQ  TIMER1_IRQHandler
+    IRQ  TIMER2_IRQHandler
+    IRQ  RTC0_IRQHandler
+    IRQ  TEMP_IRQHandler
+    IRQ  RNG_IRQHandler
+    IRQ  ECB_IRQHandler
+    IRQ  CCM_AAR_IRQHandler
+    IRQ  WDT_IRQHandler
+    IRQ  RTC1_IRQHandler
+    IRQ  QDEC_IRQHandler
+    IRQ  COMP_LPCOMP_IRQHandler
+    IRQ  SWI0_EGU0_IRQHandler
+    IRQ  SWI1_EGU1_IRQHandler
+    IRQ  SWI2_EGU2_IRQHandler
+    IRQ  SWI3_EGU3_IRQHandler
+    IRQ  SWI4_EGU4_IRQHandler
+    IRQ  SWI5_EGU5_IRQHandler
+    IRQ  TIMER3_IRQHandler
+    IRQ  TIMER4_IRQHandler
+    IRQ  PWM0_IRQHandler
+    IRQ  PDM_IRQHandler
+    IRQ  MWU_IRQHandler
+    IRQ  PWM1_IRQHandler
+    IRQ  PWM2_IRQHandler
+    IRQ  SPIM2_SPIS2_SPI2_IRQHandler
+    IRQ  RTC2_IRQHandler
+    IRQ  I2S_IRQHandler
+
+  .end
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_IAR/nRF52832.icf b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_IAR/nRF52832.icf
new file mode 100644
index 0000000000..d8dee15e57
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_IAR/nRF52832.icf
@@ -0,0 +1,46 @@
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x1c000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__   = 0x1c000;
+define symbol __ICFEDIT_region_ROM_end__     = 0x7ffff;
+define symbol __ICFEDIT_region_RAM_start__   = 0x20002ef8;
+define symbol __ICFEDIT_region_RAM_end__     = 0x2000ffff;
+export symbol __ICFEDIT_region_RAM_start__;
+export symbol __ICFEDIT_region_RAM_end__;
+/*-Sizes-*/
+/*Heap 1/4 of ram and stack 1/8*/
+define symbol __ICFEDIT_size_cstack__   = 0x800;
+define symbol __ICFEDIT_size_heap__     = 0x1800;
+/**** End of ICF editor section. ###ICF###*/
+
+define symbol __code_start_soft_device__ = 0x0;
+
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
+
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
+do not initialize  { section .noinit };
+
+keep { section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
+place in ROM_region   { readonly };
+place in RAM_region   { readwrite,
+                        block HEAP,
+                        block CSTACK };
+
+/*This is used for mbed applications build inside the Embedded workbench
+Applications build with the python scritps use a hex merge so need to merge it
+inside the linker. The linker can only use binary files so the hex merge is not possible
+through the linker. That is why a binary is used instead of a hex image for the embedded project.
+*/
+if(isdefinedsymbol(SOFT_DEVICE_BIN))
+{
+  place at address mem:__code_start_soft_device__ { section .noinit_softdevice };
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_IAR/startup_NRF52832_IAR.s b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_IAR/startup_NRF52832_IAR.s
new file mode 100644
index 0000000000..823565d975
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TOOLCHAIN_IAR/startup_NRF52832_IAR.s
@@ -0,0 +1,578 @@
+;/* Copyright (c) 2012 ARM LIMITED
+;
+;   All rights reserved.
+;   Redistribution and use in source and binary forms, with or without
+;   modification, are permitted provided that the following conditions are met:
+;   - Redistributions of source code must retain the above copyright
+;     notice, this list of conditions and the following disclaimer.
+;   - Redistributions in binary form must reproduce the above copyright
+;     notice, this list of conditions and the following disclaimer in the
+;     documentation and/or other materials provided with the distribution.
+;   - Neither the name of ARM nor the names of its contributors may be used
+;     to endorse or promote products derived from this software without
+;     specific prior written permission.
+;   *
+;   THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;   AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;   IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+;   ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
+;   LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+;   CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+;   SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+;   INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+;   CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+;   ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+;   POSSIBILITY OF SUCH DAMAGE.
+;   ---------------------------------------------------------------------------*/
+
+
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+
+
+
+        MODULE  ?cstartup
+
+        ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW.
+        ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW.
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+        PUBLIC  __Vectors
+        PUBLIC  __Vectors_End
+        PUBLIC  __Vectors_Size
+
+        DATA
+
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler
+        DCD     NMI_Handler
+        DCD     HardFault_Handler
+        DCD     MemoryManagement_Handler
+        DCD     BusFault_Handler
+        DCD     UsageFault_Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler
+        DCD     DebugMonitor_Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler
+        DCD     SysTick_Handler
+
+        ; External Interrupts
+        DCD     POWER_CLOCK_IRQHandler
+        DCD     RADIO_IRQHandler
+        DCD     UARTE0_UART0_IRQHandler
+        DCD     SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+        DCD     SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+        DCD     NFCT_IRQHandler
+        DCD     GPIOTE_IRQHandler
+        DCD     SAADC_IRQHandler
+        DCD     TIMER0_IRQHandler
+        DCD     TIMER1_IRQHandler
+        DCD     TIMER2_IRQHandler
+        DCD     RTC0_IRQHandler
+        DCD     TEMP_IRQHandler
+        DCD     RNG_IRQHandler
+        DCD     ECB_IRQHandler
+        DCD     CCM_AAR_IRQHandler
+        DCD     WDT_IRQHandler
+        DCD     RTC1_IRQHandler
+        DCD     QDEC_IRQHandler
+        DCD     COMP_LPCOMP_IRQHandler
+        DCD     SWI0_EGU0_IRQHandler
+        DCD     SWI1_EGU1_IRQHandler
+        DCD     SWI2_EGU2_IRQHandler
+        DCD     SWI3_EGU3_IRQHandler
+        DCD     SWI4_EGU4_IRQHandler
+        DCD     SWI5_EGU5_IRQHandler
+        DCD     TIMER3_IRQHandler
+        DCD     TIMER4_IRQHandler
+        DCD     PWM0_IRQHandler
+        DCD     PDM_IRQHandler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     MWU_IRQHandler
+        DCD     PWM1_IRQHandler
+        DCD     PWM2_IRQHandler
+        DCD     SPIM2_SPIS2_SPI2_IRQHandler
+        DCD     RTC2_IRQHandler
+        DCD     I2S_IRQHandler
+        DCD     FPU_IRQHandler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+
+__Vectors_End
+__Vectors                           EQU   __vector_table
+__Vectors_Size                      EQU   __Vectors_End - __Vectors
+
+
+; Default handlers.
+        THUMB
+
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:NOROOT(2)
+Reset_Handler
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        ; Dummy exception handlers
+        
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:NOROOT(1)
+NMI_Handler
+        B .
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:NOROOT(1)
+HardFault_Handler
+        B .
+
+        PUBWEAK MemoryManagement_Handler
+        SECTION .text:CODE:NOROOT(1)
+MemoryManagement_Handler
+        B .
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:NOROOT(1)
+BusFault_Handler
+        B .
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:NOROOT(1)
+UsageFault_Handler
+        B .
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:NOROOT(1)
+SVC_Handler
+        B .
+
+        PUBWEAK DebugMonitor_Handler
+        SECTION .text:CODE:NOROOT(1)
+DebugMonitor_Handler
+        B .
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:NOROOT(1)
+PendSV_Handler
+        B .
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:NOROOT(1)
+SysTick_Handler
+        B .
+
+
+       ; Dummy interrupt handlers
+
+        PUBWEAK  POWER_CLOCK_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+POWER_CLOCK_IRQHandler
+        B .
+
+        PUBWEAK  RADIO_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RADIO_IRQHandler
+        B .
+
+        PUBWEAK  UARTE0_UART0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+UARTE0_UART0_IRQHandler
+        B .
+
+        PUBWEAK  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+        B .
+
+        PUBWEAK  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+        B .
+
+        PUBWEAK  NFCT_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+NFCT_IRQHandler
+        B .
+
+        PUBWEAK  GPIOTE_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+GPIOTE_IRQHandler
+        B .
+
+        PUBWEAK  SAADC_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SAADC_IRQHandler
+        B .
+
+        PUBWEAK  TIMER0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+TIMER0_IRQHandler
+        B .
+
+        PUBWEAK  TIMER1_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+TIMER1_IRQHandler
+        B .
+
+        PUBWEAK  TIMER2_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+TIMER2_IRQHandler
+        B .
+
+        PUBWEAK  RTC0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RTC0_IRQHandler
+        B .
+
+        PUBWEAK  TEMP_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+TEMP_IRQHandler
+        B .
+
+        PUBWEAK  RNG_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RNG_IRQHandler
+        B .
+
+        PUBWEAK  ECB_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+ECB_IRQHandler
+        B .
+
+        PUBWEAK  CCM_AAR_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+CCM_AAR_IRQHandler
+        B .
+
+        PUBWEAK  WDT_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+WDT_IRQHandler
+        B .
+
+        PUBWEAK  RTC1_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RTC1_IRQHandler
+        B .
+
+        PUBWEAK  QDEC_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+QDEC_IRQHandler
+        B .
+
+        PUBWEAK  COMP_LPCOMP_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+COMP_LPCOMP_IRQHandler
+        B .
+
+        PUBWEAK  SWI0_EGU0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI0_EGU0_IRQHandler
+        B .
+
+        PUBWEAK  SWI1_EGU1_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI1_EGU1_IRQHandler
+        B .
+
+        PUBWEAK  SWI2_EGU2_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI2_EGU2_IRQHandler
+        B .
+
+        PUBWEAK  SWI3_EGU3_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI3_EGU3_IRQHandler
+        B .
+
+        PUBWEAK  SWI4_EGU4_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI4_EGU4_IRQHandler
+        B .
+
+        PUBWEAK  SWI5_EGU5_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SWI5_EGU5_IRQHandler
+        B .
+
+        PUBWEAK  TIMER3_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+TIMER3_IRQHandler
+        B .
+
+        PUBWEAK  TIMER4_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+TIMER4_IRQHandler
+        B .
+
+        PUBWEAK  PWM0_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+PWM0_IRQHandler
+        B .
+
+        PUBWEAK  PDM_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+PDM_IRQHandler
+        B .
+
+        PUBWEAK  MWU_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+MWU_IRQHandler
+        B .
+
+        PUBWEAK  PWM1_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+PWM1_IRQHandler
+        B .
+
+        PUBWEAK  PWM2_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+PWM2_IRQHandler
+        B .
+
+        PUBWEAK  SPIM2_SPIS2_SPI2_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+SPIM2_SPIS2_SPI2_IRQHandler
+        B .
+
+        PUBWEAK  RTC2_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+RTC2_IRQHandler
+        B .
+
+        PUBWEAK  I2S_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+I2S_IRQHandler
+        B .
+
+        PUBWEAK  FPU_IRQHandler
+        SECTION .text:CODE:NOROOT(1)
+FPU_IRQHandler
+        B .
+
+
+        END
+
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis.h
new file mode 100644
index 0000000000..214885742d
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis.h
@@ -0,0 +1,24 @@
+/*
+ * PackageLicenseDeclared: Apache-2.0
+ * Copyright (c) 2016 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef MBED_CMSIS_H
+#define MBED_CMSIS_H
+
+#include "nrf.h"
+#include "cmsis_nvic.h"
+
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.c b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.c
new file mode 100644
index 0000000000..02f85b1d79
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.c
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "cmsis_nvic.h"
+
+#define NVIC_RAM_VECTOR_ADDRESS   (0x10000000)  // Vectors positioned at start of SRAM2
+#define NVIC_FLASH_VECTOR_ADDRESS (0x0)  // Initial vector position in flash
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
+{
+    uint32_t *vectors = (uint32_t *) SCB->VTOR;
+    uint32_t i;
+
+    /* Copy and switch to dynamic vectors if the first time called */
+    if (SCB->VTOR != NVIC_RAM_VECTOR_ADDRESS) {
+        uint32_t *old_vectors = (uint32_t *) NVIC_FLASH_VECTOR_ADDRESS;
+        vectors = (uint32_t *) NVIC_RAM_VECTOR_ADDRESS;
+        for (i = 0; i < NVIC_NUM_VECTORS; i++) {
+            vectors[i] = old_vectors[i];
+        }
+        SCB->VTOR = (uint32_t) NVIC_RAM_VECTOR_ADDRESS;
+    }
+    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
+}
+
+uint32_t NVIC_GetVector(IRQn_Type IRQn)
+{
+    uint32_t *vectors = (uint32_t *) SCB->VTOR;
+    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
+}
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.h
new file mode 100644
index 0000000000..0837075c40
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/cmsis_nvic.h
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * CMSIS-style functionality to support dynamic vectors
+ *******************************************************************************
+ * Copyright (c) 2016 ARM Limited. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_CMSIS_NVIC_H
+#define MBED_CMSIS_NVIC_H
+
+#define NVIC_NUM_VECTORS      (16 + 38)   // CORE + MCU Peripherals
+#define NVIC_USER_IRQ_OFFSET  16
+
+#include "nrf52.h"
+#include "cmsis.h"
+
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
+uint32_t NVIC_GetVector(IRQn_Type IRQn);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.c b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.c
new file mode 100644
index 0000000000..89d125a37d
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.c
@@ -0,0 +1,321 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "system_nrf52.h"
+#include "nrf5x_lf_clk_helper.h"
+
+/*lint ++flb "Enter library region" */
+
+#define __SYSTEM_CLOCK_64M      (64000000UL)
+
+static bool errata_16(void);
+static bool errata_31(void);
+static bool errata_32(void);
+static bool errata_36(void);
+static bool errata_37(void);
+static bool errata_57(void);
+static bool errata_66(void);
+
+
+#if defined ( __CC_ARM )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#elif defined ( __ICCARM__ )
+    __root uint32_t SystemCoreClock = __SYSTEM_CLOCK_64M;
+#elif defined ( __GNUC__ )
+    uint32_t SystemCoreClock __attribute__((used)) = __SYSTEM_CLOCK_64M;
+#endif
+
+void SystemCoreClockUpdate(void)
+{
+    SystemCoreClock = __SYSTEM_CLOCK_64M;
+}
+
+void SystemInit(void)
+{
+    /* Workaround for Errata 16 "System: RAM may be corrupt on wakeup from CPU IDLE" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/ */
+    if (errata_16()){
+        *(volatile uint32_t *)0x4007C074 = 3131961357ul;
+    }
+
+    /* Workaround for Errata 31 "CLOCK: Calibration values are not correctly loaded from FICR at reset" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/ */
+    if (errata_31()){
+        *(volatile uint32_t *)0x4000053C = ((*(volatile uint32_t *)0x10000244) & 0x0000E000) >> 13;
+    }
+
+    /* Workaround for Errata 32 "DIF: Debug session automatically enables TracePort pins" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/ */
+    if (errata_32()){
+        CoreDebug->DEMCR &= ~CoreDebug_DEMCR_TRCENA_Msk;
+    }
+
+    /* Workaround for Errata 36 "CLOCK: Some registers are not reset when expected" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_36()){
+        NRF_CLOCK->EVENTS_DONE = 0;
+        NRF_CLOCK->EVENTS_CTTO = 0;
+        NRF_CLOCK->CTIV = 0;
+    }
+
+    /* Workaround for Errata 37 "RADIO: Encryption engine is slow by default" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_37()){
+        *(volatile uint32_t *)0x400005A0 = 0x3;
+    }
+
+    /* Workaround for Errata 57 "NFCT: NFC Modulation amplitude" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_57()){
+        *(volatile uint32_t *)0x40005610 = 0x00000005;
+        *(volatile uint32_t *)0x40005688 = 0x00000001;
+        *(volatile uint32_t *)0x40005618 = 0x00000000;
+        *(volatile uint32_t *)0x40005614 = 0x0000003F;
+    }
+
+    /* Workaround for Errata 66 "TEMP: Linearity specification not met with default settings" found at the Errata document
+       for your device located at https://infocenter.nordicsemi.com/  */
+    if (errata_66()){
+        NRF_TEMP->A0 = NRF_FICR->TEMP.A0;
+        NRF_TEMP->A1 = NRF_FICR->TEMP.A1;
+        NRF_TEMP->A2 = NRF_FICR->TEMP.A2;
+        NRF_TEMP->A3 = NRF_FICR->TEMP.A3;
+        NRF_TEMP->A4 = NRF_FICR->TEMP.A4;
+        NRF_TEMP->A5 = NRF_FICR->TEMP.A5;
+        NRF_TEMP->B0 = NRF_FICR->TEMP.B0;
+        NRF_TEMP->B1 = NRF_FICR->TEMP.B1;
+        NRF_TEMP->B2 = NRF_FICR->TEMP.B2;
+        NRF_TEMP->B3 = NRF_FICR->TEMP.B3;
+        NRF_TEMP->B4 = NRF_FICR->TEMP.B4;
+        NRF_TEMP->B5 = NRF_FICR->TEMP.B5;
+        NRF_TEMP->T0 = NRF_FICR->TEMP.T0;
+        NRF_TEMP->T1 = NRF_FICR->TEMP.T1;
+        NRF_TEMP->T2 = NRF_FICR->TEMP.T2;
+        NRF_TEMP->T3 = NRF_FICR->TEMP.T3;
+        NRF_TEMP->T4 = NRF_FICR->TEMP.T4;
+    }
+
+    /* Enable the FPU if the compiler used floating point unit instructions. __FPU_USED is a MACRO defined by the
+     * compiler. Since the FPU consumes energy, remember to disable FPU use in the compiler if floating point unit
+     * operations are not used in your code. */
+    #if (__FPU_USED == 1)
+        SCB->CPACR |= (3UL << 20) | (3UL << 22);
+        __DSB();
+        __ISB();
+    #endif
+
+    /* Configure NFCT pins as GPIOs if NFCT is not to be used in your code. If CONFIG_NFCT_PINS_AS_GPIOS is not defined,
+       two GPIOs (see Product Specification to see which ones) will be reserved for NFC and will not be available as
+       normal GPIOs. */
+    #if defined (CONFIG_NFCT_PINS_AS_GPIOS)
+        if ((NRF_UICR->NFCPINS & UICR_NFCPINS_PROTECT_Msk) == (UICR_NFCPINS_PROTECT_NFC << UICR_NFCPINS_PROTECT_Pos)){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->NFCPINS &= ~UICR_NFCPINS_PROTECT_Msk;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Configure GPIO pads as pPin Reset pin if Pin Reset capabilities desired. If CONFIG_GPIO_AS_PINRESET is not
+      defined, pin reset will not be available. One GPIO (see Product Specification to see which one) will then be
+      reserved for PinReset and not available as normal GPIO. */
+    #if defined (CONFIG_GPIO_AS_PINRESET)
+        if (((NRF_UICR->PSELRESET[0] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos)) ||
+            ((NRF_UICR->PSELRESET[1] & UICR_PSELRESET_CONNECT_Msk) != (UICR_PSELRESET_CONNECT_Connected << UICR_PSELRESET_CONNECT_Pos))){
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[0] = 21;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_UICR->PSELRESET[1] = 21;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos;
+            while (NRF_NVMC->READY == NVMC_READY_READY_Busy){}
+            NVIC_SystemReset();
+        }
+    #endif
+
+    /* Enable SWO trace functionality. If ENABLE_SWO is not defined, SWO pin will be used as GPIO (see Product
+       Specification to see which one). */
+    #if defined (ENABLE_SWO)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Serial << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    /* Enable Trace functionality. If ENABLE_TRACE is not defined, TRACE pins will be used as GPIOs (see Product
+       Specification to see which ones). */
+    #if defined (ENABLE_TRACE)
+        CoreDebug->DEMCR |= CoreDebug_DEMCR_TRCENA_Msk;
+        NRF_CLOCK->TRACECONFIG |= CLOCK_TRACECONFIG_TRACEMUX_Parallel << CLOCK_TRACECONFIG_TRACEMUX_Pos;
+        NRF_P0->PIN_CNF[14] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[15] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[16] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[18] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+        NRF_P0->PIN_CNF[20] = (GPIO_PIN_CNF_DRIVE_H0H1 << GPIO_PIN_CNF_DRIVE_Pos) | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos) | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+    #endif
+
+    SystemCoreClockUpdate();
+
+    // Start the LF oscilator according to the mbed configuration (over the nrf5x_lf_clk_helper.h file)
+    NRF_CLOCK->LFCLKSRC             = (CLOCK_LFCLKSRC_SRC_TO_USE << CLOCK_LFCLKSRC_SRC_Pos);
+    NRF_CLOCK->EVENTS_LFCLKSTARTED  = 0;
+    NRF_CLOCK->TASKS_LFCLKSTART     = 1;
+
+    // Wait for the external oscillator to start up.
+    while (NRF_CLOCK->EVENTS_LFCLKSTARTED == 0) {
+        // Do nothing.
+    }
+}
+
+
+static bool errata_16(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_31(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+        {
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40)
+        {
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_32(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_36(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+        {
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x40)
+        {
+            return true;
+        }
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_37(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_57(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+static bool errata_66(void)
+{
+    if ((((*(uint32_t *)0xF0000FE0) & 0x000000FF) == 0x6) && (((*(uint32_t *)0xF0000FE4) & 0x0000000F) == 0x0))
+    {
+        if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x50)
+        {
+            return true;
+        }
+    }
+
+    return false;
+}
+
+
+/*lint --flb "Leave library region" */
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.h
new file mode 100644
index 0000000000..5ecc271059
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/system_nrf52.h
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SYSTEM_NRF52_H
+#define SYSTEM_NRF52_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+extern uint32_t SystemCoreClock;    /*!< System Clock Frequency (Core Clock)  */
+
+/**
+ * Initialize the system
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Setup the microcontroller system.
+ *         Initialize the System and update the SystemCoreClock variable.
+ */
+extern void SystemInit (void);
+
+/**
+ * Update SystemCoreClock variable
+ *
+ * @param  none
+ * @return none
+ *
+ * @brief  Updates the SystemCoreClock with current core Clock
+ *         retrieved from cpu registers.
+ */
+extern void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* SYSTEM_NRF52_H */
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/nrf5x_lf_clk_helper.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/nrf5x_lf_clk_helper.h
new file mode 100644
index 0000000000..08744be767
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/nrf5x_lf_clk_helper.h
@@ -0,0 +1,66 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef __NRF5X_LF_CLK_HELPER_H_
+    
+#ifndef MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC
+    #define MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC (NRF_LF_SRC_XTAL)
+    #warning No configuration for LF clock source. Xtal source will be used as a default configuration.
+#endif
+
+
+
+#define NRF_LF_SRC_XTAL  2 
+#define NRF_LF_SRC_SYNTH 3 
+#define NRF_LF_SRC_RC    4
+
+#if MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_SYNTH
+    #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Synth)
+#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_XTAL
+    #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_Xtal)
+#elif MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC == NRF_LF_SRC_RC
+    #define CLOCK_LFCLKSRC_SRC_TO_USE (CLOCK_LFCLKSRC_SRC_RC)
+#else
+    #error Bad LFCLK configuration. Declare proper source through mbed configuration.
+#endif
+
+#undef NRF_LF_SRC_XTAL
+#undef NRF_LF_SRC_SYNTH
+#undef NRF_LF_SRC_RC
+
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/compiler_abstraction.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/compiler_abstraction.h
new file mode 100644
index 0000000000..371d95b65a
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/compiler_abstraction.h
@@ -0,0 +1,135 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef _COMPILER_ABSTRACTION_H
+#define _COMPILER_ABSTRACTION_H
+
+/*lint ++flb "Enter library region" */
+
+#if defined ( __CC_ARM )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            __inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+
+    #define GET_SP()                __current_sp()
+
+#elif defined ( __ICCARM__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __weak
+    #endif
+
+    /* Not defined for IAR since it requires a new line to work, and C preprocessor does not allow that. */
+    #ifndef __ALIGN
+        #define __ALIGN(n)
+    #endif
+
+    #define GET_SP()                __get_SP()
+
+#elif defined   ( __GNUC__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __attribute__((aligned(n)))
+    #endif
+
+    #define GET_SP()                gcc_current_sp()
+
+    static inline unsigned int gcc_current_sp(void)
+    {
+        register unsigned sp __ASM("sp");
+        return sp;
+    }
+
+#elif defined   ( __TASKING__ )
+
+    #ifndef __ASM
+        #define __ASM               __asm
+    #endif
+
+    #ifndef __INLINE
+        #define __INLINE            inline
+    #endif
+
+    #ifndef __WEAK
+        #define __WEAK              __attribute__((weak))
+    #endif
+
+    #ifndef __ALIGN
+        #define __ALIGN(n)          __align(n)
+    #endif
+
+    #define GET_SP()                __get_MSP()
+
+#endif
+
+/*lint --flb "Leave library region" */
+
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h
new file mode 100644
index 0000000000..94df5c648b
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf.h
@@ -0,0 +1,75 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_H
+#define NRF_H
+
+/* MDK version */
+#define MDK_MAJOR_VERSION   8
+#define MDK_MINOR_VERSION   5
+#define MDK_MICRO_VERSION   0
+
+#if defined(_WIN32)
+    /* Do not include nrf51 specific files when building for PC host */
+#elif defined(__unix)
+    /* Do not include nrf51 specific files when building for PC host */
+#elif defined(__APPLE__)
+    /* Do not include nrf51 specific files when building for PC host */
+#else
+
+    /* Family selection for family includes. */
+    #if defined (NRF51)
+        #include "nrf51.h"
+        #include "nrf51_bitfields.h"
+        #include "nrf51_deprecated.h"
+    #elif defined (NRF52)
+        #include "nrf52.h"
+        #include "nrf52_bitfields.h"
+        #include "nrf51_to_nrf52.h"
+        #include "nrf52_name_change.h"
+    #else
+        #error "Device family must be defined. See nrf.h."
+    #endif /* NRF51, NRF52 */
+
+    #include "compiler_abstraction.h"
+
+#endif /* _WIN32 || __unix || __APPLE__ */
+
+#endif /* NRF_H */
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h
new file mode 100644
index 0000000000..0fae756197
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51.h
@@ -0,0 +1,1285 @@
+
+/****************************************************************************************************//**
+ * @file     nrf51.h
+ *
+ * @brief    CMSIS Cortex-M0 Peripheral Access Layer Header File for
+ *           nrf51 from Nordic Semiconductor.
+ *
+ * @version  V522
+ * @date     23. February 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf51.svd' Version 522,
+ *
+ * @par      Copyright (c) 2013, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf51
+  * @{
+  */
+
+#ifndef NRF51_H
+#define NRF51_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M0 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ----------------------  nrf51 Specific Interrupt Numbers  ---------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UART0_IRQn                    =   2,              /*!<   2  UART0                                                            */
+  SPI0_TWI0_IRQn                =   3,              /*!<   3  SPI0_TWI0                                                        */
+  SPI1_TWI1_IRQn                =   4,              /*!<   4  SPI1_TWI1                                                        */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  ADC_IRQn                      =   7,              /*!<   7  ADC                                                              */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  LPCOMP_IRQn                   =  19,              /*!<  19  LPCOMP                                                           */
+  SWI0_IRQn                     =  20,              /*!<  20  SWI0                                                             */
+  SWI1_IRQn                     =  21,              /*!<  21  SWI1                                                             */
+  SWI2_IRQn                     =  22,              /*!<  22  SWI2                                                             */
+  SWI3_IRQn                     =  23,              /*!<  23  SWI3                                                             */
+  SWI4_IRQn                     =  24,              /*!<  24  SWI4                                                             */
+  SWI5_IRQn                     =  25               /*!<  25  SWI5                                                             */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
+#define __CM0_REV                 0x0301            /*!< Cortex-M0 Core Revision                                               */
+#define __MPU_PRESENT                  0            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               2            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm0.h"                               /*!< Cortex-M0 processor and core peripherals                              */
+#include "system_nrf51.h"                           /*!< nrf51 System                                                          */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __IO uint32_t  CPU0;                              /*!< Configurable priority configuration register for CPU0.                */
+  __IO uint32_t  SPIS1;                             /*!< Configurable priority configuration register for SPIS1.               */
+  __IO uint32_t  RADIO;                             /*!< Configurable priority configuration register for RADIO.               */
+  __IO uint32_t  ECB;                               /*!< Configurable priority configuration register for ECB.                 */
+  __IO uint32_t  CCM;                               /*!< Configurable priority configuration register for CCM.                 */
+  __IO uint32_t  AAR;                               /*!< Configurable priority configuration register for AAR.                 */
+} AMLI_RAMPRI_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO.                                                  */
+} SPIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer.                                                         */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer bytes to receive.                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in the last transaction.                     */
+} SPIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer.                                                         */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer bytes to send.                               */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes sent in the last transaction.                         */
+} SPIM_TXD_Type;
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Enable channel group.                                                 */
+  __O  uint32_t  DIS;                               /*!< Disable channel group.                                                */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Channel event end-point.                                              */
+  __IO uint32_t  TEP;                               /*!< Channel task end-point.                                               */
+} PPI_CH_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power Control. (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode.                                         */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency).                             */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning.                                                */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason.                                                         */
+  __I  uint32_t  RESERVED4[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Ram status register.                                                  */
+  __I  uint32_t  RESERVED5[53];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System off register.                                                  */
+  __I  uint32_t  RESERVED6[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure configuration.                                          */
+  __I  uint32_t  RESERVED7[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register. This register is a retained
+                                                         register.                                                             */
+  __I  uint32_t  RESERVED8;
+  __IO uint32_t  RAMON;                             /*!< Ram on/off.                                                           */
+  __I  uint32_t  RESERVED9[7];
+  __IO uint32_t  RESET;                             /*!< Pin reset functionality configuration register. This register
+                                                         is a retained register.                                               */
+  __I  uint32_t  RESERVED10[3];
+  __IO uint32_t  RAMONB;                            /*!< Ram on/off.                                                           */
+  __I  uint32_t  RESERVED11[8];
+  __IO uint32_t  DCDCEN;                            /*!< DCDC converter enable configuration register.                         */
+  __I  uint32_t  RESERVED12[291];
+  __IO uint32_t  DCDCFORCE;                         /*!< DCDC power-up force register.                                         */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control. (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK clock source.                                             */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK clock source.                                              */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK clock source.                                             */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK clock source.                                              */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFCLK RC oscillator.                             */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer.                                              */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer.                                               */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started.                                             */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK oscillator started.                                             */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator completed.                         */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout.                                            */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Task HFCLKSTART trigger status.                                       */
+  __I  uint32_t  HFCLKSTAT;                         /*!< High frequency clock status.                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Task LFCLKSTART triggered status.                                     */
+  __I  uint32_t  LFCLKSTAT;                         /*!< Low frequency clock status.                                           */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
+                                                         triggered.                                                            */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK clock.                                     */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval.                                           */
+  __I  uint32_t  RESERVED7[5];
+  __IO uint32_t  XTALFREQ;                          /*!< Crystal frequency.                                                    */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                       MPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Protection Unit. (MPU)
+  */
+
+typedef struct {                                    /*!< MPU Structure                                                         */
+  __I  uint32_t  RESERVED0[330];
+  __IO uint32_t  PERR0;                             /*!< Configuration of peripherals in mpu regions.                          */
+  __IO uint32_t  RLENR0;                            /*!< Length of RAM region 0.                                               */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  PROTENSET0;                        /*!< Erase and write protection bit enable set register.                   */
+  __IO uint32_t  PROTENSET1;                        /*!< Erase and write protection bit enable set register.                   */
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable erase and write protection mechanism in debug mode.           */
+  __IO uint32_t  PROTBLOCKSIZE;                     /*!< Erase and write protection block size.                                */
+} NRF_MPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      AMLI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AHB Multi-Layer Interface. (AMLI)
+  */
+
+typedef struct {                                    /*!< AMLI Structure                                                        */
+  __I  uint32_t  RESERVED0[896];
+  AMLI_RAMPRI_Type RAMPRI;                          /*!< RAM configurable priority configuration structure.                    */
+} NRF_AMLI_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief The radio. (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable radio in TX mode.                                              */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable radio in RX mode.                                              */
+  __O  uint32_t  TASKS_START;                       /*!< Start radio.                                                          */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop radio.                                                           */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable radio.                                                        */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one sample of the receive signal strength.    */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement.                                            */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter.                                                */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter.                                                 */
+  __I  uint32_t  RESERVED0[55];
+  __IO uint32_t  EVENTS_READY;                      /*!< Ready event.                                                          */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address event.                                                        */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Payload event.                                                        */
+  __IO uint32_t  EVENTS_END;                        /*!< End event.                                                            */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< Disable event.                                                        */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet.          */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet.         */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of the receive signal strength complete. A new RSSI
+                                                         sample is ready for readout at the RSSISAMPLE register.               */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value specified in BCC register.        */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the radio.                                              */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED4[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status of received packet.                                        */
+  __I  uint32_t  RESERVED5;
+  __I  uint32_t  RXMATCH;                           /*!< Received address.                                                     */
+  __I  uint32_t  RXCRC;                             /*!< Received CRC.                                                         */
+  __I  uint32_t  DAI;                               /*!< Device address match index.                                           */
+  __I  uint32_t  RESERVED6[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer. Decision point: START task.                           */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency.                                                            */
+  __IO uint32_t  TXPOWER;                           /*!< Output power.                                                         */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation.                                             */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration 0.                                               */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration 1.                                               */
+  __IO uint32_t  BASE0;                             /*!< Radio base address 0. Decision point: START task.                     */
+  __IO uint32_t  BASE1;                             /*!< Radio base address 1. Decision point: START task.                     */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0 to 3.                          */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4 to 7.                          */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select.                                              */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select.                                               */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration.                                                    */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial.                                                       */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value.                                                    */
+  __IO uint32_t  TEST;                              /*!< Test features enable register.                                        */
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in microseconds.                                  */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample.                                                          */
+  __I  uint32_t  RESERVED7;
+  __I  uint32_t  STATE;                             /*!< Current radio state.                                                  */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value.                                         */
+  __I  uint32_t  RESERVED8[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare.                                                  */
+  __I  uint32_t  RESERVED9[39];
+  __IO uint32_t  DAB[8];                            /*!< Device address base segment.                                          */
+  __IO uint32_t  DAP[8];                            /*!< Device address prefix.                                                */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration.                                   */
+  __I  uint32_t  RESERVED10[56];
+  __IO uint32_t  OVERRIDE0;                         /*!< Trim value override register 0.                                       */
+  __IO uint32_t  OVERRIDE1;                         /*!< Trim value override register 1.                                       */
+  __IO uint32_t  OVERRIDE2;                         /*!< Trim value override register 2.                                       */
+  __IO uint32_t  OVERRIDE3;                         /*!< Trim value override register 3.                                       */
+  __IO uint32_t  OVERRIDE4;                         /*!< Trim value override register 4.                                       */
+  __I  uint32_t  RESERVED11[561];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter. (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver.                                                  */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver.                                                   */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter.                                               */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter.                                                */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART.                                                         */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS activated.                                                        */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS deactivated.                                                      */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD.                                                 */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD.                                                   */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected.                                                       */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout.                                                     */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for UART.                                                   */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source. Write error field to 1 to clear error.                  */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART and acquire IOs.                                          */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS.                                                   */
+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD.                                                   */
+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS.                                                   */
+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD.                                                   */
+  __I  uint32_t  RXD;                               /*!< RXD register. On read action the buffer pointer is displaced.
+                                                         Once read the character is consumed. If read when no character
+                                                          available, the UART will stop working.                               */
+  __O  uint32_t  TXD;                               /*!< TXD register.                                                         */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< UART Baudrate.                                                        */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control register.           */
+  __I  uint32_t  RESERVED12[675];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI master 0. (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received.                                  */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI.                                                           */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RX data.                                                              */
+  __IO uint32_t  TXD;                               /*!< TX data.                                                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED7[681];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Two-wire interface master 0. (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start 2-Wire master receive sequence.                                 */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start 2-Wire master transmit sequence.                                */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop 2-Wire transaction.                                              */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend 2-Wire transaction.                                           */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume 2-Wire transaction.                                            */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Two-wire stopped.                                                     */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< Two-wire ready to deliver new RXD byte received.                      */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< Two-wire finished sending last TXD byte.                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Two-wire error detected.                                              */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< Two-wire byte boundary.                                               */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Two-wire suspended.                                                   */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for TWI.                                                    */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Two-wire error source. Write error field to 1 to clear error.         */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable two-wire master.                                               */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL.                                                   */
+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA.                                                   */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RX data register.                                                     */
+  __IO uint32_t  TXD;                               /*!< TX data register.                                                     */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< Two-wire frequency.                                                   */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the two-wire transfer.                                */
+  __I  uint32_t  RESERVED16[668];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI slave 1. (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore.                                                */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore.                                                */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed.                                        */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired.                                                   */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for SPIS.                                                   */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status.                                                     */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction.                                         */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIS.                                                          */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELSCK;                           /*!< Pin select for SCK.                                                   */
+  __IO uint32_t  PSELMISO;                          /*!< Pin select for MISO.                                                  */
+  __IO uint32_t  PSELMOSI;                          /*!< Pin select for MOSI.                                                  */
+  __IO uint32_t  PSELCSN;                           /*!< Pin select for CSN.                                                   */
+  __I  uint32_t  RESERVED10[7];
+  __IO uint32_t  RXDPTR;                            /*!< RX data pointer.                                                      */
+  __IO uint32_t  MAXRX;                             /*!< Maximum number of bytes in the receive buffer.                        */
+  __I  uint32_t  AMOUNTRX;                          /*!< Number of bytes received in last granted transaction.                 */
+  __I  uint32_t  RESERVED11;
+  __IO uint32_t  TXDPTR;                            /*!< TX data pointer.                                                      */
+  __IO uint32_t  MAXTX;                             /*!< Maximum number of bytes in the transmit buffer.                       */
+  __I  uint32_t  AMOUNTTX;                          /*!< Number of bytes transmitted in last granted transaction.              */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character.                                                    */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
+  __I  uint32_t  RESERVED15[654];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI master with easyDMA 1. (SPIM)
+  */
+
+typedef struct {                                    /*!< SPIM Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction.                                                */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction.                                                 */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction.                                              */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction.                                               */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped.                                          */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached.                                            */
+  __I  uint32_t  RESERVED4[3];
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached.                                            */
+  __I  uint32_t  RESERVED5[10];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started.                                                  */
+  __I  uint32_t  RESERVED6[109];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED7[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM.                                                          */
+  __I  uint32_t  RESERVED8;
+  SPIM_PSEL_Type PSEL;                              /*!< Pin select configuration.                                             */
+  __I  uint32_t  RESERVED9[4];
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency.                                                        */
+  __I  uint32_t  RESERVED10[3];
+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA configuration and status.                                 */
+  __I  uint32_t  RESERVED11;
+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA configuration and status.                                 */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  ORC;                               /*!< Over-read character.                                                  */
+  __I  uint32_t  RESERVED14[654];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO tasks and events. (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_IN[4];                      /*!< Tasks asssociated with GPIOTE channels.                               */
+  __I  uint32_t  RESERVED1[27];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple pins.                                   */
+  __I  uint32_t  RESERVED2[97];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[129];
+  __IO uint32_t  CONFIG[4];                         /*!< Channel configuration registers.                                      */
+  __I  uint32_t  RESERVED4[695];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                       ADC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to digital converter. (ADC)
+  */
+
+typedef struct {                                    /*!< ADC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start an ADC conversion.                                              */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop ADC.                                                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_END;                        /*!< ADC conversion complete.                                              */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  BUSY;                              /*!< ADC busy register.                                                    */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< ADC enable.                                                           */
+  __IO uint32_t  CONFIG;                            /*!< ADC configuration register.                                           */
+  __I  uint32_t  RESULT;                            /*!< Result of ADC conversion.                                             */
+  __I  uint32_t  RESERVED4[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_ADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer 0. (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer.                                                          */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer.                                                           */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (In counter mode).                                    */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear timer.                                                          */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Shutdown timer.                                                       */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[4];                  /*!< Capture Timer value to CC[n] registers.                               */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
+  __I  uint32_t  RESERVED2[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for Timer.                                                  */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED4[126];
+  __IO uint32_t  MODE;                              /*!< Timer Mode selection.                                                 */
+  __IO uint32_t  BITMODE;                           /*!< Sets timer behaviour.                                                 */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  PRESCALER;                         /*!< 4-bit prescaler to source clock frequency (max value 9). Source
+                                                         clock frequency is divided by 2^SCALE.                                */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
+  __I  uint32_t  RESERVED7[683];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0. (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC Counter.                                                    */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC Counter.                                                     */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC Counter.                                                    */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFFFF0.                                            */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment.                                           */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow.                                            */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Compare event on CC[n] match.                                         */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Configures event enable routing to PPI for each RTC event.            */
+  __IO uint32_t  EVTENSET;                          /*!< Enable events routing to PPI. The reading of this register gives
+                                                         the value of EVTEN.                                                   */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable events routing to PPI. The reading of this register
+                                                         gives the value of EVTEN.                                             */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value.                                                */
+  __IO uint32_t  PRESCALER;                         /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
+                                                         Must be written when RTC is STOPed.                                   */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Capture/compare registers.                                            */
+  __I  uint32_t  RESERVED6[683];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor. (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement.                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement.                                         */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready event.                   */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision.   */
+  __I  uint32_t  RESERVED3[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator. (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the random number generator.                                    */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the random number generator.                                     */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< New random number generated and written to VALUE register.            */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the RNG.                                                */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register                                         */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register                                       */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  VALUE;                             /*!< RNG random number.                                                    */
+  __I  uint32_t  RESERVED4[700];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption. (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt. If a crypto operation is running, this
+                                                         will not initiate a new encryption and the ERRORECB event will
+                                                          be triggered.                                                        */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Stop current ECB encryption. If a crypto operation is running,
+                                                         this will will trigger the ERRORECB event.                            */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete.                                           */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted due to a STOPECB task or due to an
+                                                         error.                                                                */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointer.                                     */
+  __I  uint32_t  RESERVED3[701];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver. (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure.                                                       */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses.                                             */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure completed.                               */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved.                                                     */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved.                                                 */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status.                                                    */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR.                                                           */
+  __IO uint32_t  NIRK;                              /*!< Number of Identity root Keys in the IRK data structure.               */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to the IRK data structure.                                    */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address (6 bytes).                          */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during
+                                                         resolution. A minimum of 3 bytes must be reserved.                    */
+  __I  uint32_t  RESERVED6[697];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption. (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encrypt/decrypt. This operation will stop by itself when
+                                                         completed.                                                            */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encrypt/decrypt.                                                 */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Keystream generation completed.                                       */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt completed.                                            */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error happened.                                                       */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the CCM.                                                */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< CCM RX MIC check result.                                              */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< CCM enable.                                                           */
+  __IO uint32_t  MODE;                              /*!< Operation mode.                                                       */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to a data structure holding AES key and NONCE vector.         */
+  __IO uint32_t  INPTR;                             /*!< Pointer to the input packet.                                          */
+  __IO uint32_t  OUTPTR;                            /*!< Pointer to the output packet.                                         */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to a scratch data area used for temporary storage during
+                                                         resolution. A minimum of 43 bytes must be reserved.                   */
+  __I  uint32_t  RESERVED5[697];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer. (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog.                                                   */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout.                                                     */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Watchdog running status.                                              */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status.                                                       */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value in number of 32kiHz clock cycles.                */
+  __IO uint32_t  RREN;                              /*!< Reload request enable.                                                */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Reload requests registers.                                            */
+  __I  uint32_t  RESERVED5[631];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Rotary decoder. (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start the quadrature decoder.                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the quadrature decoder.                                          */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Transfers the content from ACC registers to ACCREAD registers,
+                                                         and clears the ACC registers.                                         */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< A new sample is written to the sample register.                       */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< REPORTPER number of samples accumulated in ACC register, and
+                                                         ACC register different than zero.                                     */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow.                                      */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the QDEC.                                               */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the QDEC.                                                      */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity.                                              */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period.                                                        */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value.                                                  */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to generate an EVENT_REPORTRDY.                     */
+  __I  int32_t   ACC;                               /*!< Accumulated valid transitions register.                               */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
+                                                         task.                                                                 */
+  __IO uint32_t  PSELLED;                           /*!< Pin select for LED output.                                            */
+  __IO uint32_t  PSELA;                             /*!< Pin select for phase A input.                                         */
+  __IO uint32_t  PSELB;                             /*!< Pin select for phase B input.                                         */
+  __IO uint32_t  DBFEN;                             /*!< Enable debouncer input filters.                                       */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time LED is switched ON before the sample.                            */
+  __I  uint32_t  ACCDBL;                            /*!< Accumulated double (error) transitions register.                      */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
+                                                         task.                                                                 */
+  __I  uint32_t  RESERVED5[684];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low power comparator. (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start the comparator.                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the comparator.                                                  */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value.                                              */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid.                                  */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Input voltage crossed the threshold going down.                       */
+  __IO uint32_t  EVENTS_UP;                         /*!< Input voltage crossed the threshold going up.                         */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Input voltage crossed the threshold in any direction.                 */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcuts for the LPCOMP.                                             */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Interrupt enable set register.                                        */
+  __IO uint32_t  INTENCLR;                          /*!< Interrupt enable clear register.                                      */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Result of last compare.                                               */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable the LPCOMP.                                                    */
+  __IO uint32_t  PSEL;                              /*!< Input pin select.                                                     */
+  __IO uint32_t  REFSEL;                            /*!< Reference select.                                                     */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select.                                            */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration.                                          */
+  __I  uint32_t  RESERVED6[694];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control.                                             */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SW Interrupts. (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller. (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag.                                                           */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register.                                               */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Register for erasing a non-protected non-volatile memory page.        */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a non-protected non-volatile memory page.        */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory.                    */
+  __IO uint32_t  ERASEPCR0;                         /*!< Register for erasing a protected non-volatile memory page.            */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for start erasing User Information Congfiguration Registers. */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief PPI controller. (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[4];                  /*!< Channel group tasks.                                                  */
+  __I  uint32_t  RESERVED0[312];
+  __IO uint32_t  CHEN;                              /*!< Channel enable.                                                       */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set.                                                   */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear.                                                 */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[16];                               /*!< PPI Channel.                                                          */
+  __I  uint32_t  RESERVED2[156];
+  __IO uint32_t  CHG[4];                            /*!< Channel group configuration.                                          */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration. (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size in bytes.                                       */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size in pages.                                            */
+  __I  uint32_t  RESERVED1[4];
+  __I  uint32_t  CLENR0;                            /*!< Length of code region 0 in bytes.                                     */
+  __I  uint32_t  PPFC;                              /*!< Pre-programmed factory code present.                                  */
+  __I  uint32_t  RESERVED2;
+  __I  uint32_t  NUMRAMBLOCK;                       /*!< Number of individualy controllable RAM blocks.                        */
+  
+  union {
+    __I  uint32_t  SIZERAMBLOCK[4];                 /*!< Deprecated array of size of RAM block in bytes. This name is
+                                                         kept for backward compatinility purposes. Use SIZERAMBLOCKS
+                                                          instead.                                                             */
+    __I  uint32_t  SIZERAMBLOCKS;                   /*!< Size of RAM blocks in bytes.                                          */
+  };
+  __I  uint32_t  RESERVED3[5];
+  __I  uint32_t  CONFIGID;                          /*!< Configuration identifier.                                             */
+  __I  uint32_t  DEVICEID[2];                       /*!< Device identifier.                                                    */
+  __I  uint32_t  RESERVED4[6];
+  __I  uint32_t  ER[4];                             /*!< Encryption root.                                                      */
+  __I  uint32_t  IR[4];                             /*!< Identity root.                                                        */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type.                                                  */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Device address.                                                       */
+  __I  uint32_t  OVERRIDEEN;                        /*!< Radio calibration override enable.                                    */
+  __I  uint32_t  NRF_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
+                                                         mode.                                                                 */
+  __I  uint32_t  RESERVED5[10];
+  __I  uint32_t  BLE_1MBIT[5];                      /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
+                                                         mode.                                                                 */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration. (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  CLENR0;                            /*!< Length of code region 0.                                              */
+  __IO uint32_t  RBPCONF;                           /*!< Readback protection configuration.                                    */
+  __IO uint32_t  XTALFREQ;                          /*!< Reset value for CLOCK XTALFREQ register.                              */
+  __I  uint32_t  RESERVED0;
+  __I  uint32_t  FWID;                              /*!< Firmware ID.                                                          */
+  
+  union {
+    __IO uint32_t  NRFFW[15];                       /*!< Reserved for Nordic firmware design.                                  */
+    __IO uint32_t  BOOTLOADERADDR;                  /*!< Bootloader start address.                                             */
+  };
+  __IO uint32_t  NRFHW[12];                         /*!< Reserved for Nordic hardware design.                                  */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Reserved for customer.                                                */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief General purpose input and output. (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port.                                                      */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port.                                     */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port.                                   */
+  __I  uint32_t  IN;                                /*!< Read GPIO port.                                                       */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins.                                               */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register.                                                     */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register.                                                   */
+  __I  uint32_t  RESERVED1[120];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Configuration of GPIO pins.                                           */
+} NRF_GPIO_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_MPU_BASE                    0x40000000UL
+#define NRF_AMLI_BASE                   0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_SPIM1_BASE                  0x40004000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_ADC_BASE                    0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI_BASE                    0x40014000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_GPIO_BASE                   0x50000000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_MPU                         ((NRF_MPU_Type            *) NRF_MPU_BASE)
+#define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_ADC                         ((NRF_ADC_Type            *) NRF_ADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI                         ((NRF_SWI_Type            *) NRF_SWI_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_GPIO                        ((NRF_GPIO_Type           *) NRF_GPIO_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf51 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf51_H */
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h
new file mode 100644
index 0000000000..f9b512fef7
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_bitfields.h
@@ -0,0 +1,6901 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef __NRF51_BITS_H
+#define __NRF51_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver. */
+
+/* Register: AAR_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on RESOLVED event. */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: AAR_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on RESOLVED event. */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status. */
+
+/* Bits 3..0 : The IRK used last time an address was resolved. */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR. */
+
+/* Bits 1..0 : Enable AAR. */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
+#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
+
+/* Register: AAR_NIRK */
+/* Description: Number of Identity root Keys in the IRK data structure. */
+
+/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: ADC */
+/* Description: Analog to digital converter. */
+
+/* Register: ADC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on END event. */
+#define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ADC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on END event. */
+#define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ADC_BUSY */
+/* Description: ADC busy register. */
+
+/* Bit 0 : ADC busy register. */
+#define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
+#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
+#define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
+#define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
+
+/* Register: ADC_ENABLE */
+/* Description: ADC enable. */
+
+/* Bits 1..0 : ADC enable. */
+#define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
+#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
+
+/* Register: ADC_CONFIG */
+/* Description: ADC configuration register. */
+
+/* Bits 17..16 : ADC external reference pin selection. */
+#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
+#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
+
+/* Bits 15..8 : ADC analog pin selection. */
+#define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
+#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
+#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
+
+/* Bits 6..5 : ADC reference selection. */
+#define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
+#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
+#define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
+#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
+#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
+
+/* Bits 4..2 : ADC input selection. */
+#define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
+#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
+#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
+#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
+
+/* Bits 1..0 : ADC resolution. */
+#define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
+#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
+#define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
+#define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
+#define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
+
+/* Register: ADC_RESULT */
+/* Description: Result of ADC conversion. */
+
+/* Bits 9..0 : Result of ADC conversion. */
+#define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+
+/* Register: ADC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: AMLI */
+/* Description: AHB Multi-Layer Interface. */
+
+/* Register: AMLI_RAMPRI_CPU0 */
+/* Description: Configurable priority configuration register for CPU0. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_SPIS1 */
+/* Description: Configurable priority configuration register for SPIS1. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_RADIO */
+/* Description: Configurable priority configuration register for RADIO. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_ECB */
+/* Description: Configurable priority configuration register for ECB. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_CCM */
+/* Description: Configurable priority configuration register for CCM. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Register: AMLI_RAMPRI_AAR */
+/* Description: Configurable priority configuration register for AAR. */
+
+/* Bits 31..28 : Configuration field for RAM block 7. */
+#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 27..24 : Configuration field for RAM block 6. */
+#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 23..20 : Configuration field for RAM block 5. */
+#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 19..16 : Configuration field for RAM block 4. */
+#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 15..12 : Configuration field for RAM block 3. */
+#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 11..8 : Configuration field for RAM block 2. */
+#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 7..4 : Configuration field for RAM block 1. */
+#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /*!< Priority 14. */
+
+/* Bits 3..0 : Configuration field for RAM block 0. */
+#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /*!< Priority 0. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /*!< Priority 2. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /*!< Priority 4. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /*!< Priority 6. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /*!< Priority 8. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /*!< Priority 10. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /*!< Priority 12. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /*!< Priority 14. */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption. */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcuts for the CCM. */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: CCM_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ERROR event. */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ENDCRYPT event. */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDKSGEN event. */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CCM_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ERROR event. */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ENDCRYPT event. */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDKSGEN event. */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CCM_MICSTATUS */
+/* Description: CCM RX MIC check result. */
+
+/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
+
+/* Register: CCM_ENABLE */
+/* Description: CCM enable. */
+
+/* Bits 1..0 : CCM enable. */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
+#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode. */
+
+/* Bit 0 : CCM mode operation. */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
+
+/* Register: CCM_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control. */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 4 : Enable interrupt on CTTO event. */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on DONE event. */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 4 : Disable interrupt on CTTO event. */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on DONE event. */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Task HFCLKSTART trigger status. */
+
+/* Bit 0 : Task HFCLKSTART trigger status. */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task HFCLKSTART has not been triggered. */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task HFCLKSTART has been triggered. */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: High frequency clock status. */
+
+/* Bit 16 : State for the HFCLK. */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
+
+/* Bit 0 : Active clock source for the HF clock. */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Task LFCLKSTART triggered status. */
+
+/* Bit 0 : Task LFCLKSTART triggered status. */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task LFCLKSTART has not been triggered. */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task LFCLKSTART has been triggered. */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: Low frequency clock status. */
+
+/* Bit 16 : State for the LF clock. */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
+
+/* Bits 1..0 : Active clock source for the LF clock. */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+
+/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK clock. */
+
+/* Bits 1..0 : Clock source. */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval. */
+
+/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_XTALFREQ */
+/* Description: Crystal frequency. */
+
+/* Bits 7..0 : External Xtal frequency selection. */
+#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used as source for the HFCLK oscillator. */
+#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used as source for the HFCLK oscillator. */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption. */
+
+/* Register: ECB_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 1 : Enable interrupt on ERRORECB event. */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on ENDECB event. */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: ECB_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 1 : Disable interrupt on ERRORECB event. */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on ENDECB event. */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: ECB_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration. */
+
+/* Register: FICR_PPFC */
+/* Description: Pre-programmed factory code present. */
+
+/* Bits 7..0 : Pre-programmed factory code present. */
+#define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
+#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
+#define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
+#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
+
+/* Register: FICR_CONFIGID */
+/* Description: Configuration identifier. */
+
+/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
+#define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
+#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+/* Bits 15..0 : Hardware Identification Number. */
+#define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
+#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type. */
+
+/* Bit 0 : Device address type. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
+
+/* Register: FICR_OVERRIDEEN */
+/* Description: Radio calibration override enable. */
+
+/* Bit 3 : Override default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
+#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
+
+/* Bit 0 : Override default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /*!< Position of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /*!< Bit mask of NRF_1MBIT field. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /*!< Override the default values for NRF_1Mbit mode. */
+#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /*!< Do not override the default values for NRF_1Mbit mode. */
+
+
+/* Peripheral: GPIO */
+/* Description: General purpose input and output. */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins. */
+
+/* Bit 31 : Pin 31. */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 30 : Pin 30. */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 29 : Pin 29. */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 28 : Pin 28. */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 27 : Pin 27. */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 26 : Pin 26. */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 25 : Pin 25. */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 24 : Pin 24. */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 23 : Pin 23. */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 22 : Pin 22. */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 21 : Pin 21. */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 20 : Pin 20. */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 19 : Pin 19. */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 18 : Pin 18. */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 17 : Pin 17. */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 16 : Pin 16. */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 15 : Pin 15. */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 14 : Pin 14. */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 13 : Pin 13. */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 12 : Pin 12. */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 11 : Pin 11. */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 10 : Pin 10. */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 9 : Pin 9. */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 8 : Pin 8. */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 7 : Pin 7. */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 6 : Pin 6. */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 5 : Pin 5. */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 4 : Pin 4. */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 3 : Pin 3. */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 2 : Pin 2. */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 1 : Pin 1. */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
+
+/* Bit 0 : Pin 0. */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register. */
+
+/* Bit 31 : Set as output pin 31. */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 30 : Set as output pin 30. */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 29 : Set as output pin 29. */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 28 : Set as output pin 28. */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 27 : Set as output pin 27. */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 26 : Set as output pin 26. */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 25 : Set as output pin 25. */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 24 : Set as output pin 24. */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 23 : Set as output pin 23. */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 22 : Set as output pin 22. */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 21 : Set as output pin 21. */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 20 : Set as output pin 20. */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 19 : Set as output pin 19. */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 18 : Set as output pin 18. */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 17 : Set as output pin 17. */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 16 : Set as output pin 16. */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 15 : Set as output pin 15. */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 14 : Set as output pin 14. */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 13 : Set as output pin 13. */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 12 : Set as output pin 12. */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 11 : Set as output pin 11. */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 10 : Set as output pin 10. */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 9 : Set as output pin 9. */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 8 : Set as output pin 8. */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 7 : Set as output pin 7. */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 6 : Set as output pin 6. */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 5 : Set as output pin 5. */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 4 : Set as output pin 4. */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 3 : Set as output pin 3. */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 2 : Set as output pin 2. */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 1 : Set as output pin 1. */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
+
+/* Bit 0 : Set as output pin 0. */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register. */
+
+/* Bit 31 : Set as input pin 31. */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 30 : Set as input pin 30. */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 29 : Set as input pin 29. */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 28 : Set as input pin 28. */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 27 : Set as input pin 27. */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 26 : Set as input pin 26. */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 25 : Set as input pin 25. */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 24 : Set as input pin 24. */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 23 : Set as input pin 23. */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 22 : Set as input pin 22. */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 21 : Set as input pin 21. */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 20 : Set as input pin 20. */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 19 : Set as input pin 19. */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 18 : Set as input pin 18. */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 17 : Set as input pin 17. */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 16 : Set as input pin 16. */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 15 : Set as input pin 15. */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 14 : Set as input pin 14. */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 13 : Set as input pin 13. */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 12 : Set as input pin 12. */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 11 : Set as input pin 11. */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 10 : Set as input pin 10. */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 9 : Set as input pin 9. */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 8 : Set as input pin 8. */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 7 : Set as input pin 7. */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 6 : Set as input pin 6. */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 5 : Set as input pin 5. */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 4 : Set as input pin 4. */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 3 : Set as input pin 3. */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 2 : Set as input pin 2. */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 1 : Set as input pin 1. */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
+
+/* Bit 0 : Set as input pin 0. */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Configuration of GPIO pins. */
+
+/* Bits 17..16 : Pin sensing mechanism. */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
+#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
+
+/* Bits 10..8 : Drive configuration. */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
+
+/* Bits 3..2 : Pull-up or -down configuration. */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
+#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
+#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
+
+/* Bit 1 : Connect or disconnect input path. */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
+
+/* Bit 0 : Pin direction. */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO tasks and events. */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 31 : Enable interrupt on PORT event. */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on IN[3] event. */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on IN[2] event. */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on IN[1] event. */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on IN[0] event. */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 31 : Disable interrupt on PORT event. */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on IN[3] event. */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on IN[2] event. */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on IN[1] event. */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on IN[0] event. */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Channel configuration registers. */
+
+/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
+
+/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0x00UL) /*!< No task or event. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
+
+/* Bits 12..8 : Pin select. */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
+#define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
+#define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
+
+/* Register: GPIOTE_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low power comparator. */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcuts for the LPCOMP. */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task. */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between UP event and STOP task. */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task. */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between RADY event and STOP task. */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 3 : Enable interrupt on CROSS event. */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on UP event. */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on DOWN event. */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 3 : Disable interrupt on CROSS event. */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on UP event. */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on DOWN event. */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Result of last compare. */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable the LPCOMP. */
+
+/* Bits 1..0 : Enable or disable LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
+#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select. */
+
+/* Bits 2..0 : Analog input pin select. */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select. */
+
+/* Bits 2..0 : Reference select. */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use supply with a 1/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use supply with a 2/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use supply with a 3/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use supply with a 4/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use supply with a 5/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use supply with a 6/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use supply with a 7/8 prescaler as reference. */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select. */
+
+/* Bit 0 : External analog reference pin selection. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration. */
+
+/* Bits 1..0 : Analog detect configuration. */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
+
+/* Register: LPCOMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: MPU */
+/* Description: Memory Protection Unit. */
+
+/* Register: MPU_PERR0 */
+/* Description: Configuration of peripherals in mpu regions. */
+
+/* Bit 31 : PPI region configuration. */
+#define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
+#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
+#define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 30 : NVMC region configuration. */
+#define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
+#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
+#define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 19 : LPCOMP region configuration. */
+#define MPU_PERR0_LPCOMP_Pos (19UL) /*!< Position of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 18 : QDEC region configuration. */
+#define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
+#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
+#define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 17 : RTC1 region configuration. */
+#define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
+#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
+#define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 16 : WDT region configuration. */
+#define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
+#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
+#define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 15 : CCM and AAR region configuration. */
+#define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
+#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 14 : ECB region configuration. */
+#define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
+#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
+#define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 13 : RNG region configuration. */
+#define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
+#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
+#define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 12 : TEMP region configuration. */
+#define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
+#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
+#define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 11 : RTC0 region configuration. */
+#define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
+#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
+#define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 10 : TIMER2 region configuration. */
+#define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
+#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
+#define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 9 : TIMER1 region configuration. */
+#define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
+#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
+#define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 8 : TIMER0 region configuration. */
+#define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
+#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
+#define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 7 : ADC region configuration. */
+#define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
+#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
+#define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 6 : GPIOTE region configuration. */
+#define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
+#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 4 : SPI1 and TWI1 region configuration. */
+#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
+#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 3 : SPI0 and TWI0 region configuration. */
+#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
+#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 2 : UART0 region configuration. */
+#define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
+#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
+#define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 1 : RADIO region configuration. */
+#define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
+#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
+#define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Bit 0 : POWER_CLOCK region configuration. */
+#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
+#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
+#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
+
+/* Register: MPU_PROTENSET0 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 31. */
+#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
+#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 30. */
+#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
+#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 29. */
+#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
+#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 28. */
+#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
+#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 27. */
+#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
+#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 26. */
+#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
+#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 25. */
+#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
+#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 24. */
+#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
+#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 23. */
+#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
+#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 22. */
+#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
+#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 21. */
+#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
+#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 20. */
+#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
+#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 19. */
+#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
+#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 18. */
+#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
+#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 17. */
+#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
+#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 16. */
+#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
+#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 15. */
+#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
+#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 14. */
+#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
+#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 13. */
+#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
+#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 12. */
+#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
+#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 11. */
+#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
+#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 10. */
+#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
+#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 9. */
+#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
+#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 8. */
+#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
+#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 7. */
+#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
+#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 6. */
+#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
+#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 5. */
+#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
+#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 4. */
+#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
+#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 3. */
+#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
+#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 2. */
+#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
+#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 1. */
+#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
+#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 0. */
+#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
+#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_PROTENSET1 */
+/* Description: Erase and write protection bit enable set register. */
+
+/* Bit 31 : Protection enable for region 63. */
+#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
+#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 30 : Protection enable for region 62. */
+#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
+#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 29 : Protection enable for region 61. */
+#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
+#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 28 : Protection enable for region 60. */
+#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
+#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 27 : Protection enable for region 59. */
+#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
+#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 26 : Protection enable for region 58. */
+#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
+#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 25 : Protection enable for region 57. */
+#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
+#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 24 : Protection enable for region 56. */
+#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
+#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 23 : Protection enable for region 55. */
+#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
+#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 22 : Protection enable for region 54. */
+#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
+#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 21 : Protection enable for region 53. */
+#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
+#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 20 : Protection enable for region 52. */
+#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
+#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 19 : Protection enable for region 51. */
+#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
+#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 18 : Protection enable for region 50. */
+#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
+#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 17 : Protection enable for region 49. */
+#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
+#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 16 : Protection enable for region 48. */
+#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
+#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 15 : Protection enable for region 47. */
+#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
+#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 14 : Protection enable for region 46. */
+#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
+#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 13 : Protection enable for region 45. */
+#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
+#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 12 : Protection enable for region 44. */
+#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
+#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 11 : Protection enable for region 43. */
+#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
+#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 10 : Protection enable for region 42. */
+#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
+#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 9 : Protection enable for region 41. */
+#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
+#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 8 : Protection enable for region 40. */
+#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
+#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 7 : Protection enable for region 39. */
+#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
+#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 6 : Protection enable for region 38. */
+#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
+#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 5 : Protection enable for region 37. */
+#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
+#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 4 : Protection enable for region 36. */
+#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
+#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 3 : Protection enable for region 35. */
+#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
+#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 2 : Protection enable for region 34. */
+#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
+#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 1 : Protection enable for region 33. */
+#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
+#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
+
+/* Bit 0 : Protection enable for region 32. */
+#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
+#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
+#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
+#define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
+
+/* Register: MPU_DISABLEINDEBUG */
+/* Description: Disable erase and write protection mechanism in debug mode. */
+
+/* Bit 0 : Disable protection mechanism in debug mode. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
+
+/* Register: MPU_PROTBLOCKSIZE */
+/* Description: Erase and write protection block size. */
+
+/* Bits 1..0 : Erase and write protection block size. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /*!< Position of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /*!< Bit mask of PROTBLOCKSIZE field. */
+#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /*!< Erase and write protection block size is 4k. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller. */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag. */
+
+/* Bit 0 : NVMC ready. */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register. */
+
+/* Bits 1..0 : Program write enable. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
+#define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
+#define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory. */
+
+/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for start erasing User Information Congfiguration Registers. */
+
+/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
+
+
+/* Peripheral: POWER */
+/* Description: Power Control. */
+
+/* Register: POWER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on POFWARN event. */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: POWER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on POFWARN event. */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason. */
+
+/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 3 : Reset from CPU lock-up detected. */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 1 : Reset from watchdog detected. */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Reset detected. */
+
+/* Bit 0 : Reset from pin-reset detected. */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Reset not detected. */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Reset detected. */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Ram status register. */
+
+/* Bit 3 : RAM block 3 status. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< RAM block 3 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< RAM block 3 is on. */
+
+/* Bit 2 : RAM block 2 status. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< RAM block 2 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< RAM block 2 is on. */
+
+/* Bit 1 : RAM block 1 status. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< RAM block 1 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< RAM block 1 is on. */
+
+/* Bit 0 : RAM block 0 status. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< RAM block 0 is off or powering up. */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< RAM block 0 is on. */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System off register. */
+
+/* Bit 0 : Enter system off mode. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure configuration. */
+
+/* Bits 2..1 : Set threshold level. */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
+#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
+#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
+#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
+
+/* Bit 0 : Power failure comparator enable. */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register. This register is a retained register. */
+
+/* Bits 7..0 : General purpose retention register. */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 1 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
+
+/* Bit 16 : RAM block 0 behaviour in OFF mode. */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
+
+/* Bit 1 : RAM block 1 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
+
+/* Bit 0 : RAM block 0 behaviour in ON mode. */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
+
+/* Register: POWER_RESET */
+/* Description: Pin reset functionality configuration register. This register is a retained register. */
+
+/* Bit 0 : Enable or disable pin reset in debug interface mode. */
+#define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
+#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
+#define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
+#define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
+
+/* Register: POWER_RAMONB */
+/* Description: Ram on/off. */
+
+/* Bit 17 : RAM block 3 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
+
+/* Bit 16 : RAM block 2 behaviour in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
+
+/* Bit 1 : RAM block 3 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< RAM block 33 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
+
+/* Bit 0 : RAM block 2 behaviour in ON mode. */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
+
+/* Register: POWER_DCDCEN */
+/* Description: DCDC converter enable configuration register. */
+
+/* Bit 0 : Enable DCDC converter. */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
+
+/* Register: POWER_DCDCFORCE */
+/* Description: DCDC power-up force register. */
+
+/* Bit 1 : DCDC power-up force on. */
+#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /*!< Position of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /*!< Bit mask of FORCEON field. */
+#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEON_Force (1UL) /*!< Force. */
+
+/* Bit 0 : DCDC power-up force off. */
+#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /*!< Position of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /*!< Bit mask of FORCEOFF field. */
+#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /*!< No force. */
+#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /*!< Force. */
+
+
+/* Peripheral: PPI */
+/* Description: PPI controller. */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set. */
+
+/* Bit 31 : Enable PPI channel 31. */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 30 : Enable PPI channel 30. */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 29 : Enable PPI channel 29. */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 28 : Enable PPI channel 28. */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 27 : Enable PPI channel 27. */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 26 : Enable PPI channel 26. */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 25 : Enable PPI channel 25. */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 24 : Enable PPI channel 24. */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 23 : Enable PPI channel 23. */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 22 : Enable PPI channel 22. */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 21 : Enable PPI channel 21. */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 20 : Enable PPI channel 20. */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 15 : Enable PPI channel 15. */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 14 : Enable PPI channel 14. */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 13 : Enable PPI channel 13. */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 12 : Enable PPI channel 12. */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 11 : Enable PPI channel 11. */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 10 : Enable PPI channel 10. */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 9 : Enable PPI channel 9. */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 8 : Enable PPI channel 8. */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 7 : Enable PPI channel 7. */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 6 : Enable PPI channel 6. */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 5 : Enable PPI channel 5. */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 4 : Enable PPI channel 4. */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 3 : Enable PPI channel 3. */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 2 : Enable PPI channel 2. */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 1 : Enable PPI channel 1. */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
+
+/* Bit 0 : Enable PPI channel 0. */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear. */
+
+/* Bit 31 : Disable PPI channel 31. */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 30 : Disable PPI channel 30. */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 29 : Disable PPI channel 29. */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 28 : Disable PPI channel 28. */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 27 : Disable PPI channel 27. */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 26 : Disable PPI channel 26. */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 25 : Disable PPI channel 25. */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 24 : Disable PPI channel 24. */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 23 : Disable PPI channel 23. */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 22 : Disable PPI channel 22. */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 21 : Disable PPI channel 21. */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 20 : Disable PPI channel 20. */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 15 : Disable PPI channel 15. */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 14 : Disable PPI channel 14. */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 13 : Disable PPI channel 13. */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 12 : Disable PPI channel 12. */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 11 : Disable PPI channel 11. */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 10 : Disable PPI channel 10. */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 9 : Disable PPI channel 9. */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 8 : Disable PPI channel 8. */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 7 : Disable PPI channel 7. */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 6 : Disable PPI channel 6. */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 5 : Disable PPI channel 5. */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 4 : Disable PPI channel 4. */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 3 : Disable PPI channel 3. */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 2 : Disable PPI channel 2. */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 1 : Disable PPI channel 1. */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
+
+/* Bit 0 : Disable PPI channel 0. */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
+
+/* Register: PPI_CHG */
+/* Description: Channel group configuration. */
+
+/* Bit 31 : Include CH31 in channel group. */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
+
+/* Bit 30 : Include CH30 in channel group. */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
+
+/* Bit 29 : Include CH29 in channel group. */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
+
+/* Bit 28 : Include CH28 in channel group. */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
+
+/* Bit 27 : Include CH27 in channel group. */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
+
+/* Bit 26 : Include CH26 in channel group. */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
+
+/* Bit 25 : Include CH25 in channel group. */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
+
+/* Bit 24 : Include CH24 in channel group. */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
+
+/* Bit 23 : Include CH23 in channel group. */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
+
+/* Bit 22 : Include CH22 in channel group. */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
+
+/* Bit 21 : Include CH21 in channel group. */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
+
+/* Bit 20 : Include CH20 in channel group. */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
+
+/* Bit 15 : Include CH15 in channel group. */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
+
+/* Bit 14 : Include CH14 in channel group. */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
+
+/* Bit 13 : Include CH13 in channel group. */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
+
+/* Bit 12 : Include CH12 in channel group. */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
+
+/* Bit 11 : Include CH11 in channel group. */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
+
+/* Bit 10 : Include CH10 in channel group. */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
+
+/* Bit 9 : Include CH9 in channel group. */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
+
+/* Bit 8 : Include CH8 in channel group. */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
+
+/* Bit 7 : Include CH7 in channel group. */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
+
+/* Bit 6 : Include CH6 in channel group. */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
+
+/* Bit 5 : Include CH5 in channel group. */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
+
+/* Bit 4 : Include CH4 in channel group. */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
+
+/* Bit 3 : Include CH3 in channel group. */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
+
+/* Bit 2 : Include CH2 in channel group. */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
+
+/* Bit 1 : Include CH1 in channel group. */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
+
+/* Bit 0 : Include CH0 in channel group. */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
+#define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
+
+
+/* Peripheral: QDEC */
+/* Description: Rotary decoder. */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcuts for the QDEC. */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: QDEC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on ACCOF event. */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on REPORTRDY event. */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on SAMPLERDY event. */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on ACCOF event. */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on REPORTRDY event. */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on SAMPLERDY event. */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the QDEC. */
+
+/* Bit 0 : Enable or disable QDEC. */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity. */
+
+/* Bit 0 : LED output pin polarity. */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period. */
+
+/* Bits 2..0 : Sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value. */
+
+/* Bits 31..0 : Last sample taken in compliment to 2. */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to generate an EVENT_REPORTRDY. */
+
+/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable debouncer input filters. */
+
+/* Bit 0 : Enable debounce input filters. */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time LED is switched ON before the sample. */
+
+/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Accumulated double (error) transitions register. */
+
+/* Bits 3..0 : Accumulated double (error) transitions. */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
+
+/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+/* Register: QDEC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RADIO */
+/* Description: The radio. */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcuts for the radio. */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 5 : Shortcut between END event and START task. */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task.  */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between END event and DISABLE task. */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between READY event and START task. */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RADIO_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on BCMATCH event. */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on RSSIEND event. */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 6 : Enable interrupt on DEVMISS event. */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 5 : Enable interrupt on DEVMATCH event. */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : Enable interrupt on DISABLED event. */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 3 : Enable interrupt on END event. */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on PAYLOAD event. */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on ADDRESS event. */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on READY event. */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on BCMATCH event. */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on RSSIEND event. */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 6 : Disable interrupt on DEVMISS event. */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 5 : Disable interrupt on DEVMATCH event. */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on DISABLED event. */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 3 : Disable interrupt on END event. */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on PAYLOAD event. */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on ADDRESS event. */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on READY event. */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status of received packet. */
+
+/* Bit 0 : CRC status of received packet. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address. */
+
+/* Bits 2..0 : Logical address in which previous packet was received. */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: Received CRC. */
+
+/* Bits 23..0 : CRC field of previously received packet. */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index. */
+
+/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency. */
+
+/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task.  */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power. */
+
+/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation. */
+
+/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
+#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration 0. */
+
+/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration 1. */
+
+/* Bit 25 : Packet whitening enable. */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
+
+/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0 to 3. */
+
+/* Bits 31..24 : Address prefix 3. Decision point: START task. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. Decision point: START task. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. Decision point: START task. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. Decision point: START task. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4 to 7. */
+
+/* Bits 31..24 : Address prefix 7. Decision point: START task. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. Decision point: START task. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. Decision point: START task. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. Decision point: START task. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select. */
+
+/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select. */
+
+/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
+
+/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration. */
+
+/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length. Decision point: START task. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial. */
+
+/* Bits 23..0 : CRC polynomial. Decision point: START task. */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value. */
+
+/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TEST */
+/* Description: Test features enable register. */
+
+/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
+#define RADIO_TEST_PLLLOCK_Pos (1UL) /*!< Position of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /*!< Bit mask of PLLLOCK field. */
+#define RADIO_TEST_PLLLOCK_Disabled (0UL) /*!< PLL lock disabled. */
+#define RADIO_TEST_PLLLOCK_Enabled (1UL) /*!< PLL lock enabled. */
+
+/* Bit 0 : Constant carrier. Decision point: TXEN task. */
+#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /*!< Position of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /*!< Bit mask of CONSTCARRIER field. */
+#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
+#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in microseconds. */
+
+/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample. */
+
+/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state. */
+
+/* Bits 3..0 : Current radio state. */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
+#define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
+#define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
+#define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
+#define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
+#define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
+#define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
+#define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
+#define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value. */
+
+/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_DAP */
+/* Description: Device address prefix. */
+
+/* Bits 15..0 : Device address prefix. */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration. */
+
+/* Bit 15 : TxAdd for device address 7. */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6. */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5. */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4. */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3. */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2. */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1. */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0. */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7. */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 6 : Enable or disable device address matching using device address 6. */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 5 : Enable or disable device address matching using device address 5. */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 4 : Enable or disable device address matching using device address 4. */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 3 : Enable or disable device address matching using device address 3. */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 2 : Enable or disable device address matching using device address 2. */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 1 : Enable or disable device address matching using device address 1. */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
+
+/* Bit 0 : Enable or disable device address matching using device address 0. */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
+
+/* Register: RADIO_OVERRIDE0 */
+/* Description: Trim value override register 0. */
+
+/* Bits 31..0 : Trim value override 0. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
+#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
+
+/* Register: RADIO_OVERRIDE1 */
+/* Description: Trim value override register 1. */
+
+/* Bits 31..0 : Trim value override 1. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
+#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
+
+/* Register: RADIO_OVERRIDE2 */
+/* Description: Trim value override register 2. */
+
+/* Bits 31..0 : Trim value override 2. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
+#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
+
+/* Register: RADIO_OVERRIDE3 */
+/* Description: Trim value override register 3. */
+
+/* Bits 31..0 : Trim value override 3. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
+#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
+
+/* Register: RADIO_OVERRIDE4 */
+/* Description: Trim value override register 4. */
+
+/* Bit 31 : Enable or disable override of default trim values. */
+#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
+#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
+
+/* Bits 27..0 : Trim value override 4. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
+#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator. */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcuts for the RNG. */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task. */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: RNG_INTENSET */
+/* Description: Interrupt enable set register */
+
+/* Bit 0 : Enable interrupt on VALRDY event. */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RNG_INTENCLR */
+/* Description: Interrupt enable clear register */
+
+/* Bit 0 : Disable interrupt on VALRDY event. */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 0 : Digital error correction enable. */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
+
+/* Register: RNG_VALUE */
+/* Description: RNG random number. */
+
+/* Bits 7..0 : Generated random number. */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+/* Register: RNG_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0. */
+
+/* Register: RTC_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] event. */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] event. */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] event. */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] event. */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on OVRFLW event. */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on TICK event. */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: RTC_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] event. */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] event. */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] event. */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] event. */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on OVRFLW event. */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on TICK event. */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: RTC_EVTEN */
+/* Description: Configures event enable routing to PPI for each RTC event. */
+
+/* Bit 19 : COMPARE[3] event enable. */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 18 : COMPARE[2] event enable. */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 17 : COMPARE[1] event enable. */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 16 : COMPARE[0] event enable. */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 1 : OVRFLW event enable. */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+
+/* Bit 0 : TICK event enable. */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 1 : Enable routing to PPI of OVRFLW event. */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
+
+/* Bit 0 : Enable routing to PPI of TICK event. */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
+
+/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 1 : Disable routing to PPI of OVRFLW event. */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
+
+/* Bit 0 : Disable routing to PPI of TICK event. */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value. */
+
+/* Bits 23..0 : Counter value. */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
+
+/* Bits 11..0 : RTC PRESCALER value. */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Capture/compare registers. */
+
+/* Bits 23..0 : Compare value. */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+/* Register: RTC_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPI */
+/* Description: SPI master 0. */
+
+/* Register: SPI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 2 : Disable interrupt on READY event. */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI. */
+
+/* Bits 2..0 : Enable or disable SPI. */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
+#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
+
+/* Register: SPI_RXD */
+/* Description: RX data. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TX data. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI data rate. */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPIM */
+/* Description: SPI master with easyDMA 1. */
+
+/* Register: SPIM_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on STARTED event. */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 8 : Enable interrupt on ENDTX event. */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : Enable interrupt on ENDRX event. */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on STOPPED event. */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on STARTED event. */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 8 : Disable interrupt on ENDTX event. */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on ENDRX event. */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on STOPPED event. */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM. */
+
+/* Bits 3..0 : Enable or disable SPIM. */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIM. */
+#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /*!< Enable SPIM. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency. */
+
+/* Bits 31..0 : SPI master data rate. */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps. */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps. */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps. */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer. */
+
+/* Bits 31..0 : Data pointer. */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of buffer bytes to receive. */
+
+/* Bits 7..0 : Maximum number of buffer bytes to receive. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes received in the last transaction. */
+
+/* Bits 7..0 : Number of bytes received in the last transaction. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer. */
+
+/* Bits 31..0 : Data pointer. */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of buffer bytes to send. */
+
+/* Bits 7..0 : Maximum number of buffer bytes to send. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes sent in the last transaction. */
+
+/* Bits 7..0 : Number of bytes sent in the last transaction. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. */
+
+/* Bits 7..0 : Over-read character. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+/* Register: SPIM_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPIM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPIM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPIM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI slave 1. */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcuts for SPIS. */
+
+/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: SPIS_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 10 : Enable interrupt on ACQUIRED event. */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 4 : enable interrupt on ENDRX event. */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on END event. */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 10 : Disable interrupt on ACQUIRED event. */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 4 : Disable interrupt on ENDRX event. */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on END event. */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status. */
+
+/* Bits 1..0 : Semaphore status. */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction. */
+
+/* Bit 1 : RX buffer overflow detected, and prevented. */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
+
+/* Bit 0 : TX buffer overread detected, and prevented. */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPIS. */
+
+/* Bits 2..0 : Enable or disable SPIS. */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
+#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
+
+/* Register: SPIS_MAXRX */
+/* Description: Maximum number of bytes in the receive buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
+#define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
+#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
+
+/* Register: SPIS_AMOUNTRX */
+/* Description: Number of bytes received in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes received in last granted transaction. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
+
+/* Register: SPIS_MAXTX */
+/* Description: Maximum number of bytes in the transmit buffer. */
+
+/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
+#define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
+#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
+
+/* Register: SPIS_AMOUNTTX */
+/* Description: Number of bytes transmitted in last granted transaction. */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 2 : Serial clock (SCK) polarity. */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
+
+/* Bit 1 : Serial clock (SCK) phase. */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
+
+/* Bit 0 : Bit order. */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. */
+
+/* Bits 7..0 : Default character. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character. */
+
+/* Bits 7..0 : Over-read character. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+/* Register: SPIS_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor. */
+
+/* Register: TEMP_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on DATARDY event. */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on DATARDY event. */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TEMP_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer 0. */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcuts for Timer. */
+
+/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TIMER_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 19 : Enable interrupt on COMPARE[3] */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 18 : Enable interrupt on COMPARE[2] */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 17 : Enable interrupt on COMPARE[1] */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 16 : Enable interrupt on COMPARE[0] */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 19 : Disable interrupt on COMPARE[3] */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 18 : Disable interrupt on COMPARE[2] */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 17 : Disable interrupt on COMPARE[1] */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 16 : Disable interrupt on COMPARE[0] */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TIMER_MODE */
+/* Description: Timer Mode selection. */
+
+/* Bit 0 : Select Normal or Counter mode. */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
+
+/* Register: TIMER_BITMODE */
+/* Description: Sets timer behaviour. */
+
+/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
+#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
+
+/* Register: TIMER_PRESCALER */
+/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
+
+/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: TWI */
+/* Description: Two-wire interface master 0. */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcuts for TWI. */
+
+/* Bit 1 : Shortcut between BB event and the STOP task. */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: TWI_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 18 : Enable interrupt on SUSPENDED event. */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 14 : Enable interrupt on BB event. */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXDSENT event. */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on READY event. */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on STOPPED event. */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: TWI_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 18 : Disable interrupt on SUSPENDED event. */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 14 : Disable interrupt on BB event. */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXDSENT event. */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXDREADY event. */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on STOPPED event. */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Two-wire error source. Write error field to 1 to clear error. */
+
+/* Bit 2 : NACK received after sending a data byte. */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : NACK received after sending the address. */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : Byte received in RXD register before read of the last received byte (data loss). */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define TWI_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable two-wire master. */
+
+/* Bits 2..0 : Enable or disable W2M */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
+#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
+
+/* Register: TWI_RXD */
+/* Description: RX data register. */
+
+/* Bits 7..0 : RX data from last transfer. */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TX data register. */
+
+/* Bits 7..0 : TX data for next transfer. */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: Two-wire frequency. */
+
+/* Bits 31..0 : Two-wire master clock frequency. */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the two-wire transfer. */
+
+/* Bits 6..0 : Two-wire address. */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWI_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter. */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcuts for UART. */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task. */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task. */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
+
+/* Register: UART_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 17 : Enable interrupt on RXTO event. */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 9 : Enable interrupt on ERROR event. */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 7 : Enable interrupt on TXRDY event. */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 2 : Enable interrupt on RXRDY event. */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 1 : Enable interrupt on NCTS event. */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Bit 0 : Enable interrupt on CTS event. */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: UART_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 17 : Disable interrupt on RXTO event. */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 9 : Disable interrupt on ERROR event. */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 7 : Disable interrupt on TXRDY event. */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 2 : Disable interrupt on RXRDY event. */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 1 : Disable interrupt on NCTS event. */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Bit 0 : Disable interrupt on CTS event. */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source. Write error field to 1 to clear error. */
+
+/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
+
+/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
+#define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART and acquire IOs. */
+
+/* Bits 2..0 : Enable or disable UART and acquire IOs. */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
+#define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
+
+/* Register: UART_RXD */
+/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
+
+/* Bits 7..0 : RX data from previous transfer. Double buffered. */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register. */
+
+/* Bits 7..0 : TX data for transfer. */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: UART Baudrate. */
+
+/* Bits 31..0 : UART baudrate. */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud. */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control register. */
+
+/* Bits 3..1 : Include parity bit. */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
+#define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
+
+/* Bit 0 : Hardware flow control. */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
+
+/* Register: UART_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration. */
+
+/* Register: UICR_RBPCONF */
+/* Description: Readback protection configuration. */
+
+/* Bits 15..8 : Readback protect all code in the device. */
+#define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
+#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
+#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
+
+/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
+#define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
+#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
+#define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
+#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
+
+/* Register: UICR_XTALFREQ */
+/* Description: Reset value for CLOCK XTALFREQ register. */
+
+/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
+#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
+#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
+#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
+
+/* Register: UICR_FWID */
+/* Description: Firmware ID. */
+
+/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
+#define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
+#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer. */
+
+/* Register: WDT_INTENSET */
+/* Description: Interrupt enable set register. */
+
+/* Bit 0 : Enable interrupt on TIMEOUT event. */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
+
+/* Register: WDT_INTENCLR */
+/* Description: Interrupt enable clear register. */
+
+/* Bit 0 : Disable interrupt on TIMEOUT event. */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Watchdog running status. */
+
+/* Bit 0 : Watchdog running status. */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status. */
+
+/* Bit 7 : Request status for RR[7]. */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
+
+/* Bit 6 : Request status for RR[6]. */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
+
+/* Bit 5 : Request status for RR[5]. */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
+
+/* Bit 4 : Request status for RR[4]. */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
+
+/* Bit 3 : Request status for RR[3]. */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
+
+/* Bit 2 : Request status for RR[2]. */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
+
+/* Bit 1 : Request status for RR[1]. */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
+
+/* Bit 0 : Request status for RR[0]. */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
+
+/* Register: WDT_RREN */
+/* Description: Reload request enable. */
+
+/* Bit 7 : Enable or disable RR[7] register. */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
+
+/* Bit 6 : Enable or disable RR[6] register. */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
+
+/* Bit 5 : Enable or disable RR[5] register. */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
+
+/* Bit 4 : Enable or disable RR[4] register. */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
+
+/* Bit 3 : Enable or disable RR[3] register. */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
+
+/* Bit 2 : Enable or disable RR[2] register. */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
+
+/* Bit 1 : Enable or disable RR[1] register. */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
+
+/* Bit 0 : Enable or disable RR[0] register. */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register. */
+
+/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
+
+/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
+
+/* Register: WDT_RR */
+/* Description: Reload requests registers. */
+
+/* Bits 31..0 : Reload register. */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
+
+/* Register: WDT_POWER */
+/* Description: Peripheral power control. */
+
+/* Bit 0 : Peripheral power control. */
+#define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
+#define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_deprecated.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_deprecated.h
new file mode 100644
index 0000000000..81bd149663
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_deprecated.h
@@ -0,0 +1,447 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF51_DEPRECATED_H
+#define NRF51_DEPRECATED_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf51.h and 
+ * nrf51_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf51.h and nrf51_bitfields.h instead.
+ */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE is called ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE   ERASEPCR0
+
+ 
+/* LPCOMP */
+/* The interrupt ISR was renamed. Adding old name to the macros. */
+#define LPCOMP_COMP_IRQHandler      LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn            LPCOMP_IRQn
+ 
+ 
+/* MPU */
+/* The field MPU.PERR0.LPCOMP_COMP was renamed. Added into deprecated in case somebody was using the macros defined for it. */
+#define MPU_PERR0_LPCOMP_COMP_Pos           MPU_PERR0_LPCOMP_Pos
+#define MPU_PERR0_LPCOMP_COMP_Msk           MPU_PERR0_LPCOMP_Msk
+#define MPU_PERR0_LPCOMP_COMP_InRegion1     MPU_PERR0_LPCOMP_InRegion1
+#define MPU_PERR0_LPCOMP_COMP_InRegion0     MPU_PERR0_LPCOMP_InRegion0
+ 
+ 
+/* POWER */
+/* The field POWER.RAMON.OFFRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM3_Pos         (19UL)                                  
+#define POWER_RAMON_OFFRAM3_Msk         (0x1UL << POWER_RAMON_OFFRAM3_Pos)      
+#define POWER_RAMON_OFFRAM3_RAM3Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM3_RAM3On      (1UL)                                   
+/* The field POWER.RAMON.OFFRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_OFFRAM2_Pos         (18UL)                                  
+#define POWER_RAMON_OFFRAM2_Msk         (0x1UL << POWER_RAMON_OFFRAM2_Pos)      
+#define POWER_RAMON_OFFRAM2_RAM2Off     (0UL)                                   
+#define POWER_RAMON_OFFRAM2_RAM2On      (1UL)                                  
+/* The field POWER.RAMON.ONRAM3 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM3_Pos          (3UL)                                  
+#define POWER_RAMON_ONRAM3_Msk          (0x1UL << POWER_RAMON_ONRAM3_Pos)      
+#define POWER_RAMON_ONRAM3_RAM3Off      (0UL)                                  
+#define POWER_RAMON_ONRAM3_RAM3On       (1UL)                                  
+/* The field POWER.RAMON.ONRAM2 was eliminated. Added into deprecated in case somebody was using the macros defined for it. */
+#define POWER_RAMON_ONRAM2_Pos          (2UL)                                  
+#define POWER_RAMON_ONRAM2_Msk          (0x1UL << POWER_RAMON_ONRAM2_Pos)       
+#define POWER_RAMON_ONRAM2_RAM2Off      (0UL)                                  
+#define POWER_RAMON_ONRAM2_RAM2On       (1UL)                                 
+
+ 
+/* RADIO */
+/* The enumerated value RADIO.TXPOWER.TXPOWER.Neg40dBm was renamed. Added into deprecated with the new macro name. */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm  RADIO_TXPOWER_TXPOWER_Neg30dBm      
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos 
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk 
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include 
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip 
+/* The name of the field PLLLOCK was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_PLL_LOCK_Pos         RADIO_TEST_PLLLOCK_Pos 
+#define RADIO_TEST_PLL_LOCK_Msk         RADIO_TEST_PLLLOCK_Msk 
+#define RADIO_TEST_PLL_LOCK_Disabled    RADIO_TEST_PLLLOCK_Disabled 
+#define RADIO_TEST_PLL_LOCK_Enabled     RADIO_TEST_PLLLOCK_Enabled 
+/* The name of the field CONSTCARRIER was corrected. Old macros added for compatibility. */
+#define RADIO_TEST_CONST_CARRIER_Pos        RADIO_TEST_CONSTCARRIER_Pos 
+#define RADIO_TEST_CONST_CARRIER_Msk        RADIO_TEST_CONSTCARRIER_Msk 
+#define RADIO_TEST_CONST_CARRIER_Disabled   RADIO_TEST_CONSTCARRIER_Disabled 
+#define RADIO_TEST_CONST_CARRIER_Enabled    RADIO_TEST_CONSTCARRIER_Enabled 
+
+
+/* FICR */
+/* The registers FICR.SIZERAMBLOCK0, FICR.SIZERAMBLOCK1, FICR.SIZERAMBLOCK2 and FICR.SIZERAMBLOCK3 were renamed into an array. */
+#define SIZERAMBLOCK0   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK1   SIZERAMBLOCKS                   
+#define SIZERAMBLOCK2   SIZERAMBLOCK[2]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+#define SIZERAMBLOCK3   SIZERAMBLOCK[3]                 /*!< Note that this macro will disapear when SIZERAMBLOCK array is eliminated. SIZERAMBLOCK is a deprecated array. */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]                     
+#define DEVICEID1       DEVICEID[1]                     
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]                           
+#define ER1             ER[1]                          
+#define ER2             ER[2]                       
+#define ER3             ER[3]                      
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]                         
+#define IR1             IR[1]                         
+#define IR2             IR[2]                         
+#define IR3             IR[3]                          
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]                  
+#define DEVICEADDR1     DEVICEADDR[1]                  
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN                    
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS                  
+#define TASKS_CHG1EN     TASKS_CHG[1].EN                    
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS                  
+#define TASKS_CHG2EN     TASKS_CHG[2].EN                   
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS                  
+#define TASKS_CHG3EN     TASKS_CHG[3].EN                    
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS                  
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP                          
+#define CH0_TEP          CH[0].TEP                          
+#define CH1_EEP          CH[1].EEP                         
+#define CH1_TEP          CH[1].TEP                         
+#define CH2_EEP          CH[2].EEP                          
+#define CH2_TEP          CH[2].TEP                         
+#define CH3_EEP          CH[3].EEP                          
+#define CH3_TEP          CH[3].TEP                         
+#define CH4_EEP          CH[4].EEP                         
+#define CH4_TEP          CH[4].TEP                         
+#define CH5_EEP          CH[5].EEP                          
+#define CH5_TEP          CH[5].TEP                          
+#define CH6_EEP          CH[6].EEP                          
+#define CH6_TEP          CH[6].TEP                         
+#define CH7_EEP          CH[7].EEP                          
+#define CH7_TEP          CH[7].TEP                          
+#define CH8_EEP          CH[8].EEP                         
+#define CH8_TEP          CH[8].TEP                          
+#define CH9_EEP          CH[9].EEP                          
+#define CH9_TEP          CH[9].TEP                          
+#define CH10_EEP         CH[10].EEP                         
+#define CH10_TEP         CH[10].TEP                         
+#define CH11_EEP         CH[11].EEP                         
+#define CH11_TEP         CH[11].TEP                         
+#define CH12_EEP         CH[12].EEP                         
+#define CH12_TEP         CH[12].TEP                         
+#define CH13_EEP         CH[13].EEP                         
+#define CH13_TEP         CH[13].TEP                         
+#define CH14_EEP         CH[14].EEP                         
+#define CH14_TEP         CH[14].TEP                         
+#define CH15_EEP         CH[15].EEP                         
+#define CH15_TEP         CH[15].TEP                        
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]                            
+#define CHG1             CHG[1]                            
+#define CHG2             CHG[2]                             
+#define CHG3             CHG[3]                           
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos            
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included       
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos            
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos            
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included       
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded       
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included       
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos             
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk             
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included        
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos             
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded        
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk             
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included        
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded        
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded       
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos            
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded       
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk            
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk           
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included      
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included      
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos           
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk             
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included        
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk            
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included       
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk            
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded      
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos           
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded       
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included      
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded       
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded      
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos           
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk           
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded       
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded        
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk            
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included        
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos            
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded       
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos            
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk            
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included       
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos            
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk            
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded       
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included        
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk             
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included       
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos            
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded       
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included       
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos            
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk           
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded       
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded       
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included       
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos            
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk            
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded       
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included        
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos           
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk           
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded     
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included      
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos          
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk           
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded      
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included       
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos           
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk            
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded      
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included      
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos            
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk            
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded       
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included       
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos            
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk            
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded      
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included       
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos            
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk            
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded      
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included      
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos            
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk            
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded       
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included       
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos            
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk             
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded       
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included       
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos             
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk            
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded        
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included       
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos             
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk             
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded       
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included        
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos             
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk             
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded        
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included       
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos             
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk            
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded        
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included        
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos             
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk            
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded        
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included        
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos             
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk             
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded        
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included       
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos             
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk             
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded        
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included        
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos             
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk             
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded        
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included        
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_DEPRECATED_H */
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h
new file mode 100644
index 0000000000..a74b165a2b
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf51_to_nrf52.h
@@ -0,0 +1,944 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF51_TO_NRF52_H
+#define NRF51_TO_NRF52_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the name changes between nRF51 and nRF52 devices.
+ * It redefines the old nRF51 names into the new ones as long as the functionality is still supported. If the
+ * functionality is gone, there old names are not define, so compilation will fail. Note that also includes macros
+ * from the nrf51_deprecated.h file. */
+
+
+/* IRQ */
+/* Several peripherals have been added to several indexes. Names of IRQ handlers and IRQ numbers have changed. */
+#define UART0_IRQHandler        UARTE0_UART0_IRQHandler
+#define SPI0_TWI0_IRQHandler    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+#define SPI1_TWI1_IRQHandler    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#define ADC_IRQHandler          SAADC_IRQHandler
+#define LPCOMP_IRQHandler       COMP_LPCOMP_IRQHandler
+#define SWI0_IRQHandler         SWI0_EGU0_IRQHandler
+#define SWI1_IRQHandler         SWI1_EGU1_IRQHandler
+#define SWI2_IRQHandler         SWI2_EGU2_IRQHandler
+#define SWI3_IRQHandler         SWI3_EGU3_IRQHandler
+#define SWI4_IRQHandler         SWI4_EGU4_IRQHandler
+#define SWI5_IRQHandler         SWI5_EGU5_IRQHandler
+
+#define UART0_IRQn              UARTE0_UART0_IRQn
+#define SPI0_TWI0_IRQn          SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+#define SPI1_TWI1_IRQn          SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+#define ADC_IRQn                SAADC_IRQn
+#define LPCOMP_IRQn             COMP_LPCOMP_IRQn
+#define SWI0_IRQn               SWI0_EGU0_IRQn
+#define SWI1_IRQn               SWI1_EGU1_IRQn
+#define SWI2_IRQn               SWI2_EGU2_IRQn
+#define SWI3_IRQn               SWI3_EGU3_IRQn
+#define SWI4_IRQn               SWI4_EGU4_IRQn
+#define SWI5_IRQn               SWI5_EGU5_IRQn
+
+
+/* UICR */
+/* Register RBPCONF was renamed to APPROTECT. */
+#define RBPCONF     APPROTECT
+
+#define UICR_RBPCONF_PALL_Pos           UICR_APPROTECT_PALL_Pos
+#define UICR_RBPCONF_PALL_Msk           UICR_APPROTECT_PALL_Msk
+#define UICR_RBPCONF_PALL_Enabled       UICR_APPROTECT_PALL_Enabled
+#define UICR_RBPCONF_PALL_Disabled      UICR_APPROTECT_PALL_Disabled
+
+
+/* GPIO */
+/* GPIO port was renamed to P0. */
+#define NRF_GPIO        NRF_P0
+#define NRF_GPIO_BASE   NRF_P0_BASE
+
+
+/* SPIS */
+/* The registers PSELSCK, PSELMISO, PSELMOSI, PSELCSN were restructured into a struct. */
+#define PSELSCK       PSEL.SCK
+#define PSELMISO      PSEL.MISO
+#define PSELMOSI      PSEL.MOSI
+#define PSELCSN       PSEL.CSN
+
+/* The registers RXDPTR, MAXRX, AMOUNTRX were restructured into a struct */
+#define RXDPTR        RXD.PTR
+#define MAXRX         RXD.MAXCNT
+#define AMOUNTRX      RXD.AMOUNT
+
+#define SPIS_MAXRX_MAXRX_Pos        SPIS_RXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXRX_MAXRX_Msk        SPIS_RXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTRX_AMOUNTRX_Pos  SPIS_RXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTRX_AMOUNTRX_Msk  SPIS_RXD_AMOUNT_AMOUNT_Msk
+
+/* The registers TXDPTR, MAXTX, AMOUNTTX were restructured into a struct */
+#define TXDPTR        TXD.PTR
+#define MAXTX         TXD.MAXCNT
+#define AMOUNTTX      TXD.AMOUNT
+
+#define SPIS_MAXTX_MAXTX_Pos        SPIS_TXD_MAXCNT_MAXCNT_Pos
+#define SPIS_MAXTX_MAXTX_Msk        SPIS_TXD_MAXCNT_MAXCNT_Msk
+
+#define SPIS_AMOUNTTX_AMOUNTTX_Pos  SPIS_TXD_AMOUNT_AMOUNT_Pos
+#define SPIS_AMOUNTTX_AMOUNTTX_Msk  SPIS_TXD_AMOUNT_AMOUNT_Msk
+
+
+/* MPU */
+/* Part of MPU module was renamed BPROT, while the rest was eliminated. */
+#define NRF_MPU     NRF_BPROT
+
+/* Register DISABLEINDEBUG macros were affected. */
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos       BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk       BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled   BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled
+#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled  BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled
+
+/* Registers PROTENSET0 and PROTENSET1 were affected and renamed as CONFIG0 and CONFIG1. */
+#define PROTENSET0  CONFIG0
+#define PROTENSET1  CONFIG1
+
+#define MPU_PROTENSET1_PROTREG63_Pos        BPROT_CONFIG1_REGION63_Pos
+#define MPU_PROTENSET1_PROTREG63_Msk        BPROT_CONFIG1_REGION63_Msk
+#define MPU_PROTENSET1_PROTREG63_Disabled   BPROT_CONFIG1_REGION63_Disabled
+#define MPU_PROTENSET1_PROTREG63_Enabled    BPROT_CONFIG1_REGION63_Enabled
+#define MPU_PROTENSET1_PROTREG63_Set        BPROT_CONFIG1_REGION63_Enabled
+
+#define MPU_PROTENSET1_PROTREG62_Pos        BPROT_CONFIG1_REGION62_Pos
+#define MPU_PROTENSET1_PROTREG62_Msk        BPROT_CONFIG1_REGION62_Msk
+#define MPU_PROTENSET1_PROTREG62_Disabled   BPROT_CONFIG1_REGION62_Disabled
+#define MPU_PROTENSET1_PROTREG62_Enabled    BPROT_CONFIG1_REGION62_Enabled
+#define MPU_PROTENSET1_PROTREG62_Set        BPROT_CONFIG1_REGION62_Enabled
+
+#define MPU_PROTENSET1_PROTREG61_Pos        BPROT_CONFIG1_REGION61_Pos
+#define MPU_PROTENSET1_PROTREG61_Msk        BPROT_CONFIG1_REGION61_Msk
+#define MPU_PROTENSET1_PROTREG61_Disabled   BPROT_CONFIG1_REGION61_Disabled
+#define MPU_PROTENSET1_PROTREG61_Enabled    BPROT_CONFIG1_REGION61_Enabled
+#define MPU_PROTENSET1_PROTREG61_Set        BPROT_CONFIG1_REGION61_Enabled
+
+#define MPU_PROTENSET1_PROTREG60_Pos        BPROT_CONFIG1_REGION60_Pos
+#define MPU_PROTENSET1_PROTREG60_Msk        BPROT_CONFIG1_REGION60_Msk
+#define MPU_PROTENSET1_PROTREG60_Disabled   BPROT_CONFIG1_REGION60_Disabled
+#define MPU_PROTENSET1_PROTREG60_Enabled    BPROT_CONFIG1_REGION60_Enabled
+#define MPU_PROTENSET1_PROTREG60_Set        BPROT_CONFIG1_REGION60_Enabled
+
+#define MPU_PROTENSET1_PROTREG59_Pos        BPROT_CONFIG1_REGION59_Pos
+#define MPU_PROTENSET1_PROTREG59_Msk        BPROT_CONFIG1_REGION59_Msk
+#define MPU_PROTENSET1_PROTREG59_Disabled   BPROT_CONFIG1_REGION59_Disabled
+#define MPU_PROTENSET1_PROTREG59_Enabled    BPROT_CONFIG1_REGION59_Enabled
+#define MPU_PROTENSET1_PROTREG59_Set        BPROT_CONFIG1_REGION59_Enabled
+
+#define MPU_PROTENSET1_PROTREG58_Pos        BPROT_CONFIG1_REGION58_Pos
+#define MPU_PROTENSET1_PROTREG58_Msk        BPROT_CONFIG1_REGION58_Msk
+#define MPU_PROTENSET1_PROTREG58_Disabled   BPROT_CONFIG1_REGION58_Disabled
+#define MPU_PROTENSET1_PROTREG58_Enabled    BPROT_CONFIG1_REGION58_Enabled
+#define MPU_PROTENSET1_PROTREG58_Set        BPROT_CONFIG1_REGION58_Enabled
+
+#define MPU_PROTENSET1_PROTREG57_Pos        BPROT_CONFIG1_REGION57_Pos
+#define MPU_PROTENSET1_PROTREG57_Msk        BPROT_CONFIG1_REGION57_Msk
+#define MPU_PROTENSET1_PROTREG57_Disabled   BPROT_CONFIG1_REGION57_Disabled
+#define MPU_PROTENSET1_PROTREG57_Enabled    BPROT_CONFIG1_REGION57_Enabled
+#define MPU_PROTENSET1_PROTREG57_Set        BPROT_CONFIG1_REGION57_Enabled
+
+#define MPU_PROTENSET1_PROTREG56_Pos        BPROT_CONFIG1_REGION56_Pos
+#define MPU_PROTENSET1_PROTREG56_Msk        BPROT_CONFIG1_REGION56_Msk
+#define MPU_PROTENSET1_PROTREG56_Disabled   BPROT_CONFIG1_REGION56_Disabled
+#define MPU_PROTENSET1_PROTREG56_Enabled    BPROT_CONFIG1_REGION56_Enabled
+#define MPU_PROTENSET1_PROTREG56_Set        BPROT_CONFIG1_REGION56_Enabled
+
+#define MPU_PROTENSET1_PROTREG55_Pos        BPROT_CONFIG1_REGION55_Pos
+#define MPU_PROTENSET1_PROTREG55_Msk        BPROT_CONFIG1_REGION55_Msk
+#define MPU_PROTENSET1_PROTREG55_Disabled   BPROT_CONFIG1_REGION55_Disabled
+#define MPU_PROTENSET1_PROTREG55_Enabled    BPROT_CONFIG1_REGION55_Enabled
+#define MPU_PROTENSET1_PROTREG55_Set        BPROT_CONFIG1_REGION55_Enabled
+
+#define MPU_PROTENSET1_PROTREG54_Pos        BPROT_CONFIG1_REGION54_Pos
+#define MPU_PROTENSET1_PROTREG54_Msk        BPROT_CONFIG1_REGION54_Msk
+#define MPU_PROTENSET1_PROTREG54_Disabled   BPROT_CONFIG1_REGION54_Disabled
+#define MPU_PROTENSET1_PROTREG54_Enabled    BPROT_CONFIG1_REGION54_Enabled
+#define MPU_PROTENSET1_PROTREG54_Set        BPROT_CONFIG1_REGION54_Enabled
+
+#define MPU_PROTENSET1_PROTREG53_Pos        BPROT_CONFIG1_REGION53_Pos
+#define MPU_PROTENSET1_PROTREG53_Msk        BPROT_CONFIG1_REGION53_Msk
+#define MPU_PROTENSET1_PROTREG53_Disabled   BPROT_CONFIG1_REGION53_Disabled
+#define MPU_PROTENSET1_PROTREG53_Enabled    BPROT_CONFIG1_REGION53_Enabled
+#define MPU_PROTENSET1_PROTREG53_Set        BPROT_CONFIG1_REGION53_Enabled
+
+#define MPU_PROTENSET1_PROTREG52_Pos        BPROT_CONFIG1_REGION52_Pos
+#define MPU_PROTENSET1_PROTREG52_Msk        BPROT_CONFIG1_REGION52_Msk
+#define MPU_PROTENSET1_PROTREG52_Disabled   BPROT_CONFIG1_REGION52_Disabled
+#define MPU_PROTENSET1_PROTREG52_Enabled    BPROT_CONFIG1_REGION52_Enabled
+#define MPU_PROTENSET1_PROTREG52_Set        BPROT_CONFIG1_REGION52_Enabled
+
+#define MPU_PROTENSET1_PROTREG51_Pos        BPROT_CONFIG1_REGION51_Pos
+#define MPU_PROTENSET1_PROTREG51_Msk        BPROT_CONFIG1_REGION51_Msk
+#define MPU_PROTENSET1_PROTREG51_Disabled   BPROT_CONFIG1_REGION51_Disabled
+#define MPU_PROTENSET1_PROTREG51_Enabled    BPROT_CONFIG1_REGION51_Enabled
+#define MPU_PROTENSET1_PROTREG51_Set        BPROT_CONFIG1_REGION51_Enabled
+
+#define MPU_PROTENSET1_PROTREG50_Pos        BPROT_CONFIG1_REGION50_Pos
+#define MPU_PROTENSET1_PROTREG50_Msk        BPROT_CONFIG1_REGION50_Msk
+#define MPU_PROTENSET1_PROTREG50_Disabled   BPROT_CONFIG1_REGION50_Disabled
+#define MPU_PROTENSET1_PROTREG50_Enabled    BPROT_CONFIG1_REGION50_Enabled
+#define MPU_PROTENSET1_PROTREG50_Set        BPROT_CONFIG1_REGION50_Enabled
+
+#define MPU_PROTENSET1_PROTREG49_Pos        BPROT_CONFIG1_REGION49_Pos
+#define MPU_PROTENSET1_PROTREG49_Msk        BPROT_CONFIG1_REGION49_Msk
+#define MPU_PROTENSET1_PROTREG49_Disabled   BPROT_CONFIG1_REGION49_Disabled
+#define MPU_PROTENSET1_PROTREG49_Enabled    BPROT_CONFIG1_REGION49_Enabled
+#define MPU_PROTENSET1_PROTREG49_Set        BPROT_CONFIG1_REGION49_Enabled
+
+#define MPU_PROTENSET1_PROTREG48_Pos        BPROT_CONFIG1_REGION48_Pos
+#define MPU_PROTENSET1_PROTREG48_Msk        BPROT_CONFIG1_REGION48_Msk
+#define MPU_PROTENSET1_PROTREG48_Disabled   BPROT_CONFIG1_REGION48_Disabled
+#define MPU_PROTENSET1_PROTREG48_Enabled    BPROT_CONFIG1_REGION48_Enabled
+#define MPU_PROTENSET1_PROTREG48_Set        BPROT_CONFIG1_REGION48_Enabled
+
+#define MPU_PROTENSET1_PROTREG47_Pos        BPROT_CONFIG1_REGION47_Pos
+#define MPU_PROTENSET1_PROTREG47_Msk        BPROT_CONFIG1_REGION47_Msk
+#define MPU_PROTENSET1_PROTREG47_Disabled   BPROT_CONFIG1_REGION47_Disabled
+#define MPU_PROTENSET1_PROTREG47_Enabled    BPROT_CONFIG1_REGION47_Enabled
+#define MPU_PROTENSET1_PROTREG47_Set        BPROT_CONFIG1_REGION47_Enabled
+
+#define MPU_PROTENSET1_PROTREG46_Pos        BPROT_CONFIG1_REGION46_Pos
+#define MPU_PROTENSET1_PROTREG46_Msk        BPROT_CONFIG1_REGION46_Msk
+#define MPU_PROTENSET1_PROTREG46_Disabled   BPROT_CONFIG1_REGION46_Disabled
+#define MPU_PROTENSET1_PROTREG46_Enabled    BPROT_CONFIG1_REGION46_Enabled
+#define MPU_PROTENSET1_PROTREG46_Set        BPROT_CONFIG1_REGION46_Enabled
+
+#define MPU_PROTENSET1_PROTREG45_Pos        BPROT_CONFIG1_REGION45_Pos
+#define MPU_PROTENSET1_PROTREG45_Msk        BPROT_CONFIG1_REGION45_Msk
+#define MPU_PROTENSET1_PROTREG45_Disabled   BPROT_CONFIG1_REGION45_Disabled
+#define MPU_PROTENSET1_PROTREG45_Enabled    BPROT_CONFIG1_REGION45_Enabled
+#define MPU_PROTENSET1_PROTREG45_Set        BPROT_CONFIG1_REGION45_Enabled
+
+#define MPU_PROTENSET1_PROTREG44_Pos        BPROT_CONFIG1_REGION44_Pos
+#define MPU_PROTENSET1_PROTREG44_Msk        BPROT_CONFIG1_REGION44_Msk
+#define MPU_PROTENSET1_PROTREG44_Disabled   BPROT_CONFIG1_REGION44_Disabled
+#define MPU_PROTENSET1_PROTREG44_Enabled    BPROT_CONFIG1_REGION44_Enabled
+#define MPU_PROTENSET1_PROTREG44_Set        BPROT_CONFIG1_REGION44_Enabled
+
+#define MPU_PROTENSET1_PROTREG43_Pos        BPROT_CONFIG1_REGION43_Pos
+#define MPU_PROTENSET1_PROTREG43_Msk        BPROT_CONFIG1_REGION43_Msk
+#define MPU_PROTENSET1_PROTREG43_Disabled   BPROT_CONFIG1_REGION43_Disabled
+#define MPU_PROTENSET1_PROTREG43_Enabled    BPROT_CONFIG1_REGION43_Enabled
+#define MPU_PROTENSET1_PROTREG43_Set        BPROT_CONFIG1_REGION43_Enabled
+
+#define MPU_PROTENSET1_PROTREG42_Pos        BPROT_CONFIG1_REGION42_Pos
+#define MPU_PROTENSET1_PROTREG42_Msk        BPROT_CONFIG1_REGION42_Msk
+#define MPU_PROTENSET1_PROTREG42_Disabled   BPROT_CONFIG1_REGION42_Disabled
+#define MPU_PROTENSET1_PROTREG42_Enabled    BPROT_CONFIG1_REGION42_Enabled
+#define MPU_PROTENSET1_PROTREG42_Set        BPROT_CONFIG1_REGION42_Enabled
+
+#define MPU_PROTENSET1_PROTREG41_Pos        BPROT_CONFIG1_REGION41_Pos
+#define MPU_PROTENSET1_PROTREG41_Msk        BPROT_CONFIG1_REGION41_Msk
+#define MPU_PROTENSET1_PROTREG41_Disabled   BPROT_CONFIG1_REGION41_Disabled
+#define MPU_PROTENSET1_PROTREG41_Enabled    BPROT_CONFIG1_REGION41_Enabled
+#define MPU_PROTENSET1_PROTREG41_Set        BPROT_CONFIG1_REGION41_Enabled
+
+#define MPU_PROTENSET1_PROTREG40_Pos        BPROT_CONFIG1_REGION40_Pos
+#define MPU_PROTENSET1_PROTREG40_Msk        BPROT_CONFIG1_REGION40_Msk
+#define MPU_PROTENSET1_PROTREG40_Disabled   BPROT_CONFIG1_REGION40_Disabled
+#define MPU_PROTENSET1_PROTREG40_Enabled    BPROT_CONFIG1_REGION40_Enabled
+#define MPU_PROTENSET1_PROTREG40_Set        BPROT_CONFIG1_REGION40_Enabled
+
+#define MPU_PROTENSET1_PROTREG39_Pos        BPROT_CONFIG1_REGION39_Pos
+#define MPU_PROTENSET1_PROTREG39_Msk        BPROT_CONFIG1_REGION39_Msk
+#define MPU_PROTENSET1_PROTREG39_Disabled   BPROT_CONFIG1_REGION39_Disabled
+#define MPU_PROTENSET1_PROTREG39_Enabled    BPROT_CONFIG1_REGION39_Enabled
+#define MPU_PROTENSET1_PROTREG39_Set        BPROT_CONFIG1_REGION39_Enabled
+
+#define MPU_PROTENSET1_PROTREG38_Pos        BPROT_CONFIG1_REGION38_Pos
+#define MPU_PROTENSET1_PROTREG38_Msk        BPROT_CONFIG1_REGION38_Msk
+#define MPU_PROTENSET1_PROTREG38_Disabled   BPROT_CONFIG1_REGION38_Disabled
+#define MPU_PROTENSET1_PROTREG38_Enabled    BPROT_CONFIG1_REGION38_Enabled
+#define MPU_PROTENSET1_PROTREG38_Set        BPROT_CONFIG1_REGION38_Enabled
+
+#define MPU_PROTENSET1_PROTREG37_Pos        BPROT_CONFIG1_REGION37_Pos
+#define MPU_PROTENSET1_PROTREG37_Msk        BPROT_CONFIG1_REGION37_Msk
+#define MPU_PROTENSET1_PROTREG37_Disabled   BPROT_CONFIG1_REGION37_Disabled
+#define MPU_PROTENSET1_PROTREG37_Enabled    BPROT_CONFIG1_REGION37_Enabled
+#define MPU_PROTENSET1_PROTREG37_Set        BPROT_CONFIG1_REGION37_Enabled
+
+#define MPU_PROTENSET1_PROTREG36_Pos        BPROT_CONFIG1_REGION36_Pos
+#define MPU_PROTENSET1_PROTREG36_Msk        BPROT_CONFIG1_REGION36_Msk
+#define MPU_PROTENSET1_PROTREG36_Disabled   BPROT_CONFIG1_REGION36_Disabled
+#define MPU_PROTENSET1_PROTREG36_Enabled    BPROT_CONFIG1_REGION36_Enabled
+#define MPU_PROTENSET1_PROTREG36_Set        BPROT_CONFIG1_REGION36_Enabled
+
+#define MPU_PROTENSET1_PROTREG35_Pos        BPROT_CONFIG1_REGION35_Pos
+#define MPU_PROTENSET1_PROTREG35_Msk        BPROT_CONFIG1_REGION35_Msk
+#define MPU_PROTENSET1_PROTREG35_Disabled   BPROT_CONFIG1_REGION35_Disabled
+#define MPU_PROTENSET1_PROTREG35_Enabled    BPROT_CONFIG1_REGION35_Enabled
+#define MPU_PROTENSET1_PROTREG35_Set        BPROT_CONFIG1_REGION35_Enabled
+
+#define MPU_PROTENSET1_PROTREG34_Pos        BPROT_CONFIG1_REGION34_Pos
+#define MPU_PROTENSET1_PROTREG34_Msk        BPROT_CONFIG1_REGION34_Msk
+#define MPU_PROTENSET1_PROTREG34_Disabled   BPROT_CONFIG1_REGION34_Disabled
+#define MPU_PROTENSET1_PROTREG34_Enabled    BPROT_CONFIG1_REGION34_Enabled
+#define MPU_PROTENSET1_PROTREG34_Set        BPROT_CONFIG1_REGION34_Enabled
+
+#define MPU_PROTENSET1_PROTREG33_Pos        BPROT_CONFIG1_REGION33_Pos
+#define MPU_PROTENSET1_PROTREG33_Msk        BPROT_CONFIG1_REGION33_Msk
+#define MPU_PROTENSET1_PROTREG33_Disabled   BPROT_CONFIG1_REGION33_Disabled
+#define MPU_PROTENSET1_PROTREG33_Enabled    BPROT_CONFIG1_REGION33_Enabled
+#define MPU_PROTENSET1_PROTREG33_Set        BPROT_CONFIG1_REGION33_Enabled
+
+#define MPU_PROTENSET1_PROTREG32_Pos        BPROT_CONFIG1_REGION32_Pos
+#define MPU_PROTENSET1_PROTREG32_Msk        BPROT_CONFIG1_REGION32_Msk
+#define MPU_PROTENSET1_PROTREG32_Disabled   BPROT_CONFIG1_REGION32_Disabled
+#define MPU_PROTENSET1_PROTREG32_Enabled    BPROT_CONFIG1_REGION32_Enabled
+#define MPU_PROTENSET1_PROTREG32_Set        BPROT_CONFIG1_REGION32_Enabled
+
+#define MPU_PROTENSET0_PROTREG31_Pos        BPROT_CONFIG0_REGION31_Pos
+#define MPU_PROTENSET0_PROTREG31_Msk        BPROT_CONFIG0_REGION31_Msk
+#define MPU_PROTENSET0_PROTREG31_Disabled   BPROT_CONFIG0_REGION31_Disabled
+#define MPU_PROTENSET0_PROTREG31_Enabled    BPROT_CONFIG0_REGION31_Enabled
+#define MPU_PROTENSET0_PROTREG31_Set        BPROT_CONFIG0_REGION31_Enabled
+
+#define MPU_PROTENSET0_PROTREG30_Pos        BPROT_CONFIG0_REGION30_Pos
+#define MPU_PROTENSET0_PROTREG30_Msk        BPROT_CONFIG0_REGION30_Msk
+#define MPU_PROTENSET0_PROTREG30_Disabled   BPROT_CONFIG0_REGION30_Disabled
+#define MPU_PROTENSET0_PROTREG30_Enabled    BPROT_CONFIG0_REGION30_Enabled
+#define MPU_PROTENSET0_PROTREG30_Set        BPROT_CONFIG0_REGION30_Enabled
+
+#define MPU_PROTENSET0_PROTREG29_Pos        BPROT_CONFIG0_REGION29_Pos
+#define MPU_PROTENSET0_PROTREG29_Msk        BPROT_CONFIG0_REGION29_Msk
+#define MPU_PROTENSET0_PROTREG29_Disabled   BPROT_CONFIG0_REGION29_Disabled
+#define MPU_PROTENSET0_PROTREG29_Enabled    BPROT_CONFIG0_REGION29_Enabled
+#define MPU_PROTENSET0_PROTREG29_Set        BPROT_CONFIG0_REGION29_Enabled
+
+#define MPU_PROTENSET0_PROTREG28_Pos        BPROT_CONFIG0_REGION28_Pos
+#define MPU_PROTENSET0_PROTREG28_Msk        BPROT_CONFIG0_REGION28_Msk
+#define MPU_PROTENSET0_PROTREG28_Disabled   BPROT_CONFIG0_REGION28_Disabled
+#define MPU_PROTENSET0_PROTREG28_Enabled    BPROT_CONFIG0_REGION28_Enabled
+#define MPU_PROTENSET0_PROTREG28_Set        BPROT_CONFIG0_REGION28_Enabled
+
+#define MPU_PROTENSET0_PROTREG27_Pos        BPROT_CONFIG0_REGION27_Pos
+#define MPU_PROTENSET0_PROTREG27_Msk        BPROT_CONFIG0_REGION27_Msk
+#define MPU_PROTENSET0_PROTREG27_Disabled   BPROT_CONFIG0_REGION27_Disabled
+#define MPU_PROTENSET0_PROTREG27_Enabled    BPROT_CONFIG0_REGION27_Enabled
+#define MPU_PROTENSET0_PROTREG27_Set        BPROT_CONFIG0_REGION27_Enabled
+
+#define MPU_PROTENSET0_PROTREG26_Pos        BPROT_CONFIG0_REGION26_Pos
+#define MPU_PROTENSET0_PROTREG26_Msk        BPROT_CONFIG0_REGION26_Msk
+#define MPU_PROTENSET0_PROTREG26_Disabled   BPROT_CONFIG0_REGION26_Disabled
+#define MPU_PROTENSET0_PROTREG26_Enabled    BPROT_CONFIG0_REGION26_Enabled
+#define MPU_PROTENSET0_PROTREG26_Set        BPROT_CONFIG0_REGION26_Enabled
+
+#define MPU_PROTENSET0_PROTREG25_Pos        BPROT_CONFIG0_REGION25_Pos
+#define MPU_PROTENSET0_PROTREG25_Msk        BPROT_CONFIG0_REGION25_Msk
+#define MPU_PROTENSET0_PROTREG25_Disabled   BPROT_CONFIG0_REGION25_Disabled
+#define MPU_PROTENSET0_PROTREG25_Enabled    BPROT_CONFIG0_REGION25_Enabled
+#define MPU_PROTENSET0_PROTREG25_Set        BPROT_CONFIG0_REGION25_Enabled
+
+#define MPU_PROTENSET0_PROTREG24_Pos        BPROT_CONFIG0_REGION24_Pos
+#define MPU_PROTENSET0_PROTREG24_Msk        BPROT_CONFIG0_REGION24_Msk
+#define MPU_PROTENSET0_PROTREG24_Disabled   BPROT_CONFIG0_REGION24_Disabled
+#define MPU_PROTENSET0_PROTREG24_Enabled    BPROT_CONFIG0_REGION24_Enabled
+#define MPU_PROTENSET0_PROTREG24_Set        BPROT_CONFIG0_REGION24_Enabled
+
+#define MPU_PROTENSET0_PROTREG23_Pos        BPROT_CONFIG0_REGION23_Pos
+#define MPU_PROTENSET0_PROTREG23_Msk        BPROT_CONFIG0_REGION23_Msk
+#define MPU_PROTENSET0_PROTREG23_Disabled   BPROT_CONFIG0_REGION23_Disabled
+#define MPU_PROTENSET0_PROTREG23_Enabled    BPROT_CONFIG0_REGION23_Enabled
+#define MPU_PROTENSET0_PROTREG23_Set        BPROT_CONFIG0_REGION23_Enabled
+
+#define MPU_PROTENSET0_PROTREG22_Pos        BPROT_CONFIG0_REGION22_Pos
+#define MPU_PROTENSET0_PROTREG22_Msk        BPROT_CONFIG0_REGION22_Msk
+#define MPU_PROTENSET0_PROTREG22_Disabled   BPROT_CONFIG0_REGION22_Disabled
+#define MPU_PROTENSET0_PROTREG22_Enabled    BPROT_CONFIG0_REGION22_Enabled
+#define MPU_PROTENSET0_PROTREG22_Set        BPROT_CONFIG0_REGION22_Enabled
+
+#define MPU_PROTENSET0_PROTREG21_Pos        BPROT_CONFIG0_REGION21_Pos
+#define MPU_PROTENSET0_PROTREG21_Msk        BPROT_CONFIG0_REGION21_Msk
+#define MPU_PROTENSET0_PROTREG21_Disabled   BPROT_CONFIG0_REGION21_Disabled
+#define MPU_PROTENSET0_PROTREG21_Enabled    BPROT_CONFIG0_REGION21_Enabled
+#define MPU_PROTENSET0_PROTREG21_Set        BPROT_CONFIG0_REGION21_Enabled
+
+#define MPU_PROTENSET0_PROTREG20_Pos        BPROT_CONFIG0_REGION20_Pos
+#define MPU_PROTENSET0_PROTREG20_Msk        BPROT_CONFIG0_REGION20_Msk
+#define MPU_PROTENSET0_PROTREG20_Disabled   BPROT_CONFIG0_REGION20_Disabled
+#define MPU_PROTENSET0_PROTREG20_Enabled    BPROT_CONFIG0_REGION20_Enabled
+#define MPU_PROTENSET0_PROTREG20_Set        BPROT_CONFIG0_REGION20_Enabled
+
+#define MPU_PROTENSET0_PROTREG19_Pos        BPROT_CONFIG0_REGION19_Pos
+#define MPU_PROTENSET0_PROTREG19_Msk        BPROT_CONFIG0_REGION19_Msk
+#define MPU_PROTENSET0_PROTREG19_Disabled   BPROT_CONFIG0_REGION19_Disabled
+#define MPU_PROTENSET0_PROTREG19_Enabled    BPROT_CONFIG0_REGION19_Enabled
+#define MPU_PROTENSET0_PROTREG19_Set        BPROT_CONFIG0_REGION19_Enabled
+
+#define MPU_PROTENSET0_PROTREG18_Pos        BPROT_CONFIG0_REGION18_Pos
+#define MPU_PROTENSET0_PROTREG18_Msk        BPROT_CONFIG0_REGION18_Msk
+#define MPU_PROTENSET0_PROTREG18_Disabled   BPROT_CONFIG0_REGION18_Disabled
+#define MPU_PROTENSET0_PROTREG18_Enabled    BPROT_CONFIG0_REGION18_Enabled
+#define MPU_PROTENSET0_PROTREG18_Set        BPROT_CONFIG0_REGION18_Enabled
+
+#define MPU_PROTENSET0_PROTREG17_Pos        BPROT_CONFIG0_REGION17_Pos
+#define MPU_PROTENSET0_PROTREG17_Msk        BPROT_CONFIG0_REGION17_Msk
+#define MPU_PROTENSET0_PROTREG17_Disabled   BPROT_CONFIG0_REGION17_Disabled
+#define MPU_PROTENSET0_PROTREG17_Enabled    BPROT_CONFIG0_REGION17_Enabled
+#define MPU_PROTENSET0_PROTREG17_Set        BPROT_CONFIG0_REGION17_Enabled
+
+#define MPU_PROTENSET0_PROTREG16_Pos        BPROT_CONFIG0_REGION16_Pos
+#define MPU_PROTENSET0_PROTREG16_Msk        BPROT_CONFIG0_REGION16_Msk
+#define MPU_PROTENSET0_PROTREG16_Disabled   BPROT_CONFIG0_REGION16_Disabled
+#define MPU_PROTENSET0_PROTREG16_Enabled    BPROT_CONFIG0_REGION16_Enabled
+#define MPU_PROTENSET0_PROTREG16_Set        BPROT_CONFIG0_REGION16_Enabled
+
+#define MPU_PROTENSET0_PROTREG15_Pos        BPROT_CONFIG0_REGION15_Pos
+#define MPU_PROTENSET0_PROTREG15_Msk        BPROT_CONFIG0_REGION15_Msk
+#define MPU_PROTENSET0_PROTREG15_Disabled   BPROT_CONFIG0_REGION15_Disabled
+#define MPU_PROTENSET0_PROTREG15_Enabled    BPROT_CONFIG0_REGION15_Enabled
+#define MPU_PROTENSET0_PROTREG15_Set        BPROT_CONFIG0_REGION15_Enabled
+
+#define MPU_PROTENSET0_PROTREG14_Pos        BPROT_CONFIG0_REGION14_Pos
+#define MPU_PROTENSET0_PROTREG14_Msk        BPROT_CONFIG0_REGION14_Msk
+#define MPU_PROTENSET0_PROTREG14_Disabled   BPROT_CONFIG0_REGION14_Disabled
+#define MPU_PROTENSET0_PROTREG14_Enabled    BPROT_CONFIG0_REGION14_Enabled
+#define MPU_PROTENSET0_PROTREG14_Set        BPROT_CONFIG0_REGION14_Enabled
+
+#define MPU_PROTENSET0_PROTREG13_Pos        BPROT_CONFIG0_REGION13_Pos
+#define MPU_PROTENSET0_PROTREG13_Msk        BPROT_CONFIG0_REGION13_Msk
+#define MPU_PROTENSET0_PROTREG13_Disabled   BPROT_CONFIG0_REGION13_Disabled
+#define MPU_PROTENSET0_PROTREG13_Enabled    BPROT_CONFIG0_REGION13_Enabled
+#define MPU_PROTENSET0_PROTREG13_Set        BPROT_CONFIG0_REGION13_Enabled
+
+#define MPU_PROTENSET0_PROTREG12_Pos        BPROT_CONFIG0_REGION12_Pos
+#define MPU_PROTENSET0_PROTREG12_Msk        BPROT_CONFIG0_REGION12_Msk
+#define MPU_PROTENSET0_PROTREG12_Disabled   BPROT_CONFIG0_REGION12_Disabled
+#define MPU_PROTENSET0_PROTREG12_Enabled    BPROT_CONFIG0_REGION12_Enabled
+#define MPU_PROTENSET0_PROTREG12_Set        BPROT_CONFIG0_REGION12_Enabled
+
+#define MPU_PROTENSET0_PROTREG11_Pos        BPROT_CONFIG0_REGION11_Pos
+#define MPU_PROTENSET0_PROTREG11_Msk        BPROT_CONFIG0_REGION11_Msk
+#define MPU_PROTENSET0_PROTREG11_Disabled   BPROT_CONFIG0_REGION11_Disabled
+#define MPU_PROTENSET0_PROTREG11_Enabled    BPROT_CONFIG0_REGION11_Enabled
+#define MPU_PROTENSET0_PROTREG11_Set        BPROT_CONFIG0_REGION11_Enabled
+
+#define MPU_PROTENSET0_PROTREG10_Pos        BPROT_CONFIG0_REGION10_Pos
+#define MPU_PROTENSET0_PROTREG10_Msk        BPROT_CONFIG0_REGION10_Msk
+#define MPU_PROTENSET0_PROTREG10_Disabled   BPROT_CONFIG0_REGION10_Disabled
+#define MPU_PROTENSET0_PROTREG10_Enabled    BPROT_CONFIG0_REGION10_Enabled
+#define MPU_PROTENSET0_PROTREG10_Set        BPROT_CONFIG0_REGION10_Enabled
+
+#define MPU_PROTENSET0_PROTREG9_Pos        BPROT_CONFIG0_REGION9_Pos
+#define MPU_PROTENSET0_PROTREG9_Msk        BPROT_CONFIG0_REGION9_Msk
+#define MPU_PROTENSET0_PROTREG9_Disabled   BPROT_CONFIG0_REGION9_Disabled
+#define MPU_PROTENSET0_PROTREG9_Enabled    BPROT_CONFIG0_REGION9_Enabled
+#define MPU_PROTENSET0_PROTREG9_Set        BPROT_CONFIG0_REGION9_Enabled
+
+#define MPU_PROTENSET0_PROTREG8_Pos        BPROT_CONFIG0_REGION8_Pos
+#define MPU_PROTENSET0_PROTREG8_Msk        BPROT_CONFIG0_REGION8_Msk
+#define MPU_PROTENSET0_PROTREG8_Disabled   BPROT_CONFIG0_REGION8_Disabled
+#define MPU_PROTENSET0_PROTREG8_Enabled    BPROT_CONFIG0_REGION8_Enabled
+#define MPU_PROTENSET0_PROTREG8_Set        BPROT_CONFIG0_REGION8_Enabled
+
+#define MPU_PROTENSET0_PROTREG7_Pos        BPROT_CONFIG0_REGION7_Pos
+#define MPU_PROTENSET0_PROTREG7_Msk        BPROT_CONFIG0_REGION7_Msk
+#define MPU_PROTENSET0_PROTREG7_Disabled   BPROT_CONFIG0_REGION7_Disabled
+#define MPU_PROTENSET0_PROTREG7_Enabled    BPROT_CONFIG0_REGION7_Enabled
+#define MPU_PROTENSET0_PROTREG7_Set        BPROT_CONFIG0_REGION7_Enabled
+
+#define MPU_PROTENSET0_PROTREG6_Pos        BPROT_CONFIG0_REGION6_Pos
+#define MPU_PROTENSET0_PROTREG6_Msk        BPROT_CONFIG0_REGION6_Msk
+#define MPU_PROTENSET0_PROTREG6_Disabled   BPROT_CONFIG0_REGION6_Disabled
+#define MPU_PROTENSET0_PROTREG6_Enabled    BPROT_CONFIG0_REGION6_Enabled
+#define MPU_PROTENSET0_PROTREG6_Set        BPROT_CONFIG0_REGION6_Enabled
+
+#define MPU_PROTENSET0_PROTREG5_Pos        BPROT_CONFIG0_REGION5_Pos
+#define MPU_PROTENSET0_PROTREG5_Msk        BPROT_CONFIG0_REGION5_Msk
+#define MPU_PROTENSET0_PROTREG5_Disabled   BPROT_CONFIG0_REGION5_Disabled
+#define MPU_PROTENSET0_PROTREG5_Enabled    BPROT_CONFIG0_REGION5_Enabled
+#define MPU_PROTENSET0_PROTREG5_Set        BPROT_CONFIG0_REGION5_Enabled
+
+#define MPU_PROTENSET0_PROTREG4_Pos        BPROT_CONFIG0_REGION4_Pos
+#define MPU_PROTENSET0_PROTREG4_Msk        BPROT_CONFIG0_REGION4_Msk
+#define MPU_PROTENSET0_PROTREG4_Disabled   BPROT_CONFIG0_REGION4_Disabled
+#define MPU_PROTENSET0_PROTREG4_Enabled    BPROT_CONFIG0_REGION4_Enabled
+#define MPU_PROTENSET0_PROTREG4_Set        BPROT_CONFIG0_REGION4_Enabled
+
+#define MPU_PROTENSET0_PROTREG3_Pos        BPROT_CONFIG0_REGION3_Pos
+#define MPU_PROTENSET0_PROTREG3_Msk        BPROT_CONFIG0_REGION3_Msk
+#define MPU_PROTENSET0_PROTREG3_Disabled   BPROT_CONFIG0_REGION3_Disabled
+#define MPU_PROTENSET0_PROTREG3_Enabled    BPROT_CONFIG0_REGION3_Enabled
+#define MPU_PROTENSET0_PROTREG3_Set        BPROT_CONFIG0_REGION3_Enabled
+
+#define MPU_PROTENSET0_PROTREG2_Pos        BPROT_CONFIG0_REGION2_Pos
+#define MPU_PROTENSET0_PROTREG2_Msk        BPROT_CONFIG0_REGION2_Msk
+#define MPU_PROTENSET0_PROTREG2_Disabled   BPROT_CONFIG0_REGION2_Disabled
+#define MPU_PROTENSET0_PROTREG2_Enabled    BPROT_CONFIG0_REGION2_Enabled
+#define MPU_PROTENSET0_PROTREG2_Set        BPROT_CONFIG0_REGION2_Enabled
+
+#define MPU_PROTENSET0_PROTREG1_Pos        BPROT_CONFIG0_REGION1_Pos
+#define MPU_PROTENSET0_PROTREG1_Msk        BPROT_CONFIG0_REGION1_Msk
+#define MPU_PROTENSET0_PROTREG1_Disabled   BPROT_CONFIG0_REGION1_Disabled
+#define MPU_PROTENSET0_PROTREG1_Enabled    BPROT_CONFIG0_REGION1_Enabled
+#define MPU_PROTENSET0_PROTREG1_Set        BPROT_CONFIG0_REGION1_Enabled
+
+#define MPU_PROTENSET0_PROTREG0_Pos        BPROT_CONFIG0_REGION0_Pos
+#define MPU_PROTENSET0_PROTREG0_Msk        BPROT_CONFIG0_REGION0_Msk
+#define MPU_PROTENSET0_PROTREG0_Disabled   BPROT_CONFIG0_REGION0_Disabled
+#define MPU_PROTENSET0_PROTREG0_Enabled    BPROT_CONFIG0_REGION0_Enabled
+#define MPU_PROTENSET0_PROTREG0_Set        BPROT_CONFIG0_REGION0_Enabled
+
+
+/* From nrf51_deprecated.h */
+
+/* NVMC */
+/* The register ERASEPROTECTEDPAGE changed name to ERASEPCR0 in the documentation. */
+#define ERASEPROTECTEDPAGE      ERASEPCR0
+
+
+/* IRQ */
+/* COMP module was eliminated. Adapted to nrf52 headers. */
+#define LPCOMP_COMP_IRQHandler  COMP_LPCOMP_IRQHandler
+#define LPCOMP_COMP_IRQn        COMP_LPCOMP_IRQn
+
+
+/* RADIO */
+/* The name of the field SKIPADDR was corrected. Old macros added for compatibility. */
+#define RADIO_CRCCNF_SKIP_ADDR_Pos      RADIO_CRCCNF_SKIPADDR_Pos
+#define RADIO_CRCCNF_SKIP_ADDR_Msk      RADIO_CRCCNF_SKIPADDR_Msk
+#define RADIO_CRCCNF_SKIP_ADDR_Include  RADIO_CRCCNF_SKIPADDR_Include
+#define RADIO_CRCCNF_SKIP_ADDR_Skip     RADIO_CRCCNF_SKIPADDR_Skip
+
+
+/* FICR */
+/* The registers FICR.DEVICEID0 and FICR.DEVICEID1 were renamed into an array. */
+#define DEVICEID0       DEVICEID[0]
+#define DEVICEID1       DEVICEID[1]
+
+/* The registers FICR.ER0, FICR.ER1, FICR.ER2 and FICR.ER3 were renamed into an array. */
+#define ER0             ER[0]
+#define ER1             ER[1]
+#define ER2             ER[2]
+#define ER3             ER[3]
+
+/* The registers FICR.IR0, FICR.IR1, FICR.IR2 and FICR.IR3 were renamed into an array. */
+#define IR0             IR[0]
+#define IR1             IR[1]
+#define IR2             IR[2]
+#define IR3             IR[3]
+
+/* The registers FICR.DEVICEADDR0 and FICR.DEVICEADDR1 were renamed into an array. */
+#define DEVICEADDR0     DEVICEADDR[0]
+#define DEVICEADDR1     DEVICEADDR[1]
+
+
+/* PPI */
+/* The tasks PPI.TASKS_CHGxEN and PPI.TASKS_CHGxDIS were renamed into an array of structs. */
+#define TASKS_CHG0EN     TASKS_CHG[0].EN
+#define TASKS_CHG0DIS    TASKS_CHG[0].DIS
+#define TASKS_CHG1EN     TASKS_CHG[1].EN
+#define TASKS_CHG1DIS    TASKS_CHG[1].DIS
+#define TASKS_CHG2EN     TASKS_CHG[2].EN
+#define TASKS_CHG2DIS    TASKS_CHG[2].DIS
+#define TASKS_CHG3EN     TASKS_CHG[3].EN
+#define TASKS_CHG3DIS    TASKS_CHG[3].DIS
+
+/* The registers PPI.CHx_EEP and PPI.CHx_TEP were renamed into an array of structs. */
+#define CH0_EEP          CH[0].EEP
+#define CH0_TEP          CH[0].TEP
+#define CH1_EEP          CH[1].EEP
+#define CH1_TEP          CH[1].TEP
+#define CH2_EEP          CH[2].EEP
+#define CH2_TEP          CH[2].TEP
+#define CH3_EEP          CH[3].EEP
+#define CH3_TEP          CH[3].TEP
+#define CH4_EEP          CH[4].EEP
+#define CH4_TEP          CH[4].TEP
+#define CH5_EEP          CH[5].EEP
+#define CH5_TEP          CH[5].TEP
+#define CH6_EEP          CH[6].EEP
+#define CH6_TEP          CH[6].TEP
+#define CH7_EEP          CH[7].EEP
+#define CH7_TEP          CH[7].TEP
+#define CH8_EEP          CH[8].EEP
+#define CH8_TEP          CH[8].TEP
+#define CH9_EEP          CH[9].EEP
+#define CH9_TEP          CH[9].TEP
+#define CH10_EEP         CH[10].EEP
+#define CH10_TEP         CH[10].TEP
+#define CH11_EEP         CH[11].EEP
+#define CH11_TEP         CH[11].TEP
+#define CH12_EEP         CH[12].EEP
+#define CH12_TEP         CH[12].TEP
+#define CH13_EEP         CH[13].EEP
+#define CH13_TEP         CH[13].TEP
+#define CH14_EEP         CH[14].EEP
+#define CH14_TEP         CH[14].TEP
+#define CH15_EEP         CH[15].EEP
+#define CH15_TEP         CH[15].TEP
+
+/* The registers PPI.CHG0, PPI.CHG1, PPI.CHG2 and PPI.CHG3 were renamed into an array. */
+#define CHG0             CHG[0]
+#define CHG1             CHG[1]
+#define CHG2             CHG[2]
+#define CHG3             CHG[3]
+
+/* All bitfield macros for the CHGx registers therefore changed name. */
+#define PPI_CHG0_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG0_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG0_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG0_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG0_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG0_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG0_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG0_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG0_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG0_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG0_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG0_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG0_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG0_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG0_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG0_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG0_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG0_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG0_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG0_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG0_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG0_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG0_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG0_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG0_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG0_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG0_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG0_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG0_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG0_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG0_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG0_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG0_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG0_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG0_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG0_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG0_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG0_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG0_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG0_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG0_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG0_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG0_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG0_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG0_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG0_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG0_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG0_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG0_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG0_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG0_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG0_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG0_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG0_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG0_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG0_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG0_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG0_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG0_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG0_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG0_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG0_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG0_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG0_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG1_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG1_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG1_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG1_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG1_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG1_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG1_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG1_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG1_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG1_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG1_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG1_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG1_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG1_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG1_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG1_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG1_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG1_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG1_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG1_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG1_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG1_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG1_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG1_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG1_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG1_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG1_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG1_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG1_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG1_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG1_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG1_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG1_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG1_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG1_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG1_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG1_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG1_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG1_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG1_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG1_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG1_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG1_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG1_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG1_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG1_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG1_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG1_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG1_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG1_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG1_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG1_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG1_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG1_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG1_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG1_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG1_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG1_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG1_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG1_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG1_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG1_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG1_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG1_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG2_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG2_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG2_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG2_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG2_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG2_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG2_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG2_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG2_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG2_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG2_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG2_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG2_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG2_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG2_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG2_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG2_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG2_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG2_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG2_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG2_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG2_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG2_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG2_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG2_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG2_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG2_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG2_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG2_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG2_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG2_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG2_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG2_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG2_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG2_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG2_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG2_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG2_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG2_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG2_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG2_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG2_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG2_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG2_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG2_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG2_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG2_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG2_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG2_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG2_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG2_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG2_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG2_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG2_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG2_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG2_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG2_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG2_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG2_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG2_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG2_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG2_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG2_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG2_CH0_Included   PPI_CHG_CH0_Included
+
+#define PPI_CHG3_CH15_Pos       PPI_CHG_CH15_Pos
+#define PPI_CHG3_CH15_Msk       PPI_CHG_CH15_Msk
+#define PPI_CHG3_CH15_Excluded  PPI_CHG_CH15_Excluded
+#define PPI_CHG3_CH15_Included  PPI_CHG_CH15_Included
+
+#define PPI_CHG3_CH14_Pos       PPI_CHG_CH14_Pos
+#define PPI_CHG3_CH14_Msk       PPI_CHG_CH14_Msk
+#define PPI_CHG3_CH14_Excluded  PPI_CHG_CH14_Excluded
+#define PPI_CHG3_CH14_Included  PPI_CHG_CH14_Included
+
+#define PPI_CHG3_CH13_Pos       PPI_CHG_CH13_Pos
+#define PPI_CHG3_CH13_Msk       PPI_CHG_CH13_Msk
+#define PPI_CHG3_CH13_Excluded  PPI_CHG_CH13_Excluded
+#define PPI_CHG3_CH13_Included  PPI_CHG_CH13_Included
+
+#define PPI_CHG3_CH12_Pos       PPI_CHG_CH12_Pos
+#define PPI_CHG3_CH12_Msk       PPI_CHG_CH12_Msk
+#define PPI_CHG3_CH12_Excluded  PPI_CHG_CH12_Excluded
+#define PPI_CHG3_CH12_Included  PPI_CHG_CH12_Included
+
+#define PPI_CHG3_CH11_Pos       PPI_CHG_CH11_Pos
+#define PPI_CHG3_CH11_Msk       PPI_CHG_CH11_Msk
+#define PPI_CHG3_CH11_Excluded  PPI_CHG_CH11_Excluded
+#define PPI_CHG3_CH11_Included  PPI_CHG_CH11_Included
+
+#define PPI_CHG3_CH10_Pos       PPI_CHG_CH10_Pos
+#define PPI_CHG3_CH10_Msk       PPI_CHG_CH10_Msk
+#define PPI_CHG3_CH10_Excluded  PPI_CHG_CH10_Excluded
+#define PPI_CHG3_CH10_Included  PPI_CHG_CH10_Included
+
+#define PPI_CHG3_CH9_Pos        PPI_CHG_CH9_Pos
+#define PPI_CHG3_CH9_Msk        PPI_CHG_CH9_Msk
+#define PPI_CHG3_CH9_Excluded   PPI_CHG_CH9_Excluded
+#define PPI_CHG3_CH9_Included   PPI_CHG_CH9_Included
+
+#define PPI_CHG3_CH8_Pos        PPI_CHG_CH8_Pos
+#define PPI_CHG3_CH8_Msk        PPI_CHG_CH8_Msk
+#define PPI_CHG3_CH8_Excluded   PPI_CHG_CH8_Excluded
+#define PPI_CHG3_CH8_Included   PPI_CHG_CH8_Included
+
+#define PPI_CHG3_CH7_Pos        PPI_CHG_CH7_Pos
+#define PPI_CHG3_CH7_Msk        PPI_CHG_CH7_Msk
+#define PPI_CHG3_CH7_Excluded   PPI_CHG_CH7_Excluded
+#define PPI_CHG3_CH7_Included   PPI_CHG_CH7_Included
+
+#define PPI_CHG3_CH6_Pos        PPI_CHG_CH6_Pos
+#define PPI_CHG3_CH6_Msk        PPI_CHG_CH6_Msk
+#define PPI_CHG3_CH6_Excluded   PPI_CHG_CH6_Excluded
+#define PPI_CHG3_CH6_Included   PPI_CHG_CH6_Included
+
+#define PPI_CHG3_CH5_Pos        PPI_CHG_CH5_Pos
+#define PPI_CHG3_CH5_Msk        PPI_CHG_CH5_Msk
+#define PPI_CHG3_CH5_Excluded   PPI_CHG_CH5_Excluded
+#define PPI_CHG3_CH5_Included   PPI_CHG_CH5_Included
+
+#define PPI_CHG3_CH4_Pos        PPI_CHG_CH4_Pos
+#define PPI_CHG3_CH4_Msk        PPI_CHG_CH4_Msk
+#define PPI_CHG3_CH4_Excluded   PPI_CHG_CH4_Excluded
+#define PPI_CHG3_CH4_Included   PPI_CHG_CH4_Included
+
+#define PPI_CHG3_CH3_Pos        PPI_CHG_CH3_Pos
+#define PPI_CHG3_CH3_Msk        PPI_CHG_CH3_Msk
+#define PPI_CHG3_CH3_Excluded   PPI_CHG_CH3_Excluded
+#define PPI_CHG3_CH3_Included   PPI_CHG_CH3_Included
+
+#define PPI_CHG3_CH2_Pos        PPI_CHG_CH2_Pos
+#define PPI_CHG3_CH2_Msk        PPI_CHG_CH2_Msk
+#define PPI_CHG3_CH2_Excluded   PPI_CHG_CH2_Excluded
+#define PPI_CHG3_CH2_Included   PPI_CHG_CH2_Included
+
+#define PPI_CHG3_CH1_Pos        PPI_CHG_CH1_Pos
+#define PPI_CHG3_CH1_Msk        PPI_CHG_CH1_Msk
+#define PPI_CHG3_CH1_Excluded   PPI_CHG_CH1_Excluded
+#define PPI_CHG3_CH1_Included   PPI_CHG_CH1_Included
+
+#define PPI_CHG3_CH0_Pos        PPI_CHG_CH0_Pos
+#define PPI_CHG3_CH0_Msk        PPI_CHG_CH0_Msk
+#define PPI_CHG3_CH0_Excluded   PPI_CHG_CH0_Excluded
+#define PPI_CHG3_CH0_Included   PPI_CHG_CH0_Included
+
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF51_TO_NRF52_H */
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h
new file mode 100644
index 0000000000..bf7c165a0e
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52.h
@@ -0,0 +1,2125 @@
+
+/****************************************************************************************************//**
+ * @file     nrf52.h
+ *
+ * @brief    CMSIS Cortex-M4 Peripheral Access Layer Header File for
+ *           nrf52 from Nordic Semiconductor.
+ *
+ * @version  V1
+ * @date     23. February 2016
+ *
+ * @note     Generated with SVDConv V2.81d 
+ *           from CMSIS SVD File 'nrf52.svd' Version 1,
+ *
+ * @par      Copyright (c) 2015, Nordic Semiconductor ASA
+ *           All rights reserved.
+ *           
+ *           Redistribution and use in source and binary forms, with or without
+ *           modification, are permitted provided that the following conditions are met:
+ *           
+ *           * Redistributions of source code must retain the above copyright notice, this
+ *           list of conditions and the following disclaimer.
+ *           
+ *           * Redistributions in binary form must reproduce the above copyright notice,
+ *           this list of conditions and the following disclaimer in the documentation
+ *           and/or other materials provided with the distribution.
+ *           
+ *           * Neither the name of Nordic Semiconductor ASA nor the names of its
+ *           contributors may be used to endorse or promote products derived from
+ *           this software without specific prior written permission.
+ *           
+ *           THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ *           AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ *           IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ *           DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ *           FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ *           DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ *           SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ *           CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ *           OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ *           OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *           
+ *
+ *******************************************************************************************************/
+
+
+
+/** @addtogroup Nordic Semiconductor
+  * @{
+  */
+
+/** @addtogroup nrf52
+  * @{
+  */
+
+#ifndef NRF52_H
+#define NRF52_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/* -------------------------  Interrupt Number Definition  ------------------------ */
+
+typedef enum {
+/* -------------------  Cortex-M4 Processor Exceptions Numbers  ------------------- */
+  Reset_IRQn                    = -15,              /*!<   1  Reset Vector, invoked on Power up and warm reset                 */
+  NonMaskableInt_IRQn           = -14,              /*!<   2  Non maskable Interrupt, cannot be stopped or preempted           */
+  HardFault_IRQn                = -13,              /*!<   3  Hard Fault, all classes of Fault                                 */
+  MemoryManagement_IRQn         = -12,              /*!<   4  Memory Management, MPU mismatch, including Access Violation
+                                                         and No Match                                                          */
+  BusFault_IRQn                 = -11,              /*!<   5  Bus Fault, Pre-Fetch-, Memory Access Fault, other address/memory
+                                                         related Fault                                                         */
+  UsageFault_IRQn               = -10,              /*!<   6  Usage Fault, i.e. Undef Instruction, Illegal State Transition    */
+  SVCall_IRQn                   =  -5,              /*!<  11  System Service Call via SVC instruction                          */
+  DebugMonitor_IRQn             =  -4,              /*!<  12  Debug Monitor                                                    */
+  PendSV_IRQn                   =  -2,              /*!<  14  Pendable request for system service                              */
+  SysTick_IRQn                  =  -1,              /*!<  15  System Tick Timer                                                */
+/* ----------------------  nrf52 Specific Interrupt Numbers  ---------------------- */
+  POWER_CLOCK_IRQn              =   0,              /*!<   0  POWER_CLOCK                                                      */
+  RADIO_IRQn                    =   1,              /*!<   1  RADIO                                                            */
+  UARTE0_UART0_IRQn             =   2,              /*!<   2  UARTE0_UART0                                                     */
+  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn=   3,      /*!<   3  SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0                                */
+  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn=   4,      /*!<   4  SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1                                */
+  NFCT_IRQn                     =   5,              /*!<   5  NFCT                                                             */
+  GPIOTE_IRQn                   =   6,              /*!<   6  GPIOTE                                                           */
+  SAADC_IRQn                    =   7,              /*!<   7  SAADC                                                            */
+  TIMER0_IRQn                   =   8,              /*!<   8  TIMER0                                                           */
+  TIMER1_IRQn                   =   9,              /*!<   9  TIMER1                                                           */
+  TIMER2_IRQn                   =  10,              /*!<  10  TIMER2                                                           */
+  RTC0_IRQn                     =  11,              /*!<  11  RTC0                                                             */
+  TEMP_IRQn                     =  12,              /*!<  12  TEMP                                                             */
+  RNG_IRQn                      =  13,              /*!<  13  RNG                                                              */
+  ECB_IRQn                      =  14,              /*!<  14  ECB                                                              */
+  CCM_AAR_IRQn                  =  15,              /*!<  15  CCM_AAR                                                          */
+  WDT_IRQn                      =  16,              /*!<  16  WDT                                                              */
+  RTC1_IRQn                     =  17,              /*!<  17  RTC1                                                             */
+  QDEC_IRQn                     =  18,              /*!<  18  QDEC                                                             */
+  COMP_LPCOMP_IRQn              =  19,              /*!<  19  COMP_LPCOMP                                                      */
+  SWI0_EGU0_IRQn                =  20,              /*!<  20  SWI0_EGU0                                                        */
+  SWI1_EGU1_IRQn                =  21,              /*!<  21  SWI1_EGU1                                                        */
+  SWI2_EGU2_IRQn                =  22,              /*!<  22  SWI2_EGU2                                                        */
+  SWI3_EGU3_IRQn                =  23,              /*!<  23  SWI3_EGU3                                                        */
+  SWI4_EGU4_IRQn                =  24,              /*!<  24  SWI4_EGU4                                                        */
+  SWI5_EGU5_IRQn                =  25,              /*!<  25  SWI5_EGU5                                                        */
+  TIMER3_IRQn                   =  26,              /*!<  26  TIMER3                                                           */
+  TIMER4_IRQn                   =  27,              /*!<  27  TIMER4                                                           */
+  PWM0_IRQn                     =  28,              /*!<  28  PWM0                                                             */
+  PDM_IRQn                      =  29,              /*!<  29  PDM                                                              */
+  MWU_IRQn                      =  32,              /*!<  32  MWU                                                              */
+  PWM1_IRQn                     =  33,              /*!<  33  PWM1                                                             */
+  PWM2_IRQn                     =  34,              /*!<  34  PWM2                                                             */
+  SPIM2_SPIS2_SPI2_IRQn         =  35,              /*!<  35  SPIM2_SPIS2_SPI2                                                 */
+  RTC2_IRQn                     =  36,              /*!<  36  RTC2                                                             */
+  I2S_IRQn                      =  37,              /*!<  37  I2S                                                              */
+  FPU_IRQn                      =  38               /*!<  38  FPU                                                              */
+} IRQn_Type;
+
+
+/** @addtogroup Configuration_of_CMSIS
+  * @{
+  */
+
+
+/* ================================================================================ */
+/* ================      Processor and Core Peripheral Section     ================ */
+/* ================================================================================ */
+
+/* ----------------Configuration of the Cortex-M4 Processor and Core Peripherals---------------- */
+#define __CM4_REV                 0x0001            /*!< Cortex-M4 Core Revision                                               */
+#define __MPU_PRESENT                  1            /*!< MPU present or not                                                    */
+#define __NVIC_PRIO_BITS               3            /*!< Number of Bits used for Priority Levels                               */
+#define __Vendor_SysTickConfig         0            /*!< Set to 1 if different SysTick Config is used                          */
+#define __FPU_PRESENT                  1            /*!< FPU present or not                                                    */
+/** @} */ /* End of group Configuration_of_CMSIS */
+
+#include "core_cm4.h"                               /*!< Cortex-M4 processor and core peripherals                              */
+#include "system_nrf52.h"                           /*!< nrf52 System                                                          */
+
+
+/* ================================================================================ */
+/* ================       Device Specific Peripheral Section       ================ */
+/* ================================================================================ */
+
+
+/** @addtogroup Device_Peripheral_Registers
+  * @{
+  */
+
+
+/* -------------------  Start of section using anonymous unions  ------------------ */
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+/* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning 586
+#else
+  #warning Not supported compiler type
+#endif
+
+
+typedef struct {
+  __I  uint32_t  PART;                              /*!< Part code                                                             */
+  __I  uint32_t  VARIANT;                           /*!< Part Variant, Hardware version and Production configuration           */
+  __I  uint32_t  PACKAGE;                           /*!< Package option                                                        */
+  __I  uint32_t  RAM;                               /*!< RAM variant                                                           */
+  __I  uint32_t  FLASH;                             /*!< Flash variant                                                         */
+  __IO uint32_t  UNUSED0[3];                        /*!< Description collection[0]: Unspecified                                */
+} FICR_INFO_Type;
+
+typedef struct {
+  __I  uint32_t  A0;                                /*!< Slope definition A0.                                                  */
+  __I  uint32_t  A1;                                /*!< Slope definition A1.                                                  */
+  __I  uint32_t  A2;                                /*!< Slope definition A2.                                                  */
+  __I  uint32_t  A3;                                /*!< Slope definition A3.                                                  */
+  __I  uint32_t  A4;                                /*!< Slope definition A4.                                                  */
+  __I  uint32_t  A5;                                /*!< Slope definition A5.                                                  */
+  __I  uint32_t  B0;                                /*!< y-intercept B0.                                                       */
+  __I  uint32_t  B1;                                /*!< y-intercept B1.                                                       */
+  __I  uint32_t  B2;                                /*!< y-intercept B2.                                                       */
+  __I  uint32_t  B3;                                /*!< y-intercept B3.                                                       */
+  __I  uint32_t  B4;                                /*!< y-intercept B4.                                                       */
+  __I  uint32_t  B5;                                /*!< y-intercept B5.                                                       */
+  __I  uint32_t  T0;                                /*!< Segment end T0.                                                       */
+  __I  uint32_t  T1;                                /*!< Segment end T1.                                                       */
+  __I  uint32_t  T2;                                /*!< Segment end T2.                                                       */
+  __I  uint32_t  T3;                                /*!< Segment end T3.                                                       */
+  __I  uint32_t  T4;                                /*!< Segment end T4.                                                       */
+} FICR_TEMP_Type;
+
+typedef struct {
+  __I  uint32_t  TAGHEADER0;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER1;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER2;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+  __I  uint32_t  TAGHEADER3;                        /*!< Default header for NFC Tag. Software can read these values to
+                                                         populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST.            */
+} FICR_NFC_Type;
+
+typedef struct {
+  __IO uint32_t  POWER;                             /*!< Description cluster[0]: RAM0 power control register                   */
+  __O  uint32_t  POWERSET;                          /*!< Description cluster[0]: RAM0 power control set register               */
+  __O  uint32_t  POWERCLR;                          /*!< Description cluster[0]: RAM0 power control clear register             */
+  __I  uint32_t  RESERVED0;
+} POWER_RAM_Type;
+
+typedef struct {
+  __IO uint32_t  CPU0;                              /*!< AHB bus master priority register for CPU0                             */
+  __IO uint32_t  SPIS1;                             /*!< AHB bus master priority register for SPIM1, SPIS1, TWIM1 and
+                                                         TWIS1                                                                 */
+  __IO uint32_t  RADIO;                             /*!< AHB bus master priority register for RADIO                            */
+  __IO uint32_t  ECB;                               /*!< AHB bus master priority register for ECB                              */
+  __IO uint32_t  CCM;                               /*!< AHB bus master priority register for CCM                              */
+  __IO uint32_t  AAR;                               /*!< AHB bus master priority register for AAR                              */
+  __IO uint32_t  SAADC;                             /*!< AHB bus master priority register for SAADC                            */
+  __IO uint32_t  UARTE;                             /*!< AHB bus master priority register for UARTE                            */
+  __IO uint32_t  SERIAL0;                           /*!< AHB bus master priority register for SPIM0, SPIS0, TWIM0 and
+                                                         TWIS0                                                                 */
+  __IO uint32_t  SERIAL2;                           /*!< AHB bus master priority register for SPIM2 and SPIS2                  */
+  __IO uint32_t  NFCT;                              /*!< AHB bus master priority register for NFCT                             */
+  __IO uint32_t  I2S;                               /*!< AHB bus master priority register for I2S                              */
+  __IO uint32_t  PDM;                               /*!< AHB bus master priority register for PDM                              */
+  __IO uint32_t  PWM;                               /*!< AHB bus master priority register for PWM0, PWM1 and PWM2              */
+} AMLI_RAMPRI_Type;
+
+typedef struct {
+  __IO uint32_t  RTS;                               /*!< Pin select for RTS signal                                             */
+  __IO uint32_t  TXD;                               /*!< Pin select for TXD signal                                             */
+  __IO uint32_t  CTS;                               /*!< Pin select for CTS signal                                             */
+  __IO uint32_t  RXD;                               /*!< Pin select for RXD signal                                             */
+} UARTE_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+} UARTE_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+} SPIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} SPIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO signal                                            */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI signal                                            */
+  __IO uint32_t  CSN;                               /*!< Pin select for CSN signal                                             */
+} SPIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes received in last granted transaction                  */
+} SPIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transmitted in last granted transaction               */
+} SPIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in receive buffer                             */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in transmit buffer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last transaction                   */
+  __IO uint32_t  LIST;                              /*!< EasyDMA list type                                                     */
+} TWIM_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCL;                               /*!< Pin select for SCL signal                                             */
+  __IO uint32_t  SDA;                               /*!< Pin select for SDA signal                                             */
+} TWIS_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in RXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last RXD transaction               */
+} TWIS_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< TXD Data pointer                                                      */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of bytes in TXD buffer                                 */
+  __I  uint32_t  AMOUNT;                            /*!< Number of bytes transferred in the last TXD transaction               */
+} TWIS_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK                                                    */
+  __IO uint32_t  MOSI;                              /*!< Pin select for MOSI                                                   */
+  __IO uint32_t  MISO;                              /*!< Pin select for MISO                                                   */
+} SPI_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  RX;                                /*!< Result of last incoming frames                                        */
+} NFCT_FRAMESTATUS_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of outgoing frames                                      */
+  __IO uint32_t  AMOUNT;                            /*!< Size of outgoing frame                                                */
+} NFCT_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  FRAMECONFIG;                       /*!< Configuration of incoming frames                                      */
+  __I  uint32_t  AMOUNT;                            /*!< Size of last incoming frame                                           */
+} NFCT_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  LIMITH;                            /*!< Description cluster[0]: Last results is equal or above CH[0].LIMIT.HIGH */
+  __IO uint32_t  LIMITL;                            /*!< Description cluster[0]: Last results is equal or below CH[0].LIMIT.LOW */
+} SAADC_EVENTS_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PSELP;                             /*!< Description cluster[0]: Input positive pin selection for CH[0]        */
+  __IO uint32_t  PSELN;                             /*!< Description cluster[0]: Input negative pin selection for CH[0]        */
+  __IO uint32_t  CONFIG;                            /*!< Description cluster[0]: Input configuration for CH[0]                 */
+  __IO uint32_t  LIMIT;                             /*!< Description cluster[0]: High/low limits for event monitoring
+                                                         a channel                                                             */
+} SAADC_CH_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Data pointer                                                          */
+  __IO uint32_t  MAXCNT;                            /*!< Maximum number of buffer words to transfer                            */
+  __I  uint32_t  AMOUNT;                            /*!< Number of buffer words transferred since last START                   */
+} SAADC_RESULT_Type;
+
+typedef struct {
+  __IO uint32_t  LED;                               /*!< Pin select for LED signal                                             */
+  __IO uint32_t  A;                                 /*!< Pin select for A signal                                               */
+  __IO uint32_t  B;                                 /*!< Pin select for B signal                                               */
+} QDEC_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Description cluster[0]: Beginning address in Data RAM of sequence
+                                                         A                                                                     */
+  __IO uint32_t  CNT;                               /*!< Description cluster[0]: Amount of values (duty cycles) in sequence
+                                                         A                                                                     */
+  __IO uint32_t  REFRESH;                           /*!< Description cluster[0]: Amount of additional PWM periods between
+                                                         samples loaded to compare register (load every CNT+1 PWM periods)     */
+  __IO uint32_t  ENDDELAY;                          /*!< Description cluster[0]: Time added after the sequence                 */
+  __I  uint32_t  RESERVED1[4];
+} PWM_SEQ_Type;
+
+typedef struct {
+  __IO uint32_t  OUT[4];                            /*!< Description collection[0]: Output pin select for PWM channel
+                                                         0                                                                     */
+} PWM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  CLK;                               /*!< Pin number configuration for PDM CLK signal                           */
+  __IO uint32_t  DIN;                               /*!< Pin number configuration for PDM DIN signal                           */
+} PDM_PSEL_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< RAM address pointer to write samples to with EasyDMA                  */
+  __IO uint32_t  MAXCNT;                            /*!< Number of samples to allocate memory for in EasyDMA mode              */
+} PDM_SAMPLE_Type;
+
+typedef struct {
+  __O  uint32_t  EN;                                /*!< Description cluster[0]: Enable channel group 0                        */
+  __O  uint32_t  DIS;                               /*!< Description cluster[0]: Disable channel group 0                       */
+} PPI_TASKS_CHG_Type;
+
+typedef struct {
+  __IO uint32_t  EEP;                               /*!< Description cluster[0]: Channel 0 event end-point                     */
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_CH_Type;
+
+typedef struct {
+  __IO uint32_t  TEP;                               /*!< Description cluster[0]: Channel 0 task end-point                      */
+} PPI_FORK_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to region 0 detected             */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to region 0 detected              */
+} MWU_EVENTS_REGION_Type;
+
+typedef struct {
+  __IO uint32_t  WA;                                /*!< Description cluster[0]: Write access to peripheral region 0
+                                                         detected                                                              */
+  __IO uint32_t  RA;                                /*!< Description cluster[0]: Read access to peripheral region 0 detected   */
+} MWU_EVENTS_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  SUBSTATWA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, write access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+  __IO uint32_t  SUBSTATRA;                         /*!< Description cluster[0]: Source of event/interrupt in region
+                                                         0, read access detected while corresponding subregion was enabled
+                                                          for watching                                                         */
+} MWU_PERREGION_Type;
+
+typedef struct {
+  __IO uint32_t  START;                             /*!< Description cluster[0]: Start address for region 0                    */
+  __IO uint32_t  END;                               /*!< Description cluster[0]: End address of region 0                       */
+  __I  uint32_t  RESERVED2[2];
+} MWU_REGION_Type;
+
+typedef struct {
+  __I  uint32_t  START;                             /*!< Description cluster[0]: Reserved for future use                       */
+  __I  uint32_t  END;                               /*!< Description cluster[0]: Reserved for future use                       */
+  __IO uint32_t  SUBS;                              /*!< Description cluster[0]: Subregions of region 0                        */
+  __I  uint32_t  RESERVED3;
+} MWU_PREGION_Type;
+
+typedef struct {
+  __IO uint32_t  MODE;                              /*!< I2S mode.                                                             */
+  __IO uint32_t  RXEN;                              /*!< Reception (RX) enable.                                                */
+  __IO uint32_t  TXEN;                              /*!< Transmission (TX) enable.                                             */
+  __IO uint32_t  MCKEN;                             /*!< Master clock generator enable.                                        */
+  __IO uint32_t  MCKFREQ;                           /*!< Master clock generator frequency.                                     */
+  __IO uint32_t  RATIO;                             /*!< MCK / LRCK ratio.                                                     */
+  __IO uint32_t  SWIDTH;                            /*!< Sample width.                                                         */
+  __IO uint32_t  ALIGN;                             /*!< Alignment of sample within a frame.                                   */
+  __IO uint32_t  FORMAT;                            /*!< Frame format.                                                         */
+  __IO uint32_t  CHANNELS;                          /*!< Enable channels.                                                      */
+} I2S_CONFIG_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Receive buffer RAM start address.                                     */
+} I2S_RXD_Type;
+
+typedef struct {
+  __IO uint32_t  PTR;                               /*!< Transmit buffer RAM start address.                                    */
+} I2S_TXD_Type;
+
+typedef struct {
+  __IO uint32_t  MAXCNT;                            /*!< Size of RXD and TXD buffers.                                          */
+} I2S_RXTXD_Type;
+
+typedef struct {
+  __IO uint32_t  MCK;                               /*!< Pin select for MCK signal.                                            */
+  __IO uint32_t  SCK;                               /*!< Pin select for SCK signal.                                            */
+  __IO uint32_t  LRCK;                              /*!< Pin select for LRCK signal.                                           */
+  __IO uint32_t  SDIN;                              /*!< Pin select for SDIN signal.                                           */
+  __IO uint32_t  SDOUT;                             /*!< Pin select for SDOUT signal.                                          */
+} I2S_PSEL_Type;
+
+
+/* ================================================================================ */
+/* ================                      FICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Factory Information Configuration Registers (FICR)
+  */
+
+typedef struct {                                    /*!< FICR Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __I  uint32_t  CODEPAGESIZE;                      /*!< Code memory page size                                                 */
+  __I  uint32_t  CODESIZE;                          /*!< Code memory size                                                      */
+  __I  uint32_t  RESERVED1[18];
+  __I  uint32_t  DEVICEID[2];                       /*!< Description collection[0]: Device identifier                          */
+  __I  uint32_t  RESERVED2[6];
+  __I  uint32_t  ER[4];                             /*!< Description collection[0]: Encryption Root, word 0                    */
+  __I  uint32_t  IR[4];                             /*!< Description collection[0]: Identity Root, word 0                      */
+  __I  uint32_t  DEVICEADDRTYPE;                    /*!< Device address type                                                   */
+  __I  uint32_t  DEVICEADDR[2];                     /*!< Description collection[0]: Device address 0                           */
+  __I  uint32_t  RESERVED3[21];
+  FICR_INFO_Type INFO;                              /*!< Device info                                                           */
+  __I  uint32_t  RESERVED4[185];
+  FICR_TEMP_Type TEMP;                              /*!< Registers storing factory TEMP module linearization coefficients      */
+  __I  uint32_t  RESERVED5[2];
+  FICR_NFC_Type NFC;                                /*!< Unspecified                                                           */
+} NRF_FICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      UICR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief User Information Configuration Registers (UICR)
+  */
+
+typedef struct {                                    /*!< UICR Structure                                                        */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED1;                           /*!< Unspecified                                                           */
+  __IO uint32_t  UNUSED2;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED0;
+  __IO uint32_t  UNUSED3;                           /*!< Unspecified                                                           */
+  __IO uint32_t  NRFFW[15];                         /*!< Description collection[0]: Reserved for Nordic firmware design        */
+  __IO uint32_t  NRFHW[12];                         /*!< Description collection[0]: Reserved for Nordic hardware design        */
+  __IO uint32_t  CUSTOMER[32];                      /*!< Description collection[0]: Reserved for customer                      */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  PSELRESET[2];                      /*!< Description collection[0]: Mapping of the nRESET function (see
+                                                         POWER chapter for details)                                            */
+  __IO uint32_t  APPROTECT;                         /*!< Access Port protection                                                */
+  __IO uint32_t  NFCPINS;                           /*!< Setting of pins dedicated to NFC functionality: NFC antenna
+                                                         or GPIO                                                               */
+} NRF_UICR_Type;
+
+
+/* ================================================================================ */
+/* ================                      BPROT                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Block Protect (BPROT)
+  */
+
+typedef struct {                                    /*!< BPROT Structure                                                       */
+  __I  uint32_t  RESERVED0[384];
+  __IO uint32_t  CONFIG0;                           /*!< Block protect configuration register 0                                */
+  __IO uint32_t  CONFIG1;                           /*!< Block protect configuration register 1                                */
+  __IO uint32_t  DISABLEINDEBUG;                    /*!< Disable protection mechanism in debug interface mode                  */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  CONFIG2;                           /*!< Block protect configuration register 2                                */
+  __IO uint32_t  CONFIG3;                           /*!< Block protect configuration register 3                                */
+} NRF_BPROT_Type;
+
+
+/* ================================================================================ */
+/* ================                      POWER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Power control (POWER)
+  */
+
+typedef struct {                                    /*!< POWER Structure                                                       */
+  __I  uint32_t  RESERVED0[30];
+  __O  uint32_t  TASKS_CONSTLAT;                    /*!< Enable constant latency mode                                          */
+  __O  uint32_t  TASKS_LOWPWR;                      /*!< Enable low power mode (variable latency)                              */
+  __I  uint32_t  RESERVED1[34];
+  __IO uint32_t  EVENTS_POFWARN;                    /*!< Power failure warning                                                 */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_SLEEPENTER;                 /*!< CPU entered WFI/WFE sleep                                             */
+  __IO uint32_t  EVENTS_SLEEPEXIT;                  /*!< CPU exited WFI/WFE sleep                                              */
+  __I  uint32_t  RESERVED3[122];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[61];
+  __IO uint32_t  RESETREAS;                         /*!< Reset reason                                                          */
+  __I  uint32_t  RESERVED5[9];
+  __I  uint32_t  RAMSTATUS;                         /*!< Deprecated register - RAM status register                             */
+  __I  uint32_t  RESERVED6[53];
+  __O  uint32_t  SYSTEMOFF;                         /*!< System OFF register                                                   */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  POFCON;                            /*!< Power failure comparator configuration                                */
+  __I  uint32_t  RESERVED8[2];
+  __IO uint32_t  GPREGRET;                          /*!< General purpose retention register                                    */
+  __IO uint32_t  GPREGRET2;                         /*!< General purpose retention register                                    */
+  __IO uint32_t  RAMON;                             /*!< Deprecated register - RAM on/off register (this register is
+                                                         retained)                                                             */
+  __I  uint32_t  RESERVED9[11];
+  __IO uint32_t  RAMONB;                            /*!< Deprecated register - RAM on/off register (this register is
+                                                         retained)                                                             */
+  __I  uint32_t  RESERVED10[8];
+  __IO uint32_t  DCDCEN;                            /*!< DC/DC enable register                                                 */
+  __I  uint32_t  RESERVED11[225];
+  POWER_RAM_Type RAM[8];                            /*!< Unspecified                                                           */
+} NRF_POWER_Type;
+
+
+/* ================================================================================ */
+/* ================                      CLOCK                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Clock control (CLOCK)
+  */
+
+typedef struct {                                    /*!< CLOCK Structure                                                       */
+  __O  uint32_t  TASKS_HFCLKSTART;                  /*!< Start HFCLK crystal oscillator                                        */
+  __O  uint32_t  TASKS_HFCLKSTOP;                   /*!< Stop HFCLK crystal oscillator                                         */
+  __O  uint32_t  TASKS_LFCLKSTART;                  /*!< Start LFCLK source                                                    */
+  __O  uint32_t  TASKS_LFCLKSTOP;                   /*!< Stop LFCLK source                                                     */
+  __O  uint32_t  TASKS_CAL;                         /*!< Start calibration of LFRC oscillator                                  */
+  __O  uint32_t  TASKS_CTSTART;                     /*!< Start calibration timer                                               */
+  __O  uint32_t  TASKS_CTSTOP;                      /*!< Stop calibration timer                                                */
+  __I  uint32_t  RESERVED0[57];
+  __IO uint32_t  EVENTS_HFCLKSTARTED;               /*!< HFCLK oscillator started                                              */
+  __IO uint32_t  EVENTS_LFCLKSTARTED;               /*!< LFCLK started                                                         */
+  __I  uint32_t  RESERVED1;
+  __IO uint32_t  EVENTS_DONE;                       /*!< Calibration of LFCLK RC oscillator complete event                     */
+  __IO uint32_t  EVENTS_CTTO;                       /*!< Calibration timer timeout                                             */
+  __I  uint32_t  RESERVED2[124];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __I  uint32_t  HFCLKRUN;                          /*!< Status indicating that HFCLKSTART task has been triggered             */
+  __I  uint32_t  HFCLKSTAT;                         /*!< HFCLK status                                                          */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  LFCLKRUN;                          /*!< Status indicating that LFCLKSTART task has been triggered             */
+  __I  uint32_t  LFCLKSTAT;                         /*!< LFCLK status                                                          */
+  __I  uint32_t  LFCLKSRCCOPY;                      /*!< Copy of LFCLKSRC register, set when LFCLKSTART task was triggered     */
+  __I  uint32_t  RESERVED5[62];
+  __IO uint32_t  LFCLKSRC;                          /*!< Clock source for the LFCLK                                            */
+  __I  uint32_t  RESERVED6[7];
+  __IO uint32_t  CTIV;                              /*!< Calibration timer interval (retained register, same reset behaviour
+                                                         as RESETREAS)                                                         */
+  __I  uint32_t  RESERVED7[8];
+  __IO uint32_t  TRACECONFIG;                       /*!< Clocking options for the Trace Port debug interface                   */
+} NRF_CLOCK_Type;
+
+
+/* ================================================================================ */
+/* ================                      AMLI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AHB Multi-Layer Interface (AMLI)
+  */
+
+typedef struct {                                    /*!< AMLI Structure                                                        */
+  __I  uint32_t  RESERVED0[896];
+  AMLI_RAMPRI_Type RAMPRI;                          /*!< RAM configurable priority configuration structure                     */
+} NRF_AMLI_Type;
+
+
+/* ================================================================================ */
+/* ================                      RADIO                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief 2.4 GHz Radio (RADIO)
+  */
+
+typedef struct {                                    /*!< RADIO Structure                                                       */
+  __O  uint32_t  TASKS_TXEN;                        /*!< Enable RADIO in TX mode                                               */
+  __O  uint32_t  TASKS_RXEN;                        /*!< Enable RADIO in RX mode                                               */
+  __O  uint32_t  TASKS_START;                       /*!< Start RADIO                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RADIO                                                            */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable RADIO                                                         */
+  __O  uint32_t  TASKS_RSSISTART;                   /*!< Start the RSSI and take one single sample of the receive signal
+                                                         strength.                                                             */
+  __O  uint32_t  TASKS_RSSISTOP;                    /*!< Stop the RSSI measurement                                             */
+  __O  uint32_t  TASKS_BCSTART;                     /*!< Start the bit counter                                                 */
+  __O  uint32_t  TASKS_BCSTOP;                      /*!< Stop the bit counter                                                  */
+  __I  uint32_t  RESERVED0[55];
+  __IO uint32_t  EVENTS_READY;                      /*!< RADIO has ramped up and is ready to be started                        */
+  __IO uint32_t  EVENTS_ADDRESS;                    /*!< Address sent or received                                              */
+  __IO uint32_t  EVENTS_PAYLOAD;                    /*!< Packet payload sent or received                                       */
+  __IO uint32_t  EVENTS_END;                        /*!< Packet sent or received                                               */
+  __IO uint32_t  EVENTS_DISABLED;                   /*!< RADIO has been disabled                                               */
+  __IO uint32_t  EVENTS_DEVMATCH;                   /*!< A device address match occurred on the last received packet           */
+  __IO uint32_t  EVENTS_DEVMISS;                    /*!< No device address match occurred on the last received packet          */
+  __IO uint32_t  EVENTS_RSSIEND;                    /*!< Sampling of receive signal strength complete.                         */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_BCMATCH;                    /*!< Bit counter reached bit count value.                                  */
+  __I  uint32_t  RESERVED2;
+  __IO uint32_t  EVENTS_CRCOK;                      /*!< Packet received with CRC ok                                           */
+  __IO uint32_t  EVENTS_CRCERROR;                   /*!< Packet received with CRC error                                        */
+  __I  uint32_t  RESERVED3[50];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED4[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[61];
+  __I  uint32_t  CRCSTATUS;                         /*!< CRC status                                                            */
+  __I  uint32_t  RESERVED6;
+  __I  uint32_t  RXMATCH;                           /*!< Received address                                                      */
+  __I  uint32_t  RXCRC;                             /*!< CRC field of previously received packet                               */
+  __I  uint32_t  DAI;                               /*!< Device address match index                                            */
+  __I  uint32_t  RESERVED7[60];
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer                                                        */
+  __IO uint32_t  FREQUENCY;                         /*!< Frequency                                                             */
+  __IO uint32_t  TXPOWER;                           /*!< Output power                                                          */
+  __IO uint32_t  MODE;                              /*!< Data rate and modulation                                              */
+  __IO uint32_t  PCNF0;                             /*!< Packet configuration register 0                                       */
+  __IO uint32_t  PCNF1;                             /*!< Packet configuration register 1                                       */
+  __IO uint32_t  BASE0;                             /*!< Base address 0                                                        */
+  __IO uint32_t  BASE1;                             /*!< Base address 1                                                        */
+  __IO uint32_t  PREFIX0;                           /*!< Prefixes bytes for logical addresses 0-3                              */
+  __IO uint32_t  PREFIX1;                           /*!< Prefixes bytes for logical addresses 4-7                              */
+  __IO uint32_t  TXADDRESS;                         /*!< Transmit address select                                               */
+  __IO uint32_t  RXADDRESSES;                       /*!< Receive address select                                                */
+  __IO uint32_t  CRCCNF;                            /*!< CRC configuration                                                     */
+  __IO uint32_t  CRCPOLY;                           /*!< CRC polynomial                                                        */
+  __IO uint32_t  CRCINIT;                           /*!< CRC initial value                                                     */
+  __IO uint32_t  UNUSED0;                           /*!< Unspecified                                                           */
+  __IO uint32_t  TIFS;                              /*!< Inter Frame Spacing in us                                             */
+  __I  uint32_t  RSSISAMPLE;                        /*!< RSSI sample                                                           */
+  __I  uint32_t  RESERVED8;
+  __I  uint32_t  STATE;                             /*!< Current radio state                                                   */
+  __IO uint32_t  DATAWHITEIV;                       /*!< Data whitening initial value                                          */
+  __I  uint32_t  RESERVED9[2];
+  __IO uint32_t  BCC;                               /*!< Bit counter compare                                                   */
+  __I  uint32_t  RESERVED10[39];
+  __IO uint32_t  DAB[8];                            /*!< Description collection[0]: Device address base segment 0              */
+  __IO uint32_t  DAP[8];                            /*!< Description collection[0]: Device address prefix 0                    */
+  __IO uint32_t  DACNF;                             /*!< Device address match configuration                                    */
+  __I  uint32_t  RESERVED11[3];
+  __IO uint32_t  MODECNF0;                          /*!< Radio mode configuration register 0                                   */
+  __I  uint32_t  RESERVED12[618];
+  __IO uint32_t  POWER;                             /*!< Peripheral power control                                              */
+} NRF_RADIO_Type;
+
+
+/* ================================================================================ */
+/* ================                      UARTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief UART with EasyDMA (UARTE)
+  */
+
+typedef struct {                                    /*!< UARTE Structure                                                       */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[7];
+  __O  uint32_t  TASKS_FLUSHRX;                     /*!< Flush RX FIFO into RX buffer                                          */
+  __I  uint32_t  RESERVED1[52];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< Receive buffer is filled up                                           */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Last TX byte transmitted                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< UART receiver has started                                             */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< UART transmitter has started                                          */
+  __I  uint32_t  RESERVED6;
+  __IO uint32_t  EVENTS_TXSTOPPED;                  /*!< Transmitter stopped                                                   */
+  __I  uint32_t  RESERVED7[41];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED11;
+  UARTE_PSEL_Type PSEL;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[3];
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */
+  __I  uint32_t  RESERVED13[3];
+  UARTE_RXD_Type RXD;                               /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14;
+  UARTE_TXD_Type TXD;                               /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED15[7];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UARTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      UART                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Universal Asynchronous Receiver/Transmitter (UART)
+  */
+
+typedef struct {                                    /*!< UART Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start UART receiver                                                   */
+  __O  uint32_t  TASKS_STOPRX;                      /*!< Stop UART receiver                                                    */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start UART transmitter                                                */
+  __O  uint32_t  TASKS_STOPTX;                      /*!< Stop UART transmitter                                                 */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend UART                                                          */
+  __I  uint32_t  RESERVED1[56];
+  __IO uint32_t  EVENTS_CTS;                        /*!< CTS is activated (set low). Clear To Send.                            */
+  __IO uint32_t  EVENTS_NCTS;                       /*!< CTS is deactivated (set high). Not Clear To Send.                     */
+  __IO uint32_t  EVENTS_RXDRDY;                     /*!< Data received in RXD                                                  */
+  __I  uint32_t  RESERVED2[4];
+  __IO uint32_t  EVENTS_TXDRDY;                     /*!< Data sent from TXD                                                    */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< Error detected                                                        */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_RXTO;                       /*!< Receiver timeout                                                      */
+  __I  uint32_t  RESERVED5[46];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED6[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED7[93];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED8[31];
+  __IO uint32_t  ENABLE;                            /*!< Enable UART                                                           */
+  __I  uint32_t  RESERVED9;
+  __IO uint32_t  PSELRTS;                           /*!< Pin select for RTS                                                    */
+  __IO uint32_t  PSELTXD;                           /*!< Pin select for TXD                                                    */
+  __IO uint32_t  PSELCTS;                           /*!< Pin select for CTS                                                    */
+  __IO uint32_t  PSELRXD;                           /*!< Pin select for RXD                                                    */
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __O  uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED10;
+  __IO uint32_t  BAUDRATE;                          /*!< Baud rate                                                             */
+  __I  uint32_t  RESERVED11[17];
+  __IO uint32_t  CONFIG;                            /*!< Configuration of parity and hardware flow control                     */
+} NRF_UART_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface Master with EasyDMA 0 (SPIM)
+  */
+
+typedef struct {                                    /*!< SPIM Structure                                                        */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_START;                       /*!< Start SPI transaction                                                 */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop SPI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend SPI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume SPI transaction                                                */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< SPI transaction has stopped                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_END;                        /*!< End of RXD buffer and TXD buffer reached                              */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< End of TXD buffer reached                                             */
+  __I  uint32_t  RESERVED6[10];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< Transaction started                                                   */
+  __I  uint32_t  RESERVED7[44];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPIM                                                           */
+  __I  uint32_t  RESERVED10;
+  SPIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11[4];
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED12[3];
+  SPIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  SPIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character clocked out in case and over-read
+                                                         of the TXD buffer.                                                    */
+} NRF_SPIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      SPIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief SPI Slave 0 (SPIS)
+  */
+
+typedef struct {                                    /*!< SPIS Structure                                                        */
+  __I  uint32_t  RESERVED0[9];
+  __O  uint32_t  TASKS_ACQUIRE;                     /*!< Acquire SPI semaphore                                                 */
+  __O  uint32_t  TASKS_RELEASE;                     /*!< Release SPI semaphore, enabling the SPI slave to acquire it           */
+  __I  uint32_t  RESERVED1[54];
+  __IO uint32_t  EVENTS_END;                        /*!< Granted transaction completed                                         */
+  __I  uint32_t  RESERVED2[2];
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< End of RXD buffer reached                                             */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  EVENTS_ACQUIRED;                   /*!< Semaphore acquired                                                    */
+  __I  uint32_t  RESERVED4[53];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED6[61];
+  __I  uint32_t  SEMSTAT;                           /*!< Semaphore status register                                             */
+  __I  uint32_t  RESERVED7[15];
+  __IO uint32_t  STATUS;                            /*!< Status from last transaction                                          */
+  __I  uint32_t  RESERVED8[47];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI slave                                                      */
+  __I  uint32_t  RESERVED9;
+  SPIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[7];
+  SPIS_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED11;
+  SPIS_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED13;
+  __IO uint32_t  DEF;                               /*!< Default character. Character clocked out in case of an ignored
+                                                         transaction.                                                          */
+  __I  uint32_t  RESERVED14[24];
+  __IO uint32_t  ORC;                               /*!< Over-read character                                                   */
+} NRF_SPIS_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Master Interface with EasyDMA 0 (TWIM)
+  */
+
+typedef struct {                                    /*!< TWIM Structure                                                        */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction. Must be issued while the TWI master is
+                                                         not suspended.                                                        */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< Last byte has been sent out after the SUSPEND task has been
+                                                         issued, TWI traffic is now suspended.                                 */
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[2];
+  __IO uint32_t  EVENTS_LASTRX;                     /*!< Byte boundary, starting to receive the last byte                      */
+  __IO uint32_t  EVENTS_LASTTX;                     /*!< Byte boundary, starting to transmit the last byte                     */
+  __I  uint32_t  RESERVED7[39];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED10[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIM                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIM_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[5];
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
+  __I  uint32_t  RESERVED13[3];
+  TWIM_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  TWIM_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[13];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWIM_Type;
+
+
+/* ================================================================================ */
+/* ================                      TWIS                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Slave Interface with EasyDMA 0 (TWIS)
+  */
+
+typedef struct {                                    /*!< TWIS Structure                                                        */
+  __I  uint32_t  RESERVED0[5];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED2[3];
+  __O  uint32_t  TASKS_PREPARERX;                   /*!< Prepare the TWI slave to respond to a write command                   */
+  __O  uint32_t  TASKS_PREPARETX;                   /*!< Prepare the TWI slave to respond to a read command                    */
+  __I  uint32_t  RESERVED3[51];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __I  uint32_t  RESERVED4[7];
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED5[9];
+  __IO uint32_t  EVENTS_RXSTARTED;                  /*!< Receive sequence started                                              */
+  __IO uint32_t  EVENTS_TXSTARTED;                  /*!< Transmit sequence started                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_WRITE;                      /*!< Write command received                                                */
+  __IO uint32_t  EVENTS_READ;                       /*!< Read command received                                                 */
+  __I  uint32_t  RESERVED7[37];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED8[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED9[113];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  MATCH;                             /*!< Status register indicating which address had a match                  */
+  __I  uint32_t  RESERVED10[10];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWIS                                                           */
+  __I  uint32_t  RESERVED11;
+  TWIS_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED12[9];
+  TWIS_RXD_Type RXD;                                /*!< RXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED13;
+  TWIS_TXD_Type TXD;                                /*!< TXD EasyDMA channel                                                   */
+  __I  uint32_t  RESERVED14[14];
+  __IO uint32_t  ADDRESS[2];                        /*!< Description collection[0]: TWI slave address 0                        */
+  __I  uint32_t  RESERVED15;
+  __IO uint32_t  CONFIG;                            /*!< Configuration register for the address match mechanism                */
+  __I  uint32_t  RESERVED16[10];
+  __IO uint32_t  ORC;                               /*!< Over-read character. Character sent out in case of an over-read
+                                                         of the transmit buffer.                                               */
+} NRF_TWIS_Type;
+
+
+/* ================================================================================ */
+/* ================                       SPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Serial Peripheral Interface 0 (SPI)
+  */
+
+typedef struct {                                    /*!< SPI Structure                                                         */
+  __I  uint32_t  RESERVED0[66];
+  __IO uint32_t  EVENTS_READY;                      /*!< TXD byte sent and RXD byte received                                   */
+  __I  uint32_t  RESERVED1[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable SPI                                                            */
+  __I  uint32_t  RESERVED3;
+  SPI_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4;
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  FREQUENCY;                         /*!< SPI frequency                                                         */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+} NRF_SPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       TWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief I2C compatible Two-Wire Interface 0 (TWI)
+  */
+
+typedef struct {                                    /*!< TWI Structure                                                         */
+  __O  uint32_t  TASKS_STARTRX;                     /*!< Start TWI receive sequence                                            */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start TWI transmit sequence                                           */
+  __I  uint32_t  RESERVED1[2];
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop TWI transaction                                                  */
+  __I  uint32_t  RESERVED2;
+  __O  uint32_t  TASKS_SUSPEND;                     /*!< Suspend TWI transaction                                               */
+  __O  uint32_t  TASKS_RESUME;                      /*!< Resume TWI transaction                                                */
+  __I  uint32_t  RESERVED3[56];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< TWI stopped                                                           */
+  __IO uint32_t  EVENTS_RXDREADY;                   /*!< TWI RXD byte received                                                 */
+  __I  uint32_t  RESERVED4[4];
+  __IO uint32_t  EVENTS_TXDSENT;                    /*!< TWI TXD byte sent                                                     */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  EVENTS_ERROR;                      /*!< TWI error                                                             */
+  __I  uint32_t  RESERVED6[4];
+  __IO uint32_t  EVENTS_BB;                         /*!< TWI byte boundary, generated before each byte that is sent or
+                                                         received                                                              */
+  __I  uint32_t  RESERVED7[3];
+  __IO uint32_t  EVENTS_SUSPENDED;                  /*!< TWI entered the suspended state                                       */
+  __I  uint32_t  RESERVED8[45];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED9[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED10[110];
+  __IO uint32_t  ERRORSRC;                          /*!< Error source                                                          */
+  __I  uint32_t  RESERVED11[14];
+  __IO uint32_t  ENABLE;                            /*!< Enable TWI                                                            */
+  __I  uint32_t  RESERVED12;
+  __IO uint32_t  PSELSCL;                           /*!< Pin select for SCL                                                    */
+  __IO uint32_t  PSELSDA;                           /*!< Pin select for SDA                                                    */
+  __I  uint32_t  RESERVED13[2];
+  __I  uint32_t  RXD;                               /*!< RXD register                                                          */
+  __IO uint32_t  TXD;                               /*!< TXD register                                                          */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  FREQUENCY;                         /*!< TWI frequency                                                         */
+  __I  uint32_t  RESERVED15[24];
+  __IO uint32_t  ADDRESS;                           /*!< Address used in the TWI transfer                                      */
+} NRF_TWI_Type;
+
+
+/* ================================================================================ */
+/* ================                      NFCT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief NFC-A compatible radio (NFCT)
+  */
+
+typedef struct {                                    /*!< NFCT Structure                                                        */
+  __O  uint32_t  TASKS_ACTIVATE;                    /*!< Activate NFC peripheral for incoming and outgoing frames, change
+                                                         state to activated                                                    */
+  __O  uint32_t  TASKS_DISABLE;                     /*!< Disable NFC peripheral                                                */
+  __O  uint32_t  TASKS_SENSE;                       /*!< Enable NFC sense field mode, change state to sense mode               */
+  __O  uint32_t  TASKS_STARTTX;                     /*!< Start transmission of a outgoing frame, change state to transmit      */
+  __I  uint32_t  RESERVED0[3];
+  __O  uint32_t  TASKS_ENABLERXDATA;                /*!< Initializes the EasyDMA for receive.                                  */
+  __I  uint32_t  RESERVED1;
+  __O  uint32_t  TASKS_GOIDLE;                      /*!< Force state machine to IDLE state                                     */
+  __O  uint32_t  TASKS_GOSLEEP;                     /*!< Force state machine to SLEEP_A state                                  */
+  __I  uint32_t  RESERVED2[53];
+  __IO uint32_t  EVENTS_READY;                      /*!< The NFC peripheral is ready to receive and send frames                */
+  __IO uint32_t  EVENTS_FIELDDETECTED;              /*!< Remote NFC field detected                                             */
+  __IO uint32_t  EVENTS_FIELDLOST;                  /*!< Remote NFC field lost                                                 */
+  __IO uint32_t  EVENTS_TXFRAMESTART;               /*!< Marks the start of the first symbol of a transmitted frame            */
+  __IO uint32_t  EVENTS_TXFRAMEEND;                 /*!< Marks the end of the last transmitted on-air symbol of a frame        */
+  __IO uint32_t  EVENTS_RXFRAMESTART;               /*!< Marks the end of the first symbol of a received frame                 */
+  __IO uint32_t  EVENTS_RXFRAMEEND;                 /*!< Received data have been checked (CRC, parity) and transferred
+                                                         to RAM, and EasyDMA has ended accessing the RX buffer                 */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< NFC error reported. The ERRORSTATUS register contains details
+                                                         on the source of the error.                                           */
+  __I  uint32_t  RESERVED3[2];
+  __IO uint32_t  EVENTS_RXERROR;                    /*!< NFC RX frame error reported. The FRAMESTATUS.RX register contains
+                                                         details on the source of the error.                                   */
+  __IO uint32_t  EVENTS_ENDRX;                      /*!< RX buffer (as defined by PACKETPTR and MAXLEN) in Data RAM full.      */
+  __IO uint32_t  EVENTS_ENDTX;                      /*!< Transmission of data in RAM has ended, and EasyDMA has ended
+                                                         accessing the TX buffer                                               */
+  __I  uint32_t  RESERVED4;
+  __IO uint32_t  EVENTS_AUTOCOLRESSTARTED;          /*!< Auto collision resolution process has started                         */
+  __I  uint32_t  RESERVED5[3];
+  __IO uint32_t  EVENTS_COLLISION;                  /*!< NFC Auto collision resolution error reported.                         */
+  __IO uint32_t  EVENTS_SELECTED;                   /*!< NFC Auto collision resolution successfully completed                  */
+  __IO uint32_t  EVENTS_STARTED;                    /*!< EasyDMA is ready to receive or send frames.                           */
+  __I  uint32_t  RESERVED6[43];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED7[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED8[62];
+  __IO uint32_t  ERRORSTATUS;                       /*!< NFC Error Status register                                             */
+  __I  uint32_t  RESERVED9;
+  NFCT_FRAMESTATUS_Type FRAMESTATUS;                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED10[8];
+  __I  uint32_t  CURRENTLOADCTRL;                   /*!< Current value driven to the NFC Load Control                          */
+  __I  uint32_t  RESERVED11[2];
+  __I  uint32_t  FIELDPRESENT;                      /*!< Indicates the presence or not of a valid field                        */
+  __I  uint32_t  RESERVED12[49];
+  __IO uint32_t  FRAMEDELAYMIN;                     /*!< Minimum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMAX;                     /*!< Maximum frame delay                                                   */
+  __IO uint32_t  FRAMEDELAYMODE;                    /*!< Configuration register for the Frame Delay Timer                      */
+  __IO uint32_t  PACKETPTR;                         /*!< Packet pointer for TXD and RXD data storage in Data RAM               */
+  __IO uint32_t  MAXLEN;                            /*!< Size of allocated for TXD and RXD data storage buffer in Data
+                                                         RAM                                                                   */
+  NFCT_TXD_Type TXD;                                /*!< Unspecified                                                           */
+  NFCT_RXD_Type RXD;                                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED13[26];
+  __IO uint32_t  NFCID1_LAST;                       /*!< Last NFCID1 part (4, 7 or 10 bytes ID)                                */
+  __IO uint32_t  NFCID1_2ND_LAST;                   /*!< Second last NFCID1 part (7 or 10 bytes ID)                            */
+  __IO uint32_t  NFCID1_3RD_LAST;                   /*!< Third last NFCID1 part (10 bytes ID)                                  */
+  __I  uint32_t  RESERVED14;
+  __IO uint32_t  SENSRES;                           /*!< NFC-A SENS_RES auto-response settings                                 */
+  __IO uint32_t  SELRES;                            /*!< NFC-A SEL_RES auto-response settings                                  */
+} NRF_NFCT_Type;
+
+
+/* ================================================================================ */
+/* ================                     GPIOTE                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Tasks and Events (GPIOTE)
+  */
+
+typedef struct {                                    /*!< GPIOTE Structure                                                      */
+  __O  uint32_t  TASKS_OUT[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is configured in CONFIG[0].POLARITY. */
+  __I  uint32_t  RESERVED0[4];
+  __O  uint32_t  TASKS_SET[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it high.                   */
+  __I  uint32_t  RESERVED1[4];
+  __O  uint32_t  TASKS_CLR[8];                      /*!< Description collection[0]: Task for writing to pin specified
+                                                         in CONFIG[0].PSEL. Action on pin is to set it low.                    */
+  __I  uint32_t  RESERVED2[32];
+  __IO uint32_t  EVENTS_IN[8];                      /*!< Description collection[0]: Event generated from pin specified
+                                                         in CONFIG[0].PSEL                                                     */
+  __I  uint32_t  RESERVED3[23];
+  __IO uint32_t  EVENTS_PORT;                       /*!< Event generated from multiple input GPIO pins with SENSE mechanism
+                                                         enabled                                                               */
+  __I  uint32_t  RESERVED4[97];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED5[129];
+  __IO uint32_t  CONFIG[8];                         /*!< Description collection[0]: Configuration for OUT[n], SET[n]
+                                                         and CLR[n] tasks and IN[n] event                                      */
+} NRF_GPIOTE_Type;
+
+
+/* ================================================================================ */
+/* ================                      SAADC                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Analog to Digital Converter (SAADC)
+  */
+
+typedef struct {                                    /*!< SAADC Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start the ADC and prepare the result buffer in RAM                    */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Take one ADC sample, if scan is enabled all channels are sampled      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop the ADC and terminate any on-going conversion                    */
+  __O  uint32_t  TASKS_CALIBRATEOFFSET;             /*!< Starts offset auto-calibration                                        */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< The ADC has started                                                   */
+  __IO uint32_t  EVENTS_END;                        /*!< The ADC has filled up the Result buffer                               */
+  __IO uint32_t  EVENTS_DONE;                       /*!< A conversion task has been completed. Depending on the mode,
+                                                         multiple conversions might be needed for a result to be transferred
+                                                          to RAM.                                                              */
+  __IO uint32_t  EVENTS_RESULTDONE;                 /*!< A result is ready to get transferred to RAM.                          */
+  __IO uint32_t  EVENTS_CALIBRATEDONE;              /*!< Calibration is complete                                               */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< The ADC has stopped                                                   */
+  SAADC_EVENTS_CH_Type EVENTS_CH[8];                /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[106];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  STATUS;                            /*!< Status                                                                */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable or disable ADC                                                 */
+  __I  uint32_t  RESERVED4[3];
+  SAADC_CH_Type CH[8];                              /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[24];
+  __IO uint32_t  RESOLUTION;                        /*!< Resolution configuration                                              */
+  __IO uint32_t  OVERSAMPLE;                        /*!< Oversampling configuration. OVERSAMPLE should not be combined
+                                                         with SCAN. The RESOLUTION is applied before averaging, thus
+                                                          for high OVERSAMPLE a higher RESOLUTION should be used.              */
+  __IO uint32_t  SAMPLERATE;                        /*!< Controls normal or continuous sample rate                             */
+  __I  uint32_t  RESERVED6[12];
+  SAADC_RESULT_Type RESULT;                         /*!< RESULT EasyDMA channel                                                */
+} NRF_SAADC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TIMER                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Timer/Counter 0 (TIMER)
+  */
+
+typedef struct {                                    /*!< TIMER Structure                                                       */
+  __O  uint32_t  TASKS_START;                       /*!< Start Timer                                                           */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop Timer                                                            */
+  __O  uint32_t  TASKS_COUNT;                       /*!< Increment Timer (Counter mode only)                                   */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear time                                                            */
+  __O  uint32_t  TASKS_SHUTDOWN;                    /*!< Deprecated register - Shut down timer                                 */
+  __I  uint32_t  RESERVED0[11];
+  __O  uint32_t  TASKS_CAPTURE[6];                  /*!< Description collection[0]: Capture Timer value to CC[0] register      */
+  __I  uint32_t  RESERVED1[58];
+  __IO uint32_t  EVENTS_COMPARE[6];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[42];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[126];
+  __IO uint32_t  MODE;                              /*!< Timer mode selection                                                  */
+  __IO uint32_t  BITMODE;                           /*!< Configure the number of bits used by the TIMER                        */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  PRESCALER;                         /*!< Timer prescaler register                                              */
+  __I  uint32_t  RESERVED6[11];
+  __IO uint32_t  CC[6];                             /*!< Description collection[0]: Capture/Compare register 0                 */
+} NRF_TIMER_Type;
+
+
+/* ================================================================================ */
+/* ================                       RTC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Real time counter 0 (RTC)
+  */
+
+typedef struct {                                    /*!< RTC Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop RTC COUNTER                                                      */
+  __O  uint32_t  TASKS_CLEAR;                       /*!< Clear RTC COUNTER                                                     */
+  __O  uint32_t  TASKS_TRIGOVRFLW;                  /*!< Set COUNTER to 0xFFFFF0                                               */
+  __I  uint32_t  RESERVED0[60];
+  __IO uint32_t  EVENTS_TICK;                       /*!< Event on COUNTER increment                                            */
+  __IO uint32_t  EVENTS_OVRFLW;                     /*!< Event on COUNTER overflow                                             */
+  __I  uint32_t  RESERVED1[14];
+  __IO uint32_t  EVENTS_COMPARE[4];                 /*!< Description collection[0]: Compare event on CC[0] match               */
+  __I  uint32_t  RESERVED2[109];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[13];
+  __IO uint32_t  EVTEN;                             /*!< Enable or disable event routing                                       */
+  __IO uint32_t  EVTENSET;                          /*!< Enable event routing                                                  */
+  __IO uint32_t  EVTENCLR;                          /*!< Disable event routing                                                 */
+  __I  uint32_t  RESERVED4[110];
+  __I  uint32_t  COUNTER;                           /*!< Current COUNTER value                                                 */
+  __IO uint32_t  PRESCALER;                         /*!< 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must
+                                                         be written when RTC is stopped                                        */
+  __I  uint32_t  RESERVED5[13];
+  __IO uint32_t  CC[4];                             /*!< Description collection[0]: Compare register 0                         */
+} NRF_RTC_Type;
+
+
+/* ================================================================================ */
+/* ================                      TEMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Temperature Sensor (TEMP)
+  */
+
+typedef struct {                                    /*!< TEMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start temperature measurement                                         */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop temperature measurement                                          */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_DATARDY;                    /*!< Temperature measurement complete, data ready                          */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[127];
+  __I  int32_t   TEMP;                              /*!< Temperature in degC (0.25deg steps)                                   */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  A0;                                /*!< Slope of 1st piece wise linear function                               */
+  __IO uint32_t  A1;                                /*!< Slope of 2nd piece wise linear function                               */
+  __IO uint32_t  A2;                                /*!< Slope of 3rd piece wise linear function                               */
+  __IO uint32_t  A3;                                /*!< Slope of 4th piece wise linear function                               */
+  __IO uint32_t  A4;                                /*!< Slope of 5th piece wise linear function                               */
+  __IO uint32_t  A5;                                /*!< Slope of 6th piece wise linear function                               */
+  __I  uint32_t  RESERVED4[2];
+  __IO uint32_t  B0;                                /*!< y-intercept of 1st piece wise linear function                         */
+  __IO uint32_t  B1;                                /*!< y-intercept of 2nd piece wise linear function                         */
+  __IO uint32_t  B2;                                /*!< y-intercept of 3rd piece wise linear function                         */
+  __IO uint32_t  B3;                                /*!< y-intercept of 4th piece wise linear function                         */
+  __IO uint32_t  B4;                                /*!< y-intercept of 5th piece wise linear function                         */
+  __IO uint32_t  B5;                                /*!< y-intercept of 6th piece wise linear function                         */
+  __I  uint32_t  RESERVED5[2];
+  __IO uint32_t  T0;                                /*!< End point of 1st piece wise linear function                           */
+  __IO uint32_t  T1;                                /*!< End point of 2nd piece wise linear function                           */
+  __IO uint32_t  T2;                                /*!< End point of 3rd piece wise linear function                           */
+  __IO uint32_t  T3;                                /*!< End point of 4th piece wise linear function                           */
+  __IO uint32_t  T4;                                /*!< End point of 5th piece wise linear function                           */
+} NRF_TEMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       RNG                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Random Number Generator (RNG)
+  */
+
+typedef struct {                                    /*!< RNG Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the random number generator                             */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the random number generator                             */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_VALRDY;                     /*!< Event being generated for every new random number written to
+                                                         the VALUE register                                                    */
+  __I  uint32_t  RESERVED1[63];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[126];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  VALUE;                             /*!< Output random number                                                  */
+} NRF_RNG_Type;
+
+
+/* ================================================================================ */
+/* ================                       ECB                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES ECB Mode Encryption (ECB)
+  */
+
+typedef struct {                                    /*!< ECB Structure                                                         */
+  __O  uint32_t  TASKS_STARTECB;                    /*!< Start ECB block encrypt                                               */
+  __O  uint32_t  TASKS_STOPECB;                     /*!< Abort a possible executing ECB operation                              */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_ENDECB;                     /*!< ECB block encrypt complete                                            */
+  __IO uint32_t  EVENTS_ERRORECB;                   /*!< ECB block encrypt aborted because of a STOPECB task or due to
+                                                         an error                                                              */
+  __I  uint32_t  RESERVED1[127];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  ECBDATAPTR;                        /*!< ECB block encrypt memory pointers                                     */
+} NRF_ECB_Type;
+
+
+/* ================================================================================ */
+/* ================                       CCM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief AES CCM Mode Encryption (CCM)
+  */
+
+typedef struct {                                    /*!< CCM Structure                                                         */
+  __O  uint32_t  TASKS_KSGEN;                       /*!< Start generation of key-stream. This operation will stop by
+                                                         itself when completed.                                                */
+  __O  uint32_t  TASKS_CRYPT;                       /*!< Start encryption/decryption. This operation will stop by itself
+                                                         when completed.                                                       */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop encryption/decryption                                            */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_ENDKSGEN;                   /*!< Key-stream generation complete                                        */
+  __IO uint32_t  EVENTS_ENDCRYPT;                   /*!< Encrypt/decrypt complete                                              */
+  __IO uint32_t  EVENTS_ERROR;                      /*!< CCM error event                                                       */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  MICSTATUS;                         /*!< MIC check result                                                      */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable                                                                */
+  __IO uint32_t  MODE;                              /*!< Operation mode                                                        */
+  __IO uint32_t  CNFPTR;                            /*!< Pointer to data structure holding AES key and NONCE vector            */
+  __IO uint32_t  INPTR;                             /*!< Input pointer                                                         */
+  __IO uint32_t  OUTPTR;                            /*!< Output pointer                                                        */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_CCM_Type;
+
+
+/* ================================================================================ */
+/* ================                       AAR                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Accelerated Address Resolver (AAR)
+  */
+
+typedef struct {                                    /*!< AAR Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start resolving addresses based on IRKs specified in the IRK
+                                                         data structure                                                        */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop resolving addresses                                              */
+  __I  uint32_t  RESERVED1[61];
+  __IO uint32_t  EVENTS_END;                        /*!< Address resolution procedure complete                                 */
+  __IO uint32_t  EVENTS_RESOLVED;                   /*!< Address resolved                                                      */
+  __IO uint32_t  EVENTS_NOTRESOLVED;                /*!< Address not resolved                                                  */
+  __I  uint32_t  RESERVED2[126];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  STATUS;                            /*!< Resolution status                                                     */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable AAR                                                            */
+  __IO uint32_t  NIRK;                              /*!< Number of IRKs                                                        */
+  __IO uint32_t  IRKPTR;                            /*!< Pointer to IRK data structure                                         */
+  __I  uint32_t  RESERVED5;
+  __IO uint32_t  ADDRPTR;                           /*!< Pointer to the resolvable address                                     */
+  __IO uint32_t  SCRATCHPTR;                        /*!< Pointer to data area used for temporary storage                       */
+} NRF_AAR_Type;
+
+
+/* ================================================================================ */
+/* ================                       WDT                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Watchdog Timer (WDT)
+  */
+
+typedef struct {                                    /*!< WDT Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Start the watchdog                                                    */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_TIMEOUT;                    /*!< Watchdog timeout                                                      */
+  __I  uint32_t  RESERVED1[128];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[61];
+  __I  uint32_t  RUNSTATUS;                         /*!< Run status                                                            */
+  __I  uint32_t  REQSTATUS;                         /*!< Request status                                                        */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  CRV;                               /*!< Counter reload value                                                  */
+  __IO uint32_t  RREN;                              /*!< Enable register for reload request registers                          */
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  __I  uint32_t  RESERVED4[60];
+  __O  uint32_t  RR[8];                             /*!< Description collection[0]: Reload request 0                           */
+} NRF_WDT_Type;
+
+
+/* ================================================================================ */
+/* ================                      QDEC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Quadrature Decoder (QDEC)
+  */
+
+typedef struct {                                    /*!< QDEC Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Task starting the quadrature decoder                                  */
+  __O  uint32_t  TASKS_STOP;                        /*!< Task stopping the quadrature decoder                                  */
+  __O  uint32_t  TASKS_READCLRACC;                  /*!< Read and clear ACC and ACCDBL                                         */
+  __O  uint32_t  TASKS_RDCLRACC;                    /*!< Read and clear ACC                                                    */
+  __O  uint32_t  TASKS_RDCLRDBL;                    /*!< Read and clear ACCDBL                                                 */
+  __I  uint32_t  RESERVED0[59];
+  __IO uint32_t  EVENTS_SAMPLERDY;                  /*!< Event being generated for every new sample value written to
+                                                         the SAMPLE register                                                   */
+  __IO uint32_t  EVENTS_REPORTRDY;                  /*!< Non-null report ready                                                 */
+  __IO uint32_t  EVENTS_ACCOF;                      /*!< ACC or ACCDBL register overflow                                       */
+  __IO uint32_t  EVENTS_DBLRDY;                     /*!< Double displacement(s) detected                                       */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< QDEC has been stopped                                                 */
+  __I  uint32_t  RESERVED1[59];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable the quadrature decoder                                         */
+  __IO uint32_t  LEDPOL;                            /*!< LED output pin polarity                                               */
+  __IO uint32_t  SAMPLEPER;                         /*!< Sample period                                                         */
+  __I  int32_t   SAMPLE;                            /*!< Motion sample value                                                   */
+  __IO uint32_t  REPORTPER;                         /*!< Number of samples to be taken before REPORTRDY and DBLRDY events
+                                                         can be generated                                                      */
+  __I  int32_t   ACC;                               /*!< Register accumulating the valid transitions                           */
+  __I  int32_t   ACCREAD;                           /*!< Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC
+                                                         task                                                                  */
+  QDEC_PSEL_Type PSEL;                              /*!< Unspecified                                                           */
+  __IO uint32_t  DBFEN;                             /*!< Enable input debounce filters                                         */
+  __I  uint32_t  RESERVED4[5];
+  __IO uint32_t  LEDPRE;                            /*!< Time period the LED is switched ON prior to sampling                  */
+  __I  uint32_t  ACCDBL;                            /*!< Register accumulating the number of detected double transitions       */
+  __I  uint32_t  ACCDBLREAD;                        /*!< Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL
+                                                         task                                                                  */
+} NRF_QDEC_Type;
+
+
+/* ================================================================================ */
+/* ================                      COMP                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Comparator (COMP)
+  */
+
+typedef struct {                                    /*!< COMP Structure                                                        */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< COMP is ready and output is valid                                     */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< COMP enable                                                           */
+  __IO uint32_t  PSEL;                              /*!< Pin select                                                            */
+  __IO uint32_t  REFSEL;                            /*!< Reference source select                                               */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[8];
+  __IO uint32_t  TH;                                /*!< Threshold configuration for hysteresis unit                           */
+  __IO uint32_t  MODE;                              /*!< Mode configuration                                                    */
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+  __IO uint32_t  ISOURCE;                           /*!< Current source select on analog input                                 */
+} NRF_COMP_Type;
+
+
+/* ================================================================================ */
+/* ================                     LPCOMP                     ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Low Power Comparator (LPCOMP)
+  */
+
+typedef struct {                                    /*!< LPCOMP Structure                                                      */
+  __O  uint32_t  TASKS_START;                       /*!< Start comparator                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stop comparator                                                       */
+  __O  uint32_t  TASKS_SAMPLE;                      /*!< Sample comparator value                                               */
+  __I  uint32_t  RESERVED0[61];
+  __IO uint32_t  EVENTS_READY;                      /*!< LPCOMP is ready and output is valid                                   */
+  __IO uint32_t  EVENTS_DOWN;                       /*!< Downward crossing                                                     */
+  __IO uint32_t  EVENTS_UP;                         /*!< Upward crossing                                                       */
+  __IO uint32_t  EVENTS_CROSS;                      /*!< Downward or upward crossing                                           */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED2[64];
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[61];
+  __I  uint32_t  RESULT;                            /*!< Compare result                                                        */
+  __I  uint32_t  RESERVED4[63];
+  __IO uint32_t  ENABLE;                            /*!< Enable LPCOMP                                                         */
+  __IO uint32_t  PSEL;                              /*!< Input pin select                                                      */
+  __IO uint32_t  REFSEL;                            /*!< Reference select                                                      */
+  __IO uint32_t  EXTREFSEL;                         /*!< External reference select                                             */
+  __I  uint32_t  RESERVED5[4];
+  __IO uint32_t  ANADETECT;                         /*!< Analog detect configuration                                           */
+  __I  uint32_t  RESERVED6[5];
+  __IO uint32_t  HYST;                              /*!< Comparator hysteresis enable                                          */
+} NRF_LPCOMP_Type;
+
+
+/* ================================================================================ */
+/* ================                       SWI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Software interrupt 0 (SWI)
+  */
+
+typedef struct {                                    /*!< SWI Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_SWI_Type;
+
+
+/* ================================================================================ */
+/* ================                       EGU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Event Generator Unit 0 (EGU)
+  */
+
+typedef struct {                                    /*!< EGU Structure                                                         */
+  __O  uint32_t  TASKS_TRIGGER[16];                 /*!< Description collection[0]: Trigger 0 for triggering the corresponding
+                                                         TRIGGERED[0] event                                                    */
+  __I  uint32_t  RESERVED0[48];
+  __IO uint32_t  EVENTS_TRIGGERED[16];              /*!< Description collection[0]: Event number 0 generated by triggering
+                                                         the corresponding TRIGGER[0] task                                     */
+  __I  uint32_t  RESERVED1[112];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+} NRF_EGU_Type;
+
+
+/* ================================================================================ */
+/* ================                       PWM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Width Modulation Unit 0 (PWM)
+  */
+
+typedef struct {                                    /*!< PWM Structure                                                         */
+  __I  uint32_t  RESERVED0;
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PWM pulse generation on all channels at the end of current
+                                                         PWM period, and stops sequence playback                               */
+  __O  uint32_t  TASKS_SEQSTART[2];                 /*!< Description collection[0]: Loads the first PWM value on all
+                                                         enabled channels from sequence 0, and starts playing that sequence
+                                                          at the rate defined in SEQ[0]REFRESH and/or DECODER.MODE. Causes
+                                                          PWM generation to start it was not running.                          */
+  __O  uint32_t  TASKS_NEXTSTEP;                    /*!< Steps by one value in the current sequence on all enabled channels
+                                                         if DECODER.MODE=NextStep. Does not cause PWM generation to start
+                                                          it was not running.                                                  */
+  __I  uint32_t  RESERVED1[60];
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< Response to STOP task, emitted when PWM pulses are no longer
+                                                         generated                                                             */
+  __IO uint32_t  EVENTS_SEQSTARTED[2];              /*!< Description collection[0]: First PWM period started on sequence
+                                                         0                                                                     */
+  __IO uint32_t  EVENTS_SEQEND[2];                  /*!< Description collection[0]: Emitted at end of every sequence
+                                                         0, when last value from RAM has been applied to wave counter          */
+  __IO uint32_t  EVENTS_PWMPERIODEND;               /*!< Emitted at the end of each PWM period                                 */
+  __IO uint32_t  EVENTS_LOOPSDONE;                  /*!< Concatenated sequences have been played the amount of times
+                                                         defined in LOOP.CNT                                                   */
+  __I  uint32_t  RESERVED2[56];
+  __IO uint32_t  SHORTS;                            /*!< Shortcut register                                                     */
+  __I  uint32_t  RESERVED3[63];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED4[125];
+  __IO uint32_t  ENABLE;                            /*!< PWM module enable register                                            */
+  __IO uint32_t  MODE;                              /*!< Selects operating mode of the wave counter                            */
+  __IO uint32_t  COUNTERTOP;                        /*!< Value up to which the pulse generator counter counts                  */
+  __IO uint32_t  PRESCALER;                         /*!< Configuration for PWM_CLK                                             */
+  __IO uint32_t  DECODER;                           /*!< Configuration of the decoder                                          */
+  __IO uint32_t  LOOP;                              /*!< Amount of playback of a loop                                          */
+  __I  uint32_t  RESERVED5[2];
+  PWM_SEQ_Type SEQ[2];                              /*!< Unspecified                                                           */
+  PWM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_PWM_Type;
+
+
+/* ================================================================================ */
+/* ================                       PDM                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Pulse Density Modulation (Digital Microphone) Interface (PDM)
+  */
+
+typedef struct {                                    /*!< PDM Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous PDM transfer                                        */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops PDM transfer                                                    */
+  __I  uint32_t  RESERVED0[62];
+  __IO uint32_t  EVENTS_STARTED;                    /*!< PDM transfer has started                                              */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< PDM transfer has finished                                             */
+  __IO uint32_t  EVENTS_END;                        /*!< The PDM has written the last sample specified by SAMPLE.MAXCNT
+                                                         (or the last sample after a STOP task has been received) to
+                                                          Data RAM                                                             */
+  __I  uint32_t  RESERVED1[125];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED2[125];
+  __IO uint32_t  ENABLE;                            /*!< PDM module enable register                                            */
+  __IO uint32_t  PDMCLKCTRL;                        /*!< PDM clock generator control                                           */
+  __IO uint32_t  MODE;                              /*!< Defines the routing of the connected PDM microphones' signals         */
+  __I  uint32_t  RESERVED3[3];
+  __IO uint32_t  GAINL;                             /*!< Left output gain adjustment                                           */
+  __IO uint32_t  GAINR;                             /*!< Right output gain adjustment                                          */
+  __I  uint32_t  RESERVED4[8];
+  PDM_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[6];
+  PDM_SAMPLE_Type SAMPLE;                           /*!< Unspecified                                                           */
+} NRF_PDM_Type;
+
+
+/* ================================================================================ */
+/* ================                      NVMC                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Non Volatile Memory Controller (NVMC)
+  */
+
+typedef struct {                                    /*!< NVMC Structure                                                        */
+  __I  uint32_t  RESERVED0[256];
+  __I  uint32_t  READY;                             /*!< Ready flag                                                            */
+  __I  uint32_t  RESERVED1[64];
+  __IO uint32_t  CONFIG;                            /*!< Configuration register                                                */
+  
+  union {
+    __IO uint32_t  ERASEPCR1;                       /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+    __IO uint32_t  ERASEPAGE;                       /*!< Register for erasing a page in Code area                              */
+  };
+  __IO uint32_t  ERASEALL;                          /*!< Register for erasing all non-volatile user memory                     */
+  __IO uint32_t  ERASEPCR0;                         /*!< Deprecated register - Register for erasing a page in Code area.
+                                                         Equivalent to ERASEPAGE.                                              */
+  __IO uint32_t  ERASEUICR;                         /*!< Register for erasing User Information Configuration Registers         */
+  __I  uint32_t  RESERVED2[10];
+  __IO uint32_t  ICACHECNF;                         /*!< I-Code cache configuration register.                                  */
+  __I  uint32_t  RESERVED3;
+  __IO uint32_t  IHIT;                              /*!< I-Code cache hit counter.                                             */
+  __IO uint32_t  IMISS;                             /*!< I-Code cache miss counter.                                            */
+} NRF_NVMC_Type;
+
+
+/* ================================================================================ */
+/* ================                       PPI                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Programmable Peripheral Interconnect (PPI)
+  */
+
+typedef struct {                                    /*!< PPI Structure                                                         */
+  PPI_TASKS_CHG_Type TASKS_CHG[6];                  /*!< Channel group tasks                                                   */
+  __I  uint32_t  RESERVED0[308];
+  __IO uint32_t  CHEN;                              /*!< Channel enable register                                               */
+  __IO uint32_t  CHENSET;                           /*!< Channel enable set register                                           */
+  __IO uint32_t  CHENCLR;                           /*!< Channel enable clear register                                         */
+  __I  uint32_t  RESERVED1;
+  PPI_CH_Type CH[20];                               /*!< PPI Channel                                                           */
+  __I  uint32_t  RESERVED2[148];
+  __IO uint32_t  CHG[6];                            /*!< Description collection[0]: Channel group 0                            */
+  __I  uint32_t  RESERVED3[62];
+  PPI_FORK_Type FORK[32];                           /*!< Fork                                                                  */
+} NRF_PPI_Type;
+
+
+/* ================================================================================ */
+/* ================                       MWU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Memory Watch Unit (MWU)
+  */
+
+typedef struct {                                    /*!< MWU Structure                                                         */
+  __I  uint32_t  RESERVED0[64];
+  MWU_EVENTS_REGION_Type EVENTS_REGION[4];          /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED1[16];
+  MWU_EVENTS_PREGION_Type EVENTS_PREGION[2];        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED2[100];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[5];
+  __IO uint32_t  NMIEN;                             /*!< Enable or disable non-maskable interrupt                              */
+  __IO uint32_t  NMIENSET;                          /*!< Enable non-maskable interrupt                                         */
+  __IO uint32_t  NMIENCLR;                          /*!< Disable non-maskable interrupt                                        */
+  __I  uint32_t  RESERVED4[53];
+  MWU_PERREGION_Type PERREGION[2];                  /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5[64];
+  __IO uint32_t  REGIONEN;                          /*!< Enable/disable regions watch                                          */
+  __IO uint32_t  REGIONENSET;                       /*!< Enable regions watch                                                  */
+  __IO uint32_t  REGIONENCLR;                       /*!< Disable regions watch                                                 */
+  __I  uint32_t  RESERVED6[57];
+  MWU_REGION_Type REGION[4];                        /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[32];
+  MWU_PREGION_Type PREGION[2];                      /*!< Unspecified                                                           */
+} NRF_MWU_Type;
+
+
+/* ================================================================================ */
+/* ================                       I2S                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief Inter-IC Sound (I2S)
+  */
+
+typedef struct {                                    /*!< I2S Structure                                                         */
+  __O  uint32_t  TASKS_START;                       /*!< Starts continuous I2S transfer. Also starts MCK generator when
+                                                         this is enabled.                                                      */
+  __O  uint32_t  TASKS_STOP;                        /*!< Stops I2S transfer. Also stops MCK generator. Triggering this
+                                                         task will cause the {event:STOPPED} event to be generated.            */
+  __I  uint32_t  RESERVED0[63];
+  __IO uint32_t  EVENTS_RXPTRUPD;                   /*!< The RXD.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and RX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are received
+                                                          on the SDIN pin.                                                     */
+  __IO uint32_t  EVENTS_STOPPED;                    /*!< I2S transfer stopped.                                                 */
+  __I  uint32_t  RESERVED1[2];
+  __IO uint32_t  EVENTS_TXPTRUPD;                   /*!< The TDX.PTR register has been copied to internal double-buffers.
+                                                         When the I2S module is started and TX is enabled, this event
+                                                          will be generated for every RXTXD.MAXCNT words that are sent
+                                                          on the SDOUT pin.                                                    */
+  __I  uint32_t  RESERVED2[122];
+  __IO uint32_t  INTEN;                             /*!< Enable or disable interrupt                                           */
+  __IO uint32_t  INTENSET;                          /*!< Enable interrupt                                                      */
+  __IO uint32_t  INTENCLR;                          /*!< Disable interrupt                                                     */
+  __I  uint32_t  RESERVED3[125];
+  __IO uint32_t  ENABLE;                            /*!< Enable I2S module.                                                    */
+  I2S_CONFIG_Type CONFIG;                           /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED4[3];
+  I2S_RXD_Type RXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED5;
+  I2S_TXD_Type TXD;                                 /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED6[3];
+  I2S_RXTXD_Type RXTXD;                             /*!< Unspecified                                                           */
+  __I  uint32_t  RESERVED7[3];
+  I2S_PSEL_Type PSEL;                               /*!< Unspecified                                                           */
+} NRF_I2S_Type;
+
+
+/* ================================================================================ */
+/* ================                       FPU                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief FPU (FPU)
+  */
+
+typedef struct {                                    /*!< FPU Structure                                                         */
+  __I  uint32_t  UNUSED;                            /*!< Unused.                                                               */
+} NRF_FPU_Type;
+
+
+/* ================================================================================ */
+/* ================                      GPIO                      ================ */
+/* ================================================================================ */
+
+
+/**
+  * @brief GPIO Port 1 (GPIO)
+  */
+
+typedef struct {                                    /*!< GPIO Structure                                                        */
+  __I  uint32_t  RESERVED0[321];
+  __IO uint32_t  OUT;                               /*!< Write GPIO port                                                       */
+  __IO uint32_t  OUTSET;                            /*!< Set individual bits in GPIO port                                      */
+  __IO uint32_t  OUTCLR;                            /*!< Clear individual bits in GPIO port                                    */
+  __I  uint32_t  IN;                                /*!< Read GPIO port                                                        */
+  __IO uint32_t  DIR;                               /*!< Direction of GPIO pins                                                */
+  __IO uint32_t  DIRSET;                            /*!< DIR set register                                                      */
+  __IO uint32_t  DIRCLR;                            /*!< DIR clear register                                                    */
+  __IO uint32_t  LATCH;                             /*!< Latch register indicating what GPIO pins that have met the criteria
+                                                         set in the PIN_CNF[n].SENSE registers                                 */
+  __IO uint32_t  DETECTMODE;                        /*!< Select between default DETECT signal behaviour and LDETECT mode       */
+  __I  uint32_t  RESERVED1[118];
+  __IO uint32_t  PIN_CNF[32];                       /*!< Description collection[0]: Configuration of GPIO pins                 */
+} NRF_GPIO_Type;
+
+
+/* --------------------  End of section using anonymous unions  ------------------- */
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TMS470__)
+  /* anonymous unions are enabled by default */
+#elif defined(__TASKING__)
+  #pragma warning restore
+#else
+  #warning Not supported compiler type
+#endif
+
+
+
+
+/* ================================================================================ */
+/* ================              Peripheral memory map             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR_BASE                   0x10000000UL
+#define NRF_UICR_BASE                   0x10001000UL
+#define NRF_BPROT_BASE                  0x40000000UL
+#define NRF_POWER_BASE                  0x40000000UL
+#define NRF_CLOCK_BASE                  0x40000000UL
+#define NRF_AMLI_BASE                   0x40000000UL
+#define NRF_RADIO_BASE                  0x40001000UL
+#define NRF_UARTE0_BASE                 0x40002000UL
+#define NRF_UART0_BASE                  0x40002000UL
+#define NRF_SPIM0_BASE                  0x40003000UL
+#define NRF_SPIS0_BASE                  0x40003000UL
+#define NRF_TWIM0_BASE                  0x40003000UL
+#define NRF_TWIS0_BASE                  0x40003000UL
+#define NRF_SPI0_BASE                   0x40003000UL
+#define NRF_TWI0_BASE                   0x40003000UL
+#define NRF_SPIM1_BASE                  0x40004000UL
+#define NRF_SPIS1_BASE                  0x40004000UL
+#define NRF_TWIM1_BASE                  0x40004000UL
+#define NRF_TWIS1_BASE                  0x40004000UL
+#define NRF_SPI1_BASE                   0x40004000UL
+#define NRF_TWI1_BASE                   0x40004000UL
+#define NRF_NFCT_BASE                   0x40005000UL
+#define NRF_GPIOTE_BASE                 0x40006000UL
+#define NRF_SAADC_BASE                  0x40007000UL
+#define NRF_TIMER0_BASE                 0x40008000UL
+#define NRF_TIMER1_BASE                 0x40009000UL
+#define NRF_TIMER2_BASE                 0x4000A000UL
+#define NRF_RTC0_BASE                   0x4000B000UL
+#define NRF_TEMP_BASE                   0x4000C000UL
+#define NRF_RNG_BASE                    0x4000D000UL
+#define NRF_ECB_BASE                    0x4000E000UL
+#define NRF_CCM_BASE                    0x4000F000UL
+#define NRF_AAR_BASE                    0x4000F000UL
+#define NRF_WDT_BASE                    0x40010000UL
+#define NRF_RTC1_BASE                   0x40011000UL
+#define NRF_QDEC_BASE                   0x40012000UL
+#define NRF_COMP_BASE                   0x40013000UL
+#define NRF_LPCOMP_BASE                 0x40013000UL
+#define NRF_SWI0_BASE                   0x40014000UL
+#define NRF_EGU0_BASE                   0x40014000UL
+#define NRF_SWI1_BASE                   0x40015000UL
+#define NRF_EGU1_BASE                   0x40015000UL
+#define NRF_SWI2_BASE                   0x40016000UL
+#define NRF_EGU2_BASE                   0x40016000UL
+#define NRF_SWI3_BASE                   0x40017000UL
+#define NRF_EGU3_BASE                   0x40017000UL
+#define NRF_SWI4_BASE                   0x40018000UL
+#define NRF_EGU4_BASE                   0x40018000UL
+#define NRF_SWI5_BASE                   0x40019000UL
+#define NRF_EGU5_BASE                   0x40019000UL
+#define NRF_TIMER3_BASE                 0x4001A000UL
+#define NRF_TIMER4_BASE                 0x4001B000UL
+#define NRF_PWM0_BASE                   0x4001C000UL
+#define NRF_PDM_BASE                    0x4001D000UL
+#define NRF_NVMC_BASE                   0x4001E000UL
+#define NRF_PPI_BASE                    0x4001F000UL
+#define NRF_MWU_BASE                    0x40020000UL
+#define NRF_PWM1_BASE                   0x40021000UL
+#define NRF_PWM2_BASE                   0x40022000UL
+#define NRF_SPIM2_BASE                  0x40023000UL
+#define NRF_SPIS2_BASE                  0x40023000UL
+#define NRF_SPI2_BASE                   0x40023000UL
+#define NRF_RTC2_BASE                   0x40024000UL
+#define NRF_I2S_BASE                    0x40025000UL
+#define NRF_FPU_BASE                    0x40026000UL
+#define NRF_P0_BASE                     0x50000000UL
+
+
+/* ================================================================================ */
+/* ================             Peripheral declaration             ================ */
+/* ================================================================================ */
+
+#define NRF_FICR                        ((NRF_FICR_Type           *) NRF_FICR_BASE)
+#define NRF_UICR                        ((NRF_UICR_Type           *) NRF_UICR_BASE)
+#define NRF_BPROT                       ((NRF_BPROT_Type          *) NRF_BPROT_BASE)
+#define NRF_POWER                       ((NRF_POWER_Type          *) NRF_POWER_BASE)
+#define NRF_CLOCK                       ((NRF_CLOCK_Type          *) NRF_CLOCK_BASE)
+#define NRF_AMLI                        ((NRF_AMLI_Type           *) NRF_AMLI_BASE)
+#define NRF_RADIO                       ((NRF_RADIO_Type          *) NRF_RADIO_BASE)
+#define NRF_UARTE0                      ((NRF_UARTE_Type          *) NRF_UARTE0_BASE)
+#define NRF_UART0                       ((NRF_UART_Type           *) NRF_UART0_BASE)
+#define NRF_SPIM0                       ((NRF_SPIM_Type           *) NRF_SPIM0_BASE)
+#define NRF_SPIS0                       ((NRF_SPIS_Type           *) NRF_SPIS0_BASE)
+#define NRF_TWIM0                       ((NRF_TWIM_Type           *) NRF_TWIM0_BASE)
+#define NRF_TWIS0                       ((NRF_TWIS_Type           *) NRF_TWIS0_BASE)
+#define NRF_SPI0                        ((NRF_SPI_Type            *) NRF_SPI0_BASE)
+#define NRF_TWI0                        ((NRF_TWI_Type            *) NRF_TWI0_BASE)
+#define NRF_SPIM1                       ((NRF_SPIM_Type           *) NRF_SPIM1_BASE)
+#define NRF_SPIS1                       ((NRF_SPIS_Type           *) NRF_SPIS1_BASE)
+#define NRF_TWIM1                       ((NRF_TWIM_Type           *) NRF_TWIM1_BASE)
+#define NRF_TWIS1                       ((NRF_TWIS_Type           *) NRF_TWIS1_BASE)
+#define NRF_SPI1                        ((NRF_SPI_Type            *) NRF_SPI1_BASE)
+#define NRF_TWI1                        ((NRF_TWI_Type            *) NRF_TWI1_BASE)
+#define NRF_NFCT                        ((NRF_NFCT_Type           *) NRF_NFCT_BASE)
+#define NRF_GPIOTE                      ((NRF_GPIOTE_Type         *) NRF_GPIOTE_BASE)
+#define NRF_SAADC                       ((NRF_SAADC_Type          *) NRF_SAADC_BASE)
+#define NRF_TIMER0                      ((NRF_TIMER_Type          *) NRF_TIMER0_BASE)
+#define NRF_TIMER1                      ((NRF_TIMER_Type          *) NRF_TIMER1_BASE)
+#define NRF_TIMER2                      ((NRF_TIMER_Type          *) NRF_TIMER2_BASE)
+#define NRF_RTC0                        ((NRF_RTC_Type            *) NRF_RTC0_BASE)
+#define NRF_TEMP                        ((NRF_TEMP_Type           *) NRF_TEMP_BASE)
+#define NRF_RNG                         ((NRF_RNG_Type            *) NRF_RNG_BASE)
+#define NRF_ECB                         ((NRF_ECB_Type            *) NRF_ECB_BASE)
+#define NRF_CCM                         ((NRF_CCM_Type            *) NRF_CCM_BASE)
+#define NRF_AAR                         ((NRF_AAR_Type            *) NRF_AAR_BASE)
+#define NRF_WDT                         ((NRF_WDT_Type            *) NRF_WDT_BASE)
+#define NRF_RTC1                        ((NRF_RTC_Type            *) NRF_RTC1_BASE)
+#define NRF_QDEC                        ((NRF_QDEC_Type           *) NRF_QDEC_BASE)
+#define NRF_COMP                        ((NRF_COMP_Type           *) NRF_COMP_BASE)
+#define NRF_LPCOMP                      ((NRF_LPCOMP_Type         *) NRF_LPCOMP_BASE)
+#define NRF_SWI0                        ((NRF_SWI_Type            *) NRF_SWI0_BASE)
+#define NRF_EGU0                        ((NRF_EGU_Type            *) NRF_EGU0_BASE)
+#define NRF_SWI1                        ((NRF_SWI_Type            *) NRF_SWI1_BASE)
+#define NRF_EGU1                        ((NRF_EGU_Type            *) NRF_EGU1_BASE)
+#define NRF_SWI2                        ((NRF_SWI_Type            *) NRF_SWI2_BASE)
+#define NRF_EGU2                        ((NRF_EGU_Type            *) NRF_EGU2_BASE)
+#define NRF_SWI3                        ((NRF_SWI_Type            *) NRF_SWI3_BASE)
+#define NRF_EGU3                        ((NRF_EGU_Type            *) NRF_EGU3_BASE)
+#define NRF_SWI4                        ((NRF_SWI_Type            *) NRF_SWI4_BASE)
+#define NRF_EGU4                        ((NRF_EGU_Type            *) NRF_EGU4_BASE)
+#define NRF_SWI5                        ((NRF_SWI_Type            *) NRF_SWI5_BASE)
+#define NRF_EGU5                        ((NRF_EGU_Type            *) NRF_EGU5_BASE)
+#define NRF_TIMER3                      ((NRF_TIMER_Type          *) NRF_TIMER3_BASE)
+#define NRF_TIMER4                      ((NRF_TIMER_Type          *) NRF_TIMER4_BASE)
+#define NRF_PWM0                        ((NRF_PWM_Type            *) NRF_PWM0_BASE)
+#define NRF_PDM                         ((NRF_PDM_Type            *) NRF_PDM_BASE)
+#define NRF_NVMC                        ((NRF_NVMC_Type           *) NRF_NVMC_BASE)
+#define NRF_PPI                         ((NRF_PPI_Type            *) NRF_PPI_BASE)
+#define NRF_MWU                         ((NRF_MWU_Type            *) NRF_MWU_BASE)
+#define NRF_PWM1                        ((NRF_PWM_Type            *) NRF_PWM1_BASE)
+#define NRF_PWM2                        ((NRF_PWM_Type            *) NRF_PWM2_BASE)
+#define NRF_SPIM2                       ((NRF_SPIM_Type           *) NRF_SPIM2_BASE)
+#define NRF_SPIS2                       ((NRF_SPIS_Type           *) NRF_SPIS2_BASE)
+#define NRF_SPI2                        ((NRF_SPI_Type            *) NRF_SPI2_BASE)
+#define NRF_RTC2                        ((NRF_RTC_Type            *) NRF_RTC2_BASE)
+#define NRF_I2S                         ((NRF_I2S_Type            *) NRF_I2S_BASE)
+#define NRF_FPU                         ((NRF_FPU_Type            *) NRF_FPU_BASE)
+#define NRF_P0                          ((NRF_GPIO_Type           *) NRF_P0_BASE)
+
+
+/** @} */ /* End of group Device_Peripheral_Registers */
+/** @} */ /* End of group nrf52 */
+/** @} */ /* End of group Nordic Semiconductor */
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif  /* nrf52_H */
+
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h
new file mode 100644
index 0000000000..c7802c46a3
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_bitfields.h
@@ -0,0 +1,14870 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef __NRF52_BITS_H
+#define __NRF52_BITS_H
+
+/*lint ++flb "Enter library region" */
+
+/* Peripheral: AAR */
+/* Description: Accelerated Address Resolver */
+
+/* Register: AAR_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for NOTRESOLVED event */
+#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RESOLVED event */
+#define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for END event */
+#define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: AAR_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for NOTRESOLVED event */
+#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
+#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RESOLVED event */
+#define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
+#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for END event */
+#define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
+#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define AAR_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define AAR_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define AAR_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: AAR_STATUS */
+/* Description: Resolution status */
+
+/* Bits 3..0 : The IRK that was used last time an address was resolved */
+#define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+
+/* Register: AAR_ENABLE */
+/* Description: Enable AAR */
+
+/* Bits 1..0 : Enable or disable AAR */
+#define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define AAR_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define AAR_ENABLE_ENABLE_Enabled (3UL) /*!< Enable */
+
+/* Register: AAR_NIRK */
+/* Description: Number of IRKs */
+
+/* Bits 4..0 : Number of Identity root keys available in the IRK data structure */
+#define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
+#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
+
+/* Register: AAR_IRKPTR */
+/* Description: Pointer to IRK data structure */
+
+/* Bits 31..0 : Pointer to the IRK data structure */
+#define AAR_IRKPTR_IRKPTR_Pos (0UL) /*!< Position of IRKPTR field. */
+#define AAR_IRKPTR_IRKPTR_Msk (0xFFFFFFFFUL << AAR_IRKPTR_IRKPTR_Pos) /*!< Bit mask of IRKPTR field. */
+
+/* Register: AAR_ADDRPTR */
+/* Description: Pointer to the resolvable address */
+
+/* Bits 31..0 : Pointer to the resolvable address (6-bytes) */
+#define AAR_ADDRPTR_ADDRPTR_Pos (0UL) /*!< Position of ADDRPTR field. */
+#define AAR_ADDRPTR_ADDRPTR_Msk (0xFFFFFFFFUL << AAR_ADDRPTR_ADDRPTR_Pos) /*!< Bit mask of ADDRPTR field. */
+
+/* Register: AAR_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during resolution.A space of minimum 3 bytes must be reserved. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define AAR_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << AAR_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: AMLI */
+/* Description: AHB Multi-Layer Interface */
+
+/* Register: AMLI_RAMPRI_CPU0 */
+/* Description: AHB bus master priority register for CPU0 */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CPU0_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_SPIS1 */
+/* Description: AHB bus master priority register for SPIM1, SPIS1, TWIM1 and TWIS1 */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SPIS1_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_RADIO */
+/* Description: AHB bus master priority register for RADIO */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_RADIO_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_ECB */
+/* Description: AHB bus master priority register for ECB */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_ECB_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_CCM */
+/* Description: AHB bus master priority register for CCM */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_CCM_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_AAR */
+/* Description: AHB bus master priority register for AAR */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_AAR_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_SAADC */
+/* Description: AHB bus master priority register for SAADC */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_SAADC_RAM7_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_SAADC_RAM6_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_SAADC_RAM5_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_SAADC_RAM4_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_SAADC_RAM3_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_SAADC_RAM2_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_SAADC_RAM1_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_SAADC_RAM0_Msk (0xFUL << AMLI_RAMPRI_SAADC_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SAADC_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_UARTE */
+/* Description: AHB bus master priority register for UARTE */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_UARTE_RAM7_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_UARTE_RAM6_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_UARTE_RAM5_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_UARTE_RAM4_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_UARTE_RAM3_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_UARTE_RAM2_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_UARTE_RAM1_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_UARTE_RAM0_Msk (0xFUL << AMLI_RAMPRI_UARTE_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_UARTE_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_SERIAL0 */
+/* Description: AHB bus master priority register for SPIM0, SPIS0, TWIM0 and TWIS0 */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL0_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_SERIAL2 */
+/* Description: AHB bus master priority register for SPIM2 and SPIS2 */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Msk (0xFUL << AMLI_RAMPRI_SERIAL2_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_SERIAL2_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_NFCT */
+/* Description: AHB bus master priority register for NFCT */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_NFCT_RAM7_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_NFCT_RAM6_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_NFCT_RAM5_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_NFCT_RAM4_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_NFCT_RAM3_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_NFCT_RAM2_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_NFCT_RAM1_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_NFCT_RAM0_Msk (0xFUL << AMLI_RAMPRI_NFCT_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_NFCT_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_I2S */
+/* Description: AHB bus master priority register for I2S */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_I2S_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_I2S_RAM7_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_I2S_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_I2S_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_I2S_RAM6_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_I2S_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_I2S_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_I2S_RAM5_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_I2S_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_I2S_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_I2S_RAM4_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_I2S_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_I2S_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_I2S_RAM3_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_I2S_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_I2S_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_I2S_RAM2_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_I2S_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_I2S_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_I2S_RAM1_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_I2S_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_I2S_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_I2S_RAM0_Msk (0xFUL << AMLI_RAMPRI_I2S_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_I2S_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_I2S_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_PDM */
+/* Description: AHB bus master priority register for PDM */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_PDM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_PDM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_PDM_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_PDM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_PDM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_PDM_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_PDM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_PDM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_PDM_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_PDM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_PDM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_PDM_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_PDM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_PDM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_PDM_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_PDM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_PDM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_PDM_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_PDM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_PDM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_PDM_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_PDM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_PDM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PDM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_PDM_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PDM_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+/* Register: AMLI_RAMPRI_PWM */
+/* Description: AHB bus master priority register for PWM0, PWM1 and PWM2 */
+
+/* Bits 31..28 : Priority register for RAM AHB slave 7 */
+#define AMLI_RAMPRI_PWM_RAM7_Pos (28UL) /*!< Position of RAM7 field. */
+#define AMLI_RAMPRI_PWM_RAM7_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM7_Pos) /*!< Bit mask of RAM7 field. */
+#define AMLI_RAMPRI_PWM_RAM7_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM7_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 27..24 : Priority register for RAM AHB slave 6 */
+#define AMLI_RAMPRI_PWM_RAM6_Pos (24UL) /*!< Position of RAM6 field. */
+#define AMLI_RAMPRI_PWM_RAM6_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM6_Pos) /*!< Bit mask of RAM6 field. */
+#define AMLI_RAMPRI_PWM_RAM6_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM6_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 23..20 : Priority register for RAM AHB slave 5 */
+#define AMLI_RAMPRI_PWM_RAM5_Pos (20UL) /*!< Position of RAM5 field. */
+#define AMLI_RAMPRI_PWM_RAM5_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM5_Pos) /*!< Bit mask of RAM5 field. */
+#define AMLI_RAMPRI_PWM_RAM5_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM5_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 19..16 : Priority register for RAM AHB slave 4 */
+#define AMLI_RAMPRI_PWM_RAM4_Pos (16UL) /*!< Position of RAM4 field. */
+#define AMLI_RAMPRI_PWM_RAM4_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM4_Pos) /*!< Bit mask of RAM4 field. */
+#define AMLI_RAMPRI_PWM_RAM4_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM4_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 15..12 : Priority register for RAM AHB slave 3 */
+#define AMLI_RAMPRI_PWM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
+#define AMLI_RAMPRI_PWM_RAM3_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
+#define AMLI_RAMPRI_PWM_RAM3_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM3_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 11..8 : Priority register for RAM AHB slave 2 */
+#define AMLI_RAMPRI_PWM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
+#define AMLI_RAMPRI_PWM_RAM2_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
+#define AMLI_RAMPRI_PWM_RAM2_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM2_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 7..4 : Priority register for RAM AHB slave 1 */
+#define AMLI_RAMPRI_PWM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
+#define AMLI_RAMPRI_PWM_RAM1_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
+#define AMLI_RAMPRI_PWM_RAM1_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM1_Pri15 (15UL) /*!< Priority 15 */
+
+/* Bits 3..0 : Priority register for RAM AHB slave 0 */
+#define AMLI_RAMPRI_PWM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
+#define AMLI_RAMPRI_PWM_RAM0_Msk (0xFUL << AMLI_RAMPRI_PWM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
+#define AMLI_RAMPRI_PWM_RAM0_Pri0 (0UL) /*!< Priority 0 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri1 (1UL) /*!< Priority 1 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri2 (2UL) /*!< Priority 2 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri3 (3UL) /*!< Priority 3 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri4 (4UL) /*!< Priority 4 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri5 (5UL) /*!< Priority 5 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri6 (6UL) /*!< Priority 6 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri7 (7UL) /*!< Priority 7 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri8 (8UL) /*!< Priority 8 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri9 (9UL) /*!< Priority 9 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri10 (10UL) /*!< Priority 10 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri11 (11UL) /*!< Priority 11 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri12 (12UL) /*!< Priority 12 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri13 (13UL) /*!< Priority 13 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri14 (14UL) /*!< Priority 14 */
+#define AMLI_RAMPRI_PWM_RAM0_Pri15 (15UL) /*!< Priority 15 */
+
+
+/* Peripheral: BPROT */
+/* Description: Block Protect */
+
+/* Register: BPROT_CONFIG0 */
+/* Description: Block protect configuration register 0 */
+
+/* Bit 31 : Enable protection for region 31. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION31_Pos (31UL) /*!< Position of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Msk (0x1UL << BPROT_CONFIG0_REGION31_Pos) /*!< Bit mask of REGION31 field. */
+#define BPROT_CONFIG0_REGION31_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION31_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 30 : Enable protection for region 30. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION30_Pos (30UL) /*!< Position of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Msk (0x1UL << BPROT_CONFIG0_REGION30_Pos) /*!< Bit mask of REGION30 field. */
+#define BPROT_CONFIG0_REGION30_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION30_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 29 : Enable protection for region 29. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION29_Pos (29UL) /*!< Position of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Msk (0x1UL << BPROT_CONFIG0_REGION29_Pos) /*!< Bit mask of REGION29 field. */
+#define BPROT_CONFIG0_REGION29_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION29_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 28 : Enable protection for region 28. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION28_Pos (28UL) /*!< Position of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Msk (0x1UL << BPROT_CONFIG0_REGION28_Pos) /*!< Bit mask of REGION28 field. */
+#define BPROT_CONFIG0_REGION28_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION28_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 27 : Enable protection for region 27. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION27_Pos (27UL) /*!< Position of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Msk (0x1UL << BPROT_CONFIG0_REGION27_Pos) /*!< Bit mask of REGION27 field. */
+#define BPROT_CONFIG0_REGION27_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION27_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 26 : Enable protection for region 26. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION26_Pos (26UL) /*!< Position of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Msk (0x1UL << BPROT_CONFIG0_REGION26_Pos) /*!< Bit mask of REGION26 field. */
+#define BPROT_CONFIG0_REGION26_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION26_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 25 : Enable protection for region 25. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION25_Pos (25UL) /*!< Position of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Msk (0x1UL << BPROT_CONFIG0_REGION25_Pos) /*!< Bit mask of REGION25 field. */
+#define BPROT_CONFIG0_REGION25_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION25_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 24 : Enable protection for region 24. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION24_Pos (24UL) /*!< Position of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Msk (0x1UL << BPROT_CONFIG0_REGION24_Pos) /*!< Bit mask of REGION24 field. */
+#define BPROT_CONFIG0_REGION24_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION24_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 23 : Enable protection for region 23. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION23_Pos (23UL) /*!< Position of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Msk (0x1UL << BPROT_CONFIG0_REGION23_Pos) /*!< Bit mask of REGION23 field. */
+#define BPROT_CONFIG0_REGION23_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION23_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 22 : Enable protection for region 22. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION22_Pos (22UL) /*!< Position of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Msk (0x1UL << BPROT_CONFIG0_REGION22_Pos) /*!< Bit mask of REGION22 field. */
+#define BPROT_CONFIG0_REGION22_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION22_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 21 : Enable protection for region 21. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION21_Pos (21UL) /*!< Position of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Msk (0x1UL << BPROT_CONFIG0_REGION21_Pos) /*!< Bit mask of REGION21 field. */
+#define BPROT_CONFIG0_REGION21_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION21_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 20 : Enable protection for region 20. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION20_Pos (20UL) /*!< Position of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Msk (0x1UL << BPROT_CONFIG0_REGION20_Pos) /*!< Bit mask of REGION20 field. */
+#define BPROT_CONFIG0_REGION20_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION20_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 19 : Enable protection for region 19. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION19_Pos (19UL) /*!< Position of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Msk (0x1UL << BPROT_CONFIG0_REGION19_Pos) /*!< Bit mask of REGION19 field. */
+#define BPROT_CONFIG0_REGION19_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION19_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 18 : Enable protection for region 18. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION18_Pos (18UL) /*!< Position of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Msk (0x1UL << BPROT_CONFIG0_REGION18_Pos) /*!< Bit mask of REGION18 field. */
+#define BPROT_CONFIG0_REGION18_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION18_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 17 : Enable protection for region 17. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION17_Pos (17UL) /*!< Position of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Msk (0x1UL << BPROT_CONFIG0_REGION17_Pos) /*!< Bit mask of REGION17 field. */
+#define BPROT_CONFIG0_REGION17_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION17_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 16 : Enable protection for region 16. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION16_Pos (16UL) /*!< Position of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Msk (0x1UL << BPROT_CONFIG0_REGION16_Pos) /*!< Bit mask of REGION16 field. */
+#define BPROT_CONFIG0_REGION16_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION16_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 15 : Enable protection for region 15. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION15_Pos (15UL) /*!< Position of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Msk (0x1UL << BPROT_CONFIG0_REGION15_Pos) /*!< Bit mask of REGION15 field. */
+#define BPROT_CONFIG0_REGION15_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION15_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 14 : Enable protection for region 14. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION14_Pos (14UL) /*!< Position of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Msk (0x1UL << BPROT_CONFIG0_REGION14_Pos) /*!< Bit mask of REGION14 field. */
+#define BPROT_CONFIG0_REGION14_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION14_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 13 : Enable protection for region 13. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION13_Pos (13UL) /*!< Position of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Msk (0x1UL << BPROT_CONFIG0_REGION13_Pos) /*!< Bit mask of REGION13 field. */
+#define BPROT_CONFIG0_REGION13_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION13_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 12 : Enable protection for region 12. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION12_Pos (12UL) /*!< Position of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Msk (0x1UL << BPROT_CONFIG0_REGION12_Pos) /*!< Bit mask of REGION12 field. */
+#define BPROT_CONFIG0_REGION12_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION12_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 11 : Enable protection for region 11. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION11_Pos (11UL) /*!< Position of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Msk (0x1UL << BPROT_CONFIG0_REGION11_Pos) /*!< Bit mask of REGION11 field. */
+#define BPROT_CONFIG0_REGION11_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION11_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 10 : Enable protection for region 10. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION10_Pos (10UL) /*!< Position of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Msk (0x1UL << BPROT_CONFIG0_REGION10_Pos) /*!< Bit mask of REGION10 field. */
+#define BPROT_CONFIG0_REGION10_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION10_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 9 : Enable protection for region 9. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION9_Pos (9UL) /*!< Position of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Msk (0x1UL << BPROT_CONFIG0_REGION9_Pos) /*!< Bit mask of REGION9 field. */
+#define BPROT_CONFIG0_REGION9_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION9_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 8 : Enable protection for region 8. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION8_Pos (8UL) /*!< Position of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Msk (0x1UL << BPROT_CONFIG0_REGION8_Pos) /*!< Bit mask of REGION8 field. */
+#define BPROT_CONFIG0_REGION8_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION8_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 7 : Enable protection for region 7. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION7_Pos (7UL) /*!< Position of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Msk (0x1UL << BPROT_CONFIG0_REGION7_Pos) /*!< Bit mask of REGION7 field. */
+#define BPROT_CONFIG0_REGION7_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION7_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 6 : Enable protection for region 6. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION6_Pos (6UL) /*!< Position of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Msk (0x1UL << BPROT_CONFIG0_REGION6_Pos) /*!< Bit mask of REGION6 field. */
+#define BPROT_CONFIG0_REGION6_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION6_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 5 : Enable protection for region 5. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION5_Pos (5UL) /*!< Position of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Msk (0x1UL << BPROT_CONFIG0_REGION5_Pos) /*!< Bit mask of REGION5 field. */
+#define BPROT_CONFIG0_REGION5_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION5_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 4 : Enable protection for region 4. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION4_Pos (4UL) /*!< Position of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Msk (0x1UL << BPROT_CONFIG0_REGION4_Pos) /*!< Bit mask of REGION4 field. */
+#define BPROT_CONFIG0_REGION4_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION4_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 3 : Enable protection for region 3. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION3_Pos (3UL) /*!< Position of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Msk (0x1UL << BPROT_CONFIG0_REGION3_Pos) /*!< Bit mask of REGION3 field. */
+#define BPROT_CONFIG0_REGION3_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION3_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 2 : Enable protection for region 2. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION2_Pos (2UL) /*!< Position of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Msk (0x1UL << BPROT_CONFIG0_REGION2_Pos) /*!< Bit mask of REGION2 field. */
+#define BPROT_CONFIG0_REGION2_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION2_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 1 : Enable protection for region 1. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION1_Pos (1UL) /*!< Position of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Msk (0x1UL << BPROT_CONFIG0_REGION1_Pos) /*!< Bit mask of REGION1 field. */
+#define BPROT_CONFIG0_REGION1_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION1_Enabled (1UL) /*!< Protection enable */
+
+/* Bit 0 : Enable protection for region 0. Write '0' has no effect. */
+#define BPROT_CONFIG0_REGION0_Pos (0UL) /*!< Position of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Msk (0x1UL << BPROT_CONFIG0_REGION0_Pos) /*!< Bit mask of REGION0 field. */
+#define BPROT_CONFIG0_REGION0_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG0_REGION0_Enabled (1UL) /*!< Protection enable */
+
+/* Register: BPROT_CONFIG1 */
+/* Description: Block protect configuration register 1 */
+
+/* Bit 31 : Enable protection for region 63. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION63_Pos (31UL) /*!< Position of REGION63 field. */
+#define BPROT_CONFIG1_REGION63_Msk (0x1UL << BPROT_CONFIG1_REGION63_Pos) /*!< Bit mask of REGION63 field. */
+#define BPROT_CONFIG1_REGION63_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION63_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 62. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION62_Pos (30UL) /*!< Position of REGION62 field. */
+#define BPROT_CONFIG1_REGION62_Msk (0x1UL << BPROT_CONFIG1_REGION62_Pos) /*!< Bit mask of REGION62 field. */
+#define BPROT_CONFIG1_REGION62_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION62_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 61. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION61_Pos (29UL) /*!< Position of REGION61 field. */
+#define BPROT_CONFIG1_REGION61_Msk (0x1UL << BPROT_CONFIG1_REGION61_Pos) /*!< Bit mask of REGION61 field. */
+#define BPROT_CONFIG1_REGION61_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION61_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 60. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION60_Pos (28UL) /*!< Position of REGION60 field. */
+#define BPROT_CONFIG1_REGION60_Msk (0x1UL << BPROT_CONFIG1_REGION60_Pos) /*!< Bit mask of REGION60 field. */
+#define BPROT_CONFIG1_REGION60_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION60_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 59. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION59_Pos (27UL) /*!< Position of REGION59 field. */
+#define BPROT_CONFIG1_REGION59_Msk (0x1UL << BPROT_CONFIG1_REGION59_Pos) /*!< Bit mask of REGION59 field. */
+#define BPROT_CONFIG1_REGION59_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION59_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 58. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION58_Pos (26UL) /*!< Position of REGION58 field. */
+#define BPROT_CONFIG1_REGION58_Msk (0x1UL << BPROT_CONFIG1_REGION58_Pos) /*!< Bit mask of REGION58 field. */
+#define BPROT_CONFIG1_REGION58_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION58_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 57. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION57_Pos (25UL) /*!< Position of REGION57 field. */
+#define BPROT_CONFIG1_REGION57_Msk (0x1UL << BPROT_CONFIG1_REGION57_Pos) /*!< Bit mask of REGION57 field. */
+#define BPROT_CONFIG1_REGION57_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION57_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 56. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION56_Pos (24UL) /*!< Position of REGION56 field. */
+#define BPROT_CONFIG1_REGION56_Msk (0x1UL << BPROT_CONFIG1_REGION56_Pos) /*!< Bit mask of REGION56 field. */
+#define BPROT_CONFIG1_REGION56_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION56_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 55. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION55_Pos (23UL) /*!< Position of REGION55 field. */
+#define BPROT_CONFIG1_REGION55_Msk (0x1UL << BPROT_CONFIG1_REGION55_Pos) /*!< Bit mask of REGION55 field. */
+#define BPROT_CONFIG1_REGION55_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION55_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 54. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION54_Pos (22UL) /*!< Position of REGION54 field. */
+#define BPROT_CONFIG1_REGION54_Msk (0x1UL << BPROT_CONFIG1_REGION54_Pos) /*!< Bit mask of REGION54 field. */
+#define BPROT_CONFIG1_REGION54_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION54_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 53. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION53_Pos (21UL) /*!< Position of REGION53 field. */
+#define BPROT_CONFIG1_REGION53_Msk (0x1UL << BPROT_CONFIG1_REGION53_Pos) /*!< Bit mask of REGION53 field. */
+#define BPROT_CONFIG1_REGION53_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION53_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 52. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION52_Pos (20UL) /*!< Position of REGION52 field. */
+#define BPROT_CONFIG1_REGION52_Msk (0x1UL << BPROT_CONFIG1_REGION52_Pos) /*!< Bit mask of REGION52 field. */
+#define BPROT_CONFIG1_REGION52_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION52_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 51. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION51_Pos (19UL) /*!< Position of REGION51 field. */
+#define BPROT_CONFIG1_REGION51_Msk (0x1UL << BPROT_CONFIG1_REGION51_Pos) /*!< Bit mask of REGION51 field. */
+#define BPROT_CONFIG1_REGION51_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION51_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 50. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION50_Pos (18UL) /*!< Position of REGION50 field. */
+#define BPROT_CONFIG1_REGION50_Msk (0x1UL << BPROT_CONFIG1_REGION50_Pos) /*!< Bit mask of REGION50 field. */
+#define BPROT_CONFIG1_REGION50_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION50_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 49. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION49_Pos (17UL) /*!< Position of REGION49 field. */
+#define BPROT_CONFIG1_REGION49_Msk (0x1UL << BPROT_CONFIG1_REGION49_Pos) /*!< Bit mask of REGION49 field. */
+#define BPROT_CONFIG1_REGION49_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION49_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 48. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION48_Pos (16UL) /*!< Position of REGION48 field. */
+#define BPROT_CONFIG1_REGION48_Msk (0x1UL << BPROT_CONFIG1_REGION48_Pos) /*!< Bit mask of REGION48 field. */
+#define BPROT_CONFIG1_REGION48_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION48_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 47. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION47_Pos (15UL) /*!< Position of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Msk (0x1UL << BPROT_CONFIG1_REGION47_Pos) /*!< Bit mask of REGION47 field. */
+#define BPROT_CONFIG1_REGION47_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION47_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 46. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION46_Pos (14UL) /*!< Position of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Msk (0x1UL << BPROT_CONFIG1_REGION46_Pos) /*!< Bit mask of REGION46 field. */
+#define BPROT_CONFIG1_REGION46_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION46_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 45. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION45_Pos (13UL) /*!< Position of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Msk (0x1UL << BPROT_CONFIG1_REGION45_Pos) /*!< Bit mask of REGION45 field. */
+#define BPROT_CONFIG1_REGION45_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION45_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 44. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION44_Pos (12UL) /*!< Position of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Msk (0x1UL << BPROT_CONFIG1_REGION44_Pos) /*!< Bit mask of REGION44 field. */
+#define BPROT_CONFIG1_REGION44_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION44_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 43. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION43_Pos (11UL) /*!< Position of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Msk (0x1UL << BPROT_CONFIG1_REGION43_Pos) /*!< Bit mask of REGION43 field. */
+#define BPROT_CONFIG1_REGION43_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION43_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 42. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION42_Pos (10UL) /*!< Position of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Msk (0x1UL << BPROT_CONFIG1_REGION42_Pos) /*!< Bit mask of REGION42 field. */
+#define BPROT_CONFIG1_REGION42_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION42_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 41. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION41_Pos (9UL) /*!< Position of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Msk (0x1UL << BPROT_CONFIG1_REGION41_Pos) /*!< Bit mask of REGION41 field. */
+#define BPROT_CONFIG1_REGION41_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION41_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 40. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION40_Pos (8UL) /*!< Position of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Msk (0x1UL << BPROT_CONFIG1_REGION40_Pos) /*!< Bit mask of REGION40 field. */
+#define BPROT_CONFIG1_REGION40_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION40_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 39. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION39_Pos (7UL) /*!< Position of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Msk (0x1UL << BPROT_CONFIG1_REGION39_Pos) /*!< Bit mask of REGION39 field. */
+#define BPROT_CONFIG1_REGION39_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION39_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 38. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION38_Pos (6UL) /*!< Position of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Msk (0x1UL << BPROT_CONFIG1_REGION38_Pos) /*!< Bit mask of REGION38 field. */
+#define BPROT_CONFIG1_REGION38_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION38_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 37. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION37_Pos (5UL) /*!< Position of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Msk (0x1UL << BPROT_CONFIG1_REGION37_Pos) /*!< Bit mask of REGION37 field. */
+#define BPROT_CONFIG1_REGION37_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION37_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 36. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION36_Pos (4UL) /*!< Position of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Msk (0x1UL << BPROT_CONFIG1_REGION36_Pos) /*!< Bit mask of REGION36 field. */
+#define BPROT_CONFIG1_REGION36_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION36_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 35. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION35_Pos (3UL) /*!< Position of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Msk (0x1UL << BPROT_CONFIG1_REGION35_Pos) /*!< Bit mask of REGION35 field. */
+#define BPROT_CONFIG1_REGION35_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION35_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 34. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION34_Pos (2UL) /*!< Position of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Msk (0x1UL << BPROT_CONFIG1_REGION34_Pos) /*!< Bit mask of REGION34 field. */
+#define BPROT_CONFIG1_REGION34_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION34_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 33. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION33_Pos (1UL) /*!< Position of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Msk (0x1UL << BPROT_CONFIG1_REGION33_Pos) /*!< Bit mask of REGION33 field. */
+#define BPROT_CONFIG1_REGION33_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION33_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 32. Write '0' has no effect. */
+#define BPROT_CONFIG1_REGION32_Pos (0UL) /*!< Position of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Msk (0x1UL << BPROT_CONFIG1_REGION32_Pos) /*!< Bit mask of REGION32 field. */
+#define BPROT_CONFIG1_REGION32_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG1_REGION32_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_DISABLEINDEBUG */
+/* Description: Disable protection mechanism in debug interface mode */
+
+/* Bit 0 : Disable the protection mechanism for NVM regions while in debug interface mode. This register will only disable the protection mechanism if the device is in debug interface mode. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Enable in debug */
+#define BPROT_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Disable in debug */
+
+/* Register: BPROT_CONFIG2 */
+/* Description: Block protect configuration register 2 */
+
+/* Bit 31 : Enable protection for region 95. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION95_Pos (31UL) /*!< Position of REGION95 field. */
+#define BPROT_CONFIG2_REGION95_Msk (0x1UL << BPROT_CONFIG2_REGION95_Pos) /*!< Bit mask of REGION95 field. */
+#define BPROT_CONFIG2_REGION95_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION95_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 94. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION94_Pos (30UL) /*!< Position of REGION94 field. */
+#define BPROT_CONFIG2_REGION94_Msk (0x1UL << BPROT_CONFIG2_REGION94_Pos) /*!< Bit mask of REGION94 field. */
+#define BPROT_CONFIG2_REGION94_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION94_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 93. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION93_Pos (29UL) /*!< Position of REGION93 field. */
+#define BPROT_CONFIG2_REGION93_Msk (0x1UL << BPROT_CONFIG2_REGION93_Pos) /*!< Bit mask of REGION93 field. */
+#define BPROT_CONFIG2_REGION93_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION93_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 92. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION92_Pos (28UL) /*!< Position of REGION92 field. */
+#define BPROT_CONFIG2_REGION92_Msk (0x1UL << BPROT_CONFIG2_REGION92_Pos) /*!< Bit mask of REGION92 field. */
+#define BPROT_CONFIG2_REGION92_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION92_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 91. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION91_Pos (27UL) /*!< Position of REGION91 field. */
+#define BPROT_CONFIG2_REGION91_Msk (0x1UL << BPROT_CONFIG2_REGION91_Pos) /*!< Bit mask of REGION91 field. */
+#define BPROT_CONFIG2_REGION91_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION91_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 90. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION90_Pos (26UL) /*!< Position of REGION90 field. */
+#define BPROT_CONFIG2_REGION90_Msk (0x1UL << BPROT_CONFIG2_REGION90_Pos) /*!< Bit mask of REGION90 field. */
+#define BPROT_CONFIG2_REGION90_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION90_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 89. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION89_Pos (25UL) /*!< Position of REGION89 field. */
+#define BPROT_CONFIG2_REGION89_Msk (0x1UL << BPROT_CONFIG2_REGION89_Pos) /*!< Bit mask of REGION89 field. */
+#define BPROT_CONFIG2_REGION89_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION89_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 88. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION88_Pos (24UL) /*!< Position of REGION88 field. */
+#define BPROT_CONFIG2_REGION88_Msk (0x1UL << BPROT_CONFIG2_REGION88_Pos) /*!< Bit mask of REGION88 field. */
+#define BPROT_CONFIG2_REGION88_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION88_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 87. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION87_Pos (23UL) /*!< Position of REGION87 field. */
+#define BPROT_CONFIG2_REGION87_Msk (0x1UL << BPROT_CONFIG2_REGION87_Pos) /*!< Bit mask of REGION87 field. */
+#define BPROT_CONFIG2_REGION87_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION87_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 86. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION86_Pos (22UL) /*!< Position of REGION86 field. */
+#define BPROT_CONFIG2_REGION86_Msk (0x1UL << BPROT_CONFIG2_REGION86_Pos) /*!< Bit mask of REGION86 field. */
+#define BPROT_CONFIG2_REGION86_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION86_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 85. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION85_Pos (21UL) /*!< Position of REGION85 field. */
+#define BPROT_CONFIG2_REGION85_Msk (0x1UL << BPROT_CONFIG2_REGION85_Pos) /*!< Bit mask of REGION85 field. */
+#define BPROT_CONFIG2_REGION85_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION85_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 84. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION84_Pos (20UL) /*!< Position of REGION84 field. */
+#define BPROT_CONFIG2_REGION84_Msk (0x1UL << BPROT_CONFIG2_REGION84_Pos) /*!< Bit mask of REGION84 field. */
+#define BPROT_CONFIG2_REGION84_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION84_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 83. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION83_Pos (19UL) /*!< Position of REGION83 field. */
+#define BPROT_CONFIG2_REGION83_Msk (0x1UL << BPROT_CONFIG2_REGION83_Pos) /*!< Bit mask of REGION83 field. */
+#define BPROT_CONFIG2_REGION83_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION83_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 82. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION82_Pos (18UL) /*!< Position of REGION82 field. */
+#define BPROT_CONFIG2_REGION82_Msk (0x1UL << BPROT_CONFIG2_REGION82_Pos) /*!< Bit mask of REGION82 field. */
+#define BPROT_CONFIG2_REGION82_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION82_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 81. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION81_Pos (17UL) /*!< Position of REGION81 field. */
+#define BPROT_CONFIG2_REGION81_Msk (0x1UL << BPROT_CONFIG2_REGION81_Pos) /*!< Bit mask of REGION81 field. */
+#define BPROT_CONFIG2_REGION81_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION81_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 80. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION80_Pos (16UL) /*!< Position of REGION80 field. */
+#define BPROT_CONFIG2_REGION80_Msk (0x1UL << BPROT_CONFIG2_REGION80_Pos) /*!< Bit mask of REGION80 field. */
+#define BPROT_CONFIG2_REGION80_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION80_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 79. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION79_Pos (15UL) /*!< Position of REGION79 field. */
+#define BPROT_CONFIG2_REGION79_Msk (0x1UL << BPROT_CONFIG2_REGION79_Pos) /*!< Bit mask of REGION79 field. */
+#define BPROT_CONFIG2_REGION79_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION79_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 78. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION78_Pos (14UL) /*!< Position of REGION78 field. */
+#define BPROT_CONFIG2_REGION78_Msk (0x1UL << BPROT_CONFIG2_REGION78_Pos) /*!< Bit mask of REGION78 field. */
+#define BPROT_CONFIG2_REGION78_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION78_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 77. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION77_Pos (13UL) /*!< Position of REGION77 field. */
+#define BPROT_CONFIG2_REGION77_Msk (0x1UL << BPROT_CONFIG2_REGION77_Pos) /*!< Bit mask of REGION77 field. */
+#define BPROT_CONFIG2_REGION77_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION77_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 76. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION76_Pos (12UL) /*!< Position of REGION76 field. */
+#define BPROT_CONFIG2_REGION76_Msk (0x1UL << BPROT_CONFIG2_REGION76_Pos) /*!< Bit mask of REGION76 field. */
+#define BPROT_CONFIG2_REGION76_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION76_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 75. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION75_Pos (11UL) /*!< Position of REGION75 field. */
+#define BPROT_CONFIG2_REGION75_Msk (0x1UL << BPROT_CONFIG2_REGION75_Pos) /*!< Bit mask of REGION75 field. */
+#define BPROT_CONFIG2_REGION75_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION75_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 74. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION74_Pos (10UL) /*!< Position of REGION74 field. */
+#define BPROT_CONFIG2_REGION74_Msk (0x1UL << BPROT_CONFIG2_REGION74_Pos) /*!< Bit mask of REGION74 field. */
+#define BPROT_CONFIG2_REGION74_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION74_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 73. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION73_Pos (9UL) /*!< Position of REGION73 field. */
+#define BPROT_CONFIG2_REGION73_Msk (0x1UL << BPROT_CONFIG2_REGION73_Pos) /*!< Bit mask of REGION73 field. */
+#define BPROT_CONFIG2_REGION73_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION73_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 72. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION72_Pos (8UL) /*!< Position of REGION72 field. */
+#define BPROT_CONFIG2_REGION72_Msk (0x1UL << BPROT_CONFIG2_REGION72_Pos) /*!< Bit mask of REGION72 field. */
+#define BPROT_CONFIG2_REGION72_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION72_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 71. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION71_Pos (7UL) /*!< Position of REGION71 field. */
+#define BPROT_CONFIG2_REGION71_Msk (0x1UL << BPROT_CONFIG2_REGION71_Pos) /*!< Bit mask of REGION71 field. */
+#define BPROT_CONFIG2_REGION71_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION71_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 70. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION70_Pos (6UL) /*!< Position of REGION70 field. */
+#define BPROT_CONFIG2_REGION70_Msk (0x1UL << BPROT_CONFIG2_REGION70_Pos) /*!< Bit mask of REGION70 field. */
+#define BPROT_CONFIG2_REGION70_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION70_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 69. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION69_Pos (5UL) /*!< Position of REGION69 field. */
+#define BPROT_CONFIG2_REGION69_Msk (0x1UL << BPROT_CONFIG2_REGION69_Pos) /*!< Bit mask of REGION69 field. */
+#define BPROT_CONFIG2_REGION69_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION69_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 68. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION68_Pos (4UL) /*!< Position of REGION68 field. */
+#define BPROT_CONFIG2_REGION68_Msk (0x1UL << BPROT_CONFIG2_REGION68_Pos) /*!< Bit mask of REGION68 field. */
+#define BPROT_CONFIG2_REGION68_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION68_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 67. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION67_Pos (3UL) /*!< Position of REGION67 field. */
+#define BPROT_CONFIG2_REGION67_Msk (0x1UL << BPROT_CONFIG2_REGION67_Pos) /*!< Bit mask of REGION67 field. */
+#define BPROT_CONFIG2_REGION67_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION67_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 66. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION66_Pos (2UL) /*!< Position of REGION66 field. */
+#define BPROT_CONFIG2_REGION66_Msk (0x1UL << BPROT_CONFIG2_REGION66_Pos) /*!< Bit mask of REGION66 field. */
+#define BPROT_CONFIG2_REGION66_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION66_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 65. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION65_Pos (1UL) /*!< Position of REGION65 field. */
+#define BPROT_CONFIG2_REGION65_Msk (0x1UL << BPROT_CONFIG2_REGION65_Pos) /*!< Bit mask of REGION65 field. */
+#define BPROT_CONFIG2_REGION65_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION65_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 64. Write '0' has no effect. */
+#define BPROT_CONFIG2_REGION64_Pos (0UL) /*!< Position of REGION64 field. */
+#define BPROT_CONFIG2_REGION64_Msk (0x1UL << BPROT_CONFIG2_REGION64_Pos) /*!< Bit mask of REGION64 field. */
+#define BPROT_CONFIG2_REGION64_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG2_REGION64_Enabled (1UL) /*!< Protection enabled */
+
+/* Register: BPROT_CONFIG3 */
+/* Description: Block protect configuration register 3 */
+
+/* Bit 31 : Enable protection for region 127. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION127_Pos (31UL) /*!< Position of REGION127 field. */
+#define BPROT_CONFIG3_REGION127_Msk (0x1UL << BPROT_CONFIG3_REGION127_Pos) /*!< Bit mask of REGION127 field. */
+#define BPROT_CONFIG3_REGION127_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION127_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 30 : Enable protection for region 126. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION126_Pos (30UL) /*!< Position of REGION126 field. */
+#define BPROT_CONFIG3_REGION126_Msk (0x1UL << BPROT_CONFIG3_REGION126_Pos) /*!< Bit mask of REGION126 field. */
+#define BPROT_CONFIG3_REGION126_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION126_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 29 : Enable protection for region 125. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION125_Pos (29UL) /*!< Position of REGION125 field. */
+#define BPROT_CONFIG3_REGION125_Msk (0x1UL << BPROT_CONFIG3_REGION125_Pos) /*!< Bit mask of REGION125 field. */
+#define BPROT_CONFIG3_REGION125_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION125_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 28 : Enable protection for region 124. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION124_Pos (28UL) /*!< Position of REGION124 field. */
+#define BPROT_CONFIG3_REGION124_Msk (0x1UL << BPROT_CONFIG3_REGION124_Pos) /*!< Bit mask of REGION124 field. */
+#define BPROT_CONFIG3_REGION124_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION124_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 27 : Enable protection for region 123. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION123_Pos (27UL) /*!< Position of REGION123 field. */
+#define BPROT_CONFIG3_REGION123_Msk (0x1UL << BPROT_CONFIG3_REGION123_Pos) /*!< Bit mask of REGION123 field. */
+#define BPROT_CONFIG3_REGION123_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION123_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 26 : Enable protection for region 122. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION122_Pos (26UL) /*!< Position of REGION122 field. */
+#define BPROT_CONFIG3_REGION122_Msk (0x1UL << BPROT_CONFIG3_REGION122_Pos) /*!< Bit mask of REGION122 field. */
+#define BPROT_CONFIG3_REGION122_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION122_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 25 : Enable protection for region 121. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION121_Pos (25UL) /*!< Position of REGION121 field. */
+#define BPROT_CONFIG3_REGION121_Msk (0x1UL << BPROT_CONFIG3_REGION121_Pos) /*!< Bit mask of REGION121 field. */
+#define BPROT_CONFIG3_REGION121_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION121_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 24 : Enable protection for region 120. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION120_Pos (24UL) /*!< Position of REGION120 field. */
+#define BPROT_CONFIG3_REGION120_Msk (0x1UL << BPROT_CONFIG3_REGION120_Pos) /*!< Bit mask of REGION120 field. */
+#define BPROT_CONFIG3_REGION120_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION120_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 23 : Enable protection for region 119. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION119_Pos (23UL) /*!< Position of REGION119 field. */
+#define BPROT_CONFIG3_REGION119_Msk (0x1UL << BPROT_CONFIG3_REGION119_Pos) /*!< Bit mask of REGION119 field. */
+#define BPROT_CONFIG3_REGION119_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION119_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 22 : Enable protection for region 118. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION118_Pos (22UL) /*!< Position of REGION118 field. */
+#define BPROT_CONFIG3_REGION118_Msk (0x1UL << BPROT_CONFIG3_REGION118_Pos) /*!< Bit mask of REGION118 field. */
+#define BPROT_CONFIG3_REGION118_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION118_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 21 : Enable protection for region 117. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION117_Pos (21UL) /*!< Position of REGION117 field. */
+#define BPROT_CONFIG3_REGION117_Msk (0x1UL << BPROT_CONFIG3_REGION117_Pos) /*!< Bit mask of REGION117 field. */
+#define BPROT_CONFIG3_REGION117_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION117_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 20 : Enable protection for region 116. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION116_Pos (20UL) /*!< Position of REGION116 field. */
+#define BPROT_CONFIG3_REGION116_Msk (0x1UL << BPROT_CONFIG3_REGION116_Pos) /*!< Bit mask of REGION116 field. */
+#define BPROT_CONFIG3_REGION116_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION116_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 19 : Enable protection for region 115. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION115_Pos (19UL) /*!< Position of REGION115 field. */
+#define BPROT_CONFIG3_REGION115_Msk (0x1UL << BPROT_CONFIG3_REGION115_Pos) /*!< Bit mask of REGION115 field. */
+#define BPROT_CONFIG3_REGION115_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION115_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 18 : Enable protection for region 114. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION114_Pos (18UL) /*!< Position of REGION114 field. */
+#define BPROT_CONFIG3_REGION114_Msk (0x1UL << BPROT_CONFIG3_REGION114_Pos) /*!< Bit mask of REGION114 field. */
+#define BPROT_CONFIG3_REGION114_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION114_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 17 : Enable protection for region 113. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION113_Pos (17UL) /*!< Position of REGION113 field. */
+#define BPROT_CONFIG3_REGION113_Msk (0x1UL << BPROT_CONFIG3_REGION113_Pos) /*!< Bit mask of REGION113 field. */
+#define BPROT_CONFIG3_REGION113_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION113_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 16 : Enable protection for region 112. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION112_Pos (16UL) /*!< Position of REGION112 field. */
+#define BPROT_CONFIG3_REGION112_Msk (0x1UL << BPROT_CONFIG3_REGION112_Pos) /*!< Bit mask of REGION112 field. */
+#define BPROT_CONFIG3_REGION112_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION112_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 15 : Enable protection for region 111. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION111_Pos (15UL) /*!< Position of REGION111 field. */
+#define BPROT_CONFIG3_REGION111_Msk (0x1UL << BPROT_CONFIG3_REGION111_Pos) /*!< Bit mask of REGION111 field. */
+#define BPROT_CONFIG3_REGION111_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION111_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 14 : Enable protection for region 110. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION110_Pos (14UL) /*!< Position of REGION110 field. */
+#define BPROT_CONFIG3_REGION110_Msk (0x1UL << BPROT_CONFIG3_REGION110_Pos) /*!< Bit mask of REGION110 field. */
+#define BPROT_CONFIG3_REGION110_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION110_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 13 : Enable protection for region 109. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION109_Pos (13UL) /*!< Position of REGION109 field. */
+#define BPROT_CONFIG3_REGION109_Msk (0x1UL << BPROT_CONFIG3_REGION109_Pos) /*!< Bit mask of REGION109 field. */
+#define BPROT_CONFIG3_REGION109_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION109_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 12 : Enable protection for region 108. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION108_Pos (12UL) /*!< Position of REGION108 field. */
+#define BPROT_CONFIG3_REGION108_Msk (0x1UL << BPROT_CONFIG3_REGION108_Pos) /*!< Bit mask of REGION108 field. */
+#define BPROT_CONFIG3_REGION108_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION108_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 11 : Enable protection for region 107. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION107_Pos (11UL) /*!< Position of REGION107 field. */
+#define BPROT_CONFIG3_REGION107_Msk (0x1UL << BPROT_CONFIG3_REGION107_Pos) /*!< Bit mask of REGION107 field. */
+#define BPROT_CONFIG3_REGION107_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION107_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 10 : Enable protection for region 106. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION106_Pos (10UL) /*!< Position of REGION106 field. */
+#define BPROT_CONFIG3_REGION106_Msk (0x1UL << BPROT_CONFIG3_REGION106_Pos) /*!< Bit mask of REGION106 field. */
+#define BPROT_CONFIG3_REGION106_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION106_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 9 : Enable protection for region 105. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION105_Pos (9UL) /*!< Position of REGION105 field. */
+#define BPROT_CONFIG3_REGION105_Msk (0x1UL << BPROT_CONFIG3_REGION105_Pos) /*!< Bit mask of REGION105 field. */
+#define BPROT_CONFIG3_REGION105_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION105_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 8 : Enable protection for region 104. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION104_Pos (8UL) /*!< Position of REGION104 field. */
+#define BPROT_CONFIG3_REGION104_Msk (0x1UL << BPROT_CONFIG3_REGION104_Pos) /*!< Bit mask of REGION104 field. */
+#define BPROT_CONFIG3_REGION104_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION104_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 7 : Enable protection for region 103. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION103_Pos (7UL) /*!< Position of REGION103 field. */
+#define BPROT_CONFIG3_REGION103_Msk (0x1UL << BPROT_CONFIG3_REGION103_Pos) /*!< Bit mask of REGION103 field. */
+#define BPROT_CONFIG3_REGION103_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION103_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 6 : Enable protection for region 102. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION102_Pos (6UL) /*!< Position of REGION102 field. */
+#define BPROT_CONFIG3_REGION102_Msk (0x1UL << BPROT_CONFIG3_REGION102_Pos) /*!< Bit mask of REGION102 field. */
+#define BPROT_CONFIG3_REGION102_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION102_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 5 : Enable protection for region 101. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION101_Pos (5UL) /*!< Position of REGION101 field. */
+#define BPROT_CONFIG3_REGION101_Msk (0x1UL << BPROT_CONFIG3_REGION101_Pos) /*!< Bit mask of REGION101 field. */
+#define BPROT_CONFIG3_REGION101_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION101_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 4 : Enable protection for region 100. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION100_Pos (4UL) /*!< Position of REGION100 field. */
+#define BPROT_CONFIG3_REGION100_Msk (0x1UL << BPROT_CONFIG3_REGION100_Pos) /*!< Bit mask of REGION100 field. */
+#define BPROT_CONFIG3_REGION100_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION100_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 3 : Enable protection for region 99. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION99_Pos (3UL) /*!< Position of REGION99 field. */
+#define BPROT_CONFIG3_REGION99_Msk (0x1UL << BPROT_CONFIG3_REGION99_Pos) /*!< Bit mask of REGION99 field. */
+#define BPROT_CONFIG3_REGION99_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION99_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 2 : Enable protection for region 98. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION98_Pos (2UL) /*!< Position of REGION98 field. */
+#define BPROT_CONFIG3_REGION98_Msk (0x1UL << BPROT_CONFIG3_REGION98_Pos) /*!< Bit mask of REGION98 field. */
+#define BPROT_CONFIG3_REGION98_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION98_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 1 : Enable protection for region 97. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION97_Pos (1UL) /*!< Position of REGION97 field. */
+#define BPROT_CONFIG3_REGION97_Msk (0x1UL << BPROT_CONFIG3_REGION97_Pos) /*!< Bit mask of REGION97 field. */
+#define BPROT_CONFIG3_REGION97_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION97_Enabled (1UL) /*!< Protection enabled */
+
+/* Bit 0 : Enable protection for region 96. Write '0' has no effect. */
+#define BPROT_CONFIG3_REGION96_Pos (0UL) /*!< Position of REGION96 field. */
+#define BPROT_CONFIG3_REGION96_Msk (0x1UL << BPROT_CONFIG3_REGION96_Pos) /*!< Bit mask of REGION96 field. */
+#define BPROT_CONFIG3_REGION96_Disabled (0UL) /*!< Protection disabled */
+#define BPROT_CONFIG3_REGION96_Enabled (1UL) /*!< Protection enabled */
+
+
+/* Peripheral: CCM */
+/* Description: AES CCM Mode Encryption */
+
+/* Register: CCM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Disable shortcut */
+#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: CCM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for ERROR event */
+#define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ENDCRYPT event */
+#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDKSGEN event */
+#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable */
+
+/* Register: CCM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for ERROR event */
+#define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
+#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ENDCRYPT event */
+#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
+#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDKSGEN event */
+#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
+#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Read: Disabled */
+#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Read: Enabled */
+#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable */
+
+/* Register: CCM_MICSTATUS */
+/* Description: MIC check result */
+
+/* Bit 0 : The result of the MIC check performed during the previous decryption operation */
+#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
+#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed */
+#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed */
+
+/* Register: CCM_ENABLE */
+/* Description: Enable */
+
+/* Bits 1..0 : Enable or disable CCM */
+#define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define CCM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define CCM_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: CCM_MODE */
+/* Description: Operation mode */
+
+/* Bit 24 : Packet length configuration */
+#define CCM_MODE_LENGTH_Pos (24UL) /*!< Position of LENGTH field. */
+#define CCM_MODE_LENGTH_Msk (0x1UL << CCM_MODE_LENGTH_Pos) /*!< Bit mask of LENGTH field. */
+#define CCM_MODE_LENGTH_Default (0UL) /*!< Default length. Effective length of LENGTH field is 5-bit */
+#define CCM_MODE_LENGTH_Extended (1UL) /*!< Extended length. Effective length of LENGTH field is 8-bit */
+
+/* Bit 16 : Data rate that the CCM shall run in synch with */
+#define CCM_MODE_DATARATE_Pos (16UL) /*!< Position of DATARATE field. */
+#define CCM_MODE_DATARATE_Msk (0x1UL << CCM_MODE_DATARATE_Pos) /*!< Bit mask of DATARATE field. */
+#define CCM_MODE_DATARATE_1Mbit (0UL) /*!< In synch with 1 Mbit data rate */
+#define CCM_MODE_DATARATE_2Mbit (1UL) /*!< In synch with 2 Mbit data rate */
+
+/* Bit 0 : The mode of operation to be used */
+#define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define CCM_MODE_MODE_Encryption (0UL) /*!< AES CCM packet encryption mode */
+#define CCM_MODE_MODE_Decryption (1UL) /*!< AES CCM packet decryption mode */
+
+/* Register: CCM_CNFPTR */
+/* Description: Pointer to data structure holding AES key and NONCE vector */
+
+/* Bits 31..0 : Pointer to the data structure holding the AES key and the CCM NONCE vector (see Table 1 CCM data structure overview) */
+#define CCM_CNFPTR_CNFPTR_Pos (0UL) /*!< Position of CNFPTR field. */
+#define CCM_CNFPTR_CNFPTR_Msk (0xFFFFFFFFUL << CCM_CNFPTR_CNFPTR_Pos) /*!< Bit mask of CNFPTR field. */
+
+/* Register: CCM_INPTR */
+/* Description: Input pointer */
+
+/* Bits 31..0 : Input pointer */
+#define CCM_INPTR_INPTR_Pos (0UL) /*!< Position of INPTR field. */
+#define CCM_INPTR_INPTR_Msk (0xFFFFFFFFUL << CCM_INPTR_INPTR_Pos) /*!< Bit mask of INPTR field. */
+
+/* Register: CCM_OUTPTR */
+/* Description: Output pointer */
+
+/* Bits 31..0 : Output pointer */
+#define CCM_OUTPTR_OUTPTR_Pos (0UL) /*!< Position of OUTPTR field. */
+#define CCM_OUTPTR_OUTPTR_Msk (0xFFFFFFFFUL << CCM_OUTPTR_OUTPTR_Pos) /*!< Bit mask of OUTPTR field. */
+
+/* Register: CCM_SCRATCHPTR */
+/* Description: Pointer to data area used for temporary storage */
+
+/* Bits 31..0 : Pointer to a scratch data area used for temporary storage during key-stream generation, MIC generation and encryption/decryption. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Pos (0UL) /*!< Position of SCRATCHPTR field. */
+#define CCM_SCRATCHPTR_SCRATCHPTR_Msk (0xFFFFFFFFUL << CCM_SCRATCHPTR_SCRATCHPTR_Pos) /*!< Bit mask of SCRATCHPTR field. */
+
+
+/* Peripheral: CLOCK */
+/* Description: Clock control */
+
+/* Register: CLOCK_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for CTTO event */
+#define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DONE event */
+#define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable */
+
+/* Register: CLOCK_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for CTTO event */
+#define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
+#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DONE event */
+#define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
+#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for LFCLKSTARTED event */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for HFCLKSTARTED event */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable */
+
+/* Register: CLOCK_HFCLKRUN */
+/* Description: Status indicating that HFCLKSTART task has been triggered */
+
+/* Bit 0 : HFCLKSTART task triggered or not */
+#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_HFCLKSTAT */
+/* Description: HFCLK status */
+
+/* Bit 16 : HFCLK state */
+#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK not running */
+#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK running */
+
+/* Bit 0 : Source of HFCLK */
+#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< 64 MHz internal oscillator (HFINT) */
+#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< 64 MHz crystal oscillator (HFXO) */
+
+/* Register: CLOCK_LFCLKRUN */
+/* Description: Status indicating that LFCLKSTART task has been triggered */
+
+/* Bit 0 : LFCLKSTART task triggered or not */
+#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /*!< Task not triggered */
+#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /*!< Task triggered */
+
+/* Register: CLOCK_LFCLKSTAT */
+/* Description: LFCLK status */
+
+/* Bit 16 : LFCLK state */
+#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
+#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK not running */
+#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK running */
+
+/* Bits 1..0 : Source of LFCLK */
+#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRCCOPY */
+/* Description: Copy of LFCLKSRC register, set when LFCLKSTART task was triggered */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_LFCLKSRC */
+/* Description: Clock source for the LFCLK */
+
+/* Bits 1..0 : Clock source */
+#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
+#define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< 32.768 kHz RC oscillator */
+#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< 32.768 kHz crystal oscillator */
+#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< 32.768 kHz synthesized from HFCLK */
+
+/* Register: CLOCK_CTIV */
+/* Description: Calibration timer interval (retained register, same reset behaviour as RESETREAS) */
+
+/* Bits 6..0 : Calibration timer interval in multiple of 0.25 seconds. Range: 0.25 seconds to 31.75 seconds. */
+#define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
+#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
+
+/* Register: CLOCK_TRACECONFIG */
+/* Description: Clocking options for the Trace Port debug interface */
+
+/* Bits 17..16 : Pin multiplexing of trace signals. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Pos (16UL) /*!< Position of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEMUX_Pos) /*!< Bit mask of TRACEMUX field. */
+#define CLOCK_TRACECONFIG_TRACEMUX_GPIO (0UL) /*!< GPIOs multiplexed onto all trace-pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Serial (1UL) /*!< SWO multiplexed onto P0.18, GPIO multiplexed onto other trace pins */
+#define CLOCK_TRACECONFIG_TRACEMUX_Parallel (2UL) /*!< TRACECLK and TRACEDATA multiplexed onto P0.20, P0.18, P0.16, P0.15 and P0.14. */
+
+/* Bits 1..0 : Speed of Trace Port clock. Note that the TRACECLK pin will output this clock divided by two. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos (0UL) /*!< Position of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_Msk (0x3UL << CLOCK_TRACECONFIG_TRACEPORTSPEED_Pos) /*!< Bit mask of TRACEPORTSPEED field. */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_32MHz (0UL) /*!< 32 MHz Trace Port clock (TRACECLK = 16 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_16MHz (1UL) /*!< 16 MHz Trace Port clock (TRACECLK = 8 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_8MHz (2UL) /*!< 8 MHz Trace Port clock (TRACECLK = 4 MHz) */
+#define CLOCK_TRACECONFIG_TRACEPORTSPEED_4MHz (3UL) /*!< 4 MHz Trace Port clock (TRACECLK = 2 MHz) */
+
+
+/* Peripheral: COMP */
+/* Description: Comparator */
+
+/* Register: COMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: COMP_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 3 : Enable or disable interrupt for CROSS event */
+#define COMP_INTEN_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTEN_CROSS_Msk (0x1UL << COMP_INTEN_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTEN_CROSS_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_CROSS_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for UP event */
+#define COMP_INTEN_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTEN_UP_Msk (0x1UL << COMP_INTEN_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTEN_UP_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_UP_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for DOWN event */
+#define COMP_INTEN_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTEN_DOWN_Msk (0x1UL << COMP_INTEN_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTEN_DOWN_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_DOWN_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define COMP_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTEN_READY_Msk (0x1UL << COMP_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define COMP_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: COMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: COMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define COMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define COMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define COMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: COMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define COMP_RESULT_RESULT_Below (0UL) /*!< Input voltage is below the threshold (VIN+ &lt; VIN-) */
+#define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the threshold (VIN+ &gt; VIN-) */
+
+/* Register: COMP_ENABLE */
+/* Description: COMP enable */
+
+/* Bits 1..0 : Enable or disable COMP */
+#define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define COMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define COMP_ENABLE_ENABLE_Enabled (2UL) /*!< Enable */
+
+/* Register: COMP_PSEL */
+/* Description: Pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: COMP_REFSEL */
+/* Description: Reference source select */
+
+/* Bits 2..0 : Reference select */
+#define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define COMP_REFSEL_REFSEL_Int1V2 (0UL) /*!< VREF = internal 1.2 V reference (VDD &gt;= 1.7 V) */
+#define COMP_REFSEL_REFSEL_Int1V8 (1UL) /*!< VREF = internal 1.8 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_Int2V4 (2UL) /*!< VREF = internal 2.4 V reference (VDD &gt;= VREF + 0.2 V) */
+#define COMP_REFSEL_REFSEL_VDD (4UL) /*!< VREF = VDD */
+#define COMP_REFSEL_REFSEL_ARef (7UL) /*!< VREF = AREF (VDD &gt;= VREF &gt;= AREFMIN) */
+
+/* Register: COMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: COMP_TH */
+/* Description: Threshold configuration for hysteresis unit */
+
+/* Bits 13..8 : VUP = (THUP+1)/64*VREF */
+#define COMP_TH_THUP_Pos (8UL) /*!< Position of THUP field. */
+#define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
+
+/* Bits 5..0 : VDOWN = (THDOWN+1)/64*VREF */
+#define COMP_TH_THDOWN_Pos (0UL) /*!< Position of THDOWN field. */
+#define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
+
+/* Register: COMP_MODE */
+/* Description: Mode configuration */
+
+/* Bit 8 : Main operation mode */
+#define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
+#define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
+#define COMP_MODE_MAIN_SE (0UL) /*!< Single ended mode */
+#define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode */
+
+/* Bits 1..0 : Speed and power mode */
+#define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
+#define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
+#define COMP_MODE_SP_Low (0UL) /*!< Low power mode */
+#define COMP_MODE_SP_Normal (1UL) /*!< Normal mode */
+#define COMP_MODE_SP_High (2UL) /*!< High speed mode */
+
+/* Register: COMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis */
+#define COMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define COMP_HYST_HYST_Msk (0x1UL << COMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define COMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define COMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis enabled */
+
+/* Register: COMP_ISOURCE */
+/* Description: Current source select on analog input */
+
+/* Bits 1..0 : Comparator hysteresis */
+#define COMP_ISOURCE_ISOURCE_Pos (0UL) /*!< Position of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Msk (0x3UL << COMP_ISOURCE_ISOURCE_Pos) /*!< Bit mask of ISOURCE field. */
+#define COMP_ISOURCE_ISOURCE_Off (0UL) /*!< Current source disabled */
+#define COMP_ISOURCE_ISOURCE_Ien2mA5 (1UL) /*!< Current source enabled (+/- 2.5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien5mA (2UL) /*!< Current source enabled (+/- 5 uA) */
+#define COMP_ISOURCE_ISOURCE_Ien10mA (3UL) /*!< Current source enabled (+/- 10 uA) */
+
+
+/* Peripheral: ECB */
+/* Description: AES ECB Mode Encryption */
+
+/* Register: ECB_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 1 : Write '1' to Enable interrupt for ERRORECB event */
+#define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for ENDECB event */
+#define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable */
+
+/* Register: ECB_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 1 : Write '1' to Disable interrupt for ERRORECB event */
+#define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
+#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for ENDECB event */
+#define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
+#define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Read: Disabled */
+#define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Read: Enabled */
+#define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable */
+
+/* Register: ECB_ECBDATAPTR */
+/* Description: ECB block encrypt memory pointers */
+
+/* Bits 31..0 : Pointer to the ECB data structure (see Table 1 ECB data structure overview) */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Pos (0UL) /*!< Position of ECBDATAPTR field. */
+#define ECB_ECBDATAPTR_ECBDATAPTR_Msk (0xFFFFFFFFUL << ECB_ECBDATAPTR_ECBDATAPTR_Pos) /*!< Bit mask of ECBDATAPTR field. */
+
+
+/* Peripheral: EGU */
+/* Description: Event Generator Unit 0 */
+
+/* Register: EGU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 15 : Enable or disable interrupt for TRIGGERED[15] event */
+#define EGU_INTEN_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Msk (0x1UL << EGU_INTEN_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTEN_TRIGGERED15_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED15_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for TRIGGERED[14] event */
+#define EGU_INTEN_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Msk (0x1UL << EGU_INTEN_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTEN_TRIGGERED14_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED14_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for TRIGGERED[13] event */
+#define EGU_INTEN_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Msk (0x1UL << EGU_INTEN_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTEN_TRIGGERED13_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED13_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for TRIGGERED[12] event */
+#define EGU_INTEN_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Msk (0x1UL << EGU_INTEN_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTEN_TRIGGERED12_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED12_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for TRIGGERED[11] event */
+#define EGU_INTEN_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Msk (0x1UL << EGU_INTEN_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTEN_TRIGGERED11_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED11_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for TRIGGERED[10] event */
+#define EGU_INTEN_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Msk (0x1UL << EGU_INTEN_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTEN_TRIGGERED10_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED10_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for TRIGGERED[9] event */
+#define EGU_INTEN_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Msk (0x1UL << EGU_INTEN_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTEN_TRIGGERED9_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED9_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for TRIGGERED[8] event */
+#define EGU_INTEN_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Msk (0x1UL << EGU_INTEN_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTEN_TRIGGERED8_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED8_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for TRIGGERED[7] event */
+#define EGU_INTEN_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Msk (0x1UL << EGU_INTEN_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTEN_TRIGGERED7_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for TRIGGERED[6] event */
+#define EGU_INTEN_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Msk (0x1UL << EGU_INTEN_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTEN_TRIGGERED6_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for TRIGGERED[5] event */
+#define EGU_INTEN_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Msk (0x1UL << EGU_INTEN_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTEN_TRIGGERED5_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TRIGGERED[4] event */
+#define EGU_INTEN_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Msk (0x1UL << EGU_INTEN_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTEN_TRIGGERED4_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TRIGGERED[3] event */
+#define EGU_INTEN_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Msk (0x1UL << EGU_INTEN_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTEN_TRIGGERED3_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for TRIGGERED[2] event */
+#define EGU_INTEN_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Msk (0x1UL << EGU_INTEN_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTEN_TRIGGERED2_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for TRIGGERED[1] event */
+#define EGU_INTEN_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Msk (0x1UL << EGU_INTEN_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTEN_TRIGGERED1_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for TRIGGERED[0] event */
+#define EGU_INTEN_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Msk (0x1UL << EGU_INTEN_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTEN_TRIGGERED0_Disabled (0UL) /*!< Disable */
+#define EGU_INTEN_TRIGGERED0_Enabled (1UL) /*!< Enable */
+
+/* Register: EGU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 15 : Write '1' to Enable interrupt for TRIGGERED[15] event */
+#define EGU_INTENSET_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Msk (0x1UL << EGU_INTENSET_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENSET_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED15_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for TRIGGERED[14] event */
+#define EGU_INTENSET_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Msk (0x1UL << EGU_INTENSET_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENSET_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED14_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for TRIGGERED[13] event */
+#define EGU_INTENSET_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Msk (0x1UL << EGU_INTENSET_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENSET_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED13_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for TRIGGERED[12] event */
+#define EGU_INTENSET_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Msk (0x1UL << EGU_INTENSET_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENSET_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED12_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for TRIGGERED[11] event */
+#define EGU_INTENSET_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Msk (0x1UL << EGU_INTENSET_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENSET_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED11_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for TRIGGERED[10] event */
+#define EGU_INTENSET_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Msk (0x1UL << EGU_INTENSET_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENSET_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED10_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for TRIGGERED[9] event */
+#define EGU_INTENSET_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Msk (0x1UL << EGU_INTENSET_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENSET_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED9_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for TRIGGERED[8] event */
+#define EGU_INTENSET_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Msk (0x1UL << EGU_INTENSET_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENSET_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED8_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TRIGGERED[7] event */
+#define EGU_INTENSET_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Msk (0x1UL << EGU_INTENSET_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENSET_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for TRIGGERED[6] event */
+#define EGU_INTENSET_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Msk (0x1UL << EGU_INTENSET_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENSET_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for TRIGGERED[5] event */
+#define EGU_INTENSET_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Msk (0x1UL << EGU_INTENSET_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENSET_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TRIGGERED[4] event */
+#define EGU_INTENSET_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Msk (0x1UL << EGU_INTENSET_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENSET_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TRIGGERED[3] event */
+#define EGU_INTENSET_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Msk (0x1UL << EGU_INTENSET_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENSET_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for TRIGGERED[2] event */
+#define EGU_INTENSET_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Msk (0x1UL << EGU_INTENSET_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENSET_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for TRIGGERED[1] event */
+#define EGU_INTENSET_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Msk (0x1UL << EGU_INTENSET_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENSET_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TRIGGERED[0] event */
+#define EGU_INTENSET_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Msk (0x1UL << EGU_INTENSET_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENSET_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENSET_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENSET_TRIGGERED0_Set (1UL) /*!< Enable */
+
+/* Register: EGU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 15 : Write '1' to Disable interrupt for TRIGGERED[15] event */
+#define EGU_INTENCLR_TRIGGERED15_Pos (15UL) /*!< Position of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Msk (0x1UL << EGU_INTENCLR_TRIGGERED15_Pos) /*!< Bit mask of TRIGGERED15 field. */
+#define EGU_INTENCLR_TRIGGERED15_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED15_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED15_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for TRIGGERED[14] event */
+#define EGU_INTENCLR_TRIGGERED14_Pos (14UL) /*!< Position of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Msk (0x1UL << EGU_INTENCLR_TRIGGERED14_Pos) /*!< Bit mask of TRIGGERED14 field. */
+#define EGU_INTENCLR_TRIGGERED14_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED14_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED14_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for TRIGGERED[13] event */
+#define EGU_INTENCLR_TRIGGERED13_Pos (13UL) /*!< Position of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Msk (0x1UL << EGU_INTENCLR_TRIGGERED13_Pos) /*!< Bit mask of TRIGGERED13 field. */
+#define EGU_INTENCLR_TRIGGERED13_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED13_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED13_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for TRIGGERED[12] event */
+#define EGU_INTENCLR_TRIGGERED12_Pos (12UL) /*!< Position of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Msk (0x1UL << EGU_INTENCLR_TRIGGERED12_Pos) /*!< Bit mask of TRIGGERED12 field. */
+#define EGU_INTENCLR_TRIGGERED12_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED12_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED12_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for TRIGGERED[11] event */
+#define EGU_INTENCLR_TRIGGERED11_Pos (11UL) /*!< Position of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Msk (0x1UL << EGU_INTENCLR_TRIGGERED11_Pos) /*!< Bit mask of TRIGGERED11 field. */
+#define EGU_INTENCLR_TRIGGERED11_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED11_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED11_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for TRIGGERED[10] event */
+#define EGU_INTENCLR_TRIGGERED10_Pos (10UL) /*!< Position of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Msk (0x1UL << EGU_INTENCLR_TRIGGERED10_Pos) /*!< Bit mask of TRIGGERED10 field. */
+#define EGU_INTENCLR_TRIGGERED10_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED10_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED10_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for TRIGGERED[9] event */
+#define EGU_INTENCLR_TRIGGERED9_Pos (9UL) /*!< Position of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Msk (0x1UL << EGU_INTENCLR_TRIGGERED9_Pos) /*!< Bit mask of TRIGGERED9 field. */
+#define EGU_INTENCLR_TRIGGERED9_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED9_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED9_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for TRIGGERED[8] event */
+#define EGU_INTENCLR_TRIGGERED8_Pos (8UL) /*!< Position of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Msk (0x1UL << EGU_INTENCLR_TRIGGERED8_Pos) /*!< Bit mask of TRIGGERED8 field. */
+#define EGU_INTENCLR_TRIGGERED8_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED8_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED8_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TRIGGERED[7] event */
+#define EGU_INTENCLR_TRIGGERED7_Pos (7UL) /*!< Position of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Msk (0x1UL << EGU_INTENCLR_TRIGGERED7_Pos) /*!< Bit mask of TRIGGERED7 field. */
+#define EGU_INTENCLR_TRIGGERED7_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED7_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for TRIGGERED[6] event */
+#define EGU_INTENCLR_TRIGGERED6_Pos (6UL) /*!< Position of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Msk (0x1UL << EGU_INTENCLR_TRIGGERED6_Pos) /*!< Bit mask of TRIGGERED6 field. */
+#define EGU_INTENCLR_TRIGGERED6_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED6_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for TRIGGERED[5] event */
+#define EGU_INTENCLR_TRIGGERED5_Pos (5UL) /*!< Position of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Msk (0x1UL << EGU_INTENCLR_TRIGGERED5_Pos) /*!< Bit mask of TRIGGERED5 field. */
+#define EGU_INTENCLR_TRIGGERED5_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED5_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TRIGGERED[4] event */
+#define EGU_INTENCLR_TRIGGERED4_Pos (4UL) /*!< Position of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Msk (0x1UL << EGU_INTENCLR_TRIGGERED4_Pos) /*!< Bit mask of TRIGGERED4 field. */
+#define EGU_INTENCLR_TRIGGERED4_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED4_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TRIGGERED[3] event */
+#define EGU_INTENCLR_TRIGGERED3_Pos (3UL) /*!< Position of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Msk (0x1UL << EGU_INTENCLR_TRIGGERED3_Pos) /*!< Bit mask of TRIGGERED3 field. */
+#define EGU_INTENCLR_TRIGGERED3_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED3_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for TRIGGERED[2] event */
+#define EGU_INTENCLR_TRIGGERED2_Pos (2UL) /*!< Position of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Msk (0x1UL << EGU_INTENCLR_TRIGGERED2_Pos) /*!< Bit mask of TRIGGERED2 field. */
+#define EGU_INTENCLR_TRIGGERED2_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED2_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for TRIGGERED[1] event */
+#define EGU_INTENCLR_TRIGGERED1_Pos (1UL) /*!< Position of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Msk (0x1UL << EGU_INTENCLR_TRIGGERED1_Pos) /*!< Bit mask of TRIGGERED1 field. */
+#define EGU_INTENCLR_TRIGGERED1_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED1_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TRIGGERED[0] event */
+#define EGU_INTENCLR_TRIGGERED0_Pos (0UL) /*!< Position of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Msk (0x1UL << EGU_INTENCLR_TRIGGERED0_Pos) /*!< Bit mask of TRIGGERED0 field. */
+#define EGU_INTENCLR_TRIGGERED0_Disabled (0UL) /*!< Read: Disabled */
+#define EGU_INTENCLR_TRIGGERED0_Enabled (1UL) /*!< Read: Enabled */
+#define EGU_INTENCLR_TRIGGERED0_Clear (1UL) /*!< Disable */
+
+
+/* Peripheral: FICR */
+/* Description: Factory Information Configuration Registers */
+
+/* Register: FICR_CODEPAGESIZE */
+/* Description: Code memory page size */
+
+/* Bits 31..0 : Code memory page size */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Pos (0UL) /*!< Position of CODEPAGESIZE field. */
+#define FICR_CODEPAGESIZE_CODEPAGESIZE_Msk (0xFFFFFFFFUL << FICR_CODEPAGESIZE_CODEPAGESIZE_Pos) /*!< Bit mask of CODEPAGESIZE field. */
+
+/* Register: FICR_CODESIZE */
+/* Description: Code memory size */
+
+/* Bits 31..0 : Code memory size in number of pages */
+#define FICR_CODESIZE_CODESIZE_Pos (0UL) /*!< Position of CODESIZE field. */
+#define FICR_CODESIZE_CODESIZE_Msk (0xFFFFFFFFUL << FICR_CODESIZE_CODESIZE_Pos) /*!< Bit mask of CODESIZE field. */
+
+/* Register: FICR_DEVICEID */
+/* Description: Description collection[0]:  Device identifier */
+
+/* Bits 31..0 : 64 bit unique device identifier */
+#define FICR_DEVICEID_DEVICEID_Pos (0UL) /*!< Position of DEVICEID field. */
+#define FICR_DEVICEID_DEVICEID_Msk (0xFFFFFFFFUL << FICR_DEVICEID_DEVICEID_Pos) /*!< Bit mask of DEVICEID field. */
+
+/* Register: FICR_ER */
+/* Description: Description collection[0]:  Encryption Root, word 0 */
+
+/* Bits 31..0 : Encryption Root, word n */
+#define FICR_ER_ER_Pos (0UL) /*!< Position of ER field. */
+#define FICR_ER_ER_Msk (0xFFFFFFFFUL << FICR_ER_ER_Pos) /*!< Bit mask of ER field. */
+
+/* Register: FICR_IR */
+/* Description: Description collection[0]:  Identity Root, word 0 */
+
+/* Bits 31..0 : Identity Root, word n */
+#define FICR_IR_IR_Pos (0UL) /*!< Position of IR field. */
+#define FICR_IR_IR_Msk (0xFFFFFFFFUL << FICR_IR_IR_Pos) /*!< Bit mask of IR field. */
+
+/* Register: FICR_DEVICEADDRTYPE */
+/* Description: Device address type */
+
+/* Bit 0 : Device address type */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address */
+#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address */
+
+/* Register: FICR_DEVICEADDR */
+/* Description: Description collection[0]:  Device address 0 */
+
+/* Bits 31..0 : 48 bit device address */
+#define FICR_DEVICEADDR_DEVICEADDR_Pos (0UL) /*!< Position of DEVICEADDR field. */
+#define FICR_DEVICEADDR_DEVICEADDR_Msk (0xFFFFFFFFUL << FICR_DEVICEADDR_DEVICEADDR_Pos) /*!< Bit mask of DEVICEADDR field. */
+
+/* Register: FICR_INFO_PART */
+/* Description: Part code */
+
+/* Bits 31..0 : Part code */
+#define FICR_INFO_PART_PART_Pos (0UL) /*!< Position of PART field. */
+#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /*!< Bit mask of PART field. */
+#define FICR_INFO_PART_PART_N52832 (0x52832UL) /*!< nRF52832 */
+#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_VARIANT */
+/* Description: Part Variant, Hardware version and Production configuration */
+
+/* Bits 31..0 : Part Variant, Hardware version and Production configuration, encoded as ASCII */
+#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /*!< Position of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /*!< Bit mask of VARIANT field. */
+#define FICR_INFO_VARIANT_VARIANT_AAAA (0x41414141UL) /*!< AAAA */
+#define FICR_INFO_VARIANT_VARIANT_AAAB (0x41414142UL) /*!< AAAB */
+#define FICR_INFO_VARIANT_VARIANT_AABA (0x41414241UL) /*!< AABA */
+#define FICR_INFO_VARIANT_VARIANT_AABB (0x41414242UL) /*!< AABB */
+#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_PACKAGE */
+/* Description: Package option */
+
+/* Bits 31..0 : Package option */
+#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /*!< Position of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /*!< Bit mask of PACKAGE field. */
+#define FICR_INFO_PACKAGE_PACKAGE_QF (0x2000UL) /*!< QFxx - 48-pin QFN */
+#define FICR_INFO_PACKAGE_PACKAGE_CH (0x2001UL) /*!< CHxx - 7x8 WLCSP 56 balls */
+#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_RAM */
+/* Description: RAM variant */
+
+/* Bits 31..0 : RAM variant */
+#define FICR_INFO_RAM_RAM_Pos (0UL) /*!< Position of RAM field. */
+#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /*!< Bit mask of RAM field. */
+#define FICR_INFO_RAM_RAM_K16 (0x10UL) /*!< 16 kByte RAM */
+#define FICR_INFO_RAM_RAM_K32 (0x20UL) /*!< 32 kByte RAM */
+#define FICR_INFO_RAM_RAM_K64 (0x40UL) /*!< 64 kByte RAM */
+#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_INFO_FLASH */
+/* Description: Flash variant */
+
+/* Bits 31..0 : Flash variant */
+#define FICR_INFO_FLASH_FLASH_Pos (0UL) /*!< Position of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /*!< Bit mask of FLASH field. */
+#define FICR_INFO_FLASH_FLASH_K128 (0x80UL) /*!< 128 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K256 (0x100UL) /*!< 256 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_K512 (0x200UL) /*!< 512 kByte FLASH */
+#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /*!< Unspecified */
+
+/* Register: FICR_TEMP_A0 */
+/* Description: Slope definition A0. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A0_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A0_A_Msk (0xFFFUL << FICR_TEMP_A0_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A1 */
+/* Description: Slope definition A1. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A1_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A1_A_Msk (0xFFFUL << FICR_TEMP_A1_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A2 */
+/* Description: Slope definition A2. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A2_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A2_A_Msk (0xFFFUL << FICR_TEMP_A2_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A3 */
+/* Description: Slope definition A3. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A3_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A3_A_Msk (0xFFFUL << FICR_TEMP_A3_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A4 */
+/* Description: Slope definition A4. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A4_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A4_A_Msk (0xFFFUL << FICR_TEMP_A4_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_A5 */
+/* Description: Slope definition A5. */
+
+/* Bits 11..0 : A (slope definition) register. */
+#define FICR_TEMP_A5_A_Pos (0UL) /*!< Position of A field. */
+#define FICR_TEMP_A5_A_Msk (0xFFFUL << FICR_TEMP_A5_A_Pos) /*!< Bit mask of A field. */
+
+/* Register: FICR_TEMP_B0 */
+/* Description: y-intercept B0. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B0_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B0_B_Msk (0x3FFFUL << FICR_TEMP_B0_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B1 */
+/* Description: y-intercept B1. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B1_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B1_B_Msk (0x3FFFUL << FICR_TEMP_B1_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B2 */
+/* Description: y-intercept B2. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B2_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B2_B_Msk (0x3FFFUL << FICR_TEMP_B2_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B3 */
+/* Description: y-intercept B3. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B3_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B3_B_Msk (0x3FFFUL << FICR_TEMP_B3_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B4 */
+/* Description: y-intercept B4. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B4_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B4_B_Msk (0x3FFFUL << FICR_TEMP_B4_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_B5 */
+/* Description: y-intercept B5. */
+
+/* Bits 13..0 : B (y-intercept) */
+#define FICR_TEMP_B5_B_Pos (0UL) /*!< Position of B field. */
+#define FICR_TEMP_B5_B_Msk (0x3FFFUL << FICR_TEMP_B5_B_Pos) /*!< Bit mask of B field. */
+
+/* Register: FICR_TEMP_T0 */
+/* Description: Segment end T0. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T0_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T0_T_Msk (0xFFUL << FICR_TEMP_T0_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T1 */
+/* Description: Segment end T1. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T1_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T1_T_Msk (0xFFUL << FICR_TEMP_T1_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T2 */
+/* Description: Segment end T2. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T2_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T2_T_Msk (0xFFUL << FICR_TEMP_T2_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T3 */
+/* Description: Segment end T3. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T3_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T3_T_Msk (0xFFUL << FICR_TEMP_T3_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_TEMP_T4 */
+/* Description: Segment end T4. */
+
+/* Bits 7..0 : T (segment end)register. */
+#define FICR_TEMP_T4_T_Pos (0UL) /*!< Position of T field. */
+#define FICR_TEMP_T4_T_Msk (0xFFUL << FICR_TEMP_T4_T_Pos) /*!< Bit mask of T field. */
+
+/* Register: FICR_NFC_TAGHEADER0 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 3 */
+#define FICR_NFC_TAGHEADER0_UD3_Pos (24UL) /*!< Position of UD3 field. */
+#define FICR_NFC_TAGHEADER0_UD3_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD3_Pos) /*!< Bit mask of UD3 field. */
+
+/* Bits 23..16 : Unique identifier byte 2 */
+#define FICR_NFC_TAGHEADER0_UD2_Pos (16UL) /*!< Position of UD2 field. */
+#define FICR_NFC_TAGHEADER0_UD2_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD2_Pos) /*!< Bit mask of UD2 field. */
+
+/* Bits 15..8 : Unique identifier byte 1 */
+#define FICR_NFC_TAGHEADER0_UD1_Pos (8UL) /*!< Position of UD1 field. */
+#define FICR_NFC_TAGHEADER0_UD1_Msk (0xFFUL << FICR_NFC_TAGHEADER0_UD1_Pos) /*!< Bit mask of UD1 field. */
+
+/* Bits 7..0 : Default Manufacturer ID: Nordic Semiconductor ASA has ICM 0x5F */
+#define FICR_NFC_TAGHEADER0_MFGID_Pos (0UL) /*!< Position of MFGID field. */
+#define FICR_NFC_TAGHEADER0_MFGID_Msk (0xFFUL << FICR_NFC_TAGHEADER0_MFGID_Pos) /*!< Bit mask of MFGID field. */
+
+/* Register: FICR_NFC_TAGHEADER1 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 7 */
+#define FICR_NFC_TAGHEADER1_UD7_Pos (24UL) /*!< Position of UD7 field. */
+#define FICR_NFC_TAGHEADER1_UD7_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD7_Pos) /*!< Bit mask of UD7 field. */
+
+/* Bits 23..16 : Unique identifier byte 6 */
+#define FICR_NFC_TAGHEADER1_UD6_Pos (16UL) /*!< Position of UD6 field. */
+#define FICR_NFC_TAGHEADER1_UD6_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD6_Pos) /*!< Bit mask of UD6 field. */
+
+/* Bits 15..8 : Unique identifier byte 5 */
+#define FICR_NFC_TAGHEADER1_UD5_Pos (8UL) /*!< Position of UD5 field. */
+#define FICR_NFC_TAGHEADER1_UD5_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD5_Pos) /*!< Bit mask of UD5 field. */
+
+/* Bits 7..0 : Unique identifier byte 4 */
+#define FICR_NFC_TAGHEADER1_UD4_Pos (0UL) /*!< Position of UD4 field. */
+#define FICR_NFC_TAGHEADER1_UD4_Msk (0xFFUL << FICR_NFC_TAGHEADER1_UD4_Pos) /*!< Bit mask of UD4 field. */
+
+/* Register: FICR_NFC_TAGHEADER2 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 11 */
+#define FICR_NFC_TAGHEADER2_UD11_Pos (24UL) /*!< Position of UD11 field. */
+#define FICR_NFC_TAGHEADER2_UD11_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD11_Pos) /*!< Bit mask of UD11 field. */
+
+/* Bits 23..16 : Unique identifier byte 10 */
+#define FICR_NFC_TAGHEADER2_UD10_Pos (16UL) /*!< Position of UD10 field. */
+#define FICR_NFC_TAGHEADER2_UD10_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD10_Pos) /*!< Bit mask of UD10 field. */
+
+/* Bits 15..8 : Unique identifier byte 9 */
+#define FICR_NFC_TAGHEADER2_UD9_Pos (8UL) /*!< Position of UD9 field. */
+#define FICR_NFC_TAGHEADER2_UD9_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD9_Pos) /*!< Bit mask of UD9 field. */
+
+/* Bits 7..0 : Unique identifier byte 8 */
+#define FICR_NFC_TAGHEADER2_UD8_Pos (0UL) /*!< Position of UD8 field. */
+#define FICR_NFC_TAGHEADER2_UD8_Msk (0xFFUL << FICR_NFC_TAGHEADER2_UD8_Pos) /*!< Bit mask of UD8 field. */
+
+/* Register: FICR_NFC_TAGHEADER3 */
+/* Description: Default header for NFC Tag. Software can read these values to populate NFCID1_3RD_LAST, NFCID1_2ND_LAST and NFCID1_LAST. */
+
+/* Bits 31..24 : Unique identifier byte 15 */
+#define FICR_NFC_TAGHEADER3_UD15_Pos (24UL) /*!< Position of UD15 field. */
+#define FICR_NFC_TAGHEADER3_UD15_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD15_Pos) /*!< Bit mask of UD15 field. */
+
+/* Bits 23..16 : Unique identifier byte 14 */
+#define FICR_NFC_TAGHEADER3_UD14_Pos (16UL) /*!< Position of UD14 field. */
+#define FICR_NFC_TAGHEADER3_UD14_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD14_Pos) /*!< Bit mask of UD14 field. */
+
+/* Bits 15..8 : Unique identifier byte 13 */
+#define FICR_NFC_TAGHEADER3_UD13_Pos (8UL) /*!< Position of UD13 field. */
+#define FICR_NFC_TAGHEADER3_UD13_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD13_Pos) /*!< Bit mask of UD13 field. */
+
+/* Bits 7..0 : Unique identifier byte 12 */
+#define FICR_NFC_TAGHEADER3_UD12_Pos (0UL) /*!< Position of UD12 field. */
+#define FICR_NFC_TAGHEADER3_UD12_Msk (0xFFUL << FICR_NFC_TAGHEADER3_UD12_Pos) /*!< Bit mask of UD12 field. */
+
+
+/* Peripheral: GPIOTE */
+/* Description: GPIO Tasks and Events */
+
+/* Register: GPIOTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 31 : Write '1' to Enable interrupt for PORT event */
+#define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for IN[7] event */
+#define GPIOTE_INTENSET_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Msk (0x1UL << GPIOTE_INTENSET_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENSET_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN7_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for IN[6] event */
+#define GPIOTE_INTENSET_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Msk (0x1UL << GPIOTE_INTENSET_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENSET_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN6_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for IN[5] event */
+#define GPIOTE_INTENSET_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Msk (0x1UL << GPIOTE_INTENSET_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENSET_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN5_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for IN[4] event */
+#define GPIOTE_INTENSET_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Msk (0x1UL << GPIOTE_INTENSET_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENSET_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN4_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for IN[3] event */
+#define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for IN[2] event */
+#define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for IN[1] event */
+#define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for IN[0] event */
+#define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable */
+
+/* Register: GPIOTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 31 : Write '1' to Disable interrupt for PORT event */
+#define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
+#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for IN[7] event */
+#define GPIOTE_INTENCLR_IN7_Pos (7UL) /*!< Position of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Msk (0x1UL << GPIOTE_INTENCLR_IN7_Pos) /*!< Bit mask of IN7 field. */
+#define GPIOTE_INTENCLR_IN7_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN7_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN7_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for IN[6] event */
+#define GPIOTE_INTENCLR_IN6_Pos (6UL) /*!< Position of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Msk (0x1UL << GPIOTE_INTENCLR_IN6_Pos) /*!< Bit mask of IN6 field. */
+#define GPIOTE_INTENCLR_IN6_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN6_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN6_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for IN[5] event */
+#define GPIOTE_INTENCLR_IN5_Pos (5UL) /*!< Position of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Msk (0x1UL << GPIOTE_INTENCLR_IN5_Pos) /*!< Bit mask of IN5 field. */
+#define GPIOTE_INTENCLR_IN5_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN5_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN5_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for IN[4] event */
+#define GPIOTE_INTENCLR_IN4_Pos (4UL) /*!< Position of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Msk (0x1UL << GPIOTE_INTENCLR_IN4_Pos) /*!< Bit mask of IN4 field. */
+#define GPIOTE_INTENCLR_IN4_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN4_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN4_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for IN[3] event */
+#define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
+#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for IN[2] event */
+#define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
+#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for IN[1] event */
+#define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
+#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for IN[0] event */
+#define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
+#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Read: Disabled */
+#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Read: Enabled */
+#define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable */
+
+/* Register: GPIOTE_CONFIG */
+/* Description: Description collection[0]:  Configuration for OUT[n], SET[n] and CLR[n] tasks and IN[n] event */
+
+/* Bit 20 : When in task mode: Initial value of the output when the GPIOTE channel is configured. When in event mode: No effect. */
+#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
+#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Task mode: Initial value of pin before task triggering is low */
+#define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Task mode: Initial value of pin before task triggering is high */
+
+/* Bits 17..16 : When In task mode: Operation to be performed on output when OUT[n] task is triggered. When In event mode: Operation on input that shall trigger IN[n] event. */
+#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
+#define GPIOTE_CONFIG_POLARITY_None (0UL) /*!< Task mode: No effect on pin from OUT[n] task. Event mode: no IN[n] event generated on pin activity. */
+#define GPIOTE_CONFIG_POLARITY_LoToHi (1UL) /*!< Task mode: Set pin from OUT[n] task. Event mode: Generate IN[n] event when rising edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_HiToLo (2UL) /*!< Task mode: Clear pin from OUT[n] task. Event mode: Generate IN[n] event when falling edge on pin. */
+#define GPIOTE_CONFIG_POLARITY_Toggle (3UL) /*!< Task mode: Toggle pin from OUT[n]. Event mode: Generate IN[n] when any change on pin. */
+
+/* Bits 12..8 : GPIO number associated with SET[n], CLR[n] and OUT[n] tasks and IN[n] event */
+#define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
+#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
+
+/* Bits 1..0 : Mode */
+#define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define GPIOTE_CONFIG_MODE_Disabled (0UL) /*!< Disabled. Pin specified by PSEL will not be acquired by the GPIOTE module. */
+#define GPIOTE_CONFIG_MODE_Event (1UL) /*!< Event mode */
+#define GPIOTE_CONFIG_MODE_Task (3UL) /*!< Task mode */
+
+
+/* Peripheral: I2S */
+/* Description: Inter-IC Sound */
+
+/* Register: I2S_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 5 : Enable or disable interrupt for TXPTRUPD event */
+#define I2S_INTEN_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Msk (0x1UL << I2S_INTEN_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTEN_TXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_TXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for STOPPED event */
+#define I2S_INTEN_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTEN_STOPPED_Msk (0x1UL << I2S_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for RXPTRUPD event */
+#define I2S_INTEN_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Msk (0x1UL << I2S_INTEN_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTEN_RXPTRUPD_Disabled (0UL) /*!< Disable */
+#define I2S_INTEN_RXPTRUPD_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 5 : Write '1' to Enable interrupt for TXPTRUPD event */
+#define I2S_INTENSET_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Msk (0x1UL << I2S_INTENSET_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENSET_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_TXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for STOPPED event */
+#define I2S_INTENSET_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Msk (0x1UL << I2S_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for RXPTRUPD event */
+#define I2S_INTENSET_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Msk (0x1UL << I2S_INTENSET_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENSET_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENSET_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENSET_RXPTRUPD_Set (1UL) /*!< Enable */
+
+/* Register: I2S_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 5 : Write '1' to Disable interrupt for TXPTRUPD event */
+#define I2S_INTENCLR_TXPTRUPD_Pos (5UL) /*!< Position of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Msk (0x1UL << I2S_INTENCLR_TXPTRUPD_Pos) /*!< Bit mask of TXPTRUPD field. */
+#define I2S_INTENCLR_TXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_TXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_TXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for STOPPED event */
+#define I2S_INTENCLR_STOPPED_Pos (2UL) /*!< Position of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Msk (0x1UL << I2S_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define I2S_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for RXPTRUPD event */
+#define I2S_INTENCLR_RXPTRUPD_Pos (1UL) /*!< Position of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Msk (0x1UL << I2S_INTENCLR_RXPTRUPD_Pos) /*!< Bit mask of RXPTRUPD field. */
+#define I2S_INTENCLR_RXPTRUPD_Disabled (0UL) /*!< Read: Disabled */
+#define I2S_INTENCLR_RXPTRUPD_Enabled (1UL) /*!< Read: Enabled */
+#define I2S_INTENCLR_RXPTRUPD_Clear (1UL) /*!< Disable */
+
+/* Register: I2S_ENABLE */
+/* Description: Enable I2S module. */
+
+/* Bit 0 : Enable I2S module. */
+#define I2S_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Msk (0x1UL << I2S_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define I2S_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define I2S_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: I2S_CONFIG_MODE */
+/* Description: I2S mode. */
+
+/* Bit 0 : I2S mode. */
+#define I2S_CONFIG_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Msk (0x1UL << I2S_CONFIG_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define I2S_CONFIG_MODE_MODE_Master (0UL) /*!< Master mode. SCK and LRCK generated from internal master clcok (MCK) and output on pins defined by PSEL.xxx. */
+#define I2S_CONFIG_MODE_MODE_Slave (1UL) /*!< Slave mode. SCK and LRCK generated by external master and received on pins defined by PSEL.xxx */
+
+/* Register: I2S_CONFIG_RXEN */
+/* Description: Reception (RX) enable. */
+
+/* Bit 0 : Reception (RX) enable. */
+#define I2S_CONFIG_RXEN_RXEN_Pos (0UL) /*!< Position of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Msk (0x1UL << I2S_CONFIG_RXEN_RXEN_Pos) /*!< Bit mask of RXEN field. */
+#define I2S_CONFIG_RXEN_RXEN_Disabled (0UL) /*!< Reception disabled and now data will be written to the RXD.PTR address. */
+#define I2S_CONFIG_RXEN_RXEN_Enabled (1UL) /*!< Reception enabled. */
+
+/* Register: I2S_CONFIG_TXEN */
+/* Description: Transmission (TX) enable. */
+
+/* Bit 0 : Transmission (TX) enable. */
+#define I2S_CONFIG_TXEN_TXEN_Pos (0UL) /*!< Position of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Msk (0x1UL << I2S_CONFIG_TXEN_TXEN_Pos) /*!< Bit mask of TXEN field. */
+#define I2S_CONFIG_TXEN_TXEN_Disabled (0UL) /*!< Transmission disabled and now data will be read from the RXD.TXD address. */
+#define I2S_CONFIG_TXEN_TXEN_Enabled (1UL) /*!< Transmission enabled. */
+
+/* Register: I2S_CONFIG_MCKEN */
+/* Description: Master clock generator enable. */
+
+/* Bit 0 : Master clock generator enable. */
+#define I2S_CONFIG_MCKEN_MCKEN_Pos (0UL) /*!< Position of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Msk (0x1UL << I2S_CONFIG_MCKEN_MCKEN_Pos) /*!< Bit mask of MCKEN field. */
+#define I2S_CONFIG_MCKEN_MCKEN_Disabled (0UL) /*!< Master clock generator disabled and PSEL.MCK not connected(available as GPIO). */
+#define I2S_CONFIG_MCKEN_MCKEN_Enabled (1UL) /*!< Master clock generator running and MCK output on PSEL.MCK. */
+
+/* Register: I2S_CONFIG_MCKFREQ */
+/* Description: Master clock generator frequency. */
+
+/* Bits 31..0 : Master clock generator frequency. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Pos (0UL) /*!< Position of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_Msk (0xFFFFFFFFUL << I2S_CONFIG_MCKFREQ_MCKFREQ_Pos) /*!< Bit mask of MCKFREQ field. */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV125 (0x020C0000UL) /*!< 32 MHz / 125 = 0.256 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV63 (0x04100000UL) /*!< 32 MHz / 63 = 0.5079365 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV42 (0x06000000UL) /*!< 32 MHz / 42 = 0.7619048 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV32 (0x08000000UL) /*!< 32 MHz / 32 = 1.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV31 (0x08400000UL) /*!< 32 MHz / 31 = 1.0322581 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV30 (0x08800000UL) /*!< 32 MHz / 30 = 1.0666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV23 (0x0B000000UL) /*!< 32 MHz / 23 = 1.3913043 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV21 (0x0C000000UL) /*!< 32 MHz / 21 = 1.5238095 */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV16 (0x10000000UL) /*!< 32 MHz / 16 = 2.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV15 (0x11000000UL) /*!< 32 MHz / 15 = 2.1333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV11 (0x16000000UL) /*!< 32 MHz / 11 = 2.9090909 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV10 (0x18000000UL) /*!< 32 MHz / 10 = 3.2 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV8 (0x20000000UL) /*!< 32 MHz / 8 = 4.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV6 (0x28000000UL) /*!< 32 MHz / 6 = 5.3333333 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV5 (0x30000000UL) /*!< 32 MHz / 5 = 6.4 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV4 (0x40000000UL) /*!< 32 MHz / 4 = 8.0 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV3 (0x50000000UL) /*!< 32 MHz / 3 = 10.6666667 MHz */
+#define I2S_CONFIG_MCKFREQ_MCKFREQ_32MDIV2 (0x80000000UL) /*!< 32 MHz / 2 = 16.0 MHz */
+
+/* Register: I2S_CONFIG_RATIO */
+/* Description: MCK / LRCK ratio. */
+
+/* Bits 3..0 : MCK / LRCK ratio. */
+#define I2S_CONFIG_RATIO_RATIO_Pos (0UL) /*!< Position of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_Msk (0xFUL << I2S_CONFIG_RATIO_RATIO_Pos) /*!< Bit mask of RATIO field. */
+#define I2S_CONFIG_RATIO_RATIO_32X (0UL) /*!< LRCK = MCK / 32 */
+#define I2S_CONFIG_RATIO_RATIO_48X (1UL) /*!< LRCK = MCK / 48 */
+#define I2S_CONFIG_RATIO_RATIO_64X (2UL) /*!< LRCK = MCK / 64 */
+#define I2S_CONFIG_RATIO_RATIO_96X (3UL) /*!< LRCK = MCK / 96 */
+#define I2S_CONFIG_RATIO_RATIO_128X (4UL) /*!< LRCK = MCK / 128 */
+#define I2S_CONFIG_RATIO_RATIO_192X (5UL) /*!< LRCK = MCK / 192 */
+#define I2S_CONFIG_RATIO_RATIO_256X (6UL) /*!< LRCK = MCK / 256 */
+#define I2S_CONFIG_RATIO_RATIO_384X (7UL) /*!< LRCK = MCK / 384 */
+#define I2S_CONFIG_RATIO_RATIO_512X (8UL) /*!< LRCK = MCK / 512 */
+
+/* Register: I2S_CONFIG_SWIDTH */
+/* Description: Sample width. */
+
+/* Bits 1..0 : Sample width. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Pos (0UL) /*!< Position of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_Msk (0x3UL << I2S_CONFIG_SWIDTH_SWIDTH_Pos) /*!< Bit mask of SWIDTH field. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_8Bit (0UL) /*!< 8 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_16Bit (1UL) /*!< 16 bit. */
+#define I2S_CONFIG_SWIDTH_SWIDTH_24Bit (2UL) /*!< 24 bit. */
+
+/* Register: I2S_CONFIG_ALIGN */
+/* Description: Alignment of sample within a frame. */
+
+/* Bit 0 : Alignment of sample within a frame. */
+#define I2S_CONFIG_ALIGN_ALIGN_Pos (0UL) /*!< Position of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Msk (0x1UL << I2S_CONFIG_ALIGN_ALIGN_Pos) /*!< Bit mask of ALIGN field. */
+#define I2S_CONFIG_ALIGN_ALIGN_Left (0UL) /*!< Left-aligned. */
+#define I2S_CONFIG_ALIGN_ALIGN_Right (1UL) /*!< Right-aligned. */
+
+/* Register: I2S_CONFIG_FORMAT */
+/* Description: Frame format. */
+
+/* Bit 0 : Frame format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Pos (0UL) /*!< Position of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_Msk (0x1UL << I2S_CONFIG_FORMAT_FORMAT_Pos) /*!< Bit mask of FORMAT field. */
+#define I2S_CONFIG_FORMAT_FORMAT_I2S (0UL) /*!< Original I2S format. */
+#define I2S_CONFIG_FORMAT_FORMAT_Aligned (1UL) /*!< Alternate (left- or right-aligned) format. */
+
+/* Register: I2S_CONFIG_CHANNELS */
+/* Description: Enable channels. */
+
+/* Bits 1..0 : Enable channels. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Pos (0UL) /*!< Position of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Msk (0x3UL << I2S_CONFIG_CHANNELS_CHANNELS_Pos) /*!< Bit mask of CHANNELS field. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Stereo (0UL) /*!< Stereo. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Left (1UL) /*!< Left only. */
+#define I2S_CONFIG_CHANNELS_CHANNELS_Right (2UL) /*!< Right only. */
+
+/* Register: I2S_RXD_PTR */
+/* Description: Receive buffer RAM start address. */
+
+/* Bits 31..0 : Receive buffer Data RAM start address. When receiving, words containing samples will be written to this address. This address is a word aligned Data RAM address. */
+#define I2S_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_TXD_PTR */
+/* Description: Transmit buffer RAM start address. */
+
+/* Bits 31..0 : Transmit buffer Data RAM start address. When transmitting, words containing samples will be fetched from this address. This address is a word aligned Data RAM address. */
+#define I2S_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define I2S_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << I2S_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: I2S_RXTXD_MAXCNT */
+/* Description: Size of RXD and TXD buffers. */
+
+/* Bits 13..0 : Size of RXD and TXD buffers in number of 32 bit words. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define I2S_RXTXD_MAXCNT_MAXCNT_Msk (0x3FFFUL << I2S_RXTXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: I2S_PSEL_MCK */
+/* Description: Pin select for MCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_MCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Msk (0x1UL << I2S_PSEL_MCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_MCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_MCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_MCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_MCK_PIN_Msk (0x1FUL << I2S_PSEL_MCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SCK */
+/* Description: Pin select for SCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Msk (0x1UL << I2S_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SCK_PIN_Msk (0x1FUL << I2S_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_LRCK */
+/* Description: Pin select for LRCK signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_LRCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Msk (0x1UL << I2S_PSEL_LRCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_LRCK_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_LRCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_LRCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_LRCK_PIN_Msk (0x1FUL << I2S_PSEL_LRCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDIN */
+/* Description: Pin select for SDIN signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Msk (0x1UL << I2S_PSEL_SDIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDIN_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDIN_PIN_Msk (0x1FUL << I2S_PSEL_SDIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: I2S_PSEL_SDOUT */
+/* Description: Pin select for SDOUT signal. */
+
+/* Bit 31 : Connection */
+#define I2S_PSEL_SDOUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Msk (0x1UL << I2S_PSEL_SDOUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define I2S_PSEL_SDOUT_CONNECT_Connected (0UL) /*!< Connect */
+#define I2S_PSEL_SDOUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define I2S_PSEL_SDOUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define I2S_PSEL_SDOUT_PIN_Msk (0x1FUL << I2S_PSEL_SDOUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: LPCOMP */
+/* Description: Low Power Comparator */
+
+/* Register: LPCOMP_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between CROSS event and STOP task */
+#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
+#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between UP event and STOP task */
+#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
+#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DOWN event and STOP task */
+#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
+#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between READY event and STOP task */
+#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
+#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and SAMPLE task */
+#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
+#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Disable shortcut */
+#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: LPCOMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 3 : Write '1' to Enable interrupt for CROSS event */
+#define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for UP event */
+#define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for DOWN event */
+#define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: LPCOMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 3 : Write '1' to Disable interrupt for CROSS event */
+#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
+#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for UP event */
+#define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
+#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
+#define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for DOWN event */
+#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
+#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: LPCOMP_RESULT */
+/* Description: Compare result */
+
+/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
+#define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
+#define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is below the reference threshold (VIN+ &lt; VIN-). */
+#define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold (VIN+ &gt; VIN-). */
+
+/* Register: LPCOMP_ENABLE */
+/* Description: Enable LPCOMP */
+
+/* Bits 1..0 : Enable or disable LPCOMP */
+#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define LPCOMP_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define LPCOMP_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: LPCOMP_PSEL */
+/* Description: Input pin select */
+
+/* Bits 2..0 : Analog pin select */
+#define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
+#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
+#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< AIN0 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< AIN1 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< AIN2 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< AIN3 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< AIN4 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< AIN5 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< AIN6 selected as analog input */
+#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< AIN7 selected as analog input */
+
+/* Register: LPCOMP_REFSEL */
+/* Description: Reference select */
+
+/* Bits 3..0 : Reference select */
+#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Msk (0xFUL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define LPCOMP_REFSEL_REFSEL_Ref1_8Vdd (0UL) /*!< VDD * 1/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref2_8Vdd (1UL) /*!< VDD * 2/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_8Vdd (2UL) /*!< VDD * 3/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref4_8Vdd (3UL) /*!< VDD * 4/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_8Vdd (4UL) /*!< VDD * 5/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref6_8Vdd (5UL) /*!< VDD * 6/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_8Vdd (6UL) /*!< VDD * 7/8 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< External analog reference selected */
+#define LPCOMP_REFSEL_REFSEL_Ref1_16Vdd (8UL) /*!< VDD * 1/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref3_16Vdd (9UL) /*!< VDD * 3/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref5_16Vdd (10UL) /*!< VDD * 5/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref7_16Vdd (11UL) /*!< VDD * 7/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref9_16Vdd (12UL) /*!< VDD * 9/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref11_16Vdd (13UL) /*!< VDD * 11/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref13_16Vdd (14UL) /*!< VDD * 13/16 selected as reference */
+#define LPCOMP_REFSEL_REFSEL_Ref15_16Vdd (15UL) /*!< VDD * 15/16 selected as reference */
+
+/* Register: LPCOMP_EXTREFSEL */
+/* Description: External reference select */
+
+/* Bit 0 : External analog reference select */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use AIN0 as external analog reference */
+#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use AIN1 as external analog reference */
+
+/* Register: LPCOMP_ANADETECT */
+/* Description: Analog detect configuration */
+
+/* Bits 1..0 : Analog detect configuration */
+#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
+#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETECT on crossing, both upward crossing and downward crossing */
+#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETECT on upward crossing only */
+#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETECT on downward crossing only */
+
+/* Register: LPCOMP_HYST */
+/* Description: Comparator hysteresis enable */
+
+/* Bit 0 : Comparator hysteresis enable */
+#define LPCOMP_HYST_HYST_Pos (0UL) /*!< Position of HYST field. */
+#define LPCOMP_HYST_HYST_Msk (0x1UL << LPCOMP_HYST_HYST_Pos) /*!< Bit mask of HYST field. */
+#define LPCOMP_HYST_HYST_NoHyst (0UL) /*!< Comparator hysteresis disabled */
+#define LPCOMP_HYST_HYST_Hyst50mV (1UL) /*!< Comparator hysteresis disabled (typ. 50 mV) */
+
+
+/* Peripheral: MWU */
+/* Description: Memory Watch Unit */
+
+/* Register: MWU_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 27 : Enable or disable interrupt for PREGION[1].RA event */
+#define MWU_INTEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Msk (0x1UL << MWU_INTEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable interrupt for PREGION[1].WA event */
+#define MWU_INTEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Msk (0x1UL << MWU_INTEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for PREGION[0].RA event */
+#define MWU_INTEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Msk (0x1UL << MWU_INTEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable interrupt for PREGION[0].WA event */
+#define MWU_INTEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Msk (0x1UL << MWU_INTEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for REGION[3].RA event */
+#define MWU_INTEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Msk (0x1UL << MWU_INTEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for REGION[3].WA event */
+#define MWU_INTEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Msk (0x1UL << MWU_INTEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for REGION[2].RA event */
+#define MWU_INTEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Msk (0x1UL << MWU_INTEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for REGION[2].WA event */
+#define MWU_INTEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Msk (0x1UL << MWU_INTEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for REGION[1].RA event */
+#define MWU_INTEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Msk (0x1UL << MWU_INTEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for REGION[1].WA event */
+#define MWU_INTEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Msk (0x1UL << MWU_INTEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for REGION[0].RA event */
+#define MWU_INTEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Msk (0x1UL << MWU_INTEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for REGION[0].WA event */
+#define MWU_INTEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Msk (0x1UL << MWU_INTEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_INTEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 27 : Write '1' to Enable interrupt for PREGION[1].RA event */
+#define MWU_INTENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Msk (0x1UL << MWU_INTENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable interrupt for PREGION[1].WA event */
+#define MWU_INTENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Msk (0x1UL << MWU_INTENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for PREGION[0].RA event */
+#define MWU_INTENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Msk (0x1UL << MWU_INTENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable interrupt for PREGION[0].WA event */
+#define MWU_INTENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Msk (0x1UL << MWU_INTENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for REGION[3].RA event */
+#define MWU_INTENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Msk (0x1UL << MWU_INTENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for REGION[3].WA event */
+#define MWU_INTENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Msk (0x1UL << MWU_INTENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for REGION[2].RA event */
+#define MWU_INTENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Msk (0x1UL << MWU_INTENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for REGION[2].WA event */
+#define MWU_INTENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Msk (0x1UL << MWU_INTENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for REGION[1].RA event */
+#define MWU_INTENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Msk (0x1UL << MWU_INTENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for REGION[1].WA event */
+#define MWU_INTENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Msk (0x1UL << MWU_INTENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REGION[0].RA event */
+#define MWU_INTENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Msk (0x1UL << MWU_INTENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for REGION[0].WA event */
+#define MWU_INTENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Msk (0x1UL << MWU_INTENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 27 : Write '1' to Disable interrupt for PREGION[1].RA event */
+#define MWU_INTENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Msk (0x1UL << MWU_INTENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_INTENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable interrupt for PREGION[1].WA event */
+#define MWU_INTENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Msk (0x1UL << MWU_INTENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_INTENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for PREGION[0].RA event */
+#define MWU_INTENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Msk (0x1UL << MWU_INTENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_INTENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable interrupt for PREGION[0].WA event */
+#define MWU_INTENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Msk (0x1UL << MWU_INTENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_INTENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for REGION[3].RA event */
+#define MWU_INTENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Msk (0x1UL << MWU_INTENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_INTENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for REGION[3].WA event */
+#define MWU_INTENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Msk (0x1UL << MWU_INTENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_INTENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for REGION[2].RA event */
+#define MWU_INTENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Msk (0x1UL << MWU_INTENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_INTENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for REGION[2].WA event */
+#define MWU_INTENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Msk (0x1UL << MWU_INTENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_INTENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for REGION[1].RA event */
+#define MWU_INTENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Msk (0x1UL << MWU_INTENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_INTENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for REGION[1].WA event */
+#define MWU_INTENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Msk (0x1UL << MWU_INTENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_INTENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REGION[0].RA event */
+#define MWU_INTENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Msk (0x1UL << MWU_INTENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_INTENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for REGION[0].WA event */
+#define MWU_INTENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Msk (0x1UL << MWU_INTENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_INTENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_INTENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_INTENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_NMIEN */
+/* Description: Enable or disable non-maskable interrupt */
+
+/* Bit 27 : Enable or disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIEN_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Msk (0x1UL << MWU_NMIEN_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIEN_PREGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 26 : Enable or disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIEN_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Msk (0x1UL << MWU_NMIEN_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIEN_PREGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIEN_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Msk (0x1UL << MWU_NMIEN_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIEN_PREGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : Enable or disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIEN_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Msk (0x1UL << MWU_NMIEN_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIEN_PREGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_PREGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIEN_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Msk (0x1UL << MWU_NMIEN_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIEN_REGION3RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIEN_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Msk (0x1UL << MWU_NMIEN_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIEN_REGION3WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION3WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIEN_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Msk (0x1UL << MWU_NMIEN_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIEN_REGION2RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIEN_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Msk (0x1UL << MWU_NMIEN_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIEN_REGION2WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION2WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIEN_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Msk (0x1UL << MWU_NMIEN_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIEN_REGION1RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIEN_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Msk (0x1UL << MWU_NMIEN_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIEN_REGION1WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION1WA_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIEN_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Msk (0x1UL << MWU_NMIEN_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIEN_REGION0RA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0RA_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIEN_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Msk (0x1UL << MWU_NMIEN_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIEN_REGION0WA_Disabled (0UL) /*!< Disable */
+#define MWU_NMIEN_REGION0WA_Enabled (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENSET */
+/* Description: Enable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Enable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENSET_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Msk (0x1UL << MWU_NMIENSET_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENSET_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 26 : Write '1' to Enable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENSET_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Msk (0x1UL << MWU_NMIENSET_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENSET_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENSET_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Msk (0x1UL << MWU_NMIENSET_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENSET_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 24 : Write '1' to Enable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENSET_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Msk (0x1UL << MWU_NMIENSET_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENSET_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_PREGION0WA_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENSET_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Msk (0x1UL << MWU_NMIENSET_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENSET_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3RA_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENSET_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Msk (0x1UL << MWU_NMIENSET_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENSET_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION3WA_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENSET_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Msk (0x1UL << MWU_NMIENSET_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENSET_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2RA_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENSET_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Msk (0x1UL << MWU_NMIENSET_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENSET_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION2WA_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENSET_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Msk (0x1UL << MWU_NMIENSET_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENSET_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1RA_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENSET_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Msk (0x1UL << MWU_NMIENSET_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENSET_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION1WA_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENSET_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Msk (0x1UL << MWU_NMIENSET_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENSET_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0RA_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENSET_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Msk (0x1UL << MWU_NMIENSET_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENSET_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENSET_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENSET_REGION0WA_Set (1UL) /*!< Enable */
+
+/* Register: MWU_NMIENCLR */
+/* Description: Disable non-maskable interrupt */
+
+/* Bit 27 : Write '1' to Disable non-maskable interrupt for PREGION[1].RA event */
+#define MWU_NMIENCLR_PREGION1RA_Pos (27UL) /*!< Position of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Msk (0x1UL << MWU_NMIENCLR_PREGION1RA_Pos) /*!< Bit mask of PREGION1RA field. */
+#define MWU_NMIENCLR_PREGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 26 : Write '1' to Disable non-maskable interrupt for PREGION[1].WA event */
+#define MWU_NMIENCLR_PREGION1WA_Pos (26UL) /*!< Position of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Msk (0x1UL << MWU_NMIENCLR_PREGION1WA_Pos) /*!< Bit mask of PREGION1WA field. */
+#define MWU_NMIENCLR_PREGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable non-maskable interrupt for PREGION[0].RA event */
+#define MWU_NMIENCLR_PREGION0RA_Pos (25UL) /*!< Position of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Msk (0x1UL << MWU_NMIENCLR_PREGION0RA_Pos) /*!< Bit mask of PREGION0RA field. */
+#define MWU_NMIENCLR_PREGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 24 : Write '1' to Disable non-maskable interrupt for PREGION[0].WA event */
+#define MWU_NMIENCLR_PREGION0WA_Pos (24UL) /*!< Position of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Msk (0x1UL << MWU_NMIENCLR_PREGION0WA_Pos) /*!< Bit mask of PREGION0WA field. */
+#define MWU_NMIENCLR_PREGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_PREGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_PREGION0WA_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable non-maskable interrupt for REGION[3].RA event */
+#define MWU_NMIENCLR_REGION3RA_Pos (7UL) /*!< Position of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Msk (0x1UL << MWU_NMIENCLR_REGION3RA_Pos) /*!< Bit mask of REGION3RA field. */
+#define MWU_NMIENCLR_REGION3RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3RA_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable non-maskable interrupt for REGION[3].WA event */
+#define MWU_NMIENCLR_REGION3WA_Pos (6UL) /*!< Position of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Msk (0x1UL << MWU_NMIENCLR_REGION3WA_Pos) /*!< Bit mask of REGION3WA field. */
+#define MWU_NMIENCLR_REGION3WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION3WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION3WA_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable non-maskable interrupt for REGION[2].RA event */
+#define MWU_NMIENCLR_REGION2RA_Pos (5UL) /*!< Position of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Msk (0x1UL << MWU_NMIENCLR_REGION2RA_Pos) /*!< Bit mask of REGION2RA field. */
+#define MWU_NMIENCLR_REGION2RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2RA_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable non-maskable interrupt for REGION[2].WA event */
+#define MWU_NMIENCLR_REGION2WA_Pos (4UL) /*!< Position of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Msk (0x1UL << MWU_NMIENCLR_REGION2WA_Pos) /*!< Bit mask of REGION2WA field. */
+#define MWU_NMIENCLR_REGION2WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION2WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION2WA_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable non-maskable interrupt for REGION[1].RA event */
+#define MWU_NMIENCLR_REGION1RA_Pos (3UL) /*!< Position of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Msk (0x1UL << MWU_NMIENCLR_REGION1RA_Pos) /*!< Bit mask of REGION1RA field. */
+#define MWU_NMIENCLR_REGION1RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1RA_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable non-maskable interrupt for REGION[1].WA event */
+#define MWU_NMIENCLR_REGION1WA_Pos (2UL) /*!< Position of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Msk (0x1UL << MWU_NMIENCLR_REGION1WA_Pos) /*!< Bit mask of REGION1WA field. */
+#define MWU_NMIENCLR_REGION1WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION1WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION1WA_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable non-maskable interrupt for REGION[0].RA event */
+#define MWU_NMIENCLR_REGION0RA_Pos (1UL) /*!< Position of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Msk (0x1UL << MWU_NMIENCLR_REGION0RA_Pos) /*!< Bit mask of REGION0RA field. */
+#define MWU_NMIENCLR_REGION0RA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0RA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0RA_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable non-maskable interrupt for REGION[0].WA event */
+#define MWU_NMIENCLR_REGION0WA_Pos (0UL) /*!< Position of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Msk (0x1UL << MWU_NMIENCLR_REGION0WA_Pos) /*!< Bit mask of REGION0WA field. */
+#define MWU_NMIENCLR_REGION0WA_Disabled (0UL) /*!< Read: Disabled */
+#define MWU_NMIENCLR_REGION0WA_Enabled (1UL) /*!< Read: Enabled */
+#define MWU_NMIENCLR_REGION0WA_Clear (1UL) /*!< Disable */
+
+/* Register: MWU_PERREGION_SUBSTATWA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, write access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATWA_SR31_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR31_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATWA_SR30_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR30_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATWA_SR29_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR29_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATWA_SR28_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR28_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATWA_SR27_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR27_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATWA_SR26_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR26_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATWA_SR25_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR25_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATWA_SR24_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR24_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATWA_SR23_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR23_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATWA_SR22_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR22_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATWA_SR21_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR21_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATWA_SR20_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR20_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATWA_SR19_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR19_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATWA_SR18_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR18_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATWA_SR17_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR17_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATWA_SR16_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR16_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATWA_SR15_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR15_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATWA_SR14_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR14_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATWA_SR13_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR13_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATWA_SR12_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR12_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATWA_SR11_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR11_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATWA_SR10_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR10_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATWA_SR9_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR9_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATWA_SR8_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR8_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATWA_SR7_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR7_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATWA_SR6_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR6_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATWA_SR5_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR5_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATWA_SR4_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR4_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATWA_SR3_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR3_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATWA_SR2_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR2_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATWA_SR1_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR1_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATWA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATWA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATWA_SR0_NoAccess (0UL) /*!< No write access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATWA_SR0_Access (1UL) /*!< Write access(es) occurred in this subregion */
+
+/* Register: MWU_PERREGION_SUBSTATRA */
+/* Description: Description cluster[0]:  Source of event/interrupt in region 0, read access detected while corresponding subregion was enabled for watching */
+
+/* Bit 31 : Subregion 31 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PERREGION_SUBSTATRA_SR31_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR31_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 30 : Subregion 30 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PERREGION_SUBSTATRA_SR30_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR30_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 29 : Subregion 29 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PERREGION_SUBSTATRA_SR29_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR29_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 28 : Subregion 28 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PERREGION_SUBSTATRA_SR28_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR28_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 27 : Subregion 27 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PERREGION_SUBSTATRA_SR27_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR27_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 26 : Subregion 26 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PERREGION_SUBSTATRA_SR26_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR26_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 25 : Subregion 25 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PERREGION_SUBSTATRA_SR25_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR25_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 24 : Subregion 24 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PERREGION_SUBSTATRA_SR24_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR24_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 23 : Subregion 23 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PERREGION_SUBSTATRA_SR23_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR23_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 22 : Subregion 22 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PERREGION_SUBSTATRA_SR22_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR22_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 21 : Subregion 21 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PERREGION_SUBSTATRA_SR21_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR21_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 20 : Subregion 20 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PERREGION_SUBSTATRA_SR20_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR20_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 19 : Subregion 19 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PERREGION_SUBSTATRA_SR19_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR19_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 18 : Subregion 18 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PERREGION_SUBSTATRA_SR18_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR18_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 17 : Subregion 17 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PERREGION_SUBSTATRA_SR17_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR17_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 16 : Subregion 16 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PERREGION_SUBSTATRA_SR16_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR16_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 15 : Subregion 15 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PERREGION_SUBSTATRA_SR15_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR15_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 14 : Subregion 14 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PERREGION_SUBSTATRA_SR14_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR14_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 13 : Subregion 13 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PERREGION_SUBSTATRA_SR13_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR13_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 12 : Subregion 12 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PERREGION_SUBSTATRA_SR12_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR12_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 11 : Subregion 11 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PERREGION_SUBSTATRA_SR11_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR11_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 10 : Subregion 10 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PERREGION_SUBSTATRA_SR10_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR10_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 9 : Subregion 9 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PERREGION_SUBSTATRA_SR9_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR9_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 8 : Subregion 8 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PERREGION_SUBSTATRA_SR8_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR8_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 7 : Subregion 7 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PERREGION_SUBSTATRA_SR7_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR7_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 6 : Subregion 6 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PERREGION_SUBSTATRA_SR6_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR6_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 5 : Subregion 5 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PERREGION_SUBSTATRA_SR5_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR5_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 4 : Subregion 4 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PERREGION_SUBSTATRA_SR4_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR4_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 3 : Subregion 3 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PERREGION_SUBSTATRA_SR3_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR3_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 2 : Subregion 2 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PERREGION_SUBSTATRA_SR2_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR2_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 1 : Subregion 1 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PERREGION_SUBSTATRA_SR1_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR1_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Bit 0 : Subregion 0 in region 0 (write '1' to clear) */
+#define MWU_PERREGION_SUBSTATRA_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_Msk (0x1UL << MWU_PERREGION_SUBSTATRA_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PERREGION_SUBSTATRA_SR0_NoAccess (0UL) /*!< No read access occurred in this subregion */
+#define MWU_PERREGION_SUBSTATRA_SR0_Access (1UL) /*!< Read access(es) occurred in this subregion */
+
+/* Register: MWU_REGIONEN */
+/* Description: Enable/disable regions watch */
+
+/* Bit 27 : Enable/disable read access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Msk (0x1UL << MWU_REGIONEN_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONEN_PRGN1RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable/disable write access watch in PREGION[1] */
+#define MWU_REGIONEN_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Msk (0x1UL << MWU_REGIONEN_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONEN_PRGN1WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN1WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable/disable read access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Msk (0x1UL << MWU_REGIONEN_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONEN_PRGN0RA_Disable (0UL) /*!< Disable read access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0RA_Enable (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable/disable write access watch in PREGION[0] */
+#define MWU_REGIONEN_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Msk (0x1UL << MWU_REGIONEN_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONEN_PRGN0WA_Disable (0UL) /*!< Disable write access watch in this PREGION */
+#define MWU_REGIONEN_PRGN0WA_Enable (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable/disable read access watch in region[3] */
+#define MWU_REGIONEN_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Msk (0x1UL << MWU_REGIONEN_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONEN_RGN3RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN3RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable/disable write access watch in region[3] */
+#define MWU_REGIONEN_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Msk (0x1UL << MWU_REGIONEN_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONEN_RGN3WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN3WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable/disable read access watch in region[2] */
+#define MWU_REGIONEN_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Msk (0x1UL << MWU_REGIONEN_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONEN_RGN2RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN2RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable/disable write access watch in region[2] */
+#define MWU_REGIONEN_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Msk (0x1UL << MWU_REGIONEN_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONEN_RGN2WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN2WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable/disable read access watch in region[1] */
+#define MWU_REGIONEN_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Msk (0x1UL << MWU_REGIONEN_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONEN_RGN1RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN1RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable/disable write access watch in region[1] */
+#define MWU_REGIONEN_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Msk (0x1UL << MWU_REGIONEN_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONEN_RGN1WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN1WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable/disable read access watch in region[0] */
+#define MWU_REGIONEN_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Msk (0x1UL << MWU_REGIONEN_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONEN_RGN0RA_Disable (0UL) /*!< Disable read access watch in this region */
+#define MWU_REGIONEN_RGN0RA_Enable (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable/disable write access watch in region[0] */
+#define MWU_REGIONEN_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Msk (0x1UL << MWU_REGIONEN_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONEN_RGN0WA_Disable (0UL) /*!< Disable write access watch in this region */
+#define MWU_REGIONEN_RGN0WA_Enable (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENSET */
+/* Description: Enable regions watch */
+
+/* Bit 27 : Enable read access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Msk (0x1UL << MWU_REGIONENSET_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENSET_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 26 : Enable write access watch in PREGION[1] */
+#define MWU_REGIONENSET_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Msk (0x1UL << MWU_REGIONENSET_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENSET_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN1WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 25 : Enable read access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Msk (0x1UL << MWU_REGIONENSET_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENSET_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0RA_Set (1UL) /*!< Enable read access watch in this PREGION */
+
+/* Bit 24 : Enable write access watch in PREGION[0] */
+#define MWU_REGIONENSET_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Msk (0x1UL << MWU_REGIONENSET_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENSET_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENSET_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENSET_PRGN0WA_Set (1UL) /*!< Enable write access watch in this PREGION */
+
+/* Bit 7 : Enable read access watch in region[3] */
+#define MWU_REGIONENSET_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Msk (0x1UL << MWU_REGIONENSET_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENSET_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 6 : Enable write access watch in region[3] */
+#define MWU_REGIONENSET_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Msk (0x1UL << MWU_REGIONENSET_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENSET_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN3WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 5 : Enable read access watch in region[2] */
+#define MWU_REGIONENSET_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Msk (0x1UL << MWU_REGIONENSET_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENSET_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 4 : Enable write access watch in region[2] */
+#define MWU_REGIONENSET_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Msk (0x1UL << MWU_REGIONENSET_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENSET_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN2WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 3 : Enable read access watch in region[1] */
+#define MWU_REGIONENSET_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Msk (0x1UL << MWU_REGIONENSET_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENSET_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 2 : Enable write access watch in region[1] */
+#define MWU_REGIONENSET_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Msk (0x1UL << MWU_REGIONENSET_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENSET_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN1WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Bit 1 : Enable read access watch in region[0] */
+#define MWU_REGIONENSET_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Msk (0x1UL << MWU_REGIONENSET_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENSET_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0RA_Set (1UL) /*!< Enable read access watch in this region */
+
+/* Bit 0 : Enable write access watch in region[0] */
+#define MWU_REGIONENSET_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Msk (0x1UL << MWU_REGIONENSET_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENSET_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENSET_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENSET_RGN0WA_Set (1UL) /*!< Enable write access watch in this region */
+
+/* Register: MWU_REGIONENCLR */
+/* Description: Disable regions watch */
+
+/* Bit 27 : Disable read access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1RA_Pos (27UL) /*!< Position of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1RA_Pos) /*!< Bit mask of PRGN1RA field. */
+#define MWU_REGIONENCLR_PRGN1RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 26 : Disable write access watch in PREGION[1] */
+#define MWU_REGIONENCLR_PRGN1WA_Pos (26UL) /*!< Position of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN1WA_Pos) /*!< Bit mask of PRGN1WA field. */
+#define MWU_REGIONENCLR_PRGN1WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN1WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN1WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 25 : Disable read access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0RA_Pos (25UL) /*!< Position of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0RA_Pos) /*!< Bit mask of PRGN0RA field. */
+#define MWU_REGIONENCLR_PRGN0RA_Disabled (0UL) /*!< Read access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0RA_Enabled (1UL) /*!< Read access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0RA_Clear (1UL) /*!< Disable read access watch in this PREGION */
+
+/* Bit 24 : Disable write access watch in PREGION[0] */
+#define MWU_REGIONENCLR_PRGN0WA_Pos (24UL) /*!< Position of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Msk (0x1UL << MWU_REGIONENCLR_PRGN0WA_Pos) /*!< Bit mask of PRGN0WA field. */
+#define MWU_REGIONENCLR_PRGN0WA_Disabled (0UL) /*!< Write access watch in this PREGION is disabled */
+#define MWU_REGIONENCLR_PRGN0WA_Enabled (1UL) /*!< Write access watch in this PREGION is enabled */
+#define MWU_REGIONENCLR_PRGN0WA_Clear (1UL) /*!< Disable write access watch in this PREGION */
+
+/* Bit 7 : Disable read access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3RA_Pos (7UL) /*!< Position of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Msk (0x1UL << MWU_REGIONENCLR_RGN3RA_Pos) /*!< Bit mask of RGN3RA field. */
+#define MWU_REGIONENCLR_RGN3RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 6 : Disable write access watch in region[3] */
+#define MWU_REGIONENCLR_RGN3WA_Pos (6UL) /*!< Position of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Msk (0x1UL << MWU_REGIONENCLR_RGN3WA_Pos) /*!< Bit mask of RGN3WA field. */
+#define MWU_REGIONENCLR_RGN3WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN3WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN3WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 5 : Disable read access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2RA_Pos (5UL) /*!< Position of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Msk (0x1UL << MWU_REGIONENCLR_RGN2RA_Pos) /*!< Bit mask of RGN2RA field. */
+#define MWU_REGIONENCLR_RGN2RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 4 : Disable write access watch in region[2] */
+#define MWU_REGIONENCLR_RGN2WA_Pos (4UL) /*!< Position of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Msk (0x1UL << MWU_REGIONENCLR_RGN2WA_Pos) /*!< Bit mask of RGN2WA field. */
+#define MWU_REGIONENCLR_RGN2WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN2WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN2WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 3 : Disable read access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1RA_Pos (3UL) /*!< Position of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Msk (0x1UL << MWU_REGIONENCLR_RGN1RA_Pos) /*!< Bit mask of RGN1RA field. */
+#define MWU_REGIONENCLR_RGN1RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 2 : Disable write access watch in region[1] */
+#define MWU_REGIONENCLR_RGN1WA_Pos (2UL) /*!< Position of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Msk (0x1UL << MWU_REGIONENCLR_RGN1WA_Pos) /*!< Bit mask of RGN1WA field. */
+#define MWU_REGIONENCLR_RGN1WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN1WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN1WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Bit 1 : Disable read access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0RA_Pos (1UL) /*!< Position of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Msk (0x1UL << MWU_REGIONENCLR_RGN0RA_Pos) /*!< Bit mask of RGN0RA field. */
+#define MWU_REGIONENCLR_RGN0RA_Disabled (0UL) /*!< Read access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0RA_Enabled (1UL) /*!< Read access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0RA_Clear (1UL) /*!< Disable read access watch in this region */
+
+/* Bit 0 : Disable write access watch in region[0] */
+#define MWU_REGIONENCLR_RGN0WA_Pos (0UL) /*!< Position of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Msk (0x1UL << MWU_REGIONENCLR_RGN0WA_Pos) /*!< Bit mask of RGN0WA field. */
+#define MWU_REGIONENCLR_RGN0WA_Disabled (0UL) /*!< Write access watch in this region is disabled */
+#define MWU_REGIONENCLR_RGN0WA_Enabled (1UL) /*!< Write access watch in this region is enabled */
+#define MWU_REGIONENCLR_RGN0WA_Clear (1UL) /*!< Disable write access watch in this region */
+
+/* Register: MWU_REGION_START */
+/* Description: Description cluster[0]:  Start address for region 0 */
+
+/* Bits 31..0 : Start address for region */
+#define MWU_REGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_REGION_START_START_Msk (0xFFFFFFFFUL << MWU_REGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_REGION_END */
+/* Description: Description cluster[0]:  End address of region 0 */
+
+/* Bits 31..0 : End address of region. */
+#define MWU_REGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_REGION_END_END_Msk (0xFFFFFFFFUL << MWU_REGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_START */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_START_START_Pos (0UL) /*!< Position of START field. */
+#define MWU_PREGION_START_START_Msk (0xFFFFFFFFUL << MWU_PREGION_START_START_Pos) /*!< Bit mask of START field. */
+
+/* Register: MWU_PREGION_END */
+/* Description: Description cluster[0]:  Reserved for future use */
+
+/* Bits 31..0 : Reserved for future use */
+#define MWU_PREGION_END_END_Pos (0UL) /*!< Position of END field. */
+#define MWU_PREGION_END_END_Msk (0xFFFFFFFFUL << MWU_PREGION_END_END_Pos) /*!< Bit mask of END field. */
+
+/* Register: MWU_PREGION_SUBS */
+/* Description: Description cluster[0]:  Subregions of region 0 */
+
+/* Bit 31 : Include or exclude subregion 31 in region */
+#define MWU_PREGION_SUBS_SR31_Pos (31UL) /*!< Position of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Msk (0x1UL << MWU_PREGION_SUBS_SR31_Pos) /*!< Bit mask of SR31 field. */
+#define MWU_PREGION_SUBS_SR31_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR31_Include (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude subregion 30 in region */
+#define MWU_PREGION_SUBS_SR30_Pos (30UL) /*!< Position of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Msk (0x1UL << MWU_PREGION_SUBS_SR30_Pos) /*!< Bit mask of SR30 field. */
+#define MWU_PREGION_SUBS_SR30_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR30_Include (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude subregion 29 in region */
+#define MWU_PREGION_SUBS_SR29_Pos (29UL) /*!< Position of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Msk (0x1UL << MWU_PREGION_SUBS_SR29_Pos) /*!< Bit mask of SR29 field. */
+#define MWU_PREGION_SUBS_SR29_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR29_Include (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude subregion 28 in region */
+#define MWU_PREGION_SUBS_SR28_Pos (28UL) /*!< Position of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Msk (0x1UL << MWU_PREGION_SUBS_SR28_Pos) /*!< Bit mask of SR28 field. */
+#define MWU_PREGION_SUBS_SR28_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR28_Include (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude subregion 27 in region */
+#define MWU_PREGION_SUBS_SR27_Pos (27UL) /*!< Position of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Msk (0x1UL << MWU_PREGION_SUBS_SR27_Pos) /*!< Bit mask of SR27 field. */
+#define MWU_PREGION_SUBS_SR27_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR27_Include (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude subregion 26 in region */
+#define MWU_PREGION_SUBS_SR26_Pos (26UL) /*!< Position of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Msk (0x1UL << MWU_PREGION_SUBS_SR26_Pos) /*!< Bit mask of SR26 field. */
+#define MWU_PREGION_SUBS_SR26_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR26_Include (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude subregion 25 in region */
+#define MWU_PREGION_SUBS_SR25_Pos (25UL) /*!< Position of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Msk (0x1UL << MWU_PREGION_SUBS_SR25_Pos) /*!< Bit mask of SR25 field. */
+#define MWU_PREGION_SUBS_SR25_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR25_Include (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude subregion 24 in region */
+#define MWU_PREGION_SUBS_SR24_Pos (24UL) /*!< Position of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Msk (0x1UL << MWU_PREGION_SUBS_SR24_Pos) /*!< Bit mask of SR24 field. */
+#define MWU_PREGION_SUBS_SR24_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR24_Include (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude subregion 23 in region */
+#define MWU_PREGION_SUBS_SR23_Pos (23UL) /*!< Position of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Msk (0x1UL << MWU_PREGION_SUBS_SR23_Pos) /*!< Bit mask of SR23 field. */
+#define MWU_PREGION_SUBS_SR23_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR23_Include (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude subregion 22 in region */
+#define MWU_PREGION_SUBS_SR22_Pos (22UL) /*!< Position of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Msk (0x1UL << MWU_PREGION_SUBS_SR22_Pos) /*!< Bit mask of SR22 field. */
+#define MWU_PREGION_SUBS_SR22_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR22_Include (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude subregion 21 in region */
+#define MWU_PREGION_SUBS_SR21_Pos (21UL) /*!< Position of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Msk (0x1UL << MWU_PREGION_SUBS_SR21_Pos) /*!< Bit mask of SR21 field. */
+#define MWU_PREGION_SUBS_SR21_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR21_Include (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude subregion 20 in region */
+#define MWU_PREGION_SUBS_SR20_Pos (20UL) /*!< Position of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Msk (0x1UL << MWU_PREGION_SUBS_SR20_Pos) /*!< Bit mask of SR20 field. */
+#define MWU_PREGION_SUBS_SR20_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR20_Include (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude subregion 19 in region */
+#define MWU_PREGION_SUBS_SR19_Pos (19UL) /*!< Position of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Msk (0x1UL << MWU_PREGION_SUBS_SR19_Pos) /*!< Bit mask of SR19 field. */
+#define MWU_PREGION_SUBS_SR19_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR19_Include (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude subregion 18 in region */
+#define MWU_PREGION_SUBS_SR18_Pos (18UL) /*!< Position of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Msk (0x1UL << MWU_PREGION_SUBS_SR18_Pos) /*!< Bit mask of SR18 field. */
+#define MWU_PREGION_SUBS_SR18_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR18_Include (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude subregion 17 in region */
+#define MWU_PREGION_SUBS_SR17_Pos (17UL) /*!< Position of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Msk (0x1UL << MWU_PREGION_SUBS_SR17_Pos) /*!< Bit mask of SR17 field. */
+#define MWU_PREGION_SUBS_SR17_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR17_Include (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude subregion 16 in region */
+#define MWU_PREGION_SUBS_SR16_Pos (16UL) /*!< Position of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Msk (0x1UL << MWU_PREGION_SUBS_SR16_Pos) /*!< Bit mask of SR16 field. */
+#define MWU_PREGION_SUBS_SR16_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR16_Include (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude subregion 15 in region */
+#define MWU_PREGION_SUBS_SR15_Pos (15UL) /*!< Position of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Msk (0x1UL << MWU_PREGION_SUBS_SR15_Pos) /*!< Bit mask of SR15 field. */
+#define MWU_PREGION_SUBS_SR15_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR15_Include (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude subregion 14 in region */
+#define MWU_PREGION_SUBS_SR14_Pos (14UL) /*!< Position of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Msk (0x1UL << MWU_PREGION_SUBS_SR14_Pos) /*!< Bit mask of SR14 field. */
+#define MWU_PREGION_SUBS_SR14_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR14_Include (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude subregion 13 in region */
+#define MWU_PREGION_SUBS_SR13_Pos (13UL) /*!< Position of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Msk (0x1UL << MWU_PREGION_SUBS_SR13_Pos) /*!< Bit mask of SR13 field. */
+#define MWU_PREGION_SUBS_SR13_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR13_Include (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude subregion 12 in region */
+#define MWU_PREGION_SUBS_SR12_Pos (12UL) /*!< Position of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Msk (0x1UL << MWU_PREGION_SUBS_SR12_Pos) /*!< Bit mask of SR12 field. */
+#define MWU_PREGION_SUBS_SR12_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR12_Include (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude subregion 11 in region */
+#define MWU_PREGION_SUBS_SR11_Pos (11UL) /*!< Position of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Msk (0x1UL << MWU_PREGION_SUBS_SR11_Pos) /*!< Bit mask of SR11 field. */
+#define MWU_PREGION_SUBS_SR11_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR11_Include (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude subregion 10 in region */
+#define MWU_PREGION_SUBS_SR10_Pos (10UL) /*!< Position of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Msk (0x1UL << MWU_PREGION_SUBS_SR10_Pos) /*!< Bit mask of SR10 field. */
+#define MWU_PREGION_SUBS_SR10_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR10_Include (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude subregion 9 in region */
+#define MWU_PREGION_SUBS_SR9_Pos (9UL) /*!< Position of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Msk (0x1UL << MWU_PREGION_SUBS_SR9_Pos) /*!< Bit mask of SR9 field. */
+#define MWU_PREGION_SUBS_SR9_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR9_Include (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude subregion 8 in region */
+#define MWU_PREGION_SUBS_SR8_Pos (8UL) /*!< Position of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Msk (0x1UL << MWU_PREGION_SUBS_SR8_Pos) /*!< Bit mask of SR8 field. */
+#define MWU_PREGION_SUBS_SR8_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR8_Include (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude subregion 7 in region */
+#define MWU_PREGION_SUBS_SR7_Pos (7UL) /*!< Position of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Msk (0x1UL << MWU_PREGION_SUBS_SR7_Pos) /*!< Bit mask of SR7 field. */
+#define MWU_PREGION_SUBS_SR7_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR7_Include (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude subregion 6 in region */
+#define MWU_PREGION_SUBS_SR6_Pos (6UL) /*!< Position of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Msk (0x1UL << MWU_PREGION_SUBS_SR6_Pos) /*!< Bit mask of SR6 field. */
+#define MWU_PREGION_SUBS_SR6_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR6_Include (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude subregion 5 in region */
+#define MWU_PREGION_SUBS_SR5_Pos (5UL) /*!< Position of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Msk (0x1UL << MWU_PREGION_SUBS_SR5_Pos) /*!< Bit mask of SR5 field. */
+#define MWU_PREGION_SUBS_SR5_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR5_Include (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude subregion 4 in region */
+#define MWU_PREGION_SUBS_SR4_Pos (4UL) /*!< Position of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Msk (0x1UL << MWU_PREGION_SUBS_SR4_Pos) /*!< Bit mask of SR4 field. */
+#define MWU_PREGION_SUBS_SR4_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR4_Include (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude subregion 3 in region */
+#define MWU_PREGION_SUBS_SR3_Pos (3UL) /*!< Position of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Msk (0x1UL << MWU_PREGION_SUBS_SR3_Pos) /*!< Bit mask of SR3 field. */
+#define MWU_PREGION_SUBS_SR3_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR3_Include (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude subregion 2 in region */
+#define MWU_PREGION_SUBS_SR2_Pos (2UL) /*!< Position of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Msk (0x1UL << MWU_PREGION_SUBS_SR2_Pos) /*!< Bit mask of SR2 field. */
+#define MWU_PREGION_SUBS_SR2_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR2_Include (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude subregion 1 in region */
+#define MWU_PREGION_SUBS_SR1_Pos (1UL) /*!< Position of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Msk (0x1UL << MWU_PREGION_SUBS_SR1_Pos) /*!< Bit mask of SR1 field. */
+#define MWU_PREGION_SUBS_SR1_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR1_Include (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude subregion 0 in region */
+#define MWU_PREGION_SUBS_SR0_Pos (0UL) /*!< Position of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Msk (0x1UL << MWU_PREGION_SUBS_SR0_Pos) /*!< Bit mask of SR0 field. */
+#define MWU_PREGION_SUBS_SR0_Exclude (0UL) /*!< Exclude */
+#define MWU_PREGION_SUBS_SR0_Include (1UL) /*!< Include */
+
+
+/* Peripheral: NFCT */
+/* Description: NFC-A compatible radio */
+
+/* Register: NFCT_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between FIELDLOST event and SENSE task */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Pos (1UL) /*!< Position of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Msk (0x1UL << NFCT_SHORTS_FIELDLOST_SENSE_Pos) /*!< Bit mask of FIELDLOST_SENSE field. */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDLOST_SENSE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between FIELDDETECTED event and ACTIVATE task */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos (0UL) /*!< Position of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Msk (0x1UL << NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Pos) /*!< Bit mask of FIELDDETECTED_ACTIVATE field. */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Disabled (0UL) /*!< Disable shortcut */
+#define NFCT_SHORTS_FIELDDETECTED_ACTIVATE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: NFCT_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 20 : Enable or disable interrupt for STARTED event */
+#define NFCT_INTEN_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTEN_STARTED_Msk (0x1UL << NFCT_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for SELECTED event */
+#define NFCT_INTEN_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Msk (0x1UL << NFCT_INTEN_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTEN_SELECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_SELECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for COLLISION event */
+#define NFCT_INTEN_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Msk (0x1UL << NFCT_INTEN_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTEN_COLLISION_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_COLLISION_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTEN_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for ENDTX event */
+#define NFCT_INTEN_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Msk (0x1UL << NFCT_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for ENDRX event */
+#define NFCT_INTEN_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Msk (0x1UL << NFCT_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for RXERROR event */
+#define NFCT_INTEN_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Msk (0x1UL << NFCT_INTEN_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTEN_RXERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for ERROR event */
+#define NFCT_INTEN_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTEN_ERROR_Msk (0x1UL << NFCT_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for RXFRAMEEND event */
+#define NFCT_INTEN_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Msk (0x1UL << NFCT_INTEN_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTEN_RXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for RXFRAMESTART event */
+#define NFCT_INTEN_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Msk (0x1UL << NFCT_INTEN_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTEN_RXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_RXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for TXFRAMEEND event */
+#define NFCT_INTEN_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Msk (0x1UL << NFCT_INTEN_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTEN_TXFRAMEEND_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMEEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for TXFRAMESTART event */
+#define NFCT_INTEN_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Msk (0x1UL << NFCT_INTEN_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTEN_TXFRAMESTART_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_TXFRAMESTART_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for FIELDLOST event */
+#define NFCT_INTEN_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Msk (0x1UL << NFCT_INTEN_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTEN_FIELDLOST_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDLOST_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for FIELDDETECTED event */
+#define NFCT_INTEN_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Msk (0x1UL << NFCT_INTEN_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTEN_FIELDDETECTED_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_FIELDDETECTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for READY event */
+#define NFCT_INTEN_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTEN_READY_Msk (0x1UL << NFCT_INTEN_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTEN_READY_Disabled (0UL) /*!< Disable */
+#define NFCT_INTEN_READY_Enabled (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 20 : Write '1' to Enable interrupt for STARTED event */
+#define NFCT_INTENSET_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENSET_STARTED_Msk (0x1UL << NFCT_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for SELECTED event */
+#define NFCT_INTENSET_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Msk (0x1UL << NFCT_INTENSET_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENSET_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_SELECTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COLLISION event */
+#define NFCT_INTENSET_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Msk (0x1UL << NFCT_INTENSET_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENSET_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_COLLISION_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENSET_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_AUTOCOLRESSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for ENDTX event */
+#define NFCT_INTENSET_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Msk (0x1UL << NFCT_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for ENDRX event */
+#define NFCT_INTENSET_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Msk (0x1UL << NFCT_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for RXERROR event */
+#define NFCT_INTENSET_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Msk (0x1UL << NFCT_INTENSET_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENSET_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for ERROR event */
+#define NFCT_INTENSET_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENSET_ERROR_Msk (0x1UL << NFCT_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for RXFRAMEEND event */
+#define NFCT_INTENSET_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENSET_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for RXFRAMESTART event */
+#define NFCT_INTENSET_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENSET_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_RXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for TXFRAMEEND event */
+#define NFCT_INTENSET_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Msk (0x1UL << NFCT_INTENSET_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENSET_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMEEND_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for TXFRAMESTART event */
+#define NFCT_INTENSET_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Msk (0x1UL << NFCT_INTENSET_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENSET_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_TXFRAMESTART_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for FIELDLOST event */
+#define NFCT_INTENSET_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Msk (0x1UL << NFCT_INTENSET_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENSET_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDLOST_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for FIELDDETECTED event */
+#define NFCT_INTENSET_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Msk (0x1UL << NFCT_INTENSET_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENSET_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_FIELDDETECTED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define NFCT_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENSET_READY_Msk (0x1UL << NFCT_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: NFCT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 20 : Write '1' to Disable interrupt for STARTED event */
+#define NFCT_INTENCLR_STARTED_Pos (20UL) /*!< Position of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Msk (0x1UL << NFCT_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define NFCT_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for SELECTED event */
+#define NFCT_INTENCLR_SELECTED_Pos (19UL) /*!< Position of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Msk (0x1UL << NFCT_INTENCLR_SELECTED_Pos) /*!< Bit mask of SELECTED field. */
+#define NFCT_INTENCLR_SELECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_SELECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_SELECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COLLISION event */
+#define NFCT_INTENCLR_COLLISION_Pos (18UL) /*!< Position of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Msk (0x1UL << NFCT_INTENCLR_COLLISION_Pos) /*!< Bit mask of COLLISION field. */
+#define NFCT_INTENCLR_COLLISION_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_COLLISION_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_COLLISION_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for AUTOCOLRESSTARTED event */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos (14UL) /*!< Position of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Msk (0x1UL << NFCT_INTENCLR_AUTOCOLRESSTARTED_Pos) /*!< Bit mask of AUTOCOLRESSTARTED field. */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_AUTOCOLRESSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for ENDTX event */
+#define NFCT_INTENCLR_ENDTX_Pos (12UL) /*!< Position of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Msk (0x1UL << NFCT_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define NFCT_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for ENDRX event */
+#define NFCT_INTENCLR_ENDRX_Pos (11UL) /*!< Position of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Msk (0x1UL << NFCT_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define NFCT_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for RXERROR event */
+#define NFCT_INTENCLR_RXERROR_Pos (10UL) /*!< Position of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Msk (0x1UL << NFCT_INTENCLR_RXERROR_Pos) /*!< Bit mask of RXERROR field. */
+#define NFCT_INTENCLR_RXERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for ERROR event */
+#define NFCT_INTENCLR_ERROR_Pos (7UL) /*!< Position of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Msk (0x1UL << NFCT_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define NFCT_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for RXFRAMEEND event */
+#define NFCT_INTENCLR_RXFRAMEEND_Pos (6UL) /*!< Position of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_RXFRAMEEND_Pos) /*!< Bit mask of RXFRAMEEND field. */
+#define NFCT_INTENCLR_RXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for RXFRAMESTART event */
+#define NFCT_INTENCLR_RXFRAMESTART_Pos (5UL) /*!< Position of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_RXFRAMESTART_Pos) /*!< Bit mask of RXFRAMESTART field. */
+#define NFCT_INTENCLR_RXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_RXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for TXFRAMEEND event */
+#define NFCT_INTENCLR_TXFRAMEEND_Pos (4UL) /*!< Position of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Msk (0x1UL << NFCT_INTENCLR_TXFRAMEEND_Pos) /*!< Bit mask of TXFRAMEEND field. */
+#define NFCT_INTENCLR_TXFRAMEEND_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMEEND_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for TXFRAMESTART event */
+#define NFCT_INTENCLR_TXFRAMESTART_Pos (3UL) /*!< Position of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Msk (0x1UL << NFCT_INTENCLR_TXFRAMESTART_Pos) /*!< Bit mask of TXFRAMESTART field. */
+#define NFCT_INTENCLR_TXFRAMESTART_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_TXFRAMESTART_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for FIELDLOST event */
+#define NFCT_INTENCLR_FIELDLOST_Pos (2UL) /*!< Position of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Msk (0x1UL << NFCT_INTENCLR_FIELDLOST_Pos) /*!< Bit mask of FIELDLOST field. */
+#define NFCT_INTENCLR_FIELDLOST_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDLOST_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDLOST_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for FIELDDETECTED event */
+#define NFCT_INTENCLR_FIELDDETECTED_Pos (1UL) /*!< Position of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Msk (0x1UL << NFCT_INTENCLR_FIELDDETECTED_Pos) /*!< Bit mask of FIELDDETECTED field. */
+#define NFCT_INTENCLR_FIELDDETECTED_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_FIELDDETECTED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define NFCT_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define NFCT_INTENCLR_READY_Msk (0x1UL << NFCT_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define NFCT_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define NFCT_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define NFCT_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: NFCT_ERRORSTATUS */
+/* Description: NFC Error Status register */
+
+/* Bit 3 : Field level is too low at min load resistance */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos (3UL) /*!< Position of NFCFIELDTOOWEAK field. */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOWEAK_Pos) /*!< Bit mask of NFCFIELDTOOWEAK field. */
+
+/* Bit 2 : Field level is too high at max load resistance */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos (2UL) /*!< Position of NFCFIELDTOOSTRONG field. */
+#define NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Msk (0x1UL << NFCT_ERRORSTATUS_NFCFIELDTOOSTRONG_Pos) /*!< Bit mask of NFCFIELDTOOSTRONG field. */
+
+/* Bit 0 : No STARTTX task triggered before expiration of the time set in FRAMEDELAYMAX */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos (0UL) /*!< Position of FRAMEDELAYTIMEOUT field. */
+#define NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Msk (0x1UL << NFCT_ERRORSTATUS_FRAMEDELAYTIMEOUT_Pos) /*!< Bit mask of FRAMEDELAYTIMEOUT field. */
+
+/* Register: NFCT_FRAMESTATUS_RX */
+/* Description: Result of last incoming frames */
+
+/* Bit 3 : Overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Pos (3UL) /*!< Position of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Msk (0x1UL << NFCT_FRAMESTATUS_RX_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_NoOverrun (0UL) /*!< No overrun detected */
+#define NFCT_FRAMESTATUS_RX_OVERRUN_Overrun (1UL) /*!< Overrun error */
+
+/* Bit 2 : Parity status of received frame */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos (2UL) /*!< Position of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_Msk (0x1UL << NFCT_FRAMESTATUS_RX_PARITYSTATUS_Pos) /*!< Bit mask of PARITYSTATUS field. */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityOK (0UL) /*!< Frame received with parity OK */
+#define NFCT_FRAMESTATUS_RX_PARITYSTATUS_ParityError (1UL) /*!< Frame received with parity error */
+
+/* Bit 0 : No valid End of Frame detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Pos (0UL) /*!< Position of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_Msk (0x1UL << NFCT_FRAMESTATUS_RX_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCCorrect (0UL) /*!< Valid CRC detected */
+#define NFCT_FRAMESTATUS_RX_CRCERROR_CRCError (1UL) /*!< CRC received does not match local check */
+
+/* Register: NFCT_CURRENTLOADCTRL */
+/* Description: Current value driven to the NFC Load Control */
+
+/* Bits 5..0 : Current value driven to the NFC Load Control */
+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos (0UL) /*!< Position of CURRENTLOADCTRL field. */
+#define NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Msk (0x3FUL << NFCT_CURRENTLOADCTRL_CURRENTLOADCTRL_Pos) /*!< Bit mask of CURRENTLOADCTRL field. */
+
+/* Register: NFCT_FIELDPRESENT */
+/* Description: Indicates the presence or not of a valid field */
+
+/* Bit 1 : Indicates if the low level has locked to the field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Pos (1UL) /*!< Position of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Msk (0x1UL << NFCT_FIELDPRESENT_LOCKDETECT_Pos) /*!< Bit mask of LOCKDETECT field. */
+#define NFCT_FIELDPRESENT_LOCKDETECT_NotLocked (0UL) /*!< Not locked to field */
+#define NFCT_FIELDPRESENT_LOCKDETECT_Locked (1UL) /*!< Locked to field */
+
+/* Bit 0 : Indicates the presence or not of a valid field. Available only in the activated state. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Pos (0UL) /*!< Position of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_Msk (0x1UL << NFCT_FIELDPRESENT_FIELDPRESENT_Pos) /*!< Bit mask of FIELDPRESENT field. */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_NoField (0UL) /*!< No valid field detected */
+#define NFCT_FIELDPRESENT_FIELDPRESENT_FieldPresent (1UL) /*!< Valid field detected */
+
+/* Register: NFCT_FRAMEDELAYMIN */
+/* Description: Minimum frame delay */
+
+/* Bits 15..0 : Minimum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos (0UL) /*!< Position of FRAMEDELAYMIN field. */
+#define NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Msk (0xFFFFUL << NFCT_FRAMEDELAYMIN_FRAMEDELAYMIN_Pos) /*!< Bit mask of FRAMEDELAYMIN field. */
+
+/* Register: NFCT_FRAMEDELAYMAX */
+/* Description: Maximum frame delay */
+
+/* Bits 15..0 : Maximum frame delay in number of 13.56 MHz clocks */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos (0UL) /*!< Position of FRAMEDELAYMAX field. */
+#define NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Msk (0xFFFFUL << NFCT_FRAMEDELAYMAX_FRAMEDELAYMAX_Pos) /*!< Bit mask of FRAMEDELAYMAX field. */
+
+/* Register: NFCT_FRAMEDELAYMODE */
+/* Description: Configuration register for the Frame Delay Timer */
+
+/* Bits 1..0 : Configuration register for the Frame Delay Timer */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos (0UL) /*!< Position of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Msk (0x3UL << NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Pos) /*!< Bit mask of FRAMEDELAYMODE field. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_FreeRun (0UL) /*!< Transmission is independent of frame timer and will start when the STARTTX task is triggered. No timeout. */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_Window (1UL) /*!< Frame is transmitted between FRAMEDELAYMIN and FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_ExactVal (2UL) /*!< Frame is transmitted exactly at FRAMEDELAYMAX */
+#define NFCT_FRAMEDELAYMODE_FRAMEDELAYMODE_WindowGrid (3UL) /*!< Frame is transmitted on a bit grid between FRAMEDELAYMIN and FRAMEDELAYMAX */
+
+/* Register: NFCT_PACKETPTR */
+/* Description: Packet pointer for TXD and RXD data storage in Data RAM */
+
+/* Bits 31..0 : Packet pointer for TXD and RXD data storage in Data RAM. This address is a byte aligned RAM address. */
+#define NFCT_PACKETPTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define NFCT_PACKETPTR_PTR_Msk (0xFFFFFFFFUL << NFCT_PACKETPTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: NFCT_MAXLEN */
+/* Description: Size of allocated for TXD and RXD data storage buffer in Data RAM */
+
+/* Bits 8..0 : Size of allocated for TXD and RXD data storage buffer in Data RAM */
+#define NFCT_MAXLEN_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define NFCT_MAXLEN_MAXLEN_Msk (0x1FFUL << NFCT_MAXLEN_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: NFCT_TXD_FRAMECONFIG */
+/* Description: Configuration of outgoing frames */
+
+/* Bit 4 : CRC mode for outgoing frames */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos (4UL) /*!< Position of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_CRCMODETX_Pos) /*!< Bit mask of CRCMODETX field. */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_NoCRCTX (0UL) /*!< CRC is not added to the frame */
+#define NFCT_TXD_FRAMECONFIG_CRCMODETX_CRC16TX (1UL) /*!< 16 bit CRC added to the frame based on all the data read from RAM that is used in the frame */
+
+/* Bit 2 : Adding SoF or not in TX frames */
+#define NFCT_TXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_TXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol not added */
+#define NFCT_TXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol added */
+
+/* Bit 1 : Discarding unused bits in start or at end of a Frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos (1UL) /*!< Position of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_DISCARDMODE_Pos) /*!< Bit mask of DISCARDMODE field. */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardEnd (0UL) /*!< Unused bits is discarded at end of frame */
+#define NFCT_TXD_FRAMECONFIG_DISCARDMODE_DiscardStart (1UL) /*!< Unused bits is discarded at start of frame */
+
+/* Bit 0 : Adding parity or not in the frame */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_TXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_TXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not added in TX frames */
+#define NFCT_TXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is added TX frames */
+
+/* Register: NFCT_TXD_AMOUNT */
+/* Description: Size of outgoing frame */
+
+/* Bits 11..3 : Number of complete bytes that shall be included in the frame, excluding CRC, parity and framing */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Pos (3UL) /*!< Position of TXDATABYTES field. */
+#define NFCT_TXD_AMOUNT_TXDATABYTES_Msk (0x1FFUL << NFCT_TXD_AMOUNT_TXDATABYTES_Pos) /*!< Bit mask of TXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last or first byte read from RAM that shall be included in the frame (excluding parity bit). */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Pos (0UL) /*!< Position of TXDATABITS field. */
+#define NFCT_TXD_AMOUNT_TXDATABITS_Msk (0x7UL << NFCT_TXD_AMOUNT_TXDATABITS_Pos) /*!< Bit mask of TXDATABITS field. */
+
+/* Register: NFCT_RXD_FRAMECONFIG */
+/* Description: Configuration of incoming frames */
+
+/* Bit 4 : CRC mode for incoming frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos (4UL) /*!< Position of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_CRCMODERX_Pos) /*!< Bit mask of CRCMODERX field. */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_NoCRCRX (0UL) /*!< CRC is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_CRCMODERX_CRC16RX (1UL) /*!< Last 16 bits in RX frame is CRC, CRC is checked and CRCSTATUS updated */
+
+/* Bit 2 : SoF expected or not in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_Pos (2UL) /*!< Position of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_SOF_Pos) /*!< Bit mask of SOF field. */
+#define NFCT_RXD_FRAMECONFIG_SOF_NoSoF (0UL) /*!< Start of Frame symbol is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_SOF_SoF (1UL) /*!< Start of Frame symbol is expected in RX frames */
+
+/* Bit 0 : Parity expected or not in RX frame */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Pos (0UL) /*!< Position of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Msk (0x1UL << NFCT_RXD_FRAMECONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define NFCT_RXD_FRAMECONFIG_PARITY_NoParity (0UL) /*!< Parity is not expected in RX frames */
+#define NFCT_RXD_FRAMECONFIG_PARITY_Parity (1UL) /*!< Parity is expected in RX frames */
+
+/* Register: NFCT_RXD_AMOUNT */
+/* Description: Size of last incoming frame */
+
+/* Bits 11..3 : Number of complete bytes received in the frame (including CRC, but excluding parity and SoF/EoF framing) */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Pos (3UL) /*!< Position of RXDATABYTES field. */
+#define NFCT_RXD_AMOUNT_RXDATABYTES_Msk (0x1FFUL << NFCT_RXD_AMOUNT_RXDATABYTES_Pos) /*!< Bit mask of RXDATABYTES field. */
+
+/* Bits 2..0 : Number of bits in the last byte in the frame, if less than 8 (including CRC, but excluding parity and SoF/EoF framing). */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Pos (0UL) /*!< Position of RXDATABITS field. */
+#define NFCT_RXD_AMOUNT_RXDATABITS_Msk (0x7UL << NFCT_RXD_AMOUNT_RXDATABITS_Pos) /*!< Bit mask of RXDATABITS field. */
+
+/* Register: NFCT_NFCID1_LAST */
+/* Description: Last NFCID1 part (4, 7 or 10 bytes ID) */
+
+/* Bits 31..24 : NFCID1 byte W */
+#define NFCT_NFCID1_LAST_NFCID1_W_Pos (24UL) /*!< Position of NFCID1_W field. */
+#define NFCT_NFCID1_LAST_NFCID1_W_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_W_Pos) /*!< Bit mask of NFCID1_W field. */
+
+/* Bits 23..16 : NFCID1 byte X */
+#define NFCT_NFCID1_LAST_NFCID1_X_Pos (16UL) /*!< Position of NFCID1_X field. */
+#define NFCT_NFCID1_LAST_NFCID1_X_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_X_Pos) /*!< Bit mask of NFCID1_X field. */
+
+/* Bits 15..8 : NFCID1 byte Y */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Pos (8UL) /*!< Position of NFCID1_Y field. */
+#define NFCT_NFCID1_LAST_NFCID1_Y_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Y_Pos) /*!< Bit mask of NFCID1_Y field. */
+
+/* Bits 7..0 : NFCID1 byte Z (very last byte sent) */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Pos (0UL) /*!< Position of NFCID1_Z field. */
+#define NFCT_NFCID1_LAST_NFCID1_Z_Msk (0xFFUL << NFCT_NFCID1_LAST_NFCID1_Z_Pos) /*!< Bit mask of NFCID1_Z field. */
+
+/* Register: NFCT_NFCID1_2ND_LAST */
+/* Description: Second last NFCID1 part (7 or 10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte T */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos (16UL) /*!< Position of NFCID1_T field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_T_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_T_Pos) /*!< Bit mask of NFCID1_T field. */
+
+/* Bits 15..8 : NFCID1 byte U */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos (8UL) /*!< Position of NFCID1_U field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_U_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_U_Pos) /*!< Bit mask of NFCID1_U field. */
+
+/* Bits 7..0 : NFCID1 byte V */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos (0UL) /*!< Position of NFCID1_V field. */
+#define NFCT_NFCID1_2ND_LAST_NFCID1_V_Msk (0xFFUL << NFCT_NFCID1_2ND_LAST_NFCID1_V_Pos) /*!< Bit mask of NFCID1_V field. */
+
+/* Register: NFCT_NFCID1_3RD_LAST */
+/* Description: Third last NFCID1 part (10 bytes ID) */
+
+/* Bits 23..16 : NFCID1 byte Q */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos (16UL) /*!< Position of NFCID1_Q field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_Q_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_Q_Pos) /*!< Bit mask of NFCID1_Q field. */
+
+/* Bits 15..8 : NFCID1 byte R */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos (8UL) /*!< Position of NFCID1_R field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_R_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_R_Pos) /*!< Bit mask of NFCID1_R field. */
+
+/* Bits 7..0 : NFCID1 byte S */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos (0UL) /*!< Position of NFCID1_S field. */
+#define NFCT_NFCID1_3RD_LAST_NFCID1_S_Msk (0xFFUL << NFCT_NFCID1_3RD_LAST_NFCID1_S_Pos) /*!< Bit mask of NFCID1_S field. */
+
+/* Register: NFCT_SENSRES */
+/* Description: NFC-A SENS_RES auto-response settings */
+
+/* Bits 15..12 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU74_Pos (12UL) /*!< Position of RFU74 field. */
+#define NFCT_SENSRES_RFU74_Msk (0xFUL << NFCT_SENSRES_RFU74_Pos) /*!< Bit mask of RFU74 field. */
+
+/* Bits 11..8 : Tag platform configuration as defined by the b4:b1 of byte 2 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_PLATFCONFIG_Pos (8UL) /*!< Position of PLATFCONFIG field. */
+#define NFCT_SENSRES_PLATFCONFIG_Msk (0xFUL << NFCT_SENSRES_PLATFCONFIG_Pos) /*!< Bit mask of PLATFCONFIG field. */
+
+/* Bits 7..6 : NFCID1 size. This value is used by the Auto collision resolution engine. */
+#define NFCT_SENSRES_NFCIDSIZE_Pos (6UL) /*!< Position of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_Msk (0x3UL << NFCT_SENSRES_NFCIDSIZE_Pos) /*!< Bit mask of NFCIDSIZE field. */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Single (0UL) /*!< NFCID1 size: single (4 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Double (1UL) /*!< NFCID1 size: double (7 bytes) */
+#define NFCT_SENSRES_NFCIDSIZE_NFCID1Triple (2UL) /*!< NFCID1 size: triple (10 bytes) */
+
+/* Bit 5 : Reserved for future use. Shall be 0. */
+#define NFCT_SENSRES_RFU5_Pos (5UL) /*!< Position of RFU5 field. */
+#define NFCT_SENSRES_RFU5_Msk (0x1UL << NFCT_SENSRES_RFU5_Pos) /*!< Bit mask of RFU5 field. */
+
+/* Bits 4..0 : Bit frame SDD as defined by the b5:b1 of byte 1 in SENS_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SENSRES_BITFRAMESDD_Pos (0UL) /*!< Position of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_Msk (0x1FUL << NFCT_SENSRES_BITFRAMESDD_Pos) /*!< Bit mask of BITFRAMESDD field. */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00000 (0UL) /*!< SDD pattern 00000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00001 (1UL) /*!< SDD pattern 00001 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00010 (2UL) /*!< SDD pattern 00010 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD00100 (4UL) /*!< SDD pattern 00100 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD01000 (8UL) /*!< SDD pattern 01000 */
+#define NFCT_SENSRES_BITFRAMESDD_SDD10000 (16UL) /*!< SDD pattern 10000 */
+
+/* Register: NFCT_SELRES */
+/* Description: NFC-A SEL_RES auto-response settings */
+
+/* Bit 7 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU7_Pos (7UL) /*!< Position of RFU7 field. */
+#define NFCT_SELRES_RFU7_Msk (0x1UL << NFCT_SELRES_RFU7_Pos) /*!< Bit mask of RFU7 field. */
+
+/* Bits 6..5 : Protocol as defined by the b7:b6 of SEL_RES response in the NFC Forum, NFC Digital Protocol Technical Specification */
+#define NFCT_SELRES_PROTOCOL_Pos (5UL) /*!< Position of PROTOCOL field. */
+#define NFCT_SELRES_PROTOCOL_Msk (0x3UL << NFCT_SELRES_PROTOCOL_Pos) /*!< Bit mask of PROTOCOL field. */
+
+/* Bits 4..3 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU43_Pos (3UL) /*!< Position of RFU43 field. */
+#define NFCT_SELRES_RFU43_Msk (0x3UL << NFCT_SELRES_RFU43_Pos) /*!< Bit mask of RFU43 field. */
+
+/* Bit 2 : Cascade bit (controlled by hardware, write has no effect) */
+#define NFCT_SELRES_CASCADE_Pos (2UL) /*!< Position of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Msk (0x1UL << NFCT_SELRES_CASCADE_Pos) /*!< Bit mask of CASCADE field. */
+#define NFCT_SELRES_CASCADE_Complete (0UL) /*!< NFCID1 complete */
+#define NFCT_SELRES_CASCADE_NotComplete (1UL) /*!< NFCID1 not complete */
+
+/* Bits 1..0 : Reserved for future use. Shall be 0. */
+#define NFCT_SELRES_RFU10_Pos (0UL) /*!< Position of RFU10 field. */
+#define NFCT_SELRES_RFU10_Msk (0x3UL << NFCT_SELRES_RFU10_Pos) /*!< Bit mask of RFU10 field. */
+
+
+/* Peripheral: NVMC */
+/* Description: Non Volatile Memory Controller */
+
+/* Register: NVMC_READY */
+/* Description: Ready flag */
+
+/* Bit 0 : NVMC is ready or busy */
+#define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
+#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
+#define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation) */
+#define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready */
+
+/* Register: NVMC_CONFIG */
+/* Description: Configuration register */
+
+/* Bits 1..0 : Program memory access mode. It is strongly recommended to only activate erase and write modes when they are actively used. Enabling write or erase will invalidate the cache and keep it invalidated. */
+#define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
+#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
+#define NVMC_CONFIG_WEN_Ren (0UL) /*!< Read only access */
+#define NVMC_CONFIG_WEN_Wen (1UL) /*!< Write Enabled */
+#define NVMC_CONFIG_WEN_Een (2UL) /*!< Erase enabled */
+
+/* Register: NVMC_ERASEPAGE */
+/* Description: Register for erasing a page in Code area */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area */
+#define NVMC_ERASEPAGE_ERASEPAGE_Pos (0UL) /*!< Position of ERASEPAGE field. */
+#define NVMC_ERASEPAGE_ERASEPAGE_Msk (0xFFFFFFFFUL << NVMC_ERASEPAGE_ERASEPAGE_Pos) /*!< Bit mask of ERASEPAGE field. */
+
+/* Register: NVMC_ERASEPCR1 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Pos (0UL) /*!< Position of ERASEPCR1 field. */
+#define NVMC_ERASEPCR1_ERASEPCR1_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR1_ERASEPCR1_Pos) /*!< Bit mask of ERASEPCR1 field. */
+
+/* Register: NVMC_ERASEALL */
+/* Description: Register for erasing all non-volatile user memory */
+
+/* Bit 0 : Erase all non-volatile memory including UICR registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
+#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
+#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase */
+
+/* Register: NVMC_ERASEPCR0 */
+/* Description: Deprecated register -  Register for erasing a page in Code area. Equivalent to ERASEPAGE. */
+
+/* Bits 31..0 : Register for starting erase of a page in Code area. Equivalent to ERASEPAGE. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Pos (0UL) /*!< Position of ERASEPCR0 field. */
+#define NVMC_ERASEPCR0_ERASEPCR0_Msk (0xFFFFFFFFUL << NVMC_ERASEPCR0_ERASEPCR0_Pos) /*!< Bit mask of ERASEPCR0 field. */
+
+/* Register: NVMC_ERASEUICR */
+/* Description: Register for erasing User Information Configuration Registers */
+
+/* Bit 0 : Register starting erase of all User Information Configuration Registers. Note that code erase has to be enabled by CONFIG.EEN before the UICR can be erased. */
+#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
+#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation */
+#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start erase of UICR */
+
+/* Register: NVMC_ICACHECNF */
+/* Description: I-Code cache configuration register. */
+
+/* Bit 8 : Cache profiling enable */
+#define NVMC_ICACHECNF_CACHEPROFEN_Pos (8UL) /*!< Position of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEPROFEN_Pos) /*!< Bit mask of CACHEPROFEN field. */
+#define NVMC_ICACHECNF_CACHEPROFEN_Disabled (0UL) /*!< Disable cache profiling */
+#define NVMC_ICACHECNF_CACHEPROFEN_Enabled (1UL) /*!< Enable cache profiling */
+
+/* Bit 0 : Cache enable */
+#define NVMC_ICACHECNF_CACHEEN_Pos (0UL) /*!< Position of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Msk (0x1UL << NVMC_ICACHECNF_CACHEEN_Pos) /*!< Bit mask of CACHEEN field. */
+#define NVMC_ICACHECNF_CACHEEN_Disabled (0UL) /*!< Disable cache. Invalidates all cache entries. */
+#define NVMC_ICACHECNF_CACHEEN_Enabled (1UL) /*!< Enable cache */
+
+/* Register: NVMC_IHIT */
+/* Description: I-Code cache hit counter. */
+
+/* Bits 31..0 : Number of cache hits */
+#define NVMC_IHIT_HITS_Pos (0UL) /*!< Position of HITS field. */
+#define NVMC_IHIT_HITS_Msk (0xFFFFFFFFUL << NVMC_IHIT_HITS_Pos) /*!< Bit mask of HITS field. */
+
+/* Register: NVMC_IMISS */
+/* Description: I-Code cache miss counter. */
+
+/* Bits 31..0 : Number of cache misses */
+#define NVMC_IMISS_MISSES_Pos (0UL) /*!< Position of MISSES field. */
+#define NVMC_IMISS_MISSES_Msk (0xFFFFFFFFUL << NVMC_IMISS_MISSES_Pos) /*!< Bit mask of MISSES field. */
+
+
+/* Peripheral: GPIO */
+/* Description: GPIO Port 1 */
+
+/* Register: GPIO_OUT */
+/* Description: Write GPIO port */
+
+/* Bit 31 : P0.31 pin */
+#define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high */
+
+/* Bit 30 : P0.30 pin */
+#define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high */
+
+/* Bit 29 : P0.29 pin */
+#define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high */
+
+/* Bit 28 : P0.28 pin */
+#define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high */
+
+/* Bit 27 : P0.27 pin */
+#define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high */
+
+/* Bit 26 : P0.26 pin */
+#define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high */
+
+/* Bit 25 : P0.25 pin */
+#define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high */
+
+/* Bit 24 : P0.24 pin */
+#define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high */
+
+/* Bit 23 : P0.23 pin */
+#define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high */
+
+/* Bit 22 : P0.22 pin */
+#define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high */
+
+/* Bit 21 : P0.21 pin */
+#define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high */
+
+/* Bit 20 : P0.20 pin */
+#define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high */
+
+/* Bit 19 : P0.19 pin */
+#define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high */
+
+/* Bit 18 : P0.18 pin */
+#define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high */
+
+/* Bit 17 : P0.17 pin */
+#define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high */
+
+/* Bit 16 : P0.16 pin */
+#define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high */
+
+/* Bit 15 : P0.15 pin */
+#define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high */
+
+/* Bit 14 : P0.14 pin */
+#define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high */
+
+/* Bit 13 : P0.13 pin */
+#define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high */
+
+/* Bit 12 : P0.12 pin */
+#define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high */
+
+/* Bit 11 : P0.11 pin */
+#define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high */
+
+/* Bit 10 : P0.10 pin */
+#define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high */
+
+/* Bit 9 : P0.9 pin */
+#define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high */
+
+/* Bit 8 : P0.8 pin */
+#define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high */
+
+/* Bit 7 : P0.7 pin */
+#define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high */
+
+/* Bit 6 : P0.6 pin */
+#define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high */
+
+/* Bit 5 : P0.5 pin */
+#define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high */
+
+/* Bit 4 : P0.4 pin */
+#define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high */
+
+/* Bit 3 : P0.3 pin */
+#define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high */
+
+/* Bit 2 : P0.2 pin */
+#define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high */
+
+/* Bit 1 : P0.1 pin */
+#define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high */
+
+/* Bit 0 : P0.0 pin */
+#define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low */
+#define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high */
+
+/* Register: GPIO_OUTSET */
+/* Description: Set individual bits in GPIO port */
+
+/* Bit 31 : P0.31 pin */
+#define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTSET_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 30 : P0.30 pin */
+#define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTSET_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 29 : P0.29 pin */
+#define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTSET_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 28 : P0.28 pin */
+#define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTSET_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 27 : P0.27 pin */
+#define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTSET_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 26 : P0.26 pin */
+#define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTSET_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 25 : P0.25 pin */
+#define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTSET_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 24 : P0.24 pin */
+#define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTSET_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 23 : P0.23 pin */
+#define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTSET_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 22 : P0.22 pin */
+#define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTSET_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 21 : P0.21 pin */
+#define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTSET_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 20 : P0.20 pin */
+#define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTSET_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 19 : P0.19 pin */
+#define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTSET_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 18 : P0.18 pin */
+#define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTSET_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 17 : P0.17 pin */
+#define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTSET_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 16 : P0.16 pin */
+#define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTSET_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 15 : P0.15 pin */
+#define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTSET_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 14 : P0.14 pin */
+#define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTSET_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 13 : P0.13 pin */
+#define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTSET_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 12 : P0.12 pin */
+#define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTSET_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 11 : P0.11 pin */
+#define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTSET_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 10 : P0.10 pin */
+#define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTSET_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 9 : P0.9 pin */
+#define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTSET_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 8 : P0.8 pin */
+#define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTSET_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 7 : P0.7 pin */
+#define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTSET_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 6 : P0.6 pin */
+#define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTSET_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 5 : P0.5 pin */
+#define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTSET_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 4 : P0.4 pin */
+#define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTSET_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 3 : P0.3 pin */
+#define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTSET_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 2 : P0.2 pin */
+#define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTSET_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 1 : P0.1 pin */
+#define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTSET_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Bit 0 : P0.0 pin */
+#define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTSET_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTSET_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets the pin high; writing a '0' has no effect */
+
+/* Register: GPIO_OUTCLR */
+/* Description: Clear individual bits in GPIO port */
+
+/* Bit 31 : P0.31 pin */
+#define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN31_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 30 : P0.30 pin */
+#define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN30_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 29 : P0.29 pin */
+#define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN29_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 28 : P0.28 pin */
+#define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN28_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 27 : P0.27 pin */
+#define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN27_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 26 : P0.26 pin */
+#define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN26_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 25 : P0.25 pin */
+#define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN25_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 24 : P0.24 pin */
+#define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN24_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 23 : P0.23 pin */
+#define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN23_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 22 : P0.22 pin */
+#define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN22_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 21 : P0.21 pin */
+#define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN21_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 20 : P0.20 pin */
+#define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN20_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 19 : P0.19 pin */
+#define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN19_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 18 : P0.18 pin */
+#define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN18_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 17 : P0.17 pin */
+#define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN17_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 16 : P0.16 pin */
+#define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN16_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 15 : P0.15 pin */
+#define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN15_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 14 : P0.14 pin */
+#define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN14_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 13 : P0.13 pin */
+#define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN13_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 12 : P0.12 pin */
+#define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN12_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 11 : P0.11 pin */
+#define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN11_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 10 : P0.10 pin */
+#define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN10_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 9 : P0.9 pin */
+#define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN9_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 8 : P0.8 pin */
+#define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN8_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 7 : P0.7 pin */
+#define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN7_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 6 : P0.6 pin */
+#define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN6_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 5 : P0.5 pin */
+#define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN5_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 4 : P0.4 pin */
+#define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN4_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 3 : P0.3 pin */
+#define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN3_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 2 : P0.2 pin */
+#define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN2_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 1 : P0.1 pin */
+#define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN1_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Bit 0 : P0.0 pin */
+#define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Read: pin driver is low */
+#define GPIO_OUTCLR_PIN0_High (1UL) /*!< Read: pin driver is high */
+#define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets the pin low; writing a '0' has no effect */
+
+/* Register: GPIO_IN */
+/* Description: Read GPIO port */
+
+/* Bit 31 : P0.31 pin */
+#define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high */
+
+/* Bit 30 : P0.30 pin */
+#define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high */
+
+/* Bit 29 : P0.29 pin */
+#define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high */
+
+/* Bit 28 : P0.28 pin */
+#define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high */
+
+/* Bit 27 : P0.27 pin */
+#define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high */
+
+/* Bit 26 : P0.26 pin */
+#define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high */
+
+/* Bit 25 : P0.25 pin */
+#define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high */
+
+/* Bit 24 : P0.24 pin */
+#define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high */
+
+/* Bit 23 : P0.23 pin */
+#define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high */
+
+/* Bit 22 : P0.22 pin */
+#define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high */
+
+/* Bit 21 : P0.21 pin */
+#define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high */
+
+/* Bit 20 : P0.20 pin */
+#define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high */
+
+/* Bit 19 : P0.19 pin */
+#define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high */
+
+/* Bit 18 : P0.18 pin */
+#define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high */
+
+/* Bit 17 : P0.17 pin */
+#define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high */
+
+/* Bit 16 : P0.16 pin */
+#define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high */
+
+/* Bit 15 : P0.15 pin */
+#define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high */
+
+/* Bit 14 : P0.14 pin */
+#define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high */
+
+/* Bit 13 : P0.13 pin */
+#define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high */
+
+/* Bit 12 : P0.12 pin */
+#define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high */
+
+/* Bit 11 : P0.11 pin */
+#define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high */
+
+/* Bit 10 : P0.10 pin */
+#define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high */
+
+/* Bit 9 : P0.9 pin */
+#define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high */
+
+/* Bit 8 : P0.8 pin */
+#define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high */
+
+/* Bit 7 : P0.7 pin */
+#define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high */
+
+/* Bit 6 : P0.6 pin */
+#define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high */
+
+/* Bit 5 : P0.5 pin */
+#define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high */
+
+/* Bit 4 : P0.4 pin */
+#define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high */
+
+/* Bit 3 : P0.3 pin */
+#define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high */
+
+/* Bit 2 : P0.2 pin */
+#define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high */
+
+/* Bit 1 : P0.1 pin */
+#define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high */
+
+/* Bit 0 : P0.0 pin */
+#define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low */
+#define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high */
+
+/* Register: GPIO_DIR */
+/* Description: Direction of GPIO pins */
+
+/* Bit 31 : P0.31 pin */
+#define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output */
+
+/* Bit 30 : P0.30 pin */
+#define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output */
+
+/* Bit 29 : P0.29 pin */
+#define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output */
+
+/* Bit 28 : P0.28 pin */
+#define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output */
+
+/* Bit 27 : P0.27 pin */
+#define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output */
+
+/* Bit 26 : P0.26 pin */
+#define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output */
+
+/* Bit 25 : P0.25 pin */
+#define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output */
+
+/* Bit 24 : P0.24 pin */
+#define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output */
+
+/* Bit 23 : P0.23 pin */
+#define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output */
+
+/* Bit 22 : P0.22 pin */
+#define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output */
+
+/* Bit 21 : P0.21 pin */
+#define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output */
+
+/* Bit 20 : P0.20 pin */
+#define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output */
+
+/* Bit 19 : P0.19 pin */
+#define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output */
+
+/* Bit 18 : P0.18 pin */
+#define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output */
+
+/* Bit 17 : P0.17 pin */
+#define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output */
+
+/* Bit 16 : P0.16 pin */
+#define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output */
+
+/* Bit 15 : P0.15 pin */
+#define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output */
+
+/* Bit 14 : P0.14 pin */
+#define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output */
+
+/* Bit 13 : P0.13 pin */
+#define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output */
+
+/* Bit 12 : P0.12 pin */
+#define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output */
+
+/* Bit 11 : P0.11 pin */
+#define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output */
+
+/* Bit 10 : P0.10 pin */
+#define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output */
+
+/* Bit 9 : P0.9 pin */
+#define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output */
+
+/* Bit 8 : P0.8 pin */
+#define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output */
+
+/* Bit 7 : P0.7 pin */
+#define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output */
+
+/* Bit 6 : P0.6 pin */
+#define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output */
+
+/* Bit 5 : P0.5 pin */
+#define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output */
+
+/* Bit 4 : P0.4 pin */
+#define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output */
+
+/* Bit 3 : P0.3 pin */
+#define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output */
+
+/* Bit 2 : P0.2 pin */
+#define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output */
+
+/* Bit 1 : P0.1 pin */
+#define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output */
+
+/* Bit 0 : P0.0 pin */
+#define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input */
+#define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output */
+
+/* Register: GPIO_DIRSET */
+/* Description: DIR set register */
+
+/* Bit 31 : Set as output pin 31 */
+#define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRSET_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN31_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 30 : Set as output pin 30 */
+#define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRSET_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN30_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 29 : Set as output pin 29 */
+#define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRSET_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN29_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 28 : Set as output pin 28 */
+#define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRSET_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN28_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 27 : Set as output pin 27 */
+#define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRSET_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN27_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 26 : Set as output pin 26 */
+#define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRSET_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN26_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 25 : Set as output pin 25 */
+#define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRSET_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN25_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 24 : Set as output pin 24 */
+#define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRSET_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN24_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 23 : Set as output pin 23 */
+#define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRSET_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN23_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 22 : Set as output pin 22 */
+#define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRSET_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN22_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 21 : Set as output pin 21 */
+#define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRSET_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN21_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 20 : Set as output pin 20 */
+#define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRSET_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN20_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 19 : Set as output pin 19 */
+#define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRSET_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN19_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 18 : Set as output pin 18 */
+#define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRSET_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN18_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 17 : Set as output pin 17 */
+#define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRSET_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN17_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 16 : Set as output pin 16 */
+#define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRSET_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN16_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 15 : Set as output pin 15 */
+#define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRSET_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN15_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 14 : Set as output pin 14 */
+#define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRSET_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN14_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 13 : Set as output pin 13 */
+#define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRSET_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN13_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 12 : Set as output pin 12 */
+#define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRSET_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN12_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 11 : Set as output pin 11 */
+#define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRSET_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN11_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 10 : Set as output pin 10 */
+#define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRSET_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN10_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 9 : Set as output pin 9 */
+#define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRSET_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN9_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 8 : Set as output pin 8 */
+#define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRSET_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN8_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 7 : Set as output pin 7 */
+#define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRSET_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN7_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 6 : Set as output pin 6 */
+#define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRSET_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN6_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 5 : Set as output pin 5 */
+#define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRSET_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN5_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 4 : Set as output pin 4 */
+#define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRSET_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN4_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 3 : Set as output pin 3 */
+#define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRSET_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN3_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 2 : Set as output pin 2 */
+#define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRSET_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN2_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 1 : Set as output pin 1 */
+#define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRSET_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN1_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Bit 0 : Set as output pin 0 */
+#define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRSET_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRSET_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRSET_PIN0_Set (1UL) /*!< Write: writing a '1' sets pin to output; writing a '0' has no effect */
+
+/* Register: GPIO_DIRCLR */
+/* Description: DIR clear register */
+
+/* Bit 31 : Set as input pin 31 */
+#define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 30 : Set as input pin 30 */
+#define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 29 : Set as input pin 29 */
+#define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 28 : Set as input pin 28 */
+#define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 27 : Set as input pin 27 */
+#define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 26 : Set as input pin 26 */
+#define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 25 : Set as input pin 25 */
+#define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 24 : Set as input pin 24 */
+#define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 23 : Set as input pin 23 */
+#define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 22 : Set as input pin 22 */
+#define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 21 : Set as input pin 21 */
+#define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 20 : Set as input pin 20 */
+#define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 19 : Set as input pin 19 */
+#define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 18 : Set as input pin 18 */
+#define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 17 : Set as input pin 17 */
+#define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 16 : Set as input pin 16 */
+#define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 15 : Set as input pin 15 */
+#define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 14 : Set as input pin 14 */
+#define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 13 : Set as input pin 13 */
+#define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 12 : Set as input pin 12 */
+#define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 11 : Set as input pin 11 */
+#define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 10 : Set as input pin 10 */
+#define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 9 : Set as input pin 9 */
+#define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 8 : Set as input pin 8 */
+#define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 7 : Set as input pin 7 */
+#define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 6 : Set as input pin 6 */
+#define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 5 : Set as input pin 5 */
+#define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 4 : Set as input pin 4 */
+#define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 3 : Set as input pin 3 */
+#define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 2 : Set as input pin 2 */
+#define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 1 : Set as input pin 1 */
+#define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Bit 0 : Set as input pin 0 */
+#define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Read: pin set as input */
+#define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Read: pin set as output */
+#define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Write: writing a '1' sets pin to input; writing a '0' has no effect */
+
+/* Register: GPIO_LATCH */
+/* Description: Latch register indicating what GPIO pins that have met the criteria set in the PIN_CNF[n].SENSE registers */
+
+/* Bit 31 : Status on whether PIN31 has met criteria set in PIN_CNF31.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
+#define GPIO_LATCH_PIN31_Msk (0x1UL << GPIO_LATCH_PIN31_Pos) /*!< Bit mask of PIN31 field. */
+#define GPIO_LATCH_PIN31_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN31_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 30 : Status on whether PIN30 has met criteria set in PIN_CNF30.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
+#define GPIO_LATCH_PIN30_Msk (0x1UL << GPIO_LATCH_PIN30_Pos) /*!< Bit mask of PIN30 field. */
+#define GPIO_LATCH_PIN30_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN30_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 29 : Status on whether PIN29 has met criteria set in PIN_CNF29.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
+#define GPIO_LATCH_PIN29_Msk (0x1UL << GPIO_LATCH_PIN29_Pos) /*!< Bit mask of PIN29 field. */
+#define GPIO_LATCH_PIN29_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN29_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 28 : Status on whether PIN28 has met criteria set in PIN_CNF28.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
+#define GPIO_LATCH_PIN28_Msk (0x1UL << GPIO_LATCH_PIN28_Pos) /*!< Bit mask of PIN28 field. */
+#define GPIO_LATCH_PIN28_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN28_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 27 : Status on whether PIN27 has met criteria set in PIN_CNF27.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
+#define GPIO_LATCH_PIN27_Msk (0x1UL << GPIO_LATCH_PIN27_Pos) /*!< Bit mask of PIN27 field. */
+#define GPIO_LATCH_PIN27_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN27_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 26 : Status on whether PIN26 has met criteria set in PIN_CNF26.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
+#define GPIO_LATCH_PIN26_Msk (0x1UL << GPIO_LATCH_PIN26_Pos) /*!< Bit mask of PIN26 field. */
+#define GPIO_LATCH_PIN26_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN26_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 25 : Status on whether PIN25 has met criteria set in PIN_CNF25.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
+#define GPIO_LATCH_PIN25_Msk (0x1UL << GPIO_LATCH_PIN25_Pos) /*!< Bit mask of PIN25 field. */
+#define GPIO_LATCH_PIN25_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN25_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 24 : Status on whether PIN24 has met criteria set in PIN_CNF24.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
+#define GPIO_LATCH_PIN24_Msk (0x1UL << GPIO_LATCH_PIN24_Pos) /*!< Bit mask of PIN24 field. */
+#define GPIO_LATCH_PIN24_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN24_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 23 : Status on whether PIN23 has met criteria set in PIN_CNF23.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
+#define GPIO_LATCH_PIN23_Msk (0x1UL << GPIO_LATCH_PIN23_Pos) /*!< Bit mask of PIN23 field. */
+#define GPIO_LATCH_PIN23_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN23_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 22 : Status on whether PIN22 has met criteria set in PIN_CNF22.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
+#define GPIO_LATCH_PIN22_Msk (0x1UL << GPIO_LATCH_PIN22_Pos) /*!< Bit mask of PIN22 field. */
+#define GPIO_LATCH_PIN22_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN22_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 21 : Status on whether PIN21 has met criteria set in PIN_CNF21.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
+#define GPIO_LATCH_PIN21_Msk (0x1UL << GPIO_LATCH_PIN21_Pos) /*!< Bit mask of PIN21 field. */
+#define GPIO_LATCH_PIN21_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN21_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 20 : Status on whether PIN20 has met criteria set in PIN_CNF20.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
+#define GPIO_LATCH_PIN20_Msk (0x1UL << GPIO_LATCH_PIN20_Pos) /*!< Bit mask of PIN20 field. */
+#define GPIO_LATCH_PIN20_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN20_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 19 : Status on whether PIN19 has met criteria set in PIN_CNF19.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
+#define GPIO_LATCH_PIN19_Msk (0x1UL << GPIO_LATCH_PIN19_Pos) /*!< Bit mask of PIN19 field. */
+#define GPIO_LATCH_PIN19_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN19_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 18 : Status on whether PIN18 has met criteria set in PIN_CNF18.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
+#define GPIO_LATCH_PIN18_Msk (0x1UL << GPIO_LATCH_PIN18_Pos) /*!< Bit mask of PIN18 field. */
+#define GPIO_LATCH_PIN18_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN18_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 17 : Status on whether PIN17 has met criteria set in PIN_CNF17.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
+#define GPIO_LATCH_PIN17_Msk (0x1UL << GPIO_LATCH_PIN17_Pos) /*!< Bit mask of PIN17 field. */
+#define GPIO_LATCH_PIN17_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN17_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 16 : Status on whether PIN16 has met criteria set in PIN_CNF16.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
+#define GPIO_LATCH_PIN16_Msk (0x1UL << GPIO_LATCH_PIN16_Pos) /*!< Bit mask of PIN16 field. */
+#define GPIO_LATCH_PIN16_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN16_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 15 : Status on whether PIN15 has met criteria set in PIN_CNF15.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
+#define GPIO_LATCH_PIN15_Msk (0x1UL << GPIO_LATCH_PIN15_Pos) /*!< Bit mask of PIN15 field. */
+#define GPIO_LATCH_PIN15_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN15_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 14 : Status on whether PIN14 has met criteria set in PIN_CNF14.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
+#define GPIO_LATCH_PIN14_Msk (0x1UL << GPIO_LATCH_PIN14_Pos) /*!< Bit mask of PIN14 field. */
+#define GPIO_LATCH_PIN14_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN14_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 13 : Status on whether PIN13 has met criteria set in PIN_CNF13.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
+#define GPIO_LATCH_PIN13_Msk (0x1UL << GPIO_LATCH_PIN13_Pos) /*!< Bit mask of PIN13 field. */
+#define GPIO_LATCH_PIN13_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN13_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 12 : Status on whether PIN12 has met criteria set in PIN_CNF12.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
+#define GPIO_LATCH_PIN12_Msk (0x1UL << GPIO_LATCH_PIN12_Pos) /*!< Bit mask of PIN12 field. */
+#define GPIO_LATCH_PIN12_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN12_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 11 : Status on whether PIN11 has met criteria set in PIN_CNF11.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
+#define GPIO_LATCH_PIN11_Msk (0x1UL << GPIO_LATCH_PIN11_Pos) /*!< Bit mask of PIN11 field. */
+#define GPIO_LATCH_PIN11_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN11_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 10 : Status on whether PIN10 has met criteria set in PIN_CNF10.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
+#define GPIO_LATCH_PIN10_Msk (0x1UL << GPIO_LATCH_PIN10_Pos) /*!< Bit mask of PIN10 field. */
+#define GPIO_LATCH_PIN10_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN10_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 9 : Status on whether PIN9 has met criteria set in PIN_CNF9.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
+#define GPIO_LATCH_PIN9_Msk (0x1UL << GPIO_LATCH_PIN9_Pos) /*!< Bit mask of PIN9 field. */
+#define GPIO_LATCH_PIN9_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN9_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 8 : Status on whether PIN8 has met criteria set in PIN_CNF8.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
+#define GPIO_LATCH_PIN8_Msk (0x1UL << GPIO_LATCH_PIN8_Pos) /*!< Bit mask of PIN8 field. */
+#define GPIO_LATCH_PIN8_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN8_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 7 : Status on whether PIN7 has met criteria set in PIN_CNF7.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
+#define GPIO_LATCH_PIN7_Msk (0x1UL << GPIO_LATCH_PIN7_Pos) /*!< Bit mask of PIN7 field. */
+#define GPIO_LATCH_PIN7_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN7_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 6 : Status on whether PIN6 has met criteria set in PIN_CNF6.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
+#define GPIO_LATCH_PIN6_Msk (0x1UL << GPIO_LATCH_PIN6_Pos) /*!< Bit mask of PIN6 field. */
+#define GPIO_LATCH_PIN6_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN6_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 5 : Status on whether PIN5 has met criteria set in PIN_CNF5.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
+#define GPIO_LATCH_PIN5_Msk (0x1UL << GPIO_LATCH_PIN5_Pos) /*!< Bit mask of PIN5 field. */
+#define GPIO_LATCH_PIN5_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN5_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 4 : Status on whether PIN4 has met criteria set in PIN_CNF4.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
+#define GPIO_LATCH_PIN4_Msk (0x1UL << GPIO_LATCH_PIN4_Pos) /*!< Bit mask of PIN4 field. */
+#define GPIO_LATCH_PIN4_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN4_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 3 : Status on whether PIN3 has met criteria set in PIN_CNF3.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
+#define GPIO_LATCH_PIN3_Msk (0x1UL << GPIO_LATCH_PIN3_Pos) /*!< Bit mask of PIN3 field. */
+#define GPIO_LATCH_PIN3_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN3_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 2 : Status on whether PIN2 has met criteria set in PIN_CNF2.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
+#define GPIO_LATCH_PIN2_Msk (0x1UL << GPIO_LATCH_PIN2_Pos) /*!< Bit mask of PIN2 field. */
+#define GPIO_LATCH_PIN2_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN2_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 1 : Status on whether PIN1 has met criteria set in PIN_CNF1.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
+#define GPIO_LATCH_PIN1_Msk (0x1UL << GPIO_LATCH_PIN1_Pos) /*!< Bit mask of PIN1 field. */
+#define GPIO_LATCH_PIN1_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN1_Latched (1UL) /*!< Criteria has been met */
+
+/* Bit 0 : Status on whether PIN0 has met criteria set in PIN_CNF0.SENSE register. Write '1' to clear. */
+#define GPIO_LATCH_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
+#define GPIO_LATCH_PIN0_Msk (0x1UL << GPIO_LATCH_PIN0_Pos) /*!< Bit mask of PIN0 field. */
+#define GPIO_LATCH_PIN0_NotLatched (0UL) /*!< Criteria has not been met */
+#define GPIO_LATCH_PIN0_Latched (1UL) /*!< Criteria has been met */
+
+/* Register: GPIO_DETECTMODE */
+/* Description: Select between default DETECT signal behaviour and LDETECT mode */
+
+/* Bit 0 : Select between default DETECT signal behaviour and LDETECT mode */
+#define GPIO_DETECTMODE_DETECTMODE_Pos (0UL) /*!< Position of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Msk (0x1UL << GPIO_DETECTMODE_DETECTMODE_Pos) /*!< Bit mask of DETECTMODE field. */
+#define GPIO_DETECTMODE_DETECTMODE_Default (0UL) /*!< DETECT directly connected to PIN DETECT signals */
+#define GPIO_DETECTMODE_DETECTMODE_LDETECT (1UL) /*!< Use the latched LDETECT behaviour */
+
+/* Register: GPIO_PIN_CNF */
+/* Description: Description collection[0]:  Configuration of GPIO pins */
+
+/* Bits 17..16 : Pin sensing mechanism */
+#define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
+#define GPIO_PIN_CNF_SENSE_Disabled (0UL) /*!< Disabled */
+#define GPIO_PIN_CNF_SENSE_High (2UL) /*!< Sense for high level */
+#define GPIO_PIN_CNF_SENSE_Low (3UL) /*!< Sense for low level */
+
+/* Bits 10..8 : Drive configuration */
+#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
+#define GPIO_PIN_CNF_DRIVE_S0S1 (0UL) /*!< Standard '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_H0S1 (1UL) /*!< High drive '0', standard '1' */
+#define GPIO_PIN_CNF_DRIVE_S0H1 (2UL) /*!< Standard '0', high drive '1' */
+#define GPIO_PIN_CNF_DRIVE_H0H1 (3UL) /*!< High drive '0', high 'drive '1'' */
+#define GPIO_PIN_CNF_DRIVE_D0S1 (4UL) /*!< Disconnect '0' standard '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_D0H1 (5UL) /*!< Disconnect '0', high drive '1' (normally used for wired-or connections) */
+#define GPIO_PIN_CNF_DRIVE_S0D1 (6UL) /*!< Standard '0'. disconnect '1' (normally used for wired-and connections) */
+#define GPIO_PIN_CNF_DRIVE_H0D1 (7UL) /*!< High drive '0', disconnect '1' (normally used for wired-and connections) */
+
+/* Bits 3..2 : Pull configuration */
+#define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
+#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
+#define GPIO_PIN_CNF_PULL_Disabled (0UL) /*!< No pull */
+#define GPIO_PIN_CNF_PULL_Pulldown (1UL) /*!< Pull down on pin */
+#define GPIO_PIN_CNF_PULL_Pullup (3UL) /*!< Pull up on pin */
+
+/* Bit 1 : Connect or disconnect input buffer */
+#define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
+#define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input buffer */
+#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input buffer */
+
+/* Bit 0 : Pin direction. Same physical register as DIR register */
+#define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
+#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
+#define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin */
+#define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin */
+
+
+/* Peripheral: PDM */
+/* Description: Pulse Density Modulation (Digital Microphone) Interface */
+
+/* Register: PDM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 2 : Enable or disable interrupt for END event */
+#define PDM_INTEN_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTEN_END_Msk (0x1UL << PDM_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTEN_END_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PDM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTEN_STOPPED_Msk (0x1UL << PDM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define PDM_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTEN_STARTED_Msk (0x1UL << PDM_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define PDM_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for END event */
+#define PDM_INTENSET_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENSET_END_Msk (0x1UL << PDM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PDM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Msk (0x1UL << PDM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define PDM_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENSET_STARTED_Msk (0x1UL << PDM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: PDM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for END event */
+#define PDM_INTENCLR_END_Pos (2UL) /*!< Position of END field. */
+#define PDM_INTENCLR_END_Msk (0x1UL << PDM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define PDM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PDM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Msk (0x1UL << PDM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PDM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define PDM_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define PDM_INTENCLR_STARTED_Msk (0x1UL << PDM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define PDM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define PDM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define PDM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: PDM_ENABLE */
+/* Description: PDM module enable register */
+
+/* Bit 0 : Enable or disable PDM module */
+#define PDM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Msk (0x1UL << PDM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PDM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define PDM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PDM_PDMCLKCTRL */
+/* Description: PDM clock generator control */
+
+/* Bits 31..0 : PDM_CLK frequency */
+#define PDM_PDMCLKCTRL_FREQ_Pos (0UL) /*!< Position of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_Msk (0xFFFFFFFFUL << PDM_PDMCLKCTRL_FREQ_Pos) /*!< Bit mask of FREQ field. */
+#define PDM_PDMCLKCTRL_FREQ_1000K (0x08000000UL) /*!< PDM_CLK = 32 MHz / 32 = 1.000 MHz */
+#define PDM_PDMCLKCTRL_FREQ_Default (0x08400000UL) /*!< PDM_CLK = 32 MHz / 31 = 1.032 MHz */
+#define PDM_PDMCLKCTRL_FREQ_1067K (0x08800000UL) /*!< PDM_CLK = 32 MHz / 30 = 1.067 MHz */
+
+/* Register: PDM_MODE */
+/* Description: Defines the routing of the connected PDM microphones' signals */
+
+/* Bit 1 : Defines on which PDM_CLK edge Left (or mono) is sampled */
+#define PDM_MODE_EDGE_Pos (1UL) /*!< Position of EDGE field. */
+#define PDM_MODE_EDGE_Msk (0x1UL << PDM_MODE_EDGE_Pos) /*!< Bit mask of EDGE field. */
+#define PDM_MODE_EDGE_LeftFalling (0UL) /*!< Left (or mono) is sampled on falling edge of PDM_CLK */
+#define PDM_MODE_EDGE_LeftRising (1UL) /*!< Left (or mono) is sampled on rising edge of PDM_CLK */
+
+/* Bit 0 : Mono or stereo operation */
+#define PDM_MODE_OPERATION_Pos (0UL) /*!< Position of OPERATION field. */
+#define PDM_MODE_OPERATION_Msk (0x1UL << PDM_MODE_OPERATION_Pos) /*!< Bit mask of OPERATION field. */
+#define PDM_MODE_OPERATION_Stereo (0UL) /*!< Sample and store one pair (Left + Right) of 16bit samples per RAM word R=[31:16]; L=[15:0] */
+#define PDM_MODE_OPERATION_Mono (1UL) /*!< Sample and store two successive Left samples (16 bit each) per RAM word L1=[31:16]; L0=[15:0] */
+
+/* Register: PDM_GAINL */
+/* Description: Left output gain adjustment */
+
+/* Bits 6..0 : Left output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) 0x00    -20 dB gain adjust 0x01  -19.5 dB gain adjust (...) 0x27   -0.5 dB gain adjust 0x28      0 dB gain adjust 0x29   +0.5 dB gain adjust (...) 0x4F  +19.5 dB gain adjust 0x50    +20 dB gain adjust */
+#define PDM_GAINL_GAINL_Pos (0UL) /*!< Position of GAINL field. */
+#define PDM_GAINL_GAINL_Msk (0x7FUL << PDM_GAINL_GAINL_Pos) /*!< Bit mask of GAINL field. */
+#define PDM_GAINL_GAINL_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINL_GAINL_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINL_GAINL_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_GAINR */
+/* Description: Right output gain adjustment */
+
+/* Bits 7..0 : Right output gain adjustment, in 0.5 dB steps, around the default module gain (see electrical parameters) */
+#define PDM_GAINR_GAINR_Pos (0UL) /*!< Position of GAINR field. */
+#define PDM_GAINR_GAINR_Msk (0xFFUL << PDM_GAINR_GAINR_Pos) /*!< Bit mask of GAINR field. */
+#define PDM_GAINR_GAINR_MinGain (0x00UL) /*!< -20dB gain adjustment (minimum) */
+#define PDM_GAINR_GAINR_DefaultGain (0x28UL) /*!< 0dB gain adjustment ('2500 RMS' requirement) */
+#define PDM_GAINR_GAINR_MaxGain (0x50UL) /*!< +20dB gain adjustment (maximum) */
+
+/* Register: PDM_PSEL_CLK */
+/* Description: Pin number configuration for PDM CLK signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_CLK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Msk (0x1UL << PDM_PSEL_CLK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_CLK_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_CLK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_CLK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_CLK_PIN_Msk (0x1FUL << PDM_PSEL_CLK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_PSEL_DIN */
+/* Description: Pin number configuration for PDM DIN signal */
+
+/* Bit 31 : Connection */
+#define PDM_PSEL_DIN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Msk (0x1UL << PDM_PSEL_DIN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PDM_PSEL_DIN_CONNECT_Connected (0UL) /*!< Connect */
+#define PDM_PSEL_DIN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PDM_PSEL_DIN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PDM_PSEL_DIN_PIN_Msk (0x1FUL << PDM_PSEL_DIN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: PDM_SAMPLE_PTR */
+/* Description: RAM address pointer to write samples to with EasyDMA */
+
+/* Bits 31..0 : Address to write PDM samples to over DMA */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Pos (0UL) /*!< Position of SAMPLEPTR field. */
+#define PDM_SAMPLE_PTR_SAMPLEPTR_Msk (0xFFFFFFFFUL << PDM_SAMPLE_PTR_SAMPLEPTR_Pos) /*!< Bit mask of SAMPLEPTR field. */
+
+/* Register: PDM_SAMPLE_MAXCNT */
+/* Description: Number of samples to allocate memory for in EasyDMA mode */
+
+/* Bits 14..0 : Length of DMA RAM allocation in number of samples */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos (0UL) /*!< Position of BUFFSIZE field. */
+#define PDM_SAMPLE_MAXCNT_BUFFSIZE_Msk (0x7FFFUL << PDM_SAMPLE_MAXCNT_BUFFSIZE_Pos) /*!< Bit mask of BUFFSIZE field. */
+
+
+/* Peripheral: POWER */
+/* Description: Power control */
+
+/* Register: POWER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 6 : Write '1' to Enable interrupt for SLEEPEXIT event */
+#define POWER_INTENSET_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Msk (0x1UL << POWER_INTENSET_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENSET_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPEXIT_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SLEEPENTER event */
+#define POWER_INTENSET_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Msk (0x1UL << POWER_INTENSET_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENSET_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_SLEEPENTER_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for POFWARN event */
+#define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable */
+
+/* Register: POWER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 6 : Write '1' to Disable interrupt for SLEEPEXIT event */
+#define POWER_INTENCLR_SLEEPEXIT_Pos (6UL) /*!< Position of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Msk (0x1UL << POWER_INTENCLR_SLEEPEXIT_Pos) /*!< Bit mask of SLEEPEXIT field. */
+#define POWER_INTENCLR_SLEEPEXIT_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPEXIT_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPEXIT_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SLEEPENTER event */
+#define POWER_INTENCLR_SLEEPENTER_Pos (5UL) /*!< Position of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Msk (0x1UL << POWER_INTENCLR_SLEEPENTER_Pos) /*!< Bit mask of SLEEPENTER field. */
+#define POWER_INTENCLR_SLEEPENTER_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_SLEEPENTER_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_SLEEPENTER_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for POFWARN event */
+#define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
+#define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Read: Disabled */
+#define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Read: Enabled */
+#define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable */
+
+/* Register: POWER_RESETREAS */
+/* Description: Reset reason */
+
+/* Bit 19 : Reset due to wake up from System OFF mode by NFC field detect */
+#define POWER_RESETREAS_NFC_Pos (19UL) /*!< Position of NFC field. */
+#define POWER_RESETREAS_NFC_Msk (0x1UL << POWER_RESETREAS_NFC_Pos) /*!< Bit mask of NFC field. */
+#define POWER_RESETREAS_NFC_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_NFC_Detected (1UL) /*!< Detected */
+
+/* Bit 18 : Reset due to wake up from System OFF mode when wakeup is triggered from entering into debug interface mode */
+#define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
+#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
+#define POWER_RESETREAS_DIF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DIF_Detected (1UL) /*!< Detected */
+
+/* Bit 17 : Reset due to wake up from System OFF mode when wakeup is triggered from ANADETECT signal from LPCOMP */
+#define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
+#define POWER_RESETREAS_LPCOMP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LPCOMP_Detected (1UL) /*!< Detected */
+
+/* Bit 16 : Reset due to wake up from System OFF mode when wakeup is triggered from DETECT signal from GPIO */
+#define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
+#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
+#define POWER_RESETREAS_OFF_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_OFF_Detected (1UL) /*!< Detected */
+
+/* Bit 3 : Reset from CPU lock-up detected */
+#define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
+#define POWER_RESETREAS_LOCKUP_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_LOCKUP_Detected (1UL) /*!< Detected */
+
+/* Bit 2 : Reset from soft reset detected */
+#define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
+#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
+#define POWER_RESETREAS_SREQ_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_SREQ_Detected (1UL) /*!< Detected */
+
+/* Bit 1 : Reset from watchdog detected */
+#define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
+#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
+#define POWER_RESETREAS_DOG_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_DOG_Detected (1UL) /*!< Detected */
+
+/* Bit 0 : Reset from pin-reset detected */
+#define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
+#define POWER_RESETREAS_RESETPIN_NotDetected (0UL) /*!< Not detected */
+#define POWER_RESETREAS_RESETPIN_Detected (1UL) /*!< Detected */
+
+/* Register: POWER_RAMSTATUS */
+/* Description: Deprecated register -  RAM status register */
+
+/* Bit 3 : RAM block 3 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /*!< Position of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /*!< Bit mask of RAMBLOCK3 field. */
+#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /*!< On */
+
+/* Bit 2 : RAM block 2 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /*!< Position of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /*!< Bit mask of RAMBLOCK2 field. */
+#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /*!< On */
+
+/* Bit 1 : RAM block 1 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /*!< Position of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /*!< Bit mask of RAMBLOCK1 field. */
+#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /*!< On */
+
+/* Bit 0 : RAM block 0 is on or off/powering up */
+#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /*!< Position of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /*!< Bit mask of RAMBLOCK0 field. */
+#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /*!< Off */
+#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /*!< On */
+
+/* Register: POWER_SYSTEMOFF */
+/* Description: System OFF register */
+
+/* Bit 0 : Enable System OFF mode */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
+#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enable System OFF mode */
+
+/* Register: POWER_POFCON */
+/* Description: Power failure comparator configuration */
+
+/* Bits 4..1 : Power failure comparator threshold setting */
+#define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_Msk (0xFUL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
+#define POWER_POFCON_THRESHOLD_V17 (4UL) /*!< Set threshold to 1.7 V */
+#define POWER_POFCON_THRESHOLD_V18 (5UL) /*!< Set threshold to 1.8 V */
+#define POWER_POFCON_THRESHOLD_V19 (6UL) /*!< Set threshold to 1.9 V */
+#define POWER_POFCON_THRESHOLD_V20 (7UL) /*!< Set threshold to 2.0 V */
+#define POWER_POFCON_THRESHOLD_V21 (8UL) /*!< Set threshold to 2.1 V */
+#define POWER_POFCON_THRESHOLD_V22 (9UL) /*!< Set threshold to 2.2 V */
+#define POWER_POFCON_THRESHOLD_V23 (10UL) /*!< Set threshold to 2.3 V */
+#define POWER_POFCON_THRESHOLD_V24 (11UL) /*!< Set threshold to 2.4 V */
+#define POWER_POFCON_THRESHOLD_V25 (12UL) /*!< Set threshold to 2.5 V */
+#define POWER_POFCON_THRESHOLD_V26 (13UL) /*!< Set threshold to 2.6 V */
+#define POWER_POFCON_THRESHOLD_V27 (14UL) /*!< Set threshold to 2.7 V */
+#define POWER_POFCON_THRESHOLD_V28 (15UL) /*!< Set threshold to 2.8 V */
+
+/* Bit 0 : Enable or disable power failure comparator */
+#define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
+#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
+#define POWER_POFCON_POF_Disabled (0UL) /*!< Disable */
+#define POWER_POFCON_POF_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_GPREGRET */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_GPREGRET2 */
+/* Description: General purpose retention register */
+
+/* Bits 7..0 : General purpose retention register */
+#define POWER_GPREGRET2_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
+#define POWER_GPREGRET2_GPREGRET_Msk (0xFFUL << POWER_GPREGRET2_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
+
+/* Register: POWER_RAMON */
+/* Description: Deprecated register -  RAM on/off register (this register is retained) */
+
+/* Bit 17 : Keep retention on RAM block 1 when RAM block is switched off */
+#define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
+#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< Off */
+#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM block 0 when RAM block is switched off */
+#define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
+#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< Off */
+#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM block 1 on or off in system ON Mode */
+#define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
+#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< Off */
+#define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM block 0 on or off in system ON Mode */
+#define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
+#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< Off */
+#define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< On */
+
+/* Register: POWER_RAMONB */
+/* Description: Deprecated register -  RAM on/off register (this register is retained) */
+
+/* Bit 17 : Keep retention on RAM block 3 when RAM block is switched off */
+#define POWER_RAMONB_OFFRAM3_Pos (17UL) /*!< Position of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
+#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /*!< Off */
+#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM block 2 when RAM block is switched off */
+#define POWER_RAMONB_OFFRAM2_Pos (16UL) /*!< Position of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
+#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /*!< Off */
+#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM block 3 on or off in system ON Mode */
+#define POWER_RAMONB_ONRAM3_Pos (1UL) /*!< Position of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
+#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /*!< Off */
+#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM block 2 on or off in system ON Mode */
+#define POWER_RAMONB_ONRAM2_Pos (0UL) /*!< Position of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
+#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /*!< Off */
+#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /*!< On */
+
+/* Register: POWER_DCDCEN */
+/* Description: DC/DC enable register */
+
+/* Bit 0 : Enable or disable DC/DC converter */
+#define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
+#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< Disable */
+#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< Enable */
+
+/* Register: POWER_RAM_POWER */
+/* Description: Description cluster[0]:  RAM0 power control register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is in OFF */
+#define POWER_RAM_POWER_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Msk (0x1UL << POWER_RAM_POWER_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWER_S1RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is in OFF */
+#define POWER_RAM_POWER_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Msk (0x1UL << POWER_RAM_POWER_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWER_S0RETENTION_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Msk (0x1UL << POWER_RAM_POWER_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWER_S1POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 ON or OFF in System ON mode. */
+#define POWER_RAM_POWER_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Msk (0x1UL << POWER_RAM_POWER_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWER_S0POWER_Off (0UL) /*!< Off */
+#define POWER_RAM_POWER_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERSET */
+/* Description: Description cluster[0]:  RAM0 power control set register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERSET_S1RETENTION_On (1UL) /*!< On */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERSET_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERSET_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERSET_S0RETENTION_On (1UL) /*!< On */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_Msk (0x1UL << POWER_RAM_POWERSET_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERSET_S1POWER_On (1UL) /*!< On */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERSET_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_Msk (0x1UL << POWER_RAM_POWERSET_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERSET_S0POWER_On (1UL) /*!< On */
+
+/* Register: POWER_RAM_POWERCLR */
+/* Description: Description cluster[0]:  RAM0 power control clear register */
+
+/* Bit 17 : Keep retention on RAM section S1 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S1RETENTION_Pos (17UL) /*!< Position of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S1RETENTION_Pos) /*!< Bit mask of S1RETENTION field. */
+#define POWER_RAM_POWERCLR_S1RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 16 : Keep retention on RAM section S0 when RAM section is switched off */
+#define POWER_RAM_POWERCLR_S0RETENTION_Pos (16UL) /*!< Position of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Msk (0x1UL << POWER_RAM_POWERCLR_S0RETENTION_Pos) /*!< Bit mask of S0RETENTION field. */
+#define POWER_RAM_POWERCLR_S0RETENTION_Off (1UL) /*!< Off */
+
+/* Bit 1 : Keep RAM section S1 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S1POWER_Pos (1UL) /*!< Position of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S1POWER_Pos) /*!< Bit mask of S1POWER field. */
+#define POWER_RAM_POWERCLR_S1POWER_Off (1UL) /*!< Off */
+
+/* Bit 0 : Keep RAM section S0 of RAM0 on or off in System ON mode */
+#define POWER_RAM_POWERCLR_S0POWER_Pos (0UL) /*!< Position of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Msk (0x1UL << POWER_RAM_POWERCLR_S0POWER_Pos) /*!< Bit mask of S0POWER field. */
+#define POWER_RAM_POWERCLR_S0POWER_Off (1UL) /*!< Off */
+
+
+/* Peripheral: PPI */
+/* Description: Programmable Peripheral Interconnect */
+
+/* Register: PPI_CHEN */
+/* Description: Channel enable register */
+
+/* Bit 31 : Enable or disable channel 31 */
+#define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHEN_CH31_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH31_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 30 : Enable or disable channel 30 */
+#define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHEN_CH30_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH30_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 29 : Enable or disable channel 29 */
+#define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHEN_CH29_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH29_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 28 : Enable or disable channel 28 */
+#define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHEN_CH28_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH28_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 27 : Enable or disable channel 27 */
+#define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHEN_CH27_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH27_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 26 : Enable or disable channel 26 */
+#define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHEN_CH26_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH26_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 25 : Enable or disable channel 25 */
+#define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHEN_CH25_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH25_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 24 : Enable or disable channel 24 */
+#define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHEN_CH24_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH24_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 23 : Enable or disable channel 23 */
+#define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHEN_CH23_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH23_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 22 : Enable or disable channel 22 */
+#define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHEN_CH22_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH22_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 21 : Enable or disable channel 21 */
+#define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHEN_CH21_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH21_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 20 : Enable or disable channel 20 */
+#define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHEN_CH20_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH20_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 19 : Enable or disable channel 19 */
+#define PPI_CHEN_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHEN_CH19_Msk (0x1UL << PPI_CHEN_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHEN_CH19_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH19_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 18 : Enable or disable channel 18 */
+#define PPI_CHEN_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHEN_CH18_Msk (0x1UL << PPI_CHEN_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHEN_CH18_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH18_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 17 : Enable or disable channel 17 */
+#define PPI_CHEN_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHEN_CH17_Msk (0x1UL << PPI_CHEN_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHEN_CH17_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH17_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 16 : Enable or disable channel 16 */
+#define PPI_CHEN_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHEN_CH16_Msk (0x1UL << PPI_CHEN_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHEN_CH16_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH16_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 15 : Enable or disable channel 15 */
+#define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHEN_CH15_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH15_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 14 : Enable or disable channel 14 */
+#define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHEN_CH14_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH14_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 13 : Enable or disable channel 13 */
+#define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHEN_CH13_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH13_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 12 : Enable or disable channel 12 */
+#define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHEN_CH12_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH12_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 11 : Enable or disable channel 11 */
+#define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHEN_CH11_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH11_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 10 : Enable or disable channel 10 */
+#define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHEN_CH10_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH10_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 9 : Enable or disable channel 9 */
+#define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHEN_CH9_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH9_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 8 : Enable or disable channel 8 */
+#define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHEN_CH8_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH8_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 7 : Enable or disable channel 7 */
+#define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHEN_CH7_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH7_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 6 : Enable or disable channel 6 */
+#define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHEN_CH6_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH6_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 5 : Enable or disable channel 5 */
+#define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHEN_CH5_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH5_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 4 : Enable or disable channel 4 */
+#define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHEN_CH4_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH4_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 3 : Enable or disable channel 3 */
+#define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHEN_CH3_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH3_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 2 : Enable or disable channel 2 */
+#define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHEN_CH2_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH2_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 1 : Enable or disable channel 1 */
+#define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHEN_CH1_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH1_Enabled (1UL) /*!< Enable channel */
+
+/* Bit 0 : Enable or disable channel 0 */
+#define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHEN_CH0_Disabled (0UL) /*!< Disable channel */
+#define PPI_CHEN_CH0_Enabled (1UL) /*!< Enable channel */
+
+/* Register: PPI_CHENSET */
+/* Description: Channel enable set register */
+
+/* Bit 31 : Channel 31 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENSET_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH31_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 30 : Channel 30 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENSET_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH30_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 29 : Channel 29 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENSET_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH29_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 28 : Channel 28 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENSET_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH28_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 27 : Channel 27 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENSET_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH27_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 26 : Channel 26 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENSET_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH26_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 25 : Channel 25 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENSET_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH25_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 24 : Channel 24 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENSET_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH24_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 23 : Channel 23 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENSET_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH23_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 22 : Channel 22 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENSET_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH22_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 21 : Channel 21 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENSET_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH21_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 20 : Channel 20 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENSET_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH20_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 19 : Channel 19 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENSET_CH19_Msk (0x1UL << PPI_CHENSET_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENSET_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH19_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 18 : Channel 18 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENSET_CH18_Msk (0x1UL << PPI_CHENSET_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENSET_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH18_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 17 : Channel 17 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENSET_CH17_Msk (0x1UL << PPI_CHENSET_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENSET_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH17_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 16 : Channel 16 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENSET_CH16_Msk (0x1UL << PPI_CHENSET_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENSET_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH16_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 15 : Channel 15 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENSET_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH15_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 14 : Channel 14 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENSET_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH14_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 13 : Channel 13 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENSET_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH13_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 12 : Channel 12 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENSET_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH12_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 11 : Channel 11 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENSET_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH11_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 10 : Channel 10 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENSET_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH10_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 9 : Channel 9 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENSET_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH9_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 8 : Channel 8 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENSET_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH8_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 7 : Channel 7 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENSET_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH7_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 6 : Channel 6 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENSET_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH6_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 5 : Channel 5 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENSET_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH5_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 4 : Channel 4 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENSET_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH4_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 3 : Channel 3 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENSET_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH3_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 2 : Channel 2 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENSET_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH2_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 1 : Channel 1 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENSET_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH1_Set (1UL) /*!< Write: Enable channel */
+
+/* Bit 0 : Channel 0 enable set register.  Writing '0' has no effect */
+#define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENSET_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENSET_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENSET_CH0_Set (1UL) /*!< Write: Enable channel */
+
+/* Register: PPI_CHENCLR */
+/* Description: Channel enable clear register */
+
+/* Bit 31 : Channel 31 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH31_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 30 : Channel 30 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH30_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 29 : Channel 29 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH29_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 28 : Channel 28 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH28_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 27 : Channel 27 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH27_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 26 : Channel 26 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH26_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 25 : Channel 25 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH25_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 24 : Channel 24 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH24_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 23 : Channel 23 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH23_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 22 : Channel 22 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH22_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 21 : Channel 21 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH21_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 20 : Channel 20 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH20_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 19 : Channel 19 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHENCLR_CH19_Msk (0x1UL << PPI_CHENCLR_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHENCLR_CH19_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH19_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH19_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 18 : Channel 18 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHENCLR_CH18_Msk (0x1UL << PPI_CHENCLR_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHENCLR_CH18_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH18_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH18_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 17 : Channel 17 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHENCLR_CH17_Msk (0x1UL << PPI_CHENCLR_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHENCLR_CH17_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH17_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH17_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 16 : Channel 16 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHENCLR_CH16_Msk (0x1UL << PPI_CHENCLR_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHENCLR_CH16_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH16_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH16_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 15 : Channel 15 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH15_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 14 : Channel 14 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH14_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 13 : Channel 13 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH13_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 12 : Channel 12 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH12_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 11 : Channel 11 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH11_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 10 : Channel 10 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH10_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 9 : Channel 9 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH9_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 8 : Channel 8 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH8_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 7 : Channel 7 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH7_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 6 : Channel 6 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH6_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 5 : Channel 5 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH5_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 4 : Channel 4 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH4_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 3 : Channel 3 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH3_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 2 : Channel 2 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH2_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 1 : Channel 1 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH1_Clear (1UL) /*!< Write: disable channel */
+
+/* Bit 0 : Channel 0 enable clear register.  Writing '0' has no effect */
+#define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Read: channel disabled */
+#define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Read: channel enabled */
+#define PPI_CHENCLR_CH0_Clear (1UL) /*!< Write: disable channel */
+
+/* Register: PPI_CH_EEP */
+/* Description: Description cluster[0]:  Channel 0 event end-point */
+
+/* Bits 31..0 : Pointer to event register. Accepts only addresses to registers from the Event group. */
+#define PPI_CH_EEP_EEP_Pos (0UL) /*!< Position of EEP field. */
+#define PPI_CH_EEP_EEP_Msk (0xFFFFFFFFUL << PPI_CH_EEP_EEP_Pos) /*!< Bit mask of EEP field. */
+
+/* Register: PPI_CH_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register. Accepts only addresses to registers from the Task group. */
+#define PPI_CH_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_CH_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_CH_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+/* Register: PPI_CHG */
+/* Description: Description collection[0]:  Channel group 0 */
+
+/* Bit 31 : Include or exclude channel 31 */
+#define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
+#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
+#define PPI_CHG_CH31_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH31_Included (1UL) /*!< Include */
+
+/* Bit 30 : Include or exclude channel 30 */
+#define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
+#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
+#define PPI_CHG_CH30_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH30_Included (1UL) /*!< Include */
+
+/* Bit 29 : Include or exclude channel 29 */
+#define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
+#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
+#define PPI_CHG_CH29_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH29_Included (1UL) /*!< Include */
+
+/* Bit 28 : Include or exclude channel 28 */
+#define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
+#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
+#define PPI_CHG_CH28_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH28_Included (1UL) /*!< Include */
+
+/* Bit 27 : Include or exclude channel 27 */
+#define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
+#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
+#define PPI_CHG_CH27_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH27_Included (1UL) /*!< Include */
+
+/* Bit 26 : Include or exclude channel 26 */
+#define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
+#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
+#define PPI_CHG_CH26_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH26_Included (1UL) /*!< Include */
+
+/* Bit 25 : Include or exclude channel 25 */
+#define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
+#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
+#define PPI_CHG_CH25_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH25_Included (1UL) /*!< Include */
+
+/* Bit 24 : Include or exclude channel 24 */
+#define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
+#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
+#define PPI_CHG_CH24_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH24_Included (1UL) /*!< Include */
+
+/* Bit 23 : Include or exclude channel 23 */
+#define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
+#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
+#define PPI_CHG_CH23_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH23_Included (1UL) /*!< Include */
+
+/* Bit 22 : Include or exclude channel 22 */
+#define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
+#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
+#define PPI_CHG_CH22_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH22_Included (1UL) /*!< Include */
+
+/* Bit 21 : Include or exclude channel 21 */
+#define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
+#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
+#define PPI_CHG_CH21_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH21_Included (1UL) /*!< Include */
+
+/* Bit 20 : Include or exclude channel 20 */
+#define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
+#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
+#define PPI_CHG_CH20_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH20_Included (1UL) /*!< Include */
+
+/* Bit 19 : Include or exclude channel 19 */
+#define PPI_CHG_CH19_Pos (19UL) /*!< Position of CH19 field. */
+#define PPI_CHG_CH19_Msk (0x1UL << PPI_CHG_CH19_Pos) /*!< Bit mask of CH19 field. */
+#define PPI_CHG_CH19_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH19_Included (1UL) /*!< Include */
+
+/* Bit 18 : Include or exclude channel 18 */
+#define PPI_CHG_CH18_Pos (18UL) /*!< Position of CH18 field. */
+#define PPI_CHG_CH18_Msk (0x1UL << PPI_CHG_CH18_Pos) /*!< Bit mask of CH18 field. */
+#define PPI_CHG_CH18_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH18_Included (1UL) /*!< Include */
+
+/* Bit 17 : Include or exclude channel 17 */
+#define PPI_CHG_CH17_Pos (17UL) /*!< Position of CH17 field. */
+#define PPI_CHG_CH17_Msk (0x1UL << PPI_CHG_CH17_Pos) /*!< Bit mask of CH17 field. */
+#define PPI_CHG_CH17_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH17_Included (1UL) /*!< Include */
+
+/* Bit 16 : Include or exclude channel 16 */
+#define PPI_CHG_CH16_Pos (16UL) /*!< Position of CH16 field. */
+#define PPI_CHG_CH16_Msk (0x1UL << PPI_CHG_CH16_Pos) /*!< Bit mask of CH16 field. */
+#define PPI_CHG_CH16_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH16_Included (1UL) /*!< Include */
+
+/* Bit 15 : Include or exclude channel 15 */
+#define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
+#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
+#define PPI_CHG_CH15_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH15_Included (1UL) /*!< Include */
+
+/* Bit 14 : Include or exclude channel 14 */
+#define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
+#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
+#define PPI_CHG_CH14_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH14_Included (1UL) /*!< Include */
+
+/* Bit 13 : Include or exclude channel 13 */
+#define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
+#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
+#define PPI_CHG_CH13_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH13_Included (1UL) /*!< Include */
+
+/* Bit 12 : Include or exclude channel 12 */
+#define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
+#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
+#define PPI_CHG_CH12_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH12_Included (1UL) /*!< Include */
+
+/* Bit 11 : Include or exclude channel 11 */
+#define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
+#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
+#define PPI_CHG_CH11_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH11_Included (1UL) /*!< Include */
+
+/* Bit 10 : Include or exclude channel 10 */
+#define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
+#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
+#define PPI_CHG_CH10_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH10_Included (1UL) /*!< Include */
+
+/* Bit 9 : Include or exclude channel 9 */
+#define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
+#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
+#define PPI_CHG_CH9_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH9_Included (1UL) /*!< Include */
+
+/* Bit 8 : Include or exclude channel 8 */
+#define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
+#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
+#define PPI_CHG_CH8_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH8_Included (1UL) /*!< Include */
+
+/* Bit 7 : Include or exclude channel 7 */
+#define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
+#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
+#define PPI_CHG_CH7_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH7_Included (1UL) /*!< Include */
+
+/* Bit 6 : Include or exclude channel 6 */
+#define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
+#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
+#define PPI_CHG_CH6_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH6_Included (1UL) /*!< Include */
+
+/* Bit 5 : Include or exclude channel 5 */
+#define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
+#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
+#define PPI_CHG_CH5_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH5_Included (1UL) /*!< Include */
+
+/* Bit 4 : Include or exclude channel 4 */
+#define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
+#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
+#define PPI_CHG_CH4_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH4_Included (1UL) /*!< Include */
+
+/* Bit 3 : Include or exclude channel 3 */
+#define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
+#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
+#define PPI_CHG_CH3_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH3_Included (1UL) /*!< Include */
+
+/* Bit 2 : Include or exclude channel 2 */
+#define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
+#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
+#define PPI_CHG_CH2_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH2_Included (1UL) /*!< Include */
+
+/* Bit 1 : Include or exclude channel 1 */
+#define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
+#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
+#define PPI_CHG_CH1_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH1_Included (1UL) /*!< Include */
+
+/* Bit 0 : Include or exclude channel 0 */
+#define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
+#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
+#define PPI_CHG_CH0_Excluded (0UL) /*!< Exclude */
+#define PPI_CHG_CH0_Included (1UL) /*!< Include */
+
+/* Register: PPI_FORK_TEP */
+/* Description: Description cluster[0]:  Channel 0 task end-point */
+
+/* Bits 31..0 : Pointer to task register */
+#define PPI_FORK_TEP_TEP_Pos (0UL) /*!< Position of TEP field. */
+#define PPI_FORK_TEP_TEP_Msk (0xFFFFFFFFUL << PPI_FORK_TEP_TEP_Pos) /*!< Bit mask of TEP field. */
+
+
+/* Peripheral: PWM */
+/* Description: Pulse Width Modulation Unit 0 */
+
+/* Register: PWM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between LOOPSDONE event and STOP task */
+#define PWM_SHORTS_LOOPSDONE_STOP_Pos (4UL) /*!< Position of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_STOP_Pos) /*!< Bit mask of LOOPSDONE_STOP field. */
+#define PWM_SHORTS_LOOPSDONE_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between LOOPSDONE event and SEQSTART[1] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos (3UL) /*!< Position of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART1_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART1 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART1_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between LOOPSDONE event and SEQSTART[0] task */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos (2UL) /*!< Position of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk (0x1UL << PWM_SHORTS_LOOPSDONE_SEQSTART0_Pos) /*!< Bit mask of LOOPSDONE_SEQSTART0 field. */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_LOOPSDONE_SEQSTART0_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SEQEND[1] event and STOP task */
+#define PWM_SHORTS_SEQEND1_STOP_Pos (1UL) /*!< Position of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND1_STOP_Pos) /*!< Bit mask of SEQEND1_STOP field. */
+#define PWM_SHORTS_SEQEND1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between SEQEND[0] event and STOP task */
+#define PWM_SHORTS_SEQEND0_STOP_Pos (0UL) /*!< Position of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Msk (0x1UL << PWM_SHORTS_SEQEND0_STOP_Pos) /*!< Bit mask of SEQEND0_STOP field. */
+#define PWM_SHORTS_SEQEND0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define PWM_SHORTS_SEQEND0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: PWM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 7 : Enable or disable interrupt for LOOPSDONE event */
+#define PWM_INTEN_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Msk (0x1UL << PWM_INTEN_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTEN_LOOPSDONE_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_LOOPSDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for PWMPERIODEND event */
+#define PWM_INTEN_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Msk (0x1UL << PWM_INTEN_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTEN_PWMPERIODEND_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_PWMPERIODEND_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for SEQEND[1] event */
+#define PWM_INTEN_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Msk (0x1UL << PWM_INTEN_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTEN_SEQEND1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND1_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for SEQEND[0] event */
+#define PWM_INTEN_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Msk (0x1UL << PWM_INTEN_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTEN_SEQEND0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQEND0_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTEN_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Msk (0x1UL << PWM_INTEN_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTEN_SEQSTARTED1_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED1_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTEN_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Msk (0x1UL << PWM_INTEN_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTEN_SEQSTARTED0_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_SEQSTARTED0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define PWM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTEN_STOPPED_Msk (0x1UL << PWM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define PWM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 7 : Write '1' to Enable interrupt for LOOPSDONE event */
+#define PWM_INTENSET_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Msk (0x1UL << PWM_INTENSET_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENSET_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_LOOPSDONE_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for PWMPERIODEND event */
+#define PWM_INTENSET_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Msk (0x1UL << PWM_INTENSET_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENSET_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_PWMPERIODEND_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for SEQEND[1] event */
+#define PWM_INTENSET_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Msk (0x1UL << PWM_INTENSET_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENSET_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND1_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for SEQEND[0] event */
+#define PWM_INTENSET_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Msk (0x1UL << PWM_INTENSET_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENSET_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQEND0_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENSET_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Msk (0x1UL << PWM_INTENSET_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENSET_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED1_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENSET_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Msk (0x1UL << PWM_INTENSET_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENSET_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_SEQSTARTED0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define PWM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Msk (0x1UL << PWM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: PWM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 7 : Write '1' to Disable interrupt for LOOPSDONE event */
+#define PWM_INTENCLR_LOOPSDONE_Pos (7UL) /*!< Position of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Msk (0x1UL << PWM_INTENCLR_LOOPSDONE_Pos) /*!< Bit mask of LOOPSDONE field. */
+#define PWM_INTENCLR_LOOPSDONE_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_LOOPSDONE_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_LOOPSDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for PWMPERIODEND event */
+#define PWM_INTENCLR_PWMPERIODEND_Pos (6UL) /*!< Position of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Msk (0x1UL << PWM_INTENCLR_PWMPERIODEND_Pos) /*!< Bit mask of PWMPERIODEND field. */
+#define PWM_INTENCLR_PWMPERIODEND_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_PWMPERIODEND_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_PWMPERIODEND_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for SEQEND[1] event */
+#define PWM_INTENCLR_SEQEND1_Pos (5UL) /*!< Position of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Msk (0x1UL << PWM_INTENCLR_SEQEND1_Pos) /*!< Bit mask of SEQEND1 field. */
+#define PWM_INTENCLR_SEQEND1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND1_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for SEQEND[0] event */
+#define PWM_INTENCLR_SEQEND0_Pos (4UL) /*!< Position of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Msk (0x1UL << PWM_INTENCLR_SEQEND0_Pos) /*!< Bit mask of SEQEND0 field. */
+#define PWM_INTENCLR_SEQEND0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQEND0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQEND0_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for SEQSTARTED[1] event */
+#define PWM_INTENCLR_SEQSTARTED1_Pos (3UL) /*!< Position of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED1_Pos) /*!< Bit mask of SEQSTARTED1 field. */
+#define PWM_INTENCLR_SEQSTARTED1_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED1_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED1_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for SEQSTARTED[0] event */
+#define PWM_INTENCLR_SEQSTARTED0_Pos (2UL) /*!< Position of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Msk (0x1UL << PWM_INTENCLR_SEQSTARTED0_Pos) /*!< Bit mask of SEQSTARTED0 field. */
+#define PWM_INTENCLR_SEQSTARTED0_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_SEQSTARTED0_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_SEQSTARTED0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define PWM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Msk (0x1UL << PWM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define PWM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define PWM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define PWM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: PWM_ENABLE */
+/* Description: PWM module enable register */
+
+/* Bit 0 : Enable or disable PWM module */
+#define PWM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Msk (0x1UL << PWM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define PWM_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled */
+#define PWM_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: PWM_MODE */
+/* Description: Selects operating mode of the wave counter */
+
+/* Bit 0 : Selects up or up and down as wave counter mode */
+#define PWM_MODE_UPDOWN_Pos (0UL) /*!< Position of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Msk (0x1UL << PWM_MODE_UPDOWN_Pos) /*!< Bit mask of UPDOWN field. */
+#define PWM_MODE_UPDOWN_Up (0UL) /*!< Up counter - edge aligned PWM duty-cycle */
+#define PWM_MODE_UPDOWN_UpAndDown (1UL) /*!< Up and down counter - center aligned PWM duty cycle */
+
+/* Register: PWM_COUNTERTOP */
+/* Description: Value up to which the pulse generator counter counts */
+
+/* Bits 14..0 : Value up to which the pulse generator counter counts. This register is ignored when DECODER.MODE=WaveForm and only values from RAM will be used. */
+#define PWM_COUNTERTOP_COUNTERTOP_Pos (0UL) /*!< Position of COUNTERTOP field. */
+#define PWM_COUNTERTOP_COUNTERTOP_Msk (0x7FFFUL << PWM_COUNTERTOP_COUNTERTOP_Pos) /*!< Bit mask of COUNTERTOP field. */
+
+/* Register: PWM_PRESCALER */
+/* Description: Configuration for PWM_CLK */
+
+/* Bits 2..0 : Pre-scaler of PWM_CLK */
+#define PWM_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_Msk (0x7UL << PWM_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+#define PWM_PRESCALER_PRESCALER_DIV_1 (0UL) /*!< Divide by   1 (16MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_2 (1UL) /*!< Divide by   2 ( 8MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_4 (2UL) /*!< Divide by   4 ( 4MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_8 (3UL) /*!< Divide by   8 ( 2MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_16 (4UL) /*!< Divide by  16 ( 1MHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_32 (5UL) /*!< Divide by  32 ( 500kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_64 (6UL) /*!< Divide by  64 ( 250kHz) */
+#define PWM_PRESCALER_PRESCALER_DIV_128 (7UL) /*!< Divide by 128 ( 125kHz) */
+
+/* Register: PWM_DECODER */
+/* Description: Configuration of the decoder */
+
+/* Bit 8 : Selects source for advancing the active sequence */
+#define PWM_DECODER_MODE_Pos (8UL) /*!< Position of MODE field. */
+#define PWM_DECODER_MODE_Msk (0x1UL << PWM_DECODER_MODE_Pos) /*!< Bit mask of MODE field. */
+#define PWM_DECODER_MODE_RefreshCount (0UL) /*!< SEQ[n].REFRESH is used to determine loading internal compare registers */
+#define PWM_DECODER_MODE_NextStep (1UL) /*!< NEXTSTEP task causes a new value to be loaded to internal compare registers */
+
+/* Bits 2..0 : How a sequence is read from RAM and spread to the compare register */
+#define PWM_DECODER_LOAD_Pos (0UL) /*!< Position of LOAD field. */
+#define PWM_DECODER_LOAD_Msk (0x7UL << PWM_DECODER_LOAD_Pos) /*!< Bit mask of LOAD field. */
+#define PWM_DECODER_LOAD_Common (0UL) /*!< 1st half word (16-bit) used in all PWM channels 0..3 */
+#define PWM_DECODER_LOAD_Grouped (1UL) /*!< 1st half word (16-bit) used in channel 0..1; 2nd word in channel 2..3 */
+#define PWM_DECODER_LOAD_Individual (2UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in ch.3 */
+#define PWM_DECODER_LOAD_WaveForm (3UL) /*!< 1st half word (16-bit) in ch.0; 2nd in ch.1; ...; 4th in COUNTERTOP */
+
+/* Register: PWM_LOOP */
+/* Description: Amount of playback of a loop */
+
+/* Bits 15..0 : Amount of playback of pattern cycles */
+#define PWM_LOOP_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_LOOP_CNT_Msk (0xFFFFUL << PWM_LOOP_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_LOOP_CNT_Disabled (0UL) /*!< Looping disabled (stop at the end of the sequence) */
+
+/* Register: PWM_SEQ_PTR */
+/* Description: Description cluster[0]:  Beginning address in Data RAM of sequence A */
+
+/* Bits 31..0 : Beginning address in Data RAM of sequence A */
+#define PWM_SEQ_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define PWM_SEQ_PTR_PTR_Msk (0xFFFFFFFFUL << PWM_SEQ_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: PWM_SEQ_CNT */
+/* Description: Description cluster[0]:  Amount of values (duty cycles) in sequence A */
+
+/* Bits 14..0 : Amount of values (duty cycles) in sequence A */
+#define PWM_SEQ_CNT_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_CNT_CNT_Msk (0x7FFFUL << PWM_SEQ_CNT_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_CNT_CNT_Disabled (0UL) /*!< Sequence is disabled, and shall not be started as it is empty */
+
+/* Register: PWM_SEQ_REFRESH */
+/* Description: Description cluster[0]:  Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
+
+/* Bits 23..0 : Amount of additional PWM periods between samples loaded to compare register (load every CNT+1 PWM periods) */
+#define PWM_SEQ_REFRESH_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Msk (0xFFFFFFUL << PWM_SEQ_REFRESH_CNT_Pos) /*!< Bit mask of CNT field. */
+#define PWM_SEQ_REFRESH_CNT_Continuous (0UL) /*!< Update every PWM period */
+
+/* Register: PWM_SEQ_ENDDELAY */
+/* Description: Description cluster[0]:  Time added after the sequence */
+
+/* Bits 23..0 : Time added after the sequence in PWM periods */
+#define PWM_SEQ_ENDDELAY_CNT_Pos (0UL) /*!< Position of CNT field. */
+#define PWM_SEQ_ENDDELAY_CNT_Msk (0xFFFFFFUL << PWM_SEQ_ENDDELAY_CNT_Pos) /*!< Bit mask of CNT field. */
+
+/* Register: PWM_PSEL_OUT */
+/* Description: Description collection[0]:  Output pin select for PWM channel 0 */
+
+/* Bit 31 : Connection */
+#define PWM_PSEL_OUT_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Msk (0x1UL << PWM_PSEL_OUT_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define PWM_PSEL_OUT_CONNECT_Connected (0UL) /*!< Connect */
+#define PWM_PSEL_OUT_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define PWM_PSEL_OUT_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define PWM_PSEL_OUT_PIN_Msk (0x1FUL << PWM_PSEL_OUT_PIN_Pos) /*!< Bit mask of PIN field. */
+
+
+/* Peripheral: QDEC */
+/* Description: Quadrature Decoder */
+
+/* Register: QDEC_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between SAMPLERDY event and READCLRACC task */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos (6UL) /*!< Position of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_READCLRACC_Pos) /*!< Bit mask of SAMPLERDY_READCLRACC field. */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between DBLRDY event and STOP task */
+#define QDEC_SHORTS_DBLRDY_STOP_Pos (5UL) /*!< Position of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Msk (0x1UL << QDEC_SHORTS_DBLRDY_STOP_Pos) /*!< Bit mask of DBLRDY_STOP field. */
+#define QDEC_SHORTS_DBLRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between DBLRDY event and RDCLRDBL task */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos (4UL) /*!< Position of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Msk (0x1UL << QDEC_SHORTS_DBLRDY_RDCLRDBL_Pos) /*!< Bit mask of DBLRDY_RDCLRDBL field. */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_DBLRDY_RDCLRDBL_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between REPORTRDY event and STOP task */
+#define QDEC_SHORTS_REPORTRDY_STOP_Pos (3UL) /*!< Position of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_STOP_Pos) /*!< Bit mask of REPORTRDY_STOP field. */
+#define QDEC_SHORTS_REPORTRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between REPORTRDY event and RDCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos (2UL) /*!< Position of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_RDCLRACC_Pos) /*!< Bit mask of REPORTRDY_RDCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_RDCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between SAMPLERDY event and STOP task */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Disable shortcut */
+#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: QDEC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 4 : Write '1' to Enable interrupt for STOPPED event */
+#define QDEC_INTENSET_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Msk (0x1UL << QDEC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for DBLRDY event */
+#define QDEC_INTENSET_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Msk (0x1UL << QDEC_INTENSET_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENSET_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_DBLRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for ACCOF event */
+#define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for REPORTRDY event */
+#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for SAMPLERDY event */
+#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable */
+
+/* Register: QDEC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 4 : Write '1' to Disable interrupt for STOPPED event */
+#define QDEC_INTENCLR_STOPPED_Pos (4UL) /*!< Position of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Msk (0x1UL << QDEC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define QDEC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for DBLRDY event */
+#define QDEC_INTENCLR_DBLRDY_Pos (3UL) /*!< Position of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Msk (0x1UL << QDEC_INTENCLR_DBLRDY_Pos) /*!< Bit mask of DBLRDY field. */
+#define QDEC_INTENCLR_DBLRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_DBLRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_DBLRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for ACCOF event */
+#define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
+#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for REPORTRDY event */
+#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
+#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for SAMPLERDY event */
+#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
+#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Read: Disabled */
+#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Read: Enabled */
+#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable */
+
+/* Register: QDEC_ENABLE */
+/* Description: Enable the quadrature decoder */
+
+/* Bit 0 : Enable or disable the quadrature decoder */
+#define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable */
+#define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable */
+
+/* Register: QDEC_LEDPOL */
+/* Description: LED output pin polarity */
+
+/* Bit 0 : LED output pin polarity */
+#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
+#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< Led active on output pin low */
+#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< Led active on output pin high */
+
+/* Register: QDEC_SAMPLEPER */
+/* Description: Sample period */
+
+/* Bits 3..0 : Sample period. The SAMPLE register will be updated for every new sample */
+#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0xFUL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
+#define QDEC_SAMPLEPER_SAMPLEPER_128us (0UL) /*!< 128 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_256us (1UL) /*!< 256 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_512us (2UL) /*!< 512 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_1024us (3UL) /*!< 1024 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_2048us (4UL) /*!< 2048 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_4096us (5UL) /*!< 4096 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_8192us (6UL) /*!< 8192 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_16384us (7UL) /*!< 16384 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_32ms (8UL) /*!< 32768 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_65ms (9UL) /*!< 65536 us */
+#define QDEC_SAMPLEPER_SAMPLEPER_131ms (10UL) /*!< 131072 us */
+
+/* Register: QDEC_SAMPLE */
+/* Description: Motion sample value */
+
+/* Bits 31..0 : Last motion sample */
+#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
+#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
+
+/* Register: QDEC_REPORTPER */
+/* Description: Number of samples to be taken before REPORTRDY and DBLRDY events can be generated */
+
+/* Bits 3..0 : Specifies the number of samples to be accumulated in the ACC register before the REPORTRDY and DBLRDY events can be generated */
+#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_Msk (0xFUL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
+#define QDEC_REPORTPER_REPORTPER_10Smpl (0UL) /*!< 10 samples / report */
+#define QDEC_REPORTPER_REPORTPER_40Smpl (1UL) /*!< 40 samples / report */
+#define QDEC_REPORTPER_REPORTPER_80Smpl (2UL) /*!< 80 samples / report */
+#define QDEC_REPORTPER_REPORTPER_120Smpl (3UL) /*!< 120 samples / report */
+#define QDEC_REPORTPER_REPORTPER_160Smpl (4UL) /*!< 160 samples / report */
+#define QDEC_REPORTPER_REPORTPER_200Smpl (5UL) /*!< 200 samples / report */
+#define QDEC_REPORTPER_REPORTPER_240Smpl (6UL) /*!< 240 samples / report */
+#define QDEC_REPORTPER_REPORTPER_280Smpl (7UL) /*!< 280 samples / report */
+#define QDEC_REPORTPER_REPORTPER_1Smpl (8UL) /*!< 1 sample / report */
+
+/* Register: QDEC_ACC */
+/* Description: Register accumulating the valid transitions */
+
+/* Bits 31..0 : Register accumulating all valid samples (not double transition) read from the SAMPLE register */
+#define QDEC_ACC_ACC_Pos (0UL) /*!< Position of ACC field. */
+#define QDEC_ACC_ACC_Msk (0xFFFFFFFFUL << QDEC_ACC_ACC_Pos) /*!< Bit mask of ACC field. */
+
+/* Register: QDEC_ACCREAD */
+/* Description: Snapshot of the ACC register, updated by the READCLRACC or RDCLRACC task */
+
+/* Bits 31..0 : Snapshot of the ACC register. */
+#define QDEC_ACCREAD_ACCREAD_Pos (0UL) /*!< Position of ACCREAD field. */
+#define QDEC_ACCREAD_ACCREAD_Msk (0xFFFFFFFFUL << QDEC_ACCREAD_ACCREAD_Pos) /*!< Bit mask of ACCREAD field. */
+
+/* Register: QDEC_PSEL_LED */
+/* Description: Pin select for LED signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_LED_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Msk (0x1UL << QDEC_PSEL_LED_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_LED_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_LED_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_LED_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_LED_PIN_Msk (0x1FUL << QDEC_PSEL_LED_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_A */
+/* Description: Pin select for A signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_A_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Msk (0x1UL << QDEC_PSEL_A_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_A_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_A_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_A_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_A_PIN_Msk (0x1FUL << QDEC_PSEL_A_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_PSEL_B */
+/* Description: Pin select for B signal */
+
+/* Bit 31 : Connection */
+#define QDEC_PSEL_B_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Msk (0x1UL << QDEC_PSEL_B_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define QDEC_PSEL_B_CONNECT_Connected (0UL) /*!< Connect */
+#define QDEC_PSEL_B_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define QDEC_PSEL_B_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define QDEC_PSEL_B_PIN_Msk (0x1FUL << QDEC_PSEL_B_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: QDEC_DBFEN */
+/* Description: Enable input debounce filters */
+
+/* Bit 0 : Enable input debounce filters */
+#define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
+#define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled */
+#define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled */
+
+/* Register: QDEC_LEDPRE */
+/* Description: Time period the LED is switched ON prior to sampling */
+
+/* Bits 8..0 : Period in us the LED is switched on prior to sampling */
+#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
+#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
+
+/* Register: QDEC_ACCDBL */
+/* Description: Register accumulating the number of detected double transitions */
+
+/* Bits 3..0 : Register accumulating the number of detected double or illegal transitions. ( SAMPLE = 2 ). */
+#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
+#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
+
+/* Register: QDEC_ACCDBLREAD */
+/* Description: Snapshot of the ACCDBL, updated by the READCLRACC or RDCLRDBL task */
+
+/* Bits 3..0 : Snapshot of the ACCDBL register. This field is updated when the READCLRACC or RDCLRDBL task is triggered. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
+#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
+
+
+/* Peripheral: RADIO */
+/* Description: 2.4 GHz Radio */
+
+/* Register: RADIO_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 6 : Shortcut between ADDRESS event and BCSTART task */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between END event and START task */
+#define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
+#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between DISABLED event and RXEN task */
+#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
+#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between DISABLED event and TXEN task */
+#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
+#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between END event and DISABLE task */
+#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
+#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between READY event and START task */
+#define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
+#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
+#define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Disable shortcut */
+#define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RADIO_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 13 : Write '1' to Enable interrupt for CRCERROR event */
+#define RADIO_INTENSET_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Msk (0x1UL << RADIO_INTENSET_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENSET_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCERROR_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CRCOK event */
+#define RADIO_INTENSET_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Msk (0x1UL << RADIO_INTENSET_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENSET_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_CRCOK_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for BCMATCH event */
+#define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for RSSIEND event */
+#define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for DEVMISS event */
+#define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for DEVMATCH event */
+#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for DISABLED event */
+#define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for END event */
+#define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for PAYLOAD event */
+#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for ADDRESS event */
+#define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for READY event */
+#define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: RADIO_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 13 : Write '1' to Disable interrupt for CRCERROR event */
+#define RADIO_INTENCLR_CRCERROR_Pos (13UL) /*!< Position of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Msk (0x1UL << RADIO_INTENCLR_CRCERROR_Pos) /*!< Bit mask of CRCERROR field. */
+#define RADIO_INTENCLR_CRCERROR_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCERROR_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CRCOK event */
+#define RADIO_INTENCLR_CRCOK_Pos (12UL) /*!< Position of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Msk (0x1UL << RADIO_INTENCLR_CRCOK_Pos) /*!< Bit mask of CRCOK field. */
+#define RADIO_INTENCLR_CRCOK_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_CRCOK_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_CRCOK_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for BCMATCH event */
+#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
+#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for RSSIEND event */
+#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
+#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for DEVMISS event */
+#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
+#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for DEVMATCH event */
+#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
+#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for DISABLED event */
+#define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
+#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for END event */
+#define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
+#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define RADIO_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for PAYLOAD event */
+#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
+#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for ADDRESS event */
+#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for READY event */
+#define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
+#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: RADIO_CRCSTATUS */
+/* Description: CRC status */
+
+/* Bit 0 : CRC status of packet received */
+#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error */
+#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok */
+
+/* Register: RADIO_RXMATCH */
+/* Description: Received address */
+
+/* Bits 2..0 : Received address */
+#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
+#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
+
+/* Register: RADIO_RXCRC */
+/* Description: CRC field of previously received packet */
+
+/* Bits 23..0 : CRC field of previously received packet */
+#define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
+#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
+
+/* Register: RADIO_DAI */
+/* Description: Device address match index */
+
+/* Bits 2..0 : Device address match index */
+#define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
+#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
+
+/* Register: RADIO_PACKETPTR */
+/* Description: Packet pointer */
+
+/* Bits 31..0 : Packet pointer */
+#define RADIO_PACKETPTR_PACKETPTR_Pos (0UL) /*!< Position of PACKETPTR field. */
+#define RADIO_PACKETPTR_PACKETPTR_Msk (0xFFFFFFFFUL << RADIO_PACKETPTR_PACKETPTR_Pos) /*!< Bit mask of PACKETPTR field. */
+
+/* Register: RADIO_FREQUENCY */
+/* Description: Frequency */
+
+/* Bit 8 : Channel map selection. */
+#define RADIO_FREQUENCY_MAP_Pos (8UL) /*!< Position of MAP field. */
+#define RADIO_FREQUENCY_MAP_Msk (0x1UL << RADIO_FREQUENCY_MAP_Pos) /*!< Bit mask of MAP field. */
+#define RADIO_FREQUENCY_MAP_Default (0UL) /*!< Channel map between 2400 MHZ .. 2500 MHz */
+#define RADIO_FREQUENCY_MAP_Low (1UL) /*!< Channel map between 2360 MHZ .. 2460 MHz */
+
+/* Bits 6..0 : Radio channel frequency */
+#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+
+/* Register: RADIO_TXPOWER */
+/* Description: Output power */
+
+/* Bits 7..0 : RADIO output power. */
+#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
+#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos3dBm (0x03UL) /*!< +3 dBm */
+#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< Deprecated enumerator -  -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg40dBm (0xD8UL) /*!< -40 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8 dBm */
+#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4 dBm */
+
+/* Register: RADIO_MODE */
+/* Description: Data rate and modulation */
+
+/* Bits 3..0 : Radio data rate and modulation setting. The radio supports Frequency-shift Keying (FSK) modulation. */
+#define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define RADIO_MODE_MODE_Msk (0xFUL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define RADIO_MODE_MODE_Nrf_1Mbit (0UL) /*!< 1 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_2Mbit (1UL) /*!< 2 Mbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Nrf_250Kbit (2UL) /*!< Deprecated enumerator -  250 kbit/s Nordic proprietary radio mode */
+#define RADIO_MODE_MODE_Ble_1Mbit (3UL) /*!< 1 Mbit/s Bluetooth Low Energy */
+
+/* Register: RADIO_PCNF0 */
+/* Description: Packet configuration register 0 */
+
+/* Bit 24 : Length of preamble on air. Decision point: TASKS_START task */
+#define RADIO_PCNF0_PLEN_Pos (24UL) /*!< Position of PLEN field. */
+#define RADIO_PCNF0_PLEN_Msk (0x1UL << RADIO_PCNF0_PLEN_Pos) /*!< Bit mask of PLEN field. */
+#define RADIO_PCNF0_PLEN_8bit (0UL) /*!< 8-bit preamble */
+#define RADIO_PCNF0_PLEN_16bit (1UL) /*!< 16-bit preamble */
+
+/* Bit 20 : Include or exclude S1 field in RAM */
+#define RADIO_PCNF0_S1INCL_Pos (20UL) /*!< Position of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Msk (0x1UL << RADIO_PCNF0_S1INCL_Pos) /*!< Bit mask of S1INCL field. */
+#define RADIO_PCNF0_S1INCL_Automatic (0UL) /*!< Include S1 field in RAM only if S1LEN &gt; 0 */
+#define RADIO_PCNF0_S1INCL_Include (1UL) /*!< Always include S1 field in RAM independent of S1LEN */
+
+/* Bits 19..16 : Length on air of S1 field in number of bits. */
+#define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
+#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
+
+/* Bit 8 : Length on air of S0 field in number of bytes. */
+#define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
+#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
+
+/* Bits 3..0 : Length on air of LENGTH field in number of bits. */
+#define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
+#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
+
+/* Register: RADIO_PCNF1 */
+/* Description: Packet configuration register 1 */
+
+/* Bit 25 : Enable or disable packet whitening */
+#define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
+#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Disable */
+#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Enable */
+
+/* Bit 24 : On air endianness of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+#define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
+#define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least Significant bit on air first */
+#define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
+
+/* Bits 18..16 : Base address length in number of bytes */
+#define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
+#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
+
+/* Bits 15..8 : Static length in number of bytes */
+#define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
+#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
+
+/* Bits 7..0 : Maximum length of packet payload. If the packet payload is larger than MAXLEN, the radio will truncate the payload to MAXLEN. */
+#define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
+#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
+
+/* Register: RADIO_BASE0 */
+/* Description: Base address 0 */
+
+/* Bits 31..0 : Base address 0 */
+#define RADIO_BASE0_BASE0_Pos (0UL) /*!< Position of BASE0 field. */
+#define RADIO_BASE0_BASE0_Msk (0xFFFFFFFFUL << RADIO_BASE0_BASE0_Pos) /*!< Bit mask of BASE0 field. */
+
+/* Register: RADIO_BASE1 */
+/* Description: Base address 1 */
+
+/* Bits 31..0 : Base address 1 */
+#define RADIO_BASE1_BASE1_Pos (0UL) /*!< Position of BASE1 field. */
+#define RADIO_BASE1_BASE1_Msk (0xFFFFFFFFUL << RADIO_BASE1_BASE1_Pos) /*!< Bit mask of BASE1 field. */
+
+/* Register: RADIO_PREFIX0 */
+/* Description: Prefixes bytes for logical addresses 0-3 */
+
+/* Bits 31..24 : Address prefix 3. */
+#define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
+#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
+
+/* Bits 23..16 : Address prefix 2. */
+#define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
+#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
+
+/* Bits 15..8 : Address prefix 1. */
+#define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
+#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
+
+/* Bits 7..0 : Address prefix 0. */
+#define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
+#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
+
+/* Register: RADIO_PREFIX1 */
+/* Description: Prefixes bytes for logical addresses 4-7 */
+
+/* Bits 31..24 : Address prefix 7. */
+#define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
+#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
+
+/* Bits 23..16 : Address prefix 6. */
+#define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
+#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
+
+/* Bits 15..8 : Address prefix 5. */
+#define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
+#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
+
+/* Bits 7..0 : Address prefix 4. */
+#define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
+#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
+
+/* Register: RADIO_TXADDRESS */
+/* Description: Transmit address select */
+
+/* Bits 2..0 : Transmit address select */
+#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
+#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
+
+/* Register: RADIO_RXADDRESSES */
+/* Description: Receive address select */
+
+/* Bit 7 : Enable or disable reception on logical address 7. */
+#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
+#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable reception on logical address 6. */
+#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
+#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable reception on logical address 5. */
+#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
+#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable reception on logical address 4. */
+#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
+#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable reception on logical address 3. */
+#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
+#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable reception on logical address 2. */
+#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
+#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable reception on logical address 1. */
+#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
+#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable reception on logical address 0. */
+#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
+#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Disable */
+#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Enable */
+
+/* Register: RADIO_CRCCNF */
+/* Description: CRC configuration */
+
+/* Bit 8 : Include or exclude packet address field out of CRC calculation. */
+#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /*!< Position of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /*!< Bit mask of SKIPADDR field. */
+#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /*!< CRC calculation includes address field */
+#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /*!< CRC calculation does not include address field. The CRC calculation will start at the first byte after the address. */
+
+/* Bits 1..0 : CRC length in number of bytes. */
+#define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
+#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
+#define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC length is zero and CRC calculation is disabled */
+#define RADIO_CRCCNF_LEN_One (1UL) /*!< CRC length is one byte and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Two (2UL) /*!< CRC length is two bytes and CRC calculation is enabled */
+#define RADIO_CRCCNF_LEN_Three (3UL) /*!< CRC length is three bytes and CRC calculation is enabled */
+
+/* Register: RADIO_CRCPOLY */
+/* Description: CRC polynomial */
+
+/* Bits 23..0 : CRC polynomial */
+#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /*!< Position of CRCPOLY field. */
+#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
+
+/* Register: RADIO_CRCINIT */
+/* Description: CRC initial value */
+
+/* Bits 23..0 : CRC initial value */
+#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
+#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
+
+/* Register: RADIO_TIFS */
+/* Description: Inter Frame Spacing in us */
+
+/* Bits 7..0 : Inter Frame Spacing in us */
+#define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
+#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
+
+/* Register: RADIO_RSSISAMPLE */
+/* Description: RSSI sample */
+
+/* Bits 6..0 : RSSI sample */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
+#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
+
+/* Register: RADIO_STATE */
+/* Description: Current radio state */
+
+/* Bits 3..0 : Current radio state */
+#define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
+#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
+#define RADIO_STATE_STATE_Disabled (0UL) /*!< RADIO is in the Disabled state */
+#define RADIO_STATE_STATE_RxRu (1UL) /*!< RADIO is in the RXRU state */
+#define RADIO_STATE_STATE_RxIdle (2UL) /*!< RADIO is in the RXIDLE state */
+#define RADIO_STATE_STATE_Rx (3UL) /*!< RADIO is in the RX state */
+#define RADIO_STATE_STATE_RxDisable (4UL) /*!< RADIO is in the RXDISABLED state */
+#define RADIO_STATE_STATE_TxRu (9UL) /*!< RADIO is in the TXRU state */
+#define RADIO_STATE_STATE_TxIdle (10UL) /*!< RADIO is in the TXIDLE state */
+#define RADIO_STATE_STATE_Tx (11UL) /*!< RADIO is in the TX state */
+#define RADIO_STATE_STATE_TxDisable (12UL) /*!< RADIO is in the TXDISABLED state */
+
+/* Register: RADIO_DATAWHITEIV */
+/* Description: Data whitening initial value */
+
+/* Bits 6..0 : Data whitening initial value. Bit 6 is hard-wired to '1', writing '0' to it has no effect, and it will always be read back and used by the device as '1'. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
+#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
+
+/* Register: RADIO_BCC */
+/* Description: Bit counter compare */
+
+/* Bits 31..0 : Bit counter compare */
+#define RADIO_BCC_BCC_Pos (0UL) /*!< Position of BCC field. */
+#define RADIO_BCC_BCC_Msk (0xFFFFFFFFUL << RADIO_BCC_BCC_Pos) /*!< Bit mask of BCC field. */
+
+/* Register: RADIO_DAB */
+/* Description: Description collection[0]:  Device address base segment 0 */
+
+/* Bits 31..0 : Device address base segment 0 */
+#define RADIO_DAB_DAB_Pos (0UL) /*!< Position of DAB field. */
+#define RADIO_DAB_DAB_Msk (0xFFFFFFFFUL << RADIO_DAB_DAB_Pos) /*!< Bit mask of DAB field. */
+
+/* Register: RADIO_DAP */
+/* Description: Description collection[0]:  Device address prefix 0 */
+
+/* Bits 15..0 : Device address prefix 0 */
+#define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
+#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
+
+/* Register: RADIO_DACNF */
+/* Description: Device address match configuration */
+
+/* Bit 15 : TxAdd for device address 7 */
+#define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
+#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
+
+/* Bit 14 : TxAdd for device address 6 */
+#define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
+#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
+
+/* Bit 13 : TxAdd for device address 5 */
+#define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
+#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
+
+/* Bit 12 : TxAdd for device address 4 */
+#define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
+#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
+
+/* Bit 11 : TxAdd for device address 3 */
+#define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
+#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
+
+/* Bit 10 : TxAdd for device address 2 */
+#define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
+#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
+
+/* Bit 9 : TxAdd for device address 1 */
+#define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
+#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
+
+/* Bit 8 : TxAdd for device address 0 */
+#define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
+#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
+
+/* Bit 7 : Enable or disable device address matching using device address 7 */
+#define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
+#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
+#define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled */
+
+/* Bit 6 : Enable or disable device address matching using device address 6 */
+#define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
+#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
+#define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled */
+
+/* Bit 5 : Enable or disable device address matching using device address 5 */
+#define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
+#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
+#define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled */
+
+/* Bit 4 : Enable or disable device address matching using device address 4 */
+#define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
+#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
+#define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled */
+
+/* Bit 3 : Enable or disable device address matching using device address 3 */
+#define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
+#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
+#define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled */
+
+/* Bit 2 : Enable or disable device address matching using device address 2 */
+#define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
+#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
+#define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled */
+
+/* Bit 1 : Enable or disable device address matching using device address 1 */
+#define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
+#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
+#define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable device address matching using device address 0 */
+#define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
+#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
+#define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled */
+#define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled */
+
+/* Register: RADIO_MODECNF0 */
+/* Description: Radio mode configuration register 0 */
+
+/* Bits 9..8 : Default TX value */
+#define RADIO_MODECNF0_DTX_Pos (8UL) /*!< Position of DTX field. */
+#define RADIO_MODECNF0_DTX_Msk (0x3UL << RADIO_MODECNF0_DTX_Pos) /*!< Bit mask of DTX field. */
+#define RADIO_MODECNF0_DTX_B1 (0UL) /*!< Transmit '1' */
+#define RADIO_MODECNF0_DTX_B0 (1UL) /*!< Transmit '0' */
+#define RADIO_MODECNF0_DTX_Center (2UL) /*!< Transmit center frequency */
+
+/* Bit 0 : Radio ramp-up time */
+#define RADIO_MODECNF0_RU_Pos (0UL) /*!< Position of RU field. */
+#define RADIO_MODECNF0_RU_Msk (0x1UL << RADIO_MODECNF0_RU_Pos) /*!< Bit mask of RU field. */
+#define RADIO_MODECNF0_RU_Default (0UL) /*!< Default ramp-up time (tRXEN), compatible with firmware written for nRF51 */
+#define RADIO_MODECNF0_RU_Fast (1UL) /*!< Fast ramp-up (tRXEN,FAST), see electrical specification for more information */
+
+/* Register: RADIO_POWER */
+/* Description: Peripheral power control */
+
+/* Bit 0 : Peripheral power control. The peripheral and its registers will be reset to its initial state by switching the peripheral off and then back on again. */
+#define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
+#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
+#define RADIO_POWER_POWER_Disabled (0UL) /*!< Peripheral is powered off */
+#define RADIO_POWER_POWER_Enabled (1UL) /*!< Peripheral is powered on */
+
+
+/* Peripheral: RNG */
+/* Description: Random Number Generator */
+
+/* Register: RNG_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 0 : Shortcut between VALRDY event and STOP task */
+#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
+#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: RNG_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for VALRDY event */
+#define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable */
+
+/* Register: RNG_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for VALRDY event */
+#define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
+#define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Read: Disabled */
+#define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Read: Enabled */
+#define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable */
+
+/* Register: RNG_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 0 : Bias correction */
+#define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
+#define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Disabled */
+#define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Enabled */
+
+/* Register: RNG_VALUE */
+/* Description: Output random number */
+
+/* Bits 7..0 : Generated random number */
+#define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
+#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
+
+
+/* Peripheral: RTC */
+/* Description: Real time counter 0 */
+
+/* Register: RTC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for OVRFLW event */
+#define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for TICK event */
+#define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for OVRFLW event */
+#define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for TICK event */
+#define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_EVTEN */
+/* Description: Enable or disable event routing */
+
+/* Bit 19 : Enable or disable event routing for COMPARE[3] event */
+#define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable event routing for COMPARE[2] event */
+#define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable event routing for COMPARE[1] event */
+#define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable event routing for COMPARE[0] event */
+#define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable event routing for OVRFLW event */
+#define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable event routing for TICK event */
+#define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTEN_TICK_Disabled (0UL) /*!< Disable */
+#define RTC_EVTEN_TICK_Enabled (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENSET */
+/* Description: Enable event routing */
+
+/* Bit 19 : Write '1' to Enable event routing for COMPARE[3] event */
+#define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable event routing for COMPARE[2] event */
+#define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable event routing for COMPARE[1] event */
+#define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable event routing for COMPARE[0] event */
+#define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable event routing for OVRFLW event */
+#define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable event routing for TICK event */
+#define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable */
+
+/* Register: RTC_EVTENCLR */
+/* Description: Disable event routing */
+
+/* Bit 19 : Write '1' to Disable event routing for COMPARE[3] event */
+#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable event routing for COMPARE[2] event */
+#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable event routing for COMPARE[1] event */
+#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable event routing for COMPARE[0] event */
+#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable event routing for OVRFLW event */
+#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
+#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable event routing for TICK event */
+#define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
+#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
+#define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Read: Disabled */
+#define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Read: Enabled */
+#define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable */
+
+/* Register: RTC_COUNTER */
+/* Description: Current COUNTER value */
+
+/* Bits 23..0 : Counter value */
+#define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
+#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
+
+/* Register: RTC_PRESCALER */
+/* Description: 12 bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).Must be written when RTC is stopped */
+
+/* Bits 11..0 : Prescaler value */
+#define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: RTC_CC */
+/* Description: Description collection[0]:  Compare register 0 */
+
+/* Bits 23..0 : Compare value */
+#define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
+#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
+
+
+/* Peripheral: SAADC */
+/* Description: Analog to Digital Converter */
+
+/* Register: SAADC_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 21 : Enable or disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTEN_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Msk (0x1UL << SAADC_INTEN_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTEN_CH7LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTEN_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Msk (0x1UL << SAADC_INTEN_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTEN_CH7LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH7LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTEN_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Msk (0x1UL << SAADC_INTEN_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTEN_CH6LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTEN_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Msk (0x1UL << SAADC_INTEN_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTEN_CH6LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH6LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTEN_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Msk (0x1UL << SAADC_INTEN_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTEN_CH5LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 16 : Enable or disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTEN_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Msk (0x1UL << SAADC_INTEN_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTEN_CH5LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH5LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 15 : Enable or disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTEN_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Msk (0x1UL << SAADC_INTEN_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTEN_CH4LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 14 : Enable or disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTEN_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Msk (0x1UL << SAADC_INTEN_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTEN_CH4LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH4LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 13 : Enable or disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTEN_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Msk (0x1UL << SAADC_INTEN_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTEN_CH3LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 12 : Enable or disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTEN_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Msk (0x1UL << SAADC_INTEN_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTEN_CH3LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH3LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 11 : Enable or disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTEN_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Msk (0x1UL << SAADC_INTEN_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTEN_CH2LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 10 : Enable or disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTEN_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Msk (0x1UL << SAADC_INTEN_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTEN_CH2LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH2LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTEN_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Msk (0x1UL << SAADC_INTEN_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTEN_CH1LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTEN_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Msk (0x1UL << SAADC_INTEN_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTEN_CH1LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH1LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 7 : Enable or disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTEN_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Msk (0x1UL << SAADC_INTEN_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTEN_CH0LIMITL_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITL_Enabled (1UL) /*!< Enable */
+
+/* Bit 6 : Enable or disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTEN_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Msk (0x1UL << SAADC_INTEN_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTEN_CH0LIMITH_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CH0LIMITH_Enabled (1UL) /*!< Enable */
+
+/* Bit 5 : Enable or disable interrupt for STOPPED event */
+#define SAADC_INTEN_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Msk (0x1UL << SAADC_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTEN_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Msk (0x1UL << SAADC_INTEN_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTEN_CALIBRATEDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_CALIBRATEDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 3 : Enable or disable interrupt for RESULTDONE event */
+#define SAADC_INTEN_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Msk (0x1UL << SAADC_INTEN_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTEN_RESULTDONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_RESULTDONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 2 : Enable or disable interrupt for DONE event */
+#define SAADC_INTEN_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTEN_DONE_Msk (0x1UL << SAADC_INTEN_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTEN_DONE_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_DONE_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for END event */
+#define SAADC_INTEN_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTEN_END_Msk (0x1UL << SAADC_INTEN_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTEN_END_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_END_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for STARTED event */
+#define SAADC_INTEN_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTEN_STARTED_Msk (0x1UL << SAADC_INTEN_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTEN_STARTED_Disabled (0UL) /*!< Disable */
+#define SAADC_INTEN_STARTED_Enabled (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENSET_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Msk (0x1UL << SAADC_INTENSET_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENSET_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENSET_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Msk (0x1UL << SAADC_INTENSET_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENSET_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH7LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENSET_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Msk (0x1UL << SAADC_INTENSET_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENSET_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENSET_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Msk (0x1UL << SAADC_INTENSET_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENSET_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH6LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENSET_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Msk (0x1UL << SAADC_INTENSET_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENSET_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENSET_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Msk (0x1UL << SAADC_INTENSET_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENSET_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH5LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 15 : Write '1' to Enable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENSET_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Msk (0x1UL << SAADC_INTENSET_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENSET_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENSET_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Msk (0x1UL << SAADC_INTENSET_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENSET_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH4LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 13 : Write '1' to Enable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENSET_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Msk (0x1UL << SAADC_INTENSET_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENSET_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 12 : Write '1' to Enable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENSET_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Msk (0x1UL << SAADC_INTENSET_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENSET_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH3LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 11 : Write '1' to Enable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENSET_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Msk (0x1UL << SAADC_INTENSET_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENSET_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 10 : Write '1' to Enable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENSET_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Msk (0x1UL << SAADC_INTENSET_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENSET_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH2LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENSET_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Msk (0x1UL << SAADC_INTENSET_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENSET_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENSET_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Msk (0x1UL << SAADC_INTENSET_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENSET_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH1LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENSET_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Msk (0x1UL << SAADC_INTENSET_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENSET_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITL_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENSET_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Msk (0x1UL << SAADC_INTENSET_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENSET_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CH0LIMITH_Set (1UL) /*!< Enable */
+
+/* Bit 5 : Write '1' to Enable interrupt for STOPPED event */
+#define SAADC_INTENSET_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Msk (0x1UL << SAADC_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENSET_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENSET_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENSET_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_CALIBRATEDONE_Set (1UL) /*!< Enable */
+
+/* Bit 3 : Write '1' to Enable interrupt for RESULTDONE event */
+#define SAADC_INTENSET_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Msk (0x1UL << SAADC_INTENSET_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENSET_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_RESULTDONE_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for DONE event */
+#define SAADC_INTENSET_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENSET_DONE_Msk (0x1UL << SAADC_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENSET_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_DONE_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SAADC_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENSET_END_Msk (0x1UL << SAADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for STARTED event */
+#define SAADC_INTENSET_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENSET_STARTED_Msk (0x1UL << SAADC_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Register: SAADC_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for CH[7].LIMITL event */
+#define SAADC_INTENCLR_CH7LIMITL_Pos (21UL) /*!< Position of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITL_Pos) /*!< Bit mask of CH7LIMITL field. */
+#define SAADC_INTENCLR_CH7LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for CH[7].LIMITH event */
+#define SAADC_INTENCLR_CH7LIMITH_Pos (20UL) /*!< Position of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH7LIMITH_Pos) /*!< Bit mask of CH7LIMITH field. */
+#define SAADC_INTENCLR_CH7LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH7LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH7LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for CH[6].LIMITL event */
+#define SAADC_INTENCLR_CH6LIMITL_Pos (19UL) /*!< Position of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITL_Pos) /*!< Bit mask of CH6LIMITL field. */
+#define SAADC_INTENCLR_CH6LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for CH[6].LIMITH event */
+#define SAADC_INTENCLR_CH6LIMITH_Pos (18UL) /*!< Position of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH6LIMITH_Pos) /*!< Bit mask of CH6LIMITH field. */
+#define SAADC_INTENCLR_CH6LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH6LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH6LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for CH[5].LIMITL event */
+#define SAADC_INTENCLR_CH5LIMITL_Pos (17UL) /*!< Position of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITL_Pos) /*!< Bit mask of CH5LIMITL field. */
+#define SAADC_INTENCLR_CH5LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for CH[5].LIMITH event */
+#define SAADC_INTENCLR_CH5LIMITH_Pos (16UL) /*!< Position of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH5LIMITH_Pos) /*!< Bit mask of CH5LIMITH field. */
+#define SAADC_INTENCLR_CH5LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH5LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH5LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 15 : Write '1' to Disable interrupt for CH[4].LIMITL event */
+#define SAADC_INTENCLR_CH4LIMITL_Pos (15UL) /*!< Position of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITL_Pos) /*!< Bit mask of CH4LIMITL field. */
+#define SAADC_INTENCLR_CH4LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for CH[4].LIMITH event */
+#define SAADC_INTENCLR_CH4LIMITH_Pos (14UL) /*!< Position of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH4LIMITH_Pos) /*!< Bit mask of CH4LIMITH field. */
+#define SAADC_INTENCLR_CH4LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH4LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH4LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 13 : Write '1' to Disable interrupt for CH[3].LIMITL event */
+#define SAADC_INTENCLR_CH3LIMITL_Pos (13UL) /*!< Position of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITL_Pos) /*!< Bit mask of CH3LIMITL field. */
+#define SAADC_INTENCLR_CH3LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 12 : Write '1' to Disable interrupt for CH[3].LIMITH event */
+#define SAADC_INTENCLR_CH3LIMITH_Pos (12UL) /*!< Position of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH3LIMITH_Pos) /*!< Bit mask of CH3LIMITH field. */
+#define SAADC_INTENCLR_CH3LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH3LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH3LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 11 : Write '1' to Disable interrupt for CH[2].LIMITL event */
+#define SAADC_INTENCLR_CH2LIMITL_Pos (11UL) /*!< Position of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITL_Pos) /*!< Bit mask of CH2LIMITL field. */
+#define SAADC_INTENCLR_CH2LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 10 : Write '1' to Disable interrupt for CH[2].LIMITH event */
+#define SAADC_INTENCLR_CH2LIMITH_Pos (10UL) /*!< Position of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH2LIMITH_Pos) /*!< Bit mask of CH2LIMITH field. */
+#define SAADC_INTENCLR_CH2LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH2LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH2LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for CH[1].LIMITL event */
+#define SAADC_INTENCLR_CH1LIMITL_Pos (9UL) /*!< Position of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITL_Pos) /*!< Bit mask of CH1LIMITL field. */
+#define SAADC_INTENCLR_CH1LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for CH[1].LIMITH event */
+#define SAADC_INTENCLR_CH1LIMITH_Pos (8UL) /*!< Position of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH1LIMITH_Pos) /*!< Bit mask of CH1LIMITH field. */
+#define SAADC_INTENCLR_CH1LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH1LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH1LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for CH[0].LIMITL event */
+#define SAADC_INTENCLR_CH0LIMITL_Pos (7UL) /*!< Position of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITL_Pos) /*!< Bit mask of CH0LIMITL field. */
+#define SAADC_INTENCLR_CH0LIMITL_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITL_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITL_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for CH[0].LIMITH event */
+#define SAADC_INTENCLR_CH0LIMITH_Pos (6UL) /*!< Position of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Msk (0x1UL << SAADC_INTENCLR_CH0LIMITH_Pos) /*!< Bit mask of CH0LIMITH field. */
+#define SAADC_INTENCLR_CH0LIMITH_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CH0LIMITH_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CH0LIMITH_Clear (1UL) /*!< Disable */
+
+/* Bit 5 : Write '1' to Disable interrupt for STOPPED event */
+#define SAADC_INTENCLR_STOPPED_Pos (5UL) /*!< Position of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Msk (0x1UL << SAADC_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SAADC_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for CALIBRATEDONE event */
+#define SAADC_INTENCLR_CALIBRATEDONE_Pos (4UL) /*!< Position of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Msk (0x1UL << SAADC_INTENCLR_CALIBRATEDONE_Pos) /*!< Bit mask of CALIBRATEDONE field. */
+#define SAADC_INTENCLR_CALIBRATEDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_CALIBRATEDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 3 : Write '1' to Disable interrupt for RESULTDONE event */
+#define SAADC_INTENCLR_RESULTDONE_Pos (3UL) /*!< Position of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Msk (0x1UL << SAADC_INTENCLR_RESULTDONE_Pos) /*!< Bit mask of RESULTDONE field. */
+#define SAADC_INTENCLR_RESULTDONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_RESULTDONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_RESULTDONE_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for DONE event */
+#define SAADC_INTENCLR_DONE_Pos (2UL) /*!< Position of DONE field. */
+#define SAADC_INTENCLR_DONE_Msk (0x1UL << SAADC_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
+#define SAADC_INTENCLR_DONE_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_DONE_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_DONE_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SAADC_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SAADC_INTENCLR_END_Msk (0x1UL << SAADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SAADC_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for STARTED event */
+#define SAADC_INTENCLR_STARTED_Pos (0UL) /*!< Position of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Msk (0x1UL << SAADC_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SAADC_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SAADC_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SAADC_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Register: SAADC_STATUS */
+/* Description: Status */
+
+/* Bit 0 : Status */
+#define SAADC_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
+#define SAADC_STATUS_STATUS_Msk (0x1UL << SAADC_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
+#define SAADC_STATUS_STATUS_Ready (0UL) /*!< ADC is ready. No on-going conversion. */
+#define SAADC_STATUS_STATUS_Busy (1UL) /*!< ADC is busy. Conversion in progress. */
+
+/* Register: SAADC_ENABLE */
+/* Description: Enable or disable ADC */
+
+/* Bit 0 : Enable or disable ADC */
+#define SAADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Msk (0x1UL << SAADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SAADC_ENABLE_ENABLE_Disabled (0UL) /*!< Disable ADC */
+#define SAADC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable ADC */
+
+/* Register: SAADC_CH_PSELP */
+/* Description: Description cluster[0]:  Input positive pin selection for CH[0] */
+
+/* Bits 4..0 : Analog positive input channel */
+#define SAADC_CH_PSELP_PSELP_Pos (0UL) /*!< Position of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_Msk (0x1FUL << SAADC_CH_PSELP_PSELP_Pos) /*!< Bit mask of PSELP field. */
+#define SAADC_CH_PSELP_PSELP_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELP_PSELP_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELP_PSELP_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELP_PSELP_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_PSELN */
+/* Description: Description cluster[0]:  Input negative pin selection for CH[0] */
+
+/* Bits 4..0 : Analog negative input, enables differential channel */
+#define SAADC_CH_PSELN_PSELN_Pos (0UL) /*!< Position of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_Msk (0x1FUL << SAADC_CH_PSELN_PSELN_Pos) /*!< Bit mask of PSELN field. */
+#define SAADC_CH_PSELN_PSELN_NC (0UL) /*!< Not connected */
+#define SAADC_CH_PSELN_PSELN_AnalogInput0 (1UL) /*!< AIN0 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput1 (2UL) /*!< AIN1 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput2 (3UL) /*!< AIN2 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput3 (4UL) /*!< AIN3 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput4 (5UL) /*!< AIN4 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput5 (6UL) /*!< AIN5 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput6 (7UL) /*!< AIN6 */
+#define SAADC_CH_PSELN_PSELN_AnalogInput7 (8UL) /*!< AIN7 */
+#define SAADC_CH_PSELN_PSELN_VDD (9UL) /*!< VDD */
+
+/* Register: SAADC_CH_CONFIG */
+/* Description: Description cluster[0]:  Input configuration for CH[0] */
+
+/* Bit 24 : Enable burst mode */
+#define SAADC_CH_CONFIG_BURST_Pos (24UL) /*!< Position of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Msk (0x1UL << SAADC_CH_CONFIG_BURST_Pos) /*!< Bit mask of BURST field. */
+#define SAADC_CH_CONFIG_BURST_Disabled (0UL) /*!< Burst mode is disabled (normal operation) */
+#define SAADC_CH_CONFIG_BURST_Enabled (1UL) /*!< Burst mode is enabled. SAADC takes 2^OVERSAMPLE number of samples as fast as it can, and sends the average to Data RAM. */
+
+/* Bit 20 : Enable differential mode */
+#define SAADC_CH_CONFIG_MODE_Pos (20UL) /*!< Position of MODE field. */
+#define SAADC_CH_CONFIG_MODE_Msk (0x1UL << SAADC_CH_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_CH_CONFIG_MODE_SE (0UL) /*!< Single ended, PSELN will be ignored, negative input to ADC shorted to GND */
+#define SAADC_CH_CONFIG_MODE_Diff (1UL) /*!< Differential */
+
+/* Bits 18..16 : Acquisition time, the time the ADC uses to sample the input voltage */
+#define SAADC_CH_CONFIG_TACQ_Pos (16UL) /*!< Position of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_Msk (0x7UL << SAADC_CH_CONFIG_TACQ_Pos) /*!< Bit mask of TACQ field. */
+#define SAADC_CH_CONFIG_TACQ_3us (0UL) /*!< 3 us */
+#define SAADC_CH_CONFIG_TACQ_5us (1UL) /*!< 5 us */
+#define SAADC_CH_CONFIG_TACQ_10us (2UL) /*!< 10 us */
+#define SAADC_CH_CONFIG_TACQ_15us (3UL) /*!< 15 us */
+#define SAADC_CH_CONFIG_TACQ_20us (4UL) /*!< 20 us */
+#define SAADC_CH_CONFIG_TACQ_40us (5UL) /*!< 40 us */
+
+/* Bit 12 : Reference control */
+#define SAADC_CH_CONFIG_REFSEL_Pos (12UL) /*!< Position of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Msk (0x1UL << SAADC_CH_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
+#define SAADC_CH_CONFIG_REFSEL_Internal (0UL) /*!< Internal reference (0.6 V) */
+#define SAADC_CH_CONFIG_REFSEL_VDD1_4 (1UL) /*!< VDD/4 as reference */
+
+/* Bits 10..8 : Gain control */
+#define SAADC_CH_CONFIG_GAIN_Pos (8UL) /*!< Position of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Msk (0x7UL << SAADC_CH_CONFIG_GAIN_Pos) /*!< Bit mask of GAIN field. */
+#define SAADC_CH_CONFIG_GAIN_Gain1_6 (0UL) /*!< 1/6 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_5 (1UL) /*!< 1/5 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_4 (2UL) /*!< 1/4 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_3 (3UL) /*!< 1/3 */
+#define SAADC_CH_CONFIG_GAIN_Gain1_2 (4UL) /*!< 1/2 */
+#define SAADC_CH_CONFIG_GAIN_Gain1 (5UL) /*!< 1 */
+#define SAADC_CH_CONFIG_GAIN_Gain2 (6UL) /*!< 2 */
+#define SAADC_CH_CONFIG_GAIN_Gain4 (7UL) /*!< 4 */
+
+/* Bits 5..4 : Negative channel resistor control */
+#define SAADC_CH_CONFIG_RESN_Pos (4UL) /*!< Position of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Msk (0x3UL << SAADC_CH_CONFIG_RESN_Pos) /*!< Bit mask of RESN field. */
+#define SAADC_CH_CONFIG_RESN_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESN_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESN_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESN_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Bits 1..0 : Positive channel resistor control */
+#define SAADC_CH_CONFIG_RESP_Pos (0UL) /*!< Position of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Msk (0x3UL << SAADC_CH_CONFIG_RESP_Pos) /*!< Bit mask of RESP field. */
+#define SAADC_CH_CONFIG_RESP_Bypass (0UL) /*!< Bypass resistor ladder */
+#define SAADC_CH_CONFIG_RESP_Pulldown (1UL) /*!< Pull-down to GND */
+#define SAADC_CH_CONFIG_RESP_Pullup (2UL) /*!< Pull-up to VDD */
+#define SAADC_CH_CONFIG_RESP_VDD1_2 (3UL) /*!< Set input at VDD/2 */
+
+/* Register: SAADC_CH_LIMIT */
+/* Description: Description cluster[0]:  High/low limits for event monitoring a channel */
+
+/* Bits 31..16 : High level limit */
+#define SAADC_CH_LIMIT_HIGH_Pos (16UL) /*!< Position of HIGH field. */
+#define SAADC_CH_LIMIT_HIGH_Msk (0xFFFFUL << SAADC_CH_LIMIT_HIGH_Pos) /*!< Bit mask of HIGH field. */
+
+/* Bits 15..0 : Low level limit */
+#define SAADC_CH_LIMIT_LOW_Pos (0UL) /*!< Position of LOW field. */
+#define SAADC_CH_LIMIT_LOW_Msk (0xFFFFUL << SAADC_CH_LIMIT_LOW_Pos) /*!< Bit mask of LOW field. */
+
+/* Register: SAADC_RESOLUTION */
+/* Description: Resolution configuration */
+
+/* Bits 2..0 : Set the resolution */
+#define SAADC_RESOLUTION_VAL_Pos (0UL) /*!< Position of VAL field. */
+#define SAADC_RESOLUTION_VAL_Msk (0x7UL << SAADC_RESOLUTION_VAL_Pos) /*!< Bit mask of VAL field. */
+#define SAADC_RESOLUTION_VAL_8bit (0UL) /*!< 8 bit */
+#define SAADC_RESOLUTION_VAL_10bit (1UL) /*!< 10 bit */
+#define SAADC_RESOLUTION_VAL_12bit (2UL) /*!< 12 bit */
+#define SAADC_RESOLUTION_VAL_14bit (3UL) /*!< 14 bit */
+
+/* Register: SAADC_OVERSAMPLE */
+/* Description: Oversampling configuration. OVERSAMPLE should not be combined with SCAN. The RESOLUTION is applied before averaging, thus for high OVERSAMPLE a higher RESOLUTION should be used. */
+
+/* Bits 3..0 : Oversample control */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Pos (0UL) /*!< Position of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Msk (0xFUL << SAADC_OVERSAMPLE_OVERSAMPLE_Pos) /*!< Bit mask of OVERSAMPLE field. */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Bypass (0UL) /*!< Bypass oversampling */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over2x (1UL) /*!< Oversample 2x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over4x (2UL) /*!< Oversample 4x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over8x (3UL) /*!< Oversample 8x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over16x (4UL) /*!< Oversample 16x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over32x (5UL) /*!< Oversample 32x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over64x (6UL) /*!< Oversample 64x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over128x (7UL) /*!< Oversample 128x */
+#define SAADC_OVERSAMPLE_OVERSAMPLE_Over256x (8UL) /*!< Oversample 256x */
+
+/* Register: SAADC_SAMPLERATE */
+/* Description: Controls normal or continuous sample rate */
+
+/* Bit 12 : Select mode for sample rate control */
+#define SAADC_SAMPLERATE_MODE_Pos (12UL) /*!< Position of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Msk (0x1UL << SAADC_SAMPLERATE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define SAADC_SAMPLERATE_MODE_Task (0UL) /*!< Rate is controlled from SAMPLE task */
+#define SAADC_SAMPLERATE_MODE_Timers (1UL) /*!< Rate is controlled from local timer (use CC to control the rate) */
+
+/* Bits 10..0 : Capture and compare value. Sample rate is 16 MHz/CC */
+#define SAADC_SAMPLERATE_CC_Pos (0UL) /*!< Position of CC field. */
+#define SAADC_SAMPLERATE_CC_Msk (0x7FFUL << SAADC_SAMPLERATE_CC_Pos) /*!< Bit mask of CC field. */
+
+/* Register: SAADC_RESULT_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SAADC_RESULT_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SAADC_RESULT_PTR_PTR_Msk (0xFFFFFFFFUL << SAADC_RESULT_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SAADC_RESULT_MAXCNT */
+/* Description: Maximum number of buffer words to transfer */
+
+/* Bits 14..0 : Maximum number of buffer words to transfer */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SAADC_RESULT_MAXCNT_MAXCNT_Msk (0x7FFFUL << SAADC_RESULT_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SAADC_RESULT_AMOUNT */
+/* Description: Number of buffer words transferred since last START */
+
+/* Bits 14..0 : Number of buffer words transferred since last START. This register can be read after an END or STOPPED event. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SAADC_RESULT_AMOUNT_AMOUNT_Msk (0x7FFFUL << SAADC_RESULT_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+
+/* Peripheral: SPI */
+/* Description: Serial Peripheral Interface 0 */
+
+/* Register: SPI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 2 : Write '1' to Enable interrupt for READY event */
+#define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENSET_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENSET_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENSET_READY_Set (1UL) /*!< Enable */
+
+/* Register: SPI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 2 : Write '1' to Disable interrupt for READY event */
+#define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
+#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
+#define SPI_INTENCLR_READY_Disabled (0UL) /*!< Read: Disabled */
+#define SPI_INTENCLR_READY_Enabled (1UL) /*!< Read: Enabled */
+#define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable */
+
+/* Register: SPI_ENABLE */
+/* Description: Enable SPI */
+
+/* Bits 3..0 : Enable or disable SPI */
+#define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Msk (0xFUL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI */
+#define SPI_ENABLE_ENABLE_Enabled (1UL) /*!< Enable SPI */
+
+/* Register: SPI_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bits 31..0 : Pin number configuration for SPI SCK signal */
+#define SPI_PSEL_SCK_PSELSCK_Pos (0UL) /*!< Position of PSELSCK field. */
+#define SPI_PSEL_SCK_PSELSCK_Msk (0xFFFFFFFFUL << SPI_PSEL_SCK_PSELSCK_Pos) /*!< Bit mask of PSELSCK field. */
+#define SPI_PSEL_SCK_PSELSCK_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_PSEL_MOSI */
+/* Description: Pin select for MOSI */
+
+/* Bits 31..0 : Pin number configuration for SPI MOSI signal */
+#define SPI_PSEL_MOSI_PSELMOSI_Pos (0UL) /*!< Position of PSELMOSI field. */
+#define SPI_PSEL_MOSI_PSELMOSI_Msk (0xFFFFFFFFUL << SPI_PSEL_MOSI_PSELMOSI_Pos) /*!< Bit mask of PSELMOSI field. */
+#define SPI_PSEL_MOSI_PSELMOSI_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_PSEL_MISO */
+/* Description: Pin select for MISO */
+
+/* Bits 31..0 : Pin number configuration for SPI MISO signal */
+#define SPI_PSEL_MISO_PSELMISO_Pos (0UL) /*!< Position of PSELMISO field. */
+#define SPI_PSEL_MISO_PSELMISO_Msk (0xFFFFFFFFUL << SPI_PSEL_MISO_PSELMISO_Pos) /*!< Bit mask of PSELMISO field. */
+#define SPI_PSEL_MISO_PSELMISO_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: SPI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received. Double buffered */
+#define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: SPI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to send. Double buffered */
+#define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: SPI_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPI_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+
+/* Peripheral: SPIM */
+/* Description: Serial Peripheral Interface Master with EasyDMA 0 */
+
+/* Register: SPIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 17 : Shortcut between END event and START task */
+#define SPIM_SHORTS_END_START_Pos (17UL) /*!< Position of END_START field. */
+#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
+#define SPIM_SHORTS_END_START_Disabled (0UL) /*!< Disable shortcut */
+#define SPIM_SHORTS_END_START_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 19 : Write '1' to Enable interrupt for STARTED event */
+#define SPIM_INTENSET_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENSET_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STARTED_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define SPIM_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 6 : Write '1' to Enable interrupt for END event */
+#define SPIM_INTENSET_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIM_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define SPIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: SPIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 19 : Write '1' to Disable interrupt for STARTED event */
+#define SPIM_INTENCLR_STARTED_Pos (19UL) /*!< Position of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /*!< Bit mask of STARTED field. */
+#define SPIM_INTENCLR_STARTED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STARTED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define SPIM_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 6 : Write '1' to Disable interrupt for END event */
+#define SPIM_INTENCLR_END_Pos (6UL) /*!< Position of END field. */
+#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIM_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIM_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define SPIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: SPIM_ENABLE */
+/* Description: Enable SPIM */
+
+/* Bits 3..0 : Enable or disable SPIM */
+#define SPIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPIM */
+#define SPIM_ENABLE_ENABLE_Enabled (7UL) /*!< Enable SPIM */
+
+/* Register: SPIM_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Msk (0x1UL << SPIM_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_SCK_PIN_Msk (0x1FUL << SPIM_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIM_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MOSI_PIN_Msk (0x1FUL << SPIM_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIM_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Msk (0x1UL << SPIM_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIM_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIM_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIM_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIM_PSEL_MISO_PIN_Msk (0x1FUL << SPIM_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIM_FREQUENCY */
+/* Description: SPI frequency */
+
+/* Bits 31..0 : SPI master data rate */
+#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500 kbps */
+#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4 Mbps */
+#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8 Mbps */
+
+/* Register: SPIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define SPIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_RXD_LIST_LIST_Msk (0x7UL << SPIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define SPIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define SPIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define SPIM_TXD_LIST_LIST_Msk (0x7UL << SPIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define SPIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define SPIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: SPIM_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIM_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIM_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIM_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIM_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIM_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIM_ORC */
+/* Description: Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+
+/* Bits 7..0 : Over-read character. Character clocked out in case and over-read of the TXD buffer. */
+#define SPIM_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: SPIS */
+/* Description: SPI Slave 0 */
+
+/* Register: SPIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 2 : Shortcut between END event and ACQUIRE task */
+#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
+#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Disable shortcut */
+#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: SPIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 10 : Write '1' to Enable interrupt for ACQUIRED event */
+#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define SPIS_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Msk (0x1UL << SPIS_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for END event */
+#define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENSET_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENSET_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENSET_END_Set (1UL) /*!< Enable */
+
+/* Register: SPIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 10 : Write '1' to Disable interrupt for ACQUIRED event */
+#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
+#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define SPIS_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Msk (0x1UL << SPIS_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define SPIS_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for END event */
+#define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
+#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
+#define SPIS_INTENCLR_END_Disabled (0UL) /*!< Read: Disabled */
+#define SPIS_INTENCLR_END_Enabled (1UL) /*!< Read: Enabled */
+#define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable */
+
+/* Register: SPIS_SEMSTAT */
+/* Description: Semaphore status register */
+
+/* Bits 1..0 : Semaphore status */
+#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
+#define SPIS_SEMSTAT_SEMSTAT_Free (0UL) /*!< Semaphore is free */
+#define SPIS_SEMSTAT_SEMSTAT_CPU (1UL) /*!< Semaphore is assigned to CPU */
+#define SPIS_SEMSTAT_SEMSTAT_SPIS (2UL) /*!< Semaphore is assigned to SPI slave */
+#define SPIS_SEMSTAT_SEMSTAT_CPUPending (3UL) /*!< Semaphore is assigned to SPI but a handover to the CPU is pending */
+
+/* Register: SPIS_STATUS */
+/* Description: Status from last transaction */
+
+/* Bit 1 : RX buffer overflow detected, and prevented */
+#define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Bit 0 : TX buffer over-read detected, and prevented */
+#define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Read: error not present */
+#define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Read: error present */
+#define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Write: clear error on writing '1' */
+
+/* Register: SPIS_ENABLE */
+/* Description: Enable SPI slave */
+
+/* Bits 3..0 : Enable or disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Msk (0xFUL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define SPIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable SPI slave */
+#define SPIS_ENABLE_ENABLE_Enabled (2UL) /*!< Enable SPI slave */
+
+/* Register: SPIS_PSEL_SCK */
+/* Description: Pin select for SCK */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_SCK_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Msk (0x1UL << SPIS_PSEL_SCK_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_SCK_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_SCK_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_SCK_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_SCK_PIN_Msk (0x1FUL << SPIS_PSEL_SCK_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MISO */
+/* Description: Pin select for MISO signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MISO_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Msk (0x1UL << SPIS_PSEL_MISO_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MISO_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MISO_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MISO_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MISO_PIN_Msk (0x1FUL << SPIS_PSEL_MISO_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_MOSI */
+/* Description: Pin select for MOSI signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_MOSI_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Msk (0x1UL << SPIS_PSEL_MOSI_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_MOSI_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_MOSI_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_MOSI_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_MOSI_PIN_Msk (0x1FUL << SPIS_PSEL_MOSI_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_PSEL_CSN */
+/* Description: Pin select for CSN signal */
+
+/* Bit 31 : Connection */
+#define SPIS_PSEL_CSN_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Msk (0x1UL << SPIS_PSEL_CSN_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define SPIS_PSEL_CSN_CONNECT_Connected (0UL) /*!< Connect */
+#define SPIS_PSEL_CSN_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define SPIS_PSEL_CSN_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define SPIS_PSEL_CSN_PIN_Msk (0x1FUL << SPIS_PSEL_CSN_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: SPIS_RXD_PTR */
+/* Description: RXD data pointer */
+
+/* Bits 31..0 : RXD data pointer */
+#define SPIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define SPIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_RXD_AMOUNT */
+/* Description: Number of bytes received in last granted transaction */
+
+/* Bits 7..0 : Number of bytes received in the last granted transaction */
+#define SPIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_TXD_PTR */
+/* Description: TXD data pointer */
+
+/* Bits 31..0 : TXD data pointer */
+#define SPIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define SPIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: SPIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define SPIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define SPIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: SPIS_TXD_AMOUNT */
+/* Description: Number of bytes transmitted in last granted transaction */
+
+/* Bits 7..0 : Number of bytes transmitted in last granted transaction */
+#define SPIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define SPIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: SPIS_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 2 : Serial clock (SCK) polarity */
+#define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
+#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
+#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high */
+#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low */
+
+/* Bit 1 : Serial clock (SCK) phase */
+#define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
+#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
+#define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of clock, shift serial data on trailing edge */
+#define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of clock, shift serial data on leading edge */
+
+/* Bit 0 : Bit order */
+#define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
+#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
+#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit shifted out first */
+#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit shifted out first */
+
+/* Register: SPIS_DEF */
+/* Description: Default character. Character clocked out in case of an ignored transaction. */
+
+/* Bits 7..0 : Default character. Character clocked out in case of an ignored transaction. */
+#define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
+#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
+
+/* Register: SPIS_ORC */
+/* Description: Over-read character */
+
+/* Bits 7..0 : Over-read character. Character clocked out after an over-read of the transmit buffer. */
+#define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: TEMP */
+/* Description: Temperature Sensor */
+
+/* Register: TEMP_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for DATARDY event */
+#define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable */
+
+/* Register: TEMP_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for DATARDY event */
+#define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
+#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Read: Disabled */
+#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Read: Enabled */
+#define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable */
+
+/* Register: TEMP_TEMP */
+/* Description: Temperature in degC (0.25deg steps) */
+
+/* Bits 31..0 : Temperature in degC (0.25deg steps) */
+#define TEMP_TEMP_TEMP_Pos (0UL) /*!< Position of TEMP field. */
+#define TEMP_TEMP_TEMP_Msk (0xFFFFFFFFUL << TEMP_TEMP_TEMP_Pos) /*!< Bit mask of TEMP field. */
+
+/* Register: TEMP_A0 */
+/* Description: Slope of 1st piece wise linear function */
+
+/* Bits 11..0 : Slope of 1st piece wise linear function */
+#define TEMP_A0_A0_Pos (0UL) /*!< Position of A0 field. */
+#define TEMP_A0_A0_Msk (0xFFFUL << TEMP_A0_A0_Pos) /*!< Bit mask of A0 field. */
+
+/* Register: TEMP_A1 */
+/* Description: Slope of 2nd piece wise linear function */
+
+/* Bits 11..0 : Slope of 2nd piece wise linear function */
+#define TEMP_A1_A1_Pos (0UL) /*!< Position of A1 field. */
+#define TEMP_A1_A1_Msk (0xFFFUL << TEMP_A1_A1_Pos) /*!< Bit mask of A1 field. */
+
+/* Register: TEMP_A2 */
+/* Description: Slope of 3rd piece wise linear function */
+
+/* Bits 11..0 : Slope of 3rd piece wise linear function */
+#define TEMP_A2_A2_Pos (0UL) /*!< Position of A2 field. */
+#define TEMP_A2_A2_Msk (0xFFFUL << TEMP_A2_A2_Pos) /*!< Bit mask of A2 field. */
+
+/* Register: TEMP_A3 */
+/* Description: Slope of 4th piece wise linear function */
+
+/* Bits 11..0 : Slope of 4th piece wise linear function */
+#define TEMP_A3_A3_Pos (0UL) /*!< Position of A3 field. */
+#define TEMP_A3_A3_Msk (0xFFFUL << TEMP_A3_A3_Pos) /*!< Bit mask of A3 field. */
+
+/* Register: TEMP_A4 */
+/* Description: Slope of 5th piece wise linear function */
+
+/* Bits 11..0 : Slope of 5th piece wise linear function */
+#define TEMP_A4_A4_Pos (0UL) /*!< Position of A4 field. */
+#define TEMP_A4_A4_Msk (0xFFFUL << TEMP_A4_A4_Pos) /*!< Bit mask of A4 field. */
+
+/* Register: TEMP_A5 */
+/* Description: Slope of 6th piece wise linear function */
+
+/* Bits 11..0 : Slope of 6th piece wise linear function */
+#define TEMP_A5_A5_Pos (0UL) /*!< Position of A5 field. */
+#define TEMP_A5_A5_Msk (0xFFFUL << TEMP_A5_A5_Pos) /*!< Bit mask of A5 field. */
+
+/* Register: TEMP_B0 */
+/* Description: y-intercept of 1st piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 1st piece wise linear function */
+#define TEMP_B0_B0_Pos (0UL) /*!< Position of B0 field. */
+#define TEMP_B0_B0_Msk (0x3FFFUL << TEMP_B0_B0_Pos) /*!< Bit mask of B0 field. */
+
+/* Register: TEMP_B1 */
+/* Description: y-intercept of 2nd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 2nd piece wise linear function */
+#define TEMP_B1_B1_Pos (0UL) /*!< Position of B1 field. */
+#define TEMP_B1_B1_Msk (0x3FFFUL << TEMP_B1_B1_Pos) /*!< Bit mask of B1 field. */
+
+/* Register: TEMP_B2 */
+/* Description: y-intercept of 3rd piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 3rd piece wise linear function */
+#define TEMP_B2_B2_Pos (0UL) /*!< Position of B2 field. */
+#define TEMP_B2_B2_Msk (0x3FFFUL << TEMP_B2_B2_Pos) /*!< Bit mask of B2 field. */
+
+/* Register: TEMP_B3 */
+/* Description: y-intercept of 4th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 4th piece wise linear function */
+#define TEMP_B3_B3_Pos (0UL) /*!< Position of B3 field. */
+#define TEMP_B3_B3_Msk (0x3FFFUL << TEMP_B3_B3_Pos) /*!< Bit mask of B3 field. */
+
+/* Register: TEMP_B4 */
+/* Description: y-intercept of 5th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 5th piece wise linear function */
+#define TEMP_B4_B4_Pos (0UL) /*!< Position of B4 field. */
+#define TEMP_B4_B4_Msk (0x3FFFUL << TEMP_B4_B4_Pos) /*!< Bit mask of B4 field. */
+
+/* Register: TEMP_B5 */
+/* Description: y-intercept of 6th piece wise linear function */
+
+/* Bits 13..0 : y-intercept of 6th piece wise linear function */
+#define TEMP_B5_B5_Pos (0UL) /*!< Position of B5 field. */
+#define TEMP_B5_B5_Msk (0x3FFFUL << TEMP_B5_B5_Pos) /*!< Bit mask of B5 field. */
+
+/* Register: TEMP_T0 */
+/* Description: End point of 1st piece wise linear function */
+
+/* Bits 7..0 : End point of 1st piece wise linear function */
+#define TEMP_T0_T0_Pos (0UL) /*!< Position of T0 field. */
+#define TEMP_T0_T0_Msk (0xFFUL << TEMP_T0_T0_Pos) /*!< Bit mask of T0 field. */
+
+/* Register: TEMP_T1 */
+/* Description: End point of 2nd piece wise linear function */
+
+/* Bits 7..0 : End point of 2nd piece wise linear function */
+#define TEMP_T1_T1_Pos (0UL) /*!< Position of T1 field. */
+#define TEMP_T1_T1_Msk (0xFFUL << TEMP_T1_T1_Pos) /*!< Bit mask of T1 field. */
+
+/* Register: TEMP_T2 */
+/* Description: End point of 3rd piece wise linear function */
+
+/* Bits 7..0 : End point of 3rd piece wise linear function */
+#define TEMP_T2_T2_Pos (0UL) /*!< Position of T2 field. */
+#define TEMP_T2_T2_Msk (0xFFUL << TEMP_T2_T2_Pos) /*!< Bit mask of T2 field. */
+
+/* Register: TEMP_T3 */
+/* Description: End point of 4th piece wise linear function */
+
+/* Bits 7..0 : End point of 4th piece wise linear function */
+#define TEMP_T3_T3_Pos (0UL) /*!< Position of T3 field. */
+#define TEMP_T3_T3_Msk (0xFFUL << TEMP_T3_T3_Pos) /*!< Bit mask of T3 field. */
+
+/* Register: TEMP_T4 */
+/* Description: End point of 5th piece wise linear function */
+
+/* Bits 7..0 : End point of 5th piece wise linear function */
+#define TEMP_T4_T4_Pos (0UL) /*!< Position of T4 field. */
+#define TEMP_T4_T4_Msk (0xFFUL << TEMP_T4_T4_Pos) /*!< Bit mask of T4 field. */
+
+
+/* Peripheral: TIMER */
+/* Description: Timer/Counter 0 */
+
+/* Register: TIMER_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 13 : Shortcut between COMPARE[5] event and STOP task */
+#define TIMER_SHORTS_COMPARE5_STOP_Pos (13UL) /*!< Position of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE5_STOP_Pos) /*!< Bit mask of COMPARE5_STOP field. */
+#define TIMER_SHORTS_COMPARE5_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 12 : Shortcut between COMPARE[4] event and STOP task */
+#define TIMER_SHORTS_COMPARE4_STOP_Pos (12UL) /*!< Position of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE4_STOP_Pos) /*!< Bit mask of COMPARE4_STOP field. */
+#define TIMER_SHORTS_COMPARE4_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 11 : Shortcut between COMPARE[3] event and STOP task */
+#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
+#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between COMPARE[2] event and STOP task */
+#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
+#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between COMPARE[1] event and STOP task */
+#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
+#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between COMPARE[0] event and STOP task */
+#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
+#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between COMPARE[5] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Pos (5UL) /*!< Position of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE5_CLEAR_Pos) /*!< Bit mask of COMPARE5_CLEAR field. */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE5_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 4 : Shortcut between COMPARE[4] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Pos (4UL) /*!< Position of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE4_CLEAR_Pos) /*!< Bit mask of COMPARE4_CLEAR field. */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE4_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between COMPARE[3] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 2 : Shortcut between COMPARE[2] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 1 : Shortcut between COMPARE[1] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between COMPARE[0] event and CLEAR task */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Disable shortcut */
+#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TIMER_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 21 : Write '1' to Enable interrupt for COMPARE[5] event */
+#define TIMER_INTENSET_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Msk (0x1UL << TIMER_INTENSET_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENSET_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE5_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for COMPARE[4] event */
+#define TIMER_INTENSET_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Msk (0x1UL << TIMER_INTENSET_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENSET_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE4_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for COMPARE[3] event */
+#define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for COMPARE[2] event */
+#define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for COMPARE[1] event */
+#define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable */
+
+/* Bit 16 : Write '1' to Enable interrupt for COMPARE[0] event */
+#define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable */
+
+/* Register: TIMER_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 21 : Write '1' to Disable interrupt for COMPARE[5] event */
+#define TIMER_INTENCLR_COMPARE5_Pos (21UL) /*!< Position of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Msk (0x1UL << TIMER_INTENCLR_COMPARE5_Pos) /*!< Bit mask of COMPARE5 field. */
+#define TIMER_INTENCLR_COMPARE5_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE5_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE5_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for COMPARE[4] event */
+#define TIMER_INTENCLR_COMPARE4_Pos (20UL) /*!< Position of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Msk (0x1UL << TIMER_INTENCLR_COMPARE4_Pos) /*!< Bit mask of COMPARE4 field. */
+#define TIMER_INTENCLR_COMPARE4_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE4_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE4_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for COMPARE[3] event */
+#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
+#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for COMPARE[2] event */
+#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
+#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for COMPARE[1] event */
+#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
+#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable */
+
+/* Bit 16 : Write '1' to Disable interrupt for COMPARE[0] event */
+#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
+#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Read: Disabled */
+#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Read: Enabled */
+#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable */
+
+/* Register: TIMER_MODE */
+/* Description: Timer mode selection */
+
+/* Bits 1..0 : Timer mode */
+#define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
+#define TIMER_MODE_MODE_Msk (0x3UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
+#define TIMER_MODE_MODE_Timer (0UL) /*!< Select Timer mode */
+#define TIMER_MODE_MODE_Counter (1UL) /*!< Deprecated enumerator -  Select Counter mode */
+#define TIMER_MODE_MODE_LowPowerCounter (2UL) /*!< Select Low Power Counter mode */
+
+/* Register: TIMER_BITMODE */
+/* Description: Configure the number of bits used by the TIMER */
+
+/* Bits 1..0 : Timer bit width */
+#define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
+#define TIMER_BITMODE_BITMODE_16Bit (0UL) /*!< 16 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_08Bit (1UL) /*!< 8 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_24Bit (2UL) /*!< 24 bit timer bit width */
+#define TIMER_BITMODE_BITMODE_32Bit (3UL) /*!< 32 bit timer bit width */
+
+/* Register: TIMER_PRESCALER */
+/* Description: Timer prescaler register */
+
+/* Bits 3..0 : Prescaler value */
+#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
+#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
+
+/* Register: TIMER_CC */
+/* Description: Description collection[0]:  Capture/Compare register 0 */
+
+/* Bits 31..0 : Capture/Compare value */
+#define TIMER_CC_CC_Pos (0UL) /*!< Position of CC field. */
+#define TIMER_CC_CC_Msk (0xFFFFFFFFUL << TIMER_CC_CC_Pos) /*!< Bit mask of CC field. */
+
+
+/* Peripheral: TWI */
+/* Description: I2C compatible Two-Wire Interface 0 */
+
+/* Register: TWI_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 1 : Shortcut between BB event and STOP task */
+#define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
+#define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 0 : Shortcut between BB event and SUSPEND task */
+#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
+#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWI_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWI_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 14 : Write '1' to Enable interrupt for BB event */
+#define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENSET_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_BB_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDSENT event */
+#define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDREADY event */
+#define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWI_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 14 : Write '1' to Disable interrupt for BB event */
+#define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
+#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
+#define TWI_INTENCLR_BB_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_BB_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDSENT event */
+#define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
+#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDREADY event */
+#define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
+#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWI_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Read: error not present */
+#define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define TWI_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_Msk (0x1UL << TWI_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define TWI_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: no overrun occured */
+#define TWI_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: overrun occured */
+
+/* Register: TWI_ENABLE */
+/* Description: Enable TWI */
+
+/* Bits 3..0 : Enable or disable TWI */
+#define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Msk (0xFUL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWI_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWI */
+#define TWI_ENABLE_ENABLE_Enabled (5UL) /*!< Enable TWI */
+
+/* Register: TWI_PSELSCL */
+/* Description: Pin select for SCL */
+
+/* Bits 31..0 : Pin number configuration for TWI SCL signal */
+#define TWI_PSELSCL_PSELSCL_Pos (0UL) /*!< Position of PSELSCL field. */
+#define TWI_PSELSCL_PSELSCL_Msk (0xFFFFFFFFUL << TWI_PSELSCL_PSELSCL_Pos) /*!< Bit mask of PSELSCL field. */
+#define TWI_PSELSCL_PSELSCL_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: TWI_PSELSDA */
+/* Description: Pin select for SDA */
+
+/* Bits 31..0 : Pin number configuration for TWI SDA signal */
+#define TWI_PSELSDA_PSELSDA_Pos (0UL) /*!< Position of PSELSDA field. */
+#define TWI_PSELSDA_PSELSDA_Msk (0xFFFFFFFFUL << TWI_PSELSDA_PSELSDA_Pos) /*!< Bit mask of PSELSDA field. */
+#define TWI_PSELSDA_PSELSDA_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: TWI_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RXD register */
+#define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: TWI_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TXD register */
+#define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: TWI_FREQUENCY */
+/* Description: TWI frequency */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps (actual rate 410.256 kbps) */
+
+/* Register: TWI_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIM */
+/* Description: I2C compatible Two-Wire Master Interface with EasyDMA 0 */
+
+/* Register: TWIM_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 12 : Shortcut between LASTRX event and STOP task */
+#define TWIM_SHORTS_LASTRX_STOP_Pos (12UL) /*!< Position of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTRX_STOP_Pos) /*!< Bit mask of LASTRX_STOP field. */
+#define TWIM_SHORTS_LASTRX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 10 : Shortcut between LASTRX event and STARTTX task */
+#define TWIM_SHORTS_LASTRX_STARTTX_Pos (10UL) /*!< Position of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Msk (0x1UL << TWIM_SHORTS_LASTRX_STARTTX_Pos) /*!< Bit mask of LASTRX_STARTTX field. */
+#define TWIM_SHORTS_LASTRX_STARTTX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTRX_STARTTX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 9 : Shortcut between LASTTX event and STOP task */
+#define TWIM_SHORTS_LASTTX_STOP_Pos (9UL) /*!< Position of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Msk (0x1UL << TWIM_SHORTS_LASTTX_STOP_Pos) /*!< Bit mask of LASTTX_STOP field. */
+#define TWIM_SHORTS_LASTTX_STOP_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STOP_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 8 : Shortcut between LASTTX event and SUSPEND task */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Pos (8UL) /*!< Position of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Msk (0x1UL << TWIM_SHORTS_LASTTX_SUSPEND_Pos) /*!< Bit mask of LASTTX_SUSPEND field. */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 7 : Shortcut between LASTTX event and STARTRX task */
+#define TWIM_SHORTS_LASTTX_STARTRX_Pos (7UL) /*!< Position of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Msk (0x1UL << TWIM_SHORTS_LASTTX_STARTRX_Pos) /*!< Bit mask of LASTTX_STARTRX field. */
+#define TWIM_SHORTS_LASTTX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define TWIM_SHORTS_LASTTX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIM_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 24 : Enable or disable interrupt for LASTTX event */
+#define TWIM_INTEN_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Msk (0x1UL << TWIM_INTEN_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTEN_LASTTX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 23 : Enable or disable interrupt for LASTRX event */
+#define TWIM_INTEN_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Msk (0x1UL << TWIM_INTEN_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTEN_LASTRX_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_LASTRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIM_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Msk (0x1UL << TWIM_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIM_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Msk (0x1UL << TWIM_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 18 : Enable or disable interrupt for SUSPENDED event */
+#define TWIM_INTEN_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Msk (0x1UL << TWIM_INTEN_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTEN_SUSPENDED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_SUSPENDED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIM_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTEN_ERROR_Msk (0x1UL << TWIM_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIM_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Msk (0x1UL << TWIM_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIM_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 24 : Write '1' to Enable interrupt for LASTTX event */
+#define TWIM_INTENSET_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Msk (0x1UL << TWIM_INTENSET_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENSET_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTTX_Set (1UL) /*!< Enable */
+
+/* Bit 23 : Write '1' to Enable interrupt for LASTRX event */
+#define TWIM_INTENSET_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Msk (0x1UL << TWIM_INTENSET_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENSET_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_LASTRX_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIM_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Msk (0x1UL << TWIM_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIM_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Msk (0x1UL << TWIM_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 18 : Write '1' to Enable interrupt for SUSPENDED event */
+#define TWIM_INTENSET_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Msk (0x1UL << TWIM_INTENSET_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENSET_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_SUSPENDED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIM_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENSET_ERROR_Msk (0x1UL << TWIM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIM_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Msk (0x1UL << TWIM_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIM_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 24 : Write '1' to Disable interrupt for LASTTX event */
+#define TWIM_INTENCLR_LASTTX_Pos (24UL) /*!< Position of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Msk (0x1UL << TWIM_INTENCLR_LASTTX_Pos) /*!< Bit mask of LASTTX field. */
+#define TWIM_INTENCLR_LASTTX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTTX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTTX_Clear (1UL) /*!< Disable */
+
+/* Bit 23 : Write '1' to Disable interrupt for LASTRX event */
+#define TWIM_INTENCLR_LASTRX_Pos (23UL) /*!< Position of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Msk (0x1UL << TWIM_INTENCLR_LASTRX_Pos) /*!< Bit mask of LASTRX field. */
+#define TWIM_INTENCLR_LASTRX_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_LASTRX_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_LASTRX_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIM_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Msk (0x1UL << TWIM_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIM_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIM_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Msk (0x1UL << TWIM_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIM_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 18 : Write '1' to Disable interrupt for SUSPENDED event */
+#define TWIM_INTENCLR_SUSPENDED_Pos (18UL) /*!< Position of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Msk (0x1UL << TWIM_INTENCLR_SUSPENDED_Pos) /*!< Bit mask of SUSPENDED field. */
+#define TWIM_INTENCLR_SUSPENDED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_SUSPENDED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_SUSPENDED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIM_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Msk (0x1UL << TWIM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIM_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIM_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Msk (0x1UL << TWIM_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIM_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIM_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIM_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIM_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 2 : NACK received after sending a data byte (write '1' to clear) */
+#define TWIM_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_Msk (0x1UL << TWIM_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIM_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 1 : NACK received after sending the address (write '1' to clear) */
+#define TWIM_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_Msk (0x1UL << TWIM_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
+#define TWIM_ERRORSRC_ANACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIM_ERRORSRC_ANACK_Received (1UL) /*!< Error occurred */
+
+/* Register: TWIM_ENABLE */
+/* Description: Enable TWIM */
+
+/* Bits 3..0 : Enable or disable TWIM */
+#define TWIM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Msk (0xFUL << TWIM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIM_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIM */
+#define TWIM_ENABLE_ENABLE_Enabled (6UL) /*!< Enable TWIM */
+
+/* Register: TWIM_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Msk (0x1UL << TWIM_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SCL_PIN_Msk (0x1FUL << TWIM_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIM_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Msk (0x1UL << TWIM_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIM_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIM_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIM_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIM_PSEL_SDA_PIN_Msk (0x1FUL << TWIM_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIM_FREQUENCY */
+/* Description: TWI frequency */
+
+/* Bits 31..0 : TWI master clock frequency */
+#define TWIM_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWIM_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
+#define TWIM_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps */
+#define TWIM_FREQUENCY_FREQUENCY_K400 (0x06400000UL) /*!< 400 kbps */
+
+/* Register: TWIM_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define TWIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_RXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_RXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_RXD_LIST_LIST_Msk (0x7UL << TWIM_RXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_RXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_RXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define TWIM_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIM_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIM_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define TWIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIM_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIM_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction. In case of NACK error, includes the NACK'ed byte. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIM_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIM_TXD_LIST */
+/* Description: EasyDMA list type */
+
+/* Bits 2..0 : List type */
+#define TWIM_TXD_LIST_LIST_Pos (0UL) /*!< Position of LIST field. */
+#define TWIM_TXD_LIST_LIST_Msk (0x7UL << TWIM_TXD_LIST_LIST_Pos) /*!< Bit mask of LIST field. */
+#define TWIM_TXD_LIST_LIST_Disabled (0UL) /*!< Disable EasyDMA list */
+#define TWIM_TXD_LIST_LIST_ArrayList (1UL) /*!< Use array list */
+
+/* Register: TWIM_ADDRESS */
+/* Description: Address used in the TWI transfer */
+
+/* Bits 6..0 : Address used in the TWI transfer */
+#define TWIM_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIM_ADDRESS_ADDRESS_Msk (0x7FUL << TWIM_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+
+/* Peripheral: TWIS */
+/* Description: I2C compatible Two-Wire Slave Interface with EasyDMA 0 */
+
+/* Register: TWIS_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 14 : Shortcut between READ event and SUSPEND task */
+#define TWIS_SHORTS_READ_SUSPEND_Pos (14UL) /*!< Position of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Msk (0x1UL << TWIS_SHORTS_READ_SUSPEND_Pos) /*!< Bit mask of READ_SUSPEND field. */
+#define TWIS_SHORTS_READ_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_READ_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 13 : Shortcut between WRITE event and SUSPEND task */
+#define TWIS_SHORTS_WRITE_SUSPEND_Pos (13UL) /*!< Position of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Msk (0x1UL << TWIS_SHORTS_WRITE_SUSPEND_Pos) /*!< Bit mask of WRITE_SUSPEND field. */
+#define TWIS_SHORTS_WRITE_SUSPEND_Disabled (0UL) /*!< Disable shortcut */
+#define TWIS_SHORTS_WRITE_SUSPEND_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: TWIS_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 26 : Enable or disable interrupt for READ event */
+#define TWIS_INTEN_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTEN_READ_Msk (0x1UL << TWIS_INTEN_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTEN_READ_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_READ_Enabled (1UL) /*!< Enable */
+
+/* Bit 25 : Enable or disable interrupt for WRITE event */
+#define TWIS_INTEN_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTEN_WRITE_Msk (0x1UL << TWIS_INTEN_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTEN_WRITE_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_WRITE_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define TWIS_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Msk (0x1UL << TWIS_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define TWIS_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Msk (0x1UL << TWIS_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define TWIS_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTEN_ERROR_Msk (0x1UL << TWIS_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for STOPPED event */
+#define TWIS_INTEN_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Msk (0x1UL << TWIS_INTEN_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTEN_STOPPED_Disabled (0UL) /*!< Disable */
+#define TWIS_INTEN_STOPPED_Enabled (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 26 : Write '1' to Enable interrupt for READ event */
+#define TWIS_INTENSET_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENSET_READ_Msk (0x1UL << TWIS_INTENSET_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENSET_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_READ_Set (1UL) /*!< Enable */
+
+/* Bit 25 : Write '1' to Enable interrupt for WRITE event */
+#define TWIS_INTENSET_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENSET_WRITE_Msk (0x1UL << TWIS_INTENSET_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENSET_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_WRITE_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define TWIS_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Msk (0x1UL << TWIS_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define TWIS_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Msk (0x1UL << TWIS_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define TWIS_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENSET_ERROR_Msk (0x1UL << TWIS_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for STOPPED event */
+#define TWIS_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Msk (0x1UL << TWIS_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENSET_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENSET_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENSET_STOPPED_Set (1UL) /*!< Enable */
+
+/* Register: TWIS_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 26 : Write '1' to Disable interrupt for READ event */
+#define TWIS_INTENCLR_READ_Pos (26UL) /*!< Position of READ field. */
+#define TWIS_INTENCLR_READ_Msk (0x1UL << TWIS_INTENCLR_READ_Pos) /*!< Bit mask of READ field. */
+#define TWIS_INTENCLR_READ_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_READ_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_READ_Clear (1UL) /*!< Disable */
+
+/* Bit 25 : Write '1' to Disable interrupt for WRITE event */
+#define TWIS_INTENCLR_WRITE_Pos (25UL) /*!< Position of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Msk (0x1UL << TWIS_INTENCLR_WRITE_Pos) /*!< Bit mask of WRITE field. */
+#define TWIS_INTENCLR_WRITE_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_WRITE_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_WRITE_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define TWIS_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Msk (0x1UL << TWIS_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define TWIS_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define TWIS_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Msk (0x1UL << TWIS_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define TWIS_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define TWIS_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Msk (0x1UL << TWIS_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define TWIS_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for STOPPED event */
+#define TWIS_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Msk (0x1UL << TWIS_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
+#define TWIS_INTENCLR_STOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define TWIS_INTENCLR_STOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define TWIS_INTENCLR_STOPPED_Clear (1UL) /*!< Disable */
+
+/* Register: TWIS_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : TX buffer over-read detected, and prevented */
+#define TWIS_ERRORSRC_OVERREAD_Pos (3UL) /*!< Position of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_Msk (0x1UL << TWIS_ERRORSRC_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
+#define TWIS_ERRORSRC_OVERREAD_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERREAD_Detected (1UL) /*!< Error occurred */
+
+/* Bit 2 : NACK sent after receiving a data byte */
+#define TWIS_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_Msk (0x1UL << TWIS_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
+#define TWIS_ERRORSRC_DNACK_NotReceived (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_DNACK_Received (1UL) /*!< Error occurred */
+
+/* Bit 0 : RX buffer overflow detected, and prevented */
+#define TWIS_ERRORSRC_OVERFLOW_Pos (0UL) /*!< Position of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_Msk (0x1UL << TWIS_ERRORSRC_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
+#define TWIS_ERRORSRC_OVERFLOW_NotDetected (0UL) /*!< Error did not occur */
+#define TWIS_ERRORSRC_OVERFLOW_Detected (1UL) /*!< Error occurred */
+
+/* Register: TWIS_MATCH */
+/* Description: Status register indicating which address had a match */
+
+/* Bit 0 : Which of the addresses in {ADDRESS} matched the incoming address */
+#define TWIS_MATCH_MATCH_Pos (0UL) /*!< Position of MATCH field. */
+#define TWIS_MATCH_MATCH_Msk (0x1UL << TWIS_MATCH_MATCH_Pos) /*!< Bit mask of MATCH field. */
+
+/* Register: TWIS_ENABLE */
+/* Description: Enable TWIS */
+
+/* Bits 3..0 : Enable or disable TWIS */
+#define TWIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Msk (0xFUL << TWIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define TWIS_ENABLE_ENABLE_Disabled (0UL) /*!< Disable TWIS */
+#define TWIS_ENABLE_ENABLE_Enabled (9UL) /*!< Enable TWIS */
+
+/* Register: TWIS_PSEL_SCL */
+/* Description: Pin select for SCL signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SCL_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Msk (0x1UL << TWIS_PSEL_SCL_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SCL_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SCL_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SCL_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SCL_PIN_Msk (0x1FUL << TWIS_PSEL_SCL_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_PSEL_SDA */
+/* Description: Pin select for SDA signal */
+
+/* Bit 31 : Connection */
+#define TWIS_PSEL_SDA_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Msk (0x1UL << TWIS_PSEL_SDA_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define TWIS_PSEL_SDA_CONNECT_Connected (0UL) /*!< Connect */
+#define TWIS_PSEL_SDA_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define TWIS_PSEL_SDA_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define TWIS_PSEL_SDA_PIN_Msk (0x1FUL << TWIS_PSEL_SDA_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: TWIS_RXD_PTR */
+/* Description: RXD Data pointer */
+
+/* Bits 31..0 : RXD Data pointer */
+#define TWIS_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_RXD_MAXCNT */
+/* Description: Maximum number of bytes in RXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in RXD buffer */
+#define TWIS_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last RXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last RXD transaction */
+#define TWIS_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_TXD_PTR */
+/* Description: TXD Data pointer */
+
+/* Bits 31..0 : TXD Data pointer */
+#define TWIS_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define TWIS_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << TWIS_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: TWIS_TXD_MAXCNT */
+/* Description: Maximum number of bytes in TXD buffer */
+
+/* Bits 7..0 : Maximum number of bytes in TXD buffer */
+#define TWIS_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define TWIS_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << TWIS_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: TWIS_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last TXD transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last TXD transaction */
+#define TWIS_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define TWIS_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << TWIS_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: TWIS_ADDRESS */
+/* Description: Description collection[0]:  TWI slave address 0 */
+
+/* Bits 6..0 : TWI slave address */
+#define TWIS_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
+#define TWIS_ADDRESS_ADDRESS_Msk (0x7FUL << TWIS_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
+
+/* Register: TWIS_CONFIG */
+/* Description: Configuration register for the address match mechanism */
+
+/* Bit 1 : Enable or disable address matching on ADDRESS[1] */
+#define TWIS_CONFIG_ADDRESS1_Pos (1UL) /*!< Position of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Msk (0x1UL << TWIS_CONFIG_ADDRESS1_Pos) /*!< Bit mask of ADDRESS1 field. */
+#define TWIS_CONFIG_ADDRESS1_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS1_Enabled (1UL) /*!< Enabled */
+
+/* Bit 0 : Enable or disable address matching on ADDRESS[0] */
+#define TWIS_CONFIG_ADDRESS0_Pos (0UL) /*!< Position of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Msk (0x1UL << TWIS_CONFIG_ADDRESS0_Pos) /*!< Bit mask of ADDRESS0 field. */
+#define TWIS_CONFIG_ADDRESS0_Disabled (0UL) /*!< Disabled */
+#define TWIS_CONFIG_ADDRESS0_Enabled (1UL) /*!< Enabled */
+
+/* Register: TWIS_ORC */
+/* Description: Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+
+/* Bits 7..0 : Over-read character. Character sent out in case of an over-read of the transmit buffer. */
+#define TWIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
+#define TWIS_ORC_ORC_Msk (0xFFUL << TWIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
+
+
+/* Peripheral: UART */
+/* Description: Universal Asynchronous Receiver/Transmitter */
+
+/* Register: UART_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 4 : Shortcut between NCTS event and STOPRX task */
+#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
+#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 3 : Shortcut between CTS event and STARTRX task */
+#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
+#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UART_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 7 : Write '1' to Enable interrupt for TXDRDY event */
+#define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 2 : Write '1' to Enable interrupt for RXDRDY event */
+#define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UART_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 7 : Write '1' to Disable interrupt for TXDRDY event */
+#define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
+#define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 2 : Write '1' to Disable interrupt for RXDRDY event */
+#define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
+#define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UART_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UART_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UART_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UART_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UART */
+#define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UART_ENABLE_ENABLE_Msk (0xFUL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UART_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UART */
+#define UART_ENABLE_ENABLE_Enabled (4UL) /*!< Enable UART */
+
+/* Register: UART_PSELRTS */
+/* Description: Pin select for RTS */
+
+/* Bits 31..0 : Pin number configuration for UART RTS signal */
+#define UART_PSELRTS_PSELRTS_Pos (0UL) /*!< Position of PSELRTS field. */
+#define UART_PSELRTS_PSELRTS_Msk (0xFFFFFFFFUL << UART_PSELRTS_PSELRTS_Pos) /*!< Bit mask of PSELRTS field. */
+#define UART_PSELRTS_PSELRTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELTXD */
+/* Description: Pin select for TXD */
+
+/* Bits 31..0 : Pin number configuration for UART TXD signal */
+#define UART_PSELTXD_PSELTXD_Pos (0UL) /*!< Position of PSELTXD field. */
+#define UART_PSELTXD_PSELTXD_Msk (0xFFFFFFFFUL << UART_PSELTXD_PSELTXD_Pos) /*!< Bit mask of PSELTXD field. */
+#define UART_PSELTXD_PSELTXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELCTS */
+/* Description: Pin select for CTS */
+
+/* Bits 31..0 : Pin number configuration for UART CTS signal */
+#define UART_PSELCTS_PSELCTS_Pos (0UL) /*!< Position of PSELCTS field. */
+#define UART_PSELCTS_PSELCTS_Msk (0xFFFFFFFFUL << UART_PSELCTS_PSELCTS_Pos) /*!< Bit mask of PSELCTS field. */
+#define UART_PSELCTS_PSELCTS_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_PSELRXD */
+/* Description: Pin select for RXD */
+
+/* Bits 31..0 : Pin number configuration for UART RXD signal */
+#define UART_PSELRXD_PSELRXD_Pos (0UL) /*!< Position of PSELRXD field. */
+#define UART_PSELRXD_PSELRXD_Msk (0xFFFFFFFFUL << UART_PSELRXD_PSELRXD_Pos) /*!< Bit mask of PSELRXD field. */
+#define UART_PSELRXD_PSELRXD_Disconnected (0xFFFFFFFFUL) /*!< Disconnect */
+
+/* Register: UART_RXD */
+/* Description: RXD register */
+
+/* Bits 7..0 : RX data received in previous transfers, double buffered */
+#define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
+#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
+
+/* Register: UART_TXD */
+/* Description: TXD register */
+
+/* Bits 7..0 : TX data to be transferred */
+#define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
+#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
+
+/* Register: UART_BAUDRATE */
+/* Description: Baud rate */
+
+/* Bits 31..0 : Baud-rate */
+#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud (actual rate: 14414) */
+#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud (actual rate: 28829) */
+#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud (actual rate: 38462) */
+#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud (actual rate: 57762) */
+#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud (actual rate: 115942) */
+#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud (actual rate: 470588) */
+#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBED000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UART_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UART_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UART_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UART_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UART_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UARTE */
+/* Description: UART with EasyDMA */
+
+/* Register: UARTE_SHORTS */
+/* Description: Shortcut register */
+
+/* Bit 6 : Shortcut between ENDRX event and STOPRX task */
+#define UARTE_SHORTS_ENDRX_STOPRX_Pos (6UL) /*!< Position of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STOPRX_Pos) /*!< Bit mask of ENDRX_STOPRX field. */
+#define UARTE_SHORTS_ENDRX_STOPRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STOPRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Bit 5 : Shortcut between ENDRX event and STARTRX task */
+#define UARTE_SHORTS_ENDRX_STARTRX_Pos (5UL) /*!< Position of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Msk (0x1UL << UARTE_SHORTS_ENDRX_STARTRX_Pos) /*!< Bit mask of ENDRX_STARTRX field. */
+#define UARTE_SHORTS_ENDRX_STARTRX_Disabled (0UL) /*!< Disable shortcut */
+#define UARTE_SHORTS_ENDRX_STARTRX_Enabled (1UL) /*!< Enable shortcut */
+
+/* Register: UARTE_INTEN */
+/* Description: Enable or disable interrupt */
+
+/* Bit 22 : Enable or disable interrupt for TXSTOPPED event */
+#define UARTE_INTEN_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Msk (0x1UL << UARTE_INTEN_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTEN_TXSTOPPED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTOPPED_Enabled (1UL) /*!< Enable */
+
+/* Bit 20 : Enable or disable interrupt for TXSTARTED event */
+#define UARTE_INTEN_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Msk (0x1UL << UARTE_INTEN_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTEN_TXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_TXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 19 : Enable or disable interrupt for RXSTARTED event */
+#define UARTE_INTEN_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Msk (0x1UL << UARTE_INTEN_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTEN_RXSTARTED_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXSTARTED_Enabled (1UL) /*!< Enable */
+
+/* Bit 17 : Enable or disable interrupt for RXTO event */
+#define UARTE_INTEN_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTEN_RXTO_Msk (0x1UL << UARTE_INTEN_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTEN_RXTO_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_RXTO_Enabled (1UL) /*!< Enable */
+
+/* Bit 9 : Enable or disable interrupt for ERROR event */
+#define UARTE_INTEN_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTEN_ERROR_Msk (0x1UL << UARTE_INTEN_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTEN_ERROR_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ERROR_Enabled (1UL) /*!< Enable */
+
+/* Bit 8 : Enable or disable interrupt for ENDTX event */
+#define UARTE_INTEN_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Msk (0x1UL << UARTE_INTEN_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTEN_ENDTX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDTX_Enabled (1UL) /*!< Enable */
+
+/* Bit 4 : Enable or disable interrupt for ENDRX event */
+#define UARTE_INTEN_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Msk (0x1UL << UARTE_INTEN_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTEN_ENDRX_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_ENDRX_Enabled (1UL) /*!< Enable */
+
+/* Bit 1 : Enable or disable interrupt for NCTS event */
+#define UARTE_INTEN_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTEN_NCTS_Msk (0x1UL << UARTE_INTEN_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTEN_NCTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_NCTS_Enabled (1UL) /*!< Enable */
+
+/* Bit 0 : Enable or disable interrupt for CTS event */
+#define UARTE_INTEN_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTEN_CTS_Msk (0x1UL << UARTE_INTEN_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTEN_CTS_Disabled (0UL) /*!< Disable */
+#define UARTE_INTEN_CTS_Enabled (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 22 : Write '1' to Enable interrupt for TXSTOPPED event */
+#define UARTE_INTENSET_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Msk (0x1UL << UARTE_INTENSET_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENSET_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTOPPED_Set (1UL) /*!< Enable */
+
+/* Bit 20 : Write '1' to Enable interrupt for TXSTARTED event */
+#define UARTE_INTENSET_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Msk (0x1UL << UARTE_INTENSET_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENSET_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_TXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 19 : Write '1' to Enable interrupt for RXSTARTED event */
+#define UARTE_INTENSET_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Msk (0x1UL << UARTE_INTENSET_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENSET_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXSTARTED_Set (1UL) /*!< Enable */
+
+/* Bit 17 : Write '1' to Enable interrupt for RXTO event */
+#define UARTE_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENSET_RXTO_Msk (0x1UL << UARTE_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENSET_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_RXTO_Set (1UL) /*!< Enable */
+
+/* Bit 9 : Write '1' to Enable interrupt for ERROR event */
+#define UARTE_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENSET_ERROR_Msk (0x1UL << UARTE_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENSET_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ERROR_Set (1UL) /*!< Enable */
+
+/* Bit 8 : Write '1' to Enable interrupt for ENDTX event */
+#define UARTE_INTENSET_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Msk (0x1UL << UARTE_INTENSET_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENSET_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDTX_Set (1UL) /*!< Enable */
+
+/* Bit 4 : Write '1' to Enable interrupt for ENDRX event */
+#define UARTE_INTENSET_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Msk (0x1UL << UARTE_INTENSET_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENSET_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_ENDRX_Set (1UL) /*!< Enable */
+
+/* Bit 1 : Write '1' to Enable interrupt for NCTS event */
+#define UARTE_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENSET_NCTS_Msk (0x1UL << UARTE_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENSET_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_NCTS_Set (1UL) /*!< Enable */
+
+/* Bit 0 : Write '1' to Enable interrupt for CTS event */
+#define UARTE_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENSET_CTS_Msk (0x1UL << UARTE_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENSET_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENSET_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENSET_CTS_Set (1UL) /*!< Enable */
+
+/* Register: UARTE_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 22 : Write '1' to Disable interrupt for TXSTOPPED event */
+#define UARTE_INTENCLR_TXSTOPPED_Pos (22UL) /*!< Position of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Msk (0x1UL << UARTE_INTENCLR_TXSTOPPED_Pos) /*!< Bit mask of TXSTOPPED field. */
+#define UARTE_INTENCLR_TXSTOPPED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTOPPED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTOPPED_Clear (1UL) /*!< Disable */
+
+/* Bit 20 : Write '1' to Disable interrupt for TXSTARTED event */
+#define UARTE_INTENCLR_TXSTARTED_Pos (20UL) /*!< Position of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Msk (0x1UL << UARTE_INTENCLR_TXSTARTED_Pos) /*!< Bit mask of TXSTARTED field. */
+#define UARTE_INTENCLR_TXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_TXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_TXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 19 : Write '1' to Disable interrupt for RXSTARTED event */
+#define UARTE_INTENCLR_RXSTARTED_Pos (19UL) /*!< Position of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Msk (0x1UL << UARTE_INTENCLR_RXSTARTED_Pos) /*!< Bit mask of RXSTARTED field. */
+#define UARTE_INTENCLR_RXSTARTED_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXSTARTED_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXSTARTED_Clear (1UL) /*!< Disable */
+
+/* Bit 17 : Write '1' to Disable interrupt for RXTO event */
+#define UARTE_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Msk (0x1UL << UARTE_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
+#define UARTE_INTENCLR_RXTO_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_RXTO_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_RXTO_Clear (1UL) /*!< Disable */
+
+/* Bit 9 : Write '1' to Disable interrupt for ERROR event */
+#define UARTE_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Msk (0x1UL << UARTE_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
+#define UARTE_INTENCLR_ERROR_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ERROR_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ERROR_Clear (1UL) /*!< Disable */
+
+/* Bit 8 : Write '1' to Disable interrupt for ENDTX event */
+#define UARTE_INTENCLR_ENDTX_Pos (8UL) /*!< Position of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Msk (0x1UL << UARTE_INTENCLR_ENDTX_Pos) /*!< Bit mask of ENDTX field. */
+#define UARTE_INTENCLR_ENDTX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDTX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDTX_Clear (1UL) /*!< Disable */
+
+/* Bit 4 : Write '1' to Disable interrupt for ENDRX event */
+#define UARTE_INTENCLR_ENDRX_Pos (4UL) /*!< Position of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Msk (0x1UL << UARTE_INTENCLR_ENDRX_Pos) /*!< Bit mask of ENDRX field. */
+#define UARTE_INTENCLR_ENDRX_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_ENDRX_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_ENDRX_Clear (1UL) /*!< Disable */
+
+/* Bit 1 : Write '1' to Disable interrupt for NCTS event */
+#define UARTE_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Msk (0x1UL << UARTE_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
+#define UARTE_INTENCLR_NCTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_NCTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_NCTS_Clear (1UL) /*!< Disable */
+
+/* Bit 0 : Write '1' to Disable interrupt for CTS event */
+#define UARTE_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
+#define UARTE_INTENCLR_CTS_Msk (0x1UL << UARTE_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
+#define UARTE_INTENCLR_CTS_Disabled (0UL) /*!< Read: Disabled */
+#define UARTE_INTENCLR_CTS_Enabled (1UL) /*!< Read: Enabled */
+#define UARTE_INTENCLR_CTS_Clear (1UL) /*!< Disable */
+
+/* Register: UARTE_ERRORSRC */
+/* Description: Error source */
+
+/* Bit 3 : Break condition */
+#define UARTE_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_Msk (0x1UL << UARTE_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
+#define UARTE_ERRORSRC_BREAK_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_BREAK_Present (1UL) /*!< Read: error present */
+
+/* Bit 2 : Framing error occurred */
+#define UARTE_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_Msk (0x1UL << UARTE_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
+#define UARTE_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_FRAMING_Present (1UL) /*!< Read: error present */
+
+/* Bit 1 : Parity error */
+#define UARTE_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_Msk (0x1UL << UARTE_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_ERRORSRC_PARITY_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_PARITY_Present (1UL) /*!< Read: error present */
+
+/* Bit 0 : Overrun error */
+#define UARTE_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_Msk (0x1UL << UARTE_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
+#define UARTE_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Read: error not present */
+#define UARTE_ERRORSRC_OVERRUN_Present (1UL) /*!< Read: error present */
+
+/* Register: UARTE_ENABLE */
+/* Description: Enable UART */
+
+/* Bits 3..0 : Enable or disable UARTE */
+#define UARTE_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Msk (0xFUL << UARTE_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
+#define UARTE_ENABLE_ENABLE_Disabled (0UL) /*!< Disable UARTE */
+#define UARTE_ENABLE_ENABLE_Enabled (8UL) /*!< Enable UARTE */
+
+/* Register: UARTE_PSEL_RTS */
+/* Description: Pin select for RTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Msk (0x1UL << UARTE_PSEL_RTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RTS_PIN_Msk (0x1FUL << UARTE_PSEL_RTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_TXD */
+/* Description: Pin select for TXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_TXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Msk (0x1UL << UARTE_PSEL_TXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_TXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_TXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_TXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_TXD_PIN_Msk (0x1FUL << UARTE_PSEL_TXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_CTS */
+/* Description: Pin select for CTS signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_CTS_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Msk (0x1UL << UARTE_PSEL_CTS_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_CTS_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_CTS_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_CTS_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_CTS_PIN_Msk (0x1FUL << UARTE_PSEL_CTS_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_PSEL_RXD */
+/* Description: Pin select for RXD signal */
+
+/* Bit 31 : Connection */
+#define UARTE_PSEL_RXD_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Msk (0x1UL << UARTE_PSEL_RXD_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UARTE_PSEL_RXD_CONNECT_Connected (0UL) /*!< Connect */
+#define UARTE_PSEL_RXD_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : Pin number */
+#define UARTE_PSEL_RXD_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UARTE_PSEL_RXD_PIN_Msk (0x1FUL << UARTE_PSEL_RXD_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UARTE_BAUDRATE */
+/* Description: Baud rate */
+
+/* Bits 31..0 : Baud-rate */
+#define UARTE_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UARTE_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud (actual rate: 1205) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud (actual rate: 2396) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud (actual rate: 4808) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud (actual rate: 9598) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud14400 (0x003AF000UL) /*!< 14400 baud (actual rate: 14401) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud (actual rate: 19208) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud28800 (0x0075C000UL) /*!< 28800 baud (actual rate: 28777) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud38400 (0x009D0000UL) /*!< 38400 baud (actual rate: 38369) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud57600 (0x00EB0000UL) /*!< 57600 baud (actual rate: 57554) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud (actual rate: 76923) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud115200 (0x01D60000UL) /*!< 115200 baud (actual rate: 115108) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud230400 (0x03B00000UL) /*!< 230400 baud (actual rate: 231884) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud */
+#define UARTE_BAUDRATE_BAUDRATE_Baud460800 (0x07400000UL) /*!< 460800 baud (actual rate: 457143) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud921600 (0x0F000000UL) /*!< 921600 baud (actual rate: 941176) */
+#define UARTE_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1Mega baud */
+
+/* Register: UARTE_RXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_RXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_RXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_RXD_MAXCNT */
+/* Description: Maximum number of bytes in receive buffer */
+
+/* Bits 7..0 : Maximum number of bytes in receive buffer */
+#define UARTE_RXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_RXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_RXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define UARTE_RXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_RXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_TXD_PTR */
+/* Description: Data pointer */
+
+/* Bits 31..0 : Data pointer */
+#define UARTE_TXD_PTR_PTR_Pos (0UL) /*!< Position of PTR field. */
+#define UARTE_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << UARTE_TXD_PTR_PTR_Pos) /*!< Bit mask of PTR field. */
+
+/* Register: UARTE_TXD_MAXCNT */
+/* Description: Maximum number of bytes in transmit buffer */
+
+/* Bits 7..0 : Maximum number of bytes in transmit buffer */
+#define UARTE_TXD_MAXCNT_MAXCNT_Pos (0UL) /*!< Position of MAXCNT field. */
+#define UARTE_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << UARTE_TXD_MAXCNT_MAXCNT_Pos) /*!< Bit mask of MAXCNT field. */
+
+/* Register: UARTE_TXD_AMOUNT */
+/* Description: Number of bytes transferred in the last transaction */
+
+/* Bits 7..0 : Number of bytes transferred in the last transaction */
+#define UARTE_TXD_AMOUNT_AMOUNT_Pos (0UL) /*!< Position of AMOUNT field. */
+#define UARTE_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << UARTE_TXD_AMOUNT_AMOUNT_Pos) /*!< Bit mask of AMOUNT field. */
+
+/* Register: UARTE_CONFIG */
+/* Description: Configuration of parity and hardware flow control */
+
+/* Bits 3..1 : Parity */
+#define UARTE_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
+#define UARTE_CONFIG_PARITY_Msk (0x7UL << UARTE_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
+#define UARTE_CONFIG_PARITY_Excluded (0x0UL) /*!< Exclude parity bit */
+#define UARTE_CONFIG_PARITY_Included (0x7UL) /*!< Include parity bit */
+
+/* Bit 0 : Hardware flow control */
+#define UARTE_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
+#define UARTE_CONFIG_HWFC_Msk (0x1UL << UARTE_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
+#define UARTE_CONFIG_HWFC_Disabled (0UL) /*!< Disabled */
+#define UARTE_CONFIG_HWFC_Enabled (1UL) /*!< Enabled */
+
+
+/* Peripheral: UICR */
+/* Description: User Information Configuration Registers */
+
+/* Register: UICR_NRFFW */
+/* Description: Description collection[0]:  Reserved for Nordic firmware design */
+
+/* Bits 31..0 : Reserved for Nordic firmware design */
+#define UICR_NRFFW_NRFFW_Pos (0UL) /*!< Position of NRFFW field. */
+#define UICR_NRFFW_NRFFW_Msk (0xFFFFFFFFUL << UICR_NRFFW_NRFFW_Pos) /*!< Bit mask of NRFFW field. */
+
+/* Register: UICR_NRFHW */
+/* Description: Description collection[0]:  Reserved for Nordic hardware design */
+
+/* Bits 31..0 : Reserved for Nordic hardware design */
+#define UICR_NRFHW_NRFHW_Pos (0UL) /*!< Position of NRFHW field. */
+#define UICR_NRFHW_NRFHW_Msk (0xFFFFFFFFUL << UICR_NRFHW_NRFHW_Pos) /*!< Bit mask of NRFHW field. */
+
+/* Register: UICR_CUSTOMER */
+/* Description: Description collection[0]:  Reserved for customer */
+
+/* Bits 31..0 : Reserved for customer */
+#define UICR_CUSTOMER_CUSTOMER_Pos (0UL) /*!< Position of CUSTOMER field. */
+#define UICR_CUSTOMER_CUSTOMER_Msk (0xFFFFFFFFUL << UICR_CUSTOMER_CUSTOMER_Pos) /*!< Bit mask of CUSTOMER field. */
+
+/* Register: UICR_PSELRESET */
+/* Description: Description collection[0]:  Mapping of the nRESET function (see POWER chapter for details) */
+
+/* Bit 31 : Connection */
+#define UICR_PSELRESET_CONNECT_Pos (31UL) /*!< Position of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Msk (0x1UL << UICR_PSELRESET_CONNECT_Pos) /*!< Bit mask of CONNECT field. */
+#define UICR_PSELRESET_CONNECT_Connected (0UL) /*!< Connect */
+#define UICR_PSELRESET_CONNECT_Disconnected (1UL) /*!< Disconnect */
+
+/* Bits 4..0 : GPIO number P0.n onto which Reset is exposed */
+#define UICR_PSELRESET_PIN_Pos (0UL) /*!< Position of PIN field. */
+#define UICR_PSELRESET_PIN_Msk (0x1FUL << UICR_PSELRESET_PIN_Pos) /*!< Bit mask of PIN field. */
+
+/* Register: UICR_APPROTECT */
+/* Description: Access Port protection */
+
+/* Bits 7..0 : Enable or disable Access Port protection. */
+#define UICR_APPROTECT_PALL_Pos (0UL) /*!< Position of PALL field. */
+#define UICR_APPROTECT_PALL_Msk (0xFFUL << UICR_APPROTECT_PALL_Pos) /*!< Bit mask of PALL field. */
+#define UICR_APPROTECT_PALL_Enabled (0x00UL) /*!< Enable */
+#define UICR_APPROTECT_PALL_Disabled (0xFFUL) /*!< Disable */
+
+/* Register: UICR_NFCPINS */
+/* Description: Setting of pins dedicated to NFC functionality: NFC antenna or GPIO */
+
+/* Bit 0 : Setting of pins dedicated to NFC functionality */
+#define UICR_NFCPINS_PROTECT_Pos (0UL) /*!< Position of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Msk (0x1UL << UICR_NFCPINS_PROTECT_Pos) /*!< Bit mask of PROTECT field. */
+#define UICR_NFCPINS_PROTECT_Disabled (0UL) /*!< Operation as GPIO pins. Same protection as normal GPIO pins */
+#define UICR_NFCPINS_PROTECT_NFC (1UL) /*!< Operation as NFC antenna pins. Configures the protection for NFC operation */
+
+
+/* Peripheral: WDT */
+/* Description: Watchdog Timer */
+
+/* Register: WDT_INTENSET */
+/* Description: Enable interrupt */
+
+/* Bit 0 : Write '1' to Enable interrupt for TIMEOUT event */
+#define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable */
+
+/* Register: WDT_INTENCLR */
+/* Description: Disable interrupt */
+
+/* Bit 0 : Write '1' to Disable interrupt for TIMEOUT event */
+#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
+#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Read: Disabled */
+#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Read: Enabled */
+#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable */
+
+/* Register: WDT_RUNSTATUS */
+/* Description: Run status */
+
+/* Bit 0 : Indicates whether or not the watchdog is running */
+#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
+#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog not running */
+#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog is running */
+
+/* Register: WDT_REQSTATUS */
+/* Description: Request status */
+
+/* Bit 7 : Request status for RR[7] register */
+#define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled, and are not yet requesting reload */
+
+/* Bit 6 : Request status for RR[6] register */
+#define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled, and are not yet requesting reload */
+
+/* Bit 5 : Request status for RR[5] register */
+#define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled, and are not yet requesting reload */
+
+/* Bit 4 : Request status for RR[4] register */
+#define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled, and are not yet requesting reload */
+
+/* Bit 3 : Request status for RR[3] register */
+#define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled, and are not yet requesting reload */
+
+/* Bit 2 : Request status for RR[2] register */
+#define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled, and are not yet requesting reload */
+
+/* Bit 1 : Request status for RR[1] register */
+#define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled, and are not yet requesting reload */
+
+/* Bit 0 : Request status for RR[0] register */
+#define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled, or are already requesting reload */
+#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled, and are not yet requesting reload */
+
+/* Register: WDT_CRV */
+/* Description: Counter reload value */
+
+/* Bits 31..0 : Counter reload value in number of cycles of the 32.768 kHz clock */
+#define WDT_CRV_CRV_Pos (0UL) /*!< Position of CRV field. */
+#define WDT_CRV_CRV_Msk (0xFFFFFFFFUL << WDT_CRV_CRV_Pos) /*!< Bit mask of CRV field. */
+
+/* Register: WDT_RREN */
+/* Description: Enable register for reload request registers */
+
+/* Bit 7 : Enable or disable RR[7] register */
+#define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
+#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
+#define WDT_RREN_RR7_Disabled (0UL) /*!< Disable RR[7] register */
+#define WDT_RREN_RR7_Enabled (1UL) /*!< Enable RR[7] register */
+
+/* Bit 6 : Enable or disable RR[6] register */
+#define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
+#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
+#define WDT_RREN_RR6_Disabled (0UL) /*!< Disable RR[6] register */
+#define WDT_RREN_RR6_Enabled (1UL) /*!< Enable RR[6] register */
+
+/* Bit 5 : Enable or disable RR[5] register */
+#define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
+#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
+#define WDT_RREN_RR5_Disabled (0UL) /*!< Disable RR[5] register */
+#define WDT_RREN_RR5_Enabled (1UL) /*!< Enable RR[5] register */
+
+/* Bit 4 : Enable or disable RR[4] register */
+#define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
+#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
+#define WDT_RREN_RR4_Disabled (0UL) /*!< Disable RR[4] register */
+#define WDT_RREN_RR4_Enabled (1UL) /*!< Enable RR[4] register */
+
+/* Bit 3 : Enable or disable RR[3] register */
+#define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
+#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
+#define WDT_RREN_RR3_Disabled (0UL) /*!< Disable RR[3] register */
+#define WDT_RREN_RR3_Enabled (1UL) /*!< Enable RR[3] register */
+
+/* Bit 2 : Enable or disable RR[2] register */
+#define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
+#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
+#define WDT_RREN_RR2_Disabled (0UL) /*!< Disable RR[2] register */
+#define WDT_RREN_RR2_Enabled (1UL) /*!< Enable RR[2] register */
+
+/* Bit 1 : Enable or disable RR[1] register */
+#define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
+#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
+#define WDT_RREN_RR1_Disabled (0UL) /*!< Disable RR[1] register */
+#define WDT_RREN_RR1_Enabled (1UL) /*!< Enable RR[1] register */
+
+/* Bit 0 : Enable or disable RR[0] register */
+#define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
+#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
+#define WDT_RREN_RR0_Disabled (0UL) /*!< Disable RR[0] register */
+#define WDT_RREN_RR0_Enabled (1UL) /*!< Enable RR[0] register */
+
+/* Register: WDT_CONFIG */
+/* Description: Configuration register */
+
+/* Bit 3 : Configure the watchdog to either be paused, or kept running, while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
+#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
+#define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger */
+#define WDT_CONFIG_HALT_Run (1UL) /*!< Keep the watchdog running while the CPU is halted by the debugger */
+
+/* Bit 0 : Configure the watchdog to either be paused, or kept running, while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
+#define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is sleeping */
+#define WDT_CONFIG_SLEEP_Run (1UL) /*!< Keep the watchdog running while the CPU is sleeping */
+
+/* Register: WDT_RR */
+/* Description: Description collection[0]:  Reload request 0 */
+
+/* Bits 31..0 : Reload request register */
+#define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
+#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
+#define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer */
+
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_name_change.h b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_name_change.h
new file mode 100644
index 0000000000..7f362a8fd9
--- /dev/null
+++ b/hal/targets/cmsis/TARGET_NORDIC/TARGET_NRF5/sdk/device/nrf52_name_change.h
@@ -0,0 +1,79 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF52_NAME_CHANGE_H
+#define NRF52_NAME_CHANGE_H
+
+/*lint ++flb "Enter library region */
+
+/* This file is given to prevent your SW from not compiling with the updates made to nrf52.h and 
+ * nrf52_bitfields.h. The macros defined in this file were available previously. Do not use these
+ * macros on purpose. Use the ones defined in nrf52.h and nrf52_bitfields.h instead.
+ */
+
+/* I2S */
+/* Several enumerations changed case. Adding old macros to keep compilation compatibility. */
+#define I2S_ENABLE_ENABLE_DISABLE           I2S_ENABLE_ENABLE_Disabled
+#define I2S_ENABLE_ENABLE_ENABLE            I2S_ENABLE_ENABLE_Enabled
+#define I2S_CONFIG_MODE_MODE_MASTER         I2S_CONFIG_MODE_MODE_Master
+#define I2S_CONFIG_MODE_MODE_SLAVE          I2S_CONFIG_MODE_MODE_Slave
+#define I2S_CONFIG_RXEN_RXEN_DISABLE        I2S_CONFIG_RXEN_RXEN_Disabled
+#define I2S_CONFIG_RXEN_RXEN_ENABLE         I2S_CONFIG_RXEN_RXEN_Enabled
+#define I2S_CONFIG_TXEN_TXEN_DISABLE        I2S_CONFIG_TXEN_TXEN_Disabled
+#define I2S_CONFIG_TXEN_TXEN_ENABLE         I2S_CONFIG_TXEN_TXEN_Enabled
+#define I2S_CONFIG_MCKEN_MCKEN_DISABLE      I2S_CONFIG_MCKEN_MCKEN_Disabled
+#define I2S_CONFIG_MCKEN_MCKEN_ENABLE       I2S_CONFIG_MCKEN_MCKEN_Enabled
+#define I2S_CONFIG_SWIDTH_SWIDTH_8BIT       I2S_CONFIG_SWIDTH_SWIDTH_8Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_16BIT      I2S_CONFIG_SWIDTH_SWIDTH_16Bit
+#define I2S_CONFIG_SWIDTH_SWIDTH_24BIT      I2S_CONFIG_SWIDTH_SWIDTH_24Bit
+#define I2S_CONFIG_ALIGN_ALIGN_LEFT         I2S_CONFIG_ALIGN_ALIGN_Left
+#define I2S_CONFIG_ALIGN_ALIGN_RIGHT        I2S_CONFIG_ALIGN_ALIGN_Right
+#define I2S_CONFIG_FORMAT_FORMAT_ALIGNED    I2S_CONFIG_FORMAT_FORMAT_Aligned
+#define I2S_CONFIG_CHANNELS_CHANNELS_STEREO I2S_CONFIG_CHANNELS_CHANNELS_Stereo
+#define I2S_CONFIG_CHANNELS_CHANNELS_LEFT   I2S_CONFIG_CHANNELS_CHANNELS_Left
+#define I2S_CONFIG_CHANNELS_CHANNELS_RIGHT  I2S_CONFIG_CHANNELS_CHANNELS_Right
+
+
+
+
+
+/*lint --flb "Leave library region" */
+
+#endif /* NRF52_NAME_CHANGE_H */
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h
new file mode 100644
index 0000000000..65cc930c8c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/PeripheralNames.h
@@ -0,0 +1,81 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STDIO_UART_TX     TX_PIN_NUMBER
+#define STDIO_UART_RX     RX_PIN_NUMBER
+#define STDIO_UART        UART_0
+
+typedef enum {
+    UART_0 = (int)NRF_UART0_BASE
+} UARTName;
+
+
+typedef enum {
+    SPI_0 = (int)NRF_SPI0_BASE,
+    SPI_1 = (int)NRF_SPI1_BASE,
+    SPIS = (int)NRF_SPIS1_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2
+} PWMName;
+
+typedef enum {
+    I2C_0 = (int)NRF_TWI0_BASE,
+    I2C_1 = (int)NRF_TWI1_BASE
+} I2CName;
+
+typedef enum {
+    ADC0_0 = (int)NRF_ADC_BASE
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/PortNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/PortNames.h
new file mode 100644
index 0000000000..c63624639b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/PortNames.h
@@ -0,0 +1,53 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0 //GPIO pins 0-31
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h
new file mode 100644
index 0000000000..a7cfe580ab
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/PinNames.h
@@ -0,0 +1,201 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = 8,
+    p9  = 9,
+    p10 = 10,
+    p11 = 11,
+    p12 = 12,
+    p13 = 13,
+    p14 = 14,
+    p15 = 15,
+    p16 = 16,
+    p17 = 17,
+    p18 = 18,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = 28,
+    p29 = 29,
+    p30 = 30,
+
+    P0_0  = p0,
+    P0_1  = p1,
+    P0_2  = p2,
+    P0_3  = p3,
+    P0_4  = p4,
+    P0_5  = p5,
+    P0_6  = p6,
+    P0_7  = p7,
+
+    P0_8  = p8,
+    P0_9  = p9,
+    P0_10 = p10,
+    P0_11 = p11,
+    P0_12 = p12,
+    P0_13 = p13,
+    P0_14 = p14,
+    P0_15 = p15,
+
+    P0_16 = p16,
+    P0_17 = p17,
+    P0_18 = p18,
+    P0_19 = p19,
+    P0_20 = p20,
+    P0_21 = p21,
+    P0_22 = p22,
+    P0_23 = p23,
+
+    P0_24 = p24,
+    P0_25 = p25,
+    P0_26 = p26,
+    P0_27 = p27,
+    P0_28 = p28,
+    P0_29 = p29,
+    P0_30 = p30,
+
+    LED1    = p21,
+    LED2    = p22,
+    LED3    = p23,
+    LED4    = p24,
+
+    BUTTON1 = p17,
+    BUTTON2 = p18,
+    BUTTON3 = p19,
+    BUTTON4 = p20,
+
+    RX_PIN_NUMBER  = p11,
+    TX_PIN_NUMBER  = p9,
+    CTS_PIN_NUMBER = p10,
+    RTS_PIN_NUMBER = p8,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = p25,
+    SPI_PSELMISO0 = p28,
+    SPI_PSELSS0   = p24,
+    SPI_PSELSCK0  = p29,
+
+    SPI_PSELMOSI1 = p13,
+    SPI_PSELMISO1 = p14,
+    SPI_PSELSS1   = p12,
+    SPI_PSELSCK1  = p15,
+
+    SPIS_PSELMOSI = p13,
+    SPIS_PSELMISO = p14,
+    SPIS_PSELSS   = p12,
+    SPIS_PSELSCK  = p15,
+
+    I2C_SDA0 = p30,
+    I2C_SCL0 = p7,
+
+    D0  = p12,
+    D1  = p13,
+    D2  = p14,
+    D3  = p15,
+    D4  = p16,
+    D5  = p17,
+    D6  = p18,
+    D7  = p19,
+
+    D8  = p20,
+    D9  = p23,
+    D10 = p24,
+    D11 = p25,
+    D12 = p28,
+    D13 = p29,
+
+    D14 = p30,
+    D15 = p7,
+
+    A0  = p1,
+    A1  = p2,
+    A2  = p3,
+    A3  = p4,
+    A4  = p5,
+    A5  = p6,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h
new file mode 100644
index 0000000000..2427e752ea
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_NRF51_DK/device.h
@@ -0,0 +1,38 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#include "objects.h"
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c
new file mode 100644
index 0000000000..821e2b3bf4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/analogin_api.c
@@ -0,0 +1,88 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */ 
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "nrf_drv_adc.h"
+
+#ifdef DEVICE_ANALOGIN
+
+
+#define ADC_10BIT_RANGE  0x3FF
+#define ADC_RANGE        ADC_10BIT_RANGE
+
+static const PinMap PinMap_ADC[] = {
+    {p1, ADC0_0, 4},
+    {p2, ADC0_0, 8},
+    {p3, ADC0_0, 16},
+    {p4, ADC0_0, 32},
+    {p5, ADC0_0, 64},
+    {p6, ADC0_0, 128},
+#ifndef TARGET_NRF51_DONGLE
+    {p26, ADC0_0, 1},
+    {p27, ADC0_0, 2},
+#endif
+    {NC, NC, 0}
+};
+
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    uint32_t pinFunc = pinmap_function(pin, PinMap_ADC);
+    MBED_ASSERT(pinFunc != (uint32_t)NC);
+    
+    obj->adc_pin =  pinFunc;
+    
+    ret_code_t ret_code;
+                                              // p_config, event_handler
+    ret_code = nrf_drv_adc_init(NULL , NULL); // select blocking mode
+    MBED_ASSERT((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE)); //NRF_ERROR_INVALID_STATE expected for multiple channels used.
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    nrf_adc_value_t adc_value;
+       
+    nrf_drv_adc_channel_t adc_channel;
+    
+    // initialization by assigment because IAR dosen't support variable initializer in declaration statement.
+    adc_channel.config.config.resolution = NRF_ADC_CONFIG_RES_10BIT;
+    adc_channel.config.config.input      = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE;
+    adc_channel.config.config.reference  = NRF_ADC_CONFIG_REF_VBG;
+    adc_channel.config.config.ain        = (obj->adc_pin);
+    adc_channel.p_next = NULL;
+    
+
+    ret_code_t ret_code;
+    
+    ret_code = nrf_drv_adc_sample_convert( &adc_channel, &adc_value);
+    MBED_ASSERT(ret_code == NRF_SUCCESS);
+    
+    return adc_value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}
+
+#endif // DEVICE_ANALOGIN
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c
new file mode 100644
index 0000000000..c4b5b94a76
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/pwmout_api.c
@@ -0,0 +1,237 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#if DEVICE_PWMOUT
+
+#include "nrf.h"
+#include "nrf_drv_timer.h"
+#include "app_pwm.h"
+
+#define PWM_INSTANCE_COUNT          2
+#define PWM_CHANNELS_PER_INSTANCE   2
+#define PWM_DEFAULT_PERIOD_US       20000
+#define PWM_PERIOD_MIN              3
+
+typedef struct
+{
+    const app_pwm_t * const instance;
+    NRF_TIMER_Type * const  timer_reg;
+    uint8_t                 channels_allocated;
+    uint32_t                pins[PWM_CHANNELS_PER_INSTANCE];
+    uint16_t                period_us;
+    uint16_t                duty_ticks[PWM_CHANNELS_PER_INSTANCE];
+} pwm_t;
+
+
+APP_PWM_INSTANCE(m_pwm_instance_0, 1);   //PWM0: Timer 1
+APP_PWM_INSTANCE(m_pwm_instance_1, 2);   //PWM1: Timer 2
+
+
+static pwm_t m_pwm[] = {
+                    {.instance = &m_pwm_instance_0, .timer_reg = NRF_TIMER1, .channels_allocated = 0},
+                    {.instance = &m_pwm_instance_1, .timer_reg = NRF_TIMER2, .channels_allocated = 0}
+                };
+
+static inline void pwm_ticks_set(pwm_t* pwm, uint8_t channel, uint16_t ticks)
+{
+    pwm->duty_ticks[channel] = ticks;
+    while (app_pwm_channel_duty_ticks_set(pwm->instance, channel, ticks) != NRF_SUCCESS);
+}
+
+static void pwm_reinit(pwm_t * pwm)
+{
+    app_pwm_uninit(pwm->instance);
+    app_pwm_config_t pwm_cfg = APP_PWM_DEFAULT_CONFIG_2CH(pwm->period_us,
+                                                          pwm->pins[0],
+                                                          pwm->pins[1]);
+    app_pwm_init(pwm->instance, &pwm_cfg, NULL);
+    app_pwm_enable(pwm->instance);
+    
+    for (uint8_t channel = 0; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) {
+        if ((pwm->channels_allocated & (1 << channel)) && (pwm->pins[channel] != APP_PWM_NOPIN)) {
+            app_pwm_channel_duty_ticks_set(pwm->instance, channel, pwm->duty_ticks[channel]);
+        }
+    }
+}
+
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+    if (pin == NC) {
+        error("PwmOut init failed. Invalid pin name.");
+    }
+    
+    // Check if pin is already initialized and find the next free channel.
+    uint8_t free_instance = 0xFF;
+    uint8_t free_channel  = 0xFF;
+
+    for (uint8_t inst = 0; inst < PWM_INSTANCE_COUNT; ++inst) {
+        if (m_pwm[inst].channels_allocated) {
+            for (uint8_t channel = 0; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) {
+                if (m_pwm[inst].channels_allocated & (1 << channel)) {
+                    if (m_pwm[inst].pins[channel] == (uint32_t)pin) {
+                        error("PwmOut init failed. Pin is already in use.");
+                        return;
+                    }
+                }
+                else {
+                    if (free_instance == 0xFF) {
+                        free_instance = inst;
+                        free_channel  = channel;
+                    }
+                }
+            }
+        }
+        else {
+            if (free_instance == 0xFF) {
+                free_instance = inst;
+                free_channel  = 0;
+            }
+        }
+    }
+
+    if (free_instance == 0xFF)
+    {
+        error("PwmOut init failed. All available PWM channels are in use.");
+        return;
+    }
+
+    // Init / reinit PWM instance.
+    m_pwm[free_instance].pins[free_channel] = (uint32_t) pin;
+    m_pwm[free_instance].duty_ticks[free_channel] = 0;
+    if (!m_pwm[free_instance].channels_allocated) {
+        m_pwm[free_instance].period_us = PWM_DEFAULT_PERIOD_US;
+        for (uint8_t channel = 1; channel < PWM_CHANNELS_PER_INSTANCE; ++channel) {
+            m_pwm[free_instance].pins[channel] = APP_PWM_NOPIN;
+            m_pwm[free_instance].duty_ticks[channel] = 0;
+        }
+        app_pwm_config_t pwm_cfg = APP_PWM_DEFAULT_CONFIG_1CH(PWM_DEFAULT_PERIOD_US, pin);
+        app_pwm_init(m_pwm[free_instance].instance, &pwm_cfg, NULL);
+        app_pwm_enable(m_pwm[free_instance].instance);
+    }
+    else {
+        pwm_reinit(&m_pwm[free_instance]);
+    }
+    m_pwm[free_instance].channels_allocated |= (1 << free_channel);
+
+    obj->pin         = pin;
+    obj->pwm_struct  = (void *) &m_pwm[free_instance];
+    obj->pwm_channel = free_channel;
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+    MBED_ASSERT(obj->pwm_name != (PWMName)NC);
+    MBED_ASSERT(obj->pwm_channel < PWM_CHANNELS_PER_INSTANCE);
+
+    pwm_t * pwm = (pwm_t *) obj->pwm_struct;
+    pwm->channels_allocated &= ~(1 << obj->pwm_channel);
+    pwm->pins[obj->pwm_channel] = APP_PWM_NOPIN;
+    pwm->duty_ticks[obj->pwm_channel] = 0;
+
+    app_pwm_uninit(pwm->instance);
+    if (pwm->channels_allocated) {
+        pwm_reinit(pwm);
+    }
+
+    obj->pwm_struct = NULL;    
+}
+
+void pwmout_write(pwmout_t *obj, float value)
+{
+    pwm_t * pwm = (pwm_t *) obj->pwm_struct;
+    if (value > 1.0f) {
+        value = 1.0f;
+    }
+
+    app_pwm_channel_duty_set(pwm->instance, obj->pwm_channel, (app_pwm_duty_t)(value * 100.0f) );
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+    pwm_t * pwm = (pwm_t *) obj->pwm_struct;
+    MBED_ASSERT(pwm != NULL);
+    return ((float)pwm->duty_ticks[obj->pwm_channel] / (float)app_pwm_cycle_ticks_get(pwm->instance));
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+    pwmout_period_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+    pwmout_period_us(obj, ms * 1000);
+}
+
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+    pwm_t * pwm = (pwm_t *) obj->pwm_struct;
+    MBED_ASSERT(pwm != NULL);
+    if (us < PWM_PERIOD_MIN) {
+        us = PWM_PERIOD_MIN;
+    }
+    pwm->period_us = (uint32_t)us;
+    pwm_reinit(pwm);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+    pwmout_pulsewidth_us(obj, ms * 1000);
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+    pwm_t * pwm = (pwm_t *) obj->pwm_struct;
+    MBED_ASSERT(pwm);
+    
+    uint16_t ticks = nrf_timer_us_to_ticks((uint32_t)us, nrf_timer_frequency_get(pwm->timer_reg));
+    pwm_ticks_set(pwm, obj->pwm_channel, ticks);
+}
+
+#endif // DEVICE_PWMOUT
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c
new file mode 100644
index 0000000000..6bca7511be
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.c
@@ -0,0 +1,280 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_adc.h"
+#include "nrf_drv_common.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+#include "app_util.h"
+
+typedef struct
+{
+    nrf_drv_adc_event_handler_t event_handler;
+    nrf_drv_adc_channel_t     * p_head;
+    nrf_drv_adc_channel_t     * p_current_conv;
+    nrf_adc_value_t           * p_buffer;
+    uint8_t                     size;
+    uint8_t                     idx;
+    nrf_drv_state_t             state;
+} adc_cb_t;
+
+static adc_cb_t m_cb;
+static const nrf_drv_adc_config_t m_default_config = NRF_DRV_ADC_DEFAULT_CONFIG;
+
+ret_code_t nrf_drv_adc_init(nrf_drv_adc_config_t const * p_config,
+                            nrf_drv_adc_event_handler_t  event_handler)
+{
+    if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    nrf_adc_event_clear(NRF_ADC_EVENT_END);
+    if (event_handler)
+    {
+        if (!p_config)
+        {
+            p_config = (nrf_drv_adc_config_t *)&m_default_config;
+        }
+        nrf_drv_common_irq_enable(ADC_IRQn, p_config->interrupt_priority);
+    }
+    m_cb.event_handler = event_handler;
+    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+void nrf_drv_adc_uninit(void)
+{
+    m_cb.p_head = NULL;
+    nrf_drv_common_irq_disable(ADC_IRQn);
+    nrf_adc_int_disable(NRF_ADC_INT_END_MASK);
+    nrf_adc_task_trigger(NRF_ADC_TASK_STOP);
+
+    m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+void nrf_drv_adc_channel_enable(nrf_drv_adc_channel_t * const p_channel)
+{
+    ASSERT(mp_state == NRF_DRV_STATE_INITIALIZED);
+    ASSERT(!is_address_from_stack(p_channel));
+
+    p_channel->p_next = NULL;
+    if (m_cb.p_head == NULL)
+    {
+        m_cb.p_head = p_channel;
+    }
+    else
+    {
+        nrf_drv_adc_channel_t * p_curr_channel = m_cb.p_head;
+        while (p_curr_channel->p_next != NULL)
+        {
+            ASSERT(p_channel != p_curr_channel);
+            p_curr_channel = p_curr_channel->p_next;
+        }
+        p_curr_channel->p_next = p_channel;
+    }
+}
+
+void nrf_drv_adc_channel_disable(nrf_drv_adc_channel_t * const p_channel)
+{
+    ASSERT(mp_state == NRF_DRV_STATE_INITIALIZED);
+    ASSERT(m_cb.p_head);
+
+    nrf_drv_adc_channel_t * p_curr_channel = m_cb.p_head;
+    nrf_drv_adc_channel_t * p_prev_channel = NULL;
+    while(p_curr_channel != p_channel)
+    {
+        p_prev_channel = p_curr_channel;
+        p_curr_channel = p_curr_channel->p_next;
+        ASSERT(p_curr_channel == NULL);
+    }
+    if (p_prev_channel)
+    {
+        p_prev_channel->p_next = p_curr_channel->p_next;
+    }
+    else
+    {
+        m_cb.p_head = p_curr_channel->p_next;
+    }
+}
+
+void nrf_drv_adc_sample(void)
+{
+    ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(!nrf_adc_is_busy());
+    nrf_adc_start();
+}
+
+ret_code_t nrf_drv_adc_sample_convert(nrf_drv_adc_channel_t const * const p_channel, 
+                                      nrf_adc_value_t * p_value)
+{
+    ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED);
+    if(m_cb.state == NRF_DRV_STATE_POWERED_ON)
+    {
+        return NRF_ERROR_BUSY;
+    }
+    else
+    {
+        m_cb.state = NRF_DRV_STATE_POWERED_ON;
+
+        nrf_adc_config_set(p_channel->config.data);
+        nrf_adc_enable();
+        nrf_adc_int_disable(NRF_ADC_INT_END_MASK);
+        nrf_adc_start();
+        if (p_value)
+        {
+            while(!nrf_adc_event_check(NRF_ADC_EVENT_END)) {}
+            nrf_adc_event_clear(NRF_ADC_EVENT_END);
+            *p_value = (nrf_adc_value_t)nrf_adc_result_get();
+            nrf_adc_disable();
+
+            m_cb.state = NRF_DRV_STATE_INITIALIZED;
+        }
+        else
+        {
+            ASSERT(m_cb.event_handler);
+            m_cb.p_buffer = NULL;
+            nrf_adc_int_enable(NRF_ADC_INT_END_MASK);
+        }
+        return NRF_SUCCESS;
+    }
+}
+
+static bool adc_sample_process()
+{
+    nrf_adc_event_clear(NRF_ADC_EVENT_END);
+    nrf_adc_disable();
+    m_cb.p_buffer[m_cb.idx] = (nrf_adc_value_t)nrf_adc_result_get();
+    m_cb.idx++;
+    if (m_cb.idx < m_cb.size)
+    {
+        bool task_trigger = false;
+        if (m_cb.p_current_conv->p_next == NULL)
+        {
+            m_cb.p_current_conv = m_cb.p_head;
+        }
+        else
+        {
+            m_cb.p_current_conv = m_cb.p_current_conv->p_next;
+            task_trigger = true;
+        }
+        nrf_adc_config_set(m_cb.p_current_conv->config.data);
+        nrf_adc_enable();
+        if (task_trigger)
+        {
+            //nrf_adc_start();
+            nrf_adc_task_trigger(NRF_ADC_TASK_START);
+        }
+        return false;
+    }
+    else
+    {
+        return true;
+    }
+}
+
+ret_code_t nrf_drv_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size)
+{
+    ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED);
+    if(m_cb.state == NRF_DRV_STATE_POWERED_ON)
+    {
+        return NRF_ERROR_BUSY;
+    }
+    else
+    {
+        m_cb.state          = NRF_DRV_STATE_POWERED_ON;
+        m_cb.p_current_conv = m_cb.p_head;
+        m_cb.size           = size;
+        m_cb.idx            = 0;
+        m_cb.p_buffer       = buffer;
+        nrf_adc_config_set(m_cb.p_current_conv->config.data);
+        nrf_adc_event_clear(NRF_ADC_EVENT_END);
+        nrf_adc_enable();
+        if (m_cb.event_handler)
+        {
+            nrf_adc_int_enable(NRF_ADC_INT_END_MASK);
+        }
+        else
+        {
+            while(1)
+            {
+                while(!nrf_adc_event_check(NRF_ADC_EVENT_END)){}
+
+                if (adc_sample_process())
+                {
+                    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+                    break;
+                }
+            }
+        }
+        return NRF_SUCCESS;
+    }
+}
+
+bool nrf_drv_adc_is_busy(void)
+{
+    ASSERT(mp_state != NRF_DRV_STATE_UNINITIALIZED);
+    return (m_cb.state == NRF_DRV_STATE_POWERED_ON) ? true : false;
+}
+
+void ADC_IRQHandler(void)
+{
+    if (m_cb.p_buffer == NULL)
+    {
+        nrf_adc_event_clear(NRF_ADC_EVENT_END);
+        nrf_adc_int_disable(NRF_ADC_INT_END_MASK);
+        nrf_adc_disable();
+        nrf_drv_adc_evt_t evt;
+        evt.type = NRF_DRV_ADC_EVT_SAMPLE;
+        evt.data.sample.sample = (nrf_adc_value_t)nrf_adc_result_get();
+        m_cb.state = NRF_DRV_STATE_INITIALIZED;
+        m_cb.event_handler(&evt);
+    }
+    else if (adc_sample_process())
+    {
+        nrf_adc_int_disable(NRF_ADC_INT_END_MASK);
+        nrf_drv_adc_evt_t evt;
+        evt.type = NRF_DRV_ADC_EVT_DONE;
+        evt.data.done.p_buffer = m_cb.p_buffer;
+        evt.data.done.size     = m_cb.size;
+        m_cb.state = NRF_DRV_STATE_INITIALIZED;
+        m_cb.event_handler(&evt);
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h
new file mode 100644
index 0000000000..832d4d9941
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/drivers_nrf/adc/nrf_drv_adc.h
@@ -0,0 +1,324 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_adc.h"
+#include "nrf_drv_config.h"
+#include "sdk_errors.h"
+#include <stdbool.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @addtogroup nrf_adc ADC HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Analog-to-digital converter (ADC) APIs.
+ * @details The ADC HAL provides basic APIs for accessing the registers of the analog-to-digital converter.
+ * The ADC driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_adc_drv ADC driver
+ * @{
+ * @ingroup nrf_adc
+ * @brief Analog-to-digital converter (ADC) driver. 
+ */
+
+
+/**
+ * @brief Driver event types.
+ */
+typedef enum
+{
+    NRF_DRV_ADC_EVT_DONE,    ///< Event generated when the buffer is filled with samples.
+    NRF_DRV_ADC_EVT_SAMPLE,  ///< Event generated when the requested channel is sampled.
+} nrf_drv_adc_evt_type_t;
+
+typedef int16_t nrf_adc_value_t;
+
+/**
+ * @brief Analog-to-digital converter driver DONE event.
+ */
+typedef struct
+{
+    nrf_adc_value_t *        p_buffer; ///< Pointer to buffer with converted samples.
+    uint16_t                 size;     ///< Number of samples in the buffer.
+} nrf_drv_adc_done_evt_t;
+
+/**
+ * @brief Analog-to-digital converter driver SAMPLE event.
+ */
+typedef struct
+{
+    nrf_adc_value_t   sample; ///< Converted sample.
+} nrf_drv_adc_sample_evt_t;
+
+/**
+ * @brief Analog-to-digital converter driver event.
+ */
+typedef struct
+{
+    nrf_drv_adc_evt_type_t type;  ///< Event type.
+    union
+    {
+        nrf_drv_adc_done_evt_t   done;   ///< Data for DONE event.
+        nrf_drv_adc_sample_evt_t sample; ///< Data for SAMPLE event.
+    } data;
+} nrf_drv_adc_evt_t;
+
+/**@brief Macro for initializing the ADC channel with the default configuration. */
+#define NRF_DRV_ADC_DEFAULT_CHANNEL(analog_input)          \
+ {{{                                                       \
+    .resolution = NRF_ADC_CONFIG_RES_10BIT,                \
+    .input      = NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE, \
+    .reference  = NRF_ADC_CONFIG_REF_VBG,                  \
+    .ain        = (analog_input)                           \
+ }}, NULL}
+
+/**
+ * @brief ADC channel configuration.
+ *
+ * @note The bit fields reflect bit fields in the ADC CONFIG register.
+ */
+typedef struct 
+{
+    uint32_t resolution        :2; ///< 8-10 bit resolution.
+    uint32_t input             :3; ///< Input selection and scaling.
+    uint32_t reference         :2; ///< Reference source.
+    uint32_t reserved          :1; ///< Unused bit fields.
+    uint32_t ain               :8; ///< Analog input.
+    uint32_t external_reference:2; ///< Eternal reference source.
+}nrf_drv_adc_channel_config_t;
+
+// Forward declaration of the nrf_drv_adc_channel_t type.
+typedef struct nrf_drv_adc_channel_s nrf_drv_adc_channel_t;
+
+/**
+ * @brief ADC channel.
+ *
+ * This structure is defined by the user and used by the driver. Therefore, it should
+ * not be defined on the stack as a local variable.
+ */
+struct nrf_drv_adc_channel_s
+{
+    union
+    {
+        nrf_drv_adc_channel_config_t config; ///< Channel configuration.
+        uint32_t data;                       ///< Raw value.
+    } config;
+    nrf_drv_adc_channel_t      * p_next;     ///< Pointer to the next enabled channel (for internal use).
+};
+
+/**
+ * @brief ADC configuration.
+ */
+typedef struct 
+{
+    uint8_t interrupt_priority;              ///< Priority of ADC interrupt.
+} nrf_drv_adc_config_t;
+
+/** @brief ADC default configuration. */
+#define NRF_DRV_ADC_DEFAULT_CONFIG                \
+{                                                 \
+    .interrupt_priority = ADC_CONFIG_IRQ_PRIORITY \
+}
+
+/**
+ * @brief User event handler prototype.
+ *
+ * This function is called when the requested number of samples has been processed.
+ *
+ * @param p_event Event.
+ */
+typedef void (*nrf_drv_adc_event_handler_t)(nrf_drv_adc_evt_t const * p_event);
+
+/**
+ * @brief Function for initializing the ADC.
+ *
+ * If a valid event handler is provided, the driver is initialized in non-blocking mode.
+ * If event_handler is NULL, the driver works in blocking mode.
+ *
+ * @param[in] p_config Driver configuration.
+ * @param[in] event_handler Event handler provided by the user.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the driver is already initialized.
+ */
+ret_code_t nrf_drv_adc_init(nrf_drv_adc_config_t const * p_config,
+                            nrf_drv_adc_event_handler_t  event_handler);
+
+/**
+ * @brief Function for uninitializing the ADC.
+ *
+ * This function stops all ongoing conversions and disables all channels.
+ */
+void nrf_drv_adc_uninit(void);
+
+/**
+ * @brief Function for enabling an ADC channel.
+ *
+ * This function configures and enables the channel. When @ref nrf_drv_adc_buffer_convert is
+ * called, all channels that have been enabled with this function are sampled.
+ *
+ * @note The channel instance variable @p p_channel is used by the driver as an item
+ *       in a list. Therefore, it cannot be an automatic variable, and an assertion fails if it is
+ *       an automatic variable (if asserts are enabled).
+ */
+void nrf_drv_adc_channel_enable(nrf_drv_adc_channel_t * const p_channel);
+
+/**
+ * @brief Function for disabling an ADC channel.
+ */
+void nrf_drv_adc_channel_disable(nrf_drv_adc_channel_t * const p_channel);
+
+/**
+ * @brief Function for starting ADC sampling.
+ *
+ * This function triggers single ADC sampling. If more than one channel is enabled, the driver
+ * emulates scanning and all channels are sampled in the order they were enabled.
+ */
+void nrf_drv_adc_sample(void);
+
+/**
+ * @brief Function for executing a single ADC conversion.
+ *
+ * This function selects the desired input and starts a single conversion. If a valid pointer 
+ * is provided for the result, the function blocks until the conversion is completed. Otherwise, the
+ * function returns when the conversion is started, and the result is provided in an event (driver
+ * must be initialized in non-blocking mode otherwise an assertion will fail). The function will fail if
+ * ADC is busy. The channel does not need to be enabled to perform a single conversion.
+ *
+ * @param[in]  p_channel Channel.
+ * @param[out] p_value   Pointer to the location where the result should be placed. Unless NULL is
+ *                       provided, the function is blocking.
+ *
+ * @retval NRF_SUCCESS    If conversion was successful.
+ * @retval NRF_ERROR_BUSY If the ADC driver is busy.
+ */
+ret_code_t nrf_drv_adc_sample_convert(nrf_drv_adc_channel_t const * const p_channel, 
+                                      nrf_adc_value_t * p_value);
+
+/**
+ * @brief Function for converting data to the buffer.
+ *
+ * If the driver is initialized in non-blocking mode, this function returns when the first conversion
+ * is set up. When the buffer is filled, the application is notified by the event handler. If the
+ * driver is initialized in blocking mode, the function returns when the buffer is filled.
+ *
+ * Conversion is done on all enabled channels, but it is not triggered by this
+ * function. This function will prepare the ADC for sampling and then 
+ * wait for the SAMPLE task. Sampling can be triggered manually by the @ref 
+ * nrf_drv_adc_sample function or by PPI using the @ref NRF_ADC_TASK_START task.
+ *
+ * @note If more than one channel is enabled, the function emulates scanning, and 
+ * a single START task will trigger conversion on all enabled channels. For example:
+ * If 3 channels are enabled and the user requests 6 samples, the completion event 
+ * handler will be called after 2 START tasks. 
+ * @note The application must adjust the sampling frequency. The maximum frequency 
+ * depends on the sampling timer and the maximum latency of the ADC interrupt. If 
+ * an interrupt is not handled before the next sampling is triggered, the sample 
+ * will be lost.
+ *
+ * @param[in] buffer Result buffer.
+ * @param[in] size   Buffer size in samples.
+ *
+ * @retval NRF_SUCCESS    If conversion was successful.
+ * @retval NRF_ERROR_BUSY If the driver is busy.
+ */
+ret_code_t nrf_drv_adc_buffer_convert(nrf_adc_value_t * buffer, uint16_t size);
+
+/**
+ * @brief Function for retrieving the ADC state.
+ *
+ * @retval true  If the ADC is busy.
+ * @retval false If the ADC is ready.
+ */
+bool nrf_drv_adc_is_busy(void);
+
+/**
+ * @brief Function for getting the address of the ADC START task.
+ *
+ * This function is used to get the address of the START task, which can be used to trigger ADC
+ * conversion.
+ *
+ * @return Start task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_adc_start_task_get(void);
+
+/**
+ * @brief Function for converting a GPIO pin number to an analog input pin mask to be used in
+ *        the ADC channel configuration.
+ *
+ * @param[in]  pin GPIO pin.
+ *
+ * @return     Analog input pin mask. The function returns @ref NRF_ADC_CONFIG_INPUT_DISABLED
+ *             if the specified pin is not an analog input.
+ */
+__STATIC_INLINE nrf_adc_config_input_t nrf_drv_adc_gpio_to_ain(uint32_t pin);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t nrf_drv_adc_start_task_get(void)
+{
+    return nrf_adc_task_address_get(NRF_ADC_TASK_START);
+}
+
+__STATIC_INLINE nrf_adc_config_input_t nrf_drv_adc_gpio_to_ain(uint32_t pin)
+{
+    // AIN2 - AIN7
+    if (pin >= 1 && pin <= 6)
+    {
+        return (nrf_adc_config_input_t)(1 << (pin+1));
+    }
+    // AIN0 - AIN1
+    else if (pin >= 26 && pin <= 27)
+    {
+        return (nrf_adc_config_input_t)(1 <<(pin - 26));
+    }
+    else
+    {
+        return NRF_ADC_CONFIG_INPUT_DISABLED;
+    }
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h
new file mode 100644
index 0000000000..cbf187048d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/nrf_drv_config.h
@@ -0,0 +1,495 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED  1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ          NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC             NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY       APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8
+#endif
+
+/* TIMER */
+#ifdef SOFTDEVICE_PRESENT
+#define TIMER0_ENABLED 0
+#else
+#define TIMER0_ENABLED 1
+#endif
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX      0
+#endif
+
+#define TIMER1_ENABLED 1
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX      (TIMER0_ENABLED)
+#endif
+ 
+#define TIMER2_ENABLED 1
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX      (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX      (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX      (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY    32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE     false
+
+#define RTC0_INSTANCE_INDEX      0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY    32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE     false
+
+#define RTC1_INSTANCE_INDEX      (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY    32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE     false
+
+#define RTC2_INSTANCE_INDEX      (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT                (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 0
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE        8
+#define RNG_CONFIG_IRQ_PRIORITY     APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 0
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN        2
+#define PWM0_CONFIG_OUT1_PIN        3
+#define PWM0_CONFIG_OUT2_PIN        4
+#define PWM0_CONFIG_OUT3_PIN        5
+#define PWM0_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK      NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE      NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE       1000
+#define PWM0_CONFIG_LOAD_MODE       NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE       NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 0
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN        2
+#define PWM1_CONFIG_OUT1_PIN        3
+#define PWM1_CONFIG_OUT2_PIN        4
+#define PWM1_CONFIG_OUT3_PIN        5
+#define PWM1_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK      NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE      NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE       1000
+#define PWM1_CONFIG_LOAD_MODE       NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE       NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 0
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN        2
+#define PWM2_CONFIG_OUT1_PIN        3
+#define PWM2_CONFIG_OUT2_PIN        4
+#define PWM2_CONFIG_OUT3_PIN        5
+#define PWM2_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK      NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE      NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE       1000
+#define PWM2_CONFIG_LOAD_MODE       NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE       NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT   (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 0
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+
+#define SPI0_CONFIG_SCK_PIN         2
+#define SPI0_CONFIG_MOSI_PIN        3
+#define SPI0_CONFIG_MISO_PIN        4
+#define SPI0_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 1
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN         2
+#define SPI1_CONFIG_MOSI_PIN        3
+#define SPI1_CONFIG_MISO_PIN        4
+#define SPI1_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 0
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN         2
+#define SPI2_CONFIG_MOSI_PIN        3
+#define SPI2_CONFIG_MISO_PIN        4
+#define SPI2_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT   (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 0
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN         2
+#define SPIS0_CONFIG_MOSI_PIN        3
+#define SPIS0_CONFIG_MISO_PIN        4
+#define SPIS0_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 1
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN         2
+#define SPIS1_CONFIG_MOSI_PIN        3
+#define SPIS1_CONFIG_MISO_PIN        4
+#define SPIS1_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 0
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN         2
+#define SPIS2_CONFIG_MOSI_PIN        3
+#define SPIS2_CONFIG_MISO_PIN        4
+#define SPIS2_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT   (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC         NRF_UART_HWFC_ENABLED
+#define UART0_CONFIG_PARITY       NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE     NRF_UART_BAUDRATE_9600
+#define UART0_CONFIG_PSEL_TXD     9
+#define UART0_CONFIG_PSEL_RXD     11
+#define UART0_CONFIG_PSEL_CTS     10
+#define UART0_CONFIG_PSEL_RTS     8
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT     1
+#define UART_LEGACY_SUPPORT       1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY    NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL          0
+#define TWI0_CONFIG_SDA          1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX      0
+#endif
+
+#define TWI1_ENABLED 1
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY    NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL          0
+#define TWI1_CONFIG_SDA          1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX      (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT                (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 0
+
+#if (TWIS0_ENABLED == 1)
+    #define TWIS0_CONFIG_ADDR0        0
+    #define TWIS0_CONFIG_ADDR1        0 /* 0: Disabled */
+    #define TWIS0_CONFIG_SCL          0
+    #define TWIS0_CONFIG_SDA          1
+    #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+    #define TWIS0_INSTANCE_INDEX      0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED ==  1)
+    #define TWIS1_CONFIG_ADDR0        0
+    #define TWIS1_CONFIG_ADDR1        0 /* 0: Disabled */
+    #define TWIS1_CONFIG_SCL          0
+    #define TWIS1_CONFIG_SDA          1
+    #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+    #define TWIS1_INSTANCE_INDEX      (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 0
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER    NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER    NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A        1
+#define QDEC_CONFIG_PIO_B        2
+#define QDEC_CONFIG_PIO_LED      3
+#define QDEC_CONFIG_LEDPRE       511
+#define QDEC_CONFIG_LEDPOL       NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN        false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 1
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 0
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION      NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE      NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE            NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE            NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ      NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 0
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF     		NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE		NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE		NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST			NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE			NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY 	APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT        	NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 0
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE    NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION    NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT        NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 0
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR     NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE  2000
+#define WDT_CONFIG_IRQ_PRIORITY  APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+    #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 0
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN      22
+#define I2S_CONFIG_LRCK_PIN     23
+#define I2S_CONFIG_MCK_PIN      NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN    24
+#define I2S_CONFIG_SDIN_PIN     25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER       NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT       NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN        NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH       NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS     NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP    NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO        NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h
new file mode 100644
index 0000000000..09a00582dd
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf51/nrf_mbr.h
@@ -0,0 +1,202 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @defgroup nrf_mbr_api Master Boot Record API
+  @{
+
+  @brief APIs for updating SoftDevice and BootLoader
+
+*/
+
+/* Header guard */
+#ifndef NRF_MBR_H__
+#define NRF_MBR_H__
+
+#include "nrf_svc.h"
+#include <stdint.h>
+
+#ifndef NRF51
+#error "This header file shall only be included for nRF51 projects"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_MBR_DEFINES Defines
+ * @{ */
+
+/**@brief MBR SVC Base number. */
+#define MBR_SVC_BASE        (0x18)
+
+/**@brief Page size in words. */
+#define PAGE_SIZE_IN_WORDS 256
+/** @} */
+
+/** @brief The size that must be reserved for the MBR when a softdevice is written to flash.
+This is the offset where the first byte of the softdevice hex file is written.*/
+#define MBR_SIZE                (0x1000)
+
+/** @addtogroup NRF_MBR_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF Master Boot Record API SVC numbers. */
+enum NRF_MBR_SVCS
+{
+  SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */
+};
+
+/**@brief Possible values for ::sd_mbr_command_t.command */
+enum NRF_MBR_COMMANDS
+{
+  SD_MBR_COMMAND_COPY_BL,               /**< Copy a new BootLoader. @see sd_mbr_command_copy_bl_t */
+  SD_MBR_COMMAND_COPY_SD,               /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/
+  SD_MBR_COMMAND_INIT_SD,               /**< Init forwarding interrupts to SD, and run reset function in SD*/
+  SD_MBR_COMMAND_COMPARE,               /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/
+  SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Start forwarding all exception to this address @see ::sd_mbr_command_vector_table_base_set_t*/
+};
+
+/** @} */
+
+/** @addtogroup NRF_MBR_TYPES Types
+ * @{ */
+
+/**@brief This command copies part of a new SoftDevice
+ * The destination area is erased before copying.
+ * If dst is in the middle of a flash page, that whole flash page will be erased.
+ * If (dst+len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * The user of this function is responsible for setting the PROTENSET registers.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly.
+ * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying.
+ */
+typedef struct
+{
+  uint32_t *src;  /**< Pointer to the source of data to be copied.*/
+  uint32_t *dst;  /**< Pointer to the destination where the content is to be copied.*/
+  uint32_t len;   /**< Number of 32 bit words to copy. Must be a multiple of @ref PAGE_SIZE_IN_WORDS words.*/
+} sd_mbr_command_copy_sd_t;
+
+
+/**@brief This command works like memcmp, but takes the length in words.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal.
+ * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal.
+ */
+typedef struct
+{
+  uint32_t *ptr1; /**< Pointer to block of memory. */
+  uint32_t *ptr2; /**< Pointer to block of memory. */
+  uint32_t len;   /**< Number of 32 bit words to compare.*/
+} sd_mbr_command_compare_t;
+
+
+/**@brief This command copies a new BootLoader.
+ *  With this command, destination of BootLoader is always the address written in NRF_UICR->BOOTADDR.
+ *
+ *  Destination is erased by this function.
+ *  If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ *  This function will use PROTENSET to protect the flash that is not intended to be written.
+ *
+ *  On Success, this function will not return. It will start the new BootLoader from reset-vector as normal.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_FORBIDDEN if NRF_UICR->BOOTADDR is not set.
+ * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area.
+ */
+typedef struct
+{
+  uint32_t *bl_src;  /**< Pointer to the source of the Bootloader to be be copied.*/
+  uint32_t bl_len;   /**< Number of 32 bit words to copy for BootLoader. */
+} sd_mbr_command_copy_bl_t;
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR
+ *
+ * Once this function has been called, this address is where the MBR will start to forward interrupts to after a reset.
+ *
+ * To restore default forwarding this function should be called with @param address set to 0.
+ * The MBR will then start forwarding to interrupts to the address in NFR_UICR->BOOTADDR or to the SoftDevice if the BOOTADDR is not set.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size.
+ */
+typedef struct
+{
+  uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_vector_table_base_set_t;
+
+typedef struct
+{
+  uint32_t command;  /**< type of command to be issued see @ref NRF_MBR_COMMANDS. */
+  union
+  {
+    sd_mbr_command_copy_sd_t copy_sd;  /**< Parameters for copy SoftDevice.*/
+    sd_mbr_command_copy_bl_t copy_bl;  /**< Parameters for copy BootLoader.*/
+    sd_mbr_command_compare_t compare;  /**< Parameters for verify.*/
+    sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set.*/
+  } params;
+} sd_mbr_command_t;
+
+/** @} */
+
+/** @addtogroup NRF_MBR_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Issue Master Boot Record commands
+ *
+ * Commands used when updating a SoftDevice and bootloader.
+ *
+ * @param[in]  param Pointer to a struct describing the command.
+ *
+ *@note for retvals see ::sd_mbr_command_copy_sd_t ::sd_mbr_command_copy_bl_t ::sd_mbr_command_compare_t
+
+*/
+SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param));
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_MBR_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h
new file mode 100644
index 0000000000..71e3984776
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble.h
@@ -0,0 +1,635 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON BLE SoftDevice Common
+  @{
+  @defgroup ble_api Events, type definitions and API calls
+  @{
+
+  @brief Module independent events, type definitions and API calls for the BLE SoftDevice.
+
+ */
+
+#ifndef NRF_BLE_H__
+#define NRF_BLE_H__
+
+#include "nrf_ble_ranges.h"
+#include "nrf_ble_types.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble_l2cap.h"
+#include "nrf_ble_gatt.h"
+#include "nrf_ble_gattc.h"
+#include "nrf_ble_gatts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations
+ * @{ */
+
+/**
+ * @brief Common API SVC numbers.
+ */
+enum BLE_COMMON_SVCS
+{
+  SD_BLE_ENABLE = BLE_SVC_BASE,         /**< Enable and initialize the BLE stack */
+  SD_BLE_EVT_GET,                       /**< Get an event from the pending events queue. */
+  SD_BLE_TX_PACKET_COUNT_GET,           /**< Get the total number of available application transmission packets for a particular connection. */
+  SD_BLE_UUID_VS_ADD,                   /**< Add a Vendor Specific UUID. */
+  SD_BLE_UUID_DECODE,                   /**< Decode UUID bytes. */
+  SD_BLE_UUID_ENCODE,                   /**< Encode UUID bytes. */
+  SD_BLE_VERSION_GET,                   /**< Get the local version information (company id, Link Layer Version, Link Layer Subversion). */
+  SD_BLE_USER_MEM_REPLY,                /**< User Memory Reply. */
+  SD_BLE_OPT_SET,                       /**< Set a BLE option. */
+  SD_BLE_OPT_GET,                       /**< Get a BLE option. */
+};
+
+  /**
+   * @brief BLE Module Independent Event IDs.
+   */
+enum BLE_COMMON_EVTS
+{
+  BLE_EVT_TX_COMPLETE  = BLE_EVT_BASE,  /**< Transmission Complete. @ref ble_evt_tx_complete_t */
+  BLE_EVT_USER_MEM_REQUEST,             /**< User Memory request. @ref ble_evt_user_mem_request_t */
+  BLE_EVT_USER_MEM_RELEASE              /**< User Memory release. @ref ble_evt_user_mem_release_t */
+};
+
+/**@brief BLE connection bandwidth types.
+ * Bandwidth types supported by the SoftDevice in packets per connection interval.
+ */
+enum BLE_CONN_BWS
+{
+  BLE_CONN_BW_NONE = 0,
+  BLE_CONN_BW_LOW,
+  BLE_CONN_BW_MID,
+  BLE_CONN_BW_HIGH
+};
+
+/**@brief Common Option IDs.
+ * IDs that uniquely identify a common option.
+ */
+enum BLE_COMMON_OPTS
+{
+  BLE_COMMON_OPT_CONN_BW = BLE_OPT_BASE,     /**< Bandwidth configuration @ref ble_common_opt_conn_bw_t */
+  BLE_COMMON_OPT_PA_LNA                      /**< PA and LNA options */
+};
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_DEFINES Defines
+ * @{ */
+
+/** @brief  Required pointer alignment for BLE Events.
+*/
+#define BLE_EVTS_PTR_ALIGNMENT    4
+
+/** @defgroup BLE_USER_MEM_TYPES User Memory Types
+ * @{ */
+#define BLE_USER_MEM_TYPE_INVALID               0x00  /**< Invalid User Memory Types. */
+#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES   0x01  /**< User Memory for GATTS queued writes. */
+/** @} */
+
+/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific UUID counts
+ * @{
+ */
+#define BLE_UUID_VS_COUNT_MIN         1    /**< Minimum VS UUID count. */
+#define BLE_UUID_VS_COUNT_DEFAULT     0    /**< Use the default VS UUID count (10 for this version of the SoftDevice). */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_STRUCTURES Structures
+ * @{ */
+
+/**@brief User Memory Block. */
+typedef struct
+{
+  uint8_t          *p_mem;      /**< Pointer to the start of the user memory block. */
+  uint16_t          len;        /**< Length in bytes of the user memory block. */
+} ble_user_mem_block_t;
+
+/**
+ * @brief Event structure for @ref BLE_EVT_TX_COMPLETE.
+ */
+typedef struct
+{
+  uint8_t count;                        /**< Number of packets transmitted. */
+} ble_evt_tx_complete_t;
+
+/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */
+typedef struct
+{
+  uint8_t                     type;     /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
+} ble_evt_user_mem_request_t;
+
+/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */
+typedef struct
+{
+  uint8_t                     type;       /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
+  ble_user_mem_block_t        mem_block;  /**< User memory block */
+} ble_evt_user_mem_release_t;
+
+
+/**@brief Event structure for events not associated with a specific function module. */
+typedef struct
+{
+  uint16_t conn_handle;                 /**< Connection Handle on which this event occurred. */
+  union
+  {
+    ble_evt_tx_complete_t           tx_complete;        /**< Transmission Complete. */
+    ble_evt_user_mem_request_t      user_mem_request;   /**< User Memory Request Event Parameters. */
+    ble_evt_user_mem_release_t      user_mem_release;   /**< User Memory Release Event Parameters. */
+  } params;
+} ble_common_evt_t;
+
+/**@brief BLE Event header. */
+typedef struct
+{
+  uint16_t evt_id;                /**< Value from a BLE_<module>_EVT series. */
+  uint16_t evt_len;               /**< Length in octets including this header. */
+} ble_evt_hdr_t;
+
+/**@brief Common BLE Event type, wrapping the module specific event reports. */
+typedef struct
+{
+  ble_evt_hdr_t header;           /**< Event header. */
+  union
+  {
+    ble_common_evt_t  common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */
+    ble_gap_evt_t     gap_evt;    /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */
+    ble_l2cap_evt_t   l2cap_evt;  /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */
+    ble_gattc_evt_t   gattc_evt;  /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */
+    ble_gatts_evt_t   gatts_evt;  /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */
+  } evt;
+} ble_evt_t;
+
+
+/**
+ * @brief Version Information.
+ */
+typedef struct
+{
+  uint8_t   version_number;    /**< Link Layer Version number for BT 4.1 spec is 7 (https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer). */
+  uint16_t  company_id;        /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */
+  uint16_t  subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */
+} ble_version_t;
+
+/* @brief: Configuration parameters for the PA and LNA. */
+typedef struct
+{
+     uint8_t enable :1;      /**< Enable toggling for this amplifier */
+     uint8_t active_high :1; /**< Set the pin to be active high */
+     uint8_t gpio_pin :6;    /**< The GPIO pin to toggle for this amplifier */
+} ble_pa_lna_cfg_t;
+
+/*
+ * @brief PA & LNA GPIO toggle configuration
+ *
+ * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or
+ * a low noise amplifier.
+ *
+ * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided
+ * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled.
+ *
+ * @note  @ref sd_ble_opt_get is not supported for this option.
+ * @note  This feature is only supported for nRF52, on nRF51 @ref NRF_ERROR_NOT_SUPPORTED will always be returned.
+ * @note  Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences
+ * and must be avoided by the application.
+ *
+ */
+typedef struct
+{
+   ble_pa_lna_cfg_t pa_cfg;   /**< Power Amplifier configuration */
+   ble_pa_lna_cfg_t lna_cfg;  /**< Low Noise Amplifier configuration */
+
+   uint8_t ppi_ch_id_set;     /**< PPI channel used for radio pin setting */
+   uint8_t ppi_ch_id_clr;     /**< PPI channel used for radio pin clearing */
+   uint8_t gpiote_ch_id;      /**< GPIOTE channel used for radio pin toggling */
+} ble_common_opt_pa_lna_t;
+
+/**
+ * @brief BLE connection bandwidth configuration parameters
+ */
+typedef struct
+{
+  uint8_t conn_bw_tx;   /**< Connection bandwidth configuration for transmission, see @ref BLE_CONN_BWS.*/
+  uint8_t conn_bw_rx;   /**< Connection bandwidth configuration for reception, see @ref BLE_CONN_BWS.*/
+} ble_conn_bw_t;
+
+/**@brief BLE connection specific bandwidth configuration parameters.
+ *
+ * This can be used with @ref sd_ble_opt_set to set the bandwidth configuration to be used when creating connections.
+ *
+ * Call @ref sd_ble_opt_set with this option prior to calling @ref sd_ble_gap_adv_start or @ref sd_ble_gap_connect.
+ *
+ * The bandwidth configurations set via @ref sd_ble_opt_set are maintained separately for central and peripheral
+ * connections. The given configurations are used for all future connections of the role indicated in this structure
+ * unless they are changed by subsequent @ref sd_ble_opt_set calls.
+ *
+ * @note When this option is not used, the SoftDevice will use the default options:
+ * - @ref BLE_CONN_BW_HIGH for @ref BLE_GAP_ROLE_PERIPH connections (both transmission and reception).
+ * - @ref BLE_CONN_BW_MID for @ref BLE_GAP_ROLE_CENTRAL connections (both transmisison and reception).
+ * This option allows the application to selectively override these defaults for each role.
+ *
+ * @note The global memory pool configuration can be set with the @ref ble_conn_bw_counts_t configuration parameter, which
+ * is provided to @ref sd_ble_enable.
+ *
+ * @note Please refer to SoftDevice Specification for more information on bandwidth configuration.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::BLE_ERROR_INVALID_ROLE The role is invalid.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid bandwidth configuration parameters.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED If the combination of role and bandwidth configuration is not supported.
+ */
+typedef struct
+{
+  uint8_t            role;     /**< BLE role of the connection, see @ref BLE_GAP_ROLES. */
+  ble_conn_bw_t      conn_bw;  /**< Bandwidth configuration parameters. */
+} ble_common_opt_conn_bw_t;
+
+/**@brief Option structure for common options. */
+typedef union
+{
+  ble_common_opt_conn_bw_t conn_bw;       /**< Parameters for the connection bandwidth option. */
+  ble_common_opt_pa_lna_t  pa_lna;        /**< Parameters for controlling PA and LNA pin toggling. */
+} ble_common_opt_t;
+
+/**@brief Common BLE Option type, wrapping the module specific options. */
+typedef union
+{
+  ble_common_opt_t  common_opt;         /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */
+  ble_gap_opt_t     gap_opt;            /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */
+} ble_opt_t;
+
+/**
+ * @brief BLE bandwidth count parameters
+ *
+ * These parameters are used to configure the memory pools allocated within the SoftDevice for application packets
+ * (both transmission and reception) for all connections.
+ *
+ * @note The sum of all three counts must add up to the sum of @ref ble_gap_enable_params_t::central_conn_count and
+ * @ref ble_gap_enable_params_t::periph_conn_count in @ref ble_gap_enable_params_t.
+ */
+typedef struct {
+  uint8_t high_count;   /**< Total number of high bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+  uint8_t mid_count;    /**< Total number of medium bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+  uint8_t low_count;    /**< Total number of low bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+} ble_conn_bw_count_t;
+
+/**
+ * @brief BLE bandwidth global memory pool configuration parameters
+ *
+ * These configuration parameters are used to set the amount of memory dedicated to application packets for
+ * all connections. The application should specify the most demanding configuration for the intended use.
+ *
+ * Please refer to the SoftDevice Specification for more information on bandwidth configuration.
+ *
+ * @note Each connection created at runtime requires both a TX and an RX memory pool. By the use of these configuration
+ * parameters, the application can decide the size and total number of the global memory pools that will be later
+ * available for connection creation.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ */
+typedef struct {
+  ble_conn_bw_count_t tx_counts;   /**< Global memory pool configuration for transmission.*/
+  ble_conn_bw_count_t rx_counts;   /**< Global memory pool configuration for reception.*/
+} ble_conn_bw_counts_t;
+
+/**
+ * @brief BLE Common Initialization parameters.
+ *
+ * @note If @ref p_conn_bw_counts is NULL the SoftDevice will assume default bandwidth configuration for all connections.
+ * To fit a custom bandwidth configuration requirement, the application developer may have to specify a custom memory
+ * pool configuration here. See @ref ble_common_opt_conn_bw_t for bandwidth configuration of individual connections.
+ * Please refer to the SoftDevice Specification for more information on bandwidth configuration.
+ */
+typedef struct
+{
+  uint16_t                  vs_uuid_count;     /**< Maximum number of 128-bit, Vendor Specific UUID bases to allocate. */
+  ble_conn_bw_counts_t      *p_conn_bw_counts; /**< Bandwidth configuration parameters or NULL for defaults. */
+} ble_common_enable_params_t;
+
+/**
+ * @brief BLE Initialization parameters.
+ */
+typedef struct
+{
+  ble_common_enable_params_t        common_enable_params;  /**< Common init parameters @ref ble_common_enable_params_t. */
+  ble_gap_enable_params_t           gap_enable_params;   /**< GAP init parameters @ref ble_gap_enable_params_t. */
+  ble_gatts_enable_params_t         gatts_enable_params; /**< GATTS init parameters @ref ble_gatts_enable_params_t. */
+} ble_enable_params_t;
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Enable the BLE stack
+ *
+ * @param[in, out] p_ble_enable_params Pointer to ble_enable_params_t
+ * @param[in, out] p_app_ram_base      Pointer to a variable containing the start address of the application RAM region
+ * (APP_RAM_BASE). On return, this will contain the minimum start address of the application RAM region required by the
+ * SoftDevice for this configuration. Calling @ref sd_ble_enable() with *p_app_ram_base set to 0 can be used during
+ * development to find out how much memory a specific configuration will need.
+ *
+ * @note The memory requirement for a specific configuration will not increase between SoftDevices with the same major
+ * version number.
+ *
+ * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located between 0x20000000 and
+ *       APP_RAM_BASE-1 and the application's RAM region is located between APP_RAM_BASE and the start of the call stack.
+ *
+ * @details This call initializes the BLE stack, no other BLE related function can be called before this one.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_ENABLE}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS              The BLE stack has been initialized successfully.
+ * @retval ::NRF_ERROR_INVALID_STATE  The BLE stack had already been initialized and cannot be reinitialized.
+ * @retval ::NRF_ERROR_INVALID_ADDR   Invalid or not sufficiently aligned pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_LENGTH The specified Attribute Table size is either too small or not a multiple of 4.
+ *                                    The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN.
+ * @retval ::NRF_ERROR_INVALID_PARAM  Incorrectly configured VS UUID count or connection count parameters.
+ * @retval ::NRF_ERROR_NO_MEM         The amount of memory assigned to the SoftDevice by *p_app_ram_base is not
+ *                                    large enough to fit this configuration's memory requirement. Check *p_app_ram_base
+ *                                    and set the start address of the application RAM region accordingly.
+ * @retval ::NRF_ERROR_CONN_COUNT     The requested number of connections exceeds the maximum supported by the SoftDevice.
+ *                                    Please refer to the SoftDevice Specification for more information on role configuration.
+ */
+SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(ble_enable_params_t * p_ble_enable_params, uint32_t * p_app_ram_base));
+
+/**@brief Get an event from the pending events queue.
+ *
+ * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length.
+ *                    This buffer <b>must be 4-byte aligned in memory</b>.
+ * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length.
+ *
+ * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that
+ * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt.
+ * The application is free to choose whether to call this function from thread mode (main context) or directly from the
+ * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher
+ * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned)
+ * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so
+ * could potentially leave events in the internal queue without the application being aware of this fact. Sizing the
+ * p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to
+ * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event,
+ * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size.
+ * Please note that because of the variable length nature of some events, sizeof(ble_evt_t) will not always be large
+ * enough to fit certain events, and so it is the application's responsibility to provide an amount of memory large
+ * enough so that the relevant event is copied in full. The application may "peek" the event length by providing p_dest
+ * as a NULL pointer and inspecting the value of *p_len upon return:
+ *
+ *     \code
+ *     uint16_t len;
+ *     errcode = sd_ble_evt_get(NULL, &len);
+ *     \endcode
+ *
+ * @note The pointer supplied must be aligned to the extend defined by @ref BLE_EVTS_PTR_ALIGNMENT
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC}
+ * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled.
+ * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer.
+ */
+SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len));
+
+
+/**@brief Get the total number of available guaranteed application transmission packets for a particular connection.
+ *
+ * @details This call allows the application to obtain the total number of guaranteed application transmission packets
+ * available for a connection. Please note that this does not return the number of free packets, but rather the total
+ * amount of them for that particular connection. The application has two options to handle transmitting application packets:
+ * - Use a simple arithmetic calculation: after connection creation time the application should use this function to
+ * find out the total amount of guaranteed packets available to it and store it in a variable.
+ * Every time a packet is successfully queued for a transmission on this connection using any of the exposed functions in
+ * this  BLE API, the application should decrement that variable. Conversely, whenever a @ref BLE_EVT_TX_COMPLETE event
+ * with the conn_handle matching the particular connection is received by the application, it should retrieve the count
+ * field in such event and add that number to the same variable storing the number of available guaranteed packets. This
+ * mechanism allows the application to be aware at any time of the number of guaranteed application packets available for
+ * each of the active connections, and therefore it can know with certainty whether it is possible to send more data or
+ * it has to wait for a @ref BLE_EVT_TX_COMPLETE event before it proceeds.
+ * The application can still pursue transmissions when the number of guaranteed application packets available is smaller
+ * than or equal to zero, but successful queuing of the tranmsission is not guaranteed.
+ * - Choose to simply not keep track of available packets at all, and instead handle the @ref BLE_ERROR_NO_TX_PACKETS error
+ * by queueing the packet to be transmitted and try again as soon as a @ref BLE_EVT_TX_COMPLETE event arrives.
+ *
+ * The API functions that <b>may</b> consume an application packet depending on the parameters supplied to them can be found below:
+ * - @ref sd_ble_gattc_write (write without response only)
+ * - @ref sd_ble_gatts_hvx (notifications only)
+ * - @ref sd_ble_l2cap_tx (all packets)
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_count Pointer to a uint8_t which will contain the number of application transmission packets upon
+ *                     successful return.
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Number of application transmission packets retrieved successfully.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_TX_PACKET_COUNT_GET, uint32_t, sd_ble_tx_packet_count_get(uint16_t conn_handle, uint8_t *p_count));
+
+
+/**@brief Add a Vendor Specific UUID.
+ *
+ * @details This call enables the application to add a vendor specific UUID to the BLE stack's table, for later use
+ * all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t format
+ * when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code paths.
+ * The way that this is accomplished is by extending the grouping mechanism that the Bluetooth SIG standard base
+ * UUID uses for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to
+ * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the uuid field
+ * in the same structure contains the 2 bytes at indices 12 and 13. The number of possible 128-bit UUIDs available to
+ * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536,
+ * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array.
+ *
+ * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by
+ * the 16-bit uuid field in @ref ble_uuid_t.
+ *
+ * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in
+ * p_uuid_type along with an NRF_SUCCESS error code.
+ *
+ * @param[in]  p_vs_uuid    Pointer to a 16-octet (128-bit) little endian Vendor Specific UUID disregarding
+ *                          bytes 12 and 13.
+ * @param[out] p_uuid_type  Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added the Vendor Specific UUID.
+ * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid.
+ * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs.
+ */
+SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type));
+
+
+/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure.
+ *
+ * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared
+ * to the corresponding ones in each entry of the table of vendor specific UUIDs populated with @ref sd_ble_uuid_vs_add
+ * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index
+ * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type.
+ *
+ * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE.
+ *
+ * @param[in]   uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes).
+ * @param[in]   p_uuid_le   Pointer pointing to little endian raw UUID bytes.
+ * @param[out]  p_uuid      Pointer to a @ref ble_uuid_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length.
+ * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs.
+ */
+SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid));
+
+
+/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit).
+ *
+ * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed.
+ *
+ * @param[in]   p_uuid        Pointer to a @ref ble_uuid_t structure that will be encoded into bytes.
+ * @param[out]  p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes).
+ * @param[out]  p_uuid_le     Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully encoded into the buffer.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type.
+ */
+SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le));
+
+
+/**@brief Get Version Information.
+ *
+ * @details This call allows the application to get the BLE stack version information.
+ *
+ * @param[out] p_version Pointer to a ble_version_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS  Version information stored successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure).
+ */
+SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version));
+
+
+/**@brief Provide a user memory block.
+ *
+ * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application.
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in,out] p_block Pointer to a user memory block structure.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully queued a response to the peer.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no execute write request pending.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block));
+
+/**@brief Set a BLE option.
+ *
+ * @details This call allows the application to set the value of an option.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
+ * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value.
+ *
+ * @retval ::NRF_SUCCESS  Option set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
+ */
+SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt));
+
+
+/**@brief Get a BLE option.
+ *
+ * @details This call allows the application to retrieve the value of an option.
+ *
+ * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
+ * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS  Option retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported.
+ *
+ */
+SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt));
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_BLE_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h
new file mode 100644
index 0000000000..7eaf23d125
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_err.h
@@ -0,0 +1,93 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @addtogroup  nrf_error
+  @{
+    @ingroup BLE_COMMON
+  @}
+
+  @defgroup ble_err General error codes
+  @{
+
+  @brief General error code definitions for the BLE API.
+
+  @ingroup BLE_COMMON
+*/
+#ifndef NRF_BLE_ERR_H__
+#define NRF_BLE_ERR_H__
+
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* @defgroup BLE_ERRORS Error Codes
+ * @{ */
+#define BLE_ERROR_NOT_ENABLED            (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */
+#define BLE_ERROR_INVALID_CONN_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */
+#define BLE_ERROR_INVALID_ATTR_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */
+#define BLE_ERROR_NO_TX_PACKETS          (NRF_ERROR_STK_BASE_NUM+0x004) /**< Not enough application packets available on this connection. */
+#define BLE_ERROR_INVALID_ROLE           (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */
+/** @} */
+
+
+/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges
+ *  @brief Assignment of subranges for module specific error codes.
+ *  @note For specific error codes, see ble_<module>.h or ble_error_<module>.h.
+ * @{ */
+#define NRF_L2CAP_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */
+#define NRF_GAP_ERR_BASE               (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */
+#define NRF_GATTC_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */
+#define NRF_GATTS_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h
new file mode 100644
index 0000000000..926714ed36
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gap.h
@@ -0,0 +1,1745 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GAP Generic Access Profile (GAP)
+  @{
+  @brief Definitions and prototypes for the GAP interface.
+ */
+
+#ifndef NRF_BLE_GAP_H__
+#define NRF_BLE_GAP_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief GAP API SVC numbers.
+ */
+enum BLE_GAP_SVCS
+{
+  SD_BLE_GAP_ADDRESS_SET  = BLE_GAP_SVC_BASE,  /**< Set own Bluetooth Address. */
+  SD_BLE_GAP_ADDRESS_GET,                      /**< Get own Bluetooth Address. */
+  SD_BLE_GAP_ADV_DATA_SET,                     /**< Set Advertising Data. */
+  SD_BLE_GAP_ADV_START,                        /**< Start Advertising. */
+  SD_BLE_GAP_ADV_STOP,                         /**< Stop Advertising. */
+  SD_BLE_GAP_CONN_PARAM_UPDATE,                /**< Connection Parameter Update. */
+  SD_BLE_GAP_DISCONNECT,                       /**< Disconnect. */
+  SD_BLE_GAP_TX_POWER_SET,                     /**< Set TX Power. */
+  SD_BLE_GAP_APPEARANCE_SET,                   /**< Set Appearance. */
+  SD_BLE_GAP_APPEARANCE_GET,                   /**< Get Appearance. */
+  SD_BLE_GAP_PPCP_SET,                         /**< Set PPCP. */
+  SD_BLE_GAP_PPCP_GET,                         /**< Get PPCP. */
+  SD_BLE_GAP_DEVICE_NAME_SET,                  /**< Set Device Name. */
+  SD_BLE_GAP_DEVICE_NAME_GET,                  /**< Get Device Name. */
+  SD_BLE_GAP_AUTHENTICATE,                     /**< Initiate Pairing/Bonding. */
+  SD_BLE_GAP_SEC_PARAMS_REPLY,                 /**< Reply with Security Parameters. */
+  SD_BLE_GAP_AUTH_KEY_REPLY,                   /**< Reply with an authentication key. */
+  SD_BLE_GAP_LESC_DHKEY_REPLY,                 /**< Reply with an LE Secure Connections DHKey. */
+  SD_BLE_GAP_KEYPRESS_NOTIFY,                  /**< Notify of a keypress during an authentication procedure. */
+  SD_BLE_GAP_LESC_OOB_DATA_GET,                /**< Get the local LE Secure Connections OOB data. */
+  SD_BLE_GAP_LESC_OOB_DATA_SET,                /**< Set the remote LE Secure Connections OOB data. */
+  SD_BLE_GAP_ENCRYPT,                          /**< Initiate encryption procedure. */
+  SD_BLE_GAP_SEC_INFO_REPLY,                   /**< Reply with Security Information. */
+  SD_BLE_GAP_CONN_SEC_GET,                     /**< Obtain connection security level. */
+  SD_BLE_GAP_RSSI_START,                       /**< Start reporting of changes in RSSI. */
+  SD_BLE_GAP_RSSI_STOP,                        /**< Stop reporting of changes in RSSI. */
+  SD_BLE_GAP_SCAN_START,                       /**< Start Scanning. */
+  SD_BLE_GAP_SCAN_STOP,                        /**< Stop Scanning. */
+  SD_BLE_GAP_CONNECT,                          /**< Connect. */
+  SD_BLE_GAP_CONNECT_CANCEL,                   /**< Cancel ongoing connection procedure. */
+  SD_BLE_GAP_RSSI_GET,                         /**< Get the last RSSI sample. */
+};
+
+/**@brief GAP Event IDs.
+ * IDs that uniquely identify an event coming from the stack to the application.
+ */
+enum BLE_GAP_EVTS
+{
+  BLE_GAP_EVT_CONNECTED  = BLE_GAP_EVT_BASE,    /**< Connection established.                         \n See @ref ble_gap_evt_connected_t.            */
+  BLE_GAP_EVT_DISCONNECTED,                     /**< Disconnected from peer.                         \n See @ref ble_gap_evt_disconnected_t.         */
+  BLE_GAP_EVT_CONN_PARAM_UPDATE,                /**< Connection Parameters updated.                  \n See @ref ble_gap_evt_conn_param_update_t.    */
+  BLE_GAP_EVT_SEC_PARAMS_REQUEST,               /**< Request to provide security parameters.         \n Reply with @ref sd_ble_gap_sec_params_reply.  \n See @ref ble_gap_evt_sec_params_request_t. */
+  BLE_GAP_EVT_SEC_INFO_REQUEST,                 /**< Request to provide security information.        \n Reply with @ref sd_ble_gap_sec_info_reply.    \n See @ref ble_gap_evt_sec_info_request_t.   */
+  BLE_GAP_EVT_PASSKEY_DISPLAY,                  /**< Request to display a passkey to the user.       \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */
+  BLE_GAP_EVT_KEY_PRESSED,                      /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t           */
+  BLE_GAP_EVT_AUTH_KEY_REQUEST,                 /**< Request to provide an authentication key.       \n Reply with @ref sd_ble_gap_auth_key_reply.    \n See @ref ble_gap_evt_auth_key_request_t.   */
+  BLE_GAP_EVT_LESC_DHKEY_REQUEST,               /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply.  \n See @ref ble_gap_evt_lesc_dhkey_request_t */
+  BLE_GAP_EVT_AUTH_STATUS,                      /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t.          */
+  BLE_GAP_EVT_CONN_SEC_UPDATE,                  /**< Connection security updated.                    \n See @ref ble_gap_evt_conn_sec_update_t.      */
+  BLE_GAP_EVT_TIMEOUT,                          /**< Timeout expired.                                \n See @ref ble_gap_evt_timeout_t.              */
+  BLE_GAP_EVT_RSSI_CHANGED,                     /**< RSSI report.                                    \n See @ref ble_gap_evt_rssi_changed_t.         */
+  BLE_GAP_EVT_ADV_REPORT,                       /**< Advertising report.                             \n See @ref ble_gap_evt_adv_report_t.           */
+  BLE_GAP_EVT_SEC_REQUEST,                      /**< Security Request.                               \n See @ref ble_gap_evt_sec_request_t.          */
+  BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST,        /**< Connection Parameter Update Request.            \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */
+  BLE_GAP_EVT_SCAN_REQ_REPORT,                  /**< Scan request report.                            \n See @ref ble_gap_evt_scan_req_report_t.      */
+};
+
+/**@brief GAP Option IDs.
+ * IDs that uniquely identify a GAP option.
+ */
+enum BLE_GAP_OPTS
+{
+  BLE_GAP_OPT_CH_MAP  = BLE_GAP_OPT_BASE,       /**< Channel Map. @ref ble_gap_opt_ch_map_t  */
+  BLE_GAP_OPT_LOCAL_CONN_LATENCY,               /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */
+  BLE_GAP_OPT_PASSKEY,                          /**< Set passkey. @ref ble_gap_opt_passkey_t */
+  BLE_GAP_OPT_PRIVACY,                          /**< Custom privacy. @ref ble_gap_opt_privacy_t */
+  BLE_GAP_OPT_SCAN_REQ_REPORT,                  /**< Scan request report. @ref ble_gap_opt_scan_req_report_t */
+  BLE_GAP_OPT_COMPAT_MODE                       /**< Compatibility mode. @ref ble_gap_opt_compat_mode_t */
+};
+
+/** @} */
+
+/**@addtogroup BLE_GAP_DEFINES Defines
+ * @{ */
+
+/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP
+ * @{ */
+#define BLE_ERROR_GAP_UUID_LIST_MISMATCH            (NRF_GAP_ERR_BASE + 0x000)  /**< UUID list does not contain an integral number of UUIDs. */
+#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST   (NRF_GAP_ERR_BASE + 0x001)  /**< Use of Whitelist not permitted with discoverable advertising. */
+#define BLE_ERROR_GAP_INVALID_BLE_ADDR              (NRF_GAP_ERR_BASE + 0x002)  /**< The upper two bits of the address do not correspond to the specified address type. */
+#define BLE_ERROR_GAP_WHITELIST_IN_USE              (NRF_GAP_ERR_BASE + 0x003)  /**< Attempt to overwrite the whitelist while already in use by another operation. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ROLES GAP Roles
+ * @note Not explicitly used in peripheral API, but will be relevant for central API.
+ * @{ */
+#define BLE_GAP_ROLE_INVALID     0x0            /**< Invalid Role. */
+#define BLE_GAP_ROLE_PERIPH      0x1            /**< Peripheral Role. */
+#define BLE_GAP_ROLE_CENTRAL     0x2            /**< Central Role. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources
+ * @{ */
+#define BLE_GAP_TIMEOUT_SRC_ADVERTISING                0x00 /**< Advertising timeout. */
+#define BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST           0x01 /**< Security request timeout. */
+#define BLE_GAP_TIMEOUT_SRC_SCAN                       0x02 /**< Scanning timeout. */
+#define BLE_GAP_TIMEOUT_SRC_CONN                       0x03 /**< Connection timeout. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types
+ * @{ */
+#define BLE_GAP_ADDR_TYPE_PUBLIC                        0x00 /**< Public address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC                 0x01 /**< Random Static address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE     0x02 /**< Private Resolvable address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Private Non-Resolvable address. */
+/**@} */
+
+/**@defgroup BLE_GAP_ADDR_CYCLE_MODES GAP Address cycle modes
+ * @{ */
+#define BLE_GAP_ADDR_CYCLE_MODE_NONE      0x00 /**< Set addresses directly, no automatic address cycling. */
+#define BLE_GAP_ADDR_CYCLE_MODE_AUTO      0x01 /**< Automatically generate and update private addresses. */
+/** @} */
+
+/**@brief The default interval in seconds at which a private address is refreshed when address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO.  */
+#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (60 * 15)
+
+/** @brief BLE address length. */
+#define BLE_GAP_ADDR_LEN            6
+
+
+/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format
+ * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm
+ * @{ */
+#define BLE_GAP_AD_TYPE_FLAGS                               0x01 /**< Flags for discoverability. */
+#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE   0x02 /**< Partial list of 16 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE         0x03 /**< Complete list of 16 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE   0x04 /**< Partial list of 32 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE         0x05 /**< Complete list of 32 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE  0x06 /**< Partial list of 128 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE        0x07 /**< Complete list of 128 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME                    0x08 /**< Short local device name. */
+#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME                 0x09 /**< Complete local device name. */
+#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL                      0x0A /**< Transmit power level. */
+#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE                     0x0D /**< Class of device. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C               0x0E /**< Simple Pairing Hash C. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R         0x0F /**< Simple Pairing Randomizer R. */
+#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE           0x10 /**< Security Manager TK Value. */
+#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS          0x11 /**< Security Manager Out Of Band Flags. */
+#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE     0x12 /**< Slave Connection Interval Range. */
+#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT       0x14 /**< List of 16-bit Service Solicitation UUIDs. */
+#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT      0x15 /**< List of 128-bit Service Solicitation UUIDs. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA                        0x16 /**< Service Data - 16-bit UUID. */
+#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS               0x17 /**< Public Target Address. */
+#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS               0x18 /**< Random Target Address. */
+#define BLE_GAP_AD_TYPE_APPEARANCE                          0x19 /**< Appearance. */
+#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL                0x1A /**< Advertising Interval. */
+#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B /**< LE Bluetooth Device Address. */
+#define BLE_GAP_AD_TYPE_LE_ROLE                             0x1C /**< LE Role. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256            0x1D /**< Simple Pairing Hash C-256. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256      0x1E /**< Simple Pairing Randomizer R-256. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID             0x20 /**< Service Data - 32-bit UUID. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID            0x21 /**< Service Data - 128-bit UUID. */
+#define BLE_GAP_AD_TYPE_URI                                 0x24 /**< URI */
+#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA                 0x3D /**< 3D Information Data. */
+#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA          0xFF /**< Manufacturer Specific Data. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags
+ * @{ */
+#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE         (0x01)   /**< LE Limited Discoverable Mode. */
+#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE         (0x02)   /**< LE General Discoverable Mode. */
+#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED         (0x04)   /**< BR/EDR not supported. */
+#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER         (0x08)   /**< Simultaneous LE and BR/EDR, Controller. */
+#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST               (0x10)   /**< Simultaneous LE and BR/EDR, Host. */
+#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE Limited Discoverable Mode, BR/EDR not supported. */
+#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE General Discoverable Mode, BR/EDR not supported. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min
+ * @{ */
+#define BLE_GAP_ADV_INTERVAL_MIN        0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */
+#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */
+#define BLE_GAP_ADV_INTERVAL_MAX        0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */
+ /**@}  */
+
+
+/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min
+ * @{ */
+#define BLE_GAP_SCAN_INTERVAL_MIN       0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */
+#define BLE_GAP_SCAN_INTERVAL_MAX       0x4000 /**< Maximum Scan interval in 625 us units, i.e. 10.24 s. */
+ /** @}  */
+
+
+/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min
+ * @{ */
+#define BLE_GAP_SCAN_WINDOW_MIN         0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */
+#define BLE_GAP_SCAN_WINDOW_MAX         0x4000 /**< Maximum Scan window in 625 us units, i.e. 10.24 s. */
+ /** @}  */
+
+
+/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min
+ * @{ */
+#define BLE_GAP_SCAN_TIMEOUT_MIN        0x0001 /**< Minimum Scan timeout in seconds. */
+#define BLE_GAP_SCAN_TIMEOUT_MAX        0xFFFF /**< Maximum Scan timeout in seconds. */
+ /** @}  */
+
+
+/**@brief Maximum size of advertising data in octets. */
+#define  BLE_GAP_ADV_MAX_SIZE           31
+
+
+/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types
+ * @{ */
+#define BLE_GAP_ADV_TYPE_ADV_IND          0x00   /**< Connectable undirected. */
+#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND   0x01   /**< Connectable directed. */
+#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND     0x02   /**< Scannable undirected. */
+#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND  0x03   /**< Non connectable undirected. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies
+ * @{ */
+#define BLE_GAP_ADV_FP_ANY                0x00   /**< Allow scan requests and connect requests from any device. */
+#define BLE_GAP_ADV_FP_FILTER_SCANREQ     0x01   /**< Filter scan requests with whitelist. */
+#define BLE_GAP_ADV_FP_FILTER_CONNREQ     0x02   /**< Filter connect requests with whitelist. */
+#define BLE_GAP_ADV_FP_FILTER_BOTH        0x03   /**< Filter both scan and connect requests with whitelist. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values
+ * @{ */
+#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX      180 /**< Maximum advertising time in limited discoverable mode (TGAP(lim_adv_timeout) = 180s). */
+#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED  0 /**< Unlimited advertising in general discoverable mode. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes
+ * @{ */
+#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE  0x00   /**< Not discoverable discovery Mode. */
+#define BLE_GAP_DISC_MODE_LIMITED           0x01   /**< Limited Discovery Mode. */
+#define BLE_GAP_DISC_MODE_GENERAL           0x02   /**< General Discovery Mode. */
+/**@} */
+
+/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities
+ * @{ */
+#define BLE_GAP_IO_CAPS_DISPLAY_ONLY      0x00   /**< Display Only. */
+#define BLE_GAP_IO_CAPS_DISPLAY_YESNO     0x01   /**< Display and Yes/No entry. */
+#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY     0x02   /**< Keyboard Only. */
+#define BLE_GAP_IO_CAPS_NONE              0x03   /**< No I/O capabilities. */
+#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY  0x04   /**< Keyboard and Display. */
+/**@} */
+
+/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types
+ * @{ */
+#define BLE_GAP_AUTH_KEY_TYPE_NONE        0x00   /**< No key (may be used to reject). */
+#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY     0x01   /**< 6-digit Passkey. */
+#define BLE_GAP_AUTH_KEY_TYPE_OOB         0x02   /**< Out Of Band data. */
+/**@} */
+
+/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types
+ * @{ */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START       0x00   /**< Passkey entry started. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN    0x01   /**< Passkey digit entered. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT   0x02   /**< Passkey digit erased. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR       0x03   /**< Passkey cleared. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END         0x04   /**< Passkey entry completed. */
+/**@} */
+
+/**@defgroup BLE_GAP_SEC_STATUS GAP Security status
+ * @{ */
+#define BLE_GAP_SEC_STATUS_SUCCESS                0x00  /**< Procedure completed with success. */
+#define BLE_GAP_SEC_STATUS_TIMEOUT                0x01  /**< Procedure timed out. */
+#define BLE_GAP_SEC_STATUS_PDU_INVALID            0x02  /**< Invalid PDU received. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN       0x03  /**< Reserved for Future Use range #1 begin. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END         0x80  /**< Reserved for Future Use range #1 end. */
+#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED   0x81  /**< Passkey entry failed (user cancelled or other). */
+#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE      0x82  /**< Out of Band Key not available. */
+#define BLE_GAP_SEC_STATUS_AUTH_REQ               0x83  /**< Authentication requirements not met. */
+#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE          0x84  /**< Confirm value failed. */
+#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP       0x85  /**< Pairing not supported.  */
+#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE           0x86  /**< Encryption key size. */
+#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED    0x87  /**< Unsupported SMP command. */
+#define BLE_GAP_SEC_STATUS_UNSPECIFIED            0x88  /**< Unspecified reason. */
+#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS      0x89  /**< Too little time elapsed since last attempt. */
+#define BLE_GAP_SEC_STATUS_INVALID_PARAMS         0x8A  /**< Invalid parameters. */
+#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE          0x8B  /**< DHKey check failure. */
+#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE       0x8C  /**< Numeric Comparison failure. */
+#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG         0x8D  /**< BR/EDR pairing in progress. */
+#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E  /**< BR/EDR Link Key cannot be used for LE keys. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN       0x8F  /**< Reserved for Future Use range #2 begin. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END         0xFF  /**< Reserved for Future Use range #2 end. */
+/**@} */
+
+/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources
+ * @{ */
+#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL           0x00  /**< Local failure. */
+#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE          0x01  /**< Remote failure. */
+/**@} */
+
+/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits
+ * @{ */
+#define BLE_GAP_CP_MIN_CONN_INTVL_NONE           0xFFFF  /**< No new minimum connection interval specified in connect parameters. */
+#define BLE_GAP_CP_MIN_CONN_INTVL_MIN            0x0006  /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
+#define BLE_GAP_CP_MIN_CONN_INTVL_MAX            0x0C80  /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_NONE           0xFFFF  /**< No new maximum connection interval specified in connect parameters. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_MIN            0x0006  /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_MAX            0x0C80  /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
+#define BLE_GAP_CP_SLAVE_LATENCY_MAX             0x01F3  /**< Highest slave latency permitted, in connection events. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE         0xFFFF  /**< No new supervision timeout specified in connect parameters. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN          0x000A  /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX          0x0C80  /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */
+/**@} */
+
+
+/**@brief GAP device name maximum length. */
+#define BLE_GAP_DEVNAME_MAX_LEN           31
+
+/**@brief Disable RSSI events for connections */
+#define BLE_GAP_RSSI_THRESHOLD_INVALID    0xFF
+
+/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters
+ *
+ * See @ref ble_gap_conn_sec_mode_t.
+ * @{ */
+/**@brief Set sec_mode pointed to by ptr to have no access rights.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr)          do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr)               do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr)        do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr)      do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr)     do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr)   do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0)
+/**@} */
+
+
+/**@brief GAP Security Random Number Length. */
+#define BLE_GAP_SEC_RAND_LEN 8
+
+/**@brief GAP Security Key Length. */
+#define BLE_GAP_SEC_KEY_LEN 16
+
+/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */
+#define BLE_GAP_LESC_P256_PK_LEN 64
+
+/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */
+#define BLE_GAP_LESC_DHKEY_LEN   32
+
+/**@brief GAP Passkey Length. */
+#define BLE_GAP_PASSKEY_LEN 6
+
+/**@brief Maximum amount of addresses in a whitelist. */
+#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8)
+
+/**@brief Maximum amount of IRKs in a whitelist.
+ * @note  The number of IRKs is limited to 8, even if the hardware supports more.
+ */
+#define BLE_GAP_WHITELIST_IRK_MAX_COUNT (8)
+
+/**@defgroup GAP_SEC_MODES GAP Security Modes
+ * @{ */
+#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */
+/**@} */
+/** @} */
+
+/**@addtogroup BLE_GAP_STRUCTURES Structures
+ * @{ */
+
+/**
+ * @brief BLE GAP initialization parameters.
+ */
+typedef struct
+{
+  uint8_t                   periph_conn_count;  /**< Number of connections acting as a peripheral  */
+  uint8_t                   central_conn_count; /**< Number of connections acting as a central */
+  uint8_t                   central_sec_count;  /**< Number of SMP instances for all connections acting as a central. */
+} ble_gap_enable_params_t;
+
+/**@brief Bluetooth Low Energy address. */
+typedef struct
+{
+  uint8_t addr_type;                    /**< See @ref BLE_GAP_ADDR_TYPES. */
+  uint8_t addr[BLE_GAP_ADDR_LEN];       /**< 48-bit address, LSB format. */
+} ble_gap_addr_t;
+
+
+/**@brief GAP connection parameters.
+ *
+ * @note  When ble_conn_params_t is received in an event, both min_conn_interval and
+ *        max_conn_interval will be equal to the connection interval set by the central.
+ *
+ * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies:
+ *       conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval
+ *       that corresponds to the following Bluetooth Spec requirement:
+ *       The Supervision_Timeout in milliseconds shall be larger than
+ *       (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds.
+ */
+typedef struct
+{
+  uint16_t min_conn_interval;         /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t max_conn_interval;         /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t slave_latency;             /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t conn_sup_timeout;          /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+} ble_gap_conn_params_t;
+
+
+/**@brief GAP connection security modes.
+ *
+ * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n
+ * Security Mode 1 Level 1: No security is needed (aka open link).\n
+ * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n
+ * Security Mode 1 Level 3: MITM protected encrypted link required.\n
+ * Security Mode 1 Level 4: LESC MITM protected encrypted link required.\n
+ * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n
+ * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n
+ */
+typedef struct
+{
+  uint8_t sm : 4;                     /**< Security Mode (1 or 2), 0 for no permissions at all. */
+  uint8_t lv : 4;                     /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */
+
+} ble_gap_conn_sec_mode_t;
+
+
+/**@brief GAP connection security status.*/
+typedef struct
+{
+  ble_gap_conn_sec_mode_t sec_mode;           /**< Currently active security mode for this connection.*/
+  uint8_t                 encr_key_size;      /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */
+} ble_gap_conn_sec_t;
+
+
+/**@brief Identity Resolving Key. */
+typedef struct
+{
+  uint8_t irk[BLE_GAP_SEC_KEY_LEN];   /**< Array containing IRK. */
+} ble_gap_irk_t;
+
+
+/**@brief Whitelist structure. */
+typedef struct
+{
+  ble_gap_addr_t    **pp_addrs;        /**< Pointer to an array of device address pointers, pointing to addresses to be used in whitelist. NULL if none are given. */
+  uint8_t             addr_count;      /**< Count of device addresses in array, up to @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. */
+  ble_gap_irk_t     **pp_irks;         /**< Pointer to an array of Identity Resolving Key (IRK) pointers, each pointing to an IRK in the whitelist. NULL if none are given. */
+  uint8_t             irk_count;       /**< Count of IRKs in array, up to @ref BLE_GAP_WHITELIST_IRK_MAX_COUNT. */
+} ble_gap_whitelist_t;
+
+/**@brief Channel mask for RF channels used in advertising. */
+typedef struct
+{
+  uint8_t ch_37_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 37 */
+  uint8_t ch_38_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 38 */
+  uint8_t ch_39_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 39 */
+} ble_gap_adv_ch_mask_t;
+
+/**@brief GAP advertising parameters.*/
+typedef struct
+{
+  uint8_t               type;                 /**< See @ref BLE_GAP_ADV_TYPES. */
+  ble_gap_addr_t       *p_peer_addr;          /**< For @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND mode only, known peer address. */
+  uint8_t               fp;                   /**< Filter Policy, see @ref BLE_GAP_ADV_FILTER_POLICIES. */
+  ble_gap_whitelist_t  *p_whitelist;          /**< Pointer to whitelist, NULL if no whitelist or the current active whitelist is to be used. */
+  uint16_t              interval;             /**< Advertising interval between 0x0020 and 0x4000 in 0.625 ms units (20ms to 10.24s), see @ref BLE_GAP_ADV_INTERVALS.
+                                                   - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for high duty cycle directed advertising.
+                                                   - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, set @ref BLE_GAP_ADV_INTERVAL_MIN <= interval <= @ref BLE_GAP_ADV_INTERVAL_MAX for low duty cycle advertising.*/
+  uint16_t              timeout;              /**< Advertising timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. See also @ref BLE_GAP_ADV_TIMEOUT_VALUES. If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for High duty cycle directed advertising. */
+  ble_gap_adv_ch_mask_t channel_mask;         /**< Advertising channel mask. See @ref ble_gap_adv_ch_mask_t. */
+} ble_gap_adv_params_t;
+
+
+/**@brief GAP scanning parameters. */
+typedef struct
+{
+  uint8_t                 active    : 1;        /**< If 1, perform active scanning (scan requests). */
+  uint8_t                 selective : 1;        /**< If 1, ignore unknown devices (non whitelisted). */
+  ble_gap_whitelist_t *   p_whitelist;          /**< Pointer to whitelist, NULL if no whitelist or the current active whitelist is to be used. */
+  uint16_t                interval;             /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+  uint16_t                window;               /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+  uint16_t                timeout;              /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
+} ble_gap_scan_params_t;
+
+
+/** @brief Keys that can be exchanged during a bonding procedure. */
+typedef struct
+{
+  uint8_t enc     : 1;                        /**< Long Term Key and Master Identification. */
+  uint8_t id      : 1;                        /**< Identity Resolving Key and Identity Address Information. */
+  uint8_t sign    : 1;                        /**< Connection Signature Resolving Key. */
+  uint8_t link    : 1;                        /**< Derive the Link Key from the LTK. */
+} ble_gap_sec_kdist_t;
+
+
+/**@brief GAP security parameters. */
+typedef struct
+{
+  uint8_t               bond      : 1;             /**< Perform bonding. */
+  uint8_t               mitm      : 1;             /**< Enable Man In The Middle protection. */
+  uint8_t               lesc      : 1;             /**< Enable LE Secure Connection pairing. */
+  uint8_t               keypress  : 1;             /**< Enable generation of keypress notifications. */
+  uint8_t               io_caps   : 3;             /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */
+  uint8_t               oob       : 1;             /**< Out Of Band data available. */
+  uint8_t               min_key_size;              /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */
+  uint8_t               max_key_size;              /**< Maximum encryption key size in octets between min_key_size and 16. */
+  ble_gap_sec_kdist_t   kdist_own;                 /**< Key distribution bitmap: keys that the local device will distribute. */
+  ble_gap_sec_kdist_t   kdist_peer;                /**< Key distribution bitmap: keys that the remote device will distribute. */
+} ble_gap_sec_params_t;
+
+
+/**@brief GAP Encryption Information. */
+typedef struct
+{
+  uint8_t   ltk[BLE_GAP_SEC_KEY_LEN];   /**< Long Term Key. */
+  uint8_t   lesc : 1;                   /**< Key generated using LE Secure Connections. */
+  uint8_t   auth : 1;                   /**< Authenticated Key. */
+  uint8_t   ltk_len : 6;                /**< LTK length in octets. */
+} ble_gap_enc_info_t;
+
+
+/**@brief GAP Master Identification. */
+typedef struct
+{
+  uint16_t  ediv;                       /**< Encrypted Diversifier. */
+  uint8_t   rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */
+} ble_gap_master_id_t;
+
+
+/**@brief GAP Signing Information. */
+typedef struct
+{
+  uint8_t   csrk[BLE_GAP_SEC_KEY_LEN];        /**< Connection Signature Resolving Key. */
+} ble_gap_sign_info_t;
+
+/**@brief GAP LE Secure Connections P-256 Public Key. */
+typedef struct
+{
+  uint8_t   pk[BLE_GAP_LESC_P256_PK_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */
+} ble_gap_lesc_p256_pk_t;
+
+/**@brief GAP LE Secure Connections DHKey. */
+typedef struct
+{
+  uint8_t   key[BLE_GAP_LESC_DHKEY_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */
+} ble_gap_lesc_dhkey_t;
+
+/**@brief GAP LE Secure Connections OOB data. */
+typedef struct
+{
+  ble_gap_addr_t  addr;                          /**< Bluetooth address of the device. */
+  uint8_t         r[BLE_GAP_SEC_KEY_LEN];        /**< Random Number. */
+  uint8_t         c[BLE_GAP_SEC_KEY_LEN];        /**< Confirm Value. */
+} ble_gap_lesc_oob_data_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */
+typedef struct
+{
+  ble_gap_addr_t        peer_addr;              /**< Bluetooth address of the peer device. */
+  ble_gap_addr_t        own_addr;               /**< Bluetooth address of the local device used during connection setup. */
+  uint8_t               role;                   /**< BLE role for this connection, see @ref BLE_GAP_ROLES */
+  uint8_t               irk_match :1;           /**< If 1, peer device's address resolved using an IRK. */
+  uint8_t               irk_match_idx  :7;      /**< Index in IRK list where the address was matched. */
+  ble_gap_conn_params_t conn_params;            /**< GAP Connection Parameters. */
+} ble_gap_evt_connected_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */
+typedef struct
+{
+  uint8_t reason;                               /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */
+} ble_gap_evt_disconnected_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */
+typedef struct
+{
+  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
+} ble_gap_evt_conn_param_update_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */
+typedef struct
+{
+  ble_gap_sec_params_t peer_params;             /**< Initiator Security Parameters. */
+} ble_gap_evt_sec_params_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */
+typedef struct
+{
+  ble_gap_addr_t      peer_addr;                     /**< Bluetooth address of the peer device. */
+  ble_gap_master_id_t master_id;                     /**< Master Identification for LTK lookup. */
+  uint8_t             enc_info  : 1;                 /**< If 1, Encryption Information required. */
+  uint8_t             id_info   : 1;                 /**< If 1, Identity Information required. */
+  uint8_t             sign_info : 1;                 /**< If 1, Signing Information required. */
+} ble_gap_evt_sec_info_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */
+typedef struct
+{
+  uint8_t passkey[BLE_GAP_PASSKEY_LEN];         /**< 6-digit passkey in ASCII ('0'-'9' digits only). */
+  uint8_t match_request : 1;                    /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply
+                                                     with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or
+                                                     @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */
+} ble_gap_evt_passkey_display_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */
+typedef struct
+{
+  uint8_t kp_not;         /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */
+} ble_gap_evt_key_pressed_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */
+typedef struct
+{
+  uint8_t key_type;                             /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */
+} ble_gap_evt_auth_key_request_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */
+typedef struct
+{
+  ble_gap_lesc_p256_pk_t *p_pk_peer;  /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory
+                                           inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */
+  uint8_t oobd_req       :1;          /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */
+} ble_gap_evt_lesc_dhkey_request_t;
+
+
+/**@brief Security levels supported.
+ * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1.
+*/
+typedef struct
+{
+  uint8_t lv1 : 1;                              /**< If 1: Level 1 is supported. */
+  uint8_t lv2 : 1;                              /**< If 1: Level 2 is supported. */
+  uint8_t lv3 : 1;                              /**< If 1: Level 3 is supported. */
+  uint8_t lv4 : 1;                              /**< If 1: Level 4 is supported. */
+} ble_gap_sec_levels_t;
+
+
+/**@brief Encryption Key. */
+typedef struct
+{
+  ble_gap_enc_info_t    enc_info;             /**< Encryption Information. */
+  ble_gap_master_id_t   master_id;            /**< Master Identification. */
+} ble_gap_enc_key_t;
+
+
+/**@brief Identity Key. */
+typedef struct
+{
+  ble_gap_irk_t         id_info;              /**< Identity Information. */
+  ble_gap_addr_t        id_addr_info;         /**< Identity Address Information. */
+} ble_gap_id_key_t;
+
+
+/**@brief Security Keys. */
+typedef struct
+{
+  ble_gap_enc_key_t      *p_enc_key;           /**< Encryption Key, or NULL. */
+  ble_gap_id_key_t       *p_id_key;            /**< Identity Key, or NULL. */
+  ble_gap_sign_info_t    *p_sign_key;          /**< Signing Key, or NULL. */
+  ble_gap_lesc_p256_pk_t *p_pk;                /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined
+                                                    in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */
+} ble_gap_sec_keys_t;
+
+
+/**@brief Security key set for both local and peer keys. */
+typedef struct
+{
+  ble_gap_sec_keys_t            keys_own;     /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */
+  ble_gap_sec_keys_t            keys_peer;    /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */
+} ble_gap_sec_keyset_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */
+typedef struct
+{
+  uint8_t               auth_status;            /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */
+  uint8_t               error_src : 2;          /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+  uint8_t               bonded : 1;             /**< Procedure resulted in a bond. */
+  ble_gap_sec_levels_t  sm1_levels;             /**< Levels supported in Security Mode 1. */
+  ble_gap_sec_levels_t  sm2_levels;             /**< Levels supported in Security Mode 2. */
+  ble_gap_sec_kdist_t   kdist_own;              /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */
+  ble_gap_sec_kdist_t   kdist_peer;             /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */
+} ble_gap_evt_auth_status_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */
+typedef struct
+{
+  ble_gap_conn_sec_t conn_sec;                  /**< Connection security level. */
+} ble_gap_evt_conn_sec_update_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t src;                                  /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */
+} ble_gap_evt_timeout_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */
+typedef struct
+{
+  int8_t  rssi;                               /**< Received Signal Strength Indication in dBm. */
+} ble_gap_evt_rssi_changed_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. */
+typedef struct
+{
+  ble_gap_addr_t peer_addr;                     /**< Bluetooth address of the peer device. */
+  int8_t         rssi;                          /**< Received Signal Strength Indication in dBm. */
+  uint8_t        scan_rsp : 1;                  /**< If 1, the report corresponds to a scan response and the type field may be ignored. */
+  uint8_t        type     : 2;                  /**< See @ref BLE_GAP_ADV_TYPES. Only valid if the scan_rsp field is 0. */
+  uint8_t        dlen     : 5;                  /**< Advertising or scan response data length. */
+  uint8_t        data[BLE_GAP_ADV_MAX_SIZE];    /**< Advertising or scan response data. */
+} ble_gap_evt_adv_report_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */
+typedef struct
+{
+  uint8_t    bond       : 1;                       /**< Perform bonding. */
+  uint8_t    mitm       : 1;                       /**< Man In The Middle protection requested. */
+  uint8_t    lesc       : 1;                       /**< LE Secure Connections requested. */
+  uint8_t    keypress   : 1;                       /**< Generation of keypress notifications requested. */
+} ble_gap_evt_sec_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */
+typedef struct
+{
+  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
+} ble_gap_evt_conn_param_update_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */
+typedef struct
+{
+  int8_t                  rssi;              /**< Received Signal Strength Indication in dBm. */
+  ble_gap_addr_t          peer_addr;         /**< Bluetooth address of the peer device. */
+} ble_gap_evt_scan_req_report_t;
+
+
+
+/**@brief GAP event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                                     /**< Connection Handle on which event occurred. */
+  union                                                     /**< union alternative identified by evt_id in enclosing struct. */
+  {
+    ble_gap_evt_connected_t                   connected;                    /**< Connected Event Parameters. */
+    ble_gap_evt_disconnected_t                disconnected;                 /**< Disconnected Event Parameters. */
+    ble_gap_evt_conn_param_update_t           conn_param_update;            /**< Connection Parameter Update Parameters. */
+    ble_gap_evt_sec_params_request_t          sec_params_request;           /**< Security Parameters Request Event Parameters. */
+    ble_gap_evt_sec_info_request_t            sec_info_request;             /**< Security Information Request Event Parameters. */
+    ble_gap_evt_passkey_display_t             passkey_display;              /**< Passkey Display Event Parameters. */
+    ble_gap_evt_key_pressed_t                 key_pressed;                  /**< Key Pressed Event Parameters. */
+    ble_gap_evt_auth_key_request_t            auth_key_request;             /**< Authentication Key Request Event Parameters. */
+    ble_gap_evt_lesc_dhkey_request_t          lesc_dhkey_request;           /**< LE Secure Connections DHKey calculation request. */
+    ble_gap_evt_auth_status_t                 auth_status;                  /**< Authentication Status Event Parameters. */
+    ble_gap_evt_conn_sec_update_t             conn_sec_update;              /**< Connection Security Update Event Parameters. */
+    ble_gap_evt_timeout_t                     timeout;                      /**< Timeout Event Parameters. */
+    ble_gap_evt_rssi_changed_t                rssi_changed;                 /**< RSSI Event parameters. */
+    ble_gap_evt_adv_report_t                  adv_report;                   /**< Advertising Report Event Parameters. */
+    ble_gap_evt_sec_request_t                 sec_request;                  /**< Security Request Event Parameters. */
+    ble_gap_evt_conn_param_update_request_t   conn_param_update_request;    /**< Connection Parameter Update Parameters. */
+    ble_gap_evt_scan_req_report_t             scan_req_report;              /**< Scan Request Report parameters. */
+  } params;                                                                 /**< Event Parameters. */
+
+} ble_gap_evt_t;
+
+
+/**@brief Channel Map option.
+ *        Used with @ref sd_ble_opt_get to get the current channel map
+ *        or @ref sd_ble_opt_set to set a new channel map. When setting the
+ *        channel map, it applies to all current and future connections. When getting the
+ *        current channel map, it applies to a single connection and the connection handle
+ *        must be supplied.
+ *
+ * @note  Setting the channel map may take some time, depending on connection parameters.
+ *        The time taken may be different for each connection and the get operation will
+ *        return the previous channel map until the new one has taken effect.
+ *
+ * @note  After setting the channel map, by spec it can not be set again until at least 1 s has passed.
+ *        See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46.
+ *
+ * @retval ::NRF_SUCCESS Get or set successful.
+ * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Returned by sd_ble_opt_set in peripheral-only SoftDevices.
+ *
+ */
+typedef struct
+{
+  uint16_t conn_handle;                   /**< Connection Handle (only applicable for get) */
+  uint8_t ch_map[5];                      /**< Channel Map (37-bit). */
+} ble_gap_opt_ch_map_t;
+
+
+/**@brief Local connection latency option.
+ *
+ *        Local connection latency is a feature which enables the slave to improve
+ *        current consumption by ignoring the slave latency set by the peer. The
+ *        local connection latency can only be set to a multiple of the slave latency,
+ *        and cannot be longer than half of the supervision timeout.
+ *
+ *        Used with @ref sd_ble_opt_set to set the local connection latency. The
+ *        @ref sd_ble_opt_get is not supported for this option, but the actual
+ *        local connection latency (unless set to NULL) is set as a return parameter
+ *        when setting the option.
+ *
+ * @note  The latency set will be truncated down to the closest slave latency event
+ *        multiple, or the nearest multiple before half of the supervision timeout.
+ *
+ * @note  The local connection latency is disabled by default, and needs to be enabled for new
+ *        connections and whenever the connection is updated.
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
+ */
+typedef struct
+{
+  uint16_t   conn_handle;                       /**< Connection Handle */
+  uint16_t   requested_latency;                 /**< Requested local connection latency. */
+  uint16_t * p_actual_latency;                  /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */
+} ble_gap_opt_local_conn_latency_t;
+
+
+/**@brief Passkey Option.
+ *
+ *        Structure containing the passkey to be used during pairing. This can be used with @ref
+ *        sd_ble_opt_set to make the SoftDevice use a pre-programmed passkey for authentication
+ *        instead of generating a random one.
+ *
+ * @note  @ref sd_ble_opt_get is not supported for this option.
+ *
+ */
+typedef struct
+{
+  uint8_t * p_passkey;                          /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/
+} ble_gap_opt_passkey_t;
+
+
+/**@brief Custom Privacy Option.
+ *
+ *        This structure is used with both @ref sd_ble_opt_set (as input) and with
+ *        @ref sd_ble_opt_get (as output).
+ *
+ *        Structure containing:
+ *        - A pointer to an IRK to set (if input), or a place to store a read IRK (if output).
+ *        - A private address refresh cycle.
+ *
+ * @note  The specified address cycle interval is used when the address cycle mode is
+ *        @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO. If 0 is given, the address will not be automatically
+ *        refreshed at all. The default interval is @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S.
+ *
+ * @note  If the current address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address will immediately be
+ *        refreshed when a custom privacy option is set. A new address can be generated manually by calling
+ *        @ref sd_ble_gap_address_set with the same type again.
+ *
+ * @note  If the IRK is updated, the new IRK becomes the one to be distributed in all
+ *        bonding procedures performed after @ref sd_ble_opt_set returns.
+ *
+ * @retval ::NRF_SUCCESS Set or read successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR The pointer to IRK storage is invalid.
+ */
+typedef struct
+{
+  ble_gap_irk_t * p_irk;        /**< When input: Pointer to custom IRK, or NULL to use/reset to the device's default IRK. When output: Pointer to where the current IRK is to be stored, or NULL to not read out the IRK. */
+  uint16_t        interval_s;   /**< When input: Custom private address cycle interval in seconds. When output: The current private address cycle interval. */
+} ble_gap_opt_privacy_t;
+
+
+/**@brief Scan request report option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to make the SoftDevice send
+ *        @ref BLE_GAP_EVT_SCAN_REQ_REPORT events.
+ *
+ *  @note   Due to the limited space reserved for scan request report events,
+ *          not all received scan requests will be reported.
+ *
+ *  @note   If whitelisting is used, only whitelisted requests are reported.
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_STATE When advertising is ongoing while the option is set.
+ */
+typedef struct
+{
+   uint8_t enable : 1;                           /**< Enable scan request reports. */
+} ble_gap_opt_scan_req_report_t;
+
+/**@brief Compatibility mode option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to enable and disable
+ *        compatibility modes. Compatibility modes are disabled by default.
+ *
+ *  @note  Compatibility mode 1 enables interoperability with devices that do not support
+ *         a value of 0 for the WinOffset parameter in the Link Layer CONNECT_REQ packet.
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set.
+ */
+typedef struct
+{
+   uint8_t mode_1_enable : 1;                           /**< Enable compatibility mode 1.*/
+} ble_gap_opt_compat_mode_t;
+
+/**@brief Option structure for GAP options. */
+typedef union
+{
+  ble_gap_opt_ch_map_t                  ch_map;                    /**< Parameters for the Channel Map option. */
+  ble_gap_opt_local_conn_latency_t      local_conn_latency;        /**< Parameters for the Local connection latency option */
+  ble_gap_opt_passkey_t                 passkey;                   /**< Parameters for the Passkey option.*/
+  ble_gap_opt_privacy_t                 privacy;                   /**< Parameters for the Custom privacy option. */
+  ble_gap_opt_scan_req_report_t         scan_req_report;           /**< Parameters for the scan request report option.*/
+  ble_gap_opt_compat_mode_t             compat_mode;               /**< Parameters for the compatibility mode option.*/
+} ble_gap_opt_t;
+/**@} */
+
+
+/**@addtogroup BLE_GAP_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Set local Bluetooth address.
+ *
+ * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address type is required to
+ * be @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or
+ * @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. The given address is ignored and the
+ * SoftDevice will generate a new private address automatically every
+ * @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S seconds. If this API
+ * call is used again with the same parameters, the SoftDevice will immediately
+ * generate a new private address to replace the current address.
+ *
+ * @note If the application wishes to use a @ref BLE_GAP_ADDR_TYPE_PUBLIC or
+ * @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC address, the cycle mode must be
+ * @ref BLE_GAP_ADDR_CYCLE_MODE_NONE.
+ *
+ * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being
+ * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged
+ * for the lifetime of each IC.
+ *
+ * @note If this API function is called while advertising or scanning, the softdevice will immediately update the
+ * advertising or scanning address without the need to stop the procedure in the following cases:
+ *   - If the previously set address is of type @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address
+ *   is also of type @ref BLE_GAP_ADDR_TYPE_PUBLIC
+ *   - If the previously set address is not @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address is
+ *   also not @ref BLE_GAP_ADDR_TYPE_PUBLIC.
+ * If the address is changed from a @ref BLE_GAP_ADDR_TYPE_PUBLIC address to another type or from
+ * another type to a @ref BLE_GAP_ADDR_TYPE_PUBLIC address, the change will take effect the next
+ * time an advertising or scanning procedure is started.
+ *
+ * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_NONE and the application is
+ *       using privacy, the application must take care to generate and set new private addresses
+ *       periodically to comply with the Privacy specification in Bluetooth Core Spec.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @endmscs
+ *
+ * @param[in] addr_cycle_mode Address cycle mode, see @ref BLE_GAP_ADDR_CYCLE_MODES.
+ * @param[in] p_addr          Pointer to address structure.
+ *
+ * @retval ::NRF_SUCCESS Address successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ */
+SVCALL(SD_BLE_GAP_ADDRESS_SET, uint32_t, sd_ble_gap_address_set(uint8_t addr_cycle_mode, ble_gap_addr_t const *p_addr));
+
+
+/**@brief Get local Bluetooth address.
+ *
+ * @param[out] p_addr Pointer to address structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Address successfully retrieved.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_ADDRESS_GET, uint32_t, sd_ble_gap_address_get(ble_gap_addr_t *p_addr));
+
+
+/**@brief Set, clear or update advertising and scan response data.
+ *
+ * @note The format of the advertising data will be checked by this call to ensure interoperability.
+ *       Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and
+ *       duplicating the local name in the advertising data and scan response data.
+ *
+ * @note To clear the advertising data and set it to a 0-length packet, simply provide a valid pointer (p_data/p_sr_data) with its corresponding
+ *        length (dlen/srdlen) set to 0.
+ *
+ * @note The call will fail if p_data and p_sr_data are both NULL since this would have no effect.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_data    Raw data to be placed in advertising packet. If NULL, no changes are made to the current advertising packet data.
+ * @param[in] dlen      Data length for p_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_data is NULL, can be 0 if p_data is not NULL.
+ * @param[in] p_sr_data Raw data to be placed in scan response packet. If NULL, no changes are made to the current scan response packet data.
+ * @param[in] srdlen    Data length for p_sr_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_sr_data is NULL, can be 0 if p_data is not NULL.
+ *
+ * @retval ::NRF_SUCCESS Advertising data successfully updated or cleared.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, both p_data and p_sr_data cannot be NULL.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied.
+ * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied, check the advertising data format specification.
+ * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data type.
+ * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied.
+ */
+SVCALL(SD_BLE_GAP_ADV_DATA_SET, uint32_t, sd_ble_gap_adv_data_set(uint8_t const *p_data, uint8_t dlen, uint8_t const *p_sr_data, uint8_t srdlen));
+
+
+/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
+ *
+ * @note An application can start an advertising procedure for broadcasting purposes while a connection
+ *       is active. After a @ref BLE_GAP_EVT_CONNECTED event is received, this function may therefore
+ *       be called to start a broadcast advertising procedure. The advertising procedure
+ *       cannot however be connectable (it must be of type @ref BLE_GAP_ADV_TYPE_ADV_SCAN_IND or
+ *       @ref BLE_GAP_ADV_TYPE_ADV_NONCONN_IND). @note Only one advertiser may be active at any time.
+ *
+ * @note To use the currently active whitelist set p_adv_params->p_whitelist to NULL.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT, Advertisement has timed out.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_adv_params Pointer to advertising parameters structure.
+ *
+ * @retval ::NRF_SUCCESS The BLE stack has started advertising.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started.
+ * @retval ::NRF_ERROR_NO_MEM The configured memory pools (see @ref ble_conn_bw_counts_t) are not large enough for the
+ *                            bandwidth selected for this connection.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check the accepted ranges and limits.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Bluetooth address supplied.
+ * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Observer) and try again
+ */
+SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(ble_gap_adv_params_t const *p_adv_params));
+
+
+/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS The BLE stack has stopped advertising.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in advertising state).
+ */
+SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(void));
+
+
+/**@brief Update connection parameters.
+ *
+ * @details In the central role this will initiate a Link Layer connection parameter update procedure,
+ *          otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for
+ *          the central to perform the procedure. In both cases, and regardless of success or failure, the application
+ *          will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event.
+ *
+ * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CPU_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_conn_params  Pointer to desired connection parameters. If NULL is provided on a peripheral role,
+ *                           the parameters in the PPCP characteristic of the GAP service will be used instead.
+ *                           If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected
+ *
+ * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, process pending events and wait for pending procedures to complete and retry.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Disconnect (GAP Link Termination).
+ *
+ * @details This call initiates the disconnection procedure, and its completion will be communicated to the application
+ *          with a @ref BLE_GAP_EVT_DISCONNECTED event.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CONN_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE).
+ *
+ * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (disconnection is already in progress).
+ */
+SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code));
+
+
+/**@brief Set the radio's transmit power.
+ *
+ * @param[in] tx_power Radio transmit power in dBm (accepted values are -40, -30, -20, -16, -12, -8, -4, 0, and 4 dBm).
+ *
+ * @note The -30dBm setting is only available on nRF51 series ICs.
+ * @note The -40dBm setting is only available on nRF52 series ICs.
+ *
+ * @retval ::NRF_SUCCESS Successfully changed the transmit power.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(int8_t tx_power));
+
+
+/**@brief Set GAP Appearance value.
+ *
+ * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES.
+ *
+ * @retval ::NRF_SUCCESS  Appearance value set successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance));
+
+
+/**@brief Get GAP Appearance value.
+ *
+ * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES.
+ *
+ * @retval ::NRF_SUCCESS Appearance value retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance));
+
+
+/**@brief Set GAP Peripheral Preferred Connection Parameters.
+ *
+ * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters.
+ *
+ * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Get GAP Peripheral Preferred Connection Parameters.
+ *
+ * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored.
+ *
+ * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params));
+
+
+/**@brief Set GAP device name.
+ *
+ * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t.
+ * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string.
+ * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN).
+ *
+ * @retval ::NRF_SUCCESS GAP device name and permissions set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len));
+
+
+/**@brief Get GAP device name.
+ *
+ * @note          If the device name is longer than the size of the supplied buffer,
+ *                p_len will return the complete device name length,
+ *                and not the number of bytes actually returned in p_dev_name.
+ *                The application may use this information to allocate a suitable buffer size.
+ *
+ * @param[out]    p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length.
+ * @param[in,out] p_len      Length of the buffer pointed by p_dev_name, complete device name length on output.
+ *
+ * @retval ::NRF_SUCCESS GAP device name retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len));
+
+
+/**@brief Initiate the GAP Authentication procedure.
+ *
+ * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected),
+ *          otherwise in the peripheral role, an SMP Security Request will be sent.
+ *
+ * @events
+ * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:}
+ * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST}
+ * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST}
+ * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY}
+ * @event{@ref BLE_GAP_EVT_KEY_PRESSED}
+ * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST}
+ * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST}
+ * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE}
+ * @event{@ref BLE_GAP_EVT_AUTH_STATUS}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure.
+ *                         In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used.
+ *                         In the central role, this pointer may be NULL to reject a Security Request.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
+ * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited.
+ */
+SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params));
+
+
+/**@brief Reply with GAP security parameters.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS.
+ * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have
+ *                         already been provided during a previous call to @ref sd_ble_gap_authenticate.
+ * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure
+ *                         will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application
+ *                         upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event.
+ *                         Note that the SoftDevice expects the application to provide memory for storing the
+ *                         peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key
+ *                         can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the
+ *                         @ref BLE_GAP_EVT_AUTH_STATUS event.
+ *
+ * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
+ */
+SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset));
+
+
+/**@brief Reply with an authentication key.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES.
+ * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL.
+ *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination)
+ *                     or NULL when confirming LE Secure Connections Numeric Comparison.
+ *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in Little Endian format.
+ *
+ * @retval ::NRF_SUCCESS Authentication key successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key));
+
+/**@brief Reply with an LE Secure connections DHKey.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_dhkey LE Secure Connections DHKey.
+ *
+ * @retval ::NRF_SUCCESS DHKey successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey));
+
+/**@brief Notify the peer of a local keypress.
+ *
+ * @details This function can only be used when an authentication procedure using LE Secure Connection is in progress. Calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES.
+ *
+ * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either not entering a passkey or keypresses have not been enabled by both peers.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not));
+
+/**@brief Generate a set of OOB data to send to a peer out of band.
+ *
+ * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established,
+ *       the one used during connection setup). The application may manually overwrite it with an updated value.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle. Can be BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet.
+ * @param[in] p_pk_own LE Secure Connections local P-256 Public Key.
+ * @param[out] p_oobd_own The OOB data to be sent out of band to a peer.
+ *
+ * @retval ::NRF_SUCCESS OOB data successfully generated.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own));
+
+/**@brief Provide the OOB data sent/received out of band.
+ *
+ * @note At least one of the 2 pointers provided must be different from NULL.
+ * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function.
+ * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if none sent.
+ * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received.
+ *
+ * @retval ::NRF_SUCCESS OOB data accepted.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer));
+
+/**@brief Initiate GAP Encryption procedure.
+ *
+ * @details In the central role, this function will initiate the encryption procedure using the encryption information provided.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure.
+ * @param[in] p_enc_info  Pointer to a @ref ble_gap_enc_info_t encryption information structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry.
+ */
+SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info));
+
+
+/**@brief Reply with GAP security information.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ * @note    Data signing is not yet supported, and p_sign_info must therefore be NULL.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available.
+ * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available.
+ * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available.
+ *
+ * @retval ::NRF_SUCCESS Successfully accepted security information.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info));
+
+
+/**@brief Get the current connection security.
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_conn_sec  Pointer to a @ref ble_gap_conn_sec_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Current connection security successfully retrieved.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec));
+
+
+/**@brief Start reporting the received signal strength to the application.
+ *
+ * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is
+                                         dependent on the settings of the <code>threshold_dbm</code>
+                                         and <code>skip_count</code> input parameters.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle        Connection handle.
+ * @param[in] threshold_dbm      Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID.
+ * @param[in] skip_count         Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully activated RSSI reporting.
+ * @retval ::NRF_ERROR_INVALID_STATE       Disconnection in progress. Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count));
+
+
+/**@brief Stop reporting the received signal strength.
+ *
+ * @note An RSSI change detected before the call but not yet received by the application
+ * may be reported after @ref sd_ble_gap_rssi_stop has been called.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully deactivated RSSI reporting.
+ * @retval ::NRF_ERROR_INVALID_STATE       Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle));
+
+
+/**@brief Get the received signal strength for the last connection event.
+ *
+ * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND
+ * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @endmscs
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_rssi      Pointer to the location where the RSSI measurement shall be stored.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully read the RSSI.
+ * @retval ::NRF_ERROR_NOT_FOUND           No sample is available.
+ * @retval ::NRF_ERROR_INVALID_ADDR        Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE       RSSI reporting is not ongoing, or disconnection in progress.
+ */
+SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi));
+
+
+/**@brief Start scanning (GAP Discovery procedure, Observer Procedure).
+ *
+ * @note To use the currently active whitelist set p_scan_params->p_whitelist to NULL.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_scan_params Pointer to scan parameters structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated scanning procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
+ */
+SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params));
+
+
+/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully stopped scanning procedure.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in scanning state).
+ */
+SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void));
+
+
+/**@brief Create a connection (GAP Link Establishment).
+ *
+ * @note To use the currently active whitelist set p_scan_params->p_whitelist to NULL.
+ * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
+ * @endmscs
+ *
+ * @param[in] p_peer_addr   Pointer to peer address. If the selective bit is set in @ref ble_gap_scan_params_t, then this must be NULL.
+ * @param[in] p_scan_params Pointer to scan parameters structure.
+ * @param[in] p_conn_params Pointer to desired connection parameters.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated connection procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address.
+ * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached.
+ * @retval ::NRF_ERROR_NO_MEM The configured memory pool (see @ref ble_conn_bw_counts_t) is not large enough for the
+ *                            bandwidth selected for this connection.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. If another connection is being established
+ *                          wait for the corresponding @ref BLE_GAP_EVT_CONNECTED event before calling again.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
+ */
+SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Cancel a connection establishment.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully cancelled an ongoing connection procedure.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ */
+SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_GAP_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatt.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatt.h
new file mode 100644
index 0000000000..c7023502bd
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatt.h
@@ -0,0 +1,215 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common
+  @{
+  @brief  Common definitions and prototypes for the GATT interfaces.
+ */
+
+#ifndef NRF_BLE_GATT_H__
+#define NRF_BLE_GATT_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATT_DEFINES Defines
+ * @{ */
+
+/** @brief Default MTU size. */
+#define GATT_MTU_SIZE_DEFAULT 23
+
+/** @brief Only the default MTU size of 23 is currently supported. */
+#define GATT_RX_MTU 23
+
+
+/**@brief Invalid Attribute Handle. */
+#define BLE_GATT_HANDLE_INVALID            0x0000
+
+/**@brief First Attribute Handle. */
+#define BLE_GATT_HANDLE_START              0x0001
+
+/**@brief Last Attribute Handle. */
+#define BLE_GATT_HANDLE_END                0xFFFF
+
+/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources
+ * @{ */
+#define BLE_GATT_TIMEOUT_SRC_PROTOCOL                  0x00 /**< ATT Protocol timeout. */
+/** @} */
+
+/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations
+ * @{ */
+#define BLE_GATT_OP_INVALID                0x00  /**< Invalid Operation. */
+#define BLE_GATT_OP_WRITE_REQ              0x01  /**< Write Request. */
+#define BLE_GATT_OP_WRITE_CMD              0x02  /**< Write Command. */
+#define BLE_GATT_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
+#define BLE_GATT_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
+#define BLE_GATT_OP_EXEC_WRITE_REQ         0x05  /**< Execute Write Request. */
+/** @} */
+
+/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags
+ * @{ */
+#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00
+#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE  0x01
+/** @} */
+
+/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations
+ * @{ */
+#define BLE_GATT_HVX_INVALID               0x00  /**< Invalid Operation. */
+#define BLE_GATT_HVX_NOTIFICATION          0x01  /**< Handle Value Notification. */
+#define BLE_GATT_HVX_INDICATION            0x02  /**< Handle Value Indication. */
+/** @} */
+
+/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes
+ * @{ */
+#define BLE_GATT_STATUS_SUCCESS                           0x0000  /**< Success. */
+#define BLE_GATT_STATUS_UNKNOWN                           0x0001  /**< Unknown or not applicable status. */
+#define BLE_GATT_STATUS_ATTERR_INVALID                    0x0100  /**< ATT Error: Invalid Error Code. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE             0x0101  /**< ATT Error: Invalid Attribute Handle. */
+#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED         0x0102  /**< ATT Error: Read not permitted. */
+#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED        0x0103  /**< ATT Error: Write not permitted. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_PDU                0x0104  /**< ATT Error: Used in ATT as Invalid PDU. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION       0x0105  /**< ATT Error: Authenticated link required. */
+#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED      0x0106  /**< ATT Error: Used in ATT as Request Not Supported. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET             0x0107  /**< ATT Error: Offset specified was past the end of the attribute. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION        0x0108  /**< ATT Error: Used in ATT as Insufficient Authorisation. */
+#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL         0x0109  /**< ATT Error: Used in ATT as Prepare Queue Full. */
+#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND        0x010A  /**< ATT Error: Used in ATT as Attribute not found. */
+#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG         0x010B  /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE         0x010C  /**< ATT Error: Encryption key size used is insufficient. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH     0x010D  /**< ATT Error: Invalid value size. */
+#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR             0x010E  /**< ATT Error: Very unlikely error. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION           0x010F  /**< ATT Error: Encrypted link required. */
+#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE     0x0110  /**< ATT Error: Attribute type is not a supported grouping attribute. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES            0x0111  /**< ATT Error: Encrypted link required. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN           0x0112  /**< ATT Error: Reserved for Future Use range #1 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END             0x017F  /**< ATT Error: Reserved for Future Use range #1 end. */
+#define BLE_GATT_STATUS_ATTERR_APP_BEGIN                  0x0180  /**< ATT Error: Application range begin. */
+#define BLE_GATT_STATUS_ATTERR_APP_END                    0x019F  /**< ATT Error: Application range end. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN           0x01A0  /**< ATT Error: Reserved for Future Use range #2 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END             0x01DF  /**< ATT Error: Reserved for Future Use range #2 end. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN           0x01E0  /**< ATT Error: Reserved for Future Use range #3 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END             0x01FC  /**< ATT Error: Reserved for Future Use range #3 end. */
+#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR      0x01FD  /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */
+#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG       0x01FE  /**< ATT Common Profile and Service Error: Procedure Already in Progress. */
+#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE           0x01FF  /**< ATT Common Profile and Service Error: Out Of Range. */
+/** @} */
+
+
+/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats
+ *  @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
+ * @{ */
+#define BLE_GATT_CPF_FORMAT_RFU                 0x00 /**< Reserved For Future Use. */
+#define BLE_GATT_CPF_FORMAT_BOOLEAN             0x01 /**< Boolean. */
+#define BLE_GATT_CPF_FORMAT_2BIT                0x02 /**< Unsigned 2-bit integer. */
+#define BLE_GATT_CPF_FORMAT_NIBBLE              0x03 /**< Unsigned 4-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT8               0x04 /**< Unsigned 8-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT12              0x05 /**< Unsigned 12-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT16              0x06 /**< Unsigned 16-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT24              0x07 /**< Unsigned 24-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT32              0x08 /**< Unsigned 32-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT48              0x09 /**< Unsigned 48-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT64              0x0A /**< Unsigned 64-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT128             0x0B /**< Unsigned 128-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT8               0x0C /**< Signed 2-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT12              0x0D /**< Signed 12-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT16              0x0E /**< Signed 16-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT24              0x0F /**< Signed 24-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT32              0x10 /**< Signed 32-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT48              0x11 /**< Signed 48-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT64              0x12 /**< Signed 64-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT128             0x13 /**< Signed 128-bit integer. */
+#define BLE_GATT_CPF_FORMAT_FLOAT32             0x14 /**< IEEE-754 32-bit floating point. */
+#define BLE_GATT_CPF_FORMAT_FLOAT64             0x15 /**< IEEE-754 64-bit floating point. */
+#define BLE_GATT_CPF_FORMAT_SFLOAT              0x16 /**< IEEE-11073 16-bit SFLOAT. */
+#define BLE_GATT_CPF_FORMAT_FLOAT               0x17 /**< IEEE-11073 32-bit FLOAT. */
+#define BLE_GATT_CPF_FORMAT_DUINT16             0x18 /**< IEEE-20601 format. */
+#define BLE_GATT_CPF_FORMAT_UTF8S               0x19 /**< UTF-8 string. */
+#define BLE_GATT_CPF_FORMAT_UTF16S              0x1A /**< UTF-16 string. */
+#define BLE_GATT_CPF_FORMAT_STRUCT              0x1B /**< Opaque Structure. */
+/** @} */
+
+/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces
+ * @{
+ */
+#define BLE_GATT_CPF_NAMESPACE_BTSIG            0x01 /**< Bluetooth SIG defined Namespace. */
+#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATT_STRUCTURES Structures
+ * @{ */
+
+/**@brief GATT Characteristic Properties. */
+typedef struct
+{
+  /* Standard properties */
+  uint8_t broadcast       :1; /**< Broadcasting of the value permitted. */
+  uint8_t read            :1; /**< Reading the value permitted. */
+  uint8_t write_wo_resp   :1; /**< Writing the value with Write Command permitted. */
+  uint8_t write           :1; /**< Writing the value with Write Request permitted. */
+  uint8_t notify          :1; /**< Notications of the value permitted. */
+  uint8_t indicate        :1; /**< Indications of the value permitted. */
+  uint8_t auth_signed_wr  :1; /**< Writing the value with Signed Write Command permitted. */
+} ble_gatt_char_props_t;
+
+/**@brief GATT Characteristic Extended Properties. */
+typedef struct
+{
+  /* Extended properties */
+  uint8_t reliable_wr     :1; /**< Writing the value with Queued Write operations permitted. */
+  uint8_t wr_aux          :1; /**< Writing the Characteristic User Description descriptor permitted. */
+} ble_gatt_char_ext_props_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_GATT_H__
+
+/** @} */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h
new file mode 100644
index 0000000000..5aa20fe430
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gattc.h
@@ -0,0 +1,572 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client
+  @{
+  @brief  Definitions and prototypes for the GATT Client interface.
+ */
+
+#ifndef NRF_BLE_GATTC_H__
+#define NRF_BLE_GATTC_H__
+
+#include "nrf_ble_gatt.h"
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief GATTC API SVC numbers. */
+enum BLE_GATTC_SVCS
+{
+  SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */
+  SD_BLE_GATTC_RELATIONSHIPS_DISCOVER,                         /**< Relationship Discovery. */
+  SD_BLE_GATTC_CHARACTERISTICS_DISCOVER,                       /**< Characteristic Discovery. */
+  SD_BLE_GATTC_DESCRIPTORS_DISCOVER,                           /**< Characteristic Descriptor Discovery. */
+  SD_BLE_GATTC_ATTR_INFO_DISCOVER,                             /**< Attribute Information Discovery. */
+  SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ,                        /**< Read Characteristic Value by UUID. */
+  SD_BLE_GATTC_READ,                                           /**< Generic read. */
+  SD_BLE_GATTC_CHAR_VALUES_READ,                               /**< Read multiple Characteristic Values. */
+  SD_BLE_GATTC_WRITE,                                          /**< Generic write. */
+  SD_BLE_GATTC_HV_CONFIRM,                                     /**< Handle Value Confirmation. */
+};
+
+/**
+ * @brief GATT Client Event IDs.
+ */
+enum BLE_GATTC_EVTS
+{
+  BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE,  /**< Primary Service Discovery Response event.      \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t.          */
+  BLE_GATTC_EVT_REL_DISC_RSP,                             /**< Relationship Discovery Response event.         \n See @ref ble_gattc_evt_rel_disc_rsp_t.                */
+  BLE_GATTC_EVT_CHAR_DISC_RSP,                            /**< Characteristic Discovery Response event.       \n See @ref ble_gattc_evt_char_disc_rsp_t.               */
+  BLE_GATTC_EVT_DESC_DISC_RSP,                            /**< Descriptor Discovery Response event.           \n See @ref ble_gattc_evt_desc_disc_rsp_t.               */
+  BLE_GATTC_EVT_ATTR_INFO_DISC_RSP,                       /**< Attribute Information Response event.          \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */
+  BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP,                /**< Read By UUID Response event.                   \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t.   */
+  BLE_GATTC_EVT_READ_RSP,                                 /**< Read Response event.                           \n See @ref ble_gattc_evt_read_rsp_t.                    */
+  BLE_GATTC_EVT_CHAR_VALS_READ_RSP,                       /**< Read multiple Response event.                  \n See @ref ble_gattc_evt_char_vals_read_rsp_t.          */
+  BLE_GATTC_EVT_WRITE_RSP,                                /**< Write Response event.                          \n See @ref ble_gattc_evt_write_rsp_t.                   */
+  BLE_GATTC_EVT_HVX,                                      /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm.  \n See @ref ble_gattc_evt_hvx_t. */
+  BLE_GATTC_EVT_TIMEOUT                                   /**< Timeout event.                                 \n See @ref ble_gattc_evt_timeout_t.                     */
+};
+
+/** @} */
+
+/** @addtogroup BLE_GATTC_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC
+ * @{ */
+#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED    (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */
+/** @} */
+
+/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats
+ * @{ */
+#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT    1 /**< 16-bit Attribute Information Format. */
+#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT   2 /**< 128-bit Attribute Information Format. */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATTC_STRUCTURES Structures
+ * @{ */
+
+/**@brief Operation Handle Range. */
+typedef struct
+{
+  uint16_t          start_handle; /**< Start Handle. */
+  uint16_t          end_handle;   /**< End Handle. */
+} ble_gattc_handle_range_t;
+
+
+/**@brief GATT service. */
+typedef struct
+{
+  ble_uuid_t               uuid;          /**< Service UUID. */
+  ble_gattc_handle_range_t handle_range;  /**< Service Handle Range. */
+} ble_gattc_service_t;
+
+
+/**@brief  GATT include. */
+typedef struct
+{
+  uint16_t            handle;           /**< Include Handle. */
+  ble_gattc_service_t included_srvc;    /**< Handle of the included service. */
+} ble_gattc_include_t;
+
+
+/**@brief GATT characteristic. */
+typedef struct
+{
+  ble_uuid_t              uuid;                 /**< Characteristic UUID. */
+  ble_gatt_char_props_t   char_props;           /**< Characteristic Properties. */
+  uint8_t                 char_ext_props : 1;   /**< Extended properties present. */
+  uint16_t                handle_decl;          /**< Handle of the Characteristic Declaration. */
+  uint16_t                handle_value;         /**< Handle of the Characteristic Value. */
+} ble_gattc_char_t;
+
+
+/**@brief GATT descriptor. */
+typedef struct
+{
+  uint16_t          handle;         /**< Descriptor Handle. */
+  ble_uuid_t        uuid;           /**< Descriptor UUID. */
+} ble_gattc_desc_t;
+
+
+/**@brief Write Parameters. */
+typedef struct
+{
+  uint8_t    write_op;                 /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */
+  uint8_t    flags;                    /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */
+  uint16_t   handle;                   /**< Handle to the attribute to be written. */
+  uint16_t   offset;                   /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */
+  uint16_t   len;                      /**< Length of data in bytes. */
+  uint8_t   *p_value;                  /**< Pointer to the value data. */
+} ble_gattc_write_params_t;
+
+/**@brief Attribute Information. */
+typedef struct
+{
+  uint16_t      handle;                /**< Attribute handle. */
+  union {
+    ble_uuid_t    uuid16;              /**< 16-bit Attribute UUID. */
+    ble_uuid128_t uuid128;             /**< 128-bit Attribute UUID. */
+  } info;
+} ble_gattc_attr_info_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */
+typedef struct
+{
+  uint16_t             count;           /**< Service count. */
+  ble_gattc_service_t services[1];      /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_prim_srvc_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */
+typedef struct
+{
+  uint16_t             count;           /**< Include count. */
+  ble_gattc_include_t includes[1];      /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_rel_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */
+typedef struct
+{
+  uint16_t            count;          /**< Characteristic count. */
+  ble_gattc_char_t    chars[1];       /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */
+typedef struct
+{
+  uint16_t            count;          /**< Descriptor count. */
+  ble_gattc_desc_t    descs[1];       /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_desc_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */
+typedef struct
+{
+  uint16_t                     count;        /**< Attribute count. */
+  uint8_t                      format;       /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */
+  ble_gattc_attr_info_t        attr_info[1]; /**< Attribute information. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_attr_info_disc_rsp_t;
+
+/**@brief GATT read by UUID handle value pair. */
+typedef struct
+{
+  uint16_t            handle;          /**< Attribute Handle. */
+  uint8_t             *p_value;        /**< Pointer to value, variable length (length available as value_len in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t).
+                                            Please note that this pointer is absolute to the memory provided by the user when retrieving the event,
+                                            so it will effectively point to a location inside the handle_value array. */
+} ble_gattc_handle_value_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */
+typedef struct
+{
+  uint16_t                  count;            /**< Handle-Value Pair Count. */
+  uint16_t                  value_len;        /**< Length of the value in Handle-Value(s) list. */
+  ble_gattc_handle_value_t  handle_value[1];  /**< Handle-Value(s) list. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                   See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_val_by_uuid_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */
+typedef struct
+{
+  uint16_t            handle;         /**< Attribute Handle. */
+  uint16_t            offset;         /**< Offset of the attribute data. */
+  uint16_t            len;            /**< Attribute data length. */
+  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */
+typedef struct
+{
+  uint16_t            len;            /**< Concatenated Attribute values length. */
+  uint8_t             values[1];      /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_vals_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */
+typedef struct
+{
+  uint16_t            handle;           /**< Attribute Handle. */
+  uint8_t             write_op;         /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */
+  uint16_t            offset;           /**< Data offset. */
+  uint16_t            len;              /**< Data length. */
+  uint8_t             data[1];          /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_write_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */
+typedef struct
+{
+  uint16_t            handle;         /**< Handle to which the HVx operation applies. */
+  uint8_t             type;           /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
+  uint16_t            len;            /**< Attribute data length. */
+  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_hvx_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
+} ble_gattc_evt_timeout_t;
+
+/**@brief GATTC event structure. */
+typedef struct
+{
+  uint16_t            conn_handle;                /**< Connection Handle on which event occured. */
+  uint16_t            gatt_status;                /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
+  uint16_t            error_handle;               /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
+  union
+  {
+    ble_gattc_evt_prim_srvc_disc_rsp_t          prim_srvc_disc_rsp;         /**< Primary Service Discovery Response Event Parameters. */
+    ble_gattc_evt_rel_disc_rsp_t                rel_disc_rsp;               /**< Relationship Discovery Response Event Parameters. */
+    ble_gattc_evt_char_disc_rsp_t               char_disc_rsp;              /**< Characteristic Discovery Response Event Parameters. */
+    ble_gattc_evt_desc_disc_rsp_t               desc_disc_rsp;              /**< Descriptor Discovery Response Event Parameters. */
+    ble_gattc_evt_char_val_by_uuid_read_rsp_t   char_val_by_uuid_read_rsp;  /**< Characteristic Value Read by UUID Response Event Parameters. */
+    ble_gattc_evt_read_rsp_t                    read_rsp;                   /**< Read Response Event Parameters. */
+    ble_gattc_evt_char_vals_read_rsp_t          char_vals_read_rsp;         /**< Characteristic Values Read Response Event Parameters. */
+    ble_gattc_evt_write_rsp_t                   write_rsp;                  /**< Write Response Event Parameters. */
+    ble_gattc_evt_hvx_t                         hvx;                        /**< Handle Value Notification/Indication Event Parameters. */
+    ble_gattc_evt_timeout_t                     timeout;                    /**< Timeout Event Parameters. */
+    ble_gattc_evt_attr_info_disc_rsp_t          attr_info_disc_rsp;         /**< Attribute Information Discovery Event Parameters. */
+  } params;                                                                 /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */
+} ble_gattc_evt_t;
+/** @} */
+
+/** @addtogroup BLE_GATTC_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Initiate or continue a GATT Primary Service Discovery procedure.
+ *
+ * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle.
+ *          If the last service has not been reached, this function must be called again with an updated start handle value to continue the search.
+ *
+ * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
+ *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] start_handle Handle to start searching from.
+ * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid));
+
+
+/**@brief Initiate or continue a GATT Relationship Discovery procedure.
+ *
+ * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached,
+ *          this must be called again with an updated handle range to continue the search.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_REL_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Characteristic Discovery procedure.
+ *
+ * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
+ *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure.
+ *
+ * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @events
+ * @event{BLE_GATTC_EVT_DESC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure.
+ *
+ * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @events
+ * @event{BLE_GATTC_EVT_DESC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_READ_UUID_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_uuid Pointer to a Characteristic value UUID to read.
+ * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure.
+ *
+ * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor
+ *          to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the
+ *          complete value.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] handle The handle of the attribute to be read.
+ * @param[in] offset Offset into the attribute value to be read.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset));
+
+
+/**@brief Initiate a GATT Read Multiple Characteristic Values procedure.
+ *
+ * @details This function initiates a GATT Read Multiple Characteristic Values procedure.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_READ_MULT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read.
+ * @param[in] handle_count The number of handles in p_handles.
+ *
+ * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count));
+
+
+/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure.
+ *
+ * @details This function can perform all write procedures described in GATT.
+ *
+ * @note    It is important to note that a write without response will <b>consume an application buffer</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. A write (with response) on the other hand will use the
+ *          standard client internal buffer and thus will only generate a @ref BLE_GATTC_EVT_WRITE_RSP event as soon as the write response
+ *          has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Generated when using write request or queued writes.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC}
+ * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC}
+ * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC}
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_write_params A pointer to a write parameters structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully started the Write procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS No available application packets for this connection.
+ */
+SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params));
+
+
+/**@brief Send a Handle Value Confirmation to the GATT Server.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_HVI_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] handle The handle of the attribute in the indication.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle.
+ */
+SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle));
+
+/**@brief Discovers information about a range of attributes on a GATT server.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.}
+ * @endevents
+ *
+ * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range The range of handles to request information about.
+ *
+ * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state
+ * @retval ::NRF_ERROR_INVALID_ADDR  Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_BLE_GATTC_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatts.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatts.h
new file mode 100644
index 0000000000..147d1a8fbf
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_gatts.h
@@ -0,0 +1,725 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server
+  @{
+  @brief  Definitions and prototypes for the GATTS interface.
+ */
+
+#ifndef NRF_BLE_GATTS_H__
+#define NRF_BLE_GATTS_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_ble_l2cap.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble_gatt.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations
+ * @{ */
+
+/**
+ * @brief GATTS API SVC numbers.
+ */
+enum BLE_GATTS_SVCS
+{
+  SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */
+  SD_BLE_GATTS_INCLUDE_ADD,                      /**< Add an included service. */
+  SD_BLE_GATTS_CHARACTERISTIC_ADD,               /**< Add a characteristic. */
+  SD_BLE_GATTS_DESCRIPTOR_ADD,                   /**< Add a generic attribute. */
+  SD_BLE_GATTS_VALUE_SET,                        /**< Set an attribute value. */
+  SD_BLE_GATTS_VALUE_GET,                        /**< Get an attribute value. */
+  SD_BLE_GATTS_HVX,                              /**< Handle Value Notification or Indication. */
+  SD_BLE_GATTS_SERVICE_CHANGED,                  /**< Perform a Service Changed Indication to one or more peers. */
+  SD_BLE_GATTS_RW_AUTHORIZE_REPLY,               /**< Reply to an authorization request for a read or write operation on one or more attributes. */
+  SD_BLE_GATTS_SYS_ATTR_SET,                     /**< Set the persistent system attributes for a connection. */
+  SD_BLE_GATTS_SYS_ATTR_GET,                     /**< Retrieve the persistent system attributes. */
+  SD_BLE_GATTS_INITIAL_USER_HANDLE_GET,          /**< Retrieve the first valid user handle. */
+  SD_BLE_GATTS_ATTR_GET                          /**< Retrieve the UUID and/or metadata of an attribute. */
+};
+
+/**
+ * @brief GATT Server Event IDs.
+ */
+enum BLE_GATTS_EVTS
+{
+  BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE,       /**< Write operation performed.                                           \n See @ref ble_gatts_evt_write_t.                 */
+  BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST,             /**< Read/Write Authorization request.                                    \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */
+  BLE_GATTS_EVT_SYS_ATTR_MISSING,                 /**< A persistent system attribute access is pending.                     \n Respond with @ref sd_ble_gatts_sys_attr_set.     \n See @ref ble_gatts_evt_sys_attr_missing_t.     */
+  BLE_GATTS_EVT_HVC,                              /**< Handle Value Confirmation.                                           \n See @ref ble_gatts_evt_hvc_t.                   */
+  BLE_GATTS_EVT_SC_CONFIRM,                       /**< Service Changed Confirmation. No additional event structure applies.                                                    */
+  BLE_GATTS_EVT_TIMEOUT                           /**< Peer failed to resonpond to an ATT request in time.                  \n See @ref ble_gatts_evt_timeout_t.               */
+};
+/** @} */
+
+/** @addtogroup BLE_GATTS_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS
+ * @{ */
+#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE   (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */
+#define BLE_ERROR_GATTS_SYS_ATTR_MISSING    (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */
+/** @} */
+
+/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths
+ * @{ */
+#define BLE_GATTS_FIX_ATTR_LEN_MAX (510)  /**< Maximum length for fixed length Attribute Values. */
+#define BLE_GATTS_VAR_ATTR_LEN_MAX (512)  /**< Maximum length for variable length Attribute Values. */
+/** @} */
+
+/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types
+ * @{ */
+#define BLE_GATTS_SRVC_TYPE_INVALID          0x00  /**< Invalid Service Type. */
+#define BLE_GATTS_SRVC_TYPE_PRIMARY          0x01  /**< Primary Service. */
+#define BLE_GATTS_SRVC_TYPE_SECONDARY        0x02  /**< Secondary Type. */
+/** @} */
+
+
+/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types
+ * @{ */
+#define BLE_GATTS_ATTR_TYPE_INVALID         0x00  /**< Invalid Attribute Type. */
+#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL  0x01  /**< Primary Service Declaration. */
+#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL   0x02  /**< Secondary Service Declaration. */
+#define BLE_GATTS_ATTR_TYPE_INC_DECL        0x03  /**< Include Declaration. */
+#define BLE_GATTS_ATTR_TYPE_CHAR_DECL       0x04  /**< Characteristic Declaration. */
+#define BLE_GATTS_ATTR_TYPE_CHAR_VAL        0x05  /**< Characteristic Value. */
+#define BLE_GATTS_ATTR_TYPE_DESC            0x06  /**< Descriptor. */
+#define BLE_GATTS_ATTR_TYPE_OTHER           0x07  /**< Other, non-GATT specific type. */
+/** @} */
+
+
+/** @defgroup BLE_GATTS_OPS GATT Server Operations
+ * @{ */
+#define BLE_GATTS_OP_INVALID                0x00  /**< Invalid Operation. */
+#define BLE_GATTS_OP_WRITE_REQ              0x01  /**< Write Request. */
+#define BLE_GATTS_OP_WRITE_CMD              0x02  /**< Write Command. */
+#define BLE_GATTS_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
+#define BLE_GATTS_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
+#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL  0x05  /**< Execute Write Request: Cancel all prepared writes. */
+#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW     0x06  /**< Execute Write Request: Immediately execute all prepared writes. */
+/** @} */
+
+/** @defgroup BLE_GATTS_VLOCS GATT Value Locations
+ * @{ */
+#define BLE_GATTS_VLOC_INVALID       0x00  /**< Invalid Location. */
+#define BLE_GATTS_VLOC_STACK         0x01  /**< Attribute Value is located in stack memory, no user memory is required. */
+#define BLE_GATTS_VLOC_USER          0x02  /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack
+                                                will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */
+/** @} */
+
+/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types
+ * @{ */
+#define BLE_GATTS_AUTHORIZE_TYPE_INVALID    0x00  /**< Invalid Type. */
+#define BLE_GATTS_AUTHORIZE_TYPE_READ       0x01  /**< Authorize a Read Operation. */
+#define BLE_GATTS_AUTHORIZE_TYPE_WRITE      0x02  /**< Authorize a Write Request Operation. */
+/** @} */
+
+/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags
+ * @{ */
+#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0)  /**< Restrict system attributes to system services only. */
+#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1)  /**< Restrict system attributes to user services only. */
+/** @} */
+
+/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size
+ * @{
+ */
+#define BLE_GATTS_ATTR_TAB_SIZE_MIN         216    /**< Minimum Attribute Table size */
+#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT     0x0000 /**< Default Attribute Table size (0x580 bytes for this version of the SoftDevice). */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATTS_STRUCTURES Structures
+ * @{ */
+
+/**
+ * @brief BLE GATTS initialization parameters.
+ */
+typedef struct
+{
+  uint8_t   service_changed:1;             /**< Include the Service Changed characteristic in the Attribute Table. */
+  uint32_t  attr_tab_size;                 /**< Attribute Table size in bytes. The size must be a multiple of 4. @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT is used to set the default size. */
+} ble_gatts_enable_params_t;
+
+/**@brief Attribute metadata. */
+typedef struct
+{
+  ble_gap_conn_sec_mode_t read_perm;       /**< Read permissions. */
+  ble_gap_conn_sec_mode_t write_perm;      /**< Write permissions. */
+  uint8_t                 vlen       :1;   /**< Variable length attribute. */
+  uint8_t                 vloc       :2;   /**< Value location, see @ref BLE_GATTS_VLOCS.*/
+  uint8_t                 rd_auth    :1;   /**< Read authorization and value will be requested from the application on every read operation. */
+  uint8_t                 wr_auth    :1;   /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */
+} ble_gatts_attr_md_t;
+
+
+/**@brief GATT Attribute. */
+typedef struct
+{
+  ble_uuid_t          *p_uuid;          /**< Pointer to the attribute UUID. */
+  ble_gatts_attr_md_t *p_attr_md;       /**< Pointer to the attribute metadata structure. */
+  uint16_t             init_len;        /**< Initial attribute value length in bytes. */
+  uint16_t             init_offs;       /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
+  uint16_t             max_len;         /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
+  uint8_t*             p_value;         /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer
+                                             that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location.
+                                             The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/
+} ble_gatts_attr_t;
+
+/**@brief GATT Attribute Value. */
+typedef struct
+{
+  uint16_t  len;        /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/
+  uint16_t  offset;     /**< Attribute value offset. */
+  uint8_t   *p_value;   /**< Pointer to where value is stored or will be stored.
+                             If value is stored in user memory, only the attribute length is updated when p_value == NULL.
+                             Set to NULL when reading to obtain the complete length of the attribute value */
+} ble_gatts_value_t;
+
+
+/**@brief GATT Characteristic Presentation Format. */
+typedef struct
+{
+  uint8_t          format;      /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */
+  int8_t           exponent;    /**< Exponent for integer data types. */
+  uint16_t         unit;        /**< Unit from Bluetooth Assigned Numbers. */
+  uint8_t          name_space;  /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
+  uint16_t         desc;        /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
+} ble_gatts_char_pf_t;
+
+
+/**@brief GATT Characteristic metadata. */
+typedef struct
+{
+  ble_gatt_char_props_t       char_props;               /**< Characteristic Properties. */
+  ble_gatt_char_ext_props_t   char_ext_props;           /**< Characteristic Extended Properties. */
+  uint8_t                    *p_char_user_desc;         /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */
+  uint16_t                    char_user_desc_max_size;  /**< The maximum size in bytes of the user description descriptor. */
+  uint16_t                    char_user_desc_size;      /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */
+  ble_gatts_char_pf_t*        p_char_pf;                /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */
+  ble_gatts_attr_md_t*        p_user_desc_md;           /**< Attribute metadata for the User Description descriptor, or NULL for default values. */
+  ble_gatts_attr_md_t*        p_cccd_md;                /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */
+  ble_gatts_attr_md_t*        p_sccd_md;                /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */
+} ble_gatts_char_md_t;
+
+
+/**@brief GATT Characteristic Definition Handles. */
+typedef struct
+{
+  uint16_t          value_handle;       /**< Handle to the characteristic value. */
+  uint16_t          user_desc_handle;   /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+  uint16_t          cccd_handle;        /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+  uint16_t          sccd_handle;        /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+} ble_gatts_char_handles_t;
+
+
+/**@brief GATT HVx parameters. */
+typedef struct
+{
+  uint16_t          handle;             /**< Characteristic Value Handle. */
+  uint8_t           type;               /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
+  uint16_t          offset;             /**< Offset within the attribute value. */
+  uint16_t         *p_len;              /**< Length in bytes to be written, length in bytes written after successful return. */
+  uint8_t          *p_data;             /**< Actual data content, use NULL to use the current attribute value. */
+} ble_gatts_hvx_params_t;
+
+/**@brief GATT Authorization parameters. */
+typedef struct
+{
+  uint16_t          gatt_status;        /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
+  uint8_t           update : 1;         /**< If set, data supplied in p_data will be used to update the attribute value.
+                                             Please note that for @ref BLE_GATTS_OP_WRITE_REQ operations this bit must always be set,
+                                             as the data to be written needs to be stored and later provided by the application. */
+  uint16_t          offset;             /**< Offset of the attribute value being updated. */
+  uint16_t          len;                /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */
+  const uint8_t    *p_data;             /**< Pointer to new value used to update the attribute value. */
+} ble_gatts_authorize_params_t;
+
+/**@brief GATT Read or Write Authorize Reply parameters. */
+typedef struct
+{
+  uint8_t                               type;   /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
+  union {
+    ble_gatts_authorize_params_t        read;   /**< Read authorization parameters. */
+    ble_gatts_authorize_params_t        write;  /**< Write authorization parameters. */
+  } params;                                     /**< Reply Parameters. */
+} ble_gatts_rw_authorize_reply_params_t;
+
+
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */
+typedef struct
+{
+  uint16_t                    handle;             /**< Attribute Handle. */
+  ble_uuid_t                  uuid;               /**< Attribute UUID. */
+  uint8_t                     op;                 /**< Type of write operation, see @ref BLE_GATTS_OPS. */
+  uint8_t                     auth_required;      /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalise the writing operation. */
+  uint16_t                    offset;             /**< Offset for the write operation. */
+  uint16_t                    len;                /**< Length of the received data. */
+  uint8_t                     data[1];            /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gatts_evt_write_t;
+
+/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */
+typedef struct
+{
+  uint16_t                    handle;             /**< Attribute Handle. */
+  ble_uuid_t                  uuid;               /**< Attribute UUID. */
+  uint16_t                    offset;             /**< Offset for the read operation. */
+} ble_gatts_evt_read_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */
+typedef struct
+{
+  uint8_t                     type;             /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
+  union {
+    ble_gatts_evt_read_t      read;             /**< Attribute Read Parameters. */
+    ble_gatts_evt_write_t     write;            /**< Attribute Write Parameters. */
+  } request;                                    /**< Request Parameters. */
+} ble_gatts_evt_rw_authorize_request_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */
+typedef struct
+{
+  uint8_t hint;                                 /**< Hint (currently unused). */
+} ble_gatts_evt_sys_attr_missing_t;
+
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */
+typedef struct
+{
+  uint16_t          handle;                       /**< Attribute Handle. */
+} ble_gatts_evt_hvc_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
+} ble_gatts_evt_timeout_t;
+
+
+/**@brief GATT Server event callback event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                                       /**< Connection Handle on which the event occurred. */
+  union
+  {
+    ble_gatts_evt_write_t                 write;              /**< Write Event Parameters. */
+    ble_gatts_evt_rw_authorize_request_t  authorize_request;  /**< Read or Write Authorize Request Parameters. */
+    ble_gatts_evt_sys_attr_missing_t      sys_attr_missing;   /**< System attributes missing. */
+    ble_gatts_evt_hvc_t                   hvc;                /**< Handle Value Confirmation Event Parameters. */
+    ble_gatts_evt_timeout_t               timeout;            /**< Timeout Event. */
+  } params;                                                   /**< Event Parameters. */
+} ble_gatts_evt_t;
+
+/** @} */
+
+/** @addtogroup BLE_GATTS_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Add a service declaration to the Attribute Table.
+ *
+ * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to
+ *       add a secondary service declaration that is not referenced by another service later in the Attribute Table.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] type      Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES.
+ * @param[in] p_uuid    Pointer to service UUID.
+ * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a service declaration.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle));
+
+
+/**@brief Add an include declaration to the Attribute Table.
+ *
+ * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time).
+ *
+ * @note The included service must already be present in the Attribute Table prior to this call.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] service_handle    Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] inc_srvc_handle   Handle of the included service.
+ * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added an include declaration.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ */
+SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle));
+
+
+/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table.
+ *
+ * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time).
+ *
+ * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writeable auxiliaries bits,
+ *       readable (no security) and writeable (selectable) CCCDs and SCCDs and valid presentation format values.
+ *
+ * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] service_handle    Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] p_char_md         Characteristic metadata.
+ * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value.
+ * @param[out] p_handles        Pointer to the structure where the assigned handles will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a characteristic.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ */
+SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles));
+
+
+/**@brief Add a descriptor to the Attribute Table.
+ *
+ * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] char_handle   Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] p_attr        Pointer to the attribute structure.
+ * @param[out] p_handle     Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a descriptor.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ */
+SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle));
+
+/**@brief Set the value of a given attribute.
+ *
+ * @note Values other than system attributes can be set at any time, regardless of wheter any active connections exist.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle. If the value does not belong to a system attribute then @ref BLE_CONN_HANDLE_INVALID can be used.
+ * @param[in] handle       Attribute handle.
+ * @param[in,out] p_value  Attribute value information.
+ *
+ * @retval ::NRF_SUCCESS Successfully set the value of the attribute.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE @ref BLE_CONN_HANDLE_INVALID supplied on a system attribute.
+ */
+SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
+
+/**@brief Get the value of a given attribute.
+ *
+ * @note                 If the attribute value is longer than the size of the supplied buffer,
+ *                       p_len will return the total attribute value length (excluding offset),
+ *                       and not the number of bytes actually returned in p_data.
+ *                       The application may use this information to allocate a suitable buffer size.
+ *
+ * @note                 When retrieving system attribute values with this function, the connection handle
+ *                       may refer to an already disconnected connection. Refer to the documentation of
+ *                       @ref sd_ble_gatts_sys_attr_get for further information.
+ *
+ * @param[in] conn_handle  Connection handle. If the value does not belong to a system attribute then @ref BLE_CONN_HANDLE_INVALID can be used.
+ * @param[in] handle       Attribute handle.
+ * @param[in,out] p_value  Attribute value information.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE @ref BLE_CONN_HANDLE_INVALID supplied on a system attribute.
+ */
+SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
+
+/**@brief Notify or Indicate an attribute value.
+ *
+ * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation
+ *          (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that
+ *          the application can atomically perform a value update and a server initiated transaction with a single API call.
+ *          If the application chooses to indicate an attribute value, a @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from
+ *          the peer.
+ *
+ * @note    The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution.
+ *          When receiveing the error codes @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and
+ *          @ref BLE_ERROR_NO_TX_PACKETS the Attribute Table has been updated.
+ *          The caller can check whether the value has been updated by looking at the contents of *(p_hvx_params->p_len).
+ *
+ * @note    It is important to note that a notification will <b>consume an application buffer</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. An indication on the other hand will use the
+ *          standard server internal buffer and thus will only generate a @ref BLE_GATTS_EVT_HVC event as soon as the confirmation
+ *          has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_EVT_TX_COMPLETE, Transmission complete.}
+ * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
+ * @mmsc{@ref BLE_GATTS_HVN_MSC}
+ * @mmsc{@ref BLE_GATTS_HVI_MSC}
+ * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC}
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle.
+ * @param[in] p_hvx_params Pointer to an HVx parameters structure. If the p_data member contains a non-NULL pointer the attribute value will be updated with
+ *                         the contents pointed by it before sending the notification or indication.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or notifications and/or indications not enabled in the CCCD.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS  No available application packets for this connection, applies only to notifications.
+ */
+SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params));
+
+/**@brief Indicate the Service Changed attribute value.
+ *
+ * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute
+ *          Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will
+ *          be issued.
+ *
+ * @note    Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here.
+ *
+ * @events
+ * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_SC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle.
+ * @param[in] start_handle Start of affected attribute handle range.
+ * @param[in] end_handle   End of affected attribute handle range.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref sd_ble_enable and @ref ble_gatts_enable_params_t.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or notifications and/or indications not enabled in the CCCD.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ */
+SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle));
+
+/**@brief Respond to a Read/Write authorization request.
+ *
+ * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle                 Connection handle.
+ * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application.
+ *
+ * @retval ::NRF_SUCCESS               Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR    Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE   Invalid Connection State or no authorization request pending.
+ * @retval ::NRF_ERROR_INVALID_PARAM   Authorization op invalid,
+ *                                         handle supplied does not match requested handle,
+ *                                         or invalid data to be written provided by the application.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params));
+
+
+/**@brief Update persistent system attribute information.
+ *
+ * @details Supply information about persistent system attributes to the stack,
+ *          previously obtained using @ref sd_ble_gatts_sys_attr_get.
+ *          This call is only allowed for active connections, and is usually
+ *          made immediately after a connection is established with an known bonded device,
+ *          often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING.
+ *
+ *          p_sysattrs may point directly to the application's stored copy of the system attributes
+ *          obtained using @ref sd_ble_gatts_sys_attr_get.
+ *          If the pointer is NULL, the system attribute info is initialized, assuming that
+ *          the application does not have any previously saved system attribute data for this device.
+ *
+ * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration.
+ *
+ * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially.
+ *       This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or
+ *       reset the SoftDevice to return to a known state.
+ *
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified.
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC}
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
+ * @endmscs
+ *
+ * @param[in]  conn_handle        Connection handle.
+ * @param[in]  p_sys_attr_data    Pointer to a saved copy of system attributes supplied to the stack, or NULL.
+ * @param[in]  len                Size of data pointed by p_sys_attr_data, in octets.
+ * @param[in]  flags              Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
+ *
+ * @retval ::NRF_SUCCESS Successfully set the system attribute information.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags));
+
+
+/**@brief Retrieve persistent system attribute information from the stack.
+ *
+ * @details This call is used to retrieve information about values to be stored perisistently by the application
+ *          during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device,
+ *          the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set.
+ *          If retrieved after disconnection, the data should be read before a new connection established. The connection handle for
+ *          the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it.
+ *          Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes
+ *          may be written to at any time by the peer during a connection's lifetime.
+ *
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned.
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
+ * @endmscs
+ *
+ * @param[in]     conn_handle       Connection handle of the recently terminated connection.
+ * @param[out]    p_sys_attr_data   Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described
+ *                                  in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data.
+ * @param[in,out] p_len             Size of application buffer if p_sys_attr_data is not NULL. Unconditially updated to actual length of system attribute data.
+ * @param[in]     flags             Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer.
+ * @retval ::NRF_ERROR_NOT_FOUND No system attributes found.
+ */
+SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags));
+
+
+/**@brief Retrieve the first valid user attribute handle.
+ *
+ * @param[out] p_handle   Pointer to an integer where the handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle));
+
+/**@brief Retrieve the attribute UUID and/or metadata.
+ *
+ * @param[in]  handle Attribute handle
+ * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field.
+ * @param[out] p_md Metadata of the attribute. Use NULL to omit this field.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata,
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found.
+ */
+SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_GATTS_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_hci.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_hci.h
new file mode 100644
index 0000000000..a709c0a60f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_hci.h
@@ -0,0 +1,134 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+*/
+
+
+#ifndef NRF_BLE_HCI_H__
+#define NRF_BLE_HCI_H__ 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes
+ * @{ */
+
+#define BLE_HCI_STATUS_CODE_SUCCESS                        0x00   /**< Success. */
+#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND           0x01   /**< Unknown BLE Command. */
+#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER  0x02   /**< Unknown Connection Identifier. */
+/*0x03 Hardware Failure
+0x04 Page Timeout
+*/
+#define BLE_HCI_AUTHENTICATION_FAILURE                     0x05   /**< Authentication Failure. */
+#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING             0x06   /**< Pin or Key missing. */
+#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED                   0x07   /**< Memory Capacity Exceeded. */
+#define BLE_HCI_CONNECTION_TIMEOUT                         0x08   /**< Connection Timeout. */
+/*0x09 Connection Limit Exceeded
+0x0A Synchronous Connection Limit To A Device Exceeded
+0x0B ACL Connection Already Exists*/
+#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED             0x0C   /**< Command Disallowed. */
+/*0x0D Connection Rejected due to Limited Resources
+0x0E Connection Rejected Due To Security Reasons
+0x0F Connection Rejected due to Unacceptable BD_ADDR
+0x10 Connection Accept Timeout Exceeded
+0x11 Unsupported Feature or Parameter Value*/
+#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12  /**< Invalid BLE Command Parameters. */
+#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION           0x13  /**< Remote User Terminated Connection. */
+#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14  /**< Remote Device Terminated Connection due to low resources.*/
+#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF     0x15  /**< Remote Device Terminated Connection due to power off. */
+#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION            0x16  /**< Local Host Terminated Connection. */
+/*
+0x17 Repeated Attempts
+0x18 Pairing Not Allowed
+0x19 Unknown LMP PDU
+*/
+#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A                   /**< Unsupported Remote Feature. */
+/*
+0x1B SCO Offset Rejected
+0x1C SCO Interval Rejected
+0x1D SCO Air Mode Rejected*/
+#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS     0x1E       /**< Invalid LMP Parameters. */
+#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR          0x1F       /**< Unspecified Error. */
+/*0x20 Unsupported LMP Parameter Value
+0x21 Role Change Not Allowed
+*/
+#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT       0x22       /**< LMP Response Timeout. */
+/*0x23 LMP Error Transaction Collision*/
+#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED        0x24       /**< LMP PDU Not Allowed. */
+/*0x25 Encryption Mode Not Acceptable
+0x26 Link Key Can Not be Changed
+0x27 Requested QoS Not Supported
+*/
+#define BLE_HCI_INSTANT_PASSED                         0x28       /**< Instant Passed. */
+#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED      0x29       /**< Pairing with Unit Key Unsupported. */
+#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION        0x2A       /**< Different Transaction Collision. */
+/*
+0x2B Reserved
+0x2C QoS Unacceptable Parameter
+0x2D QoS Rejected
+0x2E Channel Classification Not Supported
+0x2F Insufficient Security
+0x30 Parameter Out Of Mandatory Range
+0x31 Reserved
+0x32 Role Switch Pending
+0x33 Reserved
+0x34 Reserved Slot Violation
+0x35 Role Switch Failed
+0x36 Extended Inquiry Response Too Large
+0x37 Secure Simple Pairing Not Supported By Host.
+0x38 Host Busy - Pairing
+0x39 Connection Rejected due to No Suitable Channel Found*/
+#define BLE_HCI_CONTROLLER_BUSY                        0x3A       /**< Controller Busy. */
+#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE             0x3B       /**< Connection Interval Unacceptable. */
+#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT            0x3C       /**< Directed Adverisement Timeout. */
+#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE     0x3D       /**< Connection Terminated due to MIC Failure. */
+#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED          0x3E       /**< Connection Failed to be Established. */
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_HCI_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h
new file mode 100644
index 0000000000..57d3592969
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_l2cap.h
@@ -0,0 +1,205 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP)
+  @{
+  @brief Definitions and prototypes for the L2CAP interface.
+ */
+
+#ifndef NRF_BLE_L2CAP_H__
+#define NRF_BLE_L2CAP_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_ble_err.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief L2CAP API SVC numbers. */
+enum BLE_L2CAP_SVCS
+{
+  SD_BLE_L2CAP_CID_REGISTER = BLE_L2CAP_SVC_BASE,  /**< Register a CID. */
+  SD_BLE_L2CAP_CID_UNREGISTER,                     /**< Unregister a CID. */
+  SD_BLE_L2CAP_TX                                  /**< Transmit a packet. */
+};
+
+/**@brief L2CAP Event IDs. */
+enum BLE_L2CAP_EVTS
+{
+  BLE_L2CAP_EVT_RX  = BLE_L2CAP_EVT_BASE          /**< L2CAP packet received. */
+};
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_DEFINES Defines
+ * @{ */
+
+/**@defgroup BLE_ERRORS_L2CAP SVC return values specific to L2CAP
+ * @{ */
+#define BLE_ERROR_L2CAP_CID_IN_USE            (NRF_L2CAP_ERR_BASE + 0x000)  /**< CID already in use. */
+/** @} */
+
+/**@brief Default L2CAP MTU. */
+#define BLE_L2CAP_MTU_DEF           (23)
+
+/**@brief Invalid Channel Identifier. */
+#define BLE_L2CAP_CID_INVALID       (0x0000)
+
+/**@brief Dynamic Channel Identifier base. */
+#define BLE_L2CAP_CID_DYN_BASE      (0x0040)
+
+/**@brief Maximum amount of dynamic CIDs. */
+#define BLE_L2CAP_CID_DYN_MAX       (8)
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_STRUCTURES Structures
+ * @{ */
+
+/**@brief Packet header format for L2CAP transmission. */
+typedef struct
+{
+  uint16_t   len;                                 /**< Length of valid info in data member. */
+  uint16_t   cid;                                 /**< Channel ID on which packet is transmitted. */
+} ble_l2cap_header_t;
+
+
+/**@brief L2CAP Received packet event report. */
+typedef struct
+{
+  ble_l2cap_header_t header;                      /**< L2CAP packet header. */
+  uint8_t    data[1];                             /**< Packet data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_l2cap_evt_rx_t;
+
+
+/**@brief L2CAP event callback event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                           /**< Connection Handle on which event occured. */
+  union
+  {
+    ble_l2cap_evt_rx_t rx;                        /**< RX Event parameters. */
+  } params;                                       /**< Event Parameters. */
+} ble_l2cap_evt_t;
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Register a CID with L2CAP.
+ *
+ * @details This registers a higher protocol layer with the L2CAP multiplexer, and is requried prior to all operations on the CID.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] cid L2CAP CID.
+ *
+ * @retval ::NRF_SUCCESS Successfully registered a CID with the L2CAP layer.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CID must be above @ref BLE_L2CAP_CID_DYN_BASE.
+ * @retval ::BLE_ERROR_L2CAP_CID_IN_USE L2CAP CID already in use.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_L2CAP_CID_REGISTER, uint32_t, sd_ble_l2cap_cid_register(uint16_t cid));
+
+/**@brief Unregister a CID with L2CAP.
+ *
+ * @details This unregisters a previously registerd higher protocol layer with the L2CAP multiplexer.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] cid L2CAP CID.
+ *
+ * @retval ::NRF_SUCCESS Successfully unregistered the CID.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND CID not previously registered.
+ */
+SVCALL(SD_BLE_L2CAP_CID_UNREGISTER, uint32_t, sd_ble_l2cap_cid_unregister(uint16_t cid));
+
+/**@brief Transmit an L2CAP packet.
+ *
+ * @note    It is important to note that a call to this function will <b>consume an application packet</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted.
+ *          Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_EVT_TX_COMPLETE}
+ * @event{@ref BLE_L2CAP_EVT_RX}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection Handle.
+ * @param[in] p_header    Pointer to a packet header containing length and CID.
+ * @param[in] p_data      Pointer to the data to be transmitted.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued an L2CAP packet for transmission.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CIDs must be registered beforehand with @ref sd_ble_l2cap_cid_register.
+ * @retval ::NRF_ERROR_NOT_FOUND CID not found.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS Not enough application packets available.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, see @ref BLE_L2CAP_MTU_DEF.
+ */
+SVCALL(SD_BLE_L2CAP_TX, uint32_t, sd_ble_l2cap_tx(uint16_t conn_handle, ble_l2cap_header_t const *p_header, uint8_t const *p_data));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_L2CAP_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_ranges.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_ranges.h
new file mode 100644
index 0000000000..7476d488c0
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_ranges.h
@@ -0,0 +1,129 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @defgroup ble_ranges Module specific SVC, event and option number subranges
+  @{
+
+  @brief Definition of SVC, event and option number subranges for each API module.
+
+  @note
+  SVCs, event and option numbers are split into subranges for each API module.
+  Each module receives its entire allocated range of SVC calls, whether implemented or not,
+  but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range.
+
+  Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range,
+  rather than the last SVC function call actually defined and implemented.
+
+  Specific SVC, event and option values are defined in each module's ble_<module>.h file,
+  which defines names of each individual SVC code based on the range start value.
+*/
+
+#ifndef NRF_BLE_RANGES_H__
+#define NRF_BLE_RANGES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BLE_SVC_BASE           0x60       /**< Common BLE SVC base. */
+#define BLE_SVC_LAST           0x6B       /**< Total: 12. */
+
+#define BLE_RESERVED_SVC_BASE  0x6C       /**< Reserved BLE SVC base. */
+#define BLE_RESERVED_SVC_LAST  0x6F       /**< Total: 4. */
+
+#define BLE_GAP_SVC_BASE       0x70       /**< GAP BLE SVC base. */
+#define BLE_GAP_SVC_LAST       0x8F       /**< Total: 32. */
+
+#define BLE_GATTC_SVC_BASE     0x90       /**< GATTC BLE SVC base. */
+#define BLE_GATTC_SVC_LAST     0x9F       /**< Total: 32. */
+
+#define BLE_GATTS_SVC_BASE     0xA0       /**< GATTS BLE SVC base. */
+#define BLE_GATTS_SVC_LAST     0xAF       /**< Total: 16. */
+
+#define BLE_L2CAP_SVC_BASE     0xB0       /**< L2CAP BLE SVC base. */
+#define BLE_L2CAP_SVC_LAST     0xBF       /**< Total: 16. */
+
+
+#define BLE_EVT_INVALID        0x00       /**< Invalid BLE Event. */
+
+#define BLE_EVT_BASE           0x01       /**< Common BLE Event base. */
+#define BLE_EVT_LAST           0x0F       /**< Total: 15. */
+
+#define BLE_GAP_EVT_BASE       0x10       /**< GAP BLE Event base. */
+#define BLE_GAP_EVT_LAST       0x2F       /**< Total: 32. */
+
+#define BLE_GATTC_EVT_BASE     0x30       /**< GATTC BLE Event base. */
+#define BLE_GATTC_EVT_LAST     0x4F       /**< Total: 32. */
+
+#define BLE_GATTS_EVT_BASE     0x50       /**< GATTS BLE Event base. */
+#define BLE_GATTS_EVT_LAST     0x6F       /**< Total: 32. */
+
+#define BLE_L2CAP_EVT_BASE     0x70       /**< L2CAP BLE Event base. */
+#define BLE_L2CAP_EVT_LAST     0x8F       /**< Total: 32.  */
+
+
+#define BLE_OPT_INVALID        0x00       /**< Invalid BLE Option. */
+
+#define BLE_OPT_BASE           0x01       /**< Common BLE Option base. */
+#define BLE_OPT_LAST           0x1F       /**< Total: 31. */
+
+#define BLE_GAP_OPT_BASE       0x20       /**< GAP BLE Option base. */
+#define BLE_GAP_OPT_LAST       0x3F       /**< Total: 32. */
+
+#define BLE_GATTC_OPT_BASE     0x40       /**< GATTC BLE Option base. */
+#define BLE_GATTC_OPT_LAST     0x5F       /**< Total: 32. */
+
+#define BLE_GATTS_OPT_BASE     0x60       /**< GATTS BLE Option base. */
+#define BLE_GATTS_OPT_LAST     0x7F       /**< Total: 32. */
+
+#define BLE_L2CAP_OPT_BASE     0x80       /**< L2CAP BLE Option base. */
+#define BLE_L2CAP_OPT_LAST     0x9F       /**< Total: 32.  */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_BLE_RANGES_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_types.h
new file mode 100644
index 0000000000..0ef31dd83a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_ble_types.h
@@ -0,0 +1,208 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @defgroup ble_types Common types and macro definitions
+  @{
+
+  @brief Common types and macro definitions for the BLE SoftDevice.
+ */
+
+#ifndef NRF_BLE_TYPES_H__
+#define NRF_BLE_TYPES_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_TYPES_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_CONN_HANDLES BLE Connection Handles
+ * @{ */
+#define BLE_CONN_HANDLE_INVALID 0xFFFF  /**< Invalid Connection Handle. */
+#define BLE_CONN_HANDLE_ALL     0xFFFE  /**< Applies to all Connection Handles. */
+/** @} */
+
+
+/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs
+ * @{ */
+/* Generic UUIDs, applicable to all services */
+#define BLE_UUID_UNKNOWN                              0x0000 /**< Reserved UUID. */
+#define BLE_UUID_SERVICE_PRIMARY                      0x2800 /**< Primary Service. */
+#define BLE_UUID_SERVICE_SECONDARY                    0x2801 /**< Secondary Service. */
+#define BLE_UUID_SERVICE_INCLUDE                      0x2802 /**< Include. */
+#define BLE_UUID_CHARACTERISTIC                       0x2803 /**< Characteristic. */
+#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP             0x2900 /**< Characteristic Extended Properties Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC            0x2901 /**< Characteristic User Description Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG        0x2902 /**< Client Characteristic Configuration Descriptor. */
+#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG        0x2903 /**< Server Characteristic Configuration Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT  0x2904 /**< Characteristic Presentation Format Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT     0x2905 /**< Characteristic Aggregate Format Descriptor. */
+/* GATT specific UUIDs */
+#define BLE_UUID_GATT                                 0x1801 /**< Generic Attribute Profile. */
+#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED  0x2A05 /**< Service Changed Characteristic. */
+/* GAP specific UUIDs */
+#define BLE_UUID_GAP                                  0x1800 /**< Generic Access Profile. */
+#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME       0x2A00 /**< Device Name Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE        0x2A01 /**< Appearance Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_PPF               0x2A02 /**< Peripheral Privacy Flag Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR       0x2A03 /**< Reconnection Address Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_PPCP              0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */
+/** @} */
+
+
+/** @defgroup BLE_UUID_TYPES Types of UUID
+ * @{ */
+#define BLE_UUID_TYPE_UNKNOWN       0x00 /**< Invalid UUID type. */
+#define BLE_UUID_TYPE_BLE           0x01 /**< Bluetooth SIG UUID (16-bit). */
+#define BLE_UUID_TYPE_VENDOR_BEGIN  0x02 /**< Vendor UUID types start at this index (128-bit). */
+/** @} */
+
+
+/** @defgroup BLE_APPEARANCES Bluetooth Appearance values
+ *  @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml
+ * @{ */
+#define BLE_APPEARANCE_UNKNOWN                                0 /**< Unknown. */
+#define BLE_APPEARANCE_GENERIC_PHONE                         64 /**< Generic Phone. */
+#define BLE_APPEARANCE_GENERIC_COMPUTER                     128 /**< Generic Computer. */
+#define BLE_APPEARANCE_GENERIC_WATCH                        192 /**< Generic Watch. */
+#define BLE_APPEARANCE_WATCH_SPORTS_WATCH                   193 /**< Watch: Sports Watch. */
+#define BLE_APPEARANCE_GENERIC_CLOCK                        256 /**< Generic Clock. */
+#define BLE_APPEARANCE_GENERIC_DISPLAY                      320 /**< Generic Display. */
+#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL               384 /**< Generic Remote Control. */
+#define BLE_APPEARANCE_GENERIC_EYE_GLASSES                  448 /**< Generic Eye-glasses. */
+#define BLE_APPEARANCE_GENERIC_TAG                          512 /**< Generic Tag. */
+#define BLE_APPEARANCE_GENERIC_KEYRING                      576 /**< Generic Keyring. */
+#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER                 640 /**< Generic Media Player. */
+#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER              704 /**< Generic Barcode Scanner. */
+#define BLE_APPEARANCE_GENERIC_THERMOMETER                  768 /**< Generic Thermometer. */
+#define BLE_APPEARANCE_THERMOMETER_EAR                      769 /**< Thermometer: Ear. */
+#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR            832 /**< Generic Heart rate Sensor. */
+#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT    833 /**< Heart Rate Sensor: Heart Rate Belt. */
+#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE               896 /**< Generic Blood Pressure. */
+#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM                   897 /**< Blood Pressure: Arm. */
+#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST                 898 /**< Blood Pressure: Wrist. */
+#define BLE_APPEARANCE_GENERIC_HID                          960 /**< Human Interface Device (HID). */
+#define BLE_APPEARANCE_HID_KEYBOARD                         961 /**< Keyboard (HID Subtype). */
+#define BLE_APPEARANCE_HID_MOUSE                            962 /**< Mouse (HID Subtype). */
+#define BLE_APPEARANCE_HID_JOYSTICK                         963 /**< Joystiq (HID Subtype). */
+#define BLE_APPEARANCE_HID_GAMEPAD                          964 /**< Gamepad (HID Subtype). */
+#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE                 965 /**< Digitizer Tablet (HID Subtype). */
+#define BLE_APPEARANCE_HID_CARD_READER                      966 /**< Card Reader (HID Subtype). */
+#define BLE_APPEARANCE_HID_DIGITAL_PEN                      967 /**< Digital Pen (HID Subtype). */
+#define BLE_APPEARANCE_HID_BARCODE                          968 /**< Barcode Scanner (HID Subtype). */
+#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER               1024 /**< Generic Glucose Meter. */
+#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR      1088 /**< Generic Running Walking Sensor. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE      1089 /**< Running Walking Sensor: In-Shoe. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE      1090 /**< Running Walking Sensor: On-Shoe. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP       1091 /**< Running Walking Sensor: On-Hip. */
+#define BLE_APPEARANCE_GENERIC_CYCLING                     1152 /**< Generic Cycling. */
+#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER            1153 /**< Cycling: Cycling Computer. */
+#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR                1154 /**< Cycling: Speed Sensor. */
+#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR              1155 /**< Cycling: Cadence Sensor. */
+#define BLE_APPEARANCE_CYCLING_POWER_SENSOR                1156 /**< Cycling: Power Sensor. */
+#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR        1157 /**< Cycling: Speed and Cadence Sensor. */
+#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER              3136 /**< Generic Pulse Oximeter. */
+#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP            3137 /**< Fingertip (Pulse Oximeter subtype). */
+#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN           3138 /**< Wrist Worn(Pulse Oximeter subtype). */
+#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE                3200 /**< Generic Weight Scale. */
+#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT          5184 /**< Generic Outdoor Sports Activity. */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP         5185 /**< Location Display Device (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD          5187 /**< Location Pod (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD  5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */
+/** @} */
+
+/** @brief Set .type and .uuid fields of ble_uuid_struct to specified uuid value. */
+#define BLE_UUID_BLE_ASSIGN(instance, value) do {\
+            instance.type = BLE_UUID_TYPE_BLE; \
+            instance.uuid = value;} while(0)
+
+/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */
+#define BLE_UUID_COPY_PTR(dst, src) do {\
+            (dst)->type = (src)->type; \
+            (dst)->uuid = (src)->uuid;} while(0)
+
+/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */
+#define BLE_UUID_COPY_INST(dst, src) do {\
+            (dst).type = (src).type; \
+            (dst).uuid = (src).uuid;} while(0)
+
+/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
+#define BLE_UUID_EQ(p_uuid1, p_uuid2) \
+            (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid))
+
+/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
+#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \
+            (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid))
+
+/** @} */
+
+/** @addtogroup BLE_TYPES_STRUCTURES Structures
+ * @{ */
+
+/** @brief 128 bit UUID values. */
+typedef struct
+{
+  uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */
+} ble_uuid128_t;
+
+/** @brief  Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */
+typedef struct
+{
+  uint16_t    uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */
+  uint8_t     type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */
+} ble_uuid_t;
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_BLE_TYPES_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h
new file mode 100644
index 0000000000..e4f90fd54c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error.h
@@ -0,0 +1,90 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+ /**
+  @defgroup nrf_error SoftDevice Global Error Codes
+  @{
+   
+  @brief Global Error definitions
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_H__
+#define NRF_ERROR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions
+ * @{ */
+#define NRF_ERROR_BASE_NUM      (0x0)       ///< Global error base
+#define NRF_ERROR_SDM_BASE_NUM  (0x1000)    ///< SDM error base
+#define NRF_ERROR_SOC_BASE_NUM  (0x2000)    ///< SoC error base
+#define NRF_ERROR_STK_BASE_NUM  (0x3000)    ///< STK error base
+/** @} */
+
+#define NRF_SUCCESS                           (NRF_ERROR_BASE_NUM + 0)  ///< Successful command
+#define NRF_ERROR_SVC_HANDLER_MISSING         (NRF_ERROR_BASE_NUM + 1)  ///< SVC handler is missing
+#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED      (NRF_ERROR_BASE_NUM + 2)  ///< SoftDevice has not been enabled
+#define NRF_ERROR_INTERNAL                    (NRF_ERROR_BASE_NUM + 3)  ///< Internal Error
+#define NRF_ERROR_NO_MEM                      (NRF_ERROR_BASE_NUM + 4)  ///< No Memory for operation
+#define NRF_ERROR_NOT_FOUND                   (NRF_ERROR_BASE_NUM + 5)  ///< Not found
+#define NRF_ERROR_NOT_SUPPORTED               (NRF_ERROR_BASE_NUM + 6)  ///< Not supported
+#define NRF_ERROR_INVALID_PARAM               (NRF_ERROR_BASE_NUM + 7)  ///< Invalid Parameter
+#define NRF_ERROR_INVALID_STATE               (NRF_ERROR_BASE_NUM + 8)  ///< Invalid state, operation disallowed in this state
+#define NRF_ERROR_INVALID_LENGTH              (NRF_ERROR_BASE_NUM + 9)  ///< Invalid Length
+#define NRF_ERROR_INVALID_FLAGS               (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags
+#define NRF_ERROR_INVALID_DATA                (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data
+#define NRF_ERROR_DATA_SIZE                   (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size
+#define NRF_ERROR_TIMEOUT                     (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out
+#define NRF_ERROR_NULL                        (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer
+#define NRF_ERROR_FORBIDDEN                   (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation
+#define NRF_ERROR_INVALID_ADDR                (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address
+#define NRF_ERROR_BUSY                        (NRF_ERROR_BASE_NUM + 17) ///< Busy
+#define NRF_ERROR_CONN_COUNT                  (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded.
+#define NRF_ERROR_RESOURCES                   (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h
new file mode 100644
index 0000000000..575829c7f9
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_sdm.h
@@ -0,0 +1,70 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ /**
+  @addtogroup nrf_sdm_api
+  @{
+  @defgroup nrf_sdm_error SoftDevice Manager Error Codes
+  @{
+
+  @brief Error definitions for the SDM API
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_SDM_H__
+#define NRF_ERROR_SDM_H__
+
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN              (NRF_ERROR_SDM_BASE_NUM + 0)  ///< Unknown lfclk source.
+#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1)  ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts).
+#define NRF_ERROR_SDM_INCORRECT_CLENR0                  (NRF_ERROR_SDM_BASE_NUM + 2)  ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing).
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_SDM_H__
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h
new file mode 100644
index 0000000000..28989ee4e1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_error_soc.h
@@ -0,0 +1,85 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup nrf_soc_api
+  @{
+  @defgroup nrf_soc_error SoC Library Error Codes
+  @{
+     
+  @brief Error definitions for the SoC library
+
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_SOC_H__
+#define NRF_ERROR_SOC_H__
+
+#include "nrf_error.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Mutex Errors */
+#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN                 (NRF_ERROR_SOC_BASE_NUM + 0)  ///< Mutex already taken
+
+/* NVIC errors */
+#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE        (NRF_ERROR_SOC_BASE_NUM + 1)  ///< NVIC interrupt not available
+#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2)  ///< NVIC interrupt priority not allowed
+#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN              (NRF_ERROR_SOC_BASE_NUM + 3)  ///< NVIC should not return
+
+/* Power errors */
+#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN                  (NRF_ERROR_SOC_BASE_NUM + 4)  ///< Power mode unknown
+#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN         (NRF_ERROR_SOC_BASE_NUM + 5)  ///< Power POF threshold unknown
+#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN         (NRF_ERROR_SOC_BASE_NUM + 6)  ///< Power off should not return
+
+/* Rand errors */
+#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES              (NRF_ERROR_SOC_BASE_NUM + 7)  ///< RAND not enough values
+
+/* PPI errors */
+#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL                 (NRF_ERROR_SOC_BASE_NUM + 8)  ///< Invalid PPI Channel
+#define NRF_ERROR_SOC_PPI_INVALID_GROUP                   (NRF_ERROR_SOC_BASE_NUM + 9)  ///< Invalid PPI Group
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_SOC_H__
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h
new file mode 100644
index 0000000000..8b49061c72
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_nvic.h
@@ -0,0 +1,486 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_nvic_api SoftDevice NVIC API
+ * @{
+ *
+ * @note In order to use this module, the following code has to be added to a .c file:
+ *     \code
+ *     nrf_nvic_state_t nrf_nvic_state;
+ *     \endcode
+ *
+ * @note Definitions and declarations starting with __ (double underscore) in this header file are
+ * not intended for direct use by the application.
+ *
+ * @brief APIs for the accessing NVIC when using a SoftDevice.
+ *
+ */
+
+#ifndef NRF_NVIC_H__
+#define NRF_NVIC_H__
+
+#include <stdint.h>
+#include "nrf.h"
+
+#include "nrf_error_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup NRF_NVIC_DEFINES Defines
+ * @{ */
+
+/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions
+ * @{ */
+
+#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */
+
+#ifdef NRF51
+  #define __NRF_NVIC_ISER_COUNT (1) /**< The number of ISER/ICER registers in the NVIC that are used. */
+
+  /**@brief Interrupts used by the SoftDevice. */
+  #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
+        (1U << POWER_CLOCK_IRQn) \
+      | (1U << RADIO_IRQn) \
+      | (1U << RTC0_IRQn) \
+      | (1U << TIMER0_IRQn) \
+      | (1U << RNG_IRQn) \
+      | (1U << ECB_IRQn) \
+      | (1U << CCM_AAR_IRQn) \
+      | (1U << TEMP_IRQn) \
+      | (1U << __NRF_NVIC_NVMC_IRQn) \
+      | (1U << (uint32_t)SWI4_IRQn) \
+      | (1U << (uint32_t)SWI5_IRQn) \
+    ))
+
+  /**@brief Interrupts available for to application. */
+  #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
+#endif
+
+#ifdef NRF52
+  #define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */
+
+  /**@brief Interrupts used by the SoftDevice. */
+  #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
+        (1U << POWER_CLOCK_IRQn) \
+      | (1U << RADIO_IRQn) \
+      | (1U << RTC0_IRQn) \
+      | (1U << TIMER0_IRQn) \
+      | (1U << RNG_IRQn) \
+      | (1U << ECB_IRQn) \
+      | (1U << CCM_AAR_IRQn) \
+      | (1U << TEMP_IRQn) \
+      | (1U << __NRF_NVIC_NVMC_IRQn) \
+      | (1U << (uint32_t)SWI4_EGU4_IRQn) \
+      | (1U << (uint32_t)SWI5_EGU5_IRQn) \
+    ))
+  #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0)
+
+  /**@brief Interrupts available for to application. */
+  #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
+  #define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1)
+#endif
+/**@} */
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_VARIABLES Variables
+ * @{ */
+
+/**@brief Type representing the state struct for the SoftDevice NVIC module. */
+typedef struct
+{
+  uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */
+  uint32_t volatile __cr_flag;                          /**< Non-zero if already in a critical region */
+} nrf_nvic_state_t;
+
+/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an
+ * application source file. */
+extern nrf_nvic_state_t nrf_nvic_state;
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions
+ * @{ */
+
+/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts.
+ *
+ * @retval  The value of PRIMASK prior to disabling the interrupts.
+ */
+static inline int __sd_nvic_irq_disable(void)
+{
+  int pm = __get_PRIMASK();
+  __disable_irq();
+  return pm;
+}
+
+/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts.
+ */
+static inline void __sd_nvic_irq_enable(void)
+{
+  __enable_irq();
+}
+
+/**@brief Checks if IRQn is available to application
+ * @param[in]  IRQn  irq to check
+ *
+ * @retval  1 (true) if the irq to check is available to the application
+ */
+static inline uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn)
+{
+  if (IRQn < 32)
+  {
+    return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0;
+  }
+#ifdef NRF52
+  else if (IRQn < 64)
+  {
+    return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0;
+  }
+#endif
+  else
+  {
+    return 1;
+  }
+}
+
+/**@brief Checks if IRQn is available to application
+ * @param[in]  priority  priority to check
+ *
+ * @retval  1 (true) if the priority to check is available to the application
+ */
+static inline uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority)
+{
+  if(priority >= (1 << __NVIC_PRIO_BITS))
+  {
+    return 0;
+  }
+#ifdef NRF51
+  if(   priority == 0
+     || priority == 2
+     )
+  {
+    return 0;
+  }
+#endif
+#ifdef NRF52
+  if(   priority == 0
+     || priority == 1
+     || priority == 4
+     || priority == 5
+     )
+  {
+    return 0;
+  }
+#endif
+  return 1;
+}
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions
+ * @{ */
+
+/**@brief Enable External Interrupt.
+ * @note Corresponds to NVIC_EnableIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt was enabled.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application.
+ */
+static inline uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+  if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn)))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
+  }
+
+  if (nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));
+  }
+  else
+  {
+    NVIC_EnableIRQ(IRQn);
+  }
+  return NRF_SUCCESS;
+}
+
+/**@brief  Disable External Interrupt.
+ * @note Corresponds to NVIC_DisableIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt was disabled.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
+ */
+static inline uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+
+  if (nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F));
+  }
+  else
+  {
+    NVIC_DisableIRQ(IRQn);
+  }
+
+  return NRF_SUCCESS;
+}
+
+/**@brief  Get Pending Interrupt.
+ * @note Corresponds to NVIC_GetPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in]   IRQn          See the NVIC_GetPendingIRQ documentation in CMSIS.
+ * @param[out]  p_pending_irq Return value from NVIC_GetPendingIRQ.
+ *
+ * @retval ::NRF_SUCCESS The interrupt is available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    *p_pending_irq = NVIC_GetPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief  Set Pending Interrupt.
+ * @note Corresponds to NVIC_SetPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt is set pending.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    NVIC_SetPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief  Clear Pending Interrupt.
+ * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt pending flag is cleared.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    NVIC_ClearPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief Set Interrupt Priority.
+ * @note Corresponds to NVIC_SetPriority in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ * @pre Priority is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn      See the NVIC_SetPriority documentation in CMSIS.
+ * @param[in] priority  A valid IRQ priority for use by the application.
+ *
+ * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application.
+ */
+static inline uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+
+  if (!__sd_nvic_is_app_accessible_priority(priority))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
+  }
+
+  NVIC_SetPriority(IRQn, (uint32_t)priority);
+  return NRF_SUCCESS;
+}
+
+/**@brief Get Interrupt Priority.
+ * @note Corresponds to NVIC_GetPriority in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in]  IRQn         See the NVIC_GetPriority documentation in CMSIS.
+ * @param[out] p_priority   Return value from NVIC_GetPriority.
+ *
+ * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    *p_priority = (NVIC_GetPriority(IRQn) & 0xFF);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief System Reset.
+ * @note Corresponds to NVIC_SystemReset in CMSIS.
+ *
+ * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN
+ */
+static inline uint32_t sd_nvic_SystemReset(void)
+{
+  NVIC_SystemReset();
+  return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN;
+}
+
+/**@brief Enters critical region.
+ *
+ * @post Application interrupts will be disabled.
+ * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each
+ * execution context
+ * @sa sd_nvic_critical_region_exit
+ *
+ * @retval ::NRF_SUCCESS
+ */
+static inline uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)
+{
+  int was_masked = __sd_nvic_irq_disable();
+  if (!nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__cr_flag = 1;
+    nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
+    NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
+    #ifdef NRF52
+    nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 );
+    NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1;
+    #endif
+    *p_is_nested_critical_region = 0;
+  }
+  else
+  {
+    *p_is_nested_critical_region = 1;
+  }
+  if (!was_masked)
+  {
+    __sd_nvic_irq_enable();
+  }
+  return NRF_SUCCESS;
+}
+
+/**@brief Exit critical region.
+ *
+ * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter.
+ * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called.
+ *
+ * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+static inline uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)
+{
+  if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0))
+  {
+    int was_masked = __sd_nvic_irq_disable();
+    NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
+    #ifdef NRF52
+    NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
+    #endif
+    nrf_nvic_state.__cr_flag = 0;
+    if (!was_masked)
+    {
+      __sd_nvic_irq_enable();
+    }
+  }
+
+  return NRF_SUCCESS;
+}
+/**@} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_NVIC_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h
new file mode 100644
index 0000000000..20aef49626
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sd_def.h
@@ -0,0 +1,50 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_SD_DEF_H__
+#define NRF_SD_DEF_H__
+
+#include <stdint.h>
+
+#define SD_PPI_CHANNELS_USED            0xFFF0C000uL /**< PPI channels utilized by SotfDevice (not available to the application). */
+#define SD_PPI_GROUPS_USED              0x0000000CuL /**< PPI groups utilized by SoftDevice (not available to the application). */
+#define SD_TIMERS_USED                  0x00000001uL /**< Timers used by SoftDevice. */
+#define SD_SWI_USED                     0x0000003CuL /**< Software interrupts used by SoftDevice */
+
+#endif /* NRF_SD_DEF_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h
new file mode 100644
index 0000000000..bb370abffe
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_sdm.h
@@ -0,0 +1,274 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @defgroup nrf_sdm_api SoftDevice Manager API
+  @{
+
+  @brief APIs for SoftDevice management.
+
+*/
+
+/* Header guard */
+#ifndef NRF_SDM_H__
+#define NRF_SDM_H__
+
+#include "nrf_svc.h"
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "nrf_error_sdm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_SDM_DEFINES Defines
+ * @{ */
+#ifdef NRFSOC_DOXYGEN
+//Stuff defined elsewere, to satisfy doxygen
+#define MBR_SIZE 0
+#warning test
+#endif
+
+/** @brief SoftDevice Manager SVC Base number. */
+#define SDM_SVC_BASE 0x10
+
+/** @brief Defines the SoftDevice Information Structure location (address) as an offset from
+the start of the softdevice (without MBR)*/
+#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000)
+
+/** @brief Defines the absolute Softdevice information structure location (address)*/
+#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE)
+
+/** @brief Defines the offset for Softdevice size value relative to Softdevice base address*/
+#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08)
+
+/** @brief Defines the offset for FWID value relative to Softdevice base address*/
+#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C)
+
+/** @brief Defines a macro for retreiving the actual Softdevice size value from a given base address
+           use @ref MBR_SIZE when Softdevice is installed just above the MBR (the usual case)*/
+#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET)))
+
+/** @brief Defines a macro for retreiving the actual FWID value from a given base address
+           use @ref MBR_SIZE when Softdevice is installed just above the MBR (the usual case)*/
+#define SD_FWID_GET(baseaddr) ((*((uint32_t *) ((baseaddr) + SD_FWID_OFFSET))) & 0xFFFF)
+
+/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges
+ * @{ */
+#define NRF_FAULT_ID_SD_RANGE_START     0x00000000            /**< SoftDevice ID range start. */
+#define NRF_FAULT_ID_APP_RANGE_START    0x00001000            /**< Application ID range start. */
+/**@} */
+
+/**@defgroup NRF_FAULT_IDS Fault ID types
+ * @{ */
+#define NRF_FAULT_ID_SD_ASSERT    (NRF_FAULT_ID_SD_RANGE_START + 1)           /**< SoftDevice assertion. The info parameter will be set to 0x00000000. */
+#define NRF_FAULT_ID_APP_MEMACC   (NRF_FAULT_ID_APP_RANGE_START + 1)          /**< Application invalid memory access. The info parameter will contain the address in memory that was accessed. */
+/**@} */
+
+/** @} */
+
+/** @addtogroup NRF_SDM_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF SoftDevice Manager API SVC numbers. */
+enum NRF_SD_SVCS
+{
+  SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */
+  SD_SOFTDEVICE_DISABLE,               /**< ::sd_softdevice_disable */
+  SD_SOFTDEVICE_IS_ENABLED,            /**< ::sd_softdevice_is_enabled */
+  SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */
+  SVC_SDM_LAST                         /**< Placeholder for last SDM SVC */
+};
+
+/** @} */
+
+/** @addtogroup NRF_SDM_DEFINES Defines
+ * @{ */
+
+/**@defgroup NRF_CLOCK_LF_XTAL_ACCURACY Clock accuracy * @{ */
+
+#define NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM (0) /* Default */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_500_PPM (1)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_150_PPM (2)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_100_PPM (3)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_75_PPM  (4)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM  (5)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_30_PPM  (6)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM  (7)
+
+/** @} */
+
+/**@defgroup NRF_CLOCK_LF_SRC Possible lfclk oscillator sources * @{ */
+
+#define NRF_CLOCK_LF_SRC_RC      (0)                        /**< LFCLK RC oscillator. */
+#define NRF_CLOCK_LF_SRC_XTAL    (1)                        /**< LFCLK crystal oscillator. */
+#define NRF_CLOCK_LF_SRC_SYNTH   (2)                        /**< LFCLK Synthesized from HFCLK. */
+
+/** @} */
+/** @} */
+
+/** @addtogroup NRF_SDM_TYPES Types
+ * @{ */
+
+/**@brief Type representing lfclk oscillator source. */
+typedef struct
+{
+  uint8_t source;        /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */
+  uint8_t rc_ctiv;      /**< Only for NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second
+                              units (nRF51: 1-64, nRF52: 1-32).
+                              @note To avoid excessive clock drift, 0.5 degrees Celsius is the
+                                    maximum temperature change allowed in one calibration timer
+                                    interval. The interval should be selected to ensure this.
+
+                              @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.  */
+  uint8_t rc_temp_ctiv; /**<  Only for NRF_CLOCK_LF_SRC_RC: How often (in number of calibration
+                              intervals) the RC oscillator shall be calibrated if the temperature
+                              hasn't changed.
+                                  0: Always calibrate even if the temperature hasn't changed.
+                                  1: Only calibrate if the temperature has changed (nRF51 only).
+                                  2-33: Check the temperature and only calibrate if it has changed,
+                                        however calibration will take place every rc_temp_ctiv
+                                        intervals in any case.
+
+                              @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+
+                              @note For nRF52, the application must ensure calibration at least once
+                                    every 8 seconds to ensure +/-250ppm clock stability. The
+                                    recommended configuration for NRF_CLOCK_LF_SRC_RC on nRF52 is
+                                    rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at
+                                    least once every 8 seconds and for temperature changes of 0.5
+                                    degrees Celsius every 4 seconds. See the Product Specification
+                                    for the nRF52 device being used for more information.*/
+  uint8_t xtal_accuracy; /**< External crystal clock accuracy used in the LL to compute timing windows.
+
+                              @note For the NRF_CLOCK_LF_SRC_RC clock source this parameter is ignored. */
+} nrf_clock_lf_cfg_t;
+
+/**@brief Fault Handler type.
+ *
+ * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back.
+ * The protocol stack will be in an undefined state when this happens and the only way to recover will be to
+ * perform a reset, using e.g. CMSIS NVIC_SystemReset().
+ *
+ * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback.
+ *
+ * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc The program counter of the instruction that triggered the fault.
+ * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details.
+ */
+typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info);
+
+/** @} */
+
+/** @addtogroup NRF_SDM_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Enables the SoftDevice and by extension the protocol stack.
+ *
+ * @note Some care must be taken if a low frequency clock source is already running when calling this function:
+ *       If the LF clock has a different source then the one currently running, it will be stopped. Then, the new
+ *       clock source will be started.
+ *
+ * @note This function has no effect when returning with an error.
+ *
+ * @post If return code is ::NRF_SUCCESS
+ *       - SoC library and protocol stack APIs are made available.
+ *       - A portion of RAM will be unavailable (see relevant SDS documentation).
+ *       - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation).
+ *       - Interrupts will not arrive from protected peripherals or interrupts.
+ *       - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice.
+ *       - Interrupt latency may be affected by the SoftDevice  (see relevant SDS documentation).
+ *       - Chosen low frequency clock source will be running.
+ *
+ * @param p_clock_lf_cfg Low frequency clock source and accuracy.
+                         If NULL the clock will be configured as an rc source with rc_ctiv = 16 and .rc_temp_ctiv = 2
+                         In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock.
+ * @param fault_handler Callback to be invoked in case of fault.
+ *
+ * @retval ::NRF_SUCCESS
+ * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated.
+ * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level.
+ * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected.
+ */
+SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler));
+
+
+/**@brief Disables the SoftDevice and by extension the protocol stack.
+ *
+ * Idempotent function to disable the SoftDevice.
+ *
+ * @post SoC library and protocol stack APIs are made unavailable.
+ * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest).
+ * @post All peripherals used by the SoftDevice will be reset to default values.
+ * @post All of RAM become available.
+ * @post All interrupts are forwarded to the application.
+ * @post LFCLK source chosen in ::sd_softdevice_enable will be left running.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void));
+
+/**@brief Check if the SoftDevice is enabled.
+ *
+ * @param[out]  p_softdevice_enabled If the SoftDevice is enabled: 1 else 0.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled));
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice
+ *
+ * This function is only intended to be called when a bootloader is enabled.
+ *
+ * @param[in] address The base address of the interrupt vector table for forwarded interrupts.
+
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_SDM_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h
new file mode 100644
index 0000000000..e1fbb2236a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_soc.h
@@ -0,0 +1,911 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+/**
+ * @defgroup nrf_soc_api SoC Library API
+ * @{
+ * 
+ * @brief APIs for the SoC library.
+ * 
+ */
+
+#ifndef NRF_SOC_H__
+#define NRF_SOC_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_svc.h"
+#include "nrf.h"
+
+#include "nrf_error_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup NRF_SOC_DEFINES Defines
+ * @{ */
+
+/**@brief The number of the lowest SVC number reserved for the SoC library. */
+#define SOC_SVC_BASE               (0x20)
+#define SOC_SVC_BASE_NOT_AVAILABLE (0x2B)
+
+/**@brief Guranteed time for application to process radio inactive notification. */
+#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US  (62)
+
+/**@brief The minimum allowed timeslot extension time. */
+#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200)
+
+#define SOC_ECB_KEY_LENGTH                (16)                       /**< ECB key length. */
+#define SOC_ECB_CLEARTEXT_LENGTH          (16)                       /**< ECB cleartext length. */
+#define SOC_ECB_CIPHERTEXT_LENGTH         (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */
+
+#ifdef NRF51
+#define SD_EVT_IRQn                       (SWI2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SD_EVT_IRQHandler                 (SWI2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
+#define RADIO_NOTIFICATION_IRQn           (SWI1_IRQn)        /**< The radio notification IRQ number. */
+#define RADIO_NOTIFICATION_IRQHandler     (SWI1_IRQHandler)  /**< The radio notification IRQ handler. */
+#endif
+#ifdef NRF52
+#define SD_EVT_IRQn                       (SWI2_EGU2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SD_EVT_IRQHandler                 (SWI2_EGU2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
+#define RADIO_NOTIFICATION_IRQn           (SWI1_EGU1_IRQn)        /**< The radio notification IRQ number. */
+#define RADIO_NOTIFICATION_IRQHandler     (SWI1_EGU1_IRQHandler)  /**< The radio notification IRQ handler. */
+#endif
+
+#define NRF_RADIO_LENGTH_MIN_US           (100)               /**< The shortest allowed radio timeslot, in microseconds. */
+#define NRF_RADIO_LENGTH_MAX_US           (100000)            /**< The longest allowed radio timeslot, in microseconds. */
+
+#define NRF_RADIO_DISTANCE_MAX_US         (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */
+
+#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */
+
+#define NRF_RADIO_START_JITTER_US         (2)                 /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */
+
+/**@} */
+
+/**@addtogroup NRF_SOC_ENUMS Enumerations
+ * @{ */
+
+/**@brief The SVC numbers used by the SVC functions in the SoC library. */
+enum NRF_SOC_SVCS
+{
+  SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE,
+  SD_PPI_CHANNEL_ENABLE_SET,
+  SD_PPI_CHANNEL_ENABLE_CLR,
+  SD_PPI_CHANNEL_ASSIGN,
+  SD_PPI_GROUP_TASK_ENABLE,
+  SD_PPI_GROUP_TASK_DISABLE,
+  SD_PPI_GROUP_ASSIGN,
+  SD_PPI_GROUP_GET,
+  SD_FLASH_PAGE_ERASE,
+  SD_FLASH_WRITE,
+  SD_FLASH_PROTECT,
+  SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE,
+  SD_MUTEX_ACQUIRE,
+  SD_MUTEX_RELEASE,
+  SD_RFU_1,
+  SD_RFU_2,
+  SD_RFU_3,
+  SD_RFU_4,
+  SD_RFU_5,
+  SD_RFU_6,
+  SD_RFU_7,
+  SD_RFU_8,
+  SD_RFU_9,
+  SD_RFU_10,
+  SD_RAND_APPLICATION_POOL_CAPACITY_GET,
+  SD_RAND_APPLICATION_BYTES_AVAILABLE_GET,
+  SD_RAND_APPLICATION_VECTOR_GET,
+  SD_POWER_MODE_SET,
+  SD_POWER_SYSTEM_OFF,
+  SD_POWER_RESET_REASON_GET,
+  SD_POWER_RESET_REASON_CLR,
+  SD_POWER_POF_ENABLE,
+  SD_POWER_POF_THRESHOLD_SET,
+  SD_POWER_RAMON_SET,
+  SD_POWER_RAMON_CLR,
+  SD_POWER_RAMON_GET,
+  SD_POWER_GPREGRET_SET,
+  SD_POWER_GPREGRET_CLR,
+  SD_POWER_GPREGRET_GET,
+  SD_POWER_DCDC_MODE_SET,
+  SD_APP_EVT_WAIT,
+  SD_CLOCK_HFCLK_REQUEST,
+  SD_CLOCK_HFCLK_RELEASE,
+  SD_CLOCK_HFCLK_IS_RUNNING,
+  SD_RADIO_NOTIFICATION_CFG_SET,
+  SD_ECB_BLOCK_ENCRYPT,
+  SD_ECB_BLOCKS_ENCRYPT,
+  SD_RADIO_SESSION_OPEN,
+  SD_RADIO_SESSION_CLOSE,
+  SD_RADIO_REQUEST,
+  SD_EVT_GET,
+  SD_TEMP_GET,
+  SVC_SOC_LAST
+};
+
+/**@brief Possible values of a ::nrf_mutex_t. */
+enum NRF_MUTEX_VALUES
+{
+  NRF_MUTEX_FREE,
+  NRF_MUTEX_TAKEN
+};
+
+/**@brief Power modes. */
+enum NRF_POWER_MODES
+{
+  NRF_POWER_MODE_CONSTLAT,  /**< Constant latency mode. See power management in the reference manual. */
+  NRF_POWER_MODE_LOWPWR     /**< Low power mode. See power management in the reference manual. */
+};
+
+
+/**@brief Power failure thresholds */
+enum NRF_POWER_THRESHOLDS
+{
+  NRF_POWER_THRESHOLD_V21,  /**< 2.1 Volts power failure threshold. */
+  NRF_POWER_THRESHOLD_V23,  /**< 2.3 Volts power failure threshold. */
+  NRF_POWER_THRESHOLD_V25,  /**< 2.5 Volts power failure threshold. */ 
+  NRF_POWER_THRESHOLD_V27   /**< 2.7 Volts power failure threshold. */
+};
+
+
+/**@brief DC/DC converter modes. */
+enum NRF_POWER_DCDC_MODES
+{
+  NRF_POWER_DCDC_DISABLE,          /**< The DCDC is disabled. */
+  NRF_POWER_DCDC_ENABLE            /**< The DCDC is enabled.  */
+};
+
+/**@brief Radio notification distances. */
+enum NRF_RADIO_NOTIFICATION_DISTANCES
+{
+  NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_800US,    /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_1740US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_2680US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_3620US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_4560US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_5500US    /**< The distance from the active notification to start of radio activity. */
+};
+
+
+/**@brief Radio notification types. */
+enum NRF_RADIO_NOTIFICATION_TYPES
+{
+  NRF_RADIO_NOTIFICATION_TYPE_NONE = 0,        /**< The event does not have a radio notification signal. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE,   /**< Using interrupt for notification when the radio will be enabled. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH,     /**< Using interrupt for notification both when the radio will be enabled and disabled. */
+};
+
+/**@brief The Radio signal callback types. */
+enum NRF_RADIO_CALLBACK_SIGNAL_TYPE
+{
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_START,             /**< This signal indicates the start of the radio timeslot. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0,            /**< This signal indicates the NRF_TIMER0 interrupt. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO,             /**< This signal indicates the NRF_RADIO interrupt. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED,     /**< This signal indicates extend action failed. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED   /**< This signal indicates extend action succeeded. */
+};
+
+/**@brief The actions requested by the signal callback.
+ *
+ *  This code gives the SOC instructions about what action to take when the signal callback has
+ *  returned.
+ */
+enum NRF_RADIO_SIGNAL_CALLBACK_ACTION
+{
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE,            /**< Return without action. */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND,          /**< Request an extension of the current timeslot (maximum execution time for this action is when the extension succeeded). */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_END,             /**< End the current radio timeslot. */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END  /**< Request a new radio timeslot and end the current timeslot. */
+};
+
+/**@brief Radio timeslot high frequency clock source configuration. */
+enum NRF_RADIO_HFCLK_CFG
+{
+  NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the
+                                           external crystal for the whole duration of the timeslot. This should be the
+                                           preferred option for events that use the radio or require high timing accuracy. */
+  NRF_RADIO_HFCLK_CFG_NO_GUARANTEE    /**< This configuration allows for earlier and tighter scheduling of timeslots.
+                                           The RC oscillator may be the clock source in part or for the whole duration of the timeslot.
+                                           The RC oscillator's accuracy must therefore be taken into consideration.
+                                           @note If the application will use the radio peripheral in timeslots with this configuration,
+                                           it must make sure that the crystal is running and stable before starting the radio. */
+};
+
+/**@brief Radio timeslot priorities. */
+enum NRF_RADIO_PRIORITY
+{
+  NRF_RADIO_PRIORITY_HIGH,                          /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */
+  NRF_RADIO_PRIORITY_NORMAL,                        /**< Normal (equal priority as the priority of secondary activites of the SoftDevice stack(s)). */
+};
+
+/**@brief Radio timeslot request type. */
+enum NRF_RADIO_REQUEST_TYPE
+{
+  NRF_RADIO_REQ_TYPE_EARLIEST,                      /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */
+  NRF_RADIO_REQ_TYPE_NORMAL                         /**< Normal radio timeslot request. */
+};
+
+/**@brief SoC Events. */
+enum NRF_SOC_EVTS
+{
+  NRF_EVT_HFCLKSTARTED,                         /**< Event indicating that the HFCLK has started. */
+  NRF_EVT_POWER_FAILURE_WARNING,                /**< Event indicating that a power failure warning has occurred. */
+  NRF_EVT_FLASH_OPERATION_SUCCESS,              /**< Event indicating that the ongoing flash operation has completed successfully. */
+  NRF_EVT_FLASH_OPERATION_ERROR,                /**< Event indicating that the ongoing flash operation has timed out with an error. */
+  NRF_EVT_RADIO_BLOCKED,                        /**< Event indicating that a radio timeslot was blocked. */
+  NRF_EVT_RADIO_CANCELED,                       /**< Event indicating that a radio timeslot was canceled by SoftDevice. */
+  NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */
+  NRF_EVT_RADIO_SESSION_IDLE,                   /**< Event indicating that a radio timeslot session is idle. */
+  NRF_EVT_RADIO_SESSION_CLOSED,                 /**< Event indicating that a radio timeslot session is closed. */
+  NRF_EVT_NUMBER_OF_EVTS
+};
+
+/**@} */
+
+
+/**@addtogroup NRF_SOC_STRUCTURES Structures
+ * @{ */
+
+/**@brief Represents a mutex for use with the nrf_mutex functions.
+ * @note Accessing the value directly is not safe, use the mutex functions!
+ */
+typedef volatile uint8_t nrf_mutex_t;
+
+/**@brief Parameters for a request for a timeslot as early as possible. */
+typedef struct
+{
+  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
+  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
+  uint32_t      length_us;                          /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */
+  uint32_t      timeout_us;                         /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */
+} nrf_radio_request_earliest_t;
+
+/**@brief Parameters for a normal radio timeslot request. */
+typedef struct
+{
+  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
+  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
+  uint32_t      distance_us;                        /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */
+  uint32_t      length_us;                          /**< The radio timeslot length (in the range [100..100,000] microseconds). */
+} nrf_radio_request_normal_t;
+
+/**@brief Radio timeslot request parameters. */
+typedef struct
+{
+  uint8_t                         request_type;     /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */
+  union
+  {
+    nrf_radio_request_earliest_t  earliest;         /**< Parameters for requesting a radio timeslot as early as possible. */
+    nrf_radio_request_normal_t    normal;           /**< Parameters for requesting a normal radio timeslot. */
+  } params;
+} nrf_radio_request_t;
+
+/**@brief Return parameters of the radio timeslot signal callback. */
+typedef struct
+{
+  uint8_t               callback_action;            /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */
+  union
+  {
+    struct
+    {
+      nrf_radio_request_t * p_next;                 /**< The request parameters for the next radio timeslot. */
+    } request;                                      /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */
+    struct
+    {
+      uint32_t              length_us;              /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */
+    } extend;                                       /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */
+  } params;
+} nrf_radio_signal_callback_return_param_t;
+
+/**@brief The radio timeslot signal callback type.
+ *
+ * @note In case of invalid return parameters, the radio timeslot will automatically end
+ *       immediately after returning from the signal callback and the
+ *       @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent.
+ * @note The returned struct pointer must remain valid after the signal callback
+ *       function returns. For instance, this means that it must not point to a stack variable.
+ *
+ * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE.
+ *
+ * @return Pointer to structure containing action requested by the application.
+ */
+typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type);
+
+/**@brief AES ECB parameter typedefs */
+typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH];
+typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH];
+typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH];
+
+/**@brief AES ECB data structure */
+typedef struct
+{
+  soc_ecb_key_t        key;            /**< Encryption key. */
+  soc_ecb_cleartext_t  cleartext;      /**< Cleartext data. */
+  soc_ecb_ciphertext_t ciphertext;     /**< Ciphertext data. */
+} nrf_ecb_hal_data_t;
+
+/**@brief AES ECB block. Used to provide multiple blocks in a single call
+          to @ref sd_ecb_blocks_encrypt.*/
+typedef struct
+{
+  soc_ecb_key_t*        p_key;           /**< Pointer to the Encryption key. */
+  soc_ecb_cleartext_t*  p_cleartext;     /**< Pointer to the Cleartext data. */
+  soc_ecb_ciphertext_t* p_ciphertext;    /**< Pointer to the Ciphertext data. */
+} nrf_ecb_hal_data_block_t;
+
+/**@} */
+
+/**@addtogroup NRF_SOC_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Initialize a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to initialize.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex));
+
+/**@brief Attempt to acquire a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to acquire.
+ *
+ * @retval ::NRF_SUCCESS The mutex was successfully acquired.
+ * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired.
+ */
+SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex));
+
+/**@brief Release a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to release.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex));
+
+/**@brief Query the capacity of the application random pool.
+ *
+ * @param[out] p_pool_capacity The capacity of the pool.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity));
+
+/**@brief Get number of random bytes available to the application.
+ *
+ * @param[out] p_bytes_available The number of bytes currently available in the pool.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available));
+
+/**@brief Get random bytes from the application pool.
+ *
+ * @param[out]  p_buff  Pointer to unit8_t buffer for storing the bytes.
+ * @param[in]   length  Number of bytes to take from pool and place in p_buff.
+ *
+ * @retval ::NRF_SUCCESS The requested bytes were written to p_buff.
+ * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available.
+*/
+SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length));
+
+/**@brief Gets the reset reason register. 
+ *
+ * @param[out]  p_reset_reason  Contents of the NRF_POWER->RESETREAS register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason));
+
+/**@brief Clears the bits of the reset reason register. 
+ *
+ * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk));
+
+/**@brief Sets the power mode when in CPU sleep.
+ *
+ * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait
+ *
+ * @retval ::NRF_SUCCESS The power mode was set.
+ * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown.
+ */
+SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode));
+
+/**@brief Puts the chip in System OFF mode. 
+ *
+ * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN
+ */
+SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
+
+/**@brief Enables or disables the power-fail comparator.
+ *
+ * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs.
+ * The event can be retrieved with sd_evt_get();
+ *
+ * @param[in] pof_enable    True if the power-fail comparator should be enabled, false if it should be disabled.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable));
+
+/**@brief Sets the power-fail threshold value.
+ *
+ * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS.
+ *
+ * @retval ::NRF_SUCCESS The power failure threshold was set.
+ * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
+ */
+SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold));
+
+/**@brief Sets bits in the NRF_POWER->RAMON register.
+ *
+ * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon));
+
+/**@brief Clears bits in the NRF_POWER->RAMON register.
+ *
+ * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon));
+
+/**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks.
+ *
+ * @param[out] p_ramon Content of NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon));
+
+/**@brief Set bits in the NRF_POWER->GPREGRET register.
+ *
+ * @param[in] gpregret_msk Bits to be set in the GPREGRET register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk));
+
+/**@brief Clear bits in the NRF_POWER->GPREGRET register.
+ *
+ * @param[in] gpregret_msk Bits to be clear in the GPREGRET register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk));
+
+/**@brief Get contents of the NRF_POWER->GPREGRET register.
+ *
+ * @param[out] p_gpregret Contents of the GPREGRET register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret));
+
+/**@brief Sets the DCDC mode.
+ *
+ * Enable or disable the DCDC peripheral.
+ *
+ * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES.
+ *
+ * @retval ::NRF_SUCCESS
+ * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid.
+ */
+SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode));
+
+/**@brief Request the high frequency crystal oscillator.
+ *
+ * Will start the high frequency crystal oscillator, the startup time of the crystal varies
+ * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started.
+ *
+ * @see sd_clock_hfclk_is_running
+ * @see sd_clock_hfclk_release
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void));
+
+/**@brief Releases the high frequency crystal oscillator.
+ *
+ * Will stop the high frequency crystal oscillator, this happens immediately.
+ *
+ * @see sd_clock_hfclk_is_running
+ * @see sd_clock_hfclk_request
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void));
+
+/**@brief Checks if the high frequency crystal oscillator is running.
+ *
+ * @see sd_clock_hfclk_request
+ * @see sd_clock_hfclk_release
+ *
+ * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running));
+
+/**@brief Waits for an application event.
+ * 
+ * An application event is either an application interrupt or a pended interrupt when the
+ * interrupt is disabled. When the interrupt is enabled it will be taken immediately since
+ * this function will wait in thread mode, then the execution will return in the application's
+ * main thread. When an interrupt is disabled and gets pended it will return to the application's 
+ * thread main. The application must ensure that the pended flag is cleared using 
+ * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for
+ * disabled interrupts, as the interrupt handler will clear the pending flag automatically for
+ * enabled interrupts.
+ *
+ * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0
+ * System Control Register (SCR). @sa CMSIS_SCB
+ *
+ * @note If an application interrupt has happened since the last time sd_app_evt_wait was
+ *       called this function will return immediately and not go to sleep. This is to avoid race
+ *       conditions that can occur when a flag is updated in the interrupt handler and processed
+ *       in the main loop.
+ *
+ * @post An application interrupt has happened or a interrupt pending flag is set.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void));
+
+/**@brief Get PPI channel enable register contents.
+ *
+ * @param[out] p_channel_enable The contents of the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable));
+
+/**@brief Set PPI channel enable register.
+ *
+ * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk));
+
+/**@brief Clear PPI channel enable register.
+ *
+ * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk));
+
+/**@brief Assign endpoints to a PPI channel.
+ *
+ * @param[in] channel_num Number of the PPI channel to assign.
+ * @param[in] evt_endpoint Event endpoint of the PPI channel.
+ * @param[in] task_endpoint Task endpoint of the PPI channel.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint));
+
+/**@brief Task to enable a channel group.
+ *
+ * @param[in] group_num Number of the channel group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num));
+
+/**@brief Task to disable a channel group.
+ *
+ * @param[in] group_num Number of the PPI group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num));
+
+/**@brief Assign PPI channels to a channel group.
+ *
+ * @param[in] group_num Number of the channel group.
+ * @param[in] channel_msk Mask of the channels to assign to the group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk));
+
+/**@brief Gets the PPI channels of a channel group.
+ *
+ * @param[in]   group_num Number of the channel group.
+ * @param[out]  p_channel_msk Mask of the channels assigned to the group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk));
+
+/**@brief Configures the Radio Notification signal.
+ *
+ * @note
+ *      - The notification signal latency depends on the interrupt priority settings of SWI used
+ *        for notification signal.
+ *      - To ensure that the radio notification signal behaves in a consistent way, always 
+ *        configure radio notifications when there is no protocol stack or other SoftDevice 
+ *        activity in progress. It is recommended that the radio notification signal is 
+ *        configured directly after the SoftDevice has been enabled.
+ *      - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice
+ *        will interrupt the application to do Radio Event preparation.
+ *      - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have
+ *        to shorten the connection events to have time for the Radio Notification signals.
+ *
+ * @param[in]  type      Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES.
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio
+ *                       notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is
+ *                       recommended (but not required) to be used with
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE.
+ *
+ * @param[in]  distance  Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES.
+ *                       This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or 
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. 
+ *
+ * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance));
+
+/**@brief Encrypts a block according to the specified parameters.
+ *
+ * 128-bit AES encryption.
+ *
+ * @note:
+ *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
+ *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
+ *      main or low interrupt level.
+ *
+ * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input
+ *                            parameters and one output parameter).
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data));
+
+/**@brief Encrypts multiple data blocks provided as an array of data block structures.
+ *
+ * @details: Performs 128-bit AES encryption on multiple data blocks
+ *
+ * @note:
+ *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
+ *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
+ *      main or low interrupt level.
+ *
+ * @param[in]     block_count     Count of blocks in the p_data_blocks array.
+ * @param[in,out] p_data_blocks   Pointer to the first entry in a contiguous array of
+ *                                @ref nrf_ecb_hal_data_block_t structures.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks));
+
+/**@brief Gets any pending events generated by the SoC API.
+ *
+ * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned.
+ *
+ * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending.
+ *
+ * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter.
+ * @retval ::NRF_ERROR_NOT_FOUND No pending events. 
+ */
+SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id));
+
+/**@brief Get the temperature measured on the chip
+ * 
+ * This function will block until the temperature measurement is done.
+ * It takes around 50us from call to return.
+ *
+ * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius.
+ *
+ * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp
+ */
+SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp));
+
+/**@brief Flash Write
+*
+* Commands to write a buffer to flash
+*
+* If the SoftDevice is enabled:
+*  This call initiates the flash access command, and its completion will be communicated to the
+*  application with exactly one of the following events:
+*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
+*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
+*
+* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the 
+ * write has been completed
+*
+* @note
+*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
+*        they will not interfere with the flash access. This means that all interrupts will be blocked
+*        for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
+*        and the command parameters).
+*
+*
+* @param[in]  p_dst Pointer to start of flash location to be written.
+* @param[in]  p_src Pointer to buffer with data to be written.
+* @param[in]  size  Number of 32-bit words to write. Maximum size is 256 32-bit words for nRF51 and 1024 for nRF52.
+*
+* @retval ::NRF_ERROR_INVALID_ADDR   Tried to write to a non existing flash address, or p_dst or p_src was unaligned.
+* @retval ::NRF_ERROR_BUSY           The previous command has not yet completed.
+* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size.
+* @retval ::NRF_ERROR_FORBIDDEN      Tried to write to or read from protected location.
+* @retval ::NRF_SUCCESS              The command was accepted.
+*/
+SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size));
+
+
+/**@brief Flash Erase page
+*
+* Commands to erase a flash page
+* If the SoftDevice is enabled:
+*  This call initiates the flash access command, and its completion will be communicated to the
+*  application with exactly one of the following events:
+*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
+*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
+*
+* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the 
+* erase has been completed
+*
+* @note
+*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
+*        they will not interfere with the flash access. This means that all interrupts will be blocked
+*        for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
+*        and the command parameters).
+*
+*
+* @param[in]  page_number Pagenumber of the page to erase
+* @retval ::NRF_ERROR_INTERNAL      If a new session could not be opened due to an internal error.
+* @retval ::NRF_ERROR_INVALID_ADDR  Tried to erase to a non existing flash page.
+* @retval ::NRF_ERROR_BUSY          The previous command has not yet completed.
+* @retval ::NRF_ERROR_FORBIDDEN     Tried to erase a protected page.
+* @retval ::NRF_SUCCESS             The command was accepted.
+*/
+SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number));
+
+
+/**@brief Flash Protection set
+ *
+ * Commands to set the flash protection configuration registers.
+   On nRF51 this sets the PROTENSETx registers of the MPU peripheral.
+   On nRF52 this sets the CONFIGx registers of the BPROT peripheral.
+ *
+ * @note To read the values read them directly. They are only write-protected.
+ *
+ * @param[in]  block_cfg0 Value to be written to the configuration register.
+ * @param[in]  block_cfg1 Value to be written to the configuration register.
+ * @param[in]  block_cfg2 Value to be written to the configuration register (ignored on nRF51).
+ * @param[in]  block_cfg3 Value to be written to the configuration register (ignored on nRF51).
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice.
+ * @retval ::NRF_SUCCESS Values successfully written to configuration registers.
+ */
+SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t block_cfg0, uint32_t block_cfg1, uint32_t block_cfg2, uint32_t block_cfg3));
+
+/**@brief Opens a session for radio timeslot requests.
+ *
+ * @note Only one session can be open at a time.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot
+ *       starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed
+ *       by the application.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0
+ *       interrupt occurs.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO
+ *       interrupt occurs.
+ * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This
+ *       implies that none of the sd_* API calls can be used from p_radio_signal_callback().
+ *
+ * @param[in] p_radio_signal_callback The signal callback.
+ *
+ * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer.
+ * @retval ::NRF_ERROR_BUSY If session cannot be opened.
+ * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback));
+
+/**@brief Closes a session for radio timeslot requests.
+ *
+ * @note Any current radio timeslot will be finished before the session is closed.
+ * @note If a radio timeslot is scheduled when the session is closed, it will be canceled.
+ * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED
+ *       event is received.
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN If session not opened.
+ * @retval ::NRF_ERROR_BUSY If session is currently being closed.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void));
+
+/**@brief Requests a radio timeslot.
+ *
+ * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST
+ *       and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST.
+ * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by
+ *       p_request->distance_us and is given relative to the start of the previous timeslot. 
+ * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
+ * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
+ * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths.
+ * @note If an opportunity for the first radio timeslot is not found before 100ms after the call to this
+ *       function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent.
+ *       The application may then try to schedule the first radio timeslot again.
+ * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START).
+ *       Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS.
+ * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us.
+ * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the
+ *       specified radio timeslot start, but this does not affect the actual start time of the timeslot.
+ * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency
+ *       (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is 
+ *       guaranteed to be clocked from the external crystal.
+ * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral
+ *       during the radio timeslot.
+ *
+ * @param[in] p_request Pointer to the request parameters.
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE.
+ * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid.
+ * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t * p_request ));
+
+/**@} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_SOC_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h
new file mode 100644
index 0000000000..aa91e5d35e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/headers/nrf_svc.h
@@ -0,0 +1,91 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_SVC__
+#define NRF_SVC__
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SVCALL_AS_NORMAL_FUNCTION
+#define SVCALL(number, return_type, signature) return_type signature
+#else
+
+#ifndef SVCALL
+#if defined (__CC_ARM)
+#define SVCALL(number, return_type, signature) return_type __svc(number) signature
+#elif defined (__GNUC__)
+#ifdef __cplusplus
+#define GCC_CAST_CPP (uint16_t)
+#else
+#define GCC_CAST_CPP
+#endif
+#define SVCALL(number, return_type, signature)          \
+  _Pragma("GCC diagnostic push")                        \
+  _Pragma("GCC diagnostic ignored \"-Wreturn-type\"")   \
+  __attribute__((naked))                                \
+  __attribute__((unused))                               \
+  static return_type signature                          \
+  {                                                     \
+    __asm(                                              \
+        "svc %0\n"                                      \
+        "bx r14" : : "I" (GCC_CAST_CPP number) : "r0"   \
+    );                                                  \
+  }                                                     \
+  _Pragma("GCC diagnostic pop")
+
+#elif defined (__ICCARM__)
+#define PRAGMA(x) _Pragma(#x)
+#define SVCALL(number, return_type, signature)          \
+PRAGMA(swi_number = (number))                           \
+ __swi return_type signature;
+#else
+#define SVCALL(number, return_type, signature) return_type signature
+#endif
+#endif  // SVCALL
+
+#endif  // SVCALL_AS_NORMAL_FUNCTION
+
+#ifdef __cplusplus
+}
+#endif
+#endif  // NRF_SVC__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex
new file mode 100644
index 0000000000..4cfda4eec1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/sdk/softdevice/s130/hex/s130_nrf51_2.0.0_softdevice.hex
@@ -0,0 +1,6783 @@
+:020000040000FA
+:10000000C0070000D1060000D1000000B1060000CA
+:1000100000000000000000000000000000000000E0
+:100020000000000000000000000000005107000078
+:100030000000000000000000DB000000E500000000
+:10004000EF000000F9000000030100000D010000B6
+:1000500017010000210100002B0100003501000004
+:100060003F01000049010000530100005D01000054
+:1000700067010000710100007B01000085010000A4
+:100080008F01000099010000A3010000AD010000F4
+:10009000B7010000C1010000CB010000D501000044
+:1000A000DF010000E9010000F3010000FD01000094
+:1000B00007020000110200001B02000025020000E0
+:1000C0001FB5C046C04600F0EFFA04B00FB41FBD24
+:1000D00008205A49096809580847382057490968CB
+:1000E000095808473C2055490968095808474020E5
+:1000F0005249096809580847442050490968095875
+:10010000084748204D490968095808474C204B4981
+:10011000096809580847502048490968095808479C
+:100120005420464909680958084758204349096836
+:10013000095808475C204149096809580847602068
+:100140003E4909680958084764203C49096809582C
+:100150000847682039490968095808476C20374919
+:100160000968095808477020344909680958084740
+:100170007420324909680958084778202F490968CE
+:10018000095808477C202D490968095808478020EC
+:100190002A490968095808478420284909680958E4
+:1001A0000847882025490968095808478C202349B1
+:1001B00009680958084790202049096809580847E4
+:1001C00094201E4909680958084798201B49096866
+:1001D000095808479C201949096809580847A02070
+:1001E0001649096809580847A4201449096809589C
+:1001F0000847A8201149096809580847AC200F4949
+:10020000096809580847B0200C4909680958084787
+:10021000B4200A49096809580847B82007490968FD
+:1002200009580847BC2005490968095808470000D3
+:1002300003480449024A034B7047000000000020B5
+:10024000C0070000C00700000122D84B5A6000BF61
+:10025000D74A1268002AFBD0016000BFD44A126856
+:10026000002AFBD00022D14B5A6000BFD04A12684E
+:10027000002AFBD07047F0B505460E46174600240D
+:1002800006E0A200B158A2005019FFF7DDFF641C80
+:10029000BC42F6D30020F0BD0120C043C549086030
+:1002A000401048607047014601229204086890425D
+:1002B00001D9102070470020FCE7F0B505460C4638
+:1002C0001646002706E028462168FFF7BDFF2D1DD2
+:1002D000241D7F1CB742F6D3F0BD70B505460C4611
+:1002E0002E460BE0304600F075F9FF2C01D80024B3
+:1002F00001E0FF3C013C012080023618002CF1D1C6
+:1003000070BD0146012212044868904201D90920BB
+:100310007047A9484069401C01D10F20F8E7002030
+:10032000F6E7FEB504462068030000F037FA05043E
+:100330002B4249598B00201DFFF7E3FF0546002D96
+:1003400001D02846FEBDFFF7A7FF0120C00200F044
+:1003500041F9042221469948FFF78DFF002801D07A
+:100360000320EFE708222146944800F06DF90028A9
+:1003700006D1002192480068FFF766FF00F00CF9F3
+:100380000320DFE7A768E6686068019031463846D9
+:10039000FFF7A3FF324638460199FFF78EFFB20000
+:1003A0003846019900F050F9002800D1CAE703202F
+:1003B000C8E700F0E3F9834800688349086041E03A
+:1003C00060680190E668A0680090B200009901980A
+:1003D00000F03AF90746002F00D1B3E70E20B1E74D
+:1003E000201DFFF760FF0546002D01D02846A9E734
+:1003F0006068002807D1FFF74FFF0320800200F05C
+:10040000E9F800F0C9F8FFF747FF0120C00200F04B
+:10041000E1F8042221466948FFF72DFF002801D0AA
+:1004200003208FE708222146644800F00DF90028D8
+:1004300006D1002162480068FFF706FF00F0ACF823
+:1004400003207FE700BF00207CE770B505460C461F
+:10045000182D04D12068FFF764FF206002E001201E
+:10046000206000BF00BF70BDF0B589B05248406940
+:1004700003905248806881000398081802900398FE
+:10048000000B01900121090302984018401E000B47
+:1004900000900124002520462946019A00F0C4F866
+:1004A0000022401E91410791069001260027304608
+:1004B0003946009A00F0B8F80022401E914105919B
+:1004C0000490049BDB43059AD2430698184307998E
+:1004D00011430791069037490698086007984860CD
+:1004E00009B0F0BD70B53448446934488568466841
+:1004F000AA003146204600F0A7F8002801D00020CD
+:1005000070BD0120FCE72D484068002801D0012083
+:1005100000E000200546FFF7E5FF002807D0FFF7C1
+:10052000BBFE0320800200F055F800F035F8FFF71D
+:100530009BFF002D0ED020484669204884684768FC
+:1005400021463046FFF7C9FE224639463046FFF7BE
+:10055000B4FE00BF00F020F810B5184844681A48EF
+:100560000460204600F0DCF810BD15480068006803
+:10057000401C01D100BFFEE710480068002802D0EF
+:10058000042806D101E0FFF7BEFFFFF7E5FF00BF3B
+:10059000FEE700BF00BFFEE7BFF34F8F0B480C49DB
+:1005A000C860BFF34F8F00BFFEE7000000E50140C9
+:1005B00000E40140000600400010001000080000A8
+:1005C000B8070000BC070000000000200400FA0586
+:1005D00000ED00E010B50146104B1A6808460223F2
+:1005E0000F4C636000BF0F4B1B68002BFBD0531CEC
+:1005F00004D0904202D20A4B186101E0084B986087
+:1006000000BF084B1B68002BFBD00023044C636029
+:1006100000BF044B1B68002BFBD010BD0010001066
+:1006200000E5014000E4014010B5202A04DB01464A
+:10063000203A9140002010BD914020239C1A03468F
+:10064000E3401943904010BD034610B50B439B0790
+:100650000FD1042A0DD308C810C9121FA342F8D025
+:1006600018BA21BA884201D9012010BD0020C04328
+:1006700010BD002A03D0D30703D0521C07E000208E
+:1006800010BD03780C78401C491C1B1B07D1037854
+:100690000C78401C491C1B1B01D1921EF1D118463D
+:1006A00010BD70477047704710B500F007F810BDD7
+:1006B000014B1B68DB6818470000002019481A49E5
+:1006C0007047FFF7FBFFFFF7FBFC00BD20BFFDE716
+:1006D0001649174C24688C420BD1164B1B68994263
+:1006E0000CD1154B154A1360186810498842EDD09B
+:1006F0000AE0134880F30888124B18470F4A13602A
+:1007000018680A498842E1D080F308880E49884277
+:1007100004DD0E48026802210A4302605B68184744
+:100720000346DFE7C0070000C0070000FFFFFFFF30
+:10073000000C000014100010001000000000002049
+:10074000000400206B05000000200020240500406C
+:100750000D48704502D1EFF3098101E0EFF3088104
+:10076000886902380078182802D1C046074A104725
+:10077000074A12682C3212681047000000B5054B7A
+:10078000054A9B58984700BDFDFFFFFF4B04000042
+:1007900000000020001000000400000030B4744687
+:1007A000641E2578641CAB4204D3635D5B00E318D0
+:1007B00030BC18471D46F8E7000C00000010000090
+:101000007811002045A90100752F000095A8010066
+:1010100000000000000000000000000000000000D0
+:10102000000000000000000000000000B1A9010065
+:101030000000000000000000752F0000752F000068
+:1010400019AA01001FAA0100752F0000752F0000CA
+:10105000752F0000752F0000752F0000752F000000
+:1010600025AA0100752F0000752F00002BAA010092
+:10107000752F000031AA010037AA01003DAA010026
+:10108000752F0000752F0000752F0000752F0000D0
+:10109000752F0000752F0000752F0000752F0000C0
+:1010A00043AA010049AA0100752F0000752F000016
+:1010B000752F0000752F0000752F0000752F0000A0
+:1010C00000F002F819F01FFC0CA030C808382418F2
+:1010D0002D18A246671EAB4654465D46AC4201D170
+:1010E00019F011FC7E460F3E0FCCB6460126334266
+:1010F00000D0FB1AA246AB4633431847B49E01000A
+:10110000D49E01000023002400250026103A01D3BC
+:1011100078C1FBD8520700D330C100D50B607047AF
+:101120001FB5C046C04619F08BFB04B00FB41FBDFD
+:1011300082690249816102481044704745110000EC
+:101140000100000001B41EB400B510F096F901B41E
+:101150000198864601BC01B01EBD0000F0B44046B7
+:10116000494652465B460FB402A0013001B506481D
+:10117000004700BF01BC86460FBC804689469246A8
+:101180009B46F0BC70470000C110000070B50546DA
+:101190000C46164602E00FCC0FC5103E102EFAD2B8
+:1011A000082E02D303CC03C5083E042E07D301CC7E
+:1011B00001C5361F03E021782970641C6D1C761E62
+:1011C000F9D270BD70B505461A4C08202070A01CDD
+:1011D00000F083F85920A0802946204606F07FFCC5
+:1011E00070BD10B506F088FC12490020891E0870F9
+:1011F00010BD70B50C460F49891E0978002905D02D
+:1012000001466039532905D301200EE0602801D042
+:1012100009480AE0094E211D80008019FF380EC9D7
+:101220008138256806682846B047206070BD0120D7
+:10123000704700000A00002001300000FCAA0100F5
+:101240008307FF22DB0E9A408907090E9940002888
+:101250000BDA0007000F0838830827489B0018188E
+:10126000C36993430B43C3617047830823489B00C2
+:101270001B181868904308431860704710B504465F
+:1012800000210120FFF7DCFF00211820FFF7D8FF25
+:1012900000210B20FFF7D4FF02211920FFF7D0FF18
+:1012A00002210D20FFF7CCFF02210E20FFF7C8FF1F
+:1012B00002210F20FFF7C4FF0221C81FFFF7C0FF64
+:1012C00003211620FFF7BCFF03211520FFF7B8FF0D
+:1012D0002046FFF777FF002010BD80210180704776
+:1012E00010B5FFF77EFF10BD0548704710B5FFF73A
+:1012F00080FF10BD7047704700ED00E000E400E0A3
+:1013000003F9004330B5FD4D044610280AD0112CD6
+:1013100006D028468178122C06D0132C08D0FFDF87
+:10132000AC7030BDFFDFFBE71129F9D0FFDFF7E735
+:101330001129F5D0FFDFF3E770B50EF010FA04467F
+:101340000FF05BFE201AC4B206200CF0EFFB05463E
+:1013500006200CF0F3FB2E1A07200CF0E7FB0546E5
+:1013600007200CF0EBFB281AE44932188878122881
+:101370000DD00023D21813280BD0002012180878A3
+:10138000022808D000201018201AC0B270BD012316
+:10139000F0E70120F2E70120F5E710B5D74994B056
+:1013A000C878002815D017206A46107000A80622B9
+:1013B0000230091D19F0D3F809A968460AF064F94A
+:1013C0000446112802D0002C00D0FFDF204614B0C4
+:1013D00010BD3220E8E710B502210CF0F9FB10BD7A
+:1013E000FFB595B01D460E460746FFF7F4FF040013
+:1013F0000AD02078222804D3A07F8006C00FA842FC
+:1014000004D1082019B0F0BDBD48FBE7372168467C
+:1014100001704780002D05D0012101714671179997
+:10142000817102E000206946087109A968460AF046
+:101430002BF9A07FDF21084069010843A077002035
+:10144000E0E730B50446084620380D46030019F0A1
+:1014500047FB0A06080D1D2429363B40454AFFDF9D
+:1014600042E0207820283FD1FFDF3DE0A34801780B
+:10147000032939D08078132836D02078242833D017
+:10148000252831D023282FD0FFDF2DE020782228F7
+:101490002AD0232828D8FFDF26E02078222823D04E
+:1014A000FFDF21E0207822281ED024281CD0262807
+:1014B0001AD0272818D0292816D0FFDF14E020786A
+:1014C000252811D0FFDF0FE0207825280CD0FFDF82
+:1014D0000AE02078252807D0FFDF05E020782828BB
+:1014E00002D0FFDF00E0FFDF257030BD30B5854C56
+:1014F0000B88854A022801D0934204D09D1FA54243
+:1015000025D2022802D04D88954203D04D88AD1FC8
+:10151000A5421CD24C88A34219D88B88FF25F435EC
+:10152000AB4214D8022802D0C888904205D0C8889F
+:10153000744D0A382D1FA84209D2C888904208D09D
+:10154000944206D05B1C63438000834201DB07208A
+:1015500030BD002030BD70B5044610F0BDF9002844
+:1015600033D12079002806D0082802D8217B082909
+:1015700005D9072070BD217B0029FAD0F6E70028A5
+:1015800004D0206810F0A8F900281ED1207B002884
+:1015900004D0A06810F0A0F9002816D1002508E0BA
+:1015A0002068A900405810F097F900280DD16D1C53
+:1015B000EDB22079A842F3D800250AE0A068A9007E
+:1015C000405810F089F9002801D0102070BD6D1C22
+:1015D000EDB2207BA842F1D8002070BD10B5028981
+:1015E0004A4B111F994213D24189042910D3DB1CA5
+:1015F00099420DD891420BD80178890706D54068E9
+:10160000002803D0FFF7A7FF002800D1002010BD5D
+:10161000072010BDFFB50022099B002802D0994287
+:1016200005D858E0002902D1002004B0F0BD0920FF
+:10163000FBE7845C002C12D087187D78112D43D0F5
+:1016400010DC2B0019F04CFA0A401726262C2C2E01
+:101650002E363640835C002B30D1521CD2B28A42E7
+:10166000F8D3E1E71D2D2FDA123D2B0019F038FADF
+:10167000042C2C121A2C022CD9D1BB78039C072BDA
+:10168000237001D25B0701D40A20CEE7029B01241C
+:101690001B7816E0E343DB0708E0012C08D013E0D9
+:1016A0000620C2E70F2523072D075B19002BF4D076
+:1016B0003046BAE7029B1B789C0701D50B20B4E7A4
+:1016C00002242343029C2370835C521C9A18D2B2DA
+:1016D0008A4202D9ABE7192676028A42A9D3A3E748
+:1016E00010B504780B46002C14D00121084A012CB7
+:1016F00013D0022C17D0032C1FD11AE0A801002010
+:10170000023000007B0C0000FFFF0000FD3F0000E6
+:10171000023200000021197011E0197081798909E5
+:1017200003290AD10BE0197081798909012904D1B3
+:1017300005E019708179890901D0104610BD411C5E
+:101740000622581C18F00BFF002010BD08B51346E8
+:10175000002806D0F6A00068009048796A46800903
+:10176000105C18700622581C18F0F9FE08BD30B540
+:101770000C46097895B0222902D2082015B030BD58
+:10178000282369460B704880132A03D03B2A01D0D6
+:101790000720F3E708460A7109A909F075FF05005B
+:1017A00003D121212046FFF74CFE2846E6E700B58D
+:1017B00095B0232369460B70488010888880508834
+:1017C000C880D08848819088088100208881C8819D
+:1017D00009A9684609F058FF15B000BD70B50E465E
+:1017E000050003D00021092010F037F80120D14C6A
+:1017F000022EE0701BD0032E00D0FFDF0621201D3B
+:101800000FF07CFD607A8006800E6072FFF7C5FDE8
+:10181000608A00280AD0002D08D083000122002110
+:1018200009200FF08BFF092800D0FFDF70BD0321D6
+:10183000E01D0FF063FD607A40218006800E0843B2
+:101840006072E01C02F0E7FCE0E7F0B585B0022131
+:101850006846B84E0171F18AC18000275AE001A89C
+:101860000CF01EF9050007D0F08A002858D000209F
+:10187000F0826946C8804BE0039C2078212847D03D
+:10188000A07F01072FD520462330009068462346CD
+:10189000A28E00892146363301F051FD050003D0A8
+:1018A00011282ED0FFDF2CE0A07FF7210840A07781
+:1018B000E17F480849074000C90F0843FD21014066
+:1018C0000007C00F400001432046E17720304178F7
+:1018D000C906C90E01702078282823D12921204665
+:1018E000FFF7AFFD1EE0400712D56846224600898B
+:1018F00021460E32FFF75BFF050004D0112800D00F
+:10190000FFDF00250EE0A07FFB210840A07709E063
+:101910007F1CFFB202200CF009F9401CB8429ED88F
+:10192000052D07D06846C088F082052D04D02846D2
+:1019300005B0F0BD0020F0820020F9E7FEB50400FC
+:1019400000D1FFDF72202070606808250178794E91
+:10195000091F0B0019F0C4F811F10A0B4EF00B0C23
+:10196000F0F0350B0B0B0BF172F10B00FFDFFEBD3E
+:1019700080880090FFF72FFD070000D1FFDF60781F
+:10198000042128436070307D08433075212138469A
+:10199000FFF757FD009806F0B5FE009803F016FD1E
+:1019A000009804F03BFD022000990FF056FFB87F2D
+:1019B000EF210840B877FFF748FF0028D7D0FFDFB6
+:1019C000FEBD86883046FFF706FD002800D1FFDF08
+:1019D00060688078012800D0FFDF60688179304638
+:1019E00007F017F80028EBD061782943617061682F
+:1019F000C880FEBD87883846FFF7EDFC060000D1A1
+:101A0000FFDF60783946284360706068C0883081A5
+:101A100060680089708160684089B08102200FF0A1
+:101A20001CFF0020B075B07F8007800F0228E0D136
+:101A3000FFF70BFF0028DCD0FFDFFEBD80783C28DD
+:101A400003D0002702280ED000E0012700210091DA
+:101A5000002804D03C2802D0022800D0FFDF0098E4
+:101A6000002802D078E00121F1E760782843607017
+:101A7000307D28433075002F62D16068022187884D
+:101A8000009738460CF09CF80546032138460CF0C8
+:101A900097F80290052138460CF092F80190042145
+:101AA00038460CF08DF80746002D00D1FFDF029874
+:101AB000002800D1FFDF0198002800D1FFDF002FB0
+:101AC00000D1FFDF22212846FFF7BBFC6068807948
+:101AD000012833D00227A87F0622800880003843DF
+:101AE000A8776068C08A28816068008B6881606818
+:101AF000408BA8816068C079E87561682846183015
+:101B0000083118F02CFD60680622807B68706168DF
+:101B1000A81C0F3118F023FDA87F8107890F0098BA
+:101B200006F0DFFD012F0BD0022F15D0FFDFFEBD29
+:101B30000302FF01A80100201AE01DE00127CAE707
+:101B40003078032800D0FFDF002108460FF085FE23
+:101B5000012000F065FFEAE7B078132800D0FFDF2E
+:101B6000002107200FF079FE1120FFF7CBFBDEE705
+:101B7000204601F0DFFEDAE7607828436070D6E7A0
+:101B8000F7B505460078002700090C463E460128B7
+:101B90007ED0F84902287CD007280AD00A2879D0BC
+:101BA000FFDF0298002C068001D02780668000208D
+:101BB000BDE768682246037808320D2B3DD006DC6D
+:101BC000042B68D0072B41D00A2B63D106E0122BDF
+:101BD00043D0132B4BD0142BF7D1C8E01127092683
+:101BE000002C7DD08088A0806968FB2389792172D0
+:101BF000E14905460A7D1A400A7504210BF0F9FFF8
+:101C0000052128460BF0F5FF002128460BF0F1FFD7
+:101C1000012128460BF0EDFF032128460BF0E9FFD8
+:101C2000022128460BF0E5FF062128460BF0E1FFD4
+:101C3000072128460BF0DDFFB3E701270926002C1A
+:101C4000CFD08088A080686880790EE012271026A7
+:101C50008088214600F007FFA3E71C270926002CF7
+:101C6000BFD04088A08068680079207299E78178A9
+:101C70003C2941D010272026002CB2D08088A0809B
+:101C80006868C08A60836868C08A2083686803E0E7
+:101C90007EE0A7E0CBE03AE0008BA0836868408B51
+:101CA000E0836968E07D497F4008C9074000C90FAB
+:101CB0000843E0756968C007497FC00F49084900BB
+:101CC0000843E0756968C8790831FFF73FFD696826
+:101CD000224608460F308B7B01460F32184600E043
+:101CE0007FE0FFF733FD68688079002802D001208B
+:101CF000A07507E00220FBE71B270926002C70D007
+:101D0000002020729C48F722017D11407DE01D27B4
+:101D10003026002C65D0A18069680879491DFFF73D
+:101D200015FD68682030C07AE0736868C0780428C0
+:101D3000207C19D0400840002074F92108406968CF
+:101D40001F22C9788907490F084320746968400732
+:101D5000C97A400FC90008432074696820461130D1
+:101D60000C3118F0FCFB1CE701210843E4E72027B5
+:101D70001026002C63D0A18068682246407A207229
+:101D800069680932CB1C88781946FFF7DFFC08E741
+:101D9000287E012803D0022813D0FFDF01E71F2788
+:101DA0001026002C4BD06888A080688B2081A88BDF
+:101DB0006081E88BA081288CE0816F48DF22017D63
+:101DC000A3E712271026688800F04DFE002C36D0BD
+:101DD00068784007400F0328C5D16748FD22017D80
+:101DE00093E72CE0287E030018F07AFE0604111118
+:101DF000212121271B270926002C20D0A18000208B
+:101E000020725D48017D490849000175C9E61B271C
+:101E10000926002C13D0A180287E012805D003209C
+:101E200020725548EF22017D6FE70220F8E7214636
+:101E30002846029A01F003FF79E6FFDFB1E6029837
+:101E40000680B4E610B54C4894B08078132802D0D0
+:101E5000082014B010BD22206946087009A9684600
+:101E600009F012FC0446002107200FF0F6FC204682
+:101E7000EFE700B5404895B08078122801D00820DF
+:101E8000AAE41E216846017000218170C17009A971
+:101E900009F0FAFB0028F3D1002107200FF0DDFC48
+:101EA0001120FFF72FFA002096E400B5324895B0D4
+:101EB0000078022803D0032801D008208CE41B21DD
+:101EC000684601700021817009A909F0DDFB002836
+:101ED000F4D1002108460FF0C0FC012000F0A0FD65
+:101EE000002079E4F8B5244C030018F0F9FD0A0647
+:101EF0006B176B6B6B6B38315D6BFFF7D6FF002890
+:101F000026D105F02EFD002822D0222101700021CB
+:101F1000017605F004FD207D012141E08EB23046BE
+:101F2000FFF759FA050000D1FFDF287821280FD0EC
+:101F300005F017FD00280CD012210170022707764A
+:101F400046800020A87505F0EAFC207D3843207506
+:101F5000F8BD132229463046FFF709FCF8BDA578E5
+:101F6000122D03D0132D09D0FFDFF8BDFFF781FF3D
+:101F700006E00000FFFF0000A8010020FFF762FF5D
+:101F80000028F2D105F0EDFC0028EED022210170EE
+:101F9000122D07D00221017605F0C1FC207D102111
+:101FA0000843D4E70121F6E7607A8109012907D0C7
+:101FB000800900D0FFDF03210020FFF70FFCF8BDF0
+:101FC0000221F9E7FFDFF8BDF7B582B014460D0036
+:101FD00000D1FFDF2046297818300827009001291A
+:101FE00003D0022919D0FFDFA2E40298FFF7F3F92A
+:101FF000060000D1FFDF0220B0751030207060783D
+:102000000A22384360702946009818F0A8FAF84868
+:102010002022017D114301758AE40298FFF7DBF964
+:10202000060000D1FFDF6988F248814208D1AA8802
+:10203000824205D1132231460298FFF798FB77E4DC
+:10204000814202D1A88800280BD01220207060782D
+:102050000A22384360702946009818F080FA002060
+:1020600006E078230022022002990FF067FB01208E
+:10207000B0755DE430B5054695B00C4608460FF0E6
+:102080002BFC00282FD1203D01212B0018F028FD2A
+:1020900006042640444A545B002108200FF0B7FB99
+:1020A000002802D0112015B030BD242069460870E8
+:1020B00000A80522A11C023018F051FA09A96846AF
+:1020C00009F0E2FA05002BD1082300221146184638
+:1020D0000FF034FB082823D0FFDF21E060680FF009
+:1020E0002EFC002801D01020DDE73C21684601705D
+:1020F000218841806188818009A909F0C5FA05001D
+:102100000ED1606800280BD06946098D018007E078
+:10211000206802F0BCF802E0204600F0B7FC05465B
+:102120002846C0E73D2208E0997000E0987009A9B0
+:10213000184609F0A9FAF2E734226B461A702278A1
+:10214000D207F3D0F0E70720ADE730B5054695B0EC
+:102150000C4608460FF0DDFB002801D01020A2E756
+:10216000203D2B0018F0BCFC050421212321350063
+:102170002088FFF730F9002804D00078222803D205
+:10218000082090E79C488EE7252168460170218849
+:10219000418009A909F078FA050018D10AA9052299
+:1021A0000231A01C18F0DBF911E006250FE02068D1
+:1021B000002808D00FF0C3FB002801D0102506E04E
+:1021C000206802F059F88A480025408AA0802846F5
+:1021D00069E7072067E786480A30704710B518217D
+:1021E000834818F019FA012000F01AFC1120FFF7BB
+:1021F00089F87F4C00206074E12080006082211DFE
+:10220000E01C05F07DFCE11C0722C81D18F0A7F9B1
+:10221000FFF7C3F8002800D0FFDF00F09FFC01F0BB
+:102220003FFB10BD10B50C463E21204618F0F4F9D6
+:10223000A07F80088000A077202020700020A0755B
+:102240002034A07010BD7047FEB505460E46084606
+:102250000FF042FB002801D0102068E4644C002DF0
+:1022600002D0012D31D125E00722E11C684618F08B
+:1022700076F9E11C3046FFF733FA0028EDD1FFF77D
+:102280008CF8070006D007226946E01C18F067F9B1
+:1022900038464CE43078002801D0012805D1544854
+:1022A0000722E11C0A3018F05AF9002109200FF02A
+:1022B000D4FA0FE03178002907D0012905D002298E
+:1022C00005D0032903D04D4831E407202FE4012035
+:1022D000FFF784FA6574002029E410B504460FF076
+:1022E00018FB002801D0102010BD41492246C878B3
+:1022F000091DFFF72BFA002010BDFFB599B0054668
+:10230000002008A908746946087108A908730875AF
+:102310001E46144628460FF01DFB002804D1204617
+:102320000FF018FB002802D010201DB0F0BD284689
+:10233000204318D01F270BAB0CAA009728461A99E8
+:10234000FFF768F90028F0D10DAB01AA314620460D
+:102350000097FFF75FF90028E7D168460079C007CA
+:1023600003D00A20E1E70720DFE702AF002D0FD0FE
+:102370001A20694608721A9888722946F81C1A9A17
+:1023800018F0EDF80EA902A809F07EF90028CCD1CA
+:10239000002C0ED0202168460172867232462146FA
+:1023A000F81C18F0DCF80EA902A809F06DF9002855
+:1023B000BBD108A80E49007B48700020B5E770B576
+:1023C00006460A200C46087015461146204609F0BC
+:1023D0005BF9002807D1382121702046294609F0F1
+:1023E00053F900280CD0082801D10448401C70BDC6
+:1023F000A8010020FFFF00000230000002320000B0
+:102400002A462146304600F067FB0446082800D1E2
+:10241000FFDF2046EBE7F0B50446F9A103C997B00A
+:1024200014900027159120460FF056FA002807D186
+:102430002078012807D160680FF04EFA002802D0FA
+:10244000102017B0F0BDF04D2878012801D00820E9
+:10245000F7E707200BF072FB002804D12078002852
+:102460000AD0012808D0FEF767FF002806D0287D93
+:102470000107890F08D103E01220E2E71320E0E70B
+:10248000C10701D1800701D51120DAE7208ADF4A90
+:10249000014620399142217807D301297ED10028B5
+:1024A0007CD1618A002979D110E0022901D0032969
+:1024B00001D1A02872D3012908D0D3494978C9078E
+:1024C00004D0618A002969D0B42967D8217800290D
+:1024D00006D0012908D0022904D003295ED117E0D3
+:1024E000002518E0022516E0002802D1608A0028A5
+:1024F0000CD004256068007800280CD0012809D091
+:10250000022807D0032805D0C1489AE70125F1E742
+:10251000032500E00127207A002806D0012806D0F4
+:10252000022806D0032860D105E0002604E0012639
+:1025300002E0022600E00326002D01D0022D15D175
+:10254000002E13D0E068002803D0FFF704F800281D
+:1025500093D1AD484078800702D0AD48401E70E767
+:10256000022D03D1022E40D0032E3ED01821684602
+:102570000170218A4180218A81808571A248C078BA
+:10258000002801D0012865D16946C87168460772E4
+:1025900021780930012922D0062100E025E018F039
+:1025A0003BF869460E74207D8207C107D20F4007B1
+:1025B000C90F5200C00F11438000014314A8405CB2
+:1025C0006946C873002810D009A9684609F05CF86C
+:1025D00000289AD1002D0AD0022D08D012E061689F
+:1025E0000622491C17F0BBFFDBE7072029E7002E76
+:1025F00008D0E068002805D009AA6946FFF7DFFE89
+:102600000028ACD11B20694608700120887009A9F8
+:10261000684609F039F80028A1D108A840791B289C
+:1026200018D12B0018F05CFA050404060604090012
+:10263000032000E0022000F0F3F9012D0CD0608AA5
+:10264000002809D000228300114610460FF076F8CA
+:10265000002801D00320F4E60020F2E6F3B583B0B1
+:102660000E46032508460FF075F9002866D1039839
+:10267000FEF7B1FE040004D02078222803D20820FF
+:10268000B2E46448B0E4A07F8707BF0F002E05D0F6
+:1026900031463846FEF72AFF0500F1D15A48012F8E
+:1026A00004D0022F18D0FFDF28469DE4A27D3146DA
+:1026B000012A02D0007D800701D5112094E4002971
+:1026C00005D1684600F0E7FA0028D9D16946039899
+:1026D00006F00EF90546E7E7A17D022915D1007D38
+:1026E000800612D4002E04D0A07F40070BD4002116
+:1026F00000E00121039806F050F90500D4D1A0753F
+:10270000002ED1D003E01125CEE7002E16D03246A0
+:1027100021460398FFF74BF805461128C4D1A07F46
+:102720004007C1D42046082231460E3017F017FF6B
+:10273000A07F04210843A0770025B5E7102053E4CB
+:1027400070B50C460546FEF746FE010004D0224651
+:102750002846FFF70CF84AE62E4848E600B595B043
+:10276000312269460A70887009A9684608F08CFF12
+:1027700015B000BD10B50123FEF732FE10BD0023D9
+:1027800010B51A461946FEF72BFE10BD70B594B071
+:1027900004460FF0A1F8002802D0102014B026E65D
+:1027A0002046FEF71BFF0028F8D1174DA878112806
+:1027B00001D00820F2E7FEF7BFFD002804D0287DF5
+:1027C000C00603D51120E9E71320E7E71D2168467D
+:1027D000017020780126C107C90F684681702189E0
+:1027E00081806189C18020788007C10F684641726D
+:1027F000E878002500280FD0012810D00320CDE76D
+:102800000706050403020100A8010020E13F0000C3
+:1028100002320000023000006846057201E068469E
+:10282000067209A908F030FF0028B7D12078800788
+:1028300008D56068002805D009AA6946FFF7BFFDE2
+:102840000028ABD11E21684601708670C57009A9A9
+:1028500008F01AFF0028A1D1A08900F0F5F80400C3
+:102860009CD11220FEF74EFD204697E7F0B595B0BB
+:1028700015460C4606460FF06DF8002809D1204693
+:102880000FF02AF8002804D128460FF025F8002878
+:1028900002D0102015B0F0BDAD4F387DC106890FB4
+:1028A00001D1400701D51120F4E72046FEF796FE3E
+:1028B0000028EFD120788107C90F314303D080076A
+:1028C00003D5002E01D00720E4E729460220FEF7B9
+:1028D0000DFE0028DED1B878112803D0122801D0CF
+:1028E0000820D7E706200BF029F9002804D09848E3
+:1028F0008078122802D005E01220CBE7FFF7B9FA62
+:102900000028C7D1FEF718FD022801D21320C1E725
+:102910002078800708D56068002805D009AA694694
+:10292000FFF74DFD0028B5D12121684601702189AE
+:10293000418061898180207800278007C10F684627
+:10294000817120788007002815DB3078002807D0B7
+:10295000012808D0022806D0032804D07D4899E732
+:102960006846C77102E001206946C8710622711CE1
+:1029700002A817F0F4FD7648C078002803D001289B
+:1029800004D0032086E76846877302E00120694689
+:10299000887329886846018269884182A988818272
+:1029A000E988C1820783478309A908F06DFE0028E2
+:1029B0008AD1A08900F048F8040085D11320FEF7E1
+:1029C000A1FC204666E730B5054695B00C460846A2
+:1029D0000EF09FFF002802D0102015B030BD284611
+:1029E000FEF7F9FC002807D00178222902D3807F66
+:1029F000800603D40820F0E75748EEE71321684625
+:102A00000170458009A908F03FFE0028E5D108AA19
+:102A10000A2151567F2901D02170DEE70520DCE72D
+:102A200030B54B4D040008D0012C04D0022C06D048
+:102A3000032C04D0FFDF2C7030BDFFDFFBE72878CC
+:102A40000128F8D0FFDFF6E710B5002809D0830091
+:102A50000022114607200EF071FE072801D0032046
+:102A600010BD002010BD70B50C0006460DD0FEF75D
+:102A7000B2FC050000D1FFDFA680288920812889CB
+:102A800060816889A081A889E081B0E410B504461E
+:102A90000068002806D00EF05DFF002801D010204D
+:102AA00010BD206801F0DBFBA088294C6082607CAF
+:102AB00001280DD1002109200EF0A9FE002800D028
+:102AC0000120617A8909012904D00321FEF786FEDD
+:102AD000002010BD0221F9E7F7B500260C46054697
+:102AE0000B271AE02968B00009580978002903D09B
+:102AF000012901D00720FEBDA170296806220958CE
+:102B0000E01C491C17F02BFD27702046029908F0A5
+:102B1000BBFD0028EFD1761CF6B22879B042E1D88F
+:102B2000002639270FE0A868B10041581022A01CE8
+:102B300017F015FD27702046029908F0A5FD002822
+:102B4000D9D1761CF6B2287BB042ECD80020FEBD6D
+:102B5000A8010020023200000230000010B506215A
+:102B6000D04817F059FD10BDFFB591B0149C204618
+:102B70000EF0B2FE002802D0102015B0F0BD2146A4
+:102B80000120FEF7B3FC0028F7D101246846032199
+:102B90008471C9028180002201A9204603F0EDFE64
+:102BA0000028EAD1684615218471490281800026F7
+:102BB0001C2102A8009617F031FD0120014668464D
+:102BC0001031017000200146684641708178F92774
+:102BD0003940891C21438170017A02252943017201
+:102BE00012998186C6861F2101870C9011980F903B
+:102BF00001A80B9009AA0BA902A803F0A9FC0028C0
+:102C0000BBD16846A74E808C308068468471A64947
+:102C10008180807809AA3840801C410849006846B4
+:102C200081708586058713A80F900BA902A803F071
+:102C30008FFC0028A1D16846808C7080311D1498CB
+:102C400000F0EDF899E73EB5044608206946088093
+:102C500020460EF041FE002801D010203EBD214646
+:102C60000120FEF743FC0028F8D1208869468880BF
+:102C70006088C880A0880881E0884881894801ABC5
+:102C800080886A46002104F07FF86946098808298F
+:102C9000E4D003203EBD1FB504460020029008206A
+:102CA00069460881204603910EF016FE002802D0E6
+:102CB000102004B010BD7B4802AA81887B4804F034
+:102CC00007FA0028F5D169460989082901D00320AF
+:102CD000EFE769460988218069464988618069462D
+:102CE0008988A1806946C988E180E2E701B582B0A0
+:102CF0000220694608806B4802AB40886A46002182
+:102D000004F042F869460988022900D003200EBD6C
+:102D10001CB50021009102216A46118001900EF03D
+:102D2000F8FD002801D010201CBD5E486A4641888D
+:102D30005E4804F0CDF9694609880229F4D00320E1
+:102D40001CBDFEB5064615460F4608460EF0C4FDEE
+:102D5000002801D01020FEBD1F2D01D90C20FEBD82
+:102D600030460EF0B9FD4F4C002822D1208801A931
+:102D700003F058F90028F2D130786946487120886C
+:102D800001A903F0E2FF0028E9D169460090087824
+:102D900002210843694608704979090703D00821D0
+:102DA0000843694608702088694603F06DFF0028D3
+:102DB000D5D169460D8120883B4602AA002103F047
+:102DC000E3FF69460989A942C9D00320FEBD7CB54D
+:102DD00005460020009001900C460888694608804E
+:102DE000284601950EF0ABFD002804D120460EF0D8
+:102DF00090FD002801D010207CBD002D03D0684636
+:102E00000088002809D027486A460188274804F02E
+:102E10005FF96946098821807CBD0C207CBD30B5F6
+:102E2000044693B000200D46079014210BA817F01C
+:102E3000F5FB1C21684617F0F1FB6A46112010775C
+:102E400000205077107802210843107007A80C90DA
+:102E5000012008AA907214486A46C01C10850AA86E
+:102E60000B902088108460885084A0889084E0882B
+:102E7000D084907FF9210840801C40084000907762
+:102E800008209086108708A80F9010AA0BA9684602
+:102E900003F05EFB002803D110A8008828800020E2
+:102EA00013B030BD10000020012A0000FFFF000019
+:102EB00001202049C00308601F4900200870072036
+:102EC0001E49C0058860704730B51B4D0446287800
+:102ED000A04204D0002C02D0002800D0FFDF2878C8
+:102EE000A0420BD00021164A14482C70002C18D098
+:102EF000144B012C03D0022C0AD0FFDF30BD11602F
+:102F0000022111605361032109068160416030BDD7
+:102F100011600321116053610121C9058160416085
+:102F200030BD116011600721C905816030BD00B559
+:102F3000FFDF00BD80E100E01600002000F5014049
+:102F400000F500406403002010B50DF062FB10BDD9
+:102F500003490020C863034902200860704700004D
+:102F6000C01F004080E200E00E4A12680C498A420D
+:102F70000AD118470B4A1268094B9A4204D101B58D
+:102F80000EF072FA03BC8E460749096809580847D3
+:102F900006480749054A064B70470000000000003C
+:102FA000BEBAFECA9800002004000020781100205C
+:102FB0007811002070B50C46054606F0B1FE21469A
+:102FC000284607F014FF70BD10B50EF0CBFD0EF0D3
+:102FD000F9F8FFF76DFF16F0B5F90EF0DBFC0EF017
+:102FE0005BFD10BD0348044A0168914201D10021F4
+:102FF0000160704798000020BEBAFECA7047704753
+:1030000010FFFFFFDBE5B15100B001008000FFFFC2
+:1030100010B504460EF060FC002801D0102010BD51
+:1030200020784006400F042807D86078072804D38A
+:10303000A178102901D8814201D2072010BDE07883
+:10304000410706D421794A0703D4000701D40807B1
+:1030500001D5062010BD002010BD30B5C37F147807
+:103060005B08A4075B00E40F2343C3771578FD24B6
+:103070006D07ED0F23406D002B43C37713788878DD
+:10308000DB0920405B001843887014784B78640695
+:10309000DB06640FDB0E640123434B70137840089A
+:1030A00040001B07DB0F184388705078487130BD13
+:1030B000F0B50B78C4785B08E4075B00E40F2343AA
+:1030C0000B70C478FD26A407E40F3340640023434B
+:1030D0000B70C478FB256407E40F2B40A400234346
+:1030E0000B70C778F7243F07FF0F2340FF003B43D7
+:1030F0000B70117803794908DB074900DB0F19438E
+:103100001170037931409B07DB0F5B00194311708D
+:10311000037929405B07DB0F9B001943117000798D
+:1031200021400007C00FC00001431170F0BD70B511
+:1031300014460D46064604F014FC002809D0A221CE
+:103140000170142221461830FEF720F804F0E7FB46
+:1031500070BD132229463046FEF709FB70BD70B5DD
+:1031600015460E46044604F0FCFB00280AD0222136
+:103170000170448004222946183017F0F0F904F059
+:10318000CEFB70BD132231462046FEF7F0FA70BD2B
+:1031900010B5FE4C207C00280AD12046FC4A21466E
+:1031A00010380CF060F9002800D0FFDF01202074F7
+:1031B00010BDFFB581B00B9E05461F461421304659
+:1031C0000A9C17F02BFA0C98002101600398002844
+:1031D00001D0029801E03878C007002812D020689A
+:1031E0000EF097FB00283FD10398002807D12068F4
+:1031F000123030602068143070602068B0600C9825
+:10320000216801603878800726D560680EF097FB4A
+:10321000002829D10298002829D0FEF7DCFF0146BA
+:103220002846FF300722B53017F099F9FFF7B0FFB5
+:10323000D6480090F0606268002A0DD0FF20294631
+:10324000B530FF31405DB6311032FEF77FFA102203
+:103250006068009917F083F93878400712D5A068A4
+:103260000EF057FB00280BD0102005B0F0BD6068B1
+:103270000028F9D0F060FF35813560682863EBE7FE
+:10328000A06830610020F0E730B50C4611212170B4
+:103290000022054662702035A878002806D0042850
+:1032A0000DD005280FD0062812D0FFDF20780009A6
+:1032B000012803D92878C006C00E607030BD080709
+:1032C000000F203002E00807000F30302070EDE7DB
+:1032D0000807000F4030F9E710B5002803D0A924F3
+:1032E000245C002C08D0A948447D0020002C0BD081
+:1032F00008601060186010BD0446A8340C600146D8
+:10330000D031F8301160F5E7A04C14340C60F0E7D0
+:1033100010B58AB008236C466370019102910023B6
+:103320009A490993039223744431059101466846F2
+:103330000CF06FF8002800D0FFDF0AB010BD70B5A8
+:1033400094B015460C462C226946189E0A70488097
+:10335000002B17D00822194601A817F000F968467B
+:103360008581102231460E3017F0F9F809A9684618
+:1033700008F08AF9002803D1A17F10221143A17718
+:1033800014B070BD002001900290E8E7F0B5064649
+:10339000008A8BB080B20D460390FEF71CF87B4983
+:1033A0000446483930780F4668370091030017F01B
+:1033B00097FB12FAF93A0A3B7A819DADF8F7F6F5D8
+:1033C000F4F360F3F3FAA07F8007800F012806D0A2
+:1033D000002103980AF0FCFB050003D101E0012164
+:1033E000F7E7FFDF387FC00905D068482946203855
+:1033F000006E21310DE028462130032107460DF0F3
+:103400007DFF384617F00CF9624917F022F908469B
+:10341000394617F016F970686866B068A8662078B3
+:10342000252800D0FFDFFCE0A07F8007800F012867
+:1034300006D0002103980AF0CBFB060003D101E07F
+:103440000121F7E7FFDF7078810702D52178252970
+:1034500004D00121084370700BB0F0BD0220287029
+:103460002020805D2871304621303136EE60A86022
+:10347000F2E7A07F8007800F012806D00021039883
+:103480000AF0A6FB040003D101E00121F7E7FFDF0A
+:103490006078C10604D51420287041346C60DBE7E5
+:1034A0000821084385E03948082148380DF026FFF7
+:1034B000032017E02A206946087101A81022023073
+:1034C000716817F04CF805A810220230B16817F0A7
+:1034D00046F82E4901A84C3908F0D6F8002800D04B
+:1034E000FFDF0420287000986860B5E7E07FC00621
+:1034F00000D5FFDFB0680090B3880622032103984F
+:1035000005F05CF90028A7D0FFDFA5E7002C00D16B
+:10351000FFDF7168002904D020461022233017F005
+:103520001EF828212046FDF78CFFA07F8007800F22
+:1035300002280ED120462330002300901A4621464F
+:103540000398FFF7FCFE112806D029212046FDF73D
+:1035500078FF307A2034B4E0A07F000700D5FFDF89
+:10356000A07F08210843A0770020A086204636309F
+:1035700017F052F8E07FFB220146C9071040490FBF
+:103580000843F72101408007C00F0DE07C020020B6
+:10359000FFFF000040420F0034E07BE19CE092E03E
+:1035A00063E008E043E079E1C0000143E177307A6D
+:1035B0002034607050E7A07F8007800F012806D07C
+:1035C000002103980AF004FB040003D101E001216B
+:1035D000F7E7FFDF2046022175300DF08FFE112046
+:1035E00028702046FF30B530686020466130017D8C
+:1035F0002974407D6874FE48A86010306C346C619A
+:10360000E86029E7A07F8007800F012806D000210D
+:1036100003980AF0DDFA002803D101E00121F7E761
+:10362000FFDF324621460398FFF781FD14E7002CA7
+:1036300000D1FFDF20782128BCD93079012802D0C1
+:10364000022808D103E0E07F10210843E077387FAB
+:10365000012108433877324621460398FFF767FD7A
+:1036600023212046FDF7EDFEF6E632790123032102
+:10367000039804F097FE002813D0122028703279A6
+:10368000AA802846A91D0C3008350191029000231C
+:1036900000950321039804F004FF00288AD0FFDF7F
+:1036A000DAE6A07F8007800F012806D0002103986A
+:1036B0000AF08EFA040003D101E00121F7E7FFDFF1
+:1036C00030792070C8E60321039805F030FA00280D
+:1036D00097D113202870BFE6A07F8007800F0128B4
+:1036E00006D0002103980AF073FA050003D101E027
+:1036F0000121F7E7FFDF2E466036307D8007800F1F
+:1037000001287DD1A07F8007800F0890E07F80078F
+:10371000C70F03D00898012804D031E09020405D05
+:10372000C00731D02946FF318131CA6A002A25D02D
+:10373000107CF37C8007800F9B0018431074FD23DE
+:103740001840E37FCA6ADB079B0F184310744008D8
+:1037500040003843CA6A002F107415D0C86A214649
+:103760001022233116F0FBFE28468030017C012216
+:1037700011430174307E9043307601E0002F03D076
+:103780000898022803D031E0307EC0072BD02846AD
+:10379000FF308130826A002A25D0117CF37C8907B2
+:1037A000890F9B0019431174FD231940E37F826A3E
+:1037B000DB079B0F19431174490849003943826A9A
+:1037C000002F11740FD02146806A1022233116F089
+:1037D000C6FE307E01210843307628468030017CC9
+:1037E000490849000174089802284FD00020182188
+:1037F000484340196030007E80070AD5FF2000E072
+:1038000007E0B13042592946307B6D311032FDF767
+:103810009DFF052168460175307D80358107890F40
+:1038200068464175317E8175297CC17570482221B9
+:103830009C38039A0170417805ABC908C900C91CBE
+:103840004170428004221946183016F088FE6848FC
+:103850009C3804F009FA2078252805D0212807D0C3
+:10386000FFDF2078222803D922212046FDF7E9FD39
+:10387000A07F8007800F01280AD0002103980AF05A
+:10388000B8F9002800D1E7E5FFDFE5E50120AEE764
+:103890000121F3E7716800204870DDE5FFDFDBE51B
+:1038A00070B55348524C4030017F00254906490EFF
+:1038B000017725660BF076FD21461031204604F095
+:1038C00052F92046203005740721403041712C30D8
+:1038D000E066503060671030A06770BD70B50D466F
+:1038E000FDF779FD040000D1FFDFFF21BD3128463F
+:1038F00016F094FE3E48643068612046233028610B
+:10390000A07F8007800F012809D002212846FF30C0
+:1039100021300BF048FD002800D0FFDF70BD0121F1
+:10392000F4E70A460146104610B5FF3021300BF08F
+:103930005AFD10BDF0B505464068082601789BB0D9
+:1039400008290DD00B2903D00C2938D10121817110
+:10395000686887883846FDF73EFD040036D134E0BC
+:1039600047883846FDF737FD040000D1FFDF207897
+:10397000212824D0282824D1686802210C3001F0A5
+:1039800032FA00281DD068680821001D01F02BFACA
+:10399000002816D02D21684601704780214610224C
+:1039A000233101A816F0DBFD0FA9684607F06CFE75
+:1039B000002800D0FFDF29212046FDF742FD1BB083
+:1039C000F0BD687830436870F9E7FFDFA07F8107BA
+:1039D000890F022902D1EF210840A0772078212801
+:1039E0000FD068688179002905D08078002801E02F
+:1039F0005C02002010D0A07F8007800F022858D0E2
+:103A0000FFDFA07F8007800F0228D8D1FDF71DFFC0
+:103A10000028D4D0FFDFD2E7687830436870E07FB9
+:103A2000C10720D0800701D5062100E00521222012
+:103A300001552078292818D02428E2D139460620BB
+:103A40000DF00BFF22212046FDF7FBFCA07F800735
+:103A5000800F01282BD0002138460AF0CAF8002830
+:103A6000CFD0FFDFCDE70421E1E7A07F8007800F03
+:103A7000012806D0002138460AF0AAF8050003D133
+:103A800001E00121F7E7FFDF25212046FDF7D9FC02
+:103A9000102008A908712846FF3009A921300BF031
+:103AA00097FC0228ADD00028ABD0FFDFA9E70121A9
+:103AB000D2E7687830436870A3E7FFB58BB01D4646
+:103AC0000646FDF788FC040054D02078222851D304
+:103AD00023284FD0E07FC0064CD4A07F8007800F02
+:103AE000012806D0002130460AF072F8070002D003
+:103AF0000BE00121F7E7A07F8007800F012804D1A8
+:103B0000012130460AF05CF8074601AB02AA03A97E
+:103B10003846FFF7E1FB0398002800D1FFDF002FB4
+:103B200009D0FF370398213787612078222806D0F3
+:103B3000242804D007E003990020886103E02521B0
+:103B40002046FDF77EFC03980C21417046620D99DA
+:103B500081800C9981601499C180C56002990161CE
+:103B60000199416104A90BF054FC022802D00028FD
+:103B700000D0FFDF0FB0F0BD30B589B00546FDF7CE
+:103B80002AFC0178222934D9807F8007800F012800
+:103B900006D0002128460AF01BF8040003D101E0FA
+:103BA0000121F7E7FFDF227801230321284604F0F3
+:103BB000F9FB00281DD01221684601732278028289
+:103BC00006A8694405AB00930191029000230321EC
+:103BD000284604F066FC002800D0FFDF2046FF30B6
+:103BE00003A921300BF0F4FB022802D0002800D0FA
+:103BF000FFDF09B030BD10B586B00446FDF7EBFB22
+:103C00000178222919D9807F8007800F012806D0EA
+:103C10000021204609F0DCFF040003D101E001216E
+:103C2000F7E7FFDF1320694608702046FF30213098
+:103C30000BF0CEFB002800D0FFDF06B010BDF7B5BB
+:103C4000054600780C46010920460027083082B05E
+:103C50003E46019002297DD0072902D00A2909D1C8
+:103C600040E068680178082905D00B292AD00C2982
+:103C700028D0FFDF0BE214271C26002C6BD04088D5
+:103C8000A080FDF7A8FB0090002800D1FFDF00987E
+:103C90000099C07D1831019AFDF758FD6868082227
+:103CA00080892082696820461230091D16F057FC71
+:103CB000A07E01210843F9210840A0760098402108
+:103CC000807F56E01A270A26002CD7D08088A08053
+:103CD000FDF781FB050000D1FFDF28460199FFF7C2
+:103CE000D3FAD4E1002C01D0288DA080287E0E28A4
+:103CF0007ED006DC01287CD0022808D0032804D11D
+:103D00003EE0102876D0112875D0FFDFBFE11E27D6
+:103D10000926002CB2D0A088FDF75DFB009000289A
+:103D200000D1FFDF287F8007800F0128207A24D070
+:103D3000400840002072FD210840297F4907C90F33
+:103D4000490008432072FB210840297F0907C90F59
+:103D5000890001E08FE160E108432072F72108400B
+:103D6000297FC906C90FC900084320720098802125
+:103D7000807F08430099887789E101210843D9E7CA
+:103D800013270D26002CA0D0A088FDF724FB00905F
+:103D9000807F8007800F012806D00021A08809F0CD
+:103DA00017FF050003D101E00121F7E7FFDF0098CD
+:103DB000807F8207920F012A7ED0A86E81788907C2
+:103DC000890F0129217A79D0490849002172857823
+:103DD000FD236D07ED0F19406D0029432172FB256E
+:103DE000294085782D07ED0FAD002943217203E0AE
+:103DF0009FE0E7E0CDE0DEE0F72529408578ED069D
+:103E0000ED0FED00294321728F25294005786D07BC
+:103E10006D0E2943217245784906490EED0129436B
+:103E2000217200216172C178A172E17A012A48D021
+:103E300042794908D2074900D20F1143E172427911
+:103E400019409207D20F52001143E1724579FB22CB
+:103E50006D07ED0F1140AD002943E172F7252940B0
+:103E600045792D07ED0FED002943E172217B05799E
+:103E70004908ED074900ED0F2943217319400379E3
+:103E80009B07DB0F5B001943217311400279520736
+:103E9000D20F920011432173F722007911400007DD
+:103EA000C00FC000014321730098007823286FD908
+:103EB00026217EE000E001E0686E7FE701231943E0
+:103EC00084E702794908D2074900D20F1143E17211
+:103ED000027919409207D20F52001143E17205791D
+:103EE000FB226D07ED0F1140AD002943E172F7256C
+:103EF000294005792D07ED0FED002943E172217B63
+:103F000045794908ED074900ED0F29432173194010
+:103F100043799B07DB0F5B00194321731140427902
+:103F20005207D20F920011432173F72211404079BA
+:103F3000B5E718271026002C6FD0A088FDF74BFAA4
+:103F40000190807F8007800F012807D00021A08882
+:103F500009F03EFE0090002803D101E00121F6E7C0
+:103F6000FFDFE869A06000980421407808430099C9
+:103F7000487000988078800708D501202073019848
+:103F80000078232804D92721019867E0002020E148
+:103F900066E015270F26002C68D0A088FDF71BFAD5
+:103FA00000900622E869019907F0D4FB0120A07374
+:103FB000B5E0009852E016270926002C56D0287F3D
+:103FC000207264E0297FFE4802290DD019270E26B1
+:103FD000002C4BD001290ED003291BD004291DD061
+:103FE00005291BD0FFDF24E01B270926002C4ED01B
+:103FF0000121217205E001212172617A890889007D
+:104000006172017FCA094906D201890E49000A433B
+:1040100002770EE00220207207E027E0687F0007A9
+:10402000000F8030207205291BD0607A8008800044
+:104030006072A088FDF7CFF905460078212826D0C8
+:10404000232800D0FFDFA87F8007800F012810D031
+:104050000021A08809F0CDFD22212846FDF7F1F9C5
+:1040600015E0607A80088000401CE1E70498068033
+:1040700013E00121EDE7002C01D06888A080287EA4
+:1040800003282ED004280BD005284ED0FFDF04983B
+:10409000002C068001D027806680002005B0F0BD8E
+:1040A00015270F26002CE1D0A088FDF794F9807F1A
+:1040B0008007800F012806D00021A08809F088FD24
+:1040C000050003D101E00121F7E7FFDF2846213099
+:1040D00016F0A6FA0622019907F03CFB0020A07317
+:1040E000D5E717270926002CC0D0A088FDF773F963
+:1040F0000090807F8007800F012806D00021A088D3
+:1041000009F066FD050003D101E00121F7E7FFDFBB
+:10411000A878800701D5022000E0012020720098D5
+:1041200000782328B3D9272143E719270E26002C2E
+:104130009CD0A088FDF74FF90090002800D1FFDF48
+:104140000621019816F06AFA00202072A07A032155
+:104150000843A072FB2108400099C97FC907490F95
+:104160000843A0720099C97F8A07D20F1140F72235
+:10417000C90010400143A172687E8007800F0128AA
+:1041800085D1607A0421084360720098807F80079F
+:10419000800F01281FD0607B4108E87E4900C007DE
+:1041A000C00F01436173207BAA7E4008D207400004
+:1041B000D20F10432073EB7EFD229B07DB0F1140D3
+:1041C0005B0019436173A97E10408907C90F49003C
+:1041D000084320735BE7207BE97E4008C907400065
+:1041E000C90F08432073617BAA7E4908D2074900A2
+:1041F000D20F11436173EB7EFD229B07DB0F104052
+:104200005B0018432073A87E11408007C00F400058
+:10421000014361733BE710B50446807990B0800993
+:10422000012800D0FFDFFEF7B3FF01206946487088
+:104230006448099062480AA920380190201D029024
+:10424000601C0B9068460BF0E4F8002800D0FFDFFC
+:104250000322601C0B9916F082F910B010BD10B546
+:10426000574C203C002805D001461022204616F06D
+:1042700076F90120207410BD10B50446FEF788FFC2
+:104280004F4910222039204616F069F910BD70B54B
+:1042900000254B4C0646002816D00DF01DFB0028CB
+:1042A00001D010250EE00621304607F03DFA411CF2
+:1042B00007D0434940390866207F80210843207792
+:1042C00000E00725284670BD207F4006400EF6E737
+:1042D000F3B589B00D46002708460DF03BFB0028DA
+:1042E00014D10998FDF777F8040003D0207822282C
+:1042F00015D102E034480BB0F0BD002D08D1A07FED
+:10430000C10903D08007800F022801D01020F2E7F6
+:10431000A07FC10601D4010703D5002D01D00820DC
+:10432000E9E72749097FC90701D01120E3E7E17FC9
+:10433000C90601D50D20DEE78007800F022806D1CF
+:10434000002D04D02846FEF763FE0700D3D1A07FDE
+:104350008007800F012806D00021099809F038FC59
+:10436000060002D00CE00121F7E7A07F8007800F54
+:1043700001280BD00021099809F022FC060007D083
+:10438000A07F8007800F022804D00AE00121F2E715
+:104390000420B0E7002D04D02A4631462046FEF71F
+:1043A0005CFE07AB1A4669463046FEF795FF00985B
+:1043B000002800D1FFDF00990D204870099805E022
+:1043C0009C020020FFFF00000230000048623046DF
+:1043D000FF302130486100200881A07FFB22800748
+:1043E000800F012832D0002D56D002200871301DD8
+:1043F0008861707840090877B0788007C00F4877E7
+:10440000887F2B788008DB078000DB0F18438877D4
+:104410001040E27FD207520F10438877F7221040F6
+:10442000E27F9207D20FD20010438877EF2210402C
+:10443000B278D207D20E10438877A878C8770A4698
+:10444000213228462031FEF733FE29E00120087191
+:10445000087E2B788008DB078000DB0F1843087686
+:1044600010402A789207D20F920010430876F72264
+:1044700010402A785207D20FD20010430876EF225C
+:1044800010402A781207D20F120110430876242117
+:104490002046FCF7D6FF0BE00320087105200876C4
+:1044A00025212046FCF7CDFFA07F4006400EA077D7
+:1044B00001A900980AF0ADFF022802D0002800D020
+:1044C000FFDF384617E7FFB5FB4A0D4607CA99B02C
+:1044D00003AB07C300271998FCF77DFF060005D042
+:1044E0003078262804D008201DB0F0BDF348FBE743
+:1044F000B07F8007800F1590012802D0022808D0D5
+:104500000AE0002D08D11B98FEF782FD0028EBD1B0
+:1045100002E01B98002841D1B07F8007800F01285E
+:1045200006D00021199809F053FB040003D101E0E3
+:104530000121F7E7FFDF852D26D008DC002D1BD0F9
+:10454000812D1BD0822D1BD0832D08D11AE0862D02
+:104550001CD0882D1CD0892D1CD08A2D1CD00F205A
+:1045600020710F281AD0012069460877201D089075
+:104570002079002814D062E10020F1E70120EFE764
+:104580000220EDE70320EBE70520E9E70620E7E757
+:104590000820E5E70920E3E70A20E1E70720A3E791
+:1045A0001598012814D0656EA06E16900220019017
+:1045B000012000901699A878897808400007C00F5C
+:1045C000109069D01C980DF087F9002878D138E058
+:1045D000A56E606E16900120019002200090214689
+:1045E00030461B9AFEF739FD1B99A8780978800898
+:1045F000C9078000C90F0843A870FB210840F17F5C
+:10460000C907490F0843A870F7210840F17F8907BF
+:10461000C90FC9000843A870EF210840A178C90755
+:10462000C90E0843A870607840092870A0788007F8
+:10463000C00F68701B988078E8700020687128713E
+:10464000B8E71C98C0680DF047F9002863D11C98A2
+:10465000C0690DF041F900285DD11C98C068A060C8
+:104660001C98C069E0601699A0784978C907890F3D
+:104670000843A0701699C0B28978C906C90F891E6F
+:104680000840A070002020210855304600991730BE
+:1046900002290BD001210AE0169902224978A0785C
+:1046A000C907890FD24311430840E2E7002189007E
+:1046B000091988610199701C022902D0012101E0C9
+:1046C00029E00021890009198861A8788007800FF6
+:1046D00001284CD1169880788007800F012846D198
+:1046E0001598012804D12A1D691D1B98FEF7E0FCCE
+:1046F00016982979007908AA01401175169A6879E7
+:104700005279104008AA1076014330D01C980DF061
+:10471000E3F8002801D01020E6E61C982146FF317E
+:1047200022461030159BA9317C321790022B3AD0CB
+:1047300002910192009000210DAB2046109AFEF7E5
+:1047400038FD0028E8D12146FF3122461598AD31C9
+:10475000943201282DD017980291019200900021E7
+:104760000EAB2046109AFEF724FD0028D4D1A07885
+:1047700080073DD41699A87889780843400737D533
+:104780001698159B2978007803AA012B17D04300AF
+:10479000D25A4B00DA409707BF0F18D0012F1ED016
+:1047A000022F12D11DE01C9802910192009001216C
+:1047B000C2E71C980291019200900121D0E74B00C2
+:1047C000D25A4300DA409707BF0F032F07D0109A41
+:1047D000002A0DD0012906D0042904D008E00227C0
+:1047E000F5E70127F3E7012801D0042800D10427C9
+:1047F000F07F01210843FD221040109A520010431F
+:10480000F077A07882070320002A0BDAA0711099B4
+:10481000002914D16946087606AA31461998FEF790
+:104820009EFC0CE00225022F1AD0012F1AD0042F73
+:1048300023D00020A071F07F40084000F0772521B0
+:104840003046FCF7FEFD2046FF3007A921300AF074
+:10485000BFFD002802D0022800D0FFDF002043E681
+:10486000A571D7E72046A5710D21243015F0D6FE9D
+:104870006078284360700420CCE7A171DFE7F7B5CA
+:1048800086B00D460446FCF7A6FD070005D0387833
+:10489000272804D0082009B0F0BD0848FBE7B87FFE
+:1048A0008007800F01280BD00021204609F090F9E5
+:1048B000040008D106E0000048AC0100023000000E
+:1048C0000121F2E7FFDFA679012E08D0002D0ED0DE
+:1048D00008980DF001F8002815D01020DBE70898A3
+:1048E000002821D1002D08D0012D1DD11EE0022E5F
+:1048F00005D0032E05D0FFDF28E00C2526E001259A
+:1049000024E0022522E0022D02D0012D0AD00BE086
+:10491000032E09D12046002510222130089915F0D8
+:104920001EFE13E0022E01D00720B4E720462130FE
+:1049300000251021064615F06FFE0898002805D0C6
+:10494000062106F0F1FE314615F07BFE607802216B
+:1049500008436070C20712D040084000607068468B
+:10496000017005712046213002906946FF300AF03F
+:104970002FFD022805D0002803D0FFDF01E02034FE
+:10498000257025213846FCF75CFD002083E730B513
+:1049900087B00D460446FCF71EFD002812D0807F2C
+:1049A0008007800F01280FD00021204609F010F960
+:1049B00004000ED028460CF08FFF002806D01020EF
+:1049C00007B030BDFB48FBE70121EEE76078400708
+:1049D00001D40820F4E7204629464130202205462C
+:1049E00015F0BDFD6078102108436070010710D5F7
+:1049F000F721084060701420694608702046FF3097
+:104A0000213001950AF0E4FC022802D0002800D0F1
+:104A1000FFDF0020D4E770B594B00D460646FCF7E2
+:104A2000DAFC002803D00178272945D102E0E148CB
+:104A300014B070BD807F8007800F012806D0002150
+:104A4000304609F0C5F8040003D101E00121F7E781
+:104A5000FFDFA07902282FD1A078C0072CD0002337
+:104A600002220321304603F09DFC002826D00D21B0
+:104A700068464173FF34213402220C9608948282E6
+:104A800007A8811F06AB0093019102900023032128
+:104A9000304603F006FD002800D0FFDF0421684601
+:104AA000017408A805710DA903A80AF0B2FC00283A
+:104AB00000D0FFDF0020BBE70820B9E71120B7E7EF
+:104AC00070B5064686B014460D4608460CF004FF45
+:104AD000002804D120460CF01CFF002802D0102032
+:104AE00006B070BDB44886420DD03046FCF773FC6A
+:104AF000002806D04378811C22461846FCF726FE83
+:104B000006E0AC48ECE72046FDF7E7FB0028E7D1DC
+:104B10001021E01D0CF0F2FBE21D29466846FEF76D
+:104B2000F7FB204610221730019915F018FD0020E0
+:104B3000D6E7F7B58CB00446154600270D980CF063
+:104B400009FF002804D128460CF004FF002802D0F9
+:104B500010200FB0F0BD2046FCF73DFC060003D04E
+:104B60003078272817D101E09248F2E7B07F80071C
+:104B7000800F012806D00021204609F029F8040002
+:104B800003D101E00121F7E7FFDF6078400702D59C
+:104B9000A078800701D40820DBE7B07F8007800F72
+:104BA00001281DD0616EA06E4978002901D0002D2A
+:104BB00019D04078002802D00D98002813D0002D7D
+:104BC00019D0EA1D06A8E168FEF7A2FB28461022CC
+:104BD0001730079915F096FC002806D004270AE044
+:104BE000A16E606EE0E70720B3E720461022E91DC2
+:104BF000313015F0B4FC0D98002805D0C11D2046B9
+:104C00001022213015F0ABFC60780221084360705F
+:104C1000C20714D0400840006070684601700771F8
+:104C2000204621300290103003906946EF300AF0A0
+:104C3000CFFB022805D0002803D0FFDF01E020349D
+:104C4000277025213046FCF7FCFB002081E7F8B5F2
+:104C500015460E460746FCF7BEFB040004D020783C
+:104C6000222803D00820F8BD5248F8BDA07F800755
+:104C7000800F022802D04F48C01CF8BD30460CF00F
+:104C80002BFE002804D128460CF026FE002801D077
+:104C90001020F8BD00953288B31C21463846FEF737
+:104CA0004EFB112819D00028F3D1E17F2A7C490856
+:104CB00092074900D20F1143E177FD2211402A7C6F
+:104CC000D207920F1143E177297C8A0820210A55E7
+:104CD000A17F4906490EA177F8BDA17F0907FBD442
+:104CE00020460822B11C363015F039FC3088A086E9
+:104CF000204610222946233015F031FCE07FFB21AD
+:104D00000840297C8907C90F89000843E077F7210B
+:104D10000840297CC907090F0843E077287C8108EF
+:104D200021200155A07F08210843A0770020CFE76C
+:104D300070B594B00D460646002B01D0072077E6EB
+:104D4000FCF749FB040007D02078222802D3A07F7B
+:104D5000400603D408206BE6164869E6002D1CD0F7
+:104D60002D216846017046801022294601A815F0C1
+:104D7000F6FBE07F297C400889074000C90F084303
+:104D8000E077FD210840297CC907890F0843E077B7
+:104D9000287C81082020015503E02E2168460170FF
+:104DA000468009A9684606F06FFCA17FBF2211402A
+:104DB000A1773DE602300000FFFF000070B50D4610
+:104DC000FCF709FB040006D028460CF0A2FD0028E1
+:104DD00003D0102070BD0B4870BD29462046FEF759
+:104DE00053FA002070BD05E00278401C002A01D073
+:104DF000002070470A46491E89B2002AF4D10120DA
+:104E0000704700000230000070B50D46007804992C
+:104E10001446042803D005282DD0FFDF70BDA88BD1
+:104E2000062250430E30188033200880002CF5D025
+:104E3000A88BA081002611E0A87F012812D01220A3
+:104E40007043411906227243088C1219D081102038
+:104E5000223110320AF083FB761CB6B2A089B04230
+:104E6000EAD870BDB000411906227243088C1219AD
+:104E7000D0810220ECE7A88B12225043103018801A
+:104E800034200880A87F012808D0022806D0FFDF40
+:104E9000002CE6D0A88BA081002612E0A073F7E7D3
+:104EA000A87F012811D030461221484341190A8CAD
+:104EB0000019028210221230223115F050FB761CAC
+:104EC000B6B2A089B042EBD870BDB0004119122231
+:104ED000088C7243121910820220223112320AF019
+:104EE0003EFBECE7F8B500780C46164620340E364B
+:104EF000069F022805D0032832D006287ED0FFDF87
+:104F0000F8BDCD8B0A2068430E30188031203880E0
+:104F1000002AF5D0087F9581801FC7B21AE020884B
+:104F20006168308048780A7800021043F080C878C1
+:104F30008A78000210433081B21C3846091D0AF0FD
+:104F40000EFB002F01D0002802D0002030717080AD
+:104F500008340A3628466D1EADB20028DFD1F8BDF0
+:104F6000CD8B0A2068430E30188032203880002A0A
+:104F7000F5D0087F9581401FC7B243E06168228861
+:104F80000878F2803279C30752085200DB0F1A43C7
+:104F9000FD231A408307DB0F5B001A43FB231A40F3
+:104FA0004307DB0F9B001A43F7231A400307DB0F6D
+:104FB000DB001A43EF231A40C306DB0F1B011A4321
+:104FC000DF231A408306DB0F5B011A43BF231A401D
+:104FD0004306DB0F9B011A433271C00970718A7856
+:104FE0004B7810021843308132463846C91C0AF00B
+:104FF000B6FA002804D00020B07000E008E030804D
+:1050000008340A3628466D1EADB20028B6D1F8BD68
+:10501000087FCD8B801E86B2304608306843103042
+:10502000188035203880002AF1D017469581103736
+:10503000E800D681C01900900DE0208838800098E3
+:10504000786032466168009815F089FA0098083453
+:1050500080190837009028466D1EADB20028ECD1AB
+:10506000F8BDFFB5099E1D460C46002A05D0607E9E
+:10507000FF300130D080E08B108100980078030071
+:1050800015F02EFD0C900715212A333C4A5F686805
+:105090006890087F1746082802D0032800D0FFDF59
+:1050A0000E20288030200AE00020B881FFBD087F54
+:1050B0001746042800D0FFDF0E20288031203080E2
+:1050C000002FF1D1FFBD087F1746042800D0FFDF75
+:1050D0000E2028803220F2E7087F1746022800D0F1
+:1050E000FFDF0E2028803320E9E7087F17460228DB
+:1050F00000D0FFDF102028803420E0E7087F17462B
+:10510000042800D0FFDF1020288035203080002FB9
+:10511000D8D00020B88112E0207F1746052802D0A1
+:10512000062800D0FFDF1220288036203080002F94
+:10513000C8D0E08BB8810020388200984088F88180
+:10514000FFBD087F1746072800D0FFDF0E2028800C
+:105150003720B4E714202880382017463080002AF2
+:10516000EED0E08BB8810020788200980078092882
+:1051700005D00A2809D00B280DD0FFDFFFBD087F1E
+:105180000C2800D0FFDF01200AE0087F0D2800D0A6
+:10519000FFDF042004E0087F0E2800D0FFDF052099
+:1051A000B873FFBDFFDFFFBD70B50C460546FCF7C9
+:1051B00012F9002804D00078222803D2082070BDFC
+:1051C000FA4870BD0521284608F002FD206000283D
+:1051D00001D0002070BD032070BDFFB585B00D4625
+:1051E0000746172069468881089802261446002839
+:1051F00005D108A93846FFF7D7FF002842D1002D76
+:105200000DD06846828900233146384603F0CAF83B
+:10521000002842D00898007800283ED105E0207888
+:10522000092823D00F282FD0FFDF002004A90190E8
+:10523000034600910290684682893146384603F061
+:1052400030F900281ED10898A760801D606003A96E
+:105250002046049A04F0FBF900282BD0030015F037
+:105260003FFC071E1C27272520222700684607260B
+:10527000828900233146384603F094F80028D4D1BF
+:10528000CA48801C09B0F0BD6846828900233146B7
+:10529000384603F087F80028C7D11120F2E7002034
+:1052A000F0E70820EEE7C148401CEBE70720E9E7FC
+:1052B0000320E7E70498009068468389042231467A
+:1052C000384603F07BFA0028DCD1002DDAD00899AB
+:1052D0000D70D7E730B587B01D460C46002A11D0B7
+:1052E000042369460B7013888B815288CA81A27887
+:1052F0008A7422880A8200236A462946FFF76DFFD6
+:1053000007B030BD1020FBE7F3B581B001980C4623
+:1053100000780826030015F0E3FB123B3737151120
+:10532000390A0A0A0A0A0A0A0A0A0A0A0A3B002C65
+:1053300000D1FFDF6078304360702AE0002CF9D1A3
+:10534000FFDFF7E701980521808887B2384608F02B
+:105350003FFC0546002C00D0FFDF002D00D1FFDF11
+:105360003946A81D04F06AF902F0FBFA040006D0E1
+:10537000607830436070678002F0D1FA0BE013214F
+:105380003846FDF7DDF911E0FFDF02E0FFDF00E066
+:10539000FFDF002C0AD06078000707D5932020702B
+:1053A0002046582218300199FBF7F0FE0020FEBD80
+:1053B00010B500200870881D04F03DF910BD0A46A4
+:1053C00010B50146901D04F041F910BD70B50546B9
+:1053D000052108F0FDFB040000D1FFDF2946A01DD8
+:1053E00004F02CF970BDF7B586B00C4605460020D8
+:1053F0006946088188806F880521384608F0E8FBF7
+:10540000060000D1FFDF002C03D0A7800020E08041
+:105410002081297E20461230C91E142700900B00DF
+:1054200015F05EFB0FFEF5F25E09A8676C7D2BB1EF
+:10543000C6E19090F2003078012800D0FFDFA88B01
+:105440006A46C1000E31918030211181002C13D0A9
+:10545000A08100200DE0C100327909190A74728818
+:10546000CA8182005319DA8B4A821A8C401C8A82C4
+:1054700080B2A1898142EED8E4E03078012800D0E2
+:10548000FFDFE88B6A46C1000E3191803021118127
+:10549000297F091FC9B20491002CEDD0A0810027FB
+:1054A0001AE0F8000219401900920390416A0E3286
+:1054B00004980AF054F8002804D0009900200874D9
+:1054C0000099C88103987F1C018C0098BFB241826B
+:1054D0000398418C00988182A089B842E1D8B1E05C
+:1054E00002A8009001AB224629463046FFF78CFC0B
+:1054F000A8E03078072805D0FFDF03E030780728E0
+:1055000000D0FFDFE88B69461230888036200881A2
+:10551000002C37D0A98BA1817188E18122E03078FD
+:10552000082800D0FFDFA88B6A4601460E30908025
+:1055300037201081002C25D0A1812046AA8B0E3067
+:10554000296A4DE0E88B6946123080B239228880A2
+:105550000A81002C72D0A98BA181287E102807D047
+:105560000221A173E98B2182EA8B296A009837E036
+:105570000121F6E702A8009001AB224629463046F9
+:10558000FFF7B0FC5EE03078092800D0FFDF694605
+:1055900038208F800881002C54D0A98BA181002055
+:1055A000608220820120A0734CE0000002300000E5
+:1055B00030780A2800D0FFDF288C694614308880B4
+:1055C00038200881002C3DD00421A173A98BA18132
+:1055D000E98B2182298C618220462A8C1430696AE9
+:1055E00014F0BDFF2EE030780B2800D0FFDF6946B5
+:1055F00038208F800881002C24D00521A173002041
+:10560000A081208260821DE01BE000E008E002A88B
+:10561000009001AB224629463046FFF722FD11E0FB
+:105620000D2069463A2288800A81002C06D001208C
+:10563000E08000202081207304E0FFE708990880C3
+:1056400015E0FFDF6846089980880880002C0ED09E
+:10565000684600892080684680886080287E03280C
+:1056600005D0102803D0112801D000203070002070
+:1056700008E6F7B556880F4682B015460521304634
+:1056800008F0A6FA040000D1FFDFA41D33462A4625
+:1056900039460094029804F060F905B0F0BDF7B502
+:1056A0008CB00D46144607A90C98FFF77DFD002825
+:1056B00012D1884E0127002C10D0032168460170BA
+:1056C0001021818208A802460690204605A909F00B
+:1056D0006CFF00280CD007200FB0F0BD08216846F1
+:1056E00001708581C68105218774C90201820BE0A2
+:1056F0000798A17801712188418068460521877447
+:10570000C90201828581C68102460121079B0C984E
+:10571000FFF763FDE0E708B501236A4693706E4B1F
+:1057200013800A4602236946FFF7D4FD08BD08B579
+:1057300001236A469370684B5B1C13800A4603235F
+:105740006946FFF7C7FD08BD00B587B000290CD03A
+:1057500002236A4613700B8893814988D181002304
+:105760000421FFF73AFD07B000BD1020FBE710B59C
+:10577000002903D00623FFF7ADFD10BD072010BDA3
+:1057800070B588B00D461446064607A9FFF70CFD14
+:1057900000280DD1002C0DD00621684601708581AE
+:1057A000C481079B02465C8007213046FFF715FD48
+:1057B00008B070BD0521684601708581F1E710B51C
+:1057C00088B000290BD007246B461C709A81049185
+:1057D00000236A460821FFF700FD08B010BD102025
+:1057E000FBE770B50024172288B0002914D00D788B
+:1057F0002B0015F075F90623050519041B23152246
+:10580000D21E93B2CA88002A02D08E68002E03D01E
+:105810009A4203D90C20CBE71020C9E7042D05D00C
+:105820008A88002A0AD101E00620C1E7012D11D0A3
+:10583000022D05D0042D18D0052D23D00720B7E761
+:1058400009236A4613704B889381CB88D38189687A
+:1058500004911DE00C236A4613704B889381CB881A
+:10586000D38189680924049112E00D236A461370DC
+:105870004B8893818B88D381CB88138289680A24D3
+:10588000059105E00E236A461370497811730B24C5
+:1058900000232146FFF7A1FC8AE700B587B00F235C
+:1058A0006A461370918100231946FFF796FC5AE768
+:1058B00000B587B000290BD002236A4613700B880D
+:1058C00093814988D18100230521FFF786FC4AE7AF
+:1058D000102048E7FFFF000002280000002803D046
+:1058E0008178012939D101E0102070470188FE4AF2
+:1058F000881A914233D01BDCFC4A881A91422ED080
+:105900000BDC00292BD00320C002081A27D0012865
+:1059100025D001210903401A07E001281FD00228E1
+:105920001DD0FF281BD0FF380138002815D116E004
+:10593000FF220132811A904211D008DC01280ED0DA
+:1059400002280CD0FE280AD0FF2806D107E0012942
+:1059500005D0022903D0032901D0002070470F2071
+:10596000704700B50B2826D009DC030015F0B8F805
+:105970000B1D2125251B25292325271F1B00112849
+:105980001BD008DC0C2816D00D281CD00F2814D0F2
+:10599000102808D10FE0822809D084280FD085284C
+:1059A0000FD0872811D0032000BD002000BD0520A6
+:1059B00000BDCF4800BD072000BD0F2000BD042062
+:1059C00000BD062000BD0C2000BD0D20800200BDE2
+:1059D00000B5030015F084F8070507050D0D090B48
+:1059E0000D00002000BD112000BD072000BD0820D3
+:1059F00000BD032000BD00780207120F04D0012A69
+:105A000005D0022A0CD110E0000909D10AE00009F2
+:105A1000012807D0022805D0032803D0042801D08C
+:105A2000072070470870002070470620704700B5B7
+:105A3000030015F055F8050406080A0C10000020B4
+:105A400006E0112004E0212002E0312000E04120A6
+:105A50000870002000BD072000BD38B50C460500C9
+:105A60004DD06946FFF7C7FF00281FD1694660780F
+:105A70000978C0084907C000490F084360706946AB
+:105A8000681CFFF7B8FF002810D16078C7210840D4
+:105A9000694609784907890E08436070A978490763
+:105AA000890F012903D0022905D0072038BD2178AC
+:105AB000DF22114002E021782022114321704107AA
+:105AC00007D0BF210840A9780907C90F89010843F9
+:105AD000607060788106490F0AD0A9784006C9062F
+:105AE000C90F400EC901084360708006400F02D103
+:105AF0006078400603D520784021084320700020BC
+:105B000038BD70B504460020088015466068FFF770
+:105B1000A4FF002815D12189A089814210D861688D
+:105B20008978C90708D001214902884208D8491C50
+:105B300014F08FFD298009E0FF21FF31884201D94F
+:105B40000C2070BDFF30FF3003302880002070BD76
+:105B500010B5137804785B08E4075B00E40F234377
+:105B60001370FD2423400478A407E40F640023434A
+:105B70001370FB24234004786407E40FA40023433C
+:105B80001370F724234004782407E40FE400234330
+:105B90001370EF2423400478E406E40F2401234328
+:105BA0001370DF2423400478A406E40F6401234328
+:105BB00013700078BF244006C00F234080010343C8
+:105BC0001370002906D00878C10701D1800701D5DC
+:105BD000012000E00020C0015906490E0843107062
+:105BE00010BD10B54A784378D208D2005C0702D0C5
+:105BF0005B075B0F05E09B065C0F01D05B0F00E0CD
+:105C000001231A434A70C72340781A4083065C0F69
+:105C100001D0580F05E0430702D04007400F00E0D5
+:105C20000120C00002434A7010BDF3B593B00D00CF
+:105C30000FD0139800280FD01221284614F0ECFC46
+:105C400003AAFF21012005F092FB002426463746D7
+:105C50007BE0102015B0F0BD0720FBE76846807D93
+:105C600001280BD16846818A0520C002081A0AD093
+:105C700001280AD002280CD003280CD0042C0ED006
+:105C8000052C0FD10DE0012400E002246846468A6D
+:105C900008E0032406E068460424478A02E005245D
+:105CA00000E006246846418A139881424DD12C7445
+:105CB000002E48D00DAA0EA9072002920191009053
+:105CC00010230022FF21304605F0F0FB00282AD1E6
+:105CD0006846808E2A46C0B20EA909F040FC002812
+:105CE00021D1AE81002F05E002290000012800002B
+:105CF0000330000027D00DA9072008AE02910090C4
+:105D0000132300220196FF21384605F0CFFB00281F
+:105D100009D16846808EF11CC01EC0B22A1D09F050
+:105D20001EFC002801D0032094E708A8817842785F
+:105D300008021043E881062C05D16846807DA872D0
+:105D40006846808A2881002084E703A805F018FBB4
+:105D5000002883D0FFF705FE7CE7F0B58BB00E4638
+:105D600005461C461746142103A814F057FC0120D1
+:105D7000694608730874119A4A748F82002C0AD0FD
+:105D8000A178C90707D069468875E0884883A0884C
+:105D90000883A068079001F0E4FD040024D065802A
+:105DA000172268460284002009A900910190034649
+:105DB00002900146284602F074FB002812D1684682
+:105DC000083670C008AA099B109904F0C2FD064667
+:105DD0006078000701D501F0A2FD002E0AD0304600
+:105DE000FFF7F6FD0BB0F0BD13212846FCF7A8FC29
+:105DF0000320F7E7099800906846038C04220021ED
+:105E0000284602F0DBFCEDE770B506468AB00020BC
+:105E10000D4607900590069003A9049007240246BA
+:105E200002910190102300942946304605F03EFB74
+:105E300000280DD108A804A9009102900194684699
+:105E4000838900222946304605F051F9002801D007
+:105E5000FFF787FD0AB070BD10B504F0D6FF10BD86
+:105E6000FEB500260546029600780C46082703007A
+:105E700014F036FE0CC5070F33D6686887A1C1A69B
+:105E8000B2C5002C00D0FFDF288980B201F0F5FEFA
+:105E9000B6E0A888042180B2009007F099FE019036
+:105EA000002C00D0FFDF0198002800D1FFDF01980F
+:105EB0000099083004F06BF901F053FD040007D09D
+:105EC0006078384360700098608001F028FD99E0A8
+:105ED00013210098FCF734FCA2E0002C00D1FFDF76
+:105EE0006088042107F074FE0090002800D1FFDFD5
+:105EF0000099002008802A79944620E0C3005B19AD
+:105F00009B6800936B461B781A0708D5DB0606D5FD
+:105F10006046C20050194038C08F088008E06B46C8
+:105F20005B785B0609D50871C2005019C0884880AB
+:105F3000607838436070022662E0401CC0B284453D
+:105F4000DCD85DE0E88869460880002C00D1FFDFDE
+:105F500068464078C00904D02878062805D005286E
+:105F60002CD06078384360704AE06088042107F0E4
+:105F70002FFE060000D1FFDF00203071A88870805E
+:105F80001CE0002C00D1FFDF6088042107F020FE18
+:105F90000090002800D1FFDF0098083004F087FF50
+:105FA0000121484002D1E879C00929D000986188D0
+:105FB0000226C180D5E7002C00D1FFDF0226D0E702
+:105FC000002C00D1FFDF022661880122204601F06B
+:105FD0009AFE01200290C4E7A889002C87B200D065
+:105FE000FFDF68680090288969468880012238466A
+:105FF00001F09DFE04E0002CB3D1FFDFB1E7FFDF2D
+:10600000002C0DD0607800070AD50298002807D12F
+:10601000842020702046582229461830FBF7B6F815
+:106020003046FEBD3EB50C0009D002AB6A460021E9
+:1060300005F09EFA002804D0FFF793FC3EBD102027
+:106040003EBD0321204614F0E7FA6846407801A9D6
+:106050004007400FFFF7EBFC00280BD168460079A2
+:1060600020706846407801A98006400FFFF7DFFCEA
+:10607000002801D003203EBD684600796070A278F8
+:10608000EF20024068464078C00900010243A27038
+:10609000F7200240684640784006C00FC000024327
+:1060A000A270F920024068460078800601D50220DF
+:1060B00000E00120400069460243097A5008400090
+:1060C000C907C90F0843A07000203EBD70B5064641
+:1060D000144608460D46204307D0002D10D0284610
+:1060E0000BF02DFC002812D101E0072070BD2946DD
+:1060F000304605F096FA002802D0FFF732FC70BD5A
+:10610000002C0BD020460BF01AFC002801D01020E8
+:1061100070BD21463046FFF785FF70BD002070BD81
+:10612000F7B50C460546007E22468AB00A32009238
+:10613000921E05920027811E0C323E4603920B00F0
+:1061400014F0CEFC08FC05FB34347EBEFDFB6888F1
+:10615000042107F03DFD0190002800D1FFDF0198E8
+:106160000088002802D052270726EFE0512710268A
+:10617000002C7DD06888A0800120A07101980022A9
+:1061800000790099C0004019C08BFFF79FFF0028DD
+:106190006FD101980079C0004019C08B208101980F
+:1061A0000079C0004019408CE081EBE0698C0191DE
+:1061B000062821D1E87FC0091ED008461430512797
+:1061C00086B2002CD5D0A88B00220099FFF77EFF65
+:1061D000002873D16888A0800220A071A88B20813C
+:1061E0000120A073288C208201986082696A019A3C
+:1061F000039814F0B4F9C5E008461230502786B26F
+:10620000002CB6D0A88B00220599FFF75FFF00286D
+:1062100054D16888A080A88BE080287E06280DD005
+:1062200002202073288CE081E87FC0096073019808
+:1062300020822046696A1230019ADAE70120F0E7ED
+:106240006888042107F0C4FC0290688C05900298CD
+:10625000002800D1FFDF0298083004F028FE012159
+:10626000484002D1E87FC00927D00598143001E0EA
+:106270007AE023E0512786B2002C76D06888A0808F
+:10628000A88B00220099FFF721FF002816D10220D9
+:10629000A071A88B20810420A073288C20820598EF
+:1062A0006082696A059A039814F059F902990020EE
+:1062B00008710298A98B418064E003200DB0F0BD05
+:1062C0006888FBF788F800906888042107F080FC54
+:1062D00003900098002800D1FFDF0398002800D128
+:1062E000FFDF0398FE49C088884202D05127142658
+:1062F00001E050271226002C37D06888A080502F4C
+:1063000006D00220A071287F059901F08BF939E0B1
+:10631000287FA11D01F086F90098002120308078A7
+:106320000090019103980B46428868880399FFF713
+:1063300014FD0028C2D125E001E022E018E0E9497F
+:10634000A88BC988814206D154270626002C0CD080
+:106350006888A08016E053270826002C05D068889E
+:10636000A080A88BE0800DE0FFE70C9806800FE08E
+:1063700055270726002CF8D0A88BA0800020A071FC
+:1063800000E0FFDF0C98002C068001D0278066809B
+:10639000002093E7D34900200870704730B587B0DC
+:1063A0000C4607F0E2FB0546FF2800D1FFDF002086
+:1063B000208020716080401EE08020462946083001
+:1063C00003F0D8FE01AA2946012004F0D0FF1024D2
+:1063D00015E06846C079000711D56846408929460E
+:1063E000FFF712FD6846C179FF232143C171017097
+:1063F000017A417040892946009A05F0E1F801A828
+:1064000004F0BEFF0028E4D007B030BD0A460146C4
+:1064100010B51046083003F0C2FE10BD70B5054639
+:10642000042107F0D5FB040000D1FFDF20462946F8
+:10643000083003F0ACFE70BDF3B58BB00D460B9881
+:10644000FAF7C9FF060004D03078222803D20820CA
+:1064500034E7A54832E704210B9807F0B9FB07465B
+:10646000002D02D0A88800280ED0012168460173B3
+:106470000221002401744474002D07D0A8886946C5
+:1064800008832868059003E0092017E70483059432
+:1064900001F067FA050028D00B986880172268463B
+:1064A000028409A8019400230090194602940B98D5
+:1064B00001F0F7FF0028CBD1384608300B99029045
+:1064C000203600950191B17808AA03A8099B04F031
+:1064D00040FA04466878000701D501F020FA002C44
+:1064E00009D02046FFF774FAE8E613210B98FCF771
+:1064F00027F90320E2E6099800906846038C0422FD
+:1065000000210B9802F05AF90021C943F980D5E621
+:10651000FFB585B00E9E77883846FAF75CFF0546D2
+:106520000421384607F054FB0446002D00D1FFDF5C
+:10653000002C00D1FFDF0834089869460394C1C1DC
+:1065400005A80DC82035A97803F058FE09B0F0BDA4
+:10655000F0B50446002099B007460E9010A8878138
+:106560000D46078187805F4968468F80078587844D
+:1065700087870786878508781646012808D002286D
+:1065800006D0032804D0042802D0082019B0F0BD9A
+:1065900020460BF0A1F9002856D128460BF09CF9B3
+:1065A000002851D160680BF0D5F900284CD1606803
+:1065B00000280AD060892189884203D8012252022A
+:1065C000914201D90C20E1E70E9015AA0FA92846A7
+:1065D000FFF797FA0028D9D1686880784007800FC4
+:1065E000022809D108A8407F8006400F04D02869FE
+:1065F0000BF0A5F9002827D10AA92069FFF72DFA89
+:106600000028C3D1206900280BD06078800708A833
+:10661000407A03D58006400F6FD002E08006400F1D
+:106620006BD108A8007A800610D508A8407A8006A9
+:10663000400F04D060680BF082F9002804D1606834
+:106640000BF088F9002801D010209FE70BA96069A2
+:10665000FFF703FA002899D16069002808D008A83C
+:10666000407B4107490F012947D18006400F44D0A4
+:106670000CA9A069FFF7F1F9002887D108A8007BD1
+:1066800080063AD408A8007C800636D4A069002889
+:1066900008D008A8407C4107490F01292DD1800668
+:1066A000400F2AD0E068002804D00078002824D0C9
+:1066B0001C2822D204AA611C2046FFF749FA08A828
+:1066C00040790127C108C900491C08A841716846E2
+:1066D00087730649818104AA033217A9286808E054
+:1066E000FFFF0000580300200230000003280000D4
+:1066F00003E008F05AFF002801D0072046E710A861
+:10670000007F14A9C01CC2B200200D92FF3200907D
+:10671000034602910190FF3203A80332099904F065
+:106720007EFD002852D110A9088A10902A89296973
+:10673000FD4801910092029010A98A8A6B8928680D
+:106740000F9904F06CFD01007ED12078C10601D4C0
+:10675000800626D5002010A908836069002809D189
+:106760000BA90FA8FFF73DFA08A9487BC008C00095
+:10677000401C487308A9087BC821084308A908736E
+:1067800069468F73E948888112AA16A902206D46CE
+:1067900007C50023E64A03A80B9904F040FD010059
+:1067A000D2D1E1480025001F818868464174090A5A
+:1067B0008174072104A86A4623C210A82A46FF2133
+:1067C000008A0D9B04F093FC002802D0FFF7C9F863
+:1067D000DCE66846007CC0092ED06846858408A89F
+:1067E00040790023C108C90008A8491C41716846C6
+:1067F0002921877309028181858608A8007DCC4AFA
+:10680000410860784900C007C00F014308A801751E
+:10681000FD20014060788007C00F4000014308A8B8
+:1068200001750DA9022001910090029503A8099914
+:1068300004F0F5FC010007D16068002829D0206928
+:1068400000280ED10AA900E080E00FA8FFF7C9F9DF
+:106850006078800705D408A9487AC721084008A9AC
+:106860004872B24968468773491E8181B0492089C0
+:10687000891E13F0EEFE0A4661680E9811AB009077
+:1068800002930191002303A80A9904F0C8FC0100B7
+:106890005CD12078C00727D068468586A06900288B
+:1068A00009D10CA90FA8FFF79CF908A9487CC008DA
+:1068B000C000401C487408A8017C4020014308A87F
+:1068C00001749A4968468773491C818113AA0DA9EE
+:1068D00002200292019100900023954A03A80C998E
+:1068E00004F09DFC010031D1E068002832D06846F8
+:1068F000858408A840790023C108C90008A8491C5C
+:1069000041718A4968468773891C8181E16808A8BA
+:106910000A78027549784175E068412241886846E5
+:10692000C186E068D200017908A80176E0686C466B
+:10693000C18808A84176090A81760DA9072023C4D9
+:1069400003A8099904F06BFC010003D0109800F033
+:106950007DFE1BE674480321001F0170002E0AD043
+:106960008088308010A88088708010A80089B0804E
+:1069700010A88089F080002008E630B501248BB093
+:1069800015460B46012802D002281AD104E06846B9
+:1069900005218473C90202E06846664984738181D7
+:1069A000002B11D000210182407C06AAC108C90039
+:1069B0006846491C417405A9184608F0F6FD0028F0
+:1069C00004D007200BB030BD1020FBE76A46127DD3
+:1069D00055480092801E06A9FF3201910290FF32B5
+:1069E000002303A80332049904F019FC002802D004
+:1069F000FEF7B7FFE6E74C48001F002D01D04188A5
+:106A0000298004700020DDE770B592B004460126AD
+:106A100008A8867048496846018410AA08A930462B
+:106A2000FFF7ABFF002840D120783F4DC00700247E
+:106A30002D1F00283BD01C21684613F0EFFD68464F
+:106A40000178202001436846017008A886703B4900
+:106A50006846018411940794817FF92001406846BB
+:106A6000891C817700200146684601770020014695
+:106A70006846417704218185C485018607A80A906C
+:106A800011A80D9008A809900EAA09A96846FFF759
+:106A90005FFD002809D16846008FE8806846808F36
+:106AA0002881401C68812C70002012B070BDEC80E1
+:106AB0002C8110A80088F4E7F7B51B490026091FB0
+:106AC0000A789EB0012A04D0022A02D0082021B000
+:106AD000F0BD4A88824201D00620F8E71F98824222
+:106AE00001D10720F3E7012218A812498271491C3D
+:106AF00010A8818400210182407CC308DB0010A81B
+:106B00005B1C4374684682810D4AC28118A8817358
+:106B100010A881851BA804906846C2820691FF21B7
+:106B2000017503A80EE000005C03002002290000AC
+:106B3000030200000128000001180000052A0000DF
+:106B4000FFFF000004F03EFC00242546274608AA6B
+:106B5000072103A804F039FC002810D082286FD147
+:106B6000002C6FD0002D6DD010A88480C58000212E
+:106B7000017518A8807C11AC012865D06DE008A8CB
+:106B80008079002F21D0012857D16846818CFE489A
+:106B900081421CD113AA0DA907206B4607C3684682
+:106BA000408C10230022FF2104F080FC002868D1D3
+:106BB00010A88089042801D006284CD16846818E0F
+:106BC0001F98814239D10F2081E7012835D16846CD
+:106BD000808C0521C902884202D0491C88422CD1F0
+:106BE000EA4841886846408C814201D1012700E093
+:106BF0000027002C01D0002D10D01F9988421CD1F5
+:106C000013AB0DAA07216E460EC6044610230022C0
+:106C1000FF2104F04BFC002833D101E035460CE0A5
+:106C200010A88089022801D0102814D1C0B21CAA53
+:106C30000DA908F094FC00280DD16846468C86E723
+:106C40001FE0FFE7052042E715A91CA8221D08F058
+:106C5000ACFC002801D0032039E710A8007D0023F8
+:106C6000001DC2B210A802752098009202900194F3
+:106C700019A8149904F0D3FA002802D1C34A0221BA
+:106C80001170FEF76EFE22E710B50B46401E86B06F
+:106C900084B203AA00211846FEF75AFF04AA07216E
+:106CA00003A802920191009001230022FF212046B7
+:106CB00004F01DFA04466846008A012800D0FFDF70
+:106CC0002046FEF74EFE06B010BDF0B5AF4F0446AD
+:106CD000387887B00E46032804D0042802D0082054
+:106CE00007B0F0BD04AA03A92046FEF70AFF05007D
+:106CF000F6D1606880784007800F02280BD1684683
+:106D0000407B8006400F06D020690AF018FE00285C
+:106D100001D01020E4E7208905AA6B46216907C34A
+:106D200069460A8A63892068039904F078FA002882
+:106D300002D0FEF716FED3E7002E02D06846808A06
+:106D40003080042038702846CAE738B50C00054664
+:106D500009D000236A46FF2104F00AFC002804D071
+:106D6000FEF7FFFD38BD102038BD69462046FEF70E
+:106D700074FE0028F8D1A078FF21C307DB0F284656
+:106D8000009A04F01DFCEBE77FB514460722019240
+:106D900003AD029500930A462388FF2104F0A7F96A
+:106DA000694689892180FEF7DCFD04B070BDF0B52D
+:106DB00091B00746002568460C46858600291CD000
+:106DC000E068002806D0A068002816D001886A462E
+:106DD000918605803846FAF7FEFA002810D0007830
+:106DE00022286CD3384606F0C0FE009004213846B5
+:106DF00006F0EEFE060006D104E0102011B0F0BD52
+:106E00006348FBE7FFDFA078012803D0022801D008
+:106E10000720F3E72088002808D0401C80B203AA8E
+:106E2000009904F0A4FA002829D102E05848401C37
+:106E3000E4E703A804F0A4FA69468A7D0D218902DB
+:106E4000012A09D16A46928A524B9A4204D1822879
+:106E500002D0002813D101E00846CFE7E0680028FF
+:106E600014D00DA9072202910192009069468B8EE1
+:106E7000A2882088FF2104F03AF9002802D0FEF70A
+:106E800070FDBBE76846A168808E08806846C07BBD
+:106E9000C00601D54048B1E70798002803D06846EE
+:106EA000008B022801D00320A8E717226946079823
+:106EB0000A87A1780078012903D0800711D408201F
+:106EC0009CE7C007FBD000230721384601F06AFA8F
+:106ED000002803D007200F90022005E02C48801CDA
+:106EE0008CE701200F90032008A9087021886846CC
+:106EF000818410A80090019502956846028F0023B6
+:106F000038460F9901F0CDFA002891D10836019743
+:106F1000029600950EAA072108A8109B03F019FD00
+:106F2000002802D0FEF754FD68E7109800906846EC
+:106F3000038F042238460F9901F040FC5EE770B5DC
+:106F4000064615460C460846FEF7C8FC002804D144
+:106F50002A4621463046FFF710FD70BD10B5FFF7F9
+:106F6000ABFD10BD70B51E4614460D0016D0002CAA
+:106F700014D06168002911D0002811D00349498834
+:106F800081420DD0072070BD022800005803002068
+:106F90000230000002290000013400001020F2E756
+:106FA0002068FEF79BFC0028EDD13246214628469A
+:106FB000FFF7CEFAE7E770B515460C0007D00028BA
+:106FC00007D0FE498988814203D00720DBE71020E3
+:106FD000D9E72068FEF782FC0028D4D12946204654
+:106FE000FFF773FECFE770B5054686B00E46144630
+:106FF00010460AF08EFC002861D160680AF0AAFCF5
+:1070000000285CD1EE48854204D02846FAF7E3F91F
+:10701000002814D0284606F0A8FD0546304601A9F0
+:10702000FEF703FE00280BD16846017D0F200B0000
+:1070300013F056FD0808060606060A0A0832E1485B
+:1070400006B0A0E70320FBE769468979012907D14B
+:10705000694689880322D202891AF1D00129EFD02A
+:107060006946897A012906D16946098915225202A1
+:10707000891A0529E4D96946897B01290DD1694618
+:10708000898929221202891ADAD00229D8D0032943
+:10709000D6D0042901D1D3E7FFDF6068002810D1E2
+:1070A00000236A462946304604F062FA002802D0DE
+:1070B000FEF757FCC4E768460078800601D410202C
+:1070C000BEE76188224630466368FFF75DFEB7E79A
+:1070D000F7B5074686B0144610460AF01AFC002899
+:1070E00002D0102009B0F0BD384606F03EFDB44E87
+:1070F0000546B74201D0FF2D0AD00146002303AA5E
+:10710000079804F035FA002804D0FEF72AFCE9E7D6
+:10711000AC48E7E76846007BC00601D5AA48E1E72E
+:1071200004A9072002910027009001976288334646
+:107130002946079804F0BAF9060013D160680AF0EE
+:10714000E8FB00280BD160680721029700910190AD
+:10715000238862882946079804F0A8F906466846FD
+:10716000008A20803046D0E710B5002907D0934B25
+:107170000A881B899A4202D89248401C10BDFFF72A
+:1071800016FE10BD10B586B004236C46A3828B4B4F
+:10719000DC88002C07D01B898B4201D2914204D994
+:1071A0008848401C8FE506208DE56B4619825A827F
+:1071B0000021009101911C800221997005A9029182
+:1071C00004A903916946FFF7F2FD7CE5F3B583B0AE
+:1071D0008126684606700F4608460AF07DFB0028A7
+:1071E0003ED10398FAF7F7F80190002812D0007802
+:1071F000222827D3002317221946039801F0D2F83A
+:1072000000280AD00421039806F0E2FC029000282E
+:1072100006D104E06B4805B0F0BD1120FBE7FFDFAD
+:107220000298083002F0D2FF05463878012803D0D2
+:10723000022804D00720EEE7A80703D504E0342095
+:10724000054201D10820E6E7B8793C1DC00709D006
+:10725000E088002806D0A0680AF03EFB002801D094
+:107260001020D8E720883F780021002811D0C21FC5
+:10727000FA3A0721112A1ED2130013F031FC110F24
+:107280000D130F240F1824160F0F242424240F2469
+:107290000F006846017018E0022F14D1684606708E
+:1072A0000846B8E7012FF9D00DE0EA0600E0AA068B
+:1072B000002AF3DA07E00246FF3A813A1F2A02D990
+:1072C0007D3A022AEAD86946087068460178019832
+:1072D0002346203080780090029801914288014630
+:1072E0000398FEF73AFD96E7FFB58BB000200190BA
+:1072F0001F4615460C460E460B98FAF76CF8002808
+:1073000005D00078222804D208200FB0F0BD2D4807
+:10731000FBE7B80801D00720F7E7032F00D10027CB
+:107320000B9806F022FC0890002C1FD0022D7DD374
+:1073300020460AF00FFB002806D160190090401E7D
+:107340000AF008FB002801D01020DEE7AD1EAAB22B
+:1073500021461B4804F00EFA014600981E38427F71
+:10736000037F10021843814271D1ADB21348B907AF
+:1073700002D50189491C00E0012189B20091F90779
+:1073800001D0078900E00E4F03AA0899009803F086
+:10739000EEFF0DE0F078B17800020843102856D8CF
+:1073A0000199091D401880B20190A8424FD82618B3
+:1073B000002E6ED070783278010207E0580300206A
+:1073C000FFFF00000230000001340000009811436C
+:1073D0008142DFD35DE0C07B01075AD5002C41D04C
+:1073E00001996618091D89B20991F178B3780902EB
+:1073F00019438C4610292AD809996144A94226D8F4
+:1074000071783378090219438A4220D1C00620D509
+:1074100009990AAA072061180292009101907078D8
+:107420003178000208436346002200E00FE008992B
+:1074300003F05DFE002802D0FEF793FA65E7F078CE
+:10744000B178000208436946098D884201D00B20BB
+:107450005BE7F078B178000208430999401880B2E0
+:10746000019007E0C00605D510460899FEF7CCFC50
+:107470000028E3D16946C87BEF2108406946C873FC
+:107480000870087C4870488AFF23009A089904F025
+:1074900097F803A803F074FF002803D16846428AD6
+:1074A000BA4298D904210B9806F092FB040000D14F
+:1074B000FFDF2288002A0CD00025072001950090CC
+:1074C0002B4621460B98FEF748FC0028B6D12580B4
+:1074D0001BE7002019E7F0B500248DB01F461646C3
+:1074E0000D46002A1DD0B90802D007200DB0F0BD0E
+:1074F000032F00D1002706F038FB0890FF2807D0A3
+:10750000002D10D028460AF01AFA002809D101E00F
+:107510005448EBE73188681E08180AF010FA002872
+:1075200001D01020E2E75049B80701D5488900E0B2
+:107530000120FA0702D04989491E00E04B4903AAFD
+:107540008FB2089903F013FF38E06946C97B090739
+:1075500034D509AB07210022029300910192434BDD
+:10756000089903F0A3FF002821D1002D21D06A46FD
+:10757000928C3188A2182819121D914234D3694681
+:107580004A8A0270120A42708A8C8270120AC27091
+:1075900009A90722001D0092029101906946488ABC
+:1075A0008B8C0022089903F081FF002801D0032072
+:1075B0009CE76846808C2018001D84B203A803F065
+:1075C000DFFE002804D0822806D0FEF7CAF98DE736
+:1075D0006846408AB842B8D9002C07D0002D10D098
+:1075E0003188A01C814203D20C207FE705207DE773
+:1075F000224629461D4804F0BDF829190870000AE2
+:107600004870A41C3480002070E710B504460AF0CE
+:1076100080F9002801D0102010BD13484089208037
+:10762000002010BD70B50C4605460E21204612F014
+:10763000F3FF00202080002D05D0012D01D0FFDFB9
+:10764000A1E4062000E00520A0719CE410B50C46E2
+:1076500003F060FE002800D0FFDF2046FEF781F92E
+:1076600010BD00000230000058030020FFFF0000A2
+:1076700010B50446007894B0022804D0012802D046
+:10768000FD4814B010BDA078002806D0032804D807
+:107690006078002801D0032801D90720F1E73F20B6
+:1076A000694608702078022801D0012000E00020FF
+:1076B0008870607800F090FD6946C01DC870A078A1
+:1076C000012800D1022000F087FD6946087160782A
+:1076D00000F082FD69464871A07800F07DFD6946A2
+:1076E00088712078012802D1C878401CC87009A987
+:1076F000684603F0C9FF002800D0FFDF0020C0E784
+:10770000FFB5DE4906468DB015468868C96803AAEC
+:1077100043C2687A297A4018C7B2002E0ED00024DE
+:10772000F01DC008C000B04200D0FFDF28880599D6
+:10773000401C80B20090002C02D007E00124EFE74B
+:10774000C0B207F0AFFE002800D0FFDF0098059917
+:10775000000108182969C01C0191810889003A4676
+:107760000591002C08D100200870019880B203F028
+:107770008BFC002800D0FFDF0599019823460818EC
+:107780000590A87A297A3A464018C1B205A800F0B7
+:1077900069FD0598C01C800880000590697A0091F9
+:1077A0002B7AAA7A002C00D0002001A906F0EAF872
+:1077B000002800D0FFDF694689880598169B40188D
+:1077C000C01C8008BC468000109F179A189900932F
+:1077D000019202910590002C00D000203B466246A9
+:1077E00007A906F05BFA002800D0FFDF6946898B05
+:1077F00005984018C01DC008C000821B0E99059056
+:107800000A60002C3ED101210907C96AC943090653
+:10781000090E03D19A490968491C03D09949401AB5
+:107820009949C86201232C220BA9984806F028F830
+:1078300000F0DCFC00211E22084601F0F3FEFAF7FE
+:10784000CDFC00F02BFFFEF7A5FD03AB00220521C8
+:107850008FA0FBF789F9002800D0FFDF28460C3005
+:10786000FFF7D2F8002800D0FFDFFF2189008A4807
+:1078700012F0D4FE854801211C3841760221817620
+:107880000621C17611B0F0BD10B5834CA07809284F
+:1078900000D3FFDF207870214843001900210171D7
+:1078A0004179F722C908C900C91C1140EF221140D3
+:1078B00041710121E170001D10BDF7B5054600784A
+:1078C000002700090C463E46052800D0FFDF287E31
+:1078D00000280AD0012810D0FFDF0298002C068073
+:1078E00001D0278066800020FEBD02270926002CDB
+:1078F00010D0A88BA080A87F0AE003271426002CB4
+:1079000008D06888A080286AE060A88C2082287F40
+:107910002072E2E702980680E5E70620704770B51E
+:107920005D4CE07800281BD0207870214843001976
+:10793000407900254007400F01191F204001091818
+:10794000087E401E08762078401CC0B220700928AE
+:1079500000D12570A078401CA07009F0ADFBE57047
+:1079600070BD4A481C38C07E002800D08CE77047A4
+:10797000F0B5464D00269BB07C3D686F00280BD0CB
+:10798000FFF7EFFF002876D07022696FF9F7FEFB52
+:10799000FFF7C5FF6E67F0E73C481C38407E0028C3
+:1079A00069D0FFF771FF0446384805F098FF606022
+:1079B000002800D1FFDF606803F0AFFE002811D07F
+:1079C0002046F9F7BBFF6078010706D5C008C00064
+:1079D000401C6070FFF7A3FFCFE72C48616805F0FB
+:1079E00087FFCAE72948616805F082FF01A800F017
+:1079F00072FC002871D168460321808806F0E8F8FF
+:107A000002906846808806F040FA074602980028EF
+:107A100000D1FFDF02984068002802D00078FF28DC
+:107A20005BD0FFF731FF04463846211D05F08CFE80
+:107A3000002800D1FFDF60680C90067068468088DF
+:107A40006080204600F017FF384605F0A8FE0028A9
+:107A500000D1FFDF3B21684601738188C18103A803
+:107A600005F0E5FA0DA804F0BCF86078010715D41C
+:107A7000C00619D41CE030E00530000054AC010011
+:107A8000001000100000002000050040B407002096
+:107A90006E52463578000000B8030020C008C000D0
+:107AA000801C6070FFF73BFF02990C98486064E708
+:107AB00002984068002807D00178491C0906090E81
+:107AC000017089D1FFDF58E700221146384600F0E7
+:107AD0007FFB002885D1FFDF4FE71BB0F0BD10B55D
+:107AE000FE4C0422A06020460C3012F038FDFC4809
+:107AF00001F02CFD607010BDF8490020087070473F
+:107B000070B5F84E0546706A94B00C46401C04D11E
+:107B1000B06AC0430004000C0BD0306AC007C00F2D
+:107B20002870706A12F08DFDB06A2071000A6071D1
+:107B300010E02B206946087009A9684603F0A4FDEF
+:107B4000002800D0FFDF0120287006220AA9204665
+:107B500012F005FD2878002803D06079C021084381
+:107B6000607114B070BDF0B5DE4C0646206895B06B
+:107B70000D4637460837401C08D16068401C05D1C7
+:107B8000A068401C02D1E068401C11D0206831463A
+:107B900012F057FD6068311D12F053FDA0683946A0
+:107BA00012F04FFDE06831460C3112F04AFD1DE045
+:107BB0002B206946087009A9684603F065FD002876
+:107BC00000D0FFDF08220AA9304612F0C8FC2B20A3
+:107BD0006946087009A9684603F056FD002800D0E0
+:107BE000FFDF08220AA9384612F0B9FC20692E46A8
+:107BF0000836401C08D16069401C05D1A069401CB2
+:107C000002D1E069401C12D02069294612F019FD0A
+:107C10006069291D12F015FDA069314612F011FDB1
+:107C2000E06929460C3112F00CFD15B0F0BD2B2493
+:107C30006846047009A903F027FD002800D0FFDF83
+:107C4000082209AF28460AA912F089FC6846047088
+:107C500009A903F019FD002800D0FFDF0822391D13
+:107C6000304612F07CFCE0E730B59F4C0546606F73
+:107C7000002800D0FFDF656730BD3EB50546032113
+:107C800005F0A6FF0446284606F0FFF80546002C3E
+:107C900000D1FFDF6068002803D00078FF2800D102
+:107CA000FFDF01AA6946284600F092FA00280ED1AB
+:107CB000FFDF0CE0002202A9284600F089FA002824
+:107CC00000D1FFDF6846007A002800D0FFDF6A4657
+:107CD0001078411E1170EDD260680199884201D17F
+:107CE00000206060804C6034A07E022800D3FFDF5B
+:107CF000A07E401CC0B2A076012803D1774840780E
+:107D000001F045FC3EBD70B50446784816460D4668
+:107D1000814200D1FFDF012E01D0FFDF70BD552071
+:107D2000207000202076A5830120A07770BD70B55B
+:107D300015460C460646FFF714FE00280CD05521C8
+:107D4000017046800121017621680162A188818449
+:107D50000577FFF7E4FD70BD13213046FAF7F0FC1C
+:107D600070BD70B505460C46084609F0D2FD0028E6
+:107D700001D0102070BD2846F9F72DFB002805D052
+:107D8000284600F0C7FE2070002070BD584870BD26
+:107D9000F3B5044687B000200690504801780029CA
+:107DA00002D0082009B0F0BD4C485249416020463D
+:107DB00009F0AFFD002867D1089809F0AAFD002856
+:107DC00062D1677A237AF818FF2870D82088FE28B5
+:107DD0006DD8002800D10A2020802169002901D116
+:107DE0000B21C90121616268002A15D0557890786D
+:107DF0006E00AD1928181578062675432818557990
+:107E00006E00AE191579B4466E00AD19D27806260B
+:107E100065447243551905E07800062238185A4324
+:107E200010180546FA00D21B1018DA00D21A1018E2
+:107E3000181886B21B207043059028461B22504319
+:107E40000290D82901D20920ACE7A07AB8422ED8F6
+:107E5000082F0DD8012B0BD807F081FC074609F03D
+:107E6000CCF83A1A207A617A521E43189A4201DA03
+:107E7000122097E7676801910090002F19D03846CB
+:107E800009F068FD002801D010208BE7B8787978D8
+:107E9000401839784218009901984018904206D14C
+:107EA00079793A798918FA788918884201D00720B7
+:107EB00078E70298019687B200970598029583B2F9
+:107EC000224603A90020FFF71BFC0448089A0399E7
+:107ED000406812680918914212D90DE0180000207C
+:107EE000717900008000001038070020FFFF0000BB
+:107EF000023000008812002008980160042051E739
+:107F00000097059922468BB20196029504A9FA4C76
+:107F1000FFF7F6FB04990398884200D0FFDF04982E
+:107F2000616840186060089908600120F34920707A
+:107F30000870069836E7F8B507460E46084609F079
+:107F4000E8FC002809D1384609F0F9FC002804D1E2
+:107F5000F81C80088000B84201D01020F8BDE84825
+:107F60008178002911D031880091417870225143E5
+:107F70000C182079241D0007000F334600222146EB
+:107F800000F0F6F9050004D015E00020308005204F
+:107F9000F8BD002F13D031880098814201D90C25FB
+:107FA0000DE0207833460007000F3A46214600F0E6
+:107FB000DFF9050005D00C2D01D0002030802846C7
+:107FC000F8BDCF484178491CC9B24170092901D197
+:107FD000002141708178CB4E491E81706078410745
+:107FE000490F01290BD0022903D0032917D0FFDF45
+:107FF000E5E7C006E3D46088FFF73FFEDFE7C1484E
+:1080000061681C3005F074FC707E401CC0B2707654
+:108010000128D4D1B848407801F0B9FACFE7F07E12
+:10802000401CF076CBE770B50D46044609F054FCD1
+:10803000002804D1284609F06CFC002801D010204B
+:1080400070BD2946204607F066FA70BD70B504463B
+:1080500015460E46084609F03FFC002804D1284684
+:1080600009F057FC002801D0102070BD022C03D06D
+:10807000102C01D0092070BD2A463146204607F059
+:108080006EFA0028F7D0052070BD70B514460D4675
+:10809000064609F021FC002809D1284609F039FCE0
+:1080A000002804D1204609F04AFC002801D0102005
+:1080B00070BD22462946304607F077FA0028F7D0EF
+:1080C000072070BD10B594B0044609F022FC0028CA
+:1080D00002D0102014B010BD0F2008A90873694603
+:1080E0000BA803F0D1FA0028F4D16846007A20707A
+:1080F00068464089608068468089A0800020E9E762
+:1081000070B505460C46084609F019FC002806D152
+:10811000002C09D0206809F0FCFB002801D01020B9
+:1081200070BDA088002804D021462846FEF784F9B7
+:1081300070BD092070BD70B504460D46084609F0B3
+:10814000CBFB002807D1601E1E2815D8284609F051
+:10815000C3FB002801D0102070BD022C01D90720DC
+:1081600070BD002C00D1FFDF6749A00040188038A7
+:10817000C16F2846884770BD204620381F28EED89A
+:1081800029462046F9F776FF70BD70B504460D46C6
+:10819000084609F0BEFB002807D1601E1E280ED835
+:1081A000284609F099FB002801D0102070BD012C51
+:1081B00001D0022C01D1062070BD072070BD2046E1
+:1081C00020381F28F9D829462046F9F7BEFF70BD90
+:1081D00010B505F02CF910BD032803D0022803D0F8
+:1081E00001207047062070470320704710B594B0F7
+:1081F000FAF7EAFE40484178806803F020FC3E48E8
+:1082000001240C300178012915D1302269460A7009
+:10821000C0788870002802D0012802D003E08C705A
+:1082200001E000208870084604F001FF002802D019
+:1082300009A803F0D6FC022008A9087148718871CA
+:1082400009A8FFF715FA002800D0FFDF08A804717D
+:1082500003214171817109A8FFF70AFA002800D0B3
+:10826000FFDF37E7F8B506460220002A02D05000AB
+:108270004018401DC7B23068C01C820892003260AE
+:10828000002B23D11E483B460A21283809F028FA42
+:10829000002408E0230012F023FC0A0608060A0A5C
+:1082A0000C0C06060611194804E0194802E01948AA
+:1082B00000E0194809F032FA054600E0FFDFA54268
+:1082C00000D0FFDF641CE4B20A2CE3D3306839012C
+:1082D00040183060F8BDF1B594B03A2008A9087391
+:1082E00069460BA803F0D0F9002800D0FFDF0B4E41
+:1082F00000246D4636E00000180000200800002031
+:10830000B80300209807002054AC0100E51E0000CF
+:1083100011870000B52F000059F200000430000062
+:108320002F19B87DC10706D0400704D4600040195A
+:10833000C08800F0E0FB1948807E002810D0B87D8E
+:1083400080070DD560004019C08800F04EFA002863
+:1083500006D060004019C18814980026018005E00D
+:10836000641CE4B268460079A042D9D830465CE487
+:10837000F8B5044600201880601E1D4616460F46BC
+:10838000052800D3FFDF0649A00040188038C36FDE
+:108390002A46314638469847F8BD00009807002025
+:1083A00064AC0100FFB581B015460646032105F017
+:1083B0000FFC0446304605F07CFD0C35AFB20025BD
+:1083C0002E460090002C00D1FFDF0098002800D13D
+:1083D000FFDF0298800000190189B94200D301250E
+:1083E000218CB94202D20299062900D301260499B0
+:1083F000A94304D0817A0222114381720AE00499D0
+:10840000B14307D0827A04210A4382722034A078D3
+:108410000843A0702846304005B0F0BDFFB581B0DC
+:108420000A9D174628460C3080B20E4600900B9CE1
+:1084300000232A4639460198FFF7B4FF002803D0ED
+:10844000B078C00906D01EE0072F01D01120E3E765
+:10845000FE48E1E7241F2570280A60700498A07088
+:10846000000AE070019805F024FD040000D1FFDF50
+:108470002D1D2046A9B204F0C9FE002800D1FFDF5F
+:10848000019803F04EFAB800801902890099511A38
+:108490000181062F03D2318C0098081A3084002005
+:1084A000BAE7FFB585B01E460F460F9D109C05F03C
+:1084B00000FD002833D0079A6946121D92B204F0DD
+:1084C0003CFE00282ED000980770684600890428DA
+:1084D00000D2FFDF0321019812F09EF8002211461E
+:1084E000019803F0D8FA002E03D068460089001FD7
+:1084F00030800E98002803D001980E99C01D0860A6
+:10850000002D02D06846008A2880002C04D02888DC
+:10851000002800D003982060002009B0F0BDCB48AF
+:10852000801EFAE7072F01D01120F6E7C748F4E7CD
+:10853000F0B50F46054687B016465088032105F072
+:1085400047FB040000D1FFDF002069460873A078D4
+:10855000400600D1FFDF042F5ED32978C807C0177B
+:10856000401C06D162786B789A4255D12278120766
+:1085700052D0142947DA012943D0122902D01329F5
+:1085800041D129E00C2F3ED1A1784906490E01299D
+:1085900039D02078012100090001401C2070687842
+:1085A00060706846017368792A7901021143684650
+:1085B000C181E879AA790102114368460182687A8B
+:1085C0002A7A0102114368464182E87AAA7A0102B6
+:1085D0001143684681821AE0062F14D120780009E1
+:1085E000000120707188012009F037F902216846E6
+:1085F0000173C91EC18168792A7901021143684655
+:108600001FE0062F0AD06946097B00291BD070881D
+:10861000324603A9F9F7D8FC07B0F0BD207800096D
+:10862000000120707188012009F017F902216846C5
+:10863000017368792A79010211436846C1810021DA
+:10864000C9430182E3E70028E6D076882746002464
+:1086500006A8009001942346062204210294304685
+:10866000FFF71FFF002800D0FFDF069801210170EF
+:1086700069784170022181700021C1700471210A62
+:1086800041710621009101900523042239463046AC
+:10869000FFF7C4FE0028BFD0FFDFBDE700206C4914
+:1086A00002464300401CCA520828FAD3704770B5EE
+:1086B0000C460021A17021780909090121700121CE
+:1086C00061700021616005F0F4FB050000D1FFDF5F
+:1086D000284604F030FDF5382085204600F027FBC1
+:1086E00070BD70B50D46032105F072FA040000D18B
+:1086F000FFDFA0786906C009C001490E0843A070D9
+:1087000070BD704710B50146012009F0A6F810BDF4
+:108710003EB58DB20321284605F05AFA040000D177
+:10872000FFDF2078694600090001207002200870F0
+:1087300048484880888000222846F9F745FC3EBD1D
+:10874000F7B50546002082B00746019028780C4610
+:108750000009012800D0FFDF287E032809D0FFDFB1
+:108760000498002C078002D00198208067800020A8
+:1087700052E6AE8B7020019030460A3087B2002C52
+:1087800019D06888A080688B2081E680A889001FA6
+:1087900080B200900246A96820460A30C91D11F037
+:1087A000DEFE00988642DBD9321A20180A30296989
+:1087B00011F0D5FED4E704980780D8E7FFB583B061
+:1087C0000F461C46164603210C9D039805F000FA3F
+:1087D000010007D033463A46019500940398FFF70D
+:1087E0001DFE19E71948801E16E770B505461948A1
+:1087F00086B0854214D0284605F047FB040000D11E
+:10880000FFDF2046694604F09FFF002800D1FFDF0C
+:10881000019CA079617900020843E41C052802D07C
+:10882000012006B070BD2E460321284605F0D0F980
+:10883000050000D1FFDF2079122811D1607821785E
+:10884000000208430C280BD1A87805E00430000092
+:10885000E4070020FFFF00004006400E022806D07B
+:108860000023062204213046FFF79CFDD9E70023B0
+:1088700006220521F7E7F8B5024680680179C3783A
+:1088800009021943837944791D0225439489938A07
+:10889000C01CE418241F8C4218D1042D17D0052DBC
+:1088A00022D0062D17D0402D10D30E461446284650
+:1088B00000F0DEF9082809D011202070032020766E
+:1088C0006583A6836078082108436070F8BD001DA9
+:1088D00000F0DAF9F8BD0093548813690A46011DC7
+:1088E0002046FBF7EAF8F8BD001DFFF721FEF8BDB2
+:1088F0007FB50D460646032105F06AF9040048D00D
+:1089000020780007000F012845D0002003A901901E
+:108910000346009102900C2205213046FFF7C1FD6D
+:10892000002834D103981221017061780523891C35
+:108930004170082181700021C17029880171090AE4
+:10894000417169888171090AC171A9880172090A96
+:108950004172E9888172090AC1720C21009101906B
+:108960001A4621463046FFF759FD002800D0FFDFA8
+:10897000F02300223146012008F0E0FE20780009B3
+:108980000001401C20706078801C6070002004B0E2
+:1089900070BDF048FBE71120F9E77FB50D460646AC
+:1089A000032105F015F9040006D020780007000F18
+:1089B000012803D00820EAE7E648E8E7002003A9F9
+:1089C0000190034600910290062205213046FFF7F0
+:1089D00068FD0028DBD10398132101706178417094
+:1089E000022181700021C1700571290A417106219F
+:1089F0000523009101901A4621463046FFF70EFDEF
+:108A0000002800D0FFDF207800090001207000203E
+:108A1000BDE7F3B585B00F460321059805F0D8F8FA
+:108A20000446059805F045FA019000200090002CBE
+:108A300000D1FFDF0198002853D1FFDF51E002A9E8
+:108A40000022019804F0F3FC03906846057A082D93
+:108A500000D3FFDFA80006190398318908300918F0
+:108A60003181062D02D2218C08182084072D03D1D4
+:108A70000098401CC0B20090B07AC0070DD02946C3
+:108A8000204600F0DDF8002807D1B07A4008400009
+:108A9000B0720598032D2BD0FFDFB07A810706D581
+:108AA000FD210840B0722946059800F0D9F8062D3E
+:108AB00017D8214620318878420712D5FB2630404E
+:108AC00088700025A8000119887A420705D5304032
+:108AD00088722946059800F0C3F86D1CEDB2062D8A
+:108AE000F0D338467F1EFFB20028A8D1009893E546
+:108AF000FBF781F8D1E710B5032105F069F8040010
+:108B000000D1FFDF204600F012F9A0788021084351
+:108B1000A07010BD10B5032105F05AF8040000D173
+:108B2000FFDF208D232111F094FDC0B210BD70B580
+:108B30000D46032105F04CF8040000D1FFDF062D9F
+:108B400000D9FFDF2946204600F07AF8002805D03A
+:108B5000A90009198A7A01231A438A7270BD10B5D7
+:108B60000446402801D2072010BD00F081F80828F3
+:108B700002D03120000210BD0021774802E0491CDC
+:108B8000082903D24A00825A002AF8D1082903D0C2
+:108B900049004452002010BD042010BD10B54028EB
+:108BA00001D2072010BD00F063F8082805D000218D
+:108BB000694A40001152084610BD052010BD70B52D
+:108BC00088B015460C00064607D0002D05D06088F9
+:108BD000402804D2072008B070BD1020FBE7218890
+:108BE000002929D000F044F8082827D003AA06A9B4
+:108BF00005A86B4607C3228804AB07213046FFF760
+:108C000050FC0028E7D16846028A2946059811F0F1
+:108C1000A6FC68462188008A814204D90A1A2918CC
+:108C2000039811F09CFC0598009023886288072126
+:108C30003046FFF7C3FDCEE70C20CCE70520CAE79E
+:108C4000072903D0454B4A009A5A00E0028D89005B
+:108C500008180089904201D2012070470020704717
+:108C600010B5032901D0FFDF10BDFAF785FF10BD55
+:108C700001460020384A02E0401C082803D2430085
+:108C8000D35A8B42F8D17047F7B50F4688B01446D7
+:108C900038460899FCF7EDFCC0B208283ED1002503
+:108CA0006846858203956088032104F091FF0600E1
+:108CB00000D1FFDF00213046FFF7C2FF00280ED1B0
+:108CC00017226846828203A801950295009000232E
+:108CD00060881946FFF7E5FB002800D0FFDF00940D
+:108CE00005AA3846039B0899FDF712FCC0B20300A1
+:108CF00011F0F6FE05041B1416141B006846808A4A
+:108D000000280BD003990191009060880423002271
+:108D10003146FFF783FB002800D0FFDF0BB0F0BD2A
+:108D20006078102108436070F8E7FFDFF6E710B5C0
+:108D300004462021083011F071FC084800214A0047
+:108D40008B001B19825A491C1A810629F7D9208DDC
+:108D5000A08410BD02300000E40700207CAC0100BC
+:108D600030B40121B848C9020160CD1005604A0342
+:108D70000260B64803681C02240A002304600468E9
+:108D8000240A24020460B2480468240A240204600D
+:108D9000B048012444608460AF4C23606360A360EA
+:108DA000AE4B19601D601A60AD4B19601A6001214D
+:108DB000016030BC704710B40121A348CA020260B0
+:108DC0000B0203600C060460A24841608160A54864
+:108DD00041680029FCD1A0490020086048608860F3
+:108DE0009E4802600360046010BC704701219B48EC
+:108DF000C9020160C91001607047002805D0012830
+:108E000005D0022805D1984870479848704798487F
+:108E1000704700B5FFDF002000BD30B50021954C44
+:108E2000954D964A8C4B002805D001281AD002286F
+:108E30001FD0FFDF30BD01200004A060A8601160DA
+:108E400019608F4BC2039A608E4A90607E4A00126E
+:108E500010608D480160854801608C4801608C4835
+:108E6000017030BD01204004A060A86051605960CD
+:108E700030BD01208004A060A8609160996030BD81
+:108E8000F0B594467B4A834F7B4D00240126002891
+:108E900005D001282ED002283CD0FFDFF0BD891E6E
+:108EA0000902090A0120000490603C6468606D4A70
+:108EB0001164012B1CD00021754B774A5970614613
+:108EC0001661764A546002249460042414616E4A48
+:108ED0003D3111606D490E60604A89151160694A23
+:108EE00050605F4801606649C00548601E70F0BD73
+:108EF0000121E1E701206A4E40046A4F012B04D1B1
+:108F00003464506068603964F0BD906034646860B7
+:108F10003964F0BD0120644E8004644F012BF4D10C
+:108F2000EEE750484068704770B54B4D2868002602
+:108F3000504C012806D1A068C00303D501200004CD
+:108F4000A0602E606868012809D1A068800306D55A
+:108F500001204004A0606E60012007F0A6FAA86816
+:108F6000012809D1A068400306D501208004A06033
+:108F7000AE60022007F099FA70BD10B54449087838
+:108F8000002818D001203E4AC00790603D4AC00B1F
+:108F900090602D4A001210603B4A00201060334A56
+:108FA00010603A4A106008704A78002A02D048706F
+:108FB00007F07BFA10BD0320FAE701203C490006C8
+:108FC00008607047012025490006086070470120AD
+:108FD0003749400508607047012020494005086076
+:108FE00070472D49012008611C4900020860704744
+:108FF000410A304AC005C00D5043FF300130514393
+:10900000400A0818704710B42B4C430B63431B0CE9
+:109010005C020C60274C6343C31A28485C02584327
+:10902000244B400D4343E31A0124DB03E4051B19E1
+:109030001B1613700A681018086010BC704710B532
+:1090400007F0F8FA10BD000080E100E008E400E05D
+:1090500018E400E000B0004040B1004080E200E0D1
+:1090600000E100E000B5004048B100404081004010
+:1090700044B1004000B3004040B3004040B5004060
+:1090800000F5014000830040408500400082004020
+:109090002800002000B10040008000400085004012
+:1090A00004B1004004B5004008B1004008B50040DC
+:1090B00000E200E0093D0000378600006F0C01006F
+:1090C00010B5EFF31080C407E40F72B6D8484178AA
+:1090D000491C41704078012801D108F00BF8002CA0
+:1090E00000D162B610BD70B5D14CE07800280AD12D
+:1090F0000125E570FFF7E4FF08F004F8002804D02C
+:10910000002007F0DEFF002070BDCA486571456091
+:10911000F9E770B5EFF31080C507ED0F72B6C44CD8
+:109120006078002800D1FFDF6078401E60706078B2
+:10913000002801D107F0E2FF002D00D162B670BD1A
+:1091400010B5BB48C178002904D000214171C1701D
+:10915000FFF7DFFF002010BD10B5044607F0D2FF77
+:10916000B349C978084000D001202060002010BD1C
+:10917000F8B5054641788278AD4800248171C27106
+:10918000047228782646002804D0012810D002282E
+:1091900010D0FFDF07F0C2FF002813D007F0C4FF94
+:1091A000A0420FD1204607F0C2FF0028FAD035E0D8
+:1091B0000124EFE7FFF784FF07F0A4FF0028FBD0AE
+:1091C0000224E7E701208107C8609B4F7E609B4A2D
+:1091D0009461984B02225A60886099480169C9439A
+:1091E000C906C917491C0091016910221143016188
+:1091F00000E020BF78680028FBD0204607F097FFEA
+:109200000028FAD00098002804D18D480269102166
+:109210008A4302618749022088607E60844FF87922
+:1092200000280FD0287800280CD107F06BFF0546E6
+:1092300008F038F98349002D02D0F960386101E067
+:109240003961F860002C01D03E71F8BD0120387101
+:1092500000F0CFF8F8BD10B5040000D1FFDF00200A
+:109260007449C0438860744A002111605160D16024
+:10927000116107F04DFF002805D06D490120C8702D
+:109280004878401C48702046FFF772FF10BDF8B5C3
+:109290000125AF077D61664CE07900281FD00128C9
+:1092A00003D0217A401E814219DA07F02BFF0646CF
+:1092B00008F0F8F8E179012902D9217A491C2172D4
+:1092C000002E01D0216900E0E168411A022901DA8B
+:1092D0008A1C10DC002E01D0206100E0E060FFF766
+:1092E000EFFE07F00FFF002802D03D61A57000E0FF
+:1092F000257000202072F8BDFEB54F4CA0680028F4
+:1093000001D0012600E000262068002801D00125B8
+:1093100000E000256068002801D0012700E0002758
+:10932000E068002800D0012001902069002801D0C9
+:10933000012100E00021009131462943384688434D
+:10934000019988430099884300D0FFDF304600260A
+:10935000002803D0A660012007F0B3FE2800344D9A
+:1093600012D026606879002803D06E71002007F0C3
+:10937000A8FE2878002807D007F0C4FE002803D0F4
+:109380000120A87081070861002F00D06660019855
+:10939000002808D0E660A878002800D1FFDFAE7072
+:1093A0002E70FFF7B6FE0098002805D026612879B8
+:1093B000002801D0FFF76BFFFEBD10B51C4CE07814
+:1093C000002801D107F09AFE012081078861A0786A
+:1093D000002809D0184CE068002803D107F0A7FE48
+:1093E0000028F8D10020E06000201249C0438860C6
+:1093F00010BDF8B50F48192787600124A507AC6197
+:109400000D4900200860C860086107F07BFE084E27
+:10941000002802D0B4702C6100E03470FFF750FED9
+:109420000649B0798863034847606C61F8BD000065
+:109430002C00002000030040000100400005004017
+:1094400000ED00E0FFFFFF7F8107C90E002808DA6A
+:109450000007000F083880082B4A80008018C06978
+:1094600004E08008294A800080180068C84000068F
+:10947000800F704710B50D20FFF7E6FFC4B204203F
+:10948000C043FFF7E1FFC0B2844200D0FFDF2049B4
+:109490000120486010BD01211E4A480310601E4B88
+:1094A00000221A601D4A51601D4A10601D4A116059
+:1094B00018498039086070470121164A4803106036
+:1094C000184A5160144A002111601549086070471C
+:1094D00010B511490868012801D0FFDF10BD0C4804
+:1094E00080680022C0B20A6007F026FF10BD10B5E8
+:1094F000094801680029FCD0FFF7EAFF012008496C
+:109500004003086010BD000000ED00E000E400E052
+:1095100000D5004080E100E000D1004000D30040D1
+:1095200080E200E000D00040012039494006086098
+:109530003849086038490A68FF231B029A4383129E
+:109540001A430A60324980390860704700B5024604
+:109550000420324904E0C3005B181B79002B07D0BC
+:109560000346401EC0B2002BF5D1FFDFFF2000BD37
+:10957000C300CA50002259184A718A7101220A7127
+:1095800000BD264A0021C00080180171704710B547
+:109590000446042800D3FFDF2048E1000C1820799E
+:1095A000012800D0FFDF6079A179401CC0B2814260
+:1095B00000D060710120164940068031086010BD5E
+:1095C00070B5154804250068144E0004800F144C33
+:1095D000022817D0FFDF15E02078C1008819027932
+:1095E000012A07D1427983799A4203D04279827164
+:1095F000705880472078401CC0B22070042801D3E6
+:109600000020207028466D1EEDB20028E4D170BD08
+:1096100080E100E080E200E018E400E0F4070020D0
+:109620004000002010B5FE4B586019721A80C90026
+:1096300010F0F4FF10BD00210180704710B500222A
+:10964000D2430280032008F008F910BD7047F0B53E
+:109650000E460446017801208840F24999B008403E
+:109660000090616815460888EF4A904206D0009A3B
+:10967000002A06D0EB4A521E104202D0012019B037
+:10968000F0BD009A10430880002D12D000202870F1
+:109690002178EA1C0027681C01920B0011F020FAC7
+:1096A00010F30E16233A59616F3CB4B08AB8F2F148
+:1096B000F0F320780B28EBD00420E0E7022129709A
+:1096C000A1890170090A4170032097E004212970E3
+:1096D000A1890170090A41700198E1890170090AA4
+:1096E000417005208AE006212970A1890170090ACC
+:1096F00041700199E2890A70120A4A70218A017147
+:10970000090A4171A28AE81DA16910F028FFA08A08
+:10971000C01D73E0082129702178082901D110218A
+:109720002970A1890170090A41700198E1890170CD
+:10973000090A41700520308020466A1D02A91030B8
+:1097400005F033FF00287DD169463088097A40183A
+:1097500054E00A212970A1890170090A417003208F
+:109760000BE00C212970A1890170090A4170019850
+:10977000E1890170090A4170052030809CE0A089D0
+:1097800084464000401C81B2308888425AD3052963
+:1097900058D30E202870002008E0236942009B5A0D
+:1097A000521953701B0A401C937080B26045F4D369
+:1097B0003180B9E09A48417A002973D0491E41723C
+:1097C000217B4068C9004518A988286808224018EC
+:1097D0000838216910F0C3FE02216846017100219A
+:1097E000417128680390A98868460181002101A879
+:1097F000FBF78AFD0020A880002E00D0308093E087
+:109800002978802211432970297840221143297038
+:1098100029788909890112312970A1890170090A01
+:109820004170E289E81C216910F099FEE089C01CB2
+:109830003080287841063FD5C00975D0012168469F
+:10984000017200E02CE0002141723188091D818104
+:109850000495E189019808180590001D069070484C
+:10986000017A68460177002102A8FBF74DFD074603
+:1098700030880C303080022F06D0002F54D065E0A5
+:109880003DE033E01CE05EE065486946097F4268E0
+:10989000CB00D218037A994202D29188002902D0D3
+:1098A000042753E02FE0417A491C4172156030884B
+:1098B00090800020308049E06168A089888033E092
+:1098C00029788909890116312970A1890170090A4D
+:1098D00041700198E1890170090A4170228A681D6E
+:1098E000616910F03CFE208A401D46E72878800917
+:1098F000800118302870207B687002207EE7606845
+:109900000188090401D4052720E0C088A189884284
+:1099100001D006271AE01E202870012030806068E0
+:1099200001884904490C0180009800280ED03C4869
+:1099300000220088A1688300032007F0FFFE616811
+:109940002078887007E00020308003276068009945
+:1099500002888A430280384691E6FFB59BB0249D79
+:109960000E46002805D0172803D82A882E4B9A4285
+:1099700002D107201FB0F0BD3278530601D4D209BE
+:1099800001D00820F6E700226B461A705A70144680
+:10999000327802AB1793431E19939BB21693970626
+:1099A000CB1CBF0E1893821E711C3B0011F098F85F
+:1099B000209011F066F074F0B4F0D6F0EFF0EEF015
+:1099C000EDF0ECF0EBF0F0F0EAF0E9F0E8F0E7F0C1
+:1099D00090F005287CD1042168460170A9780171B6
+:1099E000F078B278010211436846C1803179417044
+:1099F00070788006800E0C282ED009DC801E0300B3
+:109A000011F06EF80919661C662166246627660047
+:109A100012282AD00ADC0E2821D01028DAD121E021
+:109A200014080020FF710000FFFF000016281FD05F
+:109A30001828CFD11FE02878800701E02878400758
+:109A4000002845DA4FE128780007F9E72878C006B2
+:109A5000F6E728788006F3E728784006F0E72878CC
+:109A60000006EDE72888C005EAE72888C004E7E794
+:109A700028888004E4E728884004E1E72A789207F0
+:109A800026D50328A6D105206A46107048780978A3
+:109A900000020843908026E129784907F0D506287E
+:109AA00016D3707891B2012802D0022892D101E039
+:109AB000022700E010270622684602707278827141
+:109AC00000228280179AB01C1692BA1C18921EE0CF
+:109AD000BDE042780378801C17901202891E169808
+:109AE0001A431991028016983A46801C179910F073
+:109AF00036FD169A1798D219921C19996B46169230
+:109B00009A88C019C91B521C9A80189A89B28A4235
+:109B1000DFD900298DD1E6E028780007B0D5199863
+:109B20006A4681B20720107000209080701C921D40
+:109B300011E0437807781B023B431380C378877892
+:109B40001B023B4353806F46BB88091F5B1C001DF3
+:109B500089B2BB80121D0429EBD2DAE72978C90645
+:109B600075D5022873D30821684601700021C18091
+:109B7000717801718C4692B2B01C179919E091E08E
+:109B800098E086E06FE063E038E02DE021E015E04A
+:109B9000C4E0437807781B023B430B80831C4B6077
+:109BA0006346D21A6F46FB8860445B1C92B2FB800E
+:109BB00008319445EDD9002A49D194E028788006EF
+:109BC00045D5092268460270AA888280169AC2800A
+:109BD00012E0287840063AD50A206A461070A88814
+:109BE00090801698D08007E0287800062FD50B20AB
+:109BF0006A46107016989080029174E02988C90511
+:109C000025D5022823D30C20694608700020C8807F
+:109C100070780871844692B2B01C179914E04378AA
+:109C200007781B023B430B80C37887781B023B43BA
+:109C30004B80031D4B606346D21A6F46FB8860441D
+:109C40005B1C92B2FB8008319445E8D9B3E763E02E
+:109C50002988C90460D501285ED10D2168460170AC
+:109C6000A98881803FE02988890455D5052853D3E8
+:109C70000E2269460A70AA888A801899401F4A787D
+:109C8000097812020A436946CA800881701D039050
+:109C900029E0298849043FD501283DD10F20694694
+:109CA000087020E02A88120436D44A780B78120211
+:109CB0001A43EA8003282FD332789206920E1B2A89
+:109CC00026D011226B461A702A880123DB031A431F
+:109CD0002A804A780B78110219436A469180C01E87
+:109CE000D0801898029030788006800E1B2809D00A
+:109CF0001D2807D003201E9907F0AFFD2888C00B50
+:109D0000C003288068461D99FBF7FEFA204631E61D
+:109D100010226B461A70DCE70724F7E70824F5E702
+:109D200000B597B0032806D16A4610700191002152
+:109D30006846FBF7E9FA17B000BD0000FFB593B025
+:109D4000044600201D9E049015981C9D102708288D
+:109D500006D0E06901F0B0F8002809D03770CCE0F7
+:109D600028880921384328801F980227017016E0AF
+:109D7000E169012088710521E269C9029180E169E8
+:109D80008872E169F8480881E169002088732888B1
+:109D900020210843288011211F98042701701F9853
+:109DA0000225801C0390307810900A2030702046E5
+:109DB0001830119001F006FB00206FE01598102874
+:109DC00009D1022D07D06846828A04990398401A67
+:109DD0008270110AC1706846C08A1699884203D9F8
+:109DE000E249097A149106E0884204D110990029C9
+:109DF00001D0317021E003990870000A48701E9864
+:109E00000088401BC01B83B2FF20C01B984200D2B9
+:109E100003460398149AC0190CA90092019002916C
+:109E20002020015D6846C08A002201F03FFB3070AF
+:109E3000002806D0C0B2832862D06846C08A20833A
+:109E400045E00F98002805D0C848006800790A2826
+:109E500030D33CE06846008EC119C9B20491022D8E
+:109E60000FD01F99049A4978914203D16A46128C07
+:109E7000824209D0BD48049100680178032909D0C5
+:109E800027E008461F994870B848006801780429FF
+:109E900006D008E000790A281BD201200F9009E0C3
+:109EA0006946C98A81800399049808180390049828
+:109EB000281885B205AA1499119801F086FA00288D
+:109EC00005D11E980088401BB84200DB76E7022DC2
+:109ED0000ED01598102807D1049A03996846808AF5
+:109EE000891A8870000AC8701E980580002030709A
+:109EF0009E4800680078032802D0002017B0F0BD0B
+:109F00000220FBE7F8B50546406B00271346002802
+:109F100036D0491F8EB2698F954A914208D04218B7
+:109F200054791279240214430919891D8CB200E076
+:109F30000024A1192A8F083191421FD899785A78A4
+:109F40000902001911430170090A41701979DA7880
+:109F5000090211438170090AC1700671310A417109
+:109F60003246591D801D10F0FAFA6C87696B00208B
+:109F70000919B61D89190870487002E0092700E028
+:109F800083273846F8BD30B50B88048F9C4212D920
+:109F9000446BE0184478057824022C430BD04479B4
+:109FA000057924022C436404640CA41D1B190B8046
+:109FB0001060002030BD822030BDF7B588B000258C
+:109FC0006846058207275DE00398417802780E0213
+:109FD00016434179027908021043000452D40A98CA
+:109FE0000123068005A802905B02002200970195DC
+:109FF0003046099901F05AFA04004AD16846018AAC
+:10A000000183039841790279090211434378027868
+:10A010001C021443B4421ED10A041CD44B04012177
+:10A020005B0C890300950B4301970295C1788078FA
+:10A030000A0202432046099901F059F8040011D19F
+:10A04000039948790A79000210430122D203104390
+:10A050000871000A487103AA06A90898FFF793FF40
+:10A060000400CED0039900950197029548780978AD
+:10A070000002084369468B8A0022099901F037F8EB
+:10A08000822C06D103AA04A90898FFF77CFF0400DC
+:10A090009AD06846058209E003984179027909025D
+:10A0A00011434904490C0171090A417103AA04A929
+:10A0B0000898FFF768FF0028EED0822C02D02046D7
+:10A0C0000BB0F0BD0020FBE730B50446406B002527
+:10A0D00097B000280DD00B2268460270228F0281B3
+:10A0E000606B0391019000216846FBF7B9FE68465A
+:10A0F00005700020C04365636087258717B030BDB9
+:10A10000F8B50F460546696B0020069E14460029E7
+:10A110000FD0012B0DD1324639462846FFF74DFFAF
+:10A12000002806D1002C04D032463946284600F0DB
+:10A13000D2FEF8BDF8B5069E4D1D3788ADB2079C1E
+:10A14000AF4201D20620F8BD35801725257060701A
+:10A15000000AA070E270100A20710A461946601DBC
+:10A1600010F0FDF90020F8BD0128000020080020B3
+:10A17000FFFF000000220280C262831D0263C361F0
+:10A180004263531E4387028720300170704710B529
+:10A190000022D2430280042007F05FFB10BD30B5DF
+:10A1A00097B00D460446FFF78FFF208E002809D098
+:10A1B000012069460870E06A019000210295684616
+:10A1C000FBF74EFE0020E062206397E70146098816
+:10A1D00000200A0700D501200A06120F01D0022232
+:10A1E0001043CA0501D5042210438A0501D5102267
+:10A1F0001043490501D5202108437047FFB5A7B09A
+:10A200000700309D339C29981E46229016D0007876
+:10A2100041060FD48106890E1E2909D021884A05DE
+:10A22000520E0BD13288172A08D3FB4A914205D02F
+:10A23000C10906D08006800E122802D004202BB05F
+:10A24000F0BDF64928980872002018AA03901072F1
+:10A250006A46107404AA0A60319A4A6020AA908063
+:10A260009081229800781C908106681C0190781FCC
+:10A270001D902998890EC21C2492224620321B92DE
+:10A28000083A401C02920B0010F02AFC1FFEFE113F
+:10A29000FE1FFE8EFEFDFEFCFEFBFEFAFEFDFEF93D
+:10A2A000FEFEFEF8FEF7FEFEFEFEFEF6FE00032FAB
+:10A2B00076D102E018A9087236E3032028700199CC
+:10A2C00017220A7000224A70ECE2052FF0D1417883
+:10A2D000027808021043208320A98880249A5178AC
+:10A2E000127809021143618300287DD088427BD80F
+:10A2F00000202072E080401E6084029801F062F825
+:10A3000005202870A81C0190022000901BAA289903
+:10A31000029801F05AF8002867D118A8807C01281B
+:10A3200003D002206870102002E001206870022033
+:10A330002490002225A91CA805F037F900282BD16C
+:10A3400020A8007D2499814226D132880099801C62
+:10A35000511A814220DB10A8C18D01980170090AB1
+:10A36000417001991CA8891C01910099019A891CCE
+:10A37000009125A905F019F920A8007D01991BAAD3
+:10A38000091801910099081880B200902899029844
+:10A3900001F01BF80028CCD00098022825D081E2DB
+:10A3A00073E018A908727EE2072F6ED34178027815
+:10A3B00009021143218320AA9180249B5A781B789B
+:10A3C00012021A43628300290ED091420CD8012157
+:10A3D00021724179027908021043E0800020207345
+:10A3E000E06900F069FD01E098E0A9E000280ED1E5
+:10A3F000E169012088710521E269C9029180E16962
+:10A400008872E16986480881E16900208873F81F35
+:10A4100060842298C01D6062029800F0D3FF07207C
+:10A420002870681C009001200190002010A9C885A8
+:10A430002FE00198012814D0E0698079012830D0FC
+:10A4400000981E38417F007F090201430098017087
+:10A45000090A41700098801C00900198801C80B20D
+:10A46000019010A8C18D00980170090A41700098F0
+:10A47000801C0090019809E025E2A9E135E1D9E0CE
+:10A480001FE297E075E034E02FE2ABE0801C80B281
+:10A4900001901BAA2899029800F097FF002803D08A
+:10A4A00007E010A8818DD1E731880198081A0428A7
+:10A4B000BFDA0198012843D0E0698079012804D0EF
+:10A4C00010A8818D5448814206D110A8818D009832
+:10A4D0000170090A417009E000981E38417F027F2F
+:10A4E0000802009910430870000A48700198801C07
+:10A4F000D8E1072F01D0152F74D1417802780802D6
+:10A500001043208320A98880249A51781278090268
+:10A5100011436183002801D0884201D9012040E71E
+:10A52000012020720020E0802073052F0AD01D98A2
+:10A530002299E269C0B2491D05F011F8002801D046
+:10A540000A202EE70020C04360841AA8019023A9A6
+:10A550002298029603950091007800238206920EBD
+:10A5600020462899FFF7EAFB0390208B20A98880DA
+:10A5700099E1032FC0D1402220A98A814178027835
+:10A5800008021043208320A988801EAB289A0293DA
+:10A59000009231880022491E8BB21B99097800F085
+:10A5A00085FF18A90872002831D10B20287010A847
+:10A5B000008F3DE0052F9FD1802220A98A8141781C
+:10A5C0000278080210432083249984464A78097847
+:10A5D00012020A43628420A988801248824202D370
+:10A5E0000720DEE6ADE03F208002024362841FAB1D
+:10A5F0002899029300913088401E83B21B980178FD
+:10A60000604600F053FF18A9087200280CD0832878
+:10A61000AED10220DAE00000FFFF00002008002099
+:10A6200001280000010200000D20287010A8808F72
+:10A63000401C37E11C990C22C9095143C91CB9427D
+:10A6400004D91C9840067CD500202BE14278037881
+:10A650001002184320AA9080844622980078400671
+:10A6600009D505206A46107422980078C00905D0E3
+:10A67000002010743CE106206A4610742498289A41
+:10A680001F9000900023781A029383B21E900192CB
+:10A690001B9800220178604600F029FD18A9087275
+:10A6A000002269460A742299097849060DD5208846
+:10A6B000C00506D520A9208B8988884201D10020B9
+:10A6C0006062002018A90872ECE0832801D1022002
+:10A6D0000390FF21013120A88181808820831E986A
+:10A6E00060841F9860621320DAE0052F29D3417837
+:10A6F00002780802104320A98880218F002902D007
+:10A70000F94A914206D10A216A4611740121C943CE
+:10A71000218702E007216A46117422990022491D0F
+:10A72000289B0292009101221D99D20301931143AB
+:10A730008BB224994A78097812020A431B99097846
+:10A7400000E0EBE000F0D3FC18A908720022694693
+:10A750000A740122520220A98A81832808D0002885
+:10A7600015D0218FE04881427BD1002020879AE0DC
+:10A7700039462046229AFFF7C5FB18A9087200281F
+:10A7800001D0832823D120A88088208341E739463F
+:10A790002046229AFFF7B6FB18A90872002816D1A6
+:10A7A000618F606B009643180195D8789978000204
+:10A7B0000843844658791A790102114358781A7867
+:10A7C0000002104362469B1DFFF7B4FC03906AE051
+:10A7D0002298022F4078019072D1002801D00128E0
+:10A7E0006ED10820694608740198087521A8009068
+:10A7F0001B98002201782046019BFFF781FC6946E7
+:10A80000002248758A75002809D10198012811D0C5
+:10A81000002804D1B448218F401C81420AD0208FE7
+:10A82000002807D00020694608740120800220A972
+:10A8300088810EE004A83199FBF712FB03900020F9
+:10A84000694608740120800220A9888103980228A3
+:10A8500008D0A64800688079002806D018A9087298
+:10A860002AE061E0019820831DE00398002803D0CE
+:10A87000812018A908723DE021A800901B980122B0
+:10A8800001782046019BFFF73BFC18A9087220467F
+:10A890003299FFF719FC18A9087A002803D119206A
+:10A8A0002870012030806846007C002804D004A86D
+:10A8B0003199FBF7D5FA03900398002830D019E0BE
+:10A8C00016E00620F6E42078000711D5012F0FD1FD
+:10A8D000092168460174A18881820420329906F01A
+:10A8E000BCFF082120A88181AEE61C98400615D542
+:10A8F0000420039020A9208889890843208020A96A
+:10A900008889800508D5218F7748814204D129980C
+:10A91000E062278603200390039890E40420C9E4B2
+:10A9200018A8007A00280ED00120287022980078FC
+:10A93000687020A88088A870000AE87018A8007ABB
+:10A9400028710520308020A92088898988432080AB
+:10A95000E2E7FFB5A1B000201C902198012100780A
+:10A960002C9C81406248604A014010A88186208862
+:10A97000521C904203D0002904D0000702D50120C8
+:10A9800025B0F0BD249E00203070239910AA0988BC
+:10A99000118518AA10735549229A0A726A4605460B
+:10A9A000107404A808602A9848602198249E0178B1
+:10A9B000701C1E90204620300390012930D00229BF
+:10A9C00009D0032975D13078800980011D3030709D
+:10A9D00021988088A08021980078022804D13078BE
+:10A9E000800980011B3030701FAAF11C07206B46C4
+:10A9F00007C310A8008D0022C01E83B203980178FF
+:10AA00002198808800F052FD0028DBD121988188B0
+:10AA10001E980170090A417010A9888FC01CCDE0F2
+:10AA20002198417918A8017321980079012802D052
+:10AA30000228C7D144E120887F2212011040219FC3
+:10AA400010AA908602060837120F1BD00006800F4E
+:10AA500005D03888228B904201D0052597E1002946
+:10AA600010D1B878C0070DD0B868002207216B4616
+:10AA700007C30398FB880178BA88388800F037FB51
+:10AA8000002875D110A8808E80284DD006DC1028B3
+:10AA900010D020280ED0402894D12BE0FF38013868
+:10AAA00068D0FF3801387DD0FF38FF38022889D1BF
+:10AAB000D8E00FE1C00601D5082000E010201C906E
+:10AAC000042069460874002088821AA81BA91DAAC0
+:10AAD00003960092019102903B88072120461C9A20
+:10AAE000FFF72CF9A2E00000FEFF00002008002084
+:10AAF00009F800000A201C9018A8007B002836D115
+:10AB00001FAA07206B461E9907C310A8008D0022BC
+:10AB1000401E83B203980178208B00F0C7FC0146E9
+:10AB200018A801730B2018E00C201C9018A8007BBB
+:10AB30000028E4D11FAA07206B461E9907C310A85E
+:10AB4000008D628C401E83B203980178208B00F048
+:10AB5000ADFC014618A801730D20307010A8818F3C
+:10AB6000491C0185042168460174218B8182D2E051
+:10AB700061E0FFE73988208B81425CD112211C9172
+:10AB800018A9097B00291AD1616A002912D0B97865
+:10AB9000C90750D00023B96807220293019200919F
+:10ABA000FB8800E00CE00399BA88097800F09FFA6E
+:10ABB00018A9087313203070012010A90885AAE095
+:10ABC0003888218B884236D116211C9118A9097B1F
+:10ABD000002907D0606B002843D000206A4610800F
+:10ABE000D54F30E0616B002915D0B878C00722D16D
+:10ABF000608F01960B181AA80090D87899780202F5
+:10AC000058790A431D790102294358781D780002BA
+:10AC100028439B1D08E0B978C9070CD01AA90196F2
+:10AC20000091BA88F988BB68FFF784FA050072D0F2
+:10AC3000062D50D03FE005253DE00F4601AA6946AC
+:10AC40002046FFF7A0F96946628F09888A4201D041
+:10AC50000028F2D0618F626B002051180870487094
+:10AC6000678758E018201C9018A8007B002809D09E
+:10AC7000208B00281AD03888208320462B99FFF794
+:10AC800023FA48E02046183000900398237E01788C
+:10AC900001222046FFF734FA18A908730028ECD1E6
+:10ACA00019203070012010A90885E6E70525204607
+:10ACB0002B99FFF709FA6846007C032861D066E00B
+:10ACC000208801214902084010A98886FF38FF38F2
+:10ACD000022806D0062510A92088898E8843208066
+:10ACE00055E09549208F491E884200D0B5E61620D0
+:10ACF0001C902198806800280AD060632199898976
+:10AD000021870021C943618700210170417002E061
+:10AD10000020C043208710A8808E7F2109010246B1
+:10AD20008A430ED07823002204202B9906F006FDDA
+:10AD3000219810A90078A0702088898E084320806F
+:10AD400002E02188814321806846007C002805D0EC
+:10AD50007A48416804A8FBF783F8054618A8007BE9
+:10AD6000002814D01C98707001203070208BB070B7
+:10AD7000000AF07018A8007B3071052110A8018529
+:10AD800005E06E48416804A8FBF76AF8054620888C
+:10AD90004005400E25D1208E002822D0239910AAEC
+:10ADA0000988118524992A9B2B9A01930091039479
+:10ADB00002921AABE26A2299FFF720FA05460328AD
+:10ADC0000FD0012069460874E06A05902B98069020
+:10ADD000002104A8FBF744F8002800D00546002015
+:10ADE000208610A8018D239801802846C8E500B56B
+:10ADF00097B0042807D102206A4610700191002103
+:10AE00006846FBF72DF817B000BD10B54B4C037822
+:10AE100000222168012B02D0022B42D126E00B78C0
+:10AE2000002B01D0042B03D10A7122680321117079
+:10AE3000216883880A79D200921D8B5221680A7991
+:10AE4000D20008328918C2880A80216803890A79E9
+:10AE5000D2000A328B52428920680179C9000C3134
+:10AE6000425221680879401C08711EE00A748288E9
+:10AE70008A802168C288CA8022680189118122687B
+:10AE800041895181C1682068C1606168FAF7E8FFB3
+:10AE90000146022807D02068007C002802D1002942
+:10AEA00003D0812010BD832010BD002010BD406B59
+:10AEB000002800D0012070478178012909D100883D
+:10AEC0000521C902884202D0491C884201D10020D4
+:10AED000704706207047F7B586B0002468461546CF
+:10AEE0000F46848107261AE0049841780278090207
+:10AEF00011432980811D01960294009141790279C4
+:10AF00000B021343C178827809020A434178007822
+:10AF100009020843394600F0EAF8002806D104AADD
+:10AF200003A90698FFF72FF80028DDD0822800D16A
+:10AF3000002009B0F0BD0000FFFF00002008002045
+:10AF400010B58B78002B16D002789A4202D10B886C
+:10AF5000002B10D0401C8B789A4206D1437804789D
+:10AF60001B0223430C88A34205D08B79091D002BBB
+:10AF7000F1D1812010BD002010BD00B507282ED0D2
+:10AF8000002A02D0012A2ED103E049784907490F4F
+:10AF900002E049788906490F0B000FF0A1FD050476
+:10AFA000200A131A2400002A01D0032000BD022029
+:10AFB00000BD042813D0052811D006280FD0002882
+:10AFC0000BD00EE005280AD0062808D0022808D0A9
+:10AFD00003E0062803D0032803D0052000BD00208D
+:10AFE00000BD0F2000BD812000BD70B5137805465F
+:10AFF0000B70507848701446D8091ED0FE48807AED
+:10B00000A84204D8102003430B70002070BDA06834
+:10B01000EF2200781340E840C007C00E03430B70D6
+:10B020002078E1788007800D0843F4490FF011FB88
+:10B03000A06869430818401C70BD906870BD37B5A2
+:10B0400069468988118069460D79E9091BD0EA496A
+:10B0500093688C7A0121844209D8FE280FD1E80632
+:10B0600002D5A140491E00E00021197007E01C78BC
+:10B0700081408C43E906C90F81400C431C70107855
+:10B08000EF21084010703EBDF8B50746C81C800887
+:10B090000E468000B04201D08620F8BD082A01D9B2
+:10B0A0000E20F8BDD44D00202E60AF802881AA72FA
+:10B0B0003446E88016E0E988491CE980810610D40E
+:10B0C0008007E178800D0843CC490FF0C2FA206870
+:10B0D00000F0C3FA2989401880B22881381A8019F3
+:10B0E000A0600C3420784107E5D40020F8BDFFB5FE
+:10B0F00089B09F041646139DBF0C0193099800F078
+:10B100009EFA04000AD02078C00909D0BA48817A92
+:10B110000A98814204D887200DB0F0BD0120FBE7DA
+:10B12000224669460A98FFF760FF002106906846AC
+:10B130000172072D14D0012221462846FFF71DFF7A
+:10B140000028E9D1207840060AD50221684601721C
+:10B15000099981810188C1810682478212980590F0
+:10B160000198000404D500273E460125079709E011
+:10B170002078E1788007800D0843A04907900FF000
+:10B1800068FA0D460198400409D50798A84206D1EF
+:10B19000A07821798007800D0843B04201D3AE42E8
+:10B1A00001D90720B8E7B81980B20190A84201D9A7
+:10B1B0000D20B1E76846007A002804D002A8FAF70B
+:10B1C0004BFE0028A8D10798A84209D1A078019980
+:10B1D000800880008905890F0843A07001982071BC
+:10B1E0001498002800D007801298002815D00698DF
+:10B1F0003A46801912990FF0B2F9224669460A9828
+:10B20000FFF7F3FE69460878EF21084069460870A9
+:10B21000224600990A98FFF712FF00207CE7FFB54D
+:10B22000754D0C22E8882968504383B00C180D9F97
+:10B23000724905980FF00DFA0091049800F00DFA8C
+:10B2400029682A898E46611A0C31091894465118CA
+:10B250008AB2A988914202D8842007B0F0BD6A461C
+:10B26000167CF20903D0B20601D58520F5E7EA88FD
+:10B27000521C92B2EA800E9B002B00D01A80B206BC
+:10B2800001D5A76006E0604480B22881091A7046A3
+:10B290000818A0602246FE200499FFF7D0FE05980A
+:10B2A000E070009820712078059980088905800059
+:10B2B000890F0843A178009A890892058900920FA6
+:10B2C0001143A170042108432070039880786071B5
+:10B2D00003980088E08000202073F10901D0AC7A47
+:10B2E00000E00124B10600D5002700260EE007216A
+:10B2F0000020019102900097E88831460C9B069A45
+:10B30000FFF7F5FE0028A8D1761CF6B2A642EED3D0
+:10B310000020A2E7F1B5009800F091F9060002D0F4
+:10B320000025009C14E00120F8BD204600F087F9BC
+:10B330000746007831498007820DF87810430FF0F6
+:10B3400088F9386800F089F94019641C85B2A4B204
+:10B350002948C188601E8142E7DC00992648491EC1
+:10B36000C1800189491B018100203070F8BD00288F
+:10B3700004D0401E1080917000207047012070475B
+:10B3800010B5044601881C48C288914201D382202E
+:10B3900010BD00680C22514342185079A072D08829
+:10B3A0002081907811798007800D0843A081A078D2
+:10B3B000E11CFFF71AFE20612088401C2080E080FD
+:10B3C000002010BD012101827047F7B5054600201D
+:10B3D00084B0C043108068681746817868468170E1
+:10B3E000686801886846018000218171288A2C885C
+:10B3F000A04200D3044603E02C0800200102000014
+:10B400002C8234E0288A401C2882701D6968FFF76E
+:10B4100097FD002829D139889848814201D1601EC2
+:10B4200038806888A04227D3B07831798007800DB2
+:10B43000084302906946701DFFF782FD002814D171
+:10B4400069898E4881421BD0002231460598FFF75A
+:10B4500094FD002809D16A890298824205D1E968E1
+:10B46000B0680FF04FF800280AD0641CA4B2204640
+:10B4700000F0E5F80600C5D1641E2C828220ECE6BF
+:10B480007C807079B871F088B8803078F178800766
+:10B49000800D084378810298B8813946287A32466F
+:10B4A0000831FFF7A2FD38610020D6E6FFB585B070
+:10B4B0001D460F46059800F0C2F8040009D0207818
+:10B4C000C00908D06E48807AB84204D8872009B0F5
+:10B4D000F0BD0120FBE7079822468605B60D6946B8
+:10B4E0003846FFF782FD07460E98072816D000223F
+:10B4F0002146FFF742FD0028E9D1207840060DD50E
+:10B500000121684601710599018101884181868187
+:10B51000C58101A8FAF7A0FC0028D8D120782279AB
+:10B520008007810DE0780143A0788007800D1043EB
+:10B53000079A964207D0534A914204D3691E81422A
+:10B5400001DD0B20C3E7864201D90720BFE7801B3E
+:10B5500082B2AA4200D92A461098002800D0028060
+:10B560000F98002802D0B9190EF0F9FF0020AEE7BD
+:10B57000F8B51D4617460E4600F061F8040008D0E5
+:10B580002078C00907D03E48807AB04203D887208F
+:10B59000F8BD0120F8BD224639463046FFF725FDAB
+:10B5A000002D0BD02078E1788007800D08433549C5
+:10B5B000884201D2012000E0002028700020F8BD60
+:10B5C000F8B51E4617460D4600F039F8040008D0BD
+:10B5D0002078C00907D02A48807AA84203D887205B
+:10B5E000F8BD0120F8BD224639462846FFF727FD61
+:10B5F000FF2E14D02578E178A807800D0843214953
+:10B600000FF027F8002E03D1FF31FF31033189B24B
+:10B61000E170A80880008905890F08432070002088
+:10B62000F8BD10B50C4600F00AF8002805D0C18816
+:10B6300021804079A070002010BD012010BD10496C
+:10B64000CA88824207D3002805D00C2209685043DB
+:10B650000C38081870470020704703B50846694643
+:10B6600009788A0607D4C90904D00549897A414373
+:10B67000491C88B20CBD00200CBD0000FFFF00007B
+:10B680002C0800200102000010B50C4601F0CFFC90
+:10B69000002840D0204600F0A4FA002839D02278B3
+:10B6A0000E2A09D00F2A07D0022A05D0032A03D078
+:10B6B000102A2AD0FFDF1CE0A0781E2827D00FDC3C
+:10B6C0000C2820D008DC03000FF00AFA091321151A
+:10B6D00021211B1B17192100122818D1072010BD8A
+:10B6E000302814DD3A3803000FF0FAF9030F11097E
+:10B6F0001100002010BD0B4810BD042010BD0D200E
+:10B7000010BD0F2010BD082010BD112010BD03205A
+:10B7100010BDFFDFEDE7FFDFEBE710B500F061FAEA
+:10B7200010BD00000230000030B503460020024684
+:10B730000DE09C5C2546303D0A2D02D30020C0431D
+:10B7400030BD0A25684330382018521CD2B28A42D4
+:10B75000EFD330BD70B50D46144608E00A210EF057
+:10B7600078FF2A193031203A641ED177E4B2002CD8
+:10B77000F4D170BD10B5002310E0040A00020443A8
+:10B78000A0B2CC5C44402006000F60400407240CAB
+:10B7900044402006C00C60405B1C9BB29342ECD33B
+:10B7A00010BD000010B508F0D2FF042803D008F047
+:10B7B000CEFF052803D107F083FE00280BD109F046
+:10B7C00071F8032803D009F073F8032805D106F0B7
+:10B7D000D9FF002801D0012010BD002010BD70B598
+:10B7E0000C460546062102F0F3F96060002801D0FE
+:10B7F000002007E00721284602F0EAF960600028EF
+:10B8000003D001202070002070BD022070BDFEB565
+:10B810000C46064601A9FFF7E2FF00287FD16846E3
+:10B82000007900280BD006F026FFB04277D0002226
+:10B83000214630460BF098F800286DD12DE007F036
+:10B8400040FCB0426BD00022214630460AF0CDFECB
+:10B85000002861D1029D9820405D3035002804D138
+:10B86000687E002801D0012000E0002000902846DA
+:10B870002030417B002914D0817B890711D500211C
+:10B88000617001222270A170A680C27BA2712A8EF3
+:10B8900022816A8E628141733EE0029D3035687E6E
+:10B8A000E4E7304602F005FB070000D1FFDF384631
+:10B8B00001F06BFD0006000E08D0002161700D2123
+:10B8C0002170A680E0800120A07025E0304602F0C3
+:10B8D000DCFA070000D1FFDF009800281FD03846AF
+:10B8E00001F0EEFD00281AD068460079002807D143
+:10B8F00002988030C06B4188B14201D100210170B3
+:10B90000304606F020FE002060700A212170A070F1
+:10B91000A680A97EA17168760120FEBDFFE7002008
+:10B92000FBE71CB56946FFF75AFF002800D0FFDF90
+:10B93000684601F0C5FBF8480021806880304183EB
+:10B940001CBDFEB504460E46062002F0EFF8054683
+:10B95000072002F0EBF82818C7B20025BE1915E041
+:10B960002088401C80B22080B04201D3002020807B
+:10B9700080B2B84203D3B04201D20020CDE769467D
+:10B98000FFF72DFF0028C8D06D1CEDB2AE42E7D8FE
+:10B990000020C04320801220BFE738B50020C043FC
+:10B9A000694608800FE068460621008802F021F908
+:10B9B000044668460721008802F01BF9002C02D0DB
+:10B9C000002800D0FFDF00216846FFF7BAFF0028FB
+:10B9D000E9D038BD7CB5D1A103C9D24C0025019175
+:10B9E0000090A57001F065FB2146E5700420403908
+:10B9F000088710204887CC48C03460812573E081D7
+:10BA00000846203045740D7085730575C030057784
+:10BA10001D300522694605460EF0A1FD2946201F6E
+:10BA20000AF08CFE0A20A0700320E0702071607183
+:10BA30000E20A0710620E071207260727CBDF8B506
+:10BA4000B54C0D466060217006F066FDFFF7A5FF5E
+:10BA5000FFF7C0FF207808F025FCB2498431084682
+:10BA600081380F46064607F009FC60680AF02CFE94
+:10BA700020780BF06BFF284609F0BFFA39463046B4
+:10BA800006F02AFE60680AF0F4FF01F012FBA548F8
+:10BA90000021C170F8BD10B50124002A01D000209A
+:10BAA00010BD002904D0012903D00024204610BD78
+:10BAB00002210CF090FEF9E7FEB5040000D1FFDF93
+:10BAC000984D203D687C002809D00020607010212E
+:10BAD0002170A97CA170E97CE170687473E0914EDB
+:10BAE000403E3078002809D02C22B11C20460EF0B0
+:10BAF00036FD0E2020700020307064E0A87B002806
+:10BB00000AD00120E070E87BA070287C60700F20D4
+:10BB100020700020A87356E082480221CE300290A7
+:10BB2000FFF70FFF002800D0FFDF7E4FC037F889F6
+:10BB30000190062001F0FAFF0646072001F0F6FF0B
+:10BB40003018C6B2701CC0B20090F889B04214D14F
+:10BB50000021204607F06AFA002834D1287D002809
+:10BB600033D000266670132020701C21A01C0EF01C
+:10BB700053FD0220A0702E7525E0009988421DD14A
+:10BB80000021204606F050FD00281ED02078132802
+:10BB900019D1A0783C2816D1A088072102F018F806
+:10BBA000050000D1FFDF288806F0CDFCA088072122
+:10BBB00002F01FF8002806D0FFDF04E02146FFF75F
+:10BBC00026FE002801D00120A7E602210298FFF7F7
+:10BBD000B8FE002803D1F98901988142B5D100202F
+:10BBE0009BE669E710B508F0E5FA002800D0FFDF12
+:10BBF0000AF068FD002800D0FFDF07F003FB09F022
+:10BC0000E6F9002800D0FFDF0AF031FF002800D05D
+:10BC1000FFDF06F039FD002800D0FFDF0BF090FEBB
+:10BC2000002800D0FFDFFFF7B8FEFFF7D3FE06F0D5
+:10BC30005DFC02F019F901F03CFA3A480021C170AC
+:10BC400040380171012141710222C270017010BDA2
+:10BC500010B5344C403C2078002804D00A210E2036
+:10BC600001F0F4F910BDFFF79DFD002801D00C2074
+:10BC700002E001F01EFA00202071012060710A210B
+:10BC8000E170207010BD70B5264C0646403C20780F
+:10BC9000002804D039210E2001F0D8F970BDFFF73B
+:10BCA00081FD002801D00C2010E01E4DE878082806
+:10BCB0000BD20001001910223146443001F0D0F9B6
+:10BCC000E878401CE870002000E007202071012087
+:10BCD00060713921E170207070BD70B5114C06465D
+:10BCE000403C2078002804D00B210E2001F0AEF952
+:10BCF00070BD3078002803D0012801D012201FE049
+:10BD0000084D80352879082821D2FFF74BFD0028FF
+:10BD10000CD00C2014E0000044000020FFFFFFFFC7
+:10BD20001F00000078080020FFFF00003378297909
+:10BD3000721CFE4805F0BAFF2879401C28710020CB
+:10BD40002071012060710B21E170207070BD07200F
+:10BD5000F6E710B5F54CC83C2078002804D038210F
+:10BD60000E2001F073F910BDFFF71CFD002801D073
+:10BD70000C2003E0ED4900208839C87020710120B3
+:10BD800060713821E170207010BDE84810B5C838E6
+:10BD90000178002904D00F210E2001F057F910BDC1
+:10BDA000002101710E2181700F21C170FF2181716D
+:10BDB0000021C9430181DE4949680A7882728A8874
+:10BDC00082814988C18101214171017010BDD7492B
+:10BDD00010B5C8390A78002A04D03B210E2001F0A2
+:10BDE00035F910BDD14A00883832508101201073D6
+:10BDF00000220A7148713B22CA70087010BD10B54C
+:10BE0000CA4CC83C2078002804D02B210E2001F019
+:10BE10001DF910BD0821A01D05F070FA0020207149
+:10BE2000012060712B21E170207010BD70B5BF4CF6
+:10BE3000C83C2178002904D031210E2001F006F9F8
+:10BE400070BD00214156042910D000290ED0081DD4
+:10BE50000CD0001D0AD0001D08D0001D06D0001D0A
+:10BE600004D00A3002D01220207104E000250846D8
+:10BE700005F065FF25713120E070012060712070B0
+:10BE800070BD30B5A94D0446C83D28788DB0002856
+:10BE900005D02A210E2001F0D9F80DB030BD1022B6
+:10BEA0002146684601F0DCF81022A11804A801F030
+:10BEB000D7F868460DF0CFFA10222C46A81D08A925
+:10BEC00001F0CEF8002020710E20A0702A20E07032
+:10BED000012060712070E0E7F0B5944885B0C83863
+:10BEE0000178002905D03A210E2001F0AFF805B005
+:10BEF000F0BD8E480021C8388171FF300130408983
+:10BF00006946888002A9FFF76AFC0124002805D051
+:10BF1000002101A8FFF715FD002852D1684681884D
+:10BF20000180684602A90088FFF759FC002800D06C
+:10BF3000FFDF6846008801F0BCFF050000D1FFDF8D
+:10BF4000039E2846303601F0C3FA60400546684635
+:10BF5000767E008801F099FF070000D1FFDF3846A8
+:10BF600001F0AEFA60400246304610431ED06846EB
+:10BF700001886E485200C8388379AD005B001B18F9
+:10BF80001981877903461833F95C49084900314320
+:10BF9000F954FD27867939401143F154FB26827903
+:10BFA00031402943D1548179491C8171002168466F
+:10BFB000FFF7C7FC002804D16846018880888142C9
+:10BFC000AFD15A480021C838017144713A21C1707B
+:10BFD00004708CE770B5554C0546C83C20780028A5
+:10BFE00004D034210E2001F031F870BD08F0AFFB11
+:10BFF000052804D0284608F044F9002000E00C2071
+:10C000002071012060713421E170207070BD10B585
+:10C01000464CC83C2078002804D00E21084601F088
+:10C0200015F810BD424906220C31A01D0EF097FAFA
+:10C0300000202071012060710E21E170207010BD80
+:10C0400070B53A4C0646C83C2078251D002804D01F
+:10C0500032210E2000F0FAFF70BD3146002006F0BC
+:10C060000BFC287000280DD100213246084607F04D
+:10C07000CDF92870002805D12D48062231460C3014
+:10C080000EF06DFA012060713221E170207070BDF8
+:10C0900070B5264C0546C83C2078002804D03021D5
+:10C0A0000E2000F0D3FF70BD08F092F9002803D1F4
+:10C0B00009F01CFA00280DD0287808F0E1FF287854
+:10C0C00007F026FA00202071012060713021E17014
+:10C0D000207070BD0C20F6E7F8B5144C0646C83C3D
+:10C0E0002078251D002804D017210E2000F0AEFF77
+:10C0F000F8BD3146012006F0BFFB0127287000285B
+:10C100000FD13246012107F081F92870002808D1AB
+:10C110000648062231468C380EF021FA034888384A
+:10C12000877067711720E0702770F8BD0009002044
+:10C130004400002010B5FE480178002904D03021C9
+:10C140000E2000F083FF10BD122101710121417109
+:10C150003E22C270017010BDFEB5F54C054620347C
+:10C16000A07B002804D028210F2000F06FFF05E4F9
+:10C17000282020740121A173A8781A2824D00EDC6D
+:10C1800003000EF0ADFC162F2F2F2F2F212F2F2F56
+:10C190002F2F2F2F2F2F2F2F2F2F2121212F2A28E5
+:10C1A00020D00ADC1E3803000EF09AFC0C1C1C1C6C
+:10C1B0001C1C1C1C1C1C1C1C0E1C3A3803000EF002
+:10C1C0008FFC0411031103112888DA4A904209D820
+:10C1D0001F20E07328886946FFF701FB002803D081
+:10C1E000022014E0122012E068460078019F002827
+:10C1F0000FD0CE37019E00280DD0CF36684600F014
+:10C200004BFF002802D03878002806D00C20E073BD
+:10C21000DAE4B437EEE7B536F0E701203870A878F5
+:10C2200030700020E073684600F04AFFCCE4F0B5BF
+:10C23000BF4C0746207885B0002804D025210E2069
+:10C2400000F004FF53E6388802A9FFF7C8FAB84E99
+:10C250000021083600280CD0022020713160317195
+:10C26000E1800E20A0702520E07001206071207018
+:10C270003DE6039D28460830503501900020A87502
+:10C28000052230460199F4F781FFA87D0028F5D1F9
+:10C290003888E080E5E7FEB5A54C06462034A07B53
+:10C2A000002804D010210F2000F0D0FE8CE41F20C5
+:10C2B000E073102020740127A77330886946FFF7C8
+:10C2C0008EFA002810D1684600F0E6FE00280BD058
+:10C2D0006846019D007830350028019806D0E2308C
+:10C2E0000178002909D104E0022007E08030C06B0A
+:10C2F000F6E72035697B002902D03A20E07363E439
+:10C30000A97B89070DD104210170684600780028B7
+:10C3100004D1019831888030C06B4180684600F0BC
+:10C32000CFFE0020E0736F734EE4F8B5804D0646F3
+:10C330002878002804D01D210E2000F087FEF4E6A6
+:10C340001F202871012068711D21E970287008F0F4
+:10C35000FEF90C27042854D0052852D0B0791224B5
+:10C36000012801D000281DD13078002801D00128F3
+:10C3700018D1F079002801D0012813D170886E49B6
+:10C38000021F30248A420DD2B288121F8A4209D27B
+:10C390002887B0886887B0790024012804D0002855
+:10C3A0000CD013E02C71C0E6614840308078002842
+:10C3B00027D05F4A3C320121084602E05F4A002153
+:10C3C000012007F023F8040000D0FFDFF0790128F6
+:10C3D00001D0002802D107F05AF80446002C01D001
+:10C3E0001F2011E03078012802D0002803D00AE095
+:10C3F0000021022001E00021012007F058F8002868
+:10C4000001D02F7191E6002028718EE670B5484C5E
+:10C410002178002904D01E210E2000F017FE70BDE7
+:10C420001F212171012161711E22E27021700278A9
+:10C430001221012A01D0002A04D14078002803D01B
+:10C44000012801D0217170BD00260C25012A09D0D8
+:10C4500008F07DF9052803D007F05AFE002806D021
+:10C46000257170BD618F208F07F0BFFFF6E7267141
+:10C4700070BDF0B53249054603C985B02C4E039115
+:10C4800020360290B07B002804D021210F2000F03C
+:10C49000DDFD2CE51F20F073212030740120B073E6
+:10C4A0002A88254B111F3020994252D269880C1FCF
+:10C4B0009C42FAD291424CD8EA89224B911F994270
+:10C4C000F3D2298A8C1F9C42EFD28A42F3D86A8A1F
+:10C4D000FF23F4339A42EED8AA8A1A4C13460A3B39
+:10C4E000241FA342E1D2C9088A4232D9E98A2A8BA1
+:10C4F0009142E0D829791220002902D0012928D1BF
+:10C5000002E069790029F9D1297B002901D00129AC
+:10C51000F5D108F01CF905281AD008F018F90428FC
+:10C5200016D0307D002813D106F0CBFD06490DE072
+:10C5300038080020FF0E0000FD3F000050000020E2
+:10C540001CBD00007B0C0000FFFF0000884201D0F2
+:10C550000C20AFE0062104A801F00FFB04004CD032
+:10C5600003210BF077FEF74F1B22F8780090BB7881
+:10C570002088114601F0D5FB042840D0002800D0C7
+:10C58000FFDF208805F0DEFF20460D300090208878
+:10C5900001900421009804F0B1FE019900980BF07D
+:10C5A000F1FE204611300190E7A0006800900321C1
+:10C5B000684604F02CFE00206946019A0B5C135477
+:10C5C000401CC0B20328F8D3288A6080688AA08003
+:10C5D000A88AE0807979387907F0CCFE01462046B8
+:10C5E00007F0EFFE2046002720308775C775687971
+:10C5F00000280DD001280FD10CE009205AE0208836
+:10C60000062101F0F6FA002800D0FFDF072051E0F4
+:10C61000677601E00120607620460622A91D1A30C7
+:10C620000DF09DFF2046052202A90830F4F7AEFD6B
+:10C630000120C421085569460F700146684604F080
+:10C64000E6FD694608784107C206490F920F800649
+:10C650008918C00F081869460870401D20760928FF
+:10C6600001D208302076002120460BF0F3FD287B14
+:10C67000002803D0012805D0FFDF29E00021B34ABC
+:10C68000012008E0AF48C0388078002814D0AD4AB7
+:10C690000121C43A084606F0B9FE002818D02088C7
+:10C6A00005F051FF2088062101F0A3FA002800D0F0
+:10C6B000FFDF1F20F0731AE4208805F044FF208874
+:10C6C000062101F096FA002800D141E7FFDF3FE79D
+:10C6D0002879012801D0002803D106F0D8FE0028CF
+:10C6E0000CD12146032006F0E2FE002806D16A881C
+:10C6F0002988204607F0FEFD00280AD0208805F092
+:10C7000022FF2088062101F074FA0028DDD0FFDF27
+:10C710001EE7A0342776F7735BE438B58C4C20789D
+:10C72000002804D022210E2000F090FC38BD1F20EC
+:10C730002071012565712220E070257008F007F84E
+:10C74000052802D00C20207138BD002020716846D9
+:10C7500007F07EFE0028F7D10098008805F0F3FE70
+:10C7600000980621008801F044FA002800D0FFDF7D
+:10C7700077482030057575480C380078FCF707FFBE
+:10C7800038BDF8B5724E05462036B07B002804D07F
+:10C7900023210F2000F05AFCC7E41F20F073232050
+:10C7A00030740120B0736A886A4B911F302099421F
+:10C7B0004BD2A9888C1F9C4247D28A4245D8EA882E
+:10C7C000FF23F4339A4240D82A89624C13460A3B2D
+:10C7D000241FA34239D2C9088A4236D96989AA8955
+:10C7E000914232D82888062101F0F2F90227044646
+:10C7F000002809D000F041FC002805D08034E06B0F
+:10C800000178002906D101E0F7738EE4216D0978E3
+:10C81000002901D03A2018E005218171E06B002148
+:10C820000181E26BA8885081E26BE8889081E26B1D
+:10C830002889D081E06B028943899A4204D88279A1
+:10C84000082A01D89A4202D31220F0736DE42A8894
+:10C850004280E06B0770F17367E4FEB53C4C05461F
+:10C860002078002804D024210E2000F0EFFB7EE485
+:10C87000012666712420E070267028460BF0A0FD8A
+:10C88000002801D0002000E0122020710028EED105
+:10C890002C4F0522203F38463E7729461D300DF0AB
+:10C8A0005EFE002038776946062001F01DF9002859
+:10C8B00000D0FFDF684601F0F3F8002814D1684685
+:10C8C000878868468088062101F082F9050000D13A
+:10C8D000FFDFC0352E71684601F0E2F8002803D171
+:10C8E00068468088B842ECD1002020713FE470B5E2
+:10C8F000174C06462034A07B002804D026210F20A8
+:10C9000000F0A4FB70BD1F20E073262020740120DE
+:10C91000A0733088062101F05BF9050009D000F012
+:10C92000ACFB002805D08035E86B0178002906D1E2
+:10C9300001E0022016E0296D097800290CD03A2088
+:10C9400010E00000380900201122330050000020C0
+:10C95000380800207B0C000005210170E96B30884D
+:10C9600048800020E07370BD10B5FA4C2078002894
+:10C9700004D006210E2000F069FB10BD00202071BC
+:10C980000E20A0700620E0700821A01D0DF044FECE
+:10C99000A17901200143A1716071207010BDF8B52B
+:10C9A000EC4C07462034A07B002804D02C210F201B
+:10C9B00000F04CFBC3E41F20E0732C202074012006
+:10C9C000A0733888062101F003F906000AD000F0B0
+:10C9D00054FB002806D035468035E86B01780029E5
+:10C9E00006D101E002201FE0296D0978002901D05D
+:10C9F0003A2019E060363179002917D00822B91C95
+:10CA0000001D0DF0ACFDE86B79898181E86B39463A
+:10CA100010220C310E300DF0A2FDE96B03200870DE
+:10CA2000E96B388848800020E07388E40C20FBE73D
+:10CA300070B5C84E044630780C25002804D0182163
+:10CA40000E2000F003FB70BD07F02CFF03285BD025
+:10CA500007F02EFF032857D06079002801D0012865
+:10CA60002DD1A079002801D0012828D1A07B002851
+:10CA700005D0012803D0022801D003281FD1607BF4
+:10CA800000281CD0C0081AD162880120800382428D
+:10CA900002D82188814203D9207901280FD119E0D9
+:10CAA0002079002806D0012814D0022805D00328B8
+:10CAB00005D102E0202A0BD30CE0A0290AD220796C
+:10CAC000042805D12088202802D36188884201D912
+:10CAD000122519E09F48217920308175607900285E
+:10CAE00002D0012804D00FE09B4A0021204608E034
+:10CAF000984840308078002806D0964A01213C3280
+:10CB0000204605F045FE054601203571707118215B
+:10CB1000F170307070BD10B58E4C2178002904D0B2
+:10CB20001A210E2000F092FA10BD01781F2902D9B7
+:10CB30001220207106E0002121710278411C10466C
+:10CB400005F0C0FE012060711A21E170207010BD57
+:10CB500010B5804C2178002904D020210E2000F04F
+:10CB600075FA10BD01781F2902D91220207106E044
+:10CB7000002121710278411C104605F095FE01202C
+:10CB800060712021E170207010BDFEB5714C2178DC
+:10CB9000002904D01B210E2000F058FA67E601217D
+:10CBA00061710C21217100780026012803D0002832
+:10CBB0006BD012205CE005F0B9FD002859D0654823
+:10CBC0002030807D002816D0012814D0042812D0EF
+:10CBD00007F06EFE002875D107F064FE002803D030
+:10CBE00007F060FE02286DD1002008F04CFA002802
+:10CBF00049D0FFDF47E007F055FE002862D107F07B
+:10CC000057FE00285ED105F036FD5449884259D1BF
+:10CC1000072101A800F0B1FF4F4905460C39886093
+:10CC2000280000D1FFDF032128460BF0B9FA28467F
+:10CC300005F0E2FE4A4F797A387A07F03CFE014669
+:10CC4000284607F05FFEF87900901B22BB79288800
+:10CC5000114601F066F800280CD0042800D0FFDF50
+:10CC60002888072100F0C5FF002800D0FFDF07203B
+:10CC7000207127E0288805F065FC284608F003FAB3
+:10CC8000002800D0FFDF26711CE007F00BFE032810
+:10CC900003D007F00DFE032814D107F006FE054669
+:10CCA000002008F01DF900280CD12671002D09D0B4
+:10CCB000288805F048FC2888072100F09AFF002802
+:10CCC00000D0FFDF1B20E07001202070CFE5F8B519
+:10CCD000204D06462878002804D02D210E2000F093
+:10CCE000B5F959E53088072100F072FF01270028C7
+:10CCF00022D00446C034617C00290AD13C21095C61
+:10CD00000F2901D0102904D1FF210531095C002928
+:10CD10000AD00C2028710E20A8702D20E8703088D1
+:10CD2000E8806F712F7037E51022B11CD2300DF002
+:10CD300016FC67740020EDE70220EBE770B5054CA8
+:10CD40000546207800280DD02E210E2000F07EF917
+:10CD500070BD00003808002050000020FFFF0000D8
+:10CD6000380900202888072100F032FF022200281D
+:10CD700010D00146C0314B7C002B05D12030007F04
+:10CD80000F2804D0102802D00C20207103E04A7430
+:10CD90000020FAE722710E20A0702E20E070288873
+:10CDA000E080012060712070D2E77CB5CB4C054655
+:10CDB0002078002804D037210E2000F047F97CBDF0
+:10CDC00028886946FEF70BFD002807D00220207155
+:10CDD000012060713721E17020707CBD01987F22B5
+:10CDE000014630300272427200228272A8782031ED
+:10CDF0000872E8784872287988722271E8E71CB5D1
+:10CE0000B64C2178002904D013210E2000F01EF921
+:10CE10001CBD00886946FEF7E2FC002801D0022014
+:10CE200005E001992820405C012802D00C202071E7
+:10CE300006E0382000222271405C20720888E080E1
+:10CE4000012060711321E1700E21A17020701CBDC2
+:10CE5000F8B5A24C05462078002804D035210E20D4
+:10CE600000F0F4F898E4A878002801D0012804D153
+:10CE7000A888FF21F531884201D912202071288825
+:10CE8000072100F0A5FE0126002813D00146002747
+:10CE9000C0310F72AA884A81A0300671AA78012A8F
+:10CEA00000D000220A724079002801D008F007FA69
+:10CEB000277101E00220207166713520E070267034
+:10CEC0006AE4F8B5854F04463878002804D03C2140
+:10CED0000E2000F0BBF85FE42088072100F078FE08
+:10CEE00006002DD0B58864886800F2887188401CDF
+:10CEF000844217D37A484143800050430DF0A9FB88
+:10CF0000401EFF2180B2F531884200D90846844294
+:10CF100000D22046691C401C0DF09BFB6D1C684331
+:10CF2000401E85B2F020805D002800D13584FD8050
+:10CF300000203871012078713C21F97038702BE4A1
+:10CF40000220F6E770B5654C05462078002804D02D
+:10CF500033210E2000F07AF8FAE607F0A3FC00284F
+:10CF600001D00C2018E02978002911D00A290FD00F
+:10CF700014290DD01E290BD0282909D0322907D019
+:10CF80004B2905D0642903D0FF2901D0122003E0EA
+:10CF9000284608F035F90020207101206071332106
+:10CFA000E1702070D4E610B54C4C2178002904D0F3
+:10CFB0003F210E2000F04AF810BD002121710178B8
+:10CFC000002909D001290BD01220207101206071A5
+:10CFD0003F21E170207010BD0422411C414803E054
+:10CFE000411C40480422001D0DF0B9FAEEE770B56F
+:10CFF0003A4C05462078002804D03D210E2000F050
+:10D0000025F8A5E607F04EFC002803D107F050FCF8
+:10D01000002801D00C2003E0287805F05FFC0020F8
+:10D020002071012060713D21E170207090E610B503
+:10D030000178402908D22C4A89005158002903D090
+:10D04000801C8847012010BD002010BD234A2032DB
+:10D05000537C002B03D19074D1740120507470471D
+:10D0600030B5134606E0CC18203CD51AE47F5B1E91
+:10D070004455DBB2002BF6D130BD4921095C0029B3
+:10D0800008D18030017E002904D0007E042801D020
+:10D09000012070470020704701784068002905D0C2
+:10D0A0004030407A002802D000207047E5E7012098
+:10D0B00070470A4900208031886740310871704705
+:10D0C00010B50178012908D14068A03041790029C4
+:10D0D00003D00021417108F0F2F810BD380800209B
+:10D0E000C40900003A0900208CAC01003D307047B3
+:10D0F0000818C01D50433D31401880B2704770B5CC
+:10D100001D460646A818049BC01D2C4658433D34B6
+:10D11000001984B2A14200D2FFDF1C2130460DF07D
+:10D120007BFA1C3CA0B201213575C90330808842CE
+:10D1300000D9FFDF70BD00887047F0B5044684B0A9
+:10D140001C300390019015460E46A288E1885704D2
+:10D1500048047F0C400CB84208D1C90BD20BC9035C
+:10D16000D203914202D0002004B0F0BDB8421AD9D7
+:10D17000217DC01B401AC01F85422CDC0198C91DAF
+:10D18000C0190918C91E716035810021F160318212
+:10D19000021D326005702A0A42708170C170012040
+:10D1A000A07404B0F0BD2188227DC91B891AC91F53
+:10D1B000009102900FD41B2900DAFFDF009885420E
+:10D1C00001DC294600E081B2681A0204120C06D084
+:10D1D0000298824203DD0020A07404B0F0BD237DDC
+:10D1E0000198DB1DC0191B18DB1E73603181039B86
+:10D1F000F3603282031D33600170090A417082704E
+:10D20000110AC1700120A07404B0F0BDF8B5044645
+:10D2100002468088A37C40041C32400C002B0BD0BB
+:10D2200010184278037812021A43C37885781B02DB
+:10D230002B43D3188B4201D20020F8BD00268A422E
+:10D2400006D30170090A41708670310AC17014E07A
+:10D25000891A8DB2290A8570C170002D0DD0A08861
+:10D26000271D4004400CA84200D2FFDF398801206E
+:10D27000C0038843284338800BE041780278237D3F
+:10D2800008021043DB1D181881B22288201D00F00F
+:10D29000DAFAA6740120F8BDF0B4044646880346C5
+:10D2A000858870041C34400C2018AE4203D1002045
+:10D2B000D881F0BC7047457807785E892D023D43E0
+:10D2C000AE4209D3761BC57880782D020543A81B92
+:10D2D00085B23019C01E05E0AC1BA5B21C7DA41997
+:10D2E0002018001D0C88AC4200D90D805C89002CF0
+:10D2F00005D0002414700988D981F0BC704701243E
+:10D30000F8E7F8B50446014640881C314004400C5B
+:10D310004518E089002837D06189081880B26081FB
+:10D3200069782A7809021143EA78AB7812021A4325
+:10D330008918814200D2FFDF68782978000208430B
+:10D34000E978AA780D0215436289411900279142B4
+:10D3500018D1002D0DD06088A61C4004400CA842B6
+:10D3600000D2FFDF31880120C0038843284330808A
+:10D3700007E0237D2288DB1D181881B2A01C00F075
+:10D3800062FA6781E7810120F8BDF0B504468AB0F2
+:10D390001C300390218967880026B94244D0254675
+:10D3A000083548040399400C0918C8788A780002A7
+:10D3B00010430ED0009029884904490C814200D2C4
+:10D3C000FFDF29880120C003884300990843288093
+:10D3D00025E04A78207D09782B8812020A43C01D77
+:10D3E0009C4681185B045B0C2288591889B29142D3
+:10D3F0000DD2521A92B21B30824204D201206146F1
+:10D40000C00388430AE06046C00BC00305E0881AE9
+:10D4100081B201206246C003904308432880761CF5
+:10D420002189B6B2B942BCD130460AB0F0BDF0B5E0
+:10D430000B46C5880146044683B000896E041C3142
+:10D440000090760C608889190E46854202D1002032
+:10D4500003B0F0BD002A01D0081D1060002B04D0DD
+:10D46000227D311D18460DF07AF870783178070268
+:10D470000F43F078B1780002084311D0C1198FB280
+:10D480000190E188A61D4904490C814200D2FFDFCA
+:10D4900031880120C003884301990843308007E0A8
+:10D4A000237D2288DB1DD81981B2A01D00F0CBF9A5
+:10D4B0000098854201D1E0882081384603B0F0BD54
+:10D4C00041888088814201D1012070470020704747
+:10D4D0004188C088884201D10120704700207047F0
+:10D4E000F0B44588838804466A041C34520C5904FD
+:10D4F000490CA6189D4222D04389C48937781D194A
+:10D5000073781C02F378B6781B023C433343E61869
+:10D51000B54217D3002B02D08B4213D30FE0037D0B
+:10D52000D21D1C19A218008892B2801A80B2223330
+:10D53000984202D2002902D004E08A4202D1F0BC13
+:10D5400000207047F0BC01207047F0B48588C68881
+:10D5500002466C047304640C1C305B0C0719A34274
+:10D5600008D1F60BED0BF603ED03AE4202D000201E
+:10D57000108228E0A34206D9157D1B1B5B1BDB1F15
+:10D580009C46002305E01588167D2D1BAD1BED1F65
+:10D59000AC466546002DEADB9589002D16D07D78D6
+:10D5A0003E782D023543FE78BF7836023E430DD0DB
+:10D5B0009C1B0023D3748C4204DB93891818401BF6
+:10D5C000C01E18E01382F0BC002070476646771B2F
+:10D5D0000026D6748F4206DB137DDB1D1B19948950
+:10D5E0002018181806E08B4208DB0123D3749389B6
+:10D5F0001818401BC01E1182F0BC70471682E2E76B
+:10D60000F7B504460546808882B04004400C1C35BE
+:10D610002E180190208A002802D00399884202D255
+:10D62000002005B0F0BDA189002913D070783278B0
+:10D6300007021743F078B2780002104300903818C0
+:10D64000814200D0FFDFE07C0099014305D0002833
+:10D650003FD048E000270097F5E7A08900280CD0CC
+:10D66000217D019AC91D891840190818617DC01EC5
+:10D670000170A17D4170E17D81700398A2890399B9
+:10D6800038185118A1813070000A70700027B770E7
+:10D69000F770049800280DD07078237D317800024F
+:10D6A0000843DB1D181881B22288201D00F0CBF83A
+:10D6B000A78143E0207D0199C01D4018A189491927
+:10D6C0004018C01E017861754178A1758078E075B9
+:10D6D00034E0A089617D4019C01BC01E0170A17D8E
+:10D6E0004170E17D817003990098A289401851181A
+:10D6F000A1813770390A80B27170B070010AF1707F
+:10D700000646049800280FD0A088251D4004400C30
+:10D71000B04200D2FFDF29880120C0038843304394
+:10D7200028800020A08109E0A0894019C01BC01EEC
+:10D73000017861754178A1758078E07500202082BC
+:10D74000A074012005B0F0BD30B4458802466B04DA
+:10D750001C3284885B0CD318A54202D04489002C6B
+:10D7600002D030BC002070471C1D0C60007DC01D25
+:10D77000C018C01E486058781C78000220430881F9
+:10D78000CA60DC789D7823022B430B82002803D1EA
+:10D79000D21E4A600B81088230BC0120704770B5F0
+:10D7A000024641880446838848041C32400C121803
+:10D7B000994205D06189002902D1E189002901D06F
+:10D7C000002070BD5178137809021943D3789278FC
+:10D7D0001D0215430DD0A61CA84200D2FFDF3188E0
+:10D7E0000120C0038843284330800020E0810120CD
+:10D7F00070BD237D2288DB1D581881B2A01C00F06B
+:10D8000022F8F2E700218181C1740182817470479E
+:10D810008289002A01D10020704730B482880346F3
+:10D820005204520C1C339A185478157824022C4355
+:10D8300004D0037D121D9A184A6001E0DB1E4B6084
+:10D84000808930BC704730B405886C04640C611862
+:10D850008CB20121C90394420AD2121B92B21B332B
+:10D860009A4201D2A94307E0E90BC903214303E02F
+:10D87000A21A92B2A9431143018030BC7047000044
+:10D88000FFB52649D21C0A401E460446154600280C
+:10D8900009D00027E01C80088000A04200D0FFDFF4
+:10D8A000201D01210DE00127F4E702464019002F59
+:10D8B00005D1B14201D2034600E000231360491CA8
+:10D8C000C9B2B142F1D9011B0198002F016005D105
+:10D8D000002E01D0201D00E000202060FFBD014689
+:10D8E0000A680020002A02D0104612680A607047B9
+:10D8F00002680A6001607047084B10B5C91C101A15
+:10D900001940001F0CF0B3FEC0B210BD034BC91C80
+:10D9100019405143001D081870470000FCFF00002B
+:10D92000FEB5D14C0546A0780E46A84200D8FFDFD0
+:10D93000B00007190190A800B96A009008580028A3
+:10D9400000D0FFDFB868FFF7CAFF04000DD0B96A46
+:10D950000098062E0C500AD0082E00D3FFDFC349D2
+:10D9600001980A582146284690472046FEBDBE48E9
+:10D97000BF4B7A30024600902E3A2146284608F0E6
+:10D980001EFEF2E7FFB581B00A98019F18181E46E7
+:10D99000C4B2002F07D00025FF2800D9FFDF02986E
+:10D9A000002803D101E00125F6E7FFDF0198C01C44
+:10D9B000810801988900814200D0FFDF0A9903980D
+:10D9C000884200D9FFDF002D0BD1A74900204C3140
+:10D9D0000870A84A4A80A6490870A3497A3108709D
+:10D9E0004A80A1480399017046708470C470047124
+:10D9F00044710A998171C6710026FF1CB808800025
+:10DA00000746002D03D19849B20051188860974904
+:10DA1000720040318A5A9449002D8B5D00D000205D
+:10DA20006946FFF72DFF0099761C7F18F6B2082E85
+:10DA3000E3D3FF1CB808800023460646002D0FD014
+:10DA4000002002226946FFF71BFF009831180020D2
+:10DA5000A2009646C91C8A089200002D03D012E04D
+:10DA600081498864EDE78049860071188C468A6296
+:10DA700000210B4605E066468F00B66A491CF3514B
+:10DA8000C9B2A142F7D37146401C5118C0B2082850
+:10DA9000E0D30198081A02990880002005B0F0BD73
+:10DAA00070B5044603F035FF002801D0102070BD8A
+:10DAB00020786D4A80008018618892780FE0836A30
+:10DAC0008D005B59002B08D04A1C6280A180806ABF
+:10DAD00089004058A060002070BD491C89B28A426C
+:10DAE000EDD86180052070BD70B505460C4608462E
+:10DAF00003F00FFF002801D0102070BD082D01D3C6
+:10DB0000072070BD25700020608070BD0EB569468D
+:10DB1000FFF7EAFF002800D0FFDF6846FFF7C0FFED
+:10DB2000002801D000200EBD01200EBD10B5044616
+:10DB3000082800D3FFDF4C48005D10BD3EB5054608
+:10DB400000246946FFF7D0FF002803D0FFDF01E083
+:10DB5000641CE4B26846FFF7A3FF0028F8D028460B
+:10DB6000FFF7E4FF001BC0B23EBD3F498978814208
+:10DB700001D9C0B27047FF207047F8B50C46054682
+:10DB8000062901D0072C0FD1374FB86CFFF7A7FE3D
+:10DB9000384E020004D00221B86CFFF7ADFE00E061
+:10DBA00030462880B04201D10020F8BD2146FFF761
+:10DBB000B7FE040002D1288800F049F82046F8BDDD
+:10DBC0002C4A904201D0082901D300207047A7E6D3
+:10DBD000284A90420BD0082909D2234A93788342DD
+:10DBE00005D989008918896A800008587047002083
+:10DBF0007047F8B50D4604461E491F488C4202D0B6
+:10DC0000082D01D30720F8BD174A9178A142FAD90F
+:10DC1000A9008F18A200BB6A00929E58002EF2D075
+:10DC2000124A204620325258314690470020BA6AA4
+:10DC30000099062D505001D0072D02D1204600F04A
+:10DC400006F83146B868FFF753FE0020F8BD10B55E
+:10DC5000054CC2B20221A06CFFF758FE0146A06C31
+:10DC6000FFF746FE10BD0000480900208CAD010002
+:10DC700056000020FFFF000002300000014610B5F2
+:10DC80009F48002200680260037A9B001818C26057
+:10DC9000018211460C3000F022F910BDFFB50027BB
+:10DCA00081B015460446002826D00026E01C8008D6
+:10DCB0008000A04200D0FFDF002D2DD00120FFF713
+:10DCC00015FA0C996843CA000A995118471801209F
+:10DCD000FFF70CFA6843C1190B98C200049810189A
+:10DCE0000818062169430818A900143008180818F4
+:10DCF00087B2002E02D00FE00126D7E7781A0C3841
+:10DD000086B27F480460204625720C3060600CF0BB
+:10DD100085FC3046FFF7B2FF02980780002005B06F
+:10DD2000F0BDFFB5764C0546206883B0002800D1D1
+:10DD3000FFDF2068017AA94205D9A9004268019154
+:10DD40005158002902D06F4807B0F0BD0068002884
+:10DD500000D1FFDF01210C9A0598FFF7C9F96A4E3F
+:10DD6000C51C35400121069A0498FFF7C1F9C01C73
+:10DD7000304002904019001D86B2614800270068BB
+:10DD8000046801E0274604462068002807D0A188DF
+:10DD9000B142F7D13946204600F0AAF813E03046E8
+:10DDA0000830A18880B2814229D33946204600F04C
+:10DDB0009FF8A0880022811BA0190260818039464B
+:10DDC00000F08DF8A680A088608025802946201D5F
+:10DDD0000C9D059A064601230095FFF790F92088CF
+:10DDE000069D80190123049A02990095FFF787F98F
+:10DDF00043480068416801980C500020A4E70420C3
+:10DE0000A2E770B53E4C06462068002800D1FFDF2F
+:10DE10002068017AB14210D94568B300E85800285B
+:10DE20000BD041880022EA5002608180114600F048
+:10DE300056F8216800200A7A08E0324870BD4B6825
+:10DE400084001B59002B0DD1401CC0B28242F6D871
+:10DE5000002002E08A88101880B209680029F9D1F0
+:10DE6000FFF70CFF002070BD70B5254D2868002815
+:10DE70000AD0002404E02046FFF7C3FF641CE4B28C
+:10DE80002868007AA042F6D870BD70B51C4E0546D1
+:10DE900030680024002800D1FFDF3068017AA942F1
+:10DEA00005D94068A9004058002800D0041D20462C
+:10DEB00070BD70B5124E054630680024002800D1B0
+:10DEC000FFDF3068017AA94207D94068A9004158AC
+:10DED000002902D00888091D4418204670BD002979
+:10DEE00003D00A6802600860704705490968F8E7CE
+:10DEF0000068002901D00860704701490968FAE705
+:10DF00005C00002002300000FCFF000070B50446F9
+:10DF100000780E46012819D0072802D00C2819D104
+:10DF200014E0A068216905780B2D0BD0052003F0C3
+:10DF300094FC052D0ED0782300220520216903F0E2
+:10DF4000FDFB07E0782300220620F8E70520216981
+:10DF500003F083FC3146204601F0A8F970BD30B5CE
+:10DF6000411D0246393294780325C379ED432C4391
+:10DF70002340C371DB070DD04B79547923404B719B
+:10DF80000B79127913400B718278C9788A4200D9D3
+:10DF9000817030BD00224A710A71F5E7417801298C
+:10DFA00000D00C2101707047F7B58CB00D468C691C
+:10DFB0000020694608732878012716462A287CD253
+:10DFC00043007B449B885B009F4429000503450375
+:10DFD00058039103A103BD03ED03050431045C0460
+:10DFE0007C049504DA04E9040B05140534055B058B
+:10DFF0008C05B205DD05FA050406260640064C062A
+:10E0000074069406E2061607240752076E07860771
+:10E010009907D20709083408F207F607FB07002C16
+:10E0200002D020781D282BD0A8680190002844D069
+:10E03000012168460173686A0790032168460174EC
+:10E040000A214174286A0590A8880028EFD0019918
+:10E050000978002914D00F2912D20B000CF040FDD2
+:10E060000FFE1446D7FDFCFBFAF9F8F70990F6F518
+:10E07000FE00022821D1002C04D020780C2801D0E9
+:10E0800000275FE30220C3E10620696A03F0E5FB95
+:10E09000A8880728EED1204601F002F9022809D00D
+:10E0A000204601F0FDF8032808D9204601F0F8F8D1
+:10E0B000072803D20120207005E018E2002CB6D01A
+:10E0C00020780128D6D101980079C11F0A2901D3EF
+:10E0D0000A2053E0A07020460722383001990CF046
+:10E0E0003EFA01202870032020703BE00728C1D1B0
+:10E0F000002C9CD020780D28BCD101982246C178F4
+:10E100002032D07E08400007C00F01D00E2000E072
+:10E110000F20890707D1019949790142D8D1019986
+:10E1200089790142D4D10199537F497907469F43A8
+:10E130003942CDD10199927F897990430142C7D16B
+:10E1400001980079C11F0A29C2D2617F81427BD820
+:10E150000722201D01990CF002FA012028700E20E0
+:10E160002070032069460873686A0790204639309A
+:10E170000490601D059017300690FEE02877F6E3C6
+:10E18000E9880891412885D1204601F089F80428C2
+:10E1900002D1E078C00704D1204601F081F80F28B1
+:10E1A00090D1089840210A1A01991746606A491CC3
+:10E1B0000CF0D5F9606AE968C019089A0CF0CFF93B
+:10E1C0000E2069460873686A0790606A049000210F
+:10E1D00003A8FFF79BFE2078042809D0A07F002821
+:10E1E00011D001280FD003280FD010202070B8E0E4
+:10E1F00005202070032028700A2168460173686A90
+:10E2000041210790F5E311203DE11220EEE71128AE
+:10E21000B9D1204601F044F8042802D1E078C007C3
+:10E220000FD0204601F03CF8062805D1E078C00761
+:10E2300007D1A07F022804D0204601F031F8112830
+:10E24000A1D1102220460AE020E0C7E097E098E143
+:10E2500077E159E11BE1FCE0E3E01BE0B9E1019962
+:10E260004830491C0CF07BF9607801280AD0122054
+:10E270002070E078C00778D0A07F002871D00128F6
+:10E280006FD072E0607FA178884201D9062075E7DF
+:10E290000720ABE71128BBD1204601F001F8082880
+:10E2A00004D0204600F0FCFF1328B1D128690028D3
+:10E2B0001BD06869002818D02046019978301022B8
+:10E2C000491C02900CF04BF92078082811D014203A
+:10E2D0002070E078C0070ED0A07F022822D061789D
+:10E2E00002291BD003283CD03FE000206946087378
+:10E2F000FDE00920ECE70B20287029690220487016
+:10E30000206C48600298886020463830C860201D24
+:10E310000861206B4861606B8861ACE3002801D024
+:10E3200001287DD10B2028702F6908207870606A41
+:10E330007860206AB860029860E2206C0CF070F996
+:10E34000E1788906C90E491EC840C007C00F803059
+:10E3500000E000203874E06A786164E20746DEE39A
+:10E36000FFE7042028700520CCE10A2028706946C8
+:10E370000873686A07901120F8E33146F7E3112823
+:10E38000B6D1204600F08CFF0A2802D1E078C00701
+:10E3900004D1204600F084FF1528A9D10199204618
+:10E3A00010224830491C0CF0DAF820780A2810D0E6
+:10E3B000162020701220287029690A2048702046F3
+:10E3C00058304860203088601038C860206C086180
+:10E3D000A8E30B202070D1E22870B2E1022887D197
+:10E3E000204600F05DFF042804D3204600F058FFCB
+:10E3F000082809D3204600F053FF0E2877D3204683
+:10E4000000F04EFF122872D2A07F0228B8D111204E
+:10E4100069460873686A0790019840780874FAE3BF
+:10E420004FE20228ACD1204600F03AFF00285ED02F
+:10E43000204600F035FF0128F9D0204600F030FFDB
+:10E440000C28F4D005206946087401984078487477
+:10E450004EE71128FCD1002CFAD020781728F7D1EC
+:10E460006078E16A022810D000201822504318304A
+:10E47000085801991022491C0CF071F80520696AAE
+:10E4800000F002FF18202070FAE50120EDE70B28CC
+:10E49000DED1002CDCD020781828D9D16078E16A50
+:10E4A000022825D000201822504310300958019826
+:10E4B00042780A70807848706078E16A022819D042
+:10E4C0000020182250431430085801990822C91C12
+:10E4D0000CF045F80520696A00F0D6FE6078022845
+:10E4E0000AD000210919497A490849006AE0A5E1E2
+:10E4F0000120D8E70120E4E70121F3E7012000E053
+:10E5000000200019417285E31128A1D1002C9FD071
+:10E51000207819289CD16078E16A02280FD0002069
+:10E52000182250431C30085801991022491C0CF045
+:10E5300016F80520696A00F0A7FE1A20A3E701205B
+:10E54000EEE7082884D1002C86D020781A2886D1BE
+:10E550000198E16A40780870E06A01990622401C3F
+:10E56000891C0BF0FCFF0520696A00F08DFE6078C5
+:10E57000022804D000210919497AFD2221E0012155
+:10E58000F9E7112884D1002C84D020781B2884D16D
+:10E590006078E16A022818D0002018225043203009
+:10E5A000085801991022491C0BF0D9FF0520696A0F
+:10E5B00000F06AFE6078022809D000210919497A22
+:10E5C000FB22114002289BD198E70120E5E70121B9
+:10E5D000F4E70720D2E53078012896D11C22A01854
+:10E5E0007168F2F7D3FD3B21E079095D0840E178DD
+:10E5F00000074908C00F49000843E070217F002947
+:10E6000001D029771AE1217803290BD0C00700D166
+:10E61000A7E6032028700A2069460873686A0790F5
+:10E620004120B3E302272771E1792046C906C90ECC
+:10E63000E171617A0907090F6172A17A0907090F6F
+:10E64000A172FFF78CFC2F700A2069460873686A74
+:10E65000079007209AE330781228D3D10720087357
+:10E66000696A079191680591694608820722211D10
+:10E6700005980BF074FF04202070CCE2F08808901D
+:10E6800030781228BED107200873686A0790301DC1
+:10E6900007C804AB07C341206946088205980C21CE
+:10E6A000017008994022571A3A46401C216A0BF023
+:10E6B00056FF206A089AC119F0680BF050FF00213C
+:10E6C00003A8FFF723FCE078C1210840801CE0701C
+:10E6D0002078052801D00F20D5E6A07F002800D1A2
+:10E6E000D6E50128FCD0032874D10820CBE6307889
+:10E6F000032887D120460822683071680BF02FFF6D
+:10E700000520287069460873686A079035E63078F6
+:10E710000328A2D120460822703071680BF01FFF39
+:10E72000206C00283DD1A07F002805D0012803D00F
+:10E73000062028700420E5E707202870F8482064A8
+:10E7400060640327FEE33078022886D13079002800
+:10E7500073D1A07F022802D0032805D021E0B06841
+:10E7600000286BD020641BE06078012806D03A2195
+:10E77000A079095D012805D0E94806E03A20A17991
+:10E78000005DF7E7B0680028EBD02064E078C007B0
+:10E7900001D0012901D0E24802E0F0680028E0D071
+:10E7A0006064072018E60A200873696A0791E17817
+:10E7B000C9070AD06178022904D1A17F002905D0B8
+:10E7C000012903D0A17F032900D00820287011203F
+:10E7D00069467BE3CCE0307812288AD1B0682862A1
+:10E7E00009202870E0782F69C0070DD008207870C4
+:10E7F000206A7860606AB86020466830F860A07F60
+:10E80000022800D0A5E598E502207870206C786099
+:10E8100020466830B8603038F860201D3861206BC1
+:10E820007861606BB861686A3946786225E1E078A2
+:10E830003178C00703D0072002E0D8E0BCE20B200B
+:10E840008142CAD1207807281AD0112020700721D0
+:10E8500068460173686A0790286A05901121684626
+:10E86000018205980321017051681022401C0BF0B1
+:10E8700076FE002103A8FFF749FB0020286203E68B
+:10E880000820E3E730781228A7D107200873686AC8
+:10E890000790906805901120088205980421017066
+:10E8A000214610226831401C0BF059FE002103A8BC
+:10E8B000FFF72CFB2078092801D01320E3E50A207C
+:10E8C000207016E0E1783078C90701D0072100E018
+:10E8D0000B218842B5D120461022483071680BF0D8
+:10E8E00011FE002801D0042048E42078092800D136
+:10E8F0003BE50C2070E5E078C1073FD0A17F0129FE
+:10E9000002D002291DD035E00D20287029690B2086
+:10E910004870607801280BD0206A4860606A88607F
+:10E9200020466830C86010300861E06A4861A2E0A3
+:10E93000606A4860206A886020467830C860103875
+:10E94000F2E78106C90E142914D20621C84101211B
+:10E95000C90640181A21C841E0706078012807D024
+:10E9600010202070042028700520694676E171E3AC
+:10E97000062088E56078012800D185E50E202BE58A
+:10E9800030780A28A6D1287010200873686A07908A
+:10E9900050680490002103A8FFF7B8FAEAE7E0788E
+:10E9A000C0070AD0A07F012803D10F2028700420BF
+:10E9B00054E1102028700F2050E11520287029699B
+:10E9C00003204870206C48606078012804D02046FD
+:10E9D0007830886010388FE22046683088601030C8
+:10E9E0008AE230780228CDD130790028E1D028772A
+:10E9F0002DE374E030781428FAD1112028702969A9
+:10EA00000920487070684860607801280DD0204661
+:10EA1000683088601030C860206B0861606B4861A6
+:10EA2000204658308861A06A22E02046783088600D
+:10EA30001038F0E730780828DAD16078012801D062
+:10EA40001320F7E0A178A06A10224018511A0BF0A9
+:10EA5000E3FD1220287029690A20487020465830AA
+:10EA60004860203088601038C860206C08614FE032
+:10EA7000C861E06A0862686A48620C9800F02DFC80
+:10EA80006CE430780928B3D12046102248307168F0
+:10EA90000BF038FD002801D00B209BE520780B28D7
+:10EAA00015D02046FFF75BFAA178A06A1022401823
+:10EAB000511A0BF0B1FD1620287008206946087322
+:10EAC000686A079000200490A078087555E4132028
+:10EAD00028700A2168460173686A11210790684608
+:10EAE00001744AE43078122886D1B0682862142074
+:10EAF000287029690A204870204658304860103034
+:10EB000088601030C860606C08616078012809D0A6
+:10EB1000204639304861206B8861606BA8E786E247
+:10EB2000AAAE0100601D4861606B8861206B9FE7A1
+:10EB300030780928A7D107200873686A0790286AE7
+:10EB400005901120088205980D2101701022401CAB
+:10EB500071680BF004FD002103A8FFF7D7F900202E
+:10EB600028626178012903D015208CE40EE17BE155
+:10EB70001621297008216A461173696A0791049069
+:10EB8000A0781075C2E530780C28ADD11620287019
+:10EB90006078022802D12046FFF7E1F9A178706879
+:10EBA00010224018511A0BF037FD082168460173F6
+:10EBB000686A079070680490A17868460175A5E5B9
+:10EBC0003078102890D1E079C00772D017202870D3
+:10EBD000092043E03078112886D120461422311DC7
+:10EBE0001C30F2F7D3FAE06A218D4172090A817272
+:10EBF000E16AA078C871E179E26A8907890F117228
+:10EC0000E16A627A0A73E16AA07A20310871607859
+:10EC100001286ED0AAE136E26078022801D00120F6
+:10EC200000E000200019407AC0070DD0E078C0074E
+:10EC30000AD1192028700A2168460173686A079072
+:10EC400011216846017442E11E20ABE5307812289C
+:10EC50009BD1B06828621A20287005200873686A62
+:10EC6000079034E1307803288FD16078E16A022878
+:10EC700001D0012000E00020182250431430085831
+:10EC8000082271680BF06BFC1B2028702969062292
+:10EC900068694A70626A4A606278E36A022A01D04F
+:10ECA000012200E0002218277A4314329A588A6021
+:10ECB00022E184E130780F287ED16078E26A022870
+:10ECC00001D0012000E000201821484310301058E6
+:10ECD00002230932716809F049FF1C202870296954
+:10ECE00005204870206A4860E06A09308860FB4867
+:10ECF00002E159E130780E285ED16078E16A02289D
+:10ED000001D0012000E0002018225043183008589C
+:10ED1000A27871680BF023FC6078E16A022801D0C8
+:10ED2000012000E000201822504318300858A17834
+:10ED300010224018511A0BF06FFC07206946087327
+:10ED4000686A0790286A05901120088205980621B4
+:10ED500001706178E26A022901D0012100E00021FE
+:10ED600018235943183151581022401C0BF0F7FB5F
+:10ED7000002103A8FFF7CAF8002028621D20287090
+:10ED80000A2069460873686A07900B200874BDE47E
+:10ED90003078122810D1072168460173686A0790FD
+:10EDA000906805900B226846028205980170617890
+:10EDB000E26A022903D000E0A0E0012100E0002186
+:10EDC00018235943103151580A784270497881709C
+:10EDD0006178E26A022901D0012100E000211823B4
+:10EDE0005943143151580822C01C0BF0B8FB0021C4
+:10EDF00003A8FFF78BF827E76078022801D00120ED
+:10EE000000E000200019407A800701D51F2011E79B
+:10EE10002120C7E43078122870D107200873686A6F
+:10EE20000790B068059011200882059808270770A0
+:10EE30006178E26A022901D0012100E00021182353
+:10EE400059431C3151581022401C0BF088FB002103
+:10EE500003A8FFF75BF8202028700A206946087392
+:10EE6000686A07900F7451E403A8FFF74FF807E6AC
+:10EE70003078122842D107200873686A079090689A
+:10EE8000059008200882059809210170E169062291
+:10EE900009784170E169801C491C0BF060FB00217E
+:10EEA00003A8FFF733F8B3E76078022801D0012107
+:10EEB00000E000210919497A49070AD52220287063
+:10EEC0000A2069460873686A079011200874114681
+:10EED000CAE701284AD069E0307812280ED1B0681C
+:10EEE000286223202870296905204870206A48601C
+:10EEF000E06A093088607A48C860BCE56EE0307826
+:10EF00000E286BD16078E16A022801D0012000E070
+:10EF100000201822504320300858102271680BF04E
+:10EF20001EFB072069460873686A0790286A0590E7
+:10EF30001120088205980A2101706178E26A02298D
+:10EF400003D000E0A4E0012100E000211823594390
+:10EF5000203151581022401C0BF001FB002103A866
+:10EF6000FEF7D4FF002028626078B2E7242019E47D
+:10EF7000607802280BD000200019407AC10702D027
+:10EF8000E178C90705D0810705D5192096E401204D
+:10EF9000F2E7172092E4400701D51B208EE41C20E5
+:10EFA00020706078012801D01820A3E42720A1E474
+:10EFB000282028700B2051E63078132847D12920CB
+:10EFC00098E42078012842D00C2840D02046FEF753
+:10EFD000E5FF0C2069460873686A079037E03078CF
+:10EFE000122805D0132010700327262028704FE028
+:10EFF000072168460173686A0790B068059002218E
+:10F0000068460182059805210170297F4170002121
+:10F0100003A8FEF77BFF0B2168460173686A07901F
+:10F02000314603A8FEF772FF074626202870012FFD
+:10F030000DD02DE0012168460173686A0790042114
+:10F0400068460174297F41740020287713E0287FE7
+:10F05000002810D01D202070252028700A20694625
+:10F060000873686A079002200874314603A8FEF707
+:10F070004DFF07460CE0002C01D0FE2020706846B2
+:10F08000007B002804D0002103A8FEF73FFF74E4B2
+:10F0900038460FB0F0BDF7B50C464E690978012728
+:10F0A000072086B0002904D001294BD0022920D1A5
+:10F0B000C4E02179012906D0022916D0032911D0F4
+:10F0C000042916D126E07078012811D10620616A42
+:10F0D00002F09DFB00280CD102200EE0A2AE010040
+:10F0E000DCAD01001D203070F6E77178022901D0F7
+:10F0F000052790E031780C2923D169460871012059
+:10F100002070684621890079814211D20A2069461F
+:10F1100008704AE03078011F042902D30E38032812
+:10F1200079D2B07F022876D12089022873D3D3E721
+:10F13000089812210170083408980ECC001D0EC0EA
+:10F14000032768E008990978122964D16946087094
+:10F15000616A049108998D6802952179012906D088
+:10F1600002292AD0032911D0042954D15AE00227B8
+:10F17000684687800B202870207E0021C006C00EC4
+:10F1800068706846FEF7C2FE377043E002266846A4
+:10F19000868005202870207E687000216846FEF772
+:10F1A000B5FE26700B2168460170606A04906846BF
+:10F1B0000899FEF7ABFE07462DE0694688800120DE
+:10F1C0002870207F6870607FC007C00FA870A07F84
+:10F1D000C006C00EE870E17F2971C0071ED020462E
+:10F1E000203001780907090F697140780007000F86
+:10F1F000A87100216846FEF789FE3046072229469D
+:10F2000038300BF0ACF9A069407870772879B0708D
+:10F210000D2030700027384609B0F0BD0020A871DD
+:10F220006871E6E70220694688800E202870207EFB
+:10F23000687000216846FEF769FEEBE7FE2030703B
+:10F24000012168460170606A0490042168460171DA
+:10F25000217E41710021EEE700B50023012285B037
+:10F2600005280CD0062808D16846027004910221B6
+:10F27000017143710021FEF749FE05B000BD6846EB
+:10F28000027004910271F4E770B50C46054602F075
+:10F29000E4FA782300222146284602F04FFA70BD96
+:10F2A000002801D0007870470C20704770B50578B1
+:10F2B0000C000DD0002121702146F4F767F8774843
+:10F2C0002178405D884201D1032070BD022070BDCD
+:10F2D0000021F4F75BF8002070BD027B032A05D003
+:10F2E00000220A704B780C2B02D003E004207047F8
+:10F2F0000A770A62027B9300521C0273C1500320FA
+:10F300007047F0B585B00F4605460124287B800084
+:10F3100040198038C66F7078411E0D290AD25F49A6
+:10F320008000123140188038C36F3A463146284673
+:10F3300098470446002C01D0012C11D1287B401E97
+:10F340000006000E287301D00324DFE70D20694674
+:10F350000870706A0490002101966846FFF7A6FFC6
+:10F36000032CD3D0204605B0F0BD70B515460A4633
+:10F37000044629461046FFF7C4FF0646002C0FD06E
+:10F380002078FE280CD1207E002806D0002028708E
+:10F39000204629460C30FFF7B4FF2046FEF7FEFD5D
+:10F3A000304670BD704770B50D46044688210BF09D
+:10F3B00035F9012D03D0022D03D0052070BD0120A9
+:10F3C00000E0022060702046FEF7E8FD002070BDDE
+:10F3D000002806D0027E002A03D00A4601460C31DE
+:10F3E000C3E70120704730B5044687B00D460620BC
+:10F3F00002F033FA2946052002F02FFA2078FE2881
+:10F4000005D00020694608702046FFF7E1FF07B0ED
+:10F4100030BD7FB50E4600216A46117341780C2934
+:10F4200003D00D2903D0002407E0846900E044697B
+:10F43000002C02D0217E002912D015460146284614
+:10F44000FFF74BFF032809D1324629462046FFF734
+:10F450008CFF6946097B002900D0042004B070BDF0
+:10F4600025460C35EAE710B590B00C4605216B46F1
+:10F470005970019009480992801E02900848039033
+:10F480000AA96846FFF7C5FF002805D110222046CB
+:10F490000B990BF064F8002010B010BDE2AD010034
+:10F4A000A2AE010070B50D46040012D0002D10D0A0
+:10F4B000210128460BF0B0F81022534928460BF0E2
+:10F4C0004EF85148012108380180448045600020F1
+:10F4D00070BD012070BD70B54B4E00240546083E3E
+:10F4E00011E0716820014018817BAA7B914209D10B
+:10F4F000C17BEA7B914205D10C2229460BF002F830
+:10F50000002806D0641C30888442EADB0020C04317
+:10F5100070BD204670BD70B50D46060007D0002DA9
+:10F5200005D0FFF7D8FF002803DB401C14E01020B3
+:10F5300070BD354C083C20886288411C914201D93D
+:10F54000042070BD616800014018102231460BF0A4
+:10F5500006F82088401C20802870002070BD70B5FF
+:10F5600014460D001FD0002C1DD00021A1700228D0
+:10F5700002D0102817D108E06878297800020843E3
+:10F5800011D00121A17010800BE02846FFF7A3FFE6
+:10F59000002808DB401CA070687B297B0002084320
+:10F5A0002080002070BD012070BD70B50546144656
+:10F5B0000E000AD000203070A878012807D004D9A6
+:10F5C000114908390A8890420BD9012070BD002CDE
+:10F5D00004D0287820702888000A50700220087013
+:10F5E00010E0002C0CD04968000141181022204680
+:10F5F00010390AF0B4FF287820732888000A607355
+:10F6000010203070002070BD68000020F8B5FC4C60
+:10F61000207EE17D884219D00126FA4D0027E07D49
+:10F62000215C14200A4642435019037C052B0ED05E
+:10F63000037C062B19D0037C072B25D0437C012BA0
+:10F6400030D0FFDF207EE17D8842E8D1F8BD06742E
+:10F65000E07D162807D0E07D401CE075491CC8B24B
+:10F66000AA5802210CE00020F7E70674E07D162876
+:10F6700008D0E07D401CE075491CC8B2AA5803219F
+:10F680009047DFE70020F6E70674E07D162807D0F4
+:10F69000E07D401CE075491CC8B2AA580821EFE77C
+:10F6A0000020F7E74774E07D162807D0E07D401C76
+:10F6B000E075491CC8B2AA580721E1E70020F7E726
+:10F6C00070B50024D04E0C207072D048254644738B
+:10F6D000047328300476C475CD480AF079F8CD4813
+:10F6E0000575F572CC49601E88607571B570F5704E
+:10F6F00035717570C948E83905704570142060434C
+:10F7000040180574641CE4B20B2CF7D30120F9F700
+:10F7100084FB0020F9F781FB0120B071F9F704FFA9
+:10F72000BF48F9F713FFBF4C2070BF48F9F70EFF31
+:10F730006070F9F715FB70BD10B5F9F73CFBB94CDB
+:10F740002078F9F71EFF6078F9F71BFFAE4C207A9E
+:10F75000002803D0F9F7DDFC0020207210BD0B203B
+:10F760007047F8B5F9F7DDFBA74D0446A8790028E6
+:10F7700001D0FFDFF8BDE87A002800D1FFDFA64FF7
+:10F7800001237969A94A601A9B0598420ED30E1B82
+:10F790009E420BD3904203D9501A0019401C05E039
+:10F7A000964232D9101B4018401C4042002800DB12
+:10F7B000FFDF0126AE710024EC72687A0421142266
+:10F7C0005043904A80180174B868401C04D0481F08
+:10F7D000B8600120F9F721FB0020F9F71EFBF9F7CB
+:10F7E00005FB0AF06FF9F9F7FCFB9148046004602F
+:10F7F00001209049C0030860F3F7AAFB874800780E
+:10F80000022807D0032802D006E0FFDFD0E7E8781F
+:10F81000002801D0AE7000E0AC70F9F7CEFBF8BD67
+:10F82000034678490B20142242435218203A127F93
+:10F83000002A04D0401E0006000EF4D170471422A6
+:10F84000424351180A46803AD366012220390A778A
+:10F850007047012805D0032805D1002903D10020D5
+:10F8600070470029FBD010B4674C002363706B4ACB
+:10F87000002890700CD002280AD007291AD208005C
+:10F8800078440079001887441505070D0F111300FF
+:10F89000D37003E01B2000E03A20D070012060709C
+:10F8A00010BC70475820F8E77720F6E79620F4E779
+:10F8B000B520F2E710BC0020704710B557484078DB
+:10F8C000F9F796FB80B210BD411E1422504310B5CB
+:10F8D0004C4A8418203C0A2902D8207F002800D1F5
+:10F8E000FFDF207F012800D0FFDF0020207710BD40
+:10F8F00070B5464C607B217B884201D1012500E038
+:10F900000025F9F70EFBF9F773FB617B227B91422F
+:10F9100001D1012100E00021A942EBD170BDF7B572
+:10F920000646481E84468EB0C0B21422059050434D
+:10F93000344A85180495287C2D1D07282AD1304C7F
+:10F940000027E07D227E824221D0235C059A9342EB
+:10F9500001D1012701E0002F04D0162811D0421C4C
+:10F96000A25C225416280ED0401C227EC0B28242D5
+:10F97000EBD1002F0BD0207E002806D0207E401E29
+:10F9800004E00022ECE70020EFE716202076049A3E
+:10F990000120107460461C4C0A2813D814204143DF
+:10F9A000184808182038007F00280BD00498007CE5
+:10F9B000012808D00498007C012803D01098807A90
+:10F9C000012804D0FFDF1098807A012859D10498CB
+:10F9D0000C4B007C02282FD0094C207E16285CD0CE
+:10F9E000207EE17D401C884200D1FFDF0499012088
+:10F9F0004874217E05986054207E162851D052E02C
+:10FA0000BC0B0020D80B0020E00C0020940B002041
+:10FA1000EC0C0020A40B0020C00C00207A00002079
+:10FA2000FD150100780000200DF60000FFFFFF002B
+:10FA300000F5004080E200E0607A059A01469042BD
+:10FA400006D0014614277843C018807C9042F8D134
+:10FA5000627A824208D1617A14225143C918897CA2
+:10FA600061720121A17207E014224243D2181427C7
+:10FA70007943927CC9188A7414220C215043C0180F
+:10FA800081741098007A06281DD201007944097902
+:10FA900049188F440C161412100EE07D0028A4D0D3
+:10FAA000A4E7002001E0207E401C2076AFE000218A
+:10FAB0000BE0B42109E0732107E0322105E00A21BF
+:10FAC00003E0062101E0FFDF0021109802910068A9
+:10FAD000401A28601099097A002912D00221401A90
+:10FAE0000102090A29601098026840681018000293
+:10FAF000000A68601098807A0228109803D0007B72
+:10FB00006FE00421EBE7007A002812D0022202986D
+:10FB10001218109843681046103018180A90FB48C5
+:10FB2000029B4078984202D9E378002B03D00A98D0
+:10FB300005E00422EBE7029BC31A0A981818637ABF
+:10FB400011300C2B1CD0637A14277B43F04FDB1948
+:10FB50005B68994214D0EF4F617ABC461423594335
+:10FB6000EB4BC9184B6889689B1B891B1B02090258
+:10FB70001B0A090A984235D8634533D8614531D804
+:10FB800031180A980123081A0002000A2860109907
+:10FB90008018C9680002000A471ADF4A9B05BC4664
+:10FBA0009F4201D2384610E00F1A9F4201D26046B0
+:10FBB0000BE0944503D9511A0818401C05E0974200
+:10FBC00006D9101A4018401C404200285DDC00E0B5
+:10FBD000FFDF0A982968103808180002000A6860D8
+:10FBE000002028726868112710300002000A68603F
+:10FBF0001098407AA8721098007A687203280ED282
+:10FC000000280CD001F07EFA002803D007E0002085
+:10FC100011B0F0BD3221029802910F1A1137BB4882
+:10FC20000178012901D0032909D14078029988423D
+:10FC300005D9E178002902D10299401AC7196A68EA
+:10FC40002868921B801B944601021202B14B090ADC
+:10FC5000120A8F4219D81F46994216D8BA4214D8B0
+:10FC6000617A0C2915D0677A61460C2203920092C2
+:10FC70001422A74B7A43D21893689B1B834216D851
+:10FC80000397977C0C2FF3D16EE0059801F096F85E
+:10FC9000BDE70499022205980A74627A0C2A00D002
+:10FCA000627A8A7460720120A07211B0F0BD0C2FCC
+:10FCB0005AD0002238469446142203465343944AAD
+:10FCC0009A1853689B1B8B4222D2907BAB7A984246
+:10FCD00018D804980521059D0174904C207E1628A3
+:10FCE0000CD0207EE17D401C884200D1FFDF207EC9
+:10FCF0002554207E162800D0D5E6D2E6E07D0028E7
+:10FD0000F4D0F4E701208446907C0C28D4D102E0A2
+:10FD10006146002927D03D46009014202A464243E0
+:10FD20007B480621161831741C38007E16287B4843
+:10FD300013D0017EC07D491C814200D1FFDF77488E
+:10FD4000017E4554017E16290BD0017E491C0176A7
+:10FD5000B57C0098A842E0D106E0C07D0028EDD037
+:10FD6000EDE70021F3E7009704990220684D08743D
+:10FD7000607AB84207D10499009888740598607237
+:10FD80000120A0721BE003980C2F0CD00C2800D18E
+:10FD9000FFDF039814225043401905998174049998
+:10FDA000009888740BE00C2800D1FFDF0398142220
+:10FDB000504340190599817404990C2088740120DE
+:10FDC00011B0F0BD30B50D46554A441900210B461F
+:10FDD000101A8B4100D2FFDF5248854200DDFFDF61
+:10FDE0005148854200DAFFDF5048844205DA002C92
+:10FDF00001DB204630BD4D4800E04D48201830BDA5
+:10FE0000401E70B5C0B21421484341494418607B7C
+:10FE1000062813D201007944097949188F44020C4D
+:10FE20000A08060400202FE0B4200CE073200AE04A
+:10FE3000322008E00A2006E0062004E0FFDF617BB4
+:10FE40000020002920D002214018616840180002DB
+:10FE5000000AF9F7CDF80C256557314A44190021FD
+:10FE60000B46101A8B4100D2FFDF2E48854200DD81
+:10FE7000FFDF2D48854200DAFFDF2C48844207DA95
+:10FE8000002C03DB204670BD0421DDE7274800E09D
+:10FE90002748201870BDF0B5064683B0254801906C
+:10FEA000457A029534687068001B07021A483F0AB9
+:10FEB000001B00900C2D40D01420294641431448CB
+:10FEC0000122081884464168134892058646081B9B
+:10FED000904210D3631A93420DD302467046724586
+:10FEE00003D900984018401C05E0734524D9411AF5
+:10FEF0000819401C404200281FDA60460295857CA4
+:10FF00000198C0790028D5D003B0F0BD7A00002058
+:10FF1000D80B0020FFFF3F00FFFFFF00BC0B0020BD
+:10FF2000FF7F841E0020A10700E05EF80080841E91
+:10FF300000807BE1E00C0020FFDF0298854226D0A4
+:10FF400014214843FE490123401802908068FD496E
+:10FF50009B058C46011B8646994210D3221A9A4271
+:10FF60000DD36346614503D900997144491C06E0ED
+:10FF7000194662452DD9091A0819401C4142002929
+:10FF800005DD0298B17A807B814200D374460C2D46
+:10FF900015D0EB491420454368184268121B120221
+:10FFA000120ABA420BD2B37A827B934200D384689E
+:10FFB000857C0198C0790028A6D10C2DEAD1306843
+:10FFC000A042A1D0E0190002000A3460706003B0C2
+:10FFD000F0BDFFDFDBE7F0B5DB490446486885B0DC
+:10FFE000C005C00D1CD0103840B200280CDA020742
+:10FFF000120F083A920892005118C9698007C00E82
+:020000040001F9
+:10000000C1400806800F09E08108D04A890089189C
+:1000100009688007C00EC1400806800F002808D07C
+:1000200000272078002806D0012804D0002005B041
+:10003000F0BD0127F5E72079062813D201007944A5
+:10004000097949188F44020C0A080604002014E0BC
+:10005000B4200CE073200AE0322008E00A2006E019
+:10006000062004E0FFDF21790020002905D00221CD
+:100070004618B74D002F02D003E00421F8E7002016
+:10008000E871694602AAA068F8F7BDFF6946082230
+:100090008A56E06801A980180122C01C1F2801DAD5
+:1000A000019209E003AAF8F7AEFF6846007B00283A
+:1000B00002D00198401C019000990198401810301E
+:1000C0000002000A0190881B0002000A009060797B
+:1000D0006946887200980390F8F723FF009A019B05
+:1000E000121A181A9B4912020002120A000A8A42C6
+:1000F00016D8884214D86846FFF7CDFE00990398B9
+:10010000814205D088190002000AF8F771FFA0604B
+:100110000120E97900298AD0002FB0D005B0F0BDC8
+:100120000020F6E7F3B58FB08B480C460B9009F032
+:1001300057FB8A4A0F99864F5618894D203E002852
+:1001400008D08848007D002800D0FFDF20780128F3
+:100150007AD033E1687B162809D0687B297B401C64
+:10016000884200D1FFDF2078012804D009E0287BF5
+:100170000028F7D0F7E7F07F002800D0FFDF01204C
+:10018000F077697B0F981422774E514389190874D0
+:100190002078022822D0687B1421484386192079D0
+:1001A00030726079707232460C323146A068F8F7CE
+:1001B0002AFF0C2030560F2804DD1F3830733068BA
+:1001C000401C30600C217156301DE26801905018BF
+:1001D000C01C1F287EDA01200199DAE05A494868DC
+:1001E000C005C00D1DD0103840B200280CDA02073F
+:1001F000120F083A920892005118C9698007C00E80
+:10020000C1400806800F09E08108504A890089181A
+:1002100009688007C00EC1400806800F002800D181
+:10022000FFDF687B1421484386190021E0686A4695
+:100230000691117006A9F8F7E6FE6A4600201056EE
+:100240000F2802DD012001E0B2E0002006994018ED
+:1002500007900220B0722079307260797072A068C5
+:10026000311DC01C06911F2801DA012009E0F8F7B2
+:10027000CAFE68460078002804D0069806990068EF
+:10028000401C0860307A062813D2010079440979AD
+:1002900049188F44020C0A08060400200BE0B42021
+:1002A00009E0732007E0322005E00A2003E0062081
+:1002B00001E0FFDF0020217900295CD002214018F5
+:1002C0000690716810300818079908900918069868
+:1002D000081A00E051E00C900020F871F8F721FEB8
+:1002E00004463060079820180002000AF060787A0F
+:1002F0000C283CD0797A14204143114808184068F2
+:100300000899029040180002000A0390707A69462A
+:10031000887402A8FFF7BFFD0299039A091B121BFC
+:10032000090212020B4B090A120A0C9899421ED8B4
+:1003300082421CD80299069808180002000A15E0AB
+:10034000D80B0020FFFFFF0000ED00E000E400E01C
+:10035000E00C0020FFFF3F00EC0C0020B40C00205C
+:10036000940B0020A40B0020D40900203060F87901
+:100370000028B1D110E00421A1E704AA0199F8F7FF
+:1003800042FE6846007C002804D00198019900686C
+:10039000401C08602078B072687B162806D0687B05
+:1003A000401C68730B9809F033FA40E00020F8E72E
+:1003B000F07F002800D0FFDF0120F077FE490F9882
+:1003C00008742078022800D1FFDFFB4E20793072BC
+:1003D0006079707232460C323146A068F8F713FE2D
+:1003E0000C2030560F2804DD1F3830733068401C55
+:1003F00030600C22B256301DE16801908818C01C94
+:100400001F2802DA012001990BE003AA0199F8F7ED
+:10041000FAFD6846007B002804D001980199006825
+:10042000401C08602078B072E34901200875687BA1
+:10043000297B884224D07C7A0C2C23D0F8F771FDDC
+:1004400014214C43DD4961180A7C042A18D00A7C27
+:10045000032A15D04B6889681B1A081A1B02000270
+:10046000D74A1B0A000A112B0AD31146934207D818
+:10047000884205D8687B297B884201D0F8F79DFD2A
+:1004800011B0F0BD687B297B8842F7D111B0F0BD77
+:1004900010B50020F8F7B1FC10BD10B50120F8F739
+:1004A000ACFC10BDC74800787047F1B50098022831
+:1004B0001AD0C54C607A0C2800D1FFDF0026A67147
+:1004C0000125E572607A03211422BC4F5043C01904
+:1004D0000174F8F777FD009800280AD0012825D08C
+:1004E000032872D0FFDFF8BDB6480078F9F74FF85F
+:1004F000F8BDB648007F002800D0FFDF6571B34D1E
+:1005000000202E60F8F789FCA968481C04D001235C
+:1005100000221846F8F7B4FC607A617A401CC0B239
+:10052000142251437A5801219047F8BD0120F8F771
+:1005300074FC607900280DD0A4488068401C09D064
+:10054000607A617A401CC0B2142251437A58062165
+:100550009047F8BD9D48007F012807D002280FD0A2
+:1005600003281FD0042831D0FFDFF8BD20790028F0
+:1005700003D02671F8F72BFDE57094480677F8BD97
+:10058000207A002802D1F8F79BFD2572607A617A03
+:10059000401CC0B2142251437A58002190478B4826
+:1005A0000677F8BD894F0123397B78680022411A0C
+:1005B0001846F8F765FC2079002803D02671F8F773
+:1005C00006FDE57002203877F8BD19E07F4E2178EE
+:1005D00070680123411A00221846F8F751FC207A6E
+:1005E000002802D1F8F76CFD2572607A617A401C10
+:1005F000C0B2142251437A58002190473577F8BD94
+:10060000607A617A401CC0B2142251437A580521A5
+:100610008AE710B56C4C607A0C2800D1FFDF607A55
+:10062000617A401CC0B214225143644A52580421DA
+:10063000904710BDF0B583B0F8F773FC00900C2024
+:10064000614C0290617A624801900C2920D0617A55
+:100650001420414359480918097C042918D0617AAB
+:10066000142251430818007C03286ED00199009889
+:100670000A684968121A081A12020002504B120A3C
+:10068000000A112A61D319469A425ED888425CD882
+:100690004E488068401C00D0FFDF00206071607A07
+:1006A0000C2807D16078002804D04A48C1784170EE
+:1006B00081780170607A0C2815D0617A142041434A
+:1006C0003E480918097C04290DD1617A0291617AAA
+:1006D00001221423594309180A74617A59430818EE
+:1006E000807C6072A2723C4D687B297B3B4F8842C4
+:1006F00033D03B4E287B142148438019007CC05DD9
+:100700000128287B06D048438019007CC05D022860
+:100710002FD041E0142148438019807A01280AD063
+:10072000287B0221142250438019007CC155287B6C
+:10073000162808D00AE0287B002114225043801993
+:10074000007CC15528E0002002E0C5E1287B401C68
+:100750002873687B297B8842CCD1174D287D0028DF
+:100760005DD0287CC15D01293CD0C05D022844D009
+:100770004BE0287B142148438019807A012800D05F
+:10078000FFDF297B00201422514389198872297BBD
+:1007900051438919097CC855287B14214843821983
+:1007A000287B48438019017C0098FFF7B8F8287B24
+:1007B0001628CBD1C7E70000A40B0020D80B0020DF
+:1007C000FFFF3F0078000020E00C0020C00C00205C
+:1007D000D00C00207A000020940B0020B30C0020E5
+:1007E000D4090020A97A012904D00221C155002092
+:1007F00028750AE00021C15507E0A87A012800D039
+:10080000FFDF0020A872297CC855287D002806D06B
+:10081000297CFE4A0098FFF782F80020287502988C
+:100820000C281CD0014614204143F9480818017CCB
+:10083000012914D107210174F64D287E162839D0DC
+:10084000287EE97D401C884200D1FFDF297E029886
+:100850006854287E162831D0287E401C2876607A7D
+:100860000C287DD0A07A00287BD00020A072607A6E
+:1008700014214843E6494618E748B56873680246BC
+:10088000F6687C32C36796605560E44D687E002848
+:1008900016D00226607A1422DD4950434018407B6E
+:1008A00006281BD201007944097949188F440A149B
+:1008B00012100E0CE87D0028C7D0C7E70020CDE756
+:1008C0000426E7E700200BE0B42009E0732007E0EE
+:1008D000322005E00A2003E0062001E0FFDF0020CF
+:1008E0002873697E022901D0012910D12969009A53
+:1008F00009188A1A1202120A432A08D903206876B4
+:1009000032390802000A28613220287308E03228B0
+:1009100006D2207A00280AD1F8F7D2FB012005E0A0
+:10092000207A002803D0F8F7F4FB00202072BC499D
+:100930001122487820700978012901D0032906D1B5
+:1009400001212171297B884201D9421A1132A378F1
+:10095000002B00D0921C2179002904D1002B01E04A
+:1009600086E094E05AD09446AE4A00990092019AEB
+:10097000176852687F1A511A3F0209023F0A090A92
+:10098000BC451BD8A74A974218D8009A914215D85F
+:10099000297B884223D92B69421A9A1A1202120A19
+:1009A000101880190002000A2A616860002914D01A
+:1009B000032028770006000E3BD149E0002020717B
+:1009C000A070297B002922D02869401880190002D4
+:1009D000000A6860022028772BE00120E9E78142C5
+:1009E0000BD92A69511889190902090A6960002876
+:1009F00001D00420DDE70220DBE7002B00D1FFDF80
+:100A0000286980190002000A6860002004E0296952
+:100A100089190902090A6960287719E0287B0028EA
+:100A20000FD02969081880190002000A68600220A6
+:100A3000287728690123811900221846F8F720FA3F
+:100A400009E0286980190002000A68600020287700
+:100A50000120F8F7E2F9607A142148436C490C222E
+:100A600040188256012300206968F8F709FA0EE061
+:100A70000120F8F7D2F90020F8F7CFF9F8F7B6F926
+:100A8000207A002803D0F8F744FB00202072A078D9
+:100A9000002804D0F8F79BFA0020E070A07060787E
+:100AA000002804D05E48C1784170817801702079B7
+:100AB000002806D000205A49E0700978002900D1AA
+:100AC00020715448017EC07D814203D05648407851
+:100AD000F8F75DFD0120E07103B0F0BDF0B5534CB7
+:100AE0000746607A83B00C2800D1FFDF607A1421BA
+:100AF000474E48438019007C032800D0FFDF474D54
+:100B0000A868401C00D0FFDF607A14214843811997
+:100B10000C20085600216A4600911171C01901AAE3
+:100B20006946F8F770FA6A46042010560F2801DD6E
+:100B3000012000E000200099401869684018010277
+:100B4000090AA9606079002804D001230022184610
+:100B5000F8F796F903B0F0BD30B5364C344A0B1AAD
+:100B6000A34211D3451AA5420ED3934203D9101ABA
+:100B700043185B1C08E0954204D9511A0818401C20
+:100B8000434201E0FFDF0023184630BD10B50146A7
+:100B9000012300220220F8F773F910BD10B50220DE
+:100BA000F8F73BF910BD10B5F8F7BBF910BDF0B57B
+:100BB0001E4D0446E87A83B0002800D1FFDF642C84
+:100BC00068D31D4900200246091B824162D31B489D
+:100BD000417B007B81425DD10C48007D002859D1CA
+:100BE000687A14210A4F48430C4EC519306801AA8F
+:100BF00000196946F8F707FA6946042008560028E4
+:100C000002DD0098401C0090A96819E0A40B0020A8
+:100C1000D80B0020BC0B0020540C0020C00C00207E
+:100C20007A000020FFFF3F0078000020E00C002049
+:100C3000FF7F841E0020A107FF1FA107940B002047
+:100C400000986B680A18D21A12026D4B120A9A4267
+:100C500020D8AA7C0C2A08D014235A43D2195268EF
+:100C6000511A0902090A814214D3B068401C05D008
+:100C70000120F8F7D2F80020C043B06030680019B6
+:100C80003060A868009940180002000A70610120D5
+:100C900003B0F0BD002003B0F0BDF0B50646401E25
+:100CA000C5B21420574968434418207C002800D15D
+:100CB000FFDF5548017B407B81420CD0534A14230F
+:100CC0004B439B181B7CB3420CD016290CD0491CFB
+:100CD000C9B28142F3D14E48017D002964D0007C25
+:100CE000B04261D10020F0BD0021F1E7217C05294F
+:100CF00005D0217C062902D0217C072928D1012199
+:100D00002174C17D0023027E8A4221D00246565CB6
+:100D1000AE4201D1012301E0002B04D0162911D0ED
+:100D20004E1C965D565416290ED0491C167EC9B22B
+:100D30008E42ECD1002B0BD0117E002906D0117E03
+:100D4000491E04E00026ECE70021EFE716211176AA
+:100D5000617C00292AD06774C17D0023027E8A420B
+:100D600024D0425CAA4201D1012301E0002B04D02F
+:100D7000162912D04A1C825C425416290FD0491CF5
+:100D8000027EC9B28A42ECD1002B0FD0027E01460E
+:100D9000002A06D00A7E521E04E00022EBE7002162
+:100DA000EEE716220A7601E01A480027217C012985
+:100DB0009CD1617C002999D10120F0BD30B5054658
+:100DC0001420104A0521684380180174114C207EBC
+:100DD00016280ED0207EE17D401C884200D1FFDF26
+:100DE000207E2554207E162807D0207E401C2076A9
+:100DF00030BDE07D0028F2D0F2E70020F7E70000E8
+:100E0000FFFF3F00D80B0020940B0020D4090020E6
+:100E1000A40B0020BC0B0020F0B5794A1468794E71
+:100E2000002533780121002B06D1774B5D60032725
+:100E30009F6004271F6131701560744BD960196081
+:100E4000724E714D40364035F160EF688742FBD3FA
+:100E50005960D9601460F0BDF8B5044680070025DC
+:100E60000126002804DA6A48C563C6630220844369
+:100E7000684FE00405D5684846606848876080147C
+:100E80008443600003D56648456080058443E005DF
+:100E90000CD55B480560634887605B4845608560AA
+:100EA000042101615948066180158443A00409D5D5
+:100EB0005D4846605D4805605D4887605D48456007
+:100EC000401484436004C10F20040090C00F81428D
+:100ED00000D0FFDF0098800F13D057484660574876
+:100EE000876057498E6057480560574A9760574852
+:100EF000056046608E609760056046600320800351
+:100F0000844320050BD5524846608660514887606F
+:100F100050484030876050488560C014844308F0D2
+:100F2000B1FD4E48044200D0FFDFF8BDF0B500210E
+:100F300020270A46FF230446CC40E4072ED04CB2BB
+:100F4000E606F60E0125B540454E3560454E356046
+:100F5000002C13DA25072D0F083DAE08424DB600D0
+:100F60007619F569B446A407E40E1E46A640B543BB
+:100F70001646A64035436646F5610FE0A6083B4D90
+:100F8000B60076193568B446A407E40E1E46A6409E
+:100F9000B5431646A640354366463560491CB942FE
+:100FA000C9D3F0BD70B5174C0D466060FFF754FF14
+:100FB0006068FFF7BBFF2846F8F74DF908F0C2F963
+:100FC00000F000F908F05EFD08F0ADFCF8F7ACFAAF
+:100FD00008F050FA70BD10B50A4C6068FFF73CFF8E
+:100FE0006068FFF7A3FF08F04DFDF8F7E6F9002071
+:100FF000606010BD034840687047022070470000E1
+:1010000000820040800000200085004000800040F9
+:10101000C01F0040FFFFFFFF00C0004000C30040B2
+:1010200000E501400083004000D0004000D20040B5
+:1010300000D3004000D5004000E0004000E3004045
+:1010400000F0004000F2004000F3004000F50040D6
+:1010500000B0004000B3004000B50040FEFF0FFCB0
+:1010600080E100E080E200E000ED00E000E400E06C
+:1010700070B51E490A68002A17D000231D460124B6
+:101080004A68521C4A60092A00D34D600E792246F4
+:10109000B2400E6816420AD072B60B6893430B60DA
+:1010A00062B649680160002070BD052070BD5B1C00
+:1010B000092BE5D3FFDFF8E701200D498005086023
+:1010C0007047EFF31081CA07D20F72B60121814039
+:1010D0000648036819430160002A00D162B6EBE7B5
+:1010E0000248002101604160704700008800002034
+:1010F00000E200E0012081070860704701208107BD
+:10110000486070471048C068C00700D00120704791
+:101110000D488068C00700D0012070470A48406928
+:10112000C00700D0012070470748C06970470649D2
+:101130008A69D20306D589698907890F814201D15D
+:101140000120704700207047000400408107C90E4D
+:10115000002808DA0007000F08388008BD4A800020
+:101160008018C06904E08008BB4A800080180068CD
+:10117000C8400006800F7047B8494878897888428F
+:1011800001D3401A02E02122511A0818C0B2704758
+:10119000B249233148788978884201D3401A02E065
+:1011A0002122511A0818C0B27047AC49463148781C
+:1011B0008978884201D3401A02E02122511A081886
+:1011C000C0B27047A44910B50C310868FF22120262
+:1011D00090430122D20310430860A049002023312C
+:1011E000487088702339487088704631487088701C
+:1011F0009B4808F0EDFA9A48401C08F0E9FAF8F725
+:1012000039F900F01DF910BD20207047B4E770B522
+:101210000C4605460026FFF7AFFF9049A04214D3C5
+:101220000A46203A00232046641EE4B200280BD070
+:101230008878105C287088786D1C401CC0B288705B
+:101240002128F0D18B70EEE7012600F0F9F8304646
+:1012500070BD202070479BE770B50C460546002600
+:10126000FFF796FF7D492331A04214D30A46203A66
+:1012700000232046641EE4B200280BD08878105C5E
+:10128000287088786D1C401CC0B288702128F0D16D
+:101290008B70EEE7012600F0D3F8304670BD2021B8
+:1012A00001700020704710B50446FFF77EFF2070E4
+:1012B000002010BD70B50C460546FFF776FF674964
+:1012C0004631A04215D30A46203A00232046641E28
+:1012D000E4B200280BD08878105C287088786D1CE8
+:1012E000401CC0B288702128F0D18B70EEE700243A
+:1012F00000E05C4C00F0A4F8204670BD70B50C46D0
+:101300000546212900D9FFDF52484068103840B215
+:10131000FFF71CFFC6B20D20FFF718FFC0B28642D0
+:1013200003D2FFDF01E0F8F7E2F821462846FFF795
+:101330006EFF0028F7D070BDF8B507464848474C07
+:10134000401E464E0078254646362335002806D1F5
+:10135000A9786878212200F068F800280ED0A178DA
+:101360006078212200F061F8002814D0B1787078FC
+:10137000212200F05AF8002828D033E03749687855
+:10138000C91C0F546878401CC0B26870212829D14C
+:101390000020687026E03149607820390F54607869
+:1013A000401CC0B26070212801D1002060702C4F19
+:1013B0007F1E3878002815D0A1786078212200F0AF
+:1013C00034F800280ED0002038700BE023497078E4
+:1013D00026310F547078401CC0B27070212801D1A2
+:1013E00000207070A9786878212200F01EF800288B
+:1013F0001AD0A1786078212200F017F8002813D0C5
+:10140000B1787078212200F010F800280CD0F8F79D
+:1014100053F8134808F0E4F901214903884200D049
+:10142000FFDF0F4808F0F4F9F8BD401C884205D0F2
+:10143000904201D1002901D000207047012070475F
+:1014400010B5074808F0CCF9002801D1F8F723F8C7
+:1014500010BD000000ED00E000E400E0100D0020F1
+:1014600091000020072000000C4908784A78401CB1
+:10147000C0B2904200D008707047094A074820BFA8
+:1014800040BF20BF4178037843701368002B02D11E
+:1014900003788B42F3D000207047000093000020B7
+:1014A00000E200E0F0B50121184A08031060184A74
+:1014B00000231360174B1860174803690569DB4365
+:1014C000DB06DB17102425430561144D6960144EBB
+:1014D00031605B1C00E020BF1768002FFBD0002BA1
+:1014E00002D10369A34303610E4880687160A9605B
+:1014F000002111600121074A09031160F0BD10B5F8
+:101500000446FFF7CFFF2060002010BD80E100E01F
+:1015100000C1004080E200E000ED00E000C30040B8
+:1015200000C0004000C50040FEB5EA4C07466068B8
+:10153000FF213E0181552178FF2913D0090108318F
+:1015400041583246491E083209020192090A805860
+:1015500000F0B6F9002802D02478254615E061682D
+:10156000207888552770FEBDDA48426801981158E6
+:10157000280100900830105800F0A2F9002806D188
+:10158000D4482C46416800980D5CFF2DECD1D14821
+:101590002101406885554754FEBD70B5CD4A0446CB
+:1015A0000020157A53680AE00201561C9E5DA6428F
+:1015B00003D10C329A588A4204D0401CC0B28542F2
+:1015C000F2D8FF2070BD10B5FFF7EDFAC14C01460F
+:1015D0002078626800010830105800F071F9012885
+:1015E00007D920786168000108300858FFF7CEFA63
+:1015F00010BDFEF757FFF7F7CAFF10BDF8B5B54F9E
+:101600003E78FFF7D0FA0146FF2E68D03401254618
+:1016100078680835405900F053F9022802D97868F3
+:1016200040595AE0AB494868025D0A70A11C425C0F
+:10163000002A0CD0521E425441590122D205891869
+:101640000902090A41513046FFF76EFF30E0631C82
+:10165000C25C0092221D94468258002A10D00123B9
+:101660009B029A420FD99205920D43595703DB19F9
+:101670001B021B0A43516346C3589A1A920A09E097
+:10168000FF21C1540AE0435952039A181202120A68
+:101690004251002242543046FFF746FF8D480C3439
+:1016A0004168C26800980959800012580098904714
+:1016B000884C2078FF2812D0FFF775FA0146207871
+:1016C000626800010830105800F0FAF8012896D935
+:1016D00020786168000108300858FFF757FAF8BD14
+:1016E000F0B51D4614460E460746FF2B00D3FFDF1C
+:1016F000A00700D0FFDF7748FF21C7604460057274
+:101700000674017000224270104604E00201521C6F
+:10171000401CA154C0B2A842F8D3F0BD70B56D4CC6
+:1017200006466578207C854200D3FFDFE068A9008B
+:1017300046506078401C6070284670BDFFB581B08F
+:101740001D46FF24FFF72FFA624F0646797801986D
+:10175000814200D8FFDF5F480021037A406810E033
+:101760000A019446521C825CFF2A25D0019FBA428E
+:1017700005D162460C328758029A97421ED0491C06
+:10178000C9B28B42ECD8FF2C18D021014A1C019B16
+:1017900083540B460C33029AC250039B4D4F0022D8
+:1017A000012B0ED00B1DC25001239B029D4216D966
+:1017B000AA05920D08D008E00C46E0E7FF2005B02E
+:1017C000F0BD0B1DC550EFE71A4653039B190E469B
+:1017D0001B0208361B0AAA1A8351920A09E0002D3F
+:1017E00000D101256B039B191D022D0A0B460833FE
+:1017F000C550891C42543D463E782046FFF794FE72
+:101800002878B04201D0FFF7DEFE0198D7E770B527
+:101810000C460546FFF7C7F9064621462846FFF75E
+:10182000BCFEFF2817D02B4D040120466968083004
+:101830000858314600F044F801210903401869684E
+:10184000A41C095D400B002901D08902081800285A
+:1018500000D1012070BD002070BDF3B581B00F46EE
+:101860000198FFF79AFEFF2819D01A4E3578716853
+:101870002A462C4604E0844205D025462301CC5C50
+:10188000FF2CF8D10BE0FF2C09D0A5420BD11001A1
+:10189000085C3070FF2804D0FFF795FE03E00020BD
+:1018A000FEBDFFF77BF939460198FFF7B0FF220133
+:1018B0007168FF23541C0B558A5C2B01CA54FEBD72
+:1018C000401A00020121000AC905884200D90020FF
+:1018D000704700005C0D002070B504462748844224
+:1018E00001D2012500E0002500F03FF8244900283E
+:1018F00006D08C420BD32348006804E0284370BD17
+:101900008C4204D32048844201D20120F6E7002013
+:10191000F4E710B5044600F028F8012189070028F3
+:1019200006D01848006804E08C4204D2012003E08D
+:1019300015488442F8D200200121484010BD10B55E
+:10194000002805D0FFF7E5FF002801D0012010BDD9
+:10195000002010BD10B5002805D0FFF7BDFF0028FE
+:1019600001D0012010BD002010BD084808490068C2
+:10197000884201D1012070470020704700B001006B
+:10198000000000201C00002008000020980000201B
+:10199000BEBAFECA3B48002101704170102181701F
+:1019A000704770B5064614460D460220F1F78CFAD2
+:1019B00001203449344A0870E41E14619660556071
+:1019C00070BD10B50220F1F77FFA2E490120087092
+:1019D0002E48002101604160816001202C49C00532
+:1019E000486010BD10B527480178002917D00121A3
+:1019F000274AC905916025490B680022002B05D0B4
+:101A00004B68002B02D08968002902D04270102157
+:101A100003E0012141701F490968817002700020B4
+:101A2000F1F752FA10BD17480178002912D0174873
+:101A3000016800290AD00168002905D04168002901
+:101A400002D08068002803D0002070470220704731
+:101A500001207047407870470A48017800290FD06C
+:101A60000A480168002905D04168002902D0806831
+:101A7000002801D01020704706480068C0B27047A7
+:101A8000807870479C00002000F5004000F1004085
+:101A900000F5014000F400402C4800210170417025
+:101AA000704770B5064614460D460120F1F70CFA52
+:101AB00026490120264B08709E60DC601D6170BDC8
+:101AC000F8B504460120F1F7FFF92049012008701C
+:101AD0001F494C601F4900264E6003211E4D090618
+:101AE000A9601E4F002C07D0012C00D0FFDF3E6004
+:101AF000032000066860F8BD386001200006F9E7A1
+:101B000010B51248017800290ED00321124A0906A7
+:101B1000916010494A680021002A03D0104A1268D7
+:101B2000427000E0417001700020F1F7CDF910BD66
+:101B300006480178002907D006484068002802D0EE
+:101B400007480068C0B27047407870479F00002087
+:101B500000F5004000F1004000F5014000F20040B7
+:101B600000F4004070B5FC4D00246C702C706C616A
+:101B70006C72AC720120E8726C776C62F748EC62B0
+:101B800007F026FE002800D0FFDF2C7670BD00B5E0
+:101B9000F349002803D0012805D0FFDF00BDF1483C
+:101BA0004861F14802E0F1484861F148886100BDB0
+:101BB000F0B50125EF4902260E60EF490027CF63FB
+:101BC000CD63EE49C96A09070DD4ED49CB6AED4AE8
+:101BD00053620B6B93624B6BD3628B6B1363C96B5A
+:101BE000D30519435163DE4C00281FD0012821D0B2
+:101BF000FFDFE548A063FF20043060632563032016
+:101C00002061E24996204860D349182008560722EF
+:101C1000D243811A90422ED011DC163134D00A29D9
+:101C200030D00E292CD012290FD127E0CD48606189
+:101C3000CD4802E0CD486061CD48A061D9E7001DE4
+:101C400017D0042813D008280ED0FFDFD149D04880
+:101C50008860D248D0494160D1490160D1480660CE
+:101C6000D14910204860F0BD0420E060EEE7E76055
+:101C7000ECE7FC2000E0F820E060E7E7F420FBE779
+:101C8000F020F9E7EC20F7E7D820F5E710B50C468F
+:101C90000146C64808F0FFFEAF48047210BDAE48CA
+:101CA000407F7047AC4A517010707047F0B50446E1
+:101CB0000D4650791179000208436900091908841A
+:101CC000501C01460E78012730464E7836023043CC
+:101CD0008E78C9783604304309060843117800022B
+:101CE0000843A9006050284608303E468640002B35
+:101CF00008D0012B00D0FFDF206B3043AF403843CA
+:101D00002063F0BD206BB043F8E730B50D460446C4
+:101D1000082900D9FFDF0022002D0CD9A44891002A
+:101D2000635809180B6053001B191B8C0B62521C63
+:101D3000D2B2AA42F3D3206B9E49086030BD10B5E1
+:101D400004460722D2430830854994421AD008DC61
+:101D500016301FD00A281BD00E2817D0122806D103
+:101D600012E0201D0CD0042807D0082803D0FFDF84
+:101D70007948047610BD042000E00020C860F7E731
+:101D8000FC20FBE7F820F9E7F420F7E7F020F5E77F
+:101D9000EC20F3E7D820F1E78748007A70477049D4
+:101DA000C2784A6202461378184653781B021843D9
+:101DB0009378D2781B041843120610430002C861BE
+:101DC0007047252808D0262808D0272808D04100A9
+:101DD0000A2807D8091D06E0022105E01A2103E0C0
+:101DE000502101E0891DC9B25D4A9160674948618F
+:101DF0007047594948617047F8B5002812D0022051
+:101E0000554E6E4AB07203231360624C604A6260A2
+:101E100001276B4D002907D001290BD002291DD0C5
+:101E2000FFDFF8BD0120EBE7012801D06F60F8BDAE
+:101E30002F60F8BD48490128C96A03D0022807D09D
+:101E4000FFDFF8BD012000050143F1626060F8BDCD
+:101E5000012040050143F1626060F8BD706900280F
+:101E600000D1FFDF7169706A4018564988604B489D
+:101E700055498160B17A012917D05449C1600120C8
+:101E8000F16AC0030143F1624C490E68464A1020D2
+:101E90009060002008603F4A09149160FF216A4663
+:101EA00011704B4C20612F6104E0C560E7E71078AA
+:101EB000401E10701078002802D020690028F6D04B
+:101EC0001078002800D1FFDF0020E0602061606012
+:101ED0006061A0613948066001142E484160324AB1
+:101EE00010215160C9024160F8BDF8B5334801685E
+:101EF0008F082D49BF004A68D206D60F10228A608B
+:101F000000240460234822498160FF20694608704C
+:101F10002F4D2C612A490120086103E069460878A9
+:101F2000401E087068460078002802D02869002802
+:101F3000F4D068460078002800D1FFDF2C61064805
+:101F4000012144728472C1721C480760002E02D0C5
+:101F5000154910204860F8BD700D0020A00D00202C
+:101F600000150040060102002500030205010300E0
+:101F70001F00030280E100E0C01F0040800000104D
+:101F8000C0000010001700405B0600004015004034
+:101F90000040000400F501404080004080F5014011
+:101FA0001011004080E200E000130040720D00209C
+:101FB0000016004040160040900D00200012004026
+:101FC000001000404085004048810040041000405F
+:101FD0000011004001460A7810464A781202104368
+:101FE0008A78C97812041043090608430002FD49A3
+:101FF000000AC8637047FC4902200860FB4908607A
+:102000007047FB49022008607047FA490870704722
+:1020100010B5F94807F0E4FB002800D0FFDF10BD41
+:1020200010B5F54807F0F4FB10BDEE494860704765
+:1020300030B5F24C0546606AA84200D3FFDF0120AC
+:102040002073EF49002025614860EE48456001207B
+:10205000E16A80050143E162EB49486030BDE74831
+:1020600002210173C6210161E54A00215160416AE4
+:10207000E44AC63151600121C26A89050A43C2623D
+:10208000E148416070470121DF4889058160DB48F4
+:10209000C26A8A430021C26201737047DB48012192
+:1020A0004160C160D64900204860D6494860D349A4
+:1020B00048627047D64940200862D6490A68024300
+:1020C0000A607047D3480168402291430160D049BB
+:1020D000002008627047CF480168102291430160D8
+:1020E000CD49012088617047CC490020C861C948AA
+:1020F00001681022114301607047C849CA69012A6A
+:1021000001D000207047C24A92685206520E5242D5
+:1021100002700020C8610120704730B50C000546F0
+:1021200000D1FFDFE00702D0012C00D0FFDF002D3F
+:102130000AD00221B14801294172C472B54805D0C4
+:10214000022908D0FFDF30BD0121F3E70168042236
+:102150001143016030BD016808221143016030BDA8
+:10216000F8B5A64C0025E17A8A0701D5420712D4BA
+:10217000CA0606D5AA4A537A002B02D0927A002AC0
+:1021800009D00A0702D5227F002A04D1490703D5C6
+:10219000617F002900D10125677A002201239D4932
+:1021A000002F1AD00226304028433BD0086886080A
+:1021B0009C48B6004568ED06ED0F102787600020AB
+:1021C0000860914A98499160FF216A461170934FC7
+:1021D00038619149012008610CE08B4D9248A8605C
+:1021E0000868800880000860A272E372F8BD107869
+:1021F000401E10701078002802D038690028F6D0F0
+:102200001078002800D1FFDF002038616072A072D2
+:102210000120E0727F480660002DE7D08148102140
+:102220004160F8BD012F03D0022F09D0FFDFF8BDB8
+:1022300008680425A84308606272E372A372F8BDBF
+:1022400008680825A84308606272E372A672F8BDA8
+:10225000F8B56A486C49C26A8A600021C162017B94
+:10226000674D002902D06968012909D000236B4C11
+:102270002169012906D00022817A012904D006E0D3
+:102280000123F4E74022F7E7E668012E04D0002698
+:102290001643012902D004E02026F9E76268012AEA
+:1022A00005D000223243614F022902D007E01022FC
+:1022B000F8E73E68012E02D1E668012E04D0002620
+:1022C0001643022902D007E00826F9E73A68002AF7
+:1022D00002D1E268012A04D000223243022902D04E
+:1022E00005E00422F9E7002B01D0022300E00023DF
+:1022F0001343022907D16068012804D168680128C6
+:1023000001D0012700E0002749481F430168090662
+:10231000090E02D06169012900D00021404E3172BE
+:1023200000680006000E02D0A069012800D000203D
+:1023300070723748006A002803D0FFF774FB012849
+:1023400000D00020B0720026E660266166606661FB
+:10235000A6612B4846602B483D464168274C2162C8
+:1023600000686062A07A022809D16078002806D04F
+:102370001C4A526812780240207890430CD026778D
+:102380001C4FE8070BD038782A4A400880001258C2
+:1023900008469047012109E001202077F0E7A806D0
+:1023A00001D5022102E0A80707D500213A78224B87
+:1023B000520892009A58606A90473878C0073FD117
+:1023C000084841680622A01C093108F09BF8002843
+:1023D00034D10448217A40680078C00981422DD167
+:1023E00001202CE00015004080E100E080E200E0E8
+:1023F00000E100E0A1000020A00D0020700D0020F1
+:10240000408100404085004000F5014000800040D0
+:102410004015004000120040001000400011004034
+:10242000900D002000130040004000040014004004
+:102430004016004028AE010030AE01000020607759
+:102440002846FFF78DFEA80704D53878214980007B
+:10245000085880472807810F05D03978C00F1E4AD9
+:10246000890051588847A80604D538781B49800050
+:10247000085880473878022805D16E200540402D45
+:1024800005D101F048F83878042800D3FFDFA07A9E
+:10249000022818D1207B002815D011494E6002284F
+:1024A00012D0012800D0FFDF616A2069884200D87D
+:1024B000FFDF0C48216941600120E16A800501438A
+:1024C000E16209494860F8BD2169606A4118054820
+:1024D0004160F1E738AE010048AE010058AE01009E
+:1024E000408100404085004000F5014010B548485B
+:1024F00006F06CF90021464806F0A1F90121444894
+:1025000006F069F9434800218170444942488884B3
+:1025100043490880488010BD10B53D4806F056F983
+:1025200000213B4806F08BF90121394806F053F9A8
+:1025300038480021817039493748888438490880F3
+:10254000488010BD704735498A8C824204D1314899
+:1025500000228270501E888470472D4901607047A8
+:102560002F49088070472D492B4A898C914209D107
+:1025700028498A782039012A02D001600120704759
+:102580000020704700210160084670472548017807
+:10259000012907D001210170214820490088888441
+:1025A00001207047002070471D49488070471B4933
+:1025B0001B4A898C5288914207D116498A78203962
+:1025C000002A02D0016001207047002070471348A4
+:1025D000134A818C528891420AD10021C9438184D7
+:1025E00022300178002903D00021017001207047BA
+:1025F0000020704709480A49808C4988884205D1E3
+:1026000004488078002801D00020704701207047DE
+:10261000CA0D0020C40D0020FFFF0000A40D002003
+:10262000A2000020C60D002070B5FF4E0446307990
+:102630000025012805D0FD4EB07901280CD00020DE
+:1026400070BD002915D1657014202070F849A01CB8
+:1026500008F02EFA35710CE000290AD165701320BC
+:1026600020701C22F349A01C07F079FF0120A07103
+:10267000B571012070BDED488079002802D0EE4888
+:10268000408D7047ED487047F8B5ED480178002956
+:1026900002D00C263046F8BD0026E74D34462E7594
+:1026A0006E75AE75EE752E766E76E6496E734E7368
+:1026B000DE4F7F213E718170A87E002804D0FFF795
+:1026C00001FDFFF78FF9AC76BC71DF4805F01CFF08
+:1026D000DE4805F019FFDDE770B5D94A0024147013
+:1026E000DB4B1966D8651078002801D0FFDF70BD7C
+:1026F000D14D2C756C75AC75EC752C766C76D1481B
+:102700006C734473C94E7F2034719070A87E00288A
+:1027100004D0FFF7D7FCFFF765F9AC76B471CA486F
+:1027200005F0F2FEC94805F0EFFE70BDC248007D1D
+:10273000704700B5C049C87B897B42078307D20F29
+:10274000DB0FC007D218C00F10184000052911D2A6
+:102750000A007A4412799218974409050902070081
+:10276000BC49085A00BDBC4800BDBC4900E0BC499A
+:10277000085A00BDFFDF002000BDAF48B949008AFC
+:1027800048437047A9484079002800D0012070478D
+:10279000F8B50646A84C407BE07330790027A0735B
+:1027A000012825D030882082A048B37B4371A84DF2
+:1027B000AD482970114608F06EF9B0796873F11DC3
+:1027C000AA4808F068F9607B0126002800D06675E9
+:1027D0009C48407B002800D0A675A07B052831D2FC
+:1027E00001007944097949188F4404092227090016
+:1027F0002782D9E70021944805F08BFE23E00121D0
+:10280000914805F086FEE91D8F4805F0B4FE687B0F
+:10281000002803D0012806D0FFDF14E000218A48F9
+:1028200005F0BAFE0FE00121874805F0B5FE0AE089
+:102830000621854805F06DFE05E00221824805F07D
+:1028400068FE00E0FFDFE7752776691C7E4805F02B
+:1028500086FE29787C4805F093FE04217B4805F02C
+:1028600058FE691C794805F07AFE2978774805F00A
+:1028700087FE26750020F8BD70B56F4C01252576C2
+:102880006A4A9279002A01D03A2070BD704A1378C2
+:102890000022834205D1E275734808F0FCF8E57523
+:1028A00000E02276002070BD70B50446624D002025
+:1028B000A87522466E4807F052FE62484473012014
+:1028C000A87570BD10B55C4C00226275607302463D
+:1028D000684807F044FE0120607510BD5349087137
+:1028E0007047F8B5564D287800282FD1524C207DDE
+:1028F00000282BD0FFF78CFB0026A674E6746E70C0
+:102900003046FFF782FB0020FFF752F95A48FFF7E5
+:1029100046FA5A48FFF75EFBFFF7A1FBE07B012771
+:10292000C107002902D0A17CC90711D0810718D5A1
+:10293000A17C890715D42620FFF743FA0020FFF772
+:1029400026F9A07C02210843A07419E00C20F8BDF0
+:102950002520FFF736FA0020FFF719F9A07C38434D
+:102960000DE040070CD5A07C400709D42720FFF7D5
+:1029700028FA0020FFF70BF9A07C04210843A0747B
+:10298000FFF73FFB01210020FFF736FA0F2105205A
+:10299000FFF788F92E4D2978681CFFF777F9A07B9F
+:1029A00001280AD0042808D0607D002805D0627B69
+:1029B0003049254805F00AFE6675A07D002806D03E
+:1029C00020482B49427B983005F02CFEA675286ED6
+:1029D0000178002903D00178001DFFF796F9E86D12
+:1029E0000178002904D0264A401CFEF7DAFFA776BA
+:1029F000FFF716FB0020F8BD114948607047F8B595
+:102A000001260D4C054600285DD0E07B2146C2071B
+:102A1000897C002A01D0CA073ED0820745D58A07A3
+:102A200043D426202EE000006C0E00204C0E002027
+:102A3000710E0020540E00202C0E0020FFFF00001D
+:102A4000A80000200C0E00207C0E0020A40E002008
+:102A5000EC0D002078AE01009A89130080AE0100D1
+:102A600070AE010071020000ED0D0020F30D00209A
+:102A7000FA0D00201A0E00206BAE010068AE0100B6
+:102A8000CF0E0020FFF79DF90020FFF780F8A07C13
+:102A900002210843A07416E02520FFF792F90020D8
+:102AA000FFF775F8A07C3043F4E740070BD54807E3
+:102AB00009D42720FFF785F90020FFF768F8A07CEC
+:102AC00004210843A074E07C002806D0A07B0128E4
+:102AD00000D1FFDF00F058FAF8BD002D03D002212D
+:102AE0000020FFF789F9E07D002700280AD0FE4D7D
+:102AF000FE48691C05F033FD691CFD4805F02FFDFB
+:102B0000E7752776F948FFF790FAA07B05280CD2E5
+:102B100001007944097949188F4402020208020031
+:102B200001210846FFF7F9FA00E0FFDFE07BA17C16
+:102B3000884303D1A07B012803D0E674ED480670DA
+:102B4000F8BDA774FAE710B5FFF762FAE948007814
+:102B5000002808D1E848007D002804D00020FFF7B5
+:102B60004EFF002010BDFFF799FAFFF78CFAFFF730
+:102B7000BCF9FFF740FAFFF753FA0C2010BDDD490E
+:102B8000012048707047DC494876704770B50024D2
+:102B900002F06DFB00280DD0FF202D30FFF729F942
+:102BA000D44E3078012808D0022801D003282CD038
+:102BB000FFDF70BD00F0E8F970BDCF4DA87B0328A2
+:102BC00023D0A87E002803D0FEF7FBFEFFF772FAA1
+:102BD000CA48FFF72AFAA87BC94D01280DD004285E
+:102BE0000BD06879012801D0032800D110240E20D1
+:102BF000044321460020FFF790FA2879012801D1EB
+:102C0000FFF772FA0220307070BD0120FFF7F7FE67
+:102C100070BD70B5BA48B74C0079012808D1B948E1
+:102C2000FFF76BFA002801D17F20A070FFF753FA5D
+:102C3000B14DA87E002803D0FFF744FAFEF7D2FE7C
+:102C400002F015FB002807D02078022800D0FFDF13
+:102C5000A87B012803D006E000F096F970BD99200A
+:102C60008000FFF7C6F80120FFF7C9FE2078002892
+:102C7000F4D020780128F1D0FFDF70BDF0B5044614
+:102C800089B000200690FFF787F80190002002909D
+:102C900098480078022800D0FFDF994E307901284B
+:102CA00009D19848FFF729FA002802D191497F20DD
+:102CB0008870FFF710FA914805F04DFC8E4D0746DD
+:102CC000002C79D08D4805F041FD002874D0FEF726
+:102CD000E6FF002870D0A87E00280AD02824641EB1
+:102CE000E4B2FEF7A0FE022811D0012800D0002097
+:102CF0000290824A844CD01C0090062F76D2380075
+:102D00007844007900188744717171067135002C80
+:102D1000E5D1FFDFEBE7A87B012867D0042865D069
+:102D200002990198084304D17079002801D0022843
+:102D30005CD13079012816D12079002813D10120E7
+:102D4000207110784006C00F60717048009907F03C
+:102D5000A2FE684C6E4EA0787F2800D1FFDFA078DD
+:102D600030707F20A0706248FFF75FF9614803214F
+:102D700001703DE05C48D178C07981421DD15A484C
+:102D80001179037A994218D15179437A994214D131
+:102D90009179837A994210D1D179C37A99420CD131
+:102DA000117A037B994208D11178407B4906C90FFB
+:102DB000814202D1012101E018E00021A87B012815
+:102DC00001D0042801D100290AD100280ED102998E
+:102DD0000198084304D17079002801D0012805D159
+:102DE000287E002802D1687E00281BD00120069092
+:102DF000A87E002803D0FFF765F9FEF7F3FD0698DB
+:102E0000002802D00120FFF7FAFD3A480178002996
+:102E100006D00178012903D00078032800D0FFDF15
+:102E200009B0F0BD33483B4F4068397B4173797B33
+:102E30008173B97BC173F97B0174F91E0978490666
+:102E4000C90F41761A30009907F025FE2948397CD0
+:102E500040684174797C8174B97CC174F91E897DA4
+:102E6000017500994A7D0B7D11021943C182F91E3B
+:102E70008A7E4B7E12021A434280009A537E177E4E
+:102E80001A023A4382808A7F4B7F11021943C18024
+:102E90002149083007F0F4FD20480179CA06154998
+:102EA000D20E49680A7600794009C0310873B079BA
+:102EB000002800D0FFDF002030720E481849476814
+:102EC00038886885787E70737A8B8A81BA8BCA81DC
+:102ED000F88B08820448134900783075124807F0CF
+:102EE000DAFD7888A88721E0EC0D00207C0E002018
+:102EF000A40E0020A80000202C0E0020CC0E0020E4
+:102F00004C0E0020AA0000206C0E0020720E002043
+:102F1000780E0020CF0E0020EB0E0020EC0E0020DB
+:102F20004E0E0020ED0D0020610E0020B888E887CD
+:102F3000F8882080C037387BA07002980028E0789D
+:102F40000BD001210843E070FEF786FDE1784000D8
+:102F5000C907C90F0143E17002E040084000E0707A
+:102F60000120B071294C00202070FFF797F8FFF77F
+:102F70008AF8FEF7BAFFFFF73EF8FFF751F8012095
+:102F8000616802F057FA33E7F8B5FFF787F8FFF703
+:102F90007AF8FEF7AAFFFFF72EF81D4E0027B07E45
+:102FA000002804D0FFF78EF8FEF71CFDB776174D0A
+:102FB0002F70FFF735F8B07B012804D000210846B8
+:102FC00002F038FAF8BD0021022002F033FA114C69
+:102FD000A079002800D0FFDF68780028F2D00E48E2
+:102FE000417B6173007820750C490D4807F053FD53
+:102FF0000C490D4807F04FFD3C202072686800889E
+:1030000070850120A0716F70F8BD0000A80000203D
+:103010002C0E00204C0E0020EC0D0020F30D0020A3
+:103020005A0E0020ED0D0020610E0020F8B5FC4F77
+:103030000A46044600207978FA4D0646002902D057
+:10304000012909D00FE0F849497A00290BD0002A5C
+:1030500008D10120787005E0A97F002903D0002A5B
+:1030600000D17E70012079782B23594349198B7F39
+:10307000034311D0002A22D12A22A01C1F3107F0BD
+:103080006EFA6670042020700120A07078782B21E1
+:1030900048434019867712E02878012801D00020A3
+:1030A000F8BD002A0BD16670132020701C22A91CC9
+:1030B000A01C07F054FAA6712E70DC48C6770120D8
+:1030C000F8BDD8480178002901D080887047D848D9
+:1030D0007047F8B5D34E0746B07F00282DD138464B
+:1030E00005F039FA00210125D24C072824D202002C
+:1030F0007A441279921897440305081F1F1F0A008B
+:10310000217006E02570217208E0032000E0022013
+:103110002070C949384605F06FFA2072384605F02C
+:1031200037FA6070C549384605F01EFABC4CC44FEA
+:1031300020787F2803D101E02172F8BDFFDF2078DD
+:1031400038707F202070B577032001F06AFAF8BD4F
+:1031500010B5002001F0FAF9002812D0FEF751FF57
+:1031600000210120FEF748FEB648FEF75EFFAF4C97
+:10317000A06AFEF75DFF2079032805D0022803D05E
+:1031800006E000F01AFD10BD01210020FEF7C5FF8A
+:10319000FEF7AAFFAC4C6078002803D0FEF711FCC4
+:1031A000FEF788FF0320E07010BD70B59F4900282E
+:1031B000CA8D08D0FF2A0DD25004000CC885FF2804
+:1031C00008D9FF2005E0012A04D95008C88501D19B
+:1031D0000120C88592484268012A01D0002A01D105
+:1031E0000D224260D2431723974C5A43637B3B2501
+:1031F000DB436B43D2184260C98D900C07F029FA6B
+:10320000617370BDF8B5904CE078022804D0E07886
+:10321000012801D00C20F8BD0020824A05462B2150
+:10322000414389188D77401CC0B20228F7D315702E
+:103230006078002804D0FEF745FFFEF7D3FB6570E9
+:103240007A4845778577C5778049257001228A7746
+:103250000571A570CA760A774A77724E01463246E2
+:10326000736F7432B46FF66FD7688B60CC600E6189
+:103270004F6112698A6105770020F8BD10B5724A66
+:103280000023D370694B596318630120D070FFF796
+:10329000B9FF002800D0FFDF10BDF1B582B00C20CF
+:1032A000019069480090C078012806D00098C07845
+:1032B000022802D00C2003B0F0BDFEF7A9FE0020CA
+:1032C000FEF776FC594C207F002837D05549204620
+:1032D0000F4682687437C368056946694A678B6719
+:1032E000CD67FE608069386100266677A677574D06
+:1032F000E87E002805D1287F002802D1687F0028B9
+:103300001AD000980078002816D02079032802D01F
+:10331000022805D008E005214D4800F06BFC03E0D1
+:1033200003214B4800F066FCA97E3846FEF7AEFC50
+:103330000020019026770CE0267703E00098C07803
+:10334000022804D00098C078022828D00AE0002083
+:1033500001900098C078012804D100990873009862
+:103360000221C170606B0178002903D00178001D33
+:10337000FEF7CBFC206B0178002906D0354A401CB3
+:10338000FEF70FFB0099012048700298A0623248B6
+:10339000FEF720FEFEF744FE019803B0F0BD009951
+:1033A0000120C8700C2003B0F0BD70B5FEF730FEF0
+:1033B000254CE078022803D0FEF732FE0C2070BDC9
+:1033C00001201A496073C8850220FEF71EFE2348BB
+:1033D000FEF7E5FC224E0025A0780321401C07F0F3
+:1033E00038F9A170885D012807D06D1CEDB2032D5E
+:1033F000F2D3FFF7ADFE002070BDC8B21949085CDA
+:10340000FEF7DFFC0020FEF7C2FBF2E770B5074CC9
+:103410000125A577E37F002B26D03A2070BD000060
+:10342000B0000020F40E0020340F0020740F0020A4
+:10343000FFFF0000140F00201D0F0020160F0020BA
+:103440003C0F0020AC0F0020940F0020540F0020F0
+:10345000D40F0020AF0F002088AE01008EAE010017
+:103460006F0F00208BAE01000026002802D1A07B48
+:10347000884209D1A17366771146FE4807F00BFB1D
+:103480006577FD4805702577A677002070BD024658
+:1034900000200123F949002A03D0012A03D0122079
+:1034A00070478B7400E088740B774A767047F34A54
+:1034B000032800D151611076012010770020704759
+:1034C000EE48017F002903D0407E002803D17047D9
+:1034D00040790028FBD00120704710B5FEF7DEFDD3
+:1034E000FEF7D1FDFEF701FDFEF785FDE24C6078A9
+:1034F000002805D0FEF7E6FDFEF774FA00206070A4
+:10350000012020730220E070FEF78AFD002010BD2C
+:10351000D9490871704710B500F04FFB10BDF0B5E8
+:10352000D74ED54D83B0002810D0D64805F0DEF830
+:10353000002804D1D34805F0F9F8002806D0CF4C74
+:10354000207903280DD1A07F00280AD0E87805282B
+:103550007ED201007944097949188F44929292FEF3
+:10356000FD00E878052874D20100794409794918EA
+:103570008F446F6F6F02F400C24804F0ECFFC04943
+:103580008870C1480290807F002803D1FEF704FCB8
+:10359000002800D0012000906878002810D028264C
+:1035A000761EF6B2FEF73FFA0746022802D1002E39
+:1035B000F6D1FFDF0098002812D1012F10D0009023
+:1035C000AF4FB248B9780526019007297ED208008E
+:1035D000784400790018874466F5057979792300E5
+:1035E0000120ECE76878002803D0FEF76BFDFEF7BA
+:1035F000F9F9A348FEF781FD002801D17F2038703A
+:10360000FEF769FD009800284AD02079012801D0F2
+:10361000022845D1FEF769FC9A48FFF75AFD83E07E
+:103620006878002803D0FEF74DFDFEF7DBF99448DB
+:10363000FEF763FD002801D17F203870FEF74BFDB7
+:10364000009800282CD02079022805D0012801E01C
+:1036500017E0F7E120D023E08A48FFF73AFD012088
+:1036600000F074FF00280AD08949864804F09BFFC7
+:103670008748FEF7DAFC607F002845D103E000F0C0
+:103680009CFA03B0F0BD01210846FEF746FDFEF7A7
+:10369000E6FCEE7003B0F0BD7A48FFF71AFD43E098
+:1036A000FEF723FC40E06878002803D0FEF70AFD0F
+:1036B000FEF798F97248FEF720FD002801D17F201F
+:1036C0003870FEF708FD0098002800E02AE178D065
+:1036D0002079022806D00128DED0032828D0FFDF79
+:1036E00003B0F0BD6748FFF7F4FC012000F02EFFA7
+:1036F0000028C4D06649634804F055FF6448FEF7CB
+:1037000094FC607F0028BED05C4902980A898282BE
+:103710004A89C282898901835D48019904F01FFFAB
+:1037200000206077A077AEE7FFF712FD03B0F0BD91
+:1037300054482168C2788B7E9A421FD10279CB7E91
+:103740009A421BD142790B7F9A4217D182794B7FE3
+:103750009A4213D1C27902E08DE176E1F5E08B7FE8
+:103760009A420BD1027ACB7F9A4207D100784A7EE7
+:103770004006C00F904201D1012000E00020627994
+:10378000012A20D000288BD0022000F0DFFE002884
+:10379000AFD0012000F045FF3D493A4804F003FF57
+:1037A0002068C18A3A4804F085FF2068017D3848C6
+:1037B00004F084FF3648FEF738FC607F002869D1AA
+:1037C0000DE012E017E00028DED12E481A3104F097
+:1037D000CBFE2C4804F0DCFE21684876D4E70120BB
+:1037E000E0770620E87003B0F0BDFEF77EFBFFF740
+:1037F000AFFC03B0F0BD6878002803D0FEF762FC90
+:10380000FEF7F0F81E48FEF778FC002801D17F2073
+:103810003870FEF760FC00980028E6D0FEF73FFA0B
+:103820000028E2D020790328164807D0FFF751FC82
+:10383000FEF75BFBFFF78CFC03B0F0BD2168C2789C
+:103840008B7E9A422DD10279CB7E9A4229D1427940
+:103850000B7F9A4225D182794B7F9A4221D1C2793E
+:103860008B7F9A421DD1027ACB7F9A4219D1007880
+:10387000400610E07C0F0020940F0020740F002001
+:10388000B0000020AC0F0020540F0020680F002073
+:10389000D40F00202AE04A7EC00F904201D10120BF
+:1038A00000E000206279012A30D0002800D1F7E63C
+:1038B000022000F04BFE002800D1E0E6012000F0DD
+:1038C000B0FEFA49FA4804F06EFE2068C18AF74853
+:1038D00004F0F0FE2068017DF44804F0EFFEF348A8
+:1038E000FEF7A3FB607F002800D178E7F14902983A
+:1038F0000A8982824A89C28289890183EB480199B7
+:1039000004F02DFE00206077A07768E70028CFD173
+:10391000E7481A3104F028FEE54804F039FE216832
+:103920004876C5E76878002803D0FEF7CBFBFEF7A2
+:1039300059F8E148FEF7E1FB002801D17F203870FB
+:10394000FEF7C9FBFEF7D1FAEEE6D94804F003FE14
+:10395000B070D748D549C2784B7A9A421CD10279C7
+:103960008B7A9A4218D14279CB7A9A4214D18279D1
+:103970000B7B9A4210D1C2794B7B9A420CD1027ACE
+:103980008B7B9A4208D1007809784006C00FC9099C
+:10399000884201D1012400E00024FEF7A6FAB078A5
+:1039A00004283DD1002C3BD0C348FEF7A6FB0028DD
+:1039B00001D17F203070FEF78EFB287B002802D0DB
+:1039C0000020FFF7F2FB01272F73BC4CB84D607A43
+:1039D0000028B9D10420E072284604F0D9FD00285F
+:1039E00002D0012804D102E00020207300E02773F8
+:1039F000B349284604F0B8FDB249284604F028FE31
+:103A0000E0741F2801D91F20E0743078AE4D7F2864
+:103A100000D1FFDF307828707F203070677283E636
+:103A2000A548FEF76AFB002801D17F203070FEF721
+:103A300052FB287B002802D10120FFF7B6FB0020B3
+:103A4000287371E6FFDF03B0F0BD6878002803D06B
+:103A5000FEF738FBFDF7C6FF9748FEF74EFB002840
+:103A600001D17F203070FEF736FBFEF73EFAFFF7FC
+:103A70006FFB03B0F0BD9048FEF73FFB002801D17B
+:103A80007F203070FEF727FB287B002802D1012021
+:103A9000FFF78BFB00202873FEF727FAFFF758FB90
+:103AA00003B0F0BD70B5894DE87807285CD20100FD
+:103AB0007944097949188F445757575757030B00D2
+:103AC0007B48FEF7B2FAFEF70FFB0420E87070BDEA
+:103AD000FEF7E4FAFEF7D7FAFEF707FAFEF78BFADD
+:103AE00001262E730220E870FEF79AFA784C2078AF
+:103AF000002800D0FFDF0020A0706E480068018819
+:103B0000A180417EE171428B2281828B6281C18BD7
+:103B1000A1814188E18281882183C08860832879DE
+:103B200020776C486C49807EA0736C4806F0B3FF28
+:103B30006878002803D0FDF776FF012808D0607F61
+:103B40004008400060772670022000F06AFD70BDDA
+:103B5000607F30436077FDF77FFF617F4000C907DA
+:103B6000C90F01436177EEE7FFDF70BD10B5574C19
+:103B7000E07805281DD201007944097949188F445D
+:103B80001818181902004C48FEF7B7FA002802D19D
+:103B900049497F200870FEF79EFA207B002802D159
+:103BA0000120FFF702FB00202073FEF79EF9FFF7CC
+:103BB000CFFA10BD00F001F810BD10B5FEF76EFA97
+:103BC000FEF761FAFEF791F9FEF715FA3F4C6078BF
+:103BD000002805D0FEF776FAFDF704FF002060709C
+:103BE000012020730220E070FEF71AFA002000F096
+:103BF00018FD10BD70B5364C054626466036743447
+:103C0000032943D0052940D104F07EFC0521284634
+:103C100004F07FFCB17E284604F0B2FC2146284621
+:103C200004F09DFC0C34216828460D3104F026FD7B
+:103C300021682846113104F02AFD2068017D2846BC
+:103C400004F03CFD2068C18A284604F033FD20685A
+:103C50004188284604F022FD20688188284604F027
+:103C600021FD2068C188284604F020FD21682846EF
+:103C7000083104F036FD2068017E284604F020FD5E
+:103C800012480179284604F024FD70BD04F03CFC84
+:103C90000321284604F03DFCB17E284604F070FC68
+:103CA0002146284604F05BFC70BD0000D40F0020C4
+:103CB000AC0F0020740F0020B0000020340F002053
+:103CC000410F0020480F0020670F0020940F0020B4
+:103CD000F40E0020540F0020680F0020030F002076
+:103CE000F0B5054685B00F46012000F033FDC4B2A3
+:103CF0000B2000F02FFDC0B2844200D0FFDF012076
+:103D000000F028FDC4B2182000F024FDC0B28442A7
+:103D100000D0FFDF3846F84F6C1E6900CD19002631
+:103D2000403D09287ED201007944097949188F4421
+:103D3000042C343430B2B2B267000B2C00DBFFDF4E
+:103D4000E88F0621F9F744FF070000D1FFDF0B2CB5
+:103D500000DBFFDFE88F3988884200D0FFDF982042
+:103D6000C05D002800D1FFDFE448F12146604670C5
+:103D7000C6607A6A89008A4201D9561A91368660ED
+:103D8000384602F0A2FB05B0F0BD02F0F0FB05B032
+:103D9000F0BDFEF75DFA05B0F0BD0420C04300F0B1
+:103DA000D9FCC6B2192000F0D5FCC0B2864200D0C2
+:103DB000FFDF0B2C00DBFFDFE88F0621F9F708FFA0
+:103DC000060000D1FFDF0B2C00DBFFDFE88F31881E
+:103DD000884200D0FFDF304602F079FC002800D096
+:103DE000FFDF00223146684600F0CDFCA220805D56
+:103DF0006946FCF797F9308E401C308605B0F0BD5F
+:103E00000B2C00DBFFDFE88F0621F9F7E1FE07004E
+:103E100000D1FFDF0B2C00DBFFDFE88F3988884201
+:103E200002D000E037E0FFDF3C468034207E0428EB
+:103E300000D0FFDF00202076A037BD78B04E681E8E
+:103E40000B2800DBFFDFAC48690008184038C68744
+:103E5000B878FBF739FD0020B870A16A002909D0B5
+:103E6000236BE26AD2188B69D2188A61A26A616AEE
+:103E7000D16002E0A149626A0A61616A002902D048
+:103E8000A06A086101E0A16A88619E480078F5F7A0
+:103E90007EFB05B0F0BDFFDF05B0F0BDF8B507460D
+:103EA00099480025C28B521C92B2C2830078002828
+:103EB00016D0954B04285C6814D0052848D0FFDF45
+:103EC000914C29462069FBF77DFF00212061397064
+:103ED00001213971B860A068FF303130F860F8BD59
+:103EE000FFDFEDE788480A2A01D3022200E003221F
+:103EF0007A7100296FD0056980480069002825D0B3
+:103F00000646C0680028FBD1002E1FD0307800285C
+:103F100000D1FFDF7169706841182846FCF71CFE6C
+:103F2000050009D5601B6E422146401E06F09FFB2E
+:103F300060432146851B05E0214606F098FB60435F
+:103F400021462D1A8D42BBD9FFDFB9E70025B7E71F
+:103F50000220787100294FD06B488669002E00D16D
+:103F6000FFDF664BAC2000251C698259691E28467C
+:103F7000002C0CD0A069904203D3884201D20146A4
+:103F800025462046E468002CF4D1002D00D10546DA
+:103F900098363561002D1FD0E868EE60F06000288B
+:103FA00000D0066100203469B061002C0DD0A169F9
+:103FB000002908D070690090814200D2FFDFA1691A
+:103FC0000098081AB0610020A061002D0FD0287859
+:103FD000002806D104E00FE00020F0601E61E1E758
+:103FE000FFDF6969686841184748016202E0464995
+:103FF00000200862454D63E7254661E7F0B50746B6
+:1040000085B00E46012000F0A5FBC4B20B2000F0E5
+:10401000A1FBC0B2844200D0FFDF012000F09AFB78
+:10402000C4B2182000F096FBC0B2844200D0FFDF7B
+:1040300000250120344C092E5BD2310079440979E6
+:1040400049188F4404162F2F2B56561446006073C0
+:104050002073607800280AD128484560C560257320
+:10406000A068C338FFF719F9002800D0FFDF05B0BA
+:10407000F0BD6178002909D0207B002801D1FFF72D
+:104080002CFA6573FBF76DFB05B0F0BDA073FFF76D
+:104090008CF90028F8D0FFDF05B0F0BDFEF7D8F8A6
+:1040A00005B0F0BD0420C04300F054FBC4B2192099
+:1040B00000F050FBC0B2844200D0FFDF012200219B
+:1040C0006846FFF7EBFE69463846FCF72BF805B06B
+:1040D000F0BD2078052800D0FFDF207F002800D128
+:1040E000FFDF25772570207DFBF7EEFB257505B0FA
+:1040F000F0BDFFDF05B0F0BD34100020FC0F002044
+:10410000FFFF0000B800002010100020B80B0000D6
+:10411000F0B5FF4C87B020780026042805D0207821
+:10412000052802D00C2007B0F0BD01276770607B26
+:104130000025002813D072B6607B002808D0A07B31
+:10414000002805D0FFF7C9F96573A573FBF709FBD4
+:1041500062B6207DFCF7A1FD002813D018E0207D79
+:1041600000900320694608734873FBF7C1FB049075
+:104170000020C043694605900F7202A90098FBF722
+:10418000D1FFE6E720BF207DFCF787FD0028F9D0AE
+:10419000207F002805D025772078052800D0FFDF74
+:1041A0000C2665702570207DFBF78EFB257530464B
+:1041B00007B0F0BDF0B5D64883B00078002801D034
+:1041C000FFF7A6FFD3480121017069460620F9F7E1
+:1041D0008BFC002800D0FFDF0027CF4E0AE00298BA
+:1041E000002807D09821095C002903D00088B0423C
+:1041F00006D140E06846F9F753FC0028EFD03AE0DA
+:104200000621F9F7E5FC040000D1FFDF2546A035C3
+:10421000A878FCF742FD002805D120BFA878FCF75C
+:104220003CFD0028F9D080342776AC78601E0B283E
+:1042300000DBFFDFB949620051184039CE87A8780A
+:10424000FBF742FBAF7069460620F9F74DFC0028EA
+:104250000CD0FFDF0AE00298002807D09821095C03
+:10426000002903D00088B042CAD104E06846F9F7BB
+:1042700017FC0028EFD0A74807700761002003B0A3
+:10428000F0BD10B50078A64C002809D0012806D052
+:10429000FFDFA068A349884200D3FFDF10BDA2481A
+:1042A000A060F6E710B59E4C00232070984803707C
+:1042B0004370037703734373837383610375974973
+:1042C00095480880052248808880091D521EFAD131
+:1042D000180004D0002B04D09348A06002E0A36033
+:1042E00000E0FFDFA0688F49884200D3FFDFFFF7BF
+:1042F00061FF10BD70B5864C0E46217884B015461E
+:10430000002902D00C2004B070BD884A416A8A1886
+:1043100001468031CA62A061087E002800D0FFDF1C
+:104320008348464345438348ED1C30186660A560CA
+:10433000854200D82846A06076490020C860052143
+:10434000217060702077E0837B48FBF769FA207565
+:10435000002800D1FFDFFBF7CBFA2061002201210A
+:104360006846FFF79BFD207D6946FBF7DBFE0020DA
+:1043700004B070BD10B4884201D2012200E00022D6
+:104380001218D2B2814201D2012000E00020401870
+:10439000C1B28A4201D2084600E01046441A831A8C
+:1043A0001B19502451186343FF22493251435A18B4
+:1043B0009821414351189C225043081810BC98384A
+:1043C0007047CB229200914200D211464162704761
+:1043D0004F480078002801D00020704710B5062013
+:1043E000F9F794FB0121484010BD10B5484C84B04A
+:1043F0002278002A02D00C2004B010BD4C4A514350
+:104400005043C91C4B4AA16060608018814200D8AB
+:104410000846A0600020607004212170E0834648B7
+:10442000FBF7FEF92075002800D1FFDFFBF760FAEB
+:104430004249FBF7C7FC2061002201216846FFF7D3
+:104440002DFD207D6946FBF76DFE002004B010BDF8
+:1044500070B52F4CA1690160FFF75AFE00230028B8
+:1044600018D1A16980318A6A002A09D00E6BCD6A01
+:10447000AD199669AD1995618D6A4A6AEA6002E0E4
+:10448000244D4A6A2A614A6A896A002A01D0116168
+:1044900000E08B61A36170BD70B51D4C84B02078C5
+:1044A000052802D00C2004B070BDA069002800D1FE
+:1044B000FFDFA0698030007E002800D0FFDFA06908
+:1044C000A0308078002800D0FFDF1D48FBF7A8F956
+:1044D000A169A222505405460E88401E0B2800DB1D
+:1044E000FFDF0E49680040184038C687A069A03039
+:1044F0008078002800D1FFDF01226846A16900F022
+:1045000042F9A0696946A0308078FBF70BFE19E0FC
+:1045100010100020FC0F0020FFFF000034100020CE
+:10452000B80000206A180000C4090000EB04000075
+:1045300071020000B3FBFFFFFD3F0100B80B00005C
+:10454000E13C01000020A06104B070BD10B5CA4973
+:104550004C68983400280AD001280BD002280DD0CE
+:10456000FFDFC6488068A0420BD9012010BDFF3490
+:104570007934F6E7B12080002418F2E7FF34613483
+:10458000EFE7002010BDBC4882684168914202D22A
+:104590000078002801D0002070470120704730B516
+:1045A00002460423B64D803285B000290AD0012985
+:1045B00021D0022904D003291FD0FFDF05B030BD70
+:1045C000137611E00446AC4800780028F8D10122A7
+:1045D0002146684600F0D7F8A220005D6946FBF747
+:1045E000A1FD208E401C2086FBF7BBF82878F4F74D
+:1045F000CEFF05B030BD032010E04188A14B5943E8
+:10460000A14B1960D16B0B89C3828B7903754B89E0
+:1046100043808B898380C989C1800220107605B0D0
+:1046200030BDF0B50146964800250078934C85B022
+:10463000002908D0012916D002295BD003296FD0A8
+:10464000FFDF05B0F0BDE583F4F7A1FF6078002837
+:104650005FD1002211466846FFF720FC207D6946A5
+:10466000FBF760FD55E0844920694A68854B821854
+:10467000864809691018A269558898325D439142AD
+:1046800018D0216AFCF768FA060009D5A81B774202
+:104690002946401E05F0EBFF68432946C61B05E08E
+:1046A000294605F0E4FF68432946361A8E4202D9AE
+:1046B000FFDF00E0002672488068864205D2A169CB
+:1046C000704A48884243961904E06E49304605F026
+:1046D000C0FFA169C882A06905210175C08A694926
+:1046E00048436549301AC86069498842A9D3FFDF49
+:1046F00005B0F0BDE583F4F74AFF01202077A069FB
+:1047000021698030C1610576FFF7C6FE002800D020
+:10471000FFDFFBF726F86573A57305B0F0BDFFE773
+:10472000F4F735FF05B0F0BD704700B5524A0029D7
+:104730000BD0012903D0022903D0FFDF00BD401EAA
+:1047400003E05178491C5170001F506000BD4B4878
+:10475000007870478107C90E00280BDA0007000FA8
+:10476000083880084B4A80008018C069C84000069D
+:10477000800F70478008484A800080180068C84051
+:104780000006800F7047F7B50F46064649883D483A
+:104790003C4A4143F88A82B0504300253C4680346D
+:1047A0000090227E002A09D03348012A40682ED08A
+:1047B000022A16D0032A2AD0FFDF3CE00498002802
+:1047C00000D1FFDF2C4D6868002800D1FFDF68684A
+:1047D000E968001D0918314A009880180D18012059
+:1047E00013E00499491E084300D1FFDF2648016801
+:1047F00000980D180498002806D01F4841682848E2
+:104800000818A84200D9FFDF0320207611E00D46EA
+:10481000049900290DD0002804D1174840780028B9
+:1048200000D0FFDF144841681D480818A84200D98D
+:10483000FFDF002D00D1FFDF2946E069FBF7C2FA58
+:10484000E0610020307001253571E069B0603846C4
+:1048500001F078FF002801D0757104E0207E012866
+:1048600007D003207071786AFF30CF30F06005B058
+:10487000F0BD0220F6E70000FC0F00201010002021
+:10488000B8000020E2040000BC0000204E0600003A
+:104890006A18000000ED00E000E400E055040000AC
+:1048A0005F040000FD48C07E7047FD4840687047C7
+:1048B000FC48C07E704710B4884201D2012200E05B
+:1048C00000221218D2B2814201D2012000E0002061
+:1048D0004018C1B28A4201D2084600E01046441A8C
+:1048E000831A1B19502451186343FF224932514344
+:1048F0005A189821414351189C225043081810BC63
+:104900009C3870476522D200914200D21146416224
+:104910007047FFB5E14E85B0706A3468056860681D
+:104920000190306A0390298E0798401A80B2029055
+:104930000898002804D0274638372046483002E03F
+:10494000371D2846A83000900320387105980028AC
+:1049500019D001287ED0022856D003287BD0FFDF53
+:104960000898002803D03879032800D0FFDFA16A17
+:104970007069FBF727FAB860216A606A81426BD9D7
+:104980000099086022E1306A002800D1FFDFE88A40
+:10499000C5494843421806980021002804D05043D6
+:1049A000C24905F056FE411CA16101916A88BE48CA
+:1049B000002142430698002804D05043BB4905F02B
+:1049C00048FE411CE161306AB74A801CA062E98A56
+:1049D000B54B5143019A891AB54A89180918A16241
+:1049E000287D019A584352001018FF301930206278
+:1049F0006062306A081AAF49801E8842B0D2AE4960
+:104A000088427DD2FFDF86E0E88AA74AE16850430A
+:104A10000A1806980021002804D05043A34905F045
+:104A200018FE411CA1616A889F48002142430698F4
+:104A3000002804D050439D4905F00BFE411CE16164
+:104A4000306A002800D1FFDFAE20405B964A002884
+:104A5000E88A02E02EE061E0B6E0E16821D0504350
+:104A60000818A169401AA0622169A0688E4A4843CB
+:104A7000A1694018297D400051434018FF3017308C
+:104A800020626888E1695043411A8C4808186062C6
+:104A9000A06A316A401A8A49FF38553888423AD3A9
+:104AA0005EE750430818A169401A3168D638496852
+:104AB0004018D8E7284680300190C08D002800D1EA
+:104AC000FFDF306A002800D1FFDF68887649E3699C
+:104AD0004843C01AA06201999C46CA8D2169A36807
+:104AE000521A4B43A169591863465343C9182A7D8A
+:104AF0006D4B49005A438918FF311731216200E09C
+:104B000009E06E4941186162316A401A6C49FF3808
+:104B100055388842C4D20120387121E7089800280E
+:104B200003D03420005D00287ED168885E49484368
+:104B3000E169401A02994843A062284680300490F7
+:104B4000C08D0028019822D0002800D0FFDF0498F3
+:104B5000554AC18D02980818E16948434000FF306A
+:104B60001730206268885043411A54480818606220
+:104B700054484068002816D0A26A03990120511AAF
+:104B80004F4AFF39553991428AD23871E8E60028F8
+:104B900002D00398002800D1FFDF0198A16AD6381F
+:104BA0000818A062D3E7FAF7A3FE7269014610461F
+:104BB000FBF7D2FFA16A081A4149FF3850388842F2
+:104BC000ABD2012009B0F0BD009801600098696A7D
+:104BD00000684018FF305030F8609820415B07981B
+:104BE000081A00B2002804DD0598022801D003202D
+:104BF00000E0002078710E98002813D0C035298875
+:104C000000291DD0688868802A79401C42438A4266
+:104C100008D27879401E002804DD01207871688868
+:104C2000401C6880089800E007E038700898002869
+:104C300008D03420005D002804D0022009B0F0BD67
+:104C40000020E0E708980121484020346075307F5B
+:104C5000F27E3946B37E9A4202D0FBF763FA04E053
+:104C60000020F076B07630607062002009B0F0BDB0
+:104C700070B5144D09292B686A686FD20C007C440A
+:104C800024792419A74404758D9F8AAAAA69A700CC
+:104C900000201062D17E042969D215E04C1000205A
+:104CA000DC00002074100020E204000040420F00ED
+:104CB00033040000750900003104000094FBFFFF7D
+:104CC0005C080000CC0000200B007B441B79DB1843
+:104CD0009F444D4D0145516A0C6811680870116878
+:104CE000486010682030407D002808D1FAF700FEA7
+:104CF00069680968096CFBF72FFF002818DC6868F1
+:104D0000228E0168498E914206D1214680318B8BDB
+:104D10009A1ACA83238605E0891A9E2211530168D4
+:104D2000498E21860268C1681164C168416111E041
+:104D300068680168098E228E8B1A22468032D383DE
+:104D40000168098E218601680B6CC3600B6C43619E
+:104D5000886C9062204602F0C8F970BD3EE0D068D1
+:104D60005061FDF7BEFD0028F7D0FFDF70BDFFDF0B
+:104D700070BDD07E04280FD201007944097949180A
+:104D80008F440A0A010402F082FA70BDFDF7DBFECF
+:104D90000028FAD0FFDF70BDFFDF70BDFDF758FAC5
+:104DA00070BDD87E022806D0D87E032800D0FFDF51
+:104DB00000F0A9FB70BDF948007D012800D1FFDF9C
+:104DC00000F0E7FB70BDD87E0228F9D0D87E03281A
+:104DD000EED0FFDFECE7FAF777FD70BDFFDF70BDC7
+:104DE000F3B581B00298EE4E0024EE4D09284BD267
+:104DF00001007944097949188F4404313E3E314617
+:104E0000463E3E007068E74F002800D0FFDF776025
+:104E100002990198FFF72CFFE87E02282AD17068DA
+:104E20000768406A0668FAF748FD7188DE4A514310
+:104E3000FA69891AAE39B72800D8B7206523DB0094
+:104E40001818081AD949F1224018716A9200914243
+:104E500000D98C1A844200D22046F86206E001464E
+:104E60000198FFF705FFE87E022803D12968012099
+:104E70002031087503B0F0BD014635600198FFF799
+:104E8000F7FE346003B0F0BDFFDF03B0F0BDF8B54E
+:104E9000C34C07460D46092920D208007844007902
+:104EA00000188744040F13130F1B1B1313006068B3
+:104EB000BF4E002800D0FFDF294638466660FFF766
+:104EC000D7FEF8BD3846FFF7D3FEF8BDB8482060DE
+:104ED0003846FFF7CDFE00202060F8BDFFDFF8BDAB
+:104EE000F0B5B04985B0CA7E0026AD4C032A03D088
+:104EF0002831CA7E032A67D100252160002821D0ED
+:104F000001280BD0FFDF2068002E05604562256078
+:104F10005AD0A8484560002005B0F0BD032088762F
+:104F200000E020BF2168C87E002803D0C87E8A7EAA
+:104F30009042F6D0C87E002802D000268D76E2E7A7
+:104F40000126FBE70026032708468F76C97E032942
+:104F500003D0C07E002833D033E00120FDF713FEDC
+:104F60002068007F002800D1FFDF2068067F6846A8
+:104F700007714771FAF7BCFC0290FF20F5300390EF
+:104F800001216846017069463046FBF7CBF820687E
+:104F9000007FFBF782FE002806D120BF2068007F3B
+:104FA000FBF77BFE0028F8D02068007FFAF78CFC26
+:104FB00020680577C576857605600126456200E0A4
+:104FC0000126206885769EE70C2005B0F0BD10B55F
+:104FD000744800F071FB764800F06EFB6F490020CA
+:104FE0000875744948706F494861714A5061887604
+:104FF00090766B494860086010BDF8B56E4E054666
+:105000003068002401270004810F6C480068800F7D
+:10501000814200D0FFDF3068694E0004810F3068A4
+:105020000006800F814200D0FFDF6648C06931680A
+:10503000800F0904890F884200D0FFDF62480570A5
+:10504000584DEC76AC765A4EF476B4765F480771DC
+:1050500004606C6274622C60564F346028467C6039
+:1050600000F02AFB304600F027FB4C4804757C70AA
+:105070006C617461AC76B476494844600460F8BDF4
+:10508000524908717047F8B546490546CA7E4848F6
+:10509000434C002A02D1C27E002A03D0C97E0229D5
+:1050A00007D009E04A482160FAF7BAFB216808777F
+:1050B0000AE0C17E002901D00C20F8BD20604548DF
+:1050C000FAF7AEFB216808773A48002D4560216861
+:1050D00008604148486212D028460121C430FCF7DC
+:1050E0000DF90620F8F722FD06460720F8F71EFD09
+:1050F0003118C035287905F0ACFA491C29712068AF
+:10510000007F002800D1FFDFFAF7D7FB3349884240
+:1051100000D208463249401886B221680320C8767A
+:10512000FDF707FB21680861FDF727FB0127002534
+:10513000002826D0FDF721FB21684A6A1060086824
+:10514000012107706846FCF762F868460078254937
+:10515000000205F07EFA0F46FAF7CAFBF119FAF7DA
+:1051600031FE2168C86022680320107250721571E8
+:10517000107FD37E111D967EB34235D0FAF7D2FF51
+:1051800036E0FAF7B5FB3146FAF71CFE2168C86035
+:105190000868057008684770E5E700009C1000206B
+:1051A000CC0000204C100020E2040000AFFBFFFF09
+:1051B00074100020DC00002000E400E008E400E0BF
+:1051C00018E400E000ED00E0C4000020D40000205E
+:1051D000E14D01008F4E0100C8000020F6050000DF
+:1051E000BB02000010270000D57695761560556249
+:1051F000206805830020FDF7C6FC00202560F8BD6F
+:105200007047F8B5FC4EF17E002903D1FB49C97EF9
+:10521000002901D00C20F8BD0221F176F94FF84D9C
+:1052200077623560002438602C7500943979C0307D
+:105230004A00F549007B8A5A4000085A2346101854
+:1052400081B222462046FFF764FB002800D0FFDF32
+:105250002C610120AC6028756C862C86EB48847527
+:105260003968088E401E088634830020F8BD10B5CA
+:10527000E74801244068817E03290CD00168497801
+:10528000002906D0006AE349884202D90024FDF7CC
+:1052900076FC204610BD0024FBE7DD48406802682C
+:1052A0001178491C1170016A0068C26A914204D8E1
+:1052B000007D012801D00120704700207047F8B51B
+:1052C000D34DCD482860416A00680C68002734211E
+:1052D0000F54A621095D002926D1007D032823D182
+:1052E000FAF706FB29684A6901461046FBF734FCC9
+:1052F000002819DD2E68C84A716A3568096849882E
+:105300005143EA69891A05F0A4F9218E401C41181D
+:10531000BF48298632689C21095B138EC91A09B2DD
+:10532000002903DC0760F8BD2F60F8BD01212032A1
+:10533000917521464031CA898989B34F511A228E0D
+:10534000491E89188EB20546C03416E0496A0979AB
+:105350004900795A00220092028E237B007D5B0077
+:10536000FB5A591889B20123FFF7D3FA00280BD052
+:1053700001280CD0022807D0FFDF29680868028EB8
+:10538000B21A12B2002AE1DA00202860F8BD2868BB
+:105390000068018E491C0186EFE770B59C4D002620
+:1053A0006C68062844D201007944097949188F4471
+:1053B0001820020E240D002000F0BBF9E676A67638
+:1053C000266066626868002811D06E6070BD9348E0
+:1053D0002C680078F4F7DBF8E676A676266066623D
+:1053E00070BD012000F0A5F968680028EDD1FFDF4D
+:1053F000EBE721680320087570BD606A21680068CA
+:10540000CA698A604188844A51432268D160014652
+:10541000C0310A8DC282E622125C02754A8D42803A
+:105420008A8D8280C98DC18021680220087570BD77
+:10543000FFDF70BD70B50024754D002805D0012830
+:105440000AD0022827D0FFDF70BD00F0CDF96868D0
+:10545000002829D06C6070BD686801684C70C47603
+:10546000847604606E4E44620021706802F098FEFB
+:1054700071680846E0318C70CC70FFF7C2FE0028DE
+:1054800000D0FFDFFAF76DF964486C600078F4F73C
+:105490007EF86C6070BD00F0A7F96868C476847609
+:1054A000046044620028D5D1FFDFD3E7584949683A
+:1054B000CA7E022A09D10A681378002B05D15060F0
+:1054C0000968CA6A10182838C862704700B5504A7F
+:1054D0000029526808D0012903D0022903D0FFDF38
+:1054E00000BD801E00E0401F106200BD4348C07E2A
+:1054F000002801D00020704710B50720F8F706FB00
+:105500000121484010BD38B5414C206801684978F8
+:1055100001291FD001216846FBF779FE6846007813
+:105520004049000205F095F82068426AC068126898
+:105530005118FAF747FC2168C860304822680321F7
+:10554000824202D0108B0A2810D2108B401C10838C
+:1055500051720DE07D21C068C900FAF733FC216863
+:10556000C860FDF7E6F821680861E6E7022050729E
+:10557000117200231371107FD47E111D957EAC42F1
+:1055800002D0FAF7CFFD38BDD3769376136053621D
+:1055900038BDF0B51E4F83B038680568416A2E46A5
+:1055A0000C682036717D002907D0698E228E9142C9
+:1055B00003D1407A002800D1FFDFFAF799F9144FA0
+:1055C00039684A6901461046FBF7C6FA3F68002869
+:1055D000796A096807D049880F4A51433A68D26905
+:1055E000891A05F036F8228E698E131899421BDB52
+:1055F000491C69861BE000004C100020741000203C
+:105600009C100020D400002092AE0100BC100020AD
+:10561000CC000020D9821300E2040000C400002066
+:10562000DC00002010270000401C10186886B07DA8
+:10563000002806D19C21688E095B884201D1401C5C
+:105640006886388B2646401C3883204640300190BF
+:10565000C2898089101A228E401E801887B2C036F7
+:1056600016E07E4800230068406A007941007C48CB
+:10567000415A0093337B5B00C05A401881B2287DA9
+:105680000023FFF746F9002810D0012810D0FFDFD3
+:105690006A8EB81A00B20028E3DA019808218172F4
+:1056A000019801214172204601F0E6F903B0F0BDF6
+:1056B000688E401C6886EBE7F8B5684C05461F27E6
+:1056C000EE7E042E2AD230007844007900188744F8
+:1056D0002B2501206348854200D0FFDF0220256092
+:1056E000A87600E020BF2168C87E002803D0C87ECD
+:1056F0008A7E9042F6D0CA7E002A04D000228A76A2
+:105700000C2722600DE000228A760A604A6222603D
+:105710000AE00120FFF7E4FB074600E0FFDF002F6F
+:1057200002D0E87EB042CBD1E87E002800D0FFDF77
+:10573000F8BDF8B5494D01286A68516A0C6843D133
+:105740000879474940000B5A1068077D0126032F4E
+:1057500006D0027D022A13D0007D012824D033E038
+:1057600000270761106887609C200096025BCC20B0
+:10577000005D4000085AC01881B23B4603201EE07D
+:1057800022468032D78D07610096CC20005D928B37
+:105790004000085AC01881B200230220FFF7B9F870
+:1057A000696809680E750CE09C200096025BCC20AD
+:1057B000005D4000085AC01881B200230120FFF7A5
+:1057C000A8F8002800D0FFDFF9F7CBFF26480078C3
+:1057D000F3F7DDFE6968002008830B68228E5A8685
+:1057E000096820318875F8BDF8B51C4D002168683E
+:1057F0000C4600684278002A01D0447027E0007807
+:10580000002809D001216846FBF726FD684600788C
+:105810001649000204F01DFF6868426AC0681268F9
+:105820005118FAF7CFFA6A68D060147103205072E9
+:10583000107FD37E111D967EB34202D0FAF772FC20
+:1058400003E0D47694761460546268680483F9F7B0
+:1058500088FF05480078F3F79AFEF8BDCC000020D9
+:1058600092AE01004C100020C40000201027000060
+:1058700010B584B004466846FCF775FE002800D1D8
+:10588000FFDF009802F0A2FF0321009802F0BBFFA7
+:105890000098EF22017811400170214603F019F8B9
+:1058A0000D2C7CD2200078440079001887442D1FED
+:1058B0000657A2A2A31390A2A3A37800F848806879
+:1058C000A030417D009803F0A3F8FCF75FFE0028AC
+:1058D0007AD004B010BDF24880688030417C0098D6
+:1058E00003F007F9FCF752FE002870D09EE0EC4868
+:1058F00080688030016C0098491C03F074F8FCF754
+:1059000045FE002860D004B010BDE54CA068803092
+:10591000C06B8179009803F02BF8A0688030C06BD1
+:105920000189009803F01BF8A0688030C06B4189A2
+:10593000009802F0F9FFA0688030C06B8189009860
+:1059400002F0FBFFA0688030C06BC189009802F0B4
+:10595000FDFFFCF71BFE002836D004B010BDD04C74
+:10596000A0688030C16B0098091D03F055F8A0684D
+:105970008030C16B00980C3103F05AF8A068803079
+:10598000C16B00981E3103F05DF8A1680098883162
+:1059900003F065F8FCF7FAFD002844D03AE029E06E
+:1059A000BF4C60690178009803F089F860698188CC
+:1059B000009803F086F860694188009803F085F844
+:1059C000FCF7E4FD0028C8D1FFDF04B010BD2CE0D7
+:1059D0000020029069460390087A01210843694635
+:1059E000087202A9009803F086F8FCF7CFFD0028A2
+:1059F00019D00FE0FFDFFCF7C9FD002800D1FFDF61
+:105A00000C2CE2D0072C11D0012CDED0002CDCD0E5
+:105A1000022CDAD0A2480021806840304182012166
+:105A2000817504B010BDFFDFF4E7FFDF9C48002163
+:105A300080684030018304B010BDF0B5984C8DB043
+:105A40002079C0077ED020693B21C578A06800235B
+:105A50000A5C0521303002F00EFD00280FD0022D27
+:105A60000DD00B2D0BD0042D09D0052D07D0062D00
+:105A700005D00D2D03D06078082108436070607850
+:105A800000285FD12069C078801E0C287ED20100DA
+:105A90007944097949188F4405792743C47A79F400
+:105AA000791DF38BA0683D210A5C00230121303071
+:105AB00002F0E1FC00286AD1206902F0ABFFA16886
+:105AC000B622505402223D204254002040318876B4
+:105AD0008875C3E1A0682030C17E0A2973D10021F6
+:105AE000C1770D21C176B9E1A0683B21095C0E297F
+:105AF00069D1BC21095800884988814200D0FFDF64
+:105B0000A0688030C16B2069263102F0BFFFA16818
+:105B100020698C3102F0CAFFA0681121203045E0D5
+:105B2000A1683B20405C11284DD180318C46CB6B65
+:105B30005C4810260022082168440E33B51AED187F
+:105B4000203D00E092E1EF7F4770AD7F8570801CC3
+:105B5000491E921C0029F1D16146CB6B03A8102687
+:105B60000022082103301E33B51AED18203DEF7FC7
+:105B70004770AD7F8570801C491E921C0029F3D1AF
+:105B8000684603F068FCA068014601E047E1F2E0E6
+:105B900008AF6CCFC36778318267CE608D6000211B
+:105BA0008166C16601212030C1771321C17655E19C
+:105BB000A0683B21095C112901D00E2903D1403096
+:105BC000007F002802D00220607047E1206902F0C7
+:105BD0008EFFA16800250A468032107408464030C6
+:105BE000C5768575D06B09884088884200D0FFDF74
+:105BF000A06801468030C26B1570026D1378002BCF
+:105C000001D0FFDF07E10B88D380036D027C1A719E
+:105C1000026D1572036D0B221A70006D09884180A8
+:105C2000F9E0A0683B21095C152901D0022005E1BB
+:105C3000014600254031CD768D75BC21095800887C
+:105C40004988814200D0FFDFA06801468030C26BE6
+:105C50001570036D1A78002A01D0FFDFDBE00A46D9
+:105C60004032167F002E0DD015770A88DA80026D3B
+:105C70001571036D0C221A70006D09884180CAE00D
+:105C800012E079E00A88DA80026D1571036D012255
+:105C90001A72036D0B221A70006D09884180BAE0F8
+:105CA000E4000020FFFFFFFFA0683C210A5C002306
+:105CB0001946303002F0DFFB002809D1A0683B21F3
+:105CC0000A5C00230721303002F0D5FB002870D099
+:105CD000607800284FD1A0684030807F800715D4BD
+:105CE000206902F0F6FEA1684031C877206902F011
+:105CF000F2FEA16840310884206902F0F1FEA1683B
+:105D0000022240314884887F10438877A0685E2152
+:105D1000095CC90714D13C210A5C002319463030C4
+:105D200002F0A9FB002800D1FFDFA06801213C227E
+:105D300011540423B822135440308176002101838A
+:105D4000A068014620310A46C97E012903D10021FD
+:105D5000D17656231954BC21095805884B88AB428B
+:105D60007CD10B78042B79D100230B70D17E0029D4
+:105D700074D14030837571E0A0683B210A5C002338
+:105D80000621303002F077FB002856D060780028DA
+:105D900064D16946206902F0BFFE68460078C107F9
+:105DA000C90F6846017005D0A068012160300171FB
+:105DB00004E042E0A068002160300171A068002585
+:105DC00056210D54BC21095800884988814200D0D1
+:105DD000FFDFA1680A468031C86B0570086D037843
+:105DE000002B01D0FFDF16E01388C380086D6B46DF
+:105DF0000571086D1B8803816B465B8843816B4688
+:105E00009B8883816B46DB88C3810B6D06201870ED
+:105E1000096D10884880A0682030C5761EE0A06813
+:105E20003C210A5C00231946303002F024FB002894
+:105E300003D06078002811D102E0012060700DE0ED
+:105E4000206902F06FFDA1689122505405223C2088
+:105E5000425400204031088301208876A268002344
+:105E6000106F516F401C5941516710670DB0F0BD64
+:105E7000F8B5FF4C0746607800250843607020465F
+:105E80008068A288014693064031002B01DA8D819B
+:105E900002E08B895B1C8B815106890F012600294A
+:105EA00008D0014620318A7F002A03D18E77012154
+:105EB000FEF775FB002F75D16078002873D120792B
+:105EC00040070CD5A0682030C07E052800D1FFDF38
+:105ED000A0682030417F022901D1267045772079C2
+:105EE00080074ED5607800284BD1E068C0780D2837
+:105EF0007BD201007944097949188F4443330677EE
+:105F0000CACA8F1823CA55689B00A0683D210A5C45
+:105F100000230121303002F0AEFA002831D1A2680E
+:105F200003213D208154403295759576B2E0A068FA
+:105F30003C210A5C00231946303002F09CFA00280C
+:105F400077D1A7E0A0683B210A5C002319463030D6
+:105F500002F091FA002800D1FFDFA168092020316A
+:105F6000C87697E0A0683B210A5C002319463030D0
+:105F700002F081FA002800D1FFDFA168072020315C
+:105F8000C87687E0A0683B210A5C002319463030C0
+:105F900002F071FA002800D1FFDFA168082020314B
+:105FA000C87677E0E8E0A2E0A0683B210A5C002325
+:105FB0001946303002F05FFA002800D1FFDFA068F8
+:105FC0000A2201464030C6762031CA7662E0A068D7
+:105FD0002030C07E0D2800D0FFDFA0680C220146D3
+:105FE000403006772031CA7654E052E0A0683B2169
+:105FF0000A5C00231946303002F03DFA002805D132
+:10600000A0684030007F002800D1FFDFA0680E228A
+:1060100001464030C6762031CA763BE0A068203089
+:10602000C07E132800D0FFDFA16815202031C8767C
+:1060300030E02AE0A068BC21095803884A889A42C7
+:1060400019D10978042916D13B210A5C002319468D
+:10605000303002F010FA002800D1FFDFA0680146BE
+:1060600040318A7F920702D42030C67603E08D75D6
+:106070008030C06B0570A0683C210A5C0023194683
+:10608000303002F0F8F9002804D0A068403085765E
+:1060900000E0FFDF207900070AD56078002807D1EB
+:1060A000A0682030417F032902D102212170457769
+:1060B000FFF7C3FCA078000716D5A0683B210A5C57
+:1060C00000230521303002F0D6F900280AD008203C
+:1060D0006070A0688030016D08780B2800D1002026
+:1060E000087001E001F0DAFDA06800F03BFB6846B3
+:1060F000FCF739FA00283FD0607800283CD1A0682E
+:106100003D210A5C00230121303002F0B4F900285F
+:1061100032D1A068B421095C002901D0022029E015
+:106120003B210A5C0C2A0DD00D2A09D0132A20D05D
+:1061300000230421303002F09EF900281DD0D9E060
+:106140000B2017E0FBF787F80C2815D3A06808216F
+:106150008030C06B1E30FBF77FF8002806D0A068A7
+:1061600004218830FBF778F8002800D1FFDF0320F6
+:1061700000E00620FFF77CFBBCE0A0680146203170
+:106180000A7F012A26D0052A1DD0BC221258137876
+:10619000002B60D0528803889A425CD1CA7E0023CB
+:1061A0001946303002F067F9002854D0A068BC21AD
+:1061B0000958097802291AD003291AD004293CD099
+:1061C000052948D164E00720FFF752FBA068203082
+:1061D00005778FE00C20FFF74BFBA06801464030AD
+:1061E0000583827F3243827720310D7782E0002061
+:1061F00009E03F21095C002908D0403000780028E0
+:1062000000D1FFDF0A20FFF733FB24E0FBF723F880
+:106210000C2820D3A06808218030C06B1E30FBF70B
+:106220001BF8002806D0A06804218830FBF714F87A
+:10623000002800D1FFDF0320E5E74030807F8007A2
+:1062400009D10C20FFF714FBA06840304582867509
+:10625000817F314381776846FCF785F9002849D072
+:10626000A0683B210A5C00231946303002E00000A0
+:10627000E400002002F0FFF800283BD0A168C42011
+:10628000405C002836D0A0690078002802D031E0B8
+:106290000820B8E7088E0A282CD905220831E069C1
+:1062A00004F030F9002822D0A0688030016C087812
+:1062B00000280CD00522491CE06904F023F90028CD
+:1062C00018D1A0688030006C0078002806D1A06842
+:1062D000E1698030006C401C04F0D2FBA068803083
+:1062E000006C0178491C01700120FFF7C1FAA06819
+:1062F000C0300571FE4880680446A030007D30340F
+:10630000002807D1627B00230121204602F0B3F868
+:10631000002802D0208C401C20843D22002F01D078
+:10632000A27615E0F248017802290BD001290BD0A2
+:106330004178002917D0142001420BD01E20A076EE
+:10634000667648E0162002E08068A030807DA07666
+:10635000667640E00807E3D4880700D1FFDF2A20F3
+:10636000A076667637E0214620318A79002A05D06A
+:10637000628C531C6384A38C9A4214D2897A0029BC
+:1063800005D0218D4A1C2285A28C91420BD2228CF1
+:10639000E18B8A4204D38368A0331B7D002B02D19A
+:1063A000A38C9A4203D32220A076667613E0A27BC8
+:1063B000002A06D0A28B8A420AD30820A0766676ED
+:1063C00009E0A18B062903D33E20A076667602E081
+:1063D000617E002908D0E5722573C548A5730221A6
+:1063E0008068FEF7DCF8F8BD00218068FEF7D7F87A
+:1063F000F8BD10B5BE494A788B781A430ED10128F2
+:1064000009D00879400704D588682030407F0228E9
+:1064100004D0012010BDFEF7B6F810BD002010BD5D
+:1064200070B5B34C0546A0880E462843A080A80747
+:1064300003D5E80700D0FFDFE660E80700D026615B
+:10644000A8071BD5304602F06DFA062802D00B28AB
+:1064500014D10BE0A0683B21095C13290ED1002167
+:106460000167416701214030017007E0A0683B21CE
+:10647000095C0D2902D1002140300170280601D5A8
+:106480000820A070680517D5A068018E80880818BC
+:10649000801D85B2304602F045FA01280DD0304605
+:1064A00002F040FA002807D1A06829468030C06B6E
+:1064B0008580304602F060FA70BDA0682946C03081
+:1064C000C580304602F09BFA70BDF8B5884C0026B6
+:1064D000A060A68066700546A67026702F460088CC
+:1064E000FCF73EF8A0680088FCF75EF88035288C41
+:1064F000A168401C82B20846303001F0F8FE002846
+:1065000000D0FFDF2E84A06801464030827D002A43
+:1065100003D0428A838A9A4225D2827E002A03D0FF
+:10652000028B838A9A421ED2038AC28993421AD26C
+:106530002031897F8089002916D0904213D26D487E
+:1065400000906D4B6D4A3946304601F00CFAA06858
+:106550003B210A5C00230521303001F08CFF00282C
+:1065600001D001F0FCF9F8BD0628E8D3F8BD10B55C
+:106570005F48816808464030827D002A03D0428A05
+:10658000838A9A4216D2827E002A03D0028B838AA3
+:106590009A420FD2038AC28993420BD22031897F5B
+:1065A0008089002904D0904204D201F02AFB10BD5A
+:1065B0000628FAD300200146FFF75AFC10BDFFB5AC
+:1065C0000C4681B007461546D82120460A9E04F0A5
+:1065D00025F827808034E56304982665206405B09B
+:1065E000F0BD10B5F7F70DFC10BDF8B50C46174619
+:1065F0000621F7F7EDFA010062D00D468035286DCF
+:1066000000260278072A1CD0A01C0C2A27D00B2AAF
+:1066100032D0062A3FD00846C030027A002A4FD036
+:10662000667012222270027A002A08D0C2310672E5
+:106630000A8962804A89A280027A002AF7D1012061
+:10664000F8BD002FFBD1667007202070296D0A224B
+:10665000A01C091D03F083FF286D0670EFE7002FD3
+:10666000EDD166700C202070286D81886180C08813
+:10667000A080286D0670E2E7002FE0D166700B2144
+:106680002170296D8A880280CA88428009898180A8
+:10669000286D0670D3E7002FD1D1667006212170D6
+:1066A000296D8A880280CA8842800A8982804A8944
+:1066B000C2808A890281CA894281286D0670BEE73C
+:1066C0000020F8BD0020704709494861704770B547
+:1066D000044601468031088C2546401C088440351C
+:1066E000A889401CA881A87D00280BD0688A07E0F3
+:1066F000E4000020715E0100F363010021640100E9
+:10670000401C6882A87E002802D0288B401C288369
+:10671000B420005D002809D13D20025D2046002301
+:106720000121303001F0A7FE002802D0288A401C49
+:106730002882204600F016F8002070BD384AD1614A
+:10674000906170473E210A5C40308189091D002A12
+:1067500004D0C089814203D3012070470629FBD2AF
+:1067600000207047F8B5054606462036F07E2C46D8
+:106770000027803407281CD1288EC621495B401C85
+:1067800088424CD1216C28460830491C04F078F925
+:106790000221284601F05EFDF77601216620415571
+:1067A000206C0078002800D1FFDF216C0878401EA3
+:1067B0000870F07E082832D1E16B288E8988401C51
+:1067C00088422CD1206D0178002901D0FFDF15E02F
+:1067D0002988C180E06B216D40890881E06B216DC3
+:1067E00080894881E06B216DC0898881206D0771A7
+:1067F000216D07200870216D2888488001212846D6
+:1068000001F028FD03212846FDF7C9FEE06B298829
+:106810004088884200D0FFDFE06B0770F776F8BD54
+:10682000E400002030B585B004466846FBF79BFEC7
+:10683000002800D1FFDF009801F0C8FF0321009875
+:1068400001F0E1FF0098EF2201781140017021462C
+:1068500002F03FF8A01E0C2853D2010079440979B8
+:1068600049188F44054E1E4F4F164E404E4F2F2A4B
+:10687000FE486521C068095C002904D00621009803
+:1068800002F0C6F83EE0C030C17B009802F0C0F8CC
+:1068900038E0F648C0688030417C009802F029F961
+:1068A00030E0F24D0098E968B83102F0EAF8E968A2
+:1068B00000988C3102F0F1F824E00621009802F0F3
+:1068C00014F91FE0E94DA8680178009802F0F7F884
+:1068D000A8688188009802F0F4F8A86841880098B8
+:1068E00002F0F3F80EE00020029069460390087A67
+:1068F000012108436946087202A9009802F007F9CD
+:1069000000E0FFDFFBF742FE002800D1FFDF0C2C88
+:106910000AD0072C0AD0022C06D0D4480021C06827
+:10692000403001830121817605B030BDCF48002180
+:10693000C0684030018305B030BD70B50C460546D7
+:10694000FF212131204603F069FE002021462580E9
+:10695000E03108740877FF3401342071A07470BDF1
+:1069600010B5F7F74EFA10BDF8B50D4617460721DA
+:10697000F7F72EF9040078D02646E036307C002167
+:10698000002817D0002F6DD1697007202870307C47
+:106990000F4600280CD02046F23000902784377430
+:1069A0000A22A81C009903F0DAFD307C0028F5D1FA
+:1069B000AF7057E0307F00281DD0002F52D1307FBC
+:1069C0000B280BD00C2801D0FFDF4BE069700C20A6
+:1069D0002870B07FA8702088A8800AE069700B201A
+:1069E0002870B07FA8702088FF34A8800134A07878
+:1069F000A871317736E0E01DF9300279002A12D013
+:106A0000002F2FD1697008222A7022886A8002899B
+:106A1000AA804289EA8082892A81C2896A81028A9F
+:106A2000AA8101711EE0827C002A08D0002F19D1B2
+:106A3000697011222A70828A6A80817412E0827DD4
+:106A4000002A12D0002F0DD1697012222A70827D87
+:106A5000002A07D08175028B6A80428BAA80827DD2
+:106A6000002AF7D10120F8BDFFE70020F8BD002083
+:106A700070477E4988607047014610B5002220317A
+:106A8000CA760A778A77A0308079002802D0002160
+:106A9000022001E000210320FEF77FFC10BDF3B5CA
+:106AA000724C8FB0E0680D460088F7F702FA0C9040
+:106AB000002800D1FFDF607828436070A28890062C
+:106AC00006D5E06800214C231952A030017304E080
+:106AD000E06840308189491C81815006800F022581
+:106AE000002813D0E0682030817F002902D00329DC
+:106AF0000CD106E00121817700210120FEF74DFC39
+:106B000004E0857700210120FEF747FC5748C06864
+:106B1000014620318A7F012A04D1544A9288D20545
+:106B200000D58D770F9900297ED150498988890534
+:106B300002D50021C03002E0C0300188491C01802C
+:106B400000F0A9FB0DA8FBF70EFD002856D0474C1E
+:106B50006078002852D1E0683D210A5C0123194683
+:106B6000303001F088FC002848D1E0680146C0318F
+:106B70008A7B002A08D000215022115260304171D6
+:106B80000220FFF74FFECCE03C22125C0B2A17D00C
+:106B900006DC012A6ED0052A10D0092A06D18FE022
+:106BA0000F2A11D0102A24D0162A6ED001230421D6
+:106BB000303001F060FC002868D0B2E0072000E02F
+:106BC0000B20FFF72FFEACE0FAF745FB0C2815D39E
+:106BD000E0680821B830FAF73FFB002806D0E068EB
+:106BE00004218C30FAF738FB002800D1FFDF0420A5
+:106BF000E7E7497C012902D0022948D091E0FC2135
+:106C0000095C002940D105461949D23510260023D8
+:106C100008226944F41A6419203CE77F4F70A47F6E
+:106C20008C70891C521E00E02CE19B1C002AF1D1C3
+:106C3000002310260822B03003A91C460331F51AA0
+:106C40002D18203DEF7F4F70AD7F8D70891C521E37
+:106C50009B1C002AF3D1684602F0FDFB034D08AAF5
+:106C6000E868CCCA01467831C36704E0040100201B
+:106C7000FFFFFFFF26E08267CF6005208E60FFF7F1
+:106C8000D1FDE868C03044744BE011E026E05C219F
+:106C9000095C002904D0012160304171022000E02C
+:106CA0000D20FFF7BFFDE1680020C031487438E0D7
+:106CB0000620FFF7B7FDE16800204031887630E01C
+:106CC00009207EE70C20FFF7ADFDE0680021403091
+:106CD0000183817F01221143817722E0E0683B211B
+:106CE0000A5CE221095C00291BD00123002130301D
+:106CF00001F0C1FB002814D0E068E221095C0429FE
+:106D00000FD14030807F80070BD10C20FFF78AFD28
+:106D1000E168002040314882012088758A7F024363
+:106D20008A7700F0B1FF002805D0FF490020C9682C
+:106D30008031088405E0FC48C0688030018C491C23
+:106D4000018400F0A4FF002807D0F748C168A031F3
+:106D5000087B022807D8401C0873F348C068A0309D
+:106D6000007B022808D9F0480021C2681046803014
+:106D700001844184A0321173EB4C3C21E068012373
+:106D80000A5C0021303001F076FB002804D1E06875
+:106D90002030007F07285DD1E0683B210A5C012399
+:106DA0000021303001F067FB002853D0E0683D211E
+:106DB0000A5C01230021303001F05DFB002849D03E
+:106DC000E0683E21095C022944D1A030007B002804
+:106DD00040D10C98F6F774FB00283BD0FBF70AFC77
+:106DE000002837D0E068054601468035688B0128C9
+:106DF00030D90B460120A0335871084640308689AF
+:106E0000C089821E964201DB012002E0801B401EE9
+:106E100080B22A8CE688B24201D3012202E0B21A83
+:106E2000521C92B2904200D91046012801D1002292
+:106E30005A71C0310A7A002A11D06A8C49898A4273
+:106E400001D3012102E0891A491C89B2884206D97E
+:106E5000084604E0E26801200021A0325171E26896
+:106E6000138E1146181880B280311446888320345E
+:106E7000A57F002D1DD0012D1BD0022D0DD0032D7F
+:106E80000BD0FFDFA84C0F9DA0888005C00F1AD043
+:106E9000E16800208031C8851BE0657F032D0AD0A2
+:106EA000237F082B05D04032D38992899A1A921EEB
+:106EB00080180883E6E740329489032CF9D3D089FF
+:106EC0001818401CF5E7E0688030C18DC28B891826
+:106ED000C185E068CE21095C002908D13D210A5C0A
+:106EE00001231946303001F0C6FA002807D0E168C6
+:106EF000084640308031028AC98B511801823D21F9
+:106F0000002D04D0E0684030817201211AE0207821
+:106F1000022809D0012817D06078002829D014222F
+:106F2000104219D01E2119E0E0686521095C002992
+:106F300003D006224A210A5402E016224A210A54AA
+:106F40000121403041724CE0E068D021095C4030C2
+:106F500081720121417244E0020705D5E0684030AA
+:106F60008172012141723CE0800700D1FFDF2A21BC
+:106F7000F4E7E06801464030827D002A05D0438A6C
+:106F80005A1C4282828A934210D2827E002A05D005
+:106F9000028B531C0383838A9A4207D2038AC289D5
+:106FA000934208D3CE235B5C002B04D02221817254
+:106FB0000121417215E02031897F0029818906D0A5
+:106FC00091420BD3082181720121417209E0062907
+:106FD00004D33E2181720121417202E0407A0028EF
+:106FE00011D0E068002102462032D17611779177E6
+:106FF000A0308079002801D0022001E00021032088
+:10700000FEF7CBF903E000210846FEF7C6F9E16878
+:107010000020A031887111B0F0BD10B542494A7806
+:107020008B781A430ED1002809D00879000704D5BF
+:10703000C8682030407F032804D0012010BDFEF72F
+:107040002CF910BD002010BDF8B5374C0546A088BE
+:107050000E462843A080A80703D5E80700D0FFDF2D
+:107060002661E807012700281DD03046666101F03F
+:1070700059FC062802D00B2815D10AE0E068014629
+:107080002030027F122A0ED100228A66CA66C77794
+:1070900009E0E06801462030027F0C2A03D100227B
+:1070A000C27740310F77A8071AD5206901F03AFC62
+:1070B000052802D00B2813D10AE0E0683C21095CC6
+:1070C00010290DD10021016741674030077007E0AA
+:1070D000E0683C21095C0B2902D10021403001709D
+:1070E000280601D50820A070F8BDF0B50E4C85B07B
+:1070F0002269090A012609023143029100250392FF
+:107100000190A5806570A5702570A621E0600E54E1
+:107110000088F6F7CEFE0090002800D1FFDFE0687F
+:107120000088FBF71DFA01E004010020E0680088F8
+:10713000FBF73AFAE0688030408B00281DD003A8A6
+:10714000FBF711FA002818D0E068CE21095C00296D
+:1071500013D03D210A5C01231946303001F08BF930
+:1071600000280AD1E06850210D526030457102209C
+:10717000FFF758FBE068A0304571E068F021095C3A
+:10718000002905D1018C8288914201D9E18001E07A
+:107190008188E18001468031CA8B521E93B20A8CED
+:1071A000D21897B202460F84A0321479002C02D074
+:1071B0004D84157102E04C8CE4184C844030848975
+:1071C000E4188481488B012801D8401C4883002B97
+:1071D00000D015735079FE4C002814D0E088874207
+:1071E00011D20098F6F76CF900280CD0E06801463F
+:1071F000C030027A002A06D08031498C4089814211
+:1072000001D300F047FDE068A5210D543C21095C45
+:10721000062901D0072916D1E421028E095A511AF4
+:1072200009B200290FDB0146E631083003F051FCBA
+:107230000221E06800F0B4FFE068E3210D543C2136
+:107240000D5460308671E0689E210A5A0146303044
+:1072500001F04DF8E068C821095C002901D08030B8
+:107260004584DC480090DC4BDC4A0199029800F030
+:107270007AFBE0683C210A5C01230521303001F0F3
+:10728000FAF8002801D000F06AFB05B0F0BD10B597
+:1072900000F0B7FC10BDF8B5CD4C022720790025D1
+:1072A0000007002811DA607800280ED1E068014656
+:1072B00020310A7F142A03D14030C57685760D77B8
+:1072C000487F032801D127704D7700F035F9A28857
+:1072D00001265007002815DA6078002812D1E068EE
+:1072E000014620310B7F062B02D0082B05D102E08E
+:1072F000E030C67001E0E030C770487F022801D15D
+:1073000026704D7790070327002841DA607800281F
+:107310003ED12069C078801E0C287DD201007944BE
+:10732000097949188F4405B235425815B221B2285F
+:10733000864DE0683D210A5C01231946303001F09A
+:107340009AF8002824D1E0683D210F54403085751B
+:1073500009E0E0682030007F052800D0FFDFE0680A
+:107360003C210D544030857691E0E0682030007F6C
+:10737000092877D0FFDF83E0E0682030007F0B280A
+:1073800000D0FFDFE0685B210E540C212030017734
+:107390007DE0E0682030007F0F2800D0FFDFE0684C
+:1073A0005B210E5410212030017770E0E06820301E
+:1073B000007F102800D0FFDFE06812212030017725
+:1073C00065E0E0682030007F102800D0FFDFE06833
+:1073D0001421203001775AE0E0682030007F162821
+:1073E00000D0FFDFE06801464030C5768576E031A9
+:1073F000087F002800D0FFDFE068014640310A7FA7
+:10740000002A0AD00D77FF21028801310A52014675
+:10741000E0318D770C2209E038E0C21D0188F93295
+:1074200011800146E0318D7796700B220A7720306B
+:1074300005772CE0E068E221095C042916D13B21A4
+:107440000A5C01230021303001F015F8002800D13A
+:10745000FFDFE068014640318A7F920703D4203085
+:10746000C67603E00CE08D75E0308570E0683C2165
+:107470000A5C01230721303000F0FDFF002806D010
+:10748000E0685A210D542030057700E0FFDF2079B5
+:10749000C00609D56078002806D1E0682030017F59
+:1074A000062901D107210177A078000711D5E068EE
+:1074B0003C210A5C01230521303000F0DCFF00286C
+:1074C00005D008206070E068E030057701E000F04A
+:1074D000E5FBE0683C21095C08292CD10146028EBD
+:1074E000C0318B8C521C9A4225D16278002A22D15D
+:1074F0004A8D43889A4207D18B8D8488A34203D159
+:10750000CB8DC488A34208D003888B86CA868A8D17
+:107510000A87CA8D4A87F0210E5401212C4C00F0B5
+:107520003FFE00210420FDF738FFE068E3210D5401
+:10753000203005778777F8BD70B5254C82B020796B
+:10754000C0076FD060693C21C678E06801230A5CFF
+:107550000521303000F08FFF082500280CD0022EC6
+:107560000AD00A2E08D00B2E06D0032E04D0062EE9
+:1075700002D06078284360706078002852D160693A
+:10758000C0780D287DD201007944097949188F44CB
+:107590004A2706C67878FD79FC78A3BFFB00E0682F
+:1075A0003D210A5C01231946303000F064FF0028B9
+:1075B00068D1606901F02EFAE168D02250540222AD
+:1075C0003D2042540020403188768875ACE10000AF
+:1075D000040100209F6A01001B7001004970010036
+:1075E000E0683C210A5C01230021303000F043FFB9
+:1075F00000287FD06078002844D1606901F003FA48
+:10760000E168E42250520A8E801ACC4A00B29042BD
+:107610005BDC002859DDE631606901F0E9F90621FB
+:10762000E06860E188E1E0683C210A5C0123002118
+:10763000303000F020FF00285CD06078002821D195
+:10764000606901F0A2F9002831D0606901F098F971
+:10765000E168E42250520A8E801AB84A00B2904281
+:1076600033DC002831DD606901F084F9E168E03144
+:107670008871606901F077F9E168C0310885606957
+:1076800001E033E192E001F053F9E168C03148854F
+:10769000606901F056F9E168C0318885606901F0E0
+:1076A00059F9E168EE22505220310D773CE1E06853
+:1076B0003C210A5C01230021303000F0DCFE002870
+:1076C00018D06078002871D120E1282040318872DC
+:1076D0000120487228E10DE0E0683C210A5C0123AA
+:1076E0000021303000F0C7FE002803D06078002869
+:1076F0005CD102E00120607016E1E06800220146E2
+:1077000040300283012282760B20203108770BE182
+:10771000E0682030017F0C294FD10D21E4E0E068C2
+:107720003C210A5C01230021303000F0A4FE002837
+:1077300004D1E0684030007F00287DD060780028C8
+:1077400034D101E06070EFE0E1680022084640308B
+:10775000028301258576B031606901F078F9E1682E
+:107760006069883101F084F9E068FF300130007908
+:10777000002800D0FFDFE168FF200A88073042526E
+:10778000FF310931606902E01EE083E00FE001F0A3
+:1077900048F9E1686069FF31113101F04EF9FF21CC
+:1077A000E06805310D540F2120300177BCE0E0681E
+:1077B00001462030027F122A01D00220C2E70022B7
+:1077C00040318A7616218FE0E0683C210A5C012373
+:1077D0000021303000F04FFE002809D1E0683B2145
+:1077E0000A5C01230721303000F045FE002823D039
+:1077F000607800284DD1E0684030807F800715D444
+:10780000606901F066F9E1684031C877606901F0AC
+:1078100062F9E16840310884606901F061F9E1686A
+:10782000022240314884887F10438877E0685E21D7
+:10783000095CC90716D100E066E03C210A5C01231F
+:107840000021303000F017FE002800D1FFDFE06893
+:1078500001213C2211540423E32213544030817649
+:1078600000210183E06802462032D17E012903D144
+:107870000021D176562319540146E0310B46897810
+:10788000042951D100219970D27E002A4CD1403078
+:10789000817549E0E0683C210A5C01230021303019
+:1078A00000F0E9FD00282FD0607800283CD169461F
+:1078B000606901F025F968460078C107C90F68467C
+:1078C000017004D0E06801216030017103E0E068DC
+:1078D000002160300171E1680022084640310A83CE
+:1078E00001228A760921203001771DE0E0683C21E1
+:1078F0000A5C01230021303000F0BDFD002803D0D8
+:107900006078002810D101E001201BE7606901F0D8
+:1079100009F8E1689122505405223C20425400208D
+:107920004031088301208876E2680023106F516F90
+:10793000401C59415167106702B070BDFE7F0000C6
+:10794000F7480078002800D00C20704730B5F44C80
+:1079500005462078002800D0FFDF657230BDF04971
+:10796000012008727047FFB5ED4881B000780A9F8A
+:107970001E4615460C46002805D1002D03D0002ECA
+:1079800001D0002F00D1FFDFE54901984C63086367
+:107990002A460D46EF61AE616A6100222A72EA71E1
+:1079A0002A71EA706A712046AA71AA706A81074634
+:1079B000DC4E00883034F6F77CFAA8623888F6F797
+:1079C00064FAE862FAF724FB0120FAF7F1F8384686
+:1079D0001130FAF7FFFA38460D30FAF7E0F930784F
+:1079E000002810D00120FAF710FB207EFAF7E9F901
+:1079F0000120FAF7CCF8FAF704FB217CCA480029E9
+:107A000003D0CA4902E00320EDE7C949816130781B
+:107A100000280ED001210846FAF7EEF97068803090
+:107A2000806AFAF705FB01202870FAF7F9FA05B029
+:107A3000F0BD01210020FAF7DFF9F4E7F0B5B94E07
+:107A400083B031464C681B20694608803034607929
+:107A50000027B34D002828D0012859D002285BD038
+:107A6000032862D0FFDFAE4AF723116A0878184076
+:107A70000870A379DB071B0F1843FB23184008701D
+:107A8000E379DB075B0F1843EF2318400870677931
+:107A9000906AF5F725FD0546FAF7ACFD022F4BD0AD
+:107AA000012F4CD0032F4DD050E0A248FAF77FFDB4
+:107AB000002809D0012080020122296AAA706A697F
+:107AC000904703206071CEE701AA6946A86AF5F7DE
+:107AD000E3FB2862002803D02B21095D002904D094
+:107AE0009448FAF73AFD012010E069460979002927
+:107AF00005D1077047708770012100F084FE684649
+:107B00000088C1B2286A01F00EF802206071AAE76D
+:107B10008848FAF722FDA6E701AAA86AF5F7BCFB98
+:107B2000286200289FD1FFDF9DE78248FAF73FFDDA
+:107B3000002898D1FFDF96E7A84305D006E0A843C8
+:107B400002D003E0002D01D0012000E00020744DA0
+:107B50000101286A027811430170E17B002923D0DA
+:107B60006179012920D0214648318EC972488EC0E2
+:107B700021465831714802F09BFF7148FAF755FAD7
+:107B8000307800280ED000216B480176E26BA16BA3
+:107B9000426101616A492A6AF9F783FF0020F9F717
+:107BA0008FFF05E00121EFE7FAF73FFAF9F7A8FFA9
+:107BB0003078002811D0286A0078C00606D46148C1
+:107BC0000078C00602D42879002802D0A8780028BE
+:107BD00003D06879002805D008E001210846FAF7AB
+:107BE0009CFAF6E701206871FAF739FA286A0178F9
+:107BF0002973417869738078A8730220287003B0D4
+:107C0000F0BD10B546480078012800D0FFDFFAF734
+:107C1000FFF9444801784468002908D000F0D5F9FC
+:107C20002034207A012801D1FAF75EFA10BDFFF75F
+:107C300005FFF5E770B53B4900254C68FAF72EFAC9
+:107C4000FAF721FAFAF751F9FAF7D5F9F9F758FFE7
+:107C5000FAF7E6F92034207A012801D1FAF73BFA45
+:107C60002F4C0021626960899047E269E179E078F0
+:107C70009047257070BD10B529480078032800D0C2
+:107C8000FFDFFFF7D7FF10BD254840797047244834
+:107C9000007970472249012088717047F8B5204D5E
+:107CA0002049686A4C6841780126C906C90E0091CE
+:107CB00000273034E96A02F013F8002807D00128C1
+:107CC0001BD0022840D003284CD0FFDFF8BD012292
+:107CD000E86A0099F5F794FC216C606C491C00225D
+:107CE000504121646064E079012804D0E671687A2B
+:107CF000F1F74DFCF8BDE771F9E70022E86A009959
+:107D0000F5F77EFC206C616C0022401C51416164DF
+:107D10002064E079012801D1E771F8BDE671F8BD72
+:107D20001C0100204C010020001500401F00030230
+:107D30001B0003023C0100203011002049110020EB
+:107D40000A1100202B010020E86AF5F75BFD216C89
+:107D5000606C491C0022504121646064E079012874
+:107D6000DCD1D9E7E86AF5F74DFDD8E7F8B5D94F8A
+:107D7000D94D394628784C6801263034022800D085
+:107D8000FFDFA078002809D00021A170AE706A69D9
+:107D9000042090473878002800D02671286A00789F
+:107DA000C043800708D1E078002805D1E670296A31
+:107DB000AE706A69022090470121002000F04BF963
+:107DC000002802D0FFF736FFF8BD00F0FEF8F8BD3E
+:107DD000F1B5C04DC04C294620784F680126303798
+:107DE000032800D0FFDF6089012149020843608138
+:107DF000009900297ED0F9F79BFE002810D1387C2D
+:107E000000280DD0606A4178C90609D00078F97958
+:107E10000007C00F884203D1E670FFF70BFFF8BDE3
+:107E2000AD490846426A1378CB7353780B74927845
+:107E30004A744189202211434181002101716C68FB
+:107E4000303045682820405D3034012813D1FAF7DE
+:107E500042F92146284600F0E6FA00280BD09D485A
+:107E600001784068002917D0FF30173029884180F9
+:107E7000217A01710670984DB979686A00784007D7
+:107E8000C00F88424AD09348446830346079002853
+:107E90003FD0022802D011E0C830E7E7A86AF5F722
+:107EA00030FA002800D1FFDFA06BE16B0022401CFC
+:107EB0005141E163A063687AF1F769FB00206071CA
+:107EC00084480078002808D020790021002804D0B8
+:107ED0002171AE706A6910209047E078002814D0B4
+:107EE0000020E070FAF773FB002800D1FFDF0820C4
+:107EF000002100E05AE0AE706A699047A16BE06B28
+:107F0000491C00225041A163E063A07901281DD0E3
+:107F1000A6716889FF21013108436881686AFB798D
+:107F200002781107C90F994243D16A4910274C685A
+:107F300091073034890F012920D002291ED003294E
+:107F400007D0E87904210843E87132E00020A071ED
+:107F5000DFE700F07CFC00280DD0A670696AAE70E7
+:107F60006A6930469047E079012802D10020E0712B
+:107F70001FE0E6711DE0E8793843E5E74078C10687
+:107F800010D06978002914D1C006C00E1B28F2D881
+:107F9000287A002803D06A698020904709E0FFF71B
+:107FA0007DFE06E0E0790128E3D1DFE740210843C8
+:107FB00060810120009900F04EF8002802D0FFF700
+:107FC00039FEF8BDFFF73AFDF8BDF8B5424C1B216C
+:107FD000E06AF5F7BAFA00216062002801D061700A
+:107FE00003E0012060703D4860623A4E7568307869
+:107FF0003035287C002822D0294648318EC938489F
+:108000008EC029465831374802F052FD3648FAF7FB
+:108010000CF83078002810D0002101204140304871
+:1080200001766A6C296C426101612F4A616AF9F735
+:1080300038FD0120F9F744FD06E00121EDE7606A13
+:10804000F9F7F3FFF9F75CFD01210020FAF765F875
+:1080500003202070F8BD70B51F4C0546002907D1DC
+:10806000012D05D12079401CC0B2207101282DD8E6
+:10807000A16928468847002828D0A1791B480029F3
+:1080800007D0012D05D14178C90602D10178C90672
+:108090001CD5E179002919D10E490978002901D0B0
+:1080A000002102E0012D02D00121294310D1104905
+:1080B0000978CA0602D40078C00607D5A07800283F
+:1080C00004D16078002803D0C80601D4012070BD17
+:1080D000002070BD4C0100201C010020E810002091
+:1080E00030110020491100200A1100202B0100202E
+:1080F0002801002070B504460020A083208C1E4675
+:1081000048431546114602F0B2FA2084F000294691
+:1081100002F09FFA401C80B2014619226943920284
+:10812000E083914201DD401EE0837D20294600026C
+:1081300002F08FFA401CA08470BD30B50A7BD206D5
+:10814000D20E0A73002282758B181B7ADC075B083B
+:10815000DD07E40FED0F2C195B08DD07ED0F2C197F
+:108160005B08DD07ED0F2D195C08E307DB0F5B19DA
+:108170006408E507ED0FEB186408E507ED0FEB1851
+:108180006408E31884186374847D521CE318D2B227
+:108190008375052AD8D3D8B2252800D9FFDF30BD92
+:1081A000F8B504460E4625462246234621460020C1
+:1081B0003035C032A0338031032E0AD0002E38D0A3
+:1081C000012E3FD0022E03D121462846FFF7B5FFEE
+:1081D000F8BD2880A871E871E87228736873A873E5
+:1081E000A870E8702871687168762E46A8832036DA
+:1081F0006884B0712885B072E8752876E8732874B1
+:10820000F0723073B073012737752884B075088316
+:1082100048838883C883088448845871C885187344
+:10822000108050802821085520841072907350745B
+:10823000F8BDC88598716188E3880A462846FFF72B
+:1082400059FFC1E7C885D38D528D61882846FFF755
+:1082500051FFF8BD70B50446024630348032054601
+:1082600003290AD0002933D0012938D0022903D1AB
+:1082700029462046FFF761FF70BD00202080A071D5
+:10828000E071E07220736073A073A070E0702071E1
+:10829000607160762146A0832031608488712085DA
+:1082A0008872E0752076E0732074C8720873887352
+:1082B00001230B752084887529461084A0318870AD
+:1082C0001076D061282250550875C035287170BDD0
+:1082D0006988EB880A462046FFF70CFFC8E7D06B99
+:1082E0006988C38942892046FFF704FF70BDF8B54D
+:1082F000867D0F460446002E01D0252E01D912207E
+:10830000F8BD002A15D0387EE17D5043081825219C
+:1083100002F09FF90846E175CA084907490FBA18E3
+:108320000125127A2B468B401A4204D02076002079
+:10833000F8BD0020F8BD314602F08BF9491CC8B2E7
+:108340000022A118497C814214D30021BB181E7A57
+:108350002B468B401E4201D0401EC0B2002804D0E4
+:10836000491CC9B20829F3D306E0D0004018207692
+:108370000020F8BD401AC0B2521CD2B2052AE0D388
+:108380001F20F8BD30B50D460446072900D9FFDF90
+:10839000E078502108406907490F88300843E070B1
+:1083A000A078A72108401830A07060785E210840AE
+:1083B000203060702078BC2108404030207030BDF3
+:1083C0000179490901D000207047002230B41146DC
+:1083D000445C491CE3076408E507DB0FED0FEB186D
+:1083E0006408E507ED0FEB186408E507ED0FEB18DF
+:1083F0006408E507ED0FEB186408E507ED0FEB18CF
+:108400006408E507ED0FA407EB18E40FE318D21892
+:10841000D2B20529DCDB012A02D930BC0120704729
+:1084200030BC0020704738B505460C466846F9F761
+:1084300064FE00281ED069460020085620720921DB
+:1084400061560022411A00D5494220356B7A8B4291
+:108450000FDCFF2B0DD0A17A491CC9B2A172AB7AF7
+:10846000994202D8617A7F2903D160720020A072FC
+:108470000122104638BD30B414460B3C08293DD2C9
+:108480000D007D442D796D19AF4403060B10131CAC
+:108490003336002A35D031E0022A32D0032A30D0D8
+:1084A0002CE0072A2DD0062A2BD027E0082A28D036
+:1084B00024E0002B02D00B2C23D91FE00A3A0B2A10
+:1084C0001FD91BE0002B02D00B2C1AD916E00D2A65
+:1084D00017D00C2A15D02030007B002804D00D2A9C
+:1084E0000CD3152A0DD909E0112A07D3152A08D96A
+:1084F00004E0092A05D001E0012A02D030BC0020A6
+:10850000704730BC0120704710B5282102F084F874
+:1085100010BD30B5054600780A0700090001120FAA
+:108520001043287007290ED20800784400790018FB
+:1085300087440305030503070300062405E00C2414
+:1085400003E0222401E00024FFDF68788009800135
+:108550002043687030BD00780007000F704710B5E9
+:10856000C01C02F098FA10BD0A4610B5C11C104696
+:1085700002F091FA10BD10B5093002F08CFA10BD6E
+:108580000278BF23C9071A40490E0A430270704798
+:1085900000784006C00F704702785206520EC9019B
+:1085A0000A430270704770B50C460546C11C204650
+:1085B000093002F070FA20784006400E20702978C9
+:1085C0004906C90FC9010843207070BD70B5154632
+:1085D0000E4604461F2A00D9FFDF20462A463146B0
+:1085E000093001F0BCFF6078AD1D80098001A9064B
+:1085F000890E0843607070BD70B5054640780E4620
+:108600008406A40E062C00D2FFDFA41FE4B21F2CA8
+:1086100000D91F24294622460931304601F09FFF28
+:10862000204670BD70B515460E4604461F2A00D977
+:10863000FFDF20462A463146093001F090FF60787E
+:10864000AD1D80098001A906890E0843607070BDC8
+:1086500070B5044640780E468506AD0E062D00D254
+:10866000FFDFAD1FEDB21F2D00D9FFDF21462A46E7
+:108670000931304601F073FF284670BD0A78C27395
+:108680004A7802748A784274C978817470470A788B
+:10869000C2744A7802758978417570474176090A33
+:1086A00081767047C176090A017770474177090AD8
+:1086B00081777047C175090A0176704781757047E7
+:1086C00020300279C90652095201C90E0A430271CB
+:1086D000704720300279D206D20E49010A43027156
+:1086E000704710B51F3002F0CBF910BD417800780B
+:1086F0008906890E0007000F06D0012808D002283D
+:1087000009D0062810D10AE0891F1F290AD90BE0D9
+:108710000C2907D008E0891F1F2903D904E0891F0D
+:108720001F2901D801207047002070474178007848
+:1087300089060007890E000F042805D1062903D3F6
+:10874000252901D8012070470020704770B40178B6
+:108750000907090F03292ED0052931D1411C827E3A
+:108760000C46437E11021943037FC27D1D02037E26
+:10877000C67E1B021343827D407835438006800EFF
+:1087800022281DD106291BD31920C001814217D8E8
+:10879000FF26F436B54213D8002A11D0082A0FD884
+:1087A0008A420DD28B420BD8617F227F090211438E
+:1087B000814208D904E040788006800E0C2802D05F
+:1087C00070BC0020704770BC0120704710B522219A
+:1087D00001F022FF10BD00B502788B0792089200CD
+:1087E0009B0F1A43027042785209520142700129CC
+:1087F00004D0022902D0032901D0FFDF00BD0121EE
+:108800000A43427000BD00B502788B0792089200BF
+:108810009B0F1A430270427852095201427001299B
+:1088200004D0022902D0032901D0FFDF00BD0121BD
+:108830000A43427000BD00788007800F70470278BD
+:10884000EF23C9071A40C90E0A43027070474178E6
+:10885000C078C906C90E0E2835D202007A441279B2
+:108860009218974406090C0F1215181B1E21242775
+:108870002A2D0C2929D02AE0082926D027E0022910
+:1088800023D024E0172920D021E00D291DD01EE09F
+:1088900001291AD01BE0012917D018E0022914D0B1
+:1088A00015E0092911D012E009290ED00FE00129A5
+:1088B0000BD00CE0012908D009E0062905D006E01C
+:1088C000022902D003E01B2901D8012070470020B3
+:1088D000704730B50546C1700E291BD20800784498
+:1088E00000790018874406080A0C0E10100A1212AC
+:1088F0001010140A0C240FE008240DE002240BE0F1
+:10890000172409E00D2407E0012405E0092403E011
+:10891000062401E00024FFDF68784009400120437D
+:10892000687030BDC0787047C171090A0172704724
+:10893000017AC2790802104370474172090A8172B4
+:108940007047817A427A080210437047C172090A5F
+:1089500001737047017BC27A08021043704741716E
+:10896000090A817170478179427908021043704782
+:1089700001717047007970474173090A817370472C
+:10898000817B427B08021043704770B4017AC3793F
+:1089900009021943431C857A1C46467A2B0233434D
+:1089A000657926792C023443C21C664E00798D1FEE
+:1089B000B54215D8FF25F435AB4211D800280FD0A9
+:1089C00008280DD888420BD28C4209D8507A117AE7
+:1089D00000020843B11D884202D870BC01207047D4
+:1089E00070BC0020704710B5001D02F049F810BDA2
+:1089F0000A4610B5011D104602F042F810BD417242
+:108A0000090A81727047817A427A080210437047DE
+:108A1000017170470079704710B5001D02F048F8E9
+:108A200010BD0A4610B5011D104602F041F810BDF8
+:108A30000A780273497841737047027B0A70407B61
+:108A40004870704710B50E3002F032F810BD0A467B
+:108A5000014610B50E31104602F02AF810BD0A7812
+:108A600082754A78C2758A780276C97841767047ED
+:108A7000827D0A70C27D4A70027E8A70407EC87014
+:108A8000704710B5001D02F013F810BD0A4610B56E
+:108A9000011D104602F00CF810BD0A7802734A78E6
+:108AA00042738A788273C978C1737047027B0A70F7
+:108AB000427B4A70827B8A70C07BC87070470171AC
+:108AC00070474171090A81717047C171090A0172C9
+:108AD00070470079704781794279080210437047E6
+:108AE000017AC2790802104370470171704700791A
+:108AF00070470171704710B5001D01F0D9FF10BD1E
+:108B00000A4610B5011D104601F0D2FF10BD10B588
+:108B1000001D01F0CDFF10BD0A4610B5011D104625
+:108B200001F0C6FF10BD30B50C4605461B2900D923
+:108B3000FFDF6878E10640094001C90E084368700C
+:108B400030BD00007A0C000070B504461020851A74
+:108B5000281901F004FD2906090E06D0491EC9B2E4
+:108B600080206054204601F057FD70BD30B505E00F
+:108B70005B1EDBB2CC5CD55C6C40C454002BF7D1DF
+:108B800030BD10B5002409E00B78521E5B00234372
+:108B900003700B78401CDC09D2B2491C002AF3D1C7
+:108BA00010BD30B50C460978012089B01546002962
+:108BB00009D0012905D12978042902D10520107096
+:108BC000002009B030BD60680590684606900D2110
+:108BD000C01C01F021FD03226846A16801F0BFFC22
+:108BE00001202070062069460874606A08902946B2
+:108BF00004A8F6F75BFBE4E7F0B50C460978012022
+:108C0000FF4E062791B0154600290CD001291DD032
+:108C1000022945D0032904D12978042901D11770EC
+:108C2000002011B0F0BD6068002809D001900296C4
+:108C30000120207068460770606A114604905EE06B
+:108C40000220207004202870566027E0297804292B
+:108C5000E7D1696810222069FFF793FF6868C07B3D
+:108C6000000606D5E64A2069102310320146FFF7B8
+:108C70007DFF102221696069FFF783FF2069C07BB7
+:108C8000000606D5DE4A6069102310320146FFF760
+:108C90006DFF02202070042028706E600320C0E762
+:108CA00029780429BDD1A08910280AD9103880B2AA
+:108CB000A081A1681023091805A86A68FFF756FF6C
+:108CC00014E010281FD0C2B20DA8A168FFF73CFF26
+:108CD000626910230DA909A8FFF748FF102309A90D
+:108CE00005A86A68FFF742FF0320207060680190C2
+:108CF00005A8029068460770606A29460490684695
+:108D0000F6F7D4FA8DE710232269A168E3E7F8B5F6
+:108D10000D4607460B7801200721002B07D0012BB9
+:108D200004D11378062B01D111700020F8BD6C69B5
+:108D300001266170E8686060686A6062A168287CEA
+:108D40000870A681A068A9682022401C01F007FCD9
+:108D5000A08920222030A081A0686968213001F01C
+:108D6000FEFBA08921462030A0812E703846F6F700
+:108D7000B4FAF8BDF7B50D46012009781746064646
+:108D8000002913D0012922D002297DD003290CD13A
+:108D90003978062909D179681022E86901F0DFFBEA
+:108DA00008203870183500207D60FEBD2C6A072031
+:108DB000607093482022203060602020A081686A83
+:108DC00060626968A06801F0CAFB2E70D3E0397850
+:108DD0000629EAD12C6A07206070686A60625168CF
+:108DE0001022E86901F0BBFBE8696060A068002719
+:108DF0000770A681A06806224670A089401C80B238
+:108E0000A081A16808186969491C01F0A8FBA08924
+:108E1000801D80B2A0816969A2680978C907C90F5D
+:108E20001154A0890622401C80B2A081A1680818B4
+:108E30002969491C01F093FBA089801D80B2A081A3
+:108E40002969A2680978C907C90F1154A08910229D
+:108E5000401C80B2A081A1680818E96801F07FFB7E
+:108E6000A0891022103080B2A081A1680818A968DA
+:108E700001F075FBA0890422103080B2A081A168A6
+:108E800008185F49091F00E00CE001F068FBA089A9
+:108E9000001D80B2A081A1680F54A089401CA08150
+:108EA000022067E03978062993D151681022A86919
+:108EB00001F055FB2C6A07206070E8696060686A01
+:108EC0006062A16800200870A681A0680622467032
+:108ED000A089401C80B2A081A16808186969491C5A
+:108EE00001F03DFBA089801D80B2A0816969A26864
+:108EF0000978C907C90F1154A0890622401C80B205
+:108F0000A081A16808182969491C01F028FBA089E3
+:108F1000801D80B2A0812969A2680978C907C90F9C
+:108F20001154A0891022401C80B2A081A1680818A9
+:108F3000E96801F014FBA0891022103080B2A081F2
+:108F4000A1680818A96801F00AFBA0890422103062
+:108F500080B2A081A16808182949091F01F0FFFA11
+:108F6000A089001D80B2A081A1680E54A089401C78
+:108F7000A0810320287021460098F6F7AEF9FEBDC7
+:108F800070B50D46064609780120002908D0012950
+:108F900005D11178062902D109201070002070BD7A
+:108FA0002C6A0720607068686060686A6062E969BE
+:108FB0000622491CA06801F0D2FA0620A081E869C7
+:108FC000A16800780622C007C00F8871A089401CE4
+:108FD00080B2A081A1680818A969491C01F0BFFAF4
+:108FE000A089801D80B2A081A969A2680978C907FB
+:108FF000C90F1154A089401C80B2A081A16801E072
+:10900000AAAE010008180322696901F0A8FAA08934
+:109010001022C01C80B2A081A1680818296901F043
+:109020009EFAA0891022103080B2A081A168081891
+:10903000E96801F094FAA0891022103080B2A08172
+:10904000A1680818A96801F08AFAA08921461030A1
+:10905000A081012028703046F6F73FF970BD70B549
+:109060000D46064609780120144600290CD0012936
+:1090700009D12178062906D10A202070606801F004
+:10908000CFFA6060002070BD6C6907206070E868EE
+:109090006060686A606229691022A06801F05FFA66
+:1090A0001020A081A06820221030A96801F057FA92
+:1090B000A0892022203080B2A081A16808186968A8
+:1090C00001F04DFAA08921462030A08101202870AE
+:1090D0003046F6F702F970BD70B50C4609780120EC
+:1090E00006268EB0154600290BD0012932D0022960
+:1090F00005D12978042902D10B20107000200EB070
+:1091000070BD606907220078C107C90F6846017009
+:10911000A0690078C107C90F68464170801CE168EA
+:1091200001F01DFA02A807220130216901F017FAA7
+:109130006068059009A8069010236A46A168FFF7A9
+:1091400015FD0120207068460674606A0890294663
+:1091500004A822E029780429D1D1A169062205A812
+:10916000491C01F0FCF9616906A806220230491C7D
+:1091700001F0F5F9002008906068019009A80290BC
+:10918000102305AA6968FFF7F1FC022020706846E9
+:109190000670606A049029466846F6F787F8AEE7DD
+:1091A00030B50C460978012089B01546002908D051
+:1091B000012905D12978042902D10C201070002042
+:1091C000FFE460680590684606900822E16801F0B7
+:1091D000C6F9082202A8A16801F0C1F90120207097
+:1091E000062069460874606A0890294604A8F6F7C4
+:1091F0005DF8E6E430B50C460978012089B01546E3
+:10920000002908D0012905D12978042902D10D208F
+:1092100010700020D5E4606805906846069008222A
+:10922000A16801F09CF900200290039001202070B9
+:10923000062069460874606A0890294604A8F6F773
+:1092400035F8BEE410B50B7801208AB0002B09D0A8
+:10925000012B05D11178042902D10E2010700020B5
+:109260000AB010BD48680590684606908B681C7867
+:1092700004705B784370CB681C7884705B78C37033
+:109280000020019002900390012008700623684698
+:109290000374486A0890114604A8F6F707F8DFE758
+:1092A00010B50C780123002C04D0012C11D0022C15
+:1092B00028D121E001220A70CA68052353704B6847
+:1092C0005360114B93609B1ED360496A51621146F3
+:1092D0000EE014780E2C15D102230B70CB680424F9
+:1092E0005C7052685A608A689A60496A5962194685
+:1092F000F5F7F3FF034605E010780D2802D10F20A3
+:1093000010700023184610BDA4AE010070B50C46C5
+:1093100001462039342901D301200BE048280BD025
+:10932000211D074E800080190EC980382568066807
+:109330002846B047206070BD2046E7F7F9FEF9E700
+:10934000DCAE010010B5444800F042FA002800D01D
+:10935000FFDF4148401C00F03BFA002800D0FFDF4F
+:1093600010BDF1B53D4D82B06868009001263A48C5
+:1093700000F036FA384C002803D10026601C00F0BB
+:1093800047FA3749374A0120506000230B604B6091
+:10939000029B6B60106034481214344F19E003696B
+:1093A000DB0616D5324B1A60EFF31083DB07DB0FB9
+:1093B00072B600D001239C4603237B600B68002B10
+:1093C00003D14B68002B00D120BF6346002B00D196
+:1093D00062B60B68002B02D14B68002BDFD04868C7
+:1093E0000028CFD1002E05D000986860601C00F0E6
+:1093F000F7F907E0601C00F0F3F90028BED1164829
+:1094000000F006FA0020FEBDF0B58FB0064604A8B5
+:1094100008AA0D4600240C920D9017E020460C215E
+:1094200048430746E9591022684601F098F87F1929
+:10943000102279680D9801F092F86846FFF791FFC5
+:109440001022B8680C9901F08AF8641CB442E5DB7C
+:1094500000200FB0F0BD84E75401002000E500407B
+:1094600000E1004000E0004000ED00E000E30040CB
+:1094700080E200E0CB48002101708170704770B538
+:10948000C94D01236B60C94B1C68002CFCD0002423
+:1094900007E00E6806601E68002EFCD0001D091D46
+:1094A000641C9442F5D30020686018680028FCD042
+:1094B00070BD70B5BB4C0546BD4E2078022800D06B
+:1094C000FFDFB54200D3FFDF6169BA48012902D846
+:1094D000B94A954201DD03224271491C6161711B49
+:1094E000C160B4496078F6F71DFE70BD70B5AD4C33
+:1094F0000D466178884200D0FFDFAD4E2B0001F0B1
+:10950000EFFA094D0622304D4D4D4D3C4D0020786F
+:10951000022800D0FFDF03202070A078022802D0AC
+:10952000012804D008E0A06800F00EFC04E020460A
+:10953000083007C8FFF7A3FF052020700020A070A7
+:10954000F6F70FF970BDF6F7D3F901466068F7F743
+:1095500003FBB0420DD2616902290AD2FFF7A9FFCD
+:1095600070BDF6F7C5F901466068F7F7F5FAB04245
+:10957000F4D30320F7F7A5FD07E02078022809D0EF
+:10958000052805D0FFDF0420207000F002F970BD2F
+:10959000022000E00320F7F794FDF4E7FFDF70BD41
+:1095A00070B50546F6F7A4F97E4C60602078012876
+:1095B00000D0FFDF7F490220087000220A718D6011
+:1095C00004224A717A4ACA6020706078F6F7AAFDD0
+:1095D00070BD10B5734CA078002802D12078002807
+:1095E00001D0112010BD7548F6F71AF96070607847
+:1095F000002804D0012020700020606110BD0320ED
+:1096000010BD0246010B012310B55B0401209A42F4
+:1096100003D2884000F042FF10BD01239B049A4210
+:1096200004D22039884000F041FF10BD03235B04C1
+:109630009A4204D24039884000F040FF10BD012317
+:10964000DB049A4204D26039884000F039FF10BD33
+:10965000002010BDF8B515469200044617190E46B5
+:109660003F1F009200F081FB012109070A69504366
+:10967000009A9219121FB24201D2012200E0002288
+:10968000002D03D009698908A94201D20920F8BD3B
+:109690004B498C4219D3A74217D3844205D2874243
+:1096A00003D220463043800701D01020F8BD8E42FF
+:1096B0000BD3002A09D12046FFF7A3FF002804D1CD
+:1096C0003846FFF79EFF002801D00F20F8BD3D4827
+:1096D0003D490068884205D02A4631462046FFF7BA
+:1096E000CEFE0FE0FFF775FF0028EFD12D480121D6
+:1096F000C660056184608170284630214843183077
+:10970000FFF74EFF0020F8BD70B501252D07296930
+:1097100004462B4800F09DFF84420BD300F025FB4C
+:10972000A04201D8102070BD28696043FFF769FF8F
+:10973000002801D00F2070BD2248234900688842CC
+:1097400004D02869604300F0FFFA0CE0FFF741FF06
+:109750000028F0D12969134861438160022181709A
+:109760001A48FFF71DFF002070BD1548010B0120AE
+:109770008840401E704770B50D460446FFF7F5FF60
+:10978000204201D00F2070BD2946204600F09AFEED
+:1097900070BD10B5034C6078F6F796F80020207085
+:1097A000A07010BD5801002000E5014000E4014018
+:1097B000B08F06005811002030750000ED940100B4
+:1097C00000B0010098000020BEBAFECA3A56000060
+:1097D000002101700846704701460020087070475C
+:1097E000EFF31081C907C90F72B60278012A01D0C0
+:1097F000012200E0002201230370002900D162B69B
+:10980000002A01D000207047012040037047E7E79D
+:10981000EFF31081C907C90F72B600220270002948
+:1098200000D162B600207047F2E7000045490968A0
+:109830000160002070474349086000207047012103
+:10984000414A002803D0012803D040487047916363
+:1098500000E0D163002070473D49012008603B488B
+:10986000801C704704223B4B3949002805D05A60C0
+:10987000086901221043086108E0086940084000B7
+:1098800008619A6030490020C0318860002070472C
+:109890002F490622002808D0012809D002280DD01F
+:1098A00003280FD02948401C70470869904302E004
+:1098B00008699043801C0861002070470869904344
+:1098C000001DF8E708691043F5E721494A6A024399
+:1098D0004A62002070471E494A6A82434A62002059
+:1098E00070471B49496A0160002070471849CA69DE
+:1098F0000243CA61002070471549CA698243CA61A0
+:10990000002070471249C969016000207047104962
+:10991000024600204031002A03D0012A01D007204E
+:1099200070478A63704708490020C03188600A4840
+:1099300001688022090A09021143016007490120D8
+:109940000860704700040040400000400420000010
+:10995000000500400003004000E400E000E100E0FA
+:109960005A495B4B0A685B499A42096801D18904EC
+:10997000890C0160002070475449554B0A685549CD
+:109980009A4201D18004800C4860002070474F4902
+:109990004F4B0A684F499A4201D18004800C88607D
+:1099A0000020704730B5494B494D1C684A4BAC42CA
+:1099B00002D0102802D203E00E2801D3184630BD91
+:1099C000C3004448181801614261002030BD3F497E
+:1099D0003F4B0A684049491C9A4202D0042802D2EF
+:1099E00003E0022801D3084670473C4A0121C00029
+:1099F00080180160002070473449354B0A683649A9
+:109A0000491C9A4202D0042802D203E0022801D362
+:109A100008467047314A0121C0008018416000208B
+:109A2000704770B5294A2C4B14682D4E284D820082
+:109A30005B1C9219AC4203D0042803D2116006E0EB
+:109A4000022801D3184670BD8804800C10600020E5
+:109A500070BD70B51D4A204B1468214E1C4D82000C
+:109A60005B1C9219AC4203D0042803D2106806E0B4
+:109A7000022801D3184670BD10688004800C08606D
+:109A8000002070BD10B5134A164890600E200021CA
+:109A9000C3009B1819615961401C1028F8D300209D
+:109AA0000F4A05E0022803D383009B18196005E0E4
+:109AB00083009B181C68A404A40C1C60401C042890
+:109AC000F0D310BD03490748886070479800002014
+:109AD000BEBAFECA00F501400820000000F00140B7
+:109AE00000F8014000C0FFFF10B572B600F0D7F8D3
+:109AF00000280BD0E7F7F4FBF5F71EFEF7F76BFA3B
+:109B00006B490020C86288626A49086062B600201A
+:109B100010BDF3B50446002601200007C06A81B0DD
+:109B2000C0430006000E04D163480068401C00D109
+:109B3000012672B600F0B3F8002802D062B6082001
+:109B4000FEBDE7F70BFBE7F7CFFB5C4F002500906E
+:109B50006909E806C00E8900C9190968C140C8072B
+:109B60001FD0202D03D20098E840C0071FD168B253
+:109B7000002808DA0107090F08398A0850499200BD
+:109B80005118C96904E081084E4A8900891809689A
+:109B90008007C00EC1400806800F00F005F90028BC
+:109BA00005D06D1C202DD3D3002C03D003E062B66A
+:109BB0004548FEBD454C2078022803D962B60120F5
+:109BC0000003FEBD3E48C1690902090AC2051143EE
+:109BD000C161002E05D1364D3D48E862E7F784FBB0
+:109BE000A86220780028607802D000280BD107E016
+:109BF000002808D0402806D8A078212803D804E0FF
+:109C0000A078002801D00720FEBD2A49314808600D
+:109C1000314902980860E7F767FB2146F7F7C2F978
+:109C2000F5F74EFD00F0FCF9FFF724FC2046E7F7BE
+:109C300025FB040062B603D0FFF756FF2046FEBDA9
+:109C40000020FEBD10B5044600F029F8002800D021
+:109C500001202070002010BD2049086000207047BE
+:109C600010B50C46102808D011280BD012280CD0A3
+:109C700013280ED00120086010BD03CC083CFFF76C
+:109C800048FF0AE0FFF730FF07E02068FFF7DAFF40
+:109C900003E01249206808600020206010BD0548DC
+:109CA0000C490068884201D10120704700207047AC
+:109CB00000050040980000200010001000E100E0C6
+:109CC00000ED00E000E400E001100000ACAF010096
+:109CD00088120000BEBAFECA7001002004000020F5
+:109CE000F0B585B00F460446FEF7A5FD0546607841
+:109CF0006946C606F60E3846F3F78AFD01000AD01B
+:109D0000012D02D0032005B0F0BD01980279C3787F
+:109D10001002184307E0022D12D1042E10D320792F
+:109D2000E27800021043001D80B28919814202D1FD
+:109D3000002005B0F0BD814202D2012005B0F0BD87
+:109D4000022005B0F0BD00000A4A022151600A4914
+:109D50000B68002BFCD0906008680028FCD0002025
+:109D6000506008680028FCD0704701200007406957
+:109D70007047000000E5014000E401408107C90E82
+:109D8000002808DA0007000F08388008854A80009C
+:109D90008018C06904E08008834A80008018006849
+:109DA000C8400006800F7047042805D2002803D061
+:109DB000022801D0012070470020704710B50446EA
+:109DC00000F0E1F8002812D02046FFF7D7FFFFF798
+:109DD000EBFF00280DD07549E2060B78D20E01206A
+:109DE0009040002B08D04A681043486006E0704855
+:109DF00010BD6F48401C10BD6E490860002010BDAA
+:109E000010B5044600F0BFF800280BD06749E20601
+:109E10000B78D20E01209040002B05D04A68824377
+:109E20004A6004E0624810BD624980310860002049
+:109E300010BD70B50D46044600F0A5F800280BD003
+:109E40005D480068E206D20E01219140084000D032
+:109E500001202860002070BD554870BD10B5044633
+:109E600000F091F8002807D0E106C90E01208840D3
+:109E700051490860002010BD4D4810BD10B5044682
+:109E800000F081F8002808D0E106C90E01208840C2
+:109E9000494980310860002010BD454810BD70B5AB
+:109EA0000D46044600F06FF8002819D02846FFF749
+:109EB0007BFF002816D0A007C10EFF228A40A8070A
+:109EC000000E8840002C10DA2107090F08398B0892
+:109ED00034499B005B18D96991430143D9610CE077
+:109EE000334870BD3248401C70BDA3082E499B000A
+:109EF0005B181968914301431960002070BD70B56B
+:109F00000C46054600F03FF8002806D02846FFF72B
+:109F100035FFC0B22060002070BD254870BDBFF382
+:109F20004F8F20492548C860BFF34F8FFEE770B5BB
+:109F30000546F7F7EEFC002801D0072070BD1B4C4A
+:109F40000120217800290ED1207072B6F7F752F85F
+:109F5000184E8036316881436160F7F74BF8C04393
+:109F6000306062B600202870002070BD0F490A786A
+:109F7000002A06D0002804D10E4A4868106000204C
+:109F800008700020704710B50446202807DAF7F75C
+:109F900031F80121A140084201D1012010BD00206B
+:109FA00010BD000000ED00E000E400E074010020BE
+:109FB0000120000000E100E000E200E00400FA05FA
+:109FC00070B5002402460D4620462146002A1ED0C8
+:109FD000012A04D0022A04D0032A1ED103E0012062
+:109FE00002E0022013E003202B0000F079FD0716A9
+:109FF0000507090B0D0F1600012108E0022106E0FC
+:10A00000032104E0042102E0052100E00621F5F728
+:10A0100020FC002801D0204670BD0724FBE700008B
+:10A02000FA4805218170002101704170C170816082
+:10A03000704710B5F6490A78022A07D0CA68101886
+:10A04000C860C8686438F6F749FD10BD8A68101802
+:10A0500088608868F6E70378EE49EF4A002B02D063
+:10A06000012B10D014E00379012B01D0002B0FD16C
+:10A070004379002B01D0012B0AD18368643B8B42CA
+:10A0800006D2C06810E00379012B03D0002B01D069
+:10A09000002070474379002B01D0012BF8D1C36811
+:10A0A000643B8B42F4D280689042F1D80120704723
+:10A0B000F8B504460226F6F7F0F90068002800D04B
+:10A0C000FFDF0127D14D002C08D02078002817D0C1
+:10A0D000012805D0022811D0032813D02F710DE0DC
+:10A0E0006068C82808D3F6F762FD002804D06068CD
+:10A0F000FFF79FFF012603E0002601E000F0B4F91E
+:10A100003046F8BD28780028F8D16068FFF7A3FF33
+:10A110000028E3D060680078002823D0A8780428BD
+:10A1200000D0FFDFBA4F0020387060680079002847
+:10A130003DD00020387160684079002839D0042073
+:10A14000787160688168E868F5F73CFEB86060681F
+:10A15000C0686430F8600320A870AD49E878F5F76E
+:10A16000E1FFCBE7AA480221017061680979002963
+:10A1700019D00021017161684979002915D00421A5
+:10A18000417161688968643181606168C968C160D2
+:10A19000C0689E4C14346060F5F7AAFB20606F70B5
+:10A1A0000220A870AAE70321E4E70321E8E70120E1
+:10A1B000C0E70320C4E7F8B5944C0D46E178884227
+:10A1C00000D0FFDF284600250126914F030000F054
+:10A1D00087FC09060E2E4C6C727DA282A200A0782C
+:10A1E000032803D0A078022800D0FFDFF8BDA078B4
+:10A1F000032803D0A078022800D0FFDF0420A0703D
+:10A200002571207800280FD1FFF713FF3878022836
+:10A2100006D0B868E06000F061F9206100204FE0EE
+:10A22000E078F5F7EDFDF5E700F01EF9F8BDA07850
+:10A23000032803D0A078022800D0FFDF2078002870
+:10A2400002D000F019F9F8BDA07803281AD1042033
+:10A2500027E0081AF8606E49E078F5F763FFF8BD6B
+:10A260000420F6F72EFFA570F8BDA078032803D0D0
+:10A27000A078022800D0FFDF20780028E1D1A07864
+:10A2800003280DD0F5F734FB604E014614363068D4
+:10A29000F6F762FC0028E3DB71688142E0DBD8E777
+:10A2A0000520F6F70EFFA670F8BDA078042800D0B0
+:10A2B000FFDF022004E0A078042800D0FFDF0120A7
+:10A2C000A1688847FFF7F4FE05462BE0A078042834
+:10A2D000AAD0FFDFA8E7A078042806D0607800287D
+:10A2E00002D0A078022800D0FFDF20780028A8D173
+:10A2F0002079002804D00620F6F7E3FE2571D2E786
+:10A300006078002805D04249E078F5F70BFF6570CA
+:10A31000F8BD0720C5E7FFDFF8BD002D07D0012DF0
+:10A3200003D0FFDF022DF8D1F8BD0420C8E70320D9
+:10A33000C6E770B5050005D0344CA078052803D0D9
+:10A34000112070BD102070BD3448F5F769FAE07037
+:10A35000E078002803D0A5600020A07070BD032025
+:10A3600070BD10B529480178002901D0112010BD19
+:10A37000817805290ED0817801290DD081780029B6
+:10A380000AD0012101708178012905D08078002848
+:10A3900002D003E00F2010BD00F06EF8002010BDC9
+:10A3A000F8B51A4E0446B078002801D001280DD126
+:10A3B000002C0DD02046FFF74EFE00280AD0207852
+:10A3C000134D002808D0B07801282DD00F20F8BDFB
+:10A3D0001020F8BD0720F8BD02272F702079002833
+:10A3E0001ED000202871607900281BD004206871DD
+:10A3F000A0686430A860E068E860E868034C143442
+:10A400006060F5F775FA2060B77023E07C010020EA
+:10A41000681100203D860100FF1FA107B7A10100C0
+:10A420000320DFE70320E2E70020287020790028DE
+:10A4300016D0002028716079002813D0042068719C
+:10A44000A168F068F5F7BEFCA860E0686430E860D9
+:10A450000320B0700F49F078F5F764FE0020F8BDD6
+:10A460000320E7E70320EAE710B50B48006900F096
+:10A470002EF8F5F776F910BD10B5074CE078F5F732
+:10A4800023FA0820F6F71DFE0520A070002020709A
+:10A49000607010BD681100207C010020144909681B
+:10A4A000014201D0012070470020704710494968DF
+:10A4B000014201D001207047002070470020704702
+:10A4C000002070470A4A1060516000207047094917
+:10A4D0008A6A094B1A4002438A627047054A916AA8
+:10A4E0000548054BC0430840194091627047000081
+:10A4F0000006004000050040FD7EFFFF70477047EA
+:10A5000070477047034610B50B439B070FD1042AD1
+:10A510000DD308C810C9121FA342F8D018BA21BA27
+:10A52000884201D9012010BD0020C04310BD002A7F
+:10A5300003D0D30703D0521C07E0002010BD0378DE
+:10A540000C78401C491C1B1B07D103780C78401C5D
+:10A55000491C1B1B01D1921EF1D1184610BDF8B544
+:10A56000042A2CD3830712D00B78491C0370401C9B
+:10A57000521E83070BD00B78491C0370401C521EDF
+:10A58000830704D00B78491C0370401C521E8B07B4
+:10A590009B0F05D0C91ADF002023DE1B08C90AE083
+:10A5A000E6F7F4FDF8BD1D4608C9FD401C46B44061
+:10A5B0002C4310C0121F042AF5D2F308C91A521EE8
+:10A5C000F0D40B78491C0370401C521EEAD40B785F
+:10A5D000491C0370401C012AE4D409780170F8BDBD
+:10A5E00001E004C0091F0429FBD28B0701D50280BA
+:10A5F000801CC90700D00270704700290BD0C30728
+:10A6000002D00270401C491E022904D3830702D5E0
+:10A610000280801C891EE3E70022EEE70022DFE7CC
+:10A620000378C2781946437812061B0219438378CF
+:10A63000C0781B04194311430902090A00060843A4
+:10A640007047020A08704A70020C8A70020ECA70C3
+:10A650007047002203098B4273D3030A8B4258D3FD
+:10A66000030B8B423CD3030C8B4221D312E00346F5
+:10A670000B437FD4002243088B4274D303098B42DF
+:10A680005FD3030A8B4244D3030B8B4228D3030CC2
+:10A690008B420DD3FF22090212BA030C8B4202D364
+:10A6A0001212090265D0030B8B4219D300E0090A8C
+:10A6B000C30B8B4201D3CB03C01A5241830B8B4295
+:10A6C00001D38B03C01A5241430B8B4201D34B037E
+:10A6D000C01A5241030B8B4201D30B03C01A5241E3
+:10A6E000C30A8B4201D3CB02C01A5241830A8B4268
+:10A6F00001D38B02C01A5241430A8B4201D34B0251
+:10A70000C01A5241030A8B4201D30B02C01A5241B4
+:10A71000CDD2C3098B4201D3CB01C01A5241830968
+:10A720008B4201D38B01C01A524143098B4201D3A2
+:10A730004B01C01A524103098B4201D30B01C01ACD
+:10A740005241C3088B4201D3CB00C01A5241830847
+:10A750008B4201D38B00C01A524143088B4201D374
+:10A760004B00C01A5241411A00D2014652411046D4
+:10A7700070475DE0CA0F00D04942031000D3404249
+:10A78000534000229C4603098B422DD3030A8B427F
+:10A7900012D3FC22890112BA030A8B420CD389011D
+:10A7A00092118B4208D3890192118B4204D3890103
+:10A7B0003AD0921100E08909C3098B4201D3CB0141
+:10A7C000C01A524183098B4201D38B01C01A5241F6
+:10A7D00043098B4201D34B01C01A524103098B42FA
+:10A7E00001D30B01C01A5241C3088B4201D3CB00E5
+:10A7F000C01A524183088B4201D38B00C01A5241C8
+:10A80000D9D243088B4201D34B00C01A5241411A9E
+:10A8100000D20146634652415B10104601D34042CC
+:10A82000002B00D54942704763465B1000D340427D
+:10A8300001B50020C046C04602BD70477047704752
+:10A8400010B500F05DF810BD30B58C180278401CD2
+:10A8500013071B0F01D10378401C120906D102789F
+:10A86000401C03E00578401C0D70491C5B1EF9D1AB
+:10A8700001E00B70491C521EFBD1A142E6D300201F
+:10A8800030BD0000154B1860154B1960154B1A6050
+:10A890007047FEDF04207146084218D10699124A1B
+:10A8A000914214DC069902394878DF280FD10878E4
+:10A8B000FE2806D0FF280AD10C480D4A0D4B1B6814
+:10A8C00018470D480099019A0A4B1B6818470698CB
+:10A8D00005990A4B1B68DB68184700009C010020A3
+:10A8E000A0010020A401002000B001000100000030
+:10A8F0000000000070010020011000000400002092
+:10A900001D481E497047FFF7FBFFE6F709FC00BD35
+:10A9100001200007C06AC0B2FF2804D118481949B5
+:10A920000968884202D01848184901601848194936
+:10A930000968884203D1184A13605B68184700BD54
+:10A9400020BFFDE712481349096888420ED1134B16
+:10A9500018680B498842F3D080F308881049884270
+:10A9600004DD1048026802210A4302600E48804755
+:10A970000E488047FFDF000078110020781100208A
+:10A98000FFFFFFFF001000102C0500400800000032
+:10A9900000100000000000200400002000B00100B2
+:10A9A0000020002024050040E52F000011A901002F
+:10A9B00004207146084202D0EFF3098101E0EFF371
+:10A9C0000881886902380078102813DB20280FDB03
+:10A9D0002B280BDB0A4A12680A4B9A4203D16028E3
+:10A9E00004DB094A1047022008607047074A1047F5
+:10A9F000074A1047074A12682C32126810470000B5
+:10AA000098000020BEBAFECAED1200000D930100AE
+:10AA1000619C0100040000200E4B0F4908470F4BBA
+:10AA20000D4908470E4B0C4908470E4B0A49084789
+:10AA30000D4B094908470D4B074908470C4B064980
+:10AA400008470C4B044908470B4B034908470B4B7D
+:10AA500001490847F9920000692F0000492F0000C2
+:10AA60007B8F0000298F0000D1940000F7120000B6
+:10AA70002F2F00003F900000C19500003111000011
+:10AA80000A7802704B7843708A788270CA78C270F4
+:10AA90000B79037170470A7802704B7843708A789B
+:10AAA0008270CA78C2700B7903714A79427170471B
+:10AAB0000A7802704B7843708A788270CA78C270C4
+:10AAC0000B7903714A7942718A798271CB79C371AA
+:10AAD00070470A8802804A8842800A79027170476A
+:10AAE00030B47446641E2578641CAB4200D21D4607
+:10AAF000635D5B00E31830BC18470000917D0000E7
+:10AB0000377F0000637D0000278000004D8000003B
+:10AB10008B800000C58000000181000037810000AB
+:10AB20008B8100002F1200002F1200002F12000056
+:10AB30002F1200002F1200002F12000049220000E7
+:10AB4000DB220000FB22000017240000AB1E0000E7
+:10AB50005D260000412700005D270000ED2C00006D
+:10AB6000112D0000472C0000972C0000432D000001
+:10AB7000CF2D0000D1420000C74400007F480000F4
+:10AB80008F490000174A0000C14A0000334B000003
+:10AB90004F4C0000314D0000BD4D000075270000F6
+:10ABA0007F2700008D270000731E00006D28000025
+:10ABB000451E0000C72900002F1200009F5600000C
+:10ABC000175700002F57000049570000B1580000E8
+:10ABD0006F57000081570000BF570000E357000087
+:10ABE0009B5800002F1200002F1200002F120000AF
+:10ABF0002F1200002F1200002F1200003F6F0000E4
+:10AC00005D6F0000656F0000B76F0000E76F000028
+:10AC1000D17000006971000085710000CD710000E5
+:10AC2000E9720000D77400000B760000CD600000D0
+:10AC30002F1200002F1200002F1200005F8B000067
+:10AC40009D8B0000BF8B0000100110013A02000034
+:10AC50001A020000717600001B790000FFFFFFFF61
+:10AC60000000FFFF41870000811B0000E753000048
+:10AC700021610000BB7800000000000023002300D9
+:10AC800046004D0023002300F500000000000000F6
+:10AC900000000000E5BB0000000000000000000014
+:10ACA0000000000069C90000000000000000000072
+:10ACB0000000000051BC0000DBBC000000000000F0
+:10ACC000000000000FC000008BBD000097C2000014
+:10ACD0000000000000000000FFCD000000000000A8
+:10ACE0000000000000000000D9C0000031CA0000D0
+:10ACF0000000000017CB00008BCB0000000000001C
+:10AD00002BC300000DC400000000000051CB000068
+:10AD100073C400001BC7000083C700005BC80000AD
+:10AD20002FC20000EFC800000000000059C1000061
+:10AD30000000000083BE0000FFBD00009FC90000AE
+:10AD4000CFCC00003DCD00000000000091C000000D
+:10AD50002DBE000041C0000045CF0000D5BF00005F
+:10AD600051CE000000000000ABCD000053BD00003C
+:10AD700087BC0000D9BE0000CFBD0000C3CE0000DC
+:10AD8000EFCF000035C10000A7CF0000DD38000084
+:10AD9000DD38000025220000AF8600009D63000022
+:10ADA000B1530000000000003B690100233900009E
+:10ADB0002339000047220000038700000D640000D3
+:10ADC000BF530000E365010061690100BC01BC01E3
+:10ADD0003E002C0044000E00D800200101000000BD
+:10ADE0000100000000010203040010111213000012
+:10ADF00000140000A38B0100D9900100A191010073
+:10AE0000F591010045920100A1920100F98B01002A
+:10AE10000F8D0100758D0100818F01005F90010091
+:10AE2000A9DF000097F00000AD54010029470100A0
+:10AE3000CD5401002B470100132C0100777C010049
+:10AE40006D3B0100777C01007D2C0100D17D01006C
+:10AE50001F350100D17D01008D2B01006D7D0100AA
+:10AE6000A53A01006D7D0100555555D6BE898E006D
+:10AE700000007006120DB413000014035A06A00956
+:10AE800000006004F208840D555555252627D6BECE
+:10AE9000898EF401FA00960064004B0032001E0017
+:10AEA000140000000300656C7462000000000000E4
+:10AEB000000000000000000000008700000000000B
+:10AEC00000000000000000000000BE83605ADB0BA1
+:10AED000376038A5F5AA9183886C0000619901005C
+:10AEE000799901008F990100A5990100CF9901007E
+:10AEF000F9990100239A0100539A01000997010072
+:10AF00005596010077970100D1970100E197010064
+:10AF100011980100BD9D0100019E0100339E0100BA
+:10AF20005D9E01007D9E01009F9E0100FF9E01002D
+:10AF30001F9F01002F9F01006D9F01009F120100C4
+:10AF4000A7120100B51201003F98010059980100B5
+:10AF50002D98010037980100659801009198010033
+:10AF6000CB980100D7980100E3980100ED9801000B
+:10AF7000F9980100059901000F99010000000000F7
+:10AF8000E79000004191000059910000C19F01002D
+:10AF9000639301000994010033A3010063A301003E
+:10AFA000A1A3010071100100FF14010000100200B4
+:10AFB000D0AF010008000020A001000048A8010057
+:10AFC000F4AF0100A8010020D00F00000411000020
+:10AFD00001593601000100683720FB349B5F800473
+:10AFE0001F800010022001337F0102E429E485A8BC
+:04AFF000010000005C
+:00000001FF
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PeripheralNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PeripheralNames.h
new file mode 100644
index 0000000000..0fe6da592e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PeripheralNames.h
@@ -0,0 +1,81 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STDIO_UART_TX     TX_PIN_NUMBER
+#define STDIO_UART_RX     RX_PIN_NUMBER
+#define STDIO_UART        UART_0
+
+typedef enum {
+    UART_0 = (int)NRF_UART0_BASE
+} UARTName;
+
+
+typedef enum {
+    SPI_0 = (int)NRF_SPI0_BASE,
+    SPI_1 = (int)NRF_SPI1_BASE,
+    SPIS = (int)NRF_SPIS1_BASE
+} SPIName;
+
+typedef enum {
+    PWM_1 = 0,
+    PWM_2
+} PWMName;
+
+typedef enum {
+    I2C_0 = (int)NRF_TWI0_BASE,
+    I2C_1 = (int)NRF_TWI1_BASE
+} I2CName;
+
+typedef enum {
+    ADC0_0 = (int)0
+} ADCName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PortNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PortNames.h
new file mode 100644
index 0000000000..c63624639b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/PortNames.h
@@ -0,0 +1,53 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    Port0 = 0 //GPIO pins 0-31
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h
new file mode 100644
index 0000000000..0ce5babca4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/PinNames.h
@@ -0,0 +1,202 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT  3
+
+typedef enum {
+    p0  = 0,
+    p1  = 1,
+    p2  = 2,
+    p3  = 3,
+    p4  = 4,
+    p5  = 5,
+    p6  = 6,
+    p7  = 7,
+    p8  = 8,
+    p9  = 9,
+    p10 = 10,
+    p11 = 11,
+    p12 = 12,
+    p13 = 13,
+    p14 = 14,
+    p15 = 15,
+    p16 = 16,
+    p17 = 17,
+    p18 = 18,
+    p19 = 19,
+    p20 = 20,
+    p21 = 21,
+    p22 = 22,
+    p23 = 23,
+    p24 = 24,
+    p25 = 25,
+    p26 = 26,
+    p27 = 27,
+    p28 = 28,
+    p29 = 29,
+    p30 = 30,
+    p31 = 31,
+
+    P0_0  = p0,
+    P0_1  = p1,
+    P0_2  = p2,
+    P0_3  = p3,
+    P0_4  = p4,
+    P0_5  = p5,
+    P0_6  = p6,
+    P0_7  = p7,
+
+    P0_8  = p8,
+    P0_9  = p9,
+    P0_10 = p10,
+    P0_11 = p11,
+    P0_12 = p12,
+    P0_13 = p13,
+    P0_14 = p14,
+    P0_15 = p15,
+
+    P0_16 = p16,
+    P0_17 = p17,
+    P0_18 = p18,
+    P0_19 = p19,
+    P0_20 = p20,
+    P0_21 = p21,
+    P0_22 = p22,
+    P0_23 = p23,
+
+    P0_24 = p24,
+    P0_25 = p25,
+    P0_26 = p26,
+    P0_27 = p27,
+    P0_28 = p28,
+    P0_29 = p29,
+    P0_30 = p30,
+
+    LED1    = p17,
+    LED2    = p18,
+    LED3    = p19,
+    LED4    = p20,
+
+    BUTTON1 = p13,
+    BUTTON2 = p14,
+    BUTTON3 = p15,
+    BUTTON4 = p16,
+
+    RX_PIN_NUMBER  = p8,
+    TX_PIN_NUMBER  = p6,
+    CTS_PIN_NUMBER = p7,
+    RTS_PIN_NUMBER = p5,
+
+    // mBed interface Pins
+    USBTX = TX_PIN_NUMBER,
+    USBRX = RX_PIN_NUMBER,
+
+    SPI_PSELMOSI0 = p23,
+    SPI_PSELMISO0 = p24,
+    SPI_PSELSS0   = p22,
+    SPI_PSELSCK0  = p25,
+
+    SPI_PSELMOSI1 = p12,
+    SPI_PSELMISO1 = p13,
+    SPI_PSELSS1   = p11,
+    SPI_PSELSCK1  = p14,
+
+    SPIS_PSELMOSI = p12,
+    SPIS_PSELMISO = p13,
+    SPIS_PSELSS   = p11,
+    SPIS_PSELSCK  = p14,
+
+    I2C_SDA0 = p26,
+    I2C_SCL0 = p27,
+
+    D0 = p11,
+    D1 = p12,
+    D2 = p13,
+    D3 = p14,
+    D4 = p15,
+    D5 = p16,
+    D6 = p17,
+    D7 = p18,
+
+    D8 = p19,
+    D9 = p20,
+    D10 = p22,
+    D11 = p23,
+    D12 = p24,
+    D13 = p25,
+
+    D14 = p26,
+    D15 = p27,
+
+    A0 = p3,
+    A1 = p4,
+    A2 = p28,
+    A3 = p29,
+    A4 = p30,
+    A5 = p31,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone = 0,
+    PullDown = 1,
+    PullUp = 3,
+    PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/device.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/device.h
new file mode 100644
index 0000000000..2427e752ea
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_NRF52_DK/device.h
@@ -0,0 +1,38 @@
+// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
+// Check the 'features' section of the target description in 'targets.json' for more details.
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+#include "objects.h"
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c
new file mode 100644
index 0000000000..c527261e86
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/analogin_api.c
@@ -0,0 +1,87 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+ 
+#include "mbed_assert.h"
+#include "analogin_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "app_util_platform.h"
+#include "nrf_drv_saadc.h"
+
+#ifdef DEVICE_ANALOGIN
+
+#define ADC_12BIT_RANGE 0xFFF
+#define ADC_RANGE       ADC_12BIT_RANGE
+
+static void analog_in_event_handler(nrf_drv_saadc_evt_t const *p_event)// type of nrf_drv_saadc_event_handler_t 
+{
+    (void) p_event;
+}
+
+static const nrf_drv_saadc_config_t saadc_config = 
+{
+    .resolution         = NRF_SAADC_RESOLUTION_12BIT,
+    .oversample         = NRF_SAADC_OVERSAMPLE_DISABLED,
+    .interrupt_priority = APP_IRQ_PRIORITY_LOW
+};
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    ret_code_t ret_code;
+    
+    ret_code = nrf_drv_saadc_init(&saadc_config, analog_in_event_handler);
+    MBED_ASSERT(((ret_code == NRF_SUCCESS) || (ret_code == NRF_ERROR_INVALID_STATE))); //NRF_ERROR_INVALID_STATE expected for multiple channels used.
+    
+    uint8_t saadcIn = nrf_drv_saadc_gpio_to_ain(pin);
+    MBED_ASSERT(saadcIn != NRF_SAADC_INPUT_DISABLED);
+    
+    obj->adc     = ADC0_0; // only one instance of ADC in nRF52 SoC
+    obj->adc_pin = saadcIn  - 1;
+    
+    nrf_saadc_channel_config_t channel_config =
+            NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(saadcIn); //Single ended, negative input to ADC shorted to GND.
+    
+    ret_code = nrf_drv_saadc_channel_init(obj->adc_pin, &channel_config);
+    MBED_ASSERT(ret_code == NRF_SUCCESS);
+}
+
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    int16_t    adc_value;
+    ret_code_t ret_code;
+    
+    ret_code = nrf_drv_saadc_sample_convert(obj->adc_pin, &adc_value);
+    MBED_ASSERT(ret_code == NRF_SUCCESS);
+    
+    if (adc_value < 0)
+    {
+        // Even in the single ended mode measured value can be {-0}. Saturation for avoid casting to a big integer.
+        return 0;
+    }
+    else
+    {
+        return (uint16_t) adc_value;
+    }
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = analogin_read_u16(obj);
+    return (float)value * (1.0f / (float)ADC_RANGE);
+}
+
+#endif // DEVICE_ANALOGIN
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c
new file mode 100644
index 0000000000..43cb0cad2d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/pwmout_api.c
@@ -0,0 +1,376 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pwmout_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+
+#if DEVICE_PWMOUT
+
+#include "app_util_platform.h"
+#include "nrf_drv_pwm.h"
+
+#define MAX_PWM_COUNTERTOP  (0x7FFF)                 // 0x7FFF is the max of COUNTERTOP value for the PWM peripherial of the nRF52.
+#define MAX_PWM_PERIOD_US   (MAX_PWM_COUNTERTOP * 8) // PWM hw is driven by 16 MHz clock, hence the tick is 1_us/16,
+                                                     // and 128 is the max prescaler value.
+#define MAX_PWM_PERIOD_MS   ((MAX_PWM_PERIOD_US / 1000) + 1)    // approximations advance
+#define MAX_PWM_PERIOD_S    ((MAX_PWM_PERIOD_US / 1000000) + 1) // approximations advance
+
+
+#define PWM_INSTANCE_COUNT  (PWM_COUNT) // import from the nrf_drv_config.h file
+
+///> instances of nRF52 PWM driver
+static const nrf_drv_pwm_t m_pwm_driver[PWM_INSTANCE_COUNT] =
+{
+#if PWM0_ENABLED
+    NRF_DRV_PWM_INSTANCE(0),
+#endif
+#if PWM1_ENABLED
+    NRF_DRV_PWM_INSTANCE(1),
+#endif
+#if PWM2_ENABLED
+    NRF_DRV_PWM_INSTANCE(2)
+#endif
+};
+
+typedef struct
+{
+    uint32_t period_us;
+    uint32_t duty_us;
+    float    duty;
+} pwm_signal_t; /// PWM signal description type
+
+typedef struct
+{
+    nrf_drv_pwm_t * p_pwm_driver;
+    pwm_signal_t signal;
+    volatile nrf_pwm_values_common_t seq_values[1];
+} pwm_t; /// internal PWM instance support type
+
+static pwm_t m_pwm[PWM_INSTANCE_COUNT] =
+{
+#if PWM0_ENABLED
+    {.p_pwm_driver = NULL},
+#endif
+#if PWM1_ENABLED
+    {.p_pwm_driver = NULL},
+#endif
+#if PWM2_ENABLED
+    {.p_pwm_driver = NULL}
+#endif
+};  /// Array of internal PWM instances.
+
+typedef struct
+{
+    uint16_t       period_hwu; // unit related to pwm_clk
+    uint16_t       duty_hwu;   // unit related to pwm_clk
+    nrf_pwm_clk_t  pwm_clk;
+} pulsewidth_set_t; /// helper type for timing calculations
+    
+    
+static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization);
+    
+void pwmout_init(pwmout_t *obj, PinName pin)
+{
+    uint32_t i;
+    
+    for (i = 0; PWM_INSTANCE_COUNT; i++)
+    {
+        if (m_pwm[i].p_pwm_driver == NULL) // a driver instance not assigned to the obj?
+        {
+            obj->pin         = pin;
+            
+            obj->pwm_channel = i;
+            
+            m_pwm[i].p_pwm_driver = (nrf_drv_pwm_t *) &m_pwm_driver[i];
+            m_pwm[i].signal.period_us = 200000; // 0.02 s
+            m_pwm[i].signal.duty_us   = 100000;
+            m_pwm[i].signal.duty      = 0.5f;
+            
+            obj->pwm_struct  = &m_pwm[i];
+
+            internal_pwmout_exe(obj, true, true);
+
+            break;
+        }
+    }
+    
+    MBED_ASSERT(i != PWM_INSTANCE_COUNT); // assert if free instance was not found.
+}
+
+void pwmout_free(pwmout_t *obj)
+{
+    nrf_drv_pwm_uninit( (nrf_drv_pwm_t*) obj->pwm_struct );
+
+    m_pwm[obj->pwm_channel].p_pwm_driver = NULL;
+}
+
+void pwmout_write(pwmout_t *obj, float percent)
+{
+    
+    if (percent < 0)
+    {
+        percent = 0;
+    }
+    else if (percent > 1)
+    {
+        percent = 1;
+    }
+    
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    p_pwm_signal->duty = percent;
+    
+    int us  = (((int)p_pwm_signal->period_us) * percent);
+    
+    pwmout_pulsewidth_us(obj, us);
+}
+
+float pwmout_read(pwmout_t *obj)
+{
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    return (float)p_pwm_signal->duty_us / (float)p_pwm_signal->period_us;
+}
+
+void pwmout_period(pwmout_t *obj, float seconds)
+{
+    // raught saturation < 0, quasi-max>
+    if (seconds > MAX_PWM_PERIOD_S)
+    {
+        seconds = MAX_PWM_PERIOD_S;
+    }
+    else if (seconds < 0)
+    {
+        seconds = 0; // f. pwmout_period_us will set period to min. value
+    }
+    
+    int us = seconds * 1000000;
+    
+    pwmout_period_us(obj, us);
+}
+
+void pwmout_period_ms(pwmout_t *obj, int ms)
+{
+    // reught saturation < 0, quasi-max>
+    if (ms > MAX_PWM_PERIOD_MS)
+    {
+        ms = MAX_PWM_PERIOD_MS;
+    }
+    else if (ms < 0)
+    {
+        ms = 0; // f. pwmout_period_us will set period to min. value
+    }
+    
+    int us = ms * 1000;
+    
+    pwmout_period_us(obj, us);
+}
+
+
+void pwmout_period_us(pwmout_t *obj, int us)
+{
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    // saturation <1, real-max>
+    if (us > MAX_PWM_PERIOD_US)
+    {
+        us = MAX_PWM_PERIOD_US;
+    }
+    else if (us < 1)
+    {
+        us = 1;
+    }
+    
+    p_pwm_signal->duty_us = (int)((float)us * p_pwm_signal->duty);
+    
+    p_pwm_signal->period_us  = us;
+    
+    internal_pwmout_exe(obj, true, false);
+}
+
+void pwmout_pulsewidth(pwmout_t *obj, float seconds)
+{
+    // raught saturation < 0, quasi-max>
+    if (seconds > MAX_PWM_PERIOD_S)
+    {
+        seconds = MAX_PWM_PERIOD_S;
+    }
+    else if (seconds < 0)
+    {
+        seconds = 0;
+    }
+    
+    int us = seconds * 1000000;
+    
+    pwmout_pulsewidth_us(obj,us);
+}
+
+void pwmout_pulsewidth_ms(pwmout_t *obj, int ms)
+{
+    // raught saturation < 0, quasi-max>
+    if (ms > MAX_PWM_PERIOD_MS)
+    {
+        ms = MAX_PWM_PERIOD_MS;
+    }
+    else if (ms < 0)
+    {
+        ms = 0;
+    }
+    
+    int us = ms * 1000;
+    
+    pwmout_pulsewidth_us(obj, us);
+}
+
+void pwmout_pulsewidth_us(pwmout_t *obj, int us)
+{
+    // saturation <0, real-max>
+    if (us > MAX_PWM_PERIOD_US)
+    {
+        us = MAX_PWM_PERIOD_US;
+    }
+    else if (us < 0)
+    {
+        us = 0;
+    }
+    
+    pwm_signal_t * p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    p_pwm_signal->duty_us  = us;
+    p_pwm_signal->duty     = us / p_pwm_signal->period_us;
+    
+    internal_pwmout_exe(obj, false, false);
+}
+
+
+
+
+
+
+static ret_code_t pulsewidth_us_set_get(int period_hwu, int duty_hwu, pulsewidth_set_t * p_settings)
+{
+    uint16_t      div;
+    nrf_pwm_clk_t pwm_clk = NRF_PWM_CLK_16MHz;
+    
+    for(div = 1; div <= 128 ; div <<= 1) // 128 is the maximum of clock prescaler for PWM peripherial
+    {
+        if (MAX_PWM_COUNTERTOP >= period_hwu)
+        {
+            p_settings->period_hwu  = period_hwu; // unit [us/16 * div]
+            p_settings->duty_hwu = duty_hwu;       // unit [us/16 * div]
+            p_settings->pwm_clk   = pwm_clk;
+    
+            return NRF_SUCCESS;
+        }
+        
+        period_hwu >>= 1;
+        duty_hwu >>= 1;
+        pwm_clk++;
+    }
+    
+    return NRF_ERROR_INVALID_PARAM;
+}
+
+
+static void internal_pwmout_exe(pwmout_t *obj, bool new_period, bool initialization)
+{
+    pulsewidth_set_t          pulsewidth_set;
+    pwm_signal_t            * p_pwm_signal;
+    nrf_drv_pwm_t           * p_pwm_driver;
+    ret_code_t                ret_code;
+    
+    p_pwm_signal = &(((pwm_t*)obj->pwm_struct)->signal);
+    
+    if (NRF_SUCCESS == pulsewidth_us_set_get(p_pwm_signal->period_us * 16, // base clk for PWM is 16 MHz
+                                             p_pwm_signal->duty_us * 16,   // base clk for PWM is 16 MHz
+                                             &pulsewidth_set))
+    {
+        p_pwm_driver = (((pwm_t*)obj->pwm_struct)->p_pwm_driver);
+        
+        const nrf_pwm_sequence_t seq =
+        {
+            .values.p_common = (nrf_pwm_values_common_t*) (((pwm_t*)obj->pwm_struct)->seq_values),
+            .length          = 1,
+            .repeats         = 0,
+            .end_delay       = 0
+        };
+        
+        (((pwm_t*)obj->pwm_struct)->seq_values)[0] = pulsewidth_set.duty_hwu | 0x8000;
+        
+        if (new_period)
+        {
+            nrf_drv_pwm_config_t config0 =
+            {
+                .output_pins =
+                {
+                    obj->pin | NRF_DRV_PWM_PIN_INVERTED, // channel 0
+                    NRF_DRV_PWM_PIN_NOT_USED,            // channel 1
+                    NRF_DRV_PWM_PIN_NOT_USED,            // channel 2
+                    NRF_DRV_PWM_PIN_NOT_USED,            // channel 3
+                },
+                .irq_priority = APP_IRQ_PRIORITY_LOW,
+                .base_clock   = pulsewidth_set.pwm_clk,
+                .count_mode   = NRF_PWM_MODE_UP,
+                .top_value    = pulsewidth_set.period_hwu,
+                .load_mode    = NRF_PWM_LOAD_COMMON,
+                .step_mode    = NRF_PWM_STEP_AUTO
+            };
+            
+            if (!initialization)
+            {
+                nrf_drv_pwm_uninit(p_pwm_driver);
+            }
+        
+            ret_code = nrf_drv_pwm_init( p_pwm_driver, &config0, NULL);
+        
+            MBED_ASSERT(ret_code == NRF_SUCCESS); // assert if free instance was not found.
+        }
+
+        nrf_drv_pwm_simple_playback(p_pwm_driver, &seq, 0, NRF_DRV_PWM_FLAG_LOOP);
+    }
+    else
+    {
+        MBED_ASSERT(0); // force assertion
+    }
+    
+}
+
+#endif // DEVICE_PWMOUT
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/pwm/nrf_drv_pwm.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/pwm/nrf_drv_pwm.c
new file mode 100644
index 0000000000..df4ec49659
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/pwm/nrf_drv_pwm.c
@@ -0,0 +1,350 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#include <string.h>
+#include "nrf_drv_pwm.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "app_util_platform.h"
+
+#if (PWM_COUNT == 0)
+    #error "No PWM instances enabled in the driver configuration file."
+#endif
+
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_pwm_handler_t    handler;
+    nrf_drv_state_t volatile state;
+} pwm_control_block_t;
+static pwm_control_block_t m_cb[PWM_COUNT];
+
+static nrf_drv_pwm_config_t const m_default_config[PWM_COUNT] = {
+#if PWM0_ENABLED
+    NRF_DRV_PWM_DEFAULT_CONFIG(0),
+#endif
+#if PWM1_ENABLED
+    NRF_DRV_PWM_DEFAULT_CONFIG(1),
+#endif
+#if PWM2_ENABLED
+    NRF_DRV_PWM_DEFAULT_CONFIG(2),
+#endif
+};
+
+
+static void configure_pins(nrf_drv_pwm_t const * const p_instance,
+                           nrf_drv_pwm_config_t const * p_config)
+{
+    uint32_t out_pins[NRF_PWM_CHANNEL_COUNT];
+    uint8_t i;
+
+    for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
+    {
+        uint8_t output_pin = p_config->output_pins[i];
+        if (output_pin != NRF_DRV_PWM_PIN_NOT_USED)
+        {
+            bool inverted = output_pin &  NRF_DRV_PWM_PIN_INVERTED;
+            out_pins[i]   = output_pin & ~NRF_DRV_PWM_PIN_INVERTED;
+
+            if (inverted)
+            {
+                nrf_gpio_pin_set(out_pins[i]);
+            }
+            else
+            {
+                nrf_gpio_pin_clear(out_pins[i]);
+            }
+
+            nrf_gpio_cfg_output(out_pins[i]);
+        }
+        else
+        {
+            out_pins[i] = NRF_PWM_PIN_NOT_CONNECTED;
+        }
+    }
+
+    nrf_pwm_pins_set(p_instance->p_registers, out_pins);
+}
+
+
+ret_code_t nrf_drv_pwm_init(nrf_drv_pwm_t const * const p_instance,
+                            nrf_drv_pwm_config_t const * p_config,
+                            nrf_drv_pwm_handler_t        handler)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config[p_instance->drv_inst_idx];
+    }
+
+    p_cb->handler = handler;
+
+    configure_pins(p_instance, p_config);
+
+    nrf_pwm_enable(p_instance->p_registers);
+    nrf_pwm_configure(p_instance->p_registers,
+        p_config->base_clock, p_config->count_mode, p_config->top_value);
+    nrf_pwm_decoder_set(p_instance->p_registers,
+        p_config->load_mode, p_config->step_mode);
+
+    nrf_pwm_shorts_set(p_instance->p_registers, 0);
+    nrf_pwm_int_set(p_instance->p_registers, 0);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_LOOPSDONE);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND0);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_SEQEND1);
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED);
+
+    if (p_cb->handler)
+    {
+        nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_registers),
+            p_config->irq_priority);
+    }
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+
+void nrf_drv_pwm_uninit(nrf_drv_pwm_t const * const p_instance)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_registers));
+
+    nrf_pwm_disable(p_instance->p_registers);
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+
+static void start_playback(nrf_drv_pwm_t const * const p_instance,
+                           pwm_control_block_t * p_cb,
+                           uint8_t               flags,
+                           nrf_pwm_task_t        starting_task)
+{
+    p_cb->state = NRF_DRV_STATE_POWERED_ON;
+
+    if (p_cb->handler)
+    {
+        // The notification about finished playback is by default enabled, but
+        // this can be suppressed. The notification that the peripheral has been
+        // stopped is always enable.
+        uint32_t int_mask = NRF_PWM_INT_LOOPSDONE_MASK |
+                            NRF_PWM_INT_STOPPED_MASK;
+
+        if (flags & NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0)
+        {
+            int_mask |= NRF_PWM_INT_SEQEND0_MASK;
+        }
+        if (flags & NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1)
+        {
+            int_mask |= NRF_PWM_INT_SEQEND1_MASK;
+        }
+        if (flags & NRF_DRV_PWM_FLAG_NO_EVT_FINISHED)
+        {
+            int_mask &= ~NRF_PWM_INT_LOOPSDONE_MASK;
+        }
+
+        nrf_pwm_int_set(p_instance->p_registers, int_mask);
+    }
+
+    nrf_pwm_event_clear(p_instance->p_registers, NRF_PWM_EVENT_STOPPED);
+
+    nrf_pwm_task_trigger(p_instance->p_registers, starting_task);
+}
+
+
+void nrf_drv_pwm_simple_playback(nrf_drv_pwm_t const * const p_instance,
+                                 nrf_pwm_sequence_t const * p_sequence,
+                                 uint16_t                   playback_count,
+                                 uint32_t                   flags)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(playback_count > 0);
+    ASSERT(nrf_drv_is_in_RAM(p_sequence->values.p_raw));
+
+    // To take advantage of the looping mechanism, we need to use both sequences
+    // (single sequence can be played back only once).
+    nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence);
+    nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence);
+    bool odd = (playback_count & 1);
+    nrf_pwm_loop_set(p_instance->p_registers, playback_count/2 + (odd ? 1 : 0));
+
+    uint32_t shorts_mask;
+    if (flags & NRF_DRV_PWM_FLAG_STOP)
+    {
+        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
+    }
+    else if (flags & NRF_DRV_PWM_FLAG_LOOP)
+    {
+        shorts_mask = odd ? NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK
+                          : NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
+    }
+    else
+    {
+        shorts_mask = 0;
+    }
+    nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
+
+    start_playback(p_instance, p_cb, flags, odd ? NRF_PWM_TASK_SEQSTART1
+                                                : NRF_PWM_TASK_SEQSTART0);
+}
+
+
+void nrf_drv_pwm_complex_playback(nrf_drv_pwm_t const * const p_instance,
+                                  nrf_pwm_sequence_t const * p_sequence_0,
+                                  nrf_pwm_sequence_t const * p_sequence_1,
+                                  uint16_t                   playback_count,
+                                  uint32_t                   flags)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(playback_count > 0);
+    ASSERT(nrf_drv_is_in_RAM(p_sequence_0->values.p_raw));
+    ASSERT(nrf_drv_is_in_RAM(p_sequence_1->values.p_raw));
+
+    nrf_pwm_sequence_set(p_instance->p_registers, 0, p_sequence_0);
+    nrf_pwm_sequence_set(p_instance->p_registers, 1, p_sequence_1);
+    nrf_pwm_loop_set(p_instance->p_registers, playback_count);
+
+    uint32_t shorts_mask;
+    if (flags & NRF_DRV_PWM_FLAG_STOP)
+    {
+        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_STOP_MASK;
+    }
+    else if (flags & NRF_DRV_PWM_FLAG_LOOP)
+    {
+        shorts_mask = NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK;
+    }
+    else
+    {
+        shorts_mask = 0;
+    }
+    nrf_pwm_shorts_set(p_instance->p_registers, shorts_mask);
+
+    start_playback(p_instance, p_cb, flags, NRF_PWM_TASK_SEQSTART0);
+}
+
+
+bool nrf_drv_pwm_stop(nrf_drv_pwm_t const * const p_instance,
+                      bool wait_until_stopped)
+{
+    ASSERT(m_cb[p_instance->drv_inst_idx].state != NRF_DRV_STATE_UNINITIALIZED);
+
+    if (nrf_drv_pwm_is_stopped(p_instance))
+    {
+        return true;
+    }
+
+    nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_STOP);
+
+    do {
+        if (nrf_drv_pwm_is_stopped(p_instance))
+        {
+            return true;
+        }
+    } while (wait_until_stopped);
+
+    return false;
+}
+
+
+bool nrf_drv_pwm_is_stopped(nrf_drv_pwm_t const * const p_instance)
+{
+    pwm_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    // If the event handler is used (interrupts are enabled), the state will
+    // be changed in interrupt handler when the STOPPED event occurs.
+    if (p_cb->state != NRF_DRV_STATE_POWERED_ON)
+    {
+        return true;
+    }
+    // If interrupts are disabled, we must check the STOPPED event here.
+    if (nrf_pwm_event_check(p_instance->p_registers, NRF_PWM_EVENT_STOPPED))
+    {
+        p_cb->state = NRF_DRV_STATE_INITIALIZED;
+        return true;
+    }
+
+    return false;
+}
+
+
+static void irq_handler(NRF_PWM_Type * p_pwm, pwm_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    // The SEQEND0 and SEQEND1 events are only handled when the user asked for
+    // it (by setting proper flags when starting the playback).
+    if (nrf_pwm_int_enable_check(p_pwm, NRF_PWM_INT_SEQEND0_MASK) &&
+        nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND0))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND0);
+        p_cb->handler(NRF_DRV_PWM_EVT_END_SEQ0);
+    }
+    if (nrf_pwm_int_enable_check(p_pwm, NRF_PWM_INT_SEQEND1_MASK) &&
+        nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_SEQEND1))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_SEQEND1);
+        p_cb->handler(NRF_DRV_PWM_EVT_END_SEQ1);
+    }
+
+    // The LOOPSDONE event is handled by default, but this can be disabled.
+    if (nrf_pwm_int_enable_check(p_pwm, NRF_PWM_INT_LOOPSDONE_MASK) &&
+        nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_LOOPSDONE))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_LOOPSDONE);
+        p_cb->handler(NRF_DRV_PWM_EVT_FINISHED);
+    }
+
+    if (nrf_pwm_event_check(p_pwm, NRF_PWM_EVENT_STOPPED))
+    {
+        nrf_pwm_event_clear(p_pwm, NRF_PWM_EVENT_STOPPED);
+
+        p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+        p_cb->handler(NRF_DRV_PWM_EVT_STOPPED);
+    }
+}
+
+
+#if PWM0_ENABLED
+void PWM0_IRQHandler(void)
+{
+    irq_handler(NRF_PWM0, &m_cb[PWM0_INSTANCE_INDEX]);
+}
+#endif
+
+#if PWM1_ENABLED
+void PWM1_IRQHandler(void)
+{
+    irq_handler(NRF_PWM1, &m_cb[PWM1_INSTANCE_INDEX]);
+}
+#endif
+
+#if PWM2_ENABLED
+void PWM2_IRQHandler(void)
+{
+    irq_handler(NRF_PWM2, &m_cb[PWM2_INSTANCE_INDEX]);
+}
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/pwm/nrf_drv_pwm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/pwm/nrf_drv_pwm.h
new file mode 100644
index 0000000000..f8b1c1bc97
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/pwm/nrf_drv_pwm.h
@@ -0,0 +1,426 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**@file
+ * @addtogroup nrf_pwm PWM HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      @tagAPI52 Pulse Width Modulation (PWM) module APIs.
+ *
+ * @defgroup   nrf_drv_pwm PWM driver
+ * @{
+ * @ingroup    nrf_pwm
+ * @brief      @tagAPI52 Pulse Width Modulation (PWM) module driver.
+ */
+
+
+#ifndef NRF_DRV_PWM_H__
+#define NRF_DRV_PWM_H__
+
+#include "nordic_common.h"
+#include "nrf_drv_config.h"
+#include "nrf_pwm.h"
+#include "sdk_errors.h"
+
+
+/**
+ * @brief PWM driver instance data structure.
+ */
+typedef struct
+{
+    NRF_PWM_Type * p_registers;  ///< Pointer to the structure with PWM peripheral instance registers.
+    uint8_t        drv_inst_idx; ///< Driver instance index.
+} nrf_drv_pwm_t;
+
+/**
+ * @brief Macro for creating a PWM driver instance.
+ */
+#define NRF_DRV_PWM_INSTANCE(id)                        \
+{                                                       \
+    .p_registers  = CONCAT_2(NRF_PWM, id),              \
+    .drv_inst_idx = CONCAT_3(PWM, id, _INSTANCE_INDEX), \
+}
+
+
+/**
+ * @brief This value can be provided instead of a pin number for any channel
+ *        to specify that its output is not used and therefore does not need
+ *        to be connected to a pin.
+ */
+#define NRF_DRV_PWM_PIN_NOT_USED    0xFF
+
+/**
+ * @brief This value can be added to a pin number to inverse its polarity 
+ *        (set idle state = 1).
+ */
+#define NRF_DRV_PWM_PIN_INVERTED    0x80
+
+/**
+ * @brief PWM driver configuration structure.
+ */
+typedef struct
+{
+    uint8_t output_pins[NRF_PWM_CHANNEL_COUNT]; ///< Pin numbers for individual output channels (optional). 
+                                                /**< Use @ref NRF_DRV_PWM_PIN_NOT_USED
+                                                 *   if a given output channel is not needed. */
+    uint8_t            irq_priority; ///< Interrupt priority.
+    nrf_pwm_clk_t      base_clock;   ///< Base clock frequency.
+    nrf_pwm_mode_t     count_mode;   ///< Operating mode of the pulse generator counter.
+    uint16_t           top_value;    ///< Value up to which the pulse generator counter counts.
+    nrf_pwm_dec_load_t load_mode;    ///< Mode of loading sequence data from RAM.
+    nrf_pwm_dec_step_t step_mode;    ///< Mode of advancing the active sequence.
+} nrf_drv_pwm_config_t;
+
+/**
+ * @brief PWM driver default configuration.
+ */
+#define NRF_DRV_PWM_DEFAULT_CONFIG(id)                       \
+{                                                            \
+    .output_pins  = { CONCAT_3(PWM, id, _CONFIG_OUT0_PIN),   \
+                      CONCAT_3(PWM, id, _CONFIG_OUT1_PIN),   \
+                      CONCAT_3(PWM, id, _CONFIG_OUT2_PIN),   \
+                      CONCAT_3(PWM, id, _CONFIG_OUT3_PIN) }, \
+    .irq_priority = CONCAT_3(PWM, id, _CONFIG_IRQ_PRIORITY), \
+    .base_clock   = CONCAT_3(PWM, id, _CONFIG_BASE_CLOCK),   \
+    .count_mode   = CONCAT_3(PWM, id, _CONFIG_COUNT_MODE),   \
+    .top_value    = CONCAT_3(PWM, id, _CONFIG_TOP_VALUE),    \
+    .load_mode    = CONCAT_3(PWM, id, _CONFIG_LOAD_MODE),    \
+    .step_mode    = CONCAT_3(PWM, id, _CONFIG_STEP_MODE),    \
+}
+
+
+/**
+ * @brief PWM flags providing additional playback options.
+ */
+typedef enum
+{
+    NRF_DRV_PWM_FLAG_STOP = 0x01, /**< When the requested playback is finished,
+                                       the peripheral should be stopped.
+                                       @note The STOP task is triggered when
+                                       the last value of the final sequence is
+                                       loaded from RAM, and the peripheral stops
+                                       at the end of the current PWM period.
+                                       For sequences with configured repeating
+                                       of duty cycle values, this might result in
+                                       less than the requested number of repeats
+                                       of the last value. */
+    NRF_DRV_PWM_FLAG_LOOP = 0x02, /**< When the requested playback is finished,
+                                       it should be started from the beginning.
+                                       This flag is ignored if used together
+                                       with @ref NRF_DRV_PWM_FLAG_STOP. */
+    NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0 = 0x04, /**< The event handler should be
+                                                  called when the last value
+                                                  from sequence 0 is loaded. */
+    NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1 = 0x08, /**< The event handler should be
+                                                  called when the last value
+                                                  from sequence 1 is loaded. */
+    NRF_DRV_PWM_FLAG_NO_EVT_FINISHED = 0x10, /**< The playback finished event
+                                                  (enabled by default) should be
+                                                  suppressed. */
+} nrf_drv_pwm_flag_t;
+
+
+/**
+ * @brief PWM driver event type.
+ */
+typedef enum
+{
+    NRF_DRV_PWM_EVT_FINISHED, ///< Sequence playback finished.
+    NRF_DRV_PWM_EVT_END_SEQ0, /**< End of sequence 0 reached. Its data can be
+                                   safely modified now. */
+    NRF_DRV_PWM_EVT_END_SEQ1, /**< End of sequence 1 reached. Its data can be
+                                   safely modified now. */
+    NRF_DRV_PWM_EVT_STOPPED,  ///< The PWM peripheral has been stopped.
+} nrf_drv_pwm_evt_type_t;
+
+/**
+ * @brief PWM driver event handler type.
+ */
+typedef void (* nrf_drv_pwm_handler_t)(nrf_drv_pwm_evt_type_t event_type);
+
+
+/**
+ * @brief Function for initializing the PWM driver.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] p_config   Pointer to the structure with initial configuration.
+ *                       If NULL, the default configuration is used.
+ * @param[in] handler    Event handler provided by the user. If NULL is passed
+ *                       instead, event notifications are not done and PWM
+ *                       interrupts are disabled.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ */
+ret_code_t nrf_drv_pwm_init(nrf_drv_pwm_t const * const p_instance,
+                            nrf_drv_pwm_config_t const * p_config,
+                            nrf_drv_pwm_handler_t        handler);
+
+/**
+ * @brief Function for uninitializing the PWM driver.
+ *
+ * If any sequence playback is in progress, it is stopped immediately.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+void nrf_drv_pwm_uninit(nrf_drv_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for starting a single sequence playback.
+ *
+ * To take advantage of the looping mechanism in the PWM peripheral, both
+ * sequences must be used (single sequence can be played back only once by
+ * the peripheral). Therefore, the provided sequence is internally set and
+ * played back as both sequence 0 and sequence 1. Consequently, if end of
+ * sequence notifications are required, events for both sequences should be
+ * used (that means that both the @ref NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ0 flag
+ * and the @ref NRF_DRV_PWM_FLAG_SIGNAL_END_SEQ1 flag should be specified and
+ * the @ref NRF_DRV_PWM_EVT_END_SEQ0 event and the @ref NRF_DRV_PWM_EVT_END_SEQ1
+ * event should be handled in the same way).
+ *
+ * @note The array containing the duty cycle values for the specified sequence
+ *       must be in RAM and cannot be allocated on stack.
+ *       For detailed information, see @ref nrf_pwm_sequence_t.
+ *
+ * @param[in] p_instance     Pointer to the driver instance structure.
+ * @param[in] p_sequence     Sequence to be played back.
+ * @param[in] playback_count Number of playbacks to be performed (must not be 0).
+ * @param[in] flags          Additional options. Pass any combination of
+ *                           @ref nrf_drv_pwm_flag_t "playback flags", or 0
+ *                           for default settings.
+ */
+void nrf_drv_pwm_simple_playback(nrf_drv_pwm_t const * const p_instance,
+                                 nrf_pwm_sequence_t const * p_sequence,
+                                 uint16_t                   playback_count,
+                                 uint32_t                   flags);
+
+/**
+ * @brief Function for starting a two-sequence playback.
+ *
+ * @note The array containing the duty cycle values for the specified sequence
+ *       must be in RAM and cannot be allocated on stack.
+ *       For detailed information, see @ref nrf_pwm_sequence_t.
+ *
+ * @param[in] p_instance     Pointer to the driver instance structure.
+ * @param[in] p_sequence_0   First sequence to be played back.
+ * @param[in] p_sequence_1   Second sequence to be played back.
+ * @param[in] playback_count Number of playbacks to be performed (must not be 0).
+ * @param[in] flags          Additional options. Pass any combination of
+ *                           @ref nrf_drv_pwm_flag_t "playback flags", or 0
+ *                           for default settings.
+ */
+void nrf_drv_pwm_complex_playback(nrf_drv_pwm_t const * const p_instance,
+                                  nrf_pwm_sequence_t const * p_sequence_0,
+                                  nrf_pwm_sequence_t const * p_sequence_1,
+                                  uint16_t                   playback_count,
+                                  uint32_t                   flags);
+
+/**
+ * @brief Function for advancing the active sequence.
+ *
+ * This function only applies to @ref NRF_PWM_STEP_TRIGGERED mode.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ */
+__STATIC_INLINE void nrf_drv_pwm_step(nrf_drv_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for stopping the sequence playback.
+ *
+ * The playback is stopped at the end of the current PWM period.
+ * This means that if the active sequence is configured to repeat each duty
+ * cycle value for a certain number of PWM periods, the last played value
+ * might appear on the output less times than requested.
+ *
+ * @note This function can be instructed to wait until the playback is stopped
+ *       (by setting @p wait_until_stopped to true). Note that, depending on
+ *       the length of the PMW period, this might take a significant amount of
+ *       time. Alternatively, the @ref nrf_drv_pwm_is_stopped function can be
+ *       used to poll the status, or the @ref NRF_DRV_PWM_EVT_STOPPED event can
+ *       be used to get the notification when the playback is stopped, provided
+ *       the event handler is defined.
+ *
+ * @param[in] p_instance         Pointer to the driver instance structure.
+ * @param[in] wait_until_stopped If true, the function will not return until
+ *                               the playback is stopped.
+ *
+ * @retval true  If the PWM peripheral is stopped.
+ * @retval false If the PWM peripheral is not stopped.
+ */
+bool nrf_drv_pwm_stop(nrf_drv_pwm_t const * const p_instance,
+                      bool wait_until_stopped);
+
+/**
+ * @brief Function for checking the status of the PWM peripheral.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ *
+ * @retval true  If the PWM peripheral is stopped.
+ * @retval false If the PWM peripheral is not stopped.
+ */
+bool nrf_drv_pwm_is_stopped(nrf_drv_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for updating the sequence data during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] p_sequence Pointer to the new sequence definition.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t                    seq_id,
+                                        nrf_pwm_sequence_t const * p_sequence);
+
+/**
+ * @brief Function for updating the pointer to the duty cycle values
+ *        in the specified sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] values     New pointer to the duty cycle values.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_values_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t          seq_id,
+                                        nrf_pwm_values_t values);
+
+/**
+ * @brief Function for updating the number of duty cycle values
+ *        in the specified sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] length     New number of the duty cycle values.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_length_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint16_t length);
+
+/**
+ * @brief Function for updating the number of repeats for duty cycle values
+ *        in specified sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] repeats    New number of repeats.
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_repeats_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t repeats);
+
+/**
+ * @brief Function for updating the additional delay after the specified
+ *        sequence during playback.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] seq_id     Identifier of the sequence (0 or 1).
+ * @param[in] end_delay  New end delay value (in PWM periods).
+ */
+__STATIC_INLINE void nrf_drv_pwm_sequence_end_delay_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t end_delay);
+
+/**
+ * @brief Function for returning the address of a specified PWM task that can
+ *        be used in PPI module.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] task       Requested task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_pwm_task_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_task_t task);
+
+/**@brief Function for returning the address of a specified PWM event that can
+ *        be used in PPI module.
+ *
+ * @param[in] p_instance Pointer to the driver instance structure.
+ * @param[in] event      Requested event.
+ *
+ * @return Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_pwm_event_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_event_t event);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_drv_pwm_step(nrf_drv_pwm_t const * const p_instance)
+{
+    nrf_pwm_task_trigger(p_instance->p_registers, NRF_PWM_TASK_NEXTSTEP);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t                    seq_id,
+                                        nrf_pwm_sequence_t const * p_sequence)
+{
+    nrf_pwm_sequence_set(p_instance->p_registers, seq_id, p_sequence);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_values_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t          seq_id,
+                                        nrf_pwm_values_t values)
+{
+    nrf_pwm_seq_ptr_set(p_instance->p_registers, seq_id, values.p_raw);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_length_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint16_t length)
+{
+    nrf_pwm_seq_cnt_set(p_instance->p_registers, seq_id, length);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_repeats_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t repeats)
+{
+    nrf_pwm_seq_refresh_set(p_instance->p_registers, seq_id, repeats);
+}
+
+__STATIC_INLINE void nrf_drv_pwm_sequence_end_delay_update(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        uint8_t  seq_id,
+                                        uint32_t end_delay)
+{
+    nrf_pwm_seq_end_delay_set(p_instance->p_registers, seq_id, end_delay);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_pwm_task_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_task_t task)
+{
+    return nrf_pwm_task_address_get(p_instance->p_registers, task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_pwm_event_address_get(
+                                        nrf_drv_pwm_t const * const p_instance,
+                                        nrf_pwm_event_t event)
+{
+    return nrf_pwm_event_address_get(p_instance->p_registers, event);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_DRV_PWM_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/saadc/nrf_drv_saadc.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/saadc/nrf_drv_saadc.c
new file mode 100644
index 0000000000..0412f1bcdf
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/saadc/nrf_drv_saadc.c
@@ -0,0 +1,536 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_saadc.h"
+#include "nrf_assert.h"
+#include "nordic_common.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+
+
+typedef enum
+{
+    NRF_SAADC_STATE_IDLE = 0,
+    NRF_SAADC_STATE_BUSY = 1
+} nrf_saadc_state_t;
+
+
+typedef struct
+{
+    nrf_saadc_input_t pselp;
+    nrf_saadc_input_t pseln;
+} nrf_saadc_psel_buffer;
+
+static const nrf_drv_saadc_config_t m_default_config = NRF_DRV_SAADC_DEFAULT_CONFIG;
+
+/** @brief SAADC control block.*/
+typedef struct
+{
+    nrf_drv_saadc_event_handler_t event_handler;                 ///< Event handler function pointer.
+    volatile nrf_saadc_value_t *  p_buffer;                        ///< Sample buffer.
+    volatile uint16_t             buffer_size;                   ///< Size of the sample buffer.
+#ifdef NRF52_PAN_28
+    volatile uint16_t             buffer_pos;                    ///< Current sample buffer position.
+#endif
+    volatile nrf_saadc_value_t *  p_secondary_buffer;            ///< Secondary sample buffer.
+    uint32_t                      limits_enabled_flags;          ///< Enabled limits flags.
+    uint16_t                      secondary_buffer_size;         ///< Size of the secondary buffer.
+    nrf_saadc_psel_buffer         psel[NRF_SAADC_CHANNEL_COUNT]; ///< Pin configurations of SAADC channels.
+    nrf_drv_state_t               state;                         ///< Driver initialization state.
+    nrf_saadc_state_t             adc_state;                     ///< State of the SAADC.
+#ifdef NRF52_PAN_28
+    uint8_t                       scan_pos;                      ///< Current channel scanning position.
+#endif
+    uint8_t                       active_channels;               ///< Number of enabled SAADC channels.
+} nrf_drv_saadc_cb_t;
+
+static nrf_drv_saadc_cb_t m_cb;
+
+#define LOW_LIMIT_TO_FLAG(channel)  ((2*channel+1))
+#define HIGH_LIMIT_TO_FLAG(channel) ((2*channel))
+#define FLAG_IDX_TO_EVENT(idx) ((nrf_saadc_event_t)((uint32_t)NRF_SAADC_EVENT_CH0_LIMITH+4*idx))
+#define LIMIT_EVENT_TO_CHANNEL(event)(uint8_t)(((uint32_t)event-(uint32_t)NRF_SAADC_EVENT_CH0_LIMITH)/8)
+#define LIMIT_EVENT_TO_LIMIT_TYPE(event)((((uint32_t)event-(uint32_t)NRF_SAADC_EVENT_CH0_LIMITH) & 4) ? \
+                                                          NRF_SAADC_LIMIT_LOW : NRF_SAADC_LIMIT_HIGH)
+#define HW_TIMEOUT 10000
+
+
+void SAADC_IRQHandler(void)
+{
+    if (nrf_saadc_event_check(NRF_SAADC_EVENT_END))
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+#ifdef NRF52_PAN_28
+        if (m_cb.active_channels == 1)
+        {
+#endif
+            nrf_drv_saadc_evt_t evt;
+            evt.type = NRF_DRV_SAADC_EVT_DONE;
+            evt.data.done.p_buffer = (nrf_saadc_value_t *)m_cb.p_buffer;
+            evt.data.done.size = nrf_saadc_amount_get();
+
+            if (m_cb.p_secondary_buffer == NULL)
+            {
+                m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+            }
+            else
+            {
+                m_cb.p_buffer = m_cb.p_secondary_buffer;
+                m_cb.buffer_size = m_cb.secondary_buffer_size;
+                m_cb.p_secondary_buffer = NULL;
+                nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+            }
+
+            m_cb.event_handler(&evt);
+#ifdef NRF52_PAN_28
+        }
+        else
+        {
+            //PAN-28: scan mode is not working correctly, emulated by interrupts
+            ++(m_cb.buffer_pos);
+            uint16_t buffer_pos = m_cb.buffer_pos;
+            if (buffer_pos == m_cb.buffer_size)
+            {
+                nrf_drv_saadc_evt_t evt;
+                evt.type = NRF_DRV_SAADC_EVT_DONE;
+                evt.data.done.p_buffer = (nrf_saadc_value_t *)(m_cb.p_buffer);
+                evt.data.done.size = m_cb.buffer_size;
+
+                m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+                if (m_cb.p_secondary_buffer == NULL)
+                {
+                    m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+                }
+                else
+                {
+                    (void)nrf_drv_saadc_buffer_convert((nrf_saadc_value_t *)m_cb.p_secondary_buffer, (uint16_t)m_cb.secondary_buffer_size);
+                }
+                m_cb.event_handler(&evt);
+            }
+            else
+            {
+                uint8_t current_scan_pos = m_cb.scan_pos;
+
+                nrf_saadc_channel_input_set(current_scan_pos,
+                                            NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+
+                nrf_saadc_buffer_init((nrf_saadc_value_t *)(m_cb.p_buffer + m_cb.buffer_pos), 1);
+                // Find the next enabled channel.
+                for (++m_cb.scan_pos; m_cb.scan_pos < NRF_SAADC_CHANNEL_COUNT; ++m_cb.scan_pos)
+                {
+                    if (m_cb.psel[m_cb.scan_pos].pselp)
+                    {
+                        nrf_saadc_channel_input_set(m_cb.scan_pos,
+                                    m_cb.psel[m_cb.scan_pos].pselp, m_cb.psel[m_cb.scan_pos].pseln);
+                        nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+                        nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
+                        return;
+                    }
+                }
+                //if scanning is done prepare for next round.
+                for (uint8_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i)
+                {
+                    if (m_cb.psel[i].pselp)
+                    {
+                        m_cb.scan_pos = i;
+                        break;
+                    }
+                }
+                nrf_saadc_channel_input_set(m_cb.scan_pos,
+                                    m_cb.psel[m_cb.scan_pos].pselp, m_cb.psel[m_cb.scan_pos].pseln);
+                nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+            }
+        }
+#endif
+    }
+    if (nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED))
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED);
+        m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+    }
+    else
+    {
+        uint32_t limit_flags = m_cb.limits_enabled_flags;
+        uint32_t flag_idx;
+        nrf_saadc_event_t event;
+        while (limit_flags)
+        {
+            flag_idx = __CLZ(limit_flags);
+            limit_flags &= ~((1UL<<31) >> flag_idx);
+            event = FLAG_IDX_TO_EVENT(flag_idx);
+            if (nrf_saadc_event_check(event))
+            {
+                nrf_saadc_event_clear(event);
+                nrf_drv_saadc_evt_t evt;
+                evt.type = NRF_DRV_SAADC_EVT_LIMIT;
+                evt.data.limit.channel = LIMIT_EVENT_TO_CHANNEL(event);
+                evt.data.limit.limit_type = LIMIT_EVENT_TO_LIMIT_TYPE(event);
+                m_cb.event_handler(&evt);
+            }
+        }
+    }
+}
+
+
+ret_code_t nrf_drv_saadc_init(nrf_drv_saadc_config_t const * p_config,
+                              nrf_drv_saadc_event_handler_t event_handler)
+{
+    if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (event_handler == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config;
+    }
+
+    m_cb.event_handler = event_handler;
+    nrf_saadc_resolution_set(p_config->resolution);
+    nrf_saadc_oversample_set(p_config->oversample);
+    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+    m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+    m_cb.active_channels = 0;
+    m_cb.limits_enabled_flags = 0;
+#ifdef NRF52_PAN_28
+    m_cb.buffer_pos = 0;
+#endif
+
+    nrf_saadc_int_disable(NRF_SAADC_INT_ALL);
+    nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+    nrf_drv_common_irq_enable(SAADC_IRQn, p_config->interrupt_priority);
+    nrf_saadc_int_enable(NRF_SAADC_INT_END);
+
+    nrf_saadc_enable();
+
+    return NRF_SUCCESS;
+}
+
+
+void nrf_drv_saadc_uninit(void)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+    nrf_drv_common_irq_disable(SAADC_IRQn);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP);
+
+    // Wait for ADC being stopped.
+    uint32_t timeout = HW_TIMEOUT;
+    while (nrf_saadc_event_check(NRF_SAADC_EVENT_STOPPED) == 0 && timeout > 0)
+    {
+        --timeout;
+    }
+    ASSERT(timeout > 0);
+    
+    nrf_saadc_disable();
+    nrf_saadc_int_disable(NRF_SAADC_INT_ALL);
+
+    m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+
+    for (uint8_t channel = 0; channel < NRF_SAADC_CHANNEL_COUNT; ++channel)
+    {
+        if (m_cb.psel[channel].pselp != NRF_SAADC_INPUT_DISABLED)
+        {
+            (void)nrf_drv_saadc_channel_uninit(channel);
+        }
+    }
+
+    m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+
+ret_code_t nrf_drv_saadc_channel_init(uint8_t channel,
+                                      nrf_saadc_channel_config_t const * const p_config)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
+    //Oversampling can be used only with one channel.
+    ASSERT((nrf_saadc_oversample_get()==NRF_SAADC_OVERSAMPLE_DISABLED) || (m_cb.active_channels == 0));
+    ASSERT((p_config->pin_p <= NRF_SAADC_INPUT_VDD) && (p_config->pin_p > NRF_SAADC_INPUT_DISABLED));
+    ASSERT(p_config->pin_n <= NRF_SAADC_INPUT_VDD);
+
+    // A channel can only be initialized if the driver is in the idle state.
+    if (m_cb.adc_state == NRF_SAADC_STATE_BUSY)
+    {
+        return NRF_ERROR_BUSY;
+    }
+
+    if (!m_cb.psel[channel].pselp)
+    {
+        ++m_cb.active_channels;
+    }
+    m_cb.psel[channel].pselp = p_config->pin_p;
+    m_cb.psel[channel].pseln = p_config->pin_n;
+    nrf_saadc_channel_init(channel, p_config);
+
+#ifdef NRF52_PAN_28
+    nrf_saadc_channel_input_set(channel, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+#else
+    nrf_saadc_channel_input_set(channel, p_config->pin_p, p_config->pin_n);
+#endif
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t nrf_drv_saadc_channel_uninit(uint8_t channel)
+{
+    ASSERT(channel <= NRF_SAADC_CHANNEL_COUNT)
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    // A channel can only be uninitialized if the driver is in the idle state.
+    if (m_cb.adc_state == NRF_SAADC_STATE_BUSY)
+    {
+        return NRF_ERROR_BUSY;
+    }
+
+    if (m_cb.psel[channel].pselp)
+    {
+        --m_cb.active_channels;
+    }
+    m_cb.psel[channel].pselp = NRF_SAADC_INPUT_DISABLED;
+    m_cb.psel[channel].pseln = NRF_SAADC_INPUT_DISABLED;
+    nrf_saadc_channel_input_set(channel, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+    nrf_drv_saadc_limits_set(channel, NRF_DRV_SAADC_LIMITL_DISABLED, NRF_DRV_SAADC_LIMITH_DISABLED);
+
+    return NRF_SUCCESS;
+}
+
+ret_code_t nrf_drv_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value)
+{
+    if (m_cb.adc_state != NRF_SAADC_STATE_IDLE)
+    {
+        return NRF_ERROR_BUSY;
+    }
+    m_cb.adc_state = NRF_SAADC_STATE_BUSY;
+    nrf_saadc_int_disable(NRF_SAADC_INT_END);
+    nrf_saadc_buffer_init(p_value, 1);
+#ifndef NRF52_PAN_28
+    if (m_cb.active_channels > 1)
+    {
+        for (uint8_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i)
+        {
+            nrf_saadc_channel_input_set(i, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+        }
+    }
+#endif
+    nrf_saadc_channel_input_set(channel,
+                            m_cb.psel[channel].pselp, m_cb.psel[channel].pseln);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
+
+    uint32_t timeout = HW_TIMEOUT;
+    while (0 == nrf_saadc_event_check(NRF_SAADC_EVENT_END) && timeout > 0)
+    {
+        timeout--;
+    }
+    nrf_saadc_event_clear(NRF_SAADC_EVENT_END);
+
+#ifdef NRF52_PAN_28
+    nrf_saadc_channel_input_set(channel, NRF_SAADC_INPUT_DISABLED, NRF_SAADC_INPUT_DISABLED);
+#else
+    if (m_cb.active_channels > 1)
+    {
+        for (uint8_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i)
+        {
+            nrf_saadc_channel_input_set(i, m_cb.psel[i].pselp, m_cb.psel[i].pseln);
+        }
+    }
+#endif
+
+    nrf_saadc_int_enable(NRF_SAADC_INT_END);
+    m_cb.adc_state = NRF_SAADC_STATE_IDLE;
+
+    return NRF_SUCCESS;
+}
+
+ret_code_t nrf_drv_saadc_buffer_convert(nrf_saadc_value_t * p_buffer, uint16_t size)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_saadc_int_disable(NRF_SAADC_INT_END);
+    if (m_cb.adc_state == NRF_SAADC_STATE_BUSY)
+    {
+        if ( m_cb.p_secondary_buffer)
+        {
+            nrf_saadc_int_enable(NRF_SAADC_INT_END);
+            return NRF_ERROR_BUSY;
+        }
+        else
+        {
+            m_cb.p_secondary_buffer = p_buffer;
+            m_cb.secondary_buffer_size = size;
+#ifdef NRF52_PAN_28
+            if (m_cb.active_channels == 1)
+#endif
+            {
+                while (nrf_saadc_event_check(NRF_SAADC_EVENT_STARTED) == 0);
+                nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
+                nrf_saadc_buffer_init(p_buffer, size);
+            }
+            nrf_saadc_int_enable(NRF_SAADC_INT_END);
+            return NRF_SUCCESS;
+        }
+    }
+    nrf_saadc_int_enable(NRF_SAADC_INT_END);
+    m_cb.adc_state = NRF_SAADC_STATE_BUSY;
+
+#ifdef NRF52_PAN_28
+    m_cb.scan_pos = NRF_SAADC_CHANNEL_COUNT;
+    for (uint8_t i = 0; i < NRF_SAADC_CHANNEL_COUNT; ++i)
+    {
+        if (m_cb.psel[i].pselp)
+        {
+            m_cb.scan_pos = i;
+            break;
+        }
+    }
+
+    // Find the first enabled channel.
+    if (m_cb.scan_pos >= NRF_SAADC_CHANNEL_COUNT)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    m_cb.buffer_pos = 0;
+#endif
+    m_cb.p_buffer = p_buffer;
+    m_cb.buffer_size = size;
+    m_cb.p_secondary_buffer = NULL;
+
+#ifdef NRF52_PAN_28
+    nrf_saadc_channel_input_set(m_cb.scan_pos,
+                                m_cb.psel[m_cb.scan_pos].pselp, m_cb.psel[m_cb.scan_pos].pseln);
+
+    if (m_cb.active_channels == 1)
+    {
+        nrf_saadc_buffer_init(p_buffer, size);
+    }
+    else
+    {
+        nrf_saadc_buffer_init(p_buffer, 1);
+    }
+#else
+    nrf_saadc_buffer_init(p_buffer, size);
+#endif
+
+    nrf_saadc_event_clear(NRF_SAADC_EVENT_STARTED);
+    nrf_saadc_task_trigger(NRF_SAADC_TASK_START);
+
+    return NRF_SUCCESS;
+}
+
+ret_code_t nrf_drv_saadc_sample()
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+
+    ret_code_t err_code = NRF_SUCCESS;
+    if (m_cb.adc_state == NRF_SAADC_STATE_IDLE)
+    {
+        err_code = NRF_ERROR_BUSY;
+    }
+    else
+    {
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_SAMPLE);
+    }
+    
+    return err_code;
+}
+
+
+bool nrf_drv_saadc_is_busy(void)
+{
+    return (m_cb.adc_state == NRF_SAADC_STATE_BUSY);
+}
+
+void nrf_drv_saadc_abort(void)
+{
+    if (nrf_drv_saadc_is_busy())
+    {
+        nrf_saadc_event_clear(NRF_SAADC_EVENT_STOPPED);
+        nrf_saadc_task_trigger(NRF_SAADC_TASK_STOP);
+        
+        // Wait for ADC being stopped.
+        uint32_t timeout = HW_TIMEOUT;
+        while ((m_cb.adc_state != NRF_SAADC_STATE_IDLE) && (timeout > 0))
+        {
+            --timeout;
+        }
+        ASSERT(timeout > 0);
+        
+        m_cb.p_buffer = 0;
+        m_cb.p_secondary_buffer = 0;
+    }
+}
+
+void nrf_drv_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high)
+{
+    ASSERT(m_cb.state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(m_cb.event_handler); // only non blocking mode supported
+    ASSERT(limit_low>=NRF_DRV_SAADC_LIMITL_DISABLED);
+    ASSERT(limit_high<=NRF_DRV_SAADC_LIMITH_DISABLED);
+    ASSERT(limit_low<limit_high);
+    nrf_saadc_channel_limits_set(channel, limit_low, limit_high);
+
+    uint32_t int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_LOW);
+    if (limit_low == NRF_DRV_SAADC_LIMITL_DISABLED)
+    {
+        m_cb.limits_enabled_flags &= ~(0x80000000 >> LOW_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_disable(int_mask);
+    }
+    else
+    {
+        m_cb.limits_enabled_flags |= (0x80000000 >> LOW_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_enable(int_mask);
+    }
+
+    int_mask = nrf_saadc_limit_int_get(channel, NRF_SAADC_LIMIT_HIGH);
+    if (limit_high == NRF_DRV_SAADC_LIMITH_DISABLED)
+    {
+        m_cb.limits_enabled_flags &= ~(0x80000000 >> HIGH_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_disable(int_mask);
+    }
+    else
+    {
+        m_cb.limits_enabled_flags |= (0x80000000 >> HIGH_LIMIT_TO_FLAG(channel));
+        nrf_saadc_int_enable(int_mask);
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/saadc/nrf_drv_saadc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/saadc/nrf_drv_saadc.h
new file mode 100644
index 0000000000..661177c424
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/driver_nrf/saadc/nrf_drv_saadc.h
@@ -0,0 +1,330 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @addtogroup nrf_saadc SAADC HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      @tagAPI52 Successive Approximation Analog-to-Digital Converter (SAADC) APIs.
+ * @details The SAADC HAL provides basic APIs for accessing the registers of the SAADC peripheral. 
+ * The SAADC driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_saadc SAADC driver
+ * @{
+ * @ingroup  nrf_saadc
+ *
+ * @brief    @tagAPI52 Successive Approximation Analog-to-Digital Converter (SAADC) driver.
+ */
+
+#ifndef NRF_DRV_SAADC_H__
+#define NRF_DRV_SAADC_H__
+
+#include "nrf_drv_config.h"
+#include "nrf_saadc.h"
+#include "sdk_errors.h"
+
+/**
+ * @brief Value that should be set as high limit to disable limit detection.
+ */
+#define NRF_DRV_SAADC_LIMITH_DISABLED (2047)
+/**
+ * @brief Value that should be set as low limit to disable limit detection.
+ */
+#define NRF_DRV_SAADC_LIMITL_DISABLED (-2048)
+
+/**
+ * @brief Macro for setting @ref nrf_drv_saadc_config_t to default settings.
+ */
+#define NRF_DRV_SAADC_DEFAULT_CONFIG                \
+{                                                   \
+    .resolution         = SAADC_CONFIG_RESOLUTION,  \
+    .oversample         = SAADC_CONFIG_OVERSAMPLE,  \
+    .interrupt_priority = SAADC_CONFIG_IRQ_PRIORITY \
+}
+
+/**
+ * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings
+ *        in single ended mode.
+ *
+ * @param PIN_P Analog input.
+ */
+#define NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_SE(PIN_P) \
+{                                                      \
+    .resistor_p = NRF_SAADC_RESISTOR_DISABLED,         \
+    .resistor_n = NRF_SAADC_RESISTOR_DISABLED,         \
+    .gain       = NRF_SAADC_GAIN1_6,                   \
+    .reference  = NRF_SAADC_REFERENCE_INTERNAL,        \
+    .acq_time   = NRF_SAADC_ACQTIME_10US,              \
+    .mode       = NRF_SAADC_MODE_SINGLE_ENDED,         \
+    .pin_p      = (nrf_saadc_input_t)(PIN_P),          \
+    .pin_n      = NRF_SAADC_INPUT_DISABLED             \
+}
+
+/**
+ * @brief Macro for setting @ref nrf_saadc_channel_config_t to default settings
+ *        in differential mode.
+ *
+ * @param PIN_P Positive analog input.
+ * @param PIN_N Negative analog input.
+ */
+#define NRF_DRV_SAADC_DEFAULT_CHANNEL_CONFIG_DIFFERENTIAL(PIN_P, PIN_N) \
+{                                                                       \
+    .resistor_p = NRF_SAADC_RESISTOR_DISABLED,                          \
+    .resistor_n = NRF_SAADC_RESISTOR_DISABLED,                          \
+    .gain       = NRF_SAADC_GAIN1_6,                                    \
+    .reference  = NRF_SAADC_REFERENCE_INTERNAL,                         \
+    .acq_time   = NRF_SAADC_ACQTIME_10US,                               \
+    .mode       = NRF_SAADC_MODE_DIFFERENTIAL,                          \
+    .pin_p      = (nrf_saadc_input_t)(PIN_P),                           \
+    .pin_n      = (nrf_saadc_input_t)(PIN_N)                            \
+}
+
+/**
+ * @brief Analog-to-digital converter driver configuration structure.
+ */
+typedef struct
+{
+    nrf_saadc_resolution_t resolution;         ///< Resolution configuration.
+    nrf_saadc_oversample_t oversample;         ///< Oversampling configuration.
+    uint8_t                interrupt_priority; ///< Interrupt priority.
+} nrf_drv_saadc_config_t;
+
+/**
+ * @brief Driver event types.
+ */
+typedef enum
+{
+    NRF_DRV_SAADC_EVT_DONE,    ///< Event generated when the buffer is filled with samples.
+    NRF_DRV_SAADC_EVT_LIMIT,   ///< Event generated after one of the limits is reached.
+} nrf_drv_saadc_evt_type_t;
+
+/**
+ * @brief Analog-to-digital converter driver done event data.
+ */
+typedef struct
+{
+    nrf_saadc_value_t *      p_buffer; ///< Pointer to buffer with converted samples.
+    uint16_t                 size;     ///< Number of samples in the buffer.
+} nrf_drv_saadc_done_evt_t;
+
+/**
+ * @brief Analog-to-digital converter driver limit event data.
+ */
+typedef struct
+{
+    uint8_t                  channel;    ///< Channel on which the limit was detected.
+    nrf_saadc_limit_t        limit_type; ///< Type of limit detected.
+} nrf_drv_saadc_limit_evt_t;
+
+/**
+ * @brief Analog-to-digital converter driver event structure.
+ */
+typedef struct
+{
+    nrf_drv_saadc_evt_type_t type;      ///< Event type.
+    union
+    {
+        nrf_drv_saadc_done_evt_t  done; ///< Data for @ref NRF_DRV_SAADC_EVT_DONE event.
+        nrf_drv_saadc_limit_evt_t limit;///< Data for @ref NRF_DRV_SAADC_EVT_LIMIT event.
+    } data;
+} nrf_drv_saadc_evt_t;
+
+/**
+ * @brief ADC event handler.
+ *
+ * @param[in] p_event     Pointer to an ADC event. The event structure is allocated on
+ *                        the stack, so it is valid only within the context of
+ *                        the event handler.
+ */
+typedef void (*nrf_drv_saadc_event_handler_t)(nrf_drv_saadc_evt_t const * p_event);
+
+/**
+ * @brief Function for initializing the SAADC.
+ *
+ * @param[in] p_config      Pointer to a configuration structure. If NULL, the default one is used.
+ * @param[in] event_handler Event handler provided by the user.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the driver is already initialized.
+ * @retval    NRF_ERROR_INVALID_PARAM If event_handler is NULL.
+ */
+ret_code_t nrf_drv_saadc_init(nrf_drv_saadc_config_t const * p_config,
+                              nrf_drv_saadc_event_handler_t event_handler);
+
+/**
+ * @brief Function for uninitializing the SAADC.
+ *
+ * This function stops all ongoing conversions and disables all channels.
+ */
+void nrf_drv_saadc_uninit(void);
+
+/**
+ * @brief Function for getting the address of a SAMPLE SAADC task.
+ *
+ * @return     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_saadc_sample_task_get(void)
+{
+    return nrf_saadc_task_address_get(NRF_SAADC_TASK_SAMPLE);
+}
+
+
+/**
+ * @brief Function for initializing an SAADC channel.
+ *
+ * This function configures and enables the channel.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the ADC was not initialized.
+ * @retval NRF_ERROR_NO_MEM        If the specified channel was already allocated.
+ */
+ret_code_t nrf_drv_saadc_channel_init(uint8_t channel, 
+                                      nrf_saadc_channel_config_t const * const p_config);
+
+
+/**
+ * @brief Function for uninitializing an SAADC channel.
+ *
+ * @retval NRF_SUCCESS    If uninitialization was successful.
+ * @retval NRF_ERROR_BUSY If the ADC is busy.
+ */
+ret_code_t nrf_drv_saadc_channel_uninit(uint8_t channel);
+
+/**
+ * @brief Function for starting SAADC sampling.
+ *
+ * @retval NRF_SUCCESS    If ADC sampling was triggered.
+ * @retval NRF_ERROR_BUSY If ADC is in idle state.
+ */
+ret_code_t nrf_drv_saadc_sample(void);
+
+/**
+ * @brief Blocking function for executing a single ADC conversion.
+ *
+ * This function selects the desired input, starts a single conversion,
+ * waits for it to finish, and returns the result.
+ *
+ * The function will fail if ADC is busy.
+ *
+ * @param[in]  channel Channel.
+ * @param[out] p_value Pointer to the location where the result should be placed.
+ *
+ * @retval NRF_SUCCESS    If conversion was successful.
+ * @retval NRF_ERROR_BUSY If the ADC driver is busy.
+ */
+ret_code_t nrf_drv_saadc_sample_convert(uint8_t channel, nrf_saadc_value_t * p_value);
+
+/**
+ * @brief Function for issuing conversion of data to the buffer.
+ *
+ * This function is non-blocking. The application is notified about filling the buffer by the event handler.
+ * Conversion will be done on all enabled channels. If the ADC is in idle state, the function will set up Easy
+ * DMA for the conversion. The ADC will be ready for sampling and wait for the SAMPLE task. It can be
+ * triggered manually by the @ref nrf_drv_saadc_sample function or by PPI using the @ref NRF_SAADC_TASK_SAMPLE
+ * task. If one buffer is already set and the conversion is ongoing, calling this function will
+ * result in queuing the given buffer. The driver will start filling the issued buffer when the first one is
+ * completed. If the function is called again before the first buffer is filled, it will return with error.
+ *
+ * @param[in] buffer Result buffer.
+ * @param[in] size   Buffer size in words.
+ *
+ * @retval NRF_SUCCESS    If conversion was successful.
+ * @retval NRF_ERROR_BUSY If the driver already has two buffers set.
+ */
+ret_code_t nrf_drv_saadc_buffer_convert(nrf_saadc_value_t * buffer, uint16_t size);
+
+/**
+ * @brief Function for retrieving the SAADC state.
+ *
+ * @retval true  If the ADC is busy.
+ * @retval false If the ADC is ready.
+ */
+bool nrf_drv_saadc_is_busy(void);
+
+/**
+ * @brief Function for aborting ongoing and buffered conversions.
+ * @note @ref NRF_DRV_SAADC_EVT_DONE event will be generated if there is a conversion in progress.
+ *       Event will contain number of words in the sample buffer.
+ */
+void nrf_drv_saadc_abort(void);
+
+/**
+ * @brief Function for setting the SAADC channel limits.
+ *        When limits are enabled and the result exceeds the defined bounds, the limit handler function is called.
+ *
+ * @param[in] channel SAADC channel number.
+ * @param[in] limit_low Lower limit (valid values from @ref NRF_DRV_SAADC_LIMITL_DISABLED to
+ *            @ref NRF_DRV_SAADC_LIMITH_DISABLED). Conversion results below this value will trigger
+ *            the handler function. Set to @ref NRF_DRV_SAADC_LIMITL_DISABLED to disable this limit.
+ * @param[in] limit_high Upper limit (valid values from @ref NRF_DRV_SAADC_LIMITL_DISABLED to
+ *            @ref NRF_DRV_SAADC_LIMITH_DISABLED). Conversion results above this value will trigger
+ *            the handler function. Set to @ref NRF_DRV_SAADC_LIMITH_DISABLED to disable this limit.
+ */
+void nrf_drv_saadc_limits_set(uint8_t channel, int16_t limit_low, int16_t limit_high);
+
+/**
+ * @brief Function for converting a GPIO pin number to an analog input pin number used in the channel
+ *        configuration.
+ *
+ * @param[in]  pin GPIO pin.
+ *
+ * @return     Value representing an analog input pin. The function returns @ref NRF_SAADC_INPUT_DISABLED
+ *             if the specified pin is not an analog input.
+ */
+__STATIC_INLINE nrf_saadc_input_t nrf_drv_saadc_gpio_to_ain(uint32_t pin)
+{
+    // AIN0 - AIN3
+    if (pin >= 2 && pin <= 5)
+    {
+        //0 means "not connected", hence this "+ 1"
+        return (nrf_saadc_input_t)(pin - 2 + 1);
+    }
+    // AIN4 - AIN7
+    else if (pin >= 28 && pin <= 31)
+    {
+        return (nrf_saadc_input_t)(pin - 24 + 1);
+    }
+    else
+    {
+        return NRF_SAADC_INPUT_DISABLED;
+    }
+}
+
+#endif // NRF_DRV_SAADC_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h
new file mode 100644
index 0000000000..127ef3dbdb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h
@@ -0,0 +1,495 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_CONFIG_H
+#define NRF_DRV_CONFIG_H
+
+/**
+ * Provide a non-zero value here in applications that need to use several
+ * peripherals with the same ID that are sharing certain resources
+ * (for example, SPI0 and TWI0). Obviously, such peripherals cannot be used
+ * simultaneously. Therefore, this definition allows to initialize the driver
+ * for another peripheral from a given group only after the previously used one
+ * is uninitialized. Normally, this is not possible, because interrupt handlers
+ * are implemented in individual drivers.
+ * This functionality requires a more complicated interrupt handling and driver
+ * initialization, hence it is not always desirable to use it.
+ */
+#define PERIPHERAL_RESOURCE_SHARING_ENABLED  1
+
+/* CLOCK */
+#define CLOCK_ENABLED 1
+
+#if (CLOCK_ENABLED == 1)
+#define CLOCK_CONFIG_XTAL_FREQ          NRF_CLOCK_XTALFREQ_Default
+#define CLOCK_CONFIG_LF_SRC             NRF_CLOCK_LFCLK_Xtal
+#define CLOCK_CONFIG_IRQ_PRIORITY       APP_IRQ_PRIORITY_LOW
+#endif
+
+/* GPIOTE */
+#define GPIOTE_ENABLED 1
+
+#if (GPIOTE_ENABLED == 1)
+#define GPIOTE_CONFIG_USE_SWI_EGU false
+#define GPIOTE_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS 8
+#endif
+
+/* TIMER */
+#ifdef SOFTDEVICE_PRESENT
+#define TIMER0_ENABLED 0
+#else
+#define TIMER0_ENABLED 1
+#endif
+
+#if (TIMER0_ENABLED == 1)
+#define TIMER0_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER0_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER0_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_32Bit
+#define TIMER0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER0_INSTANCE_INDEX      0
+#endif
+
+#define TIMER1_ENABLED 1
+
+#if (TIMER1_ENABLED == 1)
+#define TIMER1_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER1_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER1_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER1_INSTANCE_INDEX      (TIMER0_ENABLED)
+#endif
+ 
+#define TIMER2_ENABLED 1
+
+#if (TIMER2_ENABLED == 1)
+#define TIMER2_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER2_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER2_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER2_INSTANCE_INDEX      (TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER3_ENABLED 0
+
+#if (TIMER3_ENABLED == 1)
+#define TIMER3_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER3_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER3_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER3_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER3_INSTANCE_INDEX      (TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+#define TIMER4_ENABLED 0
+
+#if (TIMER4_ENABLED == 1)
+#define TIMER4_CONFIG_FREQUENCY    NRF_TIMER_FREQ_16MHz
+#define TIMER4_CONFIG_MODE         TIMER_MODE_MODE_Timer
+#define TIMER4_CONFIG_BIT_WIDTH    TIMER_BITMODE_BITMODE_16Bit
+#define TIMER4_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TIMER4_INSTANCE_INDEX      (TIMER3_ENABLED+TIMER2_ENABLED+TIMER1_ENABLED+TIMER0_ENABLED)
+#endif
+
+
+#define TIMER_COUNT (TIMER0_ENABLED + TIMER1_ENABLED + TIMER2_ENABLED + TIMER3_ENABLED + TIMER4_ENABLED)
+
+/* RTC */
+#define RTC0_ENABLED 0
+
+#if (RTC0_ENABLED == 1)
+#define RTC0_CONFIG_FREQUENCY    32678
+#define RTC0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC0_CONFIG_RELIABLE     false
+
+#define RTC0_INSTANCE_INDEX      0
+#endif
+
+#define RTC1_ENABLED 0
+
+#if (RTC1_ENABLED == 1)
+#define RTC1_CONFIG_FREQUENCY    32768
+#define RTC1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC1_CONFIG_RELIABLE     false
+
+#define RTC1_INSTANCE_INDEX      (RTC0_ENABLED)
+#endif
+
+#define RTC2_ENABLED 0
+
+#if (RTC2_ENABLED == 1)
+#define RTC2_CONFIG_FREQUENCY    32768
+#define RTC2_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define RTC2_CONFIG_RELIABLE     false
+
+#define RTC2_INSTANCE_INDEX      (RTC0_ENABLED+RTC1_ENABLED)
+#endif
+
+
+#define RTC_COUNT                (RTC0_ENABLED+RTC1_ENABLED+RTC2_ENABLED)
+
+#define NRF_MAXIMUM_LATENCY_US 2000
+
+/* RNG */
+#define RNG_ENABLED 0
+
+#if (RNG_ENABLED == 1)
+#define RNG_CONFIG_ERROR_CORRECTION true
+#define RNG_CONFIG_POOL_SIZE        8
+#define RNG_CONFIG_IRQ_PRIORITY     APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PWM */
+
+#define PWM0_ENABLED 1
+
+#if (PWM0_ENABLED == 1)
+#define PWM0_CONFIG_OUT0_PIN        2
+#define PWM0_CONFIG_OUT1_PIN        3
+#define PWM0_CONFIG_OUT2_PIN        4
+#define PWM0_CONFIG_OUT3_PIN        5
+#define PWM0_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#define PWM0_CONFIG_BASE_CLOCK      NRF_PWM_CLK_1MHz
+#define PWM0_CONFIG_COUNT_MODE      NRF_PWM_MODE_UP
+#define PWM0_CONFIG_TOP_VALUE       1000
+#define PWM0_CONFIG_LOAD_MODE       NRF_PWM_LOAD_COMMON
+#define PWM0_CONFIG_STEP_MODE       NRF_PWM_STEP_AUTO
+
+#define PWM0_INSTANCE_INDEX 0
+#endif
+
+#define PWM1_ENABLED 1
+
+#if (PWM1_ENABLED == 1)
+#define PWM1_CONFIG_OUT0_PIN        2
+#define PWM1_CONFIG_OUT1_PIN        3
+#define PWM1_CONFIG_OUT2_PIN        4
+#define PWM1_CONFIG_OUT3_PIN        5
+#define PWM1_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#define PWM1_CONFIG_BASE_CLOCK      NRF_PWM_CLK_1MHz
+#define PWM1_CONFIG_COUNT_MODE      NRF_PWM_MODE_UP
+#define PWM1_CONFIG_TOP_VALUE       1000
+#define PWM1_CONFIG_LOAD_MODE       NRF_PWM_LOAD_COMMON
+#define PWM1_CONFIG_STEP_MODE       NRF_PWM_STEP_AUTO
+
+#define PWM1_INSTANCE_INDEX (PWM0_ENABLED)
+#endif
+
+#define PWM2_ENABLED 1
+
+#if (PWM2_ENABLED == 1)
+#define PWM2_CONFIG_OUT0_PIN        2
+#define PWM2_CONFIG_OUT1_PIN        3
+#define PWM2_CONFIG_OUT2_PIN        4
+#define PWM2_CONFIG_OUT3_PIN        5
+#define PWM2_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#define PWM2_CONFIG_BASE_CLOCK      NRF_PWM_CLK_1MHz
+#define PWM2_CONFIG_COUNT_MODE      NRF_PWM_MODE_UP
+#define PWM2_CONFIG_TOP_VALUE       1000
+#define PWM2_CONFIG_LOAD_MODE       NRF_PWM_LOAD_COMMON
+#define PWM2_CONFIG_STEP_MODE       NRF_PWM_STEP_AUTO
+
+#define PWM2_INSTANCE_INDEX (PWM0_ENABLED + PWM1_ENABLED)
+#endif
+
+#define PWM_COUNT   (PWM0_ENABLED + PWM1_ENABLED + PWM2_ENABLED)
+
+/* SPI */
+#define SPI0_ENABLED 1
+
+#if (SPI0_ENABLED == 1)
+#define SPI0_USE_EASY_DMA 0
+
+#define SPI0_CONFIG_SCK_PIN         2
+#define SPI0_CONFIG_MOSI_PIN        3
+#define SPI0_CONFIG_MISO_PIN        4
+#define SPI0_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPI0_INSTANCE_INDEX 0
+#endif
+
+#define SPI1_ENABLED 1
+
+#if (SPI1_ENABLED == 1)
+#define SPI1_USE_EASY_DMA 0
+
+#define SPI1_CONFIG_SCK_PIN         2
+#define SPI1_CONFIG_MOSI_PIN        3
+#define SPI1_CONFIG_MISO_PIN        4
+#define SPI1_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPI1_INSTANCE_INDEX (SPI0_ENABLED)
+#endif
+
+#define SPI2_ENABLED 1
+
+#if (SPI2_ENABLED == 1)
+#define SPI2_USE_EASY_DMA 0
+
+#define SPI2_CONFIG_SCK_PIN         2
+#define SPI2_CONFIG_MOSI_PIN        3
+#define SPI2_CONFIG_MISO_PIN        4
+#define SPI2_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPI2_INSTANCE_INDEX (SPI0_ENABLED + SPI1_ENABLED)
+#endif
+
+#define SPI_COUNT   (SPI0_ENABLED + SPI1_ENABLED + SPI2_ENABLED)
+
+/* SPIS */
+#define SPIS0_ENABLED 1
+
+#if (SPIS0_ENABLED == 1)
+#define SPIS0_CONFIG_SCK_PIN         2
+#define SPIS0_CONFIG_MOSI_PIN        3
+#define SPIS0_CONFIG_MISO_PIN        4
+#define SPIS0_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPIS0_INSTANCE_INDEX 0
+#endif
+
+#define SPIS1_ENABLED 1
+
+#if (SPIS1_ENABLED == 1)
+#define SPIS1_CONFIG_SCK_PIN         2
+#define SPIS1_CONFIG_MOSI_PIN        3
+#define SPIS1_CONFIG_MISO_PIN        4
+#define SPIS1_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPIS1_INSTANCE_INDEX SPIS0_ENABLED
+#endif
+
+#define SPIS2_ENABLED 1
+
+#if (SPIS2_ENABLED == 1)
+#define SPIS2_CONFIG_SCK_PIN         2
+#define SPIS2_CONFIG_MOSI_PIN        3
+#define SPIS2_CONFIG_MISO_PIN        4
+#define SPIS2_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+
+#define SPIS2_INSTANCE_INDEX (SPIS0_ENABLED + SPIS1_ENABLED)
+#endif
+
+#define SPIS_COUNT   (SPIS0_ENABLED + SPIS1_ENABLED + SPIS2_ENABLED)
+
+/* UART */
+#define UART0_ENABLED 1
+
+#if (UART0_ENABLED == 1)
+#define UART0_CONFIG_HWFC         NRF_UART_HWFC_ENABLED
+#define UART0_CONFIG_PARITY       NRF_UART_PARITY_EXCLUDED
+#define UART0_CONFIG_BAUDRATE     NRF_UART_BAUDRATE_9600
+#define UART0_CONFIG_PSEL_TXD     6
+#define UART0_CONFIG_PSEL_RXD     8
+#define UART0_CONFIG_PSEL_CTS     7
+#define UART0_CONFIG_PSEL_RTS     5
+#define UART0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#ifdef NRF52
+#define UART0_CONFIG_USE_EASY_DMA false
+//Compile time flag
+#define UART_EASY_DMA_SUPPORT     1
+#define UART_LEGACY_SUPPORT       1
+#endif //NRF52
+#endif
+
+#define TWI0_ENABLED 1
+
+#if (TWI0_ENABLED == 1)
+#define TWI0_USE_EASY_DMA 0
+
+#define TWI0_CONFIG_FREQUENCY    NRF_TWI_FREQ_100K
+#define TWI0_CONFIG_SCL          0
+#define TWI0_CONFIG_SDA          1
+#define TWI0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI0_INSTANCE_INDEX      0
+#endif
+
+#define TWI1_ENABLED 1
+
+#if (TWI1_ENABLED == 1)
+#define TWI1_USE_EASY_DMA 0
+
+#define TWI1_CONFIG_FREQUENCY    NRF_TWI_FREQ_100K
+#define TWI1_CONFIG_SCL          0
+#define TWI1_CONFIG_SDA          1
+#define TWI1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+#define TWI1_INSTANCE_INDEX      (TWI0_ENABLED)
+#endif
+
+#define TWI_COUNT                (TWI0_ENABLED + TWI1_ENABLED)
+
+/* TWIS */
+#define TWIS0_ENABLED 0
+
+#if (TWIS0_ENABLED == 1)
+    #define TWIS0_CONFIG_ADDR0        0
+    #define TWIS0_CONFIG_ADDR1        0 /* 0: Disabled */
+    #define TWIS0_CONFIG_SCL          0
+    #define TWIS0_CONFIG_SDA          1
+    #define TWIS0_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+    #define TWIS0_INSTANCE_INDEX      0
+#endif
+
+#define TWIS1_ENABLED 0
+
+#if (TWIS1_ENABLED ==  1)
+    #define TWIS1_CONFIG_ADDR0        0
+    #define TWIS1_CONFIG_ADDR1        0 /* 0: Disabled */
+    #define TWIS1_CONFIG_SCL          0
+    #define TWIS1_CONFIG_SDA          1
+    #define TWIS1_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+
+    #define TWIS1_INSTANCE_INDEX      (TWIS0_ENABLED)
+#endif
+
+#define TWIS_COUNT (TWIS0_ENABLED + TWIS1_ENABLED)
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_ASSUME_INIT_AFTER_RESET_ONLY 0
+/* For more documentation see nrf_drv_twis.h file */
+#define TWIS_NO_SYNC_MODE 0
+
+/* QDEC */
+#define QDEC_ENABLED 0
+
+#if (QDEC_ENABLED == 1)
+#define QDEC_CONFIG_REPORTPER    NRF_QDEC_REPORTPER_10
+#define QDEC_CONFIG_SAMPLEPER    NRF_QDEC_SAMPLEPER_16384us
+#define QDEC_CONFIG_PIO_A        1
+#define QDEC_CONFIG_PIO_B        2
+#define QDEC_CONFIG_PIO_LED      3
+#define QDEC_CONFIG_LEDPRE       511
+#define QDEC_CONFIG_LEDPOL       NRF_QDEC_LEPOL_ACTIVE_HIGH
+#define QDEC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define QDEC_CONFIG_DBFEN        false
+#define QDEC_CONFIG_SAMPLE_INTEN false
+#endif
+
+/* ADC */
+#define ADC_ENABLED 0
+
+#if (ADC_ENABLED == 1)
+#define ADC_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#endif
+
+
+/* SAADC */
+#define SAADC_ENABLED 1
+
+#if (SAADC_ENABLED == 1)
+#define SAADC_CONFIG_RESOLUTION      NRF_SAADC_RESOLUTION_10BIT
+#define SAADC_CONFIG_OVERSAMPLE      NRF_SAADC_OVERSAMPLE_DISABLED
+#define SAADC_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#endif
+
+/* PDM */
+#define PDM_ENABLED 0
+
+#if (PDM_ENABLED == 1)
+#define PDM_CONFIG_MODE            NRF_PDM_MODE_MONO
+#define PDM_CONFIG_EDGE            NRF_PDM_EDGE_LEFTFALLING
+#define PDM_CONFIG_CLOCK_FREQ      NRF_PDM_FREQ_1032K
+#define PDM_CONFIG_IRQ_PRIORITY    APP_IRQ_PRIORITY_LOW
+#endif
+
+/* COMP */
+#define COMP_ENABLED 0
+
+#if (COMP_ENABLED == 1)
+#define COMP_CONFIG_REF     		NRF_COMP_REF_Int1V8
+#define COMP_CONFIG_MAIN_MODE		NRF_COMP_MAIN_MODE_SE
+#define COMP_CONFIG_SPEED_MODE		NRF_COMP_SP_MODE_High
+#define COMP_CONFIG_HYST			NRF_COMP_HYST_NoHyst
+#define COMP_CONFIG_ISOURCE			NRF_COMP_ISOURCE_Off
+#define COMP_CONFIG_IRQ_PRIORITY 	APP_IRQ_PRIORITY_LOW
+#define COMP_CONFIG_INPUT        	NRF_COMP_INPUT_0
+#endif
+
+/* LPCOMP */
+#define LPCOMP_ENABLED 0
+
+#if (LPCOMP_ENABLED == 1)
+#define LPCOMP_CONFIG_REFERENCE    NRF_LPCOMP_REF_SUPPLY_4_8
+#define LPCOMP_CONFIG_DETECTION    NRF_LPCOMP_DETECT_DOWN
+#define LPCOMP_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_LOW
+#define LPCOMP_CONFIG_INPUT        NRF_LPCOMP_INPUT_0
+#endif
+
+/* WDT */
+#define WDT_ENABLED 0
+
+#if (WDT_ENABLED == 1)
+#define WDT_CONFIG_BEHAVIOUR     NRF_WDT_BEHAVIOUR_RUN_SLEEP
+#define WDT_CONFIG_RELOAD_VALUE  2000
+#define WDT_CONFIG_IRQ_PRIORITY  APP_IRQ_PRIORITY_HIGH
+#endif
+
+/* SWI EGU */
+#ifdef NRF52
+    #define EGU_ENABLED 0
+#endif
+
+/* I2S */
+#define I2S_ENABLED 0
+
+#if (I2S_ENABLED == 1)
+#define I2S_CONFIG_SCK_PIN      22
+#define I2S_CONFIG_LRCK_PIN     23
+#define I2S_CONFIG_MCK_PIN      NRF_DRV_I2S_PIN_NOT_USED
+#define I2S_CONFIG_SDOUT_PIN    24
+#define I2S_CONFIG_SDIN_PIN     25
+#define I2S_CONFIG_IRQ_PRIORITY APP_IRQ_PRIORITY_HIGH
+#define I2S_CONFIG_MASTER       NRF_I2S_MODE_MASTER
+#define I2S_CONFIG_FORMAT       NRF_I2S_FORMAT_I2S
+#define I2S_CONFIG_ALIGN        NRF_I2S_ALIGN_LEFT
+#define I2S_CONFIG_SWIDTH       NRF_I2S_SWIDTH_16BIT
+#define I2S_CONFIG_CHANNELS     NRF_I2S_CHANNELS_STEREO
+#define I2S_CONFIG_MCK_SETUP    NRF_I2S_MCK_32MDIV8
+#define I2S_CONFIG_RATIO        NRF_I2S_RATIO_256X
+#endif
+
+#include "nrf_drv_config_validation.h"
+
+#endif // NRF_DRV_CONFIG_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf52/nrf_mbr.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf52/nrf_mbr.h
new file mode 100644
index 0000000000..9506d327d3
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf52/nrf_mbr.h
@@ -0,0 +1,220 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @defgroup nrf_mbr_api Master Boot Record API
+  @{
+
+  @brief APIs for updating SoftDevice and BootLoader
+
+*/
+
+/* Header guard */
+#ifndef NRF_MBR_H__
+#define NRF_MBR_H__
+
+#include "nrf_svc.h"
+#include <stdint.h>
+
+#ifndef NRF52
+#error "This header file shall only be included for nRF52 projects"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_MBR_DEFINES Defines
+ * @{ */
+
+/**@brief MBR SVC Base number. */
+#define MBR_SVC_BASE            (0x18)
+
+/**@brief Page size in words. */
+#define MBR_PAGE_SIZE_IN_WORDS  (1024)
+
+/** @brief The size that must be reserved for the MBR when a softdevice is written to flash.
+This is the offset where the first byte of the softdevice hex file is written.*/
+#define MBR_SIZE                (0x1000)
+
+/** @} */
+
+/** @addtogroup NRF_MBR_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF Master Boot Record API SVC numbers. */
+enum NRF_MBR_SVCS
+{
+  SD_MBR_COMMAND = MBR_SVC_BASE, /**< ::sd_mbr_command */
+};
+
+/**@brief Possible values for ::sd_mbr_command_t.command */
+enum NRF_MBR_COMMANDS
+{
+  SD_MBR_COMMAND_COPY_BL,               /**< Copy a new BootLoader. @see sd_mbr_command_copy_bl_t */
+  SD_MBR_COMMAND_COPY_SD,               /**< Copy a new SoftDevice. @see ::sd_mbr_command_copy_sd_t*/
+  SD_MBR_COMMAND_INIT_SD,               /**< Init forwarding interrupts to SD, and run reset function in SD*/
+  SD_MBR_COMMAND_COMPARE,               /**< This command works like memcmp. @see ::sd_mbr_command_compare_t*/
+  SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET, /**< Start forwarding all exception to this address @see ::sd_mbr_command_vector_table_base_set_t*/
+};
+
+/** @} */
+
+/** @addtogroup NRF_MBR_TYPES Types
+ * @{ */
+
+/**@brief This command copies part of a new SoftDevice
+ * The destination area is erased before copying.
+ * If dst is in the middle of a flash page, that whole flash page will be erased.
+ * If (dst+len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ * The user of this function is responsible for setting the BPROT registers.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of the memory blocks where copied correctly.
+ * @retval ::NRF_ERROR_INTERNAL indicates that the contents of the memory blocks where not verified correctly after copying.
+ */
+typedef struct
+{
+  uint32_t *src;  /**< Pointer to the source of data to be copied.*/
+  uint32_t *dst;  /**< Pointer to the destination where the content is to be copied.*/
+  uint32_t len;   /**< Number of 32 bit words to copy. Must be a multiple of @ref MBR_PAGE_SIZE_IN_WORDS words.*/
+} sd_mbr_command_copy_sd_t;
+
+
+/**@brief This command works like memcmp, but takes the length in words.
+ *
+ * @retval ::NRF_SUCCESS indicates that the contents of both memory blocks are equal.
+ * @retval ::NRF_ERROR_NULL indicates that the contents of the memory blocks are not equal.
+ */
+typedef struct
+{
+  uint32_t *ptr1; /**< Pointer to block of memory. */
+  uint32_t *ptr2; /**< Pointer to block of memory. */
+  uint32_t len;   /**< Number of 32 bit words to compare.*/
+} sd_mbr_command_compare_t;
+
+
+/**@brief This command copies a new BootLoader.
+ *  With this command, destination of BootLoader is always the address written in NRF_UICR->BOOTADDR.
+ *
+ *  Destination is erased by this function.
+ *  If (destination+bl_len) is in the middle of a flash page, that whole flash page will be erased.
+ *
+ *  This function will use PROTENSET to protect the flash that is not intended to be written.
+ *
+ *  On Success, this function will not return. It will start the new BootLoader from reset-vector as normal.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_FORBIDDEN if NRF_UICR->BOOTADDR is not set.
+ * @retval ::NRF_ERROR_INVALID_LENGTH if parameters attempts to read or write outside flash area.
+ * @retval ::NRF_ERROR_NO_MEM if no parameter page is provided (see sds for more info)
+ */
+typedef struct
+{
+  uint32_t *bl_src;  /**< Pointer to the source of the Bootloader to be be copied.*/
+  uint32_t bl_len;   /**< Number of 32 bit words to copy for BootLoader. */
+} sd_mbr_command_copy_bl_t;
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the MBR
+ *
+ * Once this function has been called, this address is where the MBR will start to forward interrupts to after a reset.
+ *
+ * To restore default forwarding this function should be called with @param address set to 0.
+ * The MBR will then start forwarding to interrupts to the address in NFR_UICR->BOOTADDR or to the SoftDevice if the BOOTADDR is not set.
+ *
+ * On Success, this function will not return. It will reset the device.
+ *
+ * @retval ::NRF_ERROR_INTERNAL indicates an internal error that should not happen.
+ * @retval ::NRF_ERROR_INVALID_ADDR if parameter address is outside of the flash size.
+ * @retval ::NRF_ERROR_NO_MEM if no parameter page is provided (see sds for more info)
+ */
+typedef struct
+{
+  uint32_t address; /**< The base address of the interrupt vector table for forwarded interrupts.*/
+} sd_mbr_command_vector_table_base_set_t;
+
+
+typedef struct
+{
+  uint32_t command;  /**< type of command to be issued see @ref NRF_MBR_COMMANDS. */
+  union
+  {
+    sd_mbr_command_copy_sd_t copy_sd;  /**< Parameters for copy SoftDevice.*/
+    sd_mbr_command_compare_t compare;  /**< Parameters for verify.*/
+    sd_mbr_command_copy_bl_t copy_bl;  /**< Parameters for copy BootLoader. Requires parameter page. */
+    sd_mbr_command_vector_table_base_set_t base_set; /**< Parameters for vector table base set. Requires parameter page.*/
+  } params;
+} sd_mbr_command_t;
+
+/** @} */
+
+/** @addtogroup NRF_MBR_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Issue Master Boot Record commands
+ *
+ * Commands used when updating a SoftDevice and bootloader.
+ *
+ * The SD_MBR_COMMAND_COPY_BL and SD_MBR_COMMAND_VECTOR_TABLE_BASE_SET requires parameters to be
+ * retained by the MBR when resetting the IC. This is done in a separate flash page
+ * provided by the application. The uicr register UICR.NRFFW[1] must be set
+ * to an address corresponding to a page in the application flash space. This page will be cleared
+ * by the MBR and used to store the command before reset. When the UICR.NRFFW[1] field is set
+ * the page it refers to must not be used by the application. If the UICR.NRFFW[1] is set to
+ * 0xFFFFFFFF (the default) MBR commands which use flash will be unavailable and return
+ * NRF_ERROR_NO_MEM.
+ *
+ * @param[in]  param Pointer to a struct describing the command.
+ *
+ * @note for retvals see ::sd_mbr_command_copy_sd_t ::sd_mbr_command_copy_bl_t ::sd_mbr_command_compare_t ::sd_mbr_command_vector_table_base_set_t
+ *
+ * @retval NRF_ERROR_NO_MEM if UICR.NRFFW[1] is not set (i.e. is 0xFFFFFFFF).
+ * @retval NRF_ERROR_INVALID_PARAM if an invalid command is given.
+*/
+SVCALL(SD_MBR_COMMAND, uint32_t, sd_mbr_command(sd_mbr_command_t* param));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_MBR_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble.h
new file mode 100644
index 0000000000..71e3984776
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble.h
@@ -0,0 +1,635 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON BLE SoftDevice Common
+  @{
+  @defgroup ble_api Events, type definitions and API calls
+  @{
+
+  @brief Module independent events, type definitions and API calls for the BLE SoftDevice.
+
+ */
+
+#ifndef NRF_BLE_H__
+#define NRF_BLE_H__
+
+#include "nrf_ble_ranges.h"
+#include "nrf_ble_types.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble_l2cap.h"
+#include "nrf_ble_gatt.h"
+#include "nrf_ble_gattc.h"
+#include "nrf_ble_gatts.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_COMMON_ENUMERATIONS Enumerations
+ * @{ */
+
+/**
+ * @brief Common API SVC numbers.
+ */
+enum BLE_COMMON_SVCS
+{
+  SD_BLE_ENABLE = BLE_SVC_BASE,         /**< Enable and initialize the BLE stack */
+  SD_BLE_EVT_GET,                       /**< Get an event from the pending events queue. */
+  SD_BLE_TX_PACKET_COUNT_GET,           /**< Get the total number of available application transmission packets for a particular connection. */
+  SD_BLE_UUID_VS_ADD,                   /**< Add a Vendor Specific UUID. */
+  SD_BLE_UUID_DECODE,                   /**< Decode UUID bytes. */
+  SD_BLE_UUID_ENCODE,                   /**< Encode UUID bytes. */
+  SD_BLE_VERSION_GET,                   /**< Get the local version information (company id, Link Layer Version, Link Layer Subversion). */
+  SD_BLE_USER_MEM_REPLY,                /**< User Memory Reply. */
+  SD_BLE_OPT_SET,                       /**< Set a BLE option. */
+  SD_BLE_OPT_GET,                       /**< Get a BLE option. */
+};
+
+  /**
+   * @brief BLE Module Independent Event IDs.
+   */
+enum BLE_COMMON_EVTS
+{
+  BLE_EVT_TX_COMPLETE  = BLE_EVT_BASE,  /**< Transmission Complete. @ref ble_evt_tx_complete_t */
+  BLE_EVT_USER_MEM_REQUEST,             /**< User Memory request. @ref ble_evt_user_mem_request_t */
+  BLE_EVT_USER_MEM_RELEASE              /**< User Memory release. @ref ble_evt_user_mem_release_t */
+};
+
+/**@brief BLE connection bandwidth types.
+ * Bandwidth types supported by the SoftDevice in packets per connection interval.
+ */
+enum BLE_CONN_BWS
+{
+  BLE_CONN_BW_NONE = 0,
+  BLE_CONN_BW_LOW,
+  BLE_CONN_BW_MID,
+  BLE_CONN_BW_HIGH
+};
+
+/**@brief Common Option IDs.
+ * IDs that uniquely identify a common option.
+ */
+enum BLE_COMMON_OPTS
+{
+  BLE_COMMON_OPT_CONN_BW = BLE_OPT_BASE,     /**< Bandwidth configuration @ref ble_common_opt_conn_bw_t */
+  BLE_COMMON_OPT_PA_LNA                      /**< PA and LNA options */
+};
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_DEFINES Defines
+ * @{ */
+
+/** @brief  Required pointer alignment for BLE Events.
+*/
+#define BLE_EVTS_PTR_ALIGNMENT    4
+
+/** @defgroup BLE_USER_MEM_TYPES User Memory Types
+ * @{ */
+#define BLE_USER_MEM_TYPE_INVALID               0x00  /**< Invalid User Memory Types. */
+#define BLE_USER_MEM_TYPE_GATTS_QUEUED_WRITES   0x01  /**< User Memory for GATTS queued writes. */
+/** @} */
+
+/** @defgroup BLE_UUID_VS_COUNTS Vendor Specific UUID counts
+ * @{
+ */
+#define BLE_UUID_VS_COUNT_MIN         1    /**< Minimum VS UUID count. */
+#define BLE_UUID_VS_COUNT_DEFAULT     0    /**< Use the default VS UUID count (10 for this version of the SoftDevice). */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_STRUCTURES Structures
+ * @{ */
+
+/**@brief User Memory Block. */
+typedef struct
+{
+  uint8_t          *p_mem;      /**< Pointer to the start of the user memory block. */
+  uint16_t          len;        /**< Length in bytes of the user memory block. */
+} ble_user_mem_block_t;
+
+/**
+ * @brief Event structure for @ref BLE_EVT_TX_COMPLETE.
+ */
+typedef struct
+{
+  uint8_t count;                        /**< Number of packets transmitted. */
+} ble_evt_tx_complete_t;
+
+/**@brief Event structure for @ref BLE_EVT_USER_MEM_REQUEST. */
+typedef struct
+{
+  uint8_t                     type;     /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
+} ble_evt_user_mem_request_t;
+
+/**@brief Event structure for @ref BLE_EVT_USER_MEM_RELEASE. */
+typedef struct
+{
+  uint8_t                     type;       /**< User memory type, see @ref BLE_USER_MEM_TYPES. */
+  ble_user_mem_block_t        mem_block;  /**< User memory block */
+} ble_evt_user_mem_release_t;
+
+
+/**@brief Event structure for events not associated with a specific function module. */
+typedef struct
+{
+  uint16_t conn_handle;                 /**< Connection Handle on which this event occurred. */
+  union
+  {
+    ble_evt_tx_complete_t           tx_complete;        /**< Transmission Complete. */
+    ble_evt_user_mem_request_t      user_mem_request;   /**< User Memory Request Event Parameters. */
+    ble_evt_user_mem_release_t      user_mem_release;   /**< User Memory Release Event Parameters. */
+  } params;
+} ble_common_evt_t;
+
+/**@brief BLE Event header. */
+typedef struct
+{
+  uint16_t evt_id;                /**< Value from a BLE_<module>_EVT series. */
+  uint16_t evt_len;               /**< Length in octets including this header. */
+} ble_evt_hdr_t;
+
+/**@brief Common BLE Event type, wrapping the module specific event reports. */
+typedef struct
+{
+  ble_evt_hdr_t header;           /**< Event header. */
+  union
+  {
+    ble_common_evt_t  common_evt; /**< Common Event, evt_id in BLE_EVT_* series. */
+    ble_gap_evt_t     gap_evt;    /**< GAP originated event, evt_id in BLE_GAP_EVT_* series. */
+    ble_l2cap_evt_t   l2cap_evt;  /**< L2CAP originated event, evt_id in BLE_L2CAP_EVT* series. */
+    ble_gattc_evt_t   gattc_evt;  /**< GATT client originated event, evt_id in BLE_GATTC_EVT* series. */
+    ble_gatts_evt_t   gatts_evt;  /**< GATT server originated event, evt_id in BLE_GATTS_EVT* series. */
+  } evt;
+} ble_evt_t;
+
+
+/**
+ * @brief Version Information.
+ */
+typedef struct
+{
+  uint8_t   version_number;    /**< Link Layer Version number for BT 4.1 spec is 7 (https://www.bluetooth.org/en-us/specification/assigned-numbers/link-layer). */
+  uint16_t  company_id;        /**< Company ID, Nordic Semiconductor's company ID is 89 (0x0059) (https://www.bluetooth.org/apps/content/Default.aspx?doc_id=49708). */
+  uint16_t  subversion_number; /**< Link Layer Sub Version number, corresponds to the SoftDevice Config ID or Firmware ID (FWID). */
+} ble_version_t;
+
+/* @brief: Configuration parameters for the PA and LNA. */
+typedef struct
+{
+     uint8_t enable :1;      /**< Enable toggling for this amplifier */
+     uint8_t active_high :1; /**< Set the pin to be active high */
+     uint8_t gpio_pin :6;    /**< The GPIO pin to toggle for this amplifier */
+} ble_pa_lna_cfg_t;
+
+/*
+ * @brief PA & LNA GPIO toggle configuration
+ *
+ * This option configures the SoftDevice to toggle pins when the radio is active for use with a power amplifier and/or
+ * a low noise amplifier.
+ *
+ * Toggling the pins is achieved by using two PPI channels and a GPIOTE channel. The hardware channel IDs are provided
+ * by the application and should be regarded as reserved as long as any PA/LNA toggling is enabled.
+ *
+ * @note  @ref sd_ble_opt_get is not supported for this option.
+ * @note  This feature is only supported for nRF52, on nRF51 @ref NRF_ERROR_NOT_SUPPORTED will always be returned.
+ * @note  Setting this option while the radio is in use (i.e. any of the roles are active) may have undefined consequences
+ * and must be avoided by the application.
+ *
+ */
+typedef struct
+{
+   ble_pa_lna_cfg_t pa_cfg;   /**< Power Amplifier configuration */
+   ble_pa_lna_cfg_t lna_cfg;  /**< Low Noise Amplifier configuration */
+
+   uint8_t ppi_ch_id_set;     /**< PPI channel used for radio pin setting */
+   uint8_t ppi_ch_id_clr;     /**< PPI channel used for radio pin clearing */
+   uint8_t gpiote_ch_id;      /**< GPIOTE channel used for radio pin toggling */
+} ble_common_opt_pa_lna_t;
+
+/**
+ * @brief BLE connection bandwidth configuration parameters
+ */
+typedef struct
+{
+  uint8_t conn_bw_tx;   /**< Connection bandwidth configuration for transmission, see @ref BLE_CONN_BWS.*/
+  uint8_t conn_bw_rx;   /**< Connection bandwidth configuration for reception, see @ref BLE_CONN_BWS.*/
+} ble_conn_bw_t;
+
+/**@brief BLE connection specific bandwidth configuration parameters.
+ *
+ * This can be used with @ref sd_ble_opt_set to set the bandwidth configuration to be used when creating connections.
+ *
+ * Call @ref sd_ble_opt_set with this option prior to calling @ref sd_ble_gap_adv_start or @ref sd_ble_gap_connect.
+ *
+ * The bandwidth configurations set via @ref sd_ble_opt_set are maintained separately for central and peripheral
+ * connections. The given configurations are used for all future connections of the role indicated in this structure
+ * unless they are changed by subsequent @ref sd_ble_opt_set calls.
+ *
+ * @note When this option is not used, the SoftDevice will use the default options:
+ * - @ref BLE_CONN_BW_HIGH for @ref BLE_GAP_ROLE_PERIPH connections (both transmission and reception).
+ * - @ref BLE_CONN_BW_MID for @ref BLE_GAP_ROLE_CENTRAL connections (both transmisison and reception).
+ * This option allows the application to selectively override these defaults for each role.
+ *
+ * @note The global memory pool configuration can be set with the @ref ble_conn_bw_counts_t configuration parameter, which
+ * is provided to @ref sd_ble_enable.
+ *
+ * @note Please refer to SoftDevice Specification for more information on bandwidth configuration.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::BLE_ERROR_INVALID_ROLE The role is invalid.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid bandwidth configuration parameters.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED If the combination of role and bandwidth configuration is not supported.
+ */
+typedef struct
+{
+  uint8_t            role;     /**< BLE role of the connection, see @ref BLE_GAP_ROLES. */
+  ble_conn_bw_t      conn_bw;  /**< Bandwidth configuration parameters. */
+} ble_common_opt_conn_bw_t;
+
+/**@brief Option structure for common options. */
+typedef union
+{
+  ble_common_opt_conn_bw_t conn_bw;       /**< Parameters for the connection bandwidth option. */
+  ble_common_opt_pa_lna_t  pa_lna;        /**< Parameters for controlling PA and LNA pin toggling. */
+} ble_common_opt_t;
+
+/**@brief Common BLE Option type, wrapping the module specific options. */
+typedef union
+{
+  ble_common_opt_t  common_opt;         /**< COMMON options, opt_id in @ref BLE_COMMON_OPTS series. */
+  ble_gap_opt_t     gap_opt;            /**< GAP option, opt_id in @ref BLE_GAP_OPTS series. */
+} ble_opt_t;
+
+/**
+ * @brief BLE bandwidth count parameters
+ *
+ * These parameters are used to configure the memory pools allocated within the SoftDevice for application packets
+ * (both transmission and reception) for all connections.
+ *
+ * @note The sum of all three counts must add up to the sum of @ref ble_gap_enable_params_t::central_conn_count and
+ * @ref ble_gap_enable_params_t::periph_conn_count in @ref ble_gap_enable_params_t.
+ */
+typedef struct {
+  uint8_t high_count;   /**< Total number of high bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+  uint8_t mid_count;    /**< Total number of medium bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+  uint8_t low_count;    /**< Total number of low bandwidth TX or RX memory pools available to the application at runtime for all active connections. */
+} ble_conn_bw_count_t;
+
+/**
+ * @brief BLE bandwidth global memory pool configuration parameters
+ *
+ * These configuration parameters are used to set the amount of memory dedicated to application packets for
+ * all connections. The application should specify the most demanding configuration for the intended use.
+ *
+ * Please refer to the SoftDevice Specification for more information on bandwidth configuration.
+ *
+ * @note Each connection created at runtime requires both a TX and an RX memory pool. By the use of these configuration
+ * parameters, the application can decide the size and total number of the global memory pools that will be later
+ * available for connection creation.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ */
+typedef struct {
+  ble_conn_bw_count_t tx_counts;   /**< Global memory pool configuration for transmission.*/
+  ble_conn_bw_count_t rx_counts;   /**< Global memory pool configuration for reception.*/
+} ble_conn_bw_counts_t;
+
+/**
+ * @brief BLE Common Initialization parameters.
+ *
+ * @note If @ref p_conn_bw_counts is NULL the SoftDevice will assume default bandwidth configuration for all connections.
+ * To fit a custom bandwidth configuration requirement, the application developer may have to specify a custom memory
+ * pool configuration here. See @ref ble_common_opt_conn_bw_t for bandwidth configuration of individual connections.
+ * Please refer to the SoftDevice Specification for more information on bandwidth configuration.
+ */
+typedef struct
+{
+  uint16_t                  vs_uuid_count;     /**< Maximum number of 128-bit, Vendor Specific UUID bases to allocate. */
+  ble_conn_bw_counts_t      *p_conn_bw_counts; /**< Bandwidth configuration parameters or NULL for defaults. */
+} ble_common_enable_params_t;
+
+/**
+ * @brief BLE Initialization parameters.
+ */
+typedef struct
+{
+  ble_common_enable_params_t        common_enable_params;  /**< Common init parameters @ref ble_common_enable_params_t. */
+  ble_gap_enable_params_t           gap_enable_params;   /**< GAP init parameters @ref ble_gap_enable_params_t. */
+  ble_gatts_enable_params_t         gatts_enable_params; /**< GATTS init parameters @ref ble_gatts_enable_params_t. */
+} ble_enable_params_t;
+
+/** @} */
+
+/** @addtogroup BLE_COMMON_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Enable the BLE stack
+ *
+ * @param[in, out] p_ble_enable_params Pointer to ble_enable_params_t
+ * @param[in, out] p_app_ram_base      Pointer to a variable containing the start address of the application RAM region
+ * (APP_RAM_BASE). On return, this will contain the minimum start address of the application RAM region required by the
+ * SoftDevice for this configuration. Calling @ref sd_ble_enable() with *p_app_ram_base set to 0 can be used during
+ * development to find out how much memory a specific configuration will need.
+ *
+ * @note The memory requirement for a specific configuration will not increase between SoftDevices with the same major
+ * version number.
+ *
+ * @note At runtime the IC's RAM is split into 2 regions: The SoftDevice RAM region is located between 0x20000000 and
+ *       APP_RAM_BASE-1 and the application's RAM region is located between APP_RAM_BASE and the start of the call stack.
+ *
+ * @details This call initializes the BLE stack, no other BLE related function can be called before this one.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_ENABLE}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS              The BLE stack has been initialized successfully.
+ * @retval ::NRF_ERROR_INVALID_STATE  The BLE stack had already been initialized and cannot be reinitialized.
+ * @retval ::NRF_ERROR_INVALID_ADDR   Invalid or not sufficiently aligned pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_LENGTH The specified Attribute Table size is either too small or not a multiple of 4.
+ *                                    The minimum acceptable size is defined by @ref BLE_GATTS_ATTR_TAB_SIZE_MIN.
+ * @retval ::NRF_ERROR_INVALID_PARAM  Incorrectly configured VS UUID count or connection count parameters.
+ * @retval ::NRF_ERROR_NO_MEM         The amount of memory assigned to the SoftDevice by *p_app_ram_base is not
+ *                                    large enough to fit this configuration's memory requirement. Check *p_app_ram_base
+ *                                    and set the start address of the application RAM region accordingly.
+ * @retval ::NRF_ERROR_CONN_COUNT     The requested number of connections exceeds the maximum supported by the SoftDevice.
+ *                                    Please refer to the SoftDevice Specification for more information on role configuration.
+ */
+SVCALL(SD_BLE_ENABLE, uint32_t, sd_ble_enable(ble_enable_params_t * p_ble_enable_params, uint32_t * p_app_ram_base));
+
+/**@brief Get an event from the pending events queue.
+ *
+ * @param[out] p_dest Pointer to buffer to be filled in with an event, or NULL to retrieve the event length.
+ *                    This buffer <b>must be 4-byte aligned in memory</b>.
+ * @param[in, out] p_len Pointer the length of the buffer, on return it is filled with the event length.
+ *
+ * @details This call allows the application to pull a BLE event from the BLE stack. The application is signaled that
+ * an event is available from the BLE stack by the triggering of the SD_EVT_IRQn interrupt.
+ * The application is free to choose whether to call this function from thread mode (main context) or directly from the
+ * Interrupt Service Routine that maps to SD_EVT_IRQn. In any case however, and because the BLE stack runs at a higher
+ * priority than the application, this function should be called in a loop (until @ref NRF_ERROR_NOT_FOUND is returned)
+ * every time SD_EVT_IRQn is raised to ensure that all available events are pulled from the BLE stack. Failure to do so
+ * could potentially leave events in the internal queue without the application being aware of this fact. Sizing the
+ * p_dest buffer is equally important, since the application needs to provide all the memory necessary for the event to
+ * be copied into application memory. If the buffer provided is not large enough to fit the entire contents of the event,
+ * @ref NRF_ERROR_DATA_SIZE will be returned and the application can then call again with a larger buffer size.
+ * Please note that because of the variable length nature of some events, sizeof(ble_evt_t) will not always be large
+ * enough to fit certain events, and so it is the application's responsibility to provide an amount of memory large
+ * enough so that the relevant event is copied in full. The application may "peek" the event length by providing p_dest
+ * as a NULL pointer and inspecting the value of *p_len upon return:
+ *
+ *     \code
+ *     uint16_t len;
+ *     errcode = sd_ble_evt_get(NULL, &len);
+ *     \endcode
+ *
+ * @note The pointer supplied must be aligned to the extend defined by @ref BLE_EVTS_PTR_ALIGNMENT
+ *
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_IRQ_EVT_MSC}
+ * @mmsc{@ref BLE_COMMON_THREAD_EVT_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Event pulled and stored into the supplied buffer.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid or not sufficiently aligned pointer supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND No events ready to be pulled.
+ * @retval ::NRF_ERROR_DATA_SIZE Event ready but could not fit into the supplied buffer.
+ */
+SVCALL(SD_BLE_EVT_GET, uint32_t, sd_ble_evt_get(uint8_t *p_dest, uint16_t *p_len));
+
+
+/**@brief Get the total number of available guaranteed application transmission packets for a particular connection.
+ *
+ * @details This call allows the application to obtain the total number of guaranteed application transmission packets
+ * available for a connection. Please note that this does not return the number of free packets, but rather the total
+ * amount of them for that particular connection. The application has two options to handle transmitting application packets:
+ * - Use a simple arithmetic calculation: after connection creation time the application should use this function to
+ * find out the total amount of guaranteed packets available to it and store it in a variable.
+ * Every time a packet is successfully queued for a transmission on this connection using any of the exposed functions in
+ * this  BLE API, the application should decrement that variable. Conversely, whenever a @ref BLE_EVT_TX_COMPLETE event
+ * with the conn_handle matching the particular connection is received by the application, it should retrieve the count
+ * field in such event and add that number to the same variable storing the number of available guaranteed packets. This
+ * mechanism allows the application to be aware at any time of the number of guaranteed application packets available for
+ * each of the active connections, and therefore it can know with certainty whether it is possible to send more data or
+ * it has to wait for a @ref BLE_EVT_TX_COMPLETE event before it proceeds.
+ * The application can still pursue transmissions when the number of guaranteed application packets available is smaller
+ * than or equal to zero, but successful queuing of the tranmsission is not guaranteed.
+ * - Choose to simply not keep track of available packets at all, and instead handle the @ref BLE_ERROR_NO_TX_PACKETS error
+ * by queueing the packet to be transmitted and try again as soon as a @ref BLE_EVT_TX_COMPLETE event arrives.
+ *
+ * The API functions that <b>may</b> consume an application packet depending on the parameters supplied to them can be found below:
+ * - @ref sd_ble_gattc_write (write without response only)
+ * - @ref sd_ble_gatts_hvx (notifications only)
+ * - @ref sd_ble_l2cap_tx (all packets)
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_count Pointer to a uint8_t which will contain the number of application transmission packets upon
+ *                     successful return.
+ * @mscs
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Number of application transmission packets retrieved successfully.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_TX_PACKET_COUNT_GET, uint32_t, sd_ble_tx_packet_count_get(uint16_t conn_handle, uint8_t *p_count));
+
+
+/**@brief Add a Vendor Specific UUID.
+ *
+ * @details This call enables the application to add a vendor specific UUID to the BLE stack's table, for later use
+ * all other modules and APIs. This then allows the application to use the shorter, 24-bit @ref ble_uuid_t format
+ * when dealing with both 16-bit and 128-bit UUIDs without having to check for lengths and having split code paths.
+ * The way that this is accomplished is by extending the grouping mechanism that the Bluetooth SIG standard base
+ * UUID uses for all other 128-bit UUIDs. The type field in the @ref ble_uuid_t structure is an index (relative to
+ * @ref BLE_UUID_TYPE_VENDOR_BEGIN) to the table populated by multiple calls to this function, and the uuid field
+ * in the same structure contains the 2 bytes at indices 12 and 13. The number of possible 128-bit UUIDs available to
+ * the application is therefore the number of Vendor Specific UUIDs added with the help of this function times 65536,
+ * although restricted to modifying bytes 12 and 13 for each of the entries in the supplied array.
+ *
+ * @note Bytes 12 and 13 of the provided UUID will not be used internally, since those are always replaced by
+ * the 16-bit uuid field in @ref ble_uuid_t.
+ *
+ * @note If a UUID is already present in the BLE stack's internal table, the corresponding index will be returned in
+ * p_uuid_type along with an NRF_SUCCESS error code.
+ *
+ * @param[in]  p_vs_uuid    Pointer to a 16-octet (128-bit) little endian Vendor Specific UUID disregarding
+ *                          bytes 12 and 13.
+ * @param[out] p_uuid_type  Pointer to a uint8_t where the type field in @ref ble_uuid_t corresponding to this UUID will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added the Vendor Specific UUID.
+ * @retval ::NRF_ERROR_INVALID_ADDR If p_vs_uuid or p_uuid_type is NULL or invalid.
+ * @retval ::NRF_ERROR_NO_MEM If there are no more free slots for VS UUIDs.
+ */
+SVCALL(SD_BLE_UUID_VS_ADD, uint32_t, sd_ble_uuid_vs_add(ble_uuid128_t const *p_vs_uuid, uint8_t *p_uuid_type));
+
+
+/** @brief Decode little endian raw UUID bytes (16-bit or 128-bit) into a 24 bit @ref ble_uuid_t structure.
+ *
+ * @details The raw UUID bytes excluding bytes 12 and 13 (i.e. bytes 0-11 and 14-15) of p_uuid_le are compared
+ * to the corresponding ones in each entry of the table of vendor specific UUIDs populated with @ref sd_ble_uuid_vs_add
+ * to look for a match. If there is such a match, bytes 12 and 13 are returned as p_uuid->uuid and the index
+ * relative to @ref BLE_UUID_TYPE_VENDOR_BEGIN as p_uuid->type.
+ *
+ * @note If the UUID length supplied is 2, then the type set by this call will always be @ref BLE_UUID_TYPE_BLE.
+ *
+ * @param[in]   uuid_le_len Length in bytes of the buffer pointed to by p_uuid_le (must be 2 or 16 bytes).
+ * @param[in]   p_uuid_le   Pointer pointing to little endian raw UUID bytes.
+ * @param[out]  p_uuid      Pointer to a @ref ble_uuid_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Successfully decoded into the @ref ble_uuid_t structure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_LENGTH Invalid UUID length.
+ * @retval ::NRF_ERROR_NOT_FOUND For a 128-bit UUID, no match in the populated table of UUIDs.
+ */
+SVCALL(SD_BLE_UUID_DECODE, uint32_t, sd_ble_uuid_decode(uint8_t uuid_le_len, uint8_t const *p_uuid_le, ble_uuid_t *p_uuid));
+
+
+/** @brief Encode a @ref ble_uuid_t structure into little endian raw UUID bytes (16-bit or 128-bit).
+ *
+ * @note The pointer to the destination buffer p_uuid_le may be NULL, in which case only the validity and size of p_uuid is computed.
+ *
+ * @param[in]   p_uuid        Pointer to a @ref ble_uuid_t structure that will be encoded into bytes.
+ * @param[out]  p_uuid_le_len Pointer to a uint8_t that will be filled with the encoded length (2 or 16 bytes).
+ * @param[out]  p_uuid_le     Pointer to a buffer where the little endian raw UUID bytes (2 or 16) will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully encoded into the buffer.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid UUID type.
+ */
+SVCALL(SD_BLE_UUID_ENCODE, uint32_t, sd_ble_uuid_encode(ble_uuid_t const *p_uuid, uint8_t *p_uuid_le_len, uint8_t *p_uuid_le));
+
+
+/**@brief Get Version Information.
+ *
+ * @details This call allows the application to get the BLE stack version information.
+ *
+ * @param[out] p_version Pointer to a ble_version_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS  Version information stored successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy (typically doing a locally-initiated disconnection procedure).
+ */
+SVCALL(SD_BLE_VERSION_GET, uint32_t, sd_ble_version_get(ble_version_t *p_version));
+
+
+/**@brief Provide a user memory block.
+ *
+ * @note This call can only be used as a response to a @ref BLE_EVT_USER_MEM_REQUEST event issued to the application.
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in,out] p_block Pointer to a user memory block structure.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully queued a response to the peer.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection state or no execute write request pending.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_USER_MEM_REPLY, uint32_t, sd_ble_user_mem_reply(uint16_t conn_handle, ble_user_mem_block_t const *p_block));
+
+/**@brief Set a BLE option.
+ *
+ * @details This call allows the application to set the value of an option.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
+ * @mmsc{@ref BLE_COMMON_CONF_BW}
+ * @endmscs
+ *
+ * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
+ * @param[in] p_opt Pointer to a ble_opt_t structure containing the option value.
+ *
+ * @retval ::NRF_SUCCESS  Option set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Unable to set the parameter at this time.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
+ */
+SVCALL(SD_BLE_OPT_SET, uint32_t, sd_ble_opt_set(uint32_t opt_id, ble_opt_t const *p_opt));
+
+
+/**@brief Get a BLE option.
+ *
+ * @details This call allows the application to retrieve the value of an option.
+ *
+ * @param[in] opt_id Option ID, see @ref BLE_COMMON_OPTS and @ref BLE_GAP_OPTS.
+ * @param[out] p_opt Pointer to a ble_opt_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS  Option retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Unable to retrieve the parameter at this time.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy or the previous procedure has not completed.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED This option is not supported.
+ *
+ */
+SVCALL(SD_BLE_OPT_GET, uint32_t, sd_ble_opt_get(uint32_t opt_id, ble_opt_t *p_opt));
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_BLE_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_err.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_err.h
new file mode 100644
index 0000000000..7eaf23d125
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_err.h
@@ -0,0 +1,93 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @addtogroup  nrf_error
+  @{
+    @ingroup BLE_COMMON
+  @}
+
+  @defgroup ble_err General error codes
+  @{
+
+  @brief General error code definitions for the BLE API.
+
+  @ingroup BLE_COMMON
+*/
+#ifndef NRF_BLE_ERR_H__
+#define NRF_BLE_ERR_H__
+
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* @defgroup BLE_ERRORS Error Codes
+ * @{ */
+#define BLE_ERROR_NOT_ENABLED            (NRF_ERROR_STK_BASE_NUM+0x001) /**< @ref sd_ble_enable has not been called. */
+#define BLE_ERROR_INVALID_CONN_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x002) /**< Invalid connection handle. */
+#define BLE_ERROR_INVALID_ATTR_HANDLE    (NRF_ERROR_STK_BASE_NUM+0x003) /**< Invalid attribute handle. */
+#define BLE_ERROR_NO_TX_PACKETS          (NRF_ERROR_STK_BASE_NUM+0x004) /**< Not enough application packets available on this connection. */
+#define BLE_ERROR_INVALID_ROLE           (NRF_ERROR_STK_BASE_NUM+0x005) /**< Invalid role. */
+/** @} */
+
+
+/** @defgroup BLE_ERROR_SUBRANGES Module specific error code subranges
+ *  @brief Assignment of subranges for module specific error codes.
+ *  @note For specific error codes, see ble_<module>.h or ble_error_<module>.h.
+ * @{ */
+#define NRF_L2CAP_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x100) /**< L2CAP specific errors. */
+#define NRF_GAP_ERR_BASE               (NRF_ERROR_STK_BASE_NUM+0x200) /**< GAP specific errors. */
+#define NRF_GATTC_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x300) /**< GATT client specific errors. */
+#define NRF_GATTS_ERR_BASE             (NRF_ERROR_STK_BASE_NUM+0x400) /**< GATT server specific errors. */
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gap.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gap.h
new file mode 100644
index 0000000000..926714ed36
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gap.h
@@ -0,0 +1,1745 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GAP Generic Access Profile (GAP)
+  @{
+  @brief Definitions and prototypes for the GAP interface.
+ */
+
+#ifndef NRF_BLE_GAP_H__
+#define NRF_BLE_GAP_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup BLE_GAP_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief GAP API SVC numbers.
+ */
+enum BLE_GAP_SVCS
+{
+  SD_BLE_GAP_ADDRESS_SET  = BLE_GAP_SVC_BASE,  /**< Set own Bluetooth Address. */
+  SD_BLE_GAP_ADDRESS_GET,                      /**< Get own Bluetooth Address. */
+  SD_BLE_GAP_ADV_DATA_SET,                     /**< Set Advertising Data. */
+  SD_BLE_GAP_ADV_START,                        /**< Start Advertising. */
+  SD_BLE_GAP_ADV_STOP,                         /**< Stop Advertising. */
+  SD_BLE_GAP_CONN_PARAM_UPDATE,                /**< Connection Parameter Update. */
+  SD_BLE_GAP_DISCONNECT,                       /**< Disconnect. */
+  SD_BLE_GAP_TX_POWER_SET,                     /**< Set TX Power. */
+  SD_BLE_GAP_APPEARANCE_SET,                   /**< Set Appearance. */
+  SD_BLE_GAP_APPEARANCE_GET,                   /**< Get Appearance. */
+  SD_BLE_GAP_PPCP_SET,                         /**< Set PPCP. */
+  SD_BLE_GAP_PPCP_GET,                         /**< Get PPCP. */
+  SD_BLE_GAP_DEVICE_NAME_SET,                  /**< Set Device Name. */
+  SD_BLE_GAP_DEVICE_NAME_GET,                  /**< Get Device Name. */
+  SD_BLE_GAP_AUTHENTICATE,                     /**< Initiate Pairing/Bonding. */
+  SD_BLE_GAP_SEC_PARAMS_REPLY,                 /**< Reply with Security Parameters. */
+  SD_BLE_GAP_AUTH_KEY_REPLY,                   /**< Reply with an authentication key. */
+  SD_BLE_GAP_LESC_DHKEY_REPLY,                 /**< Reply with an LE Secure Connections DHKey. */
+  SD_BLE_GAP_KEYPRESS_NOTIFY,                  /**< Notify of a keypress during an authentication procedure. */
+  SD_BLE_GAP_LESC_OOB_DATA_GET,                /**< Get the local LE Secure Connections OOB data. */
+  SD_BLE_GAP_LESC_OOB_DATA_SET,                /**< Set the remote LE Secure Connections OOB data. */
+  SD_BLE_GAP_ENCRYPT,                          /**< Initiate encryption procedure. */
+  SD_BLE_GAP_SEC_INFO_REPLY,                   /**< Reply with Security Information. */
+  SD_BLE_GAP_CONN_SEC_GET,                     /**< Obtain connection security level. */
+  SD_BLE_GAP_RSSI_START,                       /**< Start reporting of changes in RSSI. */
+  SD_BLE_GAP_RSSI_STOP,                        /**< Stop reporting of changes in RSSI. */
+  SD_BLE_GAP_SCAN_START,                       /**< Start Scanning. */
+  SD_BLE_GAP_SCAN_STOP,                        /**< Stop Scanning. */
+  SD_BLE_GAP_CONNECT,                          /**< Connect. */
+  SD_BLE_GAP_CONNECT_CANCEL,                   /**< Cancel ongoing connection procedure. */
+  SD_BLE_GAP_RSSI_GET,                         /**< Get the last RSSI sample. */
+};
+
+/**@brief GAP Event IDs.
+ * IDs that uniquely identify an event coming from the stack to the application.
+ */
+enum BLE_GAP_EVTS
+{
+  BLE_GAP_EVT_CONNECTED  = BLE_GAP_EVT_BASE,    /**< Connection established.                         \n See @ref ble_gap_evt_connected_t.            */
+  BLE_GAP_EVT_DISCONNECTED,                     /**< Disconnected from peer.                         \n See @ref ble_gap_evt_disconnected_t.         */
+  BLE_GAP_EVT_CONN_PARAM_UPDATE,                /**< Connection Parameters updated.                  \n See @ref ble_gap_evt_conn_param_update_t.    */
+  BLE_GAP_EVT_SEC_PARAMS_REQUEST,               /**< Request to provide security parameters.         \n Reply with @ref sd_ble_gap_sec_params_reply.  \n See @ref ble_gap_evt_sec_params_request_t. */
+  BLE_GAP_EVT_SEC_INFO_REQUEST,                 /**< Request to provide security information.        \n Reply with @ref sd_ble_gap_sec_info_reply.    \n See @ref ble_gap_evt_sec_info_request_t.   */
+  BLE_GAP_EVT_PASSKEY_DISPLAY,                  /**< Request to display a passkey to the user.       \n In LESC Numeric Comparison, reply with @ref sd_ble_gap_auth_key_reply. \n See @ref ble_gap_evt_passkey_display_t. */
+  BLE_GAP_EVT_KEY_PRESSED,                      /**< Notification of a keypress on the remote device.\n See @ref ble_gap_evt_key_pressed_t           */
+  BLE_GAP_EVT_AUTH_KEY_REQUEST,                 /**< Request to provide an authentication key.       \n Reply with @ref sd_ble_gap_auth_key_reply.    \n See @ref ble_gap_evt_auth_key_request_t.   */
+  BLE_GAP_EVT_LESC_DHKEY_REQUEST,               /**< Request to calculate an LE Secure Connections DHKey. \n Reply with @ref sd_ble_gap_lesc_dhkey_reply.  \n See @ref ble_gap_evt_lesc_dhkey_request_t */
+  BLE_GAP_EVT_AUTH_STATUS,                      /**< Authentication procedure completed with status. \n See @ref ble_gap_evt_auth_status_t.          */
+  BLE_GAP_EVT_CONN_SEC_UPDATE,                  /**< Connection security updated.                    \n See @ref ble_gap_evt_conn_sec_update_t.      */
+  BLE_GAP_EVT_TIMEOUT,                          /**< Timeout expired.                                \n See @ref ble_gap_evt_timeout_t.              */
+  BLE_GAP_EVT_RSSI_CHANGED,                     /**< RSSI report.                                    \n See @ref ble_gap_evt_rssi_changed_t.         */
+  BLE_GAP_EVT_ADV_REPORT,                       /**< Advertising report.                             \n See @ref ble_gap_evt_adv_report_t.           */
+  BLE_GAP_EVT_SEC_REQUEST,                      /**< Security Request.                               \n See @ref ble_gap_evt_sec_request_t.          */
+  BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST,        /**< Connection Parameter Update Request.            \n Reply with @ref sd_ble_gap_conn_param_update. \n See @ref ble_gap_evt_conn_param_update_request_t. */
+  BLE_GAP_EVT_SCAN_REQ_REPORT,                  /**< Scan request report.                            \n See @ref ble_gap_evt_scan_req_report_t.      */
+};
+
+/**@brief GAP Option IDs.
+ * IDs that uniquely identify a GAP option.
+ */
+enum BLE_GAP_OPTS
+{
+  BLE_GAP_OPT_CH_MAP  = BLE_GAP_OPT_BASE,       /**< Channel Map. @ref ble_gap_opt_ch_map_t  */
+  BLE_GAP_OPT_LOCAL_CONN_LATENCY,               /**< Local connection latency. @ref ble_gap_opt_local_conn_latency_t */
+  BLE_GAP_OPT_PASSKEY,                          /**< Set passkey. @ref ble_gap_opt_passkey_t */
+  BLE_GAP_OPT_PRIVACY,                          /**< Custom privacy. @ref ble_gap_opt_privacy_t */
+  BLE_GAP_OPT_SCAN_REQ_REPORT,                  /**< Scan request report. @ref ble_gap_opt_scan_req_report_t */
+  BLE_GAP_OPT_COMPAT_MODE                       /**< Compatibility mode. @ref ble_gap_opt_compat_mode_t */
+};
+
+/** @} */
+
+/**@addtogroup BLE_GAP_DEFINES Defines
+ * @{ */
+
+/**@defgroup BLE_ERRORS_GAP SVC return values specific to GAP
+ * @{ */
+#define BLE_ERROR_GAP_UUID_LIST_MISMATCH            (NRF_GAP_ERR_BASE + 0x000)  /**< UUID list does not contain an integral number of UUIDs. */
+#define BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST   (NRF_GAP_ERR_BASE + 0x001)  /**< Use of Whitelist not permitted with discoverable advertising. */
+#define BLE_ERROR_GAP_INVALID_BLE_ADDR              (NRF_GAP_ERR_BASE + 0x002)  /**< The upper two bits of the address do not correspond to the specified address type. */
+#define BLE_ERROR_GAP_WHITELIST_IN_USE              (NRF_GAP_ERR_BASE + 0x003)  /**< Attempt to overwrite the whitelist while already in use by another operation. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ROLES GAP Roles
+ * @note Not explicitly used in peripheral API, but will be relevant for central API.
+ * @{ */
+#define BLE_GAP_ROLE_INVALID     0x0            /**< Invalid Role. */
+#define BLE_GAP_ROLE_PERIPH      0x1            /**< Peripheral Role. */
+#define BLE_GAP_ROLE_CENTRAL     0x2            /**< Central Role. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_TIMEOUT_SOURCES GAP Timeout sources
+ * @{ */
+#define BLE_GAP_TIMEOUT_SRC_ADVERTISING                0x00 /**< Advertising timeout. */
+#define BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST           0x01 /**< Security request timeout. */
+#define BLE_GAP_TIMEOUT_SRC_SCAN                       0x02 /**< Scanning timeout. */
+#define BLE_GAP_TIMEOUT_SRC_CONN                       0x03 /**< Connection timeout. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADDR_TYPES GAP Address types
+ * @{ */
+#define BLE_GAP_ADDR_TYPE_PUBLIC                        0x00 /**< Public address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_STATIC                 0x01 /**< Random Static address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE     0x02 /**< Private Resolvable address. */
+#define BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE 0x03 /**< Private Non-Resolvable address. */
+/**@} */
+
+/**@defgroup BLE_GAP_ADDR_CYCLE_MODES GAP Address cycle modes
+ * @{ */
+#define BLE_GAP_ADDR_CYCLE_MODE_NONE      0x00 /**< Set addresses directly, no automatic address cycling. */
+#define BLE_GAP_ADDR_CYCLE_MODE_AUTO      0x01 /**< Automatically generate and update private addresses. */
+/** @} */
+
+/**@brief The default interval in seconds at which a private address is refreshed when address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO.  */
+#define BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S (60 * 15)
+
+/** @brief BLE address length. */
+#define BLE_GAP_ADDR_LEN            6
+
+
+/**@defgroup BLE_GAP_AD_TYPE_DEFINITIONS GAP Advertising and Scan Response Data format
+ * @note Found at https://www.bluetooth.org/Technical/AssignedNumbers/generic_access_profile.htm
+ * @{ */
+#define BLE_GAP_AD_TYPE_FLAGS                               0x01 /**< Flags for discoverability. */
+#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE   0x02 /**< Partial list of 16 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE         0x03 /**< Complete list of 16 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_MORE_AVAILABLE   0x04 /**< Partial list of 32 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_32BIT_SERVICE_UUID_COMPLETE         0x05 /**< Complete list of 32 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE  0x06 /**< Partial list of 128 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE        0x07 /**< Complete list of 128 bit service UUIDs. */
+#define BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME                    0x08 /**< Short local device name. */
+#define BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME                 0x09 /**< Complete local device name. */
+#define BLE_GAP_AD_TYPE_TX_POWER_LEVEL                      0x0A /**< Transmit power level. */
+#define BLE_GAP_AD_TYPE_CLASS_OF_DEVICE                     0x0D /**< Class of device. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C               0x0E /**< Simple Pairing Hash C. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R         0x0F /**< Simple Pairing Randomizer R. */
+#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE           0x10 /**< Security Manager TK Value. */
+#define BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS          0x11 /**< Security Manager Out Of Band Flags. */
+#define BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE     0x12 /**< Slave Connection Interval Range. */
+#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT       0x14 /**< List of 16-bit Service Solicitation UUIDs. */
+#define BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT      0x15 /**< List of 128-bit Service Solicitation UUIDs. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA                        0x16 /**< Service Data - 16-bit UUID. */
+#define BLE_GAP_AD_TYPE_PUBLIC_TARGET_ADDRESS               0x17 /**< Public Target Address. */
+#define BLE_GAP_AD_TYPE_RANDOM_TARGET_ADDRESS               0x18 /**< Random Target Address. */
+#define BLE_GAP_AD_TYPE_APPEARANCE                          0x19 /**< Appearance. */
+#define BLE_GAP_AD_TYPE_ADVERTISING_INTERVAL                0x1A /**< Advertising Interval. */
+#define BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS         0x1B /**< LE Bluetooth Device Address. */
+#define BLE_GAP_AD_TYPE_LE_ROLE                             0x1C /**< LE Role. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_HASH_C256            0x1D /**< Simple Pairing Hash C-256. */
+#define BLE_GAP_AD_TYPE_SIMPLE_PAIRING_RANDOMIZER_R256      0x1E /**< Simple Pairing Randomizer R-256. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA_32BIT_UUID             0x20 /**< Service Data - 32-bit UUID. */
+#define BLE_GAP_AD_TYPE_SERVICE_DATA_128BIT_UUID            0x21 /**< Service Data - 128-bit UUID. */
+#define BLE_GAP_AD_TYPE_URI                                 0x24 /**< URI */
+#define BLE_GAP_AD_TYPE_3D_INFORMATION_DATA                 0x3D /**< 3D Information Data. */
+#define BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA          0xFF /**< Manufacturer Specific Data. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_FLAGS GAP Advertisement Flags
+ * @{ */
+#define BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE         (0x01)   /**< LE Limited Discoverable Mode. */
+#define BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE         (0x02)   /**< LE General Discoverable Mode. */
+#define BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED         (0x04)   /**< BR/EDR not supported. */
+#define BLE_GAP_ADV_FLAG_LE_BR_EDR_CONTROLLER         (0x08)   /**< Simultaneous LE and BR/EDR, Controller. */
+#define BLE_GAP_ADV_FLAG_LE_BR_EDR_HOST               (0x10)   /**< Simultaneous LE and BR/EDR, Host. */
+#define BLE_GAP_ADV_FLAGS_LE_ONLY_LIMITED_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_LIMITED_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE Limited Discoverable Mode, BR/EDR not supported. */
+#define BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE   (BLE_GAP_ADV_FLAG_LE_GENERAL_DISC_MODE | BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED)   /**< LE General Discoverable Mode, BR/EDR not supported. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_INTERVALS GAP Advertising interval max and min
+ * @{ */
+#define BLE_GAP_ADV_INTERVAL_MIN        0x0020 /**< Minimum Advertising interval in 625 us units, i.e. 20 ms. */
+#define BLE_GAP_ADV_NONCON_INTERVAL_MIN 0x00A0 /**< Minimum Advertising interval in 625 us units for non connectable mode, i.e. 100 ms. */
+#define BLE_GAP_ADV_INTERVAL_MAX        0x4000 /**< Maximum Advertising interval in 625 us units, i.e. 10.24 s. */
+ /**@}  */
+
+
+/**@defgroup BLE_GAP_SCAN_INTERVALS GAP Scan interval max and min
+ * @{ */
+#define BLE_GAP_SCAN_INTERVAL_MIN       0x0004 /**< Minimum Scan interval in 625 us units, i.e. 2.5 ms. */
+#define BLE_GAP_SCAN_INTERVAL_MAX       0x4000 /**< Maximum Scan interval in 625 us units, i.e. 10.24 s. */
+ /** @}  */
+
+
+/**@defgroup BLE_GAP_SCAN_WINDOW GAP Scan window max and min
+ * @{ */
+#define BLE_GAP_SCAN_WINDOW_MIN         0x0004 /**< Minimum Scan window in 625 us units, i.e. 2.5 ms. */
+#define BLE_GAP_SCAN_WINDOW_MAX         0x4000 /**< Maximum Scan window in 625 us units, i.e. 10.24 s. */
+ /** @}  */
+
+
+/**@defgroup BLE_GAP_SCAN_TIMEOUT GAP Scan timeout max and min
+ * @{ */
+#define BLE_GAP_SCAN_TIMEOUT_MIN        0x0001 /**< Minimum Scan timeout in seconds. */
+#define BLE_GAP_SCAN_TIMEOUT_MAX        0xFFFF /**< Maximum Scan timeout in seconds. */
+ /** @}  */
+
+
+/**@brief Maximum size of advertising data in octets. */
+#define  BLE_GAP_ADV_MAX_SIZE           31
+
+
+/**@defgroup BLE_GAP_ADV_TYPES GAP Advertising types
+ * @{ */
+#define BLE_GAP_ADV_TYPE_ADV_IND          0x00   /**< Connectable undirected. */
+#define BLE_GAP_ADV_TYPE_ADV_DIRECT_IND   0x01   /**< Connectable directed. */
+#define BLE_GAP_ADV_TYPE_ADV_SCAN_IND     0x02   /**< Scannable undirected. */
+#define BLE_GAP_ADV_TYPE_ADV_NONCONN_IND  0x03   /**< Non connectable undirected. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_FILTER_POLICIES GAP Advertising filter policies
+ * @{ */
+#define BLE_GAP_ADV_FP_ANY                0x00   /**< Allow scan requests and connect requests from any device. */
+#define BLE_GAP_ADV_FP_FILTER_SCANREQ     0x01   /**< Filter scan requests with whitelist. */
+#define BLE_GAP_ADV_FP_FILTER_CONNREQ     0x02   /**< Filter connect requests with whitelist. */
+#define BLE_GAP_ADV_FP_FILTER_BOTH        0x03   /**< Filter both scan and connect requests with whitelist. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_ADV_TIMEOUT_VALUES GAP Advertising timeout values
+ * @{ */
+#define BLE_GAP_ADV_TIMEOUT_LIMITED_MAX      180 /**< Maximum advertising time in limited discoverable mode (TGAP(lim_adv_timeout) = 180s). */
+#define BLE_GAP_ADV_TIMEOUT_GENERAL_UNLIMITED  0 /**< Unlimited advertising in general discoverable mode. */
+/**@} */
+
+
+/**@defgroup BLE_GAP_DISC_MODES GAP Discovery modes
+ * @{ */
+#define BLE_GAP_DISC_MODE_NOT_DISCOVERABLE  0x00   /**< Not discoverable discovery Mode. */
+#define BLE_GAP_DISC_MODE_LIMITED           0x01   /**< Limited Discovery Mode. */
+#define BLE_GAP_DISC_MODE_GENERAL           0x02   /**< General Discovery Mode. */
+/**@} */
+
+/**@defgroup BLE_GAP_IO_CAPS GAP IO Capabilities
+ * @{ */
+#define BLE_GAP_IO_CAPS_DISPLAY_ONLY      0x00   /**< Display Only. */
+#define BLE_GAP_IO_CAPS_DISPLAY_YESNO     0x01   /**< Display and Yes/No entry. */
+#define BLE_GAP_IO_CAPS_KEYBOARD_ONLY     0x02   /**< Keyboard Only. */
+#define BLE_GAP_IO_CAPS_NONE              0x03   /**< No I/O capabilities. */
+#define BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY  0x04   /**< Keyboard and Display. */
+/**@} */
+
+/**@defgroup BLE_GAP_AUTH_KEY_TYPES GAP Authentication Key Types
+ * @{ */
+#define BLE_GAP_AUTH_KEY_TYPE_NONE        0x00   /**< No key (may be used to reject). */
+#define BLE_GAP_AUTH_KEY_TYPE_PASSKEY     0x01   /**< 6-digit Passkey. */
+#define BLE_GAP_AUTH_KEY_TYPE_OOB         0x02   /**< Out Of Band data. */
+/**@} */
+
+/**@defgroup BLE_GAP_KP_NOT_TYPES GAP Keypress Notification Types
+ * @{ */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_START       0x00   /**< Passkey entry started. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_IN    0x01   /**< Passkey digit entered. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_DIGIT_OUT   0x02   /**< Passkey digit erased. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_CLEAR       0x03   /**< Passkey cleared. */
+#define BLE_GAP_KP_NOT_TYPE_PASSKEY_END         0x04   /**< Passkey entry completed. */
+/**@} */
+
+/**@defgroup BLE_GAP_SEC_STATUS GAP Security status
+ * @{ */
+#define BLE_GAP_SEC_STATUS_SUCCESS                0x00  /**< Procedure completed with success. */
+#define BLE_GAP_SEC_STATUS_TIMEOUT                0x01  /**< Procedure timed out. */
+#define BLE_GAP_SEC_STATUS_PDU_INVALID            0x02  /**< Invalid PDU received. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE1_BEGIN       0x03  /**< Reserved for Future Use range #1 begin. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE1_END         0x80  /**< Reserved for Future Use range #1 end. */
+#define BLE_GAP_SEC_STATUS_PASSKEY_ENTRY_FAILED   0x81  /**< Passkey entry failed (user cancelled or other). */
+#define BLE_GAP_SEC_STATUS_OOB_NOT_AVAILABLE      0x82  /**< Out of Band Key not available. */
+#define BLE_GAP_SEC_STATUS_AUTH_REQ               0x83  /**< Authentication requirements not met. */
+#define BLE_GAP_SEC_STATUS_CONFIRM_VALUE          0x84  /**< Confirm value failed. */
+#define BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP       0x85  /**< Pairing not supported.  */
+#define BLE_GAP_SEC_STATUS_ENC_KEY_SIZE           0x86  /**< Encryption key size. */
+#define BLE_GAP_SEC_STATUS_SMP_CMD_UNSUPPORTED    0x87  /**< Unsupported SMP command. */
+#define BLE_GAP_SEC_STATUS_UNSPECIFIED            0x88  /**< Unspecified reason. */
+#define BLE_GAP_SEC_STATUS_REPEATED_ATTEMPTS      0x89  /**< Too little time elapsed since last attempt. */
+#define BLE_GAP_SEC_STATUS_INVALID_PARAMS         0x8A  /**< Invalid parameters. */
+#define BLE_GAP_SEC_STATUS_DHKEY_FAILURE          0x8B  /**< DHKey check failure. */
+#define BLE_GAP_SEC_STATUS_NUM_COMP_FAILURE       0x8C  /**< Numeric Comparison failure. */
+#define BLE_GAP_SEC_STATUS_BR_EDR_IN_PROG         0x8D  /**< BR/EDR pairing in progress. */
+#define BLE_GAP_SEC_STATUS_X_TRANS_KEY_DISALLOWED 0x8E  /**< BR/EDR Link Key cannot be used for LE keys. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE2_BEGIN       0x8F  /**< Reserved for Future Use range #2 begin. */
+#define BLE_GAP_SEC_STATUS_RFU_RANGE2_END         0xFF  /**< Reserved for Future Use range #2 end. */
+/**@} */
+
+/**@defgroup BLE_GAP_SEC_STATUS_SOURCES GAP Security status sources
+ * @{ */
+#define BLE_GAP_SEC_STATUS_SOURCE_LOCAL           0x00  /**< Local failure. */
+#define BLE_GAP_SEC_STATUS_SOURCE_REMOTE          0x01  /**< Remote failure. */
+/**@} */
+
+/**@defgroup BLE_GAP_CP_LIMITS GAP Connection Parameters Limits
+ * @{ */
+#define BLE_GAP_CP_MIN_CONN_INTVL_NONE           0xFFFF  /**< No new minimum connection interval specified in connect parameters. */
+#define BLE_GAP_CP_MIN_CONN_INTVL_MIN            0x0006  /**< Lowest minimum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
+#define BLE_GAP_CP_MIN_CONN_INTVL_MAX            0x0C80  /**< Highest minimum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_NONE           0xFFFF  /**< No new maximum connection interval specified in connect parameters. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_MIN            0x0006  /**< Lowest maximum connection interval permitted, in units of 1.25 ms, i.e. 7.5 ms. */
+#define BLE_GAP_CP_MAX_CONN_INTVL_MAX            0x0C80  /**< Highest maximum connection interval permitted, in units of 1.25 ms, i.e. 4 s. */
+#define BLE_GAP_CP_SLAVE_LATENCY_MAX             0x01F3  /**< Highest slave latency permitted, in connection events. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_NONE         0xFFFF  /**< No new supervision timeout specified in connect parameters. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MIN          0x000A  /**< Lowest supervision timeout permitted, in units of 10 ms, i.e. 100 ms. */
+#define BLE_GAP_CP_CONN_SUP_TIMEOUT_MAX          0x0C80  /**< Highest supervision timeout permitted, in units of 10 ms, i.e. 32 s. */
+/**@} */
+
+
+/**@brief GAP device name maximum length. */
+#define BLE_GAP_DEVNAME_MAX_LEN           31
+
+/**@brief Disable RSSI events for connections */
+#define BLE_GAP_RSSI_THRESHOLD_INVALID    0xFF
+
+/**@defgroup BLE_GAP_CONN_SEC_MODE_SET_MACROS GAP attribute security requirement setters
+ *
+ * See @ref ble_gap_conn_sec_mode_t.
+ * @{ */
+/**@brief Set sec_mode pointed to by ptr to have no access rights.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(ptr)          do {(ptr)->sm = 0; (ptr)->lv = 0;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require no protection, open link.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_OPEN(ptr)               do {(ptr)->sm = 1; (ptr)->lv = 1;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require encryption, but no MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(ptr)        do {(ptr)->sm = 1; (ptr)->lv = 2;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require encryption and MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(ptr)      do {(ptr)->sm = 1; (ptr)->lv = 3;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require LESC encryption and MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_LESC_ENC_WITH_MITM(ptr) do {(ptr)->sm = 1; (ptr)->lv = 4;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require signing or encryption, no MITM protection needed.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(ptr)     do {(ptr)->sm = 2; (ptr)->lv = 1;} while(0)
+/**@brief Set sec_mode pointed to by ptr to require signing or encryption with MITM protection.*/
+#define BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(ptr)   do {(ptr)->sm = 2; (ptr)->lv = 2;} while(0)
+/**@} */
+
+
+/**@brief GAP Security Random Number Length. */
+#define BLE_GAP_SEC_RAND_LEN 8
+
+/**@brief GAP Security Key Length. */
+#define BLE_GAP_SEC_KEY_LEN 16
+
+/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key Length. */
+#define BLE_GAP_LESC_P256_PK_LEN 64
+
+/**@brief GAP LE Secure Connections Elliptic Curve Diffie-Hellman DHKey Length. */
+#define BLE_GAP_LESC_DHKEY_LEN   32
+
+/**@brief GAP Passkey Length. */
+#define BLE_GAP_PASSKEY_LEN 6
+
+/**@brief Maximum amount of addresses in a whitelist. */
+#define BLE_GAP_WHITELIST_ADDR_MAX_COUNT (8)
+
+/**@brief Maximum amount of IRKs in a whitelist.
+ * @note  The number of IRKs is limited to 8, even if the hardware supports more.
+ */
+#define BLE_GAP_WHITELIST_IRK_MAX_COUNT (8)
+
+/**@defgroup GAP_SEC_MODES GAP Security Modes
+ * @{ */
+#define BLE_GAP_SEC_MODE 0x00 /**< No key (may be used to reject). */
+/**@} */
+/** @} */
+
+/**@addtogroup BLE_GAP_STRUCTURES Structures
+ * @{ */
+
+/**
+ * @brief BLE GAP initialization parameters.
+ */
+typedef struct
+{
+  uint8_t                   periph_conn_count;  /**< Number of connections acting as a peripheral  */
+  uint8_t                   central_conn_count; /**< Number of connections acting as a central */
+  uint8_t                   central_sec_count;  /**< Number of SMP instances for all connections acting as a central. */
+} ble_gap_enable_params_t;
+
+/**@brief Bluetooth Low Energy address. */
+typedef struct
+{
+  uint8_t addr_type;                    /**< See @ref BLE_GAP_ADDR_TYPES. */
+  uint8_t addr[BLE_GAP_ADDR_LEN];       /**< 48-bit address, LSB format. */
+} ble_gap_addr_t;
+
+
+/**@brief GAP connection parameters.
+ *
+ * @note  When ble_conn_params_t is received in an event, both min_conn_interval and
+ *        max_conn_interval will be equal to the connection interval set by the central.
+ *
+ * @note If both conn_sup_timeout and max_conn_interval are specified, then the following constraint applies:
+ *       conn_sup_timeout * 4 > (1 + slave_latency) * max_conn_interval
+ *       that corresponds to the following Bluetooth Spec requirement:
+ *       The Supervision_Timeout in milliseconds shall be larger than
+ *       (1 + Conn_Latency) * Conn_Interval_Max * 2, where Conn_Interval_Max is given in milliseconds.
+ */
+typedef struct
+{
+  uint16_t min_conn_interval;         /**< Minimum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t max_conn_interval;         /**< Maximum Connection Interval in 1.25 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t slave_latency;             /**< Slave Latency in number of connection events, see @ref BLE_GAP_CP_LIMITS.*/
+  uint16_t conn_sup_timeout;          /**< Connection Supervision Timeout in 10 ms units, see @ref BLE_GAP_CP_LIMITS.*/
+} ble_gap_conn_params_t;
+
+
+/**@brief GAP connection security modes.
+ *
+ * Security Mode 0 Level 0: No access permissions at all (this level is not defined by the Bluetooth Core specification).\n
+ * Security Mode 1 Level 1: No security is needed (aka open link).\n
+ * Security Mode 1 Level 2: Encrypted link required, MITM protection not necessary.\n
+ * Security Mode 1 Level 3: MITM protected encrypted link required.\n
+ * Security Mode 1 Level 4: LESC MITM protected encrypted link required.\n
+ * Security Mode 2 Level 1: Signing or encryption required, MITM protection not necessary.\n
+ * Security Mode 2 Level 2: MITM protected signing required, unless link is MITM protected encrypted.\n
+ */
+typedef struct
+{
+  uint8_t sm : 4;                     /**< Security Mode (1 or 2), 0 for no permissions at all. */
+  uint8_t lv : 4;                     /**< Level (1, 2, 3 or 4), 0 for no permissions at all. */
+
+} ble_gap_conn_sec_mode_t;
+
+
+/**@brief GAP connection security status.*/
+typedef struct
+{
+  ble_gap_conn_sec_mode_t sec_mode;           /**< Currently active security mode for this connection.*/
+  uint8_t                 encr_key_size;      /**< Length of currently active encryption key, 7 to 16 octets (only applicable for bonding procedures). */
+} ble_gap_conn_sec_t;
+
+
+/**@brief Identity Resolving Key. */
+typedef struct
+{
+  uint8_t irk[BLE_GAP_SEC_KEY_LEN];   /**< Array containing IRK. */
+} ble_gap_irk_t;
+
+
+/**@brief Whitelist structure. */
+typedef struct
+{
+  ble_gap_addr_t    **pp_addrs;        /**< Pointer to an array of device address pointers, pointing to addresses to be used in whitelist. NULL if none are given. */
+  uint8_t             addr_count;      /**< Count of device addresses in array, up to @ref BLE_GAP_WHITELIST_ADDR_MAX_COUNT. */
+  ble_gap_irk_t     **pp_irks;         /**< Pointer to an array of Identity Resolving Key (IRK) pointers, each pointing to an IRK in the whitelist. NULL if none are given. */
+  uint8_t             irk_count;       /**< Count of IRKs in array, up to @ref BLE_GAP_WHITELIST_IRK_MAX_COUNT. */
+} ble_gap_whitelist_t;
+
+/**@brief Channel mask for RF channels used in advertising. */
+typedef struct
+{
+  uint8_t ch_37_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 37 */
+  uint8_t ch_38_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 38 */
+  uint8_t ch_39_off : 1;  /**< Setting this bit to 1 will turn off advertising on channel 39 */
+} ble_gap_adv_ch_mask_t;
+
+/**@brief GAP advertising parameters.*/
+typedef struct
+{
+  uint8_t               type;                 /**< See @ref BLE_GAP_ADV_TYPES. */
+  ble_gap_addr_t       *p_peer_addr;          /**< For @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND mode only, known peer address. */
+  uint8_t               fp;                   /**< Filter Policy, see @ref BLE_GAP_ADV_FILTER_POLICIES. */
+  ble_gap_whitelist_t  *p_whitelist;          /**< Pointer to whitelist, NULL if no whitelist or the current active whitelist is to be used. */
+  uint16_t              interval;             /**< Advertising interval between 0x0020 and 0x4000 in 0.625 ms units (20ms to 10.24s), see @ref BLE_GAP_ADV_INTERVALS.
+                                                   - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for high duty cycle directed advertising.
+                                                   - If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, set @ref BLE_GAP_ADV_INTERVAL_MIN <= interval <= @ref BLE_GAP_ADV_INTERVAL_MAX for low duty cycle advertising.*/
+  uint16_t              timeout;              /**< Advertising timeout between 0x0001 and 0x3FFF in seconds, 0x0000 disables timeout. See also @ref BLE_GAP_ADV_TIMEOUT_VALUES. If type equals @ref BLE_GAP_ADV_TYPE_ADV_DIRECT_IND, this parameter must be set to 0 for High duty cycle directed advertising. */
+  ble_gap_adv_ch_mask_t channel_mask;         /**< Advertising channel mask. See @ref ble_gap_adv_ch_mask_t. */
+} ble_gap_adv_params_t;
+
+
+/**@brief GAP scanning parameters. */
+typedef struct
+{
+  uint8_t                 active    : 1;        /**< If 1, perform active scanning (scan requests). */
+  uint8_t                 selective : 1;        /**< If 1, ignore unknown devices (non whitelisted). */
+  ble_gap_whitelist_t *   p_whitelist;          /**< Pointer to whitelist, NULL if no whitelist or the current active whitelist is to be used. */
+  uint16_t                interval;             /**< Scan interval between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+  uint16_t                window;               /**< Scan window between 0x0004 and 0x4000 in 0.625ms units (2.5ms to 10.24s). */
+  uint16_t                timeout;              /**< Scan timeout between 0x0001 and 0xFFFF in seconds, 0x0000 disables timeout. */
+} ble_gap_scan_params_t;
+
+
+/** @brief Keys that can be exchanged during a bonding procedure. */
+typedef struct
+{
+  uint8_t enc     : 1;                        /**< Long Term Key and Master Identification. */
+  uint8_t id      : 1;                        /**< Identity Resolving Key and Identity Address Information. */
+  uint8_t sign    : 1;                        /**< Connection Signature Resolving Key. */
+  uint8_t link    : 1;                        /**< Derive the Link Key from the LTK. */
+} ble_gap_sec_kdist_t;
+
+
+/**@brief GAP security parameters. */
+typedef struct
+{
+  uint8_t               bond      : 1;             /**< Perform bonding. */
+  uint8_t               mitm      : 1;             /**< Enable Man In The Middle protection. */
+  uint8_t               lesc      : 1;             /**< Enable LE Secure Connection pairing. */
+  uint8_t               keypress  : 1;             /**< Enable generation of keypress notifications. */
+  uint8_t               io_caps   : 3;             /**< IO capabilities, see @ref BLE_GAP_IO_CAPS. */
+  uint8_t               oob       : 1;             /**< Out Of Band data available. */
+  uint8_t               min_key_size;              /**< Minimum encryption key size in octets between 7 and 16. If 0 then not applicable in this instance. */
+  uint8_t               max_key_size;              /**< Maximum encryption key size in octets between min_key_size and 16. */
+  ble_gap_sec_kdist_t   kdist_own;                 /**< Key distribution bitmap: keys that the local device will distribute. */
+  ble_gap_sec_kdist_t   kdist_peer;                /**< Key distribution bitmap: keys that the remote device will distribute. */
+} ble_gap_sec_params_t;
+
+
+/**@brief GAP Encryption Information. */
+typedef struct
+{
+  uint8_t   ltk[BLE_GAP_SEC_KEY_LEN];   /**< Long Term Key. */
+  uint8_t   lesc : 1;                   /**< Key generated using LE Secure Connections. */
+  uint8_t   auth : 1;                   /**< Authenticated Key. */
+  uint8_t   ltk_len : 6;                /**< LTK length in octets. */
+} ble_gap_enc_info_t;
+
+
+/**@brief GAP Master Identification. */
+typedef struct
+{
+  uint16_t  ediv;                       /**< Encrypted Diversifier. */
+  uint8_t   rand[BLE_GAP_SEC_RAND_LEN]; /**< Random Number. */
+} ble_gap_master_id_t;
+
+
+/**@brief GAP Signing Information. */
+typedef struct
+{
+  uint8_t   csrk[BLE_GAP_SEC_KEY_LEN];        /**< Connection Signature Resolving Key. */
+} ble_gap_sign_info_t;
+
+/**@brief GAP LE Secure Connections P-256 Public Key. */
+typedef struct
+{
+  uint8_t   pk[BLE_GAP_LESC_P256_PK_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman P-256 Public Key. Stored in the standard SMP protocol format: {X,Y} both in little-endian. */
+} ble_gap_lesc_p256_pk_t;
+
+/**@brief GAP LE Secure Connections DHKey. */
+typedef struct
+{
+  uint8_t   key[BLE_GAP_LESC_DHKEY_LEN];        /**< LE Secure Connections Elliptic Curve Diffie-Hellman Key. Stored in little-endian. */
+} ble_gap_lesc_dhkey_t;
+
+/**@brief GAP LE Secure Connections OOB data. */
+typedef struct
+{
+  ble_gap_addr_t  addr;                          /**< Bluetooth address of the device. */
+  uint8_t         r[BLE_GAP_SEC_KEY_LEN];        /**< Random Number. */
+  uint8_t         c[BLE_GAP_SEC_KEY_LEN];        /**< Confirm Value. */
+} ble_gap_lesc_oob_data_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONNECTED. */
+typedef struct
+{
+  ble_gap_addr_t        peer_addr;              /**< Bluetooth address of the peer device. */
+  ble_gap_addr_t        own_addr;               /**< Bluetooth address of the local device used during connection setup. */
+  uint8_t               role;                   /**< BLE role for this connection, see @ref BLE_GAP_ROLES */
+  uint8_t               irk_match :1;           /**< If 1, peer device's address resolved using an IRK. */
+  uint8_t               irk_match_idx  :7;      /**< Index in IRK list where the address was matched. */
+  ble_gap_conn_params_t conn_params;            /**< GAP Connection Parameters. */
+} ble_gap_evt_connected_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_DISCONNECTED. */
+typedef struct
+{
+  uint8_t reason;                               /**< HCI error code, see @ref BLE_HCI_STATUS_CODES. */
+} ble_gap_evt_disconnected_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE. */
+typedef struct
+{
+  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
+} ble_gap_evt_conn_param_update_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST. */
+typedef struct
+{
+  ble_gap_sec_params_t peer_params;             /**< Initiator Security Parameters. */
+} ble_gap_evt_sec_params_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_INFO_REQUEST. */
+typedef struct
+{
+  ble_gap_addr_t      peer_addr;                     /**< Bluetooth address of the peer device. */
+  ble_gap_master_id_t master_id;                     /**< Master Identification for LTK lookup. */
+  uint8_t             enc_info  : 1;                 /**< If 1, Encryption Information required. */
+  uint8_t             id_info   : 1;                 /**< If 1, Identity Information required. */
+  uint8_t             sign_info : 1;                 /**< If 1, Signing Information required. */
+} ble_gap_evt_sec_info_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_PASSKEY_DISPLAY. */
+typedef struct
+{
+  uint8_t passkey[BLE_GAP_PASSKEY_LEN];         /**< 6-digit passkey in ASCII ('0'-'9' digits only). */
+  uint8_t match_request : 1;                    /**< If 1 requires the application to report the match using @ref sd_ble_gap_auth_key_reply
+                                                     with either @ref BLE_GAP_AUTH_KEY_TYPE_NONE if there is no match or
+                                                     @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY if there is a match. */
+} ble_gap_evt_passkey_display_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_KEY_PRESSED. */
+typedef struct
+{
+  uint8_t kp_not;         /**< Keypress notification type, see @ref BLE_GAP_KP_NOT_TYPES. */
+} ble_gap_evt_key_pressed_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_KEY_REQUEST. */
+typedef struct
+{
+  uint8_t key_type;                             /**< See @ref BLE_GAP_AUTH_KEY_TYPES. */
+} ble_gap_evt_auth_key_request_t;
+
+/**@brief Event structure for @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST. */
+typedef struct
+{
+  ble_gap_lesc_p256_pk_t *p_pk_peer;  /**< LE Secure Connections remote P-256 Public Key. This will point to the application-supplied memory
+                                           inside the keyset during the call to @ref sd_ble_gap_sec_params_reply. */
+  uint8_t oobd_req       :1;          /**< LESC OOB data required. A call to @ref sd_ble_gap_lesc_oob_data_set is required to complete the procedure. */
+} ble_gap_evt_lesc_dhkey_request_t;
+
+
+/**@brief Security levels supported.
+ * @note See Bluetooth Specification Version 4.2 Volume 3, Part C, Chapter 10, Section 10.2.1.
+*/
+typedef struct
+{
+  uint8_t lv1 : 1;                              /**< If 1: Level 1 is supported. */
+  uint8_t lv2 : 1;                              /**< If 1: Level 2 is supported. */
+  uint8_t lv3 : 1;                              /**< If 1: Level 3 is supported. */
+  uint8_t lv4 : 1;                              /**< If 1: Level 4 is supported. */
+} ble_gap_sec_levels_t;
+
+
+/**@brief Encryption Key. */
+typedef struct
+{
+  ble_gap_enc_info_t    enc_info;             /**< Encryption Information. */
+  ble_gap_master_id_t   master_id;            /**< Master Identification. */
+} ble_gap_enc_key_t;
+
+
+/**@brief Identity Key. */
+typedef struct
+{
+  ble_gap_irk_t         id_info;              /**< Identity Information. */
+  ble_gap_addr_t        id_addr_info;         /**< Identity Address Information. */
+} ble_gap_id_key_t;
+
+
+/**@brief Security Keys. */
+typedef struct
+{
+  ble_gap_enc_key_t      *p_enc_key;           /**< Encryption Key, or NULL. */
+  ble_gap_id_key_t       *p_id_key;            /**< Identity Key, or NULL. */
+  ble_gap_sign_info_t    *p_sign_key;          /**< Signing Key, or NULL. */
+  ble_gap_lesc_p256_pk_t *p_pk;                /**< LE Secure Connections P-256 Public Key. When in debug mode the application must use the value defined
+                                                    in the Core Bluetooth Specification v4.2 Vol.3, Part H, Section 2.3.5.6.1 */
+} ble_gap_sec_keys_t;
+
+
+/**@brief Security key set for both local and peer keys. */
+typedef struct
+{
+  ble_gap_sec_keys_t            keys_own;     /**< Keys distributed by the local device. For LE Secure Connections the encryption key will be generated locally and will always be stored if bonding. */
+  ble_gap_sec_keys_t            keys_peer;    /**< Keys distributed by the remote device. For LE Secure Connections, p_enc_key must always be NULL. */
+} ble_gap_sec_keyset_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_AUTH_STATUS. */
+typedef struct
+{
+  uint8_t               auth_status;            /**< Authentication status, see @ref BLE_GAP_SEC_STATUS. */
+  uint8_t               error_src : 2;          /**< On error, source that caused the failure, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+  uint8_t               bonded : 1;             /**< Procedure resulted in a bond. */
+  ble_gap_sec_levels_t  sm1_levels;             /**< Levels supported in Security Mode 1. */
+  ble_gap_sec_levels_t  sm2_levels;             /**< Levels supported in Security Mode 2. */
+  ble_gap_sec_kdist_t   kdist_own;              /**< Bitmap stating which keys were exchanged (distributed) by the local device. If bonding with LE Secure Connections, the enc bit will be always set. */
+  ble_gap_sec_kdist_t   kdist_peer;             /**< Bitmap stating which keys were exchanged (distributed) by the remote device. If bonding with LE Secure Connections, the enc bit will never be set. */
+} ble_gap_evt_auth_status_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_SEC_UPDATE. */
+typedef struct
+{
+  ble_gap_conn_sec_t conn_sec;                  /**< Connection security level. */
+} ble_gap_evt_conn_sec_update_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t src;                                  /**< Source of timeout event, see @ref BLE_GAP_TIMEOUT_SOURCES. */
+} ble_gap_evt_timeout_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_RSSI_CHANGED. */
+typedef struct
+{
+  int8_t  rssi;                               /**< Received Signal Strength Indication in dBm. */
+} ble_gap_evt_rssi_changed_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_ADV_REPORT. */
+typedef struct
+{
+  ble_gap_addr_t peer_addr;                     /**< Bluetooth address of the peer device. */
+  int8_t         rssi;                          /**< Received Signal Strength Indication in dBm. */
+  uint8_t        scan_rsp : 1;                  /**< If 1, the report corresponds to a scan response and the type field may be ignored. */
+  uint8_t        type     : 2;                  /**< See @ref BLE_GAP_ADV_TYPES. Only valid if the scan_rsp field is 0. */
+  uint8_t        dlen     : 5;                  /**< Advertising or scan response data length. */
+  uint8_t        data[BLE_GAP_ADV_MAX_SIZE];    /**< Advertising or scan response data. */
+} ble_gap_evt_adv_report_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SEC_REQUEST. */
+typedef struct
+{
+  uint8_t    bond       : 1;                       /**< Perform bonding. */
+  uint8_t    mitm       : 1;                       /**< Man In The Middle protection requested. */
+  uint8_t    lesc       : 1;                       /**< LE Secure Connections requested. */
+  uint8_t    keypress   : 1;                       /**< Generation of keypress notifications requested. */
+} ble_gap_evt_sec_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST. */
+typedef struct
+{
+  ble_gap_conn_params_t conn_params;            /**<  GAP Connection Parameters. */
+} ble_gap_evt_conn_param_update_request_t;
+
+
+/**@brief Event structure for @ref BLE_GAP_EVT_SCAN_REQ_REPORT. */
+typedef struct
+{
+  int8_t                  rssi;              /**< Received Signal Strength Indication in dBm. */
+  ble_gap_addr_t          peer_addr;         /**< Bluetooth address of the peer device. */
+} ble_gap_evt_scan_req_report_t;
+
+
+
+/**@brief GAP event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                                     /**< Connection Handle on which event occurred. */
+  union                                                     /**< union alternative identified by evt_id in enclosing struct. */
+  {
+    ble_gap_evt_connected_t                   connected;                    /**< Connected Event Parameters. */
+    ble_gap_evt_disconnected_t                disconnected;                 /**< Disconnected Event Parameters. */
+    ble_gap_evt_conn_param_update_t           conn_param_update;            /**< Connection Parameter Update Parameters. */
+    ble_gap_evt_sec_params_request_t          sec_params_request;           /**< Security Parameters Request Event Parameters. */
+    ble_gap_evt_sec_info_request_t            sec_info_request;             /**< Security Information Request Event Parameters. */
+    ble_gap_evt_passkey_display_t             passkey_display;              /**< Passkey Display Event Parameters. */
+    ble_gap_evt_key_pressed_t                 key_pressed;                  /**< Key Pressed Event Parameters. */
+    ble_gap_evt_auth_key_request_t            auth_key_request;             /**< Authentication Key Request Event Parameters. */
+    ble_gap_evt_lesc_dhkey_request_t          lesc_dhkey_request;           /**< LE Secure Connections DHKey calculation request. */
+    ble_gap_evt_auth_status_t                 auth_status;                  /**< Authentication Status Event Parameters. */
+    ble_gap_evt_conn_sec_update_t             conn_sec_update;              /**< Connection Security Update Event Parameters. */
+    ble_gap_evt_timeout_t                     timeout;                      /**< Timeout Event Parameters. */
+    ble_gap_evt_rssi_changed_t                rssi_changed;                 /**< RSSI Event parameters. */
+    ble_gap_evt_adv_report_t                  adv_report;                   /**< Advertising Report Event Parameters. */
+    ble_gap_evt_sec_request_t                 sec_request;                  /**< Security Request Event Parameters. */
+    ble_gap_evt_conn_param_update_request_t   conn_param_update_request;    /**< Connection Parameter Update Parameters. */
+    ble_gap_evt_scan_req_report_t             scan_req_report;              /**< Scan Request Report parameters. */
+  } params;                                                                 /**< Event Parameters. */
+
+} ble_gap_evt_t;
+
+
+/**@brief Channel Map option.
+ *        Used with @ref sd_ble_opt_get to get the current channel map
+ *        or @ref sd_ble_opt_set to set a new channel map. When setting the
+ *        channel map, it applies to all current and future connections. When getting the
+ *        current channel map, it applies to a single connection and the connection handle
+ *        must be supplied.
+ *
+ * @note  Setting the channel map may take some time, depending on connection parameters.
+ *        The time taken may be different for each connection and the get operation will
+ *        return the previous channel map until the new one has taken effect.
+ *
+ * @note  After setting the channel map, by spec it can not be set again until at least 1 s has passed.
+ *        See Bluetooth Specification Version 4.1 Volume 2, Part E, Section 7.3.46.
+ *
+ * @retval ::NRF_SUCCESS Get or set successful.
+ * @retval ::NRF_ERROR_BUSY Channel map was set again before enough time had passed.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied for get.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Returned by sd_ble_opt_set in peripheral-only SoftDevices.
+ *
+ */
+typedef struct
+{
+  uint16_t conn_handle;                   /**< Connection Handle (only applicable for get) */
+  uint8_t ch_map[5];                      /**< Channel Map (37-bit). */
+} ble_gap_opt_ch_map_t;
+
+
+/**@brief Local connection latency option.
+ *
+ *        Local connection latency is a feature which enables the slave to improve
+ *        current consumption by ignoring the slave latency set by the peer. The
+ *        local connection latency can only be set to a multiple of the slave latency,
+ *        and cannot be longer than half of the supervision timeout.
+ *
+ *        Used with @ref sd_ble_opt_set to set the local connection latency. The
+ *        @ref sd_ble_opt_get is not supported for this option, but the actual
+ *        local connection latency (unless set to NULL) is set as a return parameter
+ *        when setting the option.
+ *
+ * @note  The latency set will be truncated down to the closest slave latency event
+ *        multiple, or the nearest multiple before half of the supervision timeout.
+ *
+ * @note  The local connection latency is disabled by default, and needs to be enabled for new
+ *        connections and whenever the connection is updated.
+ *
+ * @retval ::NRF_SUCCESS Set successfully.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Get is not supported.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle parameter.
+ */
+typedef struct
+{
+  uint16_t   conn_handle;                       /**< Connection Handle */
+  uint16_t   requested_latency;                 /**< Requested local connection latency. */
+  uint16_t * p_actual_latency;                  /**< Pointer to storage for the actual local connection latency (can be set to NULL to skip return value). */
+} ble_gap_opt_local_conn_latency_t;
+
+
+/**@brief Passkey Option.
+ *
+ *        Structure containing the passkey to be used during pairing. This can be used with @ref
+ *        sd_ble_opt_set to make the SoftDevice use a pre-programmed passkey for authentication
+ *        instead of generating a random one.
+ *
+ * @note  @ref sd_ble_opt_get is not supported for this option.
+ *
+ */
+typedef struct
+{
+  uint8_t * p_passkey;                          /**< Pointer to 6-digit ASCII string (digit 0..9 only, no NULL termination) passkey to be used during pairing. If this is NULL, the SoftDevice will generate a random passkey if required.*/
+} ble_gap_opt_passkey_t;
+
+
+/**@brief Custom Privacy Option.
+ *
+ *        This structure is used with both @ref sd_ble_opt_set (as input) and with
+ *        @ref sd_ble_opt_get (as output).
+ *
+ *        Structure containing:
+ *        - A pointer to an IRK to set (if input), or a place to store a read IRK (if output).
+ *        - A private address refresh cycle.
+ *
+ * @note  The specified address cycle interval is used when the address cycle mode is
+ *        @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO. If 0 is given, the address will not be automatically
+ *        refreshed at all. The default interval is @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S.
+ *
+ * @note  If the current address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address will immediately be
+ *        refreshed when a custom privacy option is set. A new address can be generated manually by calling
+ *        @ref sd_ble_gap_address_set with the same type again.
+ *
+ * @note  If the IRK is updated, the new IRK becomes the one to be distributed in all
+ *        bonding procedures performed after @ref sd_ble_opt_set returns.
+ *
+ * @retval ::NRF_SUCCESS Set or read successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR The pointer to IRK storage is invalid.
+ */
+typedef struct
+{
+  ble_gap_irk_t * p_irk;        /**< When input: Pointer to custom IRK, or NULL to use/reset to the device's default IRK. When output: Pointer to where the current IRK is to be stored, or NULL to not read out the IRK. */
+  uint16_t        interval_s;   /**< When input: Custom private address cycle interval in seconds. When output: The current private address cycle interval. */
+} ble_gap_opt_privacy_t;
+
+
+/**@brief Scan request report option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to make the SoftDevice send
+ *        @ref BLE_GAP_EVT_SCAN_REQ_REPORT events.
+ *
+ *  @note   Due to the limited space reserved for scan request report events,
+ *          not all received scan requests will be reported.
+ *
+ *  @note   If whitelisting is used, only whitelisted requests are reported.
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_STATE When advertising is ongoing while the option is set.
+ */
+typedef struct
+{
+   uint8_t enable : 1;                           /**< Enable scan request reports. */
+} ble_gap_opt_scan_req_report_t;
+
+/**@brief Compatibility mode option.
+ *
+ *        This can be used with @ref sd_ble_opt_set to enable and disable
+ *        compatibility modes. Compatibility modes are disabled by default.
+ *
+ *  @note  Compatibility mode 1 enables interoperability with devices that do not support
+ *         a value of 0 for the WinOffset parameter in the Link Layer CONNECT_REQ packet.
+ *
+ *  @retval ::NRF_SUCCESS Set successfully.
+ *  @retval ::NRF_ERROR_INVALID_STATE When connection creation is ongoing while mode 1 is set.
+ */
+typedef struct
+{
+   uint8_t mode_1_enable : 1;                           /**< Enable compatibility mode 1.*/
+} ble_gap_opt_compat_mode_t;
+
+/**@brief Option structure for GAP options. */
+typedef union
+{
+  ble_gap_opt_ch_map_t                  ch_map;                    /**< Parameters for the Channel Map option. */
+  ble_gap_opt_local_conn_latency_t      local_conn_latency;        /**< Parameters for the Local connection latency option */
+  ble_gap_opt_passkey_t                 passkey;                   /**< Parameters for the Passkey option.*/
+  ble_gap_opt_privacy_t                 privacy;                   /**< Parameters for the Custom privacy option. */
+  ble_gap_opt_scan_req_report_t         scan_req_report;           /**< Parameters for the scan request report option.*/
+  ble_gap_opt_compat_mode_t             compat_mode;               /**< Parameters for the compatibility mode option.*/
+} ble_gap_opt_t;
+/**@} */
+
+
+/**@addtogroup BLE_GAP_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Set local Bluetooth address.
+ *
+ * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_AUTO, the address type is required to
+ * be @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE or
+ * @ref BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE. The given address is ignored and the
+ * SoftDevice will generate a new private address automatically every
+ * @ref BLE_GAP_DEFAULT_PRIVATE_ADDR_CYCLE_INTERVAL_S seconds. If this API
+ * call is used again with the same parameters, the SoftDevice will immediately
+ * generate a new private address to replace the current address.
+ *
+ * @note If the application wishes to use a @ref BLE_GAP_ADDR_TYPE_PUBLIC or
+ * @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC address, the cycle mode must be
+ * @ref BLE_GAP_ADDR_CYCLE_MODE_NONE.
+ *
+ * @note By default the SoftDevice will set an address of type @ref BLE_GAP_ADDR_TYPE_RANDOM_STATIC upon being
+ * enabled. The address is a random number populated during the IC manufacturing process and remains unchanged
+ * for the lifetime of each IC.
+ *
+ * @note If this API function is called while advertising or scanning, the softdevice will immediately update the
+ * advertising or scanning address without the need to stop the procedure in the following cases:
+ *   - If the previously set address is of type @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address
+ *   is also of type @ref BLE_GAP_ADDR_TYPE_PUBLIC
+ *   - If the previously set address is not @ref BLE_GAP_ADDR_TYPE_PUBLIC and the new address is
+ *   also not @ref BLE_GAP_ADDR_TYPE_PUBLIC.
+ * If the address is changed from a @ref BLE_GAP_ADDR_TYPE_PUBLIC address to another type or from
+ * another type to a @ref BLE_GAP_ADDR_TYPE_PUBLIC address, the change will take effect the next
+ * time an advertising or scanning procedure is started.
+ *
+ * @note If the address cycle mode is @ref BLE_GAP_ADDR_CYCLE_MODE_NONE and the application is
+ *       using privacy, the application must take care to generate and set new private addresses
+ *       periodically to comply with the Privacy specification in Bluetooth Core Spec.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @endmscs
+ *
+ * @param[in] addr_cycle_mode Address cycle mode, see @ref BLE_GAP_ADDR_CYCLE_MODES.
+ * @param[in] p_addr          Pointer to address structure.
+ *
+ * @retval ::NRF_SUCCESS Address successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid address.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ */
+SVCALL(SD_BLE_GAP_ADDRESS_SET, uint32_t, sd_ble_gap_address_set(uint8_t addr_cycle_mode, ble_gap_addr_t const *p_addr));
+
+
+/**@brief Get local Bluetooth address.
+ *
+ * @param[out] p_addr Pointer to address structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Address successfully retrieved.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_ADDRESS_GET, uint32_t, sd_ble_gap_address_get(ble_gap_addr_t *p_addr));
+
+
+/**@brief Set, clear or update advertising and scan response data.
+ *
+ * @note The format of the advertising data will be checked by this call to ensure interoperability.
+ *       Limitations imposed by this API call to the data provided include having a flags data type in the scan response data and
+ *       duplicating the local name in the advertising data and scan response data.
+ *
+ * @note To clear the advertising data and set it to a 0-length packet, simply provide a valid pointer (p_data/p_sr_data) with its corresponding
+ *        length (dlen/srdlen) set to 0.
+ *
+ * @note The call will fail if p_data and p_sr_data are both NULL since this would have no effect.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_data    Raw data to be placed in advertising packet. If NULL, no changes are made to the current advertising packet data.
+ * @param[in] dlen      Data length for p_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_data is NULL, can be 0 if p_data is not NULL.
+ * @param[in] p_sr_data Raw data to be placed in scan response packet. If NULL, no changes are made to the current scan response packet data.
+ * @param[in] srdlen    Data length for p_sr_data. Max size: @ref BLE_GAP_ADV_MAX_SIZE octets. Should be 0 if p_sr_data is NULL, can be 0 if p_data is not NULL.
+ *
+ * @retval ::NRF_SUCCESS Advertising data successfully updated or cleared.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, both p_data and p_sr_data cannot be NULL.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_FLAGS Invalid combination of advertising flags supplied.
+ * @retval ::NRF_ERROR_INVALID_DATA Invalid data type(s) supplied, check the advertising data format specification.
+ * @retval ::NRF_ERROR_INVALID_LENGTH Invalid data length(s) supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Unsupported data type.
+ * @retval ::BLE_ERROR_GAP_UUID_LIST_MISMATCH Invalid UUID list supplied.
+ */
+SVCALL(SD_BLE_GAP_ADV_DATA_SET, uint32_t, sd_ble_gap_adv_data_set(uint8_t const *p_data, uint8_t dlen, uint8_t const *p_sr_data, uint8_t srdlen));
+
+
+/**@brief Start advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
+ *
+ * @note An application can start an advertising procedure for broadcasting purposes while a connection
+ *       is active. After a @ref BLE_GAP_EVT_CONNECTED event is received, this function may therefore
+ *       be called to start a broadcast advertising procedure. The advertising procedure
+ *       cannot however be connectable (it must be of type @ref BLE_GAP_ADV_TYPE_ADV_SCAN_IND or
+ *       @ref BLE_GAP_ADV_TYPE_ADV_NONCONN_IND). @note Only one advertiser may be active at any time.
+ *
+ * @note To use the currently active whitelist set p_adv_params->p_whitelist to NULL.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONNECTED, Generated after connection has been established through connectable advertising.}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT, Advertisement has timed out.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_adv_params Pointer to advertising parameters structure.
+ *
+ * @retval ::NRF_SUCCESS The BLE stack has started advertising.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached; connectable advertiser cannot be started.
+ * @retval ::NRF_ERROR_NO_MEM The configured memory pools (see @ref ble_conn_bw_counts_t) are not large enough for the
+ *                            bandwidth selected for this connection.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check the accepted ranges and limits.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Bluetooth address supplied.
+ * @retval ::BLE_ERROR_GAP_DISCOVERABLE_WITH_WHITELIST Discoverable mode and whitelist incompatible.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Observer) and try again
+ */
+SVCALL(SD_BLE_GAP_ADV_START, uint32_t, sd_ble_gap_adv_start(ble_gap_adv_params_t const *p_adv_params));
+
+
+/**@brief Stop advertising (GAP Discoverable, Connectable modes, Broadcast Procedure).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_ADV_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS The BLE stack has stopped advertising.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in advertising state).
+ */
+SVCALL(SD_BLE_GAP_ADV_STOP, uint32_t, sd_ble_gap_adv_stop(void));
+
+
+/**@brief Update connection parameters.
+ *
+ * @details In the central role this will initiate a Link Layer connection parameter update procedure,
+ *          otherwise in the peripheral role, this will send the corresponding L2CAP request and wait for
+ *          the central to perform the procedure. In both cases, and regardless of success or failure, the application
+ *          will be informed of the result with a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE event.
+ *
+ * @details This function can be used as a central both to reply to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST or to start the procedure unrequested.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONN_PARAM_UPDATE, Result of the connection parameter update procedure.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CPU_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CPU_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CPU_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_conn_params  Pointer to desired connection parameters. If NULL is provided on a peripheral role,
+ *                           the parameters in the PPCP characteristic of the GAP service will be used instead.
+ *                           If NULL is provided on a central role and in response to a @ref BLE_GAP_EVT_CONN_PARAM_UPDATE_REQUEST, the peripheral request will be rejected
+ *
+ * @retval ::NRF_SUCCESS The Connection Update procedure has been started successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, check parameter limits and constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, process pending events and wait for pending procedures to complete and retry.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_GAP_CONN_PARAM_UPDATE, uint32_t, sd_ble_gap_conn_param_update(uint16_t conn_handle, ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Disconnect (GAP Link Termination).
+ *
+ * @details This call initiates the disconnection procedure, and its completion will be communicated to the application
+ *          with a @ref BLE_GAP_EVT_DISCONNECTED event.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_DISCONNECTED, Generated when disconnection procedure is complete.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CONN_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] hci_status_code HCI status code, see @ref BLE_HCI_STATUS_CODES (accepted values are @ref BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION and @ref BLE_HCI_CONN_INTERVAL_UNACCEPTABLE).
+ *
+ * @retval ::NRF_SUCCESS The disconnection procedure has been started successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (disconnection is already in progress).
+ */
+SVCALL(SD_BLE_GAP_DISCONNECT, uint32_t, sd_ble_gap_disconnect(uint16_t conn_handle, uint8_t hci_status_code));
+
+
+/**@brief Set the radio's transmit power.
+ *
+ * @param[in] tx_power Radio transmit power in dBm (accepted values are -40, -30, -20, -16, -12, -8, -4, 0, and 4 dBm).
+ *
+ * @note The -30dBm setting is only available on nRF51 series ICs.
+ * @note The -40dBm setting is only available on nRF52 series ICs.
+ *
+ * @retval ::NRF_SUCCESS Successfully changed the transmit power.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_TX_POWER_SET, uint32_t, sd_ble_gap_tx_power_set(int8_t tx_power));
+
+
+/**@brief Set GAP Appearance value.
+ *
+ * @param[in] appearance Appearance (16-bit), see @ref BLE_APPEARANCES.
+ *
+ * @retval ::NRF_SUCCESS  Appearance value set successfully.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_APPEARANCE_SET, uint32_t, sd_ble_gap_appearance_set(uint16_t appearance));
+
+
+/**@brief Get GAP Appearance value.
+ *
+ * @param[out] p_appearance Pointer to appearance (16-bit) to be filled in, see @ref BLE_APPEARANCES.
+ *
+ * @retval ::NRF_SUCCESS Appearance value retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_APPEARANCE_GET, uint32_t, sd_ble_gap_appearance_get(uint16_t *p_appearance));
+
+
+/**@brief Set GAP Peripheral Preferred Connection Parameters.
+ *
+ * @param[in] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure with the desired parameters.
+ *
+ * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_PPCP_SET, uint32_t, sd_ble_gap_ppcp_set(ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Get GAP Peripheral Preferred Connection Parameters.
+ *
+ * @param[out] p_conn_params Pointer to a @ref ble_gap_conn_params_t structure where the parameters will be stored.
+ *
+ * @retval ::NRF_SUCCESS Peripheral Preferred Connection Parameters retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GAP_PPCP_GET, uint32_t, sd_ble_gap_ppcp_get(ble_gap_conn_params_t *p_conn_params));
+
+
+/**@brief Set GAP device name.
+ *
+ * @param[in] p_write_perm Write permissions for the Device Name characteristic, see @ref ble_gap_conn_sec_mode_t.
+ * @param[in] p_dev_name Pointer to a UTF-8 encoded, <b>non NULL-terminated</b> string.
+ * @param[in] len Length of the UTF-8, <b>non NULL-terminated</b> string pointed to by p_dev_name in octets (must be smaller or equal than @ref BLE_GAP_DEVNAME_MAX_LEN).
+ *
+ * @retval ::NRF_SUCCESS GAP device name and permissions set successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_NAME_SET, uint32_t, sd_ble_gap_device_name_set(ble_gap_conn_sec_mode_t const *p_write_perm, uint8_t const *p_dev_name, uint16_t len));
+
+
+/**@brief Get GAP device name.
+ *
+ * @note          If the device name is longer than the size of the supplied buffer,
+ *                p_len will return the complete device name length,
+ *                and not the number of bytes actually returned in p_dev_name.
+ *                The application may use this information to allocate a suitable buffer size.
+ *
+ * @param[out]    p_dev_name Pointer to an empty buffer where the UTF-8 <b>non NULL-terminated</b> string will be placed. Set to NULL to obtain the complete device name length.
+ * @param[in,out] p_len      Length of the buffer pointed by p_dev_name, complete device name length on output.
+ *
+ * @retval ::NRF_SUCCESS GAP device name retrieved successfully.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ */
+SVCALL(SD_BLE_GAP_DEVICE_NAME_GET, uint32_t, sd_ble_gap_device_name_get(uint8_t *p_dev_name, uint16_t *p_len));
+
+
+/**@brief Initiate the GAP Authentication procedure.
+ *
+ * @details In the central role, this function will send an SMP Pairing Request (or an SMP Pairing Failed if rejected),
+ *          otherwise in the peripheral role, an SMP Security Request will be sent.
+ *
+ * @events
+ * @event{Depending on the security parameters set and the packet exchanges with the peer\, the following events may be generated:}
+ * @event{@ref BLE_GAP_EVT_SEC_PARAMS_REQUEST}
+ * @event{@ref BLE_GAP_EVT_SEC_INFO_REQUEST}
+ * @event{@ref BLE_GAP_EVT_PASSKEY_DISPLAY}
+ * @event{@ref BLE_GAP_EVT_KEY_PRESSED}
+ * @event{@ref BLE_GAP_EVT_AUTH_KEY_REQUEST}
+ * @event{@ref BLE_GAP_EVT_LESC_DHKEY_REQUEST}
+ * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE}
+ * @event{@ref BLE_GAP_EVT_AUTH_STATUS}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_SEC_REQ_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_sec_params Pointer to the @ref ble_gap_sec_params_t structure with the security parameters to be used during the pairing or bonding procedure.
+ *                         In the peripheral role, only the bond, mitm, lesc and keypress fields of this structure are used.
+ *                         In the central role, this pointer may be NULL to reject a Security Request.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::NRF_ERROR_NO_MEM The maximum number of authentication procedures that can run in parallel for the given role is reached.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
+ * @retval ::NRF_ERROR_TIMEOUT A SMP timeout has occurred, and further SMP operations on this link is prohibited.
+ */
+SVCALL(SD_BLE_GAP_AUTHENTICATE, uint32_t, sd_ble_gap_authenticate(uint16_t conn_handle, ble_gap_sec_params_t const *p_sec_params));
+
+
+/**@brief Reply with GAP security parameters.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_STATIC_PK_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_CONFIRM_FAIL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_KS_TOO_SMALL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_APP_ERROR_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_REMOTE_PAIRING_FAIL_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_PAIRING_TIMEOUT_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] sec_status Security status, see @ref BLE_GAP_SEC_STATUS.
+ * @param[in] p_sec_params Pointer to a @ref ble_gap_sec_params_t security parameters structure. In the central role this must be set to NULL, as the parameters have
+ *                         already been provided during a previous call to @ref sd_ble_gap_authenticate.
+ * @param[in,out] p_sec_keyset Pointer to a @ref ble_gap_sec_keyset_t security keyset structure. Any keys generated and/or distributed as a result of the ongoing security procedure
+ *                         will be stored into the memory referenced by the pointers inside this structure. The keys will be stored and available to the application
+ *                         upon reception of a @ref BLE_GAP_EVT_AUTH_STATUS event.
+ *                         Note that the SoftDevice expects the application to provide memory for storing the
+ *                         peer's keys. So it must be ensured that the relevant pointers inside this structure are not NULL. The pointers to the local key
+ *                         can, however, be NULL, in which case, the local key data will not be available to the application upon reception of the
+ *                         @ref BLE_GAP_EVT_AUTH_STATUS event.
+ *
+ * @retval ::NRF_SUCCESS Successfully accepted security parameter from the application.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Setting of sign or link fields in @ref ble_gap_sec_kdist_t not supported.
+ */
+SVCALL(SD_BLE_GAP_SEC_PARAMS_REPLY, uint32_t, sd_ble_gap_sec_params_reply(uint16_t conn_handle, uint8_t sec_status, ble_gap_sec_params_t const *p_sec_params, ble_gap_sec_keyset_t const *p_sec_keyset));
+
+
+/**@brief Reply with an authentication key.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_AUTH_KEY_REQUEST or a @ref BLE_GAP_EVT_PASSKEY_DISPLAY, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_BONDING_PK_CENTRAL_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_BONDING_PK_PERIPH_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] key_type See @ref BLE_GAP_AUTH_KEY_TYPES.
+ * @param[in] p_key If key type is @ref BLE_GAP_AUTH_KEY_TYPE_NONE, then NULL.
+ *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_PASSKEY, then a 6-byte ASCII string (digit 0..9 only, no NULL termination)
+ *                     or NULL when confirming LE Secure Connections Numeric Comparison.
+ *                  If key type is @ref BLE_GAP_AUTH_KEY_TYPE_OOB, then a 16-byte OOB key value in Little Endian format.
+ *
+ * @retval ::NRF_SUCCESS Authentication key successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_AUTH_KEY_REPLY, uint32_t, sd_ble_gap_auth_key_reply(uint16_t conn_handle, uint8_t key_type, uint8_t const *p_key));
+
+/**@brief Reply with an LE Secure connections DHKey.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST, calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_PAIRING_JW_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_NC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_PD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_dhkey LE Secure Connections DHKey.
+ *
+ * @retval ::NRF_SUCCESS DHKey successfully set.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_DHKEY_REPLY, uint32_t, sd_ble_gap_lesc_dhkey_reply(uint16_t conn_handle, ble_gap_lesc_dhkey_t const *p_dhkey));
+
+/**@brief Notify the peer of a local keypress.
+ *
+ * @details This function can only be used when an authentication procedure using LE Secure Connection is in progress. Calling it at other times will result in an @ref NRF_ERROR_INVALID_STATE.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_PKE_CD_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_PKE_CD_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] kp_not See @ref BLE_GAP_KP_NOT_TYPES.
+ *
+ * @retval ::NRF_SUCCESS Keypress notification successfully queued for transmission.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation. Either not entering a passkey or keypresses have not been enabled by both peers.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_BUSY The BLE stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GAP_KEYPRESS_NOTIFY, uint32_t, sd_ble_gap_keypress_notify(uint16_t conn_handle, uint8_t kp_not));
+
+/**@brief Generate a set of OOB data to send to a peer out of band.
+ *
+ * @note The @ref ble_gap_addr_t included in the OOB data returned will be the currently active one (or, if a connection has already been established,
+ *       the one used during connection setup). The application may manually overwrite it with an updated value.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle. Can be BLE_CONN_HANDLE_INVALID if a BLE connection has not been established yet.
+ * @param[in] p_pk_own LE Secure Connections local P-256 Public Key.
+ * @param[out] p_oobd_own The OOB data to be sent out of band to a peer.
+ *
+ * @retval ::NRF_SUCCESS OOB data successfully generated.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_OOB_DATA_GET, uint32_t, sd_ble_gap_lesc_oob_data_get(uint16_t conn_handle, ble_gap_lesc_p256_pk_t const *p_pk_own, ble_gap_lesc_oob_data_t *p_oobd_own));
+
+/**@brief Provide the OOB data sent/received out of band.
+ *
+ * @note At least one of the 2 pointers provided must be different from NULL.
+ * @note An authentication procedure with OOB selected as an algorithm must be in progress when calling this function.
+ * @note A @ref BLE_GAP_EVT_LESC_DHKEY_REQUEST event with the oobd_req set to 1 must have been received prior to calling this function.
+ *
+ * @events
+ * @event{This function is used during authentication procedures\, see the list of events in the documentation of @ref sd_ble_gap_authenticate.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_LESC_BONDING_OOB_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_LESC_BONDING_OOB_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_oobd_own The OOB data sent out of band to a peer or NULL if none sent.
+ * @param[in] p_oobd_peer The OOB data received out of band from a peer or NULL if none received.
+ *
+ * @retval ::NRF_SUCCESS OOB data accepted.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_LESC_OOB_DATA_SET, uint32_t, sd_ble_gap_lesc_oob_data_set(uint16_t conn_handle, ble_gap_lesc_oob_data_t const *p_oobd_own, ble_gap_lesc_oob_data_t const *p_oobd_peer));
+
+/**@brief Initiate GAP Encryption procedure.
+ *
+ * @details In the central role, this function will initiate the encryption procedure using the encryption information provided.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_CONN_SEC_UPDATE, The connection security has been updated.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_AUTH_MUTEX_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_ENC_MSC}
+ * @mmsc{@ref BLE_GAP_MULTILINK_CTRL_PROC_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_SEC_REQ_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_master_id Pointer to a @ref ble_gap_master_id_t master identification structure.
+ * @param[in] p_enc_info  Pointer to a @ref ble_gap_enc_info_t encryption information structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated authentication procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_INVALID_ROLE Operation is not supported in the Peripheral role.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress or not allowed at this time, wait for pending procedures to complete and retry.
+ */
+SVCALL(SD_BLE_GAP_ENCRYPT, uint32_t, sd_ble_gap_encrypt(uint16_t conn_handle, ble_gap_master_id_t const *p_master_id, ble_gap_enc_info_t const *p_enc_info));
+
+
+/**@brief Reply with GAP security information.
+ *
+ * @details This function is only used to reply to a @ref BLE_GAP_EVT_SEC_INFO_REQUEST, calling it at other times will result in @ref NRF_ERROR_INVALID_STATE.
+ * @note    If the call returns an error code, the request is still pending, and the reply call may be repeated with corrected parameters.
+ * @note    Data signing is not yet supported, and p_sign_info must therefore be NULL.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_PERIPH_ENC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ * @param[in] p_enc_info Pointer to a @ref ble_gap_enc_info_t encryption information structure. May be NULL to signal none is available.
+ * @param[in] p_id_info Pointer to a @ref ble_gap_irk_t identity information structure. May be NULL to signal none is available.
+ * @param[in] p_sign_info Pointer to a @ref ble_gap_sign_info_t signing information structure. May be NULL to signal none is available.
+ *
+ * @retval ::NRF_SUCCESS Successfully accepted security information.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_SEC_INFO_REPLY, uint32_t, sd_ble_gap_sec_info_reply(uint16_t conn_handle, ble_gap_enc_info_t const *p_enc_info, ble_gap_irk_t const *p_id_info, ble_gap_sign_info_t const *p_sign_info));
+
+
+/**@brief Get the current connection security.
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_conn_sec  Pointer to a @ref ble_gap_conn_sec_t structure to be filled in.
+ *
+ * @retval ::NRF_SUCCESS Current connection security successfully retrieved.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_CONN_SEC_GET, uint32_t, sd_ble_gap_conn_sec_get(uint16_t conn_handle, ble_gap_conn_sec_t *p_conn_sec));
+
+
+/**@brief Start reporting the received signal strength to the application.
+ *
+ * A new event is reported whenever the RSSI value changes, until @ref sd_ble_gap_rssi_stop is called.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_RSSI_CHANGED, New RSSI data available. How often the event is generated is
+                                         dependent on the settings of the <code>threshold_dbm</code>
+                                         and <code>skip_count</code> input parameters.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle        Connection handle.
+ * @param[in] threshold_dbm      Minimum change in dBm before triggering the @ref BLE_GAP_EVT_RSSI_CHANGED event. Events are disabled if threshold_dbm equals @ref BLE_GAP_RSSI_THRESHOLD_INVALID.
+ * @param[in] skip_count         Number of RSSI samples with a change of threshold_dbm or more before sending a new @ref BLE_GAP_EVT_RSSI_CHANGED event.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully activated RSSI reporting.
+ * @retval ::NRF_ERROR_INVALID_STATE       Disconnection in progress. Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_RSSI_START, uint32_t, sd_ble_gap_rssi_start(uint16_t conn_handle, uint8_t threshold_dbm, uint8_t skip_count));
+
+
+/**@brief Stop reporting the received signal strength.
+ *
+ * @note An RSSI change detected before the call but not yet received by the application
+ * may be reported after @ref sd_ble_gap_rssi_stop has been called.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @mmsc{@ref BLE_GAP_RSSI_FILT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection handle.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully deactivated RSSI reporting.
+ * @retval ::NRF_ERROR_INVALID_STATE       Invalid state to perform operation.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ */
+SVCALL(SD_BLE_GAP_RSSI_STOP, uint32_t, sd_ble_gap_rssi_stop(uint16_t conn_handle));
+
+
+/**@brief Get the received signal strength for the last connection event.
+ *
+ * @ref sd_ble_gap_rssi_start must be called to start reporting RSSI before using this function. @ref NRF_ERROR_NOT_FOUND
+ * will be returned until RSSI was sampled for the first time after calling @ref sd_ble_gap_rssi_start.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_RSSI_READ_MSC}
+ * @endmscs
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[out] p_rssi      Pointer to the location where the RSSI measurement shall be stored.
+ *
+ * @retval ::NRF_SUCCESS                   Successfully read the RSSI.
+ * @retval ::NRF_ERROR_NOT_FOUND           No sample is available.
+ * @retval ::NRF_ERROR_INVALID_ADDR        Invalid pointer supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE       RSSI reporting is not ongoing, or disconnection in progress.
+ */
+SVCALL(SD_BLE_GAP_RSSI_GET, uint32_t, sd_ble_gap_rssi_get(uint16_t conn_handle, int8_t *p_rssi));
+
+
+/**@brief Start scanning (GAP Discovery procedure, Observer Procedure).
+ *
+ * @note To use the currently active whitelist set p_scan_params->p_whitelist to NULL.
+ *
+ * @events
+ * @event{@ref BLE_GAP_EVT_ADV_REPORT, An advertising or scan response packet has been received.}
+ * @event{@ref BLE_GAP_EVT_TIMEOUT, Scanner has timed out.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @param[in] p_scan_params Pointer to scan parameters structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated scanning procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
+ */
+SVCALL(SD_BLE_GAP_SCAN_START, uint32_t, sd_ble_gap_scan_start(ble_gap_scan_params_t const *p_scan_params));
+
+
+/**@brief Stop scanning (GAP Discovery procedure, Observer Procedure).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_SCAN_MSC}
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully stopped scanning procedure.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation (most probably not in scanning state).
+ */
+SVCALL(SD_BLE_GAP_SCAN_STOP, uint32_t, sd_ble_gap_scan_stop(void));
+
+
+/**@brief Create a connection (GAP Link Establishment).
+ *
+ * @note To use the currently active whitelist set p_scan_params->p_whitelist to NULL.
+ * @note If a scanning procedure is currently in progress it will be automatically stopped when calling this function.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_WL_SHARE_MSC}
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
+ * @endmscs
+ *
+ * @param[in] p_peer_addr   Pointer to peer address. If the selective bit is set in @ref ble_gap_scan_params_t, then this must be NULL.
+ * @param[in] p_scan_params Pointer to scan parameters structure.
+ * @param[in] p_conn_params Pointer to desired connection parameters.
+ *
+ * @retval ::NRF_SUCCESS Successfully initiated connection procedure.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid parameter(s) pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::BLE_ERROR_GAP_INVALID_BLE_ADDR Invalid Peer address.
+ * @retval ::NRF_ERROR_CONN_COUNT The limit of available connections has been reached.
+ * @retval ::NRF_ERROR_NO_MEM The configured memory pool (see @ref ble_conn_bw_counts_t) is not large enough for the
+ *                            bandwidth selected for this connection.
+ * @retval ::NRF_ERROR_BUSY The stack is busy, process pending events and retry. If another connection is being established
+ *                          wait for the corresponding @ref BLE_GAP_EVT_CONNECTED event before calling again.
+ * @retval ::BLE_ERROR_GAP_WHITELIST_IN_USE Unable to replace the whitelist while another operation is using it.
+ * @retval ::NRF_ERROR_RESOURCES Not enough BLE role slots available.
+ *                               Stop one or more currently active roles (Central, Peripheral or Broadcaster) and try again
+ */
+SVCALL(SD_BLE_GAP_CONNECT, uint32_t, sd_ble_gap_connect(ble_gap_addr_t const *p_peer_addr, ble_gap_scan_params_t const *p_scan_params, ble_gap_conn_params_t const *p_conn_params));
+
+
+/**@brief Cancel a connection establishment.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GAP_CENTRAL_CONN_MSC}
+ * @endmscs
+ *
+ * @retval ::NRF_SUCCESS Successfully cancelled an ongoing connection procedure.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ */
+SVCALL(SD_BLE_GAP_CONNECT_CANCEL, uint32_t, sd_ble_gap_connect_cancel(void));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_GAP_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gatt.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gatt.h
new file mode 100644
index 0000000000..c7023502bd
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gatt.h
@@ -0,0 +1,215 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GATT Generic Attribute Profile (GATT) Common
+  @{
+  @brief  Common definitions and prototypes for the GATT interfaces.
+ */
+
+#ifndef NRF_BLE_GATT_H__
+#define NRF_BLE_GATT_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATT_DEFINES Defines
+ * @{ */
+
+/** @brief Default MTU size. */
+#define GATT_MTU_SIZE_DEFAULT 23
+
+/** @brief Only the default MTU size of 23 is currently supported. */
+#define GATT_RX_MTU 23
+
+
+/**@brief Invalid Attribute Handle. */
+#define BLE_GATT_HANDLE_INVALID            0x0000
+
+/**@brief First Attribute Handle. */
+#define BLE_GATT_HANDLE_START              0x0001
+
+/**@brief Last Attribute Handle. */
+#define BLE_GATT_HANDLE_END                0xFFFF
+
+/** @defgroup BLE_GATT_TIMEOUT_SOURCES GATT Timeout sources
+ * @{ */
+#define BLE_GATT_TIMEOUT_SRC_PROTOCOL                  0x00 /**< ATT Protocol timeout. */
+/** @} */
+
+/** @defgroup BLE_GATT_WRITE_OPS GATT Write operations
+ * @{ */
+#define BLE_GATT_OP_INVALID                0x00  /**< Invalid Operation. */
+#define BLE_GATT_OP_WRITE_REQ              0x01  /**< Write Request. */
+#define BLE_GATT_OP_WRITE_CMD              0x02  /**< Write Command. */
+#define BLE_GATT_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
+#define BLE_GATT_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
+#define BLE_GATT_OP_EXEC_WRITE_REQ         0x05  /**< Execute Write Request. */
+/** @} */
+
+/** @defgroup BLE_GATT_EXEC_WRITE_FLAGS GATT Execute Write flags
+ * @{ */
+#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_CANCEL 0x00
+#define BLE_GATT_EXEC_WRITE_FLAG_PREPARED_WRITE  0x01
+/** @} */
+
+/** @defgroup BLE_GATT_HVX_TYPES GATT Handle Value operations
+ * @{ */
+#define BLE_GATT_HVX_INVALID               0x00  /**< Invalid Operation. */
+#define BLE_GATT_HVX_NOTIFICATION          0x01  /**< Handle Value Notification. */
+#define BLE_GATT_HVX_INDICATION            0x02  /**< Handle Value Indication. */
+/** @} */
+
+/** @defgroup BLE_GATT_STATUS_CODES GATT Status Codes
+ * @{ */
+#define BLE_GATT_STATUS_SUCCESS                           0x0000  /**< Success. */
+#define BLE_GATT_STATUS_UNKNOWN                           0x0001  /**< Unknown or not applicable status. */
+#define BLE_GATT_STATUS_ATTERR_INVALID                    0x0100  /**< ATT Error: Invalid Error Code. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_HANDLE             0x0101  /**< ATT Error: Invalid Attribute Handle. */
+#define BLE_GATT_STATUS_ATTERR_READ_NOT_PERMITTED         0x0102  /**< ATT Error: Read not permitted. */
+#define BLE_GATT_STATUS_ATTERR_WRITE_NOT_PERMITTED        0x0103  /**< ATT Error: Write not permitted. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_PDU                0x0104  /**< ATT Error: Used in ATT as Invalid PDU. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHENTICATION       0x0105  /**< ATT Error: Authenticated link required. */
+#define BLE_GATT_STATUS_ATTERR_REQUEST_NOT_SUPPORTED      0x0106  /**< ATT Error: Used in ATT as Request Not Supported. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_OFFSET             0x0107  /**< ATT Error: Offset specified was past the end of the attribute. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_AUTHORIZATION        0x0108  /**< ATT Error: Used in ATT as Insufficient Authorisation. */
+#define BLE_GATT_STATUS_ATTERR_PREPARE_QUEUE_FULL         0x0109  /**< ATT Error: Used in ATT as Prepare Queue Full. */
+#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_FOUND        0x010A  /**< ATT Error: Used in ATT as Attribute not found. */
+#define BLE_GATT_STATUS_ATTERR_ATTRIBUTE_NOT_LONG         0x010B  /**< ATT Error: Attribute cannot be read or written using read/write blob requests. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_ENC_KEY_SIZE         0x010C  /**< ATT Error: Encryption key size used is insufficient. */
+#define BLE_GATT_STATUS_ATTERR_INVALID_ATT_VAL_LENGTH     0x010D  /**< ATT Error: Invalid value size. */
+#define BLE_GATT_STATUS_ATTERR_UNLIKELY_ERROR             0x010E  /**< ATT Error: Very unlikely error. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_ENCRYPTION           0x010F  /**< ATT Error: Encrypted link required. */
+#define BLE_GATT_STATUS_ATTERR_UNSUPPORTED_GROUP_TYPE     0x0110  /**< ATT Error: Attribute type is not a supported grouping attribute. */
+#define BLE_GATT_STATUS_ATTERR_INSUF_RESOURCES            0x0111  /**< ATT Error: Encrypted link required. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_BEGIN           0x0112  /**< ATT Error: Reserved for Future Use range #1 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE1_END             0x017F  /**< ATT Error: Reserved for Future Use range #1 end. */
+#define BLE_GATT_STATUS_ATTERR_APP_BEGIN                  0x0180  /**< ATT Error: Application range begin. */
+#define BLE_GATT_STATUS_ATTERR_APP_END                    0x019F  /**< ATT Error: Application range end. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_BEGIN           0x01A0  /**< ATT Error: Reserved for Future Use range #2 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE2_END             0x01DF  /**< ATT Error: Reserved for Future Use range #2 end. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_BEGIN           0x01E0  /**< ATT Error: Reserved for Future Use range #3 begin. */
+#define BLE_GATT_STATUS_ATTERR_RFU_RANGE3_END             0x01FC  /**< ATT Error: Reserved for Future Use range #3 end. */
+#define BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR      0x01FD  /**< ATT Common Profile and Service Error: Client Characteristic Configuration Descriptor improperly configured. */
+#define BLE_GATT_STATUS_ATTERR_CPS_PROC_ALR_IN_PROG       0x01FE  /**< ATT Common Profile and Service Error: Procedure Already in Progress. */
+#define BLE_GATT_STATUS_ATTERR_CPS_OUT_OF_RANGE           0x01FF  /**< ATT Common Profile and Service Error: Out Of Range. */
+/** @} */
+
+
+/** @defgroup BLE_GATT_CPF_FORMATS Characteristic Presentation Formats
+ *  @note Found at http://developer.bluetooth.org/gatt/descriptors/Pages/DescriptorViewer.aspx?u=org.bluetooth.descriptor.gatt.characteristic_presentation_format.xml
+ * @{ */
+#define BLE_GATT_CPF_FORMAT_RFU                 0x00 /**< Reserved For Future Use. */
+#define BLE_GATT_CPF_FORMAT_BOOLEAN             0x01 /**< Boolean. */
+#define BLE_GATT_CPF_FORMAT_2BIT                0x02 /**< Unsigned 2-bit integer. */
+#define BLE_GATT_CPF_FORMAT_NIBBLE              0x03 /**< Unsigned 4-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT8               0x04 /**< Unsigned 8-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT12              0x05 /**< Unsigned 12-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT16              0x06 /**< Unsigned 16-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT24              0x07 /**< Unsigned 24-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT32              0x08 /**< Unsigned 32-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT48              0x09 /**< Unsigned 48-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT64              0x0A /**< Unsigned 64-bit integer. */
+#define BLE_GATT_CPF_FORMAT_UINT128             0x0B /**< Unsigned 128-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT8               0x0C /**< Signed 2-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT12              0x0D /**< Signed 12-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT16              0x0E /**< Signed 16-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT24              0x0F /**< Signed 24-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT32              0x10 /**< Signed 32-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT48              0x11 /**< Signed 48-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT64              0x12 /**< Signed 64-bit integer. */
+#define BLE_GATT_CPF_FORMAT_SINT128             0x13 /**< Signed 128-bit integer. */
+#define BLE_GATT_CPF_FORMAT_FLOAT32             0x14 /**< IEEE-754 32-bit floating point. */
+#define BLE_GATT_CPF_FORMAT_FLOAT64             0x15 /**< IEEE-754 64-bit floating point. */
+#define BLE_GATT_CPF_FORMAT_SFLOAT              0x16 /**< IEEE-11073 16-bit SFLOAT. */
+#define BLE_GATT_CPF_FORMAT_FLOAT               0x17 /**< IEEE-11073 32-bit FLOAT. */
+#define BLE_GATT_CPF_FORMAT_DUINT16             0x18 /**< IEEE-20601 format. */
+#define BLE_GATT_CPF_FORMAT_UTF8S               0x19 /**< UTF-8 string. */
+#define BLE_GATT_CPF_FORMAT_UTF16S              0x1A /**< UTF-16 string. */
+#define BLE_GATT_CPF_FORMAT_STRUCT              0x1B /**< Opaque Structure. */
+/** @} */
+
+/** @defgroup BLE_GATT_CPF_NAMESPACES GATT Bluetooth Namespaces
+ * @{
+ */
+#define BLE_GATT_CPF_NAMESPACE_BTSIG            0x01 /**< Bluetooth SIG defined Namespace. */
+#define BLE_GATT_CPF_NAMESPACE_DESCRIPTION_UNKNOWN 0x0000 /**< Namespace Description Unknown. */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATT_STRUCTURES Structures
+ * @{ */
+
+/**@brief GATT Characteristic Properties. */
+typedef struct
+{
+  /* Standard properties */
+  uint8_t broadcast       :1; /**< Broadcasting of the value permitted. */
+  uint8_t read            :1; /**< Reading the value permitted. */
+  uint8_t write_wo_resp   :1; /**< Writing the value with Write Command permitted. */
+  uint8_t write           :1; /**< Writing the value with Write Request permitted. */
+  uint8_t notify          :1; /**< Notications of the value permitted. */
+  uint8_t indicate        :1; /**< Indications of the value permitted. */
+  uint8_t auth_signed_wr  :1; /**< Writing the value with Signed Write Command permitted. */
+} ble_gatt_char_props_t;
+
+/**@brief GATT Characteristic Extended Properties. */
+typedef struct
+{
+  /* Extended properties */
+  uint8_t reliable_wr     :1; /**< Writing the value with Queued Write operations permitted. */
+  uint8_t wr_aux          :1; /**< Writing the Characteristic User Description descriptor permitted. */
+} ble_gatt_char_ext_props_t;
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_GATT_H__
+
+/** @} */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h
new file mode 100644
index 0000000000..5aa20fe430
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gattc.h
@@ -0,0 +1,572 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GATTC Generic Attribute Profile (GATT) Client
+  @{
+  @brief  Definitions and prototypes for the GATT Client interface.
+ */
+
+#ifndef NRF_BLE_GATTC_H__
+#define NRF_BLE_GATTC_H__
+
+#include "nrf_ble_gatt.h"
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATTC_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief GATTC API SVC numbers. */
+enum BLE_GATTC_SVCS
+{
+  SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER = BLE_GATTC_SVC_BASE, /**< Primary Service Discovery. */
+  SD_BLE_GATTC_RELATIONSHIPS_DISCOVER,                         /**< Relationship Discovery. */
+  SD_BLE_GATTC_CHARACTERISTICS_DISCOVER,                       /**< Characteristic Discovery. */
+  SD_BLE_GATTC_DESCRIPTORS_DISCOVER,                           /**< Characteristic Descriptor Discovery. */
+  SD_BLE_GATTC_ATTR_INFO_DISCOVER,                             /**< Attribute Information Discovery. */
+  SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ,                        /**< Read Characteristic Value by UUID. */
+  SD_BLE_GATTC_READ,                                           /**< Generic read. */
+  SD_BLE_GATTC_CHAR_VALUES_READ,                               /**< Read multiple Characteristic Values. */
+  SD_BLE_GATTC_WRITE,                                          /**< Generic write. */
+  SD_BLE_GATTC_HV_CONFIRM,                                     /**< Handle Value Confirmation. */
+};
+
+/**
+ * @brief GATT Client Event IDs.
+ */
+enum BLE_GATTC_EVTS
+{
+  BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP = BLE_GATTC_EVT_BASE,  /**< Primary Service Discovery Response event.      \n See @ref ble_gattc_evt_prim_srvc_disc_rsp_t.          */
+  BLE_GATTC_EVT_REL_DISC_RSP,                             /**< Relationship Discovery Response event.         \n See @ref ble_gattc_evt_rel_disc_rsp_t.                */
+  BLE_GATTC_EVT_CHAR_DISC_RSP,                            /**< Characteristic Discovery Response event.       \n See @ref ble_gattc_evt_char_disc_rsp_t.               */
+  BLE_GATTC_EVT_DESC_DISC_RSP,                            /**< Descriptor Discovery Response event.           \n See @ref ble_gattc_evt_desc_disc_rsp_t.               */
+  BLE_GATTC_EVT_ATTR_INFO_DISC_RSP,                       /**< Attribute Information Response event.          \n See @ref ble_gattc_evt_attr_info_disc_rsp_t. */
+  BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP,                /**< Read By UUID Response event.                   \n See @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t.   */
+  BLE_GATTC_EVT_READ_RSP,                                 /**< Read Response event.                           \n See @ref ble_gattc_evt_read_rsp_t.                    */
+  BLE_GATTC_EVT_CHAR_VALS_READ_RSP,                       /**< Read multiple Response event.                  \n See @ref ble_gattc_evt_char_vals_read_rsp_t.          */
+  BLE_GATTC_EVT_WRITE_RSP,                                /**< Write Response event.                          \n See @ref ble_gattc_evt_write_rsp_t.                   */
+  BLE_GATTC_EVT_HVX,                                      /**< Handle Value Notification or Indication event. \n Confirm indication with @ref sd_ble_gattc_hv_confirm.  \n See @ref ble_gattc_evt_hvx_t. */
+  BLE_GATTC_EVT_TIMEOUT                                   /**< Timeout event.                                 \n See @ref ble_gattc_evt_timeout_t.                     */
+};
+
+/** @} */
+
+/** @addtogroup BLE_GATTC_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_ERRORS_GATTC SVC return values specific to GATTC
+ * @{ */
+#define BLE_ERROR_GATTC_PROC_NOT_PERMITTED    (NRF_GATTC_ERR_BASE + 0x000) /**< Procedure not Permitted. */
+/** @} */
+
+/** @defgroup BLE_GATTC_ATTR_INFO_FORMAT Attribute Information Formats
+ * @{ */
+#define BLE_GATTC_ATTR_INFO_FORMAT_16BIT    1 /**< 16-bit Attribute Information Format. */
+#define BLE_GATTC_ATTR_INFO_FORMAT_128BIT   2 /**< 128-bit Attribute Information Format. */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATTC_STRUCTURES Structures
+ * @{ */
+
+/**@brief Operation Handle Range. */
+typedef struct
+{
+  uint16_t          start_handle; /**< Start Handle. */
+  uint16_t          end_handle;   /**< End Handle. */
+} ble_gattc_handle_range_t;
+
+
+/**@brief GATT service. */
+typedef struct
+{
+  ble_uuid_t               uuid;          /**< Service UUID. */
+  ble_gattc_handle_range_t handle_range;  /**< Service Handle Range. */
+} ble_gattc_service_t;
+
+
+/**@brief  GATT include. */
+typedef struct
+{
+  uint16_t            handle;           /**< Include Handle. */
+  ble_gattc_service_t included_srvc;    /**< Handle of the included service. */
+} ble_gattc_include_t;
+
+
+/**@brief GATT characteristic. */
+typedef struct
+{
+  ble_uuid_t              uuid;                 /**< Characteristic UUID. */
+  ble_gatt_char_props_t   char_props;           /**< Characteristic Properties. */
+  uint8_t                 char_ext_props : 1;   /**< Extended properties present. */
+  uint16_t                handle_decl;          /**< Handle of the Characteristic Declaration. */
+  uint16_t                handle_value;         /**< Handle of the Characteristic Value. */
+} ble_gattc_char_t;
+
+
+/**@brief GATT descriptor. */
+typedef struct
+{
+  uint16_t          handle;         /**< Descriptor Handle. */
+  ble_uuid_t        uuid;           /**< Descriptor UUID. */
+} ble_gattc_desc_t;
+
+
+/**@brief Write Parameters. */
+typedef struct
+{
+  uint8_t    write_op;                 /**< Write Operation to be performed, see @ref BLE_GATT_WRITE_OPS. */
+  uint8_t    flags;                    /**< Flags, see @ref BLE_GATT_EXEC_WRITE_FLAGS. */
+  uint16_t   handle;                   /**< Handle to the attribute to be written. */
+  uint16_t   offset;                   /**< Offset in bytes. @note For WRITE_CMD and WRITE_REQ, offset must be 0. */
+  uint16_t   len;                      /**< Length of data in bytes. */
+  uint8_t   *p_value;                  /**< Pointer to the value data. */
+} ble_gattc_write_params_t;
+
+/**@brief Attribute Information. */
+typedef struct
+{
+  uint16_t      handle;                /**< Attribute handle. */
+  union {
+    ble_uuid_t    uuid16;              /**< 16-bit Attribute UUID. */
+    ble_uuid128_t uuid128;             /**< 128-bit Attribute UUID. */
+  } info;
+} ble_gattc_attr_info_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP. */
+typedef struct
+{
+  uint16_t             count;           /**< Service count. */
+  ble_gattc_service_t services[1];      /**< Service data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_prim_srvc_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_REL_DISC_RSP. */
+typedef struct
+{
+  uint16_t             count;           /**< Include count. */
+  ble_gattc_include_t includes[1];      /**< Include data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_rel_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_DISC_RSP. */
+typedef struct
+{
+  uint16_t            count;          /**< Characteristic count. */
+  ble_gattc_char_t    chars[1];       /**< Characteristic data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_DESC_DISC_RSP. */
+typedef struct
+{
+  uint16_t            count;          /**< Descriptor count. */
+  ble_gattc_desc_t    descs[1];       /**< Descriptor data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_desc_disc_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP. */
+typedef struct
+{
+  uint16_t                     count;        /**< Attribute count. */
+  uint8_t                      format;       /**< Attribute information format, see @ref BLE_GATTC_ATTR_INFO_FORMAT. */
+  ble_gattc_attr_info_t        attr_info[1]; /**< Attribute information. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_attr_info_disc_rsp_t;
+
+/**@brief GATT read by UUID handle value pair. */
+typedef struct
+{
+  uint16_t            handle;          /**< Attribute Handle. */
+  uint8_t             *p_value;        /**< Pointer to value, variable length (length available as value_len in @ref ble_gattc_evt_char_val_by_uuid_read_rsp_t).
+                                            Please note that this pointer is absolute to the memory provided by the user when retrieving the event,
+                                            so it will effectively point to a location inside the handle_value array. */
+} ble_gattc_handle_value_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP. */
+typedef struct
+{
+  uint16_t                  count;            /**< Handle-Value Pair Count. */
+  uint16_t                  value_len;        /**< Length of the value in Handle-Value(s) list. */
+  ble_gattc_handle_value_t  handle_value[1];  /**< Handle-Value(s) list. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                   See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_val_by_uuid_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_READ_RSP. */
+typedef struct
+{
+  uint16_t            handle;         /**< Attribute Handle. */
+  uint16_t            offset;         /**< Offset of the attribute data. */
+  uint16_t            len;            /**< Attribute data length. */
+  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP. */
+typedef struct
+{
+  uint16_t            len;            /**< Concatenated Attribute values length. */
+  uint8_t             values[1];      /**< Attribute values. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_char_vals_read_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_WRITE_RSP. */
+typedef struct
+{
+  uint16_t            handle;           /**< Attribute Handle. */
+  uint8_t             write_op;         /**< Type of write operation, see @ref BLE_GATT_WRITE_OPS. */
+  uint16_t            offset;           /**< Data offset. */
+  uint16_t            len;              /**< Data length. */
+  uint8_t             data[1];          /**< Data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                             See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_write_rsp_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_HVX. */
+typedef struct
+{
+  uint16_t            handle;         /**< Handle to which the HVx operation applies. */
+  uint8_t             type;           /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
+  uint16_t            len;            /**< Attribute data length. */
+  uint8_t             data[1];        /**< Attribute data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                           See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gattc_evt_hvx_t;
+
+/**@brief Event structure for @ref BLE_GATTC_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
+} ble_gattc_evt_timeout_t;
+
+/**@brief GATTC event structure. */
+typedef struct
+{
+  uint16_t            conn_handle;                /**< Connection Handle on which event occured. */
+  uint16_t            gatt_status;                /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
+  uint16_t            error_handle;               /**< In case of error: The handle causing the error. In all other cases @ref BLE_GATT_HANDLE_INVALID. */
+  union
+  {
+    ble_gattc_evt_prim_srvc_disc_rsp_t          prim_srvc_disc_rsp;         /**< Primary Service Discovery Response Event Parameters. */
+    ble_gattc_evt_rel_disc_rsp_t                rel_disc_rsp;               /**< Relationship Discovery Response Event Parameters. */
+    ble_gattc_evt_char_disc_rsp_t               char_disc_rsp;              /**< Characteristic Discovery Response Event Parameters. */
+    ble_gattc_evt_desc_disc_rsp_t               desc_disc_rsp;              /**< Descriptor Discovery Response Event Parameters. */
+    ble_gattc_evt_char_val_by_uuid_read_rsp_t   char_val_by_uuid_read_rsp;  /**< Characteristic Value Read by UUID Response Event Parameters. */
+    ble_gattc_evt_read_rsp_t                    read_rsp;                   /**< Read Response Event Parameters. */
+    ble_gattc_evt_char_vals_read_rsp_t          char_vals_read_rsp;         /**< Characteristic Values Read Response Event Parameters. */
+    ble_gattc_evt_write_rsp_t                   write_rsp;                  /**< Write Response Event Parameters. */
+    ble_gattc_evt_hvx_t                         hvx;                        /**< Handle Value Notification/Indication Event Parameters. */
+    ble_gattc_evt_timeout_t                     timeout;                    /**< Timeout Event Parameters. */
+    ble_gattc_evt_attr_info_disc_rsp_t          attr_info_disc_rsp;         /**< Attribute Information Discovery Event Parameters. */
+  } params;                                                                 /**< Event Parameters. @note Only valid if @ref gatt_status == @ref BLE_GATT_STATUS_SUCCESS. */
+} ble_gattc_evt_t;
+/** @} */
+
+/** @addtogroup BLE_GATTC_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Initiate or continue a GATT Primary Service Discovery procedure.
+ *
+ * @details This function initiates or resumes a Primary Service discovery procedure, starting from the supplied handle.
+ *          If the last service has not been reached, this function must be called again with an updated start handle value to continue the search.
+ *
+ * @note If any of the discovered services have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
+ *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_PRIM_SRVC_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] start_handle Handle to start searching from.
+ * @param[in] p_srvc_uuid Pointer to the service UUID to be found. If it is NULL, all primary services will be returned.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Primary Service Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_PRIMARY_SERVICES_DISCOVER, uint32_t, sd_ble_gattc_primary_services_discover(uint16_t conn_handle, uint16_t start_handle, ble_uuid_t const *p_srvc_uuid));
+
+
+/**@brief Initiate or continue a GATT Relationship Discovery procedure.
+ *
+ * @details This function initiates or resumes the Find Included Services sub-procedure. If the last included service has not been reached,
+ *          this must be called again with an updated handle range to continue the search.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_REL_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_REL_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Relationship Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_RELATIONSHIPS_DISCOVER, uint32_t, sd_ble_gattc_relationships_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Characteristic Discovery procedure.
+ *
+ * @details This function initiates or resumes a Characteristic discovery procedure. If the last Characteristic has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @note If any of the discovered characteristics have 128-bit UUIDs which are not present in the table provided to ble_vs_uuids_assign, a UUID structure with
+ *       type @ref BLE_UUID_TYPE_UNKNOWN will be received in the corresponding event.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_CHAR_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Service to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Characteristic Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHARACTERISTICS_DISCOVER, uint32_t, sd_ble_gattc_characteristics_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Characteristic Descriptor Discovery procedure.
+ *
+ * @details This function initiates or resumes a Characteristic Descriptor discovery procedure. If the last Descriptor has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @events
+ * @event{BLE_GATTC_EVT_DESC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_DESC_DISC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range A pointer to the range of handles of the Characteristic to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Descriptor Discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_DESCRIPTORS_DISCOVER, uint32_t, sd_ble_gattc_descriptors_discover(uint16_t conn_handle, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Read using Characteristic UUID procedure.
+ *
+ * @details This function initiates or resumes a Read using Characteristic UUID procedure. If the last Characteristic has not been reached,
+ *          this must be called again with an updated handle range to continue the discovery.
+ *
+ * @events
+ * @event{BLE_GATTC_EVT_DESC_DISC_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_READ_UUID_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_uuid Pointer to a Characteristic value UUID to read.
+ * @param[in] p_handle_range A pointer to the range of handles to perform this procedure on.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Read using Characteristic UUID procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHAR_VALUE_BY_UUID_READ, uint32_t, sd_ble_gattc_char_value_by_uuid_read(uint16_t conn_handle, ble_uuid_t const *p_uuid, ble_gattc_handle_range_t const *p_handle_range));
+
+
+/**@brief Initiate or continue a GATT Read (Long) Characteristic or Descriptor procedure.
+ *
+ * @details This function initiates or resumes a GATT Read (Long) Characteristic or Descriptor procedure. If the Characteristic or Descriptor
+ *          to be read is longer than ATT_MTU - 1, this function must be called multiple times with appropriate offset to read the
+ *          complete value.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_VAL_BY_UUID_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_VALUE_READ_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] handle The handle of the attribute to be read.
+ * @param[in] offset Offset into the attribute value to be read.
+ *
+ * @retval ::NRF_SUCCESS Successfully started or resumed the Read (Long) procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_READ, uint32_t, sd_ble_gattc_read(uint16_t conn_handle, uint16_t handle, uint16_t offset));
+
+
+/**@brief Initiate a GATT Read Multiple Characteristic Values procedure.
+ *
+ * @details This function initiates a GATT Read Multiple Characteristic Values procedure.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_CHAR_VALS_READ_RSP}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_READ_MULT_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handles A pointer to the handle(s) of the attribute(s) to be read.
+ * @param[in] handle_count The number of handles in p_handles.
+ *
+ * @retval ::NRF_SUCCESS Successfully started the Read Multiple Characteristic Values procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_CHAR_VALUES_READ, uint32_t, sd_ble_gattc_char_values_read(uint16_t conn_handle, uint16_t const *p_handles, uint16_t handle_count));
+
+
+/**@brief Perform a Write (Characteristic Value or Descriptor, with or without response, signed or not, long or reliable) procedure.
+ *
+ * @details This function can perform all write procedures described in GATT.
+ *
+ * @note    It is important to note that a write without response will <b>consume an application buffer</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. A write (with response) on the other hand will use the
+ *          standard client internal buffer and thus will only generate a @ref BLE_GATTC_EVT_WRITE_RSP event as soon as the write response
+ *          has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_WRITE_RSP, Generated when using write request or queued writes.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_VALUE_WRITE_MSC}
+ * @mmsc{@ref BLE_GATTC_VALUE_LONG_WRITE_MSC}
+ * @mmsc{@ref BLE_GATTC_VALUE_RELIABLE_WRITE_MSC}
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_write_params A pointer to a write parameters structure.
+ *
+ * @retval ::NRF_SUCCESS Successfully started the Write procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS No available application packets for this connection.
+ */
+SVCALL(SD_BLE_GATTC_WRITE, uint32_t, sd_ble_gattc_write(uint16_t conn_handle, ble_gattc_write_params_t const *p_write_params));
+
+
+/**@brief Send a Handle Value Confirmation to the GATT Server.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTC_HVI_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle The connection handle identifying the connection to perform this procedure on.
+ * @param[in] handle The handle of the attribute in the indication.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued the Handle Value Confirmation for transmission.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or no Indication pending to be confirmed.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle.
+ */
+SVCALL(SD_BLE_GATTC_HV_CONFIRM, uint32_t, sd_ble_gattc_hv_confirm(uint16_t conn_handle, uint16_t handle));
+
+/**@brief Discovers information about a range of attributes on a GATT server.
+ *
+ * @events
+ * @event{@ref BLE_GATTC_EVT_ATTR_INFO_DISC_RSP, Generated when information about a range of attributes has been received.}
+ * @endevents
+ *
+ * @param[in] conn_handle    The connection handle identifying the connection to perform this procedure on.
+ * @param[in] p_handle_range The range of handles to request information about.
+ *
+ * @retval ::NRF_SUCCESS Successfully started an attribute information discovery procedure.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid connection state
+ * @retval ::NRF_ERROR_INVALID_ADDR  Invalid pointer supplied.
+ * @retval ::NRF_ERROR_BUSY Client procedure already in progress.
+ */
+SVCALL(SD_BLE_GATTC_ATTR_INFO_DISCOVER, uint32_t, sd_ble_gattc_attr_info_discover(uint16_t conn_handle, ble_gattc_handle_range_t const * p_handle_range));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_BLE_GATTC_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gatts.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gatts.h
new file mode 100644
index 0000000000..147d1a8fbf
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_gatts.h
@@ -0,0 +1,725 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_GATTS Generic Attribute Profile (GATT) Server
+  @{
+  @brief  Definitions and prototypes for the GATTS interface.
+ */
+
+#ifndef NRF_BLE_GATTS_H__
+#define NRF_BLE_GATTS_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_ble_l2cap.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble_gatt.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_GATTS_ENUMERATIONS Enumerations
+ * @{ */
+
+/**
+ * @brief GATTS API SVC numbers.
+ */
+enum BLE_GATTS_SVCS
+{
+  SD_BLE_GATTS_SERVICE_ADD = BLE_GATTS_SVC_BASE, /**< Add a service. */
+  SD_BLE_GATTS_INCLUDE_ADD,                      /**< Add an included service. */
+  SD_BLE_GATTS_CHARACTERISTIC_ADD,               /**< Add a characteristic. */
+  SD_BLE_GATTS_DESCRIPTOR_ADD,                   /**< Add a generic attribute. */
+  SD_BLE_GATTS_VALUE_SET,                        /**< Set an attribute value. */
+  SD_BLE_GATTS_VALUE_GET,                        /**< Get an attribute value. */
+  SD_BLE_GATTS_HVX,                              /**< Handle Value Notification or Indication. */
+  SD_BLE_GATTS_SERVICE_CHANGED,                  /**< Perform a Service Changed Indication to one or more peers. */
+  SD_BLE_GATTS_RW_AUTHORIZE_REPLY,               /**< Reply to an authorization request for a read or write operation on one or more attributes. */
+  SD_BLE_GATTS_SYS_ATTR_SET,                     /**< Set the persistent system attributes for a connection. */
+  SD_BLE_GATTS_SYS_ATTR_GET,                     /**< Retrieve the persistent system attributes. */
+  SD_BLE_GATTS_INITIAL_USER_HANDLE_GET,          /**< Retrieve the first valid user handle. */
+  SD_BLE_GATTS_ATTR_GET                          /**< Retrieve the UUID and/or metadata of an attribute. */
+};
+
+/**
+ * @brief GATT Server Event IDs.
+ */
+enum BLE_GATTS_EVTS
+{
+  BLE_GATTS_EVT_WRITE = BLE_GATTS_EVT_BASE,       /**< Write operation performed.                                           \n See @ref ble_gatts_evt_write_t.                 */
+  BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST,             /**< Read/Write Authorization request.                                    \n Reply with @ref sd_ble_gatts_rw_authorize_reply. \n See @ref ble_gatts_evt_rw_authorize_request_t. */
+  BLE_GATTS_EVT_SYS_ATTR_MISSING,                 /**< A persistent system attribute access is pending.                     \n Respond with @ref sd_ble_gatts_sys_attr_set.     \n See @ref ble_gatts_evt_sys_attr_missing_t.     */
+  BLE_GATTS_EVT_HVC,                              /**< Handle Value Confirmation.                                           \n See @ref ble_gatts_evt_hvc_t.                   */
+  BLE_GATTS_EVT_SC_CONFIRM,                       /**< Service Changed Confirmation. No additional event structure applies.                                                    */
+  BLE_GATTS_EVT_TIMEOUT                           /**< Peer failed to resonpond to an ATT request in time.                  \n See @ref ble_gatts_evt_timeout_t.               */
+};
+/** @} */
+
+/** @addtogroup BLE_GATTS_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_ERRORS_GATTS SVC return values specific to GATTS
+ * @{ */
+#define BLE_ERROR_GATTS_INVALID_ATTR_TYPE   (NRF_GATTS_ERR_BASE + 0x000) /**< Invalid attribute type. */
+#define BLE_ERROR_GATTS_SYS_ATTR_MISSING    (NRF_GATTS_ERR_BASE + 0x001) /**< System Attributes missing. */
+/** @} */
+
+/** @defgroup BLE_GATTS_ATTR_LENS_MAX Maximum attribute lengths
+ * @{ */
+#define BLE_GATTS_FIX_ATTR_LEN_MAX (510)  /**< Maximum length for fixed length Attribute Values. */
+#define BLE_GATTS_VAR_ATTR_LEN_MAX (512)  /**< Maximum length for variable length Attribute Values. */
+/** @} */
+
+/** @defgroup BLE_GATTS_SRVC_TYPES GATT Server Service Types
+ * @{ */
+#define BLE_GATTS_SRVC_TYPE_INVALID          0x00  /**< Invalid Service Type. */
+#define BLE_GATTS_SRVC_TYPE_PRIMARY          0x01  /**< Primary Service. */
+#define BLE_GATTS_SRVC_TYPE_SECONDARY        0x02  /**< Secondary Type. */
+/** @} */
+
+
+/** @defgroup BLE_GATTS_ATTR_TYPES GATT Server Attribute Types
+ * @{ */
+#define BLE_GATTS_ATTR_TYPE_INVALID         0x00  /**< Invalid Attribute Type. */
+#define BLE_GATTS_ATTR_TYPE_PRIM_SRVC_DECL  0x01  /**< Primary Service Declaration. */
+#define BLE_GATTS_ATTR_TYPE_SEC_SRVC_DECL   0x02  /**< Secondary Service Declaration. */
+#define BLE_GATTS_ATTR_TYPE_INC_DECL        0x03  /**< Include Declaration. */
+#define BLE_GATTS_ATTR_TYPE_CHAR_DECL       0x04  /**< Characteristic Declaration. */
+#define BLE_GATTS_ATTR_TYPE_CHAR_VAL        0x05  /**< Characteristic Value. */
+#define BLE_GATTS_ATTR_TYPE_DESC            0x06  /**< Descriptor. */
+#define BLE_GATTS_ATTR_TYPE_OTHER           0x07  /**< Other, non-GATT specific type. */
+/** @} */
+
+
+/** @defgroup BLE_GATTS_OPS GATT Server Operations
+ * @{ */
+#define BLE_GATTS_OP_INVALID                0x00  /**< Invalid Operation. */
+#define BLE_GATTS_OP_WRITE_REQ              0x01  /**< Write Request. */
+#define BLE_GATTS_OP_WRITE_CMD              0x02  /**< Write Command. */
+#define BLE_GATTS_OP_SIGN_WRITE_CMD         0x03  /**< Signed Write Command. */
+#define BLE_GATTS_OP_PREP_WRITE_REQ         0x04  /**< Prepare Write Request. */
+#define BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL  0x05  /**< Execute Write Request: Cancel all prepared writes. */
+#define BLE_GATTS_OP_EXEC_WRITE_REQ_NOW     0x06  /**< Execute Write Request: Immediately execute all prepared writes. */
+/** @} */
+
+/** @defgroup BLE_GATTS_VLOCS GATT Value Locations
+ * @{ */
+#define BLE_GATTS_VLOC_INVALID       0x00  /**< Invalid Location. */
+#define BLE_GATTS_VLOC_STACK         0x01  /**< Attribute Value is located in stack memory, no user memory is required. */
+#define BLE_GATTS_VLOC_USER          0x02  /**< Attribute Value is located in user memory. This requires the user to maintain a valid buffer through the lifetime of the attribute, since the stack
+                                                will read and write directly to the memory using the pointer provided in the APIs. There are no alignment requirements for the buffer. */
+/** @} */
+
+/** @defgroup BLE_GATTS_AUTHORIZE_TYPES GATT Server Authorization Types
+ * @{ */
+#define BLE_GATTS_AUTHORIZE_TYPE_INVALID    0x00  /**< Invalid Type. */
+#define BLE_GATTS_AUTHORIZE_TYPE_READ       0x01  /**< Authorize a Read Operation. */
+#define BLE_GATTS_AUTHORIZE_TYPE_WRITE      0x02  /**< Authorize a Write Request Operation. */
+/** @} */
+
+/** @defgroup BLE_GATTS_SYS_ATTR_FLAGS System Attribute Flags
+ * @{ */
+#define BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS (1 << 0)  /**< Restrict system attributes to system services only. */
+#define BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS (1 << 1)  /**< Restrict system attributes to user services only. */
+/** @} */
+
+/** @defgroup BLE_GATTS_ATTR_TAB_SIZE Attribute Table size
+ * @{
+ */
+#define BLE_GATTS_ATTR_TAB_SIZE_MIN         216    /**< Minimum Attribute Table size */
+#define BLE_GATTS_ATTR_TAB_SIZE_DEFAULT     0x0000 /**< Default Attribute Table size (0x580 bytes for this version of the SoftDevice). */
+/** @} */
+
+/** @} */
+
+/** @addtogroup BLE_GATTS_STRUCTURES Structures
+ * @{ */
+
+/**
+ * @brief BLE GATTS initialization parameters.
+ */
+typedef struct
+{
+  uint8_t   service_changed:1;             /**< Include the Service Changed characteristic in the Attribute Table. */
+  uint32_t  attr_tab_size;                 /**< Attribute Table size in bytes. The size must be a multiple of 4. @ref BLE_GATTS_ATTR_TAB_SIZE_DEFAULT is used to set the default size. */
+} ble_gatts_enable_params_t;
+
+/**@brief Attribute metadata. */
+typedef struct
+{
+  ble_gap_conn_sec_mode_t read_perm;       /**< Read permissions. */
+  ble_gap_conn_sec_mode_t write_perm;      /**< Write permissions. */
+  uint8_t                 vlen       :1;   /**< Variable length attribute. */
+  uint8_t                 vloc       :2;   /**< Value location, see @ref BLE_GATTS_VLOCS.*/
+  uint8_t                 rd_auth    :1;   /**< Read authorization and value will be requested from the application on every read operation. */
+  uint8_t                 wr_auth    :1;   /**< Write authorization will be requested from the application on every Write Request operation (but not Write Command). */
+} ble_gatts_attr_md_t;
+
+
+/**@brief GATT Attribute. */
+typedef struct
+{
+  ble_uuid_t          *p_uuid;          /**< Pointer to the attribute UUID. */
+  ble_gatts_attr_md_t *p_attr_md;       /**< Pointer to the attribute metadata structure. */
+  uint16_t             init_len;        /**< Initial attribute value length in bytes. */
+  uint16_t             init_offs;       /**< Initial attribute value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
+  uint16_t             max_len;         /**< Maximum attribute value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
+  uint8_t*             p_value;         /**< Pointer to the attribute data. Please note that if the @ref BLE_GATTS_VLOC_USER value location is selected in the attribute metadata, this will have to point to a buffer
+                                             that remains valid through the lifetime of the attribute. This excludes usage of automatic variables that may go out of scope or any other temporary location.
+                                             The stack may access that memory directly without the application's knowledge. For writable characteristics, this value must not be a location in flash memory.*/
+} ble_gatts_attr_t;
+
+/**@brief GATT Attribute Value. */
+typedef struct
+{
+  uint16_t  len;        /**< Length in bytes to be written or read. Length in bytes written or read after successful return.*/
+  uint16_t  offset;     /**< Attribute value offset. */
+  uint8_t   *p_value;   /**< Pointer to where value is stored or will be stored.
+                             If value is stored in user memory, only the attribute length is updated when p_value == NULL.
+                             Set to NULL when reading to obtain the complete length of the attribute value */
+} ble_gatts_value_t;
+
+
+/**@brief GATT Characteristic Presentation Format. */
+typedef struct
+{
+  uint8_t          format;      /**< Format of the value, see @ref BLE_GATT_CPF_FORMATS. */
+  int8_t           exponent;    /**< Exponent for integer data types. */
+  uint16_t         unit;        /**< Unit from Bluetooth Assigned Numbers. */
+  uint8_t          name_space;  /**< Namespace from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
+  uint16_t         desc;        /**< Namespace description from Bluetooth Assigned Numbers, see @ref BLE_GATT_CPF_NAMESPACES. */
+} ble_gatts_char_pf_t;
+
+
+/**@brief GATT Characteristic metadata. */
+typedef struct
+{
+  ble_gatt_char_props_t       char_props;               /**< Characteristic Properties. */
+  ble_gatt_char_ext_props_t   char_ext_props;           /**< Characteristic Extended Properties. */
+  uint8_t                    *p_char_user_desc;         /**< Pointer to a UTF-8 encoded string (non-NULL terminated), NULL if the descriptor is not required. */
+  uint16_t                    char_user_desc_max_size;  /**< The maximum size in bytes of the user description descriptor. */
+  uint16_t                    char_user_desc_size;      /**< The size of the user description, must be smaller or equal to char_user_desc_max_size. */
+  ble_gatts_char_pf_t*        p_char_pf;                /**< Pointer to a presentation format structure or NULL if the CPF descriptor is not required. */
+  ble_gatts_attr_md_t*        p_user_desc_md;           /**< Attribute metadata for the User Description descriptor, or NULL for default values. */
+  ble_gatts_attr_md_t*        p_cccd_md;                /**< Attribute metadata for the Client Characteristic Configuration Descriptor, or NULL for default values. */
+  ble_gatts_attr_md_t*        p_sccd_md;                /**< Attribute metadata for the Server Characteristic Configuration Descriptor, or NULL for default values. */
+} ble_gatts_char_md_t;
+
+
+/**@brief GATT Characteristic Definition Handles. */
+typedef struct
+{
+  uint16_t          value_handle;       /**< Handle to the characteristic value. */
+  uint16_t          user_desc_handle;   /**< Handle to the User Description descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+  uint16_t          cccd_handle;        /**< Handle to the Client Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+  uint16_t          sccd_handle;        /**< Handle to the Server Characteristic Configuration Descriptor, or @ref BLE_GATT_HANDLE_INVALID if not present. */
+} ble_gatts_char_handles_t;
+
+
+/**@brief GATT HVx parameters. */
+typedef struct
+{
+  uint16_t          handle;             /**< Characteristic Value Handle. */
+  uint8_t           type;               /**< Indication or Notification, see @ref BLE_GATT_HVX_TYPES. */
+  uint16_t          offset;             /**< Offset within the attribute value. */
+  uint16_t         *p_len;              /**< Length in bytes to be written, length in bytes written after successful return. */
+  uint8_t          *p_data;             /**< Actual data content, use NULL to use the current attribute value. */
+} ble_gatts_hvx_params_t;
+
+/**@brief GATT Authorization parameters. */
+typedef struct
+{
+  uint16_t          gatt_status;        /**< GATT status code for the operation, see @ref BLE_GATT_STATUS_CODES. */
+  uint8_t           update : 1;         /**< If set, data supplied in p_data will be used to update the attribute value.
+                                             Please note that for @ref BLE_GATTS_OP_WRITE_REQ operations this bit must always be set,
+                                             as the data to be written needs to be stored and later provided by the application. */
+  uint16_t          offset;             /**< Offset of the attribute value being updated. */
+  uint16_t          len;                /**< Length in bytes of the value in p_data pointer, see @ref BLE_GATTS_ATTR_LENS_MAX. */
+  const uint8_t    *p_data;             /**< Pointer to new value used to update the attribute value. */
+} ble_gatts_authorize_params_t;
+
+/**@brief GATT Read or Write Authorize Reply parameters. */
+typedef struct
+{
+  uint8_t                               type;   /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
+  union {
+    ble_gatts_authorize_params_t        read;   /**< Read authorization parameters. */
+    ble_gatts_authorize_params_t        write;  /**< Write authorization parameters. */
+  } params;                                     /**< Reply Parameters. */
+} ble_gatts_rw_authorize_reply_params_t;
+
+
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_WRITE. */
+typedef struct
+{
+  uint16_t                    handle;             /**< Attribute Handle. */
+  ble_uuid_t                  uuid;               /**< Attribute UUID. */
+  uint8_t                     op;                 /**< Type of write operation, see @ref BLE_GATTS_OPS. */
+  uint8_t                     auth_required;      /**< Writing operation deferred due to authorization requirement. Application may use @ref sd_ble_gatts_value_set to finalise the writing operation. */
+  uint16_t                    offset;             /**< Offset for the write operation. */
+  uint16_t                    len;                /**< Length of the received data. */
+  uint8_t                     data[1];            /**< Received data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_gatts_evt_write_t;
+
+/**@brief Event substructure for authorized read requests, see @ref ble_gatts_evt_rw_authorize_request_t. */
+typedef struct
+{
+  uint16_t                    handle;             /**< Attribute Handle. */
+  ble_uuid_t                  uuid;               /**< Attribute UUID. */
+  uint16_t                    offset;             /**< Offset for the read operation. */
+} ble_gatts_evt_read_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST. */
+typedef struct
+{
+  uint8_t                     type;             /**< Type of authorize operation, see @ref BLE_GATTS_AUTHORIZE_TYPES. */
+  union {
+    ble_gatts_evt_read_t      read;             /**< Attribute Read Parameters. */
+    ble_gatts_evt_write_t     write;            /**< Attribute Write Parameters. */
+  } request;                                    /**< Request Parameters. */
+} ble_gatts_evt_rw_authorize_request_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_SYS_ATTR_MISSING. */
+typedef struct
+{
+  uint8_t hint;                                 /**< Hint (currently unused). */
+} ble_gatts_evt_sys_attr_missing_t;
+
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_HVC. */
+typedef struct
+{
+  uint16_t          handle;                       /**< Attribute Handle. */
+} ble_gatts_evt_hvc_t;
+
+/**@brief Event structure for @ref BLE_GATTS_EVT_TIMEOUT. */
+typedef struct
+{
+  uint8_t          src;                       /**< Timeout source, see @ref BLE_GATT_TIMEOUT_SOURCES. */
+} ble_gatts_evt_timeout_t;
+
+
+/**@brief GATT Server event callback event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                                       /**< Connection Handle on which the event occurred. */
+  union
+  {
+    ble_gatts_evt_write_t                 write;              /**< Write Event Parameters. */
+    ble_gatts_evt_rw_authorize_request_t  authorize_request;  /**< Read or Write Authorize Request Parameters. */
+    ble_gatts_evt_sys_attr_missing_t      sys_attr_missing;   /**< System attributes missing. */
+    ble_gatts_evt_hvc_t                   hvc;                /**< Handle Value Confirmation Event Parameters. */
+    ble_gatts_evt_timeout_t               timeout;            /**< Timeout Event. */
+  } params;                                                   /**< Event Parameters. */
+} ble_gatts_evt_t;
+
+/** @} */
+
+/** @addtogroup BLE_GATTS_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Add a service declaration to the Attribute Table.
+ *
+ * @note Secondary Services are only relevant in the context of the entity that references them, it is therefore forbidden to
+ *       add a secondary service declaration that is not referenced by another service later in the Attribute Table.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] type      Toggles between primary and secondary services, see @ref BLE_GATTS_SRVC_TYPES.
+ * @param[in] p_uuid    Pointer to service UUID.
+ * @param[out] p_handle Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a service declaration.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, Vendor Specific UUIDs need to be present in the table.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_GATTS_SERVICE_ADD, uint32_t, sd_ble_gatts_service_add(uint8_t type, ble_uuid_t const *p_uuid, uint16_t *p_handle));
+
+
+/**@brief Add an include declaration to the Attribute Table.
+ *
+ * @note It is currently only possible to add an include declaration to the last added service (i.e. only sequential population is supported at this time).
+ *
+ * @note The included service must already be present in the Attribute Table prior to this call.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] service_handle    Handle of the service where the included service is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] inc_srvc_handle   Handle of the included service.
+ * @param[out] p_include_handle Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added an include declaration.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, handle values need to match previously added services.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, self inclusions are not allowed.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ */
+SVCALL(SD_BLE_GATTS_INCLUDE_ADD, uint32_t, sd_ble_gatts_include_add(uint16_t service_handle, uint16_t inc_srvc_handle, uint16_t *p_include_handle));
+
+
+/**@brief Add a characteristic declaration, a characteristic value declaration and optional characteristic descriptor declarations to the Attribute Table.
+ *
+ * @note It is currently only possible to add a characteristic to the last added service (i.e. only sequential population is supported at this time).
+ *
+ * @note Several restrictions apply to the parameters, such as matching permissions between the user description descriptor and the writeable auxiliaries bits,
+ *       readable (no security) and writeable (selectable) CCCDs and SCCDs and valid presentation format values.
+ *
+ * @note If no metadata is provided for the optional descriptors, their permissions will be derived from the characteristic permissions.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] service_handle    Handle of the service where the characteristic is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] p_char_md         Characteristic metadata.
+ * @param[in] p_attr_char_value Pointer to the attribute structure corresponding to the characteristic value.
+ * @param[out] p_handles        Pointer to the structure where the assigned handles will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a characteristic.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, service handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a service context is required.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ */
+SVCALL(SD_BLE_GATTS_CHARACTERISTIC_ADD, uint32_t, sd_ble_gatts_characteristic_add(uint16_t service_handle, ble_gatts_char_md_t const *p_char_md, ble_gatts_attr_t const *p_attr_char_value, ble_gatts_char_handles_t *p_handles));
+
+
+/**@brief Add a descriptor to the Attribute Table.
+ *
+ * @note It is currently only possible to add a descriptor to the last added characteristic (i.e. only sequential population is supported at this time).
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_ATT_TABLE_POP_MSC}
+ * @endmscs
+ *
+ * @param[in] char_handle   Handle of the characteristic where the descriptor is to be placed, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in] p_attr        Pointer to the attribute structure.
+ * @param[out] p_handle     Pointer to a 16-bit word where the assigned handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully added a descriptor.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, characteristic handle, Vendor Specific UUIDs, lengths, and permissions need to adhere to the constraints.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid state to perform operation, a characteristic context is required.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden value supplied, certain UUIDs are reserved for the stack.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ */
+SVCALL(SD_BLE_GATTS_DESCRIPTOR_ADD, uint32_t, sd_ble_gatts_descriptor_add(uint16_t char_handle, ble_gatts_attr_t const *p_attr, uint16_t *p_handle));
+
+/**@brief Set the value of a given attribute.
+ *
+ * @note Values other than system attributes can be set at any time, regardless of wheter any active connections exist.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle. If the value does not belong to a system attribute then @ref BLE_CONN_HANDLE_INVALID can be used.
+ * @param[in] handle       Attribute handle.
+ * @param[in,out] p_value  Attribute value information.
+ *
+ * @retval ::NRF_SUCCESS Successfully set the value of the attribute.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_FORBIDDEN Forbidden handle supplied, certain attributes are not modifiable by the application.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, attribute lengths are restricted by @ref BLE_GATTS_ATTR_LENS_MAX.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE @ref BLE_CONN_HANDLE_INVALID supplied on a system attribute.
+ */
+SVCALL(SD_BLE_GATTS_VALUE_SET, uint32_t, sd_ble_gatts_value_set(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
+
+/**@brief Get the value of a given attribute.
+ *
+ * @note                 If the attribute value is longer than the size of the supplied buffer,
+ *                       p_len will return the total attribute value length (excluding offset),
+ *                       and not the number of bytes actually returned in p_data.
+ *                       The application may use this information to allocate a suitable buffer size.
+ *
+ * @note                 When retrieving system attribute values with this function, the connection handle
+ *                       may refer to an already disconnected connection. Refer to the documentation of
+ *                       @ref sd_ble_gatts_sys_attr_get for further information.
+ *
+ * @param[in] conn_handle  Connection handle. If the value does not belong to a system attribute then @ref BLE_CONN_HANDLE_INVALID can be used.
+ * @param[in] handle       Attribute handle.
+ * @param[in,out] p_value  Attribute value information.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the value of the attribute.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid attribute offset supplied.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid connection handle supplied.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE @ref BLE_CONN_HANDLE_INVALID supplied on a system attribute.
+ */
+SVCALL(SD_BLE_GATTS_VALUE_GET, uint32_t, sd_ble_gatts_value_get(uint16_t conn_handle, uint16_t handle, ble_gatts_value_t *p_value));
+
+/**@brief Notify or Indicate an attribute value.
+ *
+ * @details This function checks for the relevant Client Characteristic Configuration descriptor value to verify that the relevant operation
+ *          (notification or indication) has been enabled by the client. It is also able to update the attribute value before issuing the PDU, so that
+ *          the application can atomically perform a value update and a server initiated transaction with a single API call.
+ *          If the application chooses to indicate an attribute value, a @ref BLE_GATTS_EVT_HVC event will be issued as soon as the confirmation arrives from
+ *          the peer.
+ *
+ * @note    The local attribute value may be updated even if an outgoing packet is not sent to the peer due to an error during execution.
+ *          When receiveing the error codes @ref NRF_ERROR_INVALID_STATE, @ref NRF_ERROR_BUSY, @ref BLE_ERROR_GATTS_SYS_ATTR_MISSING and
+ *          @ref BLE_ERROR_NO_TX_PACKETS the Attribute Table has been updated.
+ *          The caller can check whether the value has been updated by looking at the contents of *(p_hvx_params->p_len).
+ *
+ * @note    It is important to note that a notification will <b>consume an application buffer</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted. An indication on the other hand will use the
+ *          standard server internal buffer and thus will only generate a @ref BLE_GATTS_EVT_HVC event as soon as the confirmation
+ *          has been received from the peer. Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_EVT_TX_COMPLETE, Transmission complete.}
+ * @event{@ref BLE_GATTS_EVT_HVC, Confirmation received from peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
+ * @mmsc{@ref BLE_GATTS_HVN_MSC}
+ * @mmsc{@ref BLE_GATTS_HVI_MSC}
+ * @mmsc{@ref BLE_GATTS_HVX_DISABLED_MSC}
+ * @mmsc{@ref BLE_COMMON_APP_BUFF_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle.
+ * @param[in] p_hvx_params Pointer to an HVx parameters structure. If the p_data member contains a non-NULL pointer the attribute value will be updated with
+ *                         the contents pointed by it before sending the notification or indication.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued a notification or indication for transmission, and optionally updated the attribute value.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or notifications and/or indications not enabled in the CCCD.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied. Only attributes added directly by the application are available to notify and indicate.
+ * @retval ::BLE_ERROR_GATTS_INVALID_ATTR_TYPE Invalid attribute type(s) supplied, only characteristic values may be notified and indicated.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute not found.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS  No available application packets for this connection, applies only to notifications.
+ */
+SVCALL(SD_BLE_GATTS_HVX, uint32_t, sd_ble_gatts_hvx(uint16_t conn_handle, ble_gatts_hvx_params_t const *p_hvx_params));
+
+/**@brief Indicate the Service Changed attribute value.
+ *
+ * @details This call will send a Handle Value Indication to one or more peers connected to inform them that the Attribute
+ *          Table layout has changed. As soon as the peer has confirmed the indication, a @ref BLE_GATTS_EVT_SC_CONFIRM event will
+ *          be issued.
+ *
+ * @note    Some of the restrictions and limitations that apply to @ref sd_ble_gatts_hvx also apply here.
+ *
+ * @events
+ * @event{@ref BLE_GATTS_EVT_SC_CONFIRM, Confirmation of attribute table change received from peer.}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_SC_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle  Connection handle.
+ * @param[in] start_handle Start of affected attribute handle range.
+ * @param[in] end_handle   End of affected attribute handle range.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued the Service Changed indication for transmission.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_NOT_SUPPORTED Service Changed not enabled at initialization. See @ref sd_ble_enable and @ref ble_gatts_enable_params_t.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State or notifications and/or indications not enabled in the CCCD.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::BLE_ERROR_INVALID_ATTR_HANDLE Invalid attribute handle(s) supplied, handles must be in the range populated by the application.
+ * @retval ::NRF_ERROR_BUSY Procedure already in progress.
+ * @retval ::BLE_ERROR_GATTS_SYS_ATTR_MISSING System attributes missing, use @ref sd_ble_gatts_sys_attr_set to set them to a known value.
+ */
+SVCALL(SD_BLE_GATTS_SERVICE_CHANGED, uint32_t, sd_ble_gatts_service_changed(uint16_t conn_handle, uint16_t start_handle, uint16_t end_handle));
+
+/**@brief Respond to a Read/Write authorization request.
+ *
+ * @note This call should only be used as a response to a @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event issued to the application.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_BUF_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_NOAUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_READ_REQ_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_WRITE_REQ_AUTH_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_QUEUE_FULL_MSC}
+ * @mmsc{@ref BLE_GATTS_QUEUED_WRITE_NOBUF_PEER_CANCEL_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle                 Connection handle.
+ * @param[in] p_rw_authorize_reply_params Pointer to a structure with the attribute provided by the application.
+ *
+ * @retval ::NRF_SUCCESS               Successfully queued a response to the peer, and in the case of a write operation, Attribute Table updated.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR    Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE   Invalid Connection State or no authorization request pending.
+ * @retval ::NRF_ERROR_INVALID_PARAM   Authorization op invalid,
+ *                                         handle supplied does not match requested handle,
+ *                                         or invalid data to be written provided by the application.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_RW_AUTHORIZE_REPLY, uint32_t, sd_ble_gatts_rw_authorize_reply(uint16_t conn_handle, ble_gatts_rw_authorize_reply_params_t const *p_rw_authorize_reply_params));
+
+
+/**@brief Update persistent system attribute information.
+ *
+ * @details Supply information about persistent system attributes to the stack,
+ *          previously obtained using @ref sd_ble_gatts_sys_attr_get.
+ *          This call is only allowed for active connections, and is usually
+ *          made immediately after a connection is established with an known bonded device,
+ *          often as a response to a @ref BLE_GATTS_EVT_SYS_ATTR_MISSING.
+ *
+ *          p_sysattrs may point directly to the application's stored copy of the system attributes
+ *          obtained using @ref sd_ble_gatts_sys_attr_get.
+ *          If the pointer is NULL, the system attribute info is initialized, assuming that
+ *          the application does not have any previously saved system attribute data for this device.
+ *
+ * @note The state of persistent system attributes is reset upon connection establishment and then remembered for its duration.
+ *
+ * @note If this call returns with an error code different from @ref NRF_SUCCESS, the storage of persistent system attributes may have been completed only partially.
+ *       This means that the state of the attribute table is undefined, and the application should either provide a new set of attributes using this same call or
+ *       reset the SoftDevice to return to a known state.
+ *
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be modified.
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be modified.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_HVX_SYS_ATTRS_MISSING_MSC}
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_UNK_PEER_MSC}
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
+ * @endmscs
+ *
+ * @param[in]  conn_handle        Connection handle.
+ * @param[in]  p_sys_attr_data    Pointer to a saved copy of system attributes supplied to the stack, or NULL.
+ * @param[in]  len                Size of data pointed by p_sys_attr_data, in octets.
+ * @param[in]  flags              Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
+ *
+ * @retval ::NRF_SUCCESS Successfully set the system attribute information.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_STATE Invalid Connection State.
+ * @retval ::NRF_ERROR_INVALID_DATA Invalid data supplied, the data should be exactly the same as retrieved with @ref sd_ble_gatts_sys_attr_get.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::NRF_ERROR_BUSY The stack is busy. Retry at later time.
+ */
+SVCALL(SD_BLE_GATTS_SYS_ATTR_SET, uint32_t, sd_ble_gatts_sys_attr_set(uint16_t conn_handle, uint8_t const *p_sys_attr_data, uint16_t len, uint32_t flags));
+
+
+/**@brief Retrieve persistent system attribute information from the stack.
+ *
+ * @details This call is used to retrieve information about values to be stored perisistently by the application
+ *          during the lifetime of a connection or after it has been terminated. When a new connection is established with the same bonded device,
+ *          the system attribute information retrieved with this function should be restored using using @ref sd_ble_gatts_sys_attr_set.
+ *          If retrieved after disconnection, the data should be read before a new connection established. The connection handle for
+ *          the previous, now disconnected, connection will remain valid until a new one is created to allow this API call to refer to it.
+ *          Connection handles belonging to active connections can be used as well, but care should be taken since the system attributes
+ *          may be written to at any time by the peer during a connection's lifetime.
+ *
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS is used with this function, only the system attributes included in system services will be returned.
+ * @note When the @ref BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS is used with this function, only the system attributes included in user services will be returned.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_GATTS_SYS_ATTRS_BONDED_PEER_MSC}
+ * @endmscs
+ *
+ * @param[in]     conn_handle       Connection handle of the recently terminated connection.
+ * @param[out]    p_sys_attr_data   Pointer to a buffer where updated information about system attributes will be filled in. The format of the data is described
+ *                                  in @ref BLE_GATTS_SYS_ATTRS_FORMAT. NULL can be provided to obtain the length of the data.
+ * @param[in,out] p_len             Size of application buffer if p_sys_attr_data is not NULL. Unconditially updated to actual length of system attribute data.
+ * @param[in]     flags             Optional additional flags, see @ref BLE_GATTS_SYS_ATTR_FLAGS
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the system attribute information.
+ * @retval ::BLE_ERROR_INVALID_CONN_HANDLE Invalid Connection Handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_DATA_SIZE The system attribute information did not fit into the provided buffer.
+ * @retval ::NRF_ERROR_NOT_FOUND No system attributes found.
+ */
+SVCALL(SD_BLE_GATTS_SYS_ATTR_GET, uint32_t, sd_ble_gatts_sys_attr_get(uint16_t conn_handle, uint8_t *p_sys_attr_data, uint16_t *p_len, uint32_t flags));
+
+
+/**@brief Retrieve the first valid user attribute handle.
+ *
+ * @param[out] p_handle   Pointer to an integer where the handle will be stored.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the handle.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ */
+SVCALL(SD_BLE_GATTS_INITIAL_USER_HANDLE_GET, uint32_t, sd_ble_gatts_initial_user_handle_get(uint16_t *p_handle));
+
+/**@brief Retrieve the attribute UUID and/or metadata.
+ *
+ * @param[in]  handle Attribute handle
+ * @param[out] p_uuid UUID of the attribute. Use NULL to omit this field.
+ * @param[out] p_md Metadata of the attribute. Use NULL to omit this field.
+ *
+ * @retval ::NRF_SUCCESS Successfully retrieved the attribute metadata,
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameters supplied. Returned when both @c p_uuid and @c p_md are NULL.
+ * @retval ::NRF_ERROR_NOT_FOUND Attribute was not found.
+ */
+SVCALL(SD_BLE_GATTS_ATTR_GET, uint32_t, sd_ble_gatts_attr_get(uint16_t handle, ble_uuid_t * p_uuid, ble_gatts_attr_md_t * p_md));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_GATTS_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_hci.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_hci.h
new file mode 100644
index 0000000000..a709c0a60f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_hci.h
@@ -0,0 +1,134 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+*/
+
+
+#ifndef NRF_BLE_HCI_H__
+#define NRF_BLE_HCI_H__ 
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup BLE_HCI_STATUS_CODES Bluetooth status codes
+ * @{ */
+
+#define BLE_HCI_STATUS_CODE_SUCCESS                        0x00   /**< Success. */
+#define BLE_HCI_STATUS_CODE_UNKNOWN_BTLE_COMMAND           0x01   /**< Unknown BLE Command. */
+#define BLE_HCI_STATUS_CODE_UNKNOWN_CONNECTION_IDENTIFIER  0x02   /**< Unknown Connection Identifier. */
+/*0x03 Hardware Failure
+0x04 Page Timeout
+*/
+#define BLE_HCI_AUTHENTICATION_FAILURE                     0x05   /**< Authentication Failure. */
+#define BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING             0x06   /**< Pin or Key missing. */
+#define BLE_HCI_MEMORY_CAPACITY_EXCEEDED                   0x07   /**< Memory Capacity Exceeded. */
+#define BLE_HCI_CONNECTION_TIMEOUT                         0x08   /**< Connection Timeout. */
+/*0x09 Connection Limit Exceeded
+0x0A Synchronous Connection Limit To A Device Exceeded
+0x0B ACL Connection Already Exists*/
+#define BLE_HCI_STATUS_CODE_COMMAND_DISALLOWED             0x0C   /**< Command Disallowed. */
+/*0x0D Connection Rejected due to Limited Resources
+0x0E Connection Rejected Due To Security Reasons
+0x0F Connection Rejected due to Unacceptable BD_ADDR
+0x10 Connection Accept Timeout Exceeded
+0x11 Unsupported Feature or Parameter Value*/
+#define BLE_HCI_STATUS_CODE_INVALID_BTLE_COMMAND_PARAMETERS 0x12  /**< Invalid BLE Command Parameters. */
+#define BLE_HCI_REMOTE_USER_TERMINATED_CONNECTION           0x13  /**< Remote User Terminated Connection. */
+#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_LOW_RESOURCES 0x14  /**< Remote Device Terminated Connection due to low resources.*/
+#define BLE_HCI_REMOTE_DEV_TERMINATION_DUE_TO_POWER_OFF     0x15  /**< Remote Device Terminated Connection due to power off. */
+#define BLE_HCI_LOCAL_HOST_TERMINATED_CONNECTION            0x16  /**< Local Host Terminated Connection. */
+/*
+0x17 Repeated Attempts
+0x18 Pairing Not Allowed
+0x19 Unknown LMP PDU
+*/
+#define BLE_HCI_UNSUPPORTED_REMOTE_FEATURE 0x1A                   /**< Unsupported Remote Feature. */
+/*
+0x1B SCO Offset Rejected
+0x1C SCO Interval Rejected
+0x1D SCO Air Mode Rejected*/
+#define BLE_HCI_STATUS_CODE_INVALID_LMP_PARAMETERS     0x1E       /**< Invalid LMP Parameters. */
+#define BLE_HCI_STATUS_CODE_UNSPECIFIED_ERROR          0x1F       /**< Unspecified Error. */
+/*0x20 Unsupported LMP Parameter Value
+0x21 Role Change Not Allowed
+*/
+#define BLE_HCI_STATUS_CODE_LMP_RESPONSE_TIMEOUT       0x22       /**< LMP Response Timeout. */
+/*0x23 LMP Error Transaction Collision*/
+#define BLE_HCI_STATUS_CODE_LMP_PDU_NOT_ALLOWED        0x24       /**< LMP PDU Not Allowed. */
+/*0x25 Encryption Mode Not Acceptable
+0x26 Link Key Can Not be Changed
+0x27 Requested QoS Not Supported
+*/
+#define BLE_HCI_INSTANT_PASSED                         0x28       /**< Instant Passed. */
+#define BLE_HCI_PAIRING_WITH_UNIT_KEY_UNSUPPORTED      0x29       /**< Pairing with Unit Key Unsupported. */
+#define BLE_HCI_DIFFERENT_TRANSACTION_COLLISION        0x2A       /**< Different Transaction Collision. */
+/*
+0x2B Reserved
+0x2C QoS Unacceptable Parameter
+0x2D QoS Rejected
+0x2E Channel Classification Not Supported
+0x2F Insufficient Security
+0x30 Parameter Out Of Mandatory Range
+0x31 Reserved
+0x32 Role Switch Pending
+0x33 Reserved
+0x34 Reserved Slot Violation
+0x35 Role Switch Failed
+0x36 Extended Inquiry Response Too Large
+0x37 Secure Simple Pairing Not Supported By Host.
+0x38 Host Busy - Pairing
+0x39 Connection Rejected due to No Suitable Channel Found*/
+#define BLE_HCI_CONTROLLER_BUSY                        0x3A       /**< Controller Busy. */
+#define BLE_HCI_CONN_INTERVAL_UNACCEPTABLE             0x3B       /**< Connection Interval Unacceptable. */
+#define BLE_HCI_DIRECTED_ADVERTISER_TIMEOUT            0x3C       /**< Directed Adverisement Timeout. */
+#define BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE     0x3D       /**< Connection Terminated due to MIC Failure. */
+#define BLE_HCI_CONN_FAILED_TO_BE_ESTABLISHED          0x3E       /**< Connection Failed to be Established. */
+
+/** @} */
+
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_HCI_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h
new file mode 100644
index 0000000000..57d3592969
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_l2cap.h
@@ -0,0 +1,205 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_L2CAP Logical Link Control and Adaptation Protocol (L2CAP)
+  @{
+  @brief Definitions and prototypes for the L2CAP interface.
+ */
+
+#ifndef NRF_BLE_L2CAP_H__
+#define NRF_BLE_L2CAP_H__
+
+#include "nrf_ble_types.h"
+#include "nrf_ble_ranges.h"
+#include "nrf_ble_err.h"
+#include "nrf_svc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup BLE_L2CAP_ENUMERATIONS Enumerations
+ * @{ */
+
+/**@brief L2CAP API SVC numbers. */
+enum BLE_L2CAP_SVCS
+{
+  SD_BLE_L2CAP_CID_REGISTER = BLE_L2CAP_SVC_BASE,  /**< Register a CID. */
+  SD_BLE_L2CAP_CID_UNREGISTER,                     /**< Unregister a CID. */
+  SD_BLE_L2CAP_TX                                  /**< Transmit a packet. */
+};
+
+/**@brief L2CAP Event IDs. */
+enum BLE_L2CAP_EVTS
+{
+  BLE_L2CAP_EVT_RX  = BLE_L2CAP_EVT_BASE          /**< L2CAP packet received. */
+};
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_DEFINES Defines
+ * @{ */
+
+/**@defgroup BLE_ERRORS_L2CAP SVC return values specific to L2CAP
+ * @{ */
+#define BLE_ERROR_L2CAP_CID_IN_USE            (NRF_L2CAP_ERR_BASE + 0x000)  /**< CID already in use. */
+/** @} */
+
+/**@brief Default L2CAP MTU. */
+#define BLE_L2CAP_MTU_DEF           (23)
+
+/**@brief Invalid Channel Identifier. */
+#define BLE_L2CAP_CID_INVALID       (0x0000)
+
+/**@brief Dynamic Channel Identifier base. */
+#define BLE_L2CAP_CID_DYN_BASE      (0x0040)
+
+/**@brief Maximum amount of dynamic CIDs. */
+#define BLE_L2CAP_CID_DYN_MAX       (8)
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_STRUCTURES Structures
+ * @{ */
+
+/**@brief Packet header format for L2CAP transmission. */
+typedef struct
+{
+  uint16_t   len;                                 /**< Length of valid info in data member. */
+  uint16_t   cid;                                 /**< Channel ID on which packet is transmitted. */
+} ble_l2cap_header_t;
+
+
+/**@brief L2CAP Received packet event report. */
+typedef struct
+{
+  ble_l2cap_header_t header;                      /**< L2CAP packet header. */
+  uint8_t    data[1];                             /**< Packet data. @note This is a variable length array. The size of 1 indicated is only a placeholder for compilation.
+                                                       See @ref sd_ble_evt_get for more information on how to use event structures with variable length array members. */
+} ble_l2cap_evt_rx_t;
+
+
+/**@brief L2CAP event callback event structure. */
+typedef struct
+{
+  uint16_t conn_handle;                           /**< Connection Handle on which event occured. */
+  union
+  {
+    ble_l2cap_evt_rx_t rx;                        /**< RX Event parameters. */
+  } params;                                       /**< Event Parameters. */
+} ble_l2cap_evt_t;
+
+/** @} */
+
+/**@addtogroup BLE_L2CAP_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Register a CID with L2CAP.
+ *
+ * @details This registers a higher protocol layer with the L2CAP multiplexer, and is requried prior to all operations on the CID.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] cid L2CAP CID.
+ *
+ * @retval ::NRF_SUCCESS Successfully registered a CID with the L2CAP layer.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CID must be above @ref BLE_L2CAP_CID_DYN_BASE.
+ * @retval ::BLE_ERROR_L2CAP_CID_IN_USE L2CAP CID already in use.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ */
+SVCALL(SD_BLE_L2CAP_CID_REGISTER, uint32_t, sd_ble_l2cap_cid_register(uint16_t cid));
+
+/**@brief Unregister a CID with L2CAP.
+ *
+ * @details This unregisters a previously registerd higher protocol layer with the L2CAP multiplexer.
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] cid L2CAP CID.
+ *
+ * @retval ::NRF_SUCCESS Successfully unregistered the CID.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied.
+ * @retval ::NRF_ERROR_NOT_FOUND CID not previously registered.
+ */
+SVCALL(SD_BLE_L2CAP_CID_UNREGISTER, uint32_t, sd_ble_l2cap_cid_unregister(uint16_t cid));
+
+/**@brief Transmit an L2CAP packet.
+ *
+ * @note    It is important to note that a call to this function will <b>consume an application packet</b>, and will therefore
+ *          generate a @ref BLE_EVT_TX_COMPLETE event when the packet has been transmitted.
+ *          Please see the documentation of @ref sd_ble_tx_packet_count_get for more details.
+ *
+ * @events
+ * @event{@ref BLE_EVT_TX_COMPLETE}
+ * @event{@ref BLE_L2CAP_EVT_RX}
+ * @endevents
+ *
+ * @mscs
+ * @mmsc{@ref BLE_L2CAP_API_MSC}
+ * @endmscs
+ *
+ * @param[in] conn_handle Connection Handle.
+ * @param[in] p_header    Pointer to a packet header containing length and CID.
+ * @param[in] p_data      Pointer to the data to be transmitted.
+ *
+ * @retval ::NRF_SUCCESS Successfully queued an L2CAP packet for transmission.
+ * @retval ::NRF_ERROR_INVALID_ADDR Invalid pointer supplied.
+ * @retval ::NRF_ERROR_INVALID_PARAM Invalid parameter(s) supplied, CIDs must be registered beforehand with @ref sd_ble_l2cap_cid_register.
+ * @retval ::NRF_ERROR_NOT_FOUND CID not found.
+ * @retval ::NRF_ERROR_NO_MEM Not enough memory to complete operation.
+ * @retval ::BLE_ERROR_NO_TX_PACKETS Not enough application packets available.
+ * @retval ::NRF_ERROR_DATA_SIZE Invalid data size(s) supplied, see @ref BLE_L2CAP_MTU_DEF.
+ */
+SVCALL(SD_BLE_L2CAP_TX, uint32_t, sd_ble_l2cap_tx(uint16_t conn_handle, ble_l2cap_header_t const *p_header, uint8_t const *p_data));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_BLE_L2CAP_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_ranges.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_ranges.h
new file mode 100644
index 0000000000..7476d488c0
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_ranges.h
@@ -0,0 +1,129 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @defgroup ble_ranges Module specific SVC, event and option number subranges
+  @{
+
+  @brief Definition of SVC, event and option number subranges for each API module.
+
+  @note
+  SVCs, event and option numbers are split into subranges for each API module.
+  Each module receives its entire allocated range of SVC calls, whether implemented or not,
+  but return BLE_ERROR_NOT_SUPPORTED for unimplemented or undefined calls in its range.
+
+  Note that the symbols BLE_<module>_SVC_LAST is the end of the allocated SVC range,
+  rather than the last SVC function call actually defined and implemented.
+
+  Specific SVC, event and option values are defined in each module's ble_<module>.h file,
+  which defines names of each individual SVC code based on the range start value.
+*/
+
+#ifndef NRF_BLE_RANGES_H__
+#define NRF_BLE_RANGES_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define BLE_SVC_BASE           0x60       /**< Common BLE SVC base. */
+#define BLE_SVC_LAST           0x6B       /**< Total: 12. */
+
+#define BLE_RESERVED_SVC_BASE  0x6C       /**< Reserved BLE SVC base. */
+#define BLE_RESERVED_SVC_LAST  0x6F       /**< Total: 4. */
+
+#define BLE_GAP_SVC_BASE       0x70       /**< GAP BLE SVC base. */
+#define BLE_GAP_SVC_LAST       0x8F       /**< Total: 32. */
+
+#define BLE_GATTC_SVC_BASE     0x90       /**< GATTC BLE SVC base. */
+#define BLE_GATTC_SVC_LAST     0x9F       /**< Total: 32. */
+
+#define BLE_GATTS_SVC_BASE     0xA0       /**< GATTS BLE SVC base. */
+#define BLE_GATTS_SVC_LAST     0xAF       /**< Total: 16. */
+
+#define BLE_L2CAP_SVC_BASE     0xB0       /**< L2CAP BLE SVC base. */
+#define BLE_L2CAP_SVC_LAST     0xBF       /**< Total: 16. */
+
+
+#define BLE_EVT_INVALID        0x00       /**< Invalid BLE Event. */
+
+#define BLE_EVT_BASE           0x01       /**< Common BLE Event base. */
+#define BLE_EVT_LAST           0x0F       /**< Total: 15. */
+
+#define BLE_GAP_EVT_BASE       0x10       /**< GAP BLE Event base. */
+#define BLE_GAP_EVT_LAST       0x2F       /**< Total: 32. */
+
+#define BLE_GATTC_EVT_BASE     0x30       /**< GATTC BLE Event base. */
+#define BLE_GATTC_EVT_LAST     0x4F       /**< Total: 32. */
+
+#define BLE_GATTS_EVT_BASE     0x50       /**< GATTS BLE Event base. */
+#define BLE_GATTS_EVT_LAST     0x6F       /**< Total: 32. */
+
+#define BLE_L2CAP_EVT_BASE     0x70       /**< L2CAP BLE Event base. */
+#define BLE_L2CAP_EVT_LAST     0x8F       /**< Total: 32.  */
+
+
+#define BLE_OPT_INVALID        0x00       /**< Invalid BLE Option. */
+
+#define BLE_OPT_BASE           0x01       /**< Common BLE Option base. */
+#define BLE_OPT_LAST           0x1F       /**< Total: 31. */
+
+#define BLE_GAP_OPT_BASE       0x20       /**< GAP BLE Option base. */
+#define BLE_GAP_OPT_LAST       0x3F       /**< Total: 32. */
+
+#define BLE_GATTC_OPT_BASE     0x40       /**< GATTC BLE Option base. */
+#define BLE_GATTC_OPT_LAST     0x5F       /**< Total: 32. */
+
+#define BLE_GATTS_OPT_BASE     0x60       /**< GATTS BLE Option base. */
+#define BLE_GATTS_OPT_LAST     0x7F       /**< Total: 32. */
+
+#define BLE_L2CAP_OPT_BASE     0x80       /**< L2CAP BLE Option base. */
+#define BLE_L2CAP_OPT_LAST     0x9F       /**< Total: 32.  */
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* NRF_BLE_RANGES_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_types.h
new file mode 100644
index 0000000000..0ef31dd83a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_ble_types.h
@@ -0,0 +1,208 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+  @addtogroup BLE_COMMON
+  @{
+  @defgroup ble_types Common types and macro definitions
+  @{
+
+  @brief Common types and macro definitions for the BLE SoftDevice.
+ */
+
+#ifndef NRF_BLE_TYPES_H__
+#define NRF_BLE_TYPES_H__
+
+#include <stdint.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup BLE_TYPES_DEFINES Defines
+ * @{ */
+
+/** @defgroup BLE_CONN_HANDLES BLE Connection Handles
+ * @{ */
+#define BLE_CONN_HANDLE_INVALID 0xFFFF  /**< Invalid Connection Handle. */
+#define BLE_CONN_HANDLE_ALL     0xFFFE  /**< Applies to all Connection Handles. */
+/** @} */
+
+
+/** @defgroup BLE_UUID_VALUES Assigned Values for BLE UUIDs
+ * @{ */
+/* Generic UUIDs, applicable to all services */
+#define BLE_UUID_UNKNOWN                              0x0000 /**< Reserved UUID. */
+#define BLE_UUID_SERVICE_PRIMARY                      0x2800 /**< Primary Service. */
+#define BLE_UUID_SERVICE_SECONDARY                    0x2801 /**< Secondary Service. */
+#define BLE_UUID_SERVICE_INCLUDE                      0x2802 /**< Include. */
+#define BLE_UUID_CHARACTERISTIC                       0x2803 /**< Characteristic. */
+#define BLE_UUID_DESCRIPTOR_CHAR_EXT_PROP             0x2900 /**< Characteristic Extended Properties Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_USER_DESC            0x2901 /**< Characteristic User Description Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG        0x2902 /**< Client Characteristic Configuration Descriptor. */
+#define BLE_UUID_DESCRIPTOR_SERVER_CHAR_CONFIG        0x2903 /**< Server Characteristic Configuration Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_PRESENTATION_FORMAT  0x2904 /**< Characteristic Presentation Format Descriptor. */
+#define BLE_UUID_DESCRIPTOR_CHAR_AGGREGATE_FORMAT     0x2905 /**< Characteristic Aggregate Format Descriptor. */
+/* GATT specific UUIDs */
+#define BLE_UUID_GATT                                 0x1801 /**< Generic Attribute Profile. */
+#define BLE_UUID_GATT_CHARACTERISTIC_SERVICE_CHANGED  0x2A05 /**< Service Changed Characteristic. */
+/* GAP specific UUIDs */
+#define BLE_UUID_GAP                                  0x1800 /**< Generic Access Profile. */
+#define BLE_UUID_GAP_CHARACTERISTIC_DEVICE_NAME       0x2A00 /**< Device Name Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_APPEARANCE        0x2A01 /**< Appearance Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_PPF               0x2A02 /**< Peripheral Privacy Flag Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_RECONN_ADDR       0x2A03 /**< Reconnection Address Characteristic. */
+#define BLE_UUID_GAP_CHARACTERISTIC_PPCP              0x2A04 /**< Peripheral Preferred Connection Parameters Characteristic. */
+/** @} */
+
+
+/** @defgroup BLE_UUID_TYPES Types of UUID
+ * @{ */
+#define BLE_UUID_TYPE_UNKNOWN       0x00 /**< Invalid UUID type. */
+#define BLE_UUID_TYPE_BLE           0x01 /**< Bluetooth SIG UUID (16-bit). */
+#define BLE_UUID_TYPE_VENDOR_BEGIN  0x02 /**< Vendor UUID types start at this index (128-bit). */
+/** @} */
+
+
+/** @defgroup BLE_APPEARANCES Bluetooth Appearance values
+ *  @note Retrieved from http://developer.bluetooth.org/gatt/characteristics/Pages/CharacteristicViewer.aspx?u=org.bluetooth.characteristic.gap.appearance.xml
+ * @{ */
+#define BLE_APPEARANCE_UNKNOWN                                0 /**< Unknown. */
+#define BLE_APPEARANCE_GENERIC_PHONE                         64 /**< Generic Phone. */
+#define BLE_APPEARANCE_GENERIC_COMPUTER                     128 /**< Generic Computer. */
+#define BLE_APPEARANCE_GENERIC_WATCH                        192 /**< Generic Watch. */
+#define BLE_APPEARANCE_WATCH_SPORTS_WATCH                   193 /**< Watch: Sports Watch. */
+#define BLE_APPEARANCE_GENERIC_CLOCK                        256 /**< Generic Clock. */
+#define BLE_APPEARANCE_GENERIC_DISPLAY                      320 /**< Generic Display. */
+#define BLE_APPEARANCE_GENERIC_REMOTE_CONTROL               384 /**< Generic Remote Control. */
+#define BLE_APPEARANCE_GENERIC_EYE_GLASSES                  448 /**< Generic Eye-glasses. */
+#define BLE_APPEARANCE_GENERIC_TAG                          512 /**< Generic Tag. */
+#define BLE_APPEARANCE_GENERIC_KEYRING                      576 /**< Generic Keyring. */
+#define BLE_APPEARANCE_GENERIC_MEDIA_PLAYER                 640 /**< Generic Media Player. */
+#define BLE_APPEARANCE_GENERIC_BARCODE_SCANNER              704 /**< Generic Barcode Scanner. */
+#define BLE_APPEARANCE_GENERIC_THERMOMETER                  768 /**< Generic Thermometer. */
+#define BLE_APPEARANCE_THERMOMETER_EAR                      769 /**< Thermometer: Ear. */
+#define BLE_APPEARANCE_GENERIC_HEART_RATE_SENSOR            832 /**< Generic Heart rate Sensor. */
+#define BLE_APPEARANCE_HEART_RATE_SENSOR_HEART_RATE_BELT    833 /**< Heart Rate Sensor: Heart Rate Belt. */
+#define BLE_APPEARANCE_GENERIC_BLOOD_PRESSURE               896 /**< Generic Blood Pressure. */
+#define BLE_APPEARANCE_BLOOD_PRESSURE_ARM                   897 /**< Blood Pressure: Arm. */
+#define BLE_APPEARANCE_BLOOD_PRESSURE_WRIST                 898 /**< Blood Pressure: Wrist. */
+#define BLE_APPEARANCE_GENERIC_HID                          960 /**< Human Interface Device (HID). */
+#define BLE_APPEARANCE_HID_KEYBOARD                         961 /**< Keyboard (HID Subtype). */
+#define BLE_APPEARANCE_HID_MOUSE                            962 /**< Mouse (HID Subtype). */
+#define BLE_APPEARANCE_HID_JOYSTICK                         963 /**< Joystiq (HID Subtype). */
+#define BLE_APPEARANCE_HID_GAMEPAD                          964 /**< Gamepad (HID Subtype). */
+#define BLE_APPEARANCE_HID_DIGITIZERSUBTYPE                 965 /**< Digitizer Tablet (HID Subtype). */
+#define BLE_APPEARANCE_HID_CARD_READER                      966 /**< Card Reader (HID Subtype). */
+#define BLE_APPEARANCE_HID_DIGITAL_PEN                      967 /**< Digital Pen (HID Subtype). */
+#define BLE_APPEARANCE_HID_BARCODE                          968 /**< Barcode Scanner (HID Subtype). */
+#define BLE_APPEARANCE_GENERIC_GLUCOSE_METER               1024 /**< Generic Glucose Meter. */
+#define BLE_APPEARANCE_GENERIC_RUNNING_WALKING_SENSOR      1088 /**< Generic Running Walking Sensor. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_IN_SHOE      1089 /**< Running Walking Sensor: In-Shoe. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_SHOE      1090 /**< Running Walking Sensor: On-Shoe. */
+#define BLE_APPEARANCE_RUNNING_WALKING_SENSOR_ON_HIP       1091 /**< Running Walking Sensor: On-Hip. */
+#define BLE_APPEARANCE_GENERIC_CYCLING                     1152 /**< Generic Cycling. */
+#define BLE_APPEARANCE_CYCLING_CYCLING_COMPUTER            1153 /**< Cycling: Cycling Computer. */
+#define BLE_APPEARANCE_CYCLING_SPEED_SENSOR                1154 /**< Cycling: Speed Sensor. */
+#define BLE_APPEARANCE_CYCLING_CADENCE_SENSOR              1155 /**< Cycling: Cadence Sensor. */
+#define BLE_APPEARANCE_CYCLING_POWER_SENSOR                1156 /**< Cycling: Power Sensor. */
+#define BLE_APPEARANCE_CYCLING_SPEED_CADENCE_SENSOR        1157 /**< Cycling: Speed and Cadence Sensor. */
+#define BLE_APPEARANCE_GENERIC_PULSE_OXIMETER              3136 /**< Generic Pulse Oximeter. */
+#define BLE_APPEARANCE_PULSE_OXIMETER_FINGERTIP            3137 /**< Fingertip (Pulse Oximeter subtype). */
+#define BLE_APPEARANCE_PULSE_OXIMETER_WRIST_WORN           3138 /**< Wrist Worn(Pulse Oximeter subtype). */
+#define BLE_APPEARANCE_GENERIC_WEIGHT_SCALE                3200 /**< Generic Weight Scale. */
+#define BLE_APPEARANCE_GENERIC_OUTDOOR_SPORTS_ACT          5184 /**< Generic Outdoor Sports Activity. */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_DISP         5185 /**< Location Display Device (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_DISP 5186 /**< Location and Navigation Display Device (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_POD          5187 /**< Location Pod (Outdoor Sports Activity subtype). */
+#define BLE_APPEARANCE_OUTDOOR_SPORTS_ACT_LOC_AND_NAV_POD  5188 /**< Location and Navigation Pod (Outdoor Sports Activity subtype). */
+/** @} */
+
+/** @brief Set .type and .uuid fields of ble_uuid_struct to specified uuid value. */
+#define BLE_UUID_BLE_ASSIGN(instance, value) do {\
+            instance.type = BLE_UUID_TYPE_BLE; \
+            instance.uuid = value;} while(0)
+
+/** @brief Copy type and uuid members from src to dst ble_uuid_t pointer. Both pointers must be valid/non-null. */
+#define BLE_UUID_COPY_PTR(dst, src) do {\
+            (dst)->type = (src)->type; \
+            (dst)->uuid = (src)->uuid;} while(0)
+
+/** @brief Copy type and uuid members from src to dst ble_uuid_t struct. */
+#define BLE_UUID_COPY_INST(dst, src) do {\
+            (dst).type = (src).type; \
+            (dst).uuid = (src).uuid;} while(0)
+
+/** @brief Compare for equality both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
+#define BLE_UUID_EQ(p_uuid1, p_uuid2) \
+            (((p_uuid1)->type == (p_uuid2)->type) && ((p_uuid1)->uuid == (p_uuid2)->uuid))
+
+/** @brief Compare for difference both type and uuid members of two (valid, non-null) ble_uuid_t pointers. */
+#define BLE_UUID_NEQ(p_uuid1, p_uuid2) \
+            (((p_uuid1)->type != (p_uuid2)->type) || ((p_uuid1)->uuid != (p_uuid2)->uuid))
+
+/** @} */
+
+/** @addtogroup BLE_TYPES_STRUCTURES Structures
+ * @{ */
+
+/** @brief 128 bit UUID values. */
+typedef struct
+{
+  uint8_t uuid128[16]; /**< Little-Endian UUID bytes. */
+} ble_uuid128_t;
+
+/** @brief  Bluetooth Low Energy UUID type, encapsulates both 16-bit and 128-bit UUIDs. */
+typedef struct
+{
+  uint16_t    uuid; /**< 16-bit UUID value or octets 12-13 of 128-bit UUID. */
+  uint8_t     type; /**< UUID type, see @ref BLE_UUID_TYPES. If type is @ref BLE_UUID_TYPE_UNKNOWN, the value of uuid is undefined. */
+} ble_uuid_t;
+
+/** @} */
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_BLE_TYPES_H__ */
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error.h
new file mode 100644
index 0000000000..e4f90fd54c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error.h
@@ -0,0 +1,90 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+ /**
+  @defgroup nrf_error SoftDevice Global Error Codes
+  @{
+   
+  @brief Global Error definitions
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_H__
+#define NRF_ERROR_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @defgroup NRF_ERRORS_BASE Error Codes Base number definitions
+ * @{ */
+#define NRF_ERROR_BASE_NUM      (0x0)       ///< Global error base
+#define NRF_ERROR_SDM_BASE_NUM  (0x1000)    ///< SDM error base
+#define NRF_ERROR_SOC_BASE_NUM  (0x2000)    ///< SoC error base
+#define NRF_ERROR_STK_BASE_NUM  (0x3000)    ///< STK error base
+/** @} */
+
+#define NRF_SUCCESS                           (NRF_ERROR_BASE_NUM + 0)  ///< Successful command
+#define NRF_ERROR_SVC_HANDLER_MISSING         (NRF_ERROR_BASE_NUM + 1)  ///< SVC handler is missing
+#define NRF_ERROR_SOFTDEVICE_NOT_ENABLED      (NRF_ERROR_BASE_NUM + 2)  ///< SoftDevice has not been enabled
+#define NRF_ERROR_INTERNAL                    (NRF_ERROR_BASE_NUM + 3)  ///< Internal Error
+#define NRF_ERROR_NO_MEM                      (NRF_ERROR_BASE_NUM + 4)  ///< No Memory for operation
+#define NRF_ERROR_NOT_FOUND                   (NRF_ERROR_BASE_NUM + 5)  ///< Not found
+#define NRF_ERROR_NOT_SUPPORTED               (NRF_ERROR_BASE_NUM + 6)  ///< Not supported
+#define NRF_ERROR_INVALID_PARAM               (NRF_ERROR_BASE_NUM + 7)  ///< Invalid Parameter
+#define NRF_ERROR_INVALID_STATE               (NRF_ERROR_BASE_NUM + 8)  ///< Invalid state, operation disallowed in this state
+#define NRF_ERROR_INVALID_LENGTH              (NRF_ERROR_BASE_NUM + 9)  ///< Invalid Length
+#define NRF_ERROR_INVALID_FLAGS               (NRF_ERROR_BASE_NUM + 10) ///< Invalid Flags
+#define NRF_ERROR_INVALID_DATA                (NRF_ERROR_BASE_NUM + 11) ///< Invalid Data
+#define NRF_ERROR_DATA_SIZE                   (NRF_ERROR_BASE_NUM + 12) ///< Invalid Data size
+#define NRF_ERROR_TIMEOUT                     (NRF_ERROR_BASE_NUM + 13) ///< Operation timed out
+#define NRF_ERROR_NULL                        (NRF_ERROR_BASE_NUM + 14) ///< Null Pointer
+#define NRF_ERROR_FORBIDDEN                   (NRF_ERROR_BASE_NUM + 15) ///< Forbidden Operation
+#define NRF_ERROR_INVALID_ADDR                (NRF_ERROR_BASE_NUM + 16) ///< Bad Memory Address
+#define NRF_ERROR_BUSY                        (NRF_ERROR_BASE_NUM + 17) ///< Busy
+#define NRF_ERROR_CONN_COUNT                  (NRF_ERROR_BASE_NUM + 18) ///< Maximum connection count exceeded.
+#define NRF_ERROR_RESOURCES                   (NRF_ERROR_BASE_NUM + 19) ///< Not enough resources for operation
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error_sdm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error_sdm.h
new file mode 100644
index 0000000000..575829c7f9
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error_sdm.h
@@ -0,0 +1,70 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ /**
+  @addtogroup nrf_sdm_api
+  @{
+  @defgroup nrf_sdm_error SoftDevice Manager Error Codes
+  @{
+
+  @brief Error definitions for the SDM API
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_SDM_H__
+#define NRF_ERROR_SDM_H__
+
+#include "nrf_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN              (NRF_ERROR_SDM_BASE_NUM + 0)  ///< Unknown lfclk source.
+#define NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION (NRF_ERROR_SDM_BASE_NUM + 1)  ///< Incorrect interrupt configuration (can be caused by using illegal priority levels, or having enabled SoftDevice interrupts).
+#define NRF_ERROR_SDM_INCORRECT_CLENR0                  (NRF_ERROR_SDM_BASE_NUM + 2)  ///< Incorrect CLENR0 (can be caused by erronous SoftDevice flashing).
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_SDM_H__
+
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error_soc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error_soc.h
new file mode 100644
index 0000000000..28989ee4e1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_error_soc.h
@@ -0,0 +1,85 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @addtogroup nrf_soc_api
+  @{
+  @defgroup nrf_soc_error SoC Library Error Codes
+  @{
+     
+  @brief Error definitions for the SoC library
+
+*/
+
+/* Header guard */
+#ifndef NRF_ERROR_SOC_H__
+#define NRF_ERROR_SOC_H__
+
+#include "nrf_error.h"
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Mutex Errors */
+#define NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN                 (NRF_ERROR_SOC_BASE_NUM + 0)  ///< Mutex already taken
+
+/* NVIC errors */
+#define NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE        (NRF_ERROR_SOC_BASE_NUM + 1)  ///< NVIC interrupt not available
+#define NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED (NRF_ERROR_SOC_BASE_NUM + 2)  ///< NVIC interrupt priority not allowed
+#define NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN              (NRF_ERROR_SOC_BASE_NUM + 3)  ///< NVIC should not return
+
+/* Power errors */
+#define NRF_ERROR_SOC_POWER_MODE_UNKNOWN                  (NRF_ERROR_SOC_BASE_NUM + 4)  ///< Power mode unknown
+#define NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN         (NRF_ERROR_SOC_BASE_NUM + 5)  ///< Power POF threshold unknown
+#define NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN         (NRF_ERROR_SOC_BASE_NUM + 6)  ///< Power off should not return
+
+/* Rand errors */
+#define NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES              (NRF_ERROR_SOC_BASE_NUM + 7)  ///< RAND not enough values
+
+/* PPI errors */
+#define NRF_ERROR_SOC_PPI_INVALID_CHANNEL                 (NRF_ERROR_SOC_BASE_NUM + 8)  ///< Invalid PPI Channel
+#define NRF_ERROR_SOC_PPI_INVALID_GROUP                   (NRF_ERROR_SOC_BASE_NUM + 9)  ///< Invalid PPI Group
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_ERROR_SOC_H__
+/**
+  @}
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_nvic.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_nvic.h
new file mode 100644
index 0000000000..8b49061c72
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_nvic.h
@@ -0,0 +1,486 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+ * @defgroup nrf_nvic_api SoftDevice NVIC API
+ * @{
+ *
+ * @note In order to use this module, the following code has to be added to a .c file:
+ *     \code
+ *     nrf_nvic_state_t nrf_nvic_state;
+ *     \endcode
+ *
+ * @note Definitions and declarations starting with __ (double underscore) in this header file are
+ * not intended for direct use by the application.
+ *
+ * @brief APIs for the accessing NVIC when using a SoftDevice.
+ *
+ */
+
+#ifndef NRF_NVIC_H__
+#define NRF_NVIC_H__
+
+#include <stdint.h>
+#include "nrf.h"
+
+#include "nrf_error_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup NRF_NVIC_DEFINES Defines
+ * @{ */
+
+/**@defgroup NRF_NVIC_ISER_DEFINES SoftDevice NVIC internal definitions
+ * @{ */
+
+#define __NRF_NVIC_NVMC_IRQn (30) /**< The peripheral ID of the NVMC. IRQ numbers are used to identify peripherals, but the NVMC doesn't have an IRQ number in the MDK. */
+
+#ifdef NRF51
+  #define __NRF_NVIC_ISER_COUNT (1) /**< The number of ISER/ICER registers in the NVIC that are used. */
+
+  /**@brief Interrupts used by the SoftDevice. */
+  #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
+        (1U << POWER_CLOCK_IRQn) \
+      | (1U << RADIO_IRQn) \
+      | (1U << RTC0_IRQn) \
+      | (1U << TIMER0_IRQn) \
+      | (1U << RNG_IRQn) \
+      | (1U << ECB_IRQn) \
+      | (1U << CCM_AAR_IRQn) \
+      | (1U << TEMP_IRQn) \
+      | (1U << __NRF_NVIC_NVMC_IRQn) \
+      | (1U << (uint32_t)SWI4_IRQn) \
+      | (1U << (uint32_t)SWI5_IRQn) \
+    ))
+
+  /**@brief Interrupts available for to application. */
+  #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
+#endif
+
+#ifdef NRF52
+  #define __NRF_NVIC_ISER_COUNT (2) /**< The number of ISER/ICER registers in the NVIC that are used. */
+
+  /**@brief Interrupts used by the SoftDevice. */
+  #define __NRF_NVIC_SD_IRQS_0 ((uint32_t)( \
+        (1U << POWER_CLOCK_IRQn) \
+      | (1U << RADIO_IRQn) \
+      | (1U << RTC0_IRQn) \
+      | (1U << TIMER0_IRQn) \
+      | (1U << RNG_IRQn) \
+      | (1U << ECB_IRQn) \
+      | (1U << CCM_AAR_IRQn) \
+      | (1U << TEMP_IRQn) \
+      | (1U << __NRF_NVIC_NVMC_IRQn) \
+      | (1U << (uint32_t)SWI4_EGU4_IRQn) \
+      | (1U << (uint32_t)SWI5_EGU5_IRQn) \
+    ))
+  #define __NRF_NVIC_SD_IRQS_1 ((uint32_t)0)
+
+  /**@brief Interrupts available for to application. */
+  #define __NRF_NVIC_APP_IRQS_0 (~__NRF_NVIC_SD_IRQS_0)
+  #define __NRF_NVIC_APP_IRQS_1 (~__NRF_NVIC_SD_IRQS_1)
+#endif
+/**@} */
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_VARIABLES Variables
+ * @{ */
+
+/**@brief Type representing the state struct for the SoftDevice NVIC module. */
+typedef struct
+{
+  uint32_t volatile __irq_masks[__NRF_NVIC_ISER_COUNT]; /**< IRQs enabled by the application in the NVIC. */
+  uint32_t volatile __cr_flag;                          /**< Non-zero if already in a critical region */
+} nrf_nvic_state_t;
+
+/**@brief Variable keeping the state for the SoftDevice NVIC module. This must be declared in an
+ * application source file. */
+extern nrf_nvic_state_t nrf_nvic_state;
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_INTERNAL_FUNCTIONS SoftDevice NVIC internal functions
+ * @{ */
+
+/**@brief Disables IRQ interrupts globally, including the SoftDevice's interrupts.
+ *
+ * @retval  The value of PRIMASK prior to disabling the interrupts.
+ */
+static inline int __sd_nvic_irq_disable(void)
+{
+  int pm = __get_PRIMASK();
+  __disable_irq();
+  return pm;
+}
+
+/**@brief Enables IRQ interrupts globally, including the SoftDevice's interrupts.
+ */
+static inline void __sd_nvic_irq_enable(void)
+{
+  __enable_irq();
+}
+
+/**@brief Checks if IRQn is available to application
+ * @param[in]  IRQn  irq to check
+ *
+ * @retval  1 (true) if the irq to check is available to the application
+ */
+static inline uint32_t __sd_nvic_app_accessible_irq(IRQn_Type IRQn)
+{
+  if (IRQn < 32)
+  {
+    return ((1UL<<IRQn) & __NRF_NVIC_APP_IRQS_0) != 0;
+  }
+#ifdef NRF52
+  else if (IRQn < 64)
+  {
+    return ((1UL<<(IRQn-32)) & __NRF_NVIC_APP_IRQS_1) != 0;
+  }
+#endif
+  else
+  {
+    return 1;
+  }
+}
+
+/**@brief Checks if IRQn is available to application
+ * @param[in]  priority  priority to check
+ *
+ * @retval  1 (true) if the priority to check is available to the application
+ */
+static inline uint32_t __sd_nvic_is_app_accessible_priority(uint32_t priority)
+{
+  if(priority >= (1 << __NVIC_PRIO_BITS))
+  {
+    return 0;
+  }
+#ifdef NRF51
+  if(   priority == 0
+     || priority == 2
+     )
+  {
+    return 0;
+  }
+#endif
+#ifdef NRF52
+  if(   priority == 0
+     || priority == 1
+     || priority == 4
+     || priority == 5
+     )
+  {
+    return 0;
+  }
+#endif
+  return 1;
+}
+
+/**@} */
+
+/**@addtogroup NRF_NVIC_FUNCTIONS SoftDevice NVIC public functions
+ * @{ */
+
+/**@brief Enable External Interrupt.
+ * @note Corresponds to NVIC_EnableIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_EnableIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt was enabled.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt has a priority not available for the application.
+ */
+static inline uint32_t sd_nvic_EnableIRQ(IRQn_Type IRQn)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+  if (!__sd_nvic_is_app_accessible_priority(NVIC_GetPriority(IRQn)))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
+  }
+
+  if (nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] |= (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F));
+  }
+  else
+  {
+    NVIC_EnableIRQ(IRQn);
+  }
+  return NRF_SUCCESS;
+}
+
+/**@brief  Disable External Interrupt.
+ * @note Corresponds to NVIC_DisableIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_DisableIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt was disabled.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE The interrupt is not available for the application.
+ */
+static inline uint32_t sd_nvic_DisableIRQ(IRQn_Type IRQn)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+
+  if (nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__irq_masks[(uint32_t)((int32_t)IRQn) >> 5] &= ~(1UL << ((uint32_t)(IRQn) & 0x1F));
+  }
+  else
+  {
+    NVIC_DisableIRQ(IRQn);
+  }
+
+  return NRF_SUCCESS;
+}
+
+/**@brief  Get Pending Interrupt.
+ * @note Corresponds to NVIC_GetPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in]   IRQn          See the NVIC_GetPendingIRQ documentation in CMSIS.
+ * @param[out]  p_pending_irq Return value from NVIC_GetPendingIRQ.
+ *
+ * @retval ::NRF_SUCCESS The interrupt is available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_GetPendingIRQ(IRQn_Type IRQn, uint32_t * p_pending_irq)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    *p_pending_irq = NVIC_GetPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief  Set Pending Interrupt.
+ * @note Corresponds to NVIC_SetPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_SetPendingIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt is set pending.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_SetPendingIRQ(IRQn_Type IRQn)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    NVIC_SetPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief  Clear Pending Interrupt.
+ * @note Corresponds to NVIC_ClearPendingIRQ in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn See the NVIC_ClearPendingIRQ documentation in CMSIS.
+ *
+ * @retval ::NRF_SUCCESS The interrupt pending flag is cleared.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    NVIC_ClearPendingIRQ(IRQn);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief Set Interrupt Priority.
+ * @note Corresponds to NVIC_SetPriority in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ * @pre Priority is valid and not reserved by the stack.
+ *
+ * @param[in] IRQn      See the NVIC_SetPriority documentation in CMSIS.
+ * @param[in] priority  A valid IRQ priority for use by the application.
+ *
+ * @retval ::NRF_SUCCESS The interrupt and priority level is available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE IRQn is not available for the application.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED The interrupt priority is not available for the application.
+ */
+static inline uint32_t sd_nvic_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if (!__sd_nvic_app_accessible_irq(IRQn))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+
+  if (!__sd_nvic_is_app_accessible_priority(priority))
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_PRIORITY_NOT_ALLOWED;
+  }
+
+  NVIC_SetPriority(IRQn, (uint32_t)priority);
+  return NRF_SUCCESS;
+}
+
+/**@brief Get Interrupt Priority.
+ * @note Corresponds to NVIC_GetPriority in CMSIS.
+ *
+ * @pre IRQn is valid and not reserved by the stack.
+ *
+ * @param[in]  IRQn         See the NVIC_GetPriority documentation in CMSIS.
+ * @param[out] p_priority   Return value from NVIC_GetPriority.
+ *
+ * @retval ::NRF_SUCCESS The interrupt priority is returned in p_priority.
+ * @retval ::NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE - IRQn is not available for the application.
+ */
+static inline uint32_t sd_nvic_GetPriority(IRQn_Type IRQn, uint32_t * p_priority)
+{
+  if (__sd_nvic_app_accessible_irq(IRQn))
+  {
+    *p_priority = (NVIC_GetPriority(IRQn) & 0xFF);
+    return NRF_SUCCESS;
+  }
+  else
+  {
+    return NRF_ERROR_SOC_NVIC_INTERRUPT_NOT_AVAILABLE;
+  }
+}
+
+/**@brief System Reset.
+ * @note Corresponds to NVIC_SystemReset in CMSIS.
+ *
+ * @retval ::NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN
+ */
+static inline uint32_t sd_nvic_SystemReset(void)
+{
+  NVIC_SystemReset();
+  return NRF_ERROR_SOC_NVIC_SHOULD_NOT_RETURN;
+}
+
+/**@brief Enters critical region.
+ *
+ * @post Application interrupts will be disabled.
+ * @note sd_nvic_critical_region_enter() and ::sd_nvic_critical_region_exit() must be called in matching pairs inside each
+ * execution context
+ * @sa sd_nvic_critical_region_exit
+ *
+ * @retval ::NRF_SUCCESS
+ */
+static inline uint32_t sd_nvic_critical_region_enter(uint8_t * p_is_nested_critical_region)
+{
+  int was_masked = __sd_nvic_irq_disable();
+  if (!nrf_nvic_state.__cr_flag)
+  {
+    nrf_nvic_state.__cr_flag = 1;
+    nrf_nvic_state.__irq_masks[0] = ( NVIC->ICER[0] & __NRF_NVIC_APP_IRQS_0 );
+    NVIC->ICER[0] = __NRF_NVIC_APP_IRQS_0;
+    #ifdef NRF52
+    nrf_nvic_state.__irq_masks[1] = ( NVIC->ICER[1] & __NRF_NVIC_APP_IRQS_1 );
+    NVIC->ICER[1] = __NRF_NVIC_APP_IRQS_1;
+    #endif
+    *p_is_nested_critical_region = 0;
+  }
+  else
+  {
+    *p_is_nested_critical_region = 1;
+  }
+  if (!was_masked)
+  {
+    __sd_nvic_irq_enable();
+  }
+  return NRF_SUCCESS;
+}
+
+/**@brief Exit critical region.
+ *
+ * @pre Application has entered a critical region using ::sd_nvic_critical_region_enter.
+ * @post If not in a nested critical region, the application interrupts will restored to the state before ::sd_nvic_critical_region_enter was called.
+ *
+ * @param[in] is_nested_critical_region If this is set to 1, the critical region won't be exited. @sa sd_nvic_critical_region_enter.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+static inline uint32_t sd_nvic_critical_region_exit(uint8_t is_nested_critical_region)
+{
+  if (nrf_nvic_state.__cr_flag && (is_nested_critical_region == 0))
+  {
+    int was_masked = __sd_nvic_irq_disable();
+    NVIC->ISER[0] = nrf_nvic_state.__irq_masks[0];
+    #ifdef NRF52
+    NVIC->ISER[1] = nrf_nvic_state.__irq_masks[1];
+    #endif
+    nrf_nvic_state.__cr_flag = 0;
+    if (!was_masked)
+    {
+      __sd_nvic_irq_enable();
+    }
+  }
+
+  return NRF_SUCCESS;
+}
+/**@} */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif // NRF_NVIC_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_sd_def.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_sd_def.h
new file mode 100644
index 0000000000..1af95f1dc6
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_sd_def.h
@@ -0,0 +1,50 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_SD_DEF_H__
+#define NRF_SD_DEF_H__
+
+#include <stdint.h>
+
+#define SD_PPI_CHANNELS_USED       		0xFFF0C000uL /**< PPI channels utilized by SotfDevice (not available to the application). */
+#define SD_PPI_GROUPS_USED              0x0000000CuL /**< PPI groups utilized by SoftDevice (not available to the application). */
+#define SD_TIMERS_USED                  0x00000001uL /**< Timers used by SoftDevice. */
+#define SD_SWI_USED                     0x0000003CuL /**< Software interrupts used by SoftDevice */
+
+#endif /* NRF_SD_DEF_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_sdm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_sdm.h
new file mode 100644
index 0000000000..bb370abffe
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_sdm.h
@@ -0,0 +1,274 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+/**
+  @defgroup nrf_sdm_api SoftDevice Manager API
+  @{
+
+  @brief APIs for SoftDevice management.
+
+*/
+
+/* Header guard */
+#ifndef NRF_SDM_H__
+#define NRF_SDM_H__
+
+#include "nrf_svc.h"
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "nrf_error_sdm.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup NRF_SDM_DEFINES Defines
+ * @{ */
+#ifdef NRFSOC_DOXYGEN
+//Stuff defined elsewere, to satisfy doxygen
+#define MBR_SIZE 0
+#warning test
+#endif
+
+/** @brief SoftDevice Manager SVC Base number. */
+#define SDM_SVC_BASE 0x10
+
+/** @brief Defines the SoftDevice Information Structure location (address) as an offset from
+the start of the softdevice (without MBR)*/
+#define SOFTDEVICE_INFO_STRUCT_OFFSET (0x2000)
+
+/** @brief Defines the absolute Softdevice information structure location (address)*/
+#define SOFTDEVICE_INFO_STRUCT_ADDRESS (SOFTDEVICE_INFO_STRUCT_OFFSET + MBR_SIZE)
+
+/** @brief Defines the offset for Softdevice size value relative to Softdevice base address*/
+#define SD_SIZE_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x08)
+
+/** @brief Defines the offset for FWID value relative to Softdevice base address*/
+#define SD_FWID_OFFSET (SOFTDEVICE_INFO_STRUCT_OFFSET + 0x0C)
+
+/** @brief Defines a macro for retreiving the actual Softdevice size value from a given base address
+           use @ref MBR_SIZE when Softdevice is installed just above the MBR (the usual case)*/
+#define SD_SIZE_GET(baseaddr) (*((uint32_t *) ((baseaddr) + SD_SIZE_OFFSET)))
+
+/** @brief Defines a macro for retreiving the actual FWID value from a given base address
+           use @ref MBR_SIZE when Softdevice is installed just above the MBR (the usual case)*/
+#define SD_FWID_GET(baseaddr) ((*((uint32_t *) ((baseaddr) + SD_FWID_OFFSET))) & 0xFFFF)
+
+/**@defgroup NRF_FAULT_ID_RANGES Fault ID ranges
+ * @{ */
+#define NRF_FAULT_ID_SD_RANGE_START     0x00000000            /**< SoftDevice ID range start. */
+#define NRF_FAULT_ID_APP_RANGE_START    0x00001000            /**< Application ID range start. */
+/**@} */
+
+/**@defgroup NRF_FAULT_IDS Fault ID types
+ * @{ */
+#define NRF_FAULT_ID_SD_ASSERT    (NRF_FAULT_ID_SD_RANGE_START + 1)           /**< SoftDevice assertion. The info parameter will be set to 0x00000000. */
+#define NRF_FAULT_ID_APP_MEMACC   (NRF_FAULT_ID_APP_RANGE_START + 1)          /**< Application invalid memory access. The info parameter will contain the address in memory that was accessed. */
+/**@} */
+
+/** @} */
+
+/** @addtogroup NRF_SDM_ENUMS Enumerations
+ * @{ */
+
+/**@brief nRF SoftDevice Manager API SVC numbers. */
+enum NRF_SD_SVCS
+{
+  SD_SOFTDEVICE_ENABLE = SDM_SVC_BASE, /**< ::sd_softdevice_enable */
+  SD_SOFTDEVICE_DISABLE,               /**< ::sd_softdevice_disable */
+  SD_SOFTDEVICE_IS_ENABLED,            /**< ::sd_softdevice_is_enabled */
+  SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, /**< ::sd_softdevice_vector_table_base_set */
+  SVC_SDM_LAST                         /**< Placeholder for last SDM SVC */
+};
+
+/** @} */
+
+/** @addtogroup NRF_SDM_DEFINES Defines
+ * @{ */
+
+/**@defgroup NRF_CLOCK_LF_XTAL_ACCURACY Clock accuracy * @{ */
+
+#define NRF_CLOCK_LF_XTAL_ACCURACY_250_PPM (0) /* Default */
+#define NRF_CLOCK_LF_XTAL_ACCURACY_500_PPM (1)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_150_PPM (2)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_100_PPM (3)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_75_PPM  (4)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_50_PPM  (5)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_30_PPM  (6)
+#define NRF_CLOCK_LF_XTAL_ACCURACY_20_PPM  (7)
+
+/** @} */
+
+/**@defgroup NRF_CLOCK_LF_SRC Possible lfclk oscillator sources * @{ */
+
+#define NRF_CLOCK_LF_SRC_RC      (0)                        /**< LFCLK RC oscillator. */
+#define NRF_CLOCK_LF_SRC_XTAL    (1)                        /**< LFCLK crystal oscillator. */
+#define NRF_CLOCK_LF_SRC_SYNTH   (2)                        /**< LFCLK Synthesized from HFCLK. */
+
+/** @} */
+/** @} */
+
+/** @addtogroup NRF_SDM_TYPES Types
+ * @{ */
+
+/**@brief Type representing lfclk oscillator source. */
+typedef struct
+{
+  uint8_t source;        /**< LF oscillator clock source, see @ref NRF_CLOCK_LF_SRC. */
+  uint8_t rc_ctiv;      /**< Only for NRF_CLOCK_LF_SRC_RC: Calibration timer interval in 1/4 second
+                              units (nRF51: 1-64, nRF52: 1-32).
+                              @note To avoid excessive clock drift, 0.5 degrees Celsius is the
+                                    maximum temperature change allowed in one calibration timer
+                                    interval. The interval should be selected to ensure this.
+
+                              @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.  */
+  uint8_t rc_temp_ctiv; /**<  Only for NRF_CLOCK_LF_SRC_RC: How often (in number of calibration
+                              intervals) the RC oscillator shall be calibrated if the temperature
+                              hasn't changed.
+                                  0: Always calibrate even if the temperature hasn't changed.
+                                  1: Only calibrate if the temperature has changed (nRF51 only).
+                                  2-33: Check the temperature and only calibrate if it has changed,
+                                        however calibration will take place every rc_temp_ctiv
+                                        intervals in any case.
+
+                              @note Must be 0 if source is not NRF_CLOCK_LF_SRC_RC.
+
+                              @note For nRF52, the application must ensure calibration at least once
+                                    every 8 seconds to ensure +/-250ppm clock stability. The
+                                    recommended configuration for NRF_CLOCK_LF_SRC_RC on nRF52 is
+                                    rc_ctiv=16 and rc_temp_ctiv=2. This will ensure calibration at
+                                    least once every 8 seconds and for temperature changes of 0.5
+                                    degrees Celsius every 4 seconds. See the Product Specification
+                                    for the nRF52 device being used for more information.*/
+  uint8_t xtal_accuracy; /**< External crystal clock accuracy used in the LL to compute timing windows.
+
+                              @note For the NRF_CLOCK_LF_SRC_RC clock source this parameter is ignored. */
+} nrf_clock_lf_cfg_t;
+
+/**@brief Fault Handler type.
+ *
+ * When certain unrecoverable errors occur within the application or SoftDevice the fault handler will be called back.
+ * The protocol stack will be in an undefined state when this happens and the only way to recover will be to
+ * perform a reset, using e.g. CMSIS NVIC_SystemReset().
+ *
+ * @note This callback is executed in HardFault context, thus SVC functions cannot be called from the fault callback.
+ *
+ * @param[in] id Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc The program counter of the instruction that triggered the fault.
+ * @param[in] info Optional additional information regarding the fault. Refer to each Fault identifier for details.
+ */
+typedef void (*nrf_fault_handler_t)(uint32_t id, uint32_t pc, uint32_t info);
+
+/** @} */
+
+/** @addtogroup NRF_SDM_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Enables the SoftDevice and by extension the protocol stack.
+ *
+ * @note Some care must be taken if a low frequency clock source is already running when calling this function:
+ *       If the LF clock has a different source then the one currently running, it will be stopped. Then, the new
+ *       clock source will be started.
+ *
+ * @note This function has no effect when returning with an error.
+ *
+ * @post If return code is ::NRF_SUCCESS
+ *       - SoC library and protocol stack APIs are made available.
+ *       - A portion of RAM will be unavailable (see relevant SDS documentation).
+ *       - Some peripherals will be unavailable or available only through the SoC API (see relevant SDS documentation).
+ *       - Interrupts will not arrive from protected peripherals or interrupts.
+ *       - nrf_nvic_ functions must be used instead of CMSIS NVIC_ functions for reliable usage of the SoftDevice.
+ *       - Interrupt latency may be affected by the SoftDevice  (see relevant SDS documentation).
+ *       - Chosen low frequency clock source will be running.
+ *
+ * @param p_clock_lf_cfg Low frequency clock source and accuracy.
+                         If NULL the clock will be configured as an rc source with rc_ctiv = 16 and .rc_temp_ctiv = 2
+                         In the case of XTAL source, the PPM accuracy of the chosen clock source must be greater than or equal to the actual characteristics of your XTAL clock.
+ * @param fault_handler Callback to be invoked in case of fault.
+ *
+ * @retval ::NRF_SUCCESS
+ * @retval ::NRF_ERROR_INVALID_STATE SoftDevice is already enabled, and the clock source and fault handler cannot be updated.
+ * @retval ::NRF_ERROR_SDM_INCORRECT_INTERRUPT_CONFIGURATION SoftDevice interrupt is already enabled, or an enabled interrupt has an illegal priority level.
+ * @retval ::NRF_ERROR_SDM_LFCLK_SOURCE_UNKNOWN Unknown low frequency clock source selected.
+ */
+SVCALL(SD_SOFTDEVICE_ENABLE, uint32_t, sd_softdevice_enable(nrf_clock_lf_cfg_t const * p_clock_lf_cfg, nrf_fault_handler_t fault_handler));
+
+
+/**@brief Disables the SoftDevice and by extension the protocol stack.
+ *
+ * Idempotent function to disable the SoftDevice.
+ *
+ * @post SoC library and protocol stack APIs are made unavailable.
+ * @post All interrupts that was protected by the SoftDevice will be disabled and initialized to priority 0 (highest).
+ * @post All peripherals used by the SoftDevice will be reset to default values.
+ * @post All of RAM become available.
+ * @post All interrupts are forwarded to the application.
+ * @post LFCLK source chosen in ::sd_softdevice_enable will be left running.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_DISABLE, uint32_t, sd_softdevice_disable(void));
+
+/**@brief Check if the SoftDevice is enabled.
+ *
+ * @param[out]  p_softdevice_enabled If the SoftDevice is enabled: 1 else 0.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_IS_ENABLED, uint32_t, sd_softdevice_is_enabled(uint8_t * p_softdevice_enabled));
+
+/**@brief Sets the base address of the interrupt vector table for interrupts forwarded from the SoftDevice
+ *
+ * This function is only intended to be called when a bootloader is enabled.
+ *
+ * @param[in] address The base address of the interrupt vector table for forwarded interrupts.
+
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_SOFTDEVICE_VECTOR_TABLE_BASE_SET, uint32_t, sd_softdevice_vector_table_base_set(uint32_t address));
+
+/** @} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_SDM_H__
+
+/**
+  @}
+*/
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_soc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_soc.h
new file mode 100644
index 0000000000..e1fbb2236a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_soc.h
@@ -0,0 +1,911 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+/**
+ * @defgroup nrf_soc_api SoC Library API
+ * @{
+ * 
+ * @brief APIs for the SoC library.
+ * 
+ */
+
+#ifndef NRF_SOC_H__
+#define NRF_SOC_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_svc.h"
+#include "nrf.h"
+
+#include "nrf_error_soc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**@addtogroup NRF_SOC_DEFINES Defines
+ * @{ */
+
+/**@brief The number of the lowest SVC number reserved for the SoC library. */
+#define SOC_SVC_BASE               (0x20)
+#define SOC_SVC_BASE_NOT_AVAILABLE (0x2B)
+
+/**@brief Guranteed time for application to process radio inactive notification. */
+#define NRF_RADIO_NOTIFICATION_INACTIVE_GUARANTEED_TIME_US  (62)
+
+/**@brief The minimum allowed timeslot extension time. */
+#define NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US (200)
+
+#define SOC_ECB_KEY_LENGTH                (16)                       /**< ECB key length. */
+#define SOC_ECB_CLEARTEXT_LENGTH          (16)                       /**< ECB cleartext length. */
+#define SOC_ECB_CIPHERTEXT_LENGTH         (SOC_ECB_CLEARTEXT_LENGTH) /**< ECB ciphertext length. */
+
+#ifdef NRF51
+#define SD_EVT_IRQn                       (SWI2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SD_EVT_IRQHandler                 (SWI2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
+#define RADIO_NOTIFICATION_IRQn           (SWI1_IRQn)        /**< The radio notification IRQ number. */
+#define RADIO_NOTIFICATION_IRQHandler     (SWI1_IRQHandler)  /**< The radio notification IRQ handler. */
+#endif
+#ifdef NRF52
+#define SD_EVT_IRQn                       (SWI2_EGU2_IRQn)        /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SD_EVT_IRQHandler                 (SWI2_EGU2_IRQHandler)  /**< SoftDevice Event IRQ handler. Used for both protocol events and SoC events. */
+#define RADIO_NOTIFICATION_IRQn           (SWI1_EGU1_IRQn)        /**< The radio notification IRQ number. */
+#define RADIO_NOTIFICATION_IRQHandler     (SWI1_EGU1_IRQHandler)  /**< The radio notification IRQ handler. */
+#endif
+
+#define NRF_RADIO_LENGTH_MIN_US           (100)               /**< The shortest allowed radio timeslot, in microseconds. */
+#define NRF_RADIO_LENGTH_MAX_US           (100000)            /**< The longest allowed radio timeslot, in microseconds. */
+
+#define NRF_RADIO_DISTANCE_MAX_US         (128000000UL - 1UL) /**< The longest timeslot distance, in microseconds, allowed for the distance parameter (see @ref nrf_radio_request_normal_t) in the request. */
+
+#define NRF_RADIO_EARLIEST_TIMEOUT_MAX_US (128000000UL - 1UL) /**< The longest timeout, in microseconds, allowed when requesting the earliest possible timeslot. */
+
+#define NRF_RADIO_START_JITTER_US         (2)                 /**< The maximum jitter in @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START relative to the requested start time. */
+
+/**@} */
+
+/**@addtogroup NRF_SOC_ENUMS Enumerations
+ * @{ */
+
+/**@brief The SVC numbers used by the SVC functions in the SoC library. */
+enum NRF_SOC_SVCS
+{
+  SD_PPI_CHANNEL_ENABLE_GET = SOC_SVC_BASE,
+  SD_PPI_CHANNEL_ENABLE_SET,
+  SD_PPI_CHANNEL_ENABLE_CLR,
+  SD_PPI_CHANNEL_ASSIGN,
+  SD_PPI_GROUP_TASK_ENABLE,
+  SD_PPI_GROUP_TASK_DISABLE,
+  SD_PPI_GROUP_ASSIGN,
+  SD_PPI_GROUP_GET,
+  SD_FLASH_PAGE_ERASE,
+  SD_FLASH_WRITE,
+  SD_FLASH_PROTECT,
+  SD_MUTEX_NEW = SOC_SVC_BASE_NOT_AVAILABLE,
+  SD_MUTEX_ACQUIRE,
+  SD_MUTEX_RELEASE,
+  SD_RFU_1,
+  SD_RFU_2,
+  SD_RFU_3,
+  SD_RFU_4,
+  SD_RFU_5,
+  SD_RFU_6,
+  SD_RFU_7,
+  SD_RFU_8,
+  SD_RFU_9,
+  SD_RFU_10,
+  SD_RAND_APPLICATION_POOL_CAPACITY_GET,
+  SD_RAND_APPLICATION_BYTES_AVAILABLE_GET,
+  SD_RAND_APPLICATION_VECTOR_GET,
+  SD_POWER_MODE_SET,
+  SD_POWER_SYSTEM_OFF,
+  SD_POWER_RESET_REASON_GET,
+  SD_POWER_RESET_REASON_CLR,
+  SD_POWER_POF_ENABLE,
+  SD_POWER_POF_THRESHOLD_SET,
+  SD_POWER_RAMON_SET,
+  SD_POWER_RAMON_CLR,
+  SD_POWER_RAMON_GET,
+  SD_POWER_GPREGRET_SET,
+  SD_POWER_GPREGRET_CLR,
+  SD_POWER_GPREGRET_GET,
+  SD_POWER_DCDC_MODE_SET,
+  SD_APP_EVT_WAIT,
+  SD_CLOCK_HFCLK_REQUEST,
+  SD_CLOCK_HFCLK_RELEASE,
+  SD_CLOCK_HFCLK_IS_RUNNING,
+  SD_RADIO_NOTIFICATION_CFG_SET,
+  SD_ECB_BLOCK_ENCRYPT,
+  SD_ECB_BLOCKS_ENCRYPT,
+  SD_RADIO_SESSION_OPEN,
+  SD_RADIO_SESSION_CLOSE,
+  SD_RADIO_REQUEST,
+  SD_EVT_GET,
+  SD_TEMP_GET,
+  SVC_SOC_LAST
+};
+
+/**@brief Possible values of a ::nrf_mutex_t. */
+enum NRF_MUTEX_VALUES
+{
+  NRF_MUTEX_FREE,
+  NRF_MUTEX_TAKEN
+};
+
+/**@brief Power modes. */
+enum NRF_POWER_MODES
+{
+  NRF_POWER_MODE_CONSTLAT,  /**< Constant latency mode. See power management in the reference manual. */
+  NRF_POWER_MODE_LOWPWR     /**< Low power mode. See power management in the reference manual. */
+};
+
+
+/**@brief Power failure thresholds */
+enum NRF_POWER_THRESHOLDS
+{
+  NRF_POWER_THRESHOLD_V21,  /**< 2.1 Volts power failure threshold. */
+  NRF_POWER_THRESHOLD_V23,  /**< 2.3 Volts power failure threshold. */
+  NRF_POWER_THRESHOLD_V25,  /**< 2.5 Volts power failure threshold. */ 
+  NRF_POWER_THRESHOLD_V27   /**< 2.7 Volts power failure threshold. */
+};
+
+
+/**@brief DC/DC converter modes. */
+enum NRF_POWER_DCDC_MODES
+{
+  NRF_POWER_DCDC_DISABLE,          /**< The DCDC is disabled. */
+  NRF_POWER_DCDC_ENABLE            /**< The DCDC is enabled.  */
+};
+
+/**@brief Radio notification distances. */
+enum NRF_RADIO_NOTIFICATION_DISTANCES
+{
+  NRF_RADIO_NOTIFICATION_DISTANCE_NONE = 0, /**< The event does not have a notification. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_800US,    /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_1740US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_2680US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_3620US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_4560US,   /**< The distance from the active notification to start of radio activity. */
+  NRF_RADIO_NOTIFICATION_DISTANCE_5500US    /**< The distance from the active notification to start of radio activity. */
+};
+
+
+/**@brief Radio notification types. */
+enum NRF_RADIO_NOTIFICATION_TYPES
+{
+  NRF_RADIO_NOTIFICATION_TYPE_NONE = 0,        /**< The event does not have a radio notification signal. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_ACTIVE,   /**< Using interrupt for notification when the radio will be enabled. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE, /**< Using interrupt for notification when the radio has been disabled. */
+  NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH,     /**< Using interrupt for notification both when the radio will be enabled and disabled. */
+};
+
+/**@brief The Radio signal callback types. */
+enum NRF_RADIO_CALLBACK_SIGNAL_TYPE
+{
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_START,             /**< This signal indicates the start of the radio timeslot. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0,            /**< This signal indicates the NRF_TIMER0 interrupt. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO,             /**< This signal indicates the NRF_RADIO interrupt. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_FAILED,     /**< This signal indicates extend action failed. */
+  NRF_RADIO_CALLBACK_SIGNAL_TYPE_EXTEND_SUCCEEDED   /**< This signal indicates extend action succeeded. */
+};
+
+/**@brief The actions requested by the signal callback.
+ *
+ *  This code gives the SOC instructions about what action to take when the signal callback has
+ *  returned.
+ */
+enum NRF_RADIO_SIGNAL_CALLBACK_ACTION
+{
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_NONE,            /**< Return without action. */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND,          /**< Request an extension of the current timeslot (maximum execution time for this action is when the extension succeeded). */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_END,             /**< End the current radio timeslot. */
+  NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END  /**< Request a new radio timeslot and end the current timeslot. */
+};
+
+/**@brief Radio timeslot high frequency clock source configuration. */
+enum NRF_RADIO_HFCLK_CFG
+{
+  NRF_RADIO_HFCLK_CFG_XTAL_GUARANTEED, /**< The SoftDevice will guarantee that the high frequency clock source is the
+                                           external crystal for the whole duration of the timeslot. This should be the
+                                           preferred option for events that use the radio or require high timing accuracy. */
+  NRF_RADIO_HFCLK_CFG_NO_GUARANTEE    /**< This configuration allows for earlier and tighter scheduling of timeslots.
+                                           The RC oscillator may be the clock source in part or for the whole duration of the timeslot.
+                                           The RC oscillator's accuracy must therefore be taken into consideration.
+                                           @note If the application will use the radio peripheral in timeslots with this configuration,
+                                           it must make sure that the crystal is running and stable before starting the radio. */
+};
+
+/**@brief Radio timeslot priorities. */
+enum NRF_RADIO_PRIORITY
+{
+  NRF_RADIO_PRIORITY_HIGH,                          /**< High (equal priority as the normal connection priority of the SoftDevice stack(s)). */
+  NRF_RADIO_PRIORITY_NORMAL,                        /**< Normal (equal priority as the priority of secondary activites of the SoftDevice stack(s)). */
+};
+
+/**@brief Radio timeslot request type. */
+enum NRF_RADIO_REQUEST_TYPE
+{
+  NRF_RADIO_REQ_TYPE_EARLIEST,                      /**< Request radio timeslot as early as possible. This should always be used for the first request in a session. */
+  NRF_RADIO_REQ_TYPE_NORMAL                         /**< Normal radio timeslot request. */
+};
+
+/**@brief SoC Events. */
+enum NRF_SOC_EVTS
+{
+  NRF_EVT_HFCLKSTARTED,                         /**< Event indicating that the HFCLK has started. */
+  NRF_EVT_POWER_FAILURE_WARNING,                /**< Event indicating that a power failure warning has occurred. */
+  NRF_EVT_FLASH_OPERATION_SUCCESS,              /**< Event indicating that the ongoing flash operation has completed successfully. */
+  NRF_EVT_FLASH_OPERATION_ERROR,                /**< Event indicating that the ongoing flash operation has timed out with an error. */
+  NRF_EVT_RADIO_BLOCKED,                        /**< Event indicating that a radio timeslot was blocked. */
+  NRF_EVT_RADIO_CANCELED,                       /**< Event indicating that a radio timeslot was canceled by SoftDevice. */
+  NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN, /**< Event indicating that a radio timeslot signal callback handler return was invalid. */
+  NRF_EVT_RADIO_SESSION_IDLE,                   /**< Event indicating that a radio timeslot session is idle. */
+  NRF_EVT_RADIO_SESSION_CLOSED,                 /**< Event indicating that a radio timeslot session is closed. */
+  NRF_EVT_NUMBER_OF_EVTS
+};
+
+/**@} */
+
+
+/**@addtogroup NRF_SOC_STRUCTURES Structures
+ * @{ */
+
+/**@brief Represents a mutex for use with the nrf_mutex functions.
+ * @note Accessing the value directly is not safe, use the mutex functions!
+ */
+typedef volatile uint8_t nrf_mutex_t;
+
+/**@brief Parameters for a request for a timeslot as early as possible. */
+typedef struct
+{
+  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
+  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
+  uint32_t      length_us;                          /**< The radio timeslot length (in the range 100 to 100,000] microseconds). */
+  uint32_t      timeout_us;                         /**< Longest acceptable delay until the start of the requested timeslot (up to @ref NRF_RADIO_EARLIEST_TIMEOUT_MAX_US microseconds). */
+} nrf_radio_request_earliest_t;
+
+/**@brief Parameters for a normal radio timeslot request. */
+typedef struct
+{
+  uint8_t       hfclk;                              /**< High frequency clock source, see @ref NRF_RADIO_HFCLK_CFG. */
+  uint8_t       priority;                           /**< The radio timeslot priority, see @ref NRF_RADIO_PRIORITY. */
+  uint32_t      distance_us;                        /**< Distance from the start of the previous radio timeslot (up to @ref NRF_RADIO_DISTANCE_MAX_US microseconds). */
+  uint32_t      length_us;                          /**< The radio timeslot length (in the range [100..100,000] microseconds). */
+} nrf_radio_request_normal_t;
+
+/**@brief Radio timeslot request parameters. */
+typedef struct
+{
+  uint8_t                         request_type;     /**< Type of request, see @ref NRF_RADIO_REQUEST_TYPE. */
+  union
+  {
+    nrf_radio_request_earliest_t  earliest;         /**< Parameters for requesting a radio timeslot as early as possible. */
+    nrf_radio_request_normal_t    normal;           /**< Parameters for requesting a normal radio timeslot. */
+  } params;
+} nrf_radio_request_t;
+
+/**@brief Return parameters of the radio timeslot signal callback. */
+typedef struct
+{
+  uint8_t               callback_action;            /**< The action requested by the application when returning from the signal callback, see @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION. */
+  union
+  {
+    struct
+    {
+      nrf_radio_request_t * p_next;                 /**< The request parameters for the next radio timeslot. */
+    } request;                                      /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_REQUEST_AND_END. */
+    struct
+    {
+      uint32_t              length_us;              /**< Requested extension of the radio timeslot duration (microseconds) (for minimum time see @ref NRF_RADIO_MINIMUM_TIMESLOT_LENGTH_EXTENSION_TIME_US). */
+    } extend;                                       /**< Additional parameters for return_code @ref NRF_RADIO_SIGNAL_CALLBACK_ACTION_EXTEND. */
+  } params;
+} nrf_radio_signal_callback_return_param_t;
+
+/**@brief The radio timeslot signal callback type.
+ *
+ * @note In case of invalid return parameters, the radio timeslot will automatically end
+ *       immediately after returning from the signal callback and the
+ *       @ref NRF_EVT_RADIO_SIGNAL_CALLBACK_INVALID_RETURN event will be sent.
+ * @note The returned struct pointer must remain valid after the signal callback
+ *       function returns. For instance, this means that it must not point to a stack variable.
+ *
+ * @param[in] signal_type Type of signal, see @ref NRF_RADIO_CALLBACK_SIGNAL_TYPE.
+ *
+ * @return Pointer to structure containing action requested by the application.
+ */
+typedef nrf_radio_signal_callback_return_param_t * (*nrf_radio_signal_callback_t) (uint8_t signal_type);
+
+/**@brief AES ECB parameter typedefs */
+typedef uint8_t soc_ecb_key_t[SOC_ECB_KEY_LENGTH];
+typedef uint8_t soc_ecb_cleartext_t[SOC_ECB_CLEARTEXT_LENGTH];
+typedef uint8_t soc_ecb_ciphertext_t[SOC_ECB_CIPHERTEXT_LENGTH];
+
+/**@brief AES ECB data structure */
+typedef struct
+{
+  soc_ecb_key_t        key;            /**< Encryption key. */
+  soc_ecb_cleartext_t  cleartext;      /**< Cleartext data. */
+  soc_ecb_ciphertext_t ciphertext;     /**< Ciphertext data. */
+} nrf_ecb_hal_data_t;
+
+/**@brief AES ECB block. Used to provide multiple blocks in a single call
+          to @ref sd_ecb_blocks_encrypt.*/
+typedef struct
+{
+  soc_ecb_key_t*        p_key;           /**< Pointer to the Encryption key. */
+  soc_ecb_cleartext_t*  p_cleartext;     /**< Pointer to the Cleartext data. */
+  soc_ecb_ciphertext_t* p_ciphertext;    /**< Pointer to the Ciphertext data. */
+} nrf_ecb_hal_data_block_t;
+
+/**@} */
+
+/**@addtogroup NRF_SOC_FUNCTIONS Functions
+ * @{ */
+
+/**@brief Initialize a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to initialize.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_MUTEX_NEW, uint32_t, sd_mutex_new(nrf_mutex_t * p_mutex));
+
+/**@brief Attempt to acquire a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to acquire.
+ *
+ * @retval ::NRF_SUCCESS The mutex was successfully acquired.
+ * @retval ::NRF_ERROR_SOC_MUTEX_ALREADY_TAKEN The mutex could not be acquired.
+ */
+SVCALL(SD_MUTEX_ACQUIRE, uint32_t, sd_mutex_acquire(nrf_mutex_t * p_mutex));
+
+/**@brief Release a mutex.
+ *
+ * @param[in] p_mutex Pointer to the mutex to release.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_MUTEX_RELEASE, uint32_t, sd_mutex_release(nrf_mutex_t * p_mutex));
+
+/**@brief Query the capacity of the application random pool.
+ *
+ * @param[out] p_pool_capacity The capacity of the pool.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RAND_APPLICATION_POOL_CAPACITY_GET, uint32_t, sd_rand_application_pool_capacity_get(uint8_t * p_pool_capacity));
+
+/**@brief Get number of random bytes available to the application.
+ *
+ * @param[out] p_bytes_available The number of bytes currently available in the pool.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RAND_APPLICATION_BYTES_AVAILABLE_GET, uint32_t, sd_rand_application_bytes_available_get(uint8_t * p_bytes_available));
+
+/**@brief Get random bytes from the application pool.
+ *
+ * @param[out]  p_buff  Pointer to unit8_t buffer for storing the bytes.
+ * @param[in]   length  Number of bytes to take from pool and place in p_buff.
+ *
+ * @retval ::NRF_SUCCESS The requested bytes were written to p_buff.
+ * @retval ::NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES No bytes were written to the buffer, because there were not enough bytes available.
+*/
+SVCALL(SD_RAND_APPLICATION_VECTOR_GET, uint32_t, sd_rand_application_vector_get(uint8_t * p_buff, uint8_t length));
+
+/**@brief Gets the reset reason register. 
+ *
+ * @param[out]  p_reset_reason  Contents of the NRF_POWER->RESETREAS register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RESET_REASON_GET, uint32_t, sd_power_reset_reason_get(uint32_t * p_reset_reason));
+
+/**@brief Clears the bits of the reset reason register. 
+ *
+ * @param[in] reset_reason_clr_msk Contains the bits to clear from the reset reason register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RESET_REASON_CLR, uint32_t, sd_power_reset_reason_clr(uint32_t reset_reason_clr_msk));
+
+/**@brief Sets the power mode when in CPU sleep.
+ *
+ * @param[in] power_mode The power mode to use when in CPU sleep, see @ref NRF_POWER_MODES. @sa sd_app_evt_wait
+ *
+ * @retval ::NRF_SUCCESS The power mode was set.
+ * @retval ::NRF_ERROR_SOC_POWER_MODE_UNKNOWN The power mode was unknown.
+ */
+SVCALL(SD_POWER_MODE_SET, uint32_t, sd_power_mode_set(uint8_t power_mode));
+
+/**@brief Puts the chip in System OFF mode. 
+ *
+ * @retval ::NRF_ERROR_SOC_POWER_OFF_SHOULD_NOT_RETURN
+ */
+SVCALL(SD_POWER_SYSTEM_OFF, uint32_t, sd_power_system_off(void));
+
+/**@brief Enables or disables the power-fail comparator.
+ *
+ * Enabling this will give a softdevice event (NRF_EVT_POWER_FAILURE_WARNING) when the power failure warning occurs.
+ * The event can be retrieved with sd_evt_get();
+ *
+ * @param[in] pof_enable    True if the power-fail comparator should be enabled, false if it should be disabled.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_POF_ENABLE, uint32_t, sd_power_pof_enable(uint8_t pof_enable));
+
+/**@brief Sets the power-fail threshold value.
+ *
+ * @param[in] threshold The power-fail threshold value to use, see @ref NRF_POWER_THRESHOLDS.
+ *
+ * @retval ::NRF_SUCCESS The power failure threshold was set.
+ * @retval ::NRF_ERROR_SOC_POWER_POF_THRESHOLD_UNKNOWN The power failure threshold is unknown.
+ */
+SVCALL(SD_POWER_POF_THRESHOLD_SET, uint32_t, sd_power_pof_threshold_set(uint8_t threshold));
+
+/**@brief Sets bits in the NRF_POWER->RAMON register.
+ *
+ * @param[in] ramon Contains the bits needed to be set in the NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_SET, uint32_t, sd_power_ramon_set(uint32_t ramon));
+
+/**@brief Clears bits in the NRF_POWER->RAMON register.
+ *
+ * @param ramon Contains the bits needed to be cleared in the NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_CLR, uint32_t, sd_power_ramon_clr(uint32_t ramon));
+
+/**@brief Get contents of NRF_POWER->RAMON register, indicates power status of ram blocks.
+ *
+ * @param[out] p_ramon Content of NRF_POWER->RAMON register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_RAMON_GET, uint32_t, sd_power_ramon_get(uint32_t * p_ramon));
+
+/**@brief Set bits in the NRF_POWER->GPREGRET register.
+ *
+ * @param[in] gpregret_msk Bits to be set in the GPREGRET register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_SET, uint32_t, sd_power_gpregret_set(uint32_t gpregret_msk));
+
+/**@brief Clear bits in the NRF_POWER->GPREGRET register.
+ *
+ * @param[in] gpregret_msk Bits to be clear in the GPREGRET register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_CLR, uint32_t, sd_power_gpregret_clr(uint32_t gpregret_msk));
+
+/**@brief Get contents of the NRF_POWER->GPREGRET register.
+ *
+ * @param[out] p_gpregret Contents of the GPREGRET register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_POWER_GPREGRET_GET, uint32_t, sd_power_gpregret_get(uint32_t *p_gpregret));
+
+/**@brief Sets the DCDC mode.
+ *
+ * Enable or disable the DCDC peripheral.
+ *
+ * @param[in] dcdc_mode The mode of the DCDC, see @ref NRF_POWER_DCDC_MODES.
+ *
+ * @retval ::NRF_SUCCESS
+ * @retval ::NRF_ERROR_INVALID_PARAM The DCDC mode is invalid.
+ */
+SVCALL(SD_POWER_DCDC_MODE_SET, uint32_t, sd_power_dcdc_mode_set(uint8_t dcdc_mode));
+
+/**@brief Request the high frequency crystal oscillator.
+ *
+ * Will start the high frequency crystal oscillator, the startup time of the crystal varies
+ * and the ::sd_clock_hfclk_is_running function can be polled to check if it has started.
+ *
+ * @see sd_clock_hfclk_is_running
+ * @see sd_clock_hfclk_release
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_REQUEST, uint32_t, sd_clock_hfclk_request(void));
+
+/**@brief Releases the high frequency crystal oscillator.
+ *
+ * Will stop the high frequency crystal oscillator, this happens immediately.
+ *
+ * @see sd_clock_hfclk_is_running
+ * @see sd_clock_hfclk_request
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_RELEASE, uint32_t, sd_clock_hfclk_release(void));
+
+/**@brief Checks if the high frequency crystal oscillator is running.
+ *
+ * @see sd_clock_hfclk_request
+ * @see sd_clock_hfclk_release
+ *
+ * @param[out] p_is_running 1 if the external crystal oscillator is running, 0 if not.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_CLOCK_HFCLK_IS_RUNNING, uint32_t, sd_clock_hfclk_is_running(uint32_t * p_is_running));
+
+/**@brief Waits for an application event.
+ * 
+ * An application event is either an application interrupt or a pended interrupt when the
+ * interrupt is disabled. When the interrupt is enabled it will be taken immediately since
+ * this function will wait in thread mode, then the execution will return in the application's
+ * main thread. When an interrupt is disabled and gets pended it will return to the application's 
+ * thread main. The application must ensure that the pended flag is cleared using 
+ * ::sd_nvic_ClearPendingIRQ in order to sleep using this function. This is only necessary for
+ * disabled interrupts, as the interrupt handler will clear the pending flag automatically for
+ * enabled interrupts.
+ *
+ * In order to wake up from disabled interrupts, the SEVONPEND flag has to be set in the Cortex-M0
+ * System Control Register (SCR). @sa CMSIS_SCB
+ *
+ * @note If an application interrupt has happened since the last time sd_app_evt_wait was
+ *       called this function will return immediately and not go to sleep. This is to avoid race
+ *       conditions that can occur when a flag is updated in the interrupt handler and processed
+ *       in the main loop.
+ *
+ * @post An application interrupt has happened or a interrupt pending flag is set.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_APP_EVT_WAIT, uint32_t, sd_app_evt_wait(void));
+
+/**@brief Get PPI channel enable register contents.
+ *
+ * @param[out] p_channel_enable The contents of the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_GET, uint32_t, sd_ppi_channel_enable_get(uint32_t * p_channel_enable));
+
+/**@brief Set PPI channel enable register.
+ *
+ * @param[in] channel_enable_set_msk Mask containing the bits to set in the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_SET, uint32_t, sd_ppi_channel_enable_set(uint32_t channel_enable_set_msk));
+
+/**@brief Clear PPI channel enable register.
+ *
+ * @param[in] channel_enable_clr_msk Mask containing the bits to clear in the PPI CHEN register.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ENABLE_CLR, uint32_t, sd_ppi_channel_enable_clr(uint32_t channel_enable_clr_msk));
+
+/**@brief Assign endpoints to a PPI channel.
+ *
+ * @param[in] channel_num Number of the PPI channel to assign.
+ * @param[in] evt_endpoint Event endpoint of the PPI channel.
+ * @param[in] task_endpoint Task endpoint of the PPI channel.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_CHANNEL The channel number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_CHANNEL_ASSIGN, uint32_t, sd_ppi_channel_assign(uint8_t channel_num, const volatile void * evt_endpoint, const volatile void * task_endpoint));
+
+/**@brief Task to enable a channel group.
+ *
+ * @param[in] group_num Number of the channel group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_TASK_ENABLE, uint32_t, sd_ppi_group_task_enable(uint8_t group_num));
+
+/**@brief Task to disable a channel group.
+ *
+ * @param[in] group_num Number of the PPI group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_TASK_DISABLE, uint32_t, sd_ppi_group_task_disable(uint8_t group_num));
+
+/**@brief Assign PPI channels to a channel group.
+ *
+ * @param[in] group_num Number of the channel group.
+ * @param[in] channel_msk Mask of the channels to assign to the group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_ASSIGN, uint32_t, sd_ppi_group_assign(uint8_t group_num, uint32_t channel_msk));
+
+/**@brief Gets the PPI channels of a channel group.
+ *
+ * @param[in]   group_num Number of the channel group.
+ * @param[out]  p_channel_msk Mask of the channels assigned to the group.
+ *
+ * @retval ::NRF_ERROR_SOC_PPI_INVALID_GROUP The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_PPI_GROUP_GET, uint32_t, sd_ppi_group_get(uint8_t group_num, uint32_t * p_channel_msk));
+
+/**@brief Configures the Radio Notification signal.
+ *
+ * @note
+ *      - The notification signal latency depends on the interrupt priority settings of SWI used
+ *        for notification signal.
+ *      - To ensure that the radio notification signal behaves in a consistent way, always 
+ *        configure radio notifications when there is no protocol stack or other SoftDevice 
+ *        activity in progress. It is recommended that the radio notification signal is 
+ *        configured directly after the SoftDevice has been enabled.
+ *      - In the period between the ACTIVE signal and the start of the Radio Event, the SoftDevice
+ *        will interrupt the application to do Radio Event preparation.
+ *      - Using the Radio Notification feature may limit the bandwidth, as the SoftDevice may have
+ *        to shorten the connection events to have time for the Radio Notification signals.
+ *
+ * @param[in]  type      Type of notification signal, see @ref NRF_RADIO_NOTIFICATION_TYPES.
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE shall be used to turn off radio
+ *                       notification. Using @ref NRF_RADIO_NOTIFICATION_DISTANCE_NONE is
+ *                       recommended (but not required) to be used with
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_NONE.
+ *
+ * @param[in]  distance  Distance between the notification signal and start of radio activity, see @ref NRF_RADIO_NOTIFICATION_DISTANCES.
+ *                       This parameter is ignored when @ref NRF_RADIO_NOTIFICATION_TYPE_NONE or 
+ *                       @ref NRF_RADIO_NOTIFICATION_TYPE_INT_ON_INACTIVE is used. 
+ *
+ * @retval ::NRF_ERROR_INVALID_PARAM The group number is invalid.
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_RADIO_NOTIFICATION_CFG_SET, uint32_t, sd_radio_notification_cfg_set(uint8_t type, uint8_t distance));
+
+/**@brief Encrypts a block according to the specified parameters.
+ *
+ * 128-bit AES encryption.
+ *
+ * @note:
+ *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
+ *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
+ *      main or low interrupt level.
+ *
+ * @param[in, out] p_ecb_data Pointer to the ECB parameters' struct (two input
+ *                            parameters and one output parameter).
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_ECB_BLOCK_ENCRYPT, uint32_t, sd_ecb_block_encrypt(nrf_ecb_hal_data_t * p_ecb_data));
+
+/**@brief Encrypts multiple data blocks provided as an array of data block structures.
+ *
+ * @details: Performs 128-bit AES encryption on multiple data blocks
+ *
+ * @note:
+ *    - The application may set the SEVONPEND bit in the SCR to 1 to make the SoftDevice sleep while
+ *      the ECB is running. The SEVONPEND bit should only be cleared (set to 0) from application
+ *      main or low interrupt level.
+ *
+ * @param[in]     block_count     Count of blocks in the p_data_blocks array.
+ * @param[in,out] p_data_blocks   Pointer to the first entry in a contiguous array of
+ *                                @ref nrf_ecb_hal_data_block_t structures.
+ *
+ * @retval ::NRF_SUCCESS
+ */
+SVCALL(SD_ECB_BLOCKS_ENCRYPT, uint32_t, sd_ecb_blocks_encrypt(uint8_t block_count, nrf_ecb_hal_data_block_t * p_data_blocks));
+
+/**@brief Gets any pending events generated by the SoC API.
+ *
+ * The application should keep calling this function to get events, until ::NRF_ERROR_NOT_FOUND is returned.
+ *
+ * @param[out] p_evt_id Set to one of the values in @ref NRF_SOC_EVTS, if any events are pending.
+ *
+ * @retval ::NRF_SUCCESS An event was pending. The event id is written in the p_evt_id parameter.
+ * @retval ::NRF_ERROR_NOT_FOUND No pending events. 
+ */
+SVCALL(SD_EVT_GET, uint32_t, sd_evt_get(uint32_t * p_evt_id));
+
+/**@brief Get the temperature measured on the chip
+ * 
+ * This function will block until the temperature measurement is done.
+ * It takes around 50us from call to return.
+ *
+ * @param[out] p_temp Result of temperature measurement. Die temperature in 0.25 degrees celsius.
+ *
+ * @retval ::NRF_SUCCESS A temperature measurement was done, and the temperature was written to temp
+ */
+SVCALL(SD_TEMP_GET, uint32_t, sd_temp_get(int32_t * p_temp));
+
+/**@brief Flash Write
+*
+* Commands to write a buffer to flash
+*
+* If the SoftDevice is enabled:
+*  This call initiates the flash access command, and its completion will be communicated to the
+*  application with exactly one of the following events:
+*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
+*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
+*
+* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the 
+ * write has been completed
+*
+* @note
+*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
+*        they will not interfere with the flash access. This means that all interrupts will be blocked
+*        for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
+*        and the command parameters).
+*
+*
+* @param[in]  p_dst Pointer to start of flash location to be written.
+* @param[in]  p_src Pointer to buffer with data to be written.
+* @param[in]  size  Number of 32-bit words to write. Maximum size is 256 32-bit words for nRF51 and 1024 for nRF52.
+*
+* @retval ::NRF_ERROR_INVALID_ADDR   Tried to write to a non existing flash address, or p_dst or p_src was unaligned.
+* @retval ::NRF_ERROR_BUSY           The previous command has not yet completed.
+* @retval ::NRF_ERROR_INVALID_LENGTH Size was 0, or higher than the maximum allowed size.
+* @retval ::NRF_ERROR_FORBIDDEN      Tried to write to or read from protected location.
+* @retval ::NRF_SUCCESS              The command was accepted.
+*/
+SVCALL(SD_FLASH_WRITE, uint32_t, sd_flash_write(uint32_t * const p_dst, uint32_t const * const p_src, uint32_t size));
+
+
+/**@brief Flash Erase page
+*
+* Commands to erase a flash page
+* If the SoftDevice is enabled:
+*  This call initiates the flash access command, and its completion will be communicated to the
+*  application with exactly one of the following events:
+*      - @ref NRF_EVT_FLASH_OPERATION_SUCCESS - The command was successfully completed.
+*      - @ref NRF_EVT_FLASH_OPERATION_ERROR   - The command could not be started.
+*
+* If the SoftDevice is not enabled no event will be generated, and this call will return @ref NRF_SUCCESS when the 
+* erase has been completed
+*
+* @note
+*      - This call takes control over the radio and the CPU during flash erase and write to make sure that
+*        they will not interfere with the flash access. This means that all interrupts will be blocked
+*        for a predictable time (depending on the NVMC specification in nRF51 Series Reference Manual
+*        and the command parameters).
+*
+*
+* @param[in]  page_number Pagenumber of the page to erase
+* @retval ::NRF_ERROR_INTERNAL      If a new session could not be opened due to an internal error.
+* @retval ::NRF_ERROR_INVALID_ADDR  Tried to erase to a non existing flash page.
+* @retval ::NRF_ERROR_BUSY          The previous command has not yet completed.
+* @retval ::NRF_ERROR_FORBIDDEN     Tried to erase a protected page.
+* @retval ::NRF_SUCCESS             The command was accepted.
+*/
+SVCALL(SD_FLASH_PAGE_ERASE, uint32_t, sd_flash_page_erase(uint32_t page_number));
+
+
+/**@brief Flash Protection set
+ *
+ * Commands to set the flash protection configuration registers.
+   On nRF51 this sets the PROTENSETx registers of the MPU peripheral.
+   On nRF52 this sets the CONFIGx registers of the BPROT peripheral.
+ *
+ * @note To read the values read them directly. They are only write-protected.
+ *
+ * @param[in]  block_cfg0 Value to be written to the configuration register.
+ * @param[in]  block_cfg1 Value to be written to the configuration register.
+ * @param[in]  block_cfg2 Value to be written to the configuration register (ignored on nRF51).
+ * @param[in]  block_cfg3 Value to be written to the configuration register (ignored on nRF51).
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN Tried to protect the SoftDevice.
+ * @retval ::NRF_SUCCESS Values successfully written to configuration registers.
+ */
+SVCALL(SD_FLASH_PROTECT, uint32_t, sd_flash_protect(uint32_t block_cfg0, uint32_t block_cfg1, uint32_t block_cfg2, uint32_t block_cfg3));
+
+/**@brief Opens a session for radio timeslot requests.
+ *
+ * @note Only one session can be open at a time.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) will be called when the radio timeslot
+ *       starts. From this point the NRF_RADIO and NRF_TIMER0 peripherals can be freely accessed
+ *       by the application.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_TIMER0) is called whenever the NRF_TIMER0
+ *       interrupt occurs.
+ * @note p_radio_signal_callback(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_RADIO) is called whenever the NRF_RADIO
+ *       interrupt occurs.
+ * @note p_radio_signal_callback() will be called at ARM interrupt priority level 0. This
+ *       implies that none of the sd_* API calls can be used from p_radio_signal_callback().
+ *
+ * @param[in] p_radio_signal_callback The signal callback.
+ *
+ * @retval ::NRF_ERROR_INVALID_ADDR p_radio_signal_callback is an invalid function pointer.
+ * @retval ::NRF_ERROR_BUSY If session cannot be opened.
+ * @retval ::NRF_ERROR_INTERNAL If a new session could not be opened due to an internal error.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_SESSION_OPEN, uint32_t, sd_radio_session_open(nrf_radio_signal_callback_t p_radio_signal_callback));
+
+/**@brief Closes a session for radio timeslot requests.
+ *
+ * @note Any current radio timeslot will be finished before the session is closed.
+ * @note If a radio timeslot is scheduled when the session is closed, it will be canceled.
+ * @note The application cannot consider the session closed until the @ref NRF_EVT_RADIO_SESSION_CLOSED
+ *       event is received.
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN If session not opened.
+ * @retval ::NRF_ERROR_BUSY If session is currently being closed.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_SESSION_CLOSE, uint32_t, sd_radio_session_close(void));
+
+/**@brief Requests a radio timeslot.
+ *
+ * @note The request type is determined by p_request->request_type, and can be one of @ref NRF_RADIO_REQ_TYPE_EARLIEST
+ *       and @ref NRF_RADIO_REQ_TYPE_NORMAL. The first request in a session must always be of type @ref NRF_RADIO_REQ_TYPE_EARLIEST.
+ * @note For a normal request (@ref NRF_RADIO_REQ_TYPE_NORMAL), the start time of a radio timeslot is specified by
+ *       p_request->distance_us and is given relative to the start of the previous timeslot. 
+ * @note A too small p_request->distance_us will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
+ * @note Timeslots scheduled too close will lead to a @ref NRF_EVT_RADIO_BLOCKED event.
+ * @note See the SoftDevice Specification for more on radio timeslot scheduling, distances and lengths.
+ * @note If an opportunity for the first radio timeslot is not found before 100ms after the call to this
+ *       function, it is not scheduled, and instead a @ref NRF_EVT_RADIO_BLOCKED event is sent.
+ *       The application may then try to schedule the first radio timeslot again.
+ * @note Successful requests will result in nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START).
+ *       Unsuccessful requests will result in a @ref NRF_EVT_RADIO_BLOCKED event, see @ref NRF_SOC_EVTS.
+ * @note The jitter in the start time of the radio timeslots is +/- @ref NRF_RADIO_START_JITTER_US us.
+ * @note The nrf_radio_signal_callback_t(@ref NRF_RADIO_CALLBACK_SIGNAL_TYPE_START) call has a latency relative to the
+ *       specified radio timeslot start, but this does not affect the actual start time of the timeslot.
+ * @note NRF_TIMER0 is reset at the start of the radio timeslot, and is clocked at 1MHz from the high frequency
+ *       (16 MHz) clock source. If p_request->hfclk_force_xtal is true, the high frequency clock is 
+ *       guaranteed to be clocked from the external crystal.
+ * @note The SoftDevice will neither access the NRF_RADIO peripheral nor the NRF_TIMER0 peripheral
+ *       during the radio timeslot.
+ *
+ * @param[in] p_request Pointer to the request parameters.
+ *
+ * @retval ::NRF_ERROR_FORBIDDEN If session not opened or the session is not IDLE.
+ * @retval ::NRF_ERROR_INVALID_ADDR If the p_request pointer is invalid.
+ * @retval ::NRF_ERROR_INVALID_PARAM If the parameters of p_request are not valid.
+ * @retval ::NRF_SUCCESS Otherwise.
+ */
+ SVCALL(SD_RADIO_REQUEST, uint32_t, sd_radio_request(nrf_radio_request_t * p_request ));
+
+/**@} */
+
+#ifdef __cplusplus
+}
+#endif
+#endif // NRF_SOC_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_svc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_svc.h
new file mode 100644
index 0000000000..aa91e5d35e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/headers/nrf_svc.h
@@ -0,0 +1,91 @@
+/* 
+ * Copyright (c) 2000 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_SVC__
+#define NRF_SVC__
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#ifdef SVCALL_AS_NORMAL_FUNCTION
+#define SVCALL(number, return_type, signature) return_type signature
+#else
+
+#ifndef SVCALL
+#if defined (__CC_ARM)
+#define SVCALL(number, return_type, signature) return_type __svc(number) signature
+#elif defined (__GNUC__)
+#ifdef __cplusplus
+#define GCC_CAST_CPP (uint16_t)
+#else
+#define GCC_CAST_CPP
+#endif
+#define SVCALL(number, return_type, signature)          \
+  _Pragma("GCC diagnostic push")                        \
+  _Pragma("GCC diagnostic ignored \"-Wreturn-type\"")   \
+  __attribute__((naked))                                \
+  __attribute__((unused))                               \
+  static return_type signature                          \
+  {                                                     \
+    __asm(                                              \
+        "svc %0\n"                                      \
+        "bx r14" : : "I" (GCC_CAST_CPP number) : "r0"   \
+    );                                                  \
+  }                                                     \
+  _Pragma("GCC diagnostic pop")
+
+#elif defined (__ICCARM__)
+#define PRAGMA(x) _Pragma(#x)
+#define SVCALL(number, return_type, signature)          \
+PRAGMA(swi_number = (number))                           \
+ __swi return_type signature;
+#else
+#define SVCALL(number, return_type, signature) return_type signature
+#endif
+#endif  // SVCALL
+
+#endif  // SVCALL_AS_NORMAL_FUNCTION
+
+#ifdef __cplusplus
+}
+#endif
+#endif  // NRF_SVC__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/hex/s132_nrf52_2.0.0_softdevice.hex b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/hex/s132_nrf52_2.0.0_softdevice.hex
new file mode 100644
index 0000000000..a61b7c914c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/softdevice/s132/hex/s132_nrf52_2.0.0_softdevice.hex
@@ -0,0 +1,6918 @@
+:020000040000FA
+:1000000000040020E508000079050000C508000094
+:10001000830500008D05000097050000000000002A
+:1000200000000000000000000000000009090000BE
+:10003000A105000000000000AB050000B5050000B0
+:10004000BF050000C9050000D3050000DD05000064
+:10005000E7050000F1050000FB05000005060000B3
+:100060000F06000019060000230600002D06000000
+:1000700037060000410600004B0600005506000050
+:100080005F06000069060000730600007D060000A0
+:1000900087060000910600009B060000A5060000F0
+:1000A000AF060000B9060000C3060000CD06000040
+:1000B000D7060000E1060000EB060000F506000090
+:1000C000FF06000009070000130700001D070000DD
+:1000D00027070000310700003B070000450700002C
+:1000E0004F07000059070000630700006D0700007C
+:1000F00077070000810700008B07000095070000CC
+:100100009F0700001FB500F003F88DE80F001FBD2A
+:1001100000F0DEBB1FB56FF00100009040100390AF
+:10012000029001904FF010208069000B420900F00E
+:100130001F045DF822300120A04083434DF8223097
+:10014000684600F044F91FBDF0B54FF6FF734FF459
+:10015000B4751A466E1E11E0A94201D3344600E080
+:100160000C46091B30F8027B641E3B441A44F9D14B
+:100170009CB204EB134394B204EB12420029EBD17E
+:1001800098B200EB134002EB124140EA0140F0BD8F
+:10019000DD4992B00446D1E90001CDE91001FF220A
+:1001A0004021684600F03AFB94E80F008DE80F000C
+:1001B000684610A902E004C841F8042D8842FAD12B
+:1001C00010216846FFF7C0FF1090AA208DF8440068
+:1001D000FFF7A0FF00F0F2F84FF01024A069102202
+:1001E0006946803000F001F9A069082210A900F0EA
+:1001F000FCF800F0D7F84FF080510A6949690068AF
+:100200004A43824201D8102070470020704710B541
+:10021000D0E900214FF0805002EB8103026944696C
+:100220006243934209D84FF01022536903EB8103D4
+:100230000169406941438B4201D9092010BD5069D1
+:10024000401C01D0002010BD0F2010BD70B501680A
+:100250000446AE4D4FF01020062951D2DFE801F0E0
+:10026000320318283B1DD4E90265646829463046EC
+:1002700000F0CDF82A462146304600F0B6F8AA0034
+:100280002146304600F09EFA002800D0032070BDC1
+:1002900000F050FB4FF4805007E0201DFFF7ABFF4C
+:1002A0000028F4D100F046FB60682860002070BD93
+:1002B000241D94E80700920000F084FA0028F6D08C
+:1002C0000E2070BD8069401C12D0201DFFF79FFFDB
+:1002D0000028F6D109E08069401C09D0201DFFF7F5
+:1002E0008AFF0028EDD1606820B12046FFF750FF5B
+:1002F000042070BDFFF70EFF00F060F800F052F828
+:10030000072070BD10B50C46182802D001200860E7
+:1003100010BD2068FFF79AFF206010BD4FF0102439
+:10032000A069401C05D0A569A66980353079AA2846
+:1003300008D06069401C2DD060690068401C29D03D
+:1003400060692CE010212846FFF7FEFE31688142EB
+:100350001CD1A16901F18002C03105E030B108CAA9
+:1003600051F8040D984201D1012000E000208A429A
+:10037000F4D158B1286810B1042803D0FEE728460C
+:1003800000F057F861496868086008E000F016F866
+:1003900000F008F84FF480500168491C01D000F0CB
+:1003A000A3FAFEE7BFF34F8F59480168594A01F499
+:1003B000E06111430160BFF34F8FFEE74FF0102063
+:1003C0008169491C02D0806900F0ADB87047524A7B
+:1003D00001681160121D416811604F4A8168103236
+:1003E0001160111DC068086070472DE9F041174683
+:1003F0000D460646002406E03046296800F0A6F8BF
+:10040000641C2D1D361DBC42F6D3BDE8F08170B5CD
+:100410000C4605464FF4806608E0284600F083F855
+:10042000B44205D3A4F5806405F58055002CF4D1C1
+:1004300070BD4168044609B1012500E000254FF078
+:1004400010267069A268920000F0BCF9C8B120467D
+:1004500000F01AF89DB17669A56864684FF4002031
+:1004600084420AD2854208D229463046FFF7CFFFA0
+:100470002A4621463046FFF7B8FFFFF79FFFFFF7F8
+:1004800091FFFFF747FEF8E72DE9FF414FF01024F9
+:10049000616980680D0B01EB800000F6FF70010BB5
+:1004A00000200090019002900246039068460123CC
+:1004B0000BE0560902F01F0C50F8267003FA0CFCF2
+:1004C00047EA0C0740F82670521CAA42F1D30AE012
+:1004D0004A0901F01F0650F8225003FA06F6354388
+:1004E00040F82250491C8029F2D3A169090B4A091E
+:1004F00001F01F0150F822408B409C4340F82240FD
+:10050000FFF765FFBDE8FF815809000000000020EB
+:100510000CED00E00400FA050006004014480168F4
+:100520000029FCD07047134A0221116010490B6862
+:10053000002BFCD00F4B1B1D186008680028FCD056
+:100540000020106008680028FCD07047094B10B5E7
+:1005500001221A60064A1468002CFCD00160106861
+:100560000028FCD00020186010680028FCD010BDC6
+:1005700000E4014004E5014008208F49096809585A
+:10058000084710208C4909680958084714208A49EF
+:100590000968095808471820874909680958084711
+:1005A0003020854909680958084738208249096878
+:1005B000095808473C2080490968095808474020E5
+:1005C0007D4909680958084744207B49096809584A
+:1005D0000847482078490968095808474C20764957
+:1005E000096809580847502073490968095808479D
+:1005F0005420714909680958084758206E4909680C
+:10060000095808475C206C49096809580847602068
+:100610006949096809580847642067490968095801
+:100620000847682064490968095808476C206249EE
+:1006300009680958084770205F4909680958084740
+:1006400074205D4909680958084778205A490968A3
+:10065000095808477C2058490968095808478020EC
+:1006600055490968095808478420534909680958B9
+:100670000847882050490968095808478C204E4986
+:1006800009680958084790204B49096809580847E4
+:10069000942049490968095808479820464909683B
+:1006A000095808479C204449096809580847A02070
+:1006B0004149096809580847A4203F490968095871
+:1006C0000847A8203C49096809580847AC203A491E
+:1006D000096809580847B020374909680958084788
+:1006E000B4203549096809580847B82032490968D3
+:1006F00009580847BC203049096809580847C020F4
+:100700002D49096809580847C4202B490968095828
+:100710000847C8202849096809580847CC202649B5
+:10072000096809580847D02023490968095808472B
+:10073000D4202149096809580847D8201E4909686A
+:1007400009580847DC201C49096809580847E02077
+:100750001949096809580847E420174909680958E0
+:100760000847E8201449096809580847EC2012494D
+:10077000096809580847F0200F49096809580847CF
+:10078000F4200D49096809580847F8200A49096802
+:1007900009580847FC2008490968095808475FF4C8
+:1007A0008070054909680958084700000348044952
+:1007B000024A034B70470000000000206809000057
+:1007C0006809000040EA010310B59B070FD1042A15
+:1007D0000DD310C808C9121F9C42F8D020BA19BA0C
+:1007E000884201D9012010BD4FF0FF3010BD1AB171
+:1007F000D30703D0521C07E0002010BD10F8013BC6
+:1008000011F8014B1B1B07D110F8013B11F8014BEC
+:100810001B1B01D1921EF1D1184610BD02F0FF033F
+:1008200043EA032242EA024200F005B870477047EB
+:1008300070474FF000020429C0F0128010F0030C42
+:1008400000F01B80CCF1040CBCF1020F18BF00F8C3
+:10085000012BA8BF20F8022BA1EB0C0100F00DB872
+:100860005FEAC17C24BF00F8012B00F8012B48BFD0
+:1008700000F8012B70474FF0000200B51346944674
+:100880009646203922BFA0E80C50A0E80C50B1F1E8
+:100890002001BFF4F7AF090728BFA0E80C5048BFFC
+:1008A0000CC05DF804EB890028BF40F8042B08BF9A
+:1008B000704748BF20F8022B11F0804F18BF00F896
+:1008C000012B7047014B1B68DB68184700000020B4
+:1008D00009480A497047FFF7FBFFFFF713FC00BD0B
+:1008E00020BFFDE7064B1847064A1060016881F3F8
+:1008F0000888406800470000680900006809000097
+:100900001D030000000000201EF0040F0CBFEFF3D9
+:100910000881EFF30981886902380078182803D12B
+:1009200000E00000074A1047074A12682C3212689C
+:100930001047000000B5054B1B68054A9B589847B7
+:1009400000BD000005030000000000205409000065
+:1009500004000000001000000000000000FFFFFF86
+:040960000090D00330
+:10100000881100207DB0010079960000CDAF01006D
+:1010100079960000799600007996000000000000A3
+:10102000000000000000000000000000D9B0010036
+:101030007996000000000000799600007996000083
+:1010400041B1010047B10100799600007996000096
+:101050007996000079960000799600007996000054
+:101060004DB10100799600007996000053B101005E
+:101070007996000059B101005FB1010065B101002E
+:101080007996000079960000799600007996000024
+:101090007996000079960000799600007996000014
+:1010A0006BB1010071B101007996000079960000E2
+:1010B00079960000799600007996000079960000F4
+:1010C00077B10100799600007996000079960000CA
+:1010D00079960000799600007996000079960000D4
+:1010E00079960000799600007996000079960000C4
+:1010F00079960000799600007996000079960000B4
+:10110000799600007996000000F002F819F093FF3C
+:101110000AA090E8000C82448344AAF10107DA4552
+:1011200001D119F088FFAFF2090EBAE80F0013F0F1
+:10113000010F18BFFB1A43F00103184734A5010043
+:1011400054A501000A4410F8014B14F00F0508BF24
+:1011500010F8015B240908BF10F8014B6D1E05D083
+:1011600010F8013B6D1E01F8013BF9D1641E03D05C
+:10117000641E01F8015BFBD19142E4D3704700008B
+:101180000023002400250026103A28BF78C1FBD890
+:10119000520728BF30C148BF0B6070471FB500F031
+:1011A0003DF88DE80F001FBD1EF0040F0CBFEFF3DC
+:1011B0000880EFF30980014A10470000CB9400003B
+:1011C0008269034981614FF00100104470470000BB
+:1011D000D511000001B41EB400B510F085F901B4BA
+:1011E0000198864601BC01B01EBD0000F0B4404627
+:1011F000494652465B460FB402A0013001B506488D
+:10120000004700BF01BC86460FBC80468946924617
+:101210009B46F0BC704700000911000019F008BFA0
+:1012200070B51C4C054608202070A01C00F065F825
+:101230005920A08029462046BDE8704006F067BBD3
+:1012400010B506F06FFB13490020891E087010BD11
+:1012500070B50C460F49891E097829B1A0F16001CB
+:10126000532906D3012011E0602802D043F2010087
+:101270000CE020CC084E94E80E0006EB8000A0F5B0
+:101280008050241FD0F8806E2846B047206070BD83
+:10129000012070470A000020BCB1010010B50446CF
+:1012A0000021012000F03FF80021182000F03BF859
+:1012B00000210B2000F037F80421192000F033F84A
+:1012C00004210D2000F02FF804210E2000F02BF84F
+:1012D00004210F2000F027F80421C84300F023F870
+:1012E0000721162000F01FF80721152000F01BF839
+:1012F0002046FFF795FF002010BD81210180704737
+:10130000FFF79EBF10487047104A10B514680F4B86
+:101310000F4A08331A60FFF79BFF0C48001D04605A
+:1013200010BD704770474907090E002806DA00F023
+:101330000F0000F1E02080F8141D704700F1E0205C
+:1013400080F800147047000003F9004310050240C4
+:101350000100000130B5FB4D044610280AD0112CC5
+:1013600006D02846122C817806D0132C08D0FFDF37
+:10137000AC7030BDFFDFFBE71129F9D0FFDFF7E7E5
+:101380001129F5D0FFDFF3E770B50EF03CF9044604
+:101390000FF072FE201AC4B206200CF0F9FA0546CE
+:1013A00006200CF0FDFA2E1A07200CF0F1FA054683
+:1013B00007200CF0F5FAE349281A32188878122829
+:1013C0000DD000231A4413280BD0002002440878C3
+:1013D000022808D000201044201AC0B270BD01239A
+:1013E000F0E70120F2E70120F5E7D64810B5C17813
+:1013F00094B0A9B15FF017018DF800104168CDF8E5
+:1014000002100089ADF8060009A968460AF0D1F873
+:101410000446112801D004B1FFDF14B0204610BDEE
+:101420003221E9E702210CF008BB2DE9F04194B02C
+:101430001D4690460E460746FFF7F4FF04000BD00A
+:101440002078222804D3A07FC0F34010A84206D100
+:10145000082014B0BDE8F08143F20200F9E737201C
+:101460008DF80000ADF802703DB101208DF8040048
+:101470008DF805608DF8068002E000208DF80400EC
+:1014800009A968460AF095F8A07F65F34510A07792
+:101490000020DEE730B50446A1F120000D460A2801
+:1014A0004AD2DFE800F005070C1C2328353A3F44F8
+:1014B000FFDF42E0207820283FD1FFDF3DE0A14858
+:1014C0000178032939D08078132836D02078242851
+:1014D00033D0252831D023282FD0FFDF2DE02078EE
+:1014E00022282AD0232828D8FFDF26E020782228A7
+:1014F00023D0FFDF21E0207822281ED024281CD012
+:1015000026281AD0272818D0292816D0FFDF14E063
+:101510002078252811D0FFDF0FE0207825280CD077
+:10152000FFDF0AE02078252807D0FFDF05E02078DC
+:10153000282802D0FFDF00E0FFDF257030BD30B586
+:101540000B8840F67B444FF6FF72022801D093428D
+:1015500004D09D1FA54224D2022802D04D88954276
+:1015600003D04D88AD1FA5421BD24C88A34218D88A
+:101570008B88B3F5FA7F14D2022802D0C888904233
+:1015800005D0C88840F677450A38A84209D2C888ED
+:10159000904208D0944206D05B1C6343B3EB800FAB
+:1015A00001DB072030BD002030BD70B5044610F0CF
+:1015B00003FA60BB207930B1082802D8217B0829C2
+:1015C00005D9072070BD217B0029FAD0F6E718B1B4
+:1015D000206810F0F1F9D0B9207B18B1A06810F0A4
+:1015E000EBF9A0B9002507E0206850F8250010F0BD
+:1015F000E3F960B96D1CEDB22079A842F4D800255A
+:1016000009E0A06850F8250010F0D6F908B11020C4
+:1016100070BD6D1CEDB2207BA842F2D8002070BDD9
+:1016200010B5028943F6FD73111F994212D2418908
+:1016300004290FD3B1F5804F0CD891420AD8017814
+:10164000890705D5406818B1FFF7AFFF002800D122
+:10165000002010BD072010BDF0B50024059D10B17D
+:10166000A94203D851E009B90020F0BD0920F0BD1E
+:10167000055D8DB107197E78112E3FD00FDC0A2E43
+:101680003CD2DFE806F03B1624242A2A2C2C3333E4
+:10169000025D72BB641CE4B28C42F9D3E4E71D2EF8
+:1016A0002CDAA6F11206042E28D2DFE806F027274E
+:1016B0001018022DDAD1BD781D70072D01D26D07EB
+:1016C00001D40A20F0BD157845F0010515E0EE4380
+:1016D000F60707E0012D07D010E00620F0BD2E0729
+:1016E000A6F18056002EF5D06046F0BD1578AE0705
+:1016F00001D50B20F0BD45F002051570055D641C99
+:101700002C44E4B28C4202D9B0E74FF4485C8C42DE
+:10171000AED3A9E710B504784CB1012243F20223FD
+:10172000012C07D0022C0FD0032C17D112E000227D
+:101730000A7015E00A7082790324B4EB921F0DD170
+:101740000EE00000A80100200A708479B2EB941F1B
+:1017500004D105E00A708279920901D0184610BDC3
+:1017600050F8012F41F8012F80888880002010BD9B
+:1017700008B538B1FEA06B4600680090487903EBCD
+:10178000901000781070086842F8010F88889080E7
+:1017900008BD30B50C46097895B0222902D2082040
+:1017A00015B030BD28218DF80010ADF80200132AC5
+:1017B00003D03B2A01D00720F2E78DF8042009A9C5
+:1017C000684609F0F6FE050003D121212046FFF707
+:1017D00061FE2846E4E700B595B023218DF800109E
+:1017E000ADF802001088ADF804005088ADF806008E
+:1017F000D088ADF80A009088ADF808000020ADF858
+:101800000C00ADF80E0009A9684609F0D2FE15B02B
+:1018100000BD70B50E46050003D00021092010F070
+:1018200088F8D44C0120022EE0701CD0032E00D08A
+:10183000FFDF0621201D0FF071FD607A20F0C0004F
+:1018400084F80900FFF7D1FD608A00280AD0002D36
+:1018500008D083000122002109200FF0CDFF0928C4
+:1018600000D0FFDF70BD0321E01D0FF057FD607A4F
+:1018700020F0C00040F040006072E01C02F03BFC31
+:10188000E0E72DE9FF410220BA4E8DF80400002761
+:10189000F08AADF80600B84655E001A80CF037F81C
+:1018A000050006D0F08AB0B3A6F81680ADF8068021
+:1018B00047E0039C2078212843D0A07F01072BD547
+:1018C00004F123000090A28EBDF80800214604F127
+:1018D000360301F02BFD050003D011282AD0FFDFCD
+:1018E00028E0A07F20F00800A077E07F810861F366
+:1018F0000000C10861F34100E07794F8210000F096
+:101900001F0084F820002078282824D1292120468F
+:10191000FFF7C0FD1FE01CE0400712D5BDF808002E
+:10192000214604F10E02FFF756FF050004D01128EE
+:1019300000D0FFDF00250EE0A07F20F00400A0779C
+:1019400009E07F1CFFB202200CF022F8401CB842D4
+:10195000A3D8052D07D0BDF80600F082052D04D0D0
+:10196000284604B076E5A6F816800020F9E72DE9B0
+:10197000F047040000D1FFDF20787E4E20F00F00FA
+:10198000801C20F0F0007030207060680178091F22
+:1019900011290BD2DFE801F0F1090A4FF00A0CF02F
+:1019A000F0360A0A0A0AF174F100FFDFBDE8F08799
+:1019B00087883846FFF736FD050000D1FFDF6078E5
+:1019C000212140F008006070307D40F00400307547
+:1019D0002846FFF75FFD384606F089FD384603F0DC
+:1019E00021FC384604F03BFC394602200FF0A1FFF1
+:1019F000A87F20F01000A877FFF743FF0028D5D07C
+:101A0000FFDFD3E785882846FFF70CFD00B9FFDF2D
+:101A100060688078012800D0FFDF606881792846FF
+:101A200006F0D8FE0028C1D0617841F0080161704D
+:101A30006168C880BAE786883046FFF7F3FC050086
+:101A400000D1FFDF6078314640F0080060706068C8
+:101A5000C088288160680089688160684089A881A1
+:101A600002200FF066FF0020A875A87F00F0030099
+:101A700002289BD1FFF705FF002897D0FFDF95E7ED
+:101A800080783C2803D0002502280AD000E00125F8
+:101A9000002720B13C2802D0022800D0FFDF17B178
+:101AA0007EE00127F5E7607840F008006070307D47
+:101AB00040F008003075EDBB606802218788384629
+:101AC0000BF0B2FF0546032138460BF0ADFF82460E
+:101AD000052138460BF0A8FF8146042138460BF05B
+:101AE000A3FF804605B9FFDFBAF1000F00D1FFDF89
+:101AF000B9F1000F00D1FFDFB8F1000F00D1FFDF17
+:101B000022212846FFF7C6FC60688079012837D07B
+:101B10004FF00208A87F68F30100A8776068C08AC8
+:101B200028816068008B68816068408BA88160684C
+:101B3000C07900E027E0E87560688168A961808964
+:101B4000A8836068807B6870606850F80F1FC5F8D4
+:101B500002108088E880A87F00F00301384606F074
+:101B6000B8FCB8F1010F0ED0B8F1020F18D005E0A3
+:101B70000302FF01A80100201FE023E0FFDF15E7BB
+:101B80004FF00108C6E73078032800D0FFDF0021BE
+:101B900008460FF0CEFEBDE8F047012000F087BFF9
+:101BA000B078132800D0FFDF002107200FF0C1FE1E
+:101BB000BDE8F0471120FFF7CDBB2046BDE8F04758
+:101BC00001F08CBE607840F008006070EEE62DE910
+:101BD000F0470546007800270009DFF894A69146F3
+:101BE0000C463E46012871D0BC464FF6FF710228D4
+:101BF0006DD0072809D00A286AD0FFDFA9F8006055
+:101C00000CB1278066800020D0E6686804F10802E5
+:101C100003780D2B40D006DC042B7DD0072B44D05D
+:101C20000A2B7AD106E0122B46D0132B51D0142B5D
+:101C3000F7D1C0E011270926002C6FD0B0F804803E
+:101C4000A4F804806868807920729AF814104046DD
+:101C500021F004018AF8141004210BF000FF052183
+:101C600040460BF0FCFE002140460BF0F8FE01213F
+:101C700040460BF0F4FE032140460BF0F0FE02213B
+:101C800040460BF0ECFE062140460BF0E8FE072133
+:101C900040460BF0E4FEB1E701270926002CCCD02A
+:101CA0008088A080686880790EE0122710268088DE
+:101CB000214600F01EFFA1E71C270926002CBCD0FE
+:101CC0004088A08068680079207297E78AE0B3E0D6
+:101CD00082E081783C2938D010272026002CACD017
+:101CE0008088A0806868C08A60836868C08A208312
+:101CF0006868008BA0836868408BE0836868417FD8
+:101D0000E07D61F30000E0756968497F490861F38F
+:101D10004700E075696802E022E05CE08BE0C8798A
+:101D20000831FFF725FD696804F10F0201F10F008A
+:101D30008B7B01461846FFF71BFD6868807910B160
+:101D40000120A07507E00220FBE71B270926002CD5
+:101D500071D084F808C09AF8141021F008018CE0C2
+:101D60001D273026002C66D0A1806868411D0079AF
+:101D7000FFF7FEFC686890F82B00E0736868C07895
+:101D80000428207C14D020F00100207469681F22F0
+:101D9000C97861F3420020746968C97A61F3C700A9
+:101DA0002074696804F111000C3119F043F825E73B
+:101DB00040F00100E9E720271026E4B3A18068681D
+:101DC00004F10902407A20726968CB1C88781946B0
+:101DD000FFF7CEFC12E74A4621462846BDE8F04709
+:101DE00001F001BF287E012803D0022813D0FFDFB5
+:101DF00004E71F271026F4B16888A080688B208133
+:101E0000A88B6081E88BA081288CE0819AF814105F
+:101E100021F0200131E012271026688800F069FEC9
+:101E20004CB1687800F007000328C0D19AF814106C
+:101E300021F0020121E027E0287E062822D2DFE8F7
+:101E400000F0040F0F030303C5E71B270926DCB1CD
+:101E5000A18084F808C09AF8141021F001010CE068
+:101E60001B27092684B1A180287E012808D00320E1
+:101E700020729AF8141021F010018AF81410BDE6AF
+:101E80000220F5E7FFDFB9E6A9F80060BBE610B570
+:101E9000F74894B08078132802D0082014B010BD01
+:101EA00022208DF8000009A9684609F082FB04464B
+:101EB000002107200FF03DFD2046EFE700B5EC487C
+:101EC00095B08078122801D00820A0E41E208DF85B
+:101ED000000000208DF802008DF8030009A9684673
+:101EE00009F067FB0028F0D1002107200FF021FD49
+:101EF0001120FFF72FFA002089E400B5DC4895B0E7
+:101F00000078022803D0032801D008207FE41B209A
+:101F10008DF8000000208DF8020009A9684609F03C
+:101F200048FB0028F2D1002108460FF002FD0120F5
+:101F300000F0BDFD00206AE42DE9F0410027CC4C03
+:101F40000A287CD2DFE800F0057B1C7B7B7B7B448E
+:101F50003B6AFFF7D2FF002831D105F01FFC0028B3
+:101F60002DD0017821F00F01891C21F0F0012031E2
+:101F70000170077605F0F0FB207D40F001001DE0C8
+:101F80008EB23046FFF74EFA050000D1FFDF287809
+:101F9000212814D005F002FC98B1017821F00F013E
+:101FA000891C21F0F0011031017002210176468078
+:101FB000AF7505F0D1FB207D40F002002075BDE833
+:101FC000F08129463046BDE8F0411322FFF7E1BB1E
+:101FD000A578122D03D0132D04D0FFDFEFE7FFF714
+:101FE0006DFF01E0FFF753FF0028E8D105F0D6FBB5
+:101FF0000028E4D0017821F00F01891C21F0F001C4
+:1020000020310170122D07D00221017605F0A4FBCA
+:10201000207D40F01000D1E70121F6E7607A012130
+:10202000B1EB901F02D1022104E008E0800900D04A
+:10203000FFDF0321BDE8F0410020FFF7EABBFFDF2F
+:10204000BDE72DE9F04114460D00074600D1FFDF42
+:102050002878012803D0022821D0FFDFAFE73846D7
+:10206000FFF7E0F9060000D1FFDF0220B07520780D
+:1020700020F00F00801C20F0F000103020706078FD
+:1020800040F0080060702868A0616868E0612889F5
+:1020900020847748017D41F0200101758FE73846A3
+:1020A000FFF7C0F9060000D1FFDF69884FF6FF7027
+:1020B000814209D1AA88824206D131463846BDE81C
+:1020C000F0411322FFF765BB814201D1A88898B186
+:1020D000207820F00F00801C20F0F00010302070DD
+:1020E000607840F0080060702868A0616868E0616E
+:1020F00028892084002006E0782300223946022027
+:102100000FF07AFB0120B07559E730B5054695B060
+:102110000C4608460FF050FC78BB00200121203D02
+:10212000062D5FD2DFE805F0032540444A57002121
+:1021300008200FF0D7FB10B1112015B030BD2420BE
+:102140008DF80000D4F80200CDF80200A0798DF8D7
+:10215000060009A9684609F02CFA05002CD10823CD
+:102160000022114618460FF047FB082824D0FFDF55
+:1021700022E060680FF062FC08B11020DDE73C202F
+:102180008DF800002088ADF802006088ADF80400EA
+:1021900009A9684609F00DFA05000DD1606858B12B
+:1021A000BDF82810018007E0206801F0E2FF02E09E
+:1021B000204600F0B1FC05462846BEE73D220BE074
+:1021C0008DF8021002E000BF8DF8020009A96846F0
+:1021D00009F0EFF9EFE734228DF800202278D207DA
+:1021E000F2D0EDE70720A8E730B5054695B00C46DC
+:1021F00008460FF005FC70BB203D052D35D2DFE809
+:1022000005F00323232523002088FFF70BF920B1D5
+:102210000078222804D208208FE743F202008CE7DE
+:1022200025208DF800002088ADF8020009A9684635
+:1022300009F0BFF9002880D1DDF82A10C4F8021097
+:102240009DF82E10A17178E7062076E7206838B156
+:102250000FF0F4FB08B110206FE7206801F07DFF5C
+:102260000348408AA080002067E7072065E7000058
+:10227000A8010020FE487047FD4810B518210A3813
+:1022800018F04FFE012000F012FC1120FFF762F859
+:10229000F74C00200A3C211D60744FF4617060828D
+:1022A000E01C05F043FBD4F80300C4F80A00B4F8BE
+:1022B0000700E081607A2074FFF797F800B1FFDF34
+:1022C00000F09CFCBDE8104001F0C2BA10B50C460D
+:1022D0003E21204618F025FEA07F20F00300A077C5
+:1022E000202020700020A07584F8220010BD7047C7
+:1022F0002DE9FC4105460E4608460FF05DFB10B186
+:102300001020BDE8FC81DA4C0A3C15B1012D38D112
+:102310002CE0D4F803000090B4F80700ADF80400F6
+:102320008046677A8DF80670E11C3046FFF7F2F9B7
+:102330000028E6D1FFF759F830B10099C4F803102E
+:10234000A4F807806772DCE7307808B1012808D16B
+:10235000D4F80300C4F80A00B4F80700E081607AFA
+:102360002074002109200FF0E4FA0FE0317841B128
+:10237000012906D0022906D0032904D043F2022005
+:10238000BFE70720BDE70120FFF743FA657400208F
+:10239000B7E710B504460FF033FB08B1102010BDAD
+:1023A000B34922460A39C878091DFFF7E1F9002030
+:1023B00010BD2DE9F0419AB0054600208DF85C0073
+:1023C0008DF858008DF828008DF860001E461446E0
+:1023D000884628460FF03BFB18B920460FF037FB24
+:1023E00010B110201AB0EAE555EA040018D01F27F2
+:1023F0000AAB17AA414628460097FFF72DF9002897
+:10240000F0D118AB16AA314620460097FFF724F901
+:102410000028E7D19DF85800C00703D00A20E1E763
+:102420000720DFE701AF7DB11A208DF804008DF899
+:10243000068042462946F81C18F0FCFC0BA901A8AE
+:1024400009F0B7F80028CDD17CB120208DF8040028
+:102450008DF8066032462146F81C18F0EBFC0BA9FB
+:1024600001A809F0A6F80028BCD181499DF82800F0
+:102470000A3948700020B5E770B506460A200C46B8
+:10248000087015461146204609F093F830B93821F6
+:1024900021702046294609F08CF820B1082801D186
+:1024A00043F2032070BD2A462146304600F05BFB14
+:1024B0000446082800D1FFDF204670BD2DE9F04119
+:1024C0006CA196B00446D1E90001CDE914010027C2
+:1024D00020460FF071FA30B92078012806D16068E3
+:1024E0000FF06AFA10B1102016B068E5604D0A3D91
+:1024F0002878012801D00820F6E707200BF050FAD1
+:1025000018B9207848B1012807D0FEF73DFF30B157
+:10251000287D10F00C0F09D103E01220E4E713200E
+:10252000E2E7C10702D1A846800701D51120DBE709
+:10253000208A43F6E172A0F120019142217807D36D
+:10254000012942D1002840D1618A00293DD10FE004
+:10255000022901D0032901D1A02836D3012907D0AF
+:1025600098F80110C90703D0618A71B3B4292CD837
+:10257000217831B1012908D0022904D0032924D1BE
+:1025800015E0002516E0022514E008B9608A60B164
+:1025900004256068007868B101280AD0022808D0B4
+:1025A000032806D043F202209EE70125F1E7032528
+:1025B00000E00127207A30B1012807D0022807D097
+:1025C00003286AD106E0002605E066E0012602E065
+:1025D000022600E003260DB1022D13D196B1E0686A
+:1025E00018B1FEF7E2FF002886D198F801008007B5
+:1025F00002D043F2012077E7022D03D1022E4CD006
+:10260000032E4AD018208DF82C00208AADF82E0019
+:10261000208AADF830008DF8325098F80310002071
+:102620004FF0010811B1012968D102E08DF83300A3
+:1026300001E08DF833808DF834702178012925D0A0
+:10264000CDF83500ADF839008DF83C60207DC0F341
+:102650004002014662F35F01C0F3800041EA80005E
+:1026600014A9085C8DF83B00B8B169460BA805E0D9
+:10267000B2010020070605040302010008F099FFDB
+:10268000002891D15DB1022D09D011E0606850F8A9
+:10269000011FCDF835108088D4E7072024E73EB12C
+:1026A000E06828B16A460BA9FFF7E6FE0028A2D130
+:1026B0001B208DF82C008DF82E8069460BA808F0A1
+:1026C00078FF002897D19DF801001B2816D1052D11
+:1026D00009D2DFE805F0030305050300032000E04D
+:1026E000022000F0E4F9012D0AD0608A40B10022F6
+:1026F0008300114610460FF07FF808B10320F3E67F
+:102700000020F1E62DE9FC4107460D460326084668
+:102710000FF09DF9002863D13846FEF783FE0400D0
+:1027200004D02078222804D20820EAE543F20200EF
+:10273000E7E5A07F00F0030C2DB129466046FEF7C7
+:10274000FEFE0600F1D1F948BCF1010F05D0BCF145
+:10275000020F17D0FFDF3046D3E5A27D2946012ABC
+:1027600002D0007D800701D51120CAE529B968464D
+:1027700000F0FDFA0028D8D16946384605F0A7FFD9
+:102780000646E8E7A17D022914D1007D800611D418
+:1027900025B1A07F40070BD4002100E0012138467D
+:1027A00005F0E0FF0600D6D1A075002DD3D002E0E1
+:1027B0001126D0E7A5B12A4621463846FFF70BF887
+:1027C00006461128C7D1A07F4107C4D4296844F820
+:1027D0000E1F6968616040F0040020740026BAE7AB
+:1027E00010208EE570B50C460546FEF71BFE010075
+:1027F00005D022462846BDE87040FEF7CABF43F226
+:10280000020070BD00B595B031218DF800108DF833
+:10281000020009A9684608F0CCFE15B000BD0123EE
+:10282000FEF703BE00231A461946FEF7FEBD70B53B
+:1028300094B004460FF0C0F810B1102014B070BD71
+:102840002046FEF7EDFE0028F8D1B84DA8781128F3
+:1028500001D00820F2E7FEF797FD20B1287DC006E1
+:1028600003D51120EAE71320E8E71D208DF80000CA
+:10287000207800F001008DF802002089ADF80400F6
+:102880006089ADF806002078C0F340008DF809009B
+:10289000E8780025012618B1012804D00320CDE7EF
+:1028A0008DF8085001E08DF8086009A9684608F025
+:1028B00080FE0028C2D12078800707D5606828B143
+:1028C00009AA6946FFF7D8FD0028B7D11E208DF868
+:1028D00000008DF802608DF8035009A9684608F0E1
+:1028E00068FE0028AAD1A08900F0F5F80400A5D15F
+:1028F0001220FEF72FFD2046A0E7F0B595B0154653
+:102900000C4607460FF0A3F838B920460FF054F8EC
+:1029100018B928460FF050F810B1102015B0F0BDCE
+:10292000824E307D10F0180F01D1400701D51120E3
+:10293000F4E72046FEF774FE0028EFD12078C0F3BC
+:102940004001394302D0800702D50FB10720E5E7E7
+:1029500029460220FEF7F3FD0028DFD1B0781128C8
+:1029600003D0122801D00820D8E706200BF018F871
+:1029700018B1B078122802D005E01220CEE7FFF798
+:102980009DFA0028CAD1FEF7FFFC022801D21320CD
+:10299000C4E72078800707D5606828B109AA69468E
+:1029A000FFF76AFD0028B9D121208DF800002089A9
+:1029B000ADF802006089ADF8040020784FF0010105
+:1029C000C0F340008DF80600207882074FF0000029
+:1029D00015D43A7842B1012A09D0022A07D0032A35
+:1029E00005D043F2022099E78DF8070001E08DF849
+:1029F000071057F8012F0292BA88ADF80C20F27830
+:102A00001AB1012A04D0032088E78DF80E0001E0F6
+:102A10008DF80E102988ADF810106988ADF81210E5
+:102A2000A988ADF81410E988ADF81800ADF81610B3
+:102A3000ADF81A0009A9684608F0BBFD002886D148
+:102A4000A08900F048F804008ED11320FEF782FC24
+:102A5000204663E730B5054695B00C4608460EF0B3
+:102A6000CFFF10B1102015B030BD2846FEF7DAFCBC
+:102A700038B10178222902D3807F800604D408204F
+:102A8000F1E743F20200EEE713208DF80000ADF805
+:102A9000025009A9684608F08CFD0028E3D19DF991
+:102AA0002A107F2901D02170DDE70520DBE730B552
+:102AB0001E4D040008D0012C04D0022C06D0032C9B
+:102AC00004D0FFDF2C7030BDFFDFFBE72878012842
+:102AD000F8D0FFDFF6E710B548B1830000221146B9
+:102AE00007200EF089FE072801D0032010BD00202A
+:102AF00010BD70B50C0006460DD0FEF793FC050026
+:102B000000D1FFDFA680288920812889608168891B
+:102B1000A081A889E08170BD10B50446006840B16D
+:102B20000EF095FF20B1102010BD0000A80100207C
+:102B3000206801F005FBA0882F4C6082607C012892
+:102B40000FD1002109200EF0CDFE00B10120617AE5
+:102B50000122B2EB911F01D1022100E00321FEF717
+:102B600058FE0020E0E72DE9F047002592460C468C
+:102B70000646A8464FF001090B2721E0306850F8BF
+:102B80002500007820B1012805D00720BDE8F08796
+:102B900084F8028001E084F80290306850F8250043
+:102BA00050F8011FC4F803108088A4F807002770AC
+:102BB0005146204608F0FDFC0028E7D16D1CEDB21F
+:102BC0003079A842DAD8002539270FE0B068102202
+:102BD00050F82510A01C18F02DF9277051462046FA
+:102BE00008F0E7FC0028D1D16D1CEDB2307BA84283
+:102BF000ECD80020CAE70000A8010020E848002126
+:102C00000160818070472DE9FF41804692B01C46EB
+:102C10000E4618460EF0D0FE18B1102016B0BDE8D2
+:102C2000F08121460120FEF78AFC0028F6D101251B
+:102C30008DF842504FF4C050ADF84000002210A96A
+:102C4000284603F0AAFD0028E8D18DF842504FF441
+:102C50002850ADF8400000271C216846099718F05D
+:102C600082F99DF82400ADF8346020F00F00401C7C
+:102C700020F0F00010308DF824009DF82500ADF80C
+:102C8000367020F0FF008DF825009DF8260007AA79
+:102C900020F00600801C40F001008DF826009DF811
+:102CA00000000BA940F002008DF800001F20ADF8D5
+:102CB000380009A80C9010A80B90CDF83C8068460D
+:102CC00003F06EFB0028A9D1B54EBDF81C0007AA81
+:102CD00030808DF8425042F60120ADF840009DF85A
+:102CE00026000BA920F00600801C20F001008DF8C2
+:102CF00026000220ADF83400ADF8380014A80F907B
+:102D0000684603F04DFB002888D1BDF81C00708098
+:102D1000311D204600F0ECF880E73EB5044608205F
+:102D2000ADF8000020460EF047FE08B110203EBD71
+:102D300021460120FEF703FC0028F8D12088ADF8D9
+:102D400004006088ADF80600A088ADF80800E088AF
+:102D5000ADF80A00924801AB6A468088002103F072
+:102D600009FFBDF800100829E1D003203EBD1FB5C2
+:102D70000446002002900820ADF80800CDF80CD0E1
+:102D800020460EF019FE10B1102004B010BD84488A
+:102D900002AA81884FF6FF7004F07BF80028F4D176
+:102DA000BDF80810082901D00320EEE7BDF8001097
+:102DB0002180BDF802106180BDF80410A180BDF82B
+:102DC0000610E180E1E701B582B00220ADF8000015
+:102DD000734802AB6A464088002103F0CBFEBDF881
+:102DE0000010022900D003200EBD1CB50021009167
+:102DF0000221ADF8001001900EF002FE08B1102083
+:102E00001CBD67486A4641884FF6FF7004F041F8E0
+:102E1000BDF800100229F3D003201CBDFEB5074603
+:102E200014460E4608460EF0C7FD08B11020FEBD40
+:102E30001F2C01D90C20FEBD38460EF0BDFD584DAB
+:102E400018BB288801A903F021F80028F3D13878AD
+:102E50008DF80500288801A903F06DFE0028EAD14D
+:102E600000909DF800009DF8051040F002008DF8DC
+:102E70000000090703D040F008008DF80000288802
+:102E8000694603F0FBFD0028D5D1ADF8084028883D
+:102E9000334602AA002103F06DFEBDF80810A142DE
+:102EA000C9D00320FEBD7CB50546002000900190EE
+:102EB0000888ADF800000C46284601950EF0BEFDCE
+:102EC00018B920460EF09CFD08B110207CBD15B14C
+:102ED000BDF8000050B132486A4601884FF6FF70D5
+:102EE00003F0D7FFBDF8001021807CBD0C207CBD15
+:102EF00030B593B0044600200D460090142101A87F
+:102F000018F031F81C2108A818F02DF89DF80000E1
+:102F1000CDF808D020F00F00401C20F0F000103059
+:102F20008DF800009DF8010006AA20F0FF008DF842
+:102F300001009DF8200001A940F002008DF820005A
+:102F400001208DF8460042F60420ADF8440011A897
+:102F500001902088ADF83C006088ADF83E00A08864
+:102F6000ADF84000E088ADF842009DF8020020F086
+:102F70000600801C20F001008DF802000820ADF84A
+:102F80000C00ADF810000FA8059008A803F008FA8F
+:102F9000002803D1BDF818002880002013B030BDF0
+:102FA00010000020094810B504680A490848086064
+:102FB0000DF08AFB0848046010BD08490020086035
+:102FC0004FF0E0210220C1F8800270471005024056
+:102FD000010000011805024014050240FC1F0040DA
+:102FE00070B50C46054606F0BFFE21462846BDE8F2
+:102FF000704007F09CBE704770477047704770473D
+:1030000010FFFFFFDBE5B15100C001008100FFFFB1
+:1030100010B504460EF0D0FC08B1102010BD207889
+:10302000C0F30210042807D86078072804D3A178D9
+:10303000102901D8814201D2072010BDE078410754
+:1030400006D421794A0703D4000701D4080701D523
+:10305000062010BD002010BD10B513785C08C37F9A
+:1030600064F30003C3771478A40864F34103C377BF
+:103070001078C309887863F34100887013781C09BD
+:103080004B7864F347134B701378DB0863F300004D
+:1030900088705078487110BD10B5C4780B7864F30F
+:1030A00000030B70C478640864F341030B70C478A8
+:1030B000A40864F382030B70C478E40864F3C303C8
+:1030C0000B700379117863F30001117003795B08C9
+:1030D00063F34101117003799B0863F3820111705E
+:1030E0000079C00860F3C301117010BD70B51446BB
+:1030F0000D46064604F052FB80B10178142221F0FF
+:103100000F01891C21F0F001A03100F8181B2146A5
+:1031100017F0D5FEBDE8704004F01EBB29463046CE
+:10312000BDE870401322FEF734BB70B514460E465E
+:10313000054604F033FB70B1017821F00F01891CC2
+:1031400021F0F00120310170458021688161BDE8E6
+:10315000704004F001BB31462846BDE870401322A0
+:10316000FEF717BB10B5FE4C94F8300000280CD1C8
+:1031700004F120014FF6FF72A1F110000CF0B9F834
+:1031800000B1FFDF012084F8300010BD2DE9F047C9
+:10319000064608A8894690E830041F469046142148
+:1031A000284617F0E0FE0021CAF80010B8F1000F21
+:1031B00003D0B9F1000F03D114E03878C00711D063
+:1031C00020680EF01DFCE8BBB8F1000F07D12068A5
+:1031D000123028602068143068602068A860216878
+:1031E000CAF800103878800727D560680EF026FCF2
+:1031F00040BBB9F1000F2CD0FFF73CF80168C6F8CE
+:10320000B4118188A6F8B811807986F8BA01FFF761
+:10321000A9FFDFF84C8308F12008C5F80C8062682C
+:103220005AB196F8B40106F2B5111032FEF7A0FAC1
+:1032300010224146606817F0FDFD3878400712D52E
+:10324000A06800E002E00EF0DBFB50B11020BDE80A
+:10325000F08760680028F9D0E8606068C6F8B001BF
+:10326000EBE7A06828610020F1E730B50546087853
+:103270000C4620F00F00401C20F0F00110312170AE
+:103280000020607095F8220030B104280FD0052886
+:1032900011D0062814D0FFDF20780121B1EB101FD8
+:1032A00004D295F8200000F01F00607030BD21F0BE
+:1032B000F000203002E021F0F00030302070EBE729
+:1032C00021F0F0004030F9E710B510B190F8A940B6
+:1032D00044B1A34890F8354000205CB1086010600C
+:1032E000186010BD00F1A8040C6000F1D001F830A6
+:1032F0001160F5E79A4C34340C60F0E700B58BB000
+:103300000823CDE902128DF8013001919449002380
+:1033100064310591099301468DF8103068460BF031
+:10332000C0FF002800D0FFDF0BB000BD30B595B066
+:103330000C462C2518998DF80050ADF80200B3B159
+:103340001868019058680290ADF80C2010220DF119
+:103350000E0017F06FFD09A9684608F02AF9002849
+:1033600003D1A17F41F01001A17715B030BD00203D
+:103370000190E8E72DE9F0470646008A8AB080B25E
+:103380000D468146FEF74EF80446754F3078283FCB
+:10339000DFF8CC814FF0000A122873D2DFE800F08A
+:1033A00072E9350936777E98A8F3E7E6E5E4DF5B56
+:1033B000DFDFA07F00F00300012806D0002148468F
+:1033C0000AF03BFB050003D101E00121F7E7FFDF35
+:1033D00098F85C10090602D5D8F860000BE00321CC
+:1033E00005F121000DF09AFFD5F821005D49B0FBF1
+:1033F000F1F201FB1200C5F8210070686866B06840
+:10340000A8662078252800D0FFDFECE0A07F00F040
+:103410000300012806D0002148460AF00EFB0600F2
+:1034200003D101E00121F7E7FFDF7078810702D5C2
+:103430002178252904D040F0010070700AB006E719
+:103440000220287096F82000287106F121003136FC
+:10345000C5E90206F2E7A07F00F00300012806D0CC
+:10346000002148460AF0E9FA040003D101E00121F5
+:10347000F7E7FFDF6078C10605D5142028704134D6
+:103480006C60DBE7E2E140F008006070D6E73448AA
+:10349000082128380DF042FF032016E02A208DF87D
+:1034A000000010220DF10200716817F0C3FC102219
+:1034B0000DF11200B16817F0BDFC294968462C399E
+:1034C00008F077F800B1FFDF042028706F60B5E7DF
+:1034D000E07FC00600D5FFDFB0680090B388062209
+:1034E0000321484605F063F80028A7D0FFDFA5E7D1
+:1034F00004B9FFDF716821B1102204F1230017F035
+:1035000099FC28212046FDF7C5FFA07F00F00300AD
+:1035100002280ED104F12300002300901A46214610
+:103520004846FFF703FF112807D029212046FDF761
+:10353000B1FF307A84F8200080E7A07F000700D533
+:10354000FFDF14F81E0F40F008002070A4F816A04A
+:10355000C4F818A0C4F81CA0617808460AE034E05A
+:103560005C02002040420F006CE19AE090E062E0D3
+:1035700009E03FE061F38200410861F3C30060703D
+:10358000307AE0705AE7A07F00F00300012806D0EF
+:10359000002148460AF051FA040003D101E001215C
+:1035A000F7E7FFDF022104F175000DF0B7FE1120EF
+:1035B000287004F5DA706860B4F875002882FD4858
+:1035C0006C346C61C5E9028038E7A07F00F003002D
+:1035D000012805D0002148460AF02FFA18B901E069
+:1035E0000121F8E7FFDF0AB0324621464846BDE830
+:1035F000F0477BE504B9FFDF207821289CD930799A
+:10360000012802D002280AD103E0E07F40F0100038
+:10361000E07798F85C1041F0010188F85C103246C0
+:1036200021464846FFF762FD0AB02046BDE8F04754
+:103630002321FDF72FBF327901230321484604F0EF
+:10364000B7FD98B1122005F8040B327925F8042B48
+:10365000281DA91E0095CDE901100023032148462D
+:1036600004F023FE00288DD0FFDFE7E6A07F00F006
+:103670000300012806D0002148460AF0DEF90400C4
+:1036800003D101E00121F7E7FFDF30792070D5E6B3
+:103690000321484605F02DF9002895D11320287004
+:1036A000CCE6A07F00F00300012806D000214846A8
+:1036B0000AF0C3F9050003D101E00121F7E7FFDFBC
+:1036C00095F8740000F00300012878D1A07F00F085
+:1036D0000307E07FC0F3400616B1012F04D02BE0B2
+:1036E00095F89000C0072AD0D5F8AC0118B395F82A
+:1036F0007320017C62F387010174E27FD5F8AC018D
+:1037000062F341010174D5F8AC0166F30001017464
+:10371000AEB1D5F8AC01102204F12301783517F0D1
+:1037200089FB287E40F001002876287820F00100EF
+:1037300005F8780900E016B1022F04D02CE095F8C6
+:103740007800C00726D0D5F8A80118B395F87320E3
+:10375000017C62F387010174E27FD5F8A80162F36E
+:1037600041010174D5F8A80166F3000101748EB11E
+:10377000D5F8A801102204F12301783517F05AFB7F
+:10378000287840F0010005F8180B287820F0010097
+:1037900005F89009022F51D05FF0000000EB4000C7
+:1037A00005EBC00090F87800800708D5D5F8B02167
+:1037B00095F86C0005F16D011032FDF7D9FF052079
+:1037C00060F3070815F8740F00F0030060F30F288A
+:1037D000287960F31748287F60F31F687548AC3874
+:1037E000027822F00F02921C22F0F00220320270C6
+:1037F000427822F00702D21C4270A0F80290C0F872
+:10380000188004F033F92078252805D0212807D026
+:10381000FFDF2078222803D922212046FDF73AFE37
+:10382000A07F00F0030001280AD0002148460AF0DA
+:1038300016F900283FF40EAEFFDFFFE50120ADE7EB
+:103840000121F3E7716881F801A0F7E5FFDFF5E5F5
+:1038500070B5584C0025103C14F85C0F20F0800027
+:10386000207065600BF0E7FC5249A1F1100004F0F4
+:103870008FF804F82C5C072060724E487C30206181
+:103880005030A0611030E06170BD70B50D46FDF79D
+:10389000C9FD040000D1FFDF4FF4DE71284617F0A8
+:1038A00062FB44485430686104F123002861A07F22
+:1038B00000F00300012809D05FF0020105F59070C7
+:1038C0000BF0BAFC002800D0FFDF70BD0121F5E746
+:1038D0000A46014602F590700BF0CCBC70B5054667
+:1038E00040689AB0017808290DD00B2903D00C2923
+:1038F00036D101218171686886883046FDF792FDD6
+:10390000040035D133E046883046FDF78BFD0400D6
+:1039100000D1FFDF2078212822D0282822D1686812
+:1039200002210C3001F09CF9E0B168680821001D0B
+:1039300001F096F9B0B12D208DF80000ADF80260CD
+:10394000102204F1230101A817F074FA09A96846AE
+:1039500007F02FFE00B1FFDF29212046FDF79AFD79
+:103960001AB070BD687840F008006870F8E7FFDFB3
+:10397000A07F00F00301022902D120F01000A077FF
+:10398000207821280AD06868817909B1807898B1B7
+:10399000A07F00F0030002285BD0FFDFA07F00F0D3
+:1039A00003000228DCD1FDF76CFF0028D8D0FFDF30
+:1039B000D6E700006C020020687840F008006870CC
+:1039C000E07FC10720D0800701D5062000E0052058
+:1039D00084F822002078292818D02428DED1314606
+:1039E00006200DF0A6FF22212046FDF753FDA07F03
+:1039F00000F0030001282AD0002130460AF02FF8F9
+:103A00000028CBD0FFDFC9E70420E1E7A07F00F06A
+:103A10000300012806D0002130460AF00EF8050008
+:103A200003D101E00121F7E7FFDF25212046FDF763
+:103A300031FD10208DF8500014A905F590700BF0A1
+:103A400010FC0228AAD00028A8D0FFDFA6E7012199
+:103A5000D3E7687840F0080068709FE72DE9F047E9
+:103A60008CB01D46904689460646DDF850A0FDF70D
+:103A7000D9FC040052D0207822284FD323284DD0DF
+:103A8000E07FC0064AD4A07F00F00300012806D0E2
+:103A90000021304609F0D1FF070002D00BE00121E0
+:103AA000F7E7A07F00F00300012804D10121304690
+:103AB00009F0BAFF074601AB02AA03A93846FFF78F
+:103AC00003FC039800B9FFDF4FB1039807F5907727
+:103AD00087612078222806D0242804D007E00399A3
+:103AE0000020886103E025212046FDF7D3FC0398E0
+:103AF0000C2141704662A0F80480C0F80890A0F83C
+:103B000006A0C560029901610199416104A90BF009
+:103B1000C8FB022802D0002800D0FFDF0CB0BDE8AF
+:103B2000F08730B589B00546FDF77CFC0178222985
+:103B300033D9807F00F00300012806D000212846F9
+:103B400009F07BFF040003D101E00121F7E7FFDF6B
+:103B5000227801230321284604F02AFB00281CD0E8
+:103B600012208DF80C00227806A8811F05ABCDE944
+:103B700000310290ADF8102000230321284604F004
+:103B800094FB00B1FFDF03A904F590700BF069FB13
+:103B9000022802D0002800D0FFDF09B030BD10B5E8
+:103BA00086B00446FDF73EFC0178222919D9807FB2
+:103BB00000F00300012806D00021204609F03DFF57
+:103BC000040003D101E00121F7E7FFDF13208DF8A6
+:103BD0000000694604F590700BF043FB002800D00C
+:103BE000FFDF06B010BD2DE9F05F05460C4600274B
+:103BF0000078904601093E46BB4604F1080A0229B6
+:103C00007ED0072902D00A2909D141E068680178ED
+:103C1000082905D00B292BD00C2929D0FFDFC5E1BD
+:103C200014271C26002C6CD04088A080FDF7FAFBDE
+:103C30005FEA000900D1FFDF99F81700524609F149
+:103C40001801FDF795FD68688089208269684868D9
+:103C5000C4F812008868C4F81600A07E20F00600A0
+:103C600040F00100A07699F81E0040F040014DE0C0
+:103C70001A270A26002CD6D08088A080FDF7D2FB18
+:103C8000050000D1FFDF51462846FFF7EEFA8DE12F
+:103C90000CB1288DA080287E0E287CD006DC01285F
+:103CA0007AD0022808D0032804D135E0102874D037
+:103CB000112873D0FFDF79E11E270926002CB2D02E
+:103CC000A088FDF7AFFB5FEA000900D1FFDF287F86
+:103CD00000F003000128207A1BD020F001002072A0
+:103CE000297F890861F341002072297FC90861F3A7
+:103CF00082002072297F090961F3C300207201E06C
+:103D000049E116E199F81E0040F0800189F81E1083
+:103D10004CE140F00100E2E713270D26002CAAD069
+:103D2000A088FDF77FFB8146807F00F0030001281B
+:103D300006D00021A08809F080FE050003D101E033
+:103D40000121F7E7FFDF99F81E0000F00302012AC6
+:103D500059D0A86E817801F003010129217A54D04D
+:103D600021F00101217283789B0863F341012172E4
+:103D70008378DB0863F38201217283781B0963F384
+:103D8000C3012172037863F306112172437863F350
+:103D9000C711217203E060E0A6E08EE09EE084F8A7
+:103DA00009B0C178A172012A32D04279E17A62F376
+:103DB0000001E1724279520862F34101E1724279F5
+:103DC000920862F38201E1724279D20862F3C30180
+:103DD000E1720279217B62F30001217302795208BA
+:103DE00062F3410121730279920862F38201217327
+:103DF0000079C00860F3C301217399F800002328FB
+:103E00005AD9262168E0686EA4E741F00101A9E7CC
+:103E10000279E17A62F30001E1720279520862F3F9
+:103E20004101E1720279920862F38201E172027942
+:103E3000D20862F3C301E1724279217B62F300018F
+:103E400021734279520862F3410121734279920849
+:103E500062F3820121734079CBE718271026002CEA
+:103E600067D0A088FDF7DEFA8246807F00F003006D
+:103E7000012807D00021A08809F0DFFD5FEA0009D2
+:103E800003D101E00121F6E7FFDFE869A06099F8BE
+:103E9000010040F0040189F8011099F80200800740
+:103EA00008D5012020739AF8000023287ED9272105
+:103EB000504663E084F80CB078E015270F26C4B3B1
+:103EC000A088FDF7AFFA814606225146E86907F05F
+:103ED000D6FB0120A073AEE048464FE01627092626
+:103EE0003CB3287F207261E0287FFE4902280CD075
+:103EF00019270E26ECB101280DD003281AD004286A
+:103F00001BD0052819D0FFDF23E01B270926BCB3EF
+:103F10000120207205E001202072607A20F0030069
+:103F2000607211F85C0F4208520062F306000870DC
+:103F30000FE02BE00220207207E0697F052801F0E6
+:103F40000F0141F0800121721BD0607A20F0030044
+:103F50006072A088FDF766FA05460078212825D012
+:103F6000232800D0FFDFA87F00F00300012810D035
+:103F70000021A08809F073FD22212846FDF78AFA66
+:103F800014E0607A20F00300401CE1E7A8F800602C
+:103F900011E00121EDE70CB16888A080287E03289C
+:103FA0002BD004280AD005284BD0FFDFA8F80060EA
+:103FB0000CB1278066800020BDE8F09F15270F26F2
+:103FC000002CE3D0A088FDF72DFA807F00F00300DD
+:103FD000012806D00021A08809F02FFD050003D19B
+:103FE00001E00121F7E7FFDFD5F821000622514665
+:103FF00007F045FB84F80EB0D8E717270926002CF8
+:10400000C4D0A088FDF70EFA8146807F00F003003F
+:10401000012806D00021A08809F00FFD050003D17A
+:1040200001E00121F7E7FFDFA878800701D5022032
+:1040300000E00120207299F800002328B6D927213A
+:104040004AE719270E26002CA0D0A088FDF7EAF930
+:104050005FEA000900D1FFDFC4F808B0A4F80CB093
+:1040600084F808B0A07A40F00300A07299F81F10FD
+:1040700061F38200A07299F81F1001EA510161F307
+:10408000C300A072687E00F0030001288ED1607A20
+:1040900040F00400607299F81E0000F0030001284F
+:1040A00014D0E97E607B61F300006073AA7E217BFF
+:1040B00062F300012173EA7E520862F341006073EB
+:1040C000A87E400860F3410121736FE7E87E217B01
+:1040D00060F300012173AA7E607B62F300006073CD
+:1040E000EA7E520862F341012173A97E490861F317
+:1040F000410060735AE730B504468079012591B0DC
+:10410000B5EB901F00D0FFDFFFF72CF84FF6FF70E4
+:10411000099074488DF8015020300190201D0290C4
+:10412000601C0B900AA968460BF0BBF800B1FFDFDA
+:104130000B980188A4F801108078E07011B030BDB0
+:1041400010B5684C30B10146102204F1200016F081
+:1041500071FE012084F8300010BD10B50446FFF751
+:1041600001F8604920461022BDE81040203116F0C9
+:1041700061BE70B55B4C06004FF0000514D00DF029
+:104180001BFC08B110250DE00621304607F05EFA51
+:10419000411C06D0206614F85C0F40F080002070AF
+:1041A00000E00725284670BD14F85C0F20F0800061
+:1041B000F5E72DE9F041804688B00D460027084616
+:1041C0000DF045FCA8B94046FDF72CF9040003D0DA
+:1041D0002078222815D104E043F2020008B0BDE89F
+:1041E000F08145B9A07F010603D500F00300022845
+:1041F00001D01020F2E7A07FC10601D4010702D54B
+:104200000DB10820EAE7374991F85C10C90701D0E1
+:104210001120E3E7E17FC90601D50D20DEE700F0BC
+:104220000300022805D125B12846FEF7F1FE07005C
+:10423000D4D1A07F00F00300012806D00021404621
+:1042400009F0FBFB060002D00CE00121F7E7A07F9C
+:1042500000F0030001280BD00021404609F0E4FBE8
+:10426000060007D0A07F00F00300022804D009E078
+:104270000121F2E70420B1E725B12A463146204664
+:10428000FEF7EAFE07AB1A4669463046FFF71CF810
+:10429000009800B9FFDF00990D20487006F5907076
+:1042A000C1F82480486100200881A07F00F003004D
+:1042B00001282BD0F5B302200871301D8861707879
+:1042C00040090877B078C0F340004877287800F0BC
+:1042D0000102887F62F301008877E27F62F3820047
+:1042E000887701E05C020020E27F520862F3C3009D
+:1042F0008877B27862F304108877A878C87701F1DC
+:10430000210228462031FEF7C7FE22E00120087175
+:10431000287800F00102087E62F3010008762A780E
+:10432000520862F3820008762A78920862F3C3008A
+:10433000087600E009E02A78D20862F304100876D3
+:1043400024212046FDF7A6F80BE003200871052084
+:10435000087625212046FDF79DF8A07F20F08000FB
+:10436000A07701A900980AF09CFF022801D000B1B3
+:10437000FFDF384632E72DE9FF4FF94A0D4699B085
+:104380009A4607CA14AB002783E807001998FDF77F
+:1043900049F8060006D03078262806D008201DB03F
+:1043A000BDE8F08F43F20200F9E7B07F00F00309A7
+:1043B000B9F1010F03D0B9F1020F07D008E03DB900
+:1043C0001B98FEF725FE0028E9D101E01B9878BB79
+:1043D000B07F00F00300012806D00021199809F0F1
+:1043E0002CFB040003D101E00121F7E7FFDF852D5D
+:1043F00025D007DCD5B1812D1BD0822D1BD0832D7C
+:1044000008D11AE0862D1CD0882D1CD0892D1CD0F7
+:104410008A2D1CD00F2020710F281AD001208DF872
+:104420003400201D0E902079A8B158E10020F2E759
+:104430000FE00120EFE70220EDE70320EBE7052086
+:10444000E9E70620E7E70820E5E70920E3E70A2097
+:10445000E1E70720A3E7B9F1010F17D0D4E919501C
+:1044600080460220019001200090A87898F8021060
+:10447000C0F3C000C1F3C00108405FEA000B5DD08B
+:1044800050460DF099FA00286CD12DE0D4E9198539
+:104490000120019002200090214630461B9AFEF731
+:1044A000DBFD1B98007800F00101A87861F30100A2
+:1044B000A870F17F61F38200A870F17F490861F371
+:1044C000C300A870A17861F30410A8706078400957
+:1044D0002870A078C0F3400068701B988078E8705E
+:1044E000002068712871C0E7DAF80C000DF064FA5A
+:1044F000C0BBDAF81C000DF05FFA98BBDAF80C00CC
+:10450000A060DAF81C00E06098F80100A17800F0E3
+:10451000010041EA4000A07098F80210C0B2C1F357
+:104520000011891E0840A070002084F82000009926
+:1045300006F1170002290BD001210AE098F80110BA
+:10454000A07801F00101FD2242EA41010840E2E7C2
+:10455000002104EB810188610199701C022902D0BD
+:10456000012101E028E0002104EB81018861A878A5
+:1045700000F00300012849D198F8020000F0030080
+:10458000012843D1B9F1010F04D12A1D691D1B98DF
+:10459000FEF782FD297998F8040001408DF82C106F
+:1045A000687998F8052010408DF8300001432DD02F
+:1045B00050460DF001FA08B11020F0E60AF11000A3
+:1045C00004F5D47104F17C020490B9F1020F3CD0DF
+:1045D0000090CDE9012100210BAB5A462046FEF7A1
+:1045E000D5FD0028E9D104F5D67104F19402B9F1A2
+:1045F000010F30D004980090CDE9012100210CABCF
+:104600005A462046FEF7C2FD0028D6D1A078800782
+:1046100040D4A87898F80210C0F38000C1F380015C
+:10462000084337D0297898F8000014AAB9F1010F8F
+:1046300017D032F810204B00DA4012F0030718D0E0
+:10464000012F1ED0022F12D11DE0CDF800A0CDE920
+:1046500001210121C0E7CDF800A0CDE90121012110
+:10466000CDE732F811204300DA4002F00307032FB0
+:1046700007D0BBF1000F0DD0012906D0042904D0CA
+:1046800008E00227F5E70127F3E7012801D0042815
+:1046900000D10427F07F40F001006BF34100F07778
+:1046A000A07881074FF003000CD5A071BBF1000F7B
+:1046B00015D100BF8DF85C0017AA31461998FEF796
+:1046C00034FD0CE00221022F18D0012F18D0042F46
+:1046D00022D00020A071F07F20F00100F07725218A
+:1046E0003046FCF7D7FE0DA904F590700AF0B9FD2D
+:1046F00010B1022800D0FFDF002050E6A171D9E7F9
+:10470000A1710D2104F1240016F02DFC607840F019
+:10471000020060700420CDE70120A071DFE72DE9E1
+:10472000F04387B0914688460446FCF77BFE0700BD
+:1047300006D03878272806D0082007B0BDE8F083D7
+:1047400043F20200F9E7B87F00F00300012809D026
+:104750000021204609F071F9040006D104E00000B0
+:1047600008B301000121F4E7FFDFA679012E08D08C
+:10477000B8F1000F0FD048460DF01EF9B8B1102067
+:10478000DBE7B9F1000F25D1B8F1000F09D0B8F17E
+:10479000010F1FD120E0022E05D0032E05D0FFDF30
+:1047A00028E00C2526E0012524E0022522E0B8F1CE
+:1047B000020F03D0B8F1010F0AD00BE0032E09D18C
+:1047C00000251022494604F1210016F033FB11E0C8
+:1047D000022E01D00720B0E70025102104F12100AE
+:1047E00016F09FFB5FEA090004D0062106F02EFFB9
+:1047F000C4F82100607840F002006070C10713D057
+:1048000020F00100607002208DF8000004F121000A
+:1048100002908DF804506946FF300AF022FD02280C
+:1048200004D018B1FFDF01E084F82050252138467C
+:10483000FCF730FE002080E730B587B00D46044617
+:10484000FCF7F0FD88B1807F00F0030001280FD055
+:104850000021204609F0F1F804000ED028460DF0A2
+:10486000ABF838B1102007B030BD43F20200FAE7D0
+:104870000121EEE76078400701D40820F3E72946DC
+:1048800004F141002022054616F0D4FA607840F089
+:104890001000607001070FD520F008006070142030
+:1048A0008DF80000694604F5907001950AF0D9FC76
+:1048B000022801D000B1FFDF0020D4E770B594B02A
+:1048C0000D460646FCF7AEFD18B10178272944D104
+:1048D00003E043F2020014B070BD807F00F00300DB
+:1048E000012806D00021304609F0A7F8040003D1C2
+:1048F00001E00121F7E7FFDFA07902282DD1A078A0
+:10490000C0072AD0002302220321304603F050FCC6
+:1049100028B30D208DF80D0007A80222811FADF8E5
+:10492000142006ABCDE900310C9604F5907402908A
+:10493000089400230321304603F0B7FC00B1FFDFE9
+:1049400004208DF810008DF824500DA903A80AF05A
+:10495000A8FC00B1FFDF0020BDE70820BBE7112065
+:10496000B9E770B5064686B014460D4608460DF008
+:1049700023F818B920460DF043F810B1102006B006
+:1049800070BDA6F57F40FF380DD03046FCF74AFDDC
+:1049900030B14378811C22461846FCF7E9FE07E057
+:1049A00043F20200EBE72046FDF7F3FC0028E6D1D6
+:1049B0001021E01D0CF0B2FCE21D29466846FEF70E
+:1049C0009DFC102204F11700019916F033FA002023
+:1049D000D5E72DE9F04104468CB0154688460027FE
+:1049E00008460DF034F818B928460DF030F818B123
+:1049F00010200CB0BDE8F0812046FCF713FD060046
+:104A000003D03078272818D102E043F20200F0E703
+:104A1000B07F00F00300012806D00021204609F0F5
+:104A20000CF8040003D101E00121F7E7FFDF607813
+:104A3000400702D5A078800701D40820D9E7B07FCD
+:104A400000F00300012818D0D4E91901407800B122
+:104A5000B5B1487810B1B8F1000F11D0C5B1EA1D59
+:104A600006A8E168FEF74AFC102205F11700079935
+:104A700016F0B4F930B104270AE0D4E91910E5E7DB
+:104A80000720B6E71022E91D04F1310016F0D2F933
+:104A9000B8F1000F06D0102208F1070104F121003F
+:104AA00016F0C8F9607840F002006070C10715D0B8
+:104AB00020F00100607002208DF8000004F1210058
+:104AC0000290103003908DF804706946EF300AF0C0
+:104AD000C8FB022804D018B1FFDF01E084F8207081
+:104AE00025213046FCF7D6FC002082E7F8B51546B4
+:104AF0000E460746FCF796FC040004D020782228D6
+:104B000004D00820F8BD43F20200F8BDA07F00F0F9
+:104B10000300022802D043F20500F8BD30460CF035
+:104B20004BFF18B928460CF047FF08B11020F8BD1C
+:104B300000953288B31C21463846FEF7F7FB112852
+:104B400014D00028F3D1297C4A08E17F62F30001E8
+:104B5000E1772A7C62F34101E177297C890884F8B6
+:104B60002010A17F21F08001A177F8BDA17F090766
+:104B7000FBD4D6F80200C4F83600D6F80600C4F814
+:104B80003A003088A0861022294604F1230016F04E
+:104B900051F9287C4108E07F61F38200E077297CAD
+:104BA00061F3C300E077287C800884F82100A07FAF
+:104BB00040F00800A0770020D3E770B594B00D4610
+:104BC00006460BB1072086E6FCF72CFC040007D054
+:104BD0002078222802D3A07F400604D408207AE659
+:104BE00043F2020077E6C5B12D208DF80000ADF844
+:104BF00002601022294601A816F01CF9287C410801
+:104C0000E07F61F30000E077297C61F34100E07709
+:104C1000287C800884F8200004E02E208DF8000015
+:104C2000ADF8026009A9684606F0C3FCA17F21F037
+:104C30004001A1774FE670B50D46FCF7F3FB040089
+:104C400005D028460CF0DCFE20B1102070BD43F2E8
+:104C5000020070BD29462046FEF707FB002070BD0C
+:104C600005E000BF10F8012B0AB100207047491E73
+:104C700089B2F7D20120704770B50D4600780499CB
+:104C80001446042803D0052832D0FFDF70BDA88B5E
+:104C90000E2200EB400002EB400018803320088019
+:104CA000002CF3D0A88BA081002613E0A87F012858
+:104CB00014D006EBC60005EB400106EB460204EB00
+:104CC0004202088CD0811020223110320AF08AFB77
+:104CD000761CB6B2A089B042E8D870BD05EB86015B
+:104CE00006EB460204EB4202088CD0810220EBE77F
+:104CF000A88B102200EBC00002EB4000188034208B
+:104D00000880A87F012808D0022806D0FFDF002CE9
+:104D1000E3D0A88BA081002613E0A073F7E7A87F5B
+:104D2000012812D006EBC60005EB400104EB400061
+:104D30000A8C028210221230223116F07BF8761C87
+:104D4000B6B2A089B042EAD870BD05EB860106EB89
+:104D5000C602088C04EB4202223110820220123279
+:104D60000AF040FBEBE72DE9F04105780E20DDF875
+:104D700018C001F1200402F10E074FF00008022DC7
+:104D800006D0032D2DD0062D6AD0FFDFBDE8F081BF
+:104D9000CD8B05EB850600EB460018803120ACF882
+:104DA0000000002AF2D0087F9581801FC6B214E06F
+:104DB00061682088388031F8020BF88031F8020BE6
+:104DC0003881BA1C30460AF00DFB06B118B187F8DD
+:104DD0000480A7F8028008340A376D1EADB2E7D20E
+:104DE000D4E7CD8B05EB850600EB4600188032201A
+:104DF000ACF80000002AC9D0087F9581401FC6B2D8
+:104E00002AE06168228811F8010BFA803A79430898
+:104E100060F3000263F34102830863F38202C30874
+:104E200063F3C302030963F30412430963F34512F6
+:104E3000830963F386123A71C009787131F8020B65
+:104E400038813A4630460AF0CDFA18B187F8028028
+:104E5000A7F8008008340A376D1EADB2D1D295E7AD
+:104E6000087FCD8B801E86B206F1080068431030A3
+:104E700018803520ACF80000002A87D0958102F117
+:104E80001007D68107EBC5080BE020883880C7F8EB
+:104E9000048032464046616815F0CCFF0834B044C7
+:104EA00008376D1EADB2F0D270E72DE9F0471D4610
+:104EB000089E0C4681462AB1607E00F58070D08045
+:104EC000E08B108199F800000E274FF000084FF09A
+:104ED000100A0C287ED2DFE800F096061521293151
+:104EE0003F4E636B6B6B207F9146082802D00328EE
+:104EF00000D0FFDF2F8030200BE000BFA9F80C802E
+:104F0000BDE8F087207F9146042800D0FFDF2F8086
+:104F100031203080B9F1000FF0D1F1E7207F9146C8
+:104F2000042800D0FFDF2F803220F2E7207F914657
+:104F3000022800D0FFDF2F803320EAE7207F1746CA
+:104F4000022800D0FFDF3420A5F800A03080002F19
+:104F5000D6D0A7F80C80D3E7207F1746042800D0CE
+:104F6000FFDF3520A5F800A03080002FC8D04046D4
+:104F7000A7F80C8012E0207F1746052802D00628EB
+:104F800000D0FFDF1220288036203080002FB7D0DD
+:104F9000E08BB881A7F81080B9F80200F881AFE77C
+:104FA000207F9146072800D0FFDF2F803720B0E711
+:104FB0004FF0140018804FF03800170030809FD059
+:104FC000E08BB881A7F8128099F80000092807D073
+:104FD0000A2800E017E009D00B280DD0FFDF8FE78B
+:104FE000207F0C2800D0FFDF01200AE0207F0D2861
+:104FF00000D0FFDF042004E0207F0E2800D0FFDF78
+:105000000520B8737CE7FFDF7AE770B50C460546EC
+:10501000FCF708FA20B10078222804D2082070BDDD
+:1050200043F2020070BD0521284608F006FD20600D
+:1050300008B1002070BD032070BDFFB585B00746E4
+:105040001720ADF80C00089814460D46022628B922
+:1050500008A93846FFF7D9FF00283ED15DB10023EB
+:10506000BDF80C203146384603F0A2F8B8B30898D2
+:105070000078A0BB05E02078092822D00F282FD087
+:10508000FFDF002004A9CDE9001003460290BDF81F
+:105090000C203146384603F008F900281DD1089845
+:1050A00003A9801DC4E901072046049A04F017FBF8
+:1050B00060B3072828D2DFE800F01E1C2727252030
+:1050C000220007260023BDF80C203146384603F0A5
+:1050D0006FF80028D5D143F2040009B0F0BD08E014
+:1050E0000023BDF80C203146384603F061F8002853
+:1050F000C7D11120F1E70020EFE70820EDE743F2E8
+:105100000300EAE70720E8E70320E6E704980090B9
+:10511000BDF80C3004223146384603F048FA002826
+:10512000DBD1002DD9D008990D70D6E710B588B025
+:105130001C46AAB104238DF800301388ADF80C305A
+:105140005288ADF80E208A788DF812200988ADF8C3
+:10515000101000236A462146FFF76FFF08B010BD0C
+:105160001020FBE72DE9F041074600780C46122895
+:1051700039D2DFE800F0383434141036090909094F
+:10518000090909090909090904B9FFDF607840F034
+:105190000800607028E0002CF8D1FFDFF6E7B8883F
+:1051A000052186B2304608F048FC054604B1FFDF11
+:1051B00005B9FFDF3146A81D04F08AFA02F0EEFAC5
+:1051C000040007D0607840F008006070668002F04C
+:1051D000C3FA0AE013213046FDF704FB16E0FFDFB7
+:1051E00002E0FFDF00E0FFDF84B1607800070DD54B
+:1051F0002078582220F00F00C01C20F0F0009030E2
+:105200002070394604F1180015F059FE0020BDE564
+:1052100000200870881D04F058BA0A460146901D07
+:1052200004F05CBA70B50546052108F006FC0400E0
+:1052300000D1FFDF2946A01DBDE8704004F048BA48
+:105240002DE9FE4F4FF00009ADF80890ADF804903D
+:1052500047880C46054693460521384608F0EDFB85
+:10526000060000D1FFDF24B1A780A4F80690A4F8BF
+:105270000890297E04F112003827C91E4FF001085A
+:105280004FF0360A00900F2970D2DFE801F0F9FAEA
+:105290006F6108AD6A70812CB6C9E59595003078CC
+:1052A000012800D0FFDFA88B0E2101EBC001ADF873
+:1052B00004103021ADF80810002C13D0A08100207C
+:1052C0000DE004EBC00132790A747288CA8105EBE3
+:1052D0008002401CD38B4B82128C8A8280B2A189BF
+:1052E0008142EED8E8E03078012800D0FFDFE88B7B
+:1052F0000E2101EBC001ADF804103021ADF808100B
+:10530000297F091FC9B20091002CEBD0A081002792
+:105310001AE000BF05EBC70A04EBC70808F10E024C
+:10532000DAF8241000980AF05DF818B188F81090A7
+:10533000A8F80E90BAF82010A8F81210BAF82210A7
+:105340007F1CA8F81410BFB2A089B842E2D8B3E01D
+:1053500002A8009001AB224629463046FFF78CFC9C
+:10536000AAE03078072806D0FFDF04E0A3E0307819
+:10537000072800D0FFDFE88BADF808A01230ADF8A9
+:105380000400002C38D0A98BA1817188E18123E031
+:105390003078082800D0FFDFA88B00F10E01ADF8AF
+:1053A00004103721ADF80810002C25D0A081AA8B5D
+:1053B00004F10E00296A4CE0E88B123080B23921EA
+:1053C000ADF80400ADF80810F4B3A98BA181287ED4
+:1053D000102807D00221A173E98B2182EA8B296A68
+:1053E000009836E00121F6E702A8009001AB2246C2
+:1053F00029463046FFF7B7FC5EE03078092800D038
+:10540000FFDF1420ADF80400ADF808701CB3A98BC1
+:10541000A181A4F81290A4F8109084F80E804BE0BB
+:1054200030780A2800D0FFDF288CADF808701430DF
+:10543000ADF804007CB10421A173A98BA181E98B93
+:105440002182298C618200E032E02A8C04F1140070
+:10545000696A15F0EFFC2FE030780B2800D0FFDFF1
+:105460001420ADF80400ADF8087004B30521A17351
+:10547000A4F80C90A4F81090A4F812901CE000E09E
+:1054800008E002A8009001AB224629463046FFF70B
+:105490000CFD11E00D203A21ADF80400ADF8081024
+:1054A00034B1A4F80680A4F8089084F80C9003E0C6
+:1054B000ABF8000014E0FFDFBDF80400ABF800001B
+:1054C00074B1BDF808002080BDF804006080287E1B
+:1054D000032805D0102803D0112801D086F80090A9
+:1054E0000020BDE8FE8F2DE9F84356880F46804620
+:1054F00015460521304608F0A0FA040000D1FFDF70
+:10550000A41D33462A4639464046009404F064FA06
+:10551000BDE8F8832DE9F0438DB00D461446814671
+:1055200007A9FFF772FD002814D14FF6FF76012777
+:105530004FF420588CB103208DF800001020ADF8F6
+:10554000140008A802460690204605A909F069FF44
+:1055500078B107200DB0BDE8F0830820ADF80C50FD
+:105560008DF812708DF80000ADF80E60ADF8108067
+:105570000CE00798A1780171218841808DF81270A4
+:10558000ADF80C50ADF81080ADF80E606A46012100
+:105590004846079BFFF751FDDCE708B501228DF86F
+:1055A000022042F60202ADF800200A4602236946B4
+:1055B000FFF7BCFD08BD08B501228DF8022042F6B8
+:1055C0000302ADF800200A4603236946FFF7AEFD4B
+:1055D00008BD00B587B079B102228DF800200A8895
+:1055E000ADF80C204988ADF80E1000236A4604215E
+:1055F000FFF723FD07B000BD1020FBE709B106232C
+:1056000094E50720704770B588B00D4614460646ED
+:1056100007A9FFF7FAFC00280ED17CB10620ADF8EF
+:105620000C508DF80000ADF80E40079B6A4607212C
+:105630005C803046FFF701FD08B070BD05208DF895
+:105640000000ADF80C50F0E700B587B059B1072362
+:105650008DF80030ADF80C20049100236A46082133
+:10566000FFF7EBFCC6E71020C4E770B5002488B054
+:10567000172391B10A78062A20D2DFE802F01F042E
+:10568000041503171523DB1E9DB2CB880BB18E6862
+:105690001EB1AB4203D90C20CEE71020CCE7042A80
+:1056A00004D08B8853B901E00620C5E7012A13D046
+:1056B000022A05D0042A1CD0052A2AD00720BBE7DD
+:1056C00009228DF800204A88ADF80C20CA88ADF870
+:1056D0000E208968049123E00C228DF800204A886E
+:1056E000ADF80C20CA88ADF80E2089680924049111
+:1056F00016E00D228DF800204A88ADF80C208A882B
+:10570000ADF80E20CA88ADF8102089680A240591EA
+:1057100006E00E228DF8002049788DF80C100B243D
+:1057200000236A462146FFF788FC85E700B587B06D
+:105730000F228DF80020ADF80C1000236A461946A0
+:10574000FFF77BFC56E700B587B071B102228DF8F8
+:1057500000200A88ADF80C204988ADF80E1000230F
+:105760006A460521FFF769FC44E7102042E7000084
+:1057700018B1817801293CD101E0102070470188DF
+:1057800042F60213C81A4FF48072994233D01CDCDF
+:1057900042F60103A1EB030099422CD00CDCF9B1D5
+:1057A000B1F5C05F27D06FF4C050081823D0A0F522
+:1057B0007060FF381DD11EE001281CD002281AD0CD
+:1057C000FF2818D0904214D115E0904213D008DC85
+:1057D000012810D002280ED0FE280CD0FF2808D1B6
+:1057E00009E0A0F58070013805D0012803D0022817
+:1057F00001D0002070470F2070470B2826D008DC0E
+:105800001BD2DFE800F01C2025251A252923252797
+:105810001E0011281CD008DC0C2817D00D281DD024
+:105820000F2815D0102808D110E0822809D084282C
+:1058300010D0852810D0872812D003207047002070
+:1058400070470520704743F20300704707207047F8
+:105850000F20704704207047062070470C207047C7
+:105860004FF45050704707280DD2DFE800F00406CF
+:10587000040C0C080A000020704711207047072014
+:1058800070470820704703207047007810F00F021F
+:1058900004D0012A05D0022A0CD110E0000909D158
+:1058A0000AE00009012807D0022805D0032803D008
+:1058B000042801D007207047087000207047062098
+:1058C000704705282AD2DFE800F003070F171F00F2
+:1058D000087820F0FF001EE0087820F00F00401C40
+:1058E00020F0F000103016E0087820F00F00401C87
+:1058F00020F0F00020300EE0087820F00F00401C6F
+:1059000020F0F000303006E0087820F00F00401C56
+:1059100020F0F000403008700020704707207047EA
+:1059200038B50C46050041D06946FFF7AEFF0028A8
+:1059300019D19DF80010607861F30200607069462B
+:10594000681CFFF7A2FF00280DD19DF800106078B9
+:1059500061F3C5006070A978C1F34101012903D04A
+:10596000022905D0072038BD217821F0200102E06E
+:10597000217841F020012170410704D0A978C9089D
+:1059800061F386106070607810F0380F07D0A97846
+:10599000090961F3C710607010F0380F02D1607808
+:1059A000400603D5207840F040002070002038BD2C
+:1059B00070B504460020088015466068FFF7B0FF08
+:1059C000002816D12089A189884211D86068807882
+:1059D000C0070AD0B1F5007F0AD840F20120B1FB20
+:1059E000F0F200FB1210288007E0B1F5FF7F01D92B
+:1059F0000C2070BD01F201212980002070BD10B57E
+:105A00000478137864F3000313700478640864F373
+:105A1000410313700478A40864F3820313700478BC
+:105A2000E40864F3C30313700478240964F30413D3
+:105A300013700478640964F34513137000788009C7
+:105A400060F38613137031B10878C10701D1800764
+:105A500001D5012000E0002060F3C713137010BDD2
+:105A60004278530702D002F0070306E012F0380F25
+:105A700002D0C2F3C20300E001234A7863F30202BA
+:105A80004A70407810F0380F02D0C0F3C20005E031
+:105A9000430702D000F0070000E0012060F3C502D8
+:105AA0004A7070472DE9F04792B00D00804613D040
+:105AB000B8F1000F14D01221284615F032FA03AACB
+:105AC000FF21012005F0D3FB0024264637464FF482
+:105AD00020596FF4205A6DE0102012B0BDE8F08715
+:105AE0000720FAE79DF8160001280AD1BDF8140036
+:105AF00048450BD010EB0A000AD001280CD0022830
+:105B00000CD0042C0ED0052C0FD10DE0012400E0A8
+:105B10000224BDF8126008E0032406E00424BDF866
+:105B2000127002E0052400E00624BDF81210414581
+:105B300040D12C7486B34FF007090DF134080EAA3A
+:105B4000CDF80090CDE9012810230022FF21304636
+:105B500005F029FCF0B9BDF834002A46C0B20EA900
+:105B600009F040FCB0B9AE81B7B108AECDF80090F5
+:105B7000CDE9016813230022FF21384605F013FC0C
+:105B800040B9BDF83400F11CC01EC0B22A1D09F096
+:105B900029FC10B10320A0E70AE0BDF82100E8814C
+:105BA000062C05D19DF81600A872BDF814002881B6
+:105BB000002092E703A805F062FB002892D0FFF7CF
+:105BC0001CFE8AE72DE9F0438BB00E46DDE9129802
+:105BD00005461C461746142103A815F0C4F90120F8
+:105BE0008DF810008DF80C008DF81180ADF8147050
+:105BF00064B1A178C90709D08DF81600E088ADF826
+:105C00001A00A088ADF81800A068079001F0C6FD42
+:105C1000040025D06580002009A9CDE900101722D5
+:105C2000034601460290ADF82020284602F03DFBD5
+:105C3000002812D108368DE8700008AA494603A84A
+:105C4000099B04F042FE06466078000701D501F08A
+:105C500083FD5EB13046FFF706FE0BB0BDE8F08372
+:105C600013212846FCF7BEFD0320F6E709980090B3
+:105C7000BDF8203004220021284602F098FCECE711
+:105C800070B506468AB000200D46059007240490A2
+:105C9000069003A900940790CDE901010246102364
+:105CA0002946304605F07FFB68B904A9009108A891
+:105CB000CDE90140BDF80C3000222946304605F000
+:105CC00081F9002801D0FFF798FD0AB070BD05F0FA
+:105CD0003CB82DE9FC470546002700780C46B8463D
+:105CE000B9460C2873D2DFE800F0B8060D2FCE5F5E
+:105CF0005F7F96B49AA504B1FFDF288980B201F0D6
+:105D0000BFFEABE0A888042180B2814607F095FE73
+:105D1000064604B1FFDF06B9FFDF494606F1080079
+:105D200004F03CFA01F03AFD040008D0607840F03D
+:105D300008006070A4F8029001F00EFD8FE01321BE
+:105D40004846FCF74FFD9EE004B9FFDF6088042160
+:105D500007F073FE060000D1FFDFA6F800900020D8
+:105D600029791EE005EBC0029268D3B25FEA037C9A
+:105D700007D5DB0605D505EBC10030F8020C3080F5
+:105D800007E0120A52060AD5307105EBC000C08840
+:105D900070806078022740F0080060705EE0401C70
+:105DA000C0B28142DED859E0E888ADF8000004B9FD
+:105DB000FFDF9DF80100000604D52878062807D0EB
+:105DC00005282AD0607840F00800607046E044E082
+:105DD0006088042107F031FE060000D1FFDF86F85D
+:105DE0000490A888708018E004B9FFDF608804215F
+:105DF00007F023FE060000D1FFDF06F1080004F0E3
+:105E0000F8FF90F0010F02D1E879000626D56088EE
+:105E10000227F080D6E704B9FFDF0227D2E704B9F2
+:105E2000FFDF022761880122204601F06DFE4FF05E
+:105E30000108C7E7A88986B204B1FFDF686800904F
+:105E40002889ADF8040001226946304601F077FE4A
+:105E500004E0002CB6D1FFDFB4E7FFDF9CB160782F
+:105E6000000710D5B8F1000F0DD12078582220F08E
+:105E70000F00001D20F0F00080302070294604F152
+:105E8000180015F01CF83846BDE8FC873EB50C003C
+:105E900008D06B4601AA002105F0F2FA20B1FFF705
+:105EA000ACFC3EBD10203EBD00202080A0709DF8BF
+:105EB000050002A900F00700FFF703FD50B99DF8A7
+:105EC000080020709DF8050002A9C0F3C200FFF78A
+:105ED000F8FC08B103203EBD9DF8080060709DF8F5
+:105EE0000500C109A07861F30410A0709DF80510A9
+:105EF000890961F3C300A0709DF80410890601D5DB
+:105F0000022100E0012161F342009DF8001061F3DD
+:105F10000000A07000203EBD70B5144606460D4638
+:105F200051EA040005D075B108460BF087FD78B939
+:105F300001E0072070BD2946304605F0FCFA10B19B
+:105F4000BDE8704059E454B120460BF077FD08B12C
+:105F5000102070BD21463046BDE8704096E7002015
+:105F600070BD2DE9FE4F05460C46007E0A310091BA
+:105F700004F108010027029190460C31821E3E4632
+:105F8000BB464FF0010A0191082A7CD2DFE802F0FB
+:105F9000F7047B32327EBCF86888042107F04DFD9F
+:105FA0005FEA000900D1FFDFB9F8000010B1522705
+:105FB0000726ECE051271026002C7CD06888A080B2
+:105FC00084F806A099F80400002205EBC0000099AF
+:105FD000C08BFFF7A1FF00286ED199F8040005EBF4
+:105FE000C000C08B208199F8040005EBC000408CF4
+:105FF000E081E6E0B5F82290062822D1E87F00068D
+:106000001FD5512709F1140086B2002CD5D0A88BDA
+:1060100000220099FFF780FF002873D16888A080D4
+:106020000220A071A88B208184F80EA0288C2082E9
+:10603000A4F812904A46696ADDF8040014F0FAFEEA
+:10604000BFE0502709F1120086B2002C33D0A88B94
+:1060500000220299FFF760FF002853D16888A080D2
+:10606000A88BE080287E06280ED002202073288C82
+:10607000E081E87F4A46C0096073A4F8109004F1FB
+:106080001200696ADAE79BE00120EFE768880421E3
+:1060900007F0D3FCB5F822A05FEA000900D1FFDFCA
+:1060A00009F1080004F0A5FE90F0010F02D1E87F8D
+:1060B000000626D501E076E024E00AF1140051271D
+:1060C00086B2002C70D06888A080A88B002200992E
+:1060D000FFF722FF002815D10220A071A88B208194
+:1060E0000420A073288C2082A4F812A05246696A6A
+:1060F000019814F09FFE89F804B0A98BA9F802104A
+:106100005FE00320BDE8FE8F6888FBF78BF98246CD
+:106110006888042107F091FC8146BAF1000F00D194
+:10612000FFDFB9F1000F00D1FFDFB9F80600A0F5DD
+:106130007F41FF3902D05127142601E05027122653
+:106140008CB36888A080502F06D00220A071287FD1
+:10615000029901F016F934E0287FA11D01F011F930
+:106160009AF82210CDE9001BB9F8022068880023B4
+:106170004946FFF727FD0028C4D122E000E016E0E1
+:10618000FE49A88BC988814205D15427062654B1FF
+:106190006888A08015E05327082624B16888A0806D
+:1061A000A88BE0800DE0FFE7A8F800600EE055271F
+:1061B0000726002CF8D0A88BA08084F806B000E059
+:1061C000FFDFA8F800600CB127806680002099E707
+:1061D000EA4900200870704730B587B00C4607F0D8
+:1061E000F5FB0546FF2800D1FFDF0020208020714D
+:1061F00060804FF6FF70E080294604F1080003F04C
+:10620000BFFF02AA2946012005F031F81AE000BFBD
+:106210009DF80B00000715D5BDF80E002946FFF7C5
+:106220002FFD9DF80B00FF2340F010008DF80B00B0
+:10623000BDF80B00ADF80400BDF80E002946019A28
+:1062400005F047F902A805F01AF80028E0D007B0D9
+:1062500030BD0A46014602F1080003F0A5BF70B543
+:106260000546042107F0E9FB040000D1FFDF2946C1
+:1062700004F10800BDE8704003F090BF2DE9F04143
+:106280008AB00D468046FBF7CDF8060006D0307880
+:10629000222806D208200AB0BDE8F08143F20200AD
+:1062A000F9E70421404607F0C8FB07460DB1A8886E
+:1062B00078B101208DF8140002208DF81800002418
+:1062C0008DF819403DB1A888ADF8200028680790E6
+:1062D00004E00920DFE7ADF82040079401F05EFA02
+:1062E000050026D0A5F8028004A8CDE900041722F5
+:1062F0000023ADF80C2019464046029401F0D5FF6A
+:106300000028C8D107F108000095CDE9018096F872
+:10631000221003AA05A8049B04F0D7FA0446687863
+:10632000000701D501F018FA4CB12046FFF79BFA9F
+:10633000B1E713214046FCF755FA0320ABE7049878
+:106340000090BDF80C3004220021404602F02FF9E5
+:106350004FF6FF71F9809EE72DE9FF5F83460E9EA1
+:106360009846914677888A463846FBF75BF805469B
+:106370000421384607F061FB044605B9FFDF04B984
+:10638000FFDF0834CDE90274CDE9008695F82210CC
+:106390004B465246584603F037FF04B0BDE8F09F25
+:1063A0002DE9F04F99B004464FF000087348ADF85E
+:1063B0004C80ADF82480ADF84880A0F80480ADF89A
+:1063C0000C80ADF81080ADF81880ADF8148000781E
+:1063D00016460D464746012809D0022807D0032853
+:1063E00005D0042803D0082019B0BDE8F08F20465E
+:1063F0000BF0E2FAD0BB28460BF0DEFAB0BB6068C7
+:106400000BF025FB90BB606848B160892189884208
+:1064100002D8B1F5007F01D90C20E5E7804608AA33
+:1064200004A92846FFF7C4FA0028DDD168688078FF
+:10643000C0F34100022808D19DF8110010F0380F78
+:1064400003D028690BF0FAFA80B903A92069FFF795
+:1064500067FA0028C8D1206950B1607880079DF89C
+:106460000D0000F0380002D5E8B301E011E0D0BB28
+:106470009DF80C0080060ED59DF80D0010F0380F29
+:1064800003D060680BF0DAFA18B960680BF0DFFA35
+:1064900008B11020A8E705A96069FFF741FA0028B4
+:1064A000A2D1606940B19DF8150000F007010129F3
+:1064B0003BD110F0380F38D006A9A069FFF730FAA9
+:1064C000002891D19DF8140080062ED49DF8180064
+:1064D00080062AD4A06950B19DF8190000F0070188
+:1064E000012922D100E020E010F0380F1DD0E06833
+:1064F00018B10078C8B11C2817D20CAA611C20461C
+:10650000FFF77DFA0120B94660F30F27BA46074628
+:106510008DF8460042F60300ADF844000DF1330259
+:1065200015A9286808F07DFF08B107205CE79DF8F1
+:10653000540014A9CDF80090C01CCDE9019100F0E1
+:10654000FF0B00230BF20122514611A804F0D7FDE6
+:10655000E8BBBDF850000B9008492A892869091D3D
+:106560000092CDE901016B89BDF8202028680499CB
+:1065700004F0C5FD01007CD1207801E05803002023
+:10658000C1064FF0020A01D480062BD5ADF81C904D
+:10659000606950B905A904A8FFF762FA9DF81500D3
+:1065A00020F00700401C8DF815009DF814008DF8B0
+:1065B000467040F0C8008DF8140042F60210ADF8A5
+:1065C000440009A907AA0023CDF800A000E01CE0C0
+:1065D000CDE9012140F2032211A8059904F08FFDB5
+:1065E000010046D1F8484D464FF007098088ADF8C4
+:1065F00031000CA9CDE900195B4600220295FF216C
+:10660000BDF8500004F0DEFC10B1FFF7F6F8EBE641
+:106610009DF83000000625D52946012060F30F21A2
+:106620008DF846704FF42450ADF84400ADF8285072
+:1066300062789DF82800002362F300008DF828009E
+:106640006278520862F341008DF828000AAACDF85A
+:1066500000A0CDE9012540F2032211A804F04FFD6E
+:10666000010006D1606850B3206970B903A904A87D
+:1066700000E07DE0FFF7F4F96078800705D49DF82D
+:106680000D0020F038008DF80D008DF8467042F6B0
+:106690000110ADF84400208940F20121B0FBF1F275
+:1066A00001FB1202606812ABCDF80080CDE9010356
+:1066B000002311A8039904F022FD010058D120788D
+:1066C000C00729D0ADF81C50A06950B906A904A88C
+:1066D000FFF7C6F99DF8190020F00700401C8DF85F
+:1066E00019009DF818008DF8467040F040008DF8B4
+:1066F000180042F60310ADF8440013A907AACDF81C
+:1067000000A0CDE90121002340F2032211A806993F
+:1067100004F0F5FC01002BD1E06868B329460120A4
+:1067200060F30F218DF8467042F60410ADF8440076
+:10673000E068002302788DF8582040788DF85900E1
+:10674000E06816AA4088ADF85A00E06800798DF834
+:106750005C00E068C088ADF85D00CDF80090CDE940
+:1067600001254FF4027211A804F0C9FC010003D006
+:106770000B9800F019FE37E693480321017056B1DB
+:1067800080883080BDF848007080BDF82400B0805B
+:10679000BDF84C00F080002026E670B501258AB0D7
+:1067A00016460B46012802D0022816D104E08DF8C7
+:1067B0000E504FF4205003E08DF80E5042F60100C9
+:1067C000ADF80C0063B10024601C60F30F2404AA30
+:1067D00008A9184608F025FE20B107200AB070BDB0
+:1067E0001020FBE704A99DF820207748CDE900217F
+:1067F000801C02900023214603A802F2012204F02B
+:106800007EFC10B1FEF7F9FFE8E76F480EB1418852
+:10681000318005700020E1E770B594B00446012690
+:106820008DF83E6041F60100ADF83C0012AA0FA9B8
+:106830003046FFF7B2FF002848D12078624CC007ED
+:106840004FF0000544D01C2102A814F08CFB9DF8E9
+:1068500008008DF83E6040F020008DF8080042F6F8
+:106860000520ADF83C000E959DF83A00119520F0FA
+:106870000600801C8DF83A009DF838006A4620F02A
+:10688000FF008DF838009DF8390009A920F0FF00BD
+:106890008DF839000420ADF82C00ADF830000EA8BA
+:1068A0000A9011A80D900FA80990ADF82E5002A8DB
+:1068B000FFF776FD002809D1BDF80000E080BDF8A3
+:1068C00004002081401C60812570002014B070BD40
+:1068D000E5802581BDF84800F4E72DE9F74F8B46A8
+:1068E000394900269EB00A78012A04D0022A02D033
+:1068F000082021B079E54A88824201D00620F8E7D5
+:1069000089465A4501D10720F3E701214FF00008DD
+:106910008DF86610ADF8401042464FF6FF71531CDB
+:1069200063F30F220492ADF84210ADF84A10FF2035
+:1069300042F6020A8DF86A801AAA8DF84800ADF86E
+:1069400064A0ADF868801192CDF84C8010A804F0D6
+:10695000BDFC0024254627460BAA072110A804F0F9
+:10696000B8FC78B1822857D184B37DB3ADF85C40D0
+:106970009DF85600ADF85E508DF80C8017AC0128DC
+:106980005ED065E09DF832000FB3012853D1BDF809
+:10699000301051451DD116AA07A907208DE8070020
+:1069A000BDF82E0010230022FF2104F0FCFC98BB50
+:1069B000BDF85800042801D0062847D1BDF81C10A6
+:1069C000594538D10F2094E75803002036E00128BC
+:1069D00031D1BDF83000B0F5205F03D042F601019F
+:1069E000884228D1B9F80210BDF82E00814201D1A9
+:1069F000012700E0002704B17DB158451BD116AB3B
+:106A000007AA07218DE80E00044610230022FF216B
+:106A100004F0C9FC00B902E02DE035460BE0BDF8FA
+:106A20005800022801D0102810D1C0B215AA07A919
+:106A300008F0D8FC50B9BDF82E608DE7052058E766
+:106A400003A915A8221D08F0ECFC08B1032050E7AB
+:106A50009DF80C000023001DC2B220988DF80C2078
+:106A60000092CDE9014019A8049904F048FB10B93F
+:106A7000022289F80020FEF7C0FE3AE710B50B4667
+:106A8000401E86B084B203AA00211846FEF7B7FF65
+:106A900004AA072103A88DE8070001230022FF2193
+:106AA000204604F08FFA0446BDF81000012800D0FB
+:106AB000FFDF2046FEF7A1FE06B010BDF0B5FC4F8B
+:106AC000044687B038780E46032804D0042802D044
+:106AD000082007B0F0BD04AA03A92046FEF768FF0E
+:106AE0000500F6D160688078C0F3410002280AD121
+:106AF0009DF80D0010F0380F05D020690AF09EFFB8
+:106B000008B11020E5E7208905AA21698DE8070072
+:106B10006389BDF810202068039904F0F0FA10B1E1
+:106B2000FEF76BFED5E716B1BDF8140030800420E7
+:106B300038702846CDE738B50C00054609D000234B
+:106B40006A46FF2104F09CFC28B100BFFEF755FE09
+:106B500038BD102038BD69462046FEF7E1FE00280A
+:106B6000F8D1A078FF2100F001032846009A04F034
+:106B7000B0FCEBE77FB5144603AA07250292CDE9E6
+:106B800000350A462388FF2104F01CFABDF80C10DA
+:106B90002180FEF732FE04B070BD2DE9F04192B0C5
+:106BA0004FF000050C000746ADF8105019D0E06812
+:106BB00028B1A068A8B10188ADF81010058038464A
+:106BC000FAF730FC88B1007822286AD3384606F0FC
+:106BD000FDFE80460421384606F02FFF060008D14E
+:106BE00006E0102012B0BDE8F08143F20200F9E7A0
+:106BF000FFDFA078012803D0022801D00720F1E7A9
+:106C0000208838B1401C80B206AA414604F02FFB10
+:106C100038BB02E043F20300E4E706A804F02FFBD0
+:106C20009DF822204FF45051012A09D1BDF82020AF
+:106C3000A2F52453023B03D1822801D088B901E098
+:106C40000846CFE7E06898B1072204A9CDE9000221
+:106C50000291A2882088BDF81030FF2104F0B2F91B
+:106C600010B1FEF7CAFDBDE7A168BDF810000880AD
+:106C70009DF81B00C00602D543F20140B2E70A9816
+:106C800018B1BDF82400022801D00320AAE717227A
+:106C90000A98ADF80C20A1780078012903D080076C
+:106CA00010D408209EE7C007FBD0002307213846F8
+:106CB00001F07EFA18B14FF00708022005E043F218
+:106CC00004008FE74FF0010803208DF83000208882
+:106CD000ADF834000BA8CDE9000500230295BDF8FE
+:106CE0000C204146384601F0E0FA002887D1CDE972
+:106CF00000570836029603AA07210CA80B9B03F045
+:106D0000E4FD10B1FEF7AFFD6CE70B980090BDF805
+:106D10000C3004224146384601F049FC62E770B568
+:106D2000064615460C460846FEF722FD002805D10A
+:106D30002A4621463046BDE870402EE570BDCCE5C0
+:106D400070B51E4614460D0009D044B1616831B1DA
+:106D500038B157494988814203D0072070BD1020BF
+:106D600070BD2068FEF704FD0028F9D132462146A7
+:106D70002846BDE87040FFF713BB70B515460C0000
+:106D800006D038B14A498988814203D0072070BDB6
+:106D9000102070BD2068FEF7EBFC0028F9D12946D1
+:106DA0002046BDE8704089E670B5054686B00E46BF
+:106DB000144610460AF024FEF0BB60680AF047FE55
+:106DC000D0BBA5F57F40FF3803D02846FAF72AFB51
+:106DD000A0B1284606F0FAFD054630466946FEF7A2
+:106DE00061FE00280CD19DF810100F20082936D222
+:106DF000DFE801F008060606060A0A0843F2020068
+:106E000006B070BD0320FBE79DF80210012908D1F0
+:106E1000BDF80010B1F5C05FF2D06FF4C052D1429E
+:106E2000EED09DF80610012905D1BDF80410A1F59A
+:106E300028510529E4D900E022E09DF80A10012933
+:106E40000ED1BDF80810B1F5245FD9D0A1F52451B9
+:106E50000239D5D00129D3D0022901D1D0E7FFDFF3
+:106E6000606878B9002305AA2946304604F008FB7B
+:106E700010B1FEF7C2FCC3E79DF81400800601D4F0
+:106E80001020BDE76188224630466368FFF772FE36
+:106E9000B6E72DE9F043074685B08946144610460B
+:106EA0000AF0AEFD30B1102005B0BDE8F08300005F
+:106EB00058030020384606F089FD4FF6FF76054658
+:106EC000B74201D0FF2D0AD00146002304AA48464C
+:106ED00004F0D6FA30B100BFFEF78FFCE4E743F2CE
+:106EE0000200E1E79DF81000C00602D543F2014020
+:106EF000DAE74FF0070803A90027CDF80080CDE9B5
+:106F00000171628833462946484604F04CFA06006F
+:106F100012D160680AF074FD58B96068CDF800803D
+:106F2000CDE90107238862882946484604F03BFAE8
+:106F30000646BDF80C0020803046CDE739B1FD4B48
+:106F40000A881B899A4202D843F20300704724E65C
+:106F500010B586B0F74C0423ADF81430E3883BB18C
+:106F600024898C4201D2914204D943F20300A3E563
+:106F70000620A1E5ADF81010002100910191ADF8B7
+:106F8000003002218DF8021005A9029104A9039195
+:106F9000ADF812206946FFF700FE8DE52DE9FC47AC
+:106FA00081460F4608460AF007FDD0BB4846FAF76F
+:106FB00039FA5FEA000811D098F80000222832D38D
+:106FC000002317221946484601F0F2F850B1042177
+:106FD000484606F032FD060007D105E043F2020004
+:106FE000BDE8FC871120FBE7FFDF06F1080003F096
+:106FF000F1F805463878012803D0022804D007208C
+:10700000EEE7A8070FD502E015F0340F0BD0B879E2
+:107010003C1DC00709D0E08838B1A0680AF0CCFC5C
+:1070200018B11020DCE70820DAE73A782088002140
+:1070300028B3A0F201130721112B18D20CD2DFE8DC
+:1070400003F00B090D0B1D0B121D100B0B1D1D1D4D
+:107050001D0B1D00022A11D10846C1E7012AFBD0F1
+:107060000CE0EA0600E0AA06002AF5DA06E0A0F540
+:10707000C0721F2A02D97D3A022AEDD8C1B298F80F
+:107080002200CDE900017288234631464846FEF7CA
+:1070900099FDA5E72DE9FF4F89B01E4615460C4620
+:1070A0004FF000080F460998FAF7BCF930B10078A4
+:1070B000222806D208200DB0BDE8F08F43F202006E
+:1070C000F9E7B00801D00720F5E7032E00D100262C
+:1070D000099806F07BFC83464FF6FF7ACCB1022D6F
+:1070E0006AD320460AF0B3FC30B904EB0509A9F1D4
+:1070F00001000AF0ACFC08B11020DCE7AD1EAAB21A
+:107100002146504604F0CCFA39F8021C884253D18B
+:10711000ADB28848B10702D50189491C00E00121C0
+:107120001FFA81F9F10701D0068900E0564603AA4B
+:107130005946484604F09BF84FF0070A0BE0788860
+:10714000102839D808F1040108441FFA80F8A8452E
+:1071500032D804EB08078FB339884945EFD34DE0A7
+:107160009DF80F100A0749D54CB304EB080908F144
+:107170000402B9F8023097B2102B1DD8DA19AA42CE
+:107180001AD8B9F80020904216D1C80618D5E119CE
+:10719000CDE9001A08AA0292B9F800000022594667
+:1071A00003F010FF10B1FEF728FB84E7B9F80200E6
+:1071B000BDF82010884203D00B207CE71EE005E0DC
+:1071C000B9F8020038441FFA80F806E0C90604D571
+:1071D0005946FEF755FD00288FD19DF80F00FF237B
+:1071E00020F010008DF80F00BDF80F00ADF8000082
+:1071F000BDF812005946009A04F06BF903A804F098
+:107200003EF818B9BDF81200B042A9D90421099876
+:1072100006F013FC040000D1FFDF22885AB10025DC
+:10722000CDE900A52B4621460998FEF7CBFC0028A6
+:10723000BBD125803FE700203DE72DE9F04F89B025
+:107240001E4617000D464FF000041BD0B10802D0B7
+:10725000072009B030E7032E00D1002606F0B6FB68
+:107260008046FF2805D07DB128460AF0E7FB48B9E3
+:1072700002E043F20200ECE73988681E08440AF095
+:10728000DDFB08B11020E4E72A49B00701D54889A1
+:1072900000E00120F2074FF6FF7902D04989491E2C
+:1072A00000E049468EB204AA414603F0E0FF4FF0E9
+:1072B000070A0DF10C0B33E09DF8131009072FD5C9
+:1072C0000023CDE900A3CDF808B04B46002241468B
+:1072D00004F069F8E8B9F5B1BDF80C103A8821441A
+:1072E0002819091D8A4231D3BDF8162020F8022B37
+:1072F000BDF80C2020F8022BCDE900A0CDF808B095
+:10730000BDF81600BDF80C300022414604F04BF8E1
+:1073100008B103209DE7BDF80C002044001D84B295
+:1073200004A803F0ACFF38B1822809D0FEF765FA53
+:107330008FE7000058030020BDF81600B042BBD90B
+:1073400034B175B13988A01C814203D20C2080E78A
+:1073500005207EE722462946484604F0A1F929196E
+:107360000880A41C3C80002073E710B504460AF096
+:1073700047FB08B1102010BD114840892080002033
+:1073800010BD70B50C4605460E21204613F0C9FD10
+:10739000002020802DB1012D01D0FFDF70BD06201F
+:1073A00000E00520A07170BD10B50C4603F02EFF63
+:1073B00000B1FFDF2046BDE81040FEF71EBA000016
+:1073C000580300204FF0E0224FF400410020C2F8A3
+:1073D000801120490870204990020860704730B53C
+:1073E0001C4D04462878A04218BF002C02D000286B
+:1073F00018BFFFDF2878A04208BF30BD2C701749A6
+:10740000154A0020ECB1164DDFF858C0131F012CAF
+:107410000DD0022C1CBFFFDF30BD086003200860C8
+:10742000CCF800504FF400001060186030BD0860C8
+:1074300002200860CCF800504FF0407010601860D7
+:1074400030BD086008604FF06070106030BD00B55E
+:10745000FFDF00BD1600002008F5014000F50040E8
+:107460006403002014F5004010B50446007894B081
+:10747000022805D0012803D043F2050014B010BD46
+:10748000A07828B1032803D8607808B1032801D96F
+:107490000720F3E73F208DF800002078022801D074
+:1074A000012000E000208DF80200607800F095FDDA
+:1074B000C01D8DF80300A078012800D1022000F043
+:1074C0008CFD8DF80400607800F087FD8DF80500D4
+:1074D000A07800F082FD8DF806002078012804D104
+:1074E0009DF80300401C8DF8030009A9684604F0CC
+:1074F00060F800B1FFDF0020C0E72DE9FF4F8DB03D
+:10750000FA49DDE91AB90600D1E902010396CDE98D
+:107510000901507A117A9A4608441546C7B20DD02F
+:107520000024F01D20F00700B04200D0FFDF2888C3
+:107530000399401C1FFA80F814B107E00124F0E71A
+:1075400008F0FF0007F0F4FE00B1FFDF03993A46B0
+:1075500001EB0810C01C20F00301D5F81080039146
+:107560003CB9002008701FFA88F003F0F2FC00B16B
+:10757000FFDF0399234601EB08000390A87A297ADC
+:107580003A460844C1B203A800F071FD0398C01C3C
+:1075900020F003000390697A00912B7AAA7A04B153
+:1075A000002001A906F025F900B1FFDFBDF80410A5
+:1075B0000398CDE900B90844C01C20F003001C99D1
+:1075C000CDE902103A4604B10020534605A906F061
+:1075D0009BFA00B1FFDFBDF8141003980844C01DEA
+:1075E00020F007000E99821B03900A60002C35D111
+:1075F000C04ABF491160111D401E086001232C22A2
+:107600000BA9BD4806F076F800F0F1FC00211E221F
+:10761000084602F053F8FAF72FFE00F034FFFEF7A9
+:10762000D7FD09AB00220521B4A0FBF7ECFA00B1AD
+:10763000FFDF05F10C00FFF7EFF800B1FFDF4FF4BB
+:107640007F71B04813F08FFCAE48012180F8F91328
+:10765000022180F8FA13062180F8FB1311B0BDE86F
+:10766000F08F10B5A74CA078092800D3FFDF207851
+:10767000C0EBC00004EB001010F8041F21F0FF0164
+:107680000170417821F00701C91C21F018014170F7
+:107690000121E17010BD2DE9F04105460C4600279F
+:1076A0000078052190463E46B1EB101F00D0FFDF69
+:1076B000287E58B1012810D0FFDF00BFA8F8006075
+:1076C0000CB1278066800020BDE8F08102270926E2
+:1076D0007CB1A88BA080A87F09E00327142644B1C1
+:1076E0006888A080286AE060A88C2082287F2072A9
+:1076F000E4E7A8F80060E6E700B5017895B001F08E
+:1077000001018DF80210417801F001018DF803109C
+:107710000178C1F340018DF804104178C1F34001B4
+:107720008DF80510017889088DF8061041788908D0
+:107730008DF8071081788DF80810C1788DF8091040
+:1077400000798DF80A003E208DF8000009A96846EE
+:1077500003F02FFF15B000BD70B56A4CE07800282B
+:107760001BD020780025C0EBC00004EB001040794E
+:1077700000F00700011991F8F803401E81F8F803A2
+:107780002078401CC0B22070092800D12570A07854
+:10779000401CA07009F0B1FCE57070BD594890F82C
+:1077A000FB03002800D05CE770472DE9F043554DFE
+:1077B0009BB00026D5F8F40368B1FFF7EFFF00286F
+:1077C00075D07022D5F8F41313F079FBFFF7C4FFDE
+:1077D000C5F8F463EEE795F8F903002867D0FFF7E2
+:1077E00040FF0446444805F0B6FF606000B9FFDF83
+:1077F000606803F029FF88B12046FAF7B8F860788E
+:10780000010706D520F00700401C6070FFF7A4FFB9
+:10781000D0E73948616805F0A7FFCBE736486168D3
+:1078200005F0A2FF01A800F05BFC00286CD1032149
+:10783000BDF8040006F001F98046BDF8040006F02A
+:1078400062FA0746B8F1000F00D1FFDFD8F8040054
+:1078500010B10078FF2857D0FFF703FF04463846E1
+:10786000211D05F0B0FE00B9FFDFD4F8049089F8BF
+:107870000060BDF804006080204600F0EAFE384653
+:1078800005F0CDFE00B9FFDF3B208DF81000BDF8FC
+:107890000400ADF8120004A805F050FB0EA804F097
+:1078A0003CF96078010703D4C00607D409E02BE057
+:1078B00020F00700801C6070FFF74EFFC8F80490AE
+:1078C00078E7D8F8040038B10178491C11F0FF01BD
+:1078D00001709DD1FFDF6DE700221146384600F0B0
+:1078E0007AFB002894D1FFDF64E7000014B30100A5
+:1078F0000000002000060240B40700206E5246350A
+:1079000078000000B80300201BB0BDE8F08310B57C
+:10791000FC4CA0600868E060AFF2711001F031FE2D
+:10792000607010BDF74900200870704730B50546FB
+:107930004FF080500C46D0F8A41095B0491C05D1EA
+:10794000D0F8A810C9430904090C08D050F8A01FAA
+:1079500001F0010129704168216080680EE02B2050
+:107960008DF8000009A9684603F023FE00B1FFDF8F
+:10797000012028700A982060BDF82C00A08028788B
+:10798000002803D0607940F0C000607115B030BDB0
+:10799000F0B54FF080540746D4F8800095B00D46FE
+:1079A0002B26401C0BD1D4F88400401C07D1D4F8FE
+:1079B0008800401C03D1D4F88C00401C0BD0D4F8B4
+:1079C00080003860D4F884007860D4F88800B8600B
+:1079D000D4F88C0016E08DF82C6069460BA803F0F3
+:1079E000E8FD00B1FFDF01983860029878608DF8FB
+:1079F0002C6069460BA803F0DCFD00B1FFDF0198A5
+:107A0000B8600298F860D4F89000401C0BD1D4F80C
+:107A10009400401C07D1D4F89800401C03D1D4F83E
+:107A20009C00401C08D054F8900F28606068686083
+:107A3000A068A860E06816E08DF8006009A96846B3
+:107A400003F0B7FD00B1FFDF0A9828600B9868606B
+:107A50008DF8006009A9684603F0ABFD00B1FFDFB7
+:107A60000A98A8600B98E86015B0F0BD30B5A64C38
+:107A70000546D4F8F40300B1FFDFC4F8F45330BD79
+:107A80003EB50546032105F0D8FF0446284606F01A
+:107A90003AF9054604B9FFDF606818B10078FF289D
+:107AA00000D1FFDF01AA6946284600F094FA60B9C8
+:107AB000FFDF0AE0002202A9284600F08CFA00B994
+:107AC000FFDF9DF8080000B1FFDF9DF80000411EB8
+:107AD0008DF80010EED260680199884201D1002033
+:107AE0006060894C94F8FA03022800D3FFDF94F811
+:107AF000FA03401CC0B284F8FA03012803D181487C
+:107B0000407801F05DFD3EBD70B50446A1F57F40B3
+:107B100016460D46FF3800D1FFDF012E01D0FFDFF2
+:107B200070BD207820F00F00401D20F0F000503094
+:107B3000207000202076A5830120A07770BD70B54D
+:107B400015460C460646FFF729FE90B1017821F054
+:107B50000F01491D21F0F0015031017046800121D3
+:107B6000017621680162A18881840577BDE87040B3
+:107B7000F2E53046BDE870401321FAF733BE70B528
+:107B800005460C46084609F03BFF08B1102070BDC1
+:107B90002846F9F747FC28B1284600F09DFE2070E2
+:107BA000002070BD43F2020070BD2DE9F04F87B098
+:107BB00005460020059053488946017811B10820F8
+:107BC00007B04CE54F4851494160284609F018FF7D
+:107BD000002868D1484609F013FF002863D16F7A66
+:107BE0002B7AF818FF2870D82888FE286DD800B99D
+:107BF0000A202880296909B94FF4B06129616A68AF
+:107C0000B2B15478907804EB440420441478167987
+:107C100004EB440400EB44005479D27804EB4404B0
+:107C200006EB4606344402EB420204EB420406E053
+:107C300007EB470003EB430200EB42042046C7EB8F
+:107C4000C7021044C3EBC3021044184486B206EBCB
+:107C5000C60000EB400A04EBC40000EB40000090BB
+:107C6000D82901D20920ABE7A87AB8422DD84FF025
+:107C70001208082F0DD8012B0BD807F0C4FC0746BB
+:107C800009F0FAF93A1A297A687A521E0B189A42C0
+:107C900001DA404694E76F6883468846BFB13846AC
+:107CA00009F0D5FE08B110208AE7B9787878014448
+:107CB00038780A180BEB0800904206D179793A79A6
+:107CC0001144FA781144884201D0072078E70098DF
+:107CD0001FFA8AF387B20097CDE901642A4603A907
+:107CE0000020FFF70AFCDFF81C800399D9F8002078
+:107CF000D8F80400014491420AD90420C9F80010C0
+:107D00005EE7000018000020B80300208812002061
+:107D10000097CDE901641FFA8AF32A4604A9FFF708
+:107D2000ECFBDDE90301884200D0FFDF0498D8F8BE
+:107D300004100844C8F80400C9F80000FF490120F5
+:107D400088F80000087005983AE72DE9F0470746E3
+:107D50000C46084609F054FE40B9384609F06EFE5C
+:107D600020B9F81C20F00300B84202D01020BDE872
+:107D7000F087F3484FF00008817899B14178824646
+:107D8000C1EBC10100EB0115B4F8009015F8040F28
+:107D9000234600F00F000022294600F0F0F906000B
+:107DA00004D013E0A4F800800520E0E797B1218813
+:107DB000494501D90C260DE02878234600F00F0034
+:107DC0003A46294600F0DBF9060005D00C2E01D01A
+:107DD000A4F800803046CAE79AF801005446401CD7
+:107DE000C0B28AF80100092801D184F80180A07886
+:107DF000401EA070687800F0070101290BD002290D
+:107E000003D0032918D0FFDFE4E7C006E2D4688876
+:107E1000FFF736FEDEE7CB48696805F0A5FC94F86D
+:107E2000F903401CC0B284F8F9030128D2D1C64836
+:107E3000407801F0C5FBCDE794F8FB03401C8AF8BD
+:107E4000FB03C7E770B50D46044609F0B5FD18B948
+:107E5000284609F0D5FD08B1102070BD29462046FE
+:107E6000BDE8704007F09BBA70B5044615460E4653
+:107E7000084609F0A1FD18B9284609F0C1FD08B16E
+:107E8000102070BD022C03D0102C01D0092070BD31
+:107E90002A463146204607F0A5FA0028F7D00520EB
+:107EA00070BD70B514460D46064609F085FD38B91B
+:107EB000284609F0A5FD18B9204609F0BFFD08B114
+:107EC000102070BD22462946304607F0AAFA002845
+:107ED000F7D0072070BD10B594B0044609F090FDAE
+:107EE00010B1102014B010BD0F208DF8000009A9AA
+:107EF000684603F05EFB0028F4D19DF82C0020704A
+:107F0000BDF82E006080BDF83000A0800020E9E7B9
+:107F100070B505460C46084609F090FD20B93CB105
+:107F2000206809F06DFD08B1102070BDA08828B14F
+:107F300021462846BDE87040FEF7A0B9092070BD73
+:107F400070B504460D46084609F036FD30B9601E8E
+:107F50001E2814D8284609F02FFD08B1102070BD46
+:107F6000022C01D9072070BD04B9FFDF774800EB70
+:107F7000840050F8041C2846BDE870400847A4F16E
+:107F800020001F28EED829462046BDE87040FAF7A9
+:107F9000BCB870B504460D46084609F031FD30B94D
+:107FA000601E1E280DD8284609F006FD08B11020D5
+:107FB00070BD012C01D0022C01D1062070BD07201C
+:107FC00070BDA4F120001F28F9D829462046BDE83D
+:107FD0007040FAF709B905F099B9032803D00228CF
+:107FE00003D001207047062070470320704710B56A
+:107FF00094B003F0CFFA54484178806803F0C0FC95
+:10800000514801240C300178012916D130218DF816
+:108010000010C0788DF8020010B1012803D005E0EF
+:108020008DF8024002E000208DF80200684604F05E
+:1080300085FF10B109A803F070FD02208DF824001F
+:108040008DF825008DF8260009A8FFF70DFA00B17C
+:10805000FFDF8DF8244003208DF825008DF82600E1
+:1080600009A8FFF701FA002800D0FFDF3AE72DE961
+:10807000F0410646022012B101EB4200401DC7B29A
+:108080003068C01C20F0030232601BBB2C483B460A
+:108090000A21283809F081FB002408E00A2C11D2BB
+:1080A000DFE804F005070509090B0B05050528485D
+:1080B00004E0284802E0284800E0284809F08CFB4A
+:1080C000054600E0FFDFA54200D0FFDF641CE4B2FC
+:1080D0000A2CE3D3306800EB07103060BDE8F08174
+:1080E0002DE9F04395B081463A208DF82C00694681
+:1080F0000BA803F05EFA00B1FFDF43F20406002490
+:108100006D46DFF83C8032E02F19B87DC10706D0FC
+:10811000400704D405EB4400C08800F0CEFB98F87B
+:10812000FA0310B3B87D80071FD505EB4400C08863
+:1081300000F055FAC8B105EB440011E0080000203A
+:10814000B8030020B40700201800002014B3010079
+:10815000391F0000F7840000E12F0000E9F0000063
+:10816000C188A9F80010002605E0641CE4B29DF85F
+:108170000400A042C8D815B03046BDE8F0832DE910
+:10818000F041044600201880601E1D4616460F462A
+:10819000052800D3FFDF05482A4600EB840031465E
+:1081A00050F8043C3846BDE8F041184724B30100BC
+:1081B0002DE9F0478A46984615460646032105F004
+:1081C0003CFC0446304605F0B0FD0C35AFB200254E
+:1081D00081462E4604B9FFDFB9F1000F00D1FFDF61
+:1081E00004EB8A000189B94200D30125218CB942F0
+:1081F00002D2BAF1060F00D3012638EA050104D0F5
+:10820000817A41F0020181720BE038EA060108D060
+:10821000817A41F00401817214F8220F40F00400C9
+:10822000207005EA0600BDE8F0872DE9F047824698
+:10823000DDE90854174605F10C0099460E461FFA71
+:1082400080F800232A4639465046FFF7B1FF60B157
+:10825000B07800061BD424F8045C24F8029C504635
+:1082600005F063FD040008D106E0072F01D01120BE
+:10827000D9E743F20400D6E7FFDF2D1D2046A9B25F
+:1082800004F047FF00B9FFDF504603F0E5FA06EBC4
+:108290008700062F0289A2EB0801018103D2318CED
+:1082A000A1EB080030840020BDE72DE9F04385B044
+:1082B0001E46DDE90D5491460F46DDF8308005F08D
+:1082C00034FD60B309F10402694692B204F0BBFECA
+:1082D00050B300980770BDF80800042800D2FFDFF3
+:1082E000002701983A46394607808770019803F0C5
+:1082F00075FB1EB1BDF80800001F3080B8F1000FFB
+:1083000003D00198C01DC8F8000015B1BDF81000D9
+:1083100028808CB1288870B1039820600CE043F26B
+:10832000020005B0BDE8F083072F01D01120F8E767
+:1083300043F20400F5E727600020F2E72DE9F04F53
+:108340000F46054687B016465088032105F075FB99
+:10835000040000D1FFDF4FF000098DF80C90A078E9
+:10836000400600D1FFDF042F53D3297841F30000EA
+:10837000401C06D162786B789A424AD12278120763
+:1083800047D04FF0010B4FF00208142939DA4FF6AD
+:10839000FF7A012933D0122902D0132931D11CE0F0
+:1083A0000C2F2ED1A17801F07F01012929D020784E
+:1083B00020F00F00401C2070687860708DF80CB0C1
+:1083C000A888ADF80E00E888ADF810002889ADF84F
+:1083D00012006889ADF8140016E0062F11D120783C
+:1083E00020F00F0020707188012009F0A2FA8DF8AA
+:1083F0000C80ADF80EA0A888ADF8100004E0062FA0
+:108400000AD09DF80C10B9B17088324603A9F9F76B
+:1084100018FE07B0BDE8F08F207820F00F00207024
+:108420007188012009F085FA8DF80C80A888ADF8D4
+:108430000E00ADF810A0E7E70028EAD0768806A87D
+:10844000CDE9000927464C46002306220421304688
+:10845000CDF80890FFF729FF00B1FFDF069805234C
+:10846000042280F800B069784170A0F8028084800E
+:108470000621CDE9001039463046FFF7D6FE002828
+:10848000C7D0FFDFC5E70020FE49024621F81020D3
+:10849000401C0828FAD3704770B50C46897821F043
+:1084A000FF01A170217821F00F012170012161707D
+:1084B0000021616005F039FC050000D1FFDF28468E
+:1084C00004F0BFFDF53820852046BDE8704000F07F
+:1084D00010BB70B50D46032105F0AFFA040000D1C2
+:1084E000FFDFA07865F30600A07070BD70470146FD
+:1084F000012009F01EBA3EB58DB20321284605F0D1
+:108500009CFA040000D1FFDF2078002220F00F0049
+:10851000207002208DF800004FF6FF70ADF80200C9
+:10852000ADF8040069462846F9F78BFD3EBD2DE9FC
+:10853000F04705460C4600784FF0000901219246AD
+:108540004F46B1EB101F00D0FFDF287E032809D073
+:10855000FFDF00BFAAF8007014B1A4F80090678094
+:10856000002060E6AE8B4FF0700906F10A0087B27A
+:10857000D4B16888A080688B2081E680A889A9682A
+:10858000001F80B28046024604F10A00C91D12F0A5
+:1085900051FC4645DED904EB0800A6EB08020A3080
+:1085A000296912F047FCD5E7AAF80070D8E72DE951
+:1085B000FC410F461C46164680460321089D05F0E7
+:1085C0003CFA010008D033463A464046CDE9004522
+:1085D000FFF72BFEBDE8FC8143F20200FAE770B51D
+:1085E0000546A0F57F4086B0FF3811D0284605F03B
+:1085F0008AFB040000D1FFDF2046694604F0E3FF58
+:1086000000B9FFDF019CB4F80500E41C052802D086
+:10861000012006B070BD2E460321284605F00DFA54
+:10862000050000D1FFDF2079122807D120880C280F
+:1086300004D1A87800F07F00022806D0002306228B
+:1086400004213046FFF7B4FDE3E7002306220521AD
+:10865000F7E7F8B5024680689489938A30F8031FDB
+:108660001C444588241F8C421ED1042D1DD0052D8D
+:1086700029D0062D1ED0402D16D30E46144628466E
+:1086800000F0D7F908280FD0207820F00F00401C08
+:1086900020F0F00010302070032020766583A68340
+:1086A000607840F008006070F8BDBDE8F840001D3B
+:1086B00000F0CBB90093548813690A46011D204687
+:1086C000FBF7CCF9F8BDBDE8F840001D36E67FB5F4
+:1086D0000D460646032105F0B0F904003DD0207890
+:1086E00000F00F0001283BD0002003A9CDE90010C5
+:1086F000034602900C2205213046FFF7D6FD0028E4
+:1087000029D1039812210523017061781A46891C2A
+:10871000417008214180298881806988C180A988A9
+:108720000181E98841810C21CDE9001021463046C4
+:10873000FFF77BFD00B1FFDFF0230022314601206F
+:1087400009F05AF8207820F00F00401C2070607863
+:10875000801C6070002004B070BD43F20200FAE794
+:108760001120F8E77FB50D460646032105F065F9AF
+:10877000040006D0207800F00F00012804D0082063
+:10878000E9E743F20200E6E7002003A9CDE9001083
+:1087900003460290062205213046FFF786FD002899
+:1087A000D9D103981321052301706178417002210A
+:1087B000418085800621CDE900101A4621463046C9
+:1087C000FFF733FD00B1FFDF207820F00F002070AD
+:1087D0000020C0E72DE9F84F0F468346032105F03E
+:1087E0002CF90546584605F0A0FA80464FF0000ADD
+:1087F00005B9FFDFB8F1000F56D1FFDF54E0404666
+:108800006946002204F082FD9DF800408146082C54
+:1088100000D3FFDF05EB840609F108003189062C3F
+:108820000144318102D2298C08442884072C03D1C9
+:108830000AF1010000F0FF0AB07AC0070CD021460F
+:10884000284600F0DDF838B9B07A032C20F001009A
+:10885000B07258462ED0FFDFB07A810706D520F0DF
+:108860000200B0722146584600F0DAF8062C1BD8F8
+:1088700095F82200410717D520F0040085F8220062
+:10888000002401E0E407002005EB8401887A420718
+:1088900006D520F0040088722146584600F0C0F842
+:1088A000641CE4B2062CECD37F1EFFB2A7D2504664
+:1088B000BDE8F88FFBF773F9CEE710B5032105F09B
+:1088C000BCF8040000D1FFDF204600F012F9A078C8
+:1088D00040F08000A07010BD10B5032105F0ADF888
+:1088E000040000D1FFDF208D2321B0FBF1F0C0B2E6
+:1088F00010BD70B50D46032105F09FF8040000D1AE
+:10890000FFDF062D00D9FFDF2946204600F078F86A
+:10891000002805D004EB85018A7A42F001028A72B0
+:1089200070BD10B50446402801D2072010BD00F0EC
+:1089300080F8082802D04FF4445010BD0021774839
+:1089400002E0491C082903D230F81120002AF8D18E
+:10895000082903D020F81140002010BD042010BDCC
+:1089600010B5402801D2072010BD00F062F8082899
+:1089700005D06A4A002122F81010084610BD0520D3
+:1089800010BD70B588B015460C00064606D02DB156
+:108990006088402804D2072008B070BD1020FBE793
+:1089A000218849B300F045F8082827D003AA06A972
+:1089B00005A88DE80700228804AB07213046FFF7A1
+:1089C00074FC0028E8D1BDF810202946059812F063
+:1089D00031FA2088BDF81010884204D9421A29447F
+:1089E000039812F027FA05980090238862880721DF
+:1089F0003046FFF7DCFDCFE70C20CDE70520CBE7C5
+:108A0000072903D0464A32F8112000E0028D00EB1E
+:108A100081000089904201D20120704700207047F8
+:108A200010B5032901D0FFDF10BDBDE81040FBF7F2
+:108A300078B801460020394A02E0401C082803D2D9
+:108A400032F810308B42F8D170472DE9F0410F46D3
+:108A50008046014686B014463846FCF744FDC0B255
+:108A600008283CD10025ADF81450039560880321F7
+:108A700004F0E3FF060000D1FFDF00213046FFF7DE
+:108A8000BFFF68B91722ADF8142003A8CDE900058F
+:108A90000295002360881946FFF707FC00B1FFDF4D
+:108AA000009405AA41463846039BFDF755FCC0B229
+:108AB00005281CD2DFE800F0031B13161300BDF8D5
+:108AC000140000280BD003990423CDE9000160882D
+:108AD00000223146FFF7A9FB002800D0FFDF06B0D7
+:108AE000BDE8F081607840F010006070F7E7FFDFCC
+:108AF000F5E710B504462021083012F034FA084892
+:108B0000002100BF30F8112004EB8103491C1A81B9
+:108B10000629F7D9208DA08410BD0000E4070020AD
+:108B20003CB3010030B44FF0E02001234FF4006C5F
+:108B30000021C0F880C11D02C0F880511C06C0F899
+:108B40008041E54A82F80014D21E82F80014E34AFC
+:108B500082F80014E24A53609360C2F84011C2F8F0
+:108B60004411C2F84811C0F880C2C0F88052C0F861
+:108B70008042C0F800C1C0F80041136030BC7047AB
+:108B800070B401204FF0E023C6024FF0000CC3F890
+:108B900080610402C3F880410506C3F88051D04AC1
+:108BA00050609060CF4801680029FCD1C2F840C1F4
+:108BB000C2F844C1C2F848C1C3F88062C3F8804219
+:108BC000C3F8805270BC70474FF0E0204FF4006152
+:108BD000C0F88012C910C0F880127047002804BF86
+:108BE000C1487047012804BFC0487047022804BF2D
+:108BF000BF48704700B5FFDF002000BD08B5B84989
+:108C0000002298B101282FD002281CBFFFDF08BD29
+:108C10004FF48020C1F80803C1F84803B54802604A
+:108C2000C1F84821B2480068009008BD4FF4803078
+:108C3000C1F80803C1F84803AF4B1A60C1F84021DE
+:108C4000AE4BC1031960AE49C1F808034FF0E023F1
+:108C50000012C3F88001AB480260C1F84021C1F89E
+:108C60000022A948027008BD4FF40030C1F8080383
+:108C7000C1F84803A5480260C1F844219B48006838
+:108C8000009008BD70B5DFF858C204260024012505
+:108C900058B1012840D002281CBFFFDF70BD9C4A9C
+:108CA0004FF48020012B3CD144E0881E20F07F410E
+:108CB0004FF48030CCF80803CCF84041CCF84403A2
+:108CC000CCF84015012B14BF002101218E4B5970A7
+:108CD0008B490D61DFF83CC2CCF800408E4C4FF060
+:108CE000020CC4F800C0DFF834C2CCF80060DFF832
+:108CF00014C23D32CCF80020C1F800524FF0E02CF5
+:108D00008A15CCF88022C1F80403CCF800210804AD
+:108D1000834908601D7070BD824A4FF40030012BFA
+:108D200008D0CCF80803C2F84041CCF84403C2F89C
+:108D3000401570BDC2F84041CCF80403CCF84403A0
+:108D4000C2F8401570BD67480068704770B5764836
+:108D50000568774975480860614CD4F840010026E1
+:108D600001280AD1D4F8080310F4803F05D04FF44D
+:108D70008030C4F80803C4F84061D4F844010128E5
+:108D80000DD1D4F8080310F4003F08D04FF40030A0
+:108D9000C4F80803C4F84461012007F0BEFBD4F80E
+:108DA000480101280DD1D4F8080310F4802F08D011
+:108DB0004FF48020C4F80803C4F84861022007F08B
+:108DC000ACFB5C48056070BD574810B50468584955
+:108DD000564808604C490878002808BF03201AD07C
+:108DE000464A4FF000401060454AC00BC2F80803E5
+:108DF00003124FF0E02C0020CCF88031414B18607A
+:108E0000C2F84001C2F8000208704A78002A1CBF6C
+:108E10004870002001D007F080FB4648046010BD78
+:108E20004FF0E0214FF08070C1F8000270474FF022
+:108E3000E0214FF08070C1F8800270474FF0E021D0
+:108E40004FF40010C1F8000270474FF0E0214FF4DA
+:108E50000010C1F8800270472949012008614FF0D5
+:108E6000E0210002C1F880027047410A43F609522E
+:108E70005143C0F3080010FB02F000F5807001EBD5
+:108E800050207047430B48F2376C03FB0CF31B0C6C
+:108E90004FEA432CC1F800C0DFF89CC003FB0C0371
+:108EA00026484CF2F72C5843400D10FB0CFC0CEB01
+:108EB000432303F580735B1213700A681044086043
+:108EC0007047194810B5046819491848086007F038
+:108ED00011FC1848046010BD0BE000E018E000E051
+:108EE00000B0004004B500404081004044B1004063
+:108EF00048B1004048B5004040B5004008F5014089
+:108F000000800040408500402800002044B500401B
+:108F100008B00040048500400885004010850040EE
+:108F200004F5014004B000401005024001000001BA
+:108F30001805024014050240F7C2FFFF6F0C010044
+:108F400010B5EFF3108000F0010472B6EC484178E0
+:108F5000491C41704078012801D108F0EDF8002C3F
+:108F600000D162B610BD70B5E54CE07848B9012576
+:108F7000E570FFF7E5FF08F0E7F820B1002008F002
+:108F8000C3F8002070BD4FF080406571C0F80453F5
+:108F9000F7E770B5EFF3108000F0010572B6D84C1A
+:108FA000607800B9FFDF6078401E6070607808B9B3
+:108FB00008F0C6F8002D00D162B670BDD04810B5DB
+:108FC000C17821B100214171C170FFF7E2FF00209B
+:108FD00010BD10B5044608F0B7F8C949C978084073
+:108FE00000D001202060002010BD2DE9F05FDFF8E7
+:108FF00010934278817889F80620002589F80710B7
+:10900000064689F8085000782F4620B101280FD075
+:1090100002280FD0FFDF08F0A4F898B108F0A8F8F4
+:10902000A8420FD1284608F0A7F80028FAD047E058
+:109030000125F0E7FFF784FF08F086F80028FBD051
+:109040000225E8E701208407E060C4F80471AD4917
+:109050000D600107D1F84412AA4AC1F3423124320B
+:109060001160A8494FF0020B34310860C4F804B312
+:10907000A060DFF894A2DAF80010C94341F30011B0
+:1090800001F10108DAF8001041F01001CAF80010EF
+:1090900000E020BFD4F804010028FAD0284608F0E8
+:1090A0006BF80028FAD0B8F1000F05D1DAF80010FB
+:1090B00021F01001CAF80010C4F808B3C4F8047114
+:1090C00099F807004C4670B1307860B908F03CF868
+:1090D000064608F027FA6FF0004116B1C4E9031004
+:1090E00001E0C4E9030115B12771BDE8F09F01203B
+:1090F0002071BDE8F05F00F0E1B810B5040000D1C8
+:10910000FFDF4FF080414FF0FF30C1F8080300222D
+:10911000C1F80021C1F80421C1F80C21C1F81021C7
+:1091200008F018F828B176490120C8704878401C2A
+:1091300048702046BDE8104057E72DE9F041012571
+:10914000AF077D616E4CE079F0B1012803D0217A40
+:10915000401E814218DA07F0F7FF064608F0E2F9F0
+:10916000E179012902D9217A491C21720EB12169C4
+:1091700000E0E168411A022902DA11F1020F0EDC67
+:109180000EB1206100E0E060FFF7DAFE07F0DCFFDF
+:1091900010B13D61A57000E0257000202072BDE88F
+:1091A000F0812DE9F05F5948D0F800B0574A58498E
+:1091B000083211608406D4F8080110B14FF001089C
+:1091C00001E04FF00008D4F8000100B10120814611
+:1091D000D4F8040108B1012600E00026D4F80C01FF
+:1091E00000B101208246D4F8100108B1012700E047
+:1091F000002748EA090126EA010020EA0A00B843EC
+:1092000000D0FFDF0025B8F1000F04D0C4F80851EA
+:10921000012007F079FFDFF8E880B9F1000F13D0E3
+:10922000C4F8005198F8050020B188F805500020D6
+:1092300007F06AFF98F8000030B107F085FF18B119
+:10924000012088F8020020610EB1C4F80451BAF17F
+:10925000000F0AD0C4F80C5198F80200464600B935
+:10926000FFDFB5703570FFF794FE37B1C4F81051C9
+:1092700098F8040008B1FFF760FF2449091DC1F800
+:1092800000B032E770B51E4DE87808B907F058FF16
+:1092900001208407A061A87858B100BFD4F80C0160
+:1092A00020B9002007F068FF0028F7D10020C4F89B
+:1092B0000C014FF0FF30C4F8080370BD2DE9F041F8
+:1092C0001926B507C5F808630124AC610020C5F86C
+:1092D0000001C5F80C01C5F8100107F035FF084F73
+:1092E00010B1BC702C6100E03C70FFF729FE05490D
+:1092F000B87920310860C5F804636C614FE700005D
+:109300002C0000201805004010ED00E01005024080
+:109310000100000110B50D2000F06FF8C4B26FF02D
+:10932000040000F06AF8C0B2844200D0FFDF3A497E
+:109330000120086010BD70B50D2000F048F8374CD2
+:109340000020C4F800010125C4F804530D2000F0EA
+:1093500049F825604FF0E0216014C1F8000170BDAC
+:1093600010B50D2000F033F82C4801214160002198
+:10937000C0F80011BDE810400D2000F033B82848B7
+:1093800010B5046826492748083108602349D1F8F8
+:109390000001012804D0FFDF2148001D046010BD3A
+:1093A0001D48001D00680022C0B2C1F8002107F06E
+:1093B000D4FFF1E710B51948D0F800110029FBD00F
+:1093C000FFF7DDFFBDE810400D2000F00BB800F006
+:1093D0001F02012191404009800000F1E020C0F807
+:1093E0008011704700F01F02012191404009800068
+:1093F00000F1E020C0F880127047002806DA00F083
+:109400000F0000F1E02090F8140D03E000F1E020DF
+:1094100090F800044009704704D5004000D0004097
+:10942000100502400100000110B5202000F075F881
+:10943000202000F07DF84449202081F800044349B1
+:1094400000060860091D42480860F7F75BFF3F49C6
+:10945000C83108603F48D0F8041341F00101C0F85A
+:109460000413D0F8041341F08071C0F80413364996
+:1094700001201C39C1F8000110BD10B5202000F0FA
+:109480004CF8324800210160001D01602F4A481E3F
+:10949000E83A10602F4AC2F808032C4BC833196011
+:1094A000C2F80001C2F860012B490860BDE8104015
+:1094B000202000F03DB825492848EC390860704765
+:1094C00022492648E8390860704770B51F4A80690C
+:1094D000E83A224911601F49D1F800610023204D6C
+:1094E0001D4A5C1E1EB1A84206D300210FE0D1F830
+:1094F000606186B1A84209D2C1F80031C1F860317B
+:109500001460BDE87040202000F012B81168BDE87A
+:10951000704011F05ABDFFDF70BD00F01F02012145
+:1095200091404009800000F1E020C0F880117047B0
+:1095300000F01F02012191404009800000F1E0206D
+:10954000C0F880127047000020E000E000060240F2
+:1095500084120020000002400004024001000001CB
+:1095600000C001004FF0E0214FF00070C1F8800111
+:10957000C1F88002384B802283F80024C1F8000132
+:10958000704700B502460420344903E001EBC003F4
+:109590001B792BB1401EC0B2F8D2FFDFFF2000BD07
+:1095A00041F8302001EBC00100224A718A7101228A
+:1095B0000A7100BD294A002102EBC0000171704709
+:1095C00010B50446042800D3FFDF244800EBC40490
+:1095D0002079012800D0FFDF6079A179401CC0B25A
+:1095E000814200D060714FF0E0214FF00070C1F86F
+:1095F000000210BD2DE9F0411948056818491948C5
+:10960000083108601448042690F80004134F4009FC
+:10961000154C042818D0FFDF16E0217807EBC100B5
+:109620000279012A08D1427983799A4204D0427999
+:10963000827157F8310080472078401CC0B22070FA
+:10964000042801D300202070761EF6B2E5D204482B
+:10965000001D0560BDE8F08119E000E0F40700207E
+:109660001005024001000001400000200F4A12686E
+:109670000D498A420CD118470C4A12680A4B9A428B
+:1096800006D101B507F022FFFFF715FFBDE8014045
+:10969000074909680958084706480749054A064B1B
+:1096A0007047000000000000BEBAFECA980000200B
+:1096B000040000208811002088110020F84B586019
+:1096C00019721A80C90011F04EBC00210180704748
+:1096D0004FF6FF720280032008F02BB970472DE986
+:1096E000F04F0E46017804464FF0010A0AFA01F0E5
+:1096F00047F2FF1100EA01086168154697B0088833
+:10970000A0F57F42FF3A06D0B8F1000F07D047F22C
+:10971000FE12104203D0012017B0BDE8F08F40EADE
+:10972000080008804FF00009A5B185F80090237863
+:109730000027052003220221DFF864B3102B75D225
+:10974000DFE803F0740D131C2F4A515A31A5A1759F
+:10975000A9F1F0EF20780B28E9D00420DCE729708C
+:10976000A089A5F8010032801DE104212970A1899A
+:10977000A5F80110E189A5F8031082E00620287001
+:10978000A089A5F80100E089A5F80300208AA5F8C2
+:109790000500A28AE81DA16911F04CFBA08AC01D3A
+:1097A0006FE0082129702178082901D11021297042
+:1097B000A189A5F80110E189A5F8031030806A1D80
+:1097C000694604F1100005F02CFE00287ED1308897
+:1097D0009DF80010084454E00A202870A089A5F8DC
+:1097E00001003280AAE00C212970A189A5F801109E
+:1097F000E189A5F80310B7E0A2890AEB420081B223
+:109800003088884262D3052960D30E20287000205A
+:1098100008E0236905EB400C33F81030401CACF82D
+:10982000013080B29042F4D33180BCE0CAE09BF8B2
+:1098300009005A46002873D0401E5072227BDBF884
+:109840000400236900EBC205AA882868D3F800C089
+:109850000244A2F1080042F808CC5A6842608DF830
+:1098600000108DF8019028680290A888ADF80400D7
+:1098700000216846FBF776FCA5F80490002E01D085
+:10988000484630808FE0287840F0800129702878A1
+:1098900040F040012970287820F03F0012302870F5
+:1098A000A189A5F80110E289E81C216911F0C2FA2A
+:1098B000E089C01C3080287841063FD5000672D56B
+:1098C0008DF800A08DF80190308800E026E0001DA2
+:1098D000ADF804000295E189E81C08440390001DDE
+:1098E00004909BF808008DF8140000216846FBF7EF
+:1098F00039FC074630880C303080022F01D007B386
+:1099000063E09DF81420DBF804109BF808305846FB
+:1099100001EBC2019A4201D28A882AB1042754E09D
+:1099200030E02BE022E00DE0427A521C8BF8092057
+:109930000D6030888880A6F8009046E06168A089B4
+:10994000888030E0287820F03F0016302870A08909
+:10995000A5F80100E089A5F80300228A681D616965
+:1099600011F068FA208A401D3080E7E7287820F05F
+:109970003F0018302870207B687055E760680188C8
+:10998000090401D4052720E0C088A189884201D0BC
+:1099900006271AE01E202870A6F800A0606801883B
+:1099A00021F400410180B8F1000F0ED0BBF8000097
+:1099B000002283000320A16807F01EFF6168207861
+:1099C000887007E0A6F8009003276068018821EA04
+:1099D0000801018038469FE62DE9FF4F97B00C46FD
+:1099E000249E70B117280CD83288A2F57F43FF3B24
+:1099F00007D02278530601D4120604D508201BB0E4
+:109A00008BE60720FBE74FF000098DF800908DF8FA
+:109A100001902278831E02F03F0CA0F1010A611C24
+:109A20004D461FFA8AF702AABCF1200F79D2DFE86F
+:109A30000CF089107861786C78AA78CD78F778FC8A
+:109A400078F478F378F2787878F178F078EF78EE47
+:109A50007889052876D104208DF80000B0788DF83B
+:109A600004006088ADF8060020798DF80100607868
+:109A700000F03F000C282BD00ADCA0F102000928DE
+:109A800060D2DFE800F0145F175F1C5F1F5F2200E9
+:109A9000122826D006DC0E281DD01028DAD11DE0B1
+:109AA0001408002016281FD01828D3D11FE03078C2
+:109AB000800701E030784007002843DA37E130784A
+:109AC0000007F9E73078C006F6E730788006F3E75C
+:109AD00030784006F0E730780006EDE73088C005C2
+:109AE000EAE73088C004E7E730888004E4E730889C
+:109AF0004004E1E73178890724D50328AAD105205D
+:109B00008DF80000B4F80100D2E031784907F3D5B0
+:109B1000062817D3617898B2012903D0022999D178
+:109B200002E01FE1022700E0102706218DF8001057
+:109B300061788DF80610ADF80490A11C904607F1ED
+:109B400002091BE097E000BF31F8022BA0F1020AE6
+:109B5000A8F800208B463A4608F1020011F06AF995
+:109B600008EB070202F10208BDF80420AAEB070087
+:109B7000521C0BEB070180B2ADF804208145E3D9FC
+:109B8000002878D1D3E03078000774D507208DF80D
+:109B900000001FFA8AF1ADF80490601C0DF1060276
+:109BA0000FE000BF30F8023B22F8023B30F8023BE6
+:109BB00022F8023B091FBDF8043089B25B1CADF8E6
+:109BC00004300429EED2002955D1B0E03178C9061D
+:109BD00051D502284FD308208DF80000ADF806902B
+:109BE00061789BB28DF80410A01C0CE0078822F865
+:109BF000047B871C80C25B1ABDF8067008447F1C7A
+:109C00009BB2ADF806709942F0D9A3BB8FE070E02B
+:109C100075E065E04FE042E01DE012E005E0FFE79F
+:109C20003078800627D5092003E03078400622D519
+:109C30000A208DF80000B088ADF80400ADF8067079
+:109C400007E03078000616D50B208DF80000ADF83F
+:109C5000047002916BE03188C9050CD502287FD3CE
+:109C60000C208DF8000099B2ADF8069063788DF85D
+:109C70000430A01C10E073E0078822F8027B4788BC
+:109C800022F8027B071D80C2C91ABDF8067018446D
+:109C90007F1C89B2ADF806708B42EDD993E731880D
+:109CA000C9045DD501285BD10D208DF80000B08876
+:109CB000ADF804003BE03188890451D505284FD325
+:109CC0000E218DF80010B188ADF80410B4F803101F
+:109CD000401FADF80800601DADF80610039026E0A7
+:109CE000318849043CD501283AD10F208DF8000075
+:109CF0001DE03188090433D4B4F80110F180032841
+:109D00002ED3217801F03F011B2925D011218DF898
+:109D10000010318841F40041A6F80010B4F8011099
+:109D2000ADF80410C01EADF80600E01C02902078CB
+:109D300000F03F001B2809D01D2807D003201A99E6
+:109D400007F0F7FD308800F400403080684619992C
+:109D5000FBF708FA284652E610218DF80010DDE7DF
+:109D60000725F7E70825F5E700B597B0032806D1E2
+:109D70008DF80000019100216846FBF7F3F917B058
+:109D800000BD00002DE9FF4F8DB09346DDE91A5666
+:109D9000DDF8749004464FF0000A082A06D0E06906
+:109DA00001F02CF858B110203070BCE0288809214F
+:109DB00040F01000288089F80010022717E0E169C0
+:109DC00001208871E2694FF420519180E169887225
+:109DD000E06942F601010181E16900208873288869
+:109DE00040F020002880112089F8000004273078F6
+:109DF00009900A20307004F1180009F102080225C8
+:109E00000B9001F063FA002066E000BFBBF1100F79
+:109E100006D1022D04D0A8EB0A00BDF80C20428028
+:109E2000BDF80E001099884203D9F649097A0E91BF
+:109E300004E003D1099909B131701FE0A8F80000CE
+:109E40001C980088A0EB0500A0EB070083B2C7F1C7
+:109E5000FF00984200D203460E980AAA08EB0701B9
+:109E60008DE8070094F82010BDF80E00002201F0E4
+:109E70009AFA307030B1C0B2832858D0BDF80E00C5
+:109E800020833DE0089828B1DE48006800790A2860
+:109E90002BD335E0BDF82800C11901F0FF0A022DCF
+:109EA0000ED099F80110514503D1BDF81820824217
+:109EB00008D0D4488A4600680178032908D021E0F8
+:109EC00089F801A0CF4800680178042906D008E08D
+:109ED00000790A2816D20120089006E0BDF80E107D
+:109EE000818005EB0A00D04485B203AA0E990B9835
+:109EF00001F0EFF920B91C980088401BB84285DAC0
+:109F0000022D0BD0BBF1100F04D1A8EB0A01BDF854
+:109F10000C0048801C98058000203070B94800680B
+:109F20000078032803D0002011B0BDE8F08F022094
+:109F3000FAE72DE9F0410546406B1346002758B378
+:109F4000491F8EB2698FA1F57F42FF3A05D04218B2
+:109F500092881144891D8CB200E00024A1192A8F37
+:109F60000831914216D82044B3F8011020F8021BA2
+:109F7000B3F8031020F8021B324620F8026B591D7B
+:109F800010F058FF6C87696B00202144B61D3144E6
+:109F9000088002E0092700E083273846BDE8F08109
+:109FA00010B50B88048F9C420CD9446BE0180488D0
+:109FB00044B1848824F40044A41D23440B80106021
+:109FC000002010BD822010BD2DE9F04788B000258B
+:109FD000904689468246ADF81050072745E0039821
+:109FE00006888088000440D4A8F8006005A800977F
+:109FF000CDE901504FF4007300224946304601F08C
+:10A00000D2F9040038D1BDF81000ADF8180003985B
+:10A0100004888188B44214D10A0412D4CDE90057CF
+:10A0200021F40041029541F480434288494620468C
+:10A0300000F0C8FF04000BD10398818841F400416F
+:10A04000818003AA06A95046FFF7AAFF0400DED0CC
+:10A05000CDE9005703980295BDF81430008800221E
+:10A06000494600F0AFFF822C06D103AA04A950464E
+:10A07000FFF796FF0400B2D0ADF8105004E003984B
+:10A08000818821F40041818003AA04A95046FFF78A
+:10A0900087FF0028F3D0822C03D0204608B0BDE80B
+:10A0A000F0870020FAE730B50446406B97B00025F2
+:10A0B00070B10B208DF80000208FADF80800606BA8
+:10A0C0000391019000216846FBF703FE8DF80050D4
+:10A0D0004FF6FF7065636087258717B030BD2DE9A7
+:10A0E000F041044686B00E46616B00200C9D174679
+:10A0F00000292AD0012B28D12A4631462046FFF7D5
+:10A1000063FF002821D1002F1FD0A046344600262F
+:10A11000ADF8106007270EE00398008828800398A8
+:10A120000296811DCDE90017838842880088214668
+:10A1300000F048FF30B903AA04A94046FFF730FFFA
+:10A140000028E9D0822800D1002006B026E72DE9BA
+:10A15000F0411546DDE906644A1D378892B2974200
+:10A1600001D206201AE73280172204F8012B0A4692
+:10A17000208065801946201D10F05CFE00200DE750
+:10A1800000220280C262831D0263C36142634FF6F4
+:10A19000FF734387028780F8201070474FF6FF72E5
+:10A1A0000280042007F0C5BB30B597B00D460446C9
+:10A1B000FFF779FF208E48B101208DF80000E06A9A
+:10A1C000CDE9010500216846FBF783FD0020E06230
+:10A1D000206382E70146002009880A0700D5012094
+:10A1E00011F0F00F01D040F00200CA0501D540F097
+:10A1F00004008A0501D540F01000490501D540F062
+:10A2000020007047200800202DE9FF4FA7B01F460F
+:10A21000349E299D379C5FEA000817D028784106B4
+:10A2200010D400F03F011E290AD0218811F4FE6FDE
+:10A230000CD13A88172A09D3A1F57F42FF3A05D0FD
+:10A24000010606D500F03F00122802D004202BB0F2
+:10A250006BE6FE4928984FF0000908728DF81090BF
+:10A260008DF834900DAA0A60359A4A60ADF81490C2
+:10A27000ADF890902878032200F03F038646711CC9
+:10A2800004F1180CCB464FF0040AA8F10500CDF8F4
+:10A2900098C01F2B7DD2DFE803F07C7C107C1C7CF7
+:10A2A000867CEF7CEE7CED7CEC7CEF7CEB7C7C7C3C
+:10A2B000EA7CE97C7C7C7C7CE800B8F1030F02D06E
+:10A2C0008DF810A0EFE232701720A6F801003A8056
+:10A2D000BEE2B8F1050FF3D1B5F801002083ADF867
+:10A2E0001400B5F80310618300287DD088427BD824
+:10A2F00084F808B0A4F806B04FF6FF706084269882
+:10A3000000F0E4FF05203070B01C00904FF0020A0E
+:10A3100008AA2899269800F0DCFF00287ED19DF835
+:10A320002600012803D002207070102002E00120D6
+:10A33000707002208346002201A909A805F071F877
+:10A3400030BB9DF80400834522D13A88801CA2EBE3
+:10A350000A0181421CDB0098BDF822100AF1020AB2
+:10A360000180009909A8891C0A46009101A905F0FD
+:10A3700058F89DF80400009908AA014450441FFAB7
+:10A3800080FA00912899269800F0A3FF0028D2D0E7
+:10A3900000E069E2BAF1020F40D0A7F800A057E24E
+:10A3A0008DF8100054E2B8F1070F89D3B5F8010019
+:10A3B0002083ADF81400B5F803106183A0B1884282
+:10A3C00012D84FF0010A84F808A0B5F80500E08023
+:10A3D00000202073E06900F011FD90B9E16981F877
+:10A3E00006A04FF4205100E078E0E26942F6010057
+:10A3F0009180E16981F80AA0E1690881E1690020A2
+:10A400008873A8F107006084E81D6062269800F058
+:10A410005DFF0720307006F1010A00E06FE00020C8
+:10A420004FF0010BADF8220018E000BFBBF1010FA7
+:10A430000CD0E069807901281FD03AF8021C00BFD7
+:10A440000BF102002AF8021B1FFA80FBBDF8221054
+:10A450000BF102002AF8021B1FFA80FB08AA2899B8
+:10A46000269800F036FF58B10FE0DAE16BE10AE11F
+:10A47000AEE0D2E17BE05AE01EE0BDF82010DFE75D
+:10A480003988A1EB0B000428D0DABBF1010F36D0DC
+:10A49000E069807901280CD0BDF82010A1F57F403B
+:10A4A000FF3806D03AF8021CAAF800100BF102009F
+:10A4B000B1E1BDF82010F7E7B8F1070F03D0B8F10C
+:10A4C000150F7FF4FDAEB5F801102183ADF814101F
+:10A4D000B5F80320628309B1914201D901205FE7F9
+:10A4E00001212172A4F806B084F80CB0B8F1050F70
+:10A4F00007D0C0B2691DE26904F074FF08B10A20F8
+:10A500004EE74FF6FF70608404A824A9CDE900103F
+:10A51000CDE902762878002300F03F0220462899F2
+:10A52000FFF730FC8146208BADF8140090E1B8F1C4
+:10A53000030FC6D14020ADF89000B5F8010020838C
+:10A54000ADF81400289ACDE900210AAB02933988AE
+:10A550000022491E8BB294F8201000F024FF8DF8E1
+:10A56000100058BB0B203070BDF828002EE0B8F169
+:10A57000050FA6D18020ADF89000B5F8010020832A
+:10A58000B5F803206284ADF81400B2F5007F01D95C
+:10A59000072005E742F47C426284289BCDE9003124
+:10A5A0000DF12C0CCDF808C03988491E8BB294F8F7
+:10A5B000201000F0F8FE8DF8100018B18328B5D1F6
+:10A5C0000220BEE00D203070BDF82C00401C22E1BE
+:10A5D0004FEADE1000EB400002EB8000404505D959
+:10A5E0005FEA4E607FF56CAE584614E1B5F801C0E5
+:10A5F000ADF814C02978490608D505218DF8341026
+:10A600002978090605D58DF834B031E106218DF899
+:10A610003410E91C289BA8EB000ACDE90013CDF803
+:10A6200008B009911FFA8AF394F8201000226046BE
+:10A6300000F0C8FC8DF810008DF834B02978490678
+:10A6400010D52088C00509D5208B01E02008002006
+:10A65000BDF81410884201D1C4F824B058468DF8D2
+:10A6600010B0D8E0832801D14FF002094FF4807078
+:10A67000ADF89000BDF814002083A4F822A009983A
+:10A6800060621320C5E0B8F1050FFFF419AEB5F80C
+:10A6900001C0ADF814C0218F41B3A1F57F42FE3A4D
+:10A6A00024D007218DF83410289A6B1DCDE9003293
+:10A6B00080B2CDF808B040F40043DA46B5F8032084
+:10A6C00094F82010604600F07DFC4FF400718DF886
+:10A6D00010008DF834A0ADF89010832810D0E8B1A8
+:10A6E000218FA1F57F40FE3807D0DCE00A218DF8EC
+:10A6F00034104FF6FE712187D6E7A4F838A0A7E002
+:10A700002A4641462046FFF714FC8DF8100008B198
+:10A71000832848D1BDF81400208351E72A464146DA
+:10A720002046FFF706FC8DF81000E0BB618F606BE0
+:10A73000CDE9007643185A88998833F8060BFFF75D
+:10A7400006FD814684E095F801A0B8F1020F7CD1A6
+:10A750005FEA0A0002D0BAF1010F76D108208DF825
+:10A76000340005A800908DF838A094F820105346C6
+:10A7700000222046FFF7B3FC8DF839008DF83AB07F
+:10A7800050B9BAF1010F12D0BAF1000F04D1218FE4
+:10A79000A1F57F40FF380AD0208F40B18DF834B04A
+:10A7A0004FF4806000E053E0ADF890000DE00DA89C
+:10A7B0003599FBF78EFA81464FF480608DF834B0FE
+:10A7C000ADF89000B9F1020F06D0FD48006880791D
+:10A7D00028B18DF8100043E0A4F818A038E0B9F1D2
+:10A7E000000F03D081208DF8100043E005A80090F1
+:10A7F00094F82010534601222046FFF770FC8DF894
+:10A80000100020463699FFF74EFC9DF81000F8B96D
+:10A8100019203070012038801AE006208DF81000D1
+:10A8200041E02078000723D5B8F1010F20D109209D
+:10A830008DF83400A088ADF838000420369907F070
+:10A8400078F80820ADF8900000E011E0A7F800B01B
+:10A850009DF8340020B10DA83599FBF73AFA8146EE
+:10A86000B9F1000F1CD005E05FEA4E607FF528AD1E
+:10A870004FF004092088BDF8901008432080BDF8EF
+:10A88000900080050AD5218FA1F57F40FE3805D1C3
+:10A890002998E062A4F830804FF003094846D6E4D6
+:10A8A0009DF8100058B10120307028787070BDF804
+:10A8B000140070809DF810003071052038802088C9
+:10A8C000BDF8901088432080E8E72DE9FF4F01781C
+:10A8D000A5B080464FF0010B0BFA01F04FF60901CD
+:10A8E000349C0840ADF86C0021884FF00009A1F5B8
+:10A8F0007F42FF3A02D028B1080703D5012029B0D2
+:10A90000BDE8F08F289F4FF0000A04A887F800A048
+:10A910002799269A55460988ADF87C10A8498DF8E4
+:10A9200068A00A728DF810A008603298486098F804
+:10A930000000012830D0022809D0032876D13878C9
+:10A9400020F03F001D303870B8F80400A08098F85F
+:10A950000000022804D1387820F03F001B30387006
+:10A9600021AAF91C07208DE80700BDF87C0094F8A7
+:10A970002010C01E83B2B8F80400002200F013FDBE
+:10A980000028DBD1B8F80400A7F80100BDF8840066
+:10A99000C01CADF87C005FE198F805108DF86810D8
+:10A9A00098F804004FF40079012802D00228C5D19C
+:10A9B00033E1208808F1080600F4FE60ADF86C0071
+:10A9C00010F0F00F1BD010F0C00F05D03088228B94
+:10A9D000904201D005257DE189B9B078C0070ED03D
+:10A9E000B2680720CDE90020CDF808A0F388B2882E
+:10A9F00094F82010308800F0E5FA00286FD12899EB
+:10AA0000BDF86C00491C802845D006DC10280ED00B
+:10AA100020280CD0402891D122E0B0F5807F5FD073
+:10AA200048457DD0B0F5806F88D1CBE029E1C006E4
+:10AA300001D5082000E0102081460420ADF814A0C4
+:10AA40001BAA8DF8100000921FA81AA90397CDE940
+:10AA5000011033884A4607212046FFF793F992E018
+:10AA60009DF868004FF00A09002894D121AA072018
+:10AA70008DE80700BDF87C0094F82010401E83B2DA
+:10AA8000208B002200F08FFC8DF868000B203870BE
+:10AA9000BDF8840019E09DF868004FF00C0900280B
+:10AAA0001CD123AA07208DE80700BDF87C00628C2A
+:10AAB000401E83B294F82010208B00F074FC8DF8B7
+:10AAC00068000D203870BDF88C00401CADF87C008B
+:10AAD00004208DF81000208BADF81400BCE057E086
+:10AAE0003188208B814253D19DF868104FF01209B4
+:10AAF000002918D1616A81B1B178C90748D0B3681B
+:10AB00000722CDE90032CDF808A0F388B28894F886
+:10AB1000201000F057FA8DF868001320387000E01C
+:10AB200002E0ADF87CB097E0B6F800C0208B844519
+:10AB30002ED19DF868004FF016090028606B08D0F0
+:10AB4000E0B34FF6FF7000215646ADF808A0019023
+:10AB500027E060B1B178C9071AD1618F43181FA8E7
+:10AB6000CDE900075A88998833F8060B09E0B078D8
+:10AB7000C0070DD01FA8CDE90007B288F188604654
+:10AB8000B368FFF7E4FA050066D0062D7AD03FE0FF
+:10AB900005253DE0019021AA02A92046FFF700FA11
+:10ABA0000146628FBDF80800824201D00029F1D031
+:10ABB000608F616B08440680019860874CE000005C
+:10ABC000200800209DF868004FF0180940B1208B44
+:10ABD000C8B13088208320463399FFF764FA3BE000
+:10ABE00004F118000090237E94F8201001222046E2
+:10ABF000FFF775FA8DF868000028ECD1192038703D
+:10AC0000ADF87CB0E7E7052520463399FFF74BFA0E
+:10AC10009DF81000032857D05CE0208800F40070F5
+:10AC2000ADF86C0048452CD1208FA0F57F41FE394E
+:10AC30007FF4D0AED8F808004FF0160948B1606331
+:10AC4000B8F80C1021874FF6FF716187A0F800A0BB
+:10AC500002E04FF6FF702087BDF86C0030F4FE6113
+:10AC600016D0782300220420339906F0C5FD98F809
+:10AC70000000A0702088BDF86C10084320800AE016
+:10AC800000E006252088BDF86C108843208021E074
+:10AC90002188814321809DF8100028B15F484168D8
+:10ACA00004A8FBF716F805469DF8680090B187F8F0
+:10ACB000019087F800B0208B78809DF8680038718B
+:10ACC0000520ADF87C0005E05448416804A8FBF776
+:10ACD00000F80546208810F4FE6F22D1208E00B3C4
+:10ACE0002799289B01AD0988ADF87C10DDE9321267
+:10ACF000009385E816001FABE26A2699FFF784FAF5
+:10AD0000054603280DD08DF810B0E06A0590339801
+:10AD10000690002104A8FAF7DCFF00B10546A4F86C
+:10AD200030A02798BDF87C1001802846E7E500B5E3
+:10AD300097B0042807D102208DF80000019100216E
+:10AD40006846FAF7C6FF17B000BD70B5334C0378FC
+:10AD500000222168012B02D0022B44D129E00B787C
+:10AD60000BB1042B03D10A712268032111702168F1
+:10AD7000062582880B7905EBC303CA522168082394
+:10AD80000A250A7903EBC2021144C2880A802168AD
+:10AD900002890B7905EBC303CA52418920680C2351
+:10ADA000027903EBC202815220680179491C0171CA
+:10ADB0001DE00A7482888A802168C288CA8022685D
+:10ADC00001891181226841895181C1682068C1606F
+:10ADD0006168FAF77EFF0146022806D02068007CF1
+:10ADE000002801D119B1812070BD832070BD0020E1
+:10ADF00070BD406B002800D0012070478178012988
+:10AE000009D10088B0F5205F03D042F601018842E5
+:10AE100001D1002070470620704700002008002064
+:10AE200010B58B7883B102789A4205D10B885BB15B
+:10AE300002E08B79091D4BB18B789A42F9D1B0F8B9
+:10AE400001300C88A342F4D1002010BD812010BD38
+:10AE500007282BD012B1012A2CD103E0497801F048
+:10AE6000070102E04978C1F3C201052922D2DFE8D7
+:10AE700001F0031D081017000AB1032070470220DB
+:10AE80007047042812D0052810D006280ED058B1DB
+:10AE90000EE005280AD0062808D0022808D003E0D2
+:10AEA000062803D0032803D00520704700207047F0
+:10AEB0000F2070478120704710B513880B800B78E6
+:10AEC0001C061FD5FE4CA47A844204D843F010001F
+:10AED0000870002010BD94682478C44064F3041303
+:10AEE0000B701378D17803F0030341EA032140F299
+:10AEF0000123B1FBF3F403FB1411926800FB012062
+:10AF0000401C10BD906810BD37B5BDF8041011800D
+:10AF10009DF8045029061BD5E94901239468897AD4
+:10AF2000814209D8FE280FD1E80602D58B405B1E6E
+:10AF300000E00023237007E0217883409943C5F3A4
+:10AF40000013834019432170107820F01000107016
+:10AF50003EBD2DE9F0410746C81C0E4620F0030017
+:10AF6000B04202D08620BDE8F081082A01D90E2027
+:10AF7000F9E7D34D002034462E60AF802881AA72B5
+:10AF8000E8801AE0E988491CE980810614D4E17858
+:10AF900000F0030041EA002040F20121B0FBF1F291
+:10AFA00001FB1201206800F0E3FA2989084480B20D
+:10AFB0002881381A3044A0600C3420784107E1D44D
+:10AFC0000020D0E72DE9FF4F85B01546DDE912B628
+:10AFD0008046994623F4404700F0BAFA04000BD0AB
+:10AFE000207800060AD5B648817A0698814205D8AD
+:10AFF000872009B0BDE8F08F0120FAE722466946B4
+:10B000000698FFF759FF824600208DF80400072EAE
+:10B0100018D0012221463046FFF71AFF0028E8D158
+:10B02000207840060ED502208DF80400ADF8088087
+:10B03000BDF80000ADF80C50ADF80A00ADF80E7088
+:10B04000CDF810B05FEA094004D500273D46B84668
+:10B0500001260CE02178E07801F0030140EA0120AC
+:10B0600040F20121B0FBF1F2804601FB12865FEA5B
+:10B07000494009D5B04507D1A178207901F00301F5
+:10B0800040EA0120A84201D3B54201D90720B0E728
+:10B0900078191FFA80F9B14501D90D20A9E79DF86B
+:10B0A000040020B101A8FAF712FE0028A1D1B04592
+:10B0B00007D1A0784FEA192161F30100A07084F84C
+:10B0C0000490149800B10780BBF1000F15D00AEB73
+:10B0D00005003A4659460FF0ADFE224669460698ED
+:10B0E000FFF7EAFE9DF80000224620F010008DF8E0
+:10B0F000000000990698FFF707FF002079E72DE987
+:10B10000FF4FDFF8BC9182461746B9F80610D9F810
+:10B11000000001EB410100EB810440F20120B2FB91
+:10B12000F0F183B000FB11764D46DDF844803146E6
+:10B13000049800F01DFA29682A898B46611A0C319F
+:10B1400001441144AB8889B28B4202D8842007B0F5
+:10B1500050E70499CDB2290603D5A90601D585206B
+:10B16000F5E7B9F806C00CF1010C1FFA8CFCA9F840
+:10B1700006C0129909B1A1F800C0A90602D5C4F809
+:10B18000088007E0104480B2A9F80800191A01EB02
+:10B190000B00A0602246FE200499FFF7B5FEE77081
+:10B1A00026712078390A61F30100320AA17840F053
+:10B1B000040062F30101A17020709AF8020060712E
+:10B1C000BAF80000E08000262673280602D599F818
+:10B1D0000A7000E00127A80601D54FF000084D468F
+:10B1E00000244FF007090DE0CDF80080CDE901966D
+:10B1F000E8882146109B069AFFF7E4FE0028A6D1B6
+:10B20000641CE4B2BC42EFD30020A0E72DE9F04774
+:10B21000804600F09DF9070005D000264446284DE1
+:10B2200040F2012916E00120BDE8F087204600F039
+:10B230008FF90278C17802F0030241EA0222B2FBE0
+:10B24000F9F309FB1321006800F092F93044641C03
+:10B2500086B2A4B2E988601E8142E7DCA8F1010051
+:10B26000E8802889801B288100203870DCE720B125
+:10B27000401E10809170002070470120704710B56B
+:10B280000F4904460088CA88904201D3822010BD2D
+:10B29000096800EB400001EB80025079A072D08871
+:10B2A00020819178107901F0030140EA0120A0810A
+:10B2B000A078E11CFFF700FE20612088401C01E01F
+:10B2C0002C0800202080E080002010BD0121018298
+:10B2D00070472DE9FC474FF6FF780546A2F800803D
+:10B2E000406817468A4680788DF8020068680088B2
+:10B2F000ADF8000000208DF80600288A2C88A042B6
+:10B3000000D304462C822DE0288A401C2882701D20
+:10B310006968FFF785FD18BB3988414501D1601E7A
+:10B3200038806888A04222D3B178307901F00301D7
+:10B3300040EA01296946701DFFF772FD80B96989ED
+:10B34000414519D0002231465046FFF781FD38B9FA
+:10B350006A894A4504D1E968B0680FF03FFD58B1E9
+:10B36000641CA4B2204600F0F3F80600CCD1641EA1
+:10B370002C828220BDE8FC877C807079B871F088CF
+:10B38000B8803178F07801F0030140EA012078813B
+:10B39000A7F80C90287A324607F10801FFF78CFDD8
+:10B3A00038610020E6E72DE9F04F85B01D46904654
+:10B3B0000F468346DDF838A0DDF8409000F0C8F86D
+:10B3C000040009D02078000608D57148807AB84278
+:10B3D00004D8872005B00DE60120FBE7C8F3090675
+:10B3E000224669463846FFF767FD07465046BAF1E0
+:10B3F000070F1AD000222146FFF72AFD0028E9D1C5
+:10B400002078400611D501208DF80400ADF808B071
+:10B41000BDF80000ADF80A00ADF80C60ADF80E50B4
+:10B4200001A8FAF754FC0028D4D12178E07801F083
+:10B43000030140EA0121A278207902F0030240EAE8
+:10B440000220464507D0B1F5007F04D9691E81422C
+:10B4500001DD0B20BEE7864201D90720BAE7801B39
+:10B4600082B2AA4200D92A46B9F1000F01D0A9F848
+:10B4700000200F9810B1B9190FF0DCFC0020A9E7EB
+:10B480002DE9F0411D4617460E4600F061F8040014
+:10B4900008D02078000607D53D48807AB04203D80E
+:10B4A000872060E501205EE5224639463046FFF7F9
+:10B4B00003FD65B12178E07801F0030140EA012045
+:10B4C000B0F5007F01D8012000E0002028700020A6
+:10B4D00049E52DE9F0411D4617460E4600F038F8C3
+:10B4E000040008D02078000607D52948807AB042A9
+:10B4F00003D8872037E5012035E522463946304616
+:10B50000FFF702FDFF2D14D02178E07801F003024F
+:10B5100040EA022040F20122B0FBF2F302FB1300EA
+:10B5200015B900F2012080B2E070000A60F3010159
+:10B530002170002017E510B50C4600F009F828B17D
+:10B54000C18821804079A070002010BD012010BD6D
+:10B550000F49CA88824209D340B1096800EB400014
+:10B560006FF00B0202EB8000084470470020704728
+:10B57000C0B2820609D4000605D50548807A484342
+:10B58000401C80B27047084670470020704700009A
+:10B590002C08002010B506F08BFB05F026FEFBF70B
+:10B5A00011FF0EF04FFB06F083FABDE8104006F0E5
+:10B5B0000FBB10B50C4601F0C1FC80B3204600F073
+:10B5C000ACFA68B322780E2A09D00F2A07D0022AD3
+:10B5D00005D0032A03D0102A2ED0FFDF1DE0A0786B
+:10B5E0001E282BD00FDC0C2824D008DC092825D2FB
+:10B5F000DFE800F013241724241E1E1A1C00122852
+:10B600001CD1072010BD302818DDA0F13A00032816
+:10B6100014D2DFE800F011130B00002010BD11E080
+:10B620000EE043F20200F9E70420F7E70D20F5E70A
+:10B630000F20F3E70820F1E71120EFE70320EDE703
+:10B64000FFDFEAE7FFDFE8E700F067BA70B503461F
+:10B65000002002466FF02F050EE09C5CA4F130063E
+:10B660000A2E02D34FF0FF3070BD00EB800005EBD7
+:10B670004000521C2044D2B28A42EED370BD30B595
+:10B680000A240AE0B0FBF4F304FB13008D183030F9
+:10B6900005F8010C521E1846D2B2002AF2D130BD74
+:10B6A00030B500234FF6FF7510E0040A44EA00208D
+:10B6B00084B2C85C6040C0F30314604005EA003403
+:10B6C0004440E0B25B1C84EA40109BB29342ECD34E
+:10B6D00030BD000010B509F0DBFB042803D009F0F1
+:10B6E000D7FB052802D108F0D4F950B909F05CFC69
+:10B6F000032803D009F05EFC032804D107F0AEFA5A
+:10B7000008B1012010BD002010BD70B50C460546E3
+:10B71000062102F092F9606008B1002006E00721DE
+:10B72000284602F08AF9606018B1012020700020DC
+:10B7300070BD022070BD2DE9FC470C4606466946E7
+:10B74000FFF7E3FF00287DD19DF8000058B107F016
+:10B75000E7F9B0427ED00022214630460BF0F9FCDA
+:10B76000002874D116E007F042FFB04272D00022E8
+:10B77000214630460BF0E0F8002868D1019D95F88D
+:10B780009800303518B9687E08B1012000E000202B
+:10B79000804603E0019D95F8498030354FF0010A5D
+:10B7A00095F82D004FF00009A0B195F82E00800704
+:10B7B00010D584F8019084F800A084F80290A68047
+:10B7C00095F82F10A171298E2181698E618185F8EC
+:10B7D0002D903CE0304602F0A8FA070000D1FFDFD0
+:10B7E000384601F049FD10F0FF0008D084F80190C0
+:10B7F0000D212170A680E08084F802A027E0304669
+:10B8000002F081FA070000D1FFDFB8F1000F21D06C
+:10B81000384601F0BCFDA8B19DF8000038B9019888
+:10B82000D0F8BC004188B14201D180F80090304688
+:10B8300007F0DBF884F801900A21217084F8029067
+:10B84000A68000E006E0A97EA17185F8199001208C
+:10B85000BDE8FC870020FBE71CB56946FFF755FFF4
+:10B8600000B1FFDF684601F0B1FBFD4900208968A7
+:10B87000A1F89A001CBD2DE9FC4104460E460620A5
+:10B8800002F086F80546072002F082F82844C7B285
+:10B890000025A8463E4417E02088401C80B2208046
+:10B8A000B04202D34046A4F8008080B2B84204D32C
+:10B8B000B04202D20020BDE8FC816946FFF725FFB7
+:10B8C0000028F8D06D1CEDB2AE42E5D84FF6FF70FF
+:10B8D00020801220EFE738B54FF6FF70ADF800007A
+:10B8E0000DE00621BDF8000002F0B9F8044607217A
+:10B8F000BDF8000002F0B3F80CB100B1FFDF002189
+:10B900006846FFF7B8FF0028EBD038BD2DE9F041BD
+:10B91000D4A0D64C06790025076884F8425001F07F
+:10B920004EFB84F8435004202087102060874FF698
+:10B93000FF70A4F80A0184F80C51A4F80E0184F8F1
+:10B94000315004F8EE5BC94804F8C05C04F8BA5CF6
+:10B950008030A57340F87D7FC4490671FD31481ED3
+:10B960000BF095F80A20207503206075A075E0752E
+:10B970000E20207606206076A076E076BDE8F08185
+:10B980002DE9F041B64C0D466060217007F015F8C6
+:10B99000FFF7A1FFFFF7BAFF207809F01CF8B349C1
+:10B9A000C431A1F181000F46064607F041FF6068EF
+:10B9B0000BF038F820780CF0C9FB284609F0C1FEDE
+:10B9C0003946304607F0E8F860680BF04DFC01F0AE
+:10B9D000F6FAA649002081F84300CFE710B501240C
+:10B9E0000AB1002010BD21B1012903D00024204656
+:10B9F00010BD02210DF096FBF9E72DE9F047040098
+:10BA000000D1FFDF994D002695F8310058B16670DE
+:10BA10001020207095F83200A07095F83300E07087
+:10BA200085F831606AE0287840B12C22A91C2046B4
+:10BA30000FF000FA0E2020702E705FE095F82E00B7
+:10BA400060B10120E07095F82F00A07095F83000EB
+:10BA500060700F20207085F82E604FE0844802212E
+:10BA60008246FFF708FF00B1FFDFB5F80E91062010
+:10BA700001F08EFF0746072001F08AFF3844C7B265
+:10BA8000781C00F0FF0800BFB5F80E01B84213D1D2
+:10BA90000021204607F05EFD58BB95F8340080B3C6
+:10BAA0006670132020701C21A01C0FF03AFA0220AF
+:10BAB000A07085F8346021E040451BD1002120466C
+:10BAC00007F000F8E8B12078132817D1A0783C28B7
+:10BAD00014D1A088072101F0B0FF050000D1FFDFDD
+:10BAE000288806F082FFA088072101F0B8FF00B186
+:10BAF000FFDF03E02146FFF71EFE10B10120BDE885
+:10BB0000F087FFE702215046FFF7B5FE18B9B5F8F8
+:10BB10000E114945B8D10020F1E76EE710B508F0E5
+:10BB2000C8FE00B1FFDF0AF07BFF00B1FFDF07F0C6
+:10BB300035FE09F0EFFD00B1FFDF0BF093FB00B124
+:10BB4000FFDF06F0F7FF00B1FFDF0CF0F9FA00B1FC
+:10BB5000FFDFFFF7C0FEFFF7D9FE06F017FF02F088
+:10BB6000C1F801F02CFA4148002180F8431001711E
+:10BB7000012141710222C270017010BD10B53B4C11
+:10BB8000207828B10A21BDE810400E2001F0E4B968
+:10BB9000FFF7A0FD08B10C2002E001F010FA002030
+:10BBA0002071012060710A21E170207010BD70B514
+:10BBB0002E4C0546207828B1BDE8704039210E2072
+:10BBC00001F0CAB9FFF786FD08B10C2012E094F825
+:10BBD000430008280DD204EB0010102229464430FF
+:10BBE00001F0C7F994F84300401C84F8430000209A
+:10BBF00000E007202071012060713921E170207080
+:10BC000070BD70B5194C0546207828B1BDE870406C
+:10BC10000B210E2001F0A0B9287818B1012801D01D
+:10BC2000122016E094F8C400082823D2FFF752FD32
+:10BC300008B10C200DE00E482B7894F8C4106A1C53
+:10BC4000463806F01AF994F8C400401C84F8C40081
+:10BC500000202071012060710B21E170207070BD07
+:10BC600044000020FFFFFFFF1F00000038080020F5
+:10BC7000460900200720ECE710B5FE4C207828B1DB
+:10BC80003821BDE810400E2001F066B9FFF722FD13
+:10BC900008B10C2002E0002084F84300207101204C
+:10BCA00060713821E170207010BDF248017819B13F
+:10BCB0000F210E2001F050B9002101710E21817079
+:10BCC0000F21C170FF2181714FF6FF710181EA4997
+:10BCD00049680A7882728A8882814988C1810121F3
+:10BCE000417101707047E3490A781AB13B210E2077
+:10BCF00001F032B90088A1F80A01012081F80C0195
+:10BD000000220A7148713B22CA700870704710B552
+:10BD1000D84C207828B12B21BDE810400E2001F02E
+:10BD20001BB90821A01D05F0F9FA0020207101209F
+:10BD300060712B21E170207010BD70B5CD4C217861
+:10BD400029B1BDE8704031210E2001F005B990F90C
+:10BD50000000042814D098B1011D11D010F1080F73
+:10BD60000ED010F10C0F0BD010F1100F08D010F105
+:10BD7000140F05D010F1280F02D01220207103E01B
+:10BD8000002506F0BBF825713120E07001206071BC
+:10BD9000207064E730B5B74D04468DB0287828B1DF
+:10BDA0002A210E2001F0D8F80DB030BD1022214616
+:10BDB000684601F0DEF8102204F1100104A801F039
+:10BDC000D8F868460DF0D6FF10222C46A81D08A909
+:10BDD00001F0CFF8002020710E20A0702A20E07022
+:10BDE000012060712070DFE72DE9FF41A14C207830
+:10BDF00028B13A210E2001F0AFF8BDE8FF814FF0E5
+:10BE0000000884F80680B4F80A01ADF8040002A91D
+:10BE1000FFF77BFC20B1002101A8FFF72CFDE8BB58
+:10BE2000BDF80400ADF8000002A980B2FFF76DFC78
+:10BE300000B1FFDFBDF8000001F077FF050000D181
+:10BE4000FFDF2846039F01F0A9FA80F0010697F86A
+:10BE50004950BDF8000001F056FF070000D1FFDF98
+:10BE6000384601F094FA80F0010255EA020019D038
+:10BE7000A179BDF8000004EB410108817D49A37957
+:10BE80001831585C65F300005854A37962F34100FF
+:10BE90005854A27966F38200505400E00DE0A07976
+:10BEA000401CA07100216846FFF7E5FC28B9BDF8E9
+:10BEB0000000BDF804108842B6D1012084F8048047
+:10BEC00060713A21E170207097E770B5694C0546C2
+:10BED000207828B1BDE8704034210E2001F03CB834
+:10BEE00008F0D6FF052804D0284608F061FD0020A0
+:10BEF00000E00C202071012060713421E17020707D
+:10BF0000ADE65C48017819B10E21084601F024B86D
+:10BF10005949CA68C0F80620098A41810021017187
+:10BF2000012141710E22C2700170704770B5514CF1
+:10BF30000646251D207828B1BDE8704032210E202C
+:10BF400001F00AB83146002006F00EFF287058B9FB
+:10BF500000213246084607F053FD287020B94648B4
+:10BF60003168C160B1880182012060713221E170C5
+:10BF7000207074E670B53F4C0546207828B1BDE8C6
+:10BF8000704030210E2000F0E7BF08F0C4FD10B96A
+:10BF900009F064FE68B1287809F034FC287807F0CD
+:10BFA000A7FD00202071012060713021E170207018
+:10BFB00055E60C20F6E72DE9F0412E4C0646251DEE
+:10BFC000207828B1BDE8F04117210E2000F0C4BF51
+:10BFD0003146012006F0C8FE2870012768B93246B4
+:10BFE0000121002007F00CFD287030B93068E063B3
+:10BFF000B088A4F8400084F8427067711720E070A0
+:10C000002770BBE438B51B4D0446287828B1BDE83D
+:10C01000384030210E2000F09FBF227961798A429A
+:10C0200015D0A079E379984211D01F2A0FD81F2983
+:10C030000DD8002211460EF03DF940B90022E079FA
+:10C0400011460EF037F910B9207A072801D91220CD
+:10C050001BE04FF6FF70ADF8000008F0A5FFD8B95F
+:10C0600008F0A8FFC0B908F013FFA8B9002168467E
+:10C0700004E000003808002044000020FFF7FBFB2C
+:10C0800050B1204605F032FE002028710120687171
+:10C090003E21E970287038BD0C20F6E72DE9FC47F9
+:10C0A000FE4C054694F82E0028B128210F2000F000
+:10C0B00053FFBDE8FC87282084F83000012184F874
+:10C0C0002E10A8784FF000091A2825D00EDC16286B
+:10C0D00031D2DFE800F030303030302130303030D5
+:10C0E0003030303030303030302121212A2822D0F9
+:10C0F0000BDCA0F11E000C281DD2DFE800F01C1C98
+:10C100001C1C1C1C1C1C1C1C1C0D3A38042812D2A4
+:10C11000DFE800F0110211022888B0F5706F0AD232
+:10C120001F20884684F82F0028886946FFF7EDFA1B
+:10C1300018B1022019E0122017E09DF80000019FBD
+:10C14000002806D007F1CE07019E05D106F1B506FD
+:10C1500004E007F1B407F7E706F1CF06684600F000
+:10C1600023FF08B1387818B10C2084F82F00A0E71D
+:10C1700087F80080A878307084F82F90684600F027
+:10C1800025FF96E77CB5C54C0546207820B12521D2
+:10C190000E2000F0E1FE7CBD28886946FFF7B5FA65
+:10C1A000002168B102202071BC4881600173E180E8
+:10C1B0000E20A0702520E0700120607120707CBDF1
+:10C1C000019A104612F1300282F836108368A3609B
+:10C1D000037B237392F83630002BF5D12888E0805A
+:10C1E000E6E72DE9FC41AD4C064694F82E0028B157
+:10C1F00010210F2000F0B0FEBDE8FC811F2084F864
+:10C200002F00102084F83000012784F82E70308829
+:10C210006946FFF77AFA70B9684600F0C5FE50B17A
+:10C22000019D9DF8000030350028019805D0E230CE
+:10C23000017841B904E0022006E0D0F8BC00F7E73D
+:10C2400095F82D1019B13A2084F82F00D4E795F80D
+:10C250002E1089070CD1042101709DF8000020B92F
+:10C2600001993088D1F8BC104880684600F0AEFED5
+:10C27000002084F82F0085F82D70BDE72DE9F047E8
+:10C28000864D0646287828B1BDE8F0471D210E20CE
+:10C2900000F062BE4FF01F0985F80490012068711C
+:10C2A0001D21E970287008F0F3FD0C2704284ED0FA
+:10C2B00005284CD0B0791224012800D0E8B9307894
+:10C2C00008B1012819D1F07908B1012815D1708879
+:10C2D00043F6FD71021F30248A420ED2B288121F2B
+:10C2E0008A420AD22887B0886887B0794FF0000860
+:10C2F0004446012803D050B111E02C710CE495F8AC
+:10C30000420020B3654A3C320121084602E0644AFB
+:10C310000021012007F074FB040000D0FFDFF0795A
+:10C32000012800D010B907F093FB044614B185F83A
+:10C330000490E3E73078012801D018B109E000212A
+:10C34000022001E00021012007F097FB08B12F71C6
+:10C35000D4E785F80480D1E770B5504C217829B135
+:10C36000BDE870401E210E2000F0F6BD1F21217196
+:10C37000012161711E22E270217002781221012ACE
+:10C3800000D01AB9407818B1012801D0217166E4B3
+:10C3900000260C25012A08D008F07AFD052802D0D5
+:10C3A00008F034FA30B1257159E4618F208F08F01C
+:10C3B000BFFBF7E7267152E42DE9FE4F0546AFF2C9
+:10C3C0005C71D1E90001354E01908A4696F82E0045
+:10C3D00030B103B02121BDE8F04F0F2000F0BCBD0B
+:10C3E0001F2086F82F00212086F830004FF001082A
+:10C3F00086F82E80298843F6FD730A1F30209A4262
+:10C400007ED26A88141F9C42FAD28A4278D8EA897E
+:10C4100040F67B43911F9942F2D2298A8C1F9C429D
+:10C42000EED28A42F2D86A8AB2F5FA7FE8D2AA8AB4
+:10C4300040F67744A2F10A03A342E1D2B2EBD10F56
+:10C440005ED9E98A2A8B9142E0D82979122011B16C
+:10C45000012955D102E069790029F9D1297B09B177
+:10C460000129F6D108F014FD4FF00C0905286ED013
+:10C4700008F00EFD0428FAD096F83400002866D1A2
+:10C4800007F0B5F8A0F57F41FF39F8D1062102A8E1
+:10C4900001F0A4FA040050D0032103E03808002082
+:10C4A000500000200CF02CFB96F8030100901B229A
+:10C4B00096F802312088114601F070FB04283ED026
+:10C4C00000B1FFDF208806F08FFA04F10D07B4F801
+:10C4D00000B00421384604F021FF594638460CF0DC
+:10C4E00004FCFDA03F1D006800900321684604F095
+:10C4F000A0FE002069460A5C3A54401CC0B200E02D
+:10C500006FE00328F7D3288A6080688AA080A88A11
+:10C51000E08096F8051196F8040108F0C8FA014683
+:10C52000204608F0F0FA002784F8367084F8377057
+:10C53000687968B101280FD10CE0092051E020880A
+:10C54000062101F08CFA00B1FFDF072049E071E01D
+:10C55000677601E084F81980D5F80600C4F81A005F
+:10C560006889E0830198A06084F80CA084F8C480F6
+:10C570008DF800700121684604F05BFE9DF8000014
+:10C5800000F00701C0F3C1021144C0F34010084499
+:10C590008DF80000401D2076092801D20830207651
+:10C5A000002120460CF0ACFA287B18B1012805D0F8
+:10C5B000FFDF24E00021C94A012005E096F842008F
+:10C5C00098B10121C64A084607F01AFAB8B1208886
+:10C5D00006F00BFA2088062101F041FA00B1FFDFD6
+:10C5E0001F2086F82F00BDE8FE8F208806F0FDF999
+:10C5F0002088062101F033FAE0B1FFDF1AE0287944
+:10C60000012800D010B907F023FA50B921460320C1
+:10C6100007F033FA28B96A882988204608F005FA15
+:10C6200058B1208806F0E1F92088062101F017FAB8
+:10C6300000B1FFDF86F82F90D5E784F8B87086F850
+:10C640002F70D0E738B5A64C3C3C207820B1222191
+:10C650000E2000F081FC38BD1F202071012565717E
+:10C660002220E070257008F013FC052802D00C2071
+:10C67000207138BD00202071684608F090FA00282B
+:10C68000F7D10098008806F0B0F9009806210088DC
+:10C6900001F0E5F900B1FFDF904884F834500C3820
+:10C6A0000078FCF78DFF38BD2DE9F0418C4D044634
+:10C6B0003C3D95F82E0028B1BDE8F04123210F2024
+:10C6C00000F04ABC1F2085F82F00232085F8300099
+:10C6D000012085F82E00618840F67B438A1F3020B8
+:10C6E0009A4251D2A288961F9E424DD291424BD877
+:10C6F000E188B1F5FA7F47D2218940F67746A1F16A
+:10C700000A03B34240D2B1EBD20F3DD96189A2896D
+:10C71000914239D84FF000082088062101F08DF9A8
+:10C7200006004FF0020707D000F030FC20B1D6F829
+:10C73000BC00017839B902E085F82F7061E4D6F8C1
+:10C74000D010097809B13A201EE005218171D6F890
+:10C75000BC004146A0F80880D6F8BC20A0885081D3
+:10C76000D6F8BC20E0889081D6F8BC202089D08102
+:10C77000D6F8BC00028943899A4204D88279082AF3
+:10C7800001D89A4203D3122085F82F0039E4228879
+:10C790004280D6F8BC00077085F82F1031E42DE9EF
+:10C7A000FE434F4C06463C3C207830B103B0242178
+:10C7B000BDE8F0430E2000F0CFBB012565712420B9
+:10C7C000E070257030460CF0B2FA08B1002000E0AD
+:10C7D0001220207100282DD1414884F8FC504430AB
+:10C7E000316840F87D1F317901714FF0000884F8FD
+:10C7F000FC806946062001F0ACF800B1FFDF684616
+:10C8000001F085F8A0B9BDF8047000BFBDF80400C0
+:10C81000062101F012F9060000D1FFDF86F8C450AE
+:10C82000684601F074F818B9BDF80400B842EDD1BB
+:10C8300084F80480BDE8FE8370B5294D06463C3D72
+:10C8400095F82E0028B1BDE8704026210F2000F099
+:10C8500083BB1F2085F82F00262085F8300001209B
+:10C8600085F82E003088062101F0E7F8040007D093
+:10C8700000F08CFB20B1D4F8BC00017831B901E0A4
+:10C8800002200CE0D4F8D010097809B13A2006E073
+:10C8900005210170D4F8BC1030884880002085F84C
+:10C8A0002F0074E50E483C38017819B106210E209E
+:10C8B00000F052BB002101710E2282700622C2706C
+:10C8C000C0F80610C0F80A10817941F001018171A9
+:10C8D0000121417101707047112233005000002086
+:10C8E0007408002070B5F84E054696F82E0028B161
+:10C8F000BDE870402C210F2000F02EBB1F2086F8D1
+:10C900002F002C2086F83000012086F82E00288881
+:10C91000062101F092F8040007D000F037FB20B1A7
+:10C92000D4F8BC00017831B901E0022020E0D4F84D
+:10C93000D010097809B13A201AE094F86410D1B106
+:10C94000D5F802104160D5F80610816054F8BC0F8C
+:10C95000698910228181206805F10C010E300EF0EA
+:10C9600069FA21680320087021682888488000201F
+:10C9700086F82F000BE50C20FAE770B5D24E04467E
+:10C980000C25307828B1BDE8704018210E2000F049
+:10C99000E3BA08F009FB032852D008F00BFB032888
+:10C9A0004ED0607908B1012829D1A07908B10128B9
+:10C9B00025D1A07B28B1012803D0022801D003286B
+:10C9C0001DD1607BD8B1C00819D162884FF4804076
+:10C9D000824202D82188814203D9207901280ED1D0
+:10C9E00018E0207930B1012814D0022805D003289E
+:10C9F00005D102E0202A0BD30CE0A0290AD220792D
+:10CA0000042805D12088202802D36188884201D9D2
+:10CA1000122515E0207986F83600607910B10128DA
+:10CA200004D00DE0A94A0021204606E096F8420015
+:10CA300030B1A54A01213C32204606F016F90546E0
+:10CA40000120357170711821F17030709FE410B5BC
+:10CA50009D4C217829B11A21BDE810400E2000F02C
+:10CA60007BBA01781F2902D91220207106E000212B
+:10CA700021710278411C104606F0A8F9012060716E
+:10CA80001A21E170207010BD10B58F4C217829B1AA
+:10CA90002021BDE810400E2000F05EBA01781F2969
+:10CAA00002D91220207106E0002121710278411C78
+:10CAB000104606F07AF9012060712021E1702070A3
+:10CAC00010BD2DE9FC41804C217829B1BDE8FC4125
+:10CAD0001B210E2000F040BA012767710C21217143
+:10CAE00000780026012803D000286AD012205CE0DC
+:10CAF00006F085F800287ED094F83600A0B1012811
+:10CB000012D0042810D008F055FA002873D108F08C
+:10CB10004BFA18B108F048FA02286CD1002008F04E
+:10CB200074FEE0B3FFDF4AE008F03EFA002862D16D
+:10CB300008F040FA00285ED105F0F2FFA0F57F4131
+:10CB4000FF3958D1072101A800F048FF5F49054689
+:10CB50000C398860280000D1FFDF032128460BF044
+:10CB60001DFF284606F0FCF994F8091194F8080115
+:10CB700008F023FA0146284608F04BFA94F807011A
+:10CB800000901B2294F806312888114601F006F81F
+:10CB900068B1042800D0FFDF2888072100E00EE0FC
+:10CBA00000F05DFF00B1FFDF0720207123E028883F
+:10CBB00005F01AFF284608F028FE00B1FFDF2671B5
+:10CBC00019E008F0F1F9032803D008F0F3F903287D
+:10CBD00011D108F0ECF90546002008F027FD50B906
+:10CBE000267145B1288805F000FF2888072100F04C
+:10CBF00036FF00B1FFDF1B20E0702770BDE8FC812D
+:10CC00002DE9F041304C0646207828B1BDE8F041CE
+:10CC10002D210E2000F0A0B93088072100F00DFF73
+:10CC200005004FF0010720D095F8D10040B995F8E4
+:10CC30003C000F2801D0102802D195F8040150B112
+:10CC40000C2020710E20A0702D20E0703088E08034
+:10CC50006771277072E51022B11C05F1D2000EF049
+:10CC6000E9F885F8D1700020EBE70220E9E770B51C
+:10CC7000154C0546207828B1BDE870402E210E20C5
+:10CC800000F06AB92888072100F0D7FE022178B1A8
+:10CC900090F8D1202AB990F83C200F2A04D0102A0D
+:10CCA00002D00C20207104E080F8D1100020F9E7B8
+:10CCB00021710E20A0702E20E0702888E0800120D5
+:10CCC00060712070EDE50000380800205000002061
+:10CCD0007CB5C54C0546207820B137210E2000F0E8
+:10CCE0003BF97CBD28886946FEF70FFD38B102206C
+:10CCF0002071012060713721E17020707CBD0198A6
+:10CD00007F22014680F8382080F83920002280F800
+:10CD10003A20A87801F8280FE878487028798870B8
+:10CD20002271E6E71CB5B04C217821B113210E2009
+:10CD300000F012F91CBD00886946FEF7E6FC08B158
+:10CD4000022005E0019890F82810012902D00C205B
+:10CD5000207106E0382100222271095C21720088CE
+:10CD6000E080012060711321E1700E21A17020701C
+:10CD70001CBD2DE9F0419C4C0546207828B1BDE84A
+:10CD8000F04135210E2000F0E7B8A87808B101285D
+:10CD900003D1A888B0F5FA7F01D912202071288824
+:10CDA000072100F04AFE0126A0B1002780F8C870D4
+:10CDB000A988A0F8CA1080F8A460A978012900D039
+:10CDC000002180F8C81090F8A50008B108F01CFEFA
+:10CDD000277101E00220207166713520E070267015
+:10CDE000ACE42DE9F041804C0546207828B1BDE83F
+:10CDF000F0413C210E2000F0AFB82888072100F058
+:10CE00001CFE012358B382886D88C688418803EBD5
+:10CE10004207BD4217D342F210777E43BF107943D9
+:10CE2000B6FBF1F1491E89B24FF4FA76B14200D94E
+:10CE300031468D4200D22946491C521CB1FBF2F109
+:10CE40005143491E8AB290F8F01001B90284E28081
+:10CE50000020207163713C20E07023706EE402209A
+:10CE6000F7E770B5604C0546207828B1BDE8704002
+:10CE700033210E2000F070B808F096F808B10C20AD
+:10CE800017E0297889B10A290FD014290DD01E295D
+:10CE90000BD0282909D0322907D04B2905D0642985
+:10CEA00003D0FF2901D0122003E0284608F04FFDEF
+:10CEB00000202071012060713321E1702070F0E4C6
+:10CEC00049490A781AB13F210E2000F045B80022E6
+:10CED0000A710278454B4AB1012A0CD01220087120
+:10CEE000012048713F22CA700870F4E4D0F80100B4
+:10CEF000C3F80200F4E7D0F80100C3F80600EFE73A
+:10CF000070B5394C0546207828B1BDE870403D2108
+:10CF10000E2000F021B808F047F810B908F04AF8E0
+:10CF200008B10C2003E0287805F060FF0020207194
+:10CF3000012060713D21E1702070B2E410B50178EC
+:10CF4000402907D22A4A52F8211019B1801C88477B
+:10CF5000012010BD002010BD234A92F83130002B73
+:10CF600006D182F8320082F83310012082F83100B5
+:10CF7000B1E430B5134606E0CC18D51A14F8014CCC
+:10CF80005B1E4455DBB2002BF6D130BD90F8491042
+:10CF900041B990F8981029B190F89800042801D070
+:10CFA000012098E4002096E40178406821B190F8CF
+:10CFB000490010B100208EE4E8E701208BE40A4824
+:10CFC0000021C0F8F81080F8C41084E40178012929
+:10CFD00009D1406890F8A510002904D0002180F8FC
+:10CFE000A51008F011BD76E43808002038090020AB
+:10CFF0004CB301003D3070470844C01D424301F16D
+:10D000003D00104480B2704770B51C460546A0181C
+:10D01000049BC01D00FB03F204F13D00104486B2E6
+:10D02000B14238BFFFDF1C2128460DF07AFFA6F180
+:10D030001C0080B22C752880B0F5004F88BFFFDF40
+:10D0400070BD008870472DE9F04F0E468188044678
+:10D0500000F11C0AC088154620F4004221F4004368
+:10D06000002721F4004820F400499A4208D100F436
+:10D07000004001F4004188421CBF0020BDE8F08F51
+:10D08000C14517D9207DA9EB0801091AC91F8D4296
+:10D0900027DCC11D0AEB08000144C91E71603581FF
+:10D0A000F7603782011D3160058047800120A07440
+:10D0B000BDE8F08F2088217DA0EB0800401AB0F178
+:10D0C000070B0ED4BBF11B0FB8BFFFDF5D45D4BF0C
+:10D0D00028461FFA8BF0291A0A04120C18BF4A4579
+:10D0E00003DDA7740020BDE8F08F217DCB1D0AEB86
+:10D0F00008010B44DB1E7360308104F11C03F360F4
+:10D1000032820B1D336008804A800120A074BDE884
+:10D11000F08F2DE9F041044600F11C02808820F4D4
+:10D120000043A07C002808BFBDE8F081D018028829
+:10D13000438813448B423CBF0020BDE8F0810027A8
+:10D1400091429CBF0180478013D9891A0D042D0C90
+:10D1500045800ED0A088261D20F40040854288BF5F
+:10D16000FFDF30884FF4004121EA0000284330807F
+:10D1700008E0217D0088CB1D184481B22288201D43
+:10D1800000F09AFAA7740120BDE8F08130B4B0F83D
+:10D1900002C08488034600F11C052CF4004028449A
+:10D1A000A44503D10020D88130BC7047B3F80AC031
+:10D1B0000488A44509D34088ACEB040CA0EB0C0018
+:10D1C00084B20CEB0500C01E06E0A4EB0C041D7D30
+:10D1D000A4B2AC446044001DB1F800C0A44588BFAF
+:10D1E0000C80B3F80AC0BCF1000F0CBF4FF0010C6B
+:10D1F0004FF0000C82F800C00988D98130BC70471C
+:10D200002DE9F041044600F11C01408820F4004063
+:10D210004518E089002808BFBDE8F081618908440D
+:10D2200080B2608129886A881144814238BFFFDF5B
+:10D2300028886D88628941190027914218D175B1FB
+:10D240006088A61C20F40040A84238BFFFDF308869
+:10D250004FF4004121EA00002843308007E0217D9F
+:10D260002288CB1D184481B2A01C00F025FA6781EA
+:10D27000E7810120BDE8F0812DE9F0470189B0F890
+:10D2800002800027044600F11C0A414518BF4FF4F4
+:10D29000004938D021F400400AEB00014E886EB1FD
+:10D2A000208904F1080520F40040B04238BFFFDFB8
+:10D2B000288829EA0000304328801FE0207D238948
+:10D2C000C21D088823F4004510442188284480B2F8
+:10D2D00004F1080C88420AD2091A89B21B32914221
+:10D2E0002CBF03F4004129EA030004D204E0401AF1
+:10D2F00080B229EA03010843ACF80000781C2189B8
+:10D3000087B24145C6D13846BDE8F0872DE9F047E0
+:10D31000B0F806800B46044600F11C01B0F80890F6
+:10D32000408828F4004C01EB0C05804504BF002028
+:10D33000BDE8F087002A1CBF281D106023B1227DA4
+:10D34000291D18460DF076FD2F886D8885B1E819E6
+:10D3500087B2E088A61D20F40040A84238BFFFDF56
+:10D3600030884FF4004121EA00002843308007E074
+:10D37000207D2288C31DD81981B2A01D00F09CF920
+:10D38000C84504BFE08820813846BDE8F087418861
+:10D39000808881420CBF0120002070474188C088EE
+:10D3A00088420CBF01200020704730B44488828836
+:10D3B00000F11C0324F4004C22F400416344944225
+:10D3C0001BD04289C48915191C885A88A3189D420C
+:10D3D00016D312B18A4210D212E0037D0CF1070C71
+:10D3E0001A196244008892B2801A80B2223398429D
+:10D3F00001D211B104E08A4202D130BC0020704752
+:10D4000030BC012070472DE9F0078588C48800F101
+:10D410001C06024625F4004C24F4004925F4004A79
+:10D42000002024F4004306EB0C074FF00108D1451F
+:10D430000AD104F4004405F40045AC4204D0108243
+:10D44000BDE8F00700207047634506D9147DA3EBC3
+:10D450000C031B1BDD1F002305E01488157DA4EBC6
+:10D460000C04641BE51F002DE9DB94895CB13C884A
+:10D470007F8847B1DB1BD0748B42E0DB908930445E
+:10D48000001BC01E12E02D1BD0748D4206DB107DE8
+:10D490009389C01D60443344184406E08B42CEDBC0
+:10D4A00082F8138090893044001BC01E1182BDE8B1
+:10D4B000F00770472DE9F05F044600F11C088088F2
+:10D4C000924620F4004B208A894608EB0B0608B1EF
+:10D4D000484502D20020BDE8F09FA089002804BF83
+:10D4E00000273D4605D0378875887919884218BFCE
+:10D4F000FFDFE07C50EA050101D078B338E0A08975
+:10D5000050B1217D4044C91D59440844B4F8151058
+:10D5100020F8031DE17D8170A18907EB09004944D2
+:10D52000A181308000257580207DBAF1000F09D0DF
+:10D53000C31D30882288184481B2201D00F0BCF839
+:10D54000A5813AE0A189C01D58444144084430F8FF
+:10D55000031DA4F815108078E0752EE0FFE7A08980
+:10D56000B4F815104044C01B20F8031DE17D817004
+:10D5700005EB090085B2A089BAF1000F4844A081EB
+:10D580003780758010D0A088261D20F40040A84266
+:10D5900038BFFFDF30884FF4004121EA0000284304
+:10D5A00030800020A08108E0A0894044C01B30F8F2
+:10D5B000031DA4F815108078E07500202082A07467
+:10D5C0000120BDE8F09F10B4B0F802C0848800F1DB
+:10D5D0001C022CF400431344A44504D0B0F80AC044
+:10D5E000BCF1000F02D010BC0020704703F1040C06
+:10D5F000C1F800C0007D00F1070C0CEB0300C01E59
+:10D60000486018880881CA605B880B8220B9D01EE8
+:10D6100048600B810020088210BC0120704770B563
+:10D62000044600F11C018288408820F4004319441C
+:10D63000904205D06289002A04BFE289002A01D005
+:10D64000002070BD0A884D8885B1A61C20F40040DA
+:10D65000A84238BFFFDF30884FF4004121EA0000C4
+:10D66000284330800020E081012070BD207DC31D53
+:10D67000981881B22288A01C00F01EF8F2E7002161
+:10D680008181C1740182817470478289002A04BF3C
+:10D6900000207047828800F11C0322F400421A44E3
+:10D6A000B2F800C0BCF1000F1DBF037D121D1A446B
+:10D6B000DA1E4A608089704710B4B0F800C02CF4BC
+:10D6C0000044214489B24FF4004491420AD2521AD4
+:10D6D00092B21B339A422CBF0CF4004224EA0C0194
+:10D6E00004D204E0891A89B224EA0C0211430180B1
+:10D6F00010BC70472DE9F04188464FF6FC7102F1ED
+:10D7000003021E46040002EA010509D00027E01CBE
+:10D7100020F00300A04200D0FFDF201D01210CE01B
+:10D720000127F4E7024628442FB9B14201D203464B
+:10D7300000E000231360491CC9B2B142F2D9011BB9
+:10D74000C8F80010002F04D10EB1201D00E0002009
+:10D750002060BDE8F081024600201168002902D057
+:10D76000084609681160704702680A6001607047E6
+:10D770004FF6FC73C91C1940101A001F90FBF1F002
+:10D78000C0B270474FF6FC73C91C1940001D01FB65
+:10D7900002007047F8B5D24D04460E46A878A04264
+:10D7A00000D8FFDF05EB8607B86A50F8240000B107
+:10D7B000FFDFB868FFF7CFFF05000DD0B86A062E6F
+:10D7C00040F824500AD0082E00D3FFDFC548294670
+:10D7D00050F82620204690472846F8BDC048C24B46
+:10D7E0007A30A0F12E0200902946204609F08FF8E9
+:10D7F000F2E72DE9F84F8046DDF828901E4603EB4E
+:10D80000090093468A46C4B25FEA080707D000259C
+:10D81000FF2800D9FFDFBAF1000F03D101E0012595
+:10D82000F6E7FFDF08F1030020F00301414500D0D7
+:10D83000FFDFCB4500D9FFDF65B9A94A00204C3294
+:10D840004FF6FF7110705180A74A1070A44A7A32C7
+:10D8500010705180A24880F800B046708470C47087
+:10D860000471447180F80690DFF878B2C671002622
+:10D870000BF1400B8146FF1C27F003000746002DEB
+:10D8800002D109EB860188603BF8162019F80630B2
+:10D8900001D04FF000006946FFF72CFF0098761C7E
+:10D8A000F6B20744082EE6D3FF1C27F003002346F8
+:10D8B000064675B1002002226946FFF71BFF00985B
+:10D8C0003118002003464E46C91C21F003021DB149
+:10D8D00010E0C9F84800EEE706EB80070021BA62C5
+:10D8E00006E000BFD7F828C04CF82130491CC9B267
+:10D8F000A142F7D3401CC0B202EB84010828E3D355
+:10D90000A1EB0800AAF800000020BDE8F88F10B5D0
+:10D91000044604F075F808B1102010BD2078704A54
+:10D92000618802EB800092780EE0836A53F8213020
+:10D9300043B14A1C6280A180806A50F82100A06037
+:10D94000002010BD491C89B28A42EED861800520B2
+:10D9500010BD70B505460C46084604F051F808B1F4
+:10D96000102070BD082D01D3072070BD2570002048
+:10D97000608070BD0EB56946FFF7EBFF00B1FFDFB9
+:10D980006846FFF7C4FF08B100200EBD01200EBDA0
+:10D9900010B50446082800D3FFDF5148005D10BDD4
+:10D9A0003EB5054600246946FFF7D3FF18B1FFDFF7
+:10D9B00001E0641CE4B26846FFF7A9FF0028F8D034
+:10D9C0002846FFF7E5FF001BC0B23EBD44498978F9
+:10D9D000814201D9C0B27047FF2070472DE9F04164
+:10D9E0000C460546062901D0072C10D13C4FB86CD7
+:10D9F000FFF7B1FE02004FF6FF7604D00221B86CAB
+:10DA0000FFF7B6FE00E030462880B04202D1002089
+:10DA1000BDE8F0812146FFF7BDFE040002D1288851
+:10DA200000F050F82046F3E7A0F57F42FF3A01D01E
+:10DA3000082901D300207047ACE6A0F57F42FF3AE9
+:10DA40000BD0082909D2264A9378834205D902EBE4
+:10DA50008101896A51F820007047002070472DE944
+:10DA6000F04104460D46A4F57F4143F20200FF3920
+:10DA7000CED0082D01D30720CAE719494FF000087E
+:10DA80008A78A242C4D901EB85072146BA6A52F8C6
+:10DA90002460002EBCD0134A08462032314652F88A
+:10DAA00025209047B96A062D41F8248001D0072D22
+:10DAB00002D1204600F006F83146B868FFF754FE60
+:10DAC0000020A5E710B5064CC2B20221A06CFFF7FA
+:10DAD00059FE0146A06CBDE81040FFF745BE0000AE
+:10DAE000480900204CB40100560000200146A0481F
+:10DAF000002200680260037A00EB830040F80C2FDC
+:10DB00008180114600F025B92DE9F05F9846DDF8D7
+:10DB100030B0DDF828A01546894604004FF0000615
+:10DB200025D00027E01C20F00300A04200D0FFDF3A
+:10DB30007DB30120FFF75EFA00FB05620AEBCB0024
+:10DB4000104486B20120FFF755FA00FB05620B99DD
+:10DB500008EBC100104405EB450100EB4100143017
+:10DB600000EB850000EB850086B217B111E00127BC
+:10DB7000D8E7A6EB85000C3887B27D48A900046081
+:10DB8000257204F10C0060600DF0EDF93846FFF7E6
+:10DB9000ADFFA9F800600020BDE8F09F2DE9FF4F20
+:10DBA000734C814681B020689A468B4600B9FFDFEE
+:10DBB0002068027A4A4503D9426852F8291021B1F7
+:10DBC00043F2020005B0BDE8F08F006800B9FFDF46
+:10DBD00001210E9A0398FFF70FFAC61C4FF6FC7549
+:10DBE0002E40584601215246FFF706FAC01C00EAB3
+:10DBF000050808EB0600001D85B25D480027006897
+:10DC0000046801E027460446206838B1A188A9428B
+:10DC1000F8D13946204600F0A4F813E005F10800D9
+:10DC2000A18880B2814229D33946204600F099F874
+:10DC3000A0880022411B601902608180394600F0F3
+:10DC400088F8A580A08860802680251D0E9F01236E
+:10DC5000039A314628460097FFF7D6F920884146B7
+:10DC600028445A460123CDF800A0FFF7CDF94048DB
+:10DC700000684168002041F82940A3E70420A1E79B
+:10DC800070B53B4C0546206800B9FFDF2068017A7B
+:10DC9000A94210D9426852F8250060B1418800239A
+:10DCA00042F8253003608180194600F052F821685F
+:10DCB00000200A7A08E043F2020070BD4B6853F876
+:10DCC00020306BB9401CC0B28242F7D8002002E07D
+:10DCD0008A88104480B209680029F9D1FFF706FF4D
+:10DCE000002070BD70B5224D286800280AD000249D
+:10DCF00004E02046FFF7C4FF641CE4B22868007A01
+:10DD0000A042F6D870BD70B5194E054600243068A3
+:10DD100000B9FFDF3068017AA94204D9406850F8A1
+:10DD2000250000B1041D204670BD70B5104E05469B
+:10DD30000024306800B9FFDF3068017AA94206D9B3
+:10DD4000406850F8251011B131F8040B44182046F2
+:10DD500070BD19B10A68026008607047044909681B
+:10DD6000F8E7006809B10860704701490968FAE7F7
+:10DD70005C00002070B5044600780E4601281AD0D9
+:10DD8000072802D00C281AD115E0A068216905786F
+:10DD90000B2D0CD0052003F0CCFD052D0FD07823E2
+:10DDA00000220520D4F8101003F026FD07E07823A8
+:10DDB00000220620F8E70520216903F0BAFD31466C
+:10DDC0002046BDE8704001F0BDB910B500F1390240
+:10DDD000C3799478411D64F003042340C371DB07C9
+:10DDE0000DD04B79547923404B710B791279134044
+:10DDF0000B718278C9788A4200D9817010BD0022E7
+:10DE00004A710A71F5E74178012900D00C210170AF
+:10DE100070472DE9F74F86B000208C698DF800001F
+:10DE20000878012617460D464FF0070B4FF01109F1
+:10DE30004FF00A0A2A2878D2DFE810F02A001A03E5
+:10DE400058036D03A703B603D203FF03160440046F
+:10DE500068048704A004DD04EE04110519053905E2
+:10DE60005E058905AC05D705F505FF0521063206D7
+:10DE7000440676069806EA0621072F075A077A070E
+:10DE80008E079F07D80710083C08F807FC07020810
+:10DE900014B120781D2829D0D5F808805FEA080041
+:10DEA00043D001208DF80000686A049003208DF8AB
+:10DEB00004008DF805A0286A0290A8880028EFD0F9
+:10DEC00098F8001091B10F2910D27DD2DFE801F04F
+:10DED0007C144BDCFEFDFCFBFAF9F8089EF7F6001B
+:10DEE000022822D124B120780C2801D0002676E324
+:10DEF00002208DF80000B7E10620696A03F019FDE1
+:10DF0000A8880728EDD1204601F017F9022809D08A
+:10DF1000204601F012F9032808D9204601F00DF936
+:10DF2000072803D20120207005E016E2002CB7D0AC
+:10DF300020780128D5D198F80400C11F0A2902D3FE
+:10DF400085F81CA093E2A070D8F80010A163B8F87F
+:10DF50000410A18798F8060084F83E00012028707C
+:10DF60000320207046E00728BBD1002C98D02078F1
+:10DF70000D28B6D198F8031094F83B20C1F3C000E7
+:10DF8000C2F3C002104201D00E2000E00F2089072A
+:10DF900007D198F805100142D2D198F80610014235
+:10DFA000CED194F83D2098F8051020EA02021142E3
+:10DFB000C6D194F83E2098F8061090430142BFD194
+:10DFC00098F80400C11F00E04FE20A29B8D2617F2F
+:10DFD000814201D90620C9E3D8F800106160B8F881
+:10DFE0000410218198F80600A072012028700E20EC
+:10DFF000207003208DF80000686A049004F1390055
+:10E000000190601D029017300390E1E0B5F806B072
+:10E0100041288FD1204601F090F8042802D1E07801
+:10E02000C00704D1204601F088F80F289CD1CBF11D
+:10E030004002164608F10101606A0CF0FBFE606ABE
+:10E040005A463044E9680CF0F5FE0E208DF80000C9
+:10E05000686A0490606A019000216846FFF78AFEB2
+:10E060002078042808D0A07F48B1012807D00328D1
+:10E0700008D010202070A2E00520207015E284F85E
+:10E08000009033E71220F5E71128C2D1204601F0B5
+:10E0900054F8042802D1E078C00719D0204601F0D6
+:10E0A0004CF8062805D1E078C00711D1A07F0228DE
+:10E0B0000ED0204601F041F8112808E0B9E089E0CF
+:10E0C000A1E178E158E110E1EFE0D5E01DE0A0D159
+:10E0D000102208F1010104F148000CF0ABFE607859
+:10E0E000012809D012202070E078C0076BD0A07FF3
+:10E0F000A0B3012863D066E0607FA17888423FF634
+:10E1000069AF00BF84F800B059E011288ED12046D5
+:10E1100001F013F8082804D0204601F00EF8132867
+:10E1200084D12869D8B16869C8B104F17800102297
+:10E1300008F1010106460CF07DFE2078082812D077
+:10E1400014202070E078C0070FD0A07F022818D0DC
+:10E150006178022912D0032831D034E02FE000206A
+:10E160008DF80000F9E00920EBE70B202870296901
+:10E1700002204870206CC1E9010695E208B101282F
+:10E1800079D10B202870296908204870606A48609E
+:10E19000206AC1E902067BE2206CE2780068C2F3E3
+:10E1A0004402521ED04000F0010040F0800000E028
+:10E1B00000200874E06A48617FE20646FEE304201E
+:10E1C00028700520EBE185F800A08DF800A0B9E3E8
+:10E1D0003946F4E31128C5D1204600F0AEFF0A28E5
+:10E1E00002D1E078C00704D1204600F0A6FF152830
+:10E1F000B8D1102208F1010104F148000CF01AFE18
+:10E2000020780A2810D01620207012202870296942
+:10E2100004F1580081F801A048602030886010386F
+:10E22000C860206C0861AFE30B202070E1E2287029
+:10E23000D4E1022896D1204600F07FFF042804D3C1
+:10E24000204600F07AFF082809D3204600F075FF29
+:10E250000E2887D3204600F070FF12287DD2A07FC1
+:10E260000228B8D18DF80090686A049098F80100EF
+:10E270008DF80400FEE367E20228ACD1204600F0EE
+:10E280005CFF002869D0204600F057FF0128F9D034
+:10E29000204600F052FF0C28F4D005208DF8040031
+:10E2A00098F801008DF805005CE71128FCD1002CDE
+:10E2B000FAD020781728F7D16178E06A022912D0C5
+:10E2C0005FF0000101EB4101182606EBC1011022AD
+:10E2D000405808F101010CF0ADFD0520696A00F01D
+:10E2E0001FFF267002E60121ECE70B28DCD1002C91
+:10E2F000DAD020781828D7D16178E06A02292DD0A9
+:10E300005FF0000101EB4101102202EBC101415815
+:10E31000B8F8010008806078E16A022821D0002066
+:10E3200000EB4002142000EBC2000958404650F8B0
+:10E33000032F0A60406848600520696A00F0F0FE1B
+:10E340006078022810D04FF000002044407A20F07E
+:10E3500001010CD14FF001000BE0D3E14FF00101BE
+:10E36000D0E74FF00100DBE74FF00100EDE74FF0A1
+:10E3700000002044417281E3112895D1002C93D0F4
+:10E380002078192890D16178E06A022911D0002103
+:10E3900001EB41011C2202EBC1011022405808F19F
+:10E3A00001010CF047FD0520696A00F0B9FE1A2052
+:10E3B000E9E00121ECE7082898D1002C98D02078DA
+:10E3C0001A2893D1E16A98F801000870E16AD8F838
+:10E3D000022041F8012FB8F8060088800520696AFC
+:10E3E00000F09EFE6078022807D04FF00000204425
+:10E3F000407A20F002002CD034E04FF00100F6E724
+:10E40000214448723AE31128B7D1002CB7D02078C4
+:10E410001B28B2D16178E06A02291DD05FF00001AB
+:10E4200001EB4101202202EBC1011022405808F10A
+:10E4300001010CF0FFFC0520696A00F071FE6078B4
+:10E4400002280CD04FF000002044407A20F0040055
+:10E4500008D14FF00101D3E74FF00101E0E74FF0A1
+:10E460000100F1E74FF00001CAE785F81CB0F4E3C2
+:10E470003878012886D11C2204F11C0079680CF040
+:10E480001EFDE079C10894F83B0001EAD001E07874
+:10E4900061F30000E070217F09B1297732E1217832
+:10E4A00003290AD0C0073FF4E6AD032028708DF899
+:10E4B00000A0686A04904120A7E302262671E17952
+:10E4C000204621F0E001E171617A21F0F0016172F2
+:10E4D000A17A21F0F001A172FFF777FC2E708DF880
+:10E4E00000A0686A04908DF804B071E638781228AC
+:10E4F000D4D18DF800B0696A049191680291ADF8A9
+:10E5000004B008466168016021898180A17A817127
+:10E5100004202070AEE23878B7F806801228BDD10A
+:10E520008DF800B0686A0490381D01AB07C883E815
+:10E5300007004120ADF8040008460C2100F8011B3B
+:10E54000C8F140063246216A0CF074FC206A42464B
+:10E550008119F8680CF06EFC00216846FFF70AFC90
+:10E56000E07820F03E00801CE0702078052801D083
+:10E570000F2008E0A07F00283FF4C4AD0128FBD0A5
+:10E58000032870D108202070B0E43878032885D1A2
+:10E5900078680168A1664068E066052028708DF8FB
+:10E5A0000000686A049013E638780328A0D17868E0
+:10E5B0000168216740686067206C68B9A07F28B156
+:10E5C000012803D0062028700420E8E785F800B071
+:10E5D000FE482064606401E085F800B00326F0E3A3
+:10E5E0003878022884D13879E0BBA07F02280BD08C
+:10E5F0000328F1D1607801280BD0A07994F83A1063
+:10E6000001280AD0F1480BE0B86800287AD02064CD
+:10E6100011E0A17994F83A00F2E7B8680028F5D043
+:10E620002064E078C00701D0012901D0E74802E06A
+:10E63000F8680028EAD06064CEE78DF800A0696A27
+:10E640000491E1785046C90709D06178022903D1C5
+:10E65000A17F29B1012903D0A17F032900D008207F
+:10E66000287046E101E1BFE0387812288FD1B86800
+:10E67000286209202870E0782969C0070DD0082099
+:10E680004870206A4860606A886004F16800C86069
+:10E69000A07F02287FF48CAD7EE502204870206CBC
+:10E6A000486004F16800886004F13800C860201DEB
+:10E6B0000861206B4861606B88612EE2E1783878F0
+:10E6C000C90701D0072100E00B2188428AD12078B8
+:10E6D000072818D084F800908DF800B0686A04907C
+:10E6E000286A0290ADF80490032100F8011B5168DC
+:10E6F00010220CF09FFB00216846FFF73BFB002037
+:10E700002862BEE44CE208202070E5E73878122841
+:10E71000ACD18DF800B0686A049090680290ADF8B2
+:10E720000490042100F8011B102204F168010CF090
+:10E7300081FB00216846FFF71DFB2078092801D0E6
+:10E74000132020E784F800A016E0E1783878C907A4
+:10E7500001D0072100E00B21884287D1102204F16B
+:10E76000480079680CF03AFB10B104202877B1E337
+:10E77000207809283FF4BFAC0C2058E5E078C107A9
+:10E7800037D0A17F012902D002291BD02EE00D2015
+:10E79000287029690B2048706078012809D0206A08
+:10E7A0004860606A886004F16800C86010300861E1
+:10E7B00000E5606A4860206A886004F17800C860FB
+:10E7C0001038F4E7C0F3440114290FD24FF0006170
+:10E7D00001EBB0104FEAB060E0706078012803D020
+:10E7E00010202070042061E10620CCE6607801282A
+:10E7F00087D00E201BE538780A2889D185F800A03B
+:10E8000010208DF80000686A049050680190002183
+:10E810006846FFF7AFFAE9E7E078C0070AD0A07FC3
+:10E82000012803D10F202870042041E11020287016
+:10E830000F203DE115202870296903204870206CC5
+:10E8400048606078012805D004F1780088601038AD
+:10E85000C86062E104F1680088601030F8E7387839
+:10E860000228CAD138790028E0D0287730E33878F8
+:10E870001428FBD185F80090296909204870786830
+:10E880004860607801280DD004F16800886010307D
+:10E89000C860206B0861606B486104F158008861B2
+:10E8A000A06A22E004F1780088601038F0E7387838
+:10E8B0000828DBD16078012801D0132043E2A17839
+:10E8C000A06A0844C1F110010CF02BFB1220287043
+:10E8D000296904F1580081F801A04860203088605F
+:10E8E0001038C860206C086147E0C861E06A0862BF
+:10E8F00013E18DF80490DFE038780928B6D11022B2
+:10E9000004F1480079680CF069FA08B10B202DE792
+:10E9100020780B2812D02046FFF757FAA178A06A7A
+:10E920000844C1F110010CF0FCFA162028700820F0
+:10E930008DF80000686A049000206FE013202870B2
+:10E940008DF800A0686A04908DF8049040E438784F
+:10E9500012288BD1B868286214202870296904F124
+:10E96000580081F801A04860103088601030C860FD
+:10E97000606C08616078012806D004F139004861B4
+:10E98000206B8861606BB0E7601D4861606B8861D7
+:10E99000206BAAE7387809288BD18DF800B0686A17
+:10E9A0000490286A0290ADF804900D2100F8011B34
+:10E9B000102279680CF03EFA002101E077E27CE059
+:10E9C0006846FFF7D7F90020286201E06AB5010028
+:10E9D0006178012901D01520D5E51621297008217B
+:10E9E0008DF80010696A049118E038780C2885D1F8
+:10E9F000162028706078022802D12046FFF7E5F93A
+:10EA0000A07879680A18C0F1100110460CF089FA54
+:10EA100008208DF80000686A049078680190A0785A
+:10EA20008DF8080061E53878102892D1E079C007A8
+:10EA300079D01720287009203AE03878112888D139
+:10EA40001422391D04F11C000CF039FAE16A208D02
+:10EA5000A1F80900E16AA078C871E179E26A01F0E1
+:10EA600003011172E16A627A0A73E16AA07A81F89D
+:10EA7000240000E045E26078012876D0B4E16078B7
+:10EA8000022801D0012000E000202044407AC00785
+:10EA900004D0E078C00701D1192054E11E206CE6B3
+:10EAA000387812287CD1B86828621A20287005208E
+:10EAB0008DF80000686A049011466846FFF75AF91D
+:10EAC000FFF77BBB387803286AD16078E16A0228B7
+:10EAD00001D0012000E0002000EB4002142000EBF8
+:10EAE000C20289587A6813680B6052684A601B2119
+:10EAF0002970D5E9041206234B70636A4B6066786F
+:10EB0000E36A022E01D0012600E0002606EB46064D
+:10EB100000EBC6001858C1E90202686A486206980C
+:10EB200000F027FBCCE788E138780F2838D16078EF
+:10EB3000E26A022801D0012000E0002000EB400042
+:10EB4000102101EBC00002231058093279680AF045
+:10EB50006DFC1C202870296905204870206A4860D7
+:10EB6000E06A09308860FA4872E65BE138780E287E
+:10EB700016D16178E06A022901D0012100E000216C
+:10EB800001EB4101182606EBC101A27840587968D3
+:10EB90000CF050F96178E06A022902D0012101E00D
+:10EBA000B8E0002101EB410106EBC1014158A0781A
+:10EBB0000A18C0F1100110460CF0B3F98DF800B03E
+:10EBC000686A0490286A0290ADF8049006210170EA
+:10EBD0006278E16A022A01D0012200E0002202EB01
+:10EBE000420206EBC202401C895810220CF022F9A6
+:10EBF00000216846FFF7BEF8002028621D2028701B
+:10EC00008DF800A0686A04900B208DF804006CE475
+:10EC1000387812287ED18DF800B0686A0490906828
+:10EC200002900B20ADF80400029880F800B06278E2
+:10EC3000E16A022A01D0012200E0002202EB420236
+:10EC4000102303EBC20289580988A0F801106178EB
+:10EC5000E26A022902D0012101E03BE1002101EB3F
+:10EC60004103142101EBC30151580A6840F8032FF6
+:10EC70004968416000216846FFF77CF80EE760783C
+:10EC8000022801D0012000E000202044407A8007C3
+:10EC900001D51F2057E021206FE53878122839D19F
+:10ECA0008DF800B0686A0490B8680290ADF80490DE
+:10ECB000082606706278E16A022A01D0012200E08B
+:10ECC000002202EB42021C2303EBC202401C8958C3
+:10ECD00010220CF0AFF800216846FFF74BF8202017
+:10ECE00028708DF800A0686A04908DF804605AE4DA
+:10ECF000387812280ED18DF800B0686A04909068B8
+:10ED000002900820ADF80400029809210170E16921
+:10ED1000097800E093E04170E16951F8012FC0F8F3
+:10ED200002208988C18000216846FFF723F8B2E7F6
+:10ED30006078022801D0012100E000212144497AB5
+:10ED4000490706D5222028708DF800A0686A049033
+:10ED5000CFE5012848D067E0387812286FD1B8682D
+:10ED6000286223202870296905204870206A48609D
+:10ED7000E06A0930886077486AE538780E285ED105
+:10ED80006178E06A022901D0012100E0002101EB55
+:10ED90004101202606EBC1014058516810220CF0B9
+:10EDA00049F88DF800B0686A0490286A0290ADF8BE
+:10EDB000049080F800A06278E16A022A02D0012261
+:10EDC00001E0A4E0002202EB420206EBC202401C7A
+:10EDD000895810220CF02EF800216846FEF7CAFF71
+:10EDE000002028626078B4E72420C6E46078022816
+:10EDF0000BD000202044407AC10702D0E178C90737
+:10EE000005D0810705D519209BE40120F2E71720E2
+:10EE100097E4400701D51B2093E41C202070607804
+:10EE2000012801D01820A8E42720A6E42820287073
+:10EE30000B203DE6387813284AD129209DE40CE0C8
+:10EE40002078012844D00C2842D02046FEF7DBFF72
+:10EE50000C208DF80000686A049039E038784FF093
+:10EE60002608122805D013201070032685F800808C
+:10EE70004DE08DF800B0686A0490B86802900220F6
+:10EE8000ADF80400029805210170297F417000212E
+:10EE90006846FEF76FFF0B208DF80000686A04904B
+:10EEA00039466846FEF766FF064685F80080012E63
+:10EEB0000ED02CE001208DF80000686A0490042038
+:10EEC0008DF80400287F8DF805000020287712E0D7
+:10EED000287F80B11D202070252028708DF800A08B
+:10EEE000686A049002208DF8040039466846FEF7EF
+:10EEF00041FF06460BE00CB1FE2020709DF800009B
+:10EF000028B100216846FEF735FFFEF7EFBF09B0D4
+:10EF10003046BDE8F08F2DE9F04F0C4601274E69D1
+:10EF2000097885B09046BA464FF00209072021B112
+:10EF300001294FD0022920D1C9E0217901290BD024
+:10EF4000022916D0032911D0042916D11CE0000093
+:10EF500062B501009CB40100707801280CD1062034
+:10EF6000616A02F0BFFC002807D11AE01D20307052
+:10EF700017E07178022901D0052796E031780C2935
+:10EF800027D18DF804000EE03078011F042902D348
+:10EF90000E3803281DD2B07F02281AD120890228FA
+:10EFA00017D38DF8049084F800A020899DF80410F0
+:10EFB000884203D20A208DF800003FE01221083475
+:10EFC00088F8001094E80E00C8E901120327C8F879
+:10EFD0000C306AE098F80010122966D18DF8000014
+:10EFE000616A0491D8F80850029521794FF00B0B13
+:10EFF000012906D0022929D0032911D0042954D18E
+:10F000005AE0ADF8049085F800B0207E4F4600F03D
+:10F010001F00687000216846FEF7ACFE377043E0C1
+:10F02000ADF8049005202870207E68704E460021BF
+:10F030006846FEF79FFE26708DF800B0606A049067
+:10F0400041466846FEF796FE07462EE0ADF80400FE
+:10F0500085F800A0207F6870607F00F00100A87034
+:10F06000A07F00F01F00E870E17F2971C0071FD06A
+:10F0700094F8200000F00F00687194F8210000F06F
+:10F080000F00A87100216846FEF774FE2868B0637F
+:10F09000A888B087A87986F83E00A0694078707784
+:10F0A0002879B0700D2030700027384605B030E761
+:10F0B0000020A8716871E5E7ADF804900E20287073
+:10F0C000207E687000216846FEF754FEECE7FE20C3
+:10F0D00030708DF800A0606A049004208DF8040060
+:10F0E000207E8DF80500EDE700B50023012285B0F4
+:10F0F00005280FD006280BD102208DF8002004919E
+:10F100008DF804008DF8053000216846FEF732FEC8
+:10F1100005B000BD8DF8002004918DF80420F1E7C2
+:10F1200070B50C46054602F004FC21462846BDE8B1
+:10F1300070407823002202F05FBB08B1007870476E
+:10F140000C20704770B50C0005784FF000010CD012
+:10F1500021702146F4F70EF973482178405D88420A
+:10F1600001D1032070BD022070BDF4F703F9002027
+:10F1700070BD027B032A05D000220A704B780C2B4D
+:10F1800002D003E0042070470A770A62027B9300F2
+:10F19000521C0273C15003207047F0B585B00F4672
+:10F1A00005460124287B05EB800050F8046C70783C
+:10F1B000411E0D290AD25C493A46123101EB80000A
+:10F1C000314650F8043C2846984704460CB1012CBF
+:10F1D00011D1287B401E10F0FF00287301D00324BA
+:10F1E000E0E70D208DF80000706A04900021019680
+:10F1F0006846FFF7A7FF032CD4D005B02046F0BD2A
+:10F2000070B515460A46044629461046FFF7C5FF65
+:10F21000064674B12078FE280BD1207E30B1002044
+:10F220002870294604F10C00FFF7B7FF2046FEF7CF
+:10F23000EAFD304670BD704770B50D460446882122
+:10F240000BF091FE012D03D0022D03D0052070BDDF
+:10F25000012000E0022060702046FEF7D4FD00206F
+:10F2600070BD28B1027E1AB10A4600F10C01C7E751
+:10F270000120704730B5044687B00D46062002F0E5
+:10F2800058FB2946052002F054FB2078FE2806D0C2
+:10F2900000208DF8000069462046FFF7E2FF07B026
+:10F2A00030BD7FB50E4600218DF80C1041780C2939
+:10F2B00003D00D2903D0002405E0846900E04469EF
+:10F2C0000CB1217E91B16D4601462846FFF751FFF2
+:10F2D000032809D1324629462046FFF791FF9DF8C1
+:10F2E0000C10002900D0042004B070BD04F10C05FE
+:10F2F000EAE710B590B00C4607900B480521801E38
+:10F3000008900A488DF8191009900F92694606A8CE
+:10F31000FFF7C7FF002805D11022204601990BF006
+:10F3200089FD002010B010BDA2B4010062B501003B
+:10F3300070B50D46040011D085B1210128460BF0AF
+:10F34000F0FD10224E4928460BF074FD4C48012177
+:10F350000838018044804560002070BD012070BDE8
+:10F3600070B5474E00240546083E10E07068AA7B41
+:10F3700000EB0410817B914208D1C17BEA7B914272
+:10F3800004D10C2229460BF029FD30B1641C3088D1
+:10F390008442EBDB4FF0FF3070BD204670BD70B58E
+:10F3A0000D46060006D02DB1FFF7DAFF002803DB7B
+:10F3B000401C14E0102070BD314C083C208862884D
+:10F3C000411C914201D9042070BD6168102201EBFB
+:10F3D000001031460BF02EFD2088401C2080287044
+:10F3E000002070BD70B514460D0018D0BCB10021CE
+:10F3F000A170022802D0102811D105E0288870B130
+:10F400000121A170108008E02846FFF7A9FF00281D
+:10F4100005DB401CA070A8892080002070BD012061
+:10F4200070BD70B5054614460E000BD0002030703C
+:10F43000A878012808D005D91149A1F108010A8846
+:10F4400090420AD9012070BD24B128782070288804
+:10F45000000A5070022008700FE064B14968102261
+:10F4600001EB0011204610390BF0E4FC28782073E2
+:10F470002888000A607310203070002070BD0000E2
+:10F48000680000202DE9F041FE4C207EE17D88429D
+:10F4900008BFBDE8F0810126FB4D0027E07D215C1F
+:10F4A00001EB810205EB8200037C052B10D0037C6D
+:10F4B000062B1BD0037C072B27D0437C012B18BFC6
+:10F4C000FFDF30D0207EE17D8842E7D1BDE8F081CA
+:10F4D0000674E07D16281ABFE07D401C0020E07510
+:10F4E000481CC0B255F8222002210CE00674E07DD1
+:10F4F00016281ABFE07D401C0020E075481C55F816
+:10F500002220C0B203219047DCE70674E07D162874
+:10F510001ABFE07D401C0020E075481CC0B255F8C1
+:10F5200022200821EFE74774E07D16280EBF002057
+:10F53000E07D401CE075481CC0B255F82220072130
+:10F54000E1E770B5D14E00240C2086F82900A6F51D
+:10F550003B70254680F8CD4180F8CC4100F5F47031
+:10F560000476C47506F12C000AF0B2FDA6F58E7083
+:10F57000057586F82B50601EB06086F8255086F819
+:10F58000225086F8235086F8245086F82150C0482F
+:10F5900005704570A6F1E80004EB840100EB8101E1
+:10F5A0000D74611CCCB20B2CF6D30120F9F726FBAD
+:10F5B0000020F9F723FB012086F82600F9F7D2FF97
+:10F5C000B448F9F7DEFFB44C2070B448F9F7D9FF1E
+:10F5D0006070BDE87040F9F7A5BA10B5F9F7D0FA38
+:10F5E000AD4C2078F9F7E6FF6078F9F7E3FFA74C18
+:10F5F00094F82800002808BF10BDF9F7CAFC0020C5
+:10F6000084F8280010BD0B20704770B5F9F79BFBFC
+:10F610009E4C054694F8260000281CBFFFDF70BDF5
+:10F6200094F82B00002808BFFFDF6FF07F4260696D
+:10F630000026291AB1F5800F24BF431BB3F5800FB4
+:10F640000DD38A4203D2101A2844411C07E09A4283
+:10F6500028BFFFDF05D2511B0844401C414200294E
+:10F6600000DBFFDF012584F8265084F82B6094F836
+:10F6700029100420844A01EB810102EB8101087406
+:10F68000A068B0F1FF3F04D0A81EA0600120F9F7E8
+:10F69000B5FA0020F9F7B2FAF9F796FA0AF0A6FEE1
+:10F6A000F9F7DAFB7E48066006604FF0E0214FF480
+:10F6B0000040C1F88002F3F780FC7548007802280A
+:10F6C00004D0032805D194F8230010B184F8225007
+:10F6D00001E084F82260BDE87040F9F7A1BB034661
+:10F6E00069490B2000EB800201EB820212F8042C26
+:10F6F00022B1401E10F0FF00F4D1704700EB8002F1
+:10F7000001EB8201012241F8143C01F8042C7047FE
+:10F71000012804D0032808BF002926D000E021B327
+:10F720005A4B4FF0000C83F821C0594A00289070C2
+:10F7300014BF022882F803C00BD0072915D2DFE8D6
+:10F7400001F01404060C0E1012001B2000E03A20F9
+:10F75000D070012083F8210070475820F8E7772007
+:10F76000F6E79620F4E7B520F2E700207047484816
+:10F7700010B54078F9F779FB80B210BD421E10B584
+:10F78000414900EB800001EB80040A2A02D814F8FA
+:10F79000040C00B9FFDF14F8040C012818BFFFDFC8
+:10F7A000002004F8040C10BD70B53E4C94F8CD0157
+:10F7B00094F8CC1188420CBF01250025F9F7C3FA53
+:10F7C000F9F753FB94F8CD1194F8CC2191420CBF7A
+:10F7D00001210021A942E9D170BD2DE9F05F8046E9
+:10F7E0004B1E1746DCB2284804EB840200EB82056E
+:10F7F0002E1D287CDFF88C9007282DD199F8170052
+:10F80000002299F818C0844524D000BF19F800C020
+:10F81000A44508BF012200D04AB116280CBF4FF002
+:10F82000000C00F1010C19F80CC009F800C01628F2
+:10F830000CBF0020401CC0B299F818C08445E5D127
+:10F8400042B199F818204846002A0EBF1622027EBF
+:10F85000521E0276012028740A2B10D80A4801EBA8
+:10F86000810100EB810010F8040C40B1287C0128D4
+:10F8700006D0287C012802D0B87A012816D0FFDFF4
+:10F88000B87A11E0BC0B0020D80B0020C00C00207F
+:10F890007A000020A51601007800002085F4000001
+:10F8A00000F50040D409002001284AD1FE49287CF7
+:10F8B000022816D099F8180016284AD099F818008E
+:10F8C00099F81710401C884200D1FFDF01206874AE
+:10F8D00099F8180009F8004099F8180016283DD04A
+:10F8E0003EE0DFF8C8C39CF829000246A04207D0DA
+:10F8F000024600EB820001EB8000807CA042F7D141
+:10F900009CF8293083420CD19CF8292002EB82021A
+:10F9100001EB8202927C8CF8292001228CF82A20AB
+:10F9200009E000EB800301EB830302EB820201EBB1
+:10F9300082029B7C937400EB800001EB80000C2220
+:10F940008274387A062825D2DFE800F012211E1BC7
+:10F95000181599F817000028B8D1B6E7002002E082
+:10F9600099F81800401C89F818000020BDE8F09FA5
+:10F970004FF0000A11E04FF0B40A0EE04FF0730AA6
+:10F980000BE04FF0320A08E04FF00A0A05E04FF0B2
+:10F99000060A02E0FFDF4FF0000A3868A0EB0A0019
+:10F9A0003060397A00290CBF04210221401A20F06E
+:10F9B0007F423260D7E90001084420F07F40706048
+:10F9C000B87A022818BF387B7ED1387A00280CBF5D
+:10F9D0000420022000EB0A037868591D00EB010B9C
+:10F9E000B3484078504503D9B04991F8231011B17C
+:10F9F0000BF1060003E0A0EB0A005844801DAB4960
+:10FA000091F829C0BCF10C0F24D08E4691F8291032
+:10FA100001EB810CA44901EB8C0CDCF804C06245BD
+:10FA200018D0DFF890C29EF8292002EB820201EB89
+:10FA300082014A688968A2EB080222F07F42A1EBAA
+:10FA4000080121F07F41904298BFB2F5800F49D262
+:10FA50008C4547D34044A0EB0B0020F07F41316040
+:10FA60001944F86821F07F410A1A6FF07F43B2F51C
+:10FA7000800F24BFA0EB010CBCF5800F0DD3934287
+:10FA800003D2181A0844421C07E0634528BFFFDF71
+:10FA90001FD2591A0844401C4242002A19DD052091
+:10FAA000287499F8180016282DD099F8180099F89C
+:10FAB0001710401C884200D1FFDF99F8180009F8A0
+:10FAC000004099F8180000E00BE016287FF448AFDA
+:10FAD00044E73068ABF10501084420F07F407060D6
+:10FAE000002030727068401D20F07F407060787A8E
+:10FAF000B072387A0627707203280DD260B101F017
+:10FB000023FB28B108E099F817000028D5D1D3E7E6
+:10FB1000CAF138074FF0320A65480178012918BF49
+:10FB200003290AD14078504507D9604991F823103C
+:10FB3000002904BFA0EB0A0007445E4B3068A0EB2D
+:10FB40000802706822F07F41A0EB080020F07F4C93
+:10FB50008F4298BFB1F5800F1CD263451AD3534929
+:10FB600091F829300C2B32D091F829704FF00C0B02
+:10FB70004FEA0B0A4C4907EB870301EB8303D3F8E9
+:10FB800008C0ACEB080C944531D8BB469F7C0C2FC9
+:10FB9000F0D199E00520287499F81800162811D0A2
+:10FBA00099F8180099F81710401C884200D1FFDF1F
+:10FBB00099F8180009F8004099F8180016287FF401
+:10FBC000CFAECBE699F817000028F1D1EFE702207D
+:10FBD000287491F829000C2818BF91F82900A874FE
+:10FBE00081F82940012081F82A00BDE8F09F0C2F00
+:10FBF0001CBFBA46002267D00AEB8A0301EB8303DD
+:10FC0000D3F804C0ACEB080C844528D29A7B96F854
+:10FC10000AC094451CD30520287499F818001628AA
+:10FC200011D099F8180099F81710401C884200D19B
+:10FC3000FFDF99F8180009F8004099F81800162815
+:10FC40007FF48EAE8AE699F817000028F1D1EFE72D
+:10FC500093F812A00122BAF10C0FCDD103E0002AD3
+:10FC600008BFBA4630D03E460F4806EB860200EB8E
+:10FC70008208062188F8101099F81800162836D046
+:10FC800099F8180099F81710401C884200D1FFDF3E
+:10FC900099F8180009F8006099F8180016280CBFA8
+:10FCA000002099F8180007E0D80B0020C00C0020B5
+:10FCB0007A000020FFFF3F0018BF401C89F81800A1
+:10FCC00098F81260B245CFD10220FE4E287406F19A
+:10FCD000E80090F82910B9420ED185F812A080F8FA
+:10FCE0002940012180F82A100120BDE8F09F99F8F1
+:10FCF00017000028CCD1CAE70C2F0BD0BBF10C0F9A
+:10FD000008BFFFDF0BEB8B0006EB8000847485F8E7
+:10FD100012A0E9E7BBF10C0F08BFFFDF0BEB8B0074
+:10FD200006EB800084740C20A874DDE730B50D4626
+:10FD3000E54A44190021101A71EB010038BFFFDFBA
+:10FD4000E2488542C8BFFFDFE1488542B8BFFFDF18
+:10FD5000E0488442A8BFE04804DA002CAABF20464D
+:10FD6000DC4830BD201830BD401E70B5C0B200EB7D
+:10FD70008001D44800EB8104607B062810D2DFE8C4
+:10FD800000F0030D0B090705002033E0B4200BE061
+:10FD9000732009E0322007E00A2005E0062003E096
+:10FDA000FFDF617B002029B3022108446168084419
+:10FDB00020F07F40F9F759F894F90C50C24A4419E1
+:10FDC0000021101A71EB010038BFFFDFBF488542E8
+:10FDD000C8BFFFDFBE488542B8BFFFDFBD488442D1
+:10FDE000A8BFBD4804DA002CAABF2046B94870BDA0
+:10FDF000201870BD0421D8E72DE9F04F0646B7481A
+:10FE000085B00068C005C00D11D0103840B2002880
+:10FE1000B8BF00F00F0000F1E020B4BF90F8140D5F
+:10FE200090F80004400908BF4FF0010A01D04FF0DC
+:10FE3000000A3078002817BF01283079002005B06B
+:10FE400018BFBDE8F08F062810D2DFE800F0030DE0
+:10FE50000B090705002015E0B4200BE0732009E032
+:10FE6000322007E00A2005E0062003E0FFDF3179B9
+:10FE7000002039B15FF0020100EB0109BAF1000F77
+:10FE800006D101E00421F7E79549002081F8270019
+:10FE90006C4602AA2146B068F8F7F4FF9DF90820E5
+:10FEA000F068211D10440122C01C1F28B8BF019218
+:10FEB00008DB03AAF8F7E6FF9DF80C0010B10198E3
+:10FEC000401C0190DDE900100844401D20F07F40F7
+:10FED0000190A1EB090020F07F40009070798DF82F
+:10FEE0000A0000980390F8F72EFF0099019B091A69
+:10FEF000181A7C4A21F07F4120F07F40B1F5800F35
+:10FF000010D282420ED3764890F82950009CAB461E
+:10FF1000191B21F07F486FF07F41091BA0F1E80712
+:10FF2000049101E0002080E00C2D26D005EB850037
+:10FF300007EB80026FF07F435068011BB1F5800F23
+:10FF400010D3A4EB000CBCF5800F0BD38B4203D273
+:10FF500004990844411C05E063450DD2181A204459
+:10FF6000401C4142002908DA5D48AB46957C90F878
+:10FF700027000028D8D04CE0FFDF5D4525D00BEBF3
+:10FF80008B0007EB80036FF07F429968081BB0F588
+:10FF9000800F12D3A4EB010CBCF5800F0DD382426D
+:10FFA00003D204980844401C07E0624528BFFFDFE5
+:10FFB0000BD2521A1019401C4042002805DD9DF852
+:10FFC0000A009A7B904228BF0C460C2D1CBF9DF85E
+:10FFD0000A10434A14D000BF05EB850007EB8000F0
+:10FFE00043681B1B23F07F43434509D2837B99421F
+:10FFF00028BF8468857C92F8270050B90C2DEBD17E
+:020000040001F9
+:100000000098A04205D004EB080020F07F40009447
+:10001000019000990398814206D001EB090020F07D
+:100020007F40F8F722FFB06001202D4991F827109A
+:10003000002904BF05B0BDE8F08FBAF1000F3FF40E
+:1000400023AF05B0BDE8F08F2DE9F04F814687B0B2
+:100050000C4625480AF044F8244901274FF00008CF
+:1000600001EB090500287DD0A1F5887898F81400E7
+:10007000002818BFFFDF2078012800F0238200BF8E
+:1000800088F810902078022808BFFFDF184E2079EA
+:1000900006F10C023072607970723146A068F8F790
+:1000A000F1FE96F90C000F2804DD1F38307330681C
+:1000B000401C306096F90C00E168351D0844C01CF6
+:1000C0001F2817E0D80B0020FF7F841E0020A10707
+:1000D00000E05EF80080841E00807BE104ED00E01B
+:1000E000C00C0020FFFF3F00EC0C0020B40C0020EF
+:1000F000A40B0020B8BF2F6009DB6A462946F8F739
+:10010000C1FE9DF8000010B12868401C28602078CE
+:10011000B07288F81470F64D95F8CD0195F8CC11B1
+:10012000884204BF07B0BDE8F08FF24890F829403C
+:100130000C2C00F0CF81F8F706FEEF4904EB8402A7
+:1001400001EB82010A7C042A19BF0A7C032A07B04A
+:10015000BDE8F08FE94B4A688968121A22F07F42A5
+:10016000081A00E01BE020F07F40062A3CBF07B0E1
+:10017000BDE8F08FB2F5800F24BF07B0BDE8F08F67
+:1001800083423CBF07B0BDE8F08F95F8CD0195F8EC
+:10019000CC11884240F0A78107B0BDE8F08FD44E63
+:1001A00096F8CD01162855D096F8CD0196F8CC11C9
+:1001B000401C884200D1FFDF207801284FD0CC4876
+:1001C00090F8CD1101EB810100EB810080F81090D7
+:1001D000207802284BD0C64890F8CD1101EB810160
+:1001E00000EB8105207928726079687205F10C02B4
+:1001F0002946A068F8F746FE95F90C000F2804DDA3
+:100200001F3828732868401C286095F90C00E168A5
+:100210002E1D0844C01C1F28B8BF376009DB6A4682
+:100220003146F8F72FFE9DF8000010B13068401CF1
+:1002300030602078A872AE4991F8CD0116280EBF23
+:10024000002091F8CD01401C81F8CD01AC4809F0A7
+:100250005DFF60E796F8CC010028ADD1ABE715F85B
+:10026000010C002818BFFFDF05F8017CA7E7A548AF
+:100270000068C005C00D0FD0103840B20028B8BFCC
+:1002800000F00F0000F1E020ACBF90F8000490F8FF
+:10029000140D400908BFFFDF954890F8CD1101AA61
+:1002A00001EB810100EB8106E068CDF800808DF85C
+:1002B00004806946F8F7E6FD9DF904000F28CCBFDD
+:1002C000012000200099351D084401900220B072E1
+:1002D0002079307260797072A068C01C1F28B8BF86
+:1002E0002F6009DB6A462946F8F7CCFD9DF800002F
+:1002F00010B12868401C2860307A062810D2DFE848
+:1003000000F0030D0B09070500200BE0B42009E005
+:10031000732007E0322005E00A2003E0062001E018
+:10032000FFDF0020217900290CBF042102210844AD
+:1003300002907168401D08440199009001440298A0
+:10034000081A05906B4C002084F82700F8F7FBFC96
+:10035000804630600198404420F07F40F06094F87F
+:1003600029000C287ED0204690F8291001EB81024C
+:10037000A0F1E80101EB82025468009A274622446A
+:1003800022F07F42039296F809B090F82950121B90
+:1003900022F07F4A6FF07F42121BA94604920C2D77
+:1003A00027D0554805EB850100EB81036FF07F42B4
+:1003B0005868011BB1F5800F24BFA4EB000CBCF5FD
+:1003C000800F0BD38A4203D204990844411C05E0F4
+:1003D00062450DD2111A0819401C4142002908DA61
+:1003E0004448A9469D7C90F827000028D7D04DE0CE
+:1003F000FFDF4D4525D0404809EB890100EB810125
+:100400006FF07F438868021B8146B2F5800F24BFDE
+:10041000A4EB000CBCF5800F0DD3934203D2049AD9
+:100420001044421C07E0634528BFFFDF09D21A1AB7
+:100430001019401C4242002A03DD887B834528BFF7
+:100440004C460C2D1CBF2B4BA3F1E80116D000BF6E
+:1004500005EB850001EB80025068001B20F07F4017
+:10046000504500E026E009D2907B834528BF946880
+:10047000957C93F8270048B90C2DE9D1A74205D007
+:1004800004EB0A0020F07F4027460390039AA7EB75
+:10049000080121F07F41A2EB0802059822F07F427B
+:1004A000B1F5800F06D2904204D30298384420F070
+:1004B0007F4030600F4890F8270000287FF442AF5B
+:1004C000B9E600BF15F8010C002818BFFFDF05F8DA
+:1004D000017CD5E595F8CD0195F8CC11884204BF93
+:1004E00007B0BDE8F08F07B0BDE8F04FF8F798BC53
+:1004F000D4090020C00C0020D80B0020FFFF3F00D3
+:10050000EC0C002004ED00E00020F8F767BB0120B0
+:10051000F8F764BBFD48007870472DE9F0410546C7
+:1005200002282DD0FA4C94F829000C2808BFFFDFD0
+:10053000002784F82670012684F82B6094F829108F
+:100540000320DFF8D08301EB810108EB81010874FF
+:10055000F8F76DFCD5B1012D39D0032D1CBFFFDF9D
+:10056000BDE8F08194F8290094F82910401CC0B22D
+:1005700001EB810158F82120BDE8F0410521104729
+:10058000E2480078BDE8F041F9F71AB8207F00286A
+:1005900018BFFFDF84F8256000202760F8F72EFBE6
+:1005A000A168B1F1FF3F04D0012300221846F8F7FB
+:1005B00069FB94F8290094F82910401CC0B201EBA3
+:1005C000810158F82120BDE8F041012110470120A8
+:1005D000F8F714FB94F8250000281CBFA068B0F1C0
+:1005E000FF3F0DD094F8290094F82910401CC0B2A8
+:1005F00001EB810158F82120BDE8F04106211047A8
+:10060000207F012815D002281FD0032833D00428CA
+:100610001CBFFFDFBDE8F08194F820106068012363
+:10062000411A00221846F8F72DFB94F82800B8BBB1
+:1006300037E094F8240028B184F82470F8F7FEFB22
+:1006400084F823602777BDE8F08194F8280018B972
+:10065000F8F776FC84F8286094F8290094F82910BB
+:10066000401CC0B201EB810158F8212000219047C5
+:100670002777BDE8F081217B60680123411A0022C1
+:100680001846F8F7FFFA94F8240028B184F824708B
+:10069000F8F7D4FB84F8236002202077BDE8F081CE
+:1006A00003E0F8F74DFC84F8286094F8290094F8EA
+:1006B0002910401CC0B201EB810158F82120002113
+:1006C00090472677BDE8F08110B5914C94F8290049
+:1006D0000C2808BFFFDF94F8290094F82910401C6B
+:1006E000C0B28C4A01EB810152F82120BDE81040D4
+:1006F000042110472DE9F05FF8F725FB844C814673
+:100700004FF00C0B94F829000026A4F1E8084FF0F4
+:10071000010A0C282CD094F82910204601EB810105
+:1007200008EB8101097C042922D090F8291001EB03
+:10073000810108EB8101097C032908BFBDE8F09F16
+:10074000754922696069A2EB090222F07F42A0EBA1
+:10075000090020F07F40062A38BFBDE8F09FB2F5BF
+:10076000800F28BFBDE8F09F814238BFBDE8F09FF1
+:10077000A068B0F1FF3F18BFFFDF84F8256094F850
+:100780002900664F0C2806D194F8210018B1F8789A
+:100790007870B87838705E4890F829000C281ED020
+:1007A0005B4890F8291001EB810108EB8101097C7D
+:1007B000042914D190F829B090F8291001EB810197
+:1007C00008EB810181F810A090F8291001EB81015C
+:1007D00008EB8101897C80F8291080F82AA0504C10
+:1007E00094F8CD0194F8CC1104F2DF2588424ED064
+:1007F00094F8CC0100EB800004EB8000007C405DAD
+:10080000012894F8CC0100EB800004EB800004D0B8
+:10081000007C405D022878D018E0807A01280DD055
+:1008200094F8CC11022001EB810104EB8101097CD9
+:10083000485594F8CC01162820D01BE094F8CC0140
+:1008400000EB800004EB8000007C465594F8CC015E
+:1008500000EB800004EB800294F8CC0100EB8000F8
+:1008600004EB8000017C4846FEF7B7FF94F8CC010A
+:10087000162803D094F8CC01401C00E0002084F836
+:10088000CC0194F8CD0194F8CC118842B0D1254C1C
+:10089000207D70B1207C415D012966D0405D022839
+:1008A0006BD0207D28B1217C1E4A4846FEF795FF7B
+:1008B0002675BBF10C0F06D00BEB8B0008EB80000C
+:1008C000017C012961D0124C94F829000C2800F019
+:1008D000388194F82A00002800F0428184F82A60C8
+:1008E00094F8290000EB800008EB8003A4F53B702E
+:1008F000D3E90112DB68C0F80433C0E9BF12607E9F
+:1009000000280CBF042502250EE01CE07800002022
+:10091000C00C0020D80B0020FFFF3F007A00002011
+:10092000D4090020A40B002094F82900C34600EB52
+:10093000800108EB8100407B06284DD2DFE800F003
+:10094000404A4846444294F8CC0100EB800004EB56
+:100950008000807A012818BFFFDF94F8CC0100EBFB
+:10096000800004EB8000867268E7A17A01291DBF30
+:10097000022141552675465593E7A07A012818BFF4
+:10098000FFDFA672207C46558BE707210174FE4CE1
+:10099000207E162810D0207EE17D401C884200D1A8
+:1009A000FFDF207E04F800B0207E16280EBF002056
+:1009B000207E401C207686E7E07D0028F1D1EFE71D
+:1009C00000200BE0B42009E0732007E0322005E0AE
+:1009D0000A2003E0062001E0FFDF00202073617E93
+:1009E000022918BF012911D121690144A1EB090293
+:1009F00022F07F42382A09D903206076A1F1320023
+:100A000020F07F4020613220207309E0322807D295
+:100A100094F8280058B9F8F793FA84F828A006E06B
+:100A200094F8280018B1F8F7B4FA84F828607978B7
+:100A300084F8201038780622012818BF032806D130
+:100A400084F824A0207B814284BF081A821D94F878
+:100A50002230002B18BF921C94F82400002808BFF5
+:100A6000002B6AD0D4F810806069A8EB0908DFF881
+:100A70001CC328F07F48A0EB090020F07F404245CE
+:100A800098BFB8F5800F41D284453FD3207B884280
+:100A900015D22369A1EB0002A3EB020222F07F42F0
+:100AA0001144294421F07F412261616000280CBF7C
+:100AB00001200320207710F0FF0F36D114E00AD96F
+:100AC000226900291044284420F07F4060600CBF58
+:100AD00002200420EEE7002B08BFFFDF2069284436
+:100AE00020F07F40606026770120F8F787F800BF8C
+:100AF00094F82900012300EB80010BEB8100616871
+:100B000090F90C200020F8F7BDF829E084F8246063
+:100B100084F82260207B0028E0D021690844284422
+:100B200020F07F4060600220207720690123411976
+:100B300000221846F8F7A6F8DAE7207B0028ECD167
+:100B4000CCE70120F8F75AF80020F8F757F8F8F743
+:100B50003BF894F8280018B1F8F71BFA84F82860DD
+:100B600094F8220028B1F8F769F984F8236084F832
+:100B7000226094F8210018B1F8787870B87838704D
+:100B800094F8240030B184F823603878002808BF36
+:100B900084F824607C48017EC07D814203D07C487B
+:100BA0004078F8F70DFD84F827A0BDE8F09F70B5F8
+:100BB000784C054682B094F829000C2808BFFFDF66
+:100BC00094F8290000EB8000734E06EB8000007C57
+:100BD000032818BFFFDFA068B0F1FF3F18BFFFDF99
+:100BE00094F82900002100EB800006EB800001AAA8
+:100BF00090F90C0000918DF8041028446946F8F72C
+:100C000041F99DF904000F28CCBF01200020009974
+:100C100008446168084420F07F41A16094F82500F1
+:100C2000002804BF02B070BD012302B00022BDE85D
+:100C300070401846F8F726B8584A0B1A02F1010C12
+:100C4000B3EB9C0F3CBF1846704710B5441AB4EB89
+:100C50009C0F3CBF184610BD9A4203D2101A08449C
+:100C6000401C10BD94429EBFFFDF002010BD511AF2
+:100C70000844401C404210BD0123002201460220CE
+:100C8000F8F700B80220F7F7B9BFF8F75CB8F0B58D
+:100C9000404C054683B094F82B00002808BFFFDFC6
+:100CA000642D50D33E490020491B80414BD33D4821
+:100CB00090F8CD1190F8CC01814244D13A48007DA2
+:100CC000002840D194F82900334F00EB800007EB57
+:100CD0008006206801AA28446946F8F7D3F89DF9F0
+:100CE0000400002802DD0098401C0090B2680099C2
+:100CF00073685018C01A20F07F40B0F5800F22D2E0
+:100D0000B07C0C2809D000EB800007EB8000406825
+:100D1000801A20F07F40884215D3A068B0F1FF3FD1
+:100D200005D00120F7F76AFF4FF0FF30A060206880
+:100D300028442060B0680099084420F07F4060613A
+:100D400003B00120F0BD03B00020F0BD2DE9F0415B
+:100D50000646401EC5B2104805EB850100EB810434
+:100D6000207C002808BFFFDF0E4A92F8CC1192F8D1
+:100D7000CD01814221D000BF01EB810302EB83034F
+:100D80001B7CB34220D011E0BC0B0020FFFF3F00D2
+:100D900078000020C00C0020D80B0020FF7F841EAC
+:100DA000FF1FA107D4090020A40B002016290CBFA7
+:100DB0000021491CC9B28142DED13A48017D002997
+:100DC00062D0007CB0425FD10020BDE8F081217C80
+:100DD00005291FBF217C0629217C07292CD12774D6
+:100DE000C27D0023017E914218BF014624D000BF7E
+:100DF00011F80280A84508BF012300D04BB1162A84
+:100E00000CBF4FF0000802F1010811F8088001F84A
+:100E10000280162A0CBF0022521CD2B291F8188010
+:100E20009045E5D143B10A7E002A08BF81F818C079
+:100E300002D00A7E521E0A76617C21B36674C27D9E
+:100E40000021037E934224D0835CAB4208BF012182
+:100E500000D029B1162A0CBF0023531CC35C835455
+:100E6000162A0CBF0022521CD2B2037E9342EBD151
+:100E700049B1027E0146002A08BF81F818C008D097
+:100E80000A7E521E0A7604E00127074800264FF02A
+:100E9000160C217C012904BF617C002997D1012017
+:100EA000BDE8F081A40B0020BC0B0020F0B5734A14
+:100EB000D2F80032724D002401212E7856B9714EBD
+:100EC0003460704F03263F1D3E606E4F04260C3782
+:100ED0003E602970C2F80042D1601160694C48340C
+:100EE000D16425688542FBD35160D160C2F80032DD
+:100EF000F0BD2DE9F041044680074FF000054FF0AA
+:100F0000010604D560480560066024F00204E00490
+:100F10004FF0FF3705D55D484660C0F8087324F4EC
+:100F20008054600003D55A48056024F08044E005F1
+:100F30000FD55248C0F80052C0F8087351490D60EF
+:100F4000091D0D604F4A04210C321160066124F422
+:100F50008074A00409D54F484660C0F80052C0F81C
+:100F600008734D48056024F40054C4F38030C4F382
+:100F7000C031884200D0FFDF14F4404F14D04748FE
+:100F80004660C0F8087346488660C0F80052C0F852
+:100F9000087344490D600A1D16608660C0F8087326
+:100FA0000D60166024F4404420050AD53E48466092
+:100FB0008660C0F80873C0F848733C48056024F4A4
+:100FC000006409F0EDF93A48044200D0FFDFBDE8C3
+:100FD000F08170B5202500224FEA020320FA02F1C9
+:100FE000C90719D051B201F01F060124B4404E09BF
+:100FF000B60006F1E026C6F88041C6F88042002916
+:1010000006DA01F00F0101F1E02181F8143D03E05F
+:1010100001F1E02181F80034521CAA42DED370BDF8
+:1010200070B5174C0D466060FFF763FF6068FFF70F
+:10103000D0FF2846F8F761F808F004FE00F0D5F874
+:1010400009F0AEF909F0FBF8F8F78CFABDE870404A
+:1010500008F09ABE10B50A4C6068FFF74AFF606856
+:10106000FFF7B7FF09F09CF9F8F70CF90020606072
+:1010700010BD034840687047022070470080004060
+:101080008000002004850040FC1F004000C000409C
+:1010900004E5014000D0004004D5004000E00040DD
+:1010A00000F0004000F5004000B0004008B50040EE
+:1010B000FEFF0FFC70B51F490A68BAB100231D4638
+:1010C00001244A68521C4A60092A00D34D600E79F7
+:1010D00004FA06F20E6816420AD072B60B68934301
+:1010E0000B6062B649680160002070BD052070BDCC
+:1010F0005B1C092BE5D3FFDFF8E74FF0E0214FF44D
+:101100008000C1F800027047EFF3108111F0010F69
+:1011100072B64FF0010202FA00F20648036842EA92
+:101120000302026000D162B6E7E7024800210160D5
+:1011300041607047880000200120810708607047E7
+:10114000012081074860704712480068C00700D03E
+:10115000012070470F48001F0068C00700D0012021
+:1011600070470C4808300068C00700D00120704765
+:10117000084810300068704706490C310A68D203ED
+:1011800006D5096801F00301814201D101207047B1
+:10119000002070470C040040C84911F8210F49781D
+:1011A000884201D3401A02E0C1F121010844C0B2D3
+:1011B0007047C249233111F8210F4978884201D381
+:1011C000401A02E0C1F121010844C0B27047BB4996
+:1011D000463111F8210F4978884201D3401A02E0C4
+:1011E000C1F121010844C0B27047B54910B5802053
+:1011F00081F80004B1490020233101F8210F487023
+:10120000AE4901F8210F4870AC49463101F8210F71
+:101210004870AC4808F05CFFAA48401C08F058FF32
+:10122000F8F778F8BDE8104000F03DB9202070478D
+:10123000B2E770B50C4605460026FFF7ADFF014644
+:101240009E48A14212D30022641EE4B20DD390F84E
+:101250002210435C491CC9B205F8013B80F82210FA
+:101260002129F1D180F82220EEE7012600F01BF9B8
+:10127000304670BD202070479BE770B50C46054690
+:101280000026FFF796FF01468C482330A14212D377
+:101290000022641EE4B20DD390F82210435C491C76
+:1012A000C9B205F8013B80F822102129F1D180F85C
+:1012B0002220EEE7012600F0F6F8304670BD20212E
+:1012C00001700020704710B50446FFF780FF2070C2
+:1012D000002010BD70B50C460546FFF778FF0146AB
+:1012E00076484630A14213D30022641EE4B20DD3E7
+:1012F00090F82210435C491CC9B205F8013B80F804
+:1013000022102129F1D180F82220EEE7002401E00B
+:1013100042F2070400F0C7F8204670BD70B50C46D5
+:101320000546212900D9FFDF67480068103840B220
+:1013300000F0A0F8C6B20D2000F09CF8C0B28642C2
+:1013400004D2FFDF02E000BFF8F734F82146284658
+:10135000FFF76FFF0028F7D070BD2DE9F047DFF8E9
+:101360006481564CA8F101080746233498F8000020
+:10137000DFF84891002604F1230A38B994F82210C6
+:1013800094F82100212200F084F890B14D4699F89C
+:10139000221099F82100212200F07BF8B8B15546BF
+:1013A0009AF822109AF82100212200F072F848B32E
+:1013B00035E094F82100275494F82100401CC0B275
+:1013C00084F8210021282AD184F8216027E095F8AB
+:1013D00021002F5495F82100401CC0B285F821004F
+:1013E000212801D185F8216098F800004746B0B166
+:1013F00095F8221095F82100212200F04AF870B1EA
+:101400003E700CE095F821002F5495F82100401C07
+:10141000C0B285F82100212801D185F8216094F817
+:10142000221094F82100212200F033F800281FD068
+:1014300099F8221099F82100212200F02AF80028BA
+:1014400016D09AF822109AF82100212200F021F8F3
+:1014500000280DD0F7F784FF1A4808F041FEB0F5D8
+:10146000005F00D0FFDFBDE8F047164808F04EBE31
+:10147000BDE8F087002806DA00F00F0000F1E02058
+:1014800090F8140D03E000F1E02090F8000440090A
+:101490007047401C884204D0904200D109B100201E
+:1014A00070470120704710B5064808F019FE002863
+:1014B00003D1BDE81040F7F73EBF10BDF00C00208F
+:1014C0000DE000E09100002004ED00E013490878F1
+:1014D0004A78401CC0B2904205D0114B01221A60DC
+:1014E000BFF34F8F0870704770B54FF0E0250B4C7D
+:1014F000F7F7E6FF20BF40BF20BF6078217861701A
+:10150000D5F8001229B9D5F8041211B92178814211
+:10151000EED0F7F7D0FF002070BD00009300002050
+:10152000180502402DE9F041012528034FF0E02184
+:101530000026C1F880011E4CC4F800610C2000F0A8
+:101540002CF81C4801680268C94341F3001142F0BD
+:1015500010020260C4F804532560491C00E020BF5B
+:10156000D4F80021002AFAD019B9016821F010013D
+:101570000160114807686560C4F80853C4F8006149
+:101580000C2000F00AF83846BDE8F08110B504469A
+:10159000FFF7C8FF2060002010BD00F01F020121EE
+:1015A00091404009800000F1E020C0F880127047AF
+:1015B00000C0004010ED00E008C500402DE9F047F4
+:1015C000F84C0646FF21606800EB06121170217886
+:1015D000FF2916D04FF0080909EB011109EB061796
+:1015E0004158C059491E21F07F4100F0DDF918B182
+:1015F00094F80080454614E06168207801EB0611FC
+:1016000008702670BDE8F087626809EB0510D159B3
+:10161000105800F0C9F930B96068A84600EB08100E
+:101620000578FF2DF0D1606800EB061100EB081083
+:101630000D700670E6E7F0B5DA4B04460020012590
+:101640005A680C261B7A0BE005EB0017D75DA74202
+:1016500004D106EB0017D7598F4204D0401CC0B20A
+:101660008342F1D8FF20F0BD70B5FFF70EFBCD4CE3
+:10167000014608252278606805EB0212805800F0C8
+:1016800093F9012808D92178606805EB01114058C9
+:10169000BDE87040FFF7F0BAFEF73CFFBDE87040D0
+:1016A000F7F78EBF2DE9F041BE4C2578FFF7EDFA34
+:1016B0000146FF2D6FD04FF00808626808EB051651
+:1016C000905900F071F90228606801D980595EE0F4
+:1016D00000EB051109782170022101EB0511425C34
+:1016E0005AB1521E4254815901F5000121F07F4147
+:1016F00081512846FFF762FF34E00423012203EB07
+:10170000051302EB051250F803C0875CBCF1000F13
+:1017100010D0BCF5806F10D9CCF3090250F806C088
+:101720000CEB423C2CF07F4C40F806C0C3589A1A90
+:10173000920A09E0FF2181540AE0825902EB4C32FF
+:1017400022F07F428251002242542846FFF736FFA2
+:101750000C21606801EB05114158E06850F8272022
+:10176000384690472078FF2815D0FFF78EFA0146BB
+:101770002278606808EB02124546805800F014F9A0
+:10178000012891D92178606805EB01114058BDE826
+:10179000F041FFF771BABDE8F081F0B51D4614467F
+:1017A0000E460746FF2B00D3FFDFA00700D0FFDF68
+:1017B0007C48FF210022C7604460057206740170F6
+:1017C00042701046012204E002EB0013401CE15479
+:1017D000C0B2A842F8D3F0BD70B5724C0646657829
+:1017E000207C854200D3FFDFE06840F82560607808
+:1017F000401C6070284670BD2DE9FF5F1D468B467A
+:101800000746FF24FFF741FADFF89891064699F85A
+:101810000100B84200D8FFDF00214FF001084FF06F
+:101820000C0A99F80820D9F804000EE008EB01131F
+:10183000C35CFF2B27D0BB4205D10AEB011350F844
+:1018400003C0DC4521D0491CC9B28A42EED8FF2C26
+:101850001BD008EB04110AEB0412475440F802B005
+:101860000421029B0022012B01EB041111D04250F4
+:101870004FF4806808234FF0020C454519D9A9059B
+:10188000890D08D008E00C46DDE7FF2004B0BDE874
+:10189000F09F4550ECE7414606EB413203EB041361
+:1018A00022F07F42C250691A0CEB0412890A81545B
+:1018B0000BE005B9012506EB453103EB041321F0DC
+:1018C0007F41C1500CEB0411425499F8005020465E
+:1018D000FFF774FE99F80000A84201D0FFF7C4FE9C
+:1018E0003846D3E770B50C460546FFF7CEF90646F5
+:1018F00021462846FFF79FFE0446FF2817D0294DB2
+:10190000082101EB041168684058314600F04CF89A
+:1019100000F58050400B02216A6801EB0411515C14
+:1019200009B100EB8120002800D1012070BD00200A
+:1019300070BD2DE9F0410F468046FFF77CFEFF2881
+:101940001BD0184E357871682A462C4605E0844233
+:1019500006D0254601EB05131C78FF2CF7D10CE0CF
+:10196000FF2C0AD0A5420CD101EB02100078307098
+:10197000FF2804D0FFF778FE03E000200BE7FFF715
+:1019800081F939464046FFF7ADFFFF220123716818
+:1019900003EB0413CA5401EB041201EB0511127896
+:1019A0000A70F8E65C0D0020401A20F07F40B0F588
+:1019B000000F00D90020704770B50446A0F5000064
+:1019C0002C4EB0F1786F02D23444A4F500042A48BA
+:1019D000844201D2012500E0002500F041F830B139
+:1019E000B4420BD32548006804E0284370BDB442DC
+:1019F00004D32348844201D20120F6E70020F4E713
+:101A000010B50446A0F50000B0F1786F03D2194874
+:101A10000444A4F5000400F023F84FF0804130B1F5
+:101A20001648006804E08C4204D2012003E0144808
+:101A30008442F8D2002080F0010010BD10B520B122
+:101A4000FFF7DEFF08B1012010BD002010BD10B56A
+:101A500020B1FFF7B1FF08B1012010BD002010BD7B
+:101A6000084809490068884201D1012070470020D8
+:101A7000704700000000002000C001001C00002092
+:101A80000800002098000020BEBAFECA0548064A99
+:101A90000168914201D100210160044901200860E0
+:101AA0007047000098000020BEBAFECA40E5014021
+:101AB000404800210170417010218170704770B55D
+:101AC000054616460C460220F5F789FC39490120E7
+:101AD00008703949F01E086038480560001F04602E
+:101AE00070BD10B50220F5F77AFC3249012008706C
+:101AF00033480021C0F80011C0F80411C0F80811E3
+:101B000030494FF40000086010BD2A480178C9B17F
+:101B10002D4A4FF4000111602949D1F8003100220B
+:101B2000002B1CBFD1F80431002B02D0D1F80811D2
+:101B300011B14270102103E001214170234909686D
+:101B4000817002700020F5F74ABC1A48017800291C
+:101B500004BF407870471A48D0F80011002904BF2C
+:101B600002207047D0F8001100291CBFD0F80411E2
+:101B7000002905D0D0F80801002804BF01207047D3
+:101B8000002070470B480178002904BF8078704717
+:101B90000B48D0F8001100291CBFD0F8041100290F
+:101BA00002D0D0F8080108B110207047074800683B
+:101BB000C0B270479C00002010F5004008F50040BE
+:101BC00000F0004004F5014008F5014000F4004039
+:101BD0003148002101704170704770B506461446C7
+:101BE0000D460120F5F7FBFB2B49012008702B481F
+:101BF0000660001D0460001D056070BD2DE9F04108
+:101C000004460120F5F7EBFB234901200870244925
+:101C10000C60244D0026C5F8046123494FF040773D
+:101C20000F60A1F1040844B1012C18BFFFDFC5F813
+:101C30000062C8F80070BDE8F081C5F800024FF0FE
+:101C40008070C8F80000BDE8F0811348017879B1D0
+:101C5000154A4FF0407111601249D1F8042100215A
+:101C6000002A08BF417002D0104A12684270017009
+:101C70000020F5F7B4BB08480178002904BF40787C
+:101C800070470848D0F80401002808BF704707488B
+:101C90000068C0B2704700009F00002008F50040B7
+:101CA00004F5004000F0004008F5014000F4004059
+:101CB00070B5FE4C002501266570257025626572A1
+:101CC000A572E67284F82950256304F13C00A563EF
+:101CD00008F0FEF9002818BFFFDF84F82450F4480C
+:101CE00009F062FAF3480660657770BD30B4EF49D9
+:101CF0000268DFF8C8C34A6142688A61007A0877DF
+:101D00000A7DED4BACF1040401204AB10A7E00FAD1
+:101D100002F21A608D7D002D0CBF2260CCF80020ED
+:101D20004A7D002A04BF30BC70474A7E904018604C
+:101D3000C97D00290CBF2060CCF8000030BC704782
+:101D4000DF4900B50A1D40B101281CBFFFDF00BDFF
+:101D5000DC480860DC48106000BDDC480860DC48F6
+:101D6000F9E7F0B502264FF0E02701240025C7F877
+:101D70008061D8490D600C60D7490A6822F077026B
+:101D800042F0880242F000420A60CD490A1DD0B1FB
+:101D9000012818BFFFDF1AD0D04940F25B6008600D
+:101DA000091F40F203100860081F0460CC4903209B
+:101DB0000860CC4996200860BC4C94F9240010F0CF
+:101DC000030F09D033E0C1480860C14802E0BD48B4
+:101DD0000860BD481060DFE780100A300C2826D26A
+:101DE000DFE800F021252525251D1915110D0A060E
+:101DF000BD49042008601BE0BB48056018E0BA49F3
+:101E0000FC20086014E0B849F820086010E0B649EA
+:101E1000F42008600CE0B449F020086008E0B24902
+:101E2000EC20086004E0B049D820086000E0FFDF43
+:101E3000607F002814BF4FF4C020AC48AC49086054
+:101E4000AD49AC480860091FAC480860C7F880621B
+:101E5000AB491020C1F80403F0BD944A0368C2F8EE
+:101E600002308088D08011727047904890F8290025
+:101E700070478E4A517010707047F0B50D46044699
+:101E800004EB4501908808841078D2F801100127EE
+:101E900040EA012044F8250005F1080007FA00F6A1
+:101EA000002B04BF206BB04304D0012B18BFFFDF11
+:101EB000206B304307FA05F108432063F0BD30B5CD
+:101EC0000D460446082988BFFFDF0022002D11D9E6
+:101ED00054F82210900000F1804000F58050C0F8C6
+:101EE000001604EB4201098CC0F82016501CC2B247
+:101EF0009542EDD8206B8349086030BD10B504468B
+:101F000010F0030F2BD1A0100A300C2827D2DFE8E5
+:101F100000F022262626261E1A16120E0A067249DE
+:101F2000042008601CE070490020086018E06E4939
+:101F3000FC20086014E06C49F820086010E06A4951
+:101F4000F42008600CE06849F020086008E0664969
+:101F5000EC20086004E06449D820086000E0FFDF5E
+:101F6000524880F8244010BD504890F83400704723
+:101F7000654AC178116000686449000208607047D2
+:101F8000252808BF02210ED0262808BF1A210AD012
+:101F9000272808BF502106D00A2894BF0422062211
+:101FA00002EB4001C9B25A4A11605A4908607047B1
+:101FB0003E49086270473D498A7A012A49D0022A7F
+:101FC00018BF70474B7D002B08BF7047DFF848C132
+:101FD000012A42D0CA7D4B7E002A18BF01227D30E3
+:101FE000CCF80000DFF834C10020CCF84C01180216
+:101FF00082F0010240EA025040F00312087F8300A1
+:1020000003F1804303F5C043C3F81025444A02EBB3
+:102010008002887EC30003F1804303F5F833C3F8E0
+:102020001425DFF800C1C3F810C5C97ECB0003F149
+:10203000804303F5F833C3F81425304AC3F810255C
+:10204000012202FA00F002FA01F108433649086061
+:1020500070470B7D002BB9D170478A7D0B7E002A1B
+:1020600018BF01227E30BBE72DE9F84F00280CBFD6
+:10207000012002200D4C224D0322A072C5F800223F
+:10208000627F002A14BF4FF4C022184A264F3A60DC
+:102090004FF00108002976D0012973D002291CBF16
+:1020A000FFDFBDE8F88F206A00283FE0700D0020B8
+:1020B000840D0020A0050040180500500C050050BC
+:1020C00014150040050103001F0003020601020071
+:1020D00025000302FC1F00403C170040381500405B
+:1020E00010150040441500400C1500400000040489
+:1020F00008F5014040800040A4F501401011004067
+:102100000010004040160040241500401C150040FF
+:1021100008150040541500404C85004000800040E8
+:10212000006000404C81004004F5014008BFFFDF23
+:10213000216A206B0844FB490860FC49FA480860A2
+:10214000A17AFB4801290EBF0560FA490160A06B26
+:1021500040F40020A063D5F800924FF0100AC5F8B3
+:1021600008A30026C5F80062F3484FF4802BC0F89E
+:1021700000B0FF208DF80000C5F81061C5F8108090
+:102180003DE000E01CE0012813D0C5F804800228DF
+:1021900018BFBDE8F88F607D002808BFBDE8F88F44
+:1021A000E648C0F84C80E6480068BDE8F84F0A30C1
+:1021B00001E7C5F80080207D0028F1D1BDE8F88F47
+:1021C000E0490128896B07D0022818BFFFDF09D03A
+:1021D000BDE8F84F0A20EEE641F48010A0634FF40A
+:1021E000801004E041F40010A0634FF40010386048
+:1021F000EEE700BF9DF80000401E8DF800009DF83E
+:10220000000018B1D5F810010028F3D09DF80000A7
+:10221000002808BFFFDFC5F80C61C5F81061C5F8DC
+:102220000461C5F81461C5F81861C5F82861C6488D
+:1022300000680090C5F80092C7F800B0C5F804A384
+:102240004FF400203860216A206BBDE8F84F084445
+:102250000A30B0E62DE9F847BC4CD4F8000220F073
+:102260000309D4F804034FF0100AC0F30018C4F8AF
+:1022700008A30026C4F80062B24D687F002814BF8E
+:102280004FF4C020B248AC490860A87A0127012861
+:1022900002D0022803D014E0287D10B911E0687D37
+:1022A00078B1A87EEA7E07FA00F007FA02F210433E
+:1022B0000860287F800000F1804000F5C040C0F831
+:1022C0001065FF208DF80000C4F81061276104E05C
+:1022D0009DF80000401E8DF800009DF8000018B128
+:1022E000D4F810010028F3D09DF80000002808BFA2
+:1022F000FFDFC4F81061C4F828616E72AE72EF722D
+:10230000C4F80092B8F1000F18BFC4F804A3BDE8E8
+:10231000F88700688F4920F07F40086070474FF0D1
+:10232000E0200221C0F88011C0F8801270474FF001
+:10233000E0210220C1F8000170478749087070470A
+:1023400010B5864807F0CCFE002818BFFFDF10BD8F
+:10235000824807F0DBBE82490860704730B5794C8F
+:102360000546206BA84228BFFFDF012020732561AE
+:10237000607F40B1A81C20617448D0F8001241F081
+:102380004001C0F800126D490020C1F844017549B0
+:1023900020690860A06B744940F48000A0634FF48A
+:1023A0008000086030BD674802210173CA210161C5
+:1023B000417F41B1CC2101616449D1F8002242F052
+:1023C0004002C1F800225D4A0021C2F844110269AE
+:1023D000016B1144634A1160816B41F48001816398
+:1023E00061494FF4800008607047564901204877E2
+:1023F0005E49022008605F495D480860091F5E4829
+:10240000086070474F490020487770474A494FF4A9
+:10241000800008604B48816B21F4800181630021BA
+:1024200001737047454801214160C1600021C0F837
+:1024300044114C480160434801637047414800B56E
+:10244000407F002818BFFFDF4020484908603F4810
+:10245000D0F8001241F04001C0F8001200BD394828
+:1024600000B5407F002818BFFFDF3848D0F80012C1
+:1024700021F04001C0F800123C490020086000BD76
+:102480003248D0F8001221F01001C0F800120121EA
+:10249000816170472D480021C0F81C11D0F800124E
+:1024A00041F01001C0F800127047284981B0D1F8FE
+:1024B0001C21012A1EBF002001B070472F4A12685C
+:1024C00002F07F02524202700020C1F81C012C4829
+:1024D00000680090012001B0704730B50C0005463F
+:1024E00008BFFFDF14F0010F1CBF012CFFDF002D20
+:1024F0000CBF01200220134901284872CC721349F5
+:1025000004BFD1F8000240F0040007D0022807BF42
+:10251000D1F8000240F00800FFDF30BDC1F8000232
+:1025200030BD00004885004048810040A8F50140CA
+:10253000ACF501400410004008F501400080004067
+:102540004C850040700D0020181100400010004024
+:10255000000004043C150040A1000020AC0D002048
+:10256000041500404485004004F50140601500401A
+:10257000448000409CF5014028110040481500406F
+:102580001C11004070B5EB4C0022E17A11F0020FF3
+:1025900018BF10F0040F16D111F0100F1CBF94F8E3
+:1025A0003530002B02D094F8363063B111F0080FAB
+:1025B0001CBF94F82830002B05D111F0040F03D074
+:1025C00094F8291001B90122657ADB4900234FF004
+:1025D000010C35B100F00200104314D0BDE870408A
+:1025E00038E6607F002814BF4FF4C020D348D44A97
+:1025F0001060D1F8000220F00300C1F80002A372BD
+:1026000084F80BC070BD012D14D0022D18BFFFDF60
+:102610001CD0A07A01280CBFCA48CB484FF47A716D
+:1026200000F2E730B0FBF1F0216BBDE87040081A12
+:102630008C30C0E4D1F8000220F00400C1F80002A0
+:10264000637284F80BC084F80AC0E2E7D1F8000294
+:1026500020F00800C1F80002637284F80BC0022069
+:10266000A072D6E72DE9F84FB84FD7F84C21B14CFE
+:10267000B3494FF00108A07A0026CAB1012802D060
+:10268000022803D014E0227D12B911E0627D7AB1F4
+:10269000A27EE37E08FA02F208FA03F31A430A6004
+:1026A000227F920002F1804202F5C042C2F810651A
+:1026B000A26B0A60A663217B19B1D7F844110129E6
+:1026C00000D000219C4DD5F81021012A0CBF4022DA
+:1026D0000022012805BFD5F80C31012B002320234F
+:1026E0001A43012805BFD5F80431012B002310231C
+:1026F0001343974A022804BFD2F800C0BCF1010F6F
+:1027000007D1D5F80CC1BCF1010F08BF4FF0080C80
+:1027100001D04FF0000C4CEA0303022804BF1268FA
+:10272000002A05D1D5F80C21012A08BF042200D0C7
+:1027300000221A43022803D1002918BF022100D128
+:1027400000211143022804BFD5F80401012805D156
+:10275000D7F84401012818BF012000D1002040EA29
+:1027600001097C48016811F0FF0F03D0D5F814115E
+:10277000012900D0002184F83410006810F0FF0F08
+:1027800003D0D5F81801012800D0002084F83500C6
+:102790007148006818B1FFF7D8F9012800D000206F
+:1027A00084F83600C5F80C61C5F81061C5F80461FD
+:1027B000C5F81461C5F81861C5F828616748006854
+:1027C0000090C7F84461664800684D46DFF8949170
+:1027D0000090D9F80000E062617F00291CBF801ED4
+:1027E000E062614800682063A07ADFF880A10228D7
+:1027F0000CD1607850B1DAF80010097808402178DF
+:1028000031EA000008BF84F8288001D084F82860ED
+:10281000DFF85C8115F0010F16D098F80010554ACA
+:102820004908E06A52F821108847012198F80020F1
+:10283000514B5208206B53F82220904798F8000023
+:1028400010F0010F0BD01FE015F0200F18BF022170
+:10285000ECD115F0020F18BF0021E7D1EEE7DAF84E
+:102860000000062200F10901A01C08F0B7FA40B9E7
+:10287000207ADAF800100978B0EBD11F08BF0120E8
+:1028800000D0002084F829002846FFF77BFE15F0D1
+:10289000020F05D0394898F8001050F82100804701
+:1028A00015F00C0F07D0364898F8001050F821109A
+:1028B000C5F3C000884715F0200F05D0314898F8BF
+:1028C000001050F82100804798F80000022805D138
+:1028D00005F06E00402806D101F00EF998F80000CE
+:1028E000042828BFFFDFA07A022818BFBDE8F88FB0
+:1028F000207B002808BFBDE8F88FC7F84461022894
+:1029000014D0012818BFFFDF216B2069884298BFCF
+:10291000FFDF2069C9F80000A06B1B4940F480006C
+:10292000A0634FF480000860BDE8F88F2169206B38
+:102930000844EFE7700D0020001000400000040480
+:1029400008F50140F0FE0100B0F8010000800040F1
+:10295000001400404016004060150040181100406F
+:1029600044810040448500404085004004150040FB
+:10297000A1000020E8B40100F0B40100F8B40100A7
+:1029800008B5010018B5010004F5014010B54A482A
+:1029900006F0C5FB0021484806F0F6FB0121464839
+:1029A00006F0C0FB4549002081F822004FF6FF7079
+:1029B000888443490880488010BD10B53E4806F021
+:1029C000AEFB00213C4806F0DFFB01213A4806F04F
+:1029D000A9FB3A49002081F822004FF6FF70888455
+:1029E00037490880488010BD704734498A8C82423C
+:1029F00018BF7047002081F822004FF6FF708884CE
+:102A000070472D49016070472D49088070472B4958
+:102A10008A8CA2F57F43FF3B03D00021016008466A
+:102A2000704791F822202549012A1ABF0160012030
+:102A300000207047214901F1220091F82220012A4B
+:102A400004BF00207047012202701D48008888845E
+:102A5000104670471A49488070471849184B8A8CAD
+:102A60005B889A4206D191F82220002A1EBF01609D
+:102A700001207047002070471048114A818C52880D
+:102A8000914209D14FF6FF71818410F8221F19B1CC
+:102A90000021017001207047002070470748084A54
+:102AA000818C5288914205D190F8220000281CBFE9
+:102AB0000020704701207047D60D0020B00D002087
+:102AC000A200002070B5FF4E044696F88400002551
+:102AD000012807D096F8660001281CBF002070BDB1
+:102AE000E1B90EE0D1B9657014202070D6F88500E8
+:102AF000C4F80200D6F88900C4F8060086F88450AD
+:102B00000CE06570132020701C2206F16801A01CE7
+:102B100008F090F90120A07186F86650012070BD80
+:102B2000E84890F86610002914BFB0F86A004FF624
+:102B3000FF70704770B5E4480178002918BF0C2673
+:102B400001D0304670BDDF4C0026354684F8546015
+:102B500084F8556084F8566084F8576084F85860AB
+:102B600084F8596084F84D6084F82D6084F86460BE
+:102B70007F21817094F85A0028B1FFF770FCFEF7AE
+:102B8000C4FF84F85A5084F86650D04806F074F9AF
+:102B9000CF4806F071F9D4E770B5CB4A002515701F
+:102BA000C84CC4E91701107800281CBFFFDF70BDB6
+:102BB00084F8545084F8555084F8565084F857508F
+:102BC00084F8585084F8595084F84D5084F82D50AA
+:102BD00084F864507F20907094F85A0028B1FFF771
+:102BE0003EFCFEF792FF84F85A5084F86650B748CE
+:102BF00006F042F9BDE87040B54806F03DB9B1486D
+:102C000090F854007047AF4900B591F84F0091F823
+:102C10004E10C0F38002C0F340031A4400F00100DC
+:102C20001044052910D2DFE801F00B070B0309005F
+:102C3000A84931F8100000BDA74800BDA74900E031
+:102C4000A74931F8100000BDFFDF002000BD9D48FE
+:102C500040F27121B0F8500048437047994890F80D
+:102C60006500002818BF0120704770B5954C437B64
+:102C7000002584F84F30037984F84E30012B0EBFC5
+:102C8000A4F85050B0F800C0A4F850C090F80EC09E
+:102C900084F865C021701168C4F801109188A4F807
+:102CA000051081796173D0F80710C4F80710B0F8E7
+:102CB0000B00A4F80B0094F84D000126002818BF63
+:102CC00084F8556094F82D00002818BF84F85660E9
+:102CD000052B2CD2DFE803F0030821260800002191
+:102CE0007A4806F0CCF823E00121784806F0C7F8CE
+:102CF000E11D764806F0F4F8607B20B1012818BF8A
+:102D0000FFDF05D014E00021704806F0FDF80FE069
+:102D100001216E4806F0F8F80AE006216B4806F03B
+:102D2000AEF805E00221694806F0A9F800E0FFDFEF
+:102D300084F8575084F85850611C644806F0C2F873
+:102D40002178624806F0D3F80421614806F097F82C
+:102D5000611C5F4806F0B6F821785D4806F0C7F8B8
+:102D600084F85460002070BD564A012382F8583020
+:102D700092F866C0BCF1000F1CBF3A20704710B437
+:102D800014784FF0000C844218BF82F858C009D163
+:102D900082F857C00868C2F801008888A2F80500C8
+:102DA00082F8573010BC0020704770B5454C05467E
+:102DB000002084F856002A4604F10E0008F03AF884
+:102DC00084F82D50012084F8560070BD10B53D4C9C
+:102DD000002284F8552084F84D00024604F12E00AC
+:102DE00008F028F8012084F8550010BD354981F815
+:102DF0006400704770B5344E3078A0BB314C94F805
+:102E0000540080B3FFF79CFA002584F8525084F8F0
+:102E1000535075702846FFF790FA0020FEF7A1FF87
+:102E20003048FFF7A5F83048FFF773FAFFF7BBFA11
+:102E300094F84F0010F0010F04D094F8521011F0E4
+:102E4000010F13D010F0020F04D094F8521011F0BB
+:102E5000020F18D010F0040F2CD094F8520010F08C
+:102E6000040F1BD026E0FFE70C2070BD2520FFF7E4
+:102E700087F80020FEF764FF94F8520040F001004C
+:102E800084F8520016E02620FFF77AF80020FEF7BB
+:102E900057FF94F8520040F0020009E02720FFF7A6
+:102EA0006FF80020FEF74CFF94F8520040F0040049
+:102EB00084F85200FFF73BFA01210020FFF7D4F815
+:102EC0000F2113E0F80D0020A8000020880E00203C
+:102ED000B00E002038B501009189130040B5010003
+:102EE00030B501002BB5010028B501000520FEF723
+:102EF000C0FF2178601CFEF7B0FF94F84E00012857
+:102F00001EBF042894F85500002808D094F84D20DE
+:102F100004F12E01FE4806F012F884F8555094F89A
+:102F2000560040B194F82D2004F10E01F94806F046
+:102F300032F884F85650206E017819B110F8041B4D
+:102F4000FEF7BDFFE06D017831B1F34A401CFEF79A
+:102F5000B6FD012084F85A00FFF7FAF9002070BD91
+:102F6000EE494860704770B5ED4C05003BD02046F7
+:102F700094F84F1090F8520011F0010F02D010F0A9
+:102F8000010F0CD011F0020F02D010F0020F11D07F
+:102F900011F0040F27D010F0040F18D023E02520E3
+:102FA000FEF7EEFF0020FEF7CBFE94F8520040F053
+:102FB000010009E02620FEF7E3FF0020FEF7C0FE37
+:102FC00094F8520040F0020084F852000BE02720F1
+:102FD000FEF7D6FF0020FEF7B3FE94F8520040F053
+:102FE000040084F8520094F8530040B194F84E0065
+:102FF000012808BFFFDFBDE8704000F054BA1DB1E2
+:1030000002210020FFF730F894F85700002558B14E
+:10301000611CBF4805F056FF611CBE4805F052FF19
+:1030200084F8575084F85850B948FFF794F994F849
+:103030004E00052809D2DFE800F00303030903006E
+:1030400001210846FFF749FA00E0FFDF94F84F003E
+:1030500094F8521030EA01014FF0010002D0AF495C
+:10306000087070BD94F84E10012914BF84F8530005
+:1030700084F85250F3E710B5FFF762F9A7480078DB
+:1030800040B9A74890F8540020B10020FFF76BFF2B
+:10309000002010BDFFF7C6F9FFF7B8F9FFF7DAF81F
+:1030A000FFF73DF9FFF754F90C2010BD9B490120B3
+:1030B000487070479A4981F85900704770B50025EB
+:1030C00002F07BFC68B14FF49670FEF771FF934EEF
+:1030D0003078012809D0022801D003282ED0FFDF44
+:1030E00070BDBDE8704000F0DEB98D4C94F84E0024
+:1030F000032823D094F85A0018B1FEF7F2FCFFF72A
+:103100009DF98848FFF727F994F84E00012818BF69
+:1031100004280AD094F86500012814BF032810255C
+:1031200045F00E010020FFF7D8F994F8640001285B
+:1031300008BFFFF7AFF90220307070BDBDE87040E6
+:10314000012010E770B5764C744D94F864000128A6
+:1031500020D000BF94F85A0018B1FFF780F9FEF7AD
+:10316000D4FC02F02AFCF8B12878022818BFFFDF4F
+:1031700094F84E00012804BF4FF41970FEF718FFB1
+:103180000120FFF7F0FE287800281EBF28780128CC
+:10319000FFDF70BD6448FFF788F9002804BF7F2077
+:1031A000A870FFF76DF9D5E7BDE8704000F07BB976
+:1031B0002DE9F05F82460027FEF7D6FE574D814687
+:1031C000B8462878022818BFFFDF554C4FF07F0B18
+:1031D00094F86400012825D0524805F06FFE064699
+:1031E000BAF1000F6FD04F4805F065FF00286AD094
+:1031F000FEF73BFE002866D094F85A00002818BF5E
+:103200004FF028081ED000BFA8F1010000F0FF0811
+:10321000FEF79BFC02280FD0012808BF4FF00108E1
+:1032200010D00DE04048FFF740F9002808BF85F8AE
+:1032300002B0FFF725F9CFE7B8F1000FE4D1FFDFC7
+:103240004FF0000837484FF0010A062E3BD2DFE866
+:1032500006F083838303833B94F84E10012918BF43
+:10326000042979D059EA080105D194F8651000299C
+:1032700018BF022970D194F86410012904BF94F892
+:103280008410002905D02348FFF765F80320287033
+:1032900063E084F884A0007804F18C06C0F3801009
+:1032A00084F88500D4F8E300C4F88600B4F8E70099
+:1032B000A4F88A00A8787F2808BFFFDFA8783070BC
+:1032C00085F802B0DFE747E0C178E27991421BD18F
+:1032D0000179227A914217D14179627A914213D1D0
+:1032E0008179A27A91420FD1C179E27A91420BD1D0
+:1032F000017A227B914207D10178627BC1F3801170
+:10330000914208BF012200D0002294F84E100DE037
+:10331000880E0020B00E0020DB0E0020A800002048
+:10332000F80D0020D80E0020AA000020012918BFA7
+:10333000042900D14AB979B959EA080105D194F8AC
+:103340006510002918BF012906D194F8581019B941
+:1033500094F85910A346C9B1012794F85A0018B13E
+:10336000FFF77DF8FEF7D1FB002F1CBF0120FFF710
+:10337000FAFD287800281ABF28780128BDE8F09FB8
+:103380002878032818BFFFDFBDE8F09F06466A686B
+:10339000DBF8EF10C2F80D1000786B49C0F3801015
+:1033A0005076DBF8E300C2F81A00BBF8E700D083E0
+:1033B000BBF8F300A2F811009BF8F500D074B07DC3
+:1033C0001075B6F81700D082B6F819005080B6F81C
+:1033D0001B009080B6F81D00D08002F1080007F0B5
+:1033E000E8FE96F8240000F01F016868017696F860
+:1033F0002410490980F8CC109BF86600002818BFFB
+:10340000FFDF00268BF8686068680188ABF86A10F7
+:10341000417E8BF86D10D0F81A10CBF86E10C18B6E
+:10342000ABF872109BF800108BF87410DBF80110E9
+:10343000CBF87510BBF80510ABF879104188ABF8E4
+:103440007C108188ABF87E10C188ABF8801090F8B2
+:10345000CC008BF882009BF88300B8F1000F04BF0A
+:1034600020F001008BF883000BD040F001008BF8B6
+:103470008300FEF787FB9BF8831060F347018BF80E
+:1034800083108BF866A02E70FEF7CCFFFEF7BEFF10
+:10349000FEF7E0FEFEF743FFFEF75AFF01206968E2
+:1034A00002F06AFB59E770B5FEF7BCFFFEF7AEFF0E
+:1034B000FEF7D0FEFEF733FF244C002694F85A00A6
+:1034C00028B1FEF7CCFFFEF720FB84F85A60204DB0
+:1034D0002E70FEF73DFF94F84E004FF000010128DA
+:1034E00004D0BDE87040002002F046BB022002F08C
+:1034F00043FB94F86600002818BFFFDF68780028B7
+:1035000008BF70BD607B84F86D00207884F874007B
+:10351000D4F80700C4F86E00B4F80B00A4F87200E9
+:10352000D4F80100C4F87500B4F80500A4F87900D7
+:103530003C2084F8680068680088A4F86A000120CC
+:1035400084F866006E7070BDF70E0020F80D002044
+:10355000A80000202DE9F041FF4F044600207A78B2
+:10356000FE4D4FF00108064612B1012A08D00DE0C9
+:1035700095F8492052B1002908BF87F8018004E07E
+:10358000AA7F1AB1002908BF7E7001207A782B2308
+:1035900012FB03F22A44937F184312D021BB02F19D
+:1035A0001F012A22A01C07F045FC66700420207031
+:1035B00084F8028078782B2110FB01F0284486776C
+:1035C00012E0287801281CBF0020BDE8F08159B91D
+:1035D0006670132020701C22A91CA01C07F02AFC76
+:1035E000A6712E7085F89F600120BDE8F081DB4850
+:1035F0000178002914BF80884FF6FF7070472DE9CD
+:10360000F041D64C0546A07F002818BFBDE8F081E8
+:10361000284605F053FC00210126072834D2DFE8B4
+:1036200000F004070C3333330E0084F8201009E057
+:1036300084F8206084F828100BE0032000E00220CA
+:1036400084F8200004F12901284605F08EFC84F856
+:103650002800284605F054FC84F8210004F12201DA
+:10366000284605F036FCBC4D04F1480728787F2831
+:1036700008BFFFDF287838707F202870A677BDE864
+:10368000F041032001F023BB84F82810BDE8F0814D
+:1036900010B5002001F0ACFAB04CA0B1FEF747FE27
+:1036A00000210120FEF7E0FC04F1B800FEF753FE14
+:1036B000D4F8A800FEF752FE94F88400032818BF3F
+:1036C00002281FD022E0FEF7ADFEFEF79FFEFEF7B8
+:1036D000C1FDFEF724FE94F8A10030B1FEF7BFFE55
+:1036E000FEF713FA002084F8A100012084F8AC0052
+:1036F000022084F8A300FEF72BFEBDE81040002056
+:1037000001F0E5BA01210020FEF7E7FEFEF7C2FE58
+:1037100094F8A10018B1FEF7E4F9FEF78FFE03203C
+:1037200084F8A30010BD8D490028B1F8AE202CD03C
+:10373000FF2A0BD24FF6FF7000EA4200A1F8AE005C
+:10374000FF2888BFFF2001D9A1F8AE008248426857
+:10375000012A12BF002A0D224260D243C2EBC203EB
+:1037600003EB021291F8AD30DB4303EB830CCCEB9F
+:1037700083131A444260900CB1F8AE20B0FBF2F310
+:1037800002FB130081F8AD007047012ADED9500812
+:10379000A1F8AE0008BF0120D8D1D5E770B56F4CB5
+:1037A00094F8A300022819BF94F8A3000128002070
+:1037B00005461CBF0C2070BD2B2101FB00418D77FD
+:1037C000401CC0B20228F7D3257094F8A10028B19C
+:1037D000FEF745FEFEF799F984F8A15084F89D5054
+:1037E00084F89E5084F89F5084F8A050012084F8FB
+:1037F0007E0084F8845084F8A25084F87B0084F81A
+:103800007C0084F87D00606FA16FE26FD4F8803097
+:10381000C4F88800C4F88C10C4F89020C4F8943020
+:10382000D4F88400C4F8980084F89C50002070BD3F
+:103830004A4A10B5002382F8A330C2E92C010120C6
+:1038400082F8A300FFF7AAFF002818BFFFDF10BD12
+:103850002DE9F047414C81460C2794F8A30001283C
+:103860001FBF94F8A30002280C20BDE8F087FEF7E4
+:1038700067FD0020FEF775FA94F89C004FF00108F0
+:10388000002844D0D4F88800D4F88C10D4F89020C4
+:10389000D4F894306067A167E267C4F88030D4F848
+:1038A0009800C4F88400002684F89D6084F89E6027
+:1038B00094F87B00002801BF94F87C00002894F85D
+:1038C0007D0000281ABF94F8A000002884F89C60AE
+:1038D00023D094F88400032802D0022805D008E001
+:1038E00005211F4800F0F3FC03E003211C4800F011
+:1038F000EEFC94F87A1004F17400FEF7AEFA00279B
+:1039000084F89C6094F8A300012815D10FE094F886
+:10391000A300022808BF0027F4D094F8A3000228CF
+:1039200002BF84F8A3800C20BDE8F08704E084F88F
+:10393000AC80022084F8A300D4F8B400017819B157
+:1039400010F8041BFEF7BBFAD4F8B000017879B187
+:10395000044A401C08E00000B0000020000F0020D6
+:10396000E00F0020BB0F0020FEF7A9F884F8A1802B
+:10397000FD48C4F8A890FEF7CCFCFEF7E9FC3846F9
+:10398000BDE8F08770B5FEF7DBFCF84C94F8A300B7
+:10399000022803D0FEF7DCFC0C2070BD012084F867
+:1039A000AD00A4F8AE000220FEF7C7FCF048FEF719
+:1039B000DFFAF04B002004F17B0200BF94F8A21064
+:1039C000491CA3FB015C4FEA5C0CACEB8C0C614422
+:1039D000C9B284F8A210895C012907D0401CC0B28A
+:1039E0000328EBD3FFF754FE002070BD94F8A2002B
+:1039F000E149085CFEF7C4FA0020FEF7A1F9F1E7FF
+:103A0000DA4B10B44FF0010C83F89EC093F89F403E
+:103A1000002C1EBF3A2010BC7047002418B993F840
+:103A20008E0088420FD183F88E1083F89D40106875
+:103A3000C3F888009088A3F88C0083F89DC083F8B1
+:103A4000A0C083F89CC083F89E4010BC0020704743
+:103A50000300C6494FF000004FF0010208BF81F893
+:103A6000922005D0012B16BF122081F892007047DA
+:103A700081F89C2081F899307047BC4A032808BF20
+:103A8000C2F8941082F89800012082F89C0000206F
+:103A90007047B64890F89C1029B190F8990000281A
+:103AA00008BF704704E090F88500002808BF704701
+:103AB0000120704710B5FEF7B5FCFEF7A7FCFEF736
+:103AC000C9FBFEF72CFCA94C94F8A10030B1FEF71D
+:103AD000C6FCFEF71AF8002084F8A100012084F843
+:103AE000AC00022084F8A300FEF732FC002010BDD9
+:103AF0009E4981F8A400704710B5FEF793FCFEF7CD
+:103B000085FCFEF7A7FBFEF70AFC984C94F8A10091
+:103B100030B1FEF7A4FCFDF7F8FF002084F8A10007
+:103B2000012084F8AC00022084F8A300FEF710FC0A
+:103B3000BDE81040002001F0CAB82DE9F05F002672
+:103B4000DFF83882894C7F2780B104F1B80005F096
+:103B500082FA20B904F1B80005F09DFA30B194F86A
+:103B6000840003280DD194F89E0050B194F8A3006E
+:103B7000052828BFBDE8F09FDFE800F0BABABAF523
+:103B8000F40094F8A3007E4D4FF0010A052880F060
+:103B90005D82DFE800F0FBFBFB03FA00784805F0EC
+:103BA0008DF97649887094F87E0030B9FEF7DCF91B
+:103BB000002808BF4FF0000801D04FF0010894F82A
+:103BC000A100002818BF4FF0280915D0A9F1010065
+:103BD00000F0FF09FDF7B9FF8346022803D1B9F1D0
+:103BE000000FF3D1FFDFB8F1000F14D1BBF1010FCB
+:103BF00018BF4FF000080ED0DFF880914FF0020B95
+:103C000099F80200072880F08281DFE800F073F75E
+:103C100007F6F6F625004FF00108EDE794F8A1004D
+:103C200018B1FEF71CFCFDF770FF5448FEF73DFC91
+:103C3000002808BF89F80070FEF722FCB8F1000FD9
+:103C400000F05F8194F88400012818BF022840F03A
+:103C50005881FEF7FFFAEBE094F8A10018B1FEF7E7
+:103C6000FEFBFDF752FF4548FEF71FFC002808BF8A
+:103C700089F80070FEF704FCB8F1000F00F04181F4
+:103C800094F88400022803D001287DD000F039B9CF
+:103C90003B48FFF7B4FC012000F0AAFF58B13949B6
+:103CA000A1F1280005F039F93648FEF754FB94F8E5
+:103CB0009D00A0B190E0FEF7B5FBFEF7A7FBFEF775
+:103CC000C9FAFEF72CFB94F8A100002870D000BFC1
+:103CD000FEF7C5FBFDF719FF84F8A1609DE0012107
+:103CE0000846FEF7FAFBFEF75EFB052084F8A3000A
+:103CF000BDE8F09F94F8A10018B1FEF7B0FBFDF706
+:103D000004FF1E48FEF7D1FB002808BF89F80070A9
+:103D1000FEF7B6FBB8F1000F71D094F884000228CA
+:103D200047D0012830D003281CBFFFDFBDE8F09F3B
+:103D3000E978D4F88000827E914231D12979C27E1F
+:103D400091422DD16979027F914229D1A979427F8F
+:103D5000914225D1E979827F914221D1297AC27F8E
+:103D6000914214E08BE174E148B50100000F00209E
+:103D70004EB50100ABAAAAAA4BB50100B0000020C5
+:103D8000B80F0020E00F002052E0CFE05EE107D145
+:103D90002978427EC1F38011914208BF012100D0F1
+:103DA000002194F88520012A48D0002927D0A0E0DE
+:103DB00033E0FE48FFF723FC012000F019FFF8B1C3
+:103DC000FB49A1F1280005F0A8F8F948FEF7C3FA6D
+:103DD00094F89D00002882D0D4F888006067B4F879
+:103DE0008C00A4F8780004F17401F14805F06AF839
+:103DF00084F89D6084F89E6071E788E02CE07FE0A5
+:103E0000FEF710FBFEF702FBFEF724FAFEF787FA37
+:103E100094F8A10000287FF45BAF84F8ACA084F88C
+:103E2000A3B0FEF795FABDE8F05F002000F04FBFA9
+:103E3000DE48FFF7E4FBBDE8F05F29E4F1BB00BF1B
+:103E400000F11A01D94805F044F8D84805F058F8AF
+:103E5000D4F8801048764CE094F8A10018B1FEF731
+:103E6000FEFAFDF752FED348FEF71FFB002808BFFD
+:103E700089F80070FEF704FBB8F1000F41D0FDF7A0
+:103E8000F4FFE8B394F88400032808D0C748FFF78C
+:103E9000B6FBFEF7DFF9BDE8F05FFFF7F9BBD4F83A
+:103EA0008000E978827E91421DD12979C27E9142BB
+:103EB00019D16979027F914215D100E019E0A97901
+:103EC000427F91420FD1E979827F91420BD1297AC9
+:103ED000C27F914207D12978427EC1F3801191427D
+:103EE00008BF012100D0002194F88520012A04D0C8
+:103EF00031B1BDE8F05F00F08FB90029F9D19FE73B
+:103F0000FFE7FEF7A7F9BDE8F05FFFF7C1BB94F844
+:103F1000A10018B1FEF7A3FAFDF7F7FDA548FEF7DB
+:103F2000C4FA002808BF89F80070A0E09F4804F098
+:103F3000C5FF88F802009E48E978427A91421CD178
+:103F40002979827A914218D16979C27A914214D141
+:103F5000A979027B914210D1E979427B91420CD13F
+:103F6000297A827B914208D129780078C1F38011A7
+:103F7000B1EBD01F08BF012500D00025FEF76AF97C
+:103F800098F8020004284BD1F5B38A48FEF78DFA61
+:103F9000002808BF88F80070FEF772FA94F8AC00A9
+:103FA00000281CBF0020FFF7BEFB84F8ACA07F4DAB
+:103FB00094F8490018B1BDE8F05FFFF769BB042031
+:103FC00084F84B00284604F09BFF002808BF84F8C3
+:103FD0004C6003D0012808BF84F84CA004F14D01C7
+:103FE000284604F076FF04F15401284604F0E9FF66
+:103FF00084F853001F2884BF1F2084F8530004F165
+:10400000730598F8000000E00AE07F2808BFFFDF92
+:1040100098F80000287088F8007084F849A0CAE772
+:104020006448FEF742FA002808BF88F80070FEF7DF
+:1040300027FA94F8AC00002804BF0120FFF773FBB7
+:1040400084F8AC60BDE8F05FFFF722BBFFDFBDE89E
+:10405000F09F94F8A10018B1FEF701FAFDF755FDA5
+:104060005448FEF722FA002808BF88F80070FEF7CF
+:1040700007FAFEF7EFF8BDE8F05FFFF709BB4D4820
+:10408000FEF713FA002808BF88F80070FEF7F8F969
+:1040900094F8AC00002804BF0120FFF744FB84F82B
+:1040A000AC60FEF7D7F8BDE8F05FFFF7F1BA70B586
+:1040B000414C94F8A30007285ED2DFE800F05D5D74
+:1040C0005D5D5D040D003948FEF745F9FEF7E2F944
+:1040D000042084F8A30070BDFEF7A4F9FEF796F95A
+:1040E000FEF7B8F8FEF71BF9012584F8AC50022062
+:1040F00084F8A300FEF72CF92078002818BFFFDF12
+:104100000020A070D4F880000188A180417EE17178
+:10411000D0F81A10A160C18BA1814188E182818809
+:104120002183C088608394F8A400207794F87A00F3
+:10413000A073606FC4F80F00B4F87800A4F81300FF
+:1041400094F8A10018B1FDF700FD012809D0607FA7
+:1041500020F0010060772570BDE87040022000F07B
+:10416000B6BD607F40F001006077FDF70BFD617F19
+:1041700060F347016177EEE7FFDF70BD70B50E4C6D
+:1041800094F8A3000025052828BF70BDDFE800F0E3
+:104190004343432503000748FEF787F910B9054953
+:1041A0007F200870FEF76CF908E00000B80F0020CF
+:1041B000E00F0020B0000020000F002094F8AC00B9
+:1041C000002804BF0120FFF7AEFA84F8AC50FEF7D8
+:1041D00041F8BDE87040FFF75BBAFEF723F9FEF740
+:1041E00015F9FEF737F8FEF79AF894F8A10028B110
+:1041F000FEF735F9FDF789FC84F8A150012084F819
+:10420000AC00022084F8A300FEF7A2F8BDE87040DD
+:10421000002000F05CBD70BD70B5022000F0E8FC2D
+:104220000025604C0126A0B3012000F050FD04F1F0
+:10423000E001A1F1280004F070FED4F88000C18AEA
+:1042400004F1E00004F0E9FED4F88000017D04F1FF
+:10425000E00004F0E6FE04F1E000FEF77CF894F8DC
+:104260009D0080B1D4F888006067B4F88C00A4F891
+:10427000780004F1740104F1E00004F023FE84F8F6
+:104280009D5084F89E5084F89F60062084F8A30017
+:1042900070BDFFE7FEF7C6F8FEF7B8F8FDF7DAFFE6
+:1042A000FEF73DF894F8A10028B1FEF7D8F8FDF725
+:1042B0002CFC84F8A15084F8AC60022084F8A300A0
+:1042C000FEF746F8BDE87040002000F000BD70B574
+:1042D000344C0546032952D0052918BF70BD04F09F
+:1042E000CBFD0521284604F0CAFD94F87A10284633
+:1042F00004F0FDFD04F17401284604F0E3FDD4F858
+:10430000800000F10D01284604F071FED4F8800011
+:1043100000F11101284604F06EFED4F88000017D02
+:10432000284604F07EFED4F88000C18A284604F0B6
+:1043300074FED4F880004188284604F062FED4F868
+:1043400080008188284604F060FED4F88000C1888F
+:10435000284604F05EFED4F8800000F108012846EB
+:1043600004F076FED4F88000017E284604F05BFE5F
+:1043700094F8A4102846BDE8704004F05EBE04F036
+:104380007BFD0321284604F07AFD94F87A10284634
+:1043900004F0ADFD04F174012846BDE8704004F05E
+:1043A00091BD0000000F00202DE9F047744E054636
+:1043B00084B096F800040C46DFF8C8A140099AF8CA
+:1043C00000144909884218BFFFDF96F8000440092D
+:1043D0006D4991F800144909884218BFFFDFDFF8E2
+:1043E000AC816E1E08F13809002709EB4505092C40
+:1043F00080F0C280DFE804F005323C3C37C0C0C02A
+:1044000070000B2EA8BFFFDF35F8020C0621F9F76C
+:1044100014FB040008BFFFDF0B2EA8BFFFDF35F839
+:10442000020C2188884218BFFFDF94F8980000280A
+:1044300008BFFFDFC8F8047088F80170C8F80C7076
+:10444000606AB0F5717F88BFA0F237372046C8F8A0
+:10445000087004B0BDE8F04702F0D5B904B0BDE87B
+:10446000F04702F02CBA04B0BDE8F047FEF7FAB806
+:104470009AF8140D4649400991F8001449098842F8
+:1044800018BFFFDF0B2EA8BFFFDF35F8020C062197
+:10449000F9F7D3FA040008BFFFDF0B2EA8BFFFDF38
+:1044A00035F8020C2188884218BFFFDF204602F051
+:1044B000BCFA002818BFFFDF00222146684600F042
+:1044C000EAFC94F8A2006946FBF7BEFD208E401C72
+:1044D000208604B0BDE8F0870B2EA8BFFFDF35F8BB
+:1044E000020C0621F9F7A9FA040008BFFFDF0B2E22
+:1044F000A8BFFFDF35F8020C2188884218BFFFDF14
+:1045000094F89800042818BFFFDF84F8987094F896
+:10451000A2504FF6FF76681E0B28A8BFFFDF09EBFD
+:10452000450020F8026C94F8A200FBF727F984F804
+:10453000A270D4F8A800002804BFD4F8A400C8F8DA
+:10454000100008D0D4E92B12114482691144816112
+:10455000D4E92901C860D4F8A400002819BFD4F810
+:10456000A8100161D4F8A80087610A48007804B057
+:10457000BDE8F047F5F724B8FFDF04B0BDE8F087E9
+:1045800001E000E00BE000E018E000E0081000208F
+:1045900019E000E0B80000202DE9F047FD4E074685
+:1045A0000024F08B401C80B2F0833278A046002AB1
+:1045B00008BFFFDF09D0F74B042AA3F114095D6897
+:1045C00013D0052A18BFFFDF44D021463069FBF71E
+:1045D000ADFB306187F8008001213971B860B068A7
+:1045E00000F22710F860BDE8F0870A282CBF0220EF
+:1045F0000320787100297BD0D6F810A0D9F810409C
+:1046000034B3A146E468002CFBD1B9F1000F1FD0F0
+:1046100099F80000002808BFFFDFD9F81410D9F876
+:10462000040001445046FCF707FB002807DA291A6A
+:104630004A1E92FBF5F202FB0504294604E090FBBA
+:10464000F5F202FB150429468C4288BFFFDFBCE768
+:104650004446BAE702207871002953D0D6F818A052
+:10466000BAF1000F08BFFFDF0025DAF8AC20D9F857
+:1046700010402846691E5CB1A069904228BF814263
+:1046800084BF014625462046E468002CF4D105B9D4
+:1046900005460AF19804CAF8A850002D04BFC4F8D2
+:1046A0000C80C9F8104005D0E868EC60E060002894
+:1046B00018BF0461D4F81090C4F81880B9F1000F45
+:1046C0000ED0D9F8180048B1D4F814A0504538BF1E
+:1046D000FFDFD9F81800A0EB0A00A061C9F8188024
+:1046E000002D08BFC6F8208009D02878002800E0F7
+:1046F00008E008BFFFDF696968680844306240F677
+:10470000B83462E72C4660E72DE9F041A24C8046C0
+:1047100084B094F800040E46A04F410997F80004B5
+:104720004009814218BFFFDF94F8000440099C490A
+:1047300091F800144909884218BFFFDF00250122C3
+:10474000092E944C5ED2DFE806F0051B3636315D4B
+:104750005D184C0062732273607800281CBF04B09F
+:10476000BDE8F0818F484560C5602573A068CD38ED
+:10477000FFF76EF8002818BFFFDF04B0BDE8F08136
+:10478000607850B1207B002808BFFFF793F965736C
+:1047900004B0BDE8F041FAF738BFA273FFF7F2F8B2
+:1047A000002818BFFFDF04B0BDE8F08104B0BDE809
+:1047B000F041FDF757BF97F8140D7B49400991F878
+:1047C00000144909884218BFFFDF01220021684612
+:1047D000FFF7E2FE69464046FBF736FC04B0BDE851
+:1047E000F0812078052818BFFFDF207F002808BF50
+:1047F000FFDF25772570207DFAF7C0FF257504B00F
+:10480000BDE8F081FFDF04B0BDE8F0812DE9F041A3
+:10481000604C84B00025207804281FBF207805282C
+:104820000C2004B018BFBDE8F08101276770607BE1
+:10483000002690B172B6607B00281CBFA07B0028C8
+:1048400005D0FFF737F96673A673FAF7DEFE62B696
+:10485000207DFCF77BFAD0B913E094F81480032094
+:104860008DF804008DF80500FAF79EFF02904FF0D6
+:10487000FF3003908DF8007069464046FBF7E4FB7B
+:10488000E6E720BF207DFCF761FA0028F9D0207F01
+:1048900028B126772078052818BFFFDF0C25667021
+:1048A0002670207DFAF76AFF267504B02846BDE819
+:1048B000F0812DE9F047374884B00078002818BF10
+:1048C000FFF7A4FF0120374E307069460620F9F744
+:1048D00040F8002818BFFFDF00254FF6FF7718E0EB
+:1048E000029800281CBF90F89810002911D0008869
+:1048F000B84218BFDFF8B48045D00621F9F79DF81B
+:10490000040008BFFFDF94F8A200FCF71FFA68B9A3
+:1049100005E06846F8F7FBFF0028E1D033E020BF50
+:1049200094F8A200FCF712FA0028F8D084F8985006
+:1049300094F8A2904FF6FF7AA9F101000B28A8BFC6
+:10494000FFDF08EB490020F802AC94F8A200FAF768
+:1049500015FF84F8A25069460620F8F7FAFF0028F0
+:1049600018BFFFDF0AE0029800281CBF90F89810DB
+:10497000002903D00088B842BFD104E06846F8F7A8
+:10498000C6FF0028EFD03570356104B00020BDE8C7
+:10499000F08700001C10002001E000E00BE000E0C8
+:1049A00018E000E00810002019E000E040100020AE
+:1049B00010B50078FE4C60B101280CBF40F6C41061
+:1049C000FFDF06D0A06841F66A01884228BFFFDFFA
+:1049D00010BDA060F6E710B5F54C00232070F54837
+:1049E00003704370037703734373837383610375A9
+:1049F00024304FF6FF7101800522418020F8041F0A
+:104A0000521EFAD1180008BFA36005D0002B0EBFBC
+:104A1000FFDF40F6C410A060A06841F66A0188423A
+:104A200028BFFFDFBDE8104043E770B5E14C0E46FC
+:104A300084B02178154600291EBF0C2004B070BD3B
+:104A4000416A01F29731C0F8AC10A06190F898006B
+:104A5000002818BFFFDF40F2712006FB00F1684319
+:104A60000A30C4E90110A1F53D71884288BF0846AB
+:104A7000A060D1490020C8600521217060702077B6
+:104A8000E083CE48FAF72BFE2075002808BFFFDF31
+:104A9000FAF78AFE2061002201216846FFF77CFDBB
+:104AA000207D6946FBF7D0FA04B0002070BD884233
+:104AB00034BF012200220244D2B2814234BF01201D
+:104AC00000200844C1B28A4234BF08461046831A07
+:104AD000A0EB010C114401EBC102634402EB411154
+:104AE00003EB83031B0100EB400203EBC10102EB6C
+:104AF000001201EBC201C0EBC00202EB401001EB5F
+:104B00008000983870474FF44B72B1F54B7F38BF37
+:104B1000114641627047A748007800281CBF00205A
+:104B2000704710B50620F8F725FF80F0010010BD92
+:104B300010B5A04C84B02278002A1EBF0C2004B00F
+:104B400010BD40F27122424340F2712048430A30C6
+:104B5000C4E90120A2F53D71884298BF01460020BA
+:104B6000A160607004212170E0839448FAF7B7FDDA
+:104B70002075002808BFFFDFFAF716FE40F6B831AF
+:104B8000FBF7D4F82061002201216846FFF704FDFD
+:104B9000207D6946FBF758FA04B0002010BD70B5BF
+:104BA000844CA1690160FFF731FE002308B1A361C5
+:104BB00070BDA169D1F8A8205AB1D1E92BC5AC4488
+:104BC0009569AC44C2F818C0D1E9292CCCF80C2066
+:104BD00005E0DFF8E4C1D1F8A420CCF81020D1F82A
+:104BE000A420D1F8A810002A14BF11618B61DEE760
+:104BF000714910B54968002801F1980408BF04F50F
+:104C0000BC7409D0012808BF04F5317404D002280F
+:104C100014BFFFDF04F5B07466488068A0428CBF03
+:104C20000120002010BD6448D0E90112914204D255
+:104C30000078002804BF012070470020704730B57D
+:104C40005B4D85B0042221B3012908BF03211CD08C
+:104C5000022908BF80F8982023D003291EBFFFDF58
+:104C600005B030BD418840F2E2425143544A1160E0
+:104C7000D0F8BC100A89C2828A7902754A894280BA
+:104C80008A898280C989C180022180F8981005B084
+:104C900030BD044648480078002818BF84F89820A2
+:104CA00007D0FAF7B2FC287805B0BDE83040F4F739
+:104CB00087BC01222146684600F0EDF894F8A20076
+:104CC0006946FBF7C1F9208E401C2086E9E72DE9F3
+:104CD000F041374F0100374C387884B04FF0000571
+:104CE0000ED001291CD0022976D003291EBFFFDF78
+:104CF00004B0BDE8F08104B0BDE8F041F4F760BC59
+:104D0000E583F4F75DFC6078002875D10022114638
+:104D10006846FFF741FC207D6946FBF795F96BE09B
+:104D2000DFF89480206940F2E243D8F80410084488
+:104D3000A16900F251604A88983102FB03F5D8F866
+:104D400010208A4208BF002614D0216AFBF774FFA6
+:104D5000002807DA291A4A1E92FBF5F202FB050623
+:104D6000294604E090FBF5F202FB150629468E4227
+:104D700088BFFFDFB868864208D2A06940F271227E
+:104D80004188C1824A4306EB420605E040F2E24018
+:104D9000B6FBF0F0A169C882A06905210175C08A3F
+:104DA0006FF41C71484306EB400040F635410AE0C1
+:104DB000B80000201C100020081000200947010046
+:104DC000BC00002008E0C8F80C00B0EB410F28BF81
+:104DD000FFDF04B0BDE8F081E583F4F7F1FB0120CB
+:104DE0002077A0692169C0F89C1080F8985021783C
+:104DF000052918BFFFDF06D0FAF707FC6573A57316
+:104E000004B0BDE8F081002808BFFFDFA06990F87A
+:104E10009800002818BFFFDFA06990F8A2000028C2
+:104E200018BFFFDF5B48FAF75AFCA169064681F814
+:104E3000A2000F88401E0B28A8BFFFDF564800EBDA
+:104E4000460020F8027CA06990F8A200002808BF64
+:104E5000FFDF01226846A16900F01DF8A0696946DC
+:104E600090F8A200FBF7F0F8A561C5E7704700B520
+:104E70004A4A59B1012908BF401E07D002291CBF68
+:104E8000FFDF00BD5178491C5170C01F506000BD4C
+:104E90004348007870472DE9F05F06460C46488885
+:104EA00040F2E24141439046E08A40F2E24200FB98
+:104EB00002FA94F898200025384F4FF0030B4FF07A
+:104EC000010952B13846012A40682DD0022A16D075
+:104ED000032A18BFFFDF27D036E0B8F1000F08BF64
+:104EE000FFDF7868002808BFFFDF7868F968C01D19
+:104EF00008440AF25D41451884F8989023E0A8F12F
+:104F00000101084308BFFFDF2648B8F1000F006821
+:104F100000EB0A0505D0786800F20F30A84288BF80
+:104F2000FFDF84F898B00EE00D46B8F1000F0AD00C
+:104F300018B97878002818BFFFDF786800F20F30C2
+:104F4000A84288BFFFDF05B9FFDF2946D4F89C00DF
+:104F5000FAF7ECFEC4F89C000020307086F804904C
+:104F6000D4F89C00B060204601F095FD002818BFE1
+:104F700086F8059005D0606A00F5E570F060BDE840
+:104F8000F09F94F89800012806BF0220707186F8FF
+:104F900005B0F0E7A94301004010002008100020F0
+:104FA0001C100020BC000020FE48C07E7047FE4858
+:104FB00040687047FD48C07E7047884234BF012278
+:104FC00000220244D2B2814234BF012000200844B2
+:104FD000C1B28A4234BF08461046831AA0EB010CC6
+:104FE000114401EBC102634402EB411103EB830363
+:104FF0001B0100EB400203EBC10102EB001201EBCD
+:10500000C201C0EBC00202EB401001EB80009C38F3
+:1050100070474FF44A72B1F54A7F38BF114641627A
+:1050200070472DE9FF4FDF4E83B08846706A3468C1
+:105030005FEA03090568D4F804B0306A0190298E4C
+:105040000598A0EB010080B2009019BF04F1380769
+:1050500004F1480A371D05F1A80A032038710398A6
+:10506000002832D0012800F0DF8002287DD00328FC
+:1050700018BFFFDF00F00C81B9F1000F1EBF3879B7
+:105080000328FFDFA16A7069FAF750FEB860D4E91F
+:10509000081081428EBFCAF800000846CAF8001006
+:1050A000696A084400F24F10F860B5F89810059846
+:1050B000081A00B2002840F349810398022818BF5B
+:1050C000032040F0448100F041B9306A002808BF55
+:1050D000FFDFE98A40F27120484340F2E24101EBF0
+:1050E00040010020B8F1000F06D0B14808FB01F1E3
+:1050F000B1FBF0F000F10100A061698840F2E242EA
+:1051000001FB02F24FF0000106D0A94908FB02F2B0
+:10511000B2FBF1F101F10101E161316A40F2712369
+:1051200001F10101A162EA8A02FB03F2C0EB420233
+:1051300002F237421144A1622A7D40F2E24312FB9F
+:1051400003F202EB400000F2151020626062306A48
+:10515000A1EB00009749A0F1010009188CD2B0F52D
+:10516000387F98BFFFDF5CE0FFE7E98A40F27122F9
+:10517000E068514300EB41010020B8F1000F06D078
+:105180008B4808FB01F1B1FBF0F000F10100A061D8
+:10519000688840F2E24100FB01F14FF0000006D0C8
+:1051A000834808FB01F1B1FBF0F000F10100E06180
+:1051B000306A002808BFFFDFB5F8AE00E98A002892
+:1051C00040F27122E06801FB02F100EB4100A169AD
+:1051D000A0EB010003D13168D33849680844A062CC
+:1051E0002269A168A06901FB0200297D40F2E24228
+:1051F00011FB02F101EB400000F2131020626988FC
+:105200005210E0695143C0EB4100A0F54770606265
+:10521000A06A316A401AA0F5AA7167484018BFF425
+:105220002BAF0120387127E7B5F8AE00002808BF82
+:10523000FFDF306A002808BFFFDF698840F2712273
+:10524000E0695143C0EB4101A162B5F8AE3022697B
+:10525000D4F818C0D4F808809B1A08FB02C203FBDC
+:1052600000202A7D40F2E24312FB03F202EB4000F1
+:1052700000F213102062A1F547706062306A081ACC
+:10528000A0F5AA714C484018BFF4F6AEC9E700BFBC
+:10529000B9F1000F1CBF94F83400002803D007B008
+:1052A0000220BDE8F08F698840F27122E069514325
+:1052B000C0EB410100984843A062B5F8AE0030B39E
+:1052C000BBF1000F18BFFFDFB5F8AE100098002249
+:1052D0000844E169484302EB400000F213102062E9
+:1052E000688840F271225043C1EB4000A0F547703E
+:1052F000606232484068B0B1A26A01990120511A37
+:10530000A1F5AA722C49891838BF3871B4E6BBF1EF
+:10531000000F1ABF01980028FFDFABF1D301A06A8C
+:105320000844A062D0E7FAF73FFA726901461046D6
+:10533000FBF782FCA16A081AA0F24F111E48401820
+:105340003EBF012007B0BDE8F08F95E600207871E0
+:105350001098C8B1B5F8C01000290CBF0020B5F8EE
+:10536000C200A5F8C20095F8C420401C50438842F2
+:105370000AD27879401E002806DD01207871B5F840
+:10538000C200401CA5F8C20087F80090B9F1000FD8
+:105390001CBF94F83400002881D189F0010084F802
+:1053A00035000DE058100020DC00002080100020A7
+:1053B00040420F00DBF7FFFFF4F8FFFFCC000020B6
+:1053C000307FF27E3946B37E9A4202D0FAF73CFE35
+:1053D00004E00020F076B0763060706207B0002004
+:1053E000BDE8F08F70B5FD4D0929D5E900326FD2C7
+:1053F000DFE801F0055B73816F9494589000002002
+:105400001062D17E04294ED2DFE801F04D4D0245F5
+:10541000516A0C681168087011684860106890F84B
+:10542000350040B9FAF7C0F969680968096CFBF7FB
+:1054300003FC002818DC686801684A8E218E8A42C5
+:1054400006D1B4F89C20511AA4F89E10228605E0DB
+:10545000511AA4F89E100168498E21860268C1681D
+:105460001164C168416111E068680168098E228E8B
+:10547000891AA4F89E100168098E218601680A6CB9
+:10548000C2600A6C4261886CC4F8A8002046BDE87E
+:10549000704002F01DBAD0685061FDF7ABFC0028E7
+:1054A00018BFFFDF70BDFFDF70BDD07E04280DD2B6
+:1054B000DFE800F00C0C0206BDE8704002F0D8BA3C
+:1054C000FDF7D9FD002818BFFFDF70BDFFDF70BDFD
+:1054D00024E0BDE87040FDF7C5B8D87E022804D0AE
+:1054E000D87E032818BFFFDF0CE0BD48007D0128EF
+:1054F00008BFFFDF0AE0D87E022807D0D87E032845
+:1055000018BFFFDFBDE8704000F0B5BBBDE87040DC
+:1055100000F0FCBBBDE87040FAF730B9FFDF70BDAA
+:105520002DE9F047AD4D0024AE4E82460F464FF0B8
+:10553000010809294ED2DFE801F0053B46463B4D04
+:105540004D4646006868DFF89C92002818BFFFDFD0
+:1055500039465046C5F80490FFF744FFF07E022814
+:1055600018BFBDE8F08768680568406A0768FAF701
+:10557000FEF87A8840F27123E9695A43C1EB42018F
+:10558000AB39B72898BFB72000F54A70081A796A76
+:10559000A0F20130B1F5717F88BFA1F5717484422A
+:1055A00038BF2046E862306880F83480BDE8F08774
+:1055B0005046FFF717FFF07E022804BF306880F8DE
+:1055C0003480BDE8F08750462E60FFF70BFF2C605B
+:1055D000BDE8F087FFDFBDE8F0872DE9F0417F4CA3
+:1055E00007460D4609291ED2DFE801F00510141404
+:1055F000101D1D14140060687B4E002818BFFFDFCB
+:10560000294638466660BDE8F041EBE63846BDE81D
+:10561000F041E7E6744820603846FFF7E3FE0020DB
+:105620002060BDE8F081FFDFBDE8F081F0B56D4995
+:1056300085B00026CA7E694C032A03D02831CA7E71
+:10564000032A64D10025216000B3012806BF03208E
+:105650008876FFDF0AD02068002E0560456225604D
+:1056600055D06248456005B00020F0BD2068C17E7D
+:1056700029B1C17E827E914208BF20BFF6D0C17E93
+:1056800000290CBF012600268576E4E700260327C3
+:1056900008468F76C97E032904D0C07E002808BF43
+:1056A000012631E00120FDF705FD2068007F00287C
+:1056B00008BFFFDF2068067F8DF804708DF8057045
+:1056C000FAF772F802904FF4FA70039001208DF807
+:1056D000000069463046FAF7B7FC2068007FFBF708
+:1056E00035FB30B920BF2068007FFBF72FFB002877
+:1056F000F8D02068007FFAF741F820680577C57672
+:10570000857605600126456220688576A3E705B0A9
+:105710000C20F0BD10B5334800F076FB324800F0A5
+:1057200073FB2F4900200875304948702D494861A6
+:1057300001F1280250618876907628494860086017
+:1057400010BD2DE9F0412A4C064694F80004294D7D
+:10575000400995F800144909884218BFFFDF94F802
+:1057600000044009244991F800144909884218BFEF
+:10577000FFDF95F8140D4009204991F800144909FC
+:10578000884218BFFFDF1E48164D00240670EC76D5
+:10579000AC7605F12806F476B4761030012101715B
+:1057A00004606C6274622C6000F108073460284663
+:1057B0007C6000F029FB05F1280000F025FB05F1D5
+:1057C000500004757C706C617461AC76B476A7F19E
+:1057D000100044600460BDE8F0810000CC000020AF
+:1057E000A81000205810002080100020DC000020AD
+:1057F00001E000E00BE000E018E000E019E000E06C
+:10580000C4000020F849087170472DE9F843F749B2
+:105810000546CA7EF64C01F12800002A04BFC27E6C
+:10582000002A73D0C97E022907BFC17E00290C203F
+:10583000BDE8F8832060EF48F9F751FF2168087749
+:10584000ED4845602168086014384862ADB1012117
+:1058500005F1C400FBF762FD0620F8F799F806464B
+:105860000720F8F795F895F8C4103044B1FBF0F232
+:1058700000FB1210401C85F8C4002068007F00283F
+:1058800008BFFFDFF9F773FFDC49091838BF40F2A2
+:10589000F65000F26B1087B220680326C676FDF73B
+:1058A000B2F921680861FDF7D2F94FF0010800252F
+:1058B00058B3FDF7CCF921684A6A106008680121E5
+:1058C00080F800806846FBF7B4FC9DF8000042F2C7
+:1058D00010710002B0FBF1F201FB1208F9F764FF4E
+:1058E00007EB0801FAF722FA2168C86022681672ED
+:1058F00056721571107FD37E111D92F81AC0634540
+:1059000018D0FAF7A1FB19E000E006E0BC482160DE
+:10591000F9F7E5FE2168087792E7F9F745FF394680
+:10592000FAF704FA2168C86008680570086880F80A
+:105930000180DBE7D5769576156055622068058392
+:105940000020FDF7B7FB00202560BDE8F883704715
+:10595000F8B5A64EF17E19B906F12801C97E09B144
+:105960000C20F8BD0221F1769F4FA64D776235607D
+:10597000002438602C750094A3493A7990F8CC0043
+:10598000234631F8122031F81000104481B222462B
+:105990002046FFF746FB002818BFFFDF2C610120DF
+:1059A000AC6028756C862C8685F836403868018E88
+:1059B000491E018634830020F8BD8D4810B540682B
+:1059C0000124817E032908BF002409D00168497899
+:1059D00031B1006A8D49884284BF0024FDF766FB1F
+:1059E000204610BD8248406801680A78521C0A703F
+:1059F000016A0068C26A914204D8007D01281CBF78
+:105A000001207047002070472DE9F843784C774813
+:105A100000262060416A00680D6880F8346095F8BF
+:105A2000A610002904BF007D032850D1F9F7BCFE61
+:105A30002268526901461046FBF7FEF8002846DD51
+:105A4000216840F271274A6A13680A685B88D2F8B5
+:105A50001CC07B43CCEB4303B0FBF3F02B8E401C0C
+:105A6000184410860A68B5F89C00118E401A00B2DE
+:105A700000282CDD012082F83600B5F84E00B5F87C
+:105A80004C10DFF88481401A298E401E084487B2EA
+:105A900016E0496A097938F811100096028E95F8D7
+:105AA000CC30007D38F81330194489B20123FFF758
+:105AB000B8FA60B101280DD0022818BFFFDF06D068
+:105AC00021680868028EBA1A12B2002AE1DA26604A
+:105AD000BDE8F88320680068018E491C0186EFE765
+:105AE00070B5434E00240628756843D2DFE800F005
+:105AF0001820030E240D002000F0C3F9EC76AC76DC
+:105B00002C606C62706888B1746070BD4048356804
+:105B10000078F3F755FDEC76AC762C606C6270BDC6
+:105B2000012000F0AEF970680028EDD1FFDFEBE74F
+:105B300029680320087570BD686A29680068CA6909
+:105B40008A60418840F2E24251432A68D160B0F84D
+:105B5000E810C18290F8E6100175B0F8EA104180B3
+:105B6000B0F8EC108180B0F8EE10C18029680220F6
+:105B7000087570BDFFDF70BD70B51D4D002470B19C
+:105B8000012812D002281CBFFFDF70BD00F0D5F93C
+:105B90006868C47684760460446220B93BE000F013
+:105BA000CCF96868B0B36C6070BD686801684C700F
+:105BB000C4768476104E046044620021706802F05E
+:105BC000EDFE706880F8E24080F8E340FFF7C0FE29
+:105BD000002818BFFFDFF9F718FD0D486C6000784A
+:105BE000F3F7EEFC6C6070BDD4000020581000206C
+:105BF000CC000020DB550100DC0000200AFAFFFF8A
+:105C000021550100A810002052B50100CF821300D9
+:105C1000C4000020FFE7FFDFC5E7E7494968CA7E07
+:105C2000022A18BF70470A681378002B18BF704704
+:105C300050600968CA6A10442838C8627047DE4A52
+:105C400000B5526841B1012908BF401E04D00229A5
+:105C500016BFFFDFC01F00BD106200BDD748C07E69
+:105C600000281CBF0020704710B50720F7F782FE00
+:105C700080F0010010BD38B5CF4C2068016849782C
+:105C8000012932D001216846FBF7D3FA9DF80000C4
+:105C900042F210710002B0FBF1F201FB1201206828
+:105CA000426AC06812681144FAF740F82168C86077
+:105CB000C249226803208A4205D0118B0A2924BFD9
+:105CC0000221517203D2118B491C11835072107240
+:105CD00000231371107F92F81BC0111D947EA44500
+:105CE0000FD0BDE83840FAF7AFB9C0684FF47A7109
+:105CF000FAF71CF82168C860FCF785FF2168086185
+:105D0000D6E7D37693761360536238BD2DE9F84316
+:105D1000A94E3068416A04680D6894F8351031B1B5
+:105D2000618E2A8E914202BF407A0028FFDFF9F788
+:105D30003BFD3268526901461046FAF77DFF336831
+:105D40004FF000090028596A096808BF48460AD080
+:105D50001A68498840F2712CD26901FB0CF1C2EB40
+:105D60004101B0FBF1F02A8E618E02EB000C61451F
+:105D7000AEBF481C401C1044608694F8360030B911
+:105D8000608EB5F89C10884204BF401C6086188B5A
+:105D90008B4F401C1883B5F84E00B5F84C10401AD4
+:105DA000298E401E08441FFA80F818E03068406AC7
+:105DB000007937F81000CDF8009095F8CC1037F83E
+:105DC0001110084481B2207D0023FFF72AF9002832
+:105DD00008BFBDE8F883012818BFFFDF10D0628E2E
+:105DE000A8EB020000B20028E0DA082085F84A009B
+:105DF000012085F849002846BDE8F84301F037BA8C
+:105E0000608E401C6086EAE72DE9F047DFF8B48138
+:105E1000694C05464FF01F090027EE7E042E23D261
+:105E2000DFE806F02922021D454518BFFFDF0220EA
+:105E30002560A8762168C87E28B1C87E8A7E9042F7
+:105E400008BF20BFF6D0C87E8F7600281CBF4FF059
+:105E50000C0927600CD10F604F6227600BE0012016
+:105E6000FFF7E4FB814600E0FFDFB9F1000F02D04D
+:105E7000E87EB042D1D1E87E002818BFFFDFBDE840
+:105E8000F087F8B54C4D002601286A68516A0C6805
+:105E900044D108794A4B33F81010106890F814C0B8
+:105EA0000127BCF1030F06D0027D022A12D0007D2B
+:105EB000012823D032E0066110688660009794F8CC
+:105EC000CC00B4F89C2033F810000023084481B2C1
+:105ED00003201EE0B4F8AE200261009794F8CC00D5
+:105EE000B4F89C2033F810000023084481B202204B
+:105EF000FFF797F8696809680F750CE0009794F848
+:105F0000CC00B4F89C2033F810000023084481B280
+:105F10000120FFF786F8002818BFFFDFF9F775FBAF
+:105F200029480078F3F74CFB686806830268218EE5
+:105F30005186006880F83660F8BD38B51E4C0020E8
+:105F40000546616809684A78002A18BF4D702AD151
+:105F5000097861B101216846FBF78FF99DF80000CF
+:105F600042F210710002B0FBF1F201FB1200626814
+:105F7000516A09680144D068F9F7D8FE6268D060B8
+:105F8000157103205072107FD37E111D92F81AC034
+:105F9000634502D0FAF758F803E0D5769576156098
+:105FA000556260680583F9F730FB07480078BDE863
+:105FB0003840F3F705BB0000CC0000208010002023
+:105FC00052B5010058100020C400002010B584B064
+:105FD00004466846FCF71BFD002808BFFFDF009859
+:105FE00003F09DF80321009803F0B3F800980178BE
+:105FF00021F010010170214603F00EF90D2C7CD226
+:10600000DFE804F03122075CABABAC159AABACAC6B
+:106010008100FE48806890F8B510009803F07BF985
+:10602000FCF708FD00281CBF04B010BD81E0F74854
+:10603000806890F89110009803F0BDF9FCF7FAFC25
+:10604000002808BFFFDFA6E0F0488068D0F8C00055
+:10605000411C009803F050F9FCF7ECFC00281CBF31
+:1060600004B010BD65E0E94CA068D0F8BC008179AF
+:10607000009803F015F9A068D0F8BC0001890098D9
+:1060800003F007F9A068D0F8BC004189009803F03C
+:10609000EBF8A068D0F8BC008189009803F0EBF819
+:1060A000A068D0F8BC00C189009803F0EBF8FCF7B9
+:1060B000C1FC00281CBF04B010BD3AE0D34CA0685E
+:1060C000D0F8BC00011D009803F029F9A068D0F8B1
+:1060D000BC0000F10C01009803F02BF9A068D0F887
+:1060E000BC0000F11E01009803F029F9A06800F13E
+:1060F0008801009803F031F900E02EE0FCF79AFCEB
+:1061000000283CD145E0C14C60690178009803F05B
+:106110003CF960698188009803F039F96069418829
+:10612000009803F038F9FCF785FC00281CBF04B088
+:1061300010BDFFDF04B010BD0020029003909DF859
+:10614000080002A940F001008DF80800009803F053
+:1061500034F9FCF76FFC90B91BE0FFDFFCF76AFC39
+:10616000002808BFFFDF0C2C04BF04B010BD072CB3
+:1061700011D0012C19BF002C022C04B010BD00213D
+:10618000A2488068A0F85210012180F8561004B08F
+:1061900010BDFFDFF3E79D4900208968A1F8580092
+:1061A00004B010BD2DE9F843984D04464FF00006A9
+:1061B0006878084368702846A988806811F0200F25
+:1061C00018BFA0F84C6004D1B0F84C20521CA0F8C5
+:1061D0004C2011F0600F4FF0010707D090F83E10EF
+:1061E00021B980F83E700121FEF729FD4FF0080823
+:1061F000002C40F018826878002840F01681287939
+:1062000010F0040F0DD0A86890F83B00052808BFD7
+:10621000FFDFA86890F83D10022904BF2F7080F8B6
+:106220003D60287910F0020F00F0CD8068780028DA
+:1062300040F0C980E868C0780D2880F0C380DFE8AE
+:1062400000F04333076FC1C1851823C15264900029
+:10625000A8680023012190F83D20303002F0C3FDF2
+:1062600000283FD1A868032180F83D1080F85660CF
+:106270008DE0A8680023194690F83C20303002F0E9
+:10628000B2FD00287ED19EE0A8680023194690F850
+:106290003B20303002F0A7FD002808BFFFDF0920B7
+:1062A000A96881F83B008EE0A8680023194690F8A1
+:1062B0003B20303002F097FD002808BFFFDF0720A9
+:1062C000A96881F83B007EE0A8680023194690F891
+:1062D0003B20303002F087FD002808BFFFDFA868B0
+:1062E00080F83B806FE0A8680023194690F83B20B7
+:1062F000303002F078FD002808BFFFDFA8680A21CF
+:1063000080F85B7080F83B105DE0A86890F83B0077
+:106310000D2818BFFFDFA8680C2180F85C7012E020
+:10632000A8680023194690F83B20303002F05BFD4E
+:1063300028B9A86890F85C00002808BFFFDFA868AB
+:106340000E2180F85B7080F83B103CE0A86890F864
+:106350003B00132818BFFFDF1520A96881F83B0018
+:1063600031E0A868D0F8BC1003884A889A4204BF7C
+:10637000097804290ED0A8680023194690F83C201B
+:10638000303000E002E002F02EFDE0B1A86880F8B5
+:106390005A6018E090F83B2000231946303002F094
+:1063A00022FD002808BFFFDFA86890F85E1011F0FA
+:1063B000020F0FBF80F83B7080F85660D0F8BC0029
+:1063C0000670D8E7FFDF287910F0080F0AD0687848
+:1063D00040B9A86890F83D10032903D10221297023
+:1063E00080F83D6000F0E2FBA87810F0080F19D0AB
+:1063F000A8680023052190F83B20303002F0F3FC20
+:1064000070B185F80180A86802E00000E400002077
+:10641000D0F8D01008780B2808BF0020087001E0E1
+:1064200002F029F8A86800F046FB6846FCF7EFFA8E
+:10643000002800F0F8806878002840F0F480A86810
+:106440000023012190F83D20303002F0CCFC0028E0
+:1064500040F0E980A86890F8B410002918BF022025
+:1064600026D190F83B200C2A0ED00D2A08BF0B2015
+:106470001ED0132A08BF06201AD000230421303072
+:1064800002F0B1FCB8B1CEE0FAF7F6FE0C284DD31D
+:10649000A8680821D0F8BC001E30FAF7EEFE28B13B
+:1064A000A86804218830FAF7E8FE00B9FFDF03206E
+:1064B000FFF78CFDB7E0A86890F83C10012927D0C1
+:1064C000052920D0D0F8BC100A7882B34988028808
+:1064D000914261D190F83B2000231946303002F000
+:1064E00082FC20B3A868D0F8BC100978022908BF44
+:1064F000002026D003291BD004293AD0052908BF43
+:1065000008201ED048E00720FFF760FDA8680BE0D8
+:106510000C20FFF75BFDA868A0F8586090F85E10AB
+:1065200041F0010180F85E1080F83C607BE033E0D0
+:1065300090F83F1041B190F84000002808BFFFDFFD
+:106540000A20FFF743FD27E0FAF796FE0C2823D335
+:10655000A8680821D0F8BC001E30FAF78EFE28B1DA
+:10656000A86804218830FAF788FE00B9FFDF03200D
+:10657000E7E790F85E0010F0030F0DD10C20FFF755
+:1065800025FDA868A0F8526080F8567090F85E105B
+:1065900041F0010180F85E106846FCF738FAE0B37C
+:1065A000A8680023194690F83B20303002F01BFC0D
+:1065B00098B3A86890F8C41079B3A969097861BB49
+:1065C000018E0A292FD900F108010522E86904F09B
+:1065D00005FC0028A86808BF80F8C46023D0D0F864
+:1065E000C000017851B1411C0522E86904F0F6FBB6
+:1065F00098B9A868D0F8C000007830B9A868E969EF
+:10660000D0F8C000401C04F0D4FDA868D0F8C00049
+:106610000178491C0170012000E004E0FFF7D6FC7E
+:10662000A86880F8C460A868A14600F1300490F81A
+:10663000B40030B9627B00230121204602F0D3FB75
+:1066400010B1208C401C20843D21B9F1000F18D1DD
+:106650002878022808BF16200ED0012804BFA86899
+:1066600090F8B60008D06878B0B110F0140F1CBFD5
+:106670001E20A07602D005E0A07603E010F0080FFF
+:1066800002D0A17667763AE010F0030F08BFFFDF73
+:106690002A20A076677632E094F8260028B1608C34
+:1066A000411C6184A18C884213D294F82A0028B13D
+:1066B000208D411C2185A18C88420AD2208CE18B3F
+:1066C000884203D3AA6892F8B42012B9A28C9042EF
+:1066D00003D32220A076677611E0A07B0028A08B50
+:1066E00005D0884228BF84F81A80CBD205E006285E
+:1066F00003D33E20A076677601E0607E40B1E6726B
+:106700002673A673A868BDE8F8430221FEF797BA7E
+:10671000A868BDE8F8430021FEF791BAFE494A781F
+:106720008B781A430ED101280AD0087910F0040F93
+:1067300004D0886890F83D00022803D001207047FB
+:10674000FEF771BA0020704770B5F34C05460E464F
+:10675000A0882843A08015F0020F04D015F0010F87
+:1067600018BFFFDFE66015F0010F18BF266115F0B6
+:10677000020F13D0304602F075FD062802D00B2818
+:1067800030D00BE0A06890F83B10132906D100210F
+:10679000C0E91C115FF0010180F8401015F0800F76
+:1067A0001CBF0820A07015F4806F08BF70BDA168E1
+:1067B000088E89880844801D85B2304602F052FD5B
+:1067C000012817D0304602F04DFD002818BF70BDDB
+:1067D000A0682946D0F8BC0085803046BDE87040EE
+:1067E00002F062BDA06890F83B100D2908BF00219F
+:1067F000D4D1D1E7A0682946A0F8C6503046BDE8FC
+:10680000704002F081BDF8B5C34C00260546A0607B
+:10681000A6806670A67026700088FCF7F5F8A06860
+:106820000088FCF717F9B5F8A000A168401C82B2F7
+:1068300001F1300002F0FDF9002818BFFFDFA5F8D4
+:10684000A060A06890F8561031B1B0F85210B0F8BE
+:106850005420914228BFF8BD90F85A1031B1B0F8D9
+:106860005810B0F85420914228BFF8BDB0F850201D
+:10687000B0F84E108A4228BFF8BD90F83E20B0F81C
+:106880004C00CAB1884228BFF8BDA4480090A44B70
+:10689000A44A2946304601F066FCA0680023052181
+:1068A00090F83B20303002F09EFA002808BFF8BD77
+:1068B000BDE8F84001F053BC0628E6D3F8BD964881
+:1068C000806890F8561029B1B0F85210B0F85420F2
+:1068D000914219D290F85A1029B1B0F85810B0F876
+:1068E0005420914210D2B0F85020B0F84E108A4295
+:1068F0000AD290F83E20B0F84C001AB1884203D278
+:1069000001F08BBD0628FBD3002001464AE42DE9A7
+:10691000F0410C4607461D461646D8212046DDF8B4
+:10692000188004F020FB2780C4F8D080C4E92F65CC
+:10693000BDE8F081F7F7A4B970B50C4615460621FD
+:10694000F7F77BF8002808BF70BDD0F8D0100A78A0
+:106950000021072A1ED00C2A2FD00B2A3BD0062A52
+:1069600049D090F8C820002A04BF002070BD617093
+:106970001222227090F8C82052B100BF80F8C810CF
+:10698000D0F8CA20C4F8022090F8C820002AF5D117
+:10699000012070BD002DFBD1617007222270D0F85C
+:1069A000D0205368C4F802309368C4F80630928946
+:1069B0006281D0F8D0000170EAE7002DE8D1617063
+:1069C0000C222270D0F8D0205268C4F80220D0F8EF
+:1069D000D0000170DCE7002DDAD161700B2222704B
+:1069E000D0F8D0205368C4F802301289E280D0F881
+:1069F000D0000170CCE7002DCAD161700622227050
+:106A0000D0F8D0205368D2F808C0D268C4F8023059
+:106A1000C4F806C0C4F80A20D0F8D0000170B7E767
+:106A2000002070473C494861704710B50446B0F8F3
+:106A3000A000401CA4F8A000B4F84C00401CA4F82E
+:106A40004C0094F8560020B1B4F85200401CA4F851
+:106A5000520094F85A0020B1B4F85800401CA4F831
+:106A6000580094F8B40040B994F83D200023012167
+:106A700004F1300002F0B7F920B1B4F85000401C26
+:106A8000A4F85000204600F016F8002010BD224A5D
+:106A9000C2E906017047B0F84C1090F83E20091D7D
+:106AA0002AB1B0F84E00814203D301207047062975
+:106AB000FBD20020704770B5044690F83B000025DB
+:106AC000072821D1208EB4F8C610401C884218BF78
+:106AD00070BDD4F8C000411C04F1080004F069FB4B
+:106AE0000221204602F00CF884F83B50012084F883
+:106AF0006600D4F8C0000078002808BFFFDFD4F893
+:106B0000C0000178491E017094F83B00082818BFA6
+:106B100070BD208E08E00000E4000020A5610100A7
+:106B20001D67010049670100D4F8BC10401C89882A
+:106B3000884218BF70BDD4F8D0000178002918BF72
+:106B4000FFDF1ED12188C180D4F8BC00D4F8D0105A
+:106B500040890881D4F8BC00D4F8D01080894881DD
+:106B6000D4F8BC00D4F8D010C0898881D4F8D00003
+:106B70000571D4F8D01007200870D4F8D010208800
+:106B800048800121204601F0BBFF03212046FEF78B
+:106B900056F8D4F8BC0021884088884218BFFFDF2F
+:106BA000D4F8BC00057084F83B5070BDF0B5FF4CC4
+:106BB0008DB0207910F0010F04BF0DB0F0BD206939
+:106BC00000230521C578A06890F83B20303002F002
+:106BD0000AF9002818BF022D0CD00B2D18BF042D68
+:106BE00008D0052D1CBF062D0D2D03D0607840F078
+:106BF00008006070607800281CBF0DB0F0BD2069EF
+:106C0000C078801E0C2880F0D881DFE800F006FDF7
+:106C10002B4BD2FCFDFBFD21FA96A068002301213D
+:106C200090F83D20303002F0DEF8002840F0E3819B
+:106C3000206902F072FBA16881F8B600022081F899
+:106C40003D00002081F85A0081F8560000F0D3B9C9
+:106C5000A06890F83B100A2929D1002180F83F1044
+:106C60000D2166E0A06890F83B100E291FD1D0F8E6
+:106C7000BC1000884988814218BFFFDFA068D0F8A7
+:106C8000BC0000F12601206902F074FBA06800F14D
+:106C90008C01206902F076FBA168112081F83B008D
+:106CA00000F0A9B9A66896F83B00112803D002208D
+:106CB000607000F0A0B9D6F8BC10102501F10E0CE0
+:106CC00000210DF1FF3208206B1A6344401E13F8B7
+:106CD000017C577013F8023C02F8023F01F10201F7
+:106CE000F2D1D6F8BC10102601F11E0300210822B3
+:106CF0000DF10F00A6EB010C9C44891C1CF8015CF3
+:106D000045701CF802CC00F802CF521EF2D1684642
+:106D100003F030F808ADA06895E80E1000F1780592
+:106D200085E80E100021C0E91A11012180F83F10FA
+:106D3000132180F83B1000F05EB9A16891F83B0088
+:106D4000112812BF0E2891F85C000028AFD12069ED
+:106D500002F02FFBA168002581F8900081F85B50BC
+:106D600081F85650D1F8BC0009884088884218BF85
+:106D7000FFDFA068D0F8BC100D70D0F8D0100A78F2
+:106D8000002A18BFFFDF40F014810288CA80D0F8C3
+:106D9000D02090F890101171D0F8D0100D72D0F86A
+:106DA000D0200B2111700188D0F8D000418000F074
+:106DB00000B9A06890F83B10152918BF022040F0D8
+:106DC0000981002580F85B5080F85650D0F8BC103F
+:106DD00000884988814218BFFFDFA068D0F8BC1046
+:106DE0000D70D0F8D0100A78002A18BFFFDF40F0ED
+:106DF000E08090F85C20A2B180F85C500288CA80E4
+:106E000003E020E08BE089E0D7E0D0F8D0100D71EE
+:106E1000D0F8D0200C2111700188D0F8D00041802A
+:106E2000C7E00288CA80D0F8D0100D71D0F8D02009
+:106E300001211172D0F8D0200B2111700188D0F8F7
+:106E4000D0004180B5E0A0680023194690F83C20AE
+:106E5000303001F0C8FF48B9A0680023072190F83E
+:106E60003B20303001F0BFFF00287DD06078002843
+:106E700054D1A06890F85E0010F0020F17D120697D
+:106E800002F08DFAA16881F85F00206902F089FAAA
+:106E9000A168A1F86000206902F086FAA168A1F853
+:106EA000620091F85E0040F0020081F85E00A06888
+:106EB00090F85E1011F0010F15D190F83C200023DE
+:106EC0001946303001F08FFF002808BFFFDF012195
+:106ED000A068042280F83C1080F8B82080F85A108E
+:106EE0000021A0F85810A06890F83B10012904D1A7
+:106EF000002180F83B1080F85610D0F8BC200388A1
+:106F00005188994204BF1178042974D1002111706D
+:106F100090F83B20002A08BF80F856106BE0A0686C
+:106F20000023062190F83B20303001F05CFFD8B1FF
+:106F3000607800285FD16946206902F04DFA9DF81B
+:106F4000000010F001008DF8000014BF01200020A7
+:106F5000A168002581F86400A06880F85650D0F838
+:106F6000BC100088498800E033E0814218BFFFDF91
+:106F7000A068D0F8BC100D70D0F8D0100A78002AA4
+:106F800018BFFFDF15D10288CA80D0F8D0100D716C
+:106F9000DDE90013D0F8D0209160D360D0F8D02084
+:106FA000062111700188D0F8D00001E0E400002033
+:106FB0004180A06880F83B501DE0A068002319467E
+:106FC00090F83C20303001F00EFF10B1607818B11D
+:106FD00011E0012060700EE0206902F043F9A16821
+:106FE00081F89100052081F83C000020A1F85800AC
+:106FF000012081F85A00A068D0E91C12491C42F116
+:107000000002C0E91C120DB0F0BD000030B585B023
+:1070100004466846FBF7FBFC002808BFFFDF00982A
+:1070200002F07DF80321009802F093F800980178AF
+:1070300021F010010170214602F0EEF8A01E0C288C
+:1070400051D2DFE800F006501E5151165042505107
+:10705000312CFD48C06890F8651021B106210098D8
+:1070600002F059F940E090F8CF10009802F053F97F
+:107070003AE0F548C06890F89110009802F09BF94A
+:1070800032E0F14DE86800F1B801009802F06DF9C6
+:10709000E86800F18C01009802F071F924E0062103
+:1070A000009802F084F91FE0E74DA8680178009885
+:1070B00002F06BF9A8688188009802F068F9A86866
+:1070C0004188009802F067F90EE0002002900390DA
+:1070D0009DF8080002A940F001008DF80800009812
+:1070E00002F075F900E0FFDFFBF7A4FC002808BF01
+:1070F000FFDF0C2C04BF05B030BD072C0DD0022CD7
+:1071000004BF05B030BD0021CF48C068A0F85810BA
+:10711000012180F85A1005B030BDCB490020C96864
+:10712000A1F8580005B030BD70B50C4605464FF4C7
+:107130009071204603F017FF2580002084F8F000AE
+:1071400084F8FC0084F8040184F8120170BDF6F79D
+:1071500097BD70B50C4615460721F6F76EFC002862
+:1071600008BF70BD90F8F0200021DAB1002D77D172
+:1071700061700722227090F8F0208AB1018480F8B3
+:10718000F010D0F8F220C4F80220D0F8F620C4F8AD
+:107190000620B0F8FA20628190F8F020002AEDD1A4
+:1071A000A1705DE090F8FC2002B3002D58D190F85A
+:1071B000FC200B2A0CD00C2A18BFFFDF50D16170C5
+:1071C0000C22227090F8FE20A2700288A2800AE0B1
+:1071D00061700B22227090F8FE20A2700288A280BB
+:1071E00090F80221A27180F8FC1039E090F8042197
+:1071F0008AB17DB961700822227002886280D0F85D
+:107200000821D0F80C316260A360B0F81021A2818F
+:1072100080F8041124E090F812214AB105BB617096
+:1072200011222270B0F81421628080F8121117E048
+:1072300090F81621002A04BF002070BD85B9617046
+:107240001222227090F8162152B100BF80F8161158
+:10725000D0F81821C4F8022090F81621002AF5D1A0
+:10726000012070BD00207047774988607047002179
+:1072700080F83B1080F83C1080F83E1090F8A60093
+:1072800010B10220FEF72CBC0320FEF729BC2DE92B
+:10729000F04F6D4C07468DB0E0680D460088F6F75C
+:1072A00044FD5FEA000B08BFFFDF60782843607091
+:1072B000A188E06811F0200F4FF000051CBFA0F876
+:1072C0004C5080F8AC5004D1B0F84C20521CA0F8BF
+:1072D0004C2011F0600F4FF002084FF0010613D060
+:1072E000E06890F83E1011B1032907D00CE080F857
+:1072F0003E6000210120FEF7F3FB05E080F83E80B0
+:1073000000210120FEF7ECFBE06890F83E10012917
+:1073100005D1A18811F4807F18BF80F83E80002F2E
+:1073200040F09B81A18811F4007F18BFA0F8C050E5
+:1073300004D1B0F8C010491CA0F8C01000F09AFBAE
+:107340000CA8FBF764FB002800F0E88060780028B8
+:1073500040F0E480E0680123194690F83D20303089
+:1073600001F041FD002849D1D4F80CC09CF8CE00B2
+:1073700038B1ACF850508CF865500220FFF746FE4B
+:10738000CCE09CF83C200B2A08BF0B201AD00ADC6A
+:10739000012A7BD0052A08BF072013D0092A08BF7D
+:1073A00009200FD005E00F2A0FD0102A20D0162A6E
+:1073B0007CD0012304210CF1300001F014FD0028E1
+:1073C0001CD187E0FFF722FEA8E0F9F755FF0C2853
+:1073D00014D3E0680821B830F9F74FFF28B1E0680E
+:1073E00004218C30F9F749FF00B9FFDF0420E9E7F9
+:1073F0009CF8D100012802D0022849D08EE09CF8E8
+:10740000FC00002841D100220CF1D2094FF01008F5
+:1074100008210DF1FF3000BFA8EB02034B44491EC9
+:1074200013F801AC80F801A013F8023C00F8023F09
+:1074300002F10202F0D10CF1B00800204FF0100C64
+:107440000DF10F01082201E004010020ACEB000364
+:107450004344801C13F8019C81F8019013F8023C0E
+:1074600001F8023F521EEED1684602F083FC0DF196
+:107470002008E06898E80E10783080E80E100520AB
+:10748000FFF7C4FDE06880F8D15047E015E00DE05B
+:107490009CF85C0000281ABF8CF8656002200D2063
+:1074A000FFF7B4FDE06880F8D15037E00620FFF721
+:1074B000ADFDE06880F85A5030E00C20FFF7A6FDE3
+:1074C000E068A0F8585090F85E1041F0010180F893
+:1074D0005E1023E0E06890F83B2090F8E210E9B1FC
+:1074E00001230021303001F07EFCB8B1E06890F853
+:1074F000E210042904BF90F85E0010F0030F0DD1D4
+:107500000C20FFF783FDE068A0F8525080F8566029
+:1075100090F85E1041F0010180F85E1000F0A1FFCC
+:107520000028E06818BFA0F8A05004D1B0F8A0105F
+:10753000491CA0F8A01000F097FF40B1E06890F857
+:10754000AC1002299CBF491C80F8AC1004D8E0683C
+:1075500090F8AC00022806D9E068A0F8A050A0F886
+:10756000A25080F8AC50E0680123002190F83C2044
+:10757000303001F038FC20B9E06890F83C00072872
+:1075800056D1E0680123002190F83B20303001F013
+:107590002AFCE8B3E0680123002190F83D20303058
+:1075A00001F021FCA0B3E06890F83E10022904BF6E
+:1075B00090F8AC0000283BD15846F5F7E8FE38B308
+:1075C000FBF76CFA20B3E068B0F89A1001292FD9C4
+:1075D00080F8A560B0F84E10B0F84C208B1E9A428F
+:1075E000AFBF0121891A491E89B2B0F8A030E288E4
+:1075F00093422FBF0122D21A521C92B2914288BFED
+:107600001146012908BF80F8A55090F8C82000E075
+:107610000EE08AB1B0F8A220B0F8CA0082422FBFB3
+:107620000120801A401C80B2814288BF014603E0DD
+:10763000E068012180F8A550E068028E114489B20B
+:10764000A0F89C1090F83E30002B18BF012B1DD0E5
+:10765000022B1CBF032BFFDF09D0A088C0F3402002
+:107660000028E06818BFA0F8AE5022D11AE090F8C8
+:107670003D30032B0DD090F83C20082A06D0B0F8FE
+:107680004E20B0F84C30D21A921E1144A0F8981037
+:10769000E3E7B0F84C30032BF8D3B0F84E101144A8
+:1076A000491CF3E7B0F8AE10B0F89E201144A0F8E2
+:1076B000AE10E06890F8CE1039B990F83D20012363
+:1076C0001946303001F08FFB38B1E068B0F8501047
+:1076D000B0F89E201144A0F850103D212FB1E06871
+:1076E00080F84A1080F8496069E02078022810D0BC
+:1076F00001281AD0607800B310F0140F14BF1E21B7
+:1077000010F0080FEBD110F0030F08BFFFDF2A21A4
+:10771000E5E7E06890F86510002914BF06211621FE
+:1077200080F84A1080F8496049E0E06890F8D0108D
+:1077300080F84A1080F8496041E0E06890F85610FF
+:1077400041B1B0F852104A1CA0F85220B0F85420B1
+:10775000914214D290F85A1041B1B0F858104A1C16
+:10776000A0F85820B0F85420914208D2B0F8502028
+:10777000B0F84E108A4208D390F8CE202AB12221C8
+:1077800080F84A1080F8496019E090F83E204AB12C
+:10779000B0F84C208A420FD3082180F84A1080F8B4
+:1077A00049600CE0B0F84C10062905D33E2180F862
+:1077B0004A1080F8496002E090F8490088B1E0681A
+:1077C00080F83B5080F83C5080F83E5090F8A6007E
+:1077D0004FF00001002814BF02200320FEF780F9BB
+:1077E00003E000210846FEF77BF9E06880F8A65028
+:1077F0000DB0BDE8F08FFE494A788B781A430DD161
+:1078000050B1087910F0080F04D0C86890F83D0016
+:10781000032803D001207047FEF7E4B8002070472A
+:107820002DE9F041F24C05460E46A0882843A08081
+:1078300015F0020F04D015F0010F18BFFFDF26610D
+:1078400015F0010F4FF000084FF001071CD0304633
+:10785000666101F007FD062802D00B280BD013E06B
+:10786000E06890F83C1012290ED10021C0E91A11ED
+:1078700080F83F7008E0E06890F83C100C2904BFE5
+:1078800080F83F8080F85C7015F0020F19D02069F5
+:1078900001F0E8FC052802D00B280BD011E0E068CD
+:1078A00090F83C1010290CD10021C0E91C1180F87F
+:1078B000407006E0E06890F83C100B2908BF80F8A3
+:1078C000408015F0800F1CBF0820A070BDE8F0813B
+:1078D0002DE9F043C64C83B00127216900250191B1
+:1078E000A5806570A5702570E06067F307080646FF
+:1078F00080F8A6700088F6F718FA5FEA000908BF5A
+:10790000FFDFE0680088FBF77FF8E0680088FBF79E
+:10791000A1F8E068B0F89A00D0B101A8FBF777F8B9
+:10792000B0B1E06890F8CE1091B190F83D200123FD
+:107930001946303001F057FA50B9E068A0F85050BD
+:1079400080F865500220FFF761FBE06880F8A550E1
+:10795000E26892F8F00028B9108C9188884288BFBC
+:10796000E08001D89088E080B2F89E00B2F8A010C4
+:10797000401E80B2014489B2A2F8A01092F8A4304F
+:10798000002B1CBFA2F8A25082F8A45004D1B2F878
+:10799000A2300344A2F8A230B2F84C300344A2F85B
+:1079A0004C30B2F89A30012B9CBF5B1CA2F89A3085
+:1079B000002818BF82F8AC5092F8A50000281CBF20
+:1079C000E08881420FD24846F5F7E1FC58B1E06803
+:1079D00090F8C81039B1B0F8A210B0F8CA008142CE
+:1079E00028BF00F044FDE06880F8A55090F83C10F6
+:1079F000062918BF072916D1018EB0F8E420891A8C
+:107A000009B200290FDB00F1E601083003F0D1FBD9
+:107A10000221E06800F0C2FFE06880F8E35080F8DF
+:107A20003C5080F86670E16801F13000B1F89E20AA
+:107A300001F0FFF8E06890F8C810002918BFA0F81E
+:107A4000A2506C4800906C4B6C4A3146404600F0A6
+:107A50008AFBE0680123052190F83C20303001F0DA
+:107A6000C2F9002818BF00F07AFB03B0BDE8F0832C
+:107A700000F0D3BC2DE9F0415D4C4FF002074FF010
+:107A80000005207910F0080F13D0607888B9E068FD
+:107A900090F83C10142905D180F85B5080F85A50BA
+:107AA00080F83C5090F83D10032904BF277080F8FF
+:107AB0003D5000F043F9A1884FF0010611F0040F8A
+:107AC00014D0607890B9E06890F83C20062A08BF8E
+:107AD00080F8E36003D0082A08BF80F8E37090F8CC
+:107AE0003D20022A04BF267080F83D5011F0020F9D
+:107AF0004FF0030754D06078002851D12069C07836
+:107B0000801E0C287CD2DFE800F006B636415718FC
+:107B1000B622B6298B4CE0680123194690F83D2027
+:107B2000303001F060F900283AD1E06880F83D700B
+:107B300080F8565080F85A509EE0E06890F83C007B
+:107B4000052818BFFFDFE06880F83C50F2E7E068E6
+:107B500090F83C00092818BFFFDF6FE0E06890F85C
+:107B60003C000B2818BFFFDFE0680C2180F85B6049
+:107B700080F83C1080E0E06890F83C000F2818BFC7
+:107B8000FFDFE068102180F85B60F1E7E06890F8C3
+:107B90003C00102818BFFFDF1220E16881F83C008C
+:107BA0006AE0E06890F83C00102818BFFFDF14205E
+:107BB000E16881F83C005FE0E06890F83C0016283E
+:107BC00018BFFFDFE06880F85B5080F85A5090F8EB
+:107BD000FC00002818BFFFDFE06890F85C1091B14E
+:107BE00080F85C500188A0F8001180F8FE5008E091
+:107BF000040100208F720100F77701002178010055
+:107C000039E00C2107E00188A0F8001180F8FE504F
+:107C100080F802610B2180F8FC1080F83C502BE0CA
+:107C2000E06890F8E21004290ED0E06801230721F3
+:107C300090F83C20303001F0D6F8E8B1E06880F8E8
+:107C40005A5080F83C5017E090F83B200123002167
+:107C5000303001F0C8F8002808BFFFDFE06890F876
+:107C60005E1011F0020F0EBF80F83B6080F8565096
+:107C700080F8E250D9E7FFDF207910F0100F09D02B
+:107C8000607838B9E06890F83C10062904BF0721F5
+:107C900080F83C10A07810F0080F10D0E0680123A5
+:107CA000052190F83C20303001F09DF828B10820E3
+:107CB0006070E06880F8FC5001E000F0DCFBE068F8
+:107CC00090F83C10082918BFBDE8F081018EB0F88B
+:107CD000E420491C914206BF61780029BDE8F0818B
+:107CE000B0F8EA104288914209D1B0F8EC208388BC
+:107CF0009A4204D1B0F8EE20C3889A420ED002888E
+:107D0000A0F8F420A0F8F610B0F8EC10A0F8F810E5
+:107D1000B0F8EE10A0F8FA1080F8F060012100F041
+:107D20003DFE00210420FDF7DBFEE06880F8E35013
+:107D300080F83C5080F83E70BDE8F08130B5FF4CD3
+:107D400083B0207910F0010F04BF03B030BD60692B
+:107D500001230521C578E06890F83C20303001F01F
+:107D600042F8002818BF022D0BD00A2D18BF0B2D8A
+:107D700007D0032D18BF062D03D0607840F008000F
+:107D80006070607800281CBF03B030BD6069C078A7
+:107D90000D2880F0AB81DFE800F0462207C8FEFE28
+:107DA000FDDBFCFEA3C0FB00E0680123194690F850
+:107DB0003D20303001F017F8002840F0B4816069B0
+:107DC00001F0ABFAE16881F8D000022081F83D00B3
+:107DD000002081F85A0081F8560000F0A4B9E0684C
+:107DE0000123002190F83C20303000F0FCFF0028F7
+:107DF00075D06078002840F09681606901F088FABB
+:107E0000E168A1F8E4000A8E801A00B247F6FE721B
+:107E10008242A8BF00285ADDE631606901F06FFA9E
+:107E20000620E1683FE0E0680123002190F83C2053
+:107E3000303000F0D8FF00285FD06078002840F094
+:107E40007281606901F037FA88B3606901F030FA35
+:107E5000E168A1F8E4000A8E801A00B247F6FE72CB
+:107E60008242A8BF002832DD606901F01BFAE16898
+:107E700081F8E600606901F010FAE168A1F8E80015
+:107E8000606901F0F5F9E168A1F8EA00606901F0C4
+:107E9000F6F9E168A1F8EC00606901F0F7F9E16832
+:107EA000A1F8EE00082081F83C0000F03CB9FFE7A3
+:107EB000E0680123002190F83C20303000F093FF6F
+:107EC00068B16078002800F01F8100F02CB92820EC
+:107ED00081F84A00012081F8490000F024B90CE043
+:107EE000E0680123002190F83C20303000F07BFF57
+:107EF00018B1607828B100F016B90120607000F068
+:107F000012B9E0680021A0F85810012180F85A1039
+:107F10000B2180F83C1000F006B9E06890F83C10A6
+:107F20000C2908BF0D214CD143E0E068012300215A
+:107F300090F83C20303000F056FF20B9E06890F80F
+:107F40005C0000287ED06078002801D101E06070DC
+:107F5000E9E0E06800210125A0F8581080F85A50A7
+:107F600000F1B001606901F0F1F9E06800F1880109
+:107F7000606901F0F6F9E06890F80401002818BF84
+:107F8000FFDFE0680188A0F8061100F5847103E0C6
+:107F90001EE087E010E0A9E0606901F0C5F9E06843
+:107FA00000F58871606901F0C7F9E06880F8045154
+:107FB0000F2180F83C10B6E0E06890F83C101229E0
+:107FC00001D00220C3E7002180F85A101621F0E703
+:107FD000E0680123002190F83C20303000F003FFDE
+:107FE00048B9E0680123072190F83B20303000F0C9
+:107FF000FAFE002826D06078002852D1E06890F878
+:108000005E0010F0020F17D1606901F0C8F9E16855
+:1080100081F85F00606901F0C4F9E168A1F86000CF
+:10802000606901F0C1F9E168A1F8620091F85E00B1
+:1080300040F0020081F85E00E06890F85E1011F0F8
+:10804000010F00E05EE015D190F83C2001230021F3
+:10805000303000F0C8FE002808BFFFDF0121E068D3
+:10806000042280F83C1080F8E32080F85A100021A8
+:10807000A0F85810E06890F83B10012904D10021C5
+:1080800080F83B1080F8561090F8E21004294AD18D
+:10809000002180F8E21090F83B20002A08BF80F809
+:1080A000561040E0E0680123002190F83C20303079
+:1080B00000F099FE30B3607818BB6946606901F042
+:1080C00081F99DF8000010F001008DF8000014BF48
+:1080D00001200020E16881F86400E0680021A0F838
+:1080E0005810012180F85A10092162E7E068012345
+:1080F000002190F83C20303000F075FE10B160781F
+:1081000010B110E0012022E7606901F0ABF8E168EE
+:1081100081F89100052081F83C000020A1F858006A
+:10812000012081F85A00E068D0E91C21521C41F17D
+:108130000001C0E91C2103B030BD00000401002093
+:10814000F9480078002818BF0C20704730B5F64C6D
+:1081500005462078002818BFFFDF657230BDF24960
+:108160000120087270472DE9F047EF4C8146DDF899
+:10817000208020781E4617460D4628B9002F1CBFC8
+:10818000002EB8F1000F00D1FFDFC4F81C80C4E955
+:108190000C95C4E9057600202072E0712071E07032
+:1081A0006071A071E14EA070608130784FF00108DD
+:1081B00005F130072888F5F7B8FDA0622888F5F7A3
+:1081C000A2FDE062FAF7BCF80120F9F7CAFDFAF760
+:1081D0000CF905F11100FAF79CF805F10D00F9F71B
+:1081E000C7FE307800280CBF03200120FAF7A5F85D
+:1081F000387EF9F7C5FE0120F9F7A2FDFAF797F8E6
+:10820000397CCB48002914BFCA49CB49016030787A
+:108210004FF0010170B10120F9F726FF7068D0F826
+:10822000A800FAF79BF800BF84F80080BDE8F0478B
+:10823000FAF78EB80020F9F717FFF5E72DE9F047B8
+:10824000DFF8E89282B0484600264068012700F136
+:1082500030041B20ADF8000060794FF00208A9F14E
+:10826000300570B301285AD002285CD0032818BF0B
+:10827000FFDF62D0286A0823017821F0080101702D
+:10828000A27903EAC202114321F004010170E279EC
+:10829000042303EA8202114321F01001017094F8D3
+:1082A00005A0A86AF5F781F80646FAF7F7FBBAF1D8
+:1082B000020F49D0BAF1010F49D0BAF1030F49D0EA
+:1082C0004BE0FFE79D48FAF7C8FB40B1296AAF7061
+:1082D0006A694FF48060904703206071CAE701AA81
+:1082E0006946A86AF4F752FF286210B194F82B107F
+:1082F00021B19248FAF785FB6771BBE79DF804103E
+:1083000021B906808670012100F023FFBDF800002E
+:10831000C1B2286A01F065F884F80580AAE78748A9
+:10832000FAF76FFBA6E701AA6946A86AF4F72EFFE1
+:108330002862002808BFFFDF9CE78048FAF78DFB22
+:10834000002808BFFFDF95E7B04306D103E0B04344
+:1083500003D100E00EB1012100E00021286A02787B
+:1083600042EA01110170E17B00291CBF61790129FA
+:1083700026D004F14801724891E80E1000F1480639
+:1083800086E80E10A16DC0F86110E16DC0F86510AF
+:108390002230F9F7E0FF99F8000000280CBF012116
+:1083A000002168480176D4E90E12C0E90412A0F158
+:1083B00026012A6AF9F711FC0020F9F71FFC03E0F7
+:1083C000F9F7C9FFF9F741FC99F8000028B1286ACC
+:1083D000007810F0100F05D00CE001210846FAF7E4
+:1083E0007CF80AE05848007810F0100F04BF287994
+:1083F000002802D0A8780028EFD06879002804BFB0
+:108400006F71F9F7D0FF286A0188A9818078A87375
+:1084100085F8008002B0BDE8F087434810B50078C9
+:10842000012818BFFFDFF9F78BFF40480178446847
+:1084300011B9FFF703FF01E000F0BCF994F8280040
+:10844000012818BF10BDBDE81040FAF723B8364820
+:1084500010B50078032818BFFFDFBDE8104000F01A
+:10846000F4B93148407970472F48007970472E4958
+:108470000120887170472DE9F0412C482A4D0126D2
+:1084800001784068002700F13004686A417801F003
+:108490001F08E96A02F09AF868B1012821D0022881
+:1084A00034D003281CBFFFDFBDE8F081E86ABDE8D7
+:1084B000F041F5F7E4B801224146E86AF4F7FAFF23
+:1084C000D4E91010491C40F10000C4E91010E07913
+:1084D000012814BFE671E771687ABDE8F041F1F751
+:1084E0006FB800224146E86AF4F7E4FFD4E91001CE
+:1084F000401C41F10001C4E91001E079012802D1DA
+:10850000E771BDE8F081E671BDE8F081E86AF5F752
+:10851000B6F8D4E91010491C40F10000C4E910106D
+:10852000E0790128EFD1EBE71C0100204C0100208D
+:10853000181500401F0003021B0003023C0100202D
+:10854000F8100020401100202B0100202DE9F041FF
+:10855000F04F4FF000083846A7F13004406801267C
+:1085600000F130052078022818BFFFDFA87850B14D
+:1085700085F80280A67062694146042090473878E9
+:10858000002818BF2E71206A0321007831EA00000C
+:1085900004BFE878002805D1EE70216AA6706269F0
+:1085A000022090470121002000F072F918B1BDE8C7
+:1085B000F04100F04AB9BDE8F04100F0FBB82DE908
+:1085C000F05FD44E82463046A6F1300540684FF049
+:1085D000000800F1300928780127032818BFFFDFC1
+:1085E0006889BAF1000F40F40070688104BF40F060
+:1085F0004000688100F0CE80F9F73DFB98B999F80A
+:10860000100080B1686A417811F01F0F0BD000781C
+:1086100099F80710C0F3C000884204D1EF70BDE89C
+:10862000F05F00F012B9686A0188A5F80F10807831
+:108630006874688940F02000688185F8048070685B
+:1086400000F1300B044690F82800012813D1F9F707
+:1086500017FF5946204600F09BFB60B13078002898
+:1086600070680CBFC83000F58B70218841809BF882
+:10867000081001710770686A99F806100078C0F355
+:108680008000884233D0706800F1300490F83500E3
+:1086900048B3022844D000BF84F80580307838B150
+:1086A0002079414620B12171AF706A69102090474E
+:1086B000E07890B184F80380FAF7DEF9002808BF6B
+:1086C000FFDF0820AF706A6900219047D4E90E10DF
+:1086D000491C40F10000C4E90E10A07901280CBF2C
+:1086E00084F80680A771688940F480706881686AA0
+:1086F00099F807300178C1F3C0029A424AD17268F2
+:1087000001F0030102F13004012918BF02292ED023
+:1087100003291CBFE87940F0040012D0E87139E069
+:10872000A86AF4F76DFD002808BFFFDFD4E90E103A
+:10873000491C40F10000C4E90E10687AF0F740FFD0
+:10874000AAE700F02AFD70B1A770696AAF706A6984
+:1087500038469047E079012803D100BF84F80780AC
+:1087600018E0E77116E0E87940F01000D6E74078AD
+:1087700010F01F0F17D0697861B900F01F001B2897
+:10878000F1D8287A20B180206A690021904701E061
+:10879000FFF771FE5146012000F07AF838B1BDE8CC
+:1087A000F05F00F052B8E0790128DAD1D6E7BDE8F1
+:1087B000F05F43E570B5584C1B21E06AF4F723FEE7
+:1087C000002101226062002811BF6170627053486D
+:1087D0006062504E3078706800F1300590F84000CB
+:1087E00038B305F148014D4891E80E1000F1480EEC
+:1087F0008EE80E10A96DC0F86110E96DC0F8651023
+:108800002230F9F7A8FD307800280CBF01200020A5
+:1088100080F0010142480176D5E91012C0E9041246
+:10882000A0F12602616AF9F7D8F90120F9F7E6F913
+:1088300004E0606AF9F78FFDF9F707FA01210020DB
+:10884000F9F74BFE0320207070BD70B5314900254B
+:108850004C68F9F7E7FDF9F7D9FDF9F7FBFCF9F7F3
+:108860005EFDF9F7F2F9F9F7CDFDF9F771FD94F82E
+:108870002800012808BFF9F703FE274C0021626990
+:1088800060899047E269E179E0789047257070BD92
+:1088900070B5214C0546002908BF012D05D120796E
+:1088A000401CC0B22071012831D8A16928468847F0
+:1088B00000282CD0A1791B4841B1012D01BF41787E
+:1088C00011F01F0F017811F0100F20D0E179F1B9EC
+:1088D00010490978002918BF002102D0294304D08B
+:1088E00013E0012D18BF0121F8D10F49097811F0CB
+:1088F000100F04BF007810F0100F08D0A07830B926
+:10890000607810B111F0100F01D0002070BD01206F
+:1089100070BD00004C0100201C010020F810002058
+:10892000401100202B0100202801002010B50A7BF7
+:1089300002F01F020A73002282758B181B7A03F063
+:10894000010C5B0803F00104A4445B0803F001047C
+:10895000A4445B0803F00104A4445B0803F0010491
+:1089600064444FEA530C0CF0010323444FEA5C0CBF
+:108970000CF00104234403EB5C0300EB020C521CDB
+:108980008CF8113090F816C0D2B263448375052A72
+:10899000D3D3D8B2252888BFFFDF10BD0A4610B454
+:1089A0000021032A0DD04FF4FA4C002A60D0012A8E
+:1089B0007ED0022A1CBF10BC7047014610BC30306C
+:1089C000B4E7018680F8361080F8371080F83B1045
+:1089D00080F83C1080F83D1080F83E1080F832108E
+:1089E00080F8331080F8341080F8351080F8491082
+:1089F000A0F84C10A0F8521080F85610A0F85810AB
+:108A000080F85A1080F8471080F8481080F83F101E
+:108A100080F8401080F85B1080F85C1080F85E10E1
+:108A2000012280F86420A0F8501080F86610A0F8A9
+:108A30009810A0F89A10A0F89C10A0F89E10A0F82A
+:108A4000A010A0F8A21080F8A510A0F8AE1080F831
+:108A5000AC10A0F8C010A0F8C21080F82810018453
+:108A600080F8C81080F8CE1080F8D11010BC704784
+:108A7000A0F8AE1080F8A6104288C488A0F84C1068
+:108A8000B0F8501000F13003514391FBF2F1A0F81F
+:108A90005010E100B1FBF2F1491C89B201FB02F474
+:108AA000A0F84E10B4F5C84FC4BF491ED98300E0EA
+:108AB00004E0BCFBF2F1491C99847EE7A0F8AE10FB
+:108AC00000F130024488B0F8EA30B0F8EE0091834B
+:108AD000118CC0006143B0FBF3F091FBF3F1401C3B
+:108AE000118480B200FB03F1D083B1F5C84FC4BF3D
+:108AF000401ED083BCFBF3F0401C908410BC704738
+:108B00000A4610B40021032A0DD04FF4FA4C002A73
+:108B10004FD0012A6DD0022A1CBF10BC70470146FD
+:108B200010BC303002E7018680F8361080F837102C
+:108B300080F83B1080F83C1080F83D1080F83E1023
+:108B400080F8321080F8331080F8341080F8351037
+:108B500080F84910A0F84C10A0F8521080F8561078
+:108B6000A0F8581080F85A1080F8471080F8481084
+:108B700080F83F1080F8401080F85B1080F85C109F
+:108B800080F85E10012280F86420A0F8501080F870
+:108B90006610A0F8A01080F8A21080F89810C0F815
+:108BA0009C1080F8281080F8B41080F8C41010BC15
+:108BB00070474288C488A0F84C10B0F8501000F1FB
+:108BC0003003514391FBF2F1A0F85010E100B1FBEA
+:108BD000F2F1491C89B201FB02F4A0F84E10B4F581
+:108BE000C84FC4BF491ED983BCFBF2F1491C99840C
+:108BF00095E7D0F8BC4000F1300243886089E489F1
+:108C00009183118C594391FBF0F11184E100B1FB88
+:108C1000F0F1491C89B201FB00F3D183B3F5C84FD1
+:108C2000C4BF491ED183BCFBF0F0401C908410BC33
+:108C30007047837D0BB1252B01D912207047002A84
+:108C400004BF0020704770B490F817C00C7E894DA7
+:108C500004FB02C22C464FF0000CE2FB054C4FEA2D
+:108C60001C1C6FF024040CFB0422D2B201EBD20CCA
+:108C7000C27502F007059CF808C0012404FA05F546
+:108C80001CEA050F18BF02762CD1B2FBF3FC03FBE4
+:108C90001C22521CD2B24FF0000C00BF00EB0C03A0
+:108CA0005B7C93423CBFD21AD2B20ED301EB0C05CF
+:108CB00000232D7A04FA03F635421CBF521ED2B2AD
+:108CC0006AB15B1CDBB2082BF4D30CF1010303F097
+:108CD000FF0CBCF1050FE1D370BC1F20704703EB04
+:108CE000CC01017670BC0020704730B50D460446BB
+:108CF000072988BFFFDFE07805F0070100F050008A
+:108D0000084340F08800E070A07800F0A70040F031
+:108D10001800A070607800F05E0040F020006070E5
+:108D2000207800F0BC0040F04000207030BD017998
+:108D300031F01F0113BF002000221146704710B40C
+:108D4000435C491C03F0010C5B0803F00104A444DC
+:108D50005B0803F00104A4445B0803F00104A4448D
+:108D60005B0803F00104A4445B0803F001045B0802
+:108D7000A44403F00104A4440CEB53031A44D2B2FC
+:108D80000529DDDB012A8CBF0120002010BC7047C3
+:108D900038B505460C466846F9F787FB002808BF3A
+:108DA00038BD9DF90020227294F909100020511A53
+:108DB00048BF494295F829308B42C8BF38BDFF2BC8
+:108DC00008BF38BDA17A491CC9B2A17295F82A30F2
+:108DD000994203D8617A7F2918BF38BD627200209A
+:108DE000A072012038BD10B4A2F10B0C08293AD2B0
+:108DF000DFE801F004060B10131D333782B332E0B5
+:108E0000022A18BF032A31D02DE0072A18BF062AEC
+:108E10002CD028E0082A29D025E01BB1BCF10B0F8B
+:108E200024D920E0A2F10A000B281FD91BE01BB1B6
+:108E3000BCF10B0F1AD916E00D2A18BF0C2A15D059
+:108E400090F82C0020B10D2A0DD3152A0ED90AE076
+:108E5000112A08D3152A09D905E0092A06D002E00B
+:108E600004E0012A02D010BC0020704710BC012091
+:108E70007047000053E4B36E282102F052B830B5B9
+:108E80000546007801F00F0220F00F001043287013
+:108E900007290BD2DFE801F00406040604080400E9
+:108EA000062405E00C2403E0222401E00024FFDF77
+:108EB000687820F03F002043687030BD007800F0F3
+:108EC0000F0070470A68C0F803208988A0F80710CF
+:108ED0007047D0F803200A60B0F807008880704718
+:108EE0000A68C0F809208988A0F80D107047027838
+:108EF000402322F0400203EA8111114301707047C0
+:108F00000078C0F3801070470278802322F080023E
+:108F100003EAC111114301707047D0F80320C1F872
+:108F20000920B0F80720A1F80D200A7822F080026D
+:108F30000A700078800942EAC0100870704770B566
+:108F400015460E4604461F2A88BFFFDF2A463146D3
+:108F500004F1090001F06EFF6078A91D20F03F00C8
+:108F600001F03F010843607070BD70B50546407860
+:108F70000E4600F03F04062C38BFFFDFA01FC4B22E
+:108F80001F2C88BF1F24224605F10901304601F03D
+:108F900051FF204670BD70B515460E4604461F2A87
+:108FA00088BFFFDF2A46314604F1090001F042FF85
+:108FB0006078A91D20F03F0001F03F010843607078
+:108FC00070BD70B5054640780E4600F03F04062C93
+:108FD00038BFFFDFA01FC4B21F2C88BFFFDF2246AF
+:108FE00005F10901304601F025FF204670BD0968F2
+:108FF000C0F80F1070470A88A0F8132089784175CF
+:1090000070474176090A81767047C176090A01776F
+:1090100070474177090A81777047C175090A01765F
+:1090200070478175704790F8242001F01F0122F0ED
+:109030001F02114380F82410704790F82420E02389
+:1090400022F0E00203EA4111114380F82410704736
+:109050001F3002F0AEB84178007801F03F0110F007
+:109060000F0006D0012808D0022809D006280BD00E
+:109070000FE0881F1F280AD90BE00C2909D106E050
+:10908000881F1F2803D904E0881F1F2801D801204A
+:109090007047002070474178007801F03F0100F0F0
+:1090A0000F00042805D1062903D325299CBF0120E0
+:1090B00070470020704710B4017801F00F010329B8
+:1090C00022D0052925D14478B0F81910B0F81BC07A
+:1090D000B0F81730827D04F03F04222C19D1062904
+:1090E00017D3B1F5486F98BFBCF5FA7F11D282B1A2
+:1090F000082A98BF8A420CD28B429CBFB0F81D0050
+:10910000B0F5486F05D807E0407800F03F000C2824
+:1091100002D010BC0020704710BC012070472221F3
+:1091200001F0FFBE00B5027801F0030322F0030254
+:109130001A4302704278012922F01F02427014BFC4
+:10914000022900BD032912BFFFDF42F00101417077
+:1091500000BD01F0030300B5027822F003021A43B8
+:1091600002704278012922F01F02427014BF0229C6
+:1091700000BD032912BFFFDF42F00101417000BDB5
+:10918000007800F0030070470278102322F01002EC
+:1091900003EA01111143017070474178C07801F072
+:1091A0001F010E2832D2DFE800F0070A0D10131657
+:1091B000191C1F2225282B2E0C2929D02AE008292A
+:1091C00026D027E0022923D024E0172920D021E04F
+:1091D0000D291DD01EE001291AD01BE0012917D04E
+:1091E00018E0022914D015E0092911D012E009294C
+:1091F0000ED00FE001290BD00CE0012908D009E0C6
+:10920000062905D006E0022902D003E01B2901D877
+:10921000012070470020704730B50546C1700E2907
+:1092200018D2DFE801F007090B0D0F11110B131312
+:109230001111150B0C240FE008240DE002240BE0A3
+:10924000172409E00D2407E0012405E0092403E0C8
+:10925000062401E00024FFDF687820F01F0020438F
+:10926000687030BDC0787047C171090A01727047DB
+:10927000B0F8070070474172090A81727047B0F870
+:1092800009007047C172090A01737047B0F80B00FA
+:1092900070474171090A81717047B0F80500704745
+:1092A00001717047007970474173090A81737047F3
+:1092B000B0F80D00704730B4B0F80720504DB0F84A
+:1092C00009C0B0F805300179941F2D1998BFBCF57D
+:1092D000FA7F0ED269B1082998BF914209D2934210
+:1092E0009FBFB0F80B00B0F5486F012030BC98BFAD
+:1092F0007047002030BC7047001D01F05ABF021DAE
+:109300000846114601F055BF4172090A8172704743
+:10931000B0F80900704701717047007970470A681A
+:10932000426049688160704742680A6080684860AE
+:1093300070470988818170478089088070470A6872
+:10934000C0F80E204968C0F812107047D0F80E20FF
+:109350000A60D0F81200486070470968C0F816101B
+:109360007047D0F81600086070470A684260496884
+:109370008160704742680A60806848607047096889
+:10938000C1607047C06808607047017170474171E3
+:10939000090A81717047C171090A01727047007929
+:1093A0007047B0F805007047B0F8070070470171CA
+:1093B000704700797047017170470A6842604968D8
+:1093C0008160704742680A608068486070470A6838
+:1093D000426049688160704742680A6080684860FE
+:1093E000704730B50C4605461B2988BFFFDF6878FB
+:1093F00004F01F0120F01F000843687030BD00001A
+:1094000086F3FFFF70B50446C2F11005281901F07C
+:1094100011FD15F0FF0108D0491EC9B2802060542B
+:109420002046BDE8704001F07CBD70BD30B505E060
+:109430005B1EDBB2CC5CD55C6C40C454002BF7D116
+:1094400030BD10B5002409E00B78521E44EA4303F6
+:1094500000F8013B11F8013BD2B2DC09002AF3D13C
+:1094600010BD30B50C46097889B01546012049B1C8
+:10947000012905D12978042902D105201070002086
+:1094800009B030BD60680590CDF818D00D210DF100
+:10949000030001F046FDA0680188ADF80010807857
+:1094A0008DF802000120207006208DF81000606AFF
+:1094B0000890294604A8F5F745FEE1E72DE9F041BB
+:1094C0000C46097892B0154601204FF0020CFE4F71
+:1094D00006264FF0040869B101291ED0022946D0A2
+:1094E000032904D12978042901D11670002012B073
+:1094F000BDE8F081606850B1CDE90107012020701E
+:109500008DF80060606A04901146684665E084F852
+:1095100000C085F80080576027E029780429E6D14B
+:10952000696810222069FFF78CFF6868C07B00061D
+:1095300006D5E54A2069102310320146FFF776FF71
+:10954000D4E904101022FFF77CFF2069C07B0006DD
+:1095500006D5DD4A6069102310320146FFF766FF29
+:1095600084F800C085F800806F600320BFE7297889
+:109570000429BCD1A08910280CD9A0F1100080B218
+:10958000A081A1684FF01003014468466A68FFF7A4
+:109590004DFF18E004D14FF010032269A16807E0E5
+:1095A000C2B20DA8A168FFF72DFF626910230DA9B3
+:1095B00009A8FFF73BFF102309A968466A68FFF76F
+:1095C00035FF0320207060680590CDF818D08DF825
+:1095D0001060606A0890294604A8F5F7B3FD86E795
+:1095E0002DE9F04107460D4601200B7807213BB1DC
+:1095F000012B04D11378062B01D11170002077E7DD
+:109600006C69012620226170E8686060686A6062A7
+:10961000A168287C0870A681A068A968401C01F098
+:1096200009FCA08920222030A081A068696821302F
+:1096300001F000FCA08921462030A0812E70384620
+:10964000BDE8F041F5F795BD2DE9F05F0D46834685
+:1096500001200978174606464FF00708D1B1DFF818
+:1096600068A24FF00009AAF1080A012923D00229B3
+:109670007ED003290CD13978062909D179681022C6
+:10968000E86901F0D7FB08203870183500207D60AC
+:10969000BDE8F09F2C6A8C48202284F8018020309D
+:1096A00060602020A081686A60626968A06801F03B
+:1096B000C1FB2E70D4E039780629E9D12C6A84F8F0
+:1096C0000180686A606251681022E86901F0B2FBAB
+:1096D000E8696060A0684F4680F80090A681A068A5
+:1096E0004670A089401C80B2A081A16808446969C5
+:1096F00051F8012F026089888180A089801D80B285
+:10970000A0816969A268097801F001011154A0895A
+:10971000401C80B2A081A1680844296951F8012F3A
+:10972000026089888180A089801D80B2A08129691A
+:10973000A268097801F001011154A0891022401C8F
+:1097400080B2A081A1680844E96801F073FBA08998
+:109750001022103080B2A081A1680844A96801F0ED
+:1097600069FBA089103080B2A081A168014400E0AB
+:109770000DE0DAF804000860A089001D80B2A08125
+:10978000A1680F54A089401CA081022067E03978AD
+:10979000062992D151681022A86901F04BFB2C6A6E
+:1097A00084F80180E8696060686A6062A16881F895
+:1097B0000090A681A0684670A089401C80B2A0815C
+:1097C000A1680844696951F8012F02608988818085
+:1097D000A089801D80B2A0816969A268097801F022
+:1097E00001011154A089401C80B2A081A1680844E5
+:1097F000296951F8012F026089888180A089801D24
+:1098000080B2A0812969A268097801F00101115490
+:10981000A0891022401C80B2A081A1680844E96898
+:1098200001F008FBA0891022103080B2A081A1684D
+:109830000844A96801F0FEFAA089103080B2A08126
+:10984000A1680144DAF804000860A089001D80B214
+:10985000A081A1680E54A089401CA081032028701B
+:1098600021465846BDE8F05FF5F783BC70B50D465C
+:1098700006460978012041B1012905D11178062950
+:1098800002D109201070002070BD2C6A0720607082
+:1098900068686060686A6062E969A06851F8012FD1
+:1098A0000260898881800620A081E869A16800782B
+:1098B00000F001008871A089401C80B2A081A168DD
+:1098C0000844A96902E000006AB5010051F8012FBF
+:1098D000026089888180A089801D80B2A081A969E9
+:1098E000A268097801F001011154A089401C80B2DE
+:1098F000A081A168084469690A880280897881701A
+:10990000A0891022C01C80B2A081A16808442969E6
+:1099100001F090FAA0891022103080B2A081A168D5
+:109920000844E96801F086FAA0891022103080B25C
+:10993000A081A1680844A96801F07CFAA0892146A9
+:109940001030A081012028703046BDE87040F5F746
+:1099500010BC70B50D4606460978012059B10129A1
+:1099600008D11178062905D10A20107050680068C6
+:109970005060002070BD6C69072010226070E8689C
+:109980006060686A60622969A06801F053FA10207B
+:10999000A081A06820221030A96801F04BFAA089AC
+:1099A0002022203080B2A081A1680844696801F0BB
+:1099B00041FAA08921462030A0810120287030463C
+:1099C000BDE87040F5F7D5BB70B50C4601200978AD
+:1099D0008EB01546062659B1012934D0022905D189
+:1099E0002978042902D10B20107000200EB070BD20
+:1099F000606910236A46007800F001008DF80000CD
+:109A0000A069007800F001008DF80100E0680168AD
+:109A1000CDF802108188ADF8061080798DF8080025
+:109A200020690168CDF809108188ADF80D108079A2
+:109A30008DF80F006068059009A80690A168FFF7EF
+:109A4000F5FC01201DE029780429CFD1A06910235D
+:109A50006A4650F8011F00918088ADF804006069E3
+:109A600050F8011FCDF806108088ADF80A000020DC
+:109A700003906068059009A806906968FFF7D6FC16
+:109A8000022020708DF81060606A0890294604A8B2
+:109A9000F5F758FBAAE700B50B7889B001204BB168
+:109AA000012B05D11178042902D10C20107000205F
+:109AB00009B000BD4868019005A80290C868036815
+:109AC000059340680690886803680793406808908B
+:109AD0000120087006208DF80000486A04901146A5
+:109AE0006846F5F72FFBE3E700B50B7889B0012056
+:109AF00043B1012BDCD111780429D9D10D2010708C
+:109B00000020D5E74868019005A80290886803689E
+:109B10000593406806900020079008900120087087
+:109B200006208DF80000486A049011466846F5F753
+:109B300009FBBDE700B50B7889B0012043B1012BCB
+:109B4000B6D111780429B3D10E2010700020AFE7F0
+:109B500048680590CDF818D088680088ADF80000F6
+:109B6000C8680088ADF802000020019002900390C0
+:109B70000120087006208DF81000486A08901146F0
+:109B800004A8F5F7DFFA93E730B403460C78012018
+:109B90005CB1012C15D0022C05D111780D2902D110
+:109BA0000F201070002030BC704701200870C8687A
+:109BB000052242704A6842600B4A8260921EC2606F
+:109BC0000BE014780E2CEED102200870C868042433
+:109BD0004470526842608A688260496A4162014604
+:109BE00030BC1846F5F7C5BA64B501002DE9F0415F
+:109BF0000C4611490D68104A104908321160A0F155
+:109C00002001342901D301200CE0482810D040CC99
+:109C10000B4F94E80E0007EB8000241F50F8807C67
+:109C20003046B84720600448001D0560BDE8F0815B
+:109C30002046E7F7C5FAF5E71005024001000001EC
+:109C40009CB5010010B54C4800F042FA00B1FFDFAE
+:109C50004948401C00F03CFA002800D0FFDF10BD4E
+:109C60002DE9F05F454D8246D5F800900126424827
+:109C700000F036FA404C18B90026601C00F046FA95
+:109C80003F494FF0000E4FF0010B00BFC1F804B088
+:109C9000C1F800E1C1F804E1C5F800A0C1F800B0C6
+:109CA000384A4FF480434FF0E0274FF0030C1AE09E
+:109CB0001068C00617D5C7F88032EFF3108010F097
+:109CC000010072B600D00120C1F804C3D1F80081B0
+:109CD000B8F1000F05D1D1F80481B8F1000F00D11F
+:109CE00020BF00B962B6D1F8000118B9D1F804015B
+:109CF0000028DDD0D1F804010028C7D12EB1C5F865
+:109D00000090601C00F0ECF907E0601C00F0E8F93E
+:109D10000028B2D1184800F0F9F90020BDE8F09F02
+:109D20002DE9F0438DB00D46064600240DF11009D3
+:109D30000DF1200818E000BF04EB4407102255F88D
+:109D40002710684601F076F805EB87071022484691
+:109D5000796801F06FF86846FFF782FF10224146EC
+:109D6000B86801F067F8641CB442E5DB0DB0002070
+:109D7000BDE8F08374E700005401002004E50040D2
+:109D800000E0004010ED00E0C74800210170817044
+:109D9000704770B5C54D01232B60C54B1C68002C66
+:109DA000FCD0002407E00E6806601E68002EFCD080
+:109DB000001D091D641C9442F5D30020286018681A
+:109DC0000028FCD070BD70B5B74E0446B94D307850
+:109DD000022800D0FFDFAC4200D3FFDF7169B64834
+:109DE000012903D847F23052944201DD0322427127
+:109DF000491C7161291BC160AF497078BDE8704092
+:109E0000F6F722B970B5A84C0D466178884200D0AB
+:109E1000FFDFA84E092D4FD2DFE805F04E052231B5
+:109E20004E4E4E4E3C002078022800D0FFDF03202B
+:109E30002070A078022802D0012804D008E0A06891
+:109E400000F0F4FB04E004F1080007C8FFF7A1FFED
+:109E5000052020700020A070BDE87040F5F7D5BB4C
+:109E6000F5F7A2FC01466068F6F7E6FEB04202D2C2
+:109E7000616902290BD30320F7F746F912E0F5F7E1
+:109E800093FC01466068F6F7D7FEB042F3D2BDE816
+:109E9000704098E7207802280AD0052806D0FFDF16
+:109EA00004202070BDE8704000F0F4B8022000E00B
+:109EB0000320F7F729F9F3E7FFDF70BD70B505461A
+:109EC000F5F772FC784C60602078012800D0FFDF45
+:109ED00079490220087000220A718D6004224A71BB
+:109EE000744ACA6020706078BDE87040F6F7ACB87C
+:109EF00010B56D4CA07808B9207808B1112010BDBC
+:109F00006E48F5F7ECFB6070607820B1012020709E
+:109F10000020606110BD032010BD0246010B01202E
+:109F2000B2F5003F02D2884000F014BFB2F5802F96
+:109F300003D22039884000F015BFB2F5C02F03D2FC
+:109F40004039884000F017BFB2F5002F03D26039C6
+:109F5000884000F019BF002070472DE9F0411446F9
+:109F600000EB84070E4605463F1F00F072FB4FF0E2
+:109F700080510A69504306EB8402121FB24201D29B
+:109F8000012200E000221CB10969B4EB910F02D953
+:109F90000920BDE8F0814A498D4216D3AF4214D35F
+:109FA000854205D2874203D245EA0600800701D0E8
+:109FB0001020EEE78E4208D33AB92846FFF7ADFFEE
+:109FC00018B93846FFF7A9FF08B10F20E1E73D486F
+:109FD0003D490068884205D0224631462846FFF7B1
+:109FE000D8FE10E0FFF784FF0028D2D12E480121CF
+:109FF0008560C0E9036481704FF4A97104FB01F02E
+:10A000001830FFF75BFF0020C3E770B54FF08055B5
+:10A01000044628692A49B1FBF0F084420AD300F0D3
+:10A0200018FBA04201D8102070BD28696043FFF7DB
+:10A0300074FF08B10F2070BD224823490068884290
+:10A0400004D02869604300F0F1FA0CE0FFF750FFFC
+:10A050000028F0D129691448614381600221817090
+:10A060001A48FFF72BFF002070BD1548010B012097
+:10A070008840401E704770B50D460446FFF7F5FF57
+:10A08000204201D00F2070BD29462046BDE8704017
+:10A0900000F083BE10B5044C6078F5F76FFB00202C
+:10A0A0002070A07010BD00005801002004E50140A0
+:10A0B00000E40140105C0C0068110020059E0100C6
+:10A0C00000C0010098000020BEBAFECA7C5E0100FC
+:10A0D0000021017008467047014600200870704753
+:10A0E000EFF3108101F0010172B60278012A01D06C
+:10A0F000012200E000220123037001B962B60AB117
+:10A10000002070474FF400507047E9E7EFF31081EB
+:10A1100011F0010F72B64FF00002027000D162B66A
+:10A1200000207047F2E700004C49096801600020F8
+:10A1300070474A4908600020704701218A0720B112
+:10A14000012804D042F204007047916700E0D16713
+:10A150000020704742490120086042F20600704723
+:10A1600008B504233E4A1907103230B1C1F8043350
+:10A17000106840F0010010600BE0106820F0010052
+:10A180001060C1F808330020C1F8080135480068A4
+:10A190000090002008BD3249103140B101280AD09A
+:10A1A00002280FD0032812D042F205007047086839
+:10A1B00020F01E0003E0086820F01E00801C0860EC
+:10A1C00000207047086820F01E00001DF7E70868AF
+:10A1D00020F01E00801DF2E7214924310A68024365
+:10A1E0000A60002070471E4924310A6882430A60D1
+:10A1F000002070471A492431096801600020704727
+:10A2000017491C310A6802430A600020704714494C
+:10A210001C310A6882430A600020704710491C31D3
+:10A22000096801600020704702000F494FF00000EC
+:10A2300003D0012A01D0072070470A6070474FF011
+:10A2400080410020C1F808014FF0E020802180F813
+:10A2500000140121C0F80011704700000004004004
+:10A260000005004008010040780500406249634B4A
+:10A270000A6863499A42096801D1C1F3100101607B
+:10A28000002070475C495D4B0A685D49091D9A4290
+:10A2900001D1C0F310000860002070475649574BA9
+:10A2A0000A68574908319A4201D1C0F3100008608A
+:10A2B0000020704730B5504B504D1C6842F20803E7
+:10A2C000AC4202D0142802D203E0112801D3184670
+:10A2D00030BDC3004B481844C0F81015C0F8142511
+:10A2E000002030BD4449454B0A6842F209019A42B8
+:10A2F00002D0062802D203E0042801D308467047A2
+:10A30000404A012142F83010002070473A493B4B47
+:10A310000A6842F209019A4202D0062802D203E0FA
+:10A32000042801D308467047364A012102EBC000D9
+:10A3300041600020704770B52F4A304E314C15688F
+:10A3400042F2090304EB8002B54204D0062804D28D
+:10A35000C2F8001807E0042801D3184670BDC1F305
+:10A360001000C2F80008002070BD70B5224A234ECC
+:10A37000244C156842F2090304EB8002B54204D074
+:10A38000062804D2D2F8000807E0042801D31846B2
+:10A3900070BDD2F80008C0F310000860002070BD46
+:10A3A000174910B50831184808601120154A0021D6
+:10A3B00002EBC003C3F81015C3F81415401C142891
+:10A3C000F6D3002006E0042804D302EB8003C3F890
+:10A3D000001807E002EB8003D3F80048C4F3100430
+:10A3E000C3F80048401C0628EDD310BD04490648B8
+:10A3F000083108607047000098000020BEBAFECA0D
+:10A4000000F5014000F001400000FEFF10B572B6FB
+:10A4100000F0C2F850B1E6F773FFF5F7DEF8F6F793
+:10A4200019FEEFF72AF861490020086062B60020A3
+:10A4300010BD2DE9F0410F46044672B600F0ACF8AD
+:10A4400018B162B60820BDE8F081E6F7CFFEE6F766
+:10A4500059FF064600256909890001F1E02105F050
+:10A460001F00D1F80011C140C80717D0202D03D21A
+:10A4700026FA05F0C00716D168B2002806DA00F007
+:10A480000F0000F1E02090F8140D03E000F1E0204F
+:10A4900090F80004400900F0E5F820B16D1C642D2F
+:10A4A000D9D324B104E062B641F20100CBE7404CBD
+:10A4B0002078022803D962B64FF48050C3E73D49A3
+:10A4C000802081F8140DEEF7AFFF20780028607827
+:10A4D00001D058B908E048B1202807D8A078212831
+:10A4E00004D8012802D003E0A07808B10720AAE729
+:10A4F0002E493148086031480760E6F703FF2146DE
+:10A50000F6F78EFDF5F71DF800F0F4F9FFF73CFCC7
+:10A510002046E6F7C3FE040062B603D0FFF776FFDD
+:10A52000204690E700208EE710B5044600F034F88E
+:10A5300000B101202070002010BD214908600020DA
+:10A54000704770B50C461F490D681E491E4E0831F4
+:10A550000E60102807D011280CD012280FD0132815
+:10A5600011D0012013E0D4E90001FFF762FF354666
+:10A5700020600DE0FFF74AFF0025206008E020681A
+:10A58000FFF7D2FF03E00E4920680860002020603A
+:10A590000C48001D056070BD0448074900688842EA
+:10A5A00001D1012070470020704700009800002072
+:10A5B0006CB601000BE000E0BEBAFECA70010020DC
+:10A5C000040000201005024001000001F0B585B034
+:10A5D0000F460646FEF7D4FD04467078694600F043
+:10A5E0001F053846F3F751F8C0B1012C07BF019998
+:10A5F000B1F80310032005B018BFF0BD091D89B2E2
+:10A600002844884238BF012008BF00209CBF05B005
+:10A61000F0BD00BF05B04FF00200F0BD022CF9D133
+:10A62000042D28BFB6F80310F4D3E7E70B4A022144
+:10A6300011600B490B68002BFCD0084B1B1D1860E8
+:10A6400008680028FCD00020106008680028FCD0B2
+:10A6500070474FF0805040697047000004E50140AA
+:10A6600000E40140082808D238B1042805D00128A8
+:10A6700003D0052801D0012070470020704710B595
+:10A68000044600F0F5F880B1204600F0E2F8FFF74C
+:10A69000E9FF68B17D4A04F01F010120137888406A
+:10A6A0004BB15168084350600BE042F2010010BD0D
+:10A6B00042F2020010BD6109890001F1E021C1F8F8
+:10A6C0000001002010BD10B5044600F0D1F850B1D3
+:10A6D0006E4A04F01F0101201378884033B151689D
+:10A6E0008143516008E042F2010010BD6109890018
+:10A6F00001F1E021C1F88001002010BD70B50D46C8
+:10A70000044600F0B5F878B16009800000F1E0205F
+:10A71000D0F8000204F01F0201219140084000D04F
+:10A7200001202860002070BD42F2010070BD10B50C
+:10A73000044600F09DF858B104F01F010120884044
+:10A740006109890001F1E021C1F80002002010BD7B
+:10A7500042F2010010BD10B5044600F089F858B16E
+:10A7600004F01F01012088406109890001F1E02106
+:10A77000C1F88002002010BD42F2010010BD70B58A
+:10A780000D46044600F074F870B12846FFF76AFFE2
+:10A7900068B16807000E002C0CDA04F00F0101F11B
+:10A7A000E02181F8140D09E042F2010070BD42F28F
+:10A7B000020070BD04F1E02484F80004002070BDA4
+:10A7C00070B50C46054600F053F830B1284600F04D
+:10A7D00040F8C0B22060002070BD42F2010070BDA0
+:10A7E000BFF34F8F2A4801682A4A01F4E061114300
+:10A7F0000160BFF34F8FFEE770B50546F7F700F92C
+:10A8000008B1072070BD214C0120217889B9207042
+:10A8100072B6F6F72EFC4FF0E026D6F8801106F55A
+:10A82000C07681436160F6F724FCC043306062B6B5
+:10A8300000202870002070BD14490A783AB130B960
+:10A840004FF0E0224868C2F80001002008700020A4
+:10A850007047002806DA00F00F0000F1E02090F8C1
+:10A86000140D03E000F1E02090F800044009704767
+:10A8700010B50446642807DAF6F7FBFB0121A14076
+:10A88000084201D1012010BD002010BD740100203C
+:10A890000CED00E00400FA0510B54FF000040B4683
+:10A8A0000200204621461ED0012A04D0022A04D0EC
+:10A8B000032A1DD103E0012002E0022013E003205F
+:10A8C000072B15D2DFE803F0140406080A0C0E006B
+:10A8D000012108E0022106E0032104E0042102E056
+:10A8E000052100E00621F4F713FF08B1204610BD52
+:10A8F0000724FBE7FE4805218170002101704170AB
+:10A90000C17081607047FB490A78022A06D0CA6884
+:10A910001044C860C8683238F6F749B98A681044EC
+:10A9200088608868F7E70378F349F44A13B1012B8C
+:10A930000ED011E00379012B00D06BB943790BB134
+:10A94000012B09D18368643B8B4205D2C0680EE0BD
+:10A950000379012B02D00BB10020704743790BB172
+:10A96000012BF9D1C368643B8B42F5D280689042D9
+:10A97000F2D8012070472DE9F04704460226F5F78A
+:10A98000C6FD006800B1FFDFD94D01273CB120783A
+:10A99000B0B1012805D0022810D0032813D02F71A0
+:10A9A0000CE06068C82807D3F6F771F920B1606839
+:10A9B000FFF7A9FF012603E0002601E000F0AFF950
+:10A9C0003046BDE8F08728780028F7D16068FFF7A7
+:10A9D000AAFF0028E3D06068DFF81883007810B37E
+:10A9E000A878042800D0FFDF0020474688F8000040
+:10A9F00060680079C0B30020387160684079A0B306
+:10AA00000420787160688168E868F5F78FF9B860AC
+:10AA10006068C0683230F8600320A870B549E878F3
+:10AA2000F5F712FBCAE74FF00209404688F800909C
+:10AA300061680979D1B10021017161684979B9B1C1
+:10AA40000421417161688968323181606168C96837
+:10AA5000C160C068A64C14346060F4F7A5FE2060A5
+:10AA60006F7085F80290A9E704E005E00321E3E7B1
+:10AA70000321E6E70120BFE70320C2E72DE9F04705
+:10AA80009B4C8846E178884200D0FFDFDFF8609277
+:10AA900000250127974E09F11409B8F1090F76D264
+:10AAA000DFE808F0050D2A3D646A769E7E00A078F6
+:10AAB000032886D0A078022883D0FFDF81E7A07822
+:10AAC000032803D0A078022800D0FFDF0420A07064
+:10AAD0002571207800285FD1FFF715FF3078022814
+:10AAE00006D0B068E06000F06CF92061002048E01A
+:10AAF000E078F5F739F9F5E7A078032803D0A078D6
+:10AB0000022800D0FFDF207878BBA078032812D17C
+:10AB1000042026E00420F6F7F7FAA57051E7A078A4
+:10AB2000032803D0A078022800D0FFDF2078E0B906
+:10AB3000A078032814D0F4F737FE01464F46D9F821
+:10AB40000000F6F779F80028E4DB79688142E1DB60
+:10AB5000081AF0606749E078BDE8F047F5F774BA85
+:10AB60000520F6F7D1FAA7702BE724E0A078042897
+:10AB700000D0FFDF022004E0A078042800D0FFDF2F
+:10AB80000120A1688847FFF7F6FE05462EE027E082
+:10AB9000A078042800D0FFDFBDE8F04700F0BFB880
+:10ABA000A078042805D0607810B1A078022800D0E1
+:10ABB000FFDF207818B1BDE8F04700F0B9B8207980
+:10ABC00020B10620F6F7A0FA2571CCE7607828B10D
+:10ABD0004849E078F5F738FA6570F2E60720C0E7F3
+:10ABE000FFDFEEE63DB1012D03D0FFDF022DF9D1ED
+:10ABF000E7E60420C5E70320C3E770B5050005D0EC
+:10AC00003B4CA078052803D0112070BD102070BDEA
+:10AC10003B48F4F764FDE070E07818B1A5600020CF
+:10AC2000A07070BD032070BD314810B5017809B126
+:10AC3000112010BD817805290CD0817801290BD015
+:10AC4000817849B1012101708178012904D080788F
+:10AC500010B103E00F2010BD00F06AF8002010BD15
+:10AC60002DE9F041224E0446B07808B101280AD1FE
+:10AC700064B12046FFF757FE50B120781D4D48B112
+:10AC8000B078012822D00F20BDE8F0811020FBE72A
+:10AC90000720F9E702272F70207998B1002028714A
+:10ACA000607988B104206871A0683230A860E068DB
+:10ACB000E860E8680E4C14346060F4F775FD2060BD
+:10ACC000B77022E00320EAE70320ECE700202870B9
+:10ACD000207900B3002028716079F0B104206871F8
+:10ACE000A168F068F5F722F8A860E068323009E062
+:10ACF0007C010020781100203D860100FF1FA10784
+:10AD00007DAA0100E8600320B0701049F078F5F7E3
+:10AD10009BF90020B8E70320DDE70320DFE70C48BC
+:10AD200010B5006900F045F8BDE81040F4F76DBCBF
+:10AD300010B5074CE078F4F721FD0820F6F7E4F9A8
+:10AD40000520A07000202070607010BD78110020D8
+:10AD50007C0100201F490968014201D00120704791
+:10AD6000002070471B49091D0968014201D00120DC
+:10AD7000704700207047174910310968014201D01F
+:10AD800001207047002070471249143109680142C0
+:10AD900001D0012070470020704710B50D4C206095
+:10ADA000201D01600B4810300260001D0360002070
+:10ADB00010BD09490A6848F202139A4302430A6027
+:10ADC0007047054A116848F2021301EA03009943EB
+:10ADD0001160704700060040C806024040EA0103C7
+:10ADE00010B59B070FD1042A0DD310C808C9121F34
+:10ADF0009C42F8D020BA19BA884201D9012010BD6E
+:10AE00004FF0FF3010BD1AB1D30703D0521C07E03A
+:10AE1000002010BD10F8013B11F8014B1B1B07D19E
+:10AE200010F8013B11F8014B1B1B01D1921EF1D10F
+:10AE3000184610BD032A40F2308010F0030C00F0D9
+:10AE4000158011F8013BBCF1020F624498BF11F864
+:10AE500001CB00F8013B38BF11F8013BA2F104021D
+:10AE600098BF00F801CB38BF00F8013B11F0030395
+:10AE700000F02580083AC0F0088051F8043B083AF9
+:10AE800051F804CBA0E80810F5E7121D5CBF51F89B
+:10AE9000043B40F8043BAFF30080D20724BF11F815
+:10AEA000013B11F801CB48BF11F8012B24BF00F87A
+:10AEB000013B00F801CB48BF00F8012B704710B5EB
+:10AEC000203AC0F00B80B1E81850203AA0E81850A2
+:10AED000B1E81850A0E81850BFF4F5AF5FEA027C63
+:10AEE00024BFB1E81850A0E8185044BF18C918C0D2
+:10AEF000BDE810405FEA827C24BF51F8043B40F873
+:10AF0000043B08BF7047D20728BF31F8023B48BF57
+:10AF100011F8012B28BF20F8023B48BF00F8012B95
+:10AF200070474FF000020429C0F0128010F0030CAB
+:10AF300000F01B80CCF1040CBCF1020F18BF00F82C
+:10AF4000012BA8BF20F8022BA1EB0C0100F00DB8DB
+:10AF50005FEAC17C24BF00F8012B00F8012B48BF39
+:10AF600000F8012B70474FF0000200B513469446DD
+:10AF70009646203922BFA0E80C50A0E80C50B1F151
+:10AF80002001BFF4F7AF090728BFA0E80C5048BF65
+:10AF90000CC05DF804EB890028BF40F8042B08BF03
+:10AFA000704748BF20F8022B11F0804F18BF00F8FF
+:10AFB000012B70477047704770477047164B1860F9
+:10AFC000164B1960164B1A607047FEDF042071465D
+:10AFD00008421BD10699134A914217DC069902399F
+:10AFE0004878DF2812D10878FE2808D0FF280DD134
+:10AFF0004FF001004FF000020B4B1B68184741F265
+:10B0000001000099019A084B1B681847069805999A
+:10B01000064B1B68DB6818479C010020A00100203C
+:10B02000A401002000C001007001002004000020E5
+:10B03000204821497047FFF7FBFFE6F7AFF800BD56
+:10B0400001200007C06AC0B2FF2806D14FF0FF30D0
+:10B050004FF010210968884203D018484FF00801CA
+:10B0600001604FF4805016490968884203D1154A9F
+:10B0700013605B68184700BD20BFFDE74FF48050A8
+:10B080000F490968884210D10F4B18684FF0FF3103
+:10B090008842F1D080F308884FF02021884204DDF7
+:10B0A0000A48026802210A430260094880470948A9
+:10B0B0008047FFDF88110020881100202C05004008
+:10B0C000000000200400002000C001002405004012
+:10B0D0008D1A010041B0010004207146084202D0DF
+:10B0E000EFF3098101E0EFF3088188690238007805
+:10B0F000102813DB20280FDB2B280BDB0A4A1268F1
+:10B100000A4B9A4203D1602804DB094A1047022007
+:10B1100008607047074A1047074A1047074A1268F5
+:10B120002C3212681047000098000020BEBAFECAF8
+:10B1300009130000ED9B010043A50100040000205D
+:10B140000E4B0F4908470F4B0D4908470E4B0C4952
+:10B1500008470E4B0A4908470D4B094908470D4B54
+:10B16000074908470C4B064908470C4B0449084758
+:10B170000B4B034908470B4B01490847A3910000BB
+:10B180006D960000A52F0000C98D00004D8D0000B8
+:10B190007F930000251300004F740000C38E000051
+:10B1A000F5950000A91100000021016041600172C5
+:10B1B00070470A6802600B7903717047AB7B00002F
+:10B1C0004B7D00007F7B0000457E0000697E000013
+:10B1D000A37E0000D77E0000117F0000417F0000A9
+:10B1E000937F000091120000911200009112000064
+:10B1F000911200009112000091120000F122000053
+:10B2000093230000B3230000BD240000FB1E0000B8
+:10B2100005270000E527000005280000C72D0000D5
+:10B22000EB2D00001B2D00006F2D00001D2E0000D7
+:10B23000A72E0000B3410000774300001F47000025
+:10B2400039480000BD48000063490000D3490000B0
+:10B25000ED4A0000BB4B0000374C00001F280000E7
+:10B26000252800002F280000BD1E0000FB2800003C
+:10B270008F1E0000552A0000911200001555000095
+:10B280009B550000B7550000D355000047570000FC
+:10B29000FD55000007560000495600006B5600009F
+:10B2A0002D57000091120000911200009112000031
+:10B2B0009112000091120000911200001F6D000019
+:10B2C0003F6D0000416D00007B6D0000A96D000026
+:10B2D000936E00003D6F0000516F00009D6F0000F5
+:10B2E000957000003B7200006B730000195F000056
+:10B2F00091120000911200009112000023890000B9
+:10B300006189000083890000100110013A020000E9
+:10B310001A02000069740000F9760000FFFFFFFFC9
+:10B320000000FFFF2F850000CF1B000041520000EE
+:10B33000635F0000977600000000000023002300F8
+:10B3400046004D0023002300F5000000000000002F
+:10B35000000000001DBB0000000000000000000015
+:10B3600000000000A5C80000000000000000000070
+:10B37000000000007DBB000003BC000000000000D6
+:10B380000000000003BF0000ABBC0000E3C10000F0
+:10B39000000000000000000025CD000000000000BB
+:10B3A0000000000000000000B7BF00007BC90000E3
+:10B3B000000000004FCA0000C3CA000000000000E7
+:10B3C0007DC2000059C300000000000089CA0000CF
+:10B3D000B9C3000045C60000A9C600009FC7000011
+:10B3E00085C1000039C80000000000009DC00000B9
+:10B3F0000000000095BD00000FBD0000E5C8000082
+:10B4000001CC00006FCC00000000000075BF000000
+:10B410003BBD00002DBF000063CE0000CBBE00008E
+:10B4200073CD000000000000D1CC000079BC00000A
+:10B43000AFBB0000E9BD0000E7BC0000E3CD0000A9
+:10B4400001CF000005C00000C1CE00008B38000015
+:10B450008B380000CD22000099840000D9610000E3
+:10B46000115200000000000029710100D1380000D5
+:10B47000D1380000EF220000ED840000536200008C
+:10B480001B520000356901004F710100BC01BC0175
+:10B490003E002C0044000E00D800200101000000F6
+:10B4A000010000000001020304001011121300004B
+:10B4B0000014000063940100C9990100979A0100EB
+:10B4C000E99A0100359B0100899B0100BD940100B0
+:10B4D000E1950100499601006D9801005399010022
+:10B4E00013DE000017EF00001B5C01006D4E010031
+:10B4F0003F5C01006F4E0100453101004F840100A7
+:10B500007D4101004F840100B1310100BF85010080
+:10B510003B3B0100BF850100BD3001004D850100AE
+:10B52000AF4001004D850100555555D6BE898E00AE
+:10B5300000006606F30C801300000A033B066C094A
+:10B5400000005604D308500D555555252627D6BE64
+:10B55000898EF401FA00960064004B0032001E0050
+:10B56000140000000300656C74620000000000001D
+:10B570000000000000000000000087000000000044
+:10B5800000000000000000000000BE83605ADB0BDA
+:10B59000376038A5F5AA9183886C00006DA2010080
+:10B5A00085A201009DA20100B5A20100E5A2010053
+:10B5B0000DA3010037A301006BA301000BA0010044
+:10B5C0005B9F010077A00100D1A00100E1A0010074
+:10B5D0000DA101007FA60100C7A60100FDA6010084
+:10B5E0002FA7010057A701007FA70100C1A70100F5
+:10B5F000E1A70100F9A7010039A80100BF1201006D
+:10B60000C7120100D51201003BA1010055A10100A4
+:10B6100029A1010033A1010061A1010097A101004E
+:10B62000D9A10100E7A10100F5A1010001A20100DB
+:10B630000FA201001DA2010029A2010000000000CC
+:10B64000678F0000BD8F0000D38F000099A8010014
+:10B65000619C0100219D0100FBAB010029AC0100B0
+:10B6600061AC0100B51001008D1501000010020051
+:10B6700090B6010008000020A00100004411000065
+:10B68000B4B60100A8010020E00F00008011000006
+:10B6900001593601000100683720FB349B5F8004AC
+:10B6A0001F800010022001337F0102E429E4BDAFB6
+:04B6B0000100000095
+:00000001FF
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/common_rtc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/common_rtc.h
new file mode 100644
index 0000000000..f15ff83a58
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/common_rtc.h
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#ifndef COMMON_RTC_H
+#define COMMON_RTC_H
+
+#include "nrf_rtc.h"
+
+#define RTC_COUNTER_BITS        24u
+
+// Instance 0 is reserved for SoftDevice.
+// Instance 1 is used as a common one for us_ticker, lp_ticker and (in case
+// of NRF51) as an alternative tick source for RTOS.
+// ["us_ticker.c" uses hard coded addresses of the 'NRF_RTC1->EVENT_COMPARE[1]'
+//  register in inline assembly implementations of COMMON_RTC_IRQ_HANDLER,
+//  please remember to update those in case of doing changes here]
+#define COMMON_RTC_INSTANCE     NRF_RTC1
+#define COMMON_RTC_IRQ_HANDLER  RTC1_IRQHandler
+#define US_TICKER_CC_CHANNEL    0
+#define OS_TICK_CC_CHANNEL      1
+#define LP_TICKER_CC_CHANNEL    2
+
+#define COMMON_RTC_EVENT_COMPARE(channel) \
+    CONCAT_2(NRF_RTC_EVENT_COMPARE_, channel)
+#define COMMON_RTC_INT_COMPARE_MASK(channel) \
+    CONCAT_3(NRF_RTC_INT_COMPARE, channel, _MASK)
+
+#define US_TICKER_EVENT     COMMON_RTC_EVENT_COMPARE(US_TICKER_CC_CHANNEL)
+#define US_TICKER_INT_MASK  COMMON_RTC_INT_COMPARE_MASK(US_TICKER_CC_CHANNEL)
+#define OS_TICK_EVENT       COMMON_RTC_EVENT_COMPARE(OS_TICK_CC_CHANNEL)
+#define OS_TICK_INT_MASK    COMMON_RTC_INT_COMPARE_MASK(OS_TICK_CC_CHANNEL)
+#define LP_TICKER_EVENT     COMMON_RTC_EVENT_COMPARE(LP_TICKER_CC_CHANNEL)
+#define LP_TICKER_INT_MASK  COMMON_RTC_INT_COMPARE_MASK(LP_TICKER_CC_CHANNEL)
+
+extern bool              m_common_rtc_enabled;
+extern uint32_t volatile m_common_rtc_overflows;
+
+void     common_rtc_init(void);
+uint32_t common_rtc_32bit_ticks_get(void);
+uint64_t common_rtc_64bit_us_get(void);
+void     common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
+                                  uint32_t int_mask);
+
+#endif // COMMON_RTC_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/gpio_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
new file mode 100644
index 0000000000..f9d281ecaf
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/gpio_api.c
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "nrf_drv_gpiote.h"
+
+
+#define GPIO_PIN_COUNT 31
+
+typedef enum {
+    GPIO_NOT_USED = 0,
+    GPIO_USED     = 1,
+    GPIO_USED_IRQ = 2,
+    GPIO_USED_IRQ_DISABLED = 3
+} gpio_usage_t;
+
+typedef struct {
+    bool         used_as_gpio : 1;
+    PinDirection direction    : 1;
+    bool         init_high    : 1;
+    PinMode      pull         : 2;
+    bool         used_as_irq  : 1;
+    bool         irq_fall     : 1;
+    bool         irq_rise     : 1;
+} gpio_cfg_t;
+
+uint32_t m_gpio_initialized;
+gpio_cfg_t m_gpio_cfg[GPIO_PIN_COUNT];
+
+
+/***********
+  GPIO IRQ
+***********/
+
+static gpio_irq_handler m_irq_handler;
+static uint32_t m_channel_ids[GPIO_PIN_COUNT] = {0};
+uint32_t m_gpio_irq_enabled;
+
+
+static void gpiote_irq_handler(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action)
+{
+    nrf_gpio_pin_sense_t sense =  nrf_gpio_pin_sense_get(pin);
+    gpio_irq_event event = (sense == NRF_GPIO_PIN_SENSE_LOW) ? IRQ_RISE : IRQ_FALL;
+    
+    if (m_gpio_irq_enabled & (1UL << pin)) {
+        if (((event == IRQ_RISE) && m_gpio_cfg[pin].irq_rise)
+            || ((event == IRQ_FALL) && m_gpio_cfg[pin].irq_fall)) {
+                m_irq_handler(m_channel_ids[pin], event);
+            }
+    }
+}
+
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+    if (pin == (PinName)NC) {
+        return;
+    }
+    MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
+    (void) nrf_drv_gpiote_init();
+
+    m_gpio_cfg[obj->pin].used_as_gpio = true;
+}
+
+
+int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (m_gpio_cfg[obj->pin].direction == PIN_OUTPUT) {
+        return ((NRF_GPIO->OUTSET & (1UL << obj->pin)) ? 1 : 0);
+    } else {
+        return nrf_gpio_pin_read(obj->pin);
+    }
+}
+
+
+static void gpio_apply_config(uint8_t pin)
+{
+    if (m_gpio_initialized & (1UL << pin)) {
+        if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq)) {
+            nrf_drv_gpiote_out_uninit(pin);
+        }
+        else {
+            nrf_drv_gpiote_in_uninit(pin);
+        }
+    }
+    
+    if (m_gpio_cfg[pin].used_as_gpio || m_gpio_cfg[pin].used_as_irq) {
+        if ((m_gpio_cfg[pin].direction == PIN_INPUT)
+            || (m_gpio_cfg[pin].used_as_irq)) {
+            //Configure as input.
+            nrf_drv_gpiote_in_config_t cfg;
+            
+            cfg.hi_accuracy = false;
+            cfg.is_watcher = false;
+            cfg.sense = NRF_GPIOTE_POLARITY_TOGGLE;
+            if (m_gpio_cfg[pin].used_as_irq) {
+                cfg.pull = NRF_GPIO_PIN_PULLUP;
+                nrf_drv_gpiote_in_init(pin, &cfg, gpiote_irq_handler);
+                if ((m_gpio_irq_enabled & (1 << pin))
+                    && (m_gpio_cfg[pin].irq_rise || m_gpio_cfg[pin].irq_fall))
+                {
+                    nrf_drv_gpiote_in_event_enable(pin, false);
+                }
+            }
+            else {
+                switch(m_gpio_cfg[pin].pull) {
+                    case PullUp:
+                        cfg.pull = NRF_GPIO_PIN_PULLUP;
+                    break;
+                    case PullDown:
+                        cfg.pull = NRF_GPIO_PIN_PULLDOWN;
+                    break;
+                    default:
+                        cfg.pull = NRF_GPIO_PIN_NOPULL;
+                    break;
+                }
+                nrf_drv_gpiote_in_init(pin, &cfg, NULL);
+            }
+        }
+        else {
+            // Configure as output.
+            nrf_drv_gpiote_out_config_t cfg = GPIOTE_CONFIG_OUT_SIMPLE(m_gpio_cfg[pin].init_high);
+            nrf_drv_gpiote_out_init(pin, &cfg);
+        }
+        m_gpio_initialized |= (1UL << pin);
+    }
+    else {
+        m_gpio_initialized &= ~(1UL << pin);
+    }
+}
+
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    MBED_ASSERT(obj->pin <= GPIO_PIN_COUNT);
+    m_gpio_cfg[obj->pin].pull = mode;
+    gpio_apply_config(obj->pin);
+}
+
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    MBED_ASSERT(obj->pin <= GPIO_PIN_COUNT);
+    m_gpio_cfg[obj->pin].direction = direction;
+    gpio_apply_config(obj->pin);
+}
+
+
+/***********
+  GPIO IRQ
+***********/
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    if (pin == NC) {
+        return -1;
+    }
+    MBED_ASSERT((uint32_t)pin < GPIO_PIN_COUNT);
+    (void) nrf_drv_gpiote_init();
+
+    m_gpio_cfg[pin].used_as_irq = true;
+    m_channel_ids[pin] = id;
+    obj->ch            = pin;
+    m_irq_handler      = handler;
+    m_channel_ids[pin] = id;
+
+    gpio_apply_config(pin);
+    return 1;
+}
+
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    nrf_drv_gpiote_in_uninit(obj->ch);
+    m_gpio_cfg[obj->ch].used_as_irq = false;
+    m_channel_ids[obj->ch] = 0;
+
+    gpio_apply_config(obj->ch);
+}
+
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    bool event_enabled_before = false;
+    if ((m_gpio_irq_enabled & (1 << obj->ch))
+        && (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall)) {
+        event_enabled_before = true;
+    }
+
+    if (event == IRQ_RISE) {
+        m_gpio_cfg[obj->ch].irq_rise = enable ? true : false;
+    }
+    else if (event == IRQ_FALL) {
+        m_gpio_cfg[obj->ch].irq_fall = enable ? true : false;
+    }
+
+    bool event_enabled_after = false;
+    if ((m_gpio_irq_enabled & (1 << obj->ch))
+        && (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall)) {
+        event_enabled_after = true;
+    }
+
+    if (event_enabled_before != event_enabled_after) {
+        if (event_enabled_after) {
+            nrf_drv_gpiote_in_event_enable(obj->ch,false);
+        } else {
+            nrf_drv_gpiote_in_event_disable(obj->ch);
+        }
+    }
+}
+
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    m_gpio_irq_enabled |= (1 << obj->ch);
+    if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall) {
+        nrf_drv_gpiote_in_event_enable(obj->ch, true);
+    }
+}
+
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    m_gpio_irq_enabled &= ~(1 << obj->ch);
+    if (m_gpio_cfg[obj->ch].irq_rise || m_gpio_cfg[obj->ch].irq_fall) {
+        nrf_drv_gpiote_in_event_enable(obj->ch, false);
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/gpio_object.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/gpio_object.h
new file mode 100644
index 0000000000..f7b621a9ed
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/gpio_object.h
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+
+#include "nrf_gpio.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value) {
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (value) {
+        nrf_gpio_pin_set(obj->pin);
+    } else {
+        nrf_gpio_pin_clear(obj->pin);
+    }
+}
+
+static inline int gpio_is_connected(const gpio_t *obj) {
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/i2c_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
new file mode 100644
index 0000000000..c7221533d7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/i2c_api.c
@@ -0,0 +1,302 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "i2c_api.h"
+
+#if DEVICE_I2C
+
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "nrf_drv_twi.h"
+#include "app_util_platform.h"
+
+#if DEVICE_I2C_ASYNCH
+    #define TWI_IDX(obj)    ((obj)->i2c.twi_idx)
+#else
+    #define TWI_IDX(obj)    ((obj)->twi_idx)
+#endif
+#define TWI_INFO(obj)   (&m_twi_info[TWI_IDX(obj)])
+
+typedef struct {
+    bool initialized;
+    nrf_drv_twi_config_t config;
+    volatile bool transfer_finished;
+
+    #if DEVICE_I2C_ASYNCH
+    volatile uint32_t events;
+    void (*handler)(void);
+    uint32_t event_mask;
+    #endif
+} twi_info_t;
+static twi_info_t m_twi_info[TWI_COUNT];
+
+static nrf_drv_twi_t const m_twi_instances[TWI_COUNT] = {
+#if TWI0_ENABLED
+    NRF_DRV_TWI_INSTANCE(0),
+#endif
+#if TWI1_ENABLED
+    NRF_DRV_TWI_INSTANCE(1),
+#endif
+};
+
+static void twi_event_handler(nrf_drv_twi_evt_t const *event, void *context)
+{
+    twi_info_t * twi_info = TWI_INFO((i2c_t *)context);
+    twi_info->transfer_finished = true;
+
+#if DEVICE_I2C_ASYNCH
+    switch (event->type) {
+    case NRF_DRV_TWI_EVT_DONE:
+        twi_info->events |= I2C_EVENT_TRANSFER_COMPLETE;
+        break;
+
+    case NRF_DRV_TWI_EVT_ADDRESS_NACK:
+        twi_info->events |= I2C_EVENT_ERROR_NO_SLAVE;
+        break;
+
+    case NRF_DRV_TWI_EVT_DATA_NACK:
+        twi_info->events |= I2C_EVENT_ERROR;
+        break;
+    }
+
+    if (twi_info->handler) {
+        twi_info->handler();
+    }
+#endif // DEVICE_I2C_ASYNCH
+}
+
+static uint8_t twi_address(int i2c_address)
+{
+    // The TWI driver requires 7-bit slave address (without R/W bit).
+    return (i2c_address >> 1);
+}
+
+void i2c_init(i2c_t *obj, PinName sda, PinName scl)
+{
+    int i;
+    for (i = 0; i < TWI_COUNT; ++i) {
+        if (m_twi_info[i].initialized &&
+            m_twi_info[i].config.sda == (uint32_t)sda &&
+            m_twi_info[i].config.scl == (uint32_t)scl) {
+            TWI_IDX(obj) = i;
+            TWI_INFO(obj)->config.frequency = NRF_TWI_FREQ_100K;
+            i2c_reset(obj);
+            return;
+        }
+    }
+
+    nrf_drv_twi_config_t const config = {
+        .scl                = scl,
+        .sda                = sda,
+        .frequency          = NRF_TWI_FREQ_100K,
+        .interrupt_priority = APP_IRQ_PRIORITY_LOW,
+    };
+
+    for (i = 0; i < TWI_COUNT; ++i) {
+        if (!m_twi_info[i].initialized) {
+            nrf_drv_twi_t const *twi = &m_twi_instances[i];
+            ret_code_t ret_code =
+                nrf_drv_twi_init(twi, &config, twi_event_handler, obj);
+            if (ret_code == NRF_SUCCESS) {
+                TWI_IDX(obj) = i;
+                TWI_INFO(obj)->initialized = true;
+                TWI_INFO(obj)->config = config;
+
+                nrf_drv_twi_enable(twi);
+                return;
+            }
+        }
+    }
+
+    // No available peripheral
+    error("No available I2C peripheral\r\n");
+}
+
+void i2c_reset(i2c_t *obj)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    nrf_drv_twi_t const *twi = &m_twi_instances[TWI_IDX(obj)];
+
+    nrf_drv_twi_uninit(twi);
+    nrf_drv_twi_init(twi, &twi_info->config, twi_event_handler, obj);
+    nrf_drv_twi_enable(twi);
+}
+
+int i2c_start(i2c_t *obj)
+{
+    (void)obj;
+
+    return -1; // Not implemented.
+}
+
+int i2c_stop(i2c_t *obj)
+{
+    (void)obj;
+
+    return -1; // Not implemented.
+}
+
+void i2c_frequency(i2c_t *obj, int hz)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    nrf_drv_twi_t const *twi = &m_twi_instances[TWI_IDX(obj)];
+
+    if (hz < 250000) {
+        twi_info->config.frequency = NRF_TWI_FREQ_100K;
+    } else if (hz < 400000) {
+        twi_info->config.frequency = NRF_TWI_FREQ_250K;
+    } else {
+        twi_info->config.frequency = NRF_TWI_FREQ_400K;
+    }
+    nrf_twi_frequency_set(twi->reg.p_twi, twi_info->config.frequency);
+}
+
+int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
+{
+    (void)stop;
+
+    twi_info_t *twi_info = TWI_INFO(obj);
+    nrf_drv_twi_t const *twi = &m_twi_instances[TWI_IDX(obj)];
+
+    twi_info->transfer_finished = false;
+    ret_code_t ret_code = nrf_drv_twi_rx(twi, twi_address(address),
+        (uint8_t *)data, length);
+    if (ret_code != NRF_SUCCESS) {
+        return 0;
+    }
+    while (!twi_info->transfer_finished) {}
+    return nrf_drv_twi_data_count_get(twi);
+}
+
+int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    nrf_drv_twi_t const *twi = &m_twi_instances[TWI_IDX(obj)];
+
+    twi_info->transfer_finished = false;
+    ret_code_t ret_code = nrf_drv_twi_tx(twi, twi_address(address),
+        (uint8_t const *)data, length, (stop == 0));
+    if (ret_code != NRF_SUCCESS) {
+        return 0;
+    }
+    while (!twi_info->transfer_finished) {}
+    return nrf_drv_twi_data_count_get(twi);
+}
+
+int i2c_byte_read(i2c_t *obj, int last)
+{
+    (void)obj;
+    (void)last;
+
+    return -1; // Not implemented.
+}
+
+int i2c_byte_write(i2c_t *obj, int data)
+{
+    (void)obj;
+    (void)data;
+
+    return -1; // Not implemented.
+}
+
+
+#if DEVICE_I2C_ASYNCH
+
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length,
+                         void *rx, size_t rx_length, uint32_t address,
+                         uint32_t stop, uint32_t handler,
+                         uint32_t event, DMAUsage hint)
+{
+    (void)stop;
+    (void)hint;
+
+    if (i2c_active(obj)) {
+        return;
+    }
+    if ((tx_length == 0) && (rx_length == 0)) {
+        return;
+    }
+
+    twi_info_t *twi_info = TWI_INFO(obj);
+    twi_info->events     = 0;
+    twi_info->handler    = (void (*)(void))handler;
+    twi_info->event_mask = event;
+
+    uint8_t twi_addr = twi_address(address);
+    nrf_drv_twi_t const *twi = &m_twi_instances[TWI_IDX(obj)];
+
+    if ((tx_length > 0) && (rx_length == 0)) {
+        nrf_drv_twi_xfer_desc_t const xfer =
+            NRF_DRV_TWI_XFER_DESC_TX(twi_addr, (uint8_t *)tx, tx_length);
+        nrf_drv_twi_xfer(twi, &xfer,
+            stop ? 0 : NRF_DRV_TWI_FLAG_TX_NO_STOP);
+    }
+    else if ((tx_length == 0) && (rx_length > 0)) {
+        nrf_drv_twi_xfer_desc_t const xfer =
+            NRF_DRV_TWI_XFER_DESC_RX(twi_addr, rx, rx_length);
+        nrf_drv_twi_xfer(twi, &xfer, 0);
+    }
+    else if ((tx_length > 0) && (rx_length > 0)) {
+        nrf_drv_twi_xfer_desc_t const xfer =
+            NRF_DRV_TWI_XFER_DESC_TXRX(twi_addr,
+                (uint8_t *)tx, tx_length, rx, rx_length);
+        nrf_drv_twi_xfer(twi, &xfer, 0);
+    }
+}
+
+uint32_t i2c_irq_handler_asynch(i2c_t *obj)
+{
+    twi_info_t *twi_info = TWI_INFO(obj);
+    return (twi_info->events & twi_info->event_mask);
+}
+
+uint8_t i2c_active(i2c_t *obj)
+{
+    nrf_drv_twi_t const *twi = &m_twi_instances[TWI_IDX(obj)];
+    return nrf_drv_twi_is_busy(twi);
+}
+
+void i2c_abort_asynch(i2c_t *obj)
+{
+    i2c_reset(obj);
+}
+
+#endif // DEVICE_I2C_ASYNCH
+
+#endif // DEVICE_I2C
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c
new file mode 100644
index 0000000000..ae63c2a1e1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "common_rtc.h"
+
+void lp_ticker_init(void)
+{
+    common_rtc_init();
+}
+
+uint32_t lp_ticker_read()
+{
+    return (uint32_t)common_rtc_64bit_us_get();
+}
+
+void lp_ticker_set_interrupt(timestamp_t timestamp)
+{
+    common_rtc_set_interrupt(timestamp,
+        LP_TICKER_CC_CHANNEL, LP_TICKER_INT_MASK);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK);
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
+}
+
+#endif // DEVICE_LOWPOWERTIMER
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/objects.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/objects.h
new file mode 100644
index 0000000000..209134b7d1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/objects.h
@@ -0,0 +1,94 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct serial_s {
+    uint32_t placeholder; // struct is unused by nRF5x API implementation
+};                        // but it must be not empty (required by strict compiler - IAR)
+
+struct spi_s {
+    uint8_t spi_idx;
+};
+
+struct port_s {
+    __IO uint32_t *reg_cnf;
+    __IO uint32_t *reg_out;
+    __I  uint32_t *reg_in;
+    PortName port;
+    uint32_t mask;
+};
+
+struct pwmout_s {
+    PWMName pwm_name;
+    PinName pin;
+    uint8_t pwm_channel;
+    void *  pwm_struct;
+};
+
+struct i2c_s {
+    uint8_t twi_idx;
+};
+
+struct analogin_s {
+    ADCName adc;
+    uint8_t adc_pin;
+};
+
+struct gpio_irq_s {
+    uint32_t ch;
+};
+
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/pinmap.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/pinmap.c
new file mode 100644
index 0000000000..989fbf209b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/pinmap.c
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "pinmap.h"
+
+void pin_function(PinName pin, int function)
+{
+    /* Avoid compiler warnings */
+    (void) pin;
+    (void) function;
+}
+
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    uint32_t pin_number = (uint32_t)pin;
+
+    NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_PULL_Msk;
+    NRF_GPIO->PIN_CNF[pin_number] |= (mode << GPIO_PIN_CNF_PULL_Pos);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/port_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/port_api.c
new file mode 100644
index 0000000000..ad3be04816
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/port_api.c
@@ -0,0 +1,108 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+
+PinName port_pin(PortName port, int pin_n)
+{
+    (void) port;
+    return (PinName)(pin_n);
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    obj->port = port;
+    obj->mask = mask;
+
+    obj->reg_out = &NRF_GPIO->OUT;
+    obj->reg_in  = &NRF_GPIO->IN;
+    obj->reg_cnf = NRF_GPIO->PIN_CNF;
+
+    port_dir(obj, dir);
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+    // The mode is set per pin: reuse pinmap logic
+    for (i = 0; i<31; i++) {
+        if (obj->mask & (1 << i)) {
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    int i;
+    switch (dir) {
+    case PIN_INPUT:
+        for (i = 0; i<31; i++) {
+            if (obj->mask & (1 << i)) {
+                obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+                                    | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+                                    | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
+                                    | (GPIO_PIN_CNF_DIR_Input << GPIO_PIN_CNF_DIR_Pos);
+            }
+        }
+        break;
+    case PIN_OUTPUT:
+        for (i = 0; i<31; i++) {
+            if (obj->mask & (1 << i)) {
+                obj->reg_cnf[i] = (GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)
+                                    | (GPIO_PIN_CNF_DRIVE_S0S1 << GPIO_PIN_CNF_DRIVE_Pos)
+                                    | (GPIO_PIN_CNF_PULL_Disabled << GPIO_PIN_CNF_PULL_Pos)
+                                    | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos)
+                                    | (GPIO_PIN_CNF_DIR_Output << GPIO_PIN_CNF_DIR_Pos);
+            }
+        }
+        break;
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    *obj->reg_out = value;
+}
+
+int port_read(port_t *obj)
+{
+    return (*obj->reg_in);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/rtc_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/rtc_api.c
new file mode 100644
index 0000000000..cc4d0f118f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/rtc_api.c
@@ -0,0 +1,92 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "common_rtc.h"
+#include "nrf_drv_clock.h"
+#include "app_util_platform.h"
+
+static time_t m_time_base;
+
+void rtc_init(void)
+{
+    common_rtc_init();
+}
+
+void rtc_free(void)
+{
+    // A common counter is used for RTC, lp_ticker and us_ticker, so it can't be
+    // disabled here, but this does not cause any extra cost. Besides, currently
+    // this function is not used by RTC API in mbed-drivers.
+}
+
+int rtc_isenabled(void)
+{
+    return m_common_rtc_enabled;
+}
+
+static uint32_t rtc_seconds_get(void)
+{
+    // Convert current counter value to seconds.
+    uint32_t seconds = nrf_rtc_counter_get(COMMON_RTC_INSTANCE) / RTC_INPUT_FREQ;
+    // Add proper amount of seconds for each registered overflow of the counter.
+    uint32_t seconds_per_overflow = (1uL << RTC_COUNTER_BITS) / RTC_INPUT_FREQ;
+    return (seconds + (m_common_rtc_overflows * seconds_per_overflow));
+}
+
+time_t rtc_read(void)
+{
+    return m_time_base + rtc_seconds_get();
+}
+
+void rtc_write(time_t t)
+{
+    uint32_t seconds;
+    do {
+        seconds = rtc_seconds_get();
+        m_time_base = t - seconds;
+    // If the number of seconds indicated by the counter changed during the
+    // update of the time base, just repeat the update, now using the new
+    // number of seconds.
+    } while (seconds != rtc_seconds_get());
+}
+
+#endif // DEVICE_RTC
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.c
new file mode 100644
index 0000000000..39a60f7d1c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.c
@@ -0,0 +1,594 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "ble_advdata.h"
+#include "ble_advertising.h"
+#include "nrf_soc.h"
+#include "nrf_log.h"
+#include "pstorage.h"
+#include "fstorage.h"
+#include "sdk_common.h"
+
+
+#define ADV_LOG(...)
+
+static bool                            m_advertising_start_pending = false; /**< Flag to keep track of ongoing operations on persistent memory. */
+
+static ble_gap_addr_t                  m_peer_address;     /**< Address of the most recently connected peer, used for direct advertising. */
+static ble_advdata_t                   m_advdata;          /**< Used by the initialization function to set name, appearance, and UUIDs and advertising flags visible to peer devices. */
+static ble_adv_evt_t                   m_adv_evt;          /**< Advertising event propogated to the main application. The event is either a transaction to a new advertising mode, or a request for whitelist or peer address.. */
+static ble_advertising_evt_handler_t   m_evt_handler;      /**< Handler for the advertising events. Can be initialized as NULL if no handling is implemented on in the main application. */
+static ble_advertising_error_handler_t m_error_handler;    /**< Handler for the advertising error events. */
+
+static ble_adv_mode_t                  m_adv_mode_current; /**< Variable to keep track of the current advertising mode. */
+static ble_adv_modes_config_t          m_adv_modes_config; /**< Struct to keep track of disabled and enabled advertising modes, as well as time-outs and intervals.*/
+
+static ble_gap_whitelist_t             m_whitelist;                                         /**< Struct that points to whitelisted addresses. */
+static ble_gap_addr_t                * mp_whitelist_addr[BLE_GAP_WHITELIST_ADDR_MAX_COUNT]; /**< Pointer to a list of addresses. Pointed to by the whitelist */
+static ble_gap_irk_t                 * mp_whitelist_irk[BLE_GAP_WHITELIST_IRK_MAX_COUNT];   /**< Pointer to a list of Identity Resolving Keys (IRK). Pointed to by the whitelist */
+static bool                            m_whitelist_temporarily_disabled = false;            /**< Flag to keep track of temporary disabling of the whitelist. */
+static bool                            m_whitelist_reply_expected = false;                  /**< Flag to verify that whitelist is only set when it is requested. */
+static bool                            m_peer_addr_reply_expected = false;                  /**< Flag to verify that peer address is only set when requested. */
+
+static ble_advdata_manuf_data_t        m_manuf_specific_data;                      /**< Manufacturer specific data structure*/
+static uint8_t                         m_manuf_data_array[BLE_GAP_ADV_MAX_SIZE];   /**< Array to store the Manufacturer specific data*/
+static ble_advdata_service_data_t      m_service_data;                             /**< Service data structure. */
+static uint8_t                         m_service_data_array[BLE_GAP_ADV_MAX_SIZE]; /**< Array to store the service data. */
+static ble_advdata_conn_int_t          m_slave_conn_int;                           /**< Connection interval range structure.*/
+static int8_t                          m_tx_power_level;                           /**< TX power level*/
+
+
+/**@brief Function for checking that the whitelist has entries.
+ */
+static bool whitelist_has_entries(ble_gap_whitelist_t const * whitelist)
+{
+    if ((whitelist->addr_count != 0) || (whitelist->irk_count != 0))
+    {
+        return true;
+    }
+    return false;
+}
+
+
+/**@brief Function for setting the stored peer address back to zero.
+ */
+static void ble_advertising_peer_address_clear()
+{
+    memset(&m_peer_address, 0, sizeof(m_peer_address));
+}
+
+
+/**@brief Function for checking if an address is non-zero. Used to determine if 
+ */
+static bool peer_address_exists(uint8_t const * address)
+{
+    uint32_t i;
+
+    for (i = 0; i < BLE_GAP_ADDR_LEN; i++)
+    {
+        if (address[i] != 0)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+
+uint32_t ble_advertising_init(ble_advdata_t const                 * p_advdata,
+                              ble_advdata_t const                 * p_srdata,
+                              ble_adv_modes_config_t const        * p_config,
+                              ble_advertising_evt_handler_t const   evt_handler,
+                              ble_advertising_error_handler_t const error_handler)
+{
+    uint32_t err_code;
+
+    VERIFY_PARAM_NOT_NULL(p_advdata);
+    VERIFY_PARAM_NOT_NULL(p_config);
+
+    m_adv_mode_current = BLE_ADV_MODE_IDLE;
+    m_evt_handler      = evt_handler;
+    m_error_handler    = error_handler;
+    m_adv_modes_config = *p_config;
+
+    ble_advertising_peer_address_clear();
+
+    // Prepare Whitelist. Address and IRK double pointers point to allocated arrays.
+    m_whitelist.pp_addrs = mp_whitelist_addr;
+    m_whitelist.pp_irks  = mp_whitelist_irk;
+
+    // Copy and set advertising data.
+    memset(&m_advdata, 0, sizeof(m_advdata));
+
+    // Copy advertising data.
+    m_advdata.name_type            = p_advdata->name_type;
+    m_advdata.include_appearance   = p_advdata->include_appearance;
+    m_advdata.flags                = p_advdata->flags;
+    m_advdata.short_name_len       = p_advdata->short_name_len;
+   /* 
+    if(p_advdata->uuids_complete != NULL)
+    {
+        m_advdata.uuids_complete = p_advdata->uuids_complete;
+    }
+    */
+    m_advdata.uuids_complete       = p_advdata->uuids_complete;
+    m_advdata.uuids_more_available = p_advdata->uuids_more_available;
+    m_advdata.uuids_solicited      = p_advdata->uuids_solicited;
+    
+    if(p_advdata->p_manuf_specific_data != NULL)
+    {
+        m_advdata.p_manuf_specific_data   = &m_manuf_specific_data;
+        m_manuf_specific_data.data.p_data = m_manuf_data_array;
+        m_advdata.p_manuf_specific_data->company_identifier =
+        p_advdata->p_manuf_specific_data->company_identifier;
+        m_advdata.p_manuf_specific_data->data.size = p_advdata->p_manuf_specific_data->data.size;
+        
+        for(uint32_t i = 0; i < m_advdata.p_manuf_specific_data->data.size; i++)
+        {
+            m_manuf_data_array[i] = p_advdata->p_manuf_specific_data->data.p_data[i];
+        }
+    }
+    
+    if(p_advdata->p_service_data_array != NULL)
+    {
+        m_service_data.data.p_data                   = m_service_data_array;
+        m_advdata.p_service_data_array               = &m_service_data;
+        m_advdata.p_service_data_array->data.p_data  = m_service_data_array;
+        m_advdata.p_service_data_array->data.size    = p_advdata->p_service_data_array->data.size;
+        m_advdata.p_service_data_array->service_uuid = p_advdata->p_service_data_array->service_uuid;
+
+        for(uint32_t i = 0; i < m_advdata.p_service_data_array->data.size; i++)
+        {
+            m_service_data_array[i] = p_advdata->p_service_data_array->data.p_data[i];
+        }
+
+        m_advdata.service_data_count = p_advdata->service_data_count;
+    }
+
+
+    if(p_advdata->p_slave_conn_int != NULL)
+    {
+        m_advdata.p_slave_conn_int                    = &m_slave_conn_int;
+        m_advdata.p_slave_conn_int->max_conn_interval = p_advdata->p_slave_conn_int->max_conn_interval;
+        m_advdata.p_slave_conn_int->min_conn_interval = p_advdata->p_slave_conn_int->min_conn_interval;
+    }
+    
+    if(p_advdata->p_tx_power_level != NULL)
+    {
+        m_advdata.p_tx_power_level     = &m_tx_power_level;
+        m_advdata.p_tx_power_level     = p_advdata->p_tx_power_level;
+    }
+    err_code = ble_advdata_set(&m_advdata, p_srdata);
+    return err_code;
+}
+
+/** @brief Function to determine if a flash access in in progress. If it is the case, we can not
+*          start advertising until it is finished. attempted restart
+*          in @ref ble_advertising_on_sys_evt
+*
+* @return true if a flash access is in progress, false if not.
+*/
+static bool flash_access_in_progress()
+{
+    uint32_t err_code;
+    uint32_t count = 0;
+
+    err_code = pstorage_access_status_get(&count);
+    if ((err_code != NRF_ERROR_INVALID_STATE) && (err_code != NRF_SUCCESS))
+    {
+        ADV_LOG("[ADV]: pstorage_access_status_get returned %d.\r\n", err_code);
+        return true;
+    }
+
+    if (err_code == NRF_ERROR_INVALID_STATE)
+    {
+        err_code = fs_queued_op_count_get(&count);
+        if (err_code != FS_SUCCESS)
+        {
+            return false;
+        }
+        ADV_LOG("[ADV]: fs_queued_op_count_get gives count %d.\r\n", count);
+    }
+
+    if(count != 0)
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+uint32_t ble_advertising_start(ble_adv_mode_t advertising_mode)
+{
+    uint32_t             err_code;
+    ble_gap_adv_params_t adv_params;
+
+    m_adv_mode_current = advertising_mode;
+
+    // Verify if there are any pending flash operations. If so, delay starting advertising until
+    // the flash operations are complete.
+    if(flash_access_in_progress())
+    {
+        m_advertising_start_pending = true;
+        return NRF_SUCCESS;
+    }
+
+    ADV_LOG("[ADV]: no flash operations in progress, prepare advertising.\r\n");
+    // Fetch the peer address.
+    ble_advertising_peer_address_clear();
+
+    if (  ((m_adv_modes_config.ble_adv_directed_enabled)      && (m_adv_mode_current == BLE_ADV_MODE_DIRECTED))
+        ||((m_adv_modes_config.ble_adv_directed_slow_enabled) && (m_adv_mode_current == BLE_ADV_MODE_DIRECTED))
+        ||((m_adv_modes_config.ble_adv_directed_slow_enabled) && (m_adv_mode_current == BLE_ADV_MODE_DIRECTED_SLOW))
+       )
+    {
+        if (m_evt_handler != NULL)
+        {
+            m_peer_addr_reply_expected = true;
+            m_evt_handler(BLE_ADV_EVT_PEER_ADDR_REQUEST);
+        }
+        else
+        {
+            m_peer_addr_reply_expected = false;
+        }
+    }
+
+    // If a mode is disabled, continue to the next mode. I.e fast instead of direct, slow instead of fast, idle instead of slow.
+    if (  (m_adv_mode_current == BLE_ADV_MODE_DIRECTED)
+        &&(!m_adv_modes_config.ble_adv_directed_enabled || !peer_address_exists(m_peer_address.addr)))
+    {
+        m_adv_mode_current = BLE_ADV_MODE_DIRECTED_SLOW;
+    }
+    if (  (m_adv_mode_current == BLE_ADV_MODE_DIRECTED_SLOW)
+        &&(!m_adv_modes_config.ble_adv_directed_slow_enabled || !peer_address_exists(m_peer_address.addr)))
+    {
+        m_adv_mode_current = BLE_ADV_MODE_FAST;
+    }
+    if (!m_adv_modes_config.ble_adv_fast_enabled && m_adv_mode_current == BLE_ADV_MODE_FAST)
+    {
+        m_adv_mode_current = BLE_ADV_MODE_SLOW;
+    }
+    if (!m_adv_modes_config.ble_adv_slow_enabled && m_adv_mode_current == BLE_ADV_MODE_SLOW)
+    {
+        m_adv_mode_current = BLE_ADV_MODE_IDLE;
+        m_adv_evt          = BLE_ADV_EVT_IDLE;
+    }
+
+    // Fetch the whitelist.
+    if (   (m_evt_handler != NULL)
+        && (m_adv_mode_current == BLE_ADV_MODE_FAST || m_adv_mode_current == BLE_ADV_MODE_SLOW)
+        && (m_adv_modes_config.ble_adv_whitelist_enabled)
+        && (!m_whitelist_temporarily_disabled))
+    {
+        m_whitelist_reply_expected = true;
+        m_evt_handler(BLE_ADV_EVT_WHITELIST_REQUEST);
+    }
+    else
+    {
+        m_whitelist_reply_expected = false;
+    }
+
+    // Initialize advertising parameters with default values.
+    memset(&adv_params, 0, sizeof(adv_params));
+
+    adv_params.type        = BLE_GAP_ADV_TYPE_ADV_IND;
+    adv_params.p_peer_addr = NULL;
+    adv_params.fp          = BLE_GAP_ADV_FP_ANY;
+    adv_params.p_whitelist = NULL;
+
+    // Set advertising parameters and events according to selected advertising mode.
+    switch (m_adv_mode_current)
+    {
+        case BLE_ADV_MODE_DIRECTED:
+            ADV_LOG("[ADV]: Starting direct advertisement.\r\n");
+            adv_params.p_peer_addr = &m_peer_address; // Directed advertising.
+            adv_params.type        = BLE_GAP_ADV_TYPE_ADV_DIRECT_IND;
+            adv_params.timeout     = 0;
+            adv_params.interval    = 0;
+            m_adv_evt              = BLE_ADV_EVT_DIRECTED;
+            break;
+
+        case BLE_ADV_MODE_DIRECTED_SLOW:
+            ADV_LOG("[ADV]: Starting direct advertisement.\r\n");
+            adv_params.p_peer_addr = &m_peer_address; // Directed advertising.
+            adv_params.type        = BLE_GAP_ADV_TYPE_ADV_DIRECT_IND;
+            adv_params.timeout     = m_adv_modes_config.ble_adv_directed_slow_timeout;
+            adv_params.interval    = m_adv_modes_config.ble_adv_directed_slow_interval;
+            m_adv_evt              = BLE_ADV_EVT_DIRECTED_SLOW;
+            break;
+
+        case BLE_ADV_MODE_FAST:
+            adv_params.timeout  = m_adv_modes_config.ble_adv_fast_timeout;
+            adv_params.interval = m_adv_modes_config.ble_adv_fast_interval;
+
+            if (   whitelist_has_entries(&m_whitelist)
+                && m_adv_modes_config.ble_adv_whitelist_enabled
+                && !m_whitelist_temporarily_disabled)
+            {
+                adv_params.fp          = BLE_GAP_ADV_FP_FILTER_CONNREQ;
+                adv_params.p_whitelist = &m_whitelist;
+                m_advdata.flags        = BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED;
+                err_code               = ble_advdata_set(&m_advdata, NULL);
+                VERIFY_SUCCESS(err_code);
+
+                m_adv_evt = BLE_ADV_EVT_FAST_WHITELIST;
+                ADV_LOG("[ADV]: Starting fast advertisement with whitelist.\r\n");
+            }
+            else
+            {
+                m_adv_evt = BLE_ADV_EVT_FAST;
+                ADV_LOG("[ADV]: Starting fast advertisement.\r\n");
+            }
+            break;
+
+        case BLE_ADV_MODE_SLOW:
+            adv_params.interval = m_adv_modes_config.ble_adv_slow_interval;
+            adv_params.timeout  = m_adv_modes_config.ble_adv_slow_timeout;
+
+            if (   whitelist_has_entries(&m_whitelist)
+                && m_adv_modes_config.ble_adv_whitelist_enabled
+                && !m_whitelist_temporarily_disabled)
+            {
+                adv_params.fp          = BLE_GAP_ADV_FP_FILTER_CONNREQ;
+                adv_params.p_whitelist = &m_whitelist;
+                m_advdata.flags        = BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED;
+                err_code               = ble_advdata_set(&m_advdata, NULL);
+                VERIFY_SUCCESS(err_code);
+
+                m_adv_evt = BLE_ADV_EVT_SLOW_WHITELIST;
+                ADV_LOG("[ADV]: Starting slow advertisement with whitelist.\r\n");
+            }
+            else
+            {
+                m_adv_evt = BLE_ADV_EVT_SLOW;
+                ADV_LOG("[ADV]: Starting slow advertisement.\r\n");
+            }
+            break;
+
+        default:
+            break;
+    }
+    if (m_adv_mode_current != BLE_ADV_MODE_IDLE)
+    {
+        err_code = sd_ble_gap_adv_start(&adv_params);
+        VERIFY_SUCCESS(err_code);
+    }
+    if (m_evt_handler != NULL)
+    {
+        m_evt_handler(m_adv_evt);
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+void ble_advertising_on_ble_evt(ble_evt_t const * p_ble_evt)
+{
+    static uint16_t current_slave_link_conn_handle = BLE_CONN_HANDLE_INVALID;
+
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            if (p_ble_evt->evt.gap_evt.params.connected.role == BLE_GAP_ROLE_PERIPH)
+            {
+                current_slave_link_conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
+            }
+            break;
+
+        // Upon disconnection, whitelist will be activated and direct advertising is started.
+        case BLE_GAP_EVT_DISCONNECTED:
+        {
+            uint32_t err_code;
+            m_whitelist_temporarily_disabled = false;
+
+            if (p_ble_evt->evt.gap_evt.conn_handle == current_slave_link_conn_handle)
+            {
+               err_code = ble_advertising_start(BLE_ADV_MODE_DIRECTED);
+               if ((err_code != NRF_SUCCESS) && (m_error_handler != NULL))
+               {
+                   m_error_handler(err_code);
+               }
+            }
+            break;
+        }
+        // Upon time-out, the next advertising mode is started, i.e. go from fast to slow or from slow to idle.
+        case BLE_GAP_EVT_TIMEOUT:
+            if (p_ble_evt->evt.gap_evt.params.timeout.src == BLE_GAP_TIMEOUT_SRC_ADVERTISING)
+            {
+                switch (m_adv_mode_current)
+                {
+                    case BLE_ADV_MODE_DIRECTED:
+                        ADV_LOG("[ADV]: Timed out from directed advertising.\r\n");
+                        {
+                            uint32_t err_code;
+                            err_code = ble_advertising_start(BLE_ADV_MODE_DIRECTED_SLOW);
+                            if ((err_code != NRF_SUCCESS) && (m_error_handler != NULL))
+                            {
+                                m_error_handler(err_code);
+                            }
+                        }
+                        break;
+                    case BLE_ADV_MODE_DIRECTED_SLOW:
+                        ADV_LOG("[ADV]: Timed out from directed slow advertising.\r\n");
+                        {
+                            uint32_t err_code;
+                            err_code = ble_advertising_start(BLE_ADV_MODE_FAST);
+                            if ((err_code != NRF_SUCCESS) && (m_error_handler != NULL))
+                            {
+                                m_error_handler(err_code);
+                            }
+                        }
+                        break;
+                    case BLE_ADV_MODE_FAST:
+                    {
+                        uint32_t err_code;
+                        m_adv_evt = BLE_ADV_EVT_FAST;
+                        ADV_LOG("[ADV]: Timed out from fast advertising, starting slow advertising.\r\n");
+                        err_code = ble_advertising_start(BLE_ADV_MODE_SLOW);
+                        if ((err_code != NRF_SUCCESS) && (m_error_handler != NULL))
+                        {
+                            m_error_handler(err_code);
+                        }
+                        break;
+                    }
+                    case BLE_ADV_MODE_SLOW:
+                        m_adv_evt = BLE_ADV_EVT_IDLE;
+                        ADV_LOG("[ADV]: Timed out from slow advertising, stopping advertising.\r\n");
+                        if (m_evt_handler != NULL)
+                        {
+                            m_evt_handler(m_adv_evt);
+                        }
+                        break;
+
+                    default:
+                        // No implementation needed.
+                        break;
+                }
+            }
+            break;
+
+        default:
+            // No implementation needed.
+            break;
+    }
+}
+void ble_advertising_on_sys_evt(uint32_t sys_evt)
+{
+    uint32_t err_code = NRF_SUCCESS;
+    switch (sys_evt)
+    {
+
+        case NRF_EVT_FLASH_OPERATION_SUCCESS:
+        // Fall through.
+
+        //When a flash operation finishes, advertising no longer needs to be pending.
+        case NRF_EVT_FLASH_OPERATION_ERROR:
+            if (m_advertising_start_pending)
+            {
+                m_advertising_start_pending = false;
+                err_code = ble_advertising_start(m_adv_mode_current);
+                if ((err_code != NRF_SUCCESS) && (m_error_handler != NULL))
+                {
+                    m_error_handler(err_code);
+                }
+            }
+            break;
+
+        default:
+            // No implementation needed.
+            break;
+    }
+}
+
+uint32_t ble_advertising_peer_addr_reply(ble_gap_addr_t * p_peer_address)
+{
+    if(m_peer_addr_reply_expected == false)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    m_peer_address.addr_type = p_peer_address->addr_type;
+
+    for (int i = 0; i < BLE_GAP_ADDR_LEN; i++)
+    {
+        m_peer_address.addr[i] = p_peer_address->addr[i];
+    }
+
+    m_peer_addr_reply_expected = false;
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advertising_whitelist_reply(ble_gap_whitelist_t * p_whitelist)
+{
+    uint32_t i;
+
+    if(m_whitelist_reply_expected == false)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    m_whitelist.addr_count = p_whitelist->addr_count;
+    m_whitelist.irk_count  = p_whitelist->irk_count;
+
+    for (i = 0; i < m_whitelist.irk_count; i++)
+    {
+        mp_whitelist_irk[i] = p_whitelist->pp_irks[i];
+    }
+
+    for (i = 0; i < m_whitelist.addr_count; i++)
+    {
+        mp_whitelist_addr[i] = p_whitelist->pp_addrs[i];
+    }
+
+    m_whitelist_reply_expected = false;
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advertising_restart_without_whitelist(void)
+{
+    uint32_t err_code;
+
+    if(     m_adv_modes_config.ble_adv_whitelist_enabled == BLE_ADV_WHITELIST_ENABLED
+        && !m_whitelist_temporarily_disabled)
+    {
+        if (m_adv_mode_current != BLE_ADV_MODE_IDLE)
+        {
+            err_code = sd_ble_gap_adv_stop();
+            VERIFY_SUCCESS(err_code);
+        }
+        m_whitelist_temporarily_disabled = true;
+        m_advdata.flags                  = BLE_GAP_ADV_FLAGS_LE_ONLY_GENERAL_DISC_MODE;
+        err_code                         = ble_advdata_set(&m_advdata, NULL);
+        VERIFY_SUCCESS(err_code);
+
+        err_code = ble_advertising_start(m_adv_mode_current);
+        if ((err_code != NRF_SUCCESS) && (m_error_handler != NULL))
+        {
+            m_error_handler(err_code);
+        }
+    }
+    return NRF_SUCCESS;
+}
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.h
new file mode 100644
index 0000000000..c806399eb4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_advertising/ble_advertising.h
@@ -0,0 +1,251 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+/**@file
+ *
+ * @defgroup ble_sdk_lib_advertising Advertising Module
+ * @{
+ * @ingroup  ble_sdk_lib
+ * @brief    Module for handling connectable BLE advertising.
+ *
+ * @details  The Advertising Module handles connectable advertising for your application. It can
+ *           be configured with advertising modes to suit most typical use cases.
+ *           Your main application can react to changes in advertising modes
+ *           if an event handler is provided.
+ *
+ * @note     The Advertising Module supports only applications with a single peripheral link.
+ *
+ * The application must propagate BLE stack events to this module by calling
+ * @ref ble_advertising_on_ble_evt() and system events by calling
+ * @ref ble_advertising_on_sys_evt().
+ *
+ */
+
+#ifndef BLE_ADVERTISING_H__
+#define BLE_ADVERTISING_H__
+
+#include <stdint.h>
+#include "nrf_ble_gattc.h"
+#include "nrf_ble.h"
+#include "nrf_error.h"
+#include "ble_advdata.h"
+
+/**@brief Advertising modes.
+*/
+typedef enum
+{
+    BLE_ADV_MODE_IDLE,          /**< Idle; no connectable advertising is ongoing.*/
+    BLE_ADV_MODE_DIRECTED,      /**< Directed advertising attempts to connect to the most recently disconnected peer. */
+    BLE_ADV_MODE_DIRECTED_SLOW, /**< Directed advertising (low duty cycle) attempts to connect to the most recently disconnected peer. */
+    BLE_ADV_MODE_FAST,          /**< Fast advertising will connect to any peer device, or filter with a whitelist if one exists. */
+    BLE_ADV_MODE_SLOW,          /**< Slow advertising is similar to fast advertising. By default, it uses a longer advertising interval and time-out than fast advertising. However, these options are defined by the user. */
+} ble_adv_mode_t;
+
+/**@brief Advertising events.
+ *
+ * @details These events are propagated to the main application if a handler was provided during
+ *          initialization of the Advertising Module. Events for modes that are not used can be
+ *          ignored. Similarly, BLE_ADV_EVT_WHITELIST_REQUEST and BLE_ADV_EVT_PEER_ADDR_REQUEST
+ *          can be ignored if whitelist and direct advertising is not used.
+ */
+typedef enum
+{
+    BLE_ADV_EVT_IDLE,                /**< Idle; no connectable advertising is ongoing.*/
+    BLE_ADV_EVT_DIRECTED,            /**< Direct advertising mode has started. */
+    BLE_ADV_EVT_DIRECTED_SLOW,       /**< Directed advertising (low duty cycle) has started. */
+    BLE_ADV_EVT_FAST,                /**< Fast advertising mode has started. */
+    BLE_ADV_EVT_SLOW,                /**< Slow advertising mode has started.*/
+    BLE_ADV_EVT_FAST_WHITELIST,      /**< Fast advertising mode using the whitelist has started. */
+    BLE_ADV_EVT_SLOW_WHITELIST,      /**< Slow advertising mode using the whitelist has started.*/
+    BLE_ADV_EVT_WHITELIST_REQUEST,   /**< Request a whitelist from the main application. For whitelist advertising to work, the whitelist must be set when this event occurs. */
+    BLE_ADV_EVT_PEER_ADDR_REQUEST    /**< Request a peer address from the main application. For directed advertising to work, the peer address must be set when this event occurs. */
+} ble_adv_evt_t;
+
+/**@brief Options for the different advertisement modes.
+ *
+ * @details This structure is used to enable or disable advertising modes and to configure time-out
+ *          periods and advertising intervals.
+ */
+typedef struct
+{
+    bool     ble_adv_whitelist_enabled;       /**< Enable or disable use of the whitelist. */
+    bool     ble_adv_directed_enabled;        /**< Enable or disable direct advertising mode. */
+    bool     ble_adv_directed_slow_enabled;   /**< Enable or disable direct advertising mode. */
+    uint32_t ble_adv_directed_slow_interval;  /**< Advertising interval for directed advertising. */
+    uint32_t ble_adv_directed_slow_timeout;   /**< Time-out (number of tries) for direct advertising. */
+    bool     ble_adv_fast_enabled;            /**< Enable or disable fast advertising mode. */
+    uint32_t ble_adv_fast_interval;           /**< Advertising interval for fast advertising. */
+    uint32_t ble_adv_fast_timeout;            /**< Time-out (in seconds) for fast advertising. */
+    bool     ble_adv_slow_enabled;            /**< Enable or disable slow advertising mode. */
+    uint32_t ble_adv_slow_interval;           /**< Advertising interval for slow advertising. */
+    uint32_t ble_adv_slow_timeout;            /**< Time-out (in seconds) for slow advertising. */
+}ble_adv_modes_config_t;
+
+
+/**@brief BLE advertising event handler type. */
+typedef void (*ble_advertising_evt_handler_t) (ble_adv_evt_t const adv_evt);
+
+/**@brief BLE advertising error handler type. */
+typedef void (*ble_advertising_error_handler_t) (uint32_t nrf_error);
+
+/**@brief Initialization parameters for the Advertising Module.
+ * @details This structure is used to pass advertising options, advertising data, and an event handler to the Advertising Module during initialization. */
+typedef struct
+{
+    ble_adv_modes_config_t        options;     /**< Parameters for advertising modes.*/
+    ble_advdata_t                 advdata;     /**< Advertising data. */
+    ble_advertising_evt_handler_t evt_handler; /**< Event handler. */
+}ble_adv_init_t;
+
+
+/* Defines to make the mode options easier to set during advertising init.*/
+#define BLE_ADV_DIRECTED_ENABLED       true
+#define BLE_ADV_DIRECTED_DISABLED      false
+
+#define BLE_ADV_DIRECTED_SLOW_ENABLED  true
+#define BLE_ADV_DIRECTED_SLOW_DISABLED false
+
+#define BLE_ADV_FAST_ENABLED           true
+#define BLE_ADV_FAST_DISABLED          false
+
+#define BLE_ADV_SLOW_ENABLED           true
+#define BLE_ADV_SLOW_DISABLED          false
+
+#define BLE_ADV_WHITELIST_ENABLED      true
+#define BLE_ADV_WHITELIST_DISABLED     false
+
+
+/**@brief Function for handling BLE events.
+ *
+ * @details This function must be called from the BLE stack event dispatcher for
+ *          the module to handle BLE events that are relevant for the Advertising Module.
+ *
+ * @param[in] p_ble_evt BLE stack event.
+ */
+void ble_advertising_on_ble_evt(const ble_evt_t * const p_ble_evt);
+
+
+/**@brief Function for handling system events.
+ *
+ * @details This function must be called to handle system events that are relevant
+ *          for the Advertising Module. Specifically, the advertising module can not use the
+ *          softdevice as long as there are pending writes to the flash memory. This
+ *          event handler is designed to delay advertising until there is no flash operation.
+ *
+ * @param[in] sys_evt  System event.
+ */
+void ble_advertising_on_sys_evt(uint32_t sys_evt);
+
+
+/**@brief Function for initializing the Advertising Module.
+ *
+ * @details Encodes the required advertising data and passes it to the stack.
+ *          Also builds a structure to be passed to the stack when starting advertising.
+ *          The supplied advertising data is copied to a local structure and is manipulated
+ *          depending on what advertising modes are started in @ref ble_advertising_start.
+ *
+ * @param[in] p_advdata     Advertising data: name, appearance, discovery flags, and more.
+ * @param[in] p_srdata      Scan response data: Supplement to advertising data.
+ * @param[in] p_config      Select which advertising modes and intervals will be utilized.
+ * @param[in] evt_handler   Event handler that will be called upon advertising events.
+ * @param[in] error_handler Error handler that will propogate internal errors to the main applications.
+ *
+ * @retval NRF_SUCCESS If initialization was successful. Otherwise, an error code is returned.
+ */
+uint32_t ble_advertising_init(ble_advdata_t const                 * p_advdata,
+                              ble_advdata_t const                 * p_srdata,
+                              ble_adv_modes_config_t const        * p_config,
+                              ble_advertising_evt_handler_t const   evt_handler,
+                              ble_advertising_error_handler_t const error_handler);
+
+
+/**@brief Function for starting advertising.
+ *
+ * @details You can start advertising in any of the advertising modes that you enabled
+ *          during initialization.
+ *
+ * @param[in] advertising_mode  Advertising mode.
+ *
+ * @retval @ref NRF_SUCCESS On success, else an error code indicating reason for failure.
+ * @retval @ref NRF_ERROR_INVALID_STATE
+ */
+uint32_t ble_advertising_start(ble_adv_mode_t advertising_mode);
+
+/**@brief Function for setting the peer address.
+ *
+ * @details The peer address must be set by the application upon receiving a
+ *          @ref BLE_ADV_EVT_PEER_ADDR_REQUEST event. Without the peer address, the directed
+ *          advertising mode will not be run.
+ *
+ * @param[in] p_peer_addr  Pointer to a peer address.
+ *
+ * @retval @ref NRF_SUCCESS Successfully stored the peer address pointer in the advertising module.
+ * @retval @ref NRF_ERROR_INVALID_STATE If a reply was not expected.
+ */
+uint32_t ble_advertising_peer_addr_reply(ble_gap_addr_t * p_peer_addr);
+
+
+/**@brief Function for setting a whitelist.
+ *
+ * @details The whitelist must be set by the application upon receiving a
+ *          @ref BLE_ADV_EVT_WHITELIST_REQUEST event. Without the whitelist, the whitelist
+ *          advertising for fast and slow modes will not be run.
+ *
+ * @param[in] p_whitelist  Pointer to a whitelist.
+ *
+ * @retval @ref NRF_SUCCESS Successfully stored pointers to the whitelist into the advertising module.
+ * @retval @ref NRF_ERROR_INVALID_STATE If a reply was not expected.
+ */
+uint32_t ble_advertising_whitelist_reply(ble_gap_whitelist_t * p_whitelist);
+
+
+/**@brief Function for disabling whitelist advertising.
+ *
+ * @details This function temporarily disables whitelist advertising.
+ *          Calling this function resets the current time-out countdown.
+ *
+ * @retval @ref NRF_SUCCESS On success, else an error message propogated from the Softdevice.
+ */
+uint32_t ble_advertising_restart_without_whitelist(void);
+/** @} */
+
+#endif // BLE_ADVERTISING_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.c
new file mode 100644
index 0000000000..d2a7b0b213
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.c
@@ -0,0 +1,967 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_db_discovery.h"
+#include <stdlib.h>
+#include "nrf_ble.h"
+#include "nrf_log.h"
+
+#include "sdk_common.h"
+
+#define SRV_DISC_START_HANDLE  0x0001                    /**< The start handle value used during service discovery. */
+#define DB_DISCOVERY_MAX_USERS BLE_DB_DISCOVERY_MAX_SRV  /**< The maximum number of users/registrations allowed by this module. */
+#define DB_LOG                 NRF_LOG_PRINTF_DEBUG      /**< A debug logger macro that can be used in this file to do logging information over UART. */
+
+
+/**@brief Array of structures containing information about the registered application modules. */
+static ble_uuid_t m_registered_handlers[DB_DISCOVERY_MAX_USERS];
+
+
+/**@brief   Array of structures containing pending events to be sent to the application modules.
+ *
+ * @details Whenever a discovery related event is to be raised to a user module, it will be stored
+ *          in this array first. When all services needed to be discovered have been
+ *          discovered, all pending events will be sent to the corresponding user modules.
+ **/
+static struct
+{
+    ble_db_discovery_evt_t         evt;          /**< The pending event. */
+    ble_db_discovery_evt_handler_t evt_handler;  /**< The event handler which should be called to raise this event. */
+} m_pending_user_evts[DB_DISCOVERY_MAX_USERS];
+
+static ble_db_discovery_evt_handler_t m_evt_handler;
+static uint32_t m_pending_usr_evt_index;    /**< The index to the pending user event array, pointing to the last added pending user event. */
+static uint32_t m_num_of_handlers_reg;      /**< The number of handlers registered with the DB Discovery module. */
+static bool     m_initialized = false;      /**< This variable Indicates if the module is initialized or not. */
+
+#define MODULE_INITIALIZED (m_initialized == true)
+#include "sdk_macros.h"
+
+/**@brief     Function for fetching the event handler provided by a registered application module.
+ *
+ * @param[in] srv_uuid UUID of the service.
+ *
+ * @retval    evt_handler Event handler of the module, registered for the given service UUID.
+ * @retval    NULL If no event handler is found.
+ */
+static ble_db_discovery_evt_handler_t registered_handler_get(const ble_uuid_t * const p_srv_uuid)
+{
+    uint32_t i;
+
+    for (i = 0; i < m_num_of_handlers_reg; i++)
+    {
+        if (BLE_UUID_EQ(&(m_registered_handlers[i]), p_srv_uuid))
+        {
+            return (m_evt_handler);
+        }
+    }
+
+    return NULL;
+}
+
+
+/**@brief     Function for storing the event handler provided by a registered application module.
+ *
+ * @param[in] p_srv_uuid    The UUID of the service.
+ * @param[in] p_evt_handler The event handler provided by the application.
+ *
+ * @retval    NRF_SUCCESS If the handler was stored or already present in the list.
+ * @retval    NRF_ERROR_NO_MEM If there is no space left to store the handler.
+ */
+static uint32_t registered_handler_set(const ble_uuid_t * const       p_srv_uuid,
+                                       ble_db_discovery_evt_handler_t p_evt_handler)
+{
+    if (registered_handler_get(p_srv_uuid) != NULL)
+    {
+        return NRF_SUCCESS;
+    }
+    if (m_num_of_handlers_reg < DB_DISCOVERY_MAX_USERS)
+    {
+        m_registered_handlers[m_num_of_handlers_reg] = *p_srv_uuid;
+
+        m_num_of_handlers_reg++;
+
+        return NRF_SUCCESS;
+    }
+    else
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+}
+
+
+/**@brief Function for sending all pending discovery events to the corresponding user modules.
+ */
+static void pending_user_evts_send(void)
+{
+    uint32_t i = 0;
+
+    for (i = 0; i < m_num_of_handlers_reg; i++)
+    {
+        // Pass the event to the corresponding event handler.
+        m_pending_user_evts[i].evt_handler(&(m_pending_user_evts[i].evt));
+    }
+    m_pending_usr_evt_index = 0;
+}
+
+
+/**@brief     Function for indicating error to the application.
+ *
+ * @details   This function will fetch the event handler based on the UUID of the service being
+ *            discovered. (The event handler is registered by the application beforehand).
+ *            The error code is added to the pending events together with the event handler.
+ *            If no event handler was found, then this function will do nothing.
+ *
+ * @param[in] p_db_discovery Pointer to the DB discovery structure.
+ * @param[in] err_code       Error code that should be provided to the application.
+ * @param[in] conn_handle    Connection Handle.
+ *
+ */
+static void discovery_error_evt_trigger(ble_db_discovery_t * const p_db_discovery,
+                                        uint32_t                   err_code,
+                                        uint16_t const             conn_handle)
+{
+    ble_db_discovery_evt_handler_t p_evt_handler;
+    ble_gatt_db_srv_t            * p_srv_being_discovered;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_evt_handler = registered_handler_get(&(p_srv_being_discovered->srv_uuid));
+
+    if (p_evt_handler != NULL)
+    {
+        ble_db_discovery_evt_t evt;
+
+        evt.conn_handle     = conn_handle;
+        evt.evt_type        = BLE_DB_DISCOVERY_ERROR;
+        evt.params.err_code = err_code;
+
+        p_evt_handler(&evt);
+    }
+}
+
+
+/**@brief     Function for triggering a Discovery Complete or Service Not Found event to the
+ *            application.
+ *
+ * @details   This function will fetch the event handler based on the UUID of the service being
+ *            discovered. (The event handler is registered by the application beforehand).
+ *            It then triggers an event indicating the completion of the service discovery.
+ *            If no event handler was found, then this function will do nothing.
+ *
+ * @param[in] p_db_discovery Pointer to the DB discovery structure.
+ * @param[in] is_srv_found   Variable to indicate if the service was found at the peer.
+ * @param[in] conn_handle    Connection Handle.
+ */
+static void discovery_complete_evt_trigger(ble_db_discovery_t * const p_db_discovery,
+                                           bool                       is_srv_found,
+                                           uint16_t const             conn_handle)
+{
+    ble_db_discovery_evt_handler_t p_evt_handler;
+    ble_gatt_db_srv_t            * p_srv_being_discovered;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_evt_handler = registered_handler_get(&(p_srv_being_discovered->srv_uuid));
+
+    if (p_evt_handler != NULL)
+    {
+        if (m_pending_usr_evt_index < DB_DISCOVERY_MAX_USERS)
+        {
+            // Insert an event into the pending event list.
+            m_pending_user_evts[m_pending_usr_evt_index].evt.conn_handle = conn_handle;
+
+            m_pending_user_evts[m_pending_usr_evt_index].evt.params.discovered_db =
+                *p_srv_being_discovered;
+            if (is_srv_found)
+            {
+                m_pending_user_evts[m_pending_usr_evt_index].evt.evt_type =
+                    BLE_DB_DISCOVERY_COMPLETE;
+            }
+            else
+            {
+                m_pending_user_evts[m_pending_usr_evt_index].evt.evt_type =
+                    BLE_DB_DISCOVERY_SRV_NOT_FOUND;
+            }
+            m_pending_user_evts[m_pending_usr_evt_index].evt_handler = p_evt_handler;
+
+            m_pending_usr_evt_index++;
+
+            if (m_pending_usr_evt_index == m_num_of_handlers_reg)
+            {
+                // All registered modules have pending events. Send all pending events to the user
+                // modules.
+                pending_user_evts_send();
+            }
+            else
+            {
+                // Too many events pending. Do nothing. (Ideally this should not happen.)
+            }
+        }
+    }
+}
+
+
+/**@brief     Function for handling service discovery completion.
+ *
+ * @details   This function will be used to determine if there are more services to be discovered,
+ *            and if so, initiate the discovery of the next service.
+ *
+ * @param[in] p_db_discovery Pointer to the DB Discovery Structure.
+ * @param[in] conn_handle    Connection Handle.
+ */
+static void on_srv_disc_completion(ble_db_discovery_t * p_db_discovery,
+                                   uint16_t const       conn_handle)
+{
+    p_db_discovery->discoveries_count++;
+
+    // Check if more services need to be discovered.
+    if (p_db_discovery->discoveries_count < m_num_of_handlers_reg)
+    {
+        // Reset the current characteristic index since a new service discovery is about to start.
+        p_db_discovery->curr_char_ind = 0;
+
+        // Initiate discovery of the next service.
+        p_db_discovery->curr_srv_ind++;
+
+        ble_gatt_db_srv_t * p_srv_being_discovered;
+
+        p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+        p_srv_being_discovered->srv_uuid = m_registered_handlers[p_db_discovery->curr_srv_ind];
+
+        // Reset the characteristic count in the current service to zero since a new service
+        // discovery is about to start.
+        p_srv_being_discovered->char_count = 0;
+
+        DB_LOG("[DB]: Starting discovery of service with UUID 0x%x for Connection handle %d\r\n",
+               p_srv_being_discovered->srv_uuid.uuid, conn_handle);
+
+        uint32_t err_code;
+
+        err_code = sd_ble_gattc_primary_services_discover
+                   (
+                   conn_handle,
+                   SRV_DISC_START_HANDLE,
+                   &(p_srv_being_discovered->srv_uuid)
+                   );
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            // Error with discovering the service.
+            // Indicate the error to the registered user application.
+            discovery_error_evt_trigger(p_db_discovery, err_code, conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = conn_handle;
+//            m_evt_handler(&m_pending_user_evts[0].evt);
+
+            return;
+        }
+    }
+    else
+    {
+        // No more service discovery is needed.
+        p_db_discovery->discovery_in_progress  = false;
+        m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+        m_pending_user_evts[0].evt.conn_handle = conn_handle;
+        //m_evt_handler(&m_pending_user_evts[0].evt);
+    }
+}
+
+
+/**@brief     Function for finding out if a characteristic discovery should be performed after the
+ *            last discovered characteristic.
+ *
+ * @details   This function is used during the time of database discovery to find out if there is
+ *            a need to do more characteristic discoveries. The value handles of the
+ *            last discovered characteristic is compared with the end handle of the service.
+ *            If the service handle is greater than one of the former characteristic handles,
+ *            it means that a characteristic discovery is required.
+ *
+ * @param[in] p_db_discovery The pointer to the DB Discovery structure.
+ * @param[in] p_after_char   The pointer to the last discovered characteristic.
+ *
+ * @retval    True if a characteristic discovery is required.
+ * @retval    False if a characteristic discovery is NOT required.
+ */
+static bool is_char_discovery_reqd(ble_db_discovery_t * const p_db_discovery,
+                                   ble_gattc_char_t         * p_after_char)
+{
+    if (
+        p_after_char->handle_value <
+        p_db_discovery->services[p_db_discovery->curr_srv_ind].handle_range.end_handle
+       )
+    {
+        // Handle value of the characteristic being discovered is less than the end handle of
+        // the service being discovered. There is a possibility of more characteristics being
+        // present. Hence a characteristic discovery is required.
+        return true;
+    }
+
+    return false;
+}
+
+
+/**@brief      Function to find out if a descriptor discovery is required.
+ *
+ * @details    This function finds out if there is a possibility of existence of descriptors between
+ *             current characteristic and the next characteristic. If so, this function will compute
+ *             the handle range on which the descriptors may be present and will return it.
+ *             If the current characteristic is the last known characteristic, then this function
+ *             will use the service end handle to find out if the current characteristic can have
+ *             descriptors.
+ *
+ * @param[in]  p_db_discovery Pointer to the DB Discovery structure.
+ * @param[in]  p_curr_char    Pointer to the current characteristic.
+ * @param[in]  p_next_char    Pointer to the next characteristic. This should be NULL if the
+ *                            caller knows that there is no characteristic after the current
+ *                            characteristic at the peer.
+ * @param[out] p_handle_range Pointer to the handle range in which descriptors may exist at the
+ *                            the peer.
+ *
+ * @retval     True If a descriptor discovery is required.
+ * @retval     False If a descriptor discovery is NOT required.
+ */
+static bool is_desc_discovery_reqd(ble_db_discovery_t       * p_db_discovery,
+                                   ble_gatt_db_char_t       * p_curr_char,
+                                   ble_gatt_db_char_t       * p_next_char,
+                                   ble_gattc_handle_range_t * p_handle_range)
+{
+    if (p_next_char == NULL)
+    {
+        // Current characteristic is the last characteristic in the service. Check if the value
+        // handle of the current characteristic is equal to the service end handle.
+        if (
+            p_curr_char->characteristic.handle_value ==
+            p_db_discovery->services[p_db_discovery->curr_srv_ind].handle_range.end_handle
+           )
+        {
+            // No descriptors can be present for the current characteristic. p_curr_char is the last
+            // characteristic with no descriptors.
+            return false;
+        }
+
+        p_handle_range->start_handle = p_curr_char->characteristic.handle_value + 1;
+
+        // Since the current characteristic is the last characteristic in the service, the end
+        // handle should be the end handle of the service.
+        p_handle_range->end_handle =
+            p_db_discovery->services[p_db_discovery->curr_srv_ind].handle_range.end_handle;
+
+        return true;
+    }
+
+    // p_next_char != NULL. Check for existence of descriptors between the current and the next
+    // characteristic.
+    if ((p_curr_char->characteristic.handle_value + 1) == p_next_char->characteristic.handle_decl)
+    {
+        // No descriptors can exist between the two characteristic.
+        return false;
+    }
+
+    p_handle_range->start_handle = p_curr_char->characteristic.handle_value + 1;
+    p_handle_range->end_handle   = p_next_char->characteristic.handle_decl - 1;
+
+    return true;
+}
+
+
+/**@brief     Function for performing characteristic discovery.
+ *
+ * @param[in] p_db_discovery Pointer to the DB Discovery structure.
+ * @param[in] conn_handle    Connection Handle.
+ *
+ * @return    NRF_SUCCESS if the SoftDevice was successfully requested to perform the characteristic
+ *            discovery. Otherwise an error code. This function returns the error code returned
+ *            by the SoftDevice API @ref sd_ble_gattc_characteristics_discover.
+ */
+static uint32_t characteristics_discover(ble_db_discovery_t * const p_db_discovery,
+                                         uint16_t const             conn_handle)
+{
+    ble_gatt_db_srv_t      * p_srv_being_discovered;
+    ble_gattc_handle_range_t handle_range;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    if (p_db_discovery->curr_char_ind != 0)
+    {
+        // This is not the first characteristic being discovered. Hence the 'start handle' to be
+        // used must be computed using the handle_value of the previous characteristic.
+        ble_gattc_char_t * p_prev_char;
+        uint8_t            prev_char_ind = p_db_discovery->curr_char_ind - 1;
+
+        p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+        p_prev_char = &(p_srv_being_discovered->charateristics[prev_char_ind].characteristic);
+
+        handle_range.start_handle = p_prev_char->handle_value + 1;
+    }
+    else
+    {
+        // This is the first characteristic of this service being discovered.
+        handle_range.start_handle = p_srv_being_discovered->handle_range.start_handle;
+    }
+
+    handle_range.end_handle = p_srv_being_discovered->handle_range.end_handle;
+
+    return sd_ble_gattc_characteristics_discover(conn_handle, &handle_range);
+}
+
+
+/**@brief      Function for performing descriptor discovery, if required.
+ *
+ * @details    This function will check if descriptor discovery is required and then perform it if
+ *             needed. If no more descriptor discovery is required for the service, then the output
+ *             parameter p_raise_discov_complete is set to true, indicating to the caller that a
+ *             discovery complete event can be triggered to the application.
+ *
+ * @param[in]  p_db_discovery           Pointer to the DB Discovery structure.
+ * @param[out] p_raise_discov_complete  The value pointed to by this pointer will be set to true if
+ *                                      the Discovery Complete event can be triggered to the
+ *                                      application.
+ * @param[in] conn_handle               Connection Handle.
+ *
+ * @return     NRF_SUCCESS if the SoftDevice was successfully requested to perform the descriptor
+ *             discovery, or if no more descriptor discovery is required. Otherwise an error code.
+ *             This function returns the error code returned by the SoftDevice API @ref
+ *             sd_ble_gattc_descriptors_discover.
+ */
+static uint32_t descriptors_discover(ble_db_discovery_t * const p_db_discovery,
+                                     bool *                     p_raise_discov_complete,
+                                     uint16_t const             conn_handle)
+{
+    ble_gattc_handle_range_t   handle_range;
+    ble_gatt_db_char_t       * p_curr_char_being_discovered;
+    ble_gatt_db_srv_t        * p_srv_being_discovered;
+    bool                       is_discovery_reqd = false;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_curr_char_being_discovered =
+        &(p_srv_being_discovered->charateristics[p_db_discovery->curr_char_ind]);
+
+    if ((p_db_discovery->curr_char_ind + 1) == p_srv_being_discovered->char_count)
+    {
+        // This is the last characteristic of this service.
+        is_discovery_reqd = is_desc_discovery_reqd(p_db_discovery,
+                                                   p_curr_char_being_discovered,
+                                                   NULL,
+                                                   &handle_range);
+    }
+    else
+    {
+        uint8_t                   i;
+        ble_gatt_db_char_t * p_next_char;
+
+        for (i = p_db_discovery->curr_char_ind;
+             i < p_srv_being_discovered->char_count;
+             i++)
+        {
+
+            if (i == (p_srv_being_discovered->char_count - 1))
+            {
+                // The current characteristic is the last characteristic in the service.
+                p_next_char = NULL;
+            }
+            else
+            {
+                p_next_char = &(p_srv_being_discovered->charateristics[i + 1]);
+            }
+
+            // Check if it is possible for the current characteristic to have a descriptor.
+            if (is_desc_discovery_reqd(p_db_discovery,
+                                       p_curr_char_being_discovered,
+                                       p_next_char,
+                                       &handle_range))
+            {
+                is_discovery_reqd = true;
+                break;
+            }
+            else
+            {
+                // No descriptors can exist.
+                p_curr_char_being_discovered = p_next_char;
+                p_db_discovery->curr_char_ind++;
+            }
+        }
+    }
+
+    if (!is_discovery_reqd)
+    {
+        // No more descriptor discovery required. Discovery is complete.
+        // This informs the caller that a discovery complete event can be triggered.
+        *p_raise_discov_complete = true;
+
+        return NRF_SUCCESS;
+    }
+
+    *p_raise_discov_complete = false;
+
+    return sd_ble_gattc_descriptors_discover(conn_handle, &handle_range);
+}
+
+
+/**@brief     Function for handling primary service discovery response.
+ *
+ * @details   This function will handle the primary service discovery response and start the
+ *            discovery of characteristics within that service.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GATT Client event.
+ */
+static void on_primary_srv_discovery_rsp(ble_db_discovery_t * const    p_db_discovery,
+                                         const ble_gattc_evt_t * const p_ble_gattc_evt)
+{
+    ble_gatt_db_srv_t                        * p_srv_being_discovered;
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    if (p_ble_gattc_evt->conn_handle != p_db_discovery->conn_handle)
+    {
+        return;
+    }
+    if (p_ble_gattc_evt->gatt_status == BLE_GATT_STATUS_SUCCESS)
+    {
+        uint32_t err_code;
+        const ble_gattc_evt_prim_srvc_disc_rsp_t * p_prim_srvc_disc_rsp_evt;
+
+        DB_LOG("Found service UUID 0x%x\r\n", p_srv_being_discovered->srv_uuid.uuid);
+
+        p_prim_srvc_disc_rsp_evt = &(p_ble_gattc_evt->params.prim_srvc_disc_rsp);
+
+        p_srv_being_discovered->srv_uuid     = p_prim_srvc_disc_rsp_evt->services[0].uuid;
+        p_srv_being_discovered->handle_range = p_prim_srvc_disc_rsp_evt->services[0].handle_range;
+
+        err_code = characteristics_discover(p_db_discovery,
+                                            p_ble_gattc_evt->conn_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            // Error with discovering the service.
+            // Indicate the error to the registered user application.
+            discovery_error_evt_trigger(p_db_discovery,
+                                        err_code,
+                                        p_ble_gattc_evt->conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+            //m_evt_handler(&m_pending_user_evts[0].evt);
+        }
+    }
+    else
+    {
+        DB_LOG("Service UUID 0x%x Not found\r\n", p_srv_being_discovered->srv_uuid.uuid);
+        // Trigger Service Not Found event to the application.
+        discovery_complete_evt_trigger(p_db_discovery,
+                                       false,
+                                       p_ble_gattc_evt->conn_handle);
+
+        on_srv_disc_completion(p_db_discovery,
+                               p_ble_gattc_evt->conn_handle);
+    }
+}
+
+
+/**@brief     Function for handling characteristic discovery response.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GATT Client event.
+ */
+static void on_characteristic_discovery_rsp(ble_db_discovery_t * const    p_db_discovery,
+                             const ble_gattc_evt_t * const                p_ble_gattc_evt)
+{
+    uint32_t                 err_code;
+    ble_gatt_db_srv_t      * p_srv_being_discovered;
+    bool                     perform_desc_discov = false;
+
+    if (p_ble_gattc_evt->conn_handle != p_db_discovery->conn_handle)
+    {
+        return;
+    }
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    if (p_ble_gattc_evt->gatt_status == BLE_GATT_STATUS_SUCCESS)
+    {
+        const ble_gattc_evt_char_disc_rsp_t * p_char_disc_rsp_evt;
+
+        p_char_disc_rsp_evt = &(p_ble_gattc_evt->params.char_disc_rsp);
+
+        // Find out the number of characteristics that were previously discovered (in earlier
+        // characteristic discovery responses, if any).
+        uint8_t num_chars_prev_disc = p_srv_being_discovered->char_count;
+
+        // Find out the number of characteristics that are currently discovered (in the
+        // characteristic discovery response being handled).
+        uint8_t num_chars_curr_disc = p_char_disc_rsp_evt->count;
+
+        // Check if the total number of discovered characteristics are supported by this module.
+        if ((num_chars_prev_disc + num_chars_curr_disc) <= BLE_GATT_DB_MAX_CHARS)
+        {
+            // Update the characteristics count.
+            p_srv_being_discovered->char_count += num_chars_curr_disc;
+        }
+        else
+        {
+            // The number of characteristics discovered at the peer is more than the supported
+            // maximum. This module will store only the characteristics found up to this point.
+            p_srv_being_discovered->char_count = BLE_GATT_DB_MAX_CHARS;
+        }
+
+        uint32_t i;
+        uint32_t j;
+
+        for (i = num_chars_prev_disc, j = 0; i < p_srv_being_discovered->char_count; i++, j++)
+        {
+            p_srv_being_discovered->charateristics[i].characteristic =
+                p_char_disc_rsp_evt->chars[j];
+
+            p_srv_being_discovered->charateristics[i].cccd_handle = BLE_GATT_HANDLE_INVALID;
+        }
+
+        ble_gattc_char_t * p_last_known_char;
+
+        p_last_known_char = &(p_srv_being_discovered->charateristics[i - 1].characteristic);
+
+        // If no more characteristic discovery is required, or if the maximum number of supported
+        // characteristic per service has been reached, descriptor discovery will be performed.
+        if (
+            !is_char_discovery_reqd(p_db_discovery, p_last_known_char) ||
+            (p_srv_being_discovered->char_count == BLE_GATT_DB_MAX_CHARS)
+           )
+        {
+            perform_desc_discov = true;
+        }
+        else
+        {
+            // Update the current characteristic index.
+            p_db_discovery->curr_char_ind = p_srv_being_discovered->char_count;
+
+            // Perform another round of characteristic discovery.
+            err_code = characteristics_discover(p_db_discovery,
+                                                p_ble_gattc_evt->conn_handle);
+
+            if (err_code != NRF_SUCCESS)
+            {
+                p_db_discovery->discovery_in_progress = false;
+
+                discovery_error_evt_trigger(p_db_discovery,
+                                            err_code,
+                                            p_ble_gattc_evt->conn_handle);
+
+                m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+                m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+                //m_evt_handler(&m_pending_user_evts[0].evt);
+
+                return;
+            }
+        }
+    }
+    else
+    {
+        // The previous characteristic discovery resulted in no characteristics.
+        // descriptor discovery should be performed.
+        perform_desc_discov = true;
+    }
+
+    if (perform_desc_discov)
+    {
+        bool raise_discov_complete;
+
+        p_db_discovery->curr_char_ind = 0;
+
+        err_code = descriptors_discover(p_db_discovery,
+                                        &raise_discov_complete,
+                                        p_ble_gattc_evt->conn_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            discovery_error_evt_trigger(p_db_discovery,
+                                        err_code,
+                                        p_ble_gattc_evt->conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+            //m_evt_handler(&m_pending_user_evts[0].evt);
+
+            return;
+        }
+        if (raise_discov_complete)
+        {
+            // No more characteristics and descriptors need to be discovered. Discovery is complete.
+            // Send a discovery complete event to the user application.
+            DB_LOG("[DB]: Discovery of service with UUID 0x%x completed with success for Connection"
+                   " handle %d\r\n", p_srv_being_discovered->srv_uuid.uuid,
+                   p_ble_gattc_evt->conn_handle);
+
+            discovery_complete_evt_trigger(p_db_discovery,
+                                           true,
+                                           p_ble_gattc_evt->conn_handle);
+
+            on_srv_disc_completion(p_db_discovery,
+                                   p_ble_gattc_evt->conn_handle);
+        }
+    }
+}
+
+
+/**@brief     Function for handling descriptor discovery response.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GATT Client event.
+ */
+static void on_descriptor_discovery_rsp(ble_db_discovery_t * const    p_db_discovery,
+                                        const ble_gattc_evt_t * const p_ble_gattc_evt)
+{
+    const ble_gattc_evt_desc_disc_rsp_t * p_desc_disc_rsp_evt;
+    ble_gatt_db_srv_t                   * p_srv_being_discovered;
+
+    if (p_ble_gattc_evt->conn_handle != p_db_discovery->conn_handle)
+    {
+        return;
+    }
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_desc_disc_rsp_evt = &(p_ble_gattc_evt->params.desc_disc_rsp);
+
+    ble_gatt_db_char_t * p_char_being_discovered =
+        &(p_srv_being_discovered->charateristics[p_db_discovery->curr_char_ind]);
+
+    if (p_ble_gattc_evt->gatt_status == BLE_GATT_STATUS_SUCCESS)
+    {
+        // The descriptor was found at the peer.
+        // If the descriptor was a CCCD, then the cccd_handle needs to be populated.
+
+        uint32_t i;
+
+        // Loop through all the descriptors to find the CCCD.
+        for (i = 0; i < p_desc_disc_rsp_evt->count; i++)
+        {
+            if (
+                p_desc_disc_rsp_evt->descs[i].uuid.uuid ==
+                BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG
+               )
+            {
+                p_char_being_discovered->cccd_handle = p_desc_disc_rsp_evt->descs[i].handle;
+
+                break;
+            }
+        }
+    }
+
+    bool raise_discov_complete = false;
+
+    if ((p_db_discovery->curr_char_ind + 1) == p_srv_being_discovered->char_count)
+    {
+        // No more characteristics and descriptors need to be discovered. Discovery is complete.
+        // Send a discovery complete event to the user application.
+
+        raise_discov_complete = true;
+    }
+    else
+    {
+        // Begin discovery of descriptors for the next characteristic.
+        uint32_t err_code;
+
+        p_db_discovery->curr_char_ind++;
+
+        err_code = descriptors_discover(p_db_discovery,
+                                        &raise_discov_complete,
+                                        p_ble_gattc_evt->conn_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            p_db_discovery->discovery_in_progress = false;
+
+            // Error with discovering the service.
+            // Indicate the error to the registered user application.
+            discovery_error_evt_trigger(p_db_discovery,
+                                        err_code,
+                                        p_ble_gattc_evt->conn_handle);
+
+            m_pending_user_evts[0].evt.evt_type    = BLE_DB_DISCOVERY_AVAILABLE;
+            m_pending_user_evts[0].evt.conn_handle = p_ble_gattc_evt->conn_handle;
+
+            return;
+        }
+    }
+
+    if (raise_discov_complete)
+    {
+        DB_LOG("[DB]: Discovery of service with UUID 0x%x completed with success for Connection"
+               "handle %d\r\n", p_srv_being_discovered->srv_uuid.uuid,
+               p_ble_gattc_evt->conn_handle);
+
+        discovery_complete_evt_trigger(p_db_discovery,
+                                       true,
+                                       p_ble_gattc_evt->conn_handle);
+
+        on_srv_disc_completion(p_db_discovery,
+                               p_ble_gattc_evt->conn_handle);
+    }
+}
+
+
+uint32_t ble_db_discovery_init(const ble_db_discovery_evt_handler_t evt_handler)
+{
+    uint32_t err_code = NRF_SUCCESS;
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+
+    m_num_of_handlers_reg      = 0;
+    m_initialized              = true;
+    m_pending_usr_evt_index    = 0;
+    m_evt_handler              = evt_handler;
+
+    return err_code;
+
+}
+
+
+uint32_t ble_db_discovery_close()
+{
+    m_num_of_handlers_reg      = 0;
+    m_initialized              = false;
+    m_pending_usr_evt_index    = 0;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_db_discovery_evt_register(const ble_uuid_t * const p_uuid)
+{
+    VERIFY_PARAM_NOT_NULL(p_uuid);
+    VERIFY_MODULE_INITIALIZED();
+
+    return registered_handler_set(p_uuid, m_evt_handler);
+}
+
+
+uint32_t ble_db_discovery_start(ble_db_discovery_t * const p_db_discovery,
+                                uint16_t                   conn_handle)
+{
+    VERIFY_PARAM_NOT_NULL(p_db_discovery);
+    VERIFY_MODULE_INITIALIZED();
+
+    if (m_num_of_handlers_reg == 0)
+    {
+        // No user modules were registered. There are no services to discover.
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    if (p_db_discovery->discovery_in_progress)
+    {
+        return NRF_ERROR_BUSY;
+    }
+
+    p_db_discovery->conn_handle = conn_handle;
+    ble_gatt_db_srv_t * p_srv_being_discovered;
+
+    m_pending_usr_evt_index   = 0;
+
+    p_db_discovery->discoveries_count = 0;
+    p_db_discovery->curr_srv_ind = 0;
+
+    p_srv_being_discovered = &(p_db_discovery->services[p_db_discovery->curr_srv_ind]);
+
+    p_srv_being_discovered->srv_uuid = m_registered_handlers[p_db_discovery->curr_srv_ind];
+
+    DB_LOG("[DB]: Starting discovery of service with UUID 0x%x for Connection handle %d\r\n",
+           p_srv_being_discovered->srv_uuid.uuid, conn_handle);
+
+    uint32_t err_code;
+
+    err_code = sd_ble_gattc_primary_services_discover(conn_handle,
+                                                      SRV_DISC_START_HANDLE,
+                                                      &(p_srv_being_discovered->srv_uuid));
+    VERIFY_SUCCESS(err_code);
+    p_db_discovery->discovery_in_progress = true;
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief     Function for handling disconnected event.
+ *
+ * @param[in] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in] p_ble_gattc_evt   Pointer to the GAP event.
+ */
+static void on_disconnected(ble_db_discovery_t * const  p_db_discovery,
+                            const ble_gap_evt_t * const p_evt)
+{
+    if (p_evt->conn_handle == p_db_discovery->conn_handle)
+    {
+        p_db_discovery->discovery_in_progress = false;
+    }
+}
+
+
+void ble_db_discovery_on_ble_evt(ble_db_discovery_t * const p_db_discovery,
+                                 const ble_evt_t * const    p_ble_evt)
+{
+    VERIFY_PARAM_NOT_NULL_VOID(p_db_discovery);
+    VERIFY_PARAM_NOT_NULL_VOID(p_ble_evt);
+    VERIFY_MODULE_INITIALIZED_VOID();
+
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GATTC_EVT_PRIM_SRVC_DISC_RSP:
+            on_primary_srv_discovery_rsp(p_db_discovery, &(p_ble_evt->evt.gattc_evt));
+            break;
+
+        case BLE_GATTC_EVT_CHAR_DISC_RSP:
+            on_characteristic_discovery_rsp(p_db_discovery, &(p_ble_evt->evt.gattc_evt));
+            break;
+
+        case BLE_GATTC_EVT_DESC_DISC_RSP:
+            on_descriptor_discovery_rsp(p_db_discovery, &(p_ble_evt->evt.gattc_evt));
+            break;
+
+        case BLE_GAP_EVT_DISCONNECTED:
+            on_disconnected(p_db_discovery, &(p_ble_evt->evt.gap_evt));
+            break;
+
+        default:
+            break;
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.h
new file mode 100644
index 0000000000..edca50f3e5
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_db_discovery/ble_db_discovery.h
@@ -0,0 +1,208 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+/**@file
+ *
+ * @defgroup ble_sdk_lib_db_discovery Database Discovery
+ * @{
+ * @ingroup  ble_sdk_lib
+ * @brief    Database discovery module.
+ *
+ * @details  This module contains the APIs and types exposed by the DB Discovery module. These APIs
+ *           and types can be used by the application to perform discovery of a service and its
+ *           characteristics at the peer server. This module can also be used to discover the
+ *           desired services in multiple remote devices.
+ *
+ * @warning  The maximum number of characteristics per service that can be discovered by this module
+ *           is determined by the number of characteristics in the service structure defined in
+ *           db_disc_config.h. If the peer has more than the supported number of characteristics, then
+ *           the first found will be discovered and any further characteristics will be ignored. No
+ *           descriptors other than Client Characteristic Configuration Descriptors will be searched
+ *           for at the peer.
+ *
+ * @note     Presently only one instance of a Primary Service can be discovered by this module. If
+ *           there are multiple instances of the service at the peer, only the first instance
+ *           of it at the peer is fetched and returned to the application.
+ *
+ * @note     The application must propagate BLE stack events to this module by calling
+ *           ble_db_discovery_on_ble_evt().
+ *
+ */
+
+#ifndef BLE_DB_DISCOVERY_H__
+#define BLE_DB_DISCOVERY_H__
+
+#include <stdint.h>
+#include "nrf_ble_gattc.h"
+#include "nrf_ble.h"
+#include "nrf_error.h"
+#include "ble_srv_common.h"
+#include "ble_gatt_db.h"
+
+
+#define BLE_DB_DISCOVERY_MAX_SRV          6  /**< Maximum number of services supported by this module. This also indicates the maximum number of users allowed to be registered to this module. (one user per service). */
+
+
+/**@brief   Type of the DB Discovery event.
+ */
+typedef enum
+{
+    BLE_DB_DISCOVERY_COMPLETE,      /**< Event indicating that the GATT Database discovery is complete. */
+    BLE_DB_DISCOVERY_ERROR,         /**< Event indicating that an internal error has occurred in the DB Discovery module. This could typically be because of the SoftDevice API returning an error code during the DB discover.*/
+    BLE_DB_DISCOVERY_SRV_NOT_FOUND, /**< Event indicating that the service was not found at the peer.*/
+    BLE_DB_DISCOVERY_AVAILABLE      /**< Event indicating that the DB discovery module is available.*/
+} ble_db_discovery_evt_type_t;
+
+
+
+/**@brief   Structure for holding the information related to the GATT database at the server.
+ *
+ * @details This module identifies a remote database. Use one instance of this structure per
+ *          connection.
+ *
+ * @warning This structure must be zero-initialized.
+ */
+typedef struct
+{
+    ble_gatt_db_srv_t   services[BLE_DB_DISCOVERY_MAX_SRV];  /**< Information related to the current service being discovered. This is intended for internal use during service discovery.*/
+    uint8_t             srv_count;                           /**< Number of services at the peers GATT database.*/
+    uint8_t             curr_char_ind;                       /**< Index of the current characteristic being discovered. This is intended for internal use during service discovery.*/
+    uint8_t             curr_srv_ind;                        /**< Index of the current service being discovered. This is intended for internal use during service discovery.*/
+    bool                discovery_in_progress;               /**< Variable to indicate if there is a service discovery in progress. */
+    uint8_t             discoveries_count;                   /**< Number of service discoveries made, both successful and unsuccessful. */
+    uint16_t            conn_handle;                         /**< Connection handle on which the discovery is started*/
+} ble_db_discovery_t;
+
+
+/**@brief   Structure containing the event from the DB discovery module to the application.
+ */
+typedef struct
+{
+    ble_db_discovery_evt_type_t evt_type;     /**< Type of event. */
+    uint16_t                    conn_handle;  /**< Handle of the connection for which this event has occurred. */
+    union
+    {
+        ble_gatt_db_srv_t discovered_db;  /**< Structure containing the information about the GATT Database at the server. This will be filled when the event type is @ref BLE_DB_DISCOVERY_COMPLETE.*/
+        uint32_t               err_code;       /**< nRF Error code indicating the type of error which occurred in the DB Discovery module. This will be filled when the event type is @ref BLE_DB_DISCOVERY_ERROR. */
+    } params;
+} ble_db_discovery_evt_t;
+
+
+/**@brief   DB Discovery event handler type. */
+typedef void (* ble_db_discovery_evt_handler_t)(ble_db_discovery_evt_t * p_evt);
+
+
+/**@brief     Function for initializing the DB Discovery module.
+ *
+ * @param[in] evt_handler        Event handler to be called by the DB discovery module when any event
+ *                               related to discovery of the registered service occurs.
+ *
+ * @retval  NRF_SUCCESS    On successful initialization.
+ * @retval  NRF_ERROR_NULL If the handler was NULL.
+ */
+uint32_t ble_db_discovery_init(ble_db_discovery_evt_handler_t evt_handler);
+
+
+/**@brief Function for closing the DB Discovery module.
+ *
+ * @details This function will clear up any internal variables and states maintained by the
+ *          module. To re-use the module after calling this function, the function @ref
+ *          ble_db_discovery_init must be called again.
+ *
+ * @retval  NRF_SUCCESS    Operation success.
+ */
+uint32_t ble_db_discovery_close(void);
+
+
+/**@brief Function for registering with the DB Discovery module.
+ *
+ * @details   The application can use this function to inform which service it is interested in
+ *            discovering at the server.
+ *
+ * @param[in] p_uuid             Pointer to the UUID of the service to be discovered at the server.
+ *
+ * @note      The total number of services that can be discovered by this module is @ref
+ *            BLE_DB_DISCOVERY_MAX_SRV. This effectively means that the maximum number of
+ *            registrations possible is equal to the @ref BLE_DB_DISCOVERY_MAX_SRV.
+ *
+ * @retval    NRF_SUCCESS               Operation success.
+ * @retval    NRF_ERROR_NULL            When a NULL pointer is passed as input.
+ * @retval    NRF_ERROR_INVALID_STATE   If this function is called without calling the
+ *                                      @ref ble_db_discovery_init.
+ * @retval    NRF_ERROR_NO_MEM          The maximum number of registrations allowed by this module
+ *                                      has been reached.
+ */
+uint32_t ble_db_discovery_evt_register(const ble_uuid_t * const             p_uuid);
+
+
+/**@brief Function for starting the discovery of the GATT database at the server.
+ *
+ * @warning p_db_discovery structure must be zero-initialized.
+ *
+ * @param[out] p_db_discovery    Pointer to the DB Discovery structure.
+ * @param[in]  conn_handle       The handle of the connection for which the discovery should be
+ *                               started.
+ *
+ * @retval    NRF_SUCCESS               Operation success.
+ * @retval    NRF_ERROR_NULL            When a NULL pointer is passed as input.
+ * @retval    NRF_ERROR_INVALID_STATE   If this function is called without calling the
+ *                                      @ref ble_db_discovery_init, or without calling
+ *                                      @ref ble_db_discovery_evt_register.
+ * @retval    NRF_ERROR_BUSY            If a discovery is already in progress for the current
+ *                                      connection.
+ *
+ * @return                              This API propagates the error code returned by the
+ *                                      SoftDevice API @ref sd_ble_gattc_primary_services_discover.
+ */
+uint32_t ble_db_discovery_start(ble_db_discovery_t * const p_db_discovery,
+                                uint16_t                   conn_handle);
+
+
+/**@brief Function for handling the Application's BLE Stack events.
+ *
+ * @param[in,out] p_db_discovery Pointer to the DB Discovery structure.
+ * @param[in]     p_ble_evt      Pointer to the BLE event received.
+ */
+void ble_db_discovery_on_ble_evt(ble_db_discovery_t * const p_db_discovery,
+                                 const ble_evt_t * const    p_ble_evt);
+
+#endif // BLE_DB_DISCOVERY_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c
new file mode 100644
index 0000000000..665393c6fb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.c
@@ -0,0 +1,82 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_debug_assert_handler.h"
+#include <string.h>
+#include "nrf.h"
+#include "ble_error_log.h"
+#include "nordic_common.h"
+
+#define MAX_LENGTH_FILENAME 128  /**< Max length of filename to copy for the debug error handlier. */
+
+
+// WARNING - DO NOT USE THIS FUNCTION IN END PRODUCT. - WARNING
+// WARNING -         FOR DEBUG PURPOSES ONLY.         - WARNING
+void ble_debug_assert_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name)
+{
+    // Copying parameters to static variables because parameters may not be accessible in debugger.
+    static volatile uint8_t  s_file_name[MAX_LENGTH_FILENAME];
+    static volatile uint16_t s_line_num;
+    static volatile uint32_t s_error_code;
+
+    strncpy((char *)s_file_name, (const char *)p_file_name, MAX_LENGTH_FILENAME - 1);
+    s_file_name[MAX_LENGTH_FILENAME - 1] = '\0';
+    s_line_num                           = line_num;
+    s_error_code                         = error_code;
+    UNUSED_VARIABLE(s_file_name);
+    UNUSED_VARIABLE(s_line_num);
+    UNUSED_VARIABLE(s_error_code);
+
+    // WARNING: The PRIMASK register is set to disable ALL interrups during writing the error log.
+    // 
+    // Do not use __disable_irq() in normal operation.
+    __disable_irq();
+
+    // This function will write error code, filename, and line number to the flash.
+    // In addition, the Cortex-M0 stack memory will also be written to the flash.
+    //(void) ble_error_log_write(error_code, p_file_name, line_num);
+
+    // For debug purposes, this function never returns.
+    // Attach a debugger for tracing the error cause.
+    for (;;)
+    {
+        // Do nothing.
+    }
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h
new file mode 100644
index 0000000000..7a4ffa2648
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_debug_assert_handler/ble_debug_assert_handler.h
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_debug_assert_handler Assert handler for debug purposes
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for handling of assert during application development when debugging.
+ *
+ * @details This module may be used during development of an application to facilitate debugging.
+ *          It contains a function to write file name, line number and the Stack Memory to flash.
+ *          This module is ONLY for debugging purposes and must never be used in final product.
+ *
+ */
+ 
+#ifndef BLE_DEBUG_ASSERT_HANDLER_H__
+#define BLE_DEBUG_ASSERT_HANDLER_H__
+
+#include <stdint.h>
+ 
+/**@brief Function for handling the Debug assert, which can be called from an error handler. 
+ *        To be used only for debugging purposes.
+ *
+ *@details This code will copy the filename and line number into local variables for them to always
+ *         be accessible in Keil debugger. The function will also write the ARM Cortex-M0 stack 
+ *         memory into flash where it can be retrieved and manually un-winded in order to 
+ *         back-trace the location where the error ocured.<br>
+ * @warning <b>ALL INTERRUPTS WILL BE DISABLED.</b>
+ * 
+ * @note    This function will never return but loop forever for debug purposes.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ * @param[in] line_num    Line number where the original handler is called.
+ * @param[in] p_file_name Pointer to the file name. 
+ */
+void ble_debug_assert_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+#endif /* BLE_DEBUG_ASSERT_HANDLER_H__ */
+
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.c
new file mode 100644
index 0000000000..dad99f352b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.c
@@ -0,0 +1,670 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_dtm.h"
+#include <stdbool.h>
+#include <string.h>
+#include "nrf.h"
+
+#define DTM_HEADER_OFFSET        0                                         /**< Index where the header of the pdu is located. */
+#define DTM_HEADER_SIZE          2                                         /**< Size of PDU header. */
+#define DTM_PAYLOAD_MAX_SIZE     37                                        /**< Maximum payload size allowed during dtm execution. */
+#define DTM_LENGTH_OFFSET        (DTM_HEADER_OFFSET + 1)                   /**< Index where the length of the payload is encoded. */
+#define DTM_PDU_MAX_MEMORY_SIZE  (DTM_HEADER_SIZE + DTM_PAYLOAD_MAX_SIZE)  /**< Maximum PDU size allowed during dtm execution. */
+
+/**@details The UART poll cycle in micro seconds. 
+ *          Baud rate of 19200 bits / second, and 8 data bits, 1 start/stop bit, no flow control, 
+ *          give the time to transmit a byte: 10 bits * 1/19200 = approx: 520 us. 
+ *
+ *          To ensure no loss of bytes, the UART should be polled every 260 us. 
+ *
+ * @note If UART bit rate is changed, this value should be recalculated as well.
+ */
+#define UART_POLL_CYCLE  260
+
+#define RX_MODE          true   /**< Constant defining RX mode for radio during dtm test. */
+#define TX_MODE          false  /**< Constant defining TX mode for radio during dtm test. */
+
+#define PHYS_CH_MAX      39     /**< Maximum number of valid channels in BLE. */
+
+// Values that for now are "constants" - they could be configured by a function setting them,
+// but most of these are set by the BLE DTM standard, so changing them is not relevant.
+#define RFPHY_TEST_0X0F_REF_PATTERN  0x0f  /**<  RF-PHY test packet patterns, for the repeated octet packets. */
+#define RFPHY_TEST_0X55_REF_PATTERN  0x55  /**<  RF-PHY test packet patterns, for the repeated octet packets. */
+
+#define PRBS9_CONTENT {0xff, 0xc1, 0xfb, 0xe8, 0x4c, 0x90, 0x72, 0x8b,  \
+                       0xe7, 0xb3, 0x51, 0x89, 0x63, 0xab, 0x23, 0x23,  \
+                       0x2,  0x84, 0x18, 0x72, 0xaa, 0x61, 0x2f, 0x3b,  \
+                       0x51, 0xa8, 0xe5, 0x37, 0x49, 0xfb, 0xc9, 0xca,  \
+                       0xc,  0x18, 0x53, 0x2c, 0xfd}                         /**< The PRBS9 sequence used as packet payload. */
+
+/**@brief Structure holding the PDU used for transmitting/receiving a PDU.
+ */
+typedef struct
+{
+    uint8_t content[DTM_HEADER_SIZE + DTM_PAYLOAD_MAX_SIZE];                 /**< PDU packet content. */
+} pdu_type_t;
+
+/**@brief States used for the DTM test implementation.
+ */
+typedef enum
+{
+    STATE_UNINITIALIZED,                                                     /**< The DTM is uninitialized. */
+    STATE_IDLE,                                                              /**< State when system has just initialized, or current test has completed. */
+    STATE_TRANSMITTER_TEST,                                                  /**< State used when a DTM Transmission test is running. */
+    STATE_CARRIER_TEST,                                                      /**< State used when a DTM Carrier test is running (Vendor specific test). */
+    STATE_RECEIVER_TEST                                                      /**< State used when a DTM Receive test is running. */
+} state_t;
+
+// Internal variables set as side effects of commands or events.
+static state_t           m_state = STATE_UNINITIALIZED;                      /**< Current machine state. */
+static uint16_t          m_rx_pkt_count;                                     /**< Number of valid packets received. */
+static pdu_type_t        m_pdu;                                              /**< PDU to be sent. */
+static uint16_t          m_event;                                            /**< current command status - initially "ok", may be set if error detected, or to packet count. */
+static bool              m_new_event;                                        /**< Command has been processed - number of not yet reported event bytes. */
+static uint8_t           m_packet_length;                                    /**< Payload length of transmitted PDU, bits 2:7 of 16-bit dtm command. */
+static dtm_pkt_type_t    m_packet_type;                                      /**< Bits 0..1 of 16-bit transmit command, or 0xFFFFFFFF. */
+static dtm_freq_t        m_phys_ch;                                          /**< 0..39 physical channel number (base 2402 MHz, Interval 2 MHz), bits 8:13 of 16-bit dtm command. */
+static uint32_t          m_current_time = 0;                                 /**< Counter for interrupts from timer to ensure that the 2 bytes forming a DTM command are received within the time window. */
+
+// Nordic specific configuration values (not defined by BLE standard).
+// Definition of initial values found in ble_dtm.h
+static int32_t           m_tx_power          = DEFAULT_TX_POWER;             /**< TX power for transmission test, default to maximum value (+4 dBm). */
+static NRF_TIMER_Type *  mp_timer            = DEFAULT_TIMER;                /**< Timer to be used. */
+static IRQn_Type         m_timer_irq         = DEFAULT_TIMER_IRQn;           /**< which interrupt line to clear on every timeout */
+
+static uint8_t const     m_prbs_content[]    = PRBS9_CONTENT;                /**< Pseudo-random bit sequence defined by the BLE standard. */
+static uint8_t           m_packetHeaderLFlen = 8;                            /**< Length of length field in packet Header (in bits). */
+static uint8_t           m_packetHeaderS0len = 1;                            /**< Length of S0 field in packet Header (in bytes). */
+static uint8_t           m_packetHeaderS1len = 0;                            /**< Length of S1 field in packet Header (in bits). */
+static uint8_t           m_crcConfSkipAddr   = 1;                            /**< Leave packet address field out of CRC calculation. */
+static uint8_t           m_static_length     = 0;                            /**< Number of bytes sent in addition to the var.length payload. */
+static uint32_t          m_balen             = 3;                            /**< Base address length in bytes. */
+static uint32_t          m_endian            = RADIO_PCNF1_ENDIAN_Little;    /**< On air endianess of packet, this applies to the S0, LENGTH, S1 and the PAYLOAD fields. */
+static uint32_t          m_whitening         = RADIO_PCNF1_WHITEEN_Disabled; /**< Whitening disabled. */
+static uint8_t           m_crcLength         = RADIO_CRCCNF_LEN_Three;       /**< CRC Length (in bytes). */
+static uint32_t          m_address           = 0x71764129;                   /**< Address. */
+static uint32_t          m_crc_poly          = 0x0000065B;                   /**< CRC polynomial. */
+static uint32_t          m_crc_init          = 0x00555555;                   /**< Initial value for CRC calculation. */
+static uint8_t           m_radio_mode        = RADIO_MODE_MODE_Ble_1Mbit;    /**< nRF51 specific radio mode vale. */
+static uint32_t          m_txIntervaluS      = 625;                          /**< Time between start of Tx packets (in uS). */
+
+
+/**@brief Function for verifying that a received PDU has the expected structure and content.
+ */
+static bool check_pdu(void)
+{
+    uint8_t        k;                // Byte pointer for running through PDU payload
+    uint8_t        pattern;          // Repeating octet value in payload
+    dtm_pkt_type_t pdu_packet_type;  // Note: PDU packet type is a 4-bit field in HCI, but 2 bits in BLE DTM
+    uint8_t        length;
+
+    pdu_packet_type = (dtm_pkt_type_t)(m_pdu.content[DTM_HEADER_OFFSET] & 0x0F);
+    length          = m_pdu.content[DTM_LENGTH_OFFSET];
+
+    if ((pdu_packet_type > (dtm_pkt_type_t)PACKET_TYPE_MAX) || (length > DTM_PAYLOAD_MAX_SIZE))
+    {
+        return false;
+    }
+
+    if (pdu_packet_type == DTM_PKT_PRBS9)
+    {
+        // Payload does not consist of one repeated octet; must compare ir with entire block into
+        return (memcmp(m_pdu.content+DTM_HEADER_SIZE, m_prbs_content, length) == 0);
+    }
+
+    if (pdu_packet_type == DTM_PKT_0X0F)
+    {
+        pattern = RFPHY_TEST_0X0F_REF_PATTERN;
+    }
+    else
+    {
+        pattern = RFPHY_TEST_0X55_REF_PATTERN;
+    }
+
+    for (k = 0; k < length; k++)
+    {
+        // Check repeated pattern filling the PDU payload 
+        if (m_pdu.content[k + 2] != pattern)
+        {
+            return false;
+        }
+    }
+    return true;
+}
+
+
+/**@brief Function for turning off the radio after a test.
+ *        Also called after test done, to be ready for next test.
+ */
+static void radio_reset(void)
+{
+    NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Msk | PPI_CHENCLR_CH1_Msk;
+
+    NRF_RADIO->SHORTS          = 0;
+    NRF_RADIO->EVENTS_DISABLED = 0;
+    NRF_RADIO->TASKS_DISABLE   = 1;
+
+    while (NRF_RADIO->EVENTS_DISABLED == 0)
+    {
+        // Do nothing
+    }
+
+    NRF_RADIO->EVENTS_DISABLED = 0;
+    NRF_RADIO->TASKS_RXEN      = 0;
+    NRF_RADIO->TASKS_TXEN      = 0;
+
+    m_rx_pkt_count = 0;
+}
+
+
+/**@brief Function for initializing the radio for DTM.
+ */
+static uint32_t radio_init(void)
+{
+#ifdef NRF51
+    // Handle BLE Radio tuning parameters from production for DTM if required.
+    // Only needed for DTM without SoftDevice, as the SoftDevice normally handles this.
+    // PCN-083.
+    if ( ((NRF_FICR->OVERRIDEEN) & FICR_OVERRIDEEN_BLE_1MBIT_Msk) == FICR_OVERRIDEEN_BLE_1MBIT_Override)
+    {
+        NRF_RADIO->OVERRIDE0 = NRF_FICR->BLE_1MBIT[0];
+        NRF_RADIO->OVERRIDE1 = NRF_FICR->BLE_1MBIT[1];
+        NRF_RADIO->OVERRIDE2 = NRF_FICR->BLE_1MBIT[2];
+        NRF_RADIO->OVERRIDE3 = NRF_FICR->BLE_1MBIT[3];
+        NRF_RADIO->OVERRIDE4 = NRF_FICR->BLE_1MBIT[4];
+    }
+#endif // NRF51
+
+    // Initializing code below is quite generic - for BLE, the values are fixed, and expressions
+    // are constant. Non-constant values are essentially set in radio_prepare().
+    if (((m_tx_power & 0x03) != 0)           ||      // tx_power should be a multiple of 4
+         ((m_tx_power & 0xffffff00) != 0)    ||      // Upper 24 bits are required to be zeroed
+         ((int8_t)m_tx_power > 4)            ||      // Max tx_power is +4 dBm
+         ((int8_t)(m_tx_power & 0xff) < -40) ||      // Min tx_power is -40 dBm
+         (m_radio_mode > RADIO_MODE_MODE_Ble_1Mbit)  // Values 0-2: Proprietary mode, 3 (last valid): BLE
+       )
+    {
+        return DTM_ERROR_ILLEGAL_CONFIGURATION;
+    }
+
+    // Turn off radio before configuring it
+    radio_reset();
+
+    NRF_RADIO->TXPOWER = m_tx_power;
+    NRF_RADIO->MODE    = m_radio_mode << RADIO_MODE_MODE_Pos;
+
+    // Set the access address, address0/prefix0 used for both Rx and Tx address
+    NRF_RADIO->PREFIX0    &= ~RADIO_PREFIX0_AP0_Msk;
+    NRF_RADIO->PREFIX0    |= (m_address >> 24) & RADIO_PREFIX0_AP0_Msk;
+    NRF_RADIO->BASE0       = m_address << 8;
+    NRF_RADIO->RXADDRESSES = RADIO_RXADDRESSES_ADDR0_Enabled << RADIO_RXADDRESSES_ADDR0_Pos;
+    NRF_RADIO->TXADDRESS   = (0x00 << RADIO_TXADDRESS_TXADDRESS_Pos) & RADIO_TXADDRESS_TXADDRESS_Msk;
+
+    // Configure CRC calculation
+    NRF_RADIO->CRCCNF = (m_crcConfSkipAddr << RADIO_CRCCNF_SKIP_ADDR_Pos) |
+                        (m_crcLength << RADIO_CRCCNF_LEN_Pos);
+
+    NRF_RADIO->PCNF0 = (m_packetHeaderS1len << RADIO_PCNF0_S1LEN_Pos) |
+                       (m_packetHeaderS0len << RADIO_PCNF0_S0LEN_Pos) |
+                       (m_packetHeaderLFlen << RADIO_PCNF0_LFLEN_Pos);
+
+    NRF_RADIO->PCNF1 = (m_whitening          << RADIO_PCNF1_WHITEEN_Pos) |
+                       (m_endian             << RADIO_PCNF1_ENDIAN_Pos)  |
+                       (m_balen              << RADIO_PCNF1_BALEN_Pos)   |
+                       (m_static_length      << RADIO_PCNF1_STATLEN_Pos) |
+                       (DTM_PAYLOAD_MAX_SIZE << RADIO_PCNF1_MAXLEN_Pos);
+
+    return DTM_SUCCESS;
+}
+
+
+/**@brief Function for preparing the radio. At start of each test: Turn off RF, clear interrupt flags of RF, initialize the radio
+ *        at given RF channel.
+ *
+ *@param[in] rx     boolean indicating if radio should be prepared in rx mode (true) or tx mode.
+ */
+static void radio_prepare(bool rx)
+{
+#ifdef NRF51
+    NRF_RADIO->TEST         = 0;
+#elif defined(NRF52)
+    NRF_RADIO->MODECNF0     = (RADIO_MODECNF0_RU_Default << RADIO_MODECNF0_RU_Pos) |
+                              (RADIO_MODECNF0_DTX_B1 << RADIO_MODECNF0_DTX_Pos);
+#endif // NRF51 / NRF52
+    NRF_RADIO->CRCPOLY      = m_crc_poly;
+    NRF_RADIO->CRCINIT      = m_crc_init;
+    NRF_RADIO->FREQUENCY    = (m_phys_ch << 1) + 2;                  // Actual frequency (MHz): 2400 + register value
+    NRF_RADIO->PACKETPTR    = (uint32_t)&m_pdu;                      // Setting packet pointer will start the radio
+    NRF_RADIO->EVENTS_READY = 0;
+    NRF_RADIO->SHORTS       = (1 << RADIO_SHORTS_READY_START_Pos) |  // Shortcut between READY event and START task
+                              (1 << RADIO_SHORTS_END_DISABLE_Pos);   // Shortcut between END event and DISABLE task
+
+    if (rx)
+    {
+        NRF_RADIO->EVENTS_END = 0;
+        NRF_RADIO->TASKS_RXEN = 1;  // shorts will start radio in RX mode when it is ready
+    }
+    else // tx
+    {
+        NRF_RADIO->TXPOWER = m_tx_power;
+    }
+}
+
+
+/**@brief Function for terminating the ongoing test (if any) and closing down the radio.
+ */
+static void dtm_test_done(void)
+{
+#ifdef NRF51
+    NRF_RADIO->TEST = 0;
+#elif defined(NRF52)
+    NRF_RADIO->MODECNF0 = (RADIO_MODECNF0_RU_Default << RADIO_MODECNF0_RU_Pos) |
+                          (RADIO_MODECNF0_DTX_B1 << RADIO_MODECNF0_DTX_Pos);
+#endif // NRF51 / NRF52
+    NRF_PPI->CHENCLR = 0x01;
+    NRF_PPI->CH[0].EEP = 0;     // Break connection from timer to radio to stop transmit loop
+    NRF_PPI->CH[0].TEP = 0;
+
+    radio_reset();
+    m_state = STATE_IDLE;
+}
+
+
+/**@brief Function for configuring the timer for 625us cycle time.
+ */
+static uint32_t timer_init(void)
+{
+    // Use 16MHz from external crystal
+    // This could be customized for RC/Xtal, or even to use a 32 kHz crystal
+    NRF_CLOCK->EVENTS_HFCLKSTARTED = 0;
+    NRF_CLOCK->TASKS_HFCLKSTART    = 1;
+
+    while (NRF_CLOCK->EVENTS_HFCLKSTARTED == 0)
+    {
+        // Do nothing while waiting for the clock to start
+    }
+
+    mp_timer->TASKS_STOP        = 1;                      // Stop timer, if it was running
+    mp_timer->TASKS_CLEAR       = 1;
+    mp_timer->MODE              = TIMER_MODE_MODE_Timer;  // Timer mode (not counter)
+    mp_timer->EVENTS_COMPARE[0] = 0;                      // clean up possible old events
+    mp_timer->EVENTS_COMPARE[1] = 0;
+    mp_timer->EVENTS_COMPARE[2] = 0;
+    mp_timer->EVENTS_COMPARE[3] = 0;
+
+    // Timer is polled, but enable the compare0 interrupt in order to wakeup from CPU sleep
+    mp_timer->INTENSET    = TIMER_INTENSET_COMPARE0_Msk;
+    mp_timer->SHORTS      = 1 << TIMER_SHORTS_COMPARE0_CLEAR_Pos;  // Clear the count every time timer reaches the CCREG0 count
+    mp_timer->PRESCALER   = 4;                                     // Input clock is 16MHz, timer clock = 2 ^ prescale -> interval 1us
+    mp_timer->CC[0]       = m_txIntervaluS;                        // 625uS with 1MHz clock to the timer
+    mp_timer->CC[1]       = UART_POLL_CYCLE;                       // 260uS with 1MHz clock to the timer
+    mp_timer->TASKS_START = 1;                                     // Start the timer - it will be running continuously
+    m_current_time        = 0;
+    return DTM_SUCCESS;
+}
+
+
+/**@brief Function for handling vendor specific commands.
+ *        Used when packet type is set to Vendor specific.
+ *        The length field is used for encoding vendor specific command.
+ *        The frequency field is used for encoding vendor specific options to the command.
+ *
+ * @param[in]   vendor_cmd      Vendor specific command to be executed.
+ * @param[in]   vendor_option   Vendor specific option to the vendor command.
+ *
+ * @return      DTM_SUCCESS or one of the DTM_ERROR_ values
+ */
+static uint32_t dtm_vendor_specific_pkt(uint32_t vendor_cmd, dtm_freq_t vendor_option)
+{
+    switch (vendor_cmd)
+    {
+        // nRFgo Studio uses CARRIER_TEST_STUDIO to indicate a continuous carrier without
+        // a modulated signal.
+        case CARRIER_TEST:
+        case CARRIER_TEST_STUDIO:
+            // Not a packet type, but used to indicate that a continuous carrier signal
+            // should be transmitted by the radio.
+            radio_prepare(TX_MODE);
+#ifdef NRF51
+            NRF_RADIO->TEST = (RADIO_TEST_PLL_LOCK_Enabled << RADIO_TEST_PLL_LOCK_Pos) |
+                              (RADIO_TEST_CONST_CARRIER_Enabled << RADIO_TEST_CONST_CARRIER_Pos);
+#elif defined(NRF52)
+            NRF_RADIO->MODECNF0 = (RADIO_MODECNF0_RU_Default << RADIO_MODECNF0_RU_Pos) |
+                                  (RADIO_MODECNF0_DTX_B1 << RADIO_MODECNF0_DTX_Pos);
+#endif // NRF51 / NRF52
+
+            // Shortcut between READY event and START task
+            NRF_RADIO->SHORTS = 1 << RADIO_SHORTS_READY_START_Pos;
+
+            // Shortcut will start radio in Tx mode when it is ready
+            NRF_RADIO->TASKS_TXEN = 1;
+            m_state               = STATE_CARRIER_TEST;
+            break;
+
+        case SET_TX_POWER:
+            if (!dtm_set_txpower(vendor_option))
+            {
+                return DTM_ERROR_ILLEGAL_CONFIGURATION;
+            }
+            break;
+
+        case SELECT_TIMER:
+            if (!dtm_set_timer(vendor_option))
+            {
+                return DTM_ERROR_ILLEGAL_CONFIGURATION;
+            }
+            break;
+    }
+    // Event code is unchanged, successful
+    return DTM_SUCCESS;
+}
+
+
+uint32_t dtm_init(void)
+{
+    if ((timer_init() != DTM_SUCCESS) || (radio_init() != DTM_SUCCESS))
+    {
+        return DTM_ERROR_ILLEGAL_CONFIGURATION;
+    }
+    m_new_event = false;
+    m_state     = STATE_IDLE;
+
+    // Enable wake-up on event
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    return DTM_SUCCESS;
+}
+
+
+uint32_t dtm_wait(void)
+{
+    // Enable wake-up on event
+    SCB->SCR |= SCB_SCR_SEVONPEND_Msk;
+
+    for (;;)
+    {
+        // Event may be the reception of a packet - 
+        // handle radio first, to give it highest priority:
+        if (NRF_RADIO->EVENTS_END != 0)
+        {
+            NRF_RADIO->EVENTS_END = 0;
+            NVIC_ClearPendingIRQ(RADIO_IRQn);
+
+            if (m_state == STATE_RECEIVER_TEST)
+            {
+                NRF_RADIO->TASKS_RXEN = 1;
+                if ((NRF_RADIO->CRCSTATUS == 1) && check_pdu())
+                {
+                    // Count the number of successfully received packets
+                    m_rx_pkt_count++;
+                }
+                // Note that failing packets are simply ignored (CRC or contents error).
+
+                // Zero fill all pdu fields to avoid stray data
+                memset(&m_pdu, 0, DTM_PDU_MAX_MEMORY_SIZE);
+            }
+            // If no RECEIVER_TEST is running, ignore incoming packets (but do clear IRQ!)
+        }
+
+        // Check for timeouts:
+        if (mp_timer->EVENTS_COMPARE[0] != 0)
+        {
+            mp_timer->EVENTS_COMPARE[0] = 0;
+        }
+        else if (mp_timer->EVENTS_COMPARE[1] != 0)
+        {
+            // Reset timeout event flag for next iteration.
+            mp_timer->EVENTS_COMPARE[1] = 0;
+            NVIC_ClearPendingIRQ(m_timer_irq);
+            return ++m_current_time;
+        }
+
+        // Other events: No processing
+    }
+}
+
+
+uint32_t dtm_cmd(dtm_cmd_t cmd, dtm_freq_t freq, uint32_t length, dtm_pkt_type_t payload)
+{
+    // Save specified packet in static variable for tx/rx functions to use.
+    // Note that BLE conformance testers always use full length packets.
+    m_packet_length = ((uint8_t)length & 0xFF);
+    m_packet_type   = payload;
+    m_phys_ch       = freq;
+
+    // Clean out any non-retrieved event that might linger from an earlier test
+    m_new_event     = true;
+ 
+    // Set default event; any error will set it to LE_TEST_STATUS_EVENT_ERROR
+    m_event         = LE_TEST_STATUS_EVENT_SUCCESS;
+    
+    if (m_state == STATE_UNINITIALIZED)
+    {
+        // Application has not explicitly initialized DTM, 
+        return DTM_ERROR_UNINITIALIZED;
+    }
+
+    if (cmd == LE_RESET)
+    {
+        // Note that timer will continue running after a reset
+        dtm_test_done();
+        return DTM_SUCCESS;
+    }
+
+    if (cmd == LE_TEST_END)
+    {
+        if (m_state == STATE_IDLE)
+        {
+            // Sequencing error - only rx or tx test may be ended!
+            m_event = LE_TEST_STATUS_EVENT_ERROR;
+            return DTM_ERROR_INVALID_STATE;
+        }
+        m_event = LE_PACKET_REPORTING_EVENT | m_rx_pkt_count;
+        dtm_test_done();
+        return DTM_SUCCESS;
+    }
+
+    if (m_state != STATE_IDLE)
+    {
+        // Sequencing error - only TEST_END/RESET are legal while test is running
+        // Note: State is unchanged; ongoing test not affected
+        m_event = LE_TEST_STATUS_EVENT_ERROR;               
+        return DTM_ERROR_INVALID_STATE;   
+    }
+
+    if (m_phys_ch > PHYS_CH_MAX)
+    {
+        // Parameter error
+        // Note: State is unchanged; ongoing test not affected
+        m_event = LE_TEST_STATUS_EVENT_ERROR;               
+        return DTM_ERROR_ILLEGAL_CHANNEL;
+    }
+
+    m_rx_pkt_count = 0;
+
+    if (cmd == LE_RECEIVER_TEST)
+    {
+        // Zero fill all pdu fields to avoid stray data from earlier test run
+        memset(&m_pdu, 0, DTM_PDU_MAX_MEMORY_SIZE);
+        radio_prepare(RX_MODE);                      // Reinitialize "everything"; RF interrupts OFF
+        m_state = STATE_RECEIVER_TEST;
+        return DTM_SUCCESS;
+    }
+
+    if (cmd == LE_TRANSMITTER_TEST)
+    {
+        if (m_packet_length > DTM_PAYLOAD_MAX_SIZE)
+        {
+            // Parameter error
+            m_event = LE_TEST_STATUS_EVENT_ERROR;
+            return DTM_ERROR_ILLEGAL_LENGTH;
+        }
+
+        // Note that PDU uses 4 bits even though BLE DTM uses only 2 (the HCI SDU uses all 4)
+        m_pdu.content[DTM_HEADER_OFFSET] = ((uint8_t)m_packet_type & 0x0F); 
+        m_pdu.content[DTM_LENGTH_OFFSET] = m_packet_length;
+        
+        switch (m_packet_type)
+        {
+            case DTM_PKT_PRBS9:
+                // Non-repeated, must copy entire pattern to PDU
+                memcpy(m_pdu.content + DTM_HEADER_SIZE, m_prbs_content, length);
+                break;
+                
+            case DTM_PKT_0X0F:
+                // Bit pattern 00001111 repeated
+                memset(m_pdu.content + DTM_HEADER_SIZE, RFPHY_TEST_0X0F_REF_PATTERN, length);
+                break;
+                
+            case DTM_PKT_0X55:
+                // Bit pattern 01010101 repeated
+                memset(m_pdu.content + DTM_HEADER_SIZE, RFPHY_TEST_0X55_REF_PATTERN, length);
+                break;
+                
+            case DTM_PKT_VENDORSPECIFIC:
+                // The length field is for indicating the vendor specific command to execute.
+                // The frequency field is used for vendor specific options to the command.
+                return dtm_vendor_specific_pkt(length, freq);
+                
+            default:
+                // Parameter error 
+                m_event = LE_TEST_STATUS_EVENT_ERROR;         
+                return DTM_ERROR_ILLEGAL_CONFIGURATION;
+        }
+
+        // Initialize CRC value, set channel:
+        radio_prepare(TX_MODE);
+        // Configure PPI so that timer will activate radio every 625 us
+        NRF_PPI->CH[0].EEP = (uint32_t)&mp_timer->EVENTS_COMPARE[0];
+        NRF_PPI->CH[0].TEP = (uint32_t)&NRF_RADIO->TASKS_TXEN;
+        NRF_PPI->CHENSET   = 0x01;
+        m_state            = STATE_TRANSMITTER_TEST;
+    }
+    return DTM_SUCCESS;
+}
+
+
+bool dtm_event_get(dtm_event_t *p_dtm_event)
+{
+    bool was_new = m_new_event;
+    // mark the current event as retrieved
+    m_new_event  = false;
+    *p_dtm_event = m_event;
+    // return value indicates whether this value was already retrieved.
+    return was_new;
+}
+
+
+// =================================================================================================
+// Configuration functions (only for parameters not definitely determined by the BLE DTM standard).
+// These functions return true if successful, false if value could not be set
+
+
+/**@brief Function for configuring the output power for transmitter test.
+          This function may be called directly, or through dtm_cmd() specifying
+          DTM_PKT_VENDORSPECIFIC as payload, SET_TX_POWER as length, and the dBm value as frequency.
+ */
+bool dtm_set_txpower(uint32_t new_tx_power)
+{
+    // radio->TXPOWER register is 32 bits, low octet a signed value, upper 24 bits zeroed
+    int8_t new_power8 = (int8_t)(new_tx_power & 0xFF);
+    
+    if (m_state > STATE_IDLE)
+    {
+        // radio must be idle to change the tx power
+        return false;
+    }
+
+    if ((new_power8 > 4) || (new_power8 < -40))
+    {
+        // Parameter outside valid range: nRF radio is restricted to the range -40 dBm to +4 dBm
+        return false;
+    }
+
+    if (new_tx_power & 0x03) 
+    {
+        // Parameter error: The nRF51 radio requires settings that are a multiple of 4.
+        return false;
+    }
+    m_tx_power = new_tx_power;
+
+    return true;
+}
+
+
+/**@brief Function for selecting a timer resource.
+ *        This function may be called directly, or through dtm_cmd() specifying
+ *        DTM_PKT_VENDORSPECIFIC as payload, SELECT_TIMER as length, and the timer as freq
+ *
+ * @param[in] new_timer     Timer id for the timer to use: 0, 1, or 2.
+ *
+ * @return true if the timer was successfully changed, false otherwise.
+ */
+bool dtm_set_timer(uint32_t new_timer)
+{
+    if (m_state > STATE_IDLE)
+    {
+        return false;
+    }
+    if (new_timer == 0)
+    {
+        mp_timer    = NRF_TIMER0;
+        m_timer_irq = TIMER0_IRQn;
+    }
+    else if (new_timer == 1)
+    {
+        mp_timer    = NRF_TIMER1;
+        m_timer_irq = TIMER1_IRQn;
+    }
+    else if (new_timer == 2)
+    {
+        mp_timer    = NRF_TIMER2;
+        m_timer_irq = TIMER2_IRQn;
+    }
+    else
+    {
+        // Parameter error: Only TIMER 0, 1, 2 provided by nRF51   
+        return false;
+    }
+    // New timer has been selected:
+    return true;
+}
+
+/// @} 
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.h
new file mode 100644
index 0000000000..6831a85728
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_dtm/ble_dtm.h
@@ -0,0 +1,168 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_sdk_dtmlib_dtm DTM - Direct Test Mode
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for testing RF/PHY using DTM commands.
+ */
+
+#ifndef BLE_DTM_H__
+#define BLE_DTM_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+
+
+/**@brief Configuration parameters. */
+#define DEFAULT_TX_POWER                RADIO_TXPOWER_TXPOWER_0dBm      /**< Default Transmission power using in the DTM module. */
+#define DEFAULT_TIMER                   NRF_TIMER0                      /**< Default timer used for timing. */
+#define DEFAULT_TIMER_IRQn              TIMER0_IRQn                     /**< IRQ used for timer. NOTE: MUST correspond to DEFAULT_TIMER. */
+
+/**@brief BLE DTM command codes. */
+typedef uint32_t dtm_cmd_t;                                             /**< DTM command type. */
+
+#define LE_RESET                        0                               /**< DTM command: Reset device. */
+#define LE_RECEIVER_TEST                1                               /**< DTM command: Start receive test. */
+#define LE_TRANSMITTER_TEST             2                               /**< DTM command: Start transmission test. */
+#define LE_TEST_END                     3                               /**< DTM command: End test and send packet report. */
+
+// Configuration options used as parameter 2
+// when cmd == LE_TRANSMITTER_TEST and payload == DTM_PKT_VENDORSPECIFIC
+// Configuration value, if any, is supplied in parameter 3
+
+#define CARRIER_TEST                    0                               /**< Length=0 indicates a constant, unmodulated carrier until LE_TEST_END or LE_RESET */
+#define CARRIER_TEST_STUDIO             1                               /**< nRFgo Studio uses value 1 in length field, to indicate a constant, unmodulated carrier until LE_TEST_END or LE_RESET */
+#define SET_TX_POWER                    2                               /**< Set transmission power, value -40..+4 dBm in steps of 4 */
+#define SELECT_TIMER                    3                               /**< Select on of the 16 MHz timers 0, 1 or 2 */
+
+#define LE_PACKET_REPORTING_EVENT       0x8000                          /**< DTM Packet reporting event, returned by the device to the tester. */
+#define LE_TEST_STATUS_EVENT_SUCCESS    0x0000                          /**< DTM Status event, indicating success. */
+#define LE_TEST_STATUS_EVENT_ERROR      0x0001                          /**< DTM Status event, indicating an error. */
+
+#define DTM_PKT_PRBS9                   0x00                            /**< Bit pattern PRBS9. */
+#define DTM_PKT_0X0F                    0x01                            /**< Bit pattern 11110000 (LSB is the leftmost bit). */
+#define DTM_PKT_0X55                    0x02                            /**< Bit pattern 10101010 (LSB is the leftmost bit). */
+#define DTM_PKT_VENDORSPECIFIC          0xFFFFFFFF                      /**< Vendor specific. Nordic: Continuous carrier test, or configuration. */
+
+/**@brief Return codes from dtm_cmd(). */
+#define DTM_SUCCESS                     0x00                            /**< Indicate that the DTM function completed with success. */
+#define DTM_ERROR_ILLEGAL_CHANNEL       0x01                            /**< Physical channel number must be in the range 0..39. */
+#define DTM_ERROR_INVALID_STATE         0x02                            /**< Sequencing error: Command is not valid now. */
+#define DTM_ERROR_ILLEGAL_LENGTH        0x03                            /**< Payload size must be in the range 0..37. */
+#define DTM_ERROR_ILLEGAL_CONFIGURATION 0x04                            /**< Parameter out of range (legal range is function dependent). */
+#define DTM_ERROR_UNINITIALIZED         0x05                            /**< DTM module has not been initialized by the application. */
+
+// Note: DTM_PKT_VENDORSPECIFIC, is not a packet type
+#define PACKET_TYPE_MAX                 DTM_PKT_0X55                    /**< Highest value allowed as DTM Packet type. */
+
+/** @brief BLE DTM event type. */
+typedef uint32_t dtm_event_t;                                           /**< Type for handling DTM event. */
+
+/** @brief BLE DTM frequency type. */
+typedef uint32_t dtm_freq_t;                                            /**< Physical channel, valid range: 0..39. */
+
+/**@brief BLE DTM packet types. */
+typedef uint32_t dtm_pkt_type_t;                                        /**< Type for holding the requested DTM payload type.*/
+
+
+/**@brief Function for initializing or re-initializing DTM module
+ *     
+ * @return DTM_SUCCESS on successful initialization of the DTM module.
+*/
+uint32_t dtm_init(void);
+
+
+/**@brief Function for giving control to dtmlib for handling timer and radio events.
+ *        Will return to caller at 625us intervals or whenever another event than radio occurs
+ *        (such as UART input). Function will put MCU to sleep between events.
+ *
+ * @return      Time counter, incremented every 625 us.
+ */
+uint32_t dtm_wait(void);
+
+
+/**@brief Function for calling when a complete command has been prepared by the Tester.
+ *
+ * @param[in]   cmd       One of the DTM_CMD values (bits 14:15 in the 16-bit UART format).
+ * @param[in]   freq      Phys. channel no - actual frequency = (2402 + freq * 2) MHz (bits 8:13 in
+ *                        the 16-bit UART format).
+ * @param[in]   length    Payload length, 0..37 (bits 2:7 in the 16-bit UART format).
+ * @param[in]   payload   One of the DTM_PKT values (bits 0:1 in the 16-bit UART format).
+ *
+ * @return      DTM_SUCCESS or one of the DTM_ERROR_ values
+ */
+uint32_t dtm_cmd(dtm_cmd_t cmd, dtm_freq_t freq, uint32_t length, dtm_pkt_type_t payload);
+
+
+/**@brief Function for reading the result of a DTM command
+ *
+ * @param[out]  p_dtm_event   Pointer to buffer for 16 bit event code according to DTM standard.
+ * 
+ * @return      true: new event, false: no event since last call, this event has been read earlier
+ */
+bool dtm_event_get(dtm_event_t * p_dtm_event);
+
+
+/**@brief Function for configuring the timer to use.
+ *
+ * @note        Must be called when no DTM test is running. 
+ * 
+ * @param[in]   new_timer   Index (0..2) of timer to be used by the DTM library
+ *
+ * @return      true: success, new timer was selected, false: parameter error 
+ */
+bool dtm_set_timer(uint32_t new_timer); 
+
+
+/**@brief Function for configuring the transmit power.
+ *
+ * @note        Must be called when no DTM test is running.
+ * 
+ * @param[in]   new_tx_power   New output level, +4..-40, in steps of 4.
+ *
+ * @return      true: tx power setting changed, false: parameter error
+ */
+bool dtm_set_txpower(uint32_t new_tx_power);
+
+#endif // BLE_DTM_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_error_log/ble_error_log.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_error_log/ble_error_log.h
new file mode 100644
index 0000000000..ab121c2b3c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_error_log/ble_error_log.h
@@ -0,0 +1,96 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_error_log_module Error Log Module
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for writing error and stack to flash memory.
+ *
+ * @details It contains functions for writing an error code, line number, filename/message and
+ *          the stack to the flash during an error, e.g. in the assert handler.
+ *
+ */
+#ifndef BLE_ERROR_LOG_H__
+#define BLE_ERROR_LOG_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "ble_flash.h"
+
+#define ERROR_MESSAGE_LENGTH  128                                /**< Length of error message to stored. */
+#define STACK_DUMP_LENGTH     256                                /**< Length of stack to be stored at max: 64 entries of 4 bytes each. */
+#define FLASH_PAGE_ERROR_LOG  (BLE_FLASH_PAGE_END - 2)           /**< Address in flash where stack trace can be stored. */
+
+/**@brief Error Log Data structure.
+ *
+ * @details The structure contains the error, message/filename, line number as well as the current
+ *          stack, at the time where an error occured.
+ */
+typedef struct
+{
+    uint16_t                  failure;                           /**< Indication that a major failure has occurred during last execution of the application. */
+    uint16_t                  line_number;                       /**< Line number indicating at which line the failure occurred. */
+    uint32_t                  err_code;                          /**< Error code when failure occurred. */
+    uint8_t                   message[ERROR_MESSAGE_LENGTH];     /**< Will just use the first 128 bytes of filename to store for debugging purposes. */
+    uint32_t                  stack_info[STACK_DUMP_LENGTH / 4]; /**< Will contain stack information, can be manually unwinded for debug purposes. */
+} ble_error_log_data_t;
+
+
+/**@brief Function for writing the file name/message, line number, and current program stack
+ *        to flash.
+ * 
+ * @note This function will force the writing to flash, and disregard any radio communication.
+ *       USE THIS FUNCTION WITH CARE.
+ *
+ * @param[in]   err_code    Error code to be logged.
+ * @param[in]   p_message   Message to be written to the flash together with stack dump, usually
+ *                          the file name where the error occured.
+ * @param[in]   line_number Line number where the error occured.
+ *
+ * @return      NRF_SUCCESS on successful writing of the error log.
+ *
+ */
+uint32_t ble_error_log_write(uint32_t err_code, const uint8_t * p_message, uint16_t line_number);
+
+
+#endif /* BLE_ERROR_LOG_H__ */
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.c
new file mode 100644
index 0000000000..5229f7ca24
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.c
@@ -0,0 +1,84 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+#include "ble_racp.h"
+#include <stdlib.h>
+
+
+void ble_racp_decode(uint8_t data_len, uint8_t * p_data, ble_racp_value_t * p_racp_val)
+{
+    p_racp_val->opcode      = 0xFF;
+    p_racp_val->operator    = 0xFF;
+    p_racp_val->operand_len = 0;
+    p_racp_val->p_operand   = NULL;
+    
+    if (data_len > 0)
+    {
+        p_racp_val->opcode = p_data[0];
+    }
+    if (data_len > 1)
+    {
+        p_racp_val->operator = p_data[1];      //lint !e415
+    }
+    if (data_len > 2)
+    {
+        p_racp_val->operand_len = data_len - 2;
+        p_racp_val->p_operand   = &p_data[2];  //lint !e416
+    }
+}
+
+
+uint8_t ble_racp_encode(const ble_racp_value_t * p_racp_val, uint8_t * p_data)
+{
+    uint8_t len = 0;
+    int     i;
+
+    if (p_data != NULL)
+    {
+        p_data[len++] = p_racp_val->opcode;
+        p_data[len++] = p_racp_val->operator;
+
+        for (i = 0; i < p_racp_val->operand_len; i++)
+        {
+            p_data[len++] = p_racp_val->p_operand[i];
+        }
+    }
+
+    return len;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.h
new file mode 100644
index 0000000000..baf11760f1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_racp/ble_racp.h
@@ -0,0 +1,123 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_sdk_lib_racp Record Access Control Point
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Record Access Control Point library.
+ */
+
+#ifndef BLE_RACP_H__
+#define BLE_RACP_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_ble.h"
+#include "nrf_ble_types.h"
+#include "nrf_ble.h"
+
+/**@brief Record Access Control Point opcodes. */
+#define RACP_OPCODE_RESERVED                0       /**< Record Access Control Point opcode - Reserved for future use. */
+#define RACP_OPCODE_REPORT_RECS             1       /**< Record Access Control Point opcode - Report stored records. */
+#define RACP_OPCODE_DELETE_RECS             2       /**< Record Access Control Point opcode - Delete stored records. */
+#define RACP_OPCODE_ABORT_OPERATION         3       /**< Record Access Control Point opcode - Abort operation. */
+#define RACP_OPCODE_REPORT_NUM_RECS         4       /**< Record Access Control Point opcode - Report number of stored records. */
+#define RACP_OPCODE_NUM_RECS_RESPONSE       5       /**< Record Access Control Point opcode - Number of stored records response. */
+#define RACP_OPCODE_RESPONSE_CODE           6       /**< Record Access Control Point opcode - Response code. */
+
+/**@brief Record Access Control Point operators. */
+#define RACP_OPERATOR_NULL                  0       /**< Record Access Control Point operator - Null. */
+#define RACP_OPERATOR_ALL                   1       /**< Record Access Control Point operator - All records. */
+#define RACP_OPERATOR_LESS_OR_EQUAL         2       /**< Record Access Control Point operator - Less than or equal to. */
+#define RACP_OPERATOR_GREATER_OR_EQUAL      3       /**< Record Access Control Point operator - Greater than or equal to. */
+#define RACP_OPERATOR_RANGE                 4       /**< Record Access Control Point operator - Within range of (inclusive). */
+#define RACP_OPERATOR_FIRST                 5       /**< Record Access Control Point operator - First record (i.e. oldest record). */
+#define RACP_OPERATOR_LAST                  6       /**< Record Access Control Point operator - Last record (i.e. most recent record). */
+#define RACP_OPERATOR_RFU_START             7       /**< Record Access Control Point operator - Start of Reserved for Future Use area. */
+
+/**@brief Record Access Control Point response codes. */
+#define RACP_RESPONSE_RESERVED              0       /**< Record Access Control Point response code - Reserved for future use. */
+#define RACP_RESPONSE_SUCCESS               1       /**< Record Access Control Point response code - Successful operation. */
+#define RACP_RESPONSE_OPCODE_UNSUPPORTED    2       /**< Record Access Control Point response code - Unsupported op code received. */
+#define RACP_RESPONSE_INVALID_OPERATOR      3       /**< Record Access Control Point response code - Operator not valid for service. */
+#define RACP_RESPONSE_OPERATOR_UNSUPPORTED  4       /**< Record Access Control Point response code - Unsupported operator. */
+#define RACP_RESPONSE_INVALID_OPERAND       5       /**< Record Access Control Point response code - Operand not valid for service. */
+#define RACP_RESPONSE_NO_RECORDS_FOUND      6       /**< Record Access Control Point response code - No matching records found. */
+#define RACP_RESPONSE_ABORT_FAILED          7       /**< Record Access Control Point response code - Abort could not be completed. */
+#define RACP_RESPONSE_PROCEDURE_NOT_DONE    8       /**< Record Access Control Point response code - Procedure could not be completed. */
+#define RACP_RESPONSE_OPERAND_UNSUPPORTED   9       /**< Record Access Control Point response code - Unsupported operand. */
+
+/**@brief Record Access Control Point value structure. */
+typedef struct
+{
+    uint8_t   opcode;                               /**< Op Code. */
+    uint8_t   operator;                             /**< Operator. */
+    uint8_t   operand_len;                          /**< Length of the operand. */
+    uint8_t * p_operand;                            /**< Pointer to the operand. */
+} ble_racp_value_t;
+
+/**@brief Function for decoding a Record Access Control Point write.
+ *
+ * @details This call decodes a write to the Record Access Control Point.
+ *
+ * @param[in]   data_len     Length of data in received write.
+ * @param[in]   p_data       Pointer to received data.
+ * @param[out]  p_racp_val   Pointer to decoded Record Access Control Point write.
+ *                           @note This does not do a data copy. It assumes the data pointed to by
+ *                                 p_data is persistant until no longer needed.
+ */
+void ble_racp_decode(uint8_t data_len, uint8_t * p_data, ble_racp_value_t * p_racp_val);
+
+/**@brief Function for encoding a Record Access Control Point response.
+ *
+ * @details This call encodes a response from the Record Access Control Point response.
+ *
+ * @param[in]   p_racp_val   Pointer to Record Access Control Point to encode.
+ * @param[out]  p_data       Pointer to where encoded data is written.
+ *                           NOTE! It is calling routines respsonsibility to make sure.
+ *
+ * @return      Length of encoded data.
+ */
+uint8_t ble_racp_encode(const ble_racp_value_t * p_racp_val, uint8_t * p_data);
+
+#endif // BLE_RACP_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.c
new file mode 100644
index 0000000000..b460733871
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.c
@@ -0,0 +1,88 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_radio_notification.h"
+#include <stdlib.h>
+#include "nrf_nvic.h"
+
+
+static bool                                 m_radio_active = false;  /**< Current radio state. */
+static ble_radio_notification_evt_handler_t m_evt_handler  = NULL;   /**< Application event handler for handling Radio Notification events. */
+
+
+void SWI1_IRQHandler(void)
+{
+    m_radio_active = !m_radio_active;
+    if (m_evt_handler != NULL)
+    {
+        m_evt_handler(m_radio_active);
+    }
+}
+
+
+uint32_t ble_radio_notification_init(uint32_t                             irq_priority,
+                                     uint8_t                              distance,
+                                     ble_radio_notification_evt_handler_t evt_handler)
+{
+    uint32_t err_code;
+
+    m_evt_handler = evt_handler;
+
+    // Initialize Radio Notification software interrupt
+    err_code = sd_nvic_ClearPendingIRQ(SWI1_IRQn);
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    err_code = sd_nvic_SetPriority(SWI1_IRQn, irq_priority);
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    err_code = sd_nvic_EnableIRQ(SWI1_IRQn);
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    // Configure the event
+    return sd_radio_notification_cfg_set(NRF_RADIO_NOTIFICATION_TYPE_INT_ON_BOTH, distance);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.h
new file mode 100644
index 0000000000..02e5b25bf0
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_radio_notification/ble_radio_notification.h
@@ -0,0 +1,74 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_radio_notification Radio Notification Event Handler
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for propagating Radio Notification events to the application.
+ */
+
+#ifndef BLE_RADIO_NOTIFICATION_H__
+#define BLE_RADIO_NOTIFICATION_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_soc.h"
+
+
+/**@brief Application radio notification event handler type. */
+typedef void (*ble_radio_notification_evt_handler_t) (bool radio_active);
+
+/**@brief Function for initializing the Radio Notification module.
+ *
+ * @param[in]  irq_priority   Interrupt priority for the Radio Notification interrupt handler.
+ * @param[in]  distance       The time from an Active event until the radio is activated.
+ * @param[in]  evt_handler    Handler to be executed when a radio notification event has been
+ *                            received.
+ *
+ * @return     NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_radio_notification_init(uint32_t                             irq_priority,
+                                     uint8_t                              distance,
+                                     ble_radio_notification_evt_handler_t evt_handler);
+
+#endif // BLE_RADIO_NOTIFICATION_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.c
new file mode 100644
index 0000000000..333533af54
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.c
@@ -0,0 +1,676 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_dfu.h"
+#include "nrf_ble_types.h"
+#include "nrf_ble_gatts.h"
+#include "ble_srv_common.h"
+#include <stddef.h>
+#include "sdk_common.h"
+
+#define MAX_DFU_PKT_LEN         20                                              /**< Maximum length (in bytes) of the DFU Packet characteristic. */
+#define PKT_START_DFU_PARAM_LEN 2                                               /**< Length (in bytes) of the parameters for Packet Start DFU Request. */
+#define PKT_INIT_DFU_PARAM_LEN  2                                               /**< Length (in bytes) of the parameters for Packet Init DFU Request. */
+#define PKT_RCPT_NOTIF_REQ_LEN  3                                               /**< Length (in bytes) of the Packet Receipt Notification Request. */
+#define MAX_PKTS_RCPT_NOTIF_LEN 6                                               /**< Maximum length (in bytes) of the Packets Receipt Notification. */
+#define MAX_RESPONSE_LEN        7                                               /**< Maximum length (in bytes) of the response to a Control Point command. */
+#define MAX_NOTIF_BUFFER_LEN    MAX(MAX_PKTS_RCPT_NOTIF_LEN, MAX_RESPONSE_LEN)  /**< Maximum length (in bytes) of the buffer needed by DFU Service while sending notifications to peer. */
+
+enum
+{
+    OP_CODE_START_DFU          = 1,                                             /**< Value of the Op code field for 'Start DFU' command.*/
+    OP_CODE_RECEIVE_INIT       = 2,                                             /**< Value of the Op code field for 'Initialize DFU parameters' command.*/
+    OP_CODE_RECEIVE_FW         = 3,                                             /**< Value of the Op code field for 'Receive firmware image' command.*/
+    OP_CODE_VALIDATE           = 4,                                             /**< Value of the Op code field for 'Validate firmware' command.*/
+    OP_CODE_ACTIVATE_N_RESET   = 5,                                             /**< Value of the Op code field for 'Activate & Reset' command.*/
+    OP_CODE_SYS_RESET          = 6,                                             /**< Value of the Op code field for 'Reset System' command.*/
+    OP_CODE_IMAGE_SIZE_REQ     = 7,                                             /**< Value of the Op code field for 'Report received image size' command.*/
+    OP_CODE_PKT_RCPT_NOTIF_REQ = 8,                                             /**< Value of the Op code field for 'Request packet receipt notification.*/
+    OP_CODE_RESPONSE           = 16,                                            /**< Value of the Op code field for 'Response.*/
+    OP_CODE_PKT_RCPT_NOTIF     = 17                                             /**< Value of the Op code field for 'Packets Receipt Notification'.*/
+};
+
+static bool     m_is_dfu_service_initialized = false;                           /**< Variable to check if the DFU service was initialized by the application.*/
+static uint8_t  m_notif_buffer[MAX_NOTIF_BUFFER_LEN];                           /**< Buffer used for sending notifications to peer. */
+
+/**@brief       Function for adding DFU Packet characteristic to the BLE Stack.
+ *
+ * @param[in]   p_dfu DFU Service structure.
+ *
+ * @return      NRF_SUCCESS on success. Otherwise an error code.
+ */
+static uint32_t dfu_pkt_char_add(ble_dfu_t * const p_dfu)
+{
+    ble_gatts_char_md_t char_md;
+    ble_gatts_attr_t    attr_char_value;
+    ble_uuid_t          char_uuid;
+    ble_gatts_attr_md_t attr_md;
+
+    memset(&char_md, 0, sizeof(char_md));
+
+    char_md.char_props.write_wo_resp = 1;
+    char_md.p_char_user_desc         = NULL;
+    char_md.p_char_pf                = NULL;
+    char_md.p_user_desc_md           = NULL;
+    char_md.p_cccd_md                = NULL;
+    char_md.p_sccd_md                = NULL;
+
+    char_uuid.type = p_dfu->uuid_type;
+    char_uuid.uuid = BLE_DFU_PKT_CHAR_UUID;
+
+    memset(&attr_md, 0, sizeof(attr_md));
+
+    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm);
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
+
+    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
+    attr_md.rd_auth = 0;
+    attr_md.wr_auth = 0;
+    attr_md.vlen    = 1;
+
+    memset(&attr_char_value, 0, sizeof(attr_char_value));
+
+    attr_char_value.p_uuid    = &char_uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.init_len  = 0;
+    attr_char_value.init_offs = 0;
+    attr_char_value.max_len   = MAX_DFU_PKT_LEN;
+    attr_char_value.p_value   = NULL;
+
+    return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
+                                           &char_md,
+                                           &attr_char_value,
+                                           &p_dfu->dfu_pkt_handles);
+}
+
+
+/**@brief       Function for adding DFU Revision characteristic to the BLE Stack.
+ *
+ * @param[in]   p_dfu DFU Service structure.
+ *
+ * @return      NRF_SUCCESS on success. Otherwise an error code.
+ */
+static uint32_t dfu_rev_char_add(ble_dfu_t * const p_dfu, ble_dfu_init_t const * const p_dfu_init)
+{
+    ble_gatts_char_md_t char_md;
+    ble_gatts_attr_t    attr_char_value;
+    ble_uuid_t          char_uuid;
+    ble_gatts_attr_md_t attr_md;
+
+    memset(&char_md, 0, sizeof(char_md));
+
+    char_md.char_props.read          = 1;
+    char_md.p_char_user_desc         = NULL;
+    char_md.p_char_pf                = NULL;
+    char_md.p_user_desc_md           = NULL;
+    char_md.p_cccd_md                = NULL;
+    char_md.p_sccd_md                = NULL;
+
+    char_uuid.type = p_dfu->uuid_type;
+    char_uuid.uuid = BLE_DFU_REV_CHAR_UUID;
+
+    memset(&attr_md, 0, sizeof(attr_md));
+
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.read_perm);
+    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.write_perm);
+
+    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
+    attr_md.rd_auth = 0;
+    attr_md.wr_auth = 0;
+    attr_md.vlen    = 1;
+
+    memset(&attr_char_value, 0, sizeof(attr_char_value));
+
+    attr_char_value.p_uuid    = &char_uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.init_len  = sizeof(uint16_t);
+    attr_char_value.init_offs = 0;
+    attr_char_value.max_len   = sizeof(uint16_t);
+    attr_char_value.p_value   = (uint8_t *)&p_dfu_init->revision;
+
+    return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
+                                           &char_md,
+                                           &attr_char_value,
+                                           &p_dfu->dfu_rev_handles);
+}
+
+
+/**@brief       Function for adding DFU Control Point characteristic to the BLE Stack.
+ *
+ * @param[in]   p_dfu DFU Service structure.
+ *
+ * @return      NRF_SUCCESS on success. Otherwise an error code.
+ */
+static uint32_t dfu_ctrl_pt_add(ble_dfu_t * const p_dfu)
+{
+    ble_gatts_char_md_t char_md;
+    ble_gatts_attr_t    attr_char_value;
+    ble_uuid_t          char_uuid;
+    ble_gatts_attr_md_t attr_md;
+
+    memset(&char_md, 0, sizeof(char_md));
+
+    char_md.char_props.write  = 1;
+    char_md.char_props.notify = 1;
+    char_md.p_char_user_desc  = NULL;
+    char_md.p_char_pf         = NULL;
+    char_md.p_user_desc_md    = NULL;
+    char_md.p_cccd_md         = NULL;
+    char_md.p_sccd_md         = NULL;
+
+    char_uuid.type = p_dfu->uuid_type;
+    char_uuid.uuid = BLE_DFU_CTRL_PT_UUID;
+
+    memset(&attr_md, 0, sizeof(attr_md));
+
+    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(&attr_md.read_perm);
+    BLE_GAP_CONN_SEC_MODE_SET_OPEN(&attr_md.write_perm);
+
+    attr_md.vloc    = BLE_GATTS_VLOC_STACK;
+    attr_md.rd_auth = 0;
+    attr_md.wr_auth = 1;
+    attr_md.vlen    = 1;
+
+    memset(&attr_char_value, 0, sizeof(attr_char_value));
+
+    attr_char_value.p_uuid    = &char_uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.init_len  = 0;
+    attr_char_value.init_offs = 0;
+    attr_char_value.max_len   = BLE_L2CAP_MTU_DEF;
+    attr_char_value.p_value   = NULL;
+
+    return sd_ble_gatts_characteristic_add(p_dfu->service_handle,
+                                           &char_md,
+                                           &attr_char_value,
+                                           &p_dfu->dfu_ctrl_pt_handles);
+}
+
+
+/**@brief     Function for handling the @ref BLE_GAP_EVT_CONNECTED event from the S110 SoftDevice.
+ *
+ * @param[in] p_dfu     DFU Service Structure.
+ * @param[in] p_ble_evt Pointer to the event received from BLE stack.
+ */
+static void on_connect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
+{
+    p_dfu->conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
+}
+
+
+/**@brief     Function for checking if the CCCD of DFU Control point is configured for Notification.
+ *
+ * @details   This function checks if the CCCD of DFU Control Point characteristic is configured
+ *            for Notification by the DFU Controller.
+ *
+ * @param[in] p_dfu DFU Service structure.
+ *
+ * @return    True if the CCCD of DFU Control Point characteristic is configured for Notification.
+ *            False otherwise.
+ */
+static bool is_cccd_configured(ble_dfu_t * p_dfu)
+{
+    // Check if the CCCDs are configured.
+    uint8_t  cccd_val_buf[BLE_CCCD_VALUE_LEN];
+    ble_gatts_value_t gatts_value;
+
+    // Initialize value struct.
+    memset(&gatts_value, 0, sizeof(gatts_value));
+
+    gatts_value.len     = BLE_CCCD_VALUE_LEN;
+    gatts_value.offset  = 0;
+    gatts_value.p_value = cccd_val_buf;
+
+    // Check the CCCD Value of DFU Control Point.
+    uint32_t err_code = sd_ble_gatts_value_get(p_dfu->conn_handle,
+                                               p_dfu->dfu_ctrl_pt_handles.cccd_handle,
+                                               &gatts_value);
+    if (err_code != NRF_SUCCESS)
+    {
+        if (p_dfu->error_handler != NULL)
+        {
+            p_dfu->error_handler(err_code);
+        }
+        return false;
+    }
+
+    return ble_srv_is_notification_enabled(cccd_val_buf);
+}
+
+
+/**@brief     Function for handling a Write event on the Control Point characteristic.
+ *
+ * @param[in] p_dfu             DFU Service Structure.
+ * @param[in] p_ble_write_evt   Pointer to the write event received from BLE stack.
+ *
+ * @return    NRF_SUCCESS on successful processing of control point write. Otherwise an error code.
+ */
+static uint32_t on_ctrl_pt_write(ble_dfu_t * p_dfu, ble_gatts_evt_write_t * p_ble_write_evt)
+{
+    ble_gatts_rw_authorize_reply_params_t auth_reply;
+
+    auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE;
+    auth_reply.type = BLE_GATTS_AUTHORIZE_TYPE_WRITE;
+    auth_reply.params.write.update = 1;
+    auth_reply.params.write.offset = p_ble_write_evt->offset;
+    auth_reply.params.write.len = p_ble_write_evt->len;
+    auth_reply.params.write.p_data = p_ble_write_evt->data;
+
+
+    if (!is_cccd_configured(p_dfu))
+    {
+        // Send an error response to the peer indicating that the CCCD is improperly configured.
+        auth_reply.params.write.gatt_status =
+            BLE_GATT_STATUS_ATTERR_CPS_CCCD_CONFIG_ERROR;
+
+        return (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &auth_reply));
+
+    }
+    else
+    {
+        uint32_t err_code;
+
+        auth_reply.params.write.gatt_status = BLE_GATT_STATUS_SUCCESS;
+
+        err_code = (sd_ble_gatts_rw_authorize_reply(p_dfu->conn_handle, &auth_reply));
+        VERIFY_SUCCESS(err_code);
+    }
+
+    ble_dfu_evt_t ble_dfu_evt;
+
+    switch (p_ble_write_evt->data[0])
+    {
+        case OP_CODE_START_DFU:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_START;
+
+            if (p_ble_write_evt->len < PKT_START_DFU_PARAM_LEN)
+            {
+                return ble_dfu_response_send(p_dfu,
+                                             (ble_dfu_procedure_t) p_ble_write_evt->data[0],
+                                             BLE_DFU_RESP_VAL_OPER_FAILED);
+            }
+
+            ble_dfu_evt.evt.ble_dfu_pkt_write.len    = 1;
+            ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]);
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        case OP_CODE_RECEIVE_INIT:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_INIT_DATA;
+
+            if (p_ble_write_evt->len < PKT_INIT_DFU_PARAM_LEN)
+            {
+                return ble_dfu_response_send(p_dfu,
+                                             (ble_dfu_procedure_t) p_ble_write_evt->data[0],
+                                             BLE_DFU_RESP_VAL_OPER_FAILED);
+            }
+
+            ble_dfu_evt.evt.ble_dfu_pkt_write.len    = 1;
+            ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = &(p_ble_write_evt->data[1]);
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        case OP_CODE_RECEIVE_FW:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_RECEIVE_APP_DATA;
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        case OP_CODE_VALIDATE:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_VALIDATE;
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        case OP_CODE_ACTIVATE_N_RESET:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_ACTIVATE_N_RESET;
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        case OP_CODE_SYS_RESET:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_SYS_RESET;
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        case OP_CODE_PKT_RCPT_NOTIF_REQ:
+            if (p_ble_write_evt->len < PKT_RCPT_NOTIF_REQ_LEN)
+            {
+                return (ble_dfu_response_send(p_dfu,
+                                              BLE_DFU_PKT_RCPT_REQ_PROCEDURE,
+                                              BLE_DFU_RESP_VAL_NOT_SUPPORTED));
+            }
+
+            ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts =
+                uint16_decode(&(p_ble_write_evt->data[1]));
+
+            if (ble_dfu_evt.evt.pkt_rcpt_notif_req.num_of_pkts == 0)
+            {
+                ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_DISABLED;
+            }
+            else
+            {
+                ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_PKT_RCPT_NOTIF_ENABLED;
+            }
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+
+            break;
+
+        case OP_CODE_IMAGE_SIZE_REQ:
+            ble_dfu_evt.ble_dfu_evt_type = BLE_DFU_BYTES_RECEIVED_SEND;
+
+            p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+            break;
+
+        default:
+            // Unsupported op code.
+            return ble_dfu_response_send(p_dfu,
+                                         (ble_dfu_procedure_t) p_ble_write_evt->data[0],
+                                         BLE_DFU_RESP_VAL_NOT_SUPPORTED);
+    }
+    return NRF_SUCCESS;
+}
+
+
+/**@brief     Function for handling the @ref BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST event from the S110
+ *            Stack.
+ *
+ * @param[in] p_dfu     DFU Service Structure.
+ * @param[in] p_ble_evt Pointer to the event received from BLE stack.
+ */
+static void on_rw_authorize_req(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
+{
+    ble_gatts_evt_rw_authorize_request_t * p_authorize_request;
+
+    p_authorize_request = &(p_ble_evt->evt.gatts_evt.params.authorize_request);
+
+    if (
+        (p_authorize_request->type == BLE_GATTS_AUTHORIZE_TYPE_WRITE)
+        &&
+        (p_authorize_request->request.write.handle == p_dfu->dfu_ctrl_pt_handles.value_handle)
+        &&
+        (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_PREP_WRITE_REQ)
+        &&
+        (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_EXEC_WRITE_REQ_NOW)
+        &&
+        (p_ble_evt->evt.gatts_evt.params.authorize_request.request.write.op != BLE_GATTS_OP_EXEC_WRITE_REQ_CANCEL)
+       )
+    {
+        uint32_t err_code;
+
+        err_code = on_ctrl_pt_write(p_dfu, &(p_authorize_request->request.write));
+
+        if (err_code != NRF_SUCCESS && p_dfu->error_handler != NULL)
+        {
+            p_dfu->error_handler(err_code);
+        }
+    }
+}
+
+
+/**@brief     Function for handling the @ref BLE_GATTS_EVT_WRITE event from the S110 SoftDevice.
+ *
+ * @param[in] p_dfu     DFU Service Structure.
+ * @param[in] p_ble_evt Pointer to the event received from BLE stack.
+ */
+static void on_write(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
+{
+    if (p_ble_evt->evt.gatts_evt.params.write.handle == p_dfu->dfu_pkt_handles.value_handle)
+    {
+        // DFU Packet written
+
+        ble_dfu_evt_t ble_dfu_evt;
+
+        ble_dfu_evt.ble_dfu_evt_type             = BLE_DFU_PACKET_WRITE;
+        ble_dfu_evt.evt.ble_dfu_pkt_write.len    = p_ble_evt->evt.gatts_evt.params.write.len;
+        ble_dfu_evt.evt.ble_dfu_pkt_write.p_data = p_ble_evt->evt.gatts_evt.params.write.data;
+
+        p_dfu->evt_handler(p_dfu, &ble_dfu_evt);
+    }
+}
+
+
+/**@brief     Function for handling the BLE_GAP_EVT_DISCONNECTED event from the S110 SoftDevice.
+ *
+ * @param[in] p_dfu     DFU Service Structure.
+ * @param[in] p_ble_evt Pointer to the event received from BLE stack.
+ */
+static void on_disconnect(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
+{
+    p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID;
+}
+
+
+uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init)
+{
+    if ((p_dfu == NULL) || (p_dfu_init == NULL) || (p_dfu_init->evt_handler == NULL))
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    p_dfu->conn_handle = BLE_CONN_HANDLE_INVALID;
+
+    ble_uuid_t service_uuid;
+    uint32_t   err_code;
+
+    const ble_uuid128_t base_uuid128 =
+    {
+        {
+            0x23, 0xD1, 0xBC, 0xEA, 0x5F, 0x78, 0x23, 0x15,
+            0xDE, 0xEF, 0x12, 0x12, 0x00, 0x00, 0x00, 0x00
+        }
+    };
+
+    service_uuid.uuid = BLE_DFU_SERVICE_UUID;
+
+    err_code = sd_ble_uuid_vs_add(&base_uuid128, &(service_uuid.type));
+    VERIFY_SUCCESS(err_code);
+
+    err_code = sd_ble_gatts_service_add(BLE_GATTS_SRVC_TYPE_PRIMARY,
+                                        &service_uuid,
+                                        &(p_dfu->service_handle));
+    VERIFY_SUCCESS(err_code);
+
+    p_dfu->uuid_type = service_uuid.type;
+
+    err_code = dfu_pkt_char_add(p_dfu);
+    VERIFY_SUCCESS(err_code);
+
+    err_code = dfu_ctrl_pt_add(p_dfu);
+    VERIFY_SUCCESS(err_code);
+
+    err_code = dfu_rev_char_add(p_dfu, p_dfu_init);
+    VERIFY_SUCCESS(err_code);
+
+    p_dfu->evt_handler = p_dfu_init->evt_handler;
+
+    if (p_dfu_init->error_handler != NULL)
+    {
+        p_dfu->error_handler = p_dfu_init->error_handler;
+    }
+
+    m_is_dfu_service_initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+
+void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt)
+{
+    if ((p_dfu == NULL) || (p_ble_evt == NULL))
+    {
+        return;
+    }
+
+    if (p_dfu->evt_handler != NULL)
+    {
+        switch (p_ble_evt->header.evt_id)
+        {
+            case BLE_GAP_EVT_CONNECTED:
+                on_connect(p_dfu, p_ble_evt);
+                break;
+
+            case BLE_GATTS_EVT_WRITE:
+                on_write(p_dfu, p_ble_evt);
+                break;
+
+            case BLE_GAP_EVT_DISCONNECTED:
+                on_disconnect(p_dfu, p_ble_evt);
+                break;
+
+            case BLE_GATTS_EVT_RW_AUTHORIZE_REQUEST:
+                on_rw_authorize_req(p_dfu, p_ble_evt);
+                break;
+
+            default:
+                // No implementation needed.
+                break;
+        }
+    }
+}
+
+
+uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd)
+{
+    if (p_dfu == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    ble_gatts_hvx_params_t hvx_params;
+    uint16_t               index = 0;
+
+    // Encode the Op Code.
+    m_notif_buffer[index++] = OP_CODE_RESPONSE;
+
+    // Encode the Reqest Op Code.
+    m_notif_buffer[index++] = OP_CODE_IMAGE_SIZE_REQ;
+
+    // Encode the Response Value.
+    m_notif_buffer[index++] = (uint8_t)BLE_DFU_RESP_VAL_SUCCESS;
+
+    index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]);
+
+    memset(&hvx_params, 0, sizeof(hvx_params));
+
+    hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
+    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
+    hvx_params.offset = 0;
+    hvx_params.p_len  = &index;
+    hvx_params.p_data = m_notif_buffer;
+
+    return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
+}
+
+
+uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd)
+{
+    if (p_dfu == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    ble_gatts_hvx_params_t hvx_params;
+    uint16_t               index = 0;
+
+    m_notif_buffer[index++] = OP_CODE_PKT_RCPT_NOTIF;
+
+    index += uint32_encode(num_of_firmware_bytes_rcvd, &m_notif_buffer[index]);
+
+    memset(&hvx_params, 0, sizeof(hvx_params));
+
+    hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
+    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
+    hvx_params.offset = 0;
+    hvx_params.p_len  = &index;
+    hvx_params.p_data = m_notif_buffer;
+
+    return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
+}
+
+
+uint32_t ble_dfu_response_send(ble_dfu_t         * p_dfu,
+                               ble_dfu_procedure_t dfu_proc,
+                               ble_dfu_resp_val_t  resp_val)
+{
+    if (p_dfu == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }
+
+    if ((p_dfu->conn_handle == BLE_CONN_HANDLE_INVALID) || !m_is_dfu_service_initialized)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    ble_gatts_hvx_params_t hvx_params;
+    uint16_t               index = 0;
+
+    m_notif_buffer[index++] = OP_CODE_RESPONSE;
+
+    // Encode the Request Op code
+    m_notif_buffer[index++] = (uint8_t)dfu_proc;
+
+    // Encode the Response Value.
+    m_notif_buffer[index++] = (uint8_t)resp_val;
+
+    memset(&hvx_params, 0, sizeof(hvx_params));
+
+    hvx_params.handle = p_dfu->dfu_ctrl_pt_handles.value_handle;
+    hvx_params.type   = BLE_GATT_HVX_NOTIFICATION;
+    hvx_params.offset = 0;
+    hvx_params.p_len  = &index;
+    hvx_params.p_data = m_notif_buffer;
+
+    return sd_ble_gatts_hvx(p_dfu->conn_handle, &hvx_params);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.h
new file mode 100644
index 0000000000..9ce409ee2f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/ble_services/ble_dfu/ble_dfu.h
@@ -0,0 +1,266 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup ble_sdk_srv_dfu Device Firmware Update Service
+ * @{
+ * @ingroup  ble_sdk_srv
+ * @brief    Device Firmware Update Service
+ *
+ * @details  The Device Firmware Update (DFU) service is a GATT based service that can be used for
+ *           performing firmware updates over BLE. Note that this implementation uses vendor
+ *           specific UUIDs for service and characteristics and is intended to demonstrate the
+ *           firmware updates over BLE. Refer @ref bledfu_transport_bleservice and @ref
+ *            bledfu_transport_bleprofile for more information on the service and profile respectively.
+ */
+
+#ifndef BLE_DFU_H__
+#define BLE_DFU_H__
+
+#include <stdint.h>
+#include "nrf_ble_gatts.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble.h"
+#include "ble_srv_common.h"
+
+#define BLE_DFU_SERVICE_UUID                 0x1530                       /**< The UUID of the DFU Service. */
+#define BLE_DFU_PKT_CHAR_UUID                0x1532                       /**< The UUID of the DFU Packet Characteristic. */
+#define BLE_DFU_CTRL_PT_UUID                 0x1531                       /**< The UUID of the DFU Control Point. */
+#define BLE_DFU_STATUS_REP_UUID              0x1533                       /**< The UUID of the DFU Status Report Characteristic. */
+#define BLE_DFU_REV_CHAR_UUID                0x1534                       /**< The UUID of the DFU Revision Characteristic. */
+
+/**@brief   DFU Event type.
+ *
+ * @details This enumeration contains the types of events that will be received from the DFU Service.
+ */
+typedef enum
+{
+    BLE_DFU_START,                                                      /**< The event indicating that the peer wants the application to prepare for a new firmware update. */
+    BLE_DFU_RECEIVE_INIT_DATA,                                          /**< The event indicating that the peer wants the application to prepare to receive init parameters. */
+    BLE_DFU_RECEIVE_APP_DATA,                                           /**< The event indicating that the peer wants the application to prepare to receive the new firmware image. */
+    BLE_DFU_VALIDATE,                                                   /**< The event indicating that the peer wants the application to validate the newly received firmware image. */
+    BLE_DFU_ACTIVATE_N_RESET,                                           /**< The event indicating that the peer wants the application to undergo activate new firmware and restart with new valid application */
+    BLE_DFU_SYS_RESET,                                                  /**< The event indicating that the peer wants the application to undergo a reset and start the currently valid application image.*/
+    BLE_DFU_PKT_RCPT_NOTIF_ENABLED,                                     /**< The event indicating that the peer has enabled packet receipt notifications. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify each time the number of packets indicated by num_of_pkts field in @ref ble_dfu_evt_t is received.*/
+    BLE_DFU_PKT_RCPT_NOTIF_DISABLED,                                    /**< The event indicating that the peer has disabled the packet receipt notifications.*/
+    BLE_DFU_PACKET_WRITE,                                               /**< The event indicating that the peer has written a value to the 'DFU Packet' characteristic. The data received from the peer will be present in the @ref BLE_DFU_PACKET_WRITE element contained within @ref ble_dfu_evt_t.*/
+    BLE_DFU_BYTES_RECEIVED_SEND                                         /**< The event indicating that the peer is requesting for the number of bytes of firmware data last received by the application. It is the responsibility of the application to call @ref ble_dfu_pkts_rcpt_notify in response to this event. */
+} ble_dfu_evt_type_t;
+
+/**@brief   DFU Procedure type.
+ *
+ * @details This enumeration contains the types of DFU procedures.
+ */
+typedef enum
+{
+    BLE_DFU_START_PROCEDURE        = 1,                                 /**< DFU Start procedure.*/
+    BLE_DFU_INIT_PROCEDURE         = 2,                                 /**< DFU Initialization procedure.*/
+    BLE_DFU_RECEIVE_APP_PROCEDURE  = 3,                                 /**< Firmware receiving procedure.*/
+    BLE_DFU_VALIDATE_PROCEDURE     = 4,                                 /**< Firmware image validation procedure .*/
+    BLE_DFU_PKT_RCPT_REQ_PROCEDURE = 8                                  /**< Packet receipt notification request procedure. */
+} ble_dfu_procedure_t;
+
+/**@brief   DFU Response value type.
+ */
+typedef enum
+{
+    BLE_DFU_RESP_VAL_SUCCESS = 1,                                       /**< Success.*/
+    BLE_DFU_RESP_VAL_INVALID_STATE,                                     /**< Invalid state.*/
+    BLE_DFU_RESP_VAL_NOT_SUPPORTED,                                     /**< Operation not supported.*/
+    BLE_DFU_RESP_VAL_DATA_SIZE,                                         /**< Data size exceeds limit.*/
+    BLE_DFU_RESP_VAL_CRC_ERROR,                                         /**< CRC Error.*/
+    BLE_DFU_RESP_VAL_OPER_FAILED                                        /**< Operation failed.*/
+} ble_dfu_resp_val_t;
+
+
+/**@brief   DFU Packet structure.
+ *
+ * @details This structure contains the value of the DFU Packet characteristic as written by the
+ *          peer and the length of the value written. It will be filled by the DFU Service when the
+ *          peer writes to the DFU Packet characteristic.
+ */
+typedef struct
+{
+    uint8_t *                    p_data;                                /**< Pointer to the received packet. This will point to a word aligned memory location.*/
+    uint8_t                      len;                                   /**< Length of the packet received. */
+} ble_dfu_pkt_write_t;
+
+/**@brief   Packet receipt notification request structure.
+ *
+ * @details This structure contains the contents of the packet receipt notification request
+ *          sent by the DFU Controller.
+ */
+typedef struct
+{
+    uint16_t                     num_of_pkts;                           /**< The number of packets of firmware data to be received by application before sending the next Packet Receipt Notification to the peer. */
+} ble_pkt_rcpt_notif_req_t;
+
+/**@brief   DFU Event structure.
+ *
+ * @details This structure contains the event generated by the DFU Service based on the data
+ *          received from the peer.
+ */
+typedef struct
+{
+    ble_dfu_evt_type_t           ble_dfu_evt_type;                      /**< Type of the event.*/
+    union
+    {
+        ble_dfu_pkt_write_t      ble_dfu_pkt_write;                     /**< The DFU packet received. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PACKET_WRITE.*/
+        ble_pkt_rcpt_notif_req_t pkt_rcpt_notif_req;                    /**< Packet receipt notification request. This field is when the @ref ble_dfu_evt_type field is set to @ref BLE_DFU_PKT_RCPT_NOTIF_ENABLED.*/
+    } evt;
+} ble_dfu_evt_t;
+
+// Forward declaration of the ble_dfu_t type.
+typedef struct ble_dfu_s ble_dfu_t;
+
+/**@brief DFU Service event handler type. */
+typedef void (*ble_dfu_evt_handler_t) (ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt);
+
+/**@brief   DFU service structure.
+ *
+ * @details This structure contains status information related to the service.
+ */
+struct ble_dfu_s
+{
+    uint16_t                     conn_handle;                           /**< Handle of the current connection (as provided by the SoftDevice). This will be BLE_CONN_HANDLE_INVALID when not in a connection. */
+    uint16_t                     revision;                              /**< Handle of DFU Service (as provided by the SoftDevice). */
+    uint16_t                     service_handle;                        /**< Handle of DFU Service (as provided by the SoftDevice). */
+    uint8_t                      uuid_type;                             /**< UUID type assigned for DFU Service by the SoftDevice. */
+    ble_gatts_char_handles_t     dfu_pkt_handles;                       /**< Handles related to the DFU Packet characteristic. */
+    ble_gatts_char_handles_t     dfu_ctrl_pt_handles;                   /**< Handles related to the DFU Control Point characteristic. */
+    ble_gatts_char_handles_t     dfu_status_rep_handles;                /**< Handles related to the DFU Status Report characteristic. */
+    ble_gatts_char_handles_t     dfu_rev_handles;                       /**< Handles related to the DFU Revision characteristic. */
+    ble_dfu_evt_handler_t        evt_handler;                           /**< The event handler to be called when an event is to be sent to the application.*/
+    ble_srv_error_handler_t      error_handler;                         /**< Function to be called in case of an error. */
+};
+
+/**@brief      DFU service initialization structure.
+ *
+ * @details    This structure contains the initialization information for the DFU Service. The
+ *             application needs to fill this structure and pass it to the DFU Service using the
+ *             @ref ble_dfu_init function.
+ */
+typedef struct
+{
+    uint16_t                     revision;                              /**< Revision number to be exposed by the DFU service. */
+    ble_dfu_evt_handler_t        evt_handler;                           /**< Event handler to be called for handling events in the Device Firmware Update Service. */
+    ble_srv_error_handler_t      error_handler;                         /**< Function to be called in case of an error. */
+} ble_dfu_init_t;
+
+/**@brief      Function for handling a BLE event.
+ *
+ * @details    The DFU service expects the application to call this function each time an event
+ *             is received from the SoftDevice. This function processes the event, if it is
+ *             relevant for the DFU service and calls the DFU event handler of the application if
+ *             necessary.
+ *
+ * @param[in]  p_dfu        Pointer to the DFU service structure.
+ * @param[in]  p_ble_evt    Pointer to the event received from SoftDevice.
+ */
+void ble_dfu_on_ble_evt(ble_dfu_t * p_dfu, ble_evt_t * p_ble_evt);
+
+/**@brief      Function for initializing the DFU service.
+ *
+ * @param[out] p_dfu        Device Firmware Update service structure. This structure will have to be
+ *                          supplied by the application. It will be initialized by this function,
+ *                          and will later be used to identify the service instance.
+ * @param[in]  p_dfu_init   Information needed to initialize the service.
+ *
+ * @return     NRF_SUCCESS if the DFU service and its characteristics were successfully added to the
+ *             SoftDevice. Otherwise an error code.
+ *             This function returns NRF_ERROR_NULL if the value of evt_handler in p_dfu_init
+ *             structure provided is NULL or if the pointers supplied as input are NULL.
+ */
+uint32_t ble_dfu_init(ble_dfu_t * p_dfu, ble_dfu_init_t * p_dfu_init);
+
+/**@brief       Function for sending response to a control point command.
+ *
+ * @details     This function will encode a DFU Control Point response using the given input
+ *              parameters and will send a notification of the same to the peer.
+ *
+ * @param[in]   p_dfu       Pointer to the DFU service structure.
+ * @param[in]   dfu_proc    Procedure for which this response is to be sent.
+ * @param[in]   resp_val    Response value.
+ *
+ * @return      NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to
+ *              send the notification. Otherwise an error code.
+ *              This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
+ *              peer or if the DFU service is not initialized or if the notification of the DFU
+ *              Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
+ *              if the pointer p_dfu is NULL.
+ */
+uint32_t ble_dfu_response_send(ble_dfu_t *          p_dfu,
+                               ble_dfu_procedure_t  dfu_proc,
+                               ble_dfu_resp_val_t   resp_val);
+
+/**@brief      Function for notifying the peer about the number of bytes of firmware data received.
+ *
+ * @param[in]  p_dfu                      Pointer to the DFU service structure.
+ * @param[in]  num_of_firmware_bytes_rcvd Number of bytes.
+ *
+ * @return     NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to send
+ *             the notification. Otherwise an error code.
+ *             This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
+ *             peer or if the DFU service is not initialized or if the notification of the DFU
+ *             Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
+ *             if the pointer p_dfu is NULL.
+ */
+uint32_t ble_dfu_bytes_rcvd_report(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
+
+/**@brief      Function for sending Packet Receipt Notification to the peer.
+ *
+ *             This function will encode the number of bytes received as input parameter into a
+ *             notification of the control point characteristic and send it to the peer.
+ *
+ * @param[in]  p_dfu                      Pointer to the DFU service structure.
+ * @param[in]  num_of_firmware_bytes_rcvd Number of bytes of firmware image received.
+ *
+ * @return     NRF_SUCCESS if the DFU Service has successfully requested the SoftDevice to send
+ *             the notification. Otherwise an error code.
+ *             This function returns NRF_ERROR_INVALID_STATE if the device is not connected to a
+ *             peer or if the DFU service is not initialized or if the notification of the DFU
+ *             Status Report characteristic was not enabled by the peer. It returns NRF_ERROR_NULL
+ *             if the pointer p_dfu is NULL.
+ */
+uint32_t ble_dfu_pkts_rcpt_notify(ble_dfu_t * p_dfu, uint32_t num_of_firmware_bytes_rcvd);
+
+#endif // BLE_DFU_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.c
new file mode 100644
index 0000000000..2b9eaaa286
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.c
@@ -0,0 +1,788 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_advdata.h"
+#include "nrf_ble_gap.h"
+#include "ble_srv_common.h"
+#include "sdk_common.h"
+
+// NOTE: For now, Security Manager Out of Band Flags (OOB) are omitted from the advertising data.
+
+// Types of LE Bluetooth Device Address AD type
+#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC 0UL
+#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM 1UL
+
+static uint32_t tk_value_encode(ble_advdata_tk_value_t * p_tk_value,
+                                uint8_t                * p_encoded_data,
+                                uint16_t               * p_offset,
+                                uint16_t                 max_size)
+{
+    int8_t i;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_TK_VALUE_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode LE Role.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_TK_VALUE_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_SECURITY_MANAGER_TK_VALUE;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+    for (i = AD_TYPE_TK_VALUE_DATA_SIZE - 1; i >= 0; i--, (*p_offset)++)
+    {
+        p_encoded_data[*p_offset] = p_tk_value->tk[i];
+    }
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t le_role_encode(ble_advdata_le_role_t   le_role,
+                               uint8_t               * p_encoded_data,
+                               uint16_t              * p_offset,
+                               uint16_t                max_size)
+{
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_LE_ROLE_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode LE Role.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_LE_ROLE_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_LE_ROLE;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    switch(le_role)
+    {
+        case BLE_ADVDATA_ROLE_ONLY_PERIPH:
+            p_encoded_data[*p_offset] = 0;
+            break;
+        case BLE_ADVDATA_ROLE_ONLY_CENTRAL:
+            p_encoded_data[*p_offset] = 1;
+            break;
+        case BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED:
+            p_encoded_data[*p_offset] = 2;
+            break;
+        case BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED:
+            p_encoded_data[*p_offset] = 3;
+            break;
+        default:
+            return NRF_ERROR_INVALID_PARAM;
+    }
+    *p_offset += AD_TYPE_LE_ROLE_DATA_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t ble_device_addr_encode(uint8_t  * p_encoded_data,
+                                       uint16_t * p_offset,
+                                       uint16_t   max_size)
+{
+    uint32_t err_code;
+    ble_gap_addr_t device_addr;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_BLE_DEVICE_ADDR_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Get BLE address
+    err_code = sd_ble_gap_address_get(&device_addr);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode LE Bluetooth Device Address
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE +
+                                               AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_LE_BLUETOOTH_DEVICE_ADDRESS;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    memcpy(&p_encoded_data[*p_offset], &device_addr.addr[0], BLE_GAP_ADDR_LEN);
+    *p_offset                 += BLE_GAP_ADDR_LEN;
+    if(BLE_GAP_ADDR_TYPE_PUBLIC == device_addr.addr_type)
+    {
+        p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_PUBLIC;
+    }
+    else
+    {
+        p_encoded_data[*p_offset] = AD_TYPE_BLE_DEVICE_ADDR_TYPE_RANDOM;
+    }
+    *p_offset += AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t name_encode(const ble_advdata_t * p_advdata,
+                            uint8_t             * p_encoded_data,
+                            uint16_t            * p_offset,
+                            uint16_t              max_size)
+{
+    uint32_t err_code;
+    uint16_t rem_adv_data_len;
+    uint16_t actual_length;
+    uint8_t  adv_data_format;
+
+
+    // Validate parameters
+    if((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) && (0 == p_advdata->short_name_len))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check for buffer overflow.
+    if ( (((*p_offset) + ADV_AD_DATA_OFFSET) > max_size) ||
+         ( (BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) &&
+           (((*p_offset) + ADV_AD_DATA_OFFSET + p_advdata->short_name_len) > max_size)))
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    rem_adv_data_len = max_size - (*p_offset) - ADV_AD_DATA_OFFSET;
+    actual_length    = rem_adv_data_len;
+
+    // Get GAP device name and length
+    err_code = sd_ble_gap_device_name_get(&p_encoded_data[(*p_offset) + ADV_AD_DATA_OFFSET],
+                                          &actual_length);
+    VERIFY_SUCCESS(err_code);
+
+    // Check if device intend to use short name and it can fit available data size.
+    if ((p_advdata->name_type == BLE_ADVDATA_FULL_NAME) && (actual_length <= rem_adv_data_len))
+    {
+        // Complete device name can fit, setting Complete Name in Adv Data.
+        adv_data_format = BLE_GAP_AD_TYPE_COMPLETE_LOCAL_NAME;
+    }
+    else
+    {
+        // Else short name needs to be used. Or application has requested use of short name.
+        adv_data_format = BLE_GAP_AD_TYPE_SHORT_LOCAL_NAME;
+
+        // If application has set a preference on the short name size, it needs to be considered,
+        // else fit what can be fit.
+        if ((BLE_ADVDATA_SHORT_NAME == p_advdata->name_type) &&
+                (p_advdata->short_name_len <= rem_adv_data_len))
+        {
+            // Short name fits available size.
+            actual_length = p_advdata->short_name_len;
+        }
+        // Else whatever can fit the data buffer will be packed.
+        else
+        {
+            actual_length = rem_adv_data_len;
+        }
+    }
+
+    // There is only 1 byte intended to encode length which is (actual_length + ADV_AD_TYPE_FIELD_SIZE)
+    if(actual_length > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Complete name field in encoded data.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + actual_length);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = adv_data_format;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    *p_offset                 += actual_length;
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t appearance_encode(uint8_t  * p_encoded_data,
+                                  uint16_t * p_offset,
+                                  uint16_t   max_size)
+{
+    uint32_t err_code;
+    uint16_t appearance;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_APPEARANCE_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Get GAP appearance field.
+    err_code = sd_ble_gap_appearance_get(&appearance);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode Length, AD Type and Appearance.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_APPEARANCE_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_APPEARANCE;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    *p_offset                 += uint16_encode(appearance, &p_encoded_data[*p_offset]);
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t flags_encode(int8_t     flags,
+                             uint8_t  * p_encoded_data,
+                             uint16_t * p_offset,
+                             uint16_t   max_size)
+{
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_FLAGS_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode flags.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_FLAGS_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_FLAGS;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = flags;
+    *p_offset                 += AD_TYPE_FLAGS_DATA_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t sec_mgr_oob_flags_encode(uint8_t    oob_flags,
+                                         uint8_t  * p_encoded_data,
+                                         uint16_t * p_offset,
+                                         uint16_t   max_size)
+{
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_OOB_FLAGS_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode flags.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_OOB_FLAGS_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_SECURITY_MANAGER_OOB_FLAGS;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = oob_flags;
+    *p_offset                 += AD_TYPE_OOB_FLAGS_DATA_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+static uint32_t tx_power_level_encode(int8_t     tx_power_level,
+                                      uint8_t  * p_encoded_data,
+                                      uint16_t * p_offset,
+                                      uint16_t   max_size)
+{
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_TX_POWER_LEVEL_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode TX Power Level.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE +
+                                                  AD_TYPE_TX_POWER_LEVEL_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_TX_POWER_LEVEL;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = tx_power_level;
+    *p_offset                 += AD_TYPE_TX_POWER_LEVEL_DATA_SIZE;
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t uuid_list_sized_encode(const ble_advdata_uuid_list_t * p_uuid_list,
+                                       uint8_t                         adv_type,
+                                       uint8_t                         uuid_size,
+                                       uint8_t                       * p_encoded_data,
+                                       uint16_t                      * p_offset,
+                                       uint16_t                        max_size)
+{
+    int      i;
+    bool     is_heading_written = false;
+    uint16_t start_pos          = *p_offset;
+    uint16_t length;
+
+    for (i = 0; i < p_uuid_list->uuid_cnt; i++)
+    {
+        uint32_t   err_code;
+        uint8_t    encoded_size;
+        ble_uuid_t uuid = p_uuid_list->p_uuids[i];
+
+        // Find encoded uuid size.
+        err_code = sd_ble_uuid_encode(&uuid, &encoded_size, NULL);
+        VERIFY_SUCCESS(err_code);
+
+        // Check size.
+        if (encoded_size == uuid_size)
+        {
+            uint8_t heading_bytes = (is_heading_written) ? 0 : ADV_AD_DATA_OFFSET;
+
+            // Check for buffer overflow
+            if (((*p_offset) + encoded_size + heading_bytes) > max_size)
+            {
+                return NRF_ERROR_DATA_SIZE;
+            }
+
+            if (!is_heading_written)
+            {
+                // Write AD structure heading.
+                *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+                p_encoded_data[*p_offset]  = adv_type;
+                *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+                is_heading_written         = true;
+            }
+
+            // Write UUID.
+            err_code = sd_ble_uuid_encode(&uuid, &encoded_size, &p_encoded_data[*p_offset]);
+            VERIFY_SUCCESS(err_code);
+            *p_offset += encoded_size;
+        }
+    }
+
+    if (is_heading_written)
+    {
+        // Write length.
+        length = (*p_offset) - (start_pos + ADV_LENGTH_FIELD_SIZE);
+        // There is only 1 byte intended to encode length
+        if(length > 0x00FF)
+        {
+            return NRF_ERROR_DATA_SIZE;
+        }
+        p_encoded_data[start_pos] = (uint8_t)length;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t uuid_list_encode(const ble_advdata_uuid_list_t * p_uuid_list,
+                                 uint8_t                         adv_type_16,
+                                 uint8_t                         adv_type_128,
+                                 uint8_t                       * p_encoded_data,
+                                 uint16_t                      * p_offset,
+                                 uint16_t                        max_size)
+{
+    uint32_t err_code;
+
+    // Encode 16 bit UUIDs.
+    err_code = uuid_list_sized_encode(p_uuid_list,
+                                      adv_type_16,
+                                      sizeof(uint16_le_t),
+                                      p_encoded_data,
+                                      p_offset,
+                                      max_size);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode 128 bit UUIDs.
+    err_code = uuid_list_sized_encode(p_uuid_list,
+                                      adv_type_128,
+                                      sizeof(ble_uuid128_t),
+                                      p_encoded_data,
+                                      p_offset,
+                                      max_size);
+    VERIFY_SUCCESS(err_code);
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t conn_int_check(const ble_advdata_conn_int_t *p_conn_int)
+{
+    // Check Minimum Connection Interval.
+    if ((p_conn_int->min_conn_interval < 0x0006) ||
+        (
+            (p_conn_int->min_conn_interval > 0x0c80) &&
+            (p_conn_int->min_conn_interval != 0xffff)
+        )
+       )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check Maximum Connection Interval.
+    if ((p_conn_int->max_conn_interval < 0x0006) ||
+        (
+            (p_conn_int->max_conn_interval > 0x0c80) &&
+            (p_conn_int->max_conn_interval != 0xffff)
+        )
+       )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Make sure Minimum Connection Interval is not bigger than Maximum Connection Interval.
+    if ((p_conn_int->min_conn_interval != 0xffff) &&
+        (p_conn_int->max_conn_interval != 0xffff) &&
+        (p_conn_int->min_conn_interval > p_conn_int->max_conn_interval)
+        )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t conn_int_encode(const ble_advdata_conn_int_t * p_conn_int,
+                                uint8_t                      * p_encoded_data,
+                                uint16_t                     * p_offset,
+                                uint16_t                       max_size)
+{
+    uint32_t err_code;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + AD_TYPE_CONN_INT_SIZE) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Check parameters.
+    err_code = conn_int_check(p_conn_int);
+    VERIFY_SUCCESS(err_code);
+
+    // Encode Length and AD Type.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + AD_TYPE_CONN_INT_DATA_SIZE);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_SLAVE_CONNECTION_INTERVAL_RANGE;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+    // Encode Minimum and Maximum Connection Intervals.
+    *p_offset += uint16_encode(p_conn_int->min_conn_interval, &p_encoded_data[*p_offset]);
+    *p_offset += uint16_encode(p_conn_int->max_conn_interval, &p_encoded_data[*p_offset]);
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t manuf_specific_data_encode(const ble_advdata_manuf_data_t * p_manuf_sp_data,
+                                           uint8_t                        * p_encoded_data,
+                                           uint16_t                       * p_offset,
+                                           uint16_t                         max_size)
+{
+    uint32_t data_size = AD_TYPE_MANUF_SPEC_DATA_ID_SIZE + p_manuf_sp_data->data.size;
+
+    // Check for buffer overflow.
+    if (((*p_offset) + ADV_AD_DATA_OFFSET + data_size) > max_size)
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE)
+    if(data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
+    {
+        return NRF_ERROR_DATA_SIZE;
+    }
+
+    // Encode Length and AD Type.
+    p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size);
+    *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+    p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_MANUFACTURER_SPECIFIC_DATA;
+    *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+    // Encode Company Identifier.
+    *p_offset += uint16_encode(p_manuf_sp_data->company_identifier, &p_encoded_data[*p_offset]);
+
+    // Encode additional manufacturer specific data.
+    if (p_manuf_sp_data->data.size > 0)
+    {
+        if (p_manuf_sp_data->data.p_data == NULL)
+        {
+            return NRF_ERROR_INVALID_PARAM;
+        }
+        memcpy(&p_encoded_data[*p_offset], p_manuf_sp_data->data.p_data, p_manuf_sp_data->data.size);
+        *p_offset += p_manuf_sp_data->data.size;
+    }
+
+    return NRF_SUCCESS;
+}
+
+// Implemented only for 16-bit UUIDs
+static uint32_t service_data_encode(const ble_advdata_t * p_advdata,
+                                    uint8_t             * p_encoded_data,
+                                    uint16_t            * p_offset,
+                                    uint16_t              max_size)
+{
+    uint8_t i;
+
+    // Check parameter consistency.
+    if (p_advdata->p_service_data_array == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    for (i = 0; i < p_advdata->service_data_count; i++)
+    {
+        ble_advdata_service_data_t * p_service_data;
+        uint32_t                     data_size;
+
+        p_service_data = &p_advdata->p_service_data_array[i];
+        // For now implemented only for 16-bit UUIDs
+        data_size      = AD_TYPE_SERV_DATA_16BIT_UUID_SIZE + p_service_data->data.size;
+
+        // There is only 1 byte intended to encode length which is (data_size + ADV_AD_TYPE_FIELD_SIZE)
+        if(data_size > (0x00FF - ADV_AD_TYPE_FIELD_SIZE))
+        {
+            return NRF_ERROR_DATA_SIZE;
+        }
+
+        // Encode Length and AD Type.
+        p_encoded_data[*p_offset]  = (uint8_t)(ADV_AD_TYPE_FIELD_SIZE + data_size);
+        *p_offset                 += ADV_LENGTH_FIELD_SIZE;
+        p_encoded_data[*p_offset]  = BLE_GAP_AD_TYPE_SERVICE_DATA;
+        *p_offset                 += ADV_AD_TYPE_FIELD_SIZE;
+
+        // Encode service 16-bit UUID.
+        *p_offset += uint16_encode(p_service_data->service_uuid, &p_encoded_data[*p_offset]);
+
+        // Encode additional service data.
+        if (p_service_data->data.size > 0)
+        {
+            if (p_service_data->data.p_data == NULL)
+            {
+                return NRF_ERROR_INVALID_PARAM;
+            }
+            memcpy(&p_encoded_data[*p_offset], p_service_data->data.p_data, p_service_data->data.size);
+            *p_offset += p_service_data->data.size;
+        }
+    }
+
+    return NRF_SUCCESS;
+}
+
+uint32_t adv_data_encode(ble_advdata_t const * const p_advdata,
+                         uint8_t             * const p_encoded_data,
+                         uint16_t            * const p_len)
+{
+    uint32_t err_code = NRF_SUCCESS;
+    uint16_t max_size = *p_len;
+    *p_len = 0;
+
+    //Encode Security Manager OOB Flags
+    if (p_advdata->p_sec_mgr_oob_flags != NULL)
+    {
+        err_code = sec_mgr_oob_flags_encode(*p_advdata->p_sec_mgr_oob_flags,
+                                             p_encoded_data,
+                                             p_len,
+                                             max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Security Manager TK value
+    if (NULL != p_advdata->p_tk_value)
+    {
+        err_code = tk_value_encode(p_advdata->p_tk_value, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode LE Role
+    if (BLE_ADVDATA_ROLE_NOT_PRESENT != p_advdata->le_role)
+    {
+        err_code = le_role_encode(p_advdata->le_role, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode LE Bluetooth Device Address
+    if (p_advdata->include_ble_device_addr)
+    {
+        err_code = ble_device_addr_encode(p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode appearance.
+    if (p_advdata->include_appearance)
+    {
+        err_code = appearance_encode(p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    //Encode Flags
+    if(p_advdata->flags != 0 )
+    {
+        err_code = flags_encode(p_advdata->flags, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode TX power level.
+    if (p_advdata->p_tx_power_level != NULL)
+    {
+        err_code = tx_power_level_encode(*p_advdata->p_tx_power_level,
+                                         p_encoded_data,
+                                         p_len,
+                                         max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode 'more available' uuid list.
+    if (p_advdata->uuids_more_available.uuid_cnt > 0)
+    {
+        err_code = uuid_list_encode(&p_advdata->uuids_more_available,
+                                    BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_MORE_AVAILABLE,
+                                    BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_MORE_AVAILABLE,
+                                    p_encoded_data,
+                                    p_len,
+                                    max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode 'complete' uuid list.
+    if (p_advdata->uuids_complete.uuid_cnt > 0)
+    {
+        err_code = uuid_list_encode(&p_advdata->uuids_complete,
+                                    BLE_GAP_AD_TYPE_16BIT_SERVICE_UUID_COMPLETE,
+                                    BLE_GAP_AD_TYPE_128BIT_SERVICE_UUID_COMPLETE,
+                                    p_encoded_data,
+                                    p_len,
+                                    max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode 'solicited service' uuid list.
+    if (p_advdata->uuids_solicited.uuid_cnt > 0)
+    {
+        err_code = uuid_list_encode(&p_advdata->uuids_solicited,
+                                    BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_16BIT,
+                                    BLE_GAP_AD_TYPE_SOLICITED_SERVICE_UUIDS_128BIT,
+                                    p_encoded_data,
+                                    p_len,
+                                    max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Slave Connection Interval Range.
+    if (p_advdata->p_slave_conn_int != NULL)
+    {
+        err_code = conn_int_encode(p_advdata->p_slave_conn_int, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Manufacturer Specific Data.
+    if (p_advdata->p_manuf_specific_data != NULL)
+    {
+        err_code = manuf_specific_data_encode(p_advdata->p_manuf_specific_data,
+                                              p_encoded_data,
+                                              p_len,
+                                              max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode Service Data.
+    if (p_advdata->service_data_count > 0)
+    {
+        err_code = service_data_encode(p_advdata, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    // Encode name. WARNING: it is encoded last on purpose since too long device name is truncated.
+    if (p_advdata->name_type != BLE_ADVDATA_NO_NAME)
+    {
+        err_code = name_encode(p_advdata, p_encoded_data, p_len, max_size);
+        VERIFY_SUCCESS(err_code);
+    }
+
+    return err_code;
+}
+
+
+static uint32_t advdata_check(const ble_advdata_t * p_advdata)
+{
+    // Flags must be included in advertising data, and the BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED flag must be set.
+    if (
+        ((p_advdata->flags & BLE_GAP_ADV_FLAG_BR_EDR_NOT_SUPPORTED) == 0)
+       )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+static uint32_t srdata_check(const ble_advdata_t * p_srdata)
+{
+    // Flags shall not be included in the scan response data.
+    if (p_srdata->flags)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata)
+{
+    uint32_t  err_code;
+    uint16_t  len_advdata = BLE_GAP_ADV_MAX_SIZE;
+    uint16_t  len_srdata  = BLE_GAP_ADV_MAX_SIZE;
+    uint8_t   encoded_advdata[BLE_GAP_ADV_MAX_SIZE];
+    uint8_t   encoded_srdata[BLE_GAP_ADV_MAX_SIZE];
+    uint8_t * p_encoded_advdata;
+    uint8_t * p_encoded_srdata;
+
+    // Encode advertising data (if supplied).
+    if (p_advdata != NULL)
+    {
+        err_code = advdata_check(p_advdata);
+        VERIFY_SUCCESS(err_code);
+
+        err_code = adv_data_encode(p_advdata, encoded_advdata, &len_advdata);
+        VERIFY_SUCCESS(err_code);
+        p_encoded_advdata = encoded_advdata;
+    }
+    else
+    {
+        p_encoded_advdata = NULL;
+        len_advdata = 0;
+    }
+
+    // Encode scan response data (if supplied).
+    if (p_srdata != NULL)
+    {
+        err_code = srdata_check(p_srdata);
+        VERIFY_SUCCESS(err_code);
+
+        err_code = adv_data_encode(p_srdata, encoded_srdata, &len_srdata);
+        VERIFY_SUCCESS(err_code);
+        p_encoded_srdata = encoded_srdata;
+    }
+    else
+    {
+        p_encoded_srdata = NULL;
+        len_srdata = 0;
+    }
+
+    // Pass encoded advertising data and/or scan response data to the stack.
+    return sd_ble_gap_adv_data_set(p_encoded_advdata, len_advdata, p_encoded_srdata, len_srdata);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.h
new file mode 100644
index 0000000000..75a0d014c9
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_advdata.h
@@ -0,0 +1,239 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_sdk_lib_advdata Advertising and Scan Response Data Encoder
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Functions for encoding data in the Advertising and Scan Response Data format,
+ *        and for passing the data to the stack.
+ */
+
+#ifndef BLE_ADVDATA_H__
+#define BLE_ADVDATA_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "nrf_ble.h"
+#include "app_util.h"
+
+
+#define ADV_LENGTH_FIELD_SIZE              1UL                                 /**< Advertising Data and Scan Response format contains 1 octet for the length. */
+#define ADV_AD_TYPE_FIELD_SIZE             1UL                                 /**< Advertising Data and Scan Response format contains 1 octet for the AD type. */
+#define ADV_AD_DATA_OFFSET                 (ADV_LENGTH_FIELD_SIZE + \
+                                            ADV_AD_TYPE_FIELD_SIZE)            /**< Offset for the AD data field of the Advertising Data and Scan Response format. */
+#define AD_TYPE_TK_VALUE_DATA_SIZE         (sizeof(ble_advdata_tk_value_t))    /**< Data size (in octets) of the Security Manager TK value AD type. */
+#define AD_TYPE_TK_VALUE_SIZE              (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_TK_VALUE_DATA_SIZE)        /**< Size (in octets) of the Security Manager TK value AD type. */
+#define AD_TYPE_LE_ROLE_DATA_SIZE          1UL                                 /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_LE_ROLE_SIZE               (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_LE_ROLE_DATA_SIZE)         /**< Size (in octets) of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE  1UL                                 /**< Data size (in octets) of the Address type of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE  (BLE_GAP_ADDR_LEN + \
+                                            AD_TYPE_BLE_DEVICE_ADDR_TYPE_SIZE) /**< Data size (in octets) of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_BLE_DEVICE_ADDR_SIZE       (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_BLE_DEVICE_ADDR_DATA_SIZE) /**< Size (in octets) of the LE Bluetooth Device Address AD type. */
+#define AD_TYPE_APPEARANCE_DATA_SIZE       2UL                                 /**< Data size (in octets) of the Appearance AD type. */
+#define AD_TYPE_APPEARANCE_SIZE            (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_APPEARANCE_DATA_SIZE)      /**< Size (in octets) of the Appearance AD type. */
+#define AD_TYPE_FLAGS_DATA_SIZE            1UL                                 /**< Data size (in octets) of the Flags AD type. */
+#define AD_TYPE_FLAGS_SIZE                 (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_FLAGS_DATA_SIZE)           /**< Size (in octets) of the Flags AD type. */
+#define AD_TYPE_TX_POWER_LEVEL_DATA_SIZE   1UL                                 /**< Data size (in octets) of the TX Power Level AD type. */
+#define AD_TYPE_TX_POWER_LEVEL_SIZE        (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_TX_POWER_LEVEL_DATA_SIZE)  /**< Size (in octets) of the TX Power Level AD type. */
+#define AD_TYPE_CONN_INT_DATA_SIZE         4UL                                 /**< Data size (in octets) of the Slave Connection Interval Range AD type. */
+#define AD_TYPE_CONN_INT_SIZE              (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_CONN_INT_DATA_SIZE)        /**< Data size (in octets) of the Slave Connection Interval Range AD type. */
+#define AD_TYPE_MANUF_SPEC_DATA_ID_SIZE    2UL                                 /**< Size (in octets) of the Company Identifier Code, which is a part of the Manufacturer Specific Data AD type. */
+#define AD_TYPE_SERV_DATA_16BIT_UUID_SIZE  2UL                                 /**< Size (in octets) of the 16-bit UUID, which is a part of the Service Data AD type. */
+#define AD_TYPE_OOB_FLAGS_DATA_SIZE        1UL                                 /**< Data size (in octets) of the Security Manager OOB Flags AD type. */
+#define AD_TYPE_OOB_FLAGS_SIZE             (ADV_AD_DATA_OFFSET + \
+                                            AD_TYPE_OOB_FLAGS_DATA_SIZE)       /**< Size (in octets) of the Security Manager OOB Flags AD type. */
+
+#define AD_TYPE_SEC_MGR_OOB_FLAG_SET                   1U                      /**< Security Manager OOB Flag set. Flag selection is done using _POS defines */
+#define AD_TYPE_SEC_MGR_OOB_FLAG_CLEAR                 0U                      /**< Security Manager OOB Flag clear. Flag selection is done using _POS defines */
+#define AD_TYPE_SEC_MGR_OOB_FLAG_OOB_DATA_PRESENT_POS  0UL                     /**< Security Manager OOB Data Present Flag position. */
+#define AD_TYPE_SEC_MGR_OOB_FLAG_OOB_LE_SUPPORTED_POS  1UL                     /**< Security Manager OOB Low Energy Supported Flag position. */
+#define AD_TYPE_SEC_MGR_OOB_FLAG_SIM_LE_AND_EP_POS     2UL                     /**< Security Manager OOB Simultaneous LE and BR/EDR to Same Device Capable Flag position. */
+#define AD_TYPE_SEC_MGR_OOB_ADDRESS_TYPE_PUBLIC        0UL                     /**< Security Manager OOB Public Address type. */
+#define AD_TYPE_SEC_MGR_OOB_ADDRESS_TYPE_RANDOM        1UL                     /**< Security Manager OOB Random Address type. */
+#define AD_TYPE_SEC_MGR_OOB_FLAG_ADDRESS_TYPE_POS      3UL                     /**< Security Manager OOB Address type Flag (0 = Public Address, 1 = Random Address) position. */
+
+
+/**@brief Security Manager TK value. */
+typedef struct
+{
+  uint8_t tk[BLE_GAP_SEC_KEY_LEN];   /**< Array containing TK value. */
+} ble_advdata_tk_value_t;
+
+/**@brief Advertising data LE Role types. This enumeration contains the options available for the LE role inside
+ *        the advertising data. */
+typedef enum
+{
+    BLE_ADVDATA_ROLE_NOT_PRESENT = 0,                                 /**< LE Role AD structure not present. */
+    BLE_ADVDATA_ROLE_ONLY_PERIPH,                                     /**< Only Peripheral Role supported. */
+    BLE_ADVDATA_ROLE_ONLY_CENTRAL,                                    /**< Only Central Role supported. */
+    BLE_ADVDATA_ROLE_BOTH_PERIPH_PREFERRED,                           /**< Peripheral and Central Role supported. Peripheral Role preferred for connection establishment. */
+    BLE_ADVDATA_ROLE_BOTH_CENTRAL_PREFERRED                           /**< Peripheral and Central Role supported. Central Role preferred for connection establishment */
+} ble_advdata_le_role_t;
+
+/**@brief Advertising data name type. This enumeration contains the options available for the device name inside
+ *        the advertising data. */
+typedef enum
+{
+    BLE_ADVDATA_NO_NAME,                                              /**< Include no device name in advertising data. */
+    BLE_ADVDATA_SHORT_NAME,                                           /**< Include short device name in advertising data. */
+    BLE_ADVDATA_FULL_NAME                                             /**< Include full device name in advertising data. */
+} ble_advdata_name_type_t;
+
+/**@brief UUID list type. */
+typedef struct
+{
+    uint16_t                     uuid_cnt;                            /**< Number of UUID entries. */
+    ble_uuid_t *                 p_uuids;                             /**< Pointer to UUID array entries. */
+} ble_advdata_uuid_list_t;
+
+/**@brief Connection interval range structure. */
+typedef struct
+{
+    uint16_t                     min_conn_interval;                   /**< Minimum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). */
+    uint16_t                     max_conn_interval;                   /**< Maximum connection interval, in units of 1.25 ms, range 6 to 3200 (7.5 ms to 4 s). The value 0xFFFF indicates no specific maximum. */
+} ble_advdata_conn_int_t;
+
+/**@brief Manufacturer specific data structure. */
+typedef struct
+{
+    uint16_t                     company_identifier;                  /**< Company identifier code. */
+    uint8_array_t                data;                                /**< Additional manufacturer specific data. */
+} ble_advdata_manuf_data_t;
+
+/**@brief Service data structure. */
+typedef struct
+{
+    uint16_t                     service_uuid;                        /**< Service UUID. */
+    uint8_array_t                data;                                /**< Additional service data. */
+} ble_advdata_service_data_t;
+
+/**@brief Advertising data structure. This structure contains all options and data needed for encoding and
+ *        setting the advertising data. */
+typedef struct
+{
+    ble_advdata_name_type_t      name_type;                           /**< Type of device name. */
+    uint8_t                      short_name_len;                      /**< Length of short device name (if short type is specified). */
+    bool                         include_appearance;                  /**< Determines if Appearance shall be included. */
+    uint8_t                      flags;                               /**< Advertising data Flags field. */
+    int8_t *                     p_tx_power_level;                    /**< TX Power Level field. */
+    ble_advdata_uuid_list_t      uuids_more_available;                /**< List of UUIDs in the 'More Available' list. */
+    ble_advdata_uuid_list_t      uuids_complete;                      /**< List of UUIDs in the 'Complete' list. */
+    ble_advdata_uuid_list_t      uuids_solicited;                     /**< List of solicited UUIDs. */
+    ble_advdata_conn_int_t *     p_slave_conn_int;                    /**< Slave Connection Interval Range. */
+    ble_advdata_manuf_data_t *   p_manuf_specific_data;               /**< Manufacturer specific data. */
+    ble_advdata_service_data_t * p_service_data_array;                /**< Array of Service data structures. */
+    uint8_t                      service_data_count;                  /**< Number of Service data structures. */
+    bool                         include_ble_device_addr;             /**< Determines if LE Bluetooth Device Address shall be included. */
+    ble_advdata_le_role_t        le_role;                             /**< LE Role field. Included when different from @ref BLE_ADVDATA_ROLE_NOT_PRESENT. @warning This field can be used only for NFC. For BLE advertising, set it to NULL. */
+    ble_advdata_tk_value_t *     p_tk_value;                          /**< Security Manager TK value field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
+    uint8_t *                    p_sec_mgr_oob_flags;                 /**< Security Manager Out Of Band Flags field. Included when different from NULL. @warning This field can be used only for NFC. For BLE advertising, set it to NULL.*/
+} ble_advdata_t;
+
+/**@brief Function for encoding data in the Advertising and Scan Response data format
+ *        (AD structures).
+ *
+ * @details This function encodes data into the Advertising and Scan Response data format
+ *          (AD structures) based on the selections in the supplied structures. This function can be used to
+ *          create a payload of Advertising packet or Scan Response packet, or a payload of NFC
+ *          message intended for initiating the Out-of-Band pairing.
+ *
+ * @param[in]      p_advdata       Pointer to the structure for specifying the content of encoded data.
+ * @param[out]     p_encoded_data  Pointer to the buffer where encoded data will be returned.
+ * @param[in,out]  p_len           \c in: Size of \p p_encoded_data buffer.
+ *                                 \c out: Length of encoded data.
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata.
+ * @retval NRF_ERROR_DATA_SIZE     If the operation failed because not all the requested data could fit into the
+ *                                 provided buffer or some encoded AD structure is too long and its
+ *                                 length cannot be encoded with one octet.
+ *
+ * @warning This API may override the application's request to use the long name and use a short name
+ * instead. This truncation will occur in case the long name does not fit the provided buffer size.
+ * The application can specify a preferred short name length if truncation is required.
+ * For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name
+ * length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
+ * if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name.
+ * However, it should be noted that this is just a preference that the application can specify, and
+ * if the preference is too large to fit in the provided buffer, the name can be truncated further.
+ */
+uint32_t adv_data_encode(ble_advdata_t const * const p_advdata,
+                         uint8_t             * const p_encoded_data,
+                         uint16_t            * const p_len);
+
+/**@brief Function for encoding and setting the advertising data and/or scan response data.
+ *
+ * @details This function encodes advertising data and/or scan response data based on the selections
+ *          in the supplied structures, and passes the encoded data to the stack.
+ *
+ * @param[in]   p_advdata   Structure for specifying the content of the advertising data.
+ *                          Set to NULL if advertising data is not to be set.
+ * @param[in]   p_srdata    Structure for specifying the content of the scan response data.
+ *                          Set to NULL if scan response data is not to be set.
+ *
+ * @retval NRF_SUCCESS             If the operation was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If the operation failed because a wrong parameter was provided in \p p_advdata.
+ * @retval NRF_ERROR_DATA_SIZE     If the operation failed because not all the requested data could fit into the
+ *                                 advertising packet. The maximum size of the advertisement packet
+ *                                 is @ref BLE_GAP_ADV_MAX_SIZE.
+ *
+ * @warning This API may override the application's request to use the long name and use a short name
+ * instead. This truncation will occur in case the long name does not fit the provided buffer size.
+ * The application can specify a preferred short name length if truncation is required.
+ * For example, if the complete device name is ABCD_HRMonitor, the application can specify the short name
+ * length to be 8, so that the short device name appears as ABCD_HRM instead of ABCD_HRMo or ABCD_HRMoni
+ * if the available size for the short name is 9 or 12 respectively, to have a more appropriate short name.
+ * However, it should be noted that this is just a preference that the application can specify, and
+ * if the preference is too large to fit in the provided buffer, the name can be truncated further.
+ */
+uint32_t ble_advdata_set(const ble_advdata_t * p_advdata, const ble_advdata_t * p_srdata);
+
+#endif // BLE_ADVDATA_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_params.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_params.h
new file mode 100644
index 0000000000..81bca6eae5
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_params.h
@@ -0,0 +1,138 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_sdk_lib_conn_params Connection Parameters Negotiation
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for initiating and executing a connection parameters negotiation procedure.
+ */
+
+#ifndef BLE_CONN_PARAMS_H__
+#define BLE_CONN_PARAMS_H__
+
+#include <stdint.h>
+#include "nrf_ble.h"
+#include "ble_srv_common.h"
+
+/**@brief Connection Parameters Module event type. */
+typedef enum
+{
+    BLE_CONN_PARAMS_EVT_FAILED   ,                                  /**< Negotiation procedure failed. */
+    BLE_CONN_PARAMS_EVT_SUCCEEDED                                   /**< Negotiation procedure succeeded. */
+} ble_conn_params_evt_type_t;
+
+/**@brief Connection Parameters Module event. */
+typedef struct
+{
+    ble_conn_params_evt_type_t evt_type;                            /**< Type of event. */
+} ble_conn_params_evt_t;
+
+/**@brief Connection Parameters Module event handler type. */
+typedef void (*ble_conn_params_evt_handler_t) (ble_conn_params_evt_t * p_evt);
+
+/**@brief Connection Parameters Module init structure. This contains all options and data needed for
+ *        initialization of the connection parameters negotiation module. */
+typedef struct
+{
+    ble_gap_conn_params_t *       p_conn_params;                    /**< Pointer to the connection parameters desired by the application. When calling ble_conn_params_init, if this parameter is set to NULL, the connection parameters will be fetched from host. */
+    uint32_t                      first_conn_params_update_delay;   /**< Time from initiating event (connect or start of notification) to first time sd_ble_gap_conn_param_update is called (in number of timer ticks). */
+    uint32_t                      next_conn_params_update_delay;    /**< Time between each call to sd_ble_gap_conn_param_update after the first (in number of timer ticks). Recommended value 30 seconds as per BLUETOOTH SPECIFICATION Version 4.0. */
+    uint8_t                       max_conn_params_update_count;     /**< Number of attempts before giving up the negotiation. */
+    uint16_t                      start_on_notify_cccd_handle;      /**< If procedure is to be started when notification is started, set this to the handle of the corresponding CCCD. Set to BLE_GATT_HANDLE_INVALID if procedure is to be started on connect event. */
+    bool                          disconnect_on_fail;               /**< Set to TRUE if a failed connection parameters update shall cause an automatic disconnection, set to FALSE otherwise. */
+    ble_conn_params_evt_handler_t evt_handler;                      /**< Event handler to be called for handling events in the Connection Parameters. */
+    ble_srv_error_handler_t       error_handler;                    /**< Function to be called in case of an error. */
+} ble_conn_params_init_t;
+
+
+/**@brief Function for initializing the Connection Parameters module.
+ *
+ * @note If the negotiation procedure should be triggered when notification/indication of
+ *       any characteristic is enabled by the peer, then this function must be called after
+ *       having initialized the services.
+ *
+ * @param[in]   p_init  This contains information needed to initialize this module.
+ *
+ * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_conn_params_init(const ble_conn_params_init_t * p_init);
+
+/**@brief Function for stopping the Connection Parameters module.
+ *
+ * @details This function is intended to be used by the application to clean up the connection
+ *          parameters update module. This will stop the connection parameters update timer if
+ *          running, thereby preventing any impending connection parameters update procedure. This
+ *          function must be called by the application when it needs to clean itself up (for
+ *          example, before disabling the bluetooth SoftDevice) so that an unwanted timer expiry
+ *          event can be avoided.
+ *
+ * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_conn_params_stop(void);
+
+/**@brief Function for changing the current connection parameters to a new set.
+ *
+ *  @details Use this function to change the connection parameters to a new set of parameter
+ *       (ie different from the ones given at init of the module).
+ *       This function is usefull for scenario where most of the time the application
+ *       needs a relatively big connection interval, and just sometimes, for a temporary
+ *       period requires shorter connection interval, for example to transfer a higher
+ *       amount of data.
+ *       If the given parameters does not match the current connection's parameters
+ *       this function initiates a new negotiation.
+ *
+ * @param[in]   new_params  This contains the new connections parameters to setup.
+ *
+ * @return      NRF_SUCCESS on successful initialization, otherwise an error code.
+ */
+uint32_t ble_conn_params_change_conn_params(ble_gap_conn_params_t *new_params);
+
+/**@brief Function for handling the Application's BLE Stack events.
+ *
+ * @details Handles all events from the BLE stack that are of interest to this module.
+ *
+ * @param[in]   p_ble_evt  The event received from the BLE stack.
+ */
+void ble_conn_params_on_ble_evt(ble_evt_t * p_ble_evt);
+
+#endif // BLE_CONN_PARAMS_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.c
new file mode 100644
index 0000000000..060ce77e34
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.c
@@ -0,0 +1,414 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_conn_state.h"
+#include <stdbool.h>
+#include <stdint.h>
+#include <string.h>
+#include "nrf_ble.h"
+#include "sdk_mapped_flags.h"
+#include "app_error.h"
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+#define BLE_CONN_STATE_N_DEFAULT_FLAGS 5                                                       /**< The number of flags kept for each connection, excluding user flags. */
+#define BLE_CONN_STATE_N_FLAGS (BLE_CONN_STATE_N_DEFAULT_FLAGS + BLE_CONN_STATE_N_USER_FLAGS)  /**< The number of flags kept for each connection, including user flags. */
+
+
+/**@brief Structure containing all the flag collections maintained by the Connection State module.
+ */
+typedef struct
+{
+    sdk_mapped_flags_t valid_flags;                                 /**< Flags indicating which connection handles are valid. */
+    sdk_mapped_flags_t connected_flags;                             /**< Flags indicating which connections are connected, since disconnected connection handles will not immediately be invalidated. */
+    sdk_mapped_flags_t central_flags;                               /**< Flags indicating in which connections the local device is the central. */
+    sdk_mapped_flags_t encrypted_flags;                             /**< Flags indicating which connections are encrypted. */
+    sdk_mapped_flags_t mitm_protected_flags;                        /**< Flags indicating which connections have encryption with protection from man-in-the-middle attacks. */
+    sdk_mapped_flags_t user_flags[BLE_CONN_STATE_N_USER_FLAGS];     /**< Flags that can be reserved by the user. The flags will be cleared when a connection is invalidated, otherwise, the user is wholly responsible for the flag states. */
+} ble_conn_state_flag_collections_t;
+
+
+/**@brief Structure containing the internal state of the Connection State module.
+ */
+typedef struct
+{
+    uint32_t           acquired_flags;                              /**< Bitmap for keeping track of which user flags have been acquired. */
+    uint16_t           valid_conn_handles[SDK_MAPPED_FLAGS_N_KEYS]; /**< List of connection handles used as keys for the sdk_mapped_flags module. */
+    union
+    {
+        ble_conn_state_flag_collections_t flags;                              /**< Flag collections kept by the Connection State module. */
+        sdk_mapped_flags_t                flag_array[BLE_CONN_STATE_N_FLAGS]; /**< Flag collections as array to allow use of @ref sdk_mapped_flags_bulk_update_by_key() when setting all flags. */
+    };
+} ble_conn_state_t;
+
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+static ble_conn_state_t m_bcs = {0}; /**< Instantiation of the internal state. */
+
+
+/**@brief Function for resetting all internal memory to the values it had at initialization.
+ */
+void bcs_internal_state_reset(void)
+{
+    memset( &m_bcs, 0, sizeof(ble_conn_state_t) );
+}
+
+
+/**@brief Function for activating a connection record.
+ *
+ * @param p_record     The record to activate.
+ * @param conn_handle  The connection handle to copy into the record.
+ * @param role         The role of the connection.
+ *
+ * @return whether the record was activated successfully.
+ */
+static bool record_activate(uint16_t conn_handle)
+{
+    uint16_t available_index = sdk_mapped_flags_first_key_index_get(~m_bcs.flags.valid_flags);
+
+    if (available_index != SDK_MAPPED_FLAGS_INVALID_INDEX)
+    {
+        m_bcs.valid_conn_handles[available_index] = conn_handle;
+        sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                      &m_bcs.flags.connected_flags,
+                                       conn_handle,
+                                       1);
+        sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                      &m_bcs.flags.valid_flags,
+                                       conn_handle,
+                                       1);
+
+        return true;
+    }
+
+    return false;
+}
+
+
+/**@brief Function for marking a connection record as invalid and resetting the values.
+ *
+ * @param p_record  The record to invalidate.
+ */
+static void record_invalidate(uint16_t conn_handle)
+{
+    sdk_mapped_flags_bulk_update_by_key(m_bcs.valid_conn_handles,
+                                        m_bcs.flag_array,
+                                        BLE_CONN_STATE_N_FLAGS,
+                                        conn_handle,
+                                        0);
+}
+
+
+/**@brief Function for marking a connection as disconnected. See @ref BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @param p_record   The record of the connection to set as disconnected.
+ */
+static void record_set_disconnected(uint16_t conn_handle)
+{
+    sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                  &m_bcs.flags.connected_flags,
+                                   conn_handle,
+                                   0);
+}
+
+
+/**@brief Function for invalidating records with a @ref BLE_CONN_STATUS_DISCONNECTED
+ *        connection status
+ */
+static void record_purge_disconnected()
+{
+    sdk_mapped_flags_key_list_t disconnected_list;
+
+    disconnected_list = sdk_mapped_flags_key_list_get(
+                                   m_bcs.valid_conn_handles,
+                                 (~m_bcs.flags.connected_flags) & (m_bcs.flags.valid_flags));
+
+    for (uint32_t i = 0; i < disconnected_list.len; i++)
+    {
+        record_invalidate(disconnected_list.flag_keys[i]);
+    }
+}
+
+
+/**@brief Function for checking if a user flag has been acquired.
+ *
+ * @param[in]  flag_id  Which flag to check.
+ *
+ * @return  Whether the flag has been acquired.
+ */
+static bool user_flag_is_acquired(ble_conn_state_user_flag_id_t flag_id)
+{
+    return ((m_bcs.acquired_flags & (1 << flag_id)) != 0);
+}
+
+
+/**@brief Function for marking a user flag as acquired.
+ *
+ * @param[in]  flag_id  Which flag to mark.
+ */
+static void user_flag_acquire(ble_conn_state_user_flag_id_t flag_id)
+{
+    m_bcs.acquired_flags |= (1 << flag_id);
+}
+
+
+void ble_conn_state_init(void)
+{
+    bcs_internal_state_reset();
+}
+
+
+void ble_conn_state_on_ble_evt(ble_evt_t * p_ble_evt)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            record_purge_disconnected();
+
+            if ( !record_activate(p_ble_evt->evt.gap_evt.conn_handle) )
+            {
+                // No more records available. Should not happen.
+                APP_ERROR_HANDLER(NRF_ERROR_NO_MEM);
+            }
+            else
+            {
+                bool is_central =
+                        (p_ble_evt->evt.gap_evt.params.connected.role == BLE_GAP_ROLE_CENTRAL);
+
+                sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                              &m_bcs.flags.central_flags,
+                                               p_ble_evt->evt.gap_evt.conn_handle,
+                                               is_central);
+            }
+
+            break;
+
+        case BLE_GAP_EVT_DISCONNECTED:
+            record_set_disconnected(p_ble_evt->evt.gap_evt.conn_handle);
+            break;
+
+        case BLE_GAP_EVT_CONN_SEC_UPDATE:
+            sdk_mapped_flags_update_by_key(
+                          m_bcs.valid_conn_handles,
+                         &m_bcs.flags.encrypted_flags,
+                          p_ble_evt->evt.gap_evt.conn_handle,
+                         (p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv > 1));
+            sdk_mapped_flags_update_by_key(
+                          m_bcs.valid_conn_handles,
+                         &m_bcs.flags.mitm_protected_flags,
+                          p_ble_evt->evt.gap_evt.conn_handle,
+                         (p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv > 2));
+            break;
+    }
+}
+
+
+bool ble_conn_state_valid(uint16_t conn_handle)
+{
+    return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                       m_bcs.flags.valid_flags,
+                                       conn_handle);
+}
+
+
+uint8_t ble_conn_state_role(uint16_t conn_handle)
+{
+    uint8_t role = BLE_GAP_ROLE_INVALID;
+
+    if ( sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles, m_bcs.flags.valid_flags, conn_handle) )
+    {
+        bool central = sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                                   m_bcs.flags.central_flags,
+                                                   conn_handle);
+
+        role = central ? BLE_GAP_ROLE_CENTRAL : BLE_GAP_ROLE_PERIPH;
+    }
+
+    return role;
+}
+
+
+ble_conn_state_status_t ble_conn_state_status(uint16_t conn_handle)
+{
+    ble_conn_state_status_t conn_status = BLE_CONN_STATUS_INVALID;
+    bool valid = sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                             m_bcs.flags.valid_flags,
+                                             conn_handle);
+
+    if (valid)
+    {
+        bool connected = sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                                     m_bcs.flags.connected_flags,
+                                                     conn_handle);
+
+        conn_status = connected ? BLE_CONN_STATUS_CONNECTED : BLE_CONN_STATUS_DISCONNECTED;
+    }
+
+    return conn_status;
+}
+
+
+bool ble_conn_state_encrypted(uint16_t conn_handle)
+{
+    return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                       m_bcs.flags.encrypted_flags,
+                                       conn_handle);
+}
+
+
+bool ble_conn_state_mitm_protected(uint16_t conn_handle)
+{
+    return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                       m_bcs.flags.mitm_protected_flags,
+                                       conn_handle);
+}
+
+
+uint32_t ble_conn_state_n_connections(void)
+{
+    return sdk_mapped_flags_n_flags_set(m_bcs.flags.connected_flags);
+}
+
+
+uint32_t ble_conn_state_n_centrals(void)
+{
+    return sdk_mapped_flags_n_flags_set((m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+uint32_t ble_conn_state_n_peripherals(void)
+{
+    return sdk_mapped_flags_n_flags_set((~m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+sdk_mapped_flags_key_list_t ble_conn_state_conn_handles(void)
+{
+    return sdk_mapped_flags_key_list_get(m_bcs.valid_conn_handles, m_bcs.flags.valid_flags);
+}
+
+
+sdk_mapped_flags_key_list_t ble_conn_state_central_handles(void)
+{
+    return sdk_mapped_flags_key_list_get(m_bcs.valid_conn_handles,
+                                        (m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+sdk_mapped_flags_key_list_t ble_conn_state_periph_handles(void)
+{
+    return sdk_mapped_flags_key_list_get(m_bcs.valid_conn_handles,
+                                        (~m_bcs.flags.central_flags) & (m_bcs.flags.connected_flags));
+}
+
+
+ble_conn_state_user_flag_id_t ble_conn_state_user_flag_acquire(void)
+{
+    for (ble_conn_state_user_flag_id_t i = BLE_CONN_STATE_USER_FLAG0;
+                                       i < BLE_CONN_STATE_N_USER_FLAGS;
+                                       i++)
+    {
+        if ( !user_flag_is_acquired(i) )
+        {
+            user_flag_acquire(i);
+            return i;
+        }
+    }
+
+    return BLE_CONN_STATE_USER_FLAG_INVALID;
+}
+
+
+bool ble_conn_state_user_flag_get(uint16_t conn_handle, ble_conn_state_user_flag_id_t flag_id)
+{
+    if (user_flag_is_acquired(flag_id))
+    {
+        return sdk_mapped_flags_get_by_key(m_bcs.valid_conn_handles,
+                                           m_bcs.flags.user_flags[flag_id],
+                                           conn_handle);
+    }
+    else
+    {
+        return false;
+    }
+}
+
+
+void ble_conn_state_user_flag_set(uint16_t                      conn_handle,
+                                  ble_conn_state_user_flag_id_t flag_id,
+                                  bool                          value)
+{
+    if (user_flag_is_acquired(flag_id))
+    {
+        sdk_mapped_flags_update_by_key(m_bcs.valid_conn_handles,
+                                      &m_bcs.flags.user_flags[flag_id],
+                                       conn_handle,
+                                       value);
+    }
+}
+
+
+sdk_mapped_flags_t ble_conn_state_user_flag_collection(ble_conn_state_user_flag_id_t flag_id)
+{
+    if ( user_flag_is_acquired(flag_id) )
+    {
+        return m_bcs.flags.user_flags[flag_id];
+    }
+    else
+    {
+        return 0;
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.h
new file mode 100644
index 0000000000..d5b48aa9cf
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_conn_state.h
@@ -0,0 +1,302 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file
+ *
+ * @defgroup ble_conn_state Connection state
+ * @ingroup ble_sdk_lib
+ * @{
+ * @brief Module for storing data on BLE connections.
+ *
+ * @details This module stores certain states for each connection, which can be queried by
+ *          connection handle. The module uses BLE events to keep the states updated.
+ *
+ *          In addition to the preprogrammed states, this module can also keep track of a number of
+ *          binary user states, or <i>user flags</i>. These are reset to 0 for new connections, but
+ *          otherwise not touched by this module.
+ *
+ *          This module uses the @ref sdk_mapped_flags module, with connection handles as keys and
+ *          the connection states as flags.
+ *
+ * @note A connection handle is not immediately invalidated when it is disconnected. Certain states,
+ *       such as the role, can still be queried until the next time a new connection is established
+ *       to any device.
+ *
+ *          To function properly, this module must be provided with BLE events from the SoftDevice
+ *          through the @ref ble_conn_state_on_ble_evt() function. This module should be the first
+ *          to receive BLE events if they are dispatched to multiple modules.
+ */
+
+#ifndef BLE_CONN_STATE_H__
+#define BLE_CONN_STATE_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "nrf_ble.h"
+#include "sdk_mapped_flags.h"
+
+/**@brief Connection handle statuses.
+ */
+typedef enum
+{
+    BLE_CONN_STATUS_INVALID,       /**< The connection handle is invalid. */
+    BLE_CONN_STATUS_DISCONNECTED,  /**< The connection handle refers to a connection that has been disconnected, but not yet invalidated. */
+    BLE_CONN_STATUS_CONNECTED,     /**< The connection handle refers to an active connection. */
+} ble_conn_state_status_t;
+
+#define BLE_CONN_STATE_N_USER_FLAGS 24  /**< The number of available user flags. */
+
+
+/**@brief One ID for each user flag collection.
+ *
+ * @details These IDs are used to identify user flag collections in the API calls.
+ */
+typedef enum
+{
+    BLE_CONN_STATE_USER_FLAG0 = 0,
+    BLE_CONN_STATE_USER_FLAG1,
+    BLE_CONN_STATE_USER_FLAG2,
+    BLE_CONN_STATE_USER_FLAG3,
+    BLE_CONN_STATE_USER_FLAG4,
+    BLE_CONN_STATE_USER_FLAG5,
+    BLE_CONN_STATE_USER_FLAG6,
+    BLE_CONN_STATE_USER_FLAG7,
+    BLE_CONN_STATE_USER_FLAG8,
+    BLE_CONN_STATE_USER_FLAG9,
+    BLE_CONN_STATE_USER_FLAG10,
+    BLE_CONN_STATE_USER_FLAG11,
+    BLE_CONN_STATE_USER_FLAG12,
+    BLE_CONN_STATE_USER_FLAG13,
+    BLE_CONN_STATE_USER_FLAG14,
+    BLE_CONN_STATE_USER_FLAG15,
+    BLE_CONN_STATE_USER_FLAG16,
+    BLE_CONN_STATE_USER_FLAG17,
+    BLE_CONN_STATE_USER_FLAG18,
+    BLE_CONN_STATE_USER_FLAG19,
+    BLE_CONN_STATE_USER_FLAG20,
+    BLE_CONN_STATE_USER_FLAG21,
+    BLE_CONN_STATE_USER_FLAG22,
+    BLE_CONN_STATE_USER_FLAG23,
+    BLE_CONN_STATE_USER_FLAG_INVALID,
+} ble_conn_state_user_flag_id_t;
+
+
+/**
+ * @defgroup ble_conn_state_functions BLE connection state functions
+ * @{
+ */
+
+
+/**@brief Function for initializing or resetting the module.
+ *
+ * @details This function sets all states to their default, removing all records of connection handles.
+ */
+void ble_conn_state_init(void);
+
+
+/**@brief Function for providing BLE SoftDevice events to the connection state module.
+ *
+ * @param[in]  p_ble_evt    The SoftDevice event.
+ */
+void ble_conn_state_on_ble_evt(ble_evt_t * p_ble_evt);
+
+
+/**@brief Function for querying whether a connection handle represents a valid connection.
+ *
+ * @details A connection might be valid and have a BLE_CONN_STATUS_DISCONNECTED status.
+ *          Those connections are invalidated after a new connection occurs.
+ *
+ * @param[in]  conn_handle  Handle of the connection.
+ *
+ * @retval true   If conn_handle represents a valid connection, thus a connection for which
+                  we have a record.
+ * @retval false  If conn_handle is @ref BLE_GAP_ROLE_INVALID, or if it has never been recorded.
+ */
+bool ble_conn_state_valid(uint16_t conn_handle);
+
+
+/**@brief Function for querying the role of the local device in a connection.
+ *
+ * @param[in]  conn_handle  Handle of the connection to get the role for.
+ *
+ * @return  The role of the local device in the connection (see @ref BLE_GAP_ROLES).
+ *          If conn_handle is not valid, the function returns BLE_GAP_ROLE_INVALID.
+ */
+uint8_t ble_conn_state_role(uint16_t conn_handle);
+
+
+/**@brief Function for querying the status of a connection.
+ *
+ * @param[in]  conn_handle  Handle of the connection.
+ *
+ * @return  The status of the connection.
+ *          If conn_handle is not valid, the function returns BLE_CONN_STATE_INVALID.
+ */
+ble_conn_state_status_t ble_conn_state_status(uint16_t conn_handle);
+
+
+/**@brief Function for querying whether a connection is encrypted.
+ *
+ * @param[in]  conn_handle  Handle of connection to get the encryption state for.
+ *
+ * @retval true   If the connection is encrypted.
+ * @retval false  If the connection is not encrypted or conn_handle is invalid.
+ */
+bool ble_conn_state_encrypted(uint16_t conn_handle);
+
+
+/**@brief Function for querying whether a connection encryption is protected from Man in the Middle
+ *        attacks.
+ *
+ * @param[in]  conn_handle  Handle of connection to get the MITM state for.
+ *
+ * @retval true   If the connection is encrypted with MITM protection.
+ * @retval false  If the connection is not encrypted, or encryption is not MITM protected, or
+ *                conn_handle is invalid.
+ */
+bool ble_conn_state_mitm_protected(uint16_t conn_handle);
+
+
+/**@brief Function for querying the total number of connections.
+ *
+ * @return  The total number of valid connections for which the module has a record.
+ */
+uint32_t ble_conn_state_n_connections(void);
+
+
+/**@brief Function for querying the total number of connections in which the role of the local
+ *        device is @ref BLE_GAP_ROLE_CENTRAL.
+ *
+ * @return  The number of connections in which the role of the local device is
+ *          @ref BLE_GAP_ROLE_CENTRAL.
+ */
+uint32_t ble_conn_state_n_centrals(void);
+
+
+/**@brief Function for querying the total number of connections in which the role of the local
+ *        device is @ref BLE_GAP_ROLE_PERIPH.
+ *
+ * @return  The number of connections in which the role of the local device is
+ *          @ref BLE_GAP_ROLE_PERIPH.
+ */
+uint32_t ble_conn_state_n_peripherals(void);
+
+
+/**@brief Function for obtaining a list of all connection handles for which the module has a record.
+ *
+ * @details This function takes into account connections whose state is BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @return  A list of all valid connection handles for which the module has a record.
+ */
+sdk_mapped_flags_key_list_t ble_conn_state_conn_handles(void);
+
+
+/**@brief Function for obtaining a list of connection handles in which the role of the local
+ *        device is @ref BLE_GAP_ROLE_CENTRAL.
+ *
+ * @details This function takes into account connections whose state is BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @return  A list of all valid connection handles for which the module has a record and in which
+ *          the role of local device is @ref BLE_GAP_ROLE_CENTRAL.
+ */
+sdk_mapped_flags_key_list_t ble_conn_state_central_handles(void);
+
+
+/**@brief Function for obtaining the handle for the connection in which the role of the local device
+ *        is @ref BLE_GAP_ROLE_PERIPH.
+ *
+ * @details This function takes into account connections whose state is BLE_CONN_STATUS_DISCONNECTED.
+ *
+ * @return  A list of all valid connection handles for which the module has a record and in which
+ *          the role of local device is @ref BLE_GAP_ROLE_PERIPH.
+ */
+sdk_mapped_flags_key_list_t ble_conn_state_periph_handles(void);
+
+
+/**@brief Function for obtaining exclusive access to one of the user flag collections.
+ *
+ * @details The acquired collection contains one flag for each connection. These flags can be set
+ *          and read individually for each connection.
+ *
+ *          The state of user flags will not be modified by the connection state module, except to
+ *          set it to 0 for a connection when that connection is invalidated.
+ *
+ * @return  The ID of the acquired flag, or BLE_CONN_STATE_USER_FLAG_INVALID if none are available.
+ */
+ble_conn_state_user_flag_id_t ble_conn_state_user_flag_acquire(void);
+
+
+/**@brief Function for reading the value of a user flag.
+ *
+ * @param[in]  conn_handle  Handle of connection to get the flag state for.
+ * @param[in]  flag_id      Which flag to get the state for.
+ *
+ * @return  The state of the flag. If conn_handle is invalid, the function returns false.
+ */
+bool ble_conn_state_user_flag_get(uint16_t conn_handle, ble_conn_state_user_flag_id_t flag_id);
+
+
+/**@brief Function for setting the value of a user flag.
+ *
+ * @param[in]  conn_handle  Handle of connection to set the flag state for.
+ * @param[in]  flag_id      Which flag to set the state for.
+ * @param[in]  value        Value to set the flag state to.
+ */
+void ble_conn_state_user_flag_set(uint16_t                      conn_handle,
+                                  ble_conn_state_user_flag_id_t flag_id,
+                                  bool                          value);
+
+
+/**@brief Function for getting the state of a user flag for all connection handles.
+ *
+ * @details The returned collection can be used with the @ref sdk_mapped_flags API. The returned
+ *          collection is a copy, so modifying it has no effect on the conn_state module.
+ *
+ * @param[in]  flag_id  Which flag to get states for.
+ *
+ * @return  The collection of flag states. The collection is always all zeros when the flag_id is
+ *          unregistered.
+ */
+sdk_mapped_flags_t ble_conn_state_user_flag_collection(ble_conn_state_user_flag_id_t flag_id);
+
+/** @} */
+/** @} */
+
+#endif /* BLE_CONN_STATE_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_date_time.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_date_time.h
new file mode 100644
index 0000000000..7112223857
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_date_time.h
@@ -0,0 +1,104 @@
+/* 
+ * Copyright (c) 2011 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/* Attention! 
+*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile 
+*  qualification listings, this section of source code must not be modified.
+*/
+
+/** @file
+ * @brief Contains definition of ble_date_time structure.
+ */
+
+/** @file
+ *
+ * @defgroup ble_sdk_srv_date_time BLE Date Time characteristic type
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Definition of ble_date_time_t type.
+ */
+
+#ifndef BLE_DATE_TIME_H__
+#define BLE_DATE_TIME_H__
+
+#include <stdint.h>
+
+/**@brief Date and Time structure. */
+typedef struct
+{
+    uint16_t year;
+    uint8_t  month;
+    uint8_t  day;
+    uint8_t  hours;
+    uint8_t  minutes;
+    uint8_t  seconds;
+} ble_date_time_t;
+
+static __INLINE uint8_t ble_date_time_encode(const ble_date_time_t * p_date_time,
+                                             uint8_t *               p_encoded_data)
+{
+    uint8_t len = uint16_encode(p_date_time->year, p_encoded_data);
+    
+    p_encoded_data[len++] = p_date_time->month;
+    p_encoded_data[len++] = p_date_time->day;
+    p_encoded_data[len++] = p_date_time->hours;
+    p_encoded_data[len++] = p_date_time->minutes;
+    p_encoded_data[len++] = p_date_time->seconds;
+    
+    return len;
+}
+
+static __INLINE uint8_t ble_date_time_decode(ble_date_time_t * p_date_time,
+                                             const uint8_t *   p_encoded_data)
+{
+    uint8_t len = sizeof(uint16_t);
+    
+    p_date_time->year    = uint16_decode(p_encoded_data);
+    p_date_time->month   = p_encoded_data[len++];
+    p_date_time->day     = p_encoded_data[len++]; 
+    p_date_time->hours   = p_encoded_data[len++];
+    p_date_time->minutes = p_encoded_data[len++];
+    p_date_time->seconds = p_encoded_data[len++];
+    
+    return len;
+}
+
+#endif // BLE_DATE_TIME_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_gatt_db.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_gatt_db.h
new file mode 100644
index 0000000000..9e9b0deed4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_gatt_db.h
@@ -0,0 +1,77 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /**@file
+ *
+ * @defgroup ble_sdk_lib_gatt_db GATT Database Service Structure
+ * @{
+ * @ingroup  app_common
+ */
+
+#ifndef BLE_GATT_DB_H__
+#define BLE_GATT_DB_H__
+
+#include <stdint.h>
+#include "nrf_ble.h"
+#include "nrf_ble_gattc.h"
+
+#define BLE_GATT_DB_MAX_CHARS 5       /**< The maximum number of characteristics present in a service record. */
+
+/**@brief Structure for holding the characteristic and the handle of its CCCD present on a server.
+ */
+typedef struct
+{
+    ble_gattc_char_t characteristic;  /**< Structure containing information about the characteristic. */
+    uint16_t         cccd_handle;     /**< CCCD Handle value for this characteristic. This will be set to BLE_GATT_HANDLE_INVALID if a CCCD is not present at the server. */
+} ble_gatt_db_char_t;
+
+/**@brief Structure for holding information about the service and the characteristics present on a
+ *        server.
+ */
+typedef struct
+{
+    ble_uuid_t               srv_uuid;                                  /**< UUID of the service. */
+    uint8_t                  char_count;                                /**< Number of characteristics present in the service. */
+    ble_gattc_handle_range_t handle_range;                              /**< Service Handle Range. */
+    ble_gatt_db_char_t       charateristics[BLE_GATT_DB_MAX_CHARS];     /**< Array of information related to the characteristics present in the service. This list can extend further than one. */
+} ble_gatt_db_srv_t;
+
+#endif /* BLE_GATT_DB_H__ */
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_sensor_location.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_sensor_location.h
new file mode 100644
index 0000000000..43311a6077
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_sensor_location.h
@@ -0,0 +1,67 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /* Attention!
+*  To maintain compliance with Nordic Semiconductor ASA’s Bluetooth profile
+*  qualification listings, this section of source code must not be modified.
+*/
+ 
+#ifndef BLE_SENSOR_LOCATION_H__
+#define BLE_SENSOR_LOCATION_H__
+
+typedef enum {
+    BLE_SENSOR_LOCATION_OTHER        = 0 ,  /**<-- Other        */
+    BLE_SENSOR_LOCATION_TOP_OF_SHOE  = 1 ,  /**<-- Top of shoe  */
+    BLE_SENSOR_LOCATION_IN_SHOE      = 2 ,  /**<-- In shoe      */
+    BLE_SENSOR_LOCATION_HIP          = 3 ,  /**<-- Hip          */
+    BLE_SENSOR_LOCATION_FRONT_WHEEL  = 4 ,  /**<-- Front Wheel  */
+    BLE_SENSOR_LOCATION_LEFT_CRANK   = 5 ,  /**<-- Left Crank   */
+    BLE_SENSOR_LOCATION_RIGHT_CRANK  = 6 ,  /**<-- Right Crank  */
+    BLE_SENSOR_LOCATION_LEFT_PEDAL   = 7 ,  /**<-- Left Pedal   */
+    BLE_SENSOR_LOCATION_RIGHT_PEDAL  = 8 ,  /**<-- Right Pedal  */
+    BLE_SENSOR_LOCATION_FRONT_HUB    = 9 ,  /**<-- Front Hub    */
+    BLE_SENSOR_LOCATION_REAR_DROPOUT = 10,  /**<-- Rear Dropout */
+    BLE_SENSOR_LOCATION_CHAINSTAY    = 11,  /**<-- Chainstay    */
+    BLE_SENSOR_LOCATION_REAR_WHEEL   = 12,  /**<-- Rear Wheel   */
+    BLE_SENSOR_LOCATION_REAR_HUB     = 13,  /**<-- Rear Hub     */
+}ble_sensor_location_t;
+
+#define BLE_NB_MAX_SENSOR_LOCATIONS 14
+
+#endif // BLE_SENSOR_LOCATION_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.c
new file mode 100644
index 0000000000..42cd2d4f2a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.c
@@ -0,0 +1,224 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/* Attention!
+*  To maintain compliance with Nordic Semiconductor ASA�s Bluetooth profile
+*  qualification listings, this section of source code must not be modified.
+*/
+
+#include "ble_srv_common.h"
+#include <string.h>
+#include "nordic_common.h"
+#include "app_error.h"
+#include "nrf_ble.h"
+
+uint8_t ble_srv_report_ref_encode(uint8_t                    * p_encoded_buffer,
+                                  const ble_srv_report_ref_t * p_report_ref)
+{
+    uint8_t len = 0;
+
+    p_encoded_buffer[len++] = p_report_ref->report_id;
+    p_encoded_buffer[len++] = p_report_ref->report_type;
+
+    APP_ERROR_CHECK_BOOL(len == BLE_SRV_ENCODED_REPORT_REF_LEN);
+    return len;
+}
+
+
+void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii)
+{
+    p_utf8->length = (uint16_t)strlen(p_ascii);
+    p_utf8->p_str  = (uint8_t *)p_ascii;
+}
+
+
+/**@brief Function for setting security requirements of a characteristic.
+ *
+ * @param[in]  level   required security level.
+ * @param[out] p_perm  Characteristic security requirements.
+ *
+ * @return     encoded security level and security mode.
+ */
+static inline void set_security_req(security_req_t level, ble_gap_conn_sec_mode_t * p_perm)
+{
+
+
+    BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm);
+    switch (level)
+    {
+        case SEC_NO_ACCESS:
+            BLE_GAP_CONN_SEC_MODE_SET_NO_ACCESS(p_perm);
+        break;
+        case SEC_OPEN:
+            BLE_GAP_CONN_SEC_MODE_SET_OPEN(p_perm);
+        break;
+        case SEC_JUST_WORKS:
+            BLE_GAP_CONN_SEC_MODE_SET_ENC_NO_MITM(p_perm);
+        break;
+        case SEC_MITM:
+            BLE_GAP_CONN_SEC_MODE_SET_ENC_WITH_MITM(p_perm);
+        break;
+        case SEC_SIGNED:
+            BLE_GAP_CONN_SEC_MODE_SET_SIGNED_NO_MITM(p_perm);
+        break;
+        case SEC_SIGNED_MITM:
+            BLE_GAP_CONN_SEC_MODE_SET_SIGNED_WITH_MITM(p_perm);
+        break;
+    }
+    return;
+}
+
+
+uint32_t characteristic_add(uint16_t                   service_handle,
+                            ble_add_char_params_t *    p_char_props,
+                            ble_gatts_char_handles_t * p_char_handle)
+{
+    ble_gatts_char_md_t char_md;
+    ble_gatts_attr_t    attr_char_value;
+    ble_uuid_t          char_uuid;
+    ble_gatts_attr_md_t attr_md;
+    ble_gatts_attr_md_t user_descr_attr_md;
+    ble_gatts_attr_md_t cccd_md;
+
+    if (p_char_props->uuid_type == 0)
+    {
+        char_uuid.type = BLE_UUID_TYPE_BLE;
+    }
+    else
+    {
+        char_uuid.type = p_char_props->uuid_type;
+    }
+    char_uuid.uuid = p_char_props->uuid;
+
+    memset(&attr_md, 0, sizeof(ble_gatts_attr_md_t));
+    set_security_req(p_char_props->read_access, &attr_md.read_perm);
+    set_security_req(p_char_props->write_access, & attr_md.write_perm);
+    attr_md.rd_auth    = (p_char_props->is_defered_read ? 1 : 0);
+    attr_md.wr_auth    = (p_char_props->is_defered_write ? 1 : 0);
+    attr_md.vlen       = (p_char_props->is_var_len ? 1 : 0);
+    attr_md.vloc       = (p_char_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
+
+
+    memset(&char_md, 0, sizeof(ble_gatts_char_md_t));
+    if ((p_char_props->char_props.notify == 1)||(p_char_props->char_props.indicate == 1))
+    {
+
+        memset(&cccd_md, 0, sizeof(cccd_md));
+        set_security_req(p_char_props->cccd_write_access, &cccd_md.write_perm);
+        BLE_GAP_CONN_SEC_MODE_SET_OPEN(&cccd_md.read_perm);
+
+        cccd_md.vloc       = BLE_GATTS_VLOC_STACK;
+
+        char_md.p_cccd_md  = &cccd_md;
+    }
+    char_md.char_props = p_char_props->char_props;
+
+    memset(&attr_char_value, 0, sizeof(ble_gatts_attr_t));
+    attr_char_value.p_uuid    = &char_uuid;
+    attr_char_value.p_attr_md = &attr_md;
+    attr_char_value.max_len   = p_char_props->max_len;
+    if (p_char_props->p_init_value != NULL)
+    {
+        attr_char_value.init_len  = p_char_props->init_len;
+        attr_char_value.p_value   = p_char_props->p_init_value;
+    }
+    if (p_char_props->p_user_descr != NULL)
+    {
+        memset(&user_descr_attr_md, 0, sizeof(ble_gatts_attr_md_t));
+        char_md.char_user_desc_max_size = p_char_props->p_user_descr->max_size;
+        char_md.char_user_desc_size     = p_char_props->p_user_descr->size;
+        char_md.p_char_user_desc        = p_char_props->p_user_descr->p_char_user_desc;
+
+        char_md.p_user_desc_md          = &user_descr_attr_md;
+
+        set_security_req(p_char_props->p_user_descr->read_access, &user_descr_attr_md.read_perm);
+        set_security_req(p_char_props->p_user_descr->write_access, &user_descr_attr_md.write_perm);
+
+        user_descr_attr_md.rd_auth      = (p_char_props->p_user_descr->is_defered_read ? 1 : 0);
+        user_descr_attr_md.wr_auth      = (p_char_props->p_user_descr->is_defered_write ? 1 : 0);
+        user_descr_attr_md.vlen         = (p_char_props->p_user_descr->is_var_len ? 1 : 0);
+        user_descr_attr_md.vloc         = (p_char_props->p_user_descr->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
+    }
+    if (p_char_props->p_presentation_format != NULL)
+    {
+        char_md.p_char_pf = p_char_props->p_presentation_format;
+    }
+    return sd_ble_gatts_characteristic_add(service_handle,
+                                           &char_md,
+                                           &attr_char_value,
+                                           p_char_handle);
+}
+
+
+uint32_t descriptor_add(uint16_t                   char_handle,
+                        ble_add_descr_params_t *   p_descr_props,
+                        uint16_t *                 p_descr_handle)
+{
+    ble_gatts_attr_t    descr_params;
+    ble_uuid_t          desc_uuid;
+    ble_gatts_attr_md_t attr_md;
+
+    memset(&descr_params, 0, sizeof(descr_params));
+    if (p_descr_props->uuid_type == 0)
+    {
+        desc_uuid.type = BLE_UUID_TYPE_BLE;
+    }
+    else
+    {
+        desc_uuid.type = p_descr_props->uuid_type;
+    }
+    desc_uuid.uuid = p_descr_props->uuid;
+    descr_params.p_uuid = &desc_uuid;
+
+    set_security_req(p_descr_props->read_access, &attr_md.read_perm);
+    set_security_req(p_descr_props->write_access,&attr_md.write_perm);
+
+    attr_md.rd_auth        = (p_descr_props->is_defered_read ? 1 : 0);
+    attr_md.wr_auth        = (p_descr_props->is_defered_write ? 1 : 0);
+    attr_md.vlen           = (p_descr_props->is_var_len ? 1 : 0);
+    attr_md.vloc           = (p_descr_props->is_value_user ? BLE_GATTS_VLOC_USER : BLE_GATTS_VLOC_STACK);
+    descr_params.p_attr_md = &attr_md;
+
+    descr_params.init_len  = p_descr_props->init_len;
+    descr_params.init_offs = p_descr_props->init_offs;
+    descr_params.max_len   = p_descr_props->max_len;
+    descr_params.p_value   = p_descr_props->p_value;
+
+    return sd_ble_gatts_descriptor_add(char_handle, &descr_params, p_descr_handle);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.h
new file mode 100644
index 0000000000..79a7ad0bfc
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/common/ble_srv_common.h
@@ -0,0 +1,394 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_sdk_srv_common Common service definitions
+ * @{
+ * @ingroup ble_sdk_srv
+ * @brief Constants, type definitions, and functions that are common to all services.
+ */
+
+#ifndef BLE_SRV_COMMON_H__
+#define BLE_SRV_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf_ble_types.h"
+#include "app_util.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble_gatt.h"
+
+/** @defgroup UUID_SERVICES Service UUID definitions
+ * @{ */
+#define BLE_UUID_ALERT_NOTIFICATION_SERVICE                      0x1811     /**< Alert Notification service UUID. */
+#define BLE_UUID_BATTERY_SERVICE                                 0x180F     /**< Battery service UUID. */
+#define BLE_UUID_BLOOD_PRESSURE_SERVICE                          0x1810     /**< Blood Pressure service UUID. */
+#define BLE_UUID_CURRENT_TIME_SERVICE                            0x1805     /**< Current Time service UUID. */
+#define BLE_UUID_CYCLING_SPEED_AND_CADENCE                       0x1816     /**< Cycling Speed and Cadence service UUID. */
+#define BLE_UUID_LOCATION_AND_NAVIGATION_SERVICE                 0x1819     /**< Location and Navigation service UUID. */
+#define BLE_UUID_DEVICE_INFORMATION_SERVICE                      0x180A     /**< Device Information service UUID. */
+#define BLE_UUID_GLUCOSE_SERVICE                                 0x1808     /**< Glucose service UUID. */
+#define BLE_UUID_HEALTH_THERMOMETER_SERVICE                      0x1809     /**< Health Thermometer service UUID. */
+#define BLE_UUID_HEART_RATE_SERVICE                              0x180D     /**< Heart Rate service UUID. */
+#define BLE_UUID_HUMAN_INTERFACE_DEVICE_SERVICE                  0x1812     /**< Human Interface Device service UUID. */
+#define BLE_UUID_IMMEDIATE_ALERT_SERVICE                         0x1802     /**< Immediate Alert service UUID. */
+#define BLE_UUID_LINK_LOSS_SERVICE                               0x1803     /**< Link Loss service UUID. */
+#define BLE_UUID_NEXT_DST_CHANGE_SERVICE                         0x1807     /**< Next Dst Change service UUID. */
+#define BLE_UUID_PHONE_ALERT_STATUS_SERVICE                      0x180E     /**< Phone Alert Status service UUID. */
+#define BLE_UUID_REFERENCE_TIME_UPDATE_SERVICE                   0x1806     /**< Reference Time Update service UUID. */
+#define BLE_UUID_RUNNING_SPEED_AND_CADENCE                       0x1814     /**< Running Speed and Cadence service UUID. */
+#define BLE_UUID_SCAN_PARAMETERS_SERVICE                         0x1813     /**< Scan Parameters service UUID. */
+#define BLE_UUID_TX_POWER_SERVICE                                0x1804     /**< TX Power service UUID. */
+#define BLE_UUID_IPSP_SERVICE                                    0x1820     /**< Internet Protocol Support service UUID. */
+#define BLE_UUID_BMS_SERVICE                                     0x181E     /**< BOND MANAGEMENT service UUID*/
+#define BLE_UUID_CGM_SERVICE                                     0x181F     /**< Contiunous Glucose Monitoring service UUID*/
+#define BLE_UUID_PLX_SERVICE                                     0x1822     /**< Pulse Oximeter Service UUID*/
+
+
+/** @} */
+
+/** @defgroup UUID_CHARACTERISTICS Characteristic UUID definitions
+ * @{ */
+#define BLE_UUID_REMOVABLE_CHAR                                  0x2A3A     /**< Removable characteristic UUID. */
+#define BLE_UUID_SERVICE_REQUIRED_CHAR                           0x2A3B     /**< Service Required characteristic UUID. */
+#define BLE_UUID_ALERT_CATEGORY_ID_CHAR                          0x2A43     /**< Alert Category Id characteristic UUID. */
+#define BLE_UUID_ALERT_CATEGORY_ID_BIT_MASK_CHAR                 0x2A42     /**< Alert Category Id Bit Mask characteristic UUID. */
+#define BLE_UUID_ALERT_LEVEL_CHAR                                0x2A06     /**< Alert Level characteristic UUID. */
+#define BLE_UUID_ALERT_NOTIFICATION_CONTROL_POINT_CHAR           0x2A44     /**< Alert Notification Control Point characteristic UUID. */
+#define BLE_UUID_ALERT_STATUS_CHAR                               0x2A3F     /**< Alert Status characteristic UUID. */
+#define BLE_UUID_BATTERY_LEVEL_CHAR                              0x2A19     /**< Battery Level characteristic UUID. */
+#define BLE_UUID_BLOOD_PRESSURE_FEATURE_CHAR                     0x2A49     /**< Blood Pressure Feature characteristic UUID. */
+#define BLE_UUID_BLOOD_PRESSURE_MEASUREMENT_CHAR                 0x2A35     /**< Blood Pressure Measurement characteristic UUID. */
+#define BLE_UUID_BODY_SENSOR_LOCATION_CHAR                       0x2A38     /**< Body Sensor Location characteristic UUID. */
+#define BLE_UUID_BOOT_KEYBOARD_INPUT_REPORT_CHAR                 0x2A22     /**< Boot Keyboard Input Report characteristic UUID. */
+#define BLE_UUID_BOOT_KEYBOARD_OUTPUT_REPORT_CHAR                0x2A32     /**< Boot Keyboard Output Report characteristic UUID. */
+#define BLE_UUID_BOOT_MOUSE_INPUT_REPORT_CHAR                    0x2A33     /**< Boot Mouse Input Report characteristic UUID. */
+#define BLE_UUID_CURRENT_TIME_CHAR                               0x2A2B     /**< Current Time characteristic UUID. */
+#define BLE_UUID_DATE_TIME_CHAR                                  0x2A08     /**< Date Time characteristic UUID. */
+#define BLE_UUID_DAY_DATE_TIME_CHAR                              0x2A0A     /**< Day Date Time characteristic UUID. */
+#define BLE_UUID_DAY_OF_WEEK_CHAR                                0x2A09     /**< Day Of Week characteristic UUID. */
+#define BLE_UUID_DST_OFFSET_CHAR                                 0x2A0D     /**< Dst Offset characteristic UUID. */
+#define BLE_UUID_EXACT_TIME_256_CHAR                             0x2A0C     /**< Exact Time 256 characteristic UUID. */
+#define BLE_UUID_FIRMWARE_REVISION_STRING_CHAR                   0x2A26     /**< Firmware Revision String characteristic UUID. */
+#define BLE_UUID_GLUCOSE_FEATURE_CHAR                            0x2A51     /**< Glucose Feature characteristic UUID. */
+#define BLE_UUID_GLUCOSE_MEASUREMENT_CHAR                        0x2A18     /**< Glucose Measurement characteristic UUID. */
+#define BLE_UUID_GLUCOSE_MEASUREMENT_CONTEXT_CHAR                0x2A34     /**< Glucose Measurement Context characteristic UUID. */
+#define BLE_UUID_HARDWARE_REVISION_STRING_CHAR                   0x2A27     /**< Hardware Revision String characteristic UUID. */
+#define BLE_UUID_HEART_RATE_CONTROL_POINT_CHAR                   0x2A39     /**< Heart Rate Control Point characteristic UUID. */
+#define BLE_UUID_HEART_RATE_MEASUREMENT_CHAR                     0x2A37     /**< Heart Rate Measurement characteristic UUID. */
+#define BLE_UUID_HID_CONTROL_POINT_CHAR                          0x2A4C     /**< Hid Control Point characteristic UUID. */
+#define BLE_UUID_HID_INFORMATION_CHAR                            0x2A4A     /**< Hid Information characteristic UUID. */
+#define BLE_UUID_IEEE_REGULATORY_CERTIFICATION_DATA_LIST_CHAR    0x2A2A     /**< IEEE Regulatory Certification Data List characteristic UUID. */
+#define BLE_UUID_INTERMEDIATE_CUFF_PRESSURE_CHAR                 0x2A36     /**< Intermediate Cuff Pressure characteristic UUID. */
+#define BLE_UUID_INTERMEDIATE_TEMPERATURE_CHAR                   0x2A1E     /**< Intermediate Temperature characteristic UUID. */
+#define BLE_UUID_LOCAL_TIME_INFORMATION_CHAR                     0x2A0F     /**< Local Time Information characteristic UUID. */
+#define BLE_UUID_MANUFACTURER_NAME_STRING_CHAR                   0x2A29     /**< Manufacturer Name String characteristic UUID. */
+#define BLE_UUID_MEASUREMENT_INTERVAL_CHAR                       0x2A21     /**< Measurement Interval characteristic UUID. */
+#define BLE_UUID_MODEL_NUMBER_STRING_CHAR                        0x2A24     /**< Model Number String characteristic UUID. */
+#define BLE_UUID_UNREAD_ALERT_CHAR                               0x2A45     /**< Unread Alert characteristic UUID. */
+#define BLE_UUID_NEW_ALERT_CHAR                                  0x2A46     /**< New Alert characteristic UUID. */
+#define BLE_UUID_PNP_ID_CHAR                                     0x2A50     /**< PNP Id characteristic UUID. */
+#define BLE_UUID_PROTOCOL_MODE_CHAR                              0x2A4E     /**< Protocol Mode characteristic UUID. */
+#define BLE_UUID_RECORD_ACCESS_CONTROL_POINT_CHAR                0x2A52     /**< Record Access Control Point characteristic UUID. */
+#define BLE_UUID_REFERENCE_TIME_INFORMATION_CHAR                 0x2A14     /**< Reference Time Information characteristic UUID. */
+#define BLE_UUID_REPORT_CHAR                                     0x2A4D     /**< Report characteristic UUID. */
+#define BLE_UUID_REPORT_MAP_CHAR                                 0x2A4B     /**< Report Map characteristic UUID. */
+#define BLE_UUID_RINGER_CONTROL_POINT_CHAR                       0x2A40     /**< Ringer Control Point characteristic UUID. */
+#define BLE_UUID_RINGER_SETTING_CHAR                             0x2A41     /**< Ringer Setting characteristic UUID. */
+#define BLE_UUID_SCAN_INTERVAL_WINDOW_CHAR                       0x2A4F     /**< Scan Interval Window characteristic UUID. */
+#define BLE_UUID_SCAN_REFRESH_CHAR                               0x2A31     /**< Scan Refresh characteristic UUID. */
+#define BLE_UUID_SERIAL_NUMBER_STRING_CHAR                       0x2A25     /**< Serial Number String characteristic UUID. */
+#define BLE_UUID_SOFTWARE_REVISION_STRING_CHAR                   0x2A28     /**< Software Revision String characteristic UUID. */
+#define BLE_UUID_SUPPORTED_NEW_ALERT_CATEGORY_CHAR               0x2A47     /**< Supported New Alert Category characteristic UUID. */
+#define BLE_UUID_SUPPORTED_UNREAD_ALERT_CATEGORY_CHAR            0x2A48     /**< Supported Unread Alert Category characteristic UUID. */
+#define BLE_UUID_SYSTEM_ID_CHAR                                  0x2A23     /**< System Id characteristic UUID. */
+#define BLE_UUID_TEMPERATURE_MEASUREMENT_CHAR                    0x2A1C     /**< Temperature Measurement characteristic UUID. */
+#define BLE_UUID_TEMPERATURE_TYPE_CHAR                           0x2A1D     /**< Temperature Type characteristic UUID. */
+#define BLE_UUID_TIME_ACCURACY_CHAR                              0x2A12     /**< Time Accuracy characteristic UUID. */
+#define BLE_UUID_TIME_SOURCE_CHAR                                0x2A13     /**< Time Source characteristic UUID. */
+#define BLE_UUID_TIME_UPDATE_CONTROL_POINT_CHAR                  0x2A16     /**< Time Update Control Point characteristic UUID. */
+#define BLE_UUID_TIME_UPDATE_STATE_CHAR                          0x2A17     /**< Time Update State characteristic UUID. */
+#define BLE_UUID_TIME_WITH_DST_CHAR                              0x2A11     /**< Time With Dst characteristic UUID. */
+#define BLE_UUID_TIME_ZONE_CHAR                                  0x2A0E     /**< Time Zone characteristic UUID. */
+#define BLE_UUID_TX_POWER_LEVEL_CHAR                             0x2A07     /**< TX Power Level characteristic UUID. */
+#define BLE_UUID_CSC_FEATURE_CHAR                                0x2A5C     /**< Cycling Speed and Cadence Feature characteristic UUID. */
+#define BLE_UUID_CSC_MEASUREMENT_CHAR                            0x2A5B     /**< Cycling Speed and Cadence Measurement characteristic UUID. */
+#define BLE_UUID_RSC_FEATURE_CHAR                                0x2A54     /**< Running Speed and Cadence Feature characteristic UUID. */
+#define BLE_UUID_SC_CTRLPT_CHAR                                  0x2A55     /**< Speed and Cadence Control Point UUID. */
+#define BLE_UUID_RSC_MEASUREMENT_CHAR                            0x2A53     /**< Running Speed and Cadence Measurement characteristic UUID. */
+#define BLE_UUID_SENSOR_LOCATION_CHAR                            0x2A5D     /**< Sensor Location characteristic UUID. */
+#define BLE_UUID_EXTERNAL_REPORT_REF_DESCR                       0x2907     /**< External Report Reference descriptor UUID. */
+#define BLE_UUID_REPORT_REF_DESCR                                0x2908     /**< Report Reference descriptor UUID. */
+#define BLE_UUID_LN_FEATURE_CHAR                                 0x2A6A     /**< Location Navigation Service, Feature characteristic UUID. */
+#define BLE_UUID_LN_POSITION_QUALITY_CHAR                        0x2A69     /**< Location Navigation Service, Position quality UUID. */
+#define BLE_UUID_LN_LOCATION_AND_SPEED_CHAR                      0x2A67     /**< Location Navigation Service, Location and Speed characteristic UUID. */
+#define BLE_UUID_LN_NAVIGATION_CHAR                              0x2A68     /**< Location Navigation Service, Navigation characteristic UUID. */
+#define BLE_UUID_LN_CONTROL_POINT_CHAR                           0x2A6B     /**< Location Navigation Service, Control point characteristic UUID. */
+#define BLE_UUID_BMS_CTRLPT                                      0x2AA4     /**< BMS Control Point characteristic UUID. */
+#define BLE_UUID_BMS_FEATURE                                     0x2AA5     /**< BMS Feature characteristic UUID. */
+#define BLE_UUID_CGM_MEASUREMENT                                 0x2AA7     /**< CGM Service, Measurement characteristic UUID*/
+#define BLE_UUID_CGM_FEATURE                                     0x2AA8     /**< CGM Service, Feature characteristic UUID*/
+#define BLE_UUID_CGM_STATUS                                      0x2AA9     /**< CGM Service, Status characteristic UUID*/
+#define BLE_UUID_CGM_SESSION_START_TIME                          0x2AAA     /**< CGM Service, session start time characteristic UUID*/
+#define BLE_UUID_CGM_SESSION_RUN_TIME                            0x2AAB     /**< CGM Service, session run time characteristic UUID*/
+#define BLE_UUID_CGM_SPECIFIC_OPS_CTRLPT                         0x2AAC     /**< CGM Service, specific ops ctrlpt characteristic UUID*/
+#define BLE_UUID_PLX_SPOT_CHECK_MEAS                             0x2A5E     /**< PLX Service, spot check measurement characteristic UUID*/
+#define BLE_UUID_PLX_CONTINUOUS_MEAS                             0x2A5F     /**< PLX Service, continuous measurement characteristic UUID*/
+#define BLE_UUID_PLX_FEATURES                                    0x2A60     /**< PLX Service, feature characteristic UUID*/
+
+
+
+
+
+/** @} */
+
+/** @defgroup ALERT_LEVEL_VALUES Definitions for the Alert Level characteristic values
+ * @{ */
+#define BLE_CHAR_ALERT_LEVEL_NO_ALERT                            0x00       /**< No Alert. */
+#define BLE_CHAR_ALERT_LEVEL_MILD_ALERT                          0x01       /**< Mild Alert. */
+#define BLE_CHAR_ALERT_LEVEL_HIGH_ALERT                          0x02       /**< High Alert. */
+/** @} */
+
+#define BLE_SRV_ENCODED_REPORT_REF_LEN                           2          /**< The length of an encoded Report Reference Descriptor. */
+#define BLE_CCCD_VALUE_LEN                                       2          /**< The length of a CCCD value. */
+
+/**@brief Type definition for error handler function that will be called in case of an error in
+ *        a service or a service library module. */
+typedef void (*ble_srv_error_handler_t) (uint32_t nrf_error);
+
+
+
+/**@brief Value of a Report Reference descriptor.
+ *
+ * @details This is mapping information that maps the parent characteristic to the Report ID(s) and
+ *          Report Type(s) defined within a Report Map characteristic.
+ */
+typedef struct
+{
+    uint8_t report_id;                                  /**< Non-zero value if there is more than one instance of the same Report Type */
+    uint8_t report_type;                                /**< Type of Report characteristic (see @ref BLE_HIDS_REPORT_TYPE) */
+} ble_srv_report_ref_t;
+
+/**@brief UTF-8 string data type.
+ *
+ * @note The type can only hold a pointer to the string data (i.e. not the actual data).
+ */
+typedef struct
+{
+    uint16_t  length;                                   /**< String length. */
+    uint8_t * p_str;                                    /**< String data. */
+} ble_srv_utf8_str_t;
+
+
+/**@brief Security settings structure.
+ * @details This structure contains the security options needed during initialization of the
+ *          service.
+ */
+typedef struct
+{
+    ble_gap_conn_sec_mode_t read_perm;                  /**< Read permissions. */
+    ble_gap_conn_sec_mode_t write_perm;                 /**< Write permissions. */
+} ble_srv_security_mode_t;
+
+/**@brief Security settings structure.
+ * @details This structure contains the security options needed during initialization of the
+ *          service. It can be used when the characteristics contains a CCCD.
+ */
+typedef struct
+{
+    ble_gap_conn_sec_mode_t cccd_write_perm;            /**< Write permissions for Client Characteristic Configuration Descriptor. */
+    ble_gap_conn_sec_mode_t read_perm;                  /**< Read permissions. */
+    ble_gap_conn_sec_mode_t write_perm;                 /**< Write permissions. */
+} ble_srv_cccd_security_mode_t;
+
+/**@brief Function for decoding a CCCD value, and then testing if notification is
+ *        enabled.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded CCCD is stored.
+ *
+ * @retval      TRUE If notification is enabled.
+ * @retval      FALSE Otherwise.
+ */
+static __INLINE bool ble_srv_is_notification_enabled(uint8_t const * p_encoded_data)
+{
+    uint16_t cccd_value = uint16_decode(p_encoded_data);
+    return ((cccd_value & BLE_GATT_HVX_NOTIFICATION) != 0);
+}
+
+/**@brief Function for decoding a CCCD value, and then testing if indication is
+ *        enabled.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded CCCD is stored.
+ *
+ * @retval      TRUE If indication is enabled.
+ * @retval      FALSE Otherwise.
+ */
+static __INLINE bool ble_srv_is_indication_enabled(uint8_t const * p_encoded_data)
+{
+    uint16_t cccd_value = uint16_decode(p_encoded_data);
+    return ((cccd_value & BLE_GATT_HVX_INDICATION) != 0);
+}
+
+/**@brief Function for encoding a Report Reference Descriptor.
+ *
+ * @param[in]   p_encoded_buffer  The buffer of the encoded data.
+ * @param[in]   p_report_ref      Report Reference value to be encoded.
+ *
+ * @return      Length of the encoded data.
+ */
+uint8_t ble_srv_report_ref_encode(uint8_t *                    p_encoded_buffer,
+                                  const ble_srv_report_ref_t * p_report_ref);
+
+/**@brief Function for making a UTF-8 structure refer to an ASCII string.
+ *
+ * @param[out]  p_utf8   UTF-8 structure to be set.
+ * @param[in]   p_ascii  ASCII string to be referred to.
+ */
+void ble_srv_ascii_to_utf8(ble_srv_utf8_str_t * p_utf8, char * p_ascii);
+
+
+/**@brief Security Access enumeration.
+ * @details This enumeration gives the possible requirements for accessing a characteristic value.
+ */
+typedef enum
+{
+    SEC_NO_ACCESS    = 0,            /**< Not possible to access. */
+    SEC_OPEN         = 1,            /**< Access open. */
+    SEC_JUST_WORKS   = 2,            /**< Access possible with 'Just Works' security at least. */
+    SEC_MITM         = 3,            /**< Access possible with 'MITM' security at least. */
+    SEC_SIGNED       = 4,            /**< Access possible with 'signed' security at least. */
+    SEC_SIGNED_MITM  = 5             /**< Access possible with 'signed and MITM' security at least. */
+}security_req_t;
+
+
+/**@brief Characteristic User Descriptor parameters.
+ * @details This structure contains the parameters for User Descriptor.
+ */
+typedef struct
+{
+    uint16_t               max_size;                      /**< Maximum size of the user descriptor*/
+    uint16_t               size;                          /**< Size of the user descriptor*/
+    uint8_t                *p_char_user_desc;             /**< User descriptor content, pointer to a UTF-8 encoded string (non-NULL terminated)*/
+    bool                   is_var_len;                    /**< Indicates if the user descriptor has variable length.*/
+    ble_gatt_char_props_t  char_props;                    /**< user descriptor properties.*/
+    bool                   is_defered_read;               /**< Indicate if deferred read operations are supported.*/
+    bool                   is_defered_write;              /**< Indicate if deferred write operations are supported.*/
+    security_req_t         read_access;                   /**< Security requirement for reading the user descriptor.*/
+    security_req_t         write_access;                  /**< Security requirement for writing the user descriptor.*/
+    bool                   is_value_user;                 /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
+}ble_add_char_user_desc_t;
+
+
+/**@brief Add characteristic parameters structure.
+ * @details This structure contains the parameters needed to use the @ref characteristic_add function.
+ */
+typedef struct
+{
+    uint16_t                    uuid;                     /**< Characteristic UUID (16 bits UUIDs).*/
+    uint8_t                     uuid_type;                /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/
+    uint16_t                    max_len;                  /**< Maximum length of the characteristic value.*/
+    uint16_t                    init_len;                 /**< Initial length of the characteristic value.*/
+    uint8_t *                   p_init_value;             /**< Initial encoded value of the characteristic.*/
+    bool                        is_var_len;               /**< Indicates if the characteristic value has variable length.*/
+    ble_gatt_char_props_t       char_props;               /**< Characteristic properties.*/
+    bool                        is_defered_read;          /**< Indicate if deferred read operations are supported.*/
+    bool                        is_defered_write;         /**< Indicate if deferred write operations are supported.*/
+    security_req_t              read_access;              /**< Security requirement for reading the characteristic value.*/
+    security_req_t              write_access;             /**< Security requirement for writing the characteristic value.*/
+    security_req_t              cccd_write_access;        /**< Security requirement for writing the characteristic's CCCD.*/
+    bool                        is_value_user;            /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
+    ble_add_char_user_desc_t    *p_user_descr;            /**< Pointer to user descriptor if needed*/
+    ble_gatts_char_pf_t         *p_presentation_format;   /**< Pointer to characteristic format if needed*/
+} ble_add_char_params_t;
+
+
+/**@brief Add descriptor parameters structure.
+ * @details This structure contains the parameters needed to use the @ref descriptor_add function.
+ */
+typedef struct
+{
+    uint16_t       uuid;                     /**< descriptor UUID (16 bits UUIDs).*/
+    uint8_t        uuid_type;                /**< Base UUID. If 0, the Bluetooth SIG UUID will be used. Otherwise, this should be a value returned by @ref sd_ble_uuid_vs_add when adding the base UUID.*/
+    bool           is_defered_read;          /**< Indicate if deferred read operations are supported.*/
+    bool           is_defered_write;         /**< Indicate if deferred write operations are supported.*/
+    bool           is_var_len;               /**< Indicates if the descriptor value has variable length.*/
+    security_req_t read_access;              /**< Security requirement for reading the descriptor value.*/
+    security_req_t write_access;             /**< Security requirement for writing the descriptor value.*/
+    bool           is_value_user;            /**< Indicate if the content of the characteristic is to be stored in the application (user) or in the stack.*/
+    uint16_t       init_len;                 /**< Initial descriptor value length in bytes. */
+    uint16_t       init_offs;                /**< Initial descriptor value offset in bytes. If different from zero, the first init_offs bytes of the attribute value will be left uninitialized. */
+    uint16_t       max_len;                  /**< Maximum descriptor value length in bytes, see @ref BLE_GATTS_ATTR_LENS_MAX for maximum values. */
+    uint8_t*       p_value;                  /**< Pointer to the value of the descriptor*/
+} ble_add_descr_params_t;
+
+
+/**@brief Function for adding a characteristic to a given service.
+ *
+ * If no pointer is given for the initial value,
+ * the initial length parameter will be ignored and the initial length will be 0.
+ *
+ * @param[in]  service_handle Handle of the service to which the characteristic is to be added.
+ * @param[in]  p_char_props   Information needed to add the characteristic.
+ * @param[out] p_char_handle  Handle of the added characteristic.
+ *
+ * @retval      NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned.
+ */
+uint32_t characteristic_add(uint16_t                   service_handle,
+                            ble_add_char_params_t *    p_char_props,
+                            ble_gatts_char_handles_t * p_char_handle);
+
+
+/**@brief Function for adding a characteristic's descriptor to a given characteristic.
+ *
+ * @param[in]  char_handle    Handle of the characteristic to which the descriptor is to be added, if @ref BLE_GATT_HANDLE_INVALID is used, it will be placed sequentially.
+ * @param[in]  p_descr_props  Information needed to add the descriptor.
+ * @param[out] p_descr_handle Handle of the added descriptor.
+ *
+ * @retval      NRF_SUCCESS If the characteristic was added successfully. Otherwise, an error code is returned.
+ */
+uint32_t descriptor_add(uint16_t                   char_handle,
+                        ble_add_descr_params_t *   p_descr_props,
+                        uint16_t *                 p_descr_handle);
+
+
+#endif // BLE_SRV_COMMON_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/config/device_manager_cnfg.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/config/device_manager_cnfg.h
new file mode 100644
index 0000000000..394a118874
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/config/device_manager_cnfg.h
@@ -0,0 +1,126 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /**
+ * @file device_manager_cnfg.h
+ *
+ * @cond
+ * @defgroup device_manager_cnfg Device Manager Configuration 
+ * @ingroup device_manager
+ * @{
+ *
+ * @brief Defines application specific configuration for Device Manager.
+ *
+ * @details All configurations that are specific to application have been defined
+ *          here. Application should configuration that best suits its requirements.
+ */
+ 
+#ifndef DEVICE_MANAGER_CNFG_H__
+#define DEVICE_MANAGER_CNFG_H__
+
+/**
+ * @defgroup device_manager_inst Device Manager Instances
+ * @{
+ */
+/**
+ * @brief Maximum applications that Device Manager can support.
+ *
+ * @details Maximum application that the Device Manager can support.
+ *          Currently only one application can be supported.
+ *          Minimum value : 1
+ *          Maximum value : 1
+ *          Dependencies  : None.
+ */
+#define DEVICE_MANAGER_MAX_APPLICATIONS  1
+
+/**
+ * @brief Maximum connections that Device Manager should simultaneously manage.
+ *
+ * @details Maximum connections that Device Manager should simultaneously manage.
+ *          Minimum value : 1
+ *          Maximum value : Maximum links supported by SoftDevice.
+ *          Dependencies  : None.
+ */
+#define DEVICE_MANAGER_MAX_CONNECTIONS   1
+
+
+/**
+ * @brief Maximum bonds that Device Manager should manage.
+ *
+ * @details Maximum bonds that Device Manager should manage.
+ *          Minimum value : 1
+ *          Maximum value : 254.
+ *          Dependencies  : None.
+ * @note In case of GAP Peripheral role, the Device Manager will accept bonding procedure 
+ *       requests from peers even if this limit is reached, but bonding information will not 
+ *       be stored. In such cases, application will be notified with DM_DEVICE_CONTEXT_FULL 
+ *       as event result at the completion of the security procedure.
+ */
+#define DEVICE_MANAGER_MAX_BONDS         7
+
+
+/**
+ * @brief Maximum Characteristic Client Descriptors used for GATT Server.
+ *
+ * @details Maximum Characteristic Client Descriptors used for GATT Server.
+ *          Minimum value : 1
+ *          Maximum value : 254.
+ *          Dependencies  : None.
+ */
+#define DM_GATT_CCCD_COUNT               2
+
+
+/**
+ * @brief Size of application context.
+ *
+ * @details Size of application context that Device Manager should manage for each bonded device.
+ *          Size had to be a multiple of word size.
+ *          Minimum value : 4.
+ *          Maximum value : 256. 
+ *          Dependencies  : Needed only if Application Context saving is used by the application.
+ * @note If set to zero, its an indication that application context is not required to be managed
+ *       by the module.
+ */
+#define DEVICE_MANAGER_APP_CONTEXT_SIZE    0
+
+/* @} */
+/* @} */
+/** @endcond */
+#endif // DEVICE_MANAGER_CNFG_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager.h
new file mode 100644
index 0000000000..0b085abc64
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager.h
@@ -0,0 +1,915 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file device_manager.h
+ *
+ * @defgroup device_manager Device Manager
+ * @ingroup ble_sdk_lib
+ * @{
+ * @brief Device Manager Application Interface Abstraction.
+ *
+ * @details The Device Manager module manages Active and Bonded Peers. Management of peer includes
+ *          book keeping of contextual information like the Security Keys, GATT
+ *          configuration and any application specific information.
+ *
+ *          Active Peers are devices which are connected, and may or may not be bonded.
+ *          Bonded Peers are devices which are bonded, and may or may not be Active (Connected).
+ *          Active Bonded Peer refers to a device which is connected and bonded.
+ *
+ *          Paired Devices refers to peer devices that are connected and have necessary context
+ *          establishment/exchange for the current connection session. On disconnect,
+ *          all contextual information is flushed. For example, SMP Information Exchanged during
+ *          pairing and GATT Configuration is not retained on disconnection.
+ *
+ *          Note that this module allows management of contextual information but
+ *          does not provide an interface for connection management. Therefore, entering connectible
+ *          mode, connection establishment, or disconnection of a link with peer is not in scope
+ *          of this module.
+ *
+ *          For bonded peers, the contextual information is required to be retained on disconnection
+ *          and power cycling. Persistent storage of contextual information is handled by the
+ *          module. This module categorizes the contextual information into 3 categories:
+ *             - <b>Bonding Information</b>
+ *               Bond information is the information exchanged between local and peer device to
+ *               establish a bond. It also includes peer identification information,
+ *               like the peer address or the IRK or both. From here on this category of information
+ *               is referred to as Device Context.
+ *             - <b>Service/Protocol Information</b>
+ *               Service/Protocol information is the information retained for the peer to save on one-time
+ *               procedures like the GATT Service Discovery procedures and Service Configurations.
+ *               It allows devices to resume data exchange on subsequent reconnection without having
+ *               to perform initial set-up procedures each time. From here on this category is
+ *               referred to as Service Context.
+ *             - <b>Application Information</b>
+ *               Application information is the context that the application would like to associate with
+ *               each of the bonded device. For example, if the application chooses to rank its peers
+ *               in order to manage them better, the rank information could be treated as
+ *               Application Information. This storage space is provided to save the application from
+ *               maintaining a mapping table with each Device Instance and Application Information.
+ *               However, if the application have no use for this, it is possible to not
+ *               use or employ this at compile time. From here on this category of information is
+ *               referred to as Application Context.
+ */
+
+
+#ifndef DEVICE_MANAGER_H__
+#define DEVICE_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdk_common.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "device_manager_cnfg.h"
+
+/**
+ * @defgroup dm_service_cntext_types Service/Protocol Types
+ *
+ * @brief Describes the possible types of Service/Protocol Contexts for a bonded/peer device.
+ *
+ * @details Possible Service/Protocol context per peer device. The Device Manager provides the
+ *          functionality of persistently storing the Service/Protocol context and can automatically
+ *          load them when needed.
+ *          For example system attributes for a GATT Server. Based on the nature of the application,
+ *          not all service types may be needed. The application can specify
+ *          only the service/protocol context it wants to use at the time of registration.
+ * @{
+ */
+#define DM_PROTOCOL_CNTXT_NONE         0x00  /**< No Service Context, this implies the application does not want to associate any service/protocol context with the peer device */
+#define DM_PROTOCOL_CNTXT_GATT_SRVR_ID 0x01  /**< GATT Server Service Context, this implies the application does associate GATT Server with the peer device and this information will be loaded when needed for a bonded device */
+#define DM_PROTOCOL_CNTXT_GATT_CLI_ID  0x02  /**< GATT Client Service Context, this implies the application does associate GATT Client with the peer device and this information will be loaded when needed for a bonded device */
+#define DM_PROTOCOL_CNTXT_ALL                                                                     \
+        (DM_PROTOCOL_CNTXT_GATT_SRVR_ID | DM_PROTOCOL_CNTXT_GATT_CLI_ID) /**< All Service/Protocol Context, this implies that the application wants to associate all Service/Protocol Information with the bonded device. This is configurable based on system requirements. If the application has only one type of service, this define could be altered to reflect the same.  */
+/** @} */
+
+
+/**
+ * @defgroup dm_events Device Manager Events
+ *
+ * @brief This section describes the device manager events that are notified to the application.
+ *
+ * @details The Device Manager notifies the application of various asynchronous events using the
+ *          asynchronous event notification callback. All events has been categorized into:
+ *          a. General.
+ *          b. Link Status.
+ *          c. Context Management.
+ *
+ *          In the callback, these events are notified along with handle that uniquely identifies:
+ *          application instance, active instance (if applicable), device instance
+ *          bonding instance, (if applicable) and service instance.
+ *          Not all events are pertaining to an active connection, for example a context deletion event could occur even if the peer
+ *          is not connected. Also, general category of events may not be pertaining to any specific peer.
+ *          See also \ref dm_event_cb_t and \ref dm_register.
+ * @{
+ */
+/**
+ * @defgroup general_events General Events
+ *
+ * @brief General or miscellaneous events.
+ *
+ * @details This category of events are general events not pertaining to a peer or context.
+ *
+ * @{
+ */
+#define DM_EVT_RFU   0x00 /**< Reserved for future use, is never notified. */
+#define DM_EVT_ERROR 0x01 /**< Device Manager Event Error. */
+/** @} */
+
+/**
+ * @defgroup link_status_events Link Status Events
+ *
+ * @brief Link Status Events.
+ *
+ * @details This category of events notify the application of the link status. Event result associated
+ *          with the event is provided along with the event in the callback to provide more details of
+ *          whether a procedure succeeded or failed and assist the application in decision making of
+ *          how to proceed. For example if a DM_DEVICE_CONNECT_IND is indicated with NRF_SUCCESS
+ *          result, the application may want to proceed with discovering and association with
+ *          service of the peer. However, if indicated with a failure result, the application may
+ *          want to take an alternate action such as reattempting to connect or go into a
+ *          sleep mode.
+ *
+ * @{
+ */
+#define DM_EVT_CONNECTION              0x11 /**< Indicates that link with the peer is established. */
+#define DM_EVT_DISCONNECTION           0x12 /**< Indicates that link with peer is torn down. */
+#define DM_EVT_SECURITY_SETUP          0x13 /**< Security procedure for link started indication */
+#define DM_EVT_SECURITY_SETUP_COMPLETE 0x14 /**< Security procedure for link completion indication. */
+#define DM_EVT_LINK_SECURED            0x15 /**< Indicates that link with the peer is secured. For bonded devices, subsequent reconnections with bonded peer will result only in this event when the link is secured and setup procedures will not occur unless the bonding information is either lost or deleted on either or both sides.  */
+#define DM_EVT_SECURITY_SETUP_REFRESH  0x16 /**< Indicates that the security on the link was re-established. */
+/** @} */
+
+/**
+ * @defgroup context_mgmt_events Context Management Events
+ *
+ * @brief Context Management Events.
+ *
+ * @details These events notify the application of the status of context loading and storing.
+ *
+ * @{
+ */
+#define DM_EVT_DEVICE_CONTEXT_LOADED   0x21 /**< Indicates that device context for a peer is loaded. */
+#define DM_EVT_DEVICE_CONTEXT_STORED   0x22 /**< Indicates that device context is stored persistently. */
+#define DM_EVT_DEVICE_CONTEXT_DELETED  0x23 /**< Indicates that device context is deleted. */
+#define DM_EVT_SERVICE_CONTEXT_LOADED  0x31 /**< Indicates that service context for a peer is loaded. */
+#define DM_EVT_SERVICE_CONTEXT_STORED  0x32 /**< Indicates that service context is stored persistently. */
+#define DM_EVT_SERVICE_CONTEXT_DELETED 0x33 /**< Indicates that service context is deleted. */
+#define DM_EVT_APPL_CONTEXT_LOADED     0x41 /**< Indicates that application context for a peer is loaded. */
+#define DM_EVT_APPL_CONTEXT_STORED     0x42 /**< Indicates that application context is stored persistently. */
+#define DM_EVT_APPL_CONTEXT_DELETED    0x43 /**< Indicates that application context is deleted. */
+/** @} */
+/** @} */
+
+#define DM_INVALID_ID 0xFF /**< Invalid instance idenitifer. */
+
+/**
+ * @defgroup dm_data_structure Device Manager Data Types
+ *
+ * @brief This section describes all the data types exposed by the module to the application.
+ * @{
+ */
+
+/**
+ * @brief Application Instance.
+ *
+ * @details Application instance uniquely identifies an application. The identifier is allocated by
+ *          the device manager when application registers with the module. The application is
+ *          expected to identify itself with this instance identifier when initiating subsequent
+ *          requests. Application should use the utility API \ref dm_application_instance_set in
+ *          order to set its application instance in dm_handle_t needed for all subsequent APIs.
+ *          See also \ref dm_register.
+ */
+typedef uint8_t dm_application_instance_t;
+
+/**
+ * @brief Connection Instance.
+ *
+ * @details Identifies connection instance for an active device. This instance is allocated by the
+ *          device manager when a connection is established and is notified with DM_EVT_CONNECTION
+ *          with the event result NRF_SUCCESS.
+ */
+typedef uint8_t dm_connection_instance_t;
+
+/**
+ * @brief Device Instance.
+ *
+ * @details Uniquely identifies a bonded peer device. The peer device may or may not be connected.
+ *          In case of the central: The bonded device instance to identify the peer is allocated when bonding procedure is initiated by the central using dm_security_setup_req.
+ *          In case of the peripheral: When the bonding procedure is successful, the DM_EVT_SECURITY_SETUP_COMPLETE event with success event result, is received.
+ *          In case the module cannot add more bonded devices, no instance is allocated, this is indicated by an appropriate error code for the API/event as the case may be. Application can choose to disconnect the link.
+ */
+typedef uint8_t dm_device_instance_t;
+
+/**
+ * @brief Service Instance.
+ *
+ * @details Uniquely identifies a peer device. The peer device may or may not be connected. This
+ *          instance is allocated by the device manager when a device is bonded and is notified
+ *          when security procedures have been initiated.
+ *          Security Procedures initiation is notified with DM_SECURITY_SETUP_IND with
+ *          success event result. In case the event result indicates that the module cannot add more
+ *          bonded devices, no instance is allocated. Application can chose to disconnect the link.
+ */
+typedef uint8_t dm_service_instance_t;
+
+/**
+ * @brief Service/Protocol Type Identifier.
+ *
+ * @details Uniquely identifies a service or a protocol type. Service/Protocol Type identification
+ *          is needed as each service/protocol can have its own contextual data.
+ *          This allows the peer to access more than one service at a time. \ref dm_service_cntext_types describes the
+ *          list of services/protocols supported.
+ */
+typedef uint8_t service_type_t;
+
+/**@brief Device Manager Master identification and encryption information. */
+typedef struct dm_enc_key
+{
+    ble_gap_enc_info_t  enc_info;  /**< GAP encryption information. */
+    ble_gap_master_id_t master_id; /**< Master identification. */
+} dm_enc_key_t;
+
+/** @brief Device Manager identity and address information. */
+typedef struct dm_id_key
+{
+  ble_gap_irk_t  id_info;      /**< Identity information. */
+  ble_gap_addr_t id_addr_info; /**< Identity address information. */
+} dm_id_key_t;
+
+/** @brief Device Manager signing information. */
+typedef struct dm_sign_key
+{
+    ble_gap_sign_info_t sign_key; /**< GAP signing information. */
+} dm_sign_key_t;
+
+/** @brief Security keys. */
+typedef struct dm_sec_keyset
+{
+    union
+    {
+        dm_enc_key_t       * p_enc_key;  /**< Pointer to Device Manager encryption information structure. */
+    } enc_key;
+    dm_id_key_t   * p_id_key;            /**< Identity key, or NULL. */
+    dm_sign_key_t * p_sign_key;          /**< Signing key, or NULL. */
+} dm_sec_keys_t;
+
+/** @brief Device Manager security key set. */
+typedef struct
+{
+  dm_sec_keys_t keys_periph;  /**< Keys distributed by the device in the Peripheral role. */
+  dm_sec_keys_t keys_central; /**< Keys distributed by the device in the Central role. */
+} dm_sec_keyset_t;
+
+/**
+ * @brief Device Handle used for unique identification of each peer.
+ *
+ * @details This data type is used to uniquely identify each peer device. A peer device could be
+ *          active and/or bonded. Therefore an instance for active and bonded is provided.
+ *          However, the application is expected to treat this is an opaque structure and use this for
+ *          all API interactions once stored on appropriate events.
+ *          See \ref dm_events.
+ */
+typedef struct device_handle
+{
+    dm_application_instance_t    appl_id;       /**< Identifies the application instances for the device that is being managed. */
+    dm_connection_instance_t     connection_id; /**< Identifies the active connection instance. */
+    dm_device_instance_t         device_id;     /**< Identifies peer instance in the data base. */
+    dm_service_instance_t        service_id;    /**< Service instance identifier. */
+} dm_handle_t;
+
+/**
+ * @brief Definition of Data Context.
+ *
+ * @details Defines contextual data format, it consists of context data length and pointer to data.
+ */
+typedef struct
+{
+    uint32_t  flags;  /**< Additional flags identifying data. */
+    uint32_t  len;    /**< Length of data. */
+    uint8_t * p_data; /**< Pointer to contextual data, a copy is made of the data. */
+} dm_context_t;
+
+
+/**
+ * @brief Device Context.
+ *
+ * @details Defines "device context" type for a device managed by device manager.
+ */
+typedef dm_context_t dm_device_context_t;
+
+/**
+ * @brief Service Context.
+ *
+ * @details Service context data for a service identified by the 'service_type' field.
+ */
+typedef struct
+{
+    service_type_t service_type; /**< Identifies the service/protocol to which the context data is related. */
+    dm_context_t   context_data; /**< Contains length and pointer to context data */
+} dm_service_context_t;
+
+/**
+ * @brief Application context.
+ *
+ * @details The application context can be used by the application to map any application level
+ *          information that is to be mapped with a particular peer.
+ *          For bonded peers, this information will be stored by the bond manager persistently.
+ *          Note that the device manager treats this information as an
+ *          opaque block of bytes.
+ *          Necessary APIs to get and set this context for a peer have been provided.
+ */
+typedef dm_context_t dm_application_context_t;
+
+/**
+ * @brief Event parameters.
+ *
+ * @details Defines event parameters for each of the events notified by the module.
+ */
+typedef union
+{
+    ble_gap_evt_t            * p_gap_param;       /**< All events that are triggered in device manager as a result of GAP events, like connection, disconnection and security procedures are accompanied with GAP parameters. */
+    dm_application_context_t * p_app_context;     /**< All events that are associated with application context procedures of store, load, and deletion have this as event parameter. */
+    dm_service_context_t     * p_service_context; /**< All events that are associated with service context procedures of store, load and deletion have this as event parameter. */
+    dm_device_context_t      * p_device_context;  /**< All events that are associated with device context procedures of store, load and deletion have this as event parameter. */
+} dm_event_param_t;
+
+/**
+ * @brief Asynchronous events details notified to the application by the module.
+ *
+ * @details Defines event type along with event parameters notified to the application by the
+ *          module.
+ */
+typedef struct
+{
+    uint8_t          event_id;       /**< Identifies the event. See \ref dm_events for details on event types and their significance. */
+    dm_event_param_t event_param;    /**< Event parameters. Can be NULL if the event does not have any parameters. */
+    uint16_t         event_paramlen; /**< Length of the event parameters, is zero if the event does not have any parameters. */
+} dm_event_t;
+
+/**
+ * @brief Event notification callback registered by application with the module.
+ *
+ * @details Event notification callback registered by application with the module when registering
+ *          the module using \ref dm_register API.
+ *
+ * @param[in] p_handle   Identifies the peer for which the event is being notified.
+ * @param[in] p_event    Identifies the event, any associated parameters and parameter length.
+ *                       See \ref dm_events for details on event types and their significance.
+ * @param[in,out] event_result   Provide additional information on the event.
+ *                      In addition to SDK error codes there is also a return value
+ *                      indicating if maximum number of connections has been reached when connecting or bonding.
+ *
+ * @retval NRF_SUCCESS on success, or a failure to indicate if it could handle the event
+ *         successfully. There is no action taken in case application returns a failure.
+ */
+typedef ret_code_t (*dm_event_cb_t)(dm_handle_t const * p_handle,
+                                    dm_event_t const  * p_event,
+                                    ret_code_t        event_result);
+
+/**
+ * @brief Initialization Parameters.
+ *
+ * @details Indicates the application parameters. Currently this only encompasses clearing
+ *          all persistent data.
+ */
+typedef struct
+{
+    bool clear_persistent_data; /**< Set to true in case the module should clear all persistent data. */
+} dm_init_param_t;
+
+/**
+ * @brief Application Registration Parameters.
+ *
+ * @details Parameters needed by the module when registering with it.
+ */
+typedef struct
+{
+    dm_event_cb_t        evt_handler;  /**< Event Handler to be registered. It will receive asynchronous notification from the module, see \ref dm_events for asynchronous events. */
+    uint8_t              service_type; /**< Bit mask identifying services that the application intends to support for all peers. */
+    ble_gap_sec_params_t sec_param;    /**< Security parameters to be used for the application. */
+} dm_application_param_t;
+
+/**
+ * @brief Defines possible security status/states.
+ *
+ * @details Defines possible security status/states of a link when requested by application using
+ *          the \ref dm_security_status_req.
+ */
+typedef enum
+{
+    NOT_ENCRYPTED,          /**< The link is not secured. */
+    ENCRYPTION_IN_PROGRESS, /**< Link security is being established.*/
+    ENCRYPTED               /**< The link is secure.*/
+} dm_security_status_t;
+/** @} */
+
+/**
+ * @defgroup dm_api Device Module APIs
+ *
+ * @brief This section describes APIs exposed by the module.
+ *
+ * @details This section describes APIs exposed by the module. The APIs have been categorized to provide
+ *          better and specific look up for developers. Categories are:
+ *          - Set up APIs.
+ *          - Context Management APIs.
+ *          - Utility APIs.
+ *
+ *          MSCs describe usage of these APIs.
+ *          See @ref dm_msc.
+ * @{
+ */
+/**
+ * @defgroup dm_setup_api Device Module Set-up APIs
+ *
+ * @brief Initialization & registration APIs that are pre-requisite for all other module procedures.
+ * @details This section describes the Module Initialization and Registration APIs needed to be set up by
+ *          the application before device manager can start managing devices and device contexts
+ *          for the application.
+ *
+ * @{
+ */
+
+/**
+ * @brief Module Initialization Routine.
+ *
+ * @details Function for initializing the module. Must called before any other APIs of the module are used.
+ *
+ * @param[in] p_init_param Initialization parameters.
+ *
+ * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
+ *
+ * @note It is mandatory that pstorage is initialized before initializing this module.
+ */
+ret_code_t dm_init(dm_init_param_t const * p_init_param);
+
+/**
+ * @brief Function for registering the application.
+ *
+ * @details This routine is used by the application to register for asynchronous events with the
+ *          device manager. During registration the application also indicates the services that it
+ *          intends to support on this instance. It is possible to register multiple times with the
+ *          device manager. At least one instance shall be registered with the device manager after
+ *          the module has been initialized.
+ *          Maximum number of application instances device manager can support is determined
+ *          by DM_MAX_APPLICATIONS.
+ *
+ *          All applications must be registered before initiating or accepting connections from the peer.
+ *
+ * @param[in]  p_appl_param    Application parameters.
+ * @param[out] p_appl_instance Application Instance Identifier in case registration is successful.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization.
+ * @retval NRF_ERROR_NO_MEM        If module cannot support more applications.
+ *
+ * @note Currently only one application instance is supported by the module.
+ */
+ret_code_t dm_register(dm_application_instance_t    * p_appl_instance,
+                       dm_application_param_t const * p_appl_param);
+
+/**
+ * @brief Function for handling BLE events.
+ *
+ * @details BLE Event Handler for the module. This routine should be called from BLE stack event
+ *          dispatcher for the module to work as expected.
+ *
+ * @param[in] p_ble_evt BLE stack event being dispatched to the function.
+ *
+ */
+void dm_ble_evt_handler(ble_evt_t * p_ble_evt);
+
+/** @} */
+
+
+/**
+ * @defgroup dm_security_api APIs to set up or read status of security on a link.
+ *
+ * @brief This section describes APIs to set up Security. These APIs require that the peer is
+ *        connected before the procedures can be requested.
+ *
+ * @details This group allows application to request security procedures
+ *          or get the status of the security on a link.
+ * @{
+ */
+/**
+ * @brief Function for requesting setting up security on a link.
+ *
+ * @details This API initiates security procedures with a peer device.
+ *          @note For the GAP Central role, in case peer is not bonded, request to bond/pair is
+ *          initiated. If it is bonded, the link is re-encrypted using the existing bond information.
+ *          For the GAP peripheral role, a Slave security request is sent.
+ * @details If a pairing procedure is initiated successfully, application is notified of
+ *          @ref DM_EVT_SECURITY_SETUP_COMPLETE. A result indicating success or failure is notified along with the event.
+ *          In case the link is re-encrypted using existing bond information, @ref DM_EVT_LINK_SECURED is
+ *          notified to the application.
+ *
+ * @param[in] p_handle Identifies the link on which security is desired.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application
+ *                                 or if the peer is not connected when this procedure is requested.
+ */
+ret_code_t dm_security_setup_req(dm_handle_t * p_handle);
+
+/**
+ * @brief Function for reading the status of the security on a link.
+ *
+ * @details This API allows application to query status of security on a link.
+ *
+ * @param[in]  p_handle  Identifies the link on which security is desired.
+ * @param[out] p_status  Pointer where security status is provided to the application.
+ *                       See \ref dm_security_status_t for possible statuses that can be expected.
+ *
+ * @retval NRF_SUCCESS             Or appropriate error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle or p_status is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified by the handle provided by the application
+ *                                 or if peer is not connected when this procedure is requested.
+ */
+ret_code_t dm_security_status_req(dm_handle_t const * p_handle, dm_security_status_t * p_status);
+
+/**
+ * @brief Function for creating the whitelist.
+ *
+ * @details This API allows application to create whitelist based on bonded peer devices in module
+ *          data base.
+ *
+ * @param[in]  p_handle       Identifies the application requesting whitelist creation.
+ * @param[in,out] p_whitelist Pointer where created whitelist is provided to the application.
+ *
+ * @note 'addr_count' and 'irk_count' fields of the structure should be populated with the maximum
+ *       number of devices that the application wishes to request in the whitelist.
+ *       If the number of bonded devices is less than requested, the fields are updated with that number of devices.
+ *       If the number of devices are more than requested, the module will populate the list
+ *       with devices in the order the bond was established with the peer devices. Also, if this routine is
+ *       called when a connection exists with one or more peer devices,
+ *       those connected devices are not added to the whitelist.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle or p_whitelist is NULL.
+ */
+ret_code_t dm_whitelist_create(dm_application_instance_t const * p_handle,
+                               ble_gap_whitelist_t             * p_whitelist);
+
+/** @} */
+
+
+/**
+ * @defgroup dm_cntxt_mgmt_api Context Management APIs
+ *
+ * @brief Utility APIs offered by the device manager to get information about the peer if and
+ *        when needed.
+ *
+ * @details This group of API allow the application to access information that is not required to be
+ *          maintained by the application but may be needed. Hence it is possible to get the
+ *          information from the module instead of mapping all the information with a device
+ *          context.
+ * @{
+ */
+
+ret_code_t dm_device_add(dm_handle_t               * p_handle,
+                         dm_device_context_t const * p_context);
+
+/**
+ * @brief Function for deleting a peer device context and all related information from the database.
+ *
+ * @details Delete peer device context and all related information from database. If
+ *          this API returns NRF_SUCCESS, DM_EVT_DEVICE_CONTEXT_DELETED event is notified to the
+ *          application. Event result notified along with the event indicates success or failure
+ *          of this procedure.
+ *
+ * @param[in] p_handle Identifies the peer device to be deleted.
+ *
+ * @retval NRF_SUCCESS             on success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE In the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
+ *
+ * @note Deleting device context results in deleting service and application context for the
+ *       bonded device. The respective events DM_EVT_SERVICE_CONTEXT_DELETED and
+ *       DM_EVT_APPL_CONTEXT_DELETED are not notified to the application.
+ */
+ret_code_t dm_device_delete(dm_handle_t const * p_handle);
+
+/**
+ * @brief Function for deleting all peer device context and all related information from the database.
+ *
+ * @details Delete peer device context and all related information from database. If
+ *          this API returns NRF_SUCCESS, DM_EVT_DEVICE_CONTEXT_DELETED event is notified to the
+ *          application for each device that is deleted from the data base. Event result
+ *          notified along with the event indicates success or failure of this procedure.
+ *
+ * @param[in] p_handle Identifies application instance that is requesting
+ *                     the deletion of all bonded devices.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
+ *
+ * @note Deleting device context results in deleting both service and application context for the
+ *       bonded device. The respective events DM_EVT_SERVICE_CONTEXT_DELETED and
+ *       DM_EVT_APPL_CONTEXT_DELETED are not notified to the application.
+ */
+ret_code_t dm_device_delete_all(dm_application_instance_t const * p_handle);
+
+/**
+ * @brief Function for setting Service Context for a peer device identified by 'p_handle' parameter.
+ *
+ * @details This API allows application to Set Service Context for a peer device identified by the
+ *          'p_handle' parameter. This API is useful when the Service Context cannot be requested
+ *          from the SoftDevice, but needs to be assembled by the application or an another module.
+ *          (or when service context is exchanged in an out of band way.)
+ *          This API could also be used to trigger a storing of service context into persistent
+ *          memory. If this is desired, a NULL pointer could be passed to the p_context.
+ *
+ * @param[in] p_handle  Identifies peer device for which the procedure is requested.
+ * @param[in] p_context Service context being set. The context information includes length of
+ *                      data and pointer to the contextual data being set. The memory pointed to by
+ *                      the pointer to data is assumed to be resident when API is being called and
+ *                      can be freed or reused once the set procedure is complete. Set procedure
+ *                      completion is indicated by the event \ref DM_EVT_SERVICE_CONTEXT_STORED.
+ *                      The Event result is notified along with the event and indicates success or failure of
+ *                      this procedure.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
+ */
+ret_code_t dm_service_context_set(dm_handle_t const          * p_handle,
+                                  dm_service_context_t const * p_context);
+
+/**
+ * @brief Function for getting Service Context for a peer device identified by 'p_handle' parameter.
+ *
+ * @details Get Service Context for a peer device identified by the 'p_handle' parameter. If
+ *          this API returns NRF_SUCCESS, DM_EVT_SERVICE_CONTEXT_LOADED event is notified to the
+ *          application. The event result is notified along with the event indicates success or failure
+ *          of this procedure.
+ *
+ * @param[in] p_handle  Identifies peer device for which procedure is requested.
+ * @param[in] p_context Application context being requested. The context information includes length
+ *                      of the data and a pointer to the data. Note that requesting a 'get'
+ *                      of application does not need to provide memory, the pointer to data will be
+ *                      pointing to service data and hence no data movement is involved.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE In case API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
+ */
+ret_code_t dm_service_context_get(dm_handle_t const    * p_handle,
+                                  dm_service_context_t * p_context);
+
+/**
+ * @brief Function for deleting a Service Context for a peer device identified by the 'p_handle' parameter.
+ *
+ * @details This API allows application to delete a Service Context identified for a peer device
+ *          identified by the 'p_handle' parameter. If this API returns NRF_SUCCESS,
+ *          DM_EVT_SERVICE_CONTEXT_DELETED event is notified to the application.
+ *          Event result is notified along with the event and indicates success or failure of this
+ *          procedure.
+ *
+ * @param[in] p_handle Identifies peer device for which procedure is requested.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
+ */
+ret_code_t dm_service_context_delete(dm_handle_t const * p_handle);
+
+/**
+ * @brief Function for setting Application Context for a peer device identified by the 'p_handle' parameter.
+ *
+ * @details This application allows the setting of the application context for the peer device identified by
+ *          the 'p_handle'. Application context is stored persistently by the module and can be
+ *          requested by the application at any time using the \ref dm_application_context_get
+ *          API. Note that this procedure is permitted only for bonded devices. If the
+ *          device is not bonded, application context cannot be set. However, it is not mandatory
+ *          that the bonded device is connected when requesting this procedure.
+ *
+ * @param[in] p_handle  Identifies peer device for which procedure is requested.
+ *
+ * @param[in] p_context Application context being set. The context information includes length of the
+ *                      data and pointer to the contextual data being set. The memory pointed to by
+ *                      the data pointer is assumed to be resident when API is being called and
+ *                      can be freed or reused once the set procedure is complete. Set procedure
+ *                      completion is notified by the event \ref DM_EVT_APPL_CONTEXT_STORED.
+ *                      The event result is notified along with the event and indicates success or
+ *                      failure of this procedure.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle and/or p_context is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
+ *
+ * @note The API returns FEATURE_NOT_ENABLED in case DEVICE_MANAGER_APP_CONTEXT_SIZE is set to zero.
+ */
+ret_code_t dm_application_context_set(dm_handle_t const              * p_handle,
+                                      dm_application_context_t const * p_context);
+
+/**
+ * @brief Function for getting Application Context for a peer device identified by the 'p_handle' parameter.
+ *
+ * @details Get Application Context for a peer device identified by the 'p_handle' parameter. If
+ *          this API returns NRF_SUCCESS, DM_EVT_APPL_CONTEXT_LOADED event is notified to the
+ *          application. Event result notified along with the event indicates success or failure
+ *          of this procedure.
+ *
+ * @param[in] p_handle  Identifies peer device for which procedure is requested.
+ * @param[in] p_context Application context being requested. The context information includes
+ *                      length of data and pointer to the contextual data is provided.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle and/or p_context is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
+ * @retval DM_NO_APP_CONTEXT       If no application context was set that can be fetched.
+ *
+ * @note The API returns FEATURE_NOT_ENABLED in case DEVICE_MANAGER_APP_CONTEXT_SIZE is set to
+ *       zero.
+ */
+ret_code_t dm_application_context_get(dm_handle_t const        * p_handle,
+                                      dm_application_context_t * p_context);
+
+/**
+ * @brief Function for deleting Application Context for a peer device identified by the 'p_handle' parameter.
+ *
+ * @details Delete Application Context for a peer device identified by the 'p_handle' parameter. If
+ *          this API returns NRF_SUCCESS, DM_EVT_APPL_CONTEXT_DELETED event is notified to the
+ *          application. The event result notified along with the event and indicates success or failure
+ *          of this procedure.
+ *
+ * @param[in] p_handle Identifies peer device for which procedure is requested.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If the p_handle is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If peer is not identified the handle provided by the application.
+ * @retval DM_NO_APP_CONTEXT       If no application context was set that can be deleted.
+ *
+ * @note The API returns FEATURE_NOT_ENABLED if the DEVICE_MANAGER_APP_CONTEXT_SIZE is set to zero.
+ */
+ret_code_t dm_application_context_delete(dm_handle_t const * p_handle);
+
+/** @} */
+
+
+/**
+ * @defgroup utility_api Utility APIs
+ * @{
+ * @brief This section describes the utility APIs offered by the module.
+ *
+ * @details APIs defined in this section are utility or assisting/helper APIs.
+ */
+/**
+ * @brief Function for Setting/Copying Application instance to Device Manager handle.
+ *
+ * @param[in]  p_appl_instance Application instance to be set.
+ * @param[out] p_handle        Device Manager handle for which the instance is to be copied.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle and/or p_addr is NULL.
+ */
+ret_code_t dm_application_instance_set(dm_application_instance_t const * p_appl_instance,
+                                       dm_handle_t                     * p_handle);
+
+/**
+ * @brief Function for getting a peer's device address.
+ *
+ * @param[in]  p_handle Identifies the peer device whose address is requested. Can not be NULL.
+ * @param[out] p_addr   Pointer where address is to be copied. Can not be NULL.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle and/or p_addr is NULL.
+ * @retval NRF_ERROR_NOT_FOUND     If the peer could not be identified.
+ */
+ret_code_t dm_peer_addr_get(dm_handle_t const * p_handle,
+                            ble_gap_addr_t    * p_addr);
+
+/**
+ * @brief Function for setting/updating a peer's device address.
+ *
+ * @param[in]  p_handle Identifies the peer device whose address is requested to be set/updated.
+ * @param[out] p_addr   Address to be set/updated.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If p_handle and/or p_addr is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
+ * @retval NRF_ERROR_INVALID_PARAM If this procedure is requested while connected to the peer or if the address
+ *                                 type was set to BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE.
+ *
+ * @note Setting or updating a peer's device address is permitted
+ *       only for a peer that is bonded and disconnected.
+ * @note Updated address is reflected only after DM_EVT_DEVICE_CONTEXT_STORED is notified to the
+ *       application for this bonded device instance. In order to avoid abnormal behaviour, it is
+ *       recommended to not invite/initiate connections on the updated address unless this event
+ *       has been notified.
+ */
+ret_code_t dm_peer_addr_set(dm_handle_t const    * p_handle,
+                            ble_gap_addr_t const * p_addr);
+
+/**
+ * @brief Function for initializing Device Manager handle.
+ *
+ * @param[in] p_handle Device Manager handle to be initialized.
+ *
+ * @retval NRF_SUCCESS    On success.
+ * @retval NRF_ERROR_NULL If p_handle is NULL.
+ *
+ * @note This routine is permitted before initialization of the module.
+ */
+ret_code_t dm_handle_initialize(dm_handle_t * p_handle);
+
+/**
+ * @brief Function for getting distributed keys for a device.
+ *
+ * @param[in]  p_handle   Device Manager handle identifying the peer.
+ * @param[out] p_key_dist Pointer to distributed keys.
+ *
+ * @retval NRF_SUCCESS             On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_INVALID_STATE If the API is called without module initialization and/or
+ *                                 application registration.
+ * @retval NRF_ERROR_NULL          If the p_handle and/or p_key_dist pointer is NULL.
+ * @retval NRF_ERROR_INVALID_ADDR  If the peer is not identified by the handle provided by the application.
+ */
+ret_code_t dm_distributed_keys_get(dm_handle_t const * p_handle,
+                                   dm_sec_keyset_t   * p_key_dist);
+
+/**
+ * @brief Function for getting the corresponding dm_handle_t based on the connection handle.
+ *
+ * @param[in]     conn_handle Connection handle as provided by the SoftDevice.
+ * @param[in,out] p_handle    Pointer to the p_handle containg the application instance for the
+ *                            registered application. If the application instance is valid then
+ *                            the p_handle will be filled with requested data.
+ *
+ * @retval NRF_SUCCESS          On success, else an error code indicating reason for failure.
+ * @retval NRF_ERROR_NULL       If the p_handle pointer is NULL.
+ * @retval NRF_ERROR_NOT_FOUND  If no p_handle is found for the provided connection handle.
+ */
+ret_code_t dm_handle_get(uint16_t conn_handle, dm_handle_t * p_handle);
+
+/** @} */
+/** @} */
+/** @} */
+#endif // DEVICE_MANAGER_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager_peripheral.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager_peripheral.c
new file mode 100644
index 0000000000..0302e2ff9e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/device_manager/device_manager_peripheral.c
@@ -0,0 +1,2971 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "device_manager.h"
+#include "app_trace.h"
+#include "pstorage.h"
+#include "nrf_ble_hci.h"
+#include "app_error.h"
+
+#if defined ( __CC_ARM )
+    #ifndef __ALIGN
+        #define __ALIGN(x)      __align(x)                  /**< Forced aligment keyword for ARM Compiler */
+    #endif
+#elif defined ( __ICCARM__ )
+    #ifndef __ALIGN
+        #define __ALIGN(x)                                  /**< Forced aligment keyword for IAR Compiler */
+    #endif
+#elif defined   ( __GNUC__ )
+    #ifndef __ALIGN
+        #define __ALIGN(x)      __attribute__((aligned(x))) /**< Forced aligment keyword for GNU Compiler */
+    #endif
+#endif
+
+#define INVALID_ADDR_TYPE 0xFF   /**< Identifier for an invalid address type. */
+#define EDIV_INIT_VAL     0xFFFF /**< Initial value for diversifier. */
+
+/**
+ * @defgroup device_manager_app_states Connection Manager Application States
+ * @{
+ */
+#define STATE_CONTROL_PROCEDURE_IN_PROGRESS 0x01 /**< State where a security procedure is ongoing. */
+#define STATE_QUEUED_CONTROL_REQUEST        0x02 /**< State where it is known if there is any queued security request or not. */
+/** @} */
+
+/**
+ * @defgroup device_manager_conn_inst_states Connection Manager Connection Instances States.
+ * @{
+ */
+#define STATE_IDLE             0x01 /**< State where connection instance is free. */
+#define STATE_CONNECTED        0x02 /**< State where connection is successfully established. */
+#define STATE_PAIRING          0x04 /**< State where pairing procedure is in progress. This state is used for pairing and bonding, as pairing is needed for both. */
+#define STATE_BONDED           0x08 /**< State where device is bonded. */
+#define STATE_DISCONNECTING    0x10 /**< State where disconnection is in progress, application will be notified first, but no further active procedures on the link. */
+#define STATE_PAIRING_PENDING  0x20 /**< State where pairing request is pending on the link. */
+#define STATE_BOND_INFO_UPDATE 0x40 /**< State where information has been updated, update the flash. */
+#define STATE_LINK_ENCRYPTED   0x80 /**< State where link is encrypted. */
+/** @} */
+
+/**
+ * @defgroup device_manager_peer_id_defines Peer Identification Information Defines.
+ *
+ * @brief These defines are used to know which of the peer identification is applicable for a peer.
+ *
+ * @details These defines are used for peer identification. Here, bit map is used because it is
+ *          possible that the application has both IRK and address for identification.
+ * @{
+ */
+#define UNASSIGNED            0xFF /**< Peer instance is unassigned/unused. */
+#define IRK_ENTRY             0x01 /**< Peer instance has IRK as identification information. */
+#define ADDR_ENTRY            0x02 /**< Peer instance has address as identification information. */
+#define SERVICE_CONTEXT_ENTRY 0x04 /**< Peer instance has service context set. */
+#define APP_CONTEXT_ENTRY     0x08 /**< Peer instance has an application context set. */
+/** @} */
+
+/**@brief Device store state identifiers. */
+typedef enum
+{
+    STORE_ALL_CONTEXT, /**< Store all context. */
+    FIRST_BOND_STORE,  /**< Store bond. */
+    UPDATE_PEER_ADDR   /**< Update peer address. */
+} device_store_state_t;
+
+/**
+ * @defgroup device_manager_context_offsets Context Offsets
+ * @{
+ *
+ * @brief Context offsets each of the context information in persistent memory.
+ *
+ * @details Below is a layout showing how each how the context information is stored in persistent
+ *          memory.
+ *
+ * All Device context is stored in the flash as follows:
+ * +---------+---------+---------+------------------+----------------+--------------------+
+ * | Block / Device ID + Layout of stored information in storage block                    |
+ * +---------+---------+---------+------------------+----------------+--------------------+
+ * | Block 0 | Device 0| Peer Id | Bond Information | Service Context| Application Context|
+ * +---------+---------+---------+------------------+----------------+--------------------+
+ * | Block 1 | Device 1| Peer Id | Bond Information | Service Context| Application Context|
+ * +---------+---------+---------+------------------+----------------+--------------------+
+ * |  ...              | ....                                                             |
+ * +---------+---------+---------+------------------+----------------+--------------------+
+ * | Block N | Device N| Peer Id | Bond Information | Service Context| Application Context|
+ * +---------+---------+---------+------------------+----------------+--------------------+
+ *
+ * The following defines are used to get offset of each of the components within a block.
+ */
+
+#define PEER_ID_STORAGE_OFFSET     0                                               /**< Offset at which peer id is stored in the block. */
+#define BOND_STORAGE_OFFSET        PEER_ID_SIZE                                    /**< Offset at which bond information is stored in the block. */
+#define SERVICE_STORAGE_OFFSET     (BOND_STORAGE_OFFSET + BOND_SIZE)               /**< Offset at which service context is stored in the block. */
+#define APP_CONTEXT_STORAGE_OFFSET (SERVICE_STORAGE_OFFSET + SERVICE_CONTEXT_SIZE) /**< Offset at which application context is stored in the block. */
+/** @} */
+
+/**
+ * @defgroup device_manager_context_size Context size.
+ * @{
+ *
+ * @brief This group defines the size of each of the context information.
+ */
+#define PEER_ID_SIZE               (sizeof(peer_id_t))                                             /**< Size of peer identification information. */
+#define BOND_SIZE                  (sizeof(bond_context_t))                                        /**< Size of bond information. */
+#define DEVICE_CONTEXT_SIZE        (PEER_ID_SIZE + BOND_SIZE)                                      /**< Size of Device context, include peer identification and bond information. */
+#define GATTS_SERVICE_CONTEXT_SIZE (sizeof(dm_gatts_context_t))                                    /**< Size of GATTS service context. */
+#define GATTC_SERVICE_CONTEXT_SIZE (sizeof(dm_gatt_client_context_t))                              /**< Size of GATTC service context. */
+#define SERVICE_CONTEXT_SIZE       (GATTS_SERVICE_CONTEXT_SIZE + GATTC_SERVICE_CONTEXT_SIZE)       /**< Combined size of GATTS and GATTC service contexts. */
+#define APP_CONTEXT_MIN_SIZE       4                                                               /**< Minimum size for application context data. */
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+#define APP_CONTEXT_SIZE           (sizeof(uint32_t) + DEVICE_MANAGER_APP_CONTEXT_SIZE)            /**< Size of application context including length field. */
+#else //DEVICE_MANAGER_APP_CONTEXT_SIZE
+#define APP_CONTEXT_SIZE           0                                                               /**< Size of application context. */
+#endif // DEVICE_MANAGER_APP_CONTEXT_SIZE
+#define ALL_CONTEXT_SIZE           (DEVICE_CONTEXT_SIZE + SERVICE_CONTEXT_SIZE + APP_CONTEXT_SIZE) /**< Size of all contexts. */
+/** @} */
+
+
+/**
+ * @defgroup device_manager_log Module's Log Macros
+ *
+ * @details Macros used for creating module logs which can be useful in understanding handling
+ *          of events or actions on API requests. These are intended for debugging purposes and
+ *          can be disabled by defining the DM_DISABLE_LOGS.
+ *
+ * @note That if ENABLE_DEBUG_LOG_SUPPORT is disabled, having DM_DISABLE_LOGS has no effect.
+ * @{
+ */
+#define nDM_DISABLE_LOGS        /**< Enable this macro to disable any logs from this module. */
+
+#ifndef DM_DISABLE_LOGS
+#define DM_LOG  app_trace_log  /**< Used for logging details. */
+#define DM_ERR  app_trace_log  /**< Used for logging errors in the module. */
+#define DM_TRC  app_trace_log  /**< Used for getting trace of execution in the module. */
+#define DM_DUMP app_trace_dump /**< Used for dumping octet information to get details of bond information etc. */
+#else //DM_DISABLE_LOGS
+#define DM_DUMP(...)           /**< Disables dumping of octet streams. */
+#define DM_LOG(...)            /**< Disables detailed logs. */
+#define DM_ERR(...)            /**< Disables error logs. */
+#define DM_TRC(...)            /**< Disables traces. */
+#endif //DM_DISABLE_LOGS
+/** @} */
+
+/**
+ * @defgroup device_manager_mutex_lock_unlock Module's Mutex Lock/Unlock Macros.
+ *
+ * @details Macros used to lock and unlock modules. Currently the SDK does not use mutexes but
+ *          framework is provided in case need arises to use an alternative architecture.
+ * @{
+ */
+#define DM_MUTEX_LOCK()   SDK_MUTEX_LOCK(m_dm_mutex)   /**< Lock module using mutex. */
+#define DM_MUTEX_UNLOCK() SDK_MUTEX_UNLOCK(m_dm_mutex) /**< Unlock module using mutex. */
+/** @} */
+
+
+/**
+ * @defgroup device_manager_misc_defines Miscellaneous defines used across the module.
+ * @{
+ */
+#define DM_GATT_ATTR_SIZE            6                                                   /**< Size of each GATT attribute to be stored persistently. */
+#define DM_GATT_SERVER_ATTR_MAX_SIZE ((DM_GATT_ATTR_SIZE * DM_GATT_CCCD_COUNT) + 2) /**< Maximum size of GATT attributes to be stored.*/
+#define DM_SERVICE_CONTEXT_COUNT     (DM_PROTOCOL_CNTXT_ALL + 1)                         /**< Maximum number of service contexts. */
+#define DM_EVT_DEVICE_CONTEXT_BASE   0x20                                                /**< Base for device context base. */
+#define DM_EVT_SERVICE_CONTEXT_BASE  0x30                                                /**< Base for service context base. */
+#define DM_EVT_APP_CONTEXT_BASE      0x40                                                /**< Base for application context base. */
+#define DM_LOAD_OPERATION_ID         0x01                                                /**< Load operation identifier. */
+#define DM_STORE_OPERATION_ID        0x02                                                /**< Store operation identifier. */
+#define DM_CLEAR_OPERATION_ID        0x03                                                /**< Clear operation identifier. */
+/** @} */
+
+#define DM_GATTS_INVALID_SIZE        0xFFFFFFFF                                     /**< Identifer for GATTS invalid size. */
+
+/**
+ * @defgroup api_param_check API Parameters check macros.
+ *
+ * @details Macros for verifying parameters passed to the module in the APIs. These macros
+ *          could be mapped to nothing in the final version of the code in order to save execution
+ *          time and program size.
+ * @{
+ */
+
+//#define DM_DISABLE_API_PARAM_CHECK /**< Macro to disable API parameters check. */
+
+#undef NULL_PARAM_CHECK
+#undef VERIFY_MODULE_INITIALIZED
+#undef VERIFY_MODULE_INITIALIZED_VOID
+#undef VERIFY_APP_REGISTERED
+#undef VERIFY_APP_REGISTERED_VOID
+#undef VERIFY_CONNECTION_INSTANCE
+#undef VERIFY_DEVICE_INSTANCE
+
+#ifndef DM_DISABLE_API_PARAM_CHECK
+
+/**@brief Macro for verifying NULL parameters are not passed to API.
+ *
+ * @param[in] PARAM Parameter checked for NULL.
+ *
+ * @retval (NRF_ERROR_NULL | DEVICE_MANAGER_ERR_BASE) when @ref PARAM is NULL.
+ */
+#define NULL_PARAM_CHECK(PARAM)                            \
+    if ((PARAM) == NULL)                                   \
+    {                                                      \
+        return (NRF_ERROR_NULL | DEVICE_MANAGER_ERR_BASE); \
+    }
+/**@} */
+
+
+/**@brief Macro for verifying module's initialization status.
+ *
+ * @retval (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE) when module is not initialized.
+ */
+#define VERIFY_MODULE_INITIALIZED()                                     \
+    do                                                                  \
+    {                                                                   \
+        if (!m_module_initialized)                                      \
+        {                                                               \
+            return (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE); \
+        }                                                               \
+    } while (0)
+
+
+/**@brief Macro for verifying module's initialization status. Returns in case it is not initialized.
+ */
+#define VERIFY_MODULE_INITIALIZED_VOID() \
+    do                                   \
+    {                                    \
+        if (!m_module_initialized)       \
+        {                                \
+            return;                      \
+        }                                \
+    } while (0)
+
+
+/**@brief Macro for verifying that the application is registered.
+ *
+ * @param[in] X Application instance identifier.
+ *
+ * @retval (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE) when module API is called without
+ *         registering an application with the module.
+ */
+#define VERIFY_APP_REGISTERED(X)                                        \
+    do                                                                  \
+    {                                                                   \
+        if (((X) >= DEVICE_MANAGER_MAX_APPLICATIONS) ||                 \
+            (m_application_table[(X)].ntf_cb == NULL))                  \
+        {                                                               \
+            return (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE); \
+        }                                                               \
+    } while (0)
+
+
+/**@brief Macro for verifying that the application is registered. Returns in case it is not
+ *        registered.
+ *
+ * @param[in] X Application instance identifier.
+ */
+#define VERIFY_APP_REGISTERED_VOID(X)                   \
+    do                                                  \
+    {                                                   \
+        if (((X) >= DEVICE_MANAGER_MAX_APPLICATIONS) || \
+            (m_application_table[(X)].ntf_cb == NULL))  \
+        {                                               \
+            return;                                     \
+        }                                               \
+    } while (0)
+
+
+/**@brief Macro for verifying connection instance is allocated.
+ *
+ * @param[in] X Connection instance identifier.
+ *
+ * @retval (NRF_ERROR_INVALID_ADDR | DEVICE_MANAGER_ERR_BASE) when connection instance is not
+ *         allocated.
+ */
+#define VERIFY_CONNECTION_INSTANCE(X)                                  \
+    do                                                                 \
+    {                                                                  \
+        if (((X) >= DEVICE_MANAGER_MAX_CONNECTIONS) ||                 \
+            (m_connection_table[(X)].state == STATE_IDLE))             \
+        {                                                              \
+            return (NRF_ERROR_INVALID_ADDR | DEVICE_MANAGER_ERR_BASE); \
+        }                                                              \
+    } while (0)
+
+
+/**@brief Macro for verifying if device instance is allocated.
+ *
+ * @param[in] X Device instance identifier.
+ *
+ * @retval (NRF_ERROR_INVALID_ADDR | DEVICE_MANAGER_ERR_BASE) when device instance is not allocated.
+ */
+#define VERIFY_DEVICE_INSTANCE(X)                                      \
+    do                                                                 \
+    {                                                                  \
+        if (((X) >= DEVICE_MANAGER_MAX_BONDS) ||                       \
+            (m_peer_table[(X)].id_bitmap == UNASSIGNED))               \
+        {                                                              \
+            return (NRF_ERROR_INVALID_ADDR | DEVICE_MANAGER_ERR_BASE); \
+        }                                                              \
+    } while (0)
+
+/**@brief Macro for verifying if device is bonded and thus can store data persistantly.
+ *
+ * @param[in] X Connection instance identifier.
+ *
+ * @retval (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE) when device is not bonded.
+ */
+#define VERIFY_DEVICE_BOND(X)                                              \
+    do                                                                     \
+    {                                                                      \
+        if ((m_connection_table[(X)].state & STATE_BONDED) != STATE_BONDED)\
+        {                                                                  \
+            return (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE);    \
+        }                                                                  \
+    } while (0)
+#else
+#define NULL_PARAM_CHECK(X)
+#define VERIFY_MODULE_INITIALIZED()
+#define VERIFY_MODULE_INITIALIZED_VOID()
+#define VERIFY_APP_REGISTERED(X)
+#define VERIFY_APP_REGISTERED_VOID(X)
+#define VERIFY_CONNECTION_INSTANCE(X)
+#define VERIFY_DEVICE_INSTANCE(X)
+#endif //DM_DISABLE_API_PARAM_CHECK
+/** @} */
+
+#define INVALID_CONTEXT_LEN 0xFFFFFFFF /**< Identifier for invalid context length. */
+/**@brief Macro for checking that application context size is greater that minimal size.
+ *
+ * @param[in] X Size of application context.
+ *
+ * @retval (NRF_ERROR_INVALID_PARAM) when size is smaller than minimun required size.
+ */
+#define SIZE_CHECK_APP_CONTEXT(X)                                      \
+    if ((X) < (APP_CONTEXT_MIN_SIZE))                                  \
+    {                                                                  \
+        return NRF_ERROR_INVALID_PARAM;                                \
+    }
+
+
+/**
+ * @defgroup dm_data_types Module's internal data types.
+ *
+ * @brief This section describes a module's internal data structures.
+ * @{
+ */
+/**@brief Peer identification information.
+ */
+typedef struct
+{
+    ble_gap_id_key_t peer_id;   /**< IRK and/or address of peer. */
+    uint16_t         ediv;      /**< Peer's encrypted diversifier. */
+    uint8_t          id_bitmap; /**< Contains information if above field is valid. */
+} peer_id_t;
+
+STATIC_ASSERT(sizeof(peer_id_t) % 4 == 0); /**< Check to ensure Peer identification information is a multiple of 4. */
+
+/**@brief Portion of bonding information exchanged by a device during bond creation that needs to
+ *        be stored persistently.
+ *
+ * @note  An entry is not made in this table unless device is bonded.
+ */
+typedef struct
+{
+    ble_gap_enc_key_t peer_enc_key; /**< Local LTK info, central IRK and address */
+} bond_context_t;
+
+STATIC_ASSERT(sizeof(bond_context_t) % 4 == 0); /**< Check to ensure bond information is a multiple of 4. */
+
+/**@brief GATT Server Attributes size and data.
+ */
+typedef struct
+{
+    uint32_t flags;                                    /**< Flags identifying the stored attributes. */
+    uint32_t size;                                     /**< Size of stored attributes. */
+    uint8_t  attributes[DM_GATT_SERVER_ATTR_MAX_SIZE]; /**< Array to hold the server attributes. */
+} dm_gatts_context_t;
+
+STATIC_ASSERT(sizeof(dm_gatts_context_t) % 4 == 0); /**< Check to ensure GATT Server Attributes size and data information is a multiple of 4. */
+
+/**@brief GATT Client context information. Placeholder for now.
+ */
+typedef struct
+{
+    void * p_dummy; /**< Placeholder, currently unused. */
+} dm_gatt_client_context_t;
+
+STATIC_ASSERT(sizeof(dm_gatt_client_context_t) % 4 == 0);  /**< Check to ensure GATT Client context information is a multiple of 4. */
+STATIC_ASSERT((DEVICE_MANAGER_APP_CONTEXT_SIZE % 4) == 0); /**< Check to ensure device manager application context information is a multiple of 4. */
+
+/**@brief Connection instance definition. Maintains information with respect to an active peer.
+ */
+typedef struct
+{
+    ble_gap_addr_t peer_addr;     /**< Peer identification information. This information is retained as long as the connection session exists, once disconnected, for non-bonded devices this information is not stored persistently. */
+    uint16_t       conn_handle;   /**< Connection handle for the device. */
+    uint8_t        state;         /**< Link state. */
+    uint8_t        bonded_dev_id; /**< In case the device is bonded, this points to the corresponding bonded device. This index can be used to index service and bond context as well. */
+} connection_instance_t;
+
+/**@brief Application instance definition. Maintains information with respect to a registered
+ *        application.
+ */
+typedef struct
+{
+    dm_event_cb_t        ntf_cb;    /**< Callback registered with the application. */
+    ble_gap_sec_params_t sec_param; /**< Local security parameters registered by the application. */
+    uint8_t              state;     /**< Application state. Currently this is used only for knowing if any security procedure is in progress and/or a security procedure is pending to be requested. */
+    uint8_t              service;   /**< Service registered by the application. */
+} application_instance_t;
+
+/**@brief Function for performing necessary action of storing each of the service context as
+ *        registered by the application.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is stored.
+ *
+ * @retval Operation result code.
+ */
+typedef ret_code_t (* service_context_access_t)(pstorage_handle_t const * p_block_handle,
+                                                dm_handle_t const       * p_handle);
+
+/**@brief Function for performing necessary action of applying the context information.
+ *
+ * @param[in] p_handle Device handle identifying device that is stored.
+ *
+ * @retval Operation result code.
+ */
+typedef ret_code_t (* service_context_apply_t)(dm_handle_t * p_handle);
+
+/**@brief Function for performing necessary functions of storing or updating.
+ *
+ * @param[in] p_dest Destination address where data is stored persistently.
+ * @param[in] p_src  Source address containing data to be stored.
+ * @param[in] size   Size of data to be stored expressed in bytes. Must be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ *
+ * @retval Operation result code.
+ */
+typedef uint32_t (* storage_operation)(pstorage_handle_t * p_dest,
+                                       uint8_t           * p_src,
+                                       pstorage_size_t     size,
+                                       pstorage_size_t     offset);
+/** @} */
+
+/**
+ * @defgroup dm_tables Module's internal tables.
+ *
+ * @brief This section describes the module's internal tables and the static global variables
+ *        needed for its functionality.
+ * @{
+ */
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+static uint8_t * m_app_context_table[DEVICE_MANAGER_MAX_BONDS];                     /**< Table to remember application contexts of bonded devices. */
+#endif //DEVICE_MANAGER_APP_CONTEXT_SIZE
+__ALIGN(sizeof(uint32_t))
+static peer_id_t              m_peer_table[DEVICE_MANAGER_MAX_BONDS] ;              /**< Table to maintain bonded devices' identification information, an instance is allocated in the table when a device is bonded and freed when bond information is deleted. */
+__ALIGN(sizeof(uint32_t))
+static bond_context_t         m_bond_table[DEVICE_MANAGER_MAX_CONNECTIONS];         /**< Table to maintain bond information for active peers. */
+static dm_gatts_context_t     m_gatts_table[DEVICE_MANAGER_MAX_CONNECTIONS];        /**< Table for service information for active connection instances. */
+static connection_instance_t  m_connection_table[DEVICE_MANAGER_MAX_CONNECTIONS];   /**< Table to maintain active peer information. An instance is allocated in the table when a new connection is established and freed on disconnection. */
+static application_instance_t m_application_table[DEVICE_MANAGER_MAX_APPLICATIONS]; /**< Table to maintain application instances. */
+static pstorage_handle_t      m_storage_handle;                                     /**< Persistent storage handle for blocks requested by the module. */
+static uint32_t               m_peer_addr_update;                                   /**< 32-bit bitmap to remember peer device address update. */
+static ble_gap_id_key_t       m_local_id_info;                                      /**< ID information of central in case resolvable address is used. */
+static bool                   m_module_initialized = false;                         /**< State indicating if module is initialized or not. */
+static uint8_t                m_irk_index_table[DEVICE_MANAGER_MAX_BONDS];          /**< List maintaining IRK index list. */
+
+SDK_MUTEX_DEFINE(m_dm_mutex) /**< Mutex variable. Currently unused, this declaration does not occupy any space in RAM. */
+/** @} */
+
+static __INLINE ret_code_t no_service_context_store(pstorage_handle_t const * p_block_handle,
+                                                    dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t gatts_context_store(pstorage_handle_t const * p_block_handle,
+                                               dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t gattc_context_store(pstorage_handle_t const * p_block_handle,
+                                               dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t gattsc_context_store(pstorage_handle_t const * p_block_handle,
+                                                dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t no_service_context_load(pstorage_handle_t const * p_block_handle,
+                                                   dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t gatts_context_load(pstorage_handle_t const * p_block_handle,
+                                              dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t gattc_context_load(pstorage_handle_t const * p_block_handle,
+                                              dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t gattsc_context_load(pstorage_handle_t const * p_block_handle,
+                                               dm_handle_t const       * p_handle);
+
+static __INLINE ret_code_t no_service_context_apply(dm_handle_t * p_handle);
+
+static __INLINE ret_code_t gatts_context_apply(dm_handle_t * p_handle);
+
+static __INLINE ret_code_t gattc_context_apply(dm_handle_t * p_handle);
+
+static __INLINE ret_code_t gattsc_context_apply(dm_handle_t * p_handle);
+
+
+/**< Array of function pointers based on the types of service registered. */
+const service_context_access_t m_service_context_store[DM_SERVICE_CONTEXT_COUNT] =
+{
+    no_service_context_store, /**< Dummy function, when there is no service context registered. */
+    gatts_context_store,      /**< GATT Server context store function. */
+    gattc_context_store,      /**< GATT Client context store function. */
+    gattsc_context_store      /**< GATT Server & Client context store function. */
+};
+
+
+/**< Array of function pointers based on the types of service registered. */
+const service_context_access_t m_service_context_load[DM_SERVICE_CONTEXT_COUNT] =
+{
+    no_service_context_load,  /**< Dummy function, when there is no service context registered. */
+    gatts_context_load,       /**< GATT Server context load function. */
+    gattc_context_load,       /**< GATT Client context load function. */
+    gattsc_context_load       /**< GATT Server & Client context load function. */
+};
+
+
+/**< Array of function pointers based on the types of service registered. */
+const service_context_apply_t m_service_context_apply[DM_SERVICE_CONTEXT_COUNT] =
+{
+    no_service_context_apply, /**< Dummy function, when there is no service context registered. */
+    gatts_context_apply,      /**< GATT Server context apply function. */
+    gattc_context_apply,      /**< GATT Client context apply function. */
+    gattsc_context_apply      /**< GATT Server & Client context apply function. */
+};
+
+
+const uint32_t m_context_init_len = 0xFFFFFFFF; /**< Constant used to update the initial value for context in the flash. */
+
+/**@brief Function for setting update status for the device identified by 'index'.
+ *
+ * @param[in] index Device identifier.
+ */
+static __INLINE void update_status_bit_set(uint32_t index)
+{
+    m_peer_addr_update |= (BIT_0 << index);
+}
+
+
+/**@brief Function for resetting update status for device identified by 'index'.
+ *
+ * @param[in] index Device identifier.
+ */
+static __INLINE void update_status_bit_reset(uint32_t index)
+{
+    m_peer_addr_update &= (~((uint32_t)BIT_0 << index));
+}
+
+
+/**@brief Function for providing update status for the device identified by 'index'.
+ *
+ * @param[in] index Device identifier.
+ *
+ * @retval true if the bit is set, false otherwise.
+ */
+static __INLINE bool update_status_bit_is_set(uint32_t index)
+{
+    return ((m_peer_addr_update & (BIT_0 << index)) ? true : false);
+}
+
+
+/**@brief Function for initialiasing the application instance identified by 'index'.
+ *
+ * @param[in] index Device identifier.
+ */
+static __INLINE void application_instance_init(uint32_t index)
+{
+    DM_TRC("[DM]: Initializing Application Instance 0x%08X.\r\n", index);
+
+    m_application_table[index].ntf_cb  = NULL;
+    m_application_table[index].state   = 0x00;
+    m_application_table[index].service = 0x00;
+}
+
+
+/**@brief Function for initialiasing the connection instance identified by 'index'.
+ *
+ * @param[in] index Device identifier.
+ */
+static __INLINE void connection_instance_init(uint32_t index)
+{
+    DM_TRC("[DM]: Initializing Connection Instance 0x%08X.\r\n", index);
+
+    m_connection_table[index].state         = STATE_IDLE;
+    m_connection_table[index].conn_handle   = BLE_CONN_HANDLE_INVALID;
+    m_connection_table[index].bonded_dev_id = DM_INVALID_ID;
+
+    memset(&m_connection_table[index].peer_addr, 0, sizeof (ble_gap_addr_t));
+}
+
+
+/**@brief Function for initialiasing the peer device instance identified by 'index'.
+ *
+ * @param[in] index Device identifier.
+ */
+static __INLINE void peer_instance_init(uint32_t index)
+{
+    DM_TRC("[DM]: Initializing Peer Instance 0x%08X.\r\n", index);
+
+    memset(m_peer_table[index].peer_id.id_addr_info.addr, 0, BLE_GAP_ADDR_LEN);
+    memset(m_peer_table[index].peer_id.id_info.irk, 0, BLE_GAP_SEC_KEY_LEN);
+
+    //Initialize the address type to invalid.
+    m_peer_table[index].peer_id.id_addr_info.addr_type = INVALID_ADDR_TYPE;
+
+    //Initialize the identification bit map to unassigned.
+    m_peer_table[index].id_bitmap = UNASSIGNED;
+
+    // Initialize diversifier.
+    m_peer_table[index].ediv      = EDIV_INIT_VAL;
+
+
+    //Reset the status bit.
+    update_status_bit_reset(index);
+
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+    //Initialize the application context for bond device.
+    m_app_context_table[index] = NULL;
+#endif //DEVICE_MANAGER_APP_CONTEXT_SIZE
+}
+
+
+/**@brief Function for searching connection instance matching the connection handle and the state
+ *        requested.
+ *
+ * @details Connection handle and state information is used to get a connection instance, it
+ *          is possible to ignore the connection handle by using BLE_CONN_HANDLE_INVALID.
+ *
+ * @param[in]  conn_handle Connection handle.
+ * @param[in]  state       Connection instance state.
+ * @param[out] p_instance  Connection instance.
+ *
+ * @retval NRF_SUCCESS             Operation success.
+ * @retval NRF_ERROR_INVALID_STATE Operation failure. Invalid state
+ * @retval NRF_ERROR_NOT_FOUND     Operation failure. Not found
+ */
+static ret_code_t connection_instance_find(uint16_t   conn_handle,
+                                           uint8_t    state,
+                                           uint32_t * p_instance)
+{
+    ret_code_t err_code;
+    uint32_t   index;
+
+    err_code = NRF_ERROR_INVALID_STATE;
+
+    for (index = 0; index < DEVICE_MANAGER_MAX_CONNECTIONS; index++)
+    {
+        //Search only based on the state.
+        if (state & m_connection_table[index].state)
+        {
+            //Ignore the connection handle.
+            if ((conn_handle == BLE_CONN_HANDLE_INVALID) ||
+                (conn_handle == m_connection_table[index].conn_handle))
+            {
+                //Search for matching connection handle.
+                (*p_instance) = index;
+                err_code      = NRF_SUCCESS;
+
+                break;
+            }
+            else
+            {
+                err_code = NRF_ERROR_NOT_FOUND;
+            }
+        }
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for allocating device instance for a bonded device.
+ *
+ * @param[out] p_device_index Device index.
+ * @param[in]  p_addr         Peer identification information.
+ *
+ * @retval NRF_SUCCESS            Operation success.
+ * @retval DM_DEVICE_CONTEXT_FULL Operation failure.
+ */
+static __INLINE ret_code_t device_instance_allocate(uint8_t *              p_device_index,
+                                                    ble_gap_addr_t const * p_addr)
+{
+    ret_code_t err_code;
+    uint32_t   index;
+
+    err_code = DM_DEVICE_CONTEXT_FULL;
+
+    for (index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+    {
+        DM_TRC("[DM]:[DI 0x%02X]: Device type 0x%02X.\r\n",
+               index, m_peer_table[index].peer_id.id_addr_info.addr_type);
+        DM_TRC("[DM]: Device Addr 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\r\n",
+               m_peer_table[index].peer_id.id_addr_info.addr[0],
+               m_peer_table[index].peer_id.id_addr_info.addr[1],
+               m_peer_table[index].peer_id.id_addr_info.addr[2],
+               m_peer_table[index].peer_id.id_addr_info.addr[3],
+               m_peer_table[index].peer_id.id_addr_info.addr[4],
+               m_peer_table[index].peer_id.id_addr_info.addr[5]);
+
+        if (m_peer_table[index].id_bitmap == UNASSIGNED)
+        {
+            if (p_addr->addr_type != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE)
+            {
+                m_peer_table[index].id_bitmap            &= (~ADDR_ENTRY);
+                m_peer_table[index].peer_id.id_addr_info  = (*p_addr);
+            }
+            else
+            {
+                m_peer_table[index].id_bitmap &= (~IRK_ENTRY);
+            }
+
+            (*p_device_index) = index;
+            err_code          = NRF_SUCCESS;
+
+            DM_LOG("[DM]: Allocated device instance 0x%02X\r\n", index);
+
+            break;
+        }
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for freeing a device instance allocated for bonded device.
+ *
+ * @param[in] device_index Device index.
+ *
+ * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
+ */
+static __INLINE ret_code_t device_instance_free(uint32_t device_index)
+{
+    ret_code_t        err_code;
+    pstorage_handle_t block_handle;
+
+    //Get the block handle.
+    err_code = pstorage_block_identifier_get(&m_storage_handle, device_index, &block_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        DM_TRC("[DM]:[DI 0x%02X]: Freeing Instance.\r\n", device_index);
+
+        //Request clearing of the block.
+        err_code = pstorage_clear(&block_handle, ALL_CONTEXT_SIZE);
+
+        if (err_code == NRF_SUCCESS)
+        {
+            peer_instance_init(device_index);
+        }
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for searching for the device in the bonded device list.
+ *
+ * @param[in]  p_addr         Peer identification information.
+ * @param[out] p_device_index Device index.
+ *
+ * @retval NRF_SUCCESS         Operation success.
+ * @retval NRF_ERROR_NOT_FOUND Operation failure.
+ */
+static ret_code_t device_instance_find(ble_gap_addr_t const * p_addr, uint32_t * p_device_index, uint16_t ediv)
+{
+    ret_code_t err_code;
+    uint32_t   index;
+
+    err_code = NRF_ERROR_NOT_FOUND;
+
+    if (NULL != p_addr)
+    {
+        DM_TRC("[DM]: Searching for device 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\r\n",
+               p_addr->addr[0],
+               p_addr->addr[1],
+               p_addr->addr[2],
+               p_addr->addr[3],
+               p_addr->addr[4],
+               p_addr->addr[5]);
+    }
+
+    for (index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+    {
+        DM_TRC("[DM]:[DI 0x%02X]: Device type 0x%02X.\r\n",
+               index, m_peer_table[index].peer_id.id_addr_info.addr_type);
+        DM_TRC("[DM]: Device Addr 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\r\n",
+               m_peer_table[index].peer_id.id_addr_info.addr[0],
+               m_peer_table[index].peer_id.id_addr_info.addr[1],
+               m_peer_table[index].peer_id.id_addr_info.addr[2],
+               m_peer_table[index].peer_id.id_addr_info.addr[3],
+               m_peer_table[index].peer_id.id_addr_info.addr[4],
+               m_peer_table[index].peer_id.id_addr_info.addr[5]);
+
+        if (((NULL == p_addr) && (ediv == m_peer_table[index].ediv)) ||
+            ((NULL != p_addr) && (memcmp(&m_peer_table[index].peer_id.id_addr_info, p_addr, sizeof(ble_gap_addr_t)) == 0)))
+        {
+            DM_LOG("[DM]: Found device at instance 0x%02X\r\n", index);
+
+            (*p_device_index) = index;
+            err_code          = NRF_SUCCESS;
+
+            break;
+        }
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for notifying connection manager event to the application.
+ *
+ * @param[in] p_handle     Device handle identifying device.
+ * @param[in] p_event      Connection manager event details.
+ * @param[in] event_result Event result code.
+ */
+static __INLINE void app_evt_notify(dm_handle_t const * const p_handle,
+                                    dm_event_t const * const  p_event,
+                                    uint32_t                  event_result)
+{
+    dm_event_cb_t app_cb = m_application_table[0].ntf_cb;
+
+    DM_MUTEX_UNLOCK();
+
+    DM_TRC("[DM]: Notifying application of event 0x%02X\r\n", p_event->event_id);
+
+    //No need to do any kind of return value processing thus can be supressed.
+    UNUSED_VARIABLE(app_cb(p_handle, p_event, event_result));
+
+    DM_MUTEX_LOCK();
+}
+
+
+/**@brief Function for allocating instance.
+ *
+ * @details The instance identifier is provided in the 'p_instance' parameter if the routine
+ *          succeeds.
+ *
+ * @param[out] p_instance Connection instance.
+ *
+ * @retval NRF_SUCCESS      Operation success.
+ * @retval NRF_ERROR_NO_MEM Operation failure. No memory.
+ */
+static __INLINE uint32_t connection_instance_allocate(uint32_t * p_instance)
+{
+    uint32_t err_code;
+
+    DM_TRC("[DM]: Request to allocation connection instance\r\n");
+
+    err_code = connection_instance_find(BLE_CONN_HANDLE_INVALID, STATE_IDLE, p_instance);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        DM_LOG("[DM]:[%02X]: Connection Instance Allocated.\r\n", (*p_instance));
+        m_connection_table[*p_instance].state = STATE_CONNECTED;
+    }
+    else
+    {
+        DM_LOG("[DM]: No free connection instances available\r\n");
+        err_code = NRF_ERROR_NO_MEM;
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for freeing instance. Instance identifier is provided in the parameter
+ *        'p_instance' in case the routine succeeds.
+ *
+ * @param[in] p_instance Connection instance.
+ */
+static __INLINE void connection_instance_free(uint32_t const * p_instance)
+{
+    DM_TRC("[DM]:[CI 0x%02X]: Freeing connection instance\r\n", (*p_instance));
+
+    if (m_connection_table[*p_instance].state != STATE_IDLE)
+    {
+        DM_LOG("[DM]:[%02X]: Freed connection instance.\r\n", (*p_instance));
+        connection_instance_init(*p_instance);
+    }
+}
+
+
+/**@brief Function for storage operation dummy handler.
+ *
+ * @param[in] p_dest Destination address where data is to be stored persistently.
+ * @param[in] p_src  Source address containing data to be stored. API assumes this to be resident
+ *                   memory and no intermediate copy of data is made by the API.
+ * @param[in] size   Size of data to be stored expressed in bytes. Should be word aligned.
+ * @param[in] offset Offset in bytes to be applied when writing to the block.
+ *                   For example, if within a block of 100 bytes, application wishes to
+ *                   write 20 bytes at offset of 12, then this field should be set to 12.
+ *                   Should be word aligned.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+static uint32_t storage_operation_dummy_handler(pstorage_handle_t * p_dest,
+                                                uint8_t           * p_src,
+                                                pstorage_size_t     size,
+                                                pstorage_size_t     offset)
+{
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for saving the device context persistently.
+ *
+ * @param[in] p_handle Device handle identifying device.
+ * @param[in] state    Device store state.
+ */
+static __INLINE void device_context_store(dm_handle_t const * p_handle, device_store_state_t state)
+{
+    pstorage_handle_t block_handle;
+    storage_operation store_fn;
+    ret_code_t        err_code;
+
+    DM_LOG("[DM]: --> device_context_store\r\n");
+
+    err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                             p_handle->device_id,
+                                             &block_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        if ((STATE_BOND_INFO_UPDATE ==
+             (m_connection_table[p_handle->connection_id].state & STATE_BOND_INFO_UPDATE)) ||
+            (state == UPDATE_PEER_ADDR))
+        {
+            DM_LOG("[DM]:[DI %02X]:[CI %02X]: -> Updating bonding information.\r\n",
+                   p_handle->device_id, p_handle->connection_id);
+
+            store_fn = pstorage_update;
+        }
+        else if (state == FIRST_BOND_STORE)
+        {
+            DM_LOG("[DM]:[DI %02X]:[CI %02X]: -> Storing bonding information.\r\n",
+                   p_handle->device_id, p_handle->connection_id);
+
+            store_fn = pstorage_store;
+        }
+        else
+        {
+            DM_LOG("[DM]:[DI %02X]:[CI %02X]: -> No update in bonding information.\r\n",
+                   p_handle->device_id, p_handle->connection_id);
+
+            //No operation needed.
+            store_fn = storage_operation_dummy_handler;
+        }
+
+        //Store the peer id.
+        err_code = store_fn(&block_handle,
+                            (uint8_t *)&m_peer_table[p_handle->device_id],
+                            PEER_ID_SIZE,
+                            PEER_ID_STORAGE_OFFSET);
+
+        if ((err_code == NRF_SUCCESS) && (state != UPDATE_PEER_ADDR))
+        {
+            m_connection_table[p_handle->connection_id].state &= (~STATE_BOND_INFO_UPDATE);
+
+            //Store the bond information.
+            err_code = store_fn(&block_handle,
+                                (uint8_t *)&m_bond_table[p_handle->connection_id],
+                                BOND_SIZE,
+                                BOND_STORAGE_OFFSET);
+
+            if (err_code != NRF_SUCCESS)
+            {
+                DM_ERR("[DM]:[0x%02X]:Failed to store bond information, reason 0x%08X\r\n",
+                       p_handle->device_id, err_code);
+            }
+        }
+
+        if (state != UPDATE_PEER_ADDR)
+        {
+            //Store the service information
+            err_code = m_service_context_store[m_application_table[p_handle->appl_id].service]
+                    (
+                        &block_handle,
+                        p_handle
+                    );
+
+            if (err_code != NRF_SUCCESS)
+            {
+                //Notify application of an error event.
+                DM_ERR("[DM]: Failed to store service context, reason %08X\r\n", err_code);
+            }
+        }
+    }
+
+    if (err_code != NRF_SUCCESS)
+    {
+        //Notify application of an error event.
+        DM_ERR("[DM]: Failed to store device context, reason %08X\r\n", err_code);
+    }
+}
+
+
+/**@brief Function for storing when there is no service registered.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is loaded.
+ *
+ * @retval NRF_SUCCESS
+ */
+static __INLINE ret_code_t no_service_context_store(pstorage_handle_t const * p_block_handle,
+                                                    dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]: --> no_service_context_store\r\n");
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for storing GATT Server context.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is stored.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+static __INLINE ret_code_t gatts_context_store(pstorage_handle_t const * p_block_handle,
+                                               dm_handle_t const       * p_handle)
+{
+    storage_operation store_fn;
+    uint32_t          attr_flags = BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS | BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS;
+    uint16_t          attr_len   = DM_GATT_SERVER_ATTR_MAX_SIZE;
+    uint8_t           sys_data[DM_GATT_SERVER_ATTR_MAX_SIZE];
+
+    DM_LOG("[DM]: --> gatts_context_store\r\n");
+
+    uint32_t err_code = sd_ble_gatts_sys_attr_get(
+        m_connection_table[p_handle->connection_id].conn_handle,
+        sys_data,
+        &attr_len,
+        attr_flags);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        if (memcmp(m_gatts_table[p_handle->connection_id].attributes, sys_data, attr_len) == 0)
+        {
+            //No store operation is needed.
+            DM_LOG("[DM]:[0x%02X]: No change in GATTS Context information.\r\n",
+                   p_handle->device_id);
+
+            if ((m_connection_table[p_handle->connection_id].state & STATE_CONNECTED) !=
+                STATE_CONNECTED)
+            {
+                DM_LOG("[DM]:[0x%02X]: Resetting GATTS for active instance.\r\n",
+                       p_handle->connection_id);
+
+                //Reset GATTS information for the current context.
+                memset(&m_gatts_table[p_handle->connection_id], 0, sizeof(dm_gatts_context_t));
+            }
+        }
+        else
+        {
+            if (m_gatts_table[p_handle->connection_id].size != 0)
+            {
+                //There is data already stored in persistent memory, therefore an update is needed.
+                DM_LOG("[DM]:[0x%02X]: Updating stored service context\r\n", p_handle->device_id);
+
+                store_fn = pstorage_update;
+            }
+            else
+            {
+                //Fresh write, a store is needed.
+                DM_LOG("[DM]:[0x%02X]: Storing service context\r\n", p_handle->device_id);
+
+                store_fn = pstorage_store;
+            }
+
+            m_gatts_table[p_handle->connection_id].flags = attr_flags;
+            m_gatts_table[p_handle->connection_id].size  = attr_len;
+            memcpy(m_gatts_table[p_handle->connection_id].attributes, sys_data, attr_len);
+
+            DM_DUMP((uint8_t *)&m_gatts_table[p_handle->connection_id], sizeof(dm_gatts_context_t));
+
+            DM_LOG("[DM]:[0x%02X]: GATTS Data size 0x%08X\r\n",
+                   p_handle->device_id,
+                   m_gatts_table[p_handle->connection_id].size);
+
+            //Store GATTS information.
+            err_code = store_fn((pstorage_handle_t *)p_block_handle,
+                                (uint8_t *)&m_gatts_table[p_handle->connection_id],
+                                GATTS_SERVICE_CONTEXT_SIZE,
+                                SERVICE_STORAGE_OFFSET);
+
+            if (err_code != NRF_SUCCESS)
+            {
+                DM_ERR("[DM]:[0x%02X]:Failed to store service context, reason 0x%08X\r\n",
+                       p_handle->device_id,
+                       err_code);
+            }
+            else
+            {
+                DM_LOG("[DM]: Service context successfully stored.\r\n");
+            }
+        }
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for storing GATT Client context.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is stored.
+ *
+ * @retval NRF_SUCCESS Operation success.
+ */
+static __INLINE ret_code_t gattc_context_store(pstorage_handle_t const * p_block_handle,
+                                               dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]: --> gattc_context_store\r\n");
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for storing GATT Server & Client context.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is stored.
+ *
+ * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
+ */
+static __INLINE ret_code_t gattsc_context_store(pstorage_handle_t const * p_block_handle,
+                                                dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]: --> gattsc_context_store\r\n");
+
+    ret_code_t err_code = gatts_context_store(p_block_handle, p_handle);
+
+    if (NRF_SUCCESS == err_code)
+    {
+        err_code = gattc_context_store(p_block_handle, p_handle);
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for loading when there is no service registered.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is loaded.
+ *
+ * @retval NRF_SUCCESS
+ */
+static __INLINE ret_code_t no_service_context_load(pstorage_handle_t const * p_block_handle,
+                                                   dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]: --> no_service_context_load\r\n");
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for loading GATT Server context.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is loaded.
+ *
+ * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
+ */
+static __INLINE ret_code_t gatts_context_load(pstorage_handle_t const * p_block_handle,
+                                              dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]:[CI 0x%02X]:[DI 0x%02X]: --> gatts_context_load\r\n",
+           p_handle->connection_id,
+           p_handle->device_id);
+
+    ret_code_t err_code = pstorage_load((uint8_t *)&m_gatts_table[p_handle->connection_id],
+                                        (pstorage_handle_t *)p_block_handle,
+                                        GATTS_SERVICE_CONTEXT_SIZE,
+                                        SERVICE_STORAGE_OFFSET);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        DM_LOG("[DM]:[%02X]:[Block ID 0x%08X]: Service context loaded, size 0x%08X\r\n",
+               p_handle->connection_id,
+               p_block_handle->block_id,
+               m_gatts_table[p_handle->connection_id].size);
+        DM_DUMP((uint8_t *)&m_gatts_table[p_handle->connection_id], sizeof(dm_gatts_context_t));
+
+        if (m_gatts_table[p_handle->connection_id].size == DM_GATTS_INVALID_SIZE)
+        {
+            m_gatts_table[p_handle->connection_id].size = 0;
+        }
+    }
+    else
+    {
+        DM_ERR("[DM]:[%02X]: Failed to load Service context, reason %08X\r\n",
+               p_handle->connection_id,
+               err_code);
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for loading GATT Client context.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is loaded.
+ *
+ * @retval NRF_SUCCESS
+ */
+static __INLINE ret_code_t gattc_context_load(pstorage_handle_t const * p_block_handle,
+                                              dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]: --> gattc_context_load\r\n");
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for loading GATT Server & Client context.
+ *
+ * @param[in] p_block_handle Storage block identifier.
+ * @param[in] p_handle       Device handle identifying device that is loaded.
+ *
+ * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
+ */
+static __INLINE ret_code_t gattsc_context_load(pstorage_handle_t const * p_block_handle,
+                                               dm_handle_t const       * p_handle)
+{
+    DM_LOG("[DM]: --> gattsc_context_load\r\n");
+
+    ret_code_t err_code = gatts_context_load(p_block_handle, p_handle);
+
+    if (NRF_SUCCESS == err_code)
+    {
+        err_code = gattc_context_load(p_block_handle, p_handle);
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for applying when there is no service registered.
+ *
+ * @param[in] p_handle Device handle identifying device that is applied.
+ *
+ * @retval NRF_SUCCESS
+ */
+static __INLINE ret_code_t no_service_context_apply(dm_handle_t * p_handle)
+{
+    DM_LOG("[DM]: --> no_service_context_apply\r\n");
+    DM_LOG("[DM]:[CI 0x%02X]: No Service context\r\n", p_handle->connection_id);
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for applying GATT Server context.
+ *
+ * @param[in] p_handle Device handle identifying device that is applied.
+ *
+ * @retval NRF_SUCCESS                    On success.
+ * @retval DM_SERVICE_CONTEXT_NOT_APPLIED On failure.
+ */
+static __INLINE ret_code_t gatts_context_apply(dm_handle_t * p_handle)
+{
+    uint32_t err_code;
+
+    uint8_t * p_gatts_context = NULL;
+    uint16_t  context_len     = 0;
+    uint32_t  context_flags   = 0;
+
+    DM_LOG("[DM]: --> gatts_context_apply\r\n");
+    DM_LOG("[DM]:[CI 0x%02X]: State 0x%02X, Size 0x%08X\r\n",
+           p_handle->connection_id,
+           m_connection_table[p_handle->connection_id].state,
+           m_gatts_table[p_handle->connection_id].size);
+
+    if ((m_gatts_table[p_handle->connection_id].size != 0) &&
+        (
+            ((m_connection_table[p_handle->connection_id].state & STATE_LINK_ENCRYPTED) == STATE_LINK_ENCRYPTED) &&
+            ((m_connection_table[p_handle->connection_id].state & STATE_BOND_INFO_UPDATE)
+             != STATE_BOND_INFO_UPDATE)
+        )
+       )
+    {
+        DM_LOG("[DM]: Setting stored context.\r\n");
+
+        p_gatts_context = &m_gatts_table[p_handle->connection_id].attributes[0];
+        context_len     = m_gatts_table[p_handle->connection_id].size;
+        context_flags   = m_gatts_table[p_handle->connection_id].flags;
+    }
+
+    err_code = sd_ble_gatts_sys_attr_set(m_connection_table[p_handle->connection_id].conn_handle,
+                                         p_gatts_context,
+                                         context_len,
+                                         context_flags);
+
+    if (err_code == NRF_ERROR_INVALID_DATA)
+    {
+        // Indication that the ATT table has changed. Restore the system attributes to system
+        // services only and send a service changed indication if possible.
+        context_flags = BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS;
+        err_code      = sd_ble_gatts_sys_attr_set(m_connection_table[p_handle->connection_id].conn_handle,
+                                                  p_gatts_context,
+                                                  context_len,
+                                                  context_flags);
+    }
+
+    if (err_code != NRF_SUCCESS)
+    {
+        DM_LOG("[DM]: Failed to set system attributes, reason 0x%08X.\r\n", err_code);
+
+        err_code = DM_SERVICE_CONTEXT_NOT_APPLIED;
+    }
+
+    if (context_flags == BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS)
+    {
+        err_code = sd_ble_gatts_service_changed(m_connection_table[p_handle->connection_id].conn_handle,
+                                                0x000C,
+                                                0xFFFF);
+        if (err_code != NRF_SUCCESS)
+        {
+            DM_LOG("[DM]: Failed to send Service Changed indication, reason 0x%08X.\r\n", err_code);
+            if ((err_code != BLE_ERROR_INVALID_CONN_HANDLE) &&
+                (err_code != NRF_ERROR_INVALID_STATE) &&
+                (err_code != BLE_ERROR_NO_TX_PACKETS) &&
+                (err_code != NRF_ERROR_BUSY))
+            {
+                // Those errors can be expected when sending trying to send Service Changed
+                // Indication if the CCCD is not set to indicate. Thus set the returning error
+                //  code to success.
+                err_code = NRF_SUCCESS;
+            }
+            else
+            {
+                err_code = DM_SERVICE_CONTEXT_NOT_APPLIED;
+            }
+        }
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for applying GATT Client context.
+ *
+ * @param[in] p_handle Device handle identifying device that is applied.
+ *
+ * @retval NRF_SUCCESS On success.
+ */
+static __INLINE ret_code_t gattc_context_apply(dm_handle_t * p_handle)
+{
+    DM_LOG("[DM]: --> gattc_context_apply\r\n");
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief Function for applying GATT Server & Client context.
+ *
+ * @param[in] p_handle Device handle identifying device that is applied.
+ *
+ * @retval NRF_SUCCESS On success, else an error code indicating reason for failure.
+ */
+static __INLINE ret_code_t gattsc_context_apply(dm_handle_t * p_handle)
+{
+    uint32_t err_code;
+
+    DM_LOG("[DM]: --> gattsc_context_apply\r\n");
+
+    err_code = gatts_context_apply(p_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        err_code = gattc_context_apply(p_handle);
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for pstorage module callback.
+ *
+ * @param[in] p_handle Identifies module and block for which callback is received.
+ * @param[in] op_code  Identifies the operation for which the event is notified.
+ * @param[in] result   Identifies the result of flash access operation.
+ *                     NRF_SUCCESS implies, operation succeeded.
+ * @param[in] p_data   Identifies the application data pointer. In case of store operation, this
+ *                     points to the resident source of application memory that application can now
+ *                     free or reuse. In case of clear, this is NULL as no application pointer is
+ *                     needed for this operation.
+ * @param[in] data_len Length of data provided by the application for the operation.
+ */
+static void dm_pstorage_cb_handler(pstorage_handle_t * p_handle,
+                                   uint8_t             op_code,
+                                   uint32_t            result,
+                                   uint8_t           * p_data,
+                                   uint32_t            data_len)
+{
+    VERIFY_APP_REGISTERED_VOID(0);
+
+    if (data_len > ALL_CONTEXT_SIZE)
+    {
+        //Clearing of all bonds at initialization, no event is generated.
+        return;
+    }
+
+    DM_MUTEX_LOCK();
+
+    dm_event_t        dm_event;
+    dm_handle_t       dm_handle;
+    dm_context_t      context_data;
+    pstorage_handle_t block_handle;
+    uint32_t          index_count;
+    uint32_t          err_code;
+
+    bool app_notify = true;
+
+    err_code = dm_handle_initialize(&dm_handle);
+    APP_ERROR_CHECK(err_code);
+
+    dm_handle.appl_id = 0;
+    dm_event.event_id = 0x00;
+
+    //Construct the event which it is related to.
+
+    //Initialize context data information and length.
+    context_data.p_data = p_data;
+    context_data.len    = data_len;
+
+    for (uint32_t index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+    {
+        err_code = pstorage_block_identifier_get(&m_storage_handle, index, &block_handle);
+        if ((err_code == NRF_SUCCESS) &&
+            (
+                (memcmp(p_handle, &block_handle, sizeof(pstorage_handle_t)) == 0)
+            )
+           )
+        {
+            dm_handle.device_id = index;
+            break;
+        }
+    }
+
+    if (dm_handle.device_id != DM_INVALID_ID)
+    {
+        if (op_code == PSTORAGE_CLEAR_OP_CODE)
+        {
+            if (data_len == ALL_CONTEXT_SIZE)
+            {
+                dm_event.event_id = DM_EVT_DEVICE_CONTEXT_BASE;
+            }
+            else
+            {
+                dm_event.event_id = DM_EVT_APP_CONTEXT_BASE;
+            }
+        }
+        else
+        {
+            //Update or store operation.
+            //Context is identified based on the pointer value. Device context, application context
+            //and service context all have their own value range.
+            index_count = ((uint32_t)(p_data - (uint8_t *)m_peer_table)) / PEER_ID_SIZE;
+
+            if (index_count < DEVICE_MANAGER_MAX_BONDS)
+            {
+                dm_event.event_param.p_device_context = &context_data;
+
+                //Only the peer identification is stored, not bond information. Hence do not notify
+                //the application yet, unless the store operation resulted in a failure.
+                if ((result == NRF_SUCCESS) &&
+                    (
+                        (update_status_bit_is_set(dm_handle.device_id) == false)
+                    )
+                   )
+                {
+                    app_notify = false;
+                }
+                else
+                {
+                    //Reset update status since update is complete.
+                    update_status_bit_reset(dm_handle.device_id);
+
+                    //Notify application of error in storing the context.
+                    dm_event.event_id = DM_EVT_DEVICE_CONTEXT_BASE;
+                }
+            }
+            else
+            {
+                index_count = ((uint32_t)(p_data - (uint8_t *)m_bond_table)) / BOND_SIZE;
+
+                if (index_count < DEVICE_MANAGER_MAX_CONNECTIONS)
+                {
+                    DM_LOG("[DM]:[0x%02X]:[0x%02X]: Bond context Event\r\n",
+                           dm_handle.device_id,
+                           dm_handle.connection_id);
+
+                    dm_event.event_param.p_device_context = &context_data;
+                    dm_event.event_id                     = DM_EVT_DEVICE_CONTEXT_BASE;
+                    dm_handle.connection_id               = index_count;
+
+                    ble_gap_sec_keyset_t keys_exchanged;
+                    keys_exchanged.keys_peer.p_enc_key = NULL;
+                    keys_exchanged.keys_peer.p_id_key  = &m_local_id_info;
+                    keys_exchanged.keys_own.p_enc_key  = &m_bond_table[index_count].peer_enc_key;
+                    keys_exchanged.keys_own.p_id_key   = &m_peer_table[dm_handle.device_id].peer_id;
+
+                    //Context information updated to provide the keys.
+                    context_data.p_data = (uint8_t *)&keys_exchanged;
+                    context_data.len    = sizeof(ble_gap_sec_keyset_t);
+                }
+                else
+                {
+                    index_count = ((uint32_t)(p_data - (uint8_t *)m_gatts_table)) /
+                                  GATTS_SERVICE_CONTEXT_SIZE;
+
+                    if (index_count < DEVICE_MANAGER_MAX_CONNECTIONS)
+                    {
+                        DM_LOG("[DM]:[0x%02X]:[0x%02X]: Service context Event\r\n",
+                               dm_handle.device_id,
+                               dm_handle.connection_id);
+
+                        //Notify application.
+                        dm_event.event_id       = DM_EVT_SERVICE_CONTEXT_BASE;
+                        dm_handle.connection_id = index_count;
+                        dm_handle.service_id    = DM_PROTOCOL_CNTXT_GATT_SRVR_ID;
+
+                        //Reset the service context now that it was successfully written to the
+                        //application and the link is disconnected.
+                        if ((m_connection_table[index_count].state & STATE_CONNECTED) !=
+                            STATE_CONNECTED)
+                        {
+                            DM_LOG("[DM]:[0x%02X]:[0x%02X]: Resetting bond information for "
+                                   "active instance.\r\n",
+                                   dm_handle.device_id,
+                                   dm_handle.connection_id);
+
+                            memset(&m_gatts_table[dm_handle.connection_id],
+                                   0,
+                                   sizeof(dm_gatts_context_t));
+                        }
+                    }
+                    else
+                    {
+                        DM_LOG("[DM]:[0x%02X]:[0x%02X]: App context Event\r\n",
+                               dm_handle.device_id,
+                               dm_handle.connection_id);
+
+                        app_notify        = false;
+                        dm_event.event_id = DM_EVT_APP_CONTEXT_BASE;
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+
+                        if (p_data == (uint8_t *)(&m_context_init_len))
+                        {
+                            //Context data is deleted.
+                            //This is a workaround to get the right event as on delete operation
+                            //update operation is used instead of clear.
+                            op_code    = PSTORAGE_CLEAR_OP_CODE;
+                            app_notify = true;
+                        }
+                        else if (m_app_context_table[dm_handle.device_id] == p_data)
+                        {
+                            app_notify                         = true;
+                            dm_event.event_param.p_app_context = &context_data;
+
+                            //Verify if the device is connected, if yes set connection instance.
+                            for (uint32_t index = 0;
+                                 index < DEVICE_MANAGER_MAX_CONNECTIONS;
+                                 index++)
+                            {
+                                if (dm_handle.device_id == m_connection_table[index].bonded_dev_id)
+                                {
+                                    dm_handle.connection_id = index;
+                                    break;
+                                }
+                            }
+                        }
+                        else
+                        {
+                            //No implementation needed.
+                        }
+#endif //DEVICE_MANAGER_APP_CONTEXT_SIZE
+                    }
+                }
+            }
+        }
+
+        if (app_notify == true)
+        {
+            if (op_code == PSTORAGE_CLEAR_OP_CODE)
+            {
+                dm_event.event_id |= DM_CLEAR_OPERATION_ID;
+            }
+            else if (op_code == PSTORAGE_LOAD_OP_CODE)
+            {
+                dm_event.event_id |= DM_LOAD_OPERATION_ID;
+            }
+            else
+            {
+                dm_event.event_id |= DM_STORE_OPERATION_ID;
+            }
+
+            dm_event.event_param.p_app_context = &context_data;
+            app_evt_notify(&dm_handle, &dm_event, result);
+        }
+    }
+
+    DM_MUTEX_UNLOCK();
+}
+
+
+ret_code_t dm_init(dm_init_param_t const * const p_init_param)
+{
+    pstorage_module_param_t param;
+    pstorage_handle_t       block_handle;
+    ret_code_t              err_code;
+    uint32_t                index;
+
+    DM_LOG("[DM]: >> dm_init.\r\n");
+
+    NULL_PARAM_CHECK(p_init_param);
+
+    SDK_MUTEX_INIT(m_dm_mutex);
+
+    DM_MUTEX_LOCK();
+
+    for (index = 0; index < DEVICE_MANAGER_MAX_APPLICATIONS; index++)
+    {
+        application_instance_init(index);
+    }
+
+    for (index = 0; index < DEVICE_MANAGER_MAX_CONNECTIONS; index++)
+    {
+        connection_instance_init(index);
+    }
+
+    memset(m_gatts_table, 0, sizeof(m_gatts_table));
+
+    //Initialization of all device instances.
+    for (index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+    {
+        peer_instance_init(index);
+        m_irk_index_table[index] = DM_INVALID_ID;
+    }
+
+    //All context with respect to a particular device is stored contiguously.
+    param.block_size  = ALL_CONTEXT_SIZE;
+    param.block_count = DEVICE_MANAGER_MAX_BONDS;
+    param.cb          = dm_pstorage_cb_handler;
+
+    err_code = pstorage_register(&param, &m_storage_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        m_module_initialized = true;
+
+        if (p_init_param->clear_persistent_data == false)
+        {
+            DM_LOG("[DM]: Storage handle 0x%08X.\r\n", m_storage_handle.block_id);
+
+            //Copy bonded peer device address and IRK to RAM table.
+
+            //Bonded devices are stored in range (0,DEVICE_MANAGER_MAX_BONDS-1). The remaining
+            //range is for active connections that may or may not be bonded.
+            for (index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+            {
+                err_code = pstorage_block_identifier_get(&m_storage_handle, index, &block_handle);
+
+                //Issue read request if you successfully get the block identifier.
+                if (err_code == NRF_SUCCESS)
+                {
+                    DM_TRC("[DM]:[0x%02X]: Block handle 0x%08X.\r\n", index, block_handle.block_id);
+
+                    err_code = pstorage_load((uint8_t *)&m_peer_table[index],
+                                             &block_handle,
+                                             sizeof(peer_id_t),
+                                             0);
+
+                    if (err_code != NRF_SUCCESS)
+                    {
+                        // In case a peer device could not be loaded successfully, rest of the
+                        // initialization procedure are skipped and an error is sent to the
+                        // application.
+                        DM_ERR(
+                            "[DM]: Failed to load peer device %08X from storage, reason %08X.\r\n",
+                            index,
+                            err_code);
+
+                        m_module_initialized = false;
+                        break;
+                    }
+                    else
+                    {
+                        DM_TRC("[DM]:[DI 0x%02X]: Device type 0x%02X.\r\n",
+                               index,
+                               m_peer_table[index].peer_id.id_addr_info.addr_type);
+                        DM_TRC("[DM]: Device Addr 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X 0x%02X.\r\n",
+                               m_peer_table[index].peer_id.id_addr_info.addr[0],
+                               m_peer_table[index].peer_id.id_addr_info.addr[1],
+                               m_peer_table[index].peer_id.id_addr_info.addr[2],
+                               m_peer_table[index].peer_id.id_addr_info.addr[3],
+                               m_peer_table[index].peer_id.id_addr_info.addr[4],
+                               m_peer_table[index].peer_id.id_addr_info.addr[5]);
+                    }
+                }
+                else
+                {
+                    //In case a peer device could not be loaded successfully, rest of the
+                    //initialization procedure are skipped and an error is sent to the application.
+                    DM_LOG("[DM]: Failed to get block handle for instance %08X, reason %08X.\r\n",
+                           index,
+                           err_code);
+
+                    m_module_initialized = false;
+                    break;
+                }
+            }
+        }
+        else
+        {
+            err_code = pstorage_clear(&m_storage_handle, (param.block_size * param.block_count));
+            DM_ERR("[DM]: Successfully requested clear of persistent data.\r\n");
+        }
+    }
+    else
+    {
+        DM_ERR("[DM]: Failed to register with storage module, reason 0x%08X.\r\n", err_code);
+    }
+
+    DM_MUTEX_UNLOCK();
+
+    DM_TRC("[DM]: << dm_init.\r\n");
+
+    return err_code;
+}
+
+
+ret_code_t dm_register(dm_application_instance_t    * p_appl_instance,
+                       dm_application_param_t const * p_appl_param)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_appl_instance);
+    NULL_PARAM_CHECK(p_appl_param);
+    NULL_PARAM_CHECK(p_appl_param->evt_handler);
+
+    DM_MUTEX_LOCK();
+
+    DM_LOG("[DM]: >> dm_register.\r\n");
+
+    uint32_t err_code;
+
+    //Verify if an application instance is available. Currently only one instance is supported.
+    if (m_application_table[0].ntf_cb == NULL)
+    {
+        DM_LOG("[DM]: Application Instance allocated.\r\n");
+
+        //Mark instance as allocated.
+        m_application_table[0].ntf_cb    = p_appl_param->evt_handler;
+        m_application_table[0].sec_param = p_appl_param->sec_param;
+        m_application_table[0].service   = p_appl_param->service_type;
+
+        m_application_table[0].sec_param.kdist_peer.enc  = 0;
+        m_application_table[0].sec_param.kdist_peer.id   = 1;
+        m_application_table[0].sec_param.kdist_peer.sign = 0;
+        m_application_table[0].sec_param.kdist_own.enc   = 1;
+        m_application_table[0].sec_param.kdist_own.id    = 1;
+        m_application_table[0].sec_param.kdist_own.sign  = 0;
+        //Populate application's instance variable with the assigned allocation instance.
+        *p_appl_instance = 0;
+        err_code         = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code = (NRF_ERROR_NO_MEM | DEVICE_MANAGER_ERR_BASE);
+    }
+
+    DM_MUTEX_UNLOCK();
+
+    DM_TRC("[DM]: << dm_register.\r\n");
+
+    return err_code;
+}
+
+
+ret_code_t dm_security_setup_req(dm_handle_t * p_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_CONNECTION_INSTANCE(p_handle->connection_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_LOG("[DM]: >> dm_security_setup_req\r\n");
+
+    uint32_t err_code = (NRF_ERROR_INVALID_STATE | DEVICE_MANAGER_ERR_BASE);
+
+    if ((m_connection_table[p_handle->connection_id].state & STATE_CONNECTED) == STATE_CONNECTED)
+    {
+        err_code = sd_ble_gap_authenticate(m_connection_table[p_handle->connection_id].conn_handle,
+                                           &m_application_table[0].sec_param);
+    }
+
+    DM_TRC("[DM]: << dm_security_setup_req, 0x%08X\r\n", err_code);
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_security_status_req(dm_handle_t const    * p_handle,
+                                  dm_security_status_t * p_status)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_status);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_CONNECTION_INSTANCE(p_handle->connection_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_LOG("[DM]: >> dm_security_status_req\r\n");
+
+    if ((m_connection_table[p_handle->connection_id].state & STATE_PAIRING) ||
+        (m_connection_table[p_handle->connection_id].state & STATE_PAIRING_PENDING))
+    {
+        (*p_status) = ENCRYPTION_IN_PROGRESS;
+    }
+    else if (m_connection_table[p_handle->connection_id].state & STATE_LINK_ENCRYPTED)
+    {
+        (*p_status) = ENCRYPTED;
+    }
+    else
+    {
+        (*p_status) = NOT_ENCRYPTED;
+    }
+
+    DM_TRC("[DM]: << dm_security_status_req\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t dm_whitelist_create(dm_application_instance_t const * p_handle,
+                               ble_gap_whitelist_t             * p_whitelist)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_whitelist);
+    NULL_PARAM_CHECK(p_whitelist->pp_addrs);
+    NULL_PARAM_CHECK(p_whitelist->pp_irks);
+    VERIFY_APP_REGISTERED(*p_handle);
+
+    DM_MUTEX_LOCK();
+
+    DM_LOG("[DM]: >> dm_whitelist_create\r\n");
+
+    uint32_t addr_count = 0;
+    uint32_t irk_count  = 0;
+    bool     connected  = false;
+
+    for (uint32_t index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+    {
+        connected = false;
+
+        for (uint32_t c_index = 0; c_index < DEVICE_MANAGER_MAX_CONNECTIONS; c_index++)
+        {
+            if ((index == m_connection_table[c_index].bonded_dev_id) &&
+                ((m_connection_table[c_index].state & STATE_CONNECTED) == STATE_CONNECTED))
+            {
+                connected = true;
+                break;
+            }
+        }
+
+        if (connected == false)
+        {
+            if ((irk_count < p_whitelist->irk_count) &&
+                ((m_peer_table[index].id_bitmap & IRK_ENTRY) == 0))
+            {
+                p_whitelist->pp_irks[irk_count] = &m_peer_table[index].peer_id.id_info;
+                m_irk_index_table[irk_count]    = index;
+                irk_count++;
+            }
+
+            if ((addr_count < p_whitelist->addr_count) &&
+                (m_peer_table[index].id_bitmap & ADDR_ENTRY) == 0)
+            {
+                p_whitelist->pp_addrs[addr_count] = &m_peer_table[index].peer_id.id_addr_info;
+                addr_count++;
+            }
+        }
+    }
+
+    p_whitelist->addr_count = addr_count;
+    p_whitelist->irk_count  = irk_count;
+
+    DM_LOG("[DM]: Created whitelist, number of IRK = 0x%02X, number of addr = 0x%02X\r\n",
+           irk_count,
+           addr_count);
+
+    DM_TRC("[DM]: << dm_whitelist_create\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t dm_device_add(dm_handle_t               * p_handle,
+                         dm_device_context_t const * p_context)
+{
+    return (API_NOT_IMPLEMENTED | DEVICE_MANAGER_ERR_BASE);
+}
+
+
+ret_code_t dm_device_delete(dm_handle_t const * p_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_device_delete\r\n");
+
+    uint32_t err_code = device_instance_free(p_handle->device_id);
+
+    DM_TRC("[DM]: << dm_device_delete\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_device_delete_all(dm_application_instance_t const * p_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    VERIFY_APP_REGISTERED((*p_handle));
+
+    DM_MUTEX_LOCK();
+
+    uint32_t err_code = NRF_SUCCESS;
+
+    DM_TRC("[DM]: >> dm_device_delete_all\r\n");
+
+    for (uint32_t index = 0; index < DEVICE_MANAGER_MAX_BONDS; index++)
+    {
+        if (m_peer_table[index].id_bitmap != UNASSIGNED)
+        {
+            err_code = device_instance_free(index);
+        }
+    }
+
+    DM_TRC("[DM]: << dm_device_delete_all\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_service_context_set(dm_handle_t const          * p_handle,
+                                  dm_service_context_t const * p_context)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_context);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_CONNECTION_INSTANCE(p_handle->connection_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_service_context_set\r\n");
+
+    if ((p_context->context_data.p_data != NULL) &&
+        (
+            (p_context->context_data.len != 0) &&
+            (p_context->context_data.len < DM_GATT_SERVER_ATTR_MAX_SIZE)
+        )
+       )
+    {
+        if (p_context->service_type == DM_PROTOCOL_CNTXT_GATT_SRVR_ID)
+        {
+            memcpy(m_gatts_table[p_handle->connection_id].attributes,
+                   p_context->context_data.p_data,
+                   p_context->context_data.len);
+        }
+    }
+
+    pstorage_handle_t block_handle;
+    uint32_t          err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                                               p_handle->device_id,
+                                                               &block_handle);
+
+    err_code = m_service_context_store[p_context->service_type](&block_handle, p_handle);
+
+    DM_TRC("[DM]: << dm_service_context_set\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_service_context_get(dm_handle_t const    * p_handle,
+                                  dm_service_context_t * p_context)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_context);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    if ((m_connection_table[p_handle->connection_id].state & STATE_CONNECTED) != STATE_CONNECTED)
+    {
+        DM_TRC("[DM]: Device must be connected to get context. \r\n");
+
+        return (FEATURE_NOT_ENABLED | DEVICE_MANAGER_ERR_BASE);
+    }
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_service_context_get\r\n");
+
+    if (p_context->service_type == DM_PROTOCOL_CNTXT_GATT_SRVR_ID)
+    {
+        p_context->context_data.p_data = m_gatts_table[p_handle->connection_id].attributes;
+        p_context->context_data.len    = m_gatts_table[p_handle->connection_id].size;
+    }
+
+    pstorage_handle_t block_handle;
+    uint32_t          err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                                               p_handle->device_id,
+                                                               &block_handle);
+
+    err_code = m_service_context_load[p_context->service_type](&block_handle, p_handle);
+
+    if (p_context->service_type == DM_PROTOCOL_CNTXT_GATT_SRVR_ID)
+    {
+        p_context->context_data.p_data = m_gatts_table[p_handle->connection_id].attributes;
+        p_context->context_data.len    = m_gatts_table[p_handle->connection_id].size;
+    }
+
+    DM_TRC("[DM]: << dm_service_context_get\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_service_context_delete(dm_handle_t const * p_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_LOG("[DM]: Context delete is not supported yet.\r\n");
+
+    return (API_NOT_IMPLEMENTED | DEVICE_MANAGER_ERR_BASE);
+}
+
+
+ret_code_t dm_application_context_set(dm_handle_t const              * p_handle,
+                                      dm_application_context_t const * p_context)
+{
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_context);
+    NULL_PARAM_CHECK(p_context->p_data);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+    VERIFY_DEVICE_BOND(p_handle->connection_id);
+    SIZE_CHECK_APP_CONTEXT(p_context->len);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_application_context_set\r\n");
+
+    uint32_t          err_code;
+    uint32_t          context_len;
+    pstorage_handle_t block_handle;
+
+    storage_operation store_fn = pstorage_store;
+
+    err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                             p_handle->device_id,
+                                             &block_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        err_code = pstorage_load((uint8_t *)&context_len,
+                                 &block_handle,
+                                 sizeof(uint32_t),
+                                 APP_CONTEXT_STORAGE_OFFSET);
+
+        if ((err_code == NRF_SUCCESS) && (context_len != INVALID_CONTEXT_LEN))
+        {
+            //Data already exists. Need an update.
+            store_fn = pstorage_update;
+
+            DM_LOG("[DM]:[DI 0x%02X]: Updating existing application context, existing len 0x%08X, "
+                   "new length 0x%08X.\r\n",
+                   p_handle->device_id,
+                   context_len,
+                   p_context->len);
+        }
+        else
+        {
+            DM_LOG("[DM]: Storing application context.\r\n");
+        }
+
+        //Store/update context length.
+        err_code = store_fn(&block_handle,
+                            (uint8_t *)(&p_context->len),
+                            sizeof(uint32_t),
+                            APP_CONTEXT_STORAGE_OFFSET);
+
+        if (err_code == NRF_SUCCESS)
+        {
+            //Update context data is used for application context as flash is never
+            //cleared if a delete of application context is called.
+            err_code = pstorage_update(&block_handle,
+                                       p_context->p_data,
+                                       DEVICE_MANAGER_APP_CONTEXT_SIZE,
+                                       (APP_CONTEXT_STORAGE_OFFSET + sizeof(uint32_t)));
+            if (err_code == NRF_SUCCESS)
+            {
+                m_app_context_table[p_handle->device_id] = p_context->p_data;
+            }
+        }
+    }
+
+    DM_TRC("[DM]: << dm_application_context_set\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+
+#else //DEVICE_MANAGER_APP_CONTEXT_SIZE
+    return (FEATURE_NOT_ENABLED | DEVICE_MANAGER_ERR_BASE);
+#endif //DEVICE_MANAGER_APP_CONTEXT_SIZE
+}
+
+
+ret_code_t dm_application_context_get(dm_handle_t const        * p_handle,
+                                      dm_application_context_t * p_context)
+{
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_context);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_application_context_get\r\n");
+
+    uint32_t          context_len;
+    uint32_t          err_code;
+    pstorage_handle_t block_handle;
+
+    //Check if the context exists.
+    if (NULL == p_context->p_data)
+    {
+        p_context->p_data = m_app_context_table[p_handle->device_id];
+    }
+    else
+    {
+        m_app_context_table[p_handle->device_id] = p_context->p_data;
+    }
+
+    err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                             p_handle->device_id,
+                                             &block_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        err_code = pstorage_load((uint8_t *)&context_len,
+                                 &block_handle,
+                                 sizeof(uint32_t),
+                                 APP_CONTEXT_STORAGE_OFFSET);
+
+        if ((err_code == NRF_SUCCESS) && (context_len != INVALID_CONTEXT_LEN))
+        {
+            err_code = pstorage_load(p_context->p_data,
+                                     &block_handle,
+                                     DEVICE_MANAGER_APP_CONTEXT_SIZE,
+                                     (APP_CONTEXT_STORAGE_OFFSET + sizeof(uint32_t)));
+            if (err_code == NRF_SUCCESS)
+            {
+                p_context->len = context_len;
+            }
+        }
+        else
+        {
+            err_code = DM_NO_APP_CONTEXT;
+        }
+    }
+
+    DM_TRC("[DM]: << dm_application_context_get\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+
+#else //DEVICE_MANAGER_APP_CONTEXT_SIZE
+    return (FEATURE_NOT_ENABLED | DEVICE_MANAGER_ERR_BASE);
+#endif //DEVICE_MANAGER_APP_CONTEXT_SIZE
+}
+
+
+ret_code_t dm_application_context_delete(const dm_handle_t * p_handle)
+{
+#if (DEVICE_MANAGER_APP_CONTEXT_SIZE != 0)
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_application_context_delete\r\n");
+
+    uint32_t          err_code;
+    uint32_t          context_len;
+    pstorage_handle_t block_handle;
+
+    err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                             p_handle->device_id,
+                                             &block_handle);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        err_code = pstorage_load((uint8_t *)&context_len,
+                                 &block_handle,
+                                 sizeof(uint32_t),
+                                 APP_CONTEXT_STORAGE_OFFSET);
+
+        if (context_len != m_context_init_len)
+        {
+            err_code = pstorage_update(&block_handle,
+                                       (uint8_t *)&m_context_init_len,
+                                       sizeof(uint32_t),
+                                       APP_CONTEXT_STORAGE_OFFSET);
+
+            if (err_code != NRF_SUCCESS)
+            {
+                DM_ERR("[DM]: Failed to delete application context, reason 0x%08X\r\n", err_code);
+            }
+            else
+            {
+                m_app_context_table[p_handle->device_id] = NULL;
+            }
+        }
+    }
+
+    DM_TRC("[DM]: << dm_application_context_delete\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+#else //DEVICE_MANAGER_APP_CONTEXT_SIZE
+    return (FEATURE_NOT_ENABLED | DEVICE_MANAGER_ERR_BASE);
+#endif //DEVICE_MANAGER_APP_CONTEXT_SIZE
+}
+
+
+ret_code_t dm_application_instance_set(dm_application_instance_t const * p_appl_instance,
+                                       dm_handle_t                     * p_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_appl_instance);
+    VERIFY_APP_REGISTERED((*p_appl_instance));
+
+    p_handle->appl_id = (*p_appl_instance);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t dm_handle_initialize(dm_handle_t * p_handle)
+{
+    NULL_PARAM_CHECK(p_handle);
+
+    p_handle->appl_id       = DM_INVALID_ID;
+    p_handle->connection_id = DM_INVALID_ID;
+    p_handle->device_id     = DM_INVALID_ID;
+    p_handle->service_id    = DM_INVALID_ID;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t dm_peer_addr_set(dm_handle_t const    * p_handle,
+                            ble_gap_addr_t const * p_addr)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_addr);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_peer_addr_set\r\n");
+
+    ret_code_t err_code;
+
+    if ((p_handle->connection_id == DM_INVALID_ID) &&
+        (p_addr->addr_type != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE))
+    {
+        m_peer_table[p_handle->device_id].peer_id.id_addr_info = (*p_addr);
+        update_status_bit_set(p_handle->device_id);
+        device_context_store(p_handle, UPDATE_PEER_ADDR);
+        err_code = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code = (NRF_ERROR_INVALID_PARAM | DEVICE_MANAGER_ERR_BASE);
+    }
+
+    DM_TRC("[DM]: << dm_peer_addr_set\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_peer_addr_get(dm_handle_t const * p_handle,
+                            ble_gap_addr_t    * p_addr)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_addr);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_peer_addr_get\r\n");
+
+    ret_code_t err_code;
+
+    err_code = (NRF_ERROR_NOT_FOUND | DEVICE_MANAGER_ERR_BASE);
+
+    if (p_handle->device_id == DM_INVALID_ID)
+    {
+        if ((p_handle->connection_id != DM_INVALID_ID) &&
+            ((m_connection_table[p_handle->connection_id].state & STATE_CONNECTED) ==
+             STATE_CONNECTED))
+        {
+            DM_TRC("[DM]:[CI 0x%02X]: Address get for non bonded active connection.\r\n",
+                   p_handle->connection_id);
+
+            (*p_addr) = m_connection_table[p_handle->connection_id].peer_addr;
+            err_code  = NRF_SUCCESS;
+        }
+    }
+    else
+    {
+        if ((m_peer_table[p_handle->device_id].id_bitmap & ADDR_ENTRY) == 0)
+        {
+            DM_TRC("[DM]:[DI 0x%02X]: Address get for bonded device.\r\n",
+                   p_handle->device_id);
+
+            (*p_addr) = m_peer_table[p_handle->device_id].peer_id.id_addr_info;
+            err_code  = NRF_SUCCESS;
+        }
+    }
+
+    DM_TRC("[DM]: << dm_peer_addr_get\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+ret_code_t dm_distributed_keys_get(dm_handle_t const * p_handle,
+                                   dm_sec_keyset_t   * p_key_dist)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_handle);
+    NULL_PARAM_CHECK(p_key_dist);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+    VERIFY_DEVICE_INSTANCE(p_handle->device_id);
+
+    DM_MUTEX_LOCK();
+
+    DM_TRC("[DM]: >> dm_distributed_keys_get\r\n");
+
+    ret_code_t        err_code;
+    ble_gap_enc_key_t peer_enc_key;
+    pstorage_handle_t block_handle;
+
+    err_code                                   = NRF_ERROR_NOT_FOUND;
+    p_key_dist->keys_central.enc_key.p_enc_key = NULL;
+    p_key_dist->keys_central.p_id_key          = (dm_id_key_t *)&m_peer_table[p_handle->device_id].peer_id;
+    p_key_dist->keys_central.p_sign_key        = NULL;
+    p_key_dist->keys_periph.p_id_key           = (dm_id_key_t *)&m_local_id_info;
+    p_key_dist->keys_periph.p_sign_key         = NULL;
+    p_key_dist->keys_periph.enc_key.p_enc_key  = (dm_enc_key_t *)&peer_enc_key;
+
+    if ((m_peer_table[p_handle->device_id].id_bitmap & IRK_ENTRY) == 0)
+    {
+//        p_key_dist->keys_periph.p_id_key->id_addr_info.addr_type = INVALID_ADDR_TYPE;
+    }
+
+    err_code = pstorage_block_identifier_get(&m_storage_handle, p_handle->device_id, &block_handle);
+    if (err_code == NRF_SUCCESS)
+    {
+
+        err_code = pstorage_load((uint8_t *)&peer_enc_key,
+                                 &block_handle,
+                                 BOND_SIZE,
+                                 BOND_STORAGE_OFFSET);
+
+        if (err_code == NRF_SUCCESS)
+        {
+            p_key_dist->keys_central.enc_key.p_enc_key = NULL;
+            p_key_dist->keys_central.p_id_key          = (dm_id_key_t *)&m_peer_table[p_handle->device_id].peer_id;
+            p_key_dist->keys_central.p_sign_key        = NULL;
+            p_key_dist->keys_periph.p_id_key           = (dm_id_key_t *)&m_local_id_info;
+            p_key_dist->keys_periph.p_sign_key         = NULL;
+            p_key_dist->keys_periph.enc_key.p_enc_key  = (dm_enc_key_t *)&peer_enc_key;
+        }
+    }
+
+    DM_TRC("[DM]: << dm_distributed_keys_get\r\n");
+
+    DM_MUTEX_UNLOCK();
+
+    return err_code;
+}
+
+
+/**@brief Function for loading bond information for a connection instance.
+ */
+void bond_data_load(dm_handle_t * p_handle)
+{
+    pstorage_handle_t block_handle;
+
+    uint32_t err_code = pstorage_block_identifier_get(&m_storage_handle,
+                                                       p_handle->device_id,
+                                                       &block_handle);
+    if (err_code == NRF_SUCCESS)
+    {
+        DM_LOG(
+            "[DM]:[%02X]:[Block ID 0x%08X]:Loading bond information at %p, size 0x%08X, offset 0x%08X.\r\n",
+            p_handle->connection_id,
+            block_handle.block_id,
+            &m_bond_table[p_handle->connection_id],
+            BOND_SIZE,
+            BOND_STORAGE_OFFSET);
+
+        err_code = pstorage_load((uint8_t *)&m_bond_table[p_handle->connection_id],
+                                 &block_handle,
+                                 BOND_SIZE,
+                                 BOND_STORAGE_OFFSET);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            DM_ERR("[DM]:[%02X]: Failed to load Bond information, reason %08X\r\n",
+                   p_handle->connection_id,
+                   err_code);
+        }
+
+        DM_LOG(
+            "[DM]:[%02X]:Loading service context at %p, size 0x%08X, offset 0x%08X.\r\n",
+            p_handle->connection_id,
+            &m_gatts_table[p_handle->connection_id],
+            sizeof(dm_gatts_context_t),
+            SERVICE_STORAGE_OFFSET);
+
+        err_code = m_service_context_load[m_application_table[0].service](
+            &block_handle,
+            p_handle);
+
+        if (err_code != NRF_SUCCESS)
+        {
+            DM_ERR(
+                "[DM]:[%02X]: Failed to load service information, reason %08X\r\n",
+                p_handle->connection_id,
+                err_code);
+        }
+    }
+    else
+    {
+        DM_ERR("[DM]:[%02X]: Failed to get block identifier for "
+               "device %08X, reason %08X.\r\n", p_handle->connection_id, p_handle->device_id, err_code);
+    }
+}
+
+
+void dm_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    uint32_t    err_code;
+    uint32_t    index;
+    uint32_t    device_index        = DM_INVALID_ID;
+    bool        notify_app          = false;
+    dm_handle_t handle;
+    dm_event_t  event;
+    uint32_t    event_result;
+    ble_gap_enc_info_t * p_enc_info = NULL;
+
+    VERIFY_MODULE_INITIALIZED_VOID();
+    VERIFY_APP_REGISTERED_VOID(0);
+    DM_MUTEX_LOCK();
+
+    err_code = dm_handle_initialize(&handle);
+    APP_ERROR_CHECK(err_code);
+
+    event_result                    = NRF_SUCCESS;
+    err_code                        = NRF_SUCCESS;
+    event.event_param.p_gap_param   = &p_ble_evt->evt.gap_evt;
+    event.event_paramlen            = sizeof(ble_gap_evt_t);
+    handle.device_id                = DM_INVALID_ID;
+    handle.appl_id                  = 0;
+    index                           = 0x00;
+
+    if (p_ble_evt->header.evt_id != BLE_GAP_EVT_CONNECTED)
+    {
+        err_code = connection_instance_find(p_ble_evt->evt.gap_evt.conn_handle,
+                                            STATE_CONNECTED,
+                                            &index);
+
+        if (err_code == NRF_SUCCESS)
+        {
+            handle.device_id     = m_connection_table[index].bonded_dev_id;
+            handle.connection_id = index;
+        }
+    }
+
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+            //Allocate connection instance for a new connection.
+            err_code = connection_instance_allocate(&index);
+
+            //Connection instance is successfully allocated.
+            if (err_code == NRF_SUCCESS)
+            {
+                //Application notification related information.
+                notify_app           = true;
+                event.event_id       = DM_EVT_CONNECTION;
+                handle.connection_id = index;
+
+                m_connection_table[index].conn_handle = p_ble_evt->evt.gap_evt.conn_handle;
+                m_connection_table[index].state       = STATE_CONNECTED;
+                m_connection_table[index].peer_addr   =
+                    p_ble_evt->evt.gap_evt.params.connected.peer_addr;
+
+                if (p_ble_evt->evt.gap_evt.params.connected.irk_match == 1)
+                {
+                    if (m_irk_index_table[p_ble_evt->evt.gap_evt.params.connected.irk_match_idx] != DM_INVALID_ID)
+                    {
+                        device_index = m_irk_index_table[p_ble_evt->evt.gap_evt.params.connected.irk_match_idx];
+                        err_code = NRF_SUCCESS;
+                    }
+                }
+                else
+                {
+                    //Use the device address to check if the device exists in the bonded device list.
+                    err_code = device_instance_find(&p_ble_evt->evt.gap_evt.params.connected.peer_addr,
+                                                    &device_index, EDIV_INIT_VAL);
+                }
+
+                if (err_code == NRF_SUCCESS)
+                {
+                    m_connection_table[index].bonded_dev_id = device_index;
+                    m_connection_table[index].state        |= STATE_BONDED;
+                    handle.device_id                        = device_index;
+
+                    bond_data_load(&handle);
+                }
+            }
+            break;
+
+        case BLE_GAP_EVT_DISCONNECTED:
+            //Disconnection could be peer or self initiated hence disconnecting and connecting
+            //both states are permitted, however, connection handle must be known.
+            DM_LOG("[DM]: Disconnect Reason 0x%04X\r\n",
+                   p_ble_evt->evt.gap_evt.params.disconnected.reason);
+
+            m_connection_table[index].state &= (~STATE_CONNECTED);
+
+            if ((m_connection_table[index].state & STATE_BONDED) == STATE_BONDED)
+            {
+                if ((m_connection_table[index].state & STATE_LINK_ENCRYPTED) == STATE_LINK_ENCRYPTED)
+                {
+                    //Write bond information persistently.
+                    device_context_store(&handle, STORE_ALL_CONTEXT);
+                }
+            }
+            else
+            {
+                //Free any allocated instances for devices that is not bonded.
+                if (handle.device_id != DM_INVALID_ID)
+                {
+                    peer_instance_init(handle.device_id);
+                    handle.device_id = DM_INVALID_ID;
+                }
+            }
+
+            m_connection_table[index].state = STATE_DISCONNECTING;
+            notify_app                      = true;
+            event.event_id                  = DM_EVT_DISCONNECTION;
+
+            break;
+
+        case BLE_GAP_EVT_SEC_INFO_REQUEST:
+            DM_LOG("[DM]: >> BLE_GAP_EVT_SEC_INFO_REQUEST\r\n");
+
+            //If the device is already bonded, respond with existing info, else NULL.
+            if (m_connection_table[index].bonded_dev_id == DM_INVALID_ID)
+            {
+                //Find device based on div.
+                err_code = device_instance_find(NULL,&device_index, p_ble_evt->evt.gap_evt.params.sec_info_request.master_id.ediv);
+                if (err_code == NRF_SUCCESS)
+                {
+                    //Load needed bonding information.
+                    m_connection_table[index].bonded_dev_id = device_index;
+                    m_connection_table[index].state        |= STATE_BONDED;
+                    handle.device_id                        = device_index;
+                    bond_data_load(&handle);
+                }
+            }
+
+            if (m_connection_table[index].bonded_dev_id != DM_INVALID_ID)
+            {
+                p_enc_info = &m_bond_table[index].peer_enc_key.enc_info;
+                DM_DUMP((uint8_t *)p_enc_info, sizeof(ble_gap_enc_info_t));
+            }
+
+            err_code = sd_ble_gap_sec_info_reply(p_ble_evt->evt.gap_evt.conn_handle,
+                                                 p_enc_info,
+                                                 &m_peer_table[index].peer_id.id_info,
+                                                 NULL);
+
+            if (err_code != NRF_SUCCESS)
+            {
+                DM_ERR("[DM]:[CI %02X]:[DI %02X]: Security information response failed, reason "
+                       "0x%08X\r\n", index, m_connection_table[index].bonded_dev_id, err_code);
+            }
+            break;
+
+        case BLE_GAP_EVT_SEC_PARAMS_REQUEST:
+            DM_LOG("[DM]: >> BLE_GAP_EVT_SEC_PARAMS_REQUEST\r\n");
+
+            event.event_id = DM_EVT_SECURITY_SETUP;
+
+            m_connection_table[index].state |= STATE_PAIRING;
+            notify_app                       = true;
+
+            if (m_connection_table[index].bonded_dev_id == DM_INVALID_ID)
+            {
+                //Assign a peer index as a new bond or update existing bonds.
+                err_code = device_instance_allocate((uint8_t *)&device_index,
+                                                    &m_connection_table[index].peer_addr);
+
+                //Allocation successful.
+                if (err_code == NRF_SUCCESS)
+                {
+                    DM_LOG("[DM]:[CI 0x%02X]:[DI 0x%02X]: Bonded!\r\n",index, device_index);
+
+                    handle.device_id                        = device_index;
+                    m_connection_table[index].bonded_dev_id = device_index;
+                }
+                else
+                {
+                    DM_LOG("[DM]: Security parameter request failed, reason 0x%08X.\r\n", err_code);
+                    event_result = err_code;
+                    notify_app   = true;
+                }
+
+                ble_gap_sec_keyset_t keys_exchanged;
+
+                DM_LOG("[DM]: 0x%02X, 0x%02X, 0x%02X, 0x%02X\r\n",
+                       p_ble_evt->evt.gap_evt.params.sec_params_request.peer_params.kdist_peer.enc,
+                       p_ble_evt->evt.gap_evt.params.sec_params_request.peer_params.kdist_own.id,
+                       p_ble_evt->evt.gap_evt.params.sec_params_request.peer_params.kdist_peer.sign,
+                       p_ble_evt->evt.gap_evt.params.sec_params_request.peer_params.bond);
+
+                keys_exchanged.keys_peer.p_enc_key  = NULL;
+                keys_exchanged.keys_peer.p_id_key   = &m_peer_table[m_connection_table[index].bonded_dev_id].peer_id;
+                keys_exchanged.keys_peer.p_sign_key = NULL;
+                keys_exchanged.keys_peer.p_pk       = NULL;
+                keys_exchanged.keys_own.p_enc_key   = &m_bond_table[index].peer_enc_key;
+                keys_exchanged.keys_own.p_id_key    = NULL;
+                keys_exchanged.keys_own.p_sign_key  = NULL;
+                keys_exchanged.keys_own.p_pk        = NULL;
+
+                err_code = sd_ble_gap_sec_params_reply(p_ble_evt->evt.gap_evt.conn_handle,
+                                                       BLE_GAP_SEC_STATUS_SUCCESS,
+                                                       &m_application_table[0].sec_param,
+                                                       &keys_exchanged);
+
+                if (err_code != NRF_SUCCESS)
+                {
+                    DM_LOG("[DM]: Security parameter reply request failed, reason 0x%08X.\r\n", err_code);
+                    event_result = err_code;
+                    notify_app   = false;
+                }
+
+            }
+            else
+            {
+                //Bond/key refresh.
+                DM_LOG("[DM]: !!! Bond/key refresh !!!\r\n");
+                //Set the update flag for bond data.
+                m_connection_table[index].state |= STATE_BOND_INFO_UPDATE;
+                event.event_id                   = DM_EVT_SECURITY_SETUP_REFRESH;
+
+                err_code = sd_ble_gap_sec_params_reply(p_ble_evt->evt.gap_evt.conn_handle,
+                                                       BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP,
+                                                       NULL,
+                                                       NULL);
+
+                if (err_code != NRF_SUCCESS)
+                {
+                    DM_LOG("[DM]: Security parameter reply request failed, reason 0x%08X.\r\n", err_code);
+                    event_result = err_code;
+                    notify_app   = false;
+                }
+
+            }
+            break;
+
+        case BLE_GAP_EVT_AUTH_STATUS:
+        {
+            DM_LOG("[DM]: >> BLE_GAP_EVT_AUTH_STATUS, status %08X\r\n",
+                   p_ble_evt->evt.gap_evt.params.auth_status.auth_status);
+
+            m_application_table[0].state    &= (~STATE_CONTROL_PROCEDURE_IN_PROGRESS);
+            m_connection_table[index].state &= (~STATE_PAIRING);
+            event.event_id                   = DM_EVT_SECURITY_SETUP_COMPLETE;
+            notify_app                       = true;
+
+            if (p_ble_evt->evt.gap_evt.params.auth_status.auth_status != BLE_GAP_SEC_STATUS_SUCCESS)
+            {
+                // In case of key refresh attempt, since this behavior is now rejected, we don't do anything here
+                if ((m_connection_table[index].state & STATE_BOND_INFO_UPDATE)
+                    != STATE_BOND_INFO_UPDATE)
+                {
+                    // Free the allocation as bonding failed.
+                    ret_code_t result = device_instance_free(m_connection_table[index].bonded_dev_id);
+                    (void) result;
+                    event_result = p_ble_evt->evt.gap_evt.params.auth_status.auth_status;
+                }
+            }
+            else
+            {
+                DM_DUMP((uint8_t *)&p_ble_evt->evt.gap_evt.params.auth_status,
+                        sizeof(ble_gap_evt_auth_status_t));
+                DM_DUMP((uint8_t *)&m_bond_table[index], sizeof(bond_context_t));
+
+                if (p_ble_evt->evt.gap_evt.params.auth_status.bonded == 1)
+                {
+                    if (handle.device_id != DM_INVALID_ID)
+                    {
+                        m_connection_table[index].state |= STATE_BONDED;
+
+                        //IRK and/or public address is shared, update it.
+                        if (p_ble_evt->evt.gap_evt.params.auth_status.kdist_peer.id == 1)
+                        {
+                            m_peer_table[handle.device_id].id_bitmap &= (~IRK_ENTRY);
+                        }
+
+                        if (m_connection_table[index].bonded_dev_id != DM_INVALID_ID)
+                        {
+                            DM_LOG("[DM]:[CI 0x%02X]:[DI 0x%02X]: Bonded!\r\n",
+                                   index,
+                                   handle.device_id);
+
+                            if (m_connection_table[index].peer_addr.addr_type !=
+                                BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE)
+                            {
+                               m_peer_table[handle.device_id].peer_id.id_addr_info =
+                                    m_connection_table[index].peer_addr;
+                               m_peer_table[handle.device_id].id_bitmap &= (~ADDR_ENTRY);
+
+                               DM_DUMP((uint8_t *)&m_peer_table[handle.device_id].peer_id.id_addr_info,
+                                       sizeof(m_peer_table[handle.device_id].peer_id.id_addr_info));
+                            }
+                            else
+                            {
+                                // Here we must fetch the keys from the keyset distributed.
+                                m_peer_table[handle.device_id].ediv       = m_bond_table[index].peer_enc_key.master_id.ediv;
+                                m_peer_table[handle.device_id].id_bitmap &= (~IRK_ENTRY);
+                            }
+
+                            device_context_store(&handle, FIRST_BOND_STORE);
+                        }
+                    }
+                }
+                else
+                {
+                    //Pairing request, no need to touch the bonding info.
+                }
+            }
+            break;
+        }
+
+        case BLE_GAP_EVT_CONN_SEC_UPDATE:
+            DM_LOG("[DM]: >> BLE_GAP_EVT_CONN_SEC_UPDATE, Mode 0x%02X, Level 0x%02X\r\n",
+                   p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.sm,
+                   p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv);
+
+            if ((p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.lv == 1) &&
+                (p_ble_evt->evt.gap_evt.params.conn_sec_update.conn_sec.sec_mode.sm == 1) &&
+                ((m_connection_table[index].state & STATE_BONDED) == STATE_BONDED))
+            {
+                //Lost bond case, generate a security refresh event!
+                memset(m_gatts_table[index].attributes, 0, DM_GATT_SERVER_ATTR_MAX_SIZE);
+
+                event.event_id                   = DM_EVT_SECURITY_SETUP_REFRESH;
+                m_connection_table[index].state |= STATE_PAIRING_PENDING;
+                m_connection_table[index].state |= STATE_BOND_INFO_UPDATE;
+                m_application_table[0].state    |= STATE_QUEUED_CONTROL_REQUEST;
+            }
+            else
+            {
+                m_connection_table[index].state |= STATE_LINK_ENCRYPTED;
+                event.event_id                   = DM_EVT_LINK_SECURED;
+
+                //Apply service context.
+                err_code = m_service_context_apply[m_application_table[0].service](&handle);
+
+                if (err_code != NRF_SUCCESS)
+                {
+                    DM_ERR("[DM]:[CI 0x%02X]:[DI 0x%02X]: Failed to apply service context\r\n",
+                            handle.connection_id,
+                            handle.device_id);
+
+                    event_result = DM_SERVICE_CONTEXT_NOT_APPLIED;
+                }
+            }
+            event_result = NRF_SUCCESS;
+            notify_app   = true;
+
+            break;
+
+        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
+            DM_LOG("[DM]: >> BLE_GATTS_EVT_SYS_ATTR_MISSING\r\n");
+
+            //Apply service context.
+            event_result = m_service_context_apply[m_application_table[0].service](&handle);
+            break;
+
+        case BLE_GAP_EVT_SEC_REQUEST:
+            DM_LOG("[DM]: >> BLE_GAP_EVT_SEC_REQUEST\r\n");
+
+            //Verify if the device is already bonded, and if it is bonded, initiate encryption.
+            //If the device is not bonded, an instance needs to be allocated in order to initiate
+            //bonding. The application have to initiate the procedure, the module will not do this
+            //automatically.
+            event.event_id = DM_EVT_SECURITY_SETUP;
+            notify_app     = true;
+
+            break;
+
+        default:
+            break;
+    }
+
+    if (notify_app)
+    {
+        app_evt_notify(&handle, &event, event_result);
+
+        //Freeing the instance after the event is notified so the application can get the context.
+        if (event.event_id == DM_EVT_DISCONNECTION)
+        {
+            //Free the instance.
+            connection_instance_free(&index);
+        }
+    }
+
+    UNUSED_VARIABLE(err_code);
+
+    DM_MUTEX_UNLOCK();
+}
+
+
+ret_code_t dm_handle_get(uint16_t conn_handle, dm_handle_t * p_handle)
+{
+    ret_code_t err_code;
+    uint32_t   index;
+
+    NULL_PARAM_CHECK(p_handle);
+    VERIFY_APP_REGISTERED(p_handle->appl_id);
+
+    p_handle->device_id  = DM_INVALID_ID;
+
+    err_code = NRF_ERROR_NOT_FOUND;
+
+    for (index = 0; index < DEVICE_MANAGER_MAX_CONNECTIONS; index++)
+    {
+        //Search for matching connection handle.
+        if (conn_handle == m_connection_table[index].conn_handle)
+        {
+            p_handle->connection_id = index;
+            p_handle->device_id     = m_connection_table[index].bonded_dev_id;
+
+            err_code = NRF_SUCCESS;
+            break;
+        }
+    }
+    return err_code;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.c
new file mode 100644
index 0000000000..ef09362c4c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.c
@@ -0,0 +1,595 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "gatt_cache_manager.h"
+
+#include "nrf_ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_database.h"
+#include "id_manager.h"
+#include "security_dispatcher.h"
+#include "gatts_cache_manager.h"
+#include "gattc_cache_manager.h"
+#include "sdk_common.h"
+
+/**@brief Structure containing the module variable(s) of the GCM module.
+ */
+typedef struct
+{
+    gcm_evt_handler_t             evt_handler;                     /**< The event handler to use for outbound GSCM events. */
+    ble_conn_state_user_flag_id_t flag_id_local_db_update_pending; /**< Flag ID for flag collection to keep track of which connections need a local DB update procedure. */
+    ble_conn_state_user_flag_id_t flag_id_local_db_apply_pending;  /**< Flag ID for flag collection to keep track of which connections need a local DB apply procedure. */
+    ble_conn_state_user_flag_id_t flag_id_service_changed_pending; /**< Flag ID for flag collection to keep track of which connections need to be sent a service changed indication. */
+    ble_conn_state_user_flag_id_t flag_id_service_changed_sent;    /**< Flag ID for flag collection to keep track of which connections have been sent a service changed indication and are waiting for a handle value confirmation. */
+} gcm_t;
+
+static gcm_t m_gcm;  /**< Instantiation of module variable(s). */
+
+#define MODULE_INITIALIZED (m_gcm.evt_handler != NULL)
+#include "sdk_macros.h"
+
+
+static void service_changed_pending_flags_check(void);
+
+/**@brief Function for resetting the module variable(s) of the GSCM module.
+ *
+ * @param[out]  The instance to reset.
+ */
+static void internal_state_reset(gcm_t * p_gcm)
+{
+    memset(p_gcm, 0, sizeof(gcm_t));
+}
+
+
+/**@brief Function for checking a write event for whether a CCCD was written during the write
+ *        operation.
+ *
+ * @param[in]  p_write_evt  The parameters of the write event.
+ *
+ * @return  Whether the write was on a CCCD.
+ */
+static bool cccd_written(ble_gatts_evt_write_t * p_write_evt)
+{
+    return (    (p_write_evt->op        == BLE_GATTS_OP_WRITE_REQ)
+             && (p_write_evt->uuid.type == BLE_UUID_TYPE_BLE)
+             && (p_write_evt->uuid.uuid == BLE_UUID_DESCRIPTOR_CLIENT_CHAR_CONFIG)
+           );
+}
+
+
+/**@brief Function for performing the local DB update procedure in an event context, where no return
+ *        code can be given.
+ *
+ * @details This function will do the procedure, and check the result, set a flag if needed, and
+ *          send an event if needed.
+ *
+ * @param[in]  conn_handle  The connection to perform the procedure on.
+ */
+static void local_db_apply_in_evt(uint16_t conn_handle)
+{
+    bool set_procedure_as_pending = false;
+    ret_code_t err_code;
+    gcm_evt_t event;
+
+    if (conn_handle == BLE_CONN_HANDLE_INVALID)
+    {
+        return;
+    }
+
+    err_code = gscm_local_db_cache_apply(conn_handle);
+
+    switch(err_code)
+    {
+        case NRF_SUCCESS:
+            event.evt_id                                    = GCM_EVT_LOCAL_DB_CACHE_APPLIED;
+            event.peer_id                                   = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.local_db_cache_applied.conn_handle = conn_handle;
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case NRF_ERROR_BUSY:
+            set_procedure_as_pending = true;
+            break;
+
+        case NRF_ERROR_INVALID_DATA:
+            event.evt_id                                        = GCM_EVT_ERROR_LOCAL_DB_CACHE_APPLY;
+            event.peer_id                                       = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.error_local_db_cache_apply.conn_handle = conn_handle;
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            /* Do nothing */
+            break;
+
+        default:
+            event.evt_id                              = GCM_EVT_ERROR_UNEXPECTED;
+            event.peer_id                             = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.error_unexpected.conn_handle = conn_handle;
+            event.params.error_unexpected.error       = err_code;
+
+            m_gcm.evt_handler(&event);
+            break;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_gcm.flag_id_local_db_apply_pending, set_procedure_as_pending);
+}
+
+
+/**@brief Function for performing the local DB apply procedure in an event context, where no return
+ *        code can be given.
+ *
+ * @details This function will do the procedure, and check the result, set a flag if needed, and
+ *          send an event if needed.
+ *
+ * @param[in]  conn_handle  The connection to perform the procedure on.
+ */
+static void local_db_update_in_evt(uint16_t conn_handle)
+{
+    gcm_evt_t event;
+    bool set_procedure_as_pending = false;
+    ret_code_t err_code = gscm_local_db_cache_update(conn_handle);
+
+    switch(err_code)
+    {
+        case NRF_SUCCESS:
+            event.evt_id                                    = GCM_EVT_LOCAL_DB_CACHE_UPDATED;
+            event.params.local_db_cache_applied.conn_handle = conn_handle;
+            event.peer_id                                   = im_peer_id_get_by_conn_handle(conn_handle);
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            /* Do nothing */
+            break;
+
+        case NRF_ERROR_BUSY:
+            set_procedure_as_pending = true;
+            break;
+
+        case NRF_ERROR_DATA_SIZE:
+            event.evt_id = GCM_EVT_ERROR_DATA_SIZE;
+            event.params.error_data_size.conn_handle = conn_handle;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case NRF_ERROR_NO_MEM:
+            event.evt_id = GCM_EVT_ERROR_STORAGE_FULL;
+            event.params.error_no_mem.conn_handle = conn_handle;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        default:
+            event.evt_id                              = GCM_EVT_ERROR_UNEXPECTED;
+            event.peer_id                             = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.error_unexpected.conn_handle = conn_handle;
+            event.params.error_unexpected.error       = err_code;
+
+            m_gcm.evt_handler(&event);
+            break;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_gcm.flag_id_local_db_update_pending, set_procedure_as_pending);
+}
+
+
+/**@brief Function for sending a service changed indication in an event context, where no return
+ *        code can be given.
+ *
+ * @details This function will do the procedure, and check the result, set a flag if needed, and
+ *          send an event if needed.
+ *
+ * @param[in]  conn_handle  The connection to perform the procedure on.
+ */
+static void service_changed_send_in_evt(uint16_t conn_handle)
+{
+    gcm_evt_t event;
+    bool sc_pending_state = true;
+    bool sc_sent_state = false;
+    ret_code_t err_code = gscm_service_changed_ind_send(conn_handle);
+
+    switch(err_code)
+    {
+        case NRF_SUCCESS:
+            sc_sent_state = true;
+
+            event.evt_id = GCM_EVT_SERVICE_CHANGED_IND_SENT;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+            event.params.service_changed_ind_sent.conn_handle = conn_handle;
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case NRF_ERROR_BUSY:
+            // Do nothing.
+            break;
+
+        case NRF_ERROR_INVALID_STATE:
+            // CCCDs not enabled. Drop indication.
+            // Fallthrough.
+
+        case NRF_ERROR_NOT_SUPPORTED:
+            // Service changed not supported. Drop indication.
+            sc_pending_state = false;
+            gscm_db_change_notification_done(im_peer_id_get_by_conn_handle(conn_handle));
+            break;
+
+        case BLE_ERROR_GATTS_SYS_ATTR_MISSING:
+            local_db_apply_in_evt(conn_handle);
+            break;
+
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+            // Do nothing.
+            break;
+
+        default:
+            event.evt_id = GCM_EVT_ERROR_UNEXPECTED;
+            event.params.error_unexpected.conn_handle = conn_handle;
+            event.params.error_unexpected.error = err_code;
+            event.peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+            m_gcm.evt_handler(&event);
+            break;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_gcm.flag_id_service_changed_pending, sc_pending_state);
+    ble_conn_state_user_flag_set(conn_handle, m_gcm.flag_id_service_changed_sent, sc_sent_state);
+}
+
+
+/**@brief Callback function for events from the GATT Cache Server Manager module.
+ *
+ * @param[in]  p_event  The event from the GATT Cache Server Manager module.
+ */
+static void gscm_evt_handler(gscm_evt_t const * p_event)
+{
+    gcm_evt_t event;
+    event.peer_id = p_event->peer_id;
+
+    switch (p_event->evt_id)
+    {
+        case GSCM_EVT_LOCAL_DB_CACHE_STORED:
+            event.evt_id = GCM_EVT_LOCAL_DB_CACHE_STORED;
+
+            m_gcm.evt_handler(&event);
+            local_db_apply_in_evt(im_conn_handle_get(p_event->peer_id));
+            break;
+
+        case GSCM_EVT_LOCAL_DB_CACHE_UPDATED:
+            event.evt_id = GCM_EVT_LOCAL_DB_CACHE_UPDATED;
+            event.params.local_db_cache_updated.conn_handle = p_event->params.local_db_cache_updated.conn_handle;
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case GSCM_EVT_SC_STATE_STORED:
+            if (p_event->params.sc_state_stored.state)
+            {
+                uint16_t conn_handle = im_conn_handle_get(p_event->peer_id);
+                if (conn_handle != BLE_CONN_HANDLE_INVALID)
+                {
+                    ble_conn_state_user_flag_set(conn_handle, m_gcm.flag_id_service_changed_pending, true);
+                    service_changed_pending_flags_check();
+                }
+            }
+            break;
+    }
+}
+
+
+/**@brief Callback function for events from the GATT Cache Client Manager module.
+ *
+ * @param[in]  p_event  The event from the GATT Cache Client Manager module.
+ */
+static void gccm_evt_handler(gccm_evt_t const * p_event)
+{
+
+}
+
+
+/**@brief Callback function for events from the Identity Manager module.
+ *
+ * @param[in]  p_event  The event from the Identity Manager module.
+ */
+static void im_evt_handler(im_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case IM_EVT_BONDED_PEER_CONNECTED:
+            local_db_apply_in_evt(p_event->conn_handle);
+            if (gscm_service_changed_ind_needed(p_event->conn_handle))
+            {
+                ble_conn_state_user_flag_set(p_event->conn_handle, m_gcm.flag_id_service_changed_pending, true);
+            }
+            break;
+        default:
+            break;
+    }
+}
+
+
+/**@brief Callback function for events from the Security Dispatcher module.
+ *
+ * @param[in]  p_event  The event from the Security Dispatcher module.
+ */
+static void smd_evt_handler(smd_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case SMD_EVT_BONDING_INFO_STORED:
+            local_db_update_in_evt(p_event->conn_handle);
+            break;
+        default:
+            break;
+    }
+}
+
+
+ret_code_t gcm_init(gcm_evt_handler_t evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+
+    ret_code_t err_code;
+
+    err_code = gscm_init(gscm_evt_handler);
+    VERIFY_SUCCESS(err_code);
+
+    err_code = gccm_init(gccm_evt_handler);
+    VERIFY_SUCCESS(err_code);
+
+    internal_state_reset(&m_gcm);
+    m_gcm.evt_handler = evt_handler;
+
+    err_code = im_register(im_evt_handler);
+    VERIFY_SUCCESS(err_code);
+
+    err_code = smd_register(smd_evt_handler);
+    VERIFY_SUCCESS(err_code);
+
+
+    m_gcm.flag_id_local_db_update_pending = ble_conn_state_user_flag_acquire();
+    m_gcm.flag_id_local_db_apply_pending  = ble_conn_state_user_flag_acquire();
+    m_gcm.flag_id_service_changed_pending = ble_conn_state_user_flag_acquire();
+    m_gcm.flag_id_service_changed_sent    = ble_conn_state_user_flag_acquire();
+
+    if  ((m_gcm.flag_id_local_db_update_pending  == BLE_CONN_STATE_USER_FLAG_INVALID)
+      || (m_gcm.flag_id_local_db_apply_pending   == BLE_CONN_STATE_USER_FLAG_INVALID)
+      || (m_gcm.flag_id_service_changed_pending  == BLE_CONN_STATE_USER_FLAG_INVALID)
+      || (m_gcm.flag_id_service_changed_sent     == BLE_CONN_STATE_USER_FLAG_INVALID))
+    {
+        err_code = NRF_ERROR_INTERNAL;
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for performing the Local DB apply procedure if it is pending on any connections.
+ */
+static void apply_pending_flags_check(void)
+{
+    sdk_mapped_flags_t apply_pending_flags;
+
+    apply_pending_flags = ble_conn_state_user_flag_collection(m_gcm.flag_id_local_db_apply_pending);
+    if (sdk_mapped_flags_any_set(apply_pending_flags))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list;
+        conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            if (ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_gcm.flag_id_local_db_apply_pending))
+            {
+                local_db_apply_in_evt(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Function for performing the Local DB update procedure if it is pending on any connections.
+ */
+static void update_pending_flags_check(void)
+{
+    sdk_mapped_flags_t update_pending_flags;
+
+    update_pending_flags = ble_conn_state_user_flag_collection(m_gcm.flag_id_local_db_update_pending);
+    if (sdk_mapped_flags_any_set(update_pending_flags))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list;
+        conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            if (ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_gcm.flag_id_local_db_update_pending))
+            {
+                local_db_update_in_evt(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Function for sending service changed indications if it is pending on any connections.
+ */
+static void service_changed_pending_flags_check(void)
+{
+    sdk_mapped_flags_t service_changed_pending_flags;
+
+    service_changed_pending_flags = ble_conn_state_user_flag_collection(m_gcm.flag_id_service_changed_pending);
+    if (sdk_mapped_flags_any_set(service_changed_pending_flags))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list;
+        conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            if (    ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i],
+                                                 m_gcm.flag_id_service_changed_pending)
+                && !ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i],
+                                                 m_gcm.flag_id_service_changed_sent))
+            {
+                service_changed_send_in_evt(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+/**@brief Callback function for BLE events from the SoftDevice.
+ *
+ * @param[in]  p_ble_evt  The BLE event from the SoftDevice.
+ */
+void gcm_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    gcm_evt_t event;
+
+    switch(p_ble_evt->header.evt_id)
+    {
+        case BLE_GATTS_EVT_SYS_ATTR_MISSING:
+            local_db_apply_in_evt(p_ble_evt->evt.gatts_evt.conn_handle);
+            break;
+
+        case BLE_GATTS_EVT_SC_CONFIRM:
+            event.evt_id = GCM_EVT_SERVICE_CHANGED_IND_CONFIRMED;
+            event.peer_id = im_peer_id_get_by_conn_handle(p_ble_evt->evt.gatts_evt.conn_handle);
+            event.params.service_changed_ind_sent.conn_handle = p_ble_evt->evt.gatts_evt.conn_handle;
+
+            gscm_db_change_notification_done(event.peer_id);
+            ble_conn_state_user_flag_set(p_ble_evt->evt.gatts_evt.conn_handle, m_gcm.flag_id_service_changed_pending, false);
+
+            m_gcm.evt_handler(&event);
+            break;
+
+        case BLE_GATTS_EVT_WRITE:
+            if (cccd_written(&p_ble_evt->evt.gatts_evt.params.write))
+            {
+                local_db_update_in_evt(p_ble_evt->evt.gatts_evt.conn_handle);
+            }
+            break;
+    }
+
+    apply_pending_flags_check();
+    update_pending_flags_check();
+    service_changed_pending_flags_check();
+}
+
+
+ret_code_t gcm_remote_db_store(pm_peer_id_t        peer_id,
+                               ble_gatt_db_srv_t * p_remote_db,
+                               uint32_t            n_services)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return gccm_remote_db_store(peer_id, p_remote_db, n_services);
+}
+
+
+ret_code_t gcm_remote_db_retrieve(pm_peer_id_t        peer_id,
+                                  ble_gatt_db_srv_t * p_remote_db,
+                                  uint32_t          * p_n_services)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_remote_db);
+
+    return gccm_remote_db_retrieve(peer_id, p_remote_db, p_n_services);
+}
+
+
+ret_code_t gcm_local_db_cache_update(uint16_t conn_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code = gscm_local_db_cache_update(conn_handle);
+    bool set_procedure_as_pending = false;
+
+    if (err_code == NRF_ERROR_BUSY)
+    {
+        set_procedure_as_pending = true;
+        err_code = NRF_SUCCESS;
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_gcm.flag_id_local_db_update_pending, set_procedure_as_pending);
+
+    return err_code;
+}
+
+
+ret_code_t gcm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return gscm_local_db_cache_set(peer_id, p_local_db);
+}
+
+
+ret_code_t gcm_local_db_cache_get(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return gscm_local_db_cache_get(peer_id, p_local_db);
+}
+
+
+void gcm_local_database_has_changed(void)
+{
+    gscm_local_database_has_changed();
+
+    sdk_mapped_flags_key_list_t conn_handles = ble_conn_state_conn_handles();
+
+    for (uint16_t i = 0; i < conn_handles.len; i++)
+    {
+        if (im_peer_id_get_by_conn_handle(conn_handles.flag_keys[i]) == PM_PEER_ID_INVALID)
+        {
+            ble_conn_state_user_flag_set(conn_handles.flag_keys[i], m_gcm.flag_id_service_changed_pending, true);
+        }
+    }
+
+    service_changed_pending_flags_check();
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.h
new file mode 100644
index 0000000000..c4b763c358
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatt_cache_manager.h
@@ -0,0 +1,236 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef GATT_CACHE_MANAGER_H__
+#define GATT_CACHE_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup gatt_cache_manager GATT Cache Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for managing persistent storing of GATT
+ *        attributes.
+ */
+
+
+/**@brief Events that can come from the GATT Cache Manager module.
+ */
+typedef enum
+{
+    GCM_EVT_LOCAL_DB_CACHE_STORED,           /**< The persistent cache for the local database has been updated with provided values, for one peer. */
+    GCM_EVT_LOCAL_DB_CACHE_UPDATED,          /**< The persistent cache for the local database has been updated with values from the SoftDevice, for one peer. */
+    GCM_EVT_LOCAL_DB_CACHE_APPLIED,          /**< The SoftDevice has been given local database values from the persistent cache, for one peer. */
+    GCM_EVT_ERROR_LOCAL_DB_CACHE_APPLY,      /**< The stored local database values for a peer were rejected by the SoftDevice, which means the database has changed. */
+    GCM_EVT_REMOTE_DB_CACHE_UPDATED,         /**< The persistent cache for the remote database has been updated with provided values, for one peer. */
+    GCM_EVT_SERVICE_CHANGED_IND_SENT,        /**< A service changed indication has been sent to a peer. */
+    GCM_EVT_SERVICE_CHANGED_IND_CONFIRMED,   /**< A sent service changed indication has been confirmed by a peer. */
+    GCM_EVT_ERROR_DATA_SIZE,                 /**< An operation failed because the write buffer of the Peer Database module was not large enough. This is a fatal error. */
+    GCM_EVT_ERROR_STORAGE_FULL,              /**< An operation failed because there was no available storage room in persistent storage. Please free up room, and the operation will automatically continue. */
+    GCM_EVT_ERROR_UNEXPECTED,                /**< An operation failed with an unexpected error. The error is provided. This is possibly a fatal error. */
+} gcm_evt_id_t;
+
+
+/**@brief A structure meant to be used for event parameters for multiple event types.
+ */
+typedef struct
+{
+    uint16_t conn_handle;  /**< The connection handle. Likely the connection handle an event pertains to. */
+} gcm_evt_param_conn_handle_t;
+
+
+/**@brief Structure containing an event from the GCM module.
+ */
+typedef struct
+{
+    gcm_evt_id_t   evt_id;  /**< The type of event this is. */
+    pm_peer_id_t   peer_id; /**< The peer ID this event pertains to. */
+    union
+    {
+        gcm_evt_param_conn_handle_t local_db_cache_updated;
+        gcm_evt_param_conn_handle_t local_db_cache_applied;
+        gcm_evt_param_conn_handle_t error_local_db_cache_apply;
+        gcm_evt_param_conn_handle_t service_changed_ind_sent;
+        gcm_evt_param_conn_handle_t service_changed_ind_confirmed;
+        gcm_evt_param_conn_handle_t error_data_size;
+        gcm_evt_param_conn_handle_t error_no_mem;
+        struct
+        {
+            uint16_t   conn_handle; /**< The handle of the connection the event pertains to. */
+            ret_code_t error;       /**< The unexpected error that occurred. */
+        } error_unexpected;
+    } params; /**< Event specific parameters. Chosen based on evt_id. */
+} gcm_evt_t;
+
+/**@brief Event handler for events from the GATT Cache Manager module.
+ *
+ * @param[in]  event   The event that has happened.
+ * @param[in]  peer  The id of the peer the event pertains to.
+ * @param[in]  flags   The data the event pertains to.
+ */
+typedef void (*gcm_evt_handler_t)(gcm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the GATT Cache Manager module.
+ *
+ * @param[in]  evt_handler  Callback for events from the GATT Cache Manager module.
+ *
+ * @retval NRF_SUCCESS     Initialization was successful.
+ * @retval NRF_ERROR_NULL  evt_handler was NULL.
+ */
+ret_code_t gcm_init(gcm_evt_handler_t evt_handler);
+
+
+/**@brief Function for dispatching SoftDevice events to the GATT Cache Manager module.
+ *
+ * @param[in]  p_ble_evt  The SoftDevice event.
+ */
+void gcm_ble_evt_handler(ble_evt_t * p_ble_evt);
+
+
+
+/**@brief Function for storing a discovered remote database persistently.
+ *
+ * @param[in]  peer_id      Peer to store the database for.
+ * @param[in]  p_remote_db  Database values to store as an array. Can be NULL if n_services is 0.
+ * @param[in]  n_services   Number of services in p_remote_db array. If 0, values are cleared.
+ *
+ * @retval NRF_SUCCESS              Store procedure successfully started.
+ * @retval NRF_ERROR_NOT_FOUND      The peer id is invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_remote_db_store(pm_peer_id_t        peer_id,
+                               ble_gatt_db_srv_t * p_remote_db,
+                               uint32_t            n_services);
+
+
+/**@brief Function for retrieving a persistently stored remote database.
+ *
+ * @param[in]    peer_id      Peer to retrieve data for.
+ * @param[out]   p_remote_db  If p_n_services was large enough: Copied database values.
+ * @param[inout] p_n_services In: Size of provided p_remote_db array. Out: Size of data in flash.
+ *
+ * @note p_n_services is always updated with the size of the data to be retrieved. The data is only
+ *       copied if p_remote_db is large enough (p_n_services is large enough initially).
+ *
+ * @retval NRF_SUCCESS              Data retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID is invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_remote_db is NULL.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_remote_db_retrieve(pm_peer_id_t        peer_id,
+                                  ble_gatt_db_srv_t * p_remote_db,
+                                  uint32_t          * p_n_services);
+
+
+/**@brief Function for triggering local GATT database data to be stored persistently. Values are
+ *        retrieved from SoftDevice and written to persistent storage.
+ *
+ * @note This function is only needed when you want to override the regular functionality of the
+ *       module, e.g. to immediately store to flash instead of waiting for the native logic to
+ *       perform the update.
+ *
+ * @param[in]  conn_handle  Connection handle to perform update on.
+ *
+ * @retval NRF_SUCCESS                    Store operation started.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  conn_handle does not refer to an active, bonded connection.
+ * @retval NRF_ERROR_DATA_SIZE            Write buffer not large enough. Call will never work with
+ *                                        this GATT database.
+ * @retval NRF_ERROR_NO_MEM               No room in persistent_storage. Free up space; the
+ *                                        operation will be automatically reattempted after the
+ *                                        next compression procedure
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ */
+ret_code_t gcm_local_db_cache_update(uint16_t conn_handle);
+
+
+/**@brief Function for setting new values in the local database cache.
+ *
+ * @note If the peer is connected, the values will also be applied immediately to the connection.
+ * @note This function is only needed when you want to override the regular functionality of the
+ *       module.
+ * @note The data in the pointer must be available until the GCM_EVT_LOCAL_DB_CACHE_SET event is
+ *       received.
+ *
+ * @param[in]  peer_id     Peer to set values for.
+ * @param[in]  p_local_db  Database values to apply. If NULL, the values will instead be cleared.
+ *
+ * @retval NRF_SUCCESS              Operation started, and values were applied (if connected).
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for retrieving values in the local database cache.
+ *
+ * @note This function is not needed for regular operation of the module.
+ *
+ * @param[in]  peer_id     Peer to get values for.
+ * @param[out] p_local_db  Database values.
+ *
+ * @retval NRF_SUCCESS              Values retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_local_db was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gcm_local_db_cache_get(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for manually informing that the local database has changed.
+ *
+ * @details This causes a service changed notification to be sent to all bonded peers that
+ *          subscribe to it.
+ */
+void gcm_local_database_has_changed(void);
+
+/** @}
+  * @endcond
+ */
+
+#endif /* GATT_CACHE_MANAGER_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.c
new file mode 100644
index 0000000000..e6b5469b41
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.c
@@ -0,0 +1,139 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "gattc_cache_manager.h"
+
+#include "nrf_ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+#include "id_manager.h"
+#include "sdk_common.h"
+
+#define MAX_SIMUL_SEC_PROCEDURES 2
+
+typedef struct
+{
+    gccm_evt_handler_t  evt_handler;
+} gccm_t;
+
+static gccm_t m_gccm;
+
+#define MODULE_INITIALIZED (m_gccm.evt_handler != NULL)
+#include "sdk_macros.h"
+
+static void internal_state_reset(gccm_t * gccm)
+{
+    memset(gccm, 0, sizeof(gccm_t));
+}
+
+
+/**@brief Event handler for events from the peer_database module.
+ *
+ * @param[in]  p_event The event that has happend with peer id and flags.
+ */
+static void pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    gccm_evt_t gccm_evt;
+    gccm_evt.evt_id  = GCCM_EVT_REMOTE_DB_STORED;
+    gccm_evt.peer_id = p_event->peer_id;
+    m_gccm.evt_handler(&gccm_evt);
+}
+
+
+ret_code_t gccm_init(gccm_evt_handler_t evt_handler)
+{
+    ret_code_t err_code;
+    if (evt_handler == NULL)
+    {
+        err_code = NRF_ERROR_NULL;
+    }
+    else
+    {
+        err_code = pdb_register(pdb_evt_handler);
+        if (err_code == NRF_SUCCESS)
+        {
+            internal_state_reset(&m_gccm);
+            m_gccm.evt_handler = evt_handler;
+        }
+    }
+    return err_code;
+}
+
+
+ret_code_t gccm_remote_db_store(pm_peer_id_t        peer_id,
+                                ble_gatt_db_srv_t * p_remote_db,
+                                uint32_t            n_services)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_remote_db);
+
+    // Initialize the peer_data
+    pm_peer_data_const_t peer_data;
+    memset(&peer_data, 0, sizeof(peer_data));
+    peer_data.data_id = PM_PEER_DATA_ID_GATT_REMOTE;
+    peer_data.p_remote_gatt_db = p_remote_db;
+    peer_data.length_words = PM_REMOTE_DB_N_WORDS(n_services);
+
+    return pdb_raw_store(peer_id, &peer_data, NULL);
+}
+
+
+ret_code_t gccm_remote_db_retrieve(pm_peer_id_t        peer_id,
+                                   ble_gatt_db_srv_t * p_remote_db,
+                                   uint32_t          * p_n_services)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_remote_db);
+    VERIFY_PARAM_NOT_NULL(p_n_services);
+
+    // Initialize the peer_data
+    pm_peer_data_t peer_data;
+    memset(&peer_data, 0, sizeof(peer_data));
+    peer_data.data_id = PM_PEER_DATA_ID_GATT_REMOTE;
+    peer_data.p_remote_gatt_db = p_remote_db;
+    peer_data.length_words = PM_REMOTE_DB_N_WORDS(*p_n_services);
+
+    ret_code_t err_code = pdb_raw_read(peer_id, PM_PEER_DATA_ID_GATT_REMOTE, &peer_data);
+
+    *p_n_services = PM_REMOTE_DB_N_SERVICES(peer_data.length_words);
+
+    return err_code;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.h
new file mode 100644
index 0000000000..abfca986a4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gattc_cache_manager.h
@@ -0,0 +1,132 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef GATTC_CACHE_MANAGER_H__
+#define GATTC_CACHE_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup gattc_cache_manager GATT Client Cache Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for managing persistent storing of GATT
+ *        attributes pertaining to the GATT client role of the local device.
+ */
+
+
+/**@brief Events that can come from the GATT Cache Manager module.
+ */
+typedef enum
+{
+    GCCM_EVT_REMOTE_DB_UPDATED,  /**< Values for the specified data has been updated in persistent storage. */
+    GCCM_EVT_REMOTE_DB_STORED,   /**< New values for the specified data has been written in persistent storage. */
+} gccm_evt_id_t;
+
+
+typedef struct
+{
+    gccm_evt_id_t  evt_id;
+    pm_peer_id_t   peer_id;
+} gccm_evt_t;
+
+/**@brief Event handler for events from the GATT Client Cache Manager module.
+ *
+ * @param[in]  event   The event that has happened.
+ * @param[in]  peer    The id of the peer the event pertains to.
+ * @param[in]  flags   The data the event pertains to.
+ */
+typedef void (*gccm_evt_handler_t)(gccm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the GATT Client Cache Manager module.
+ *
+ * @param[in]  evt_handler  Callback for events from the GATT Client Cache Manager module.
+ *
+ * @retval NRF_SUCCESS     Initialization was successful.
+ * @retval NRF_ERROR_NULL  evt_handler was NULL.
+ */
+ret_code_t gccm_init(gccm_evt_handler_t evt_handler);
+
+
+/**@brief Function for storing a discovered remote database persistently.
+ *
+ * @param[in]  peer_id      Peer to store the database for.
+ * @param[in]  p_remote_db  Database values to store as an array. Can be NULL if n_services is 0.
+ * @param[in]  n_services   Number of services in p_remote_db array. If 0, values are cleared.
+ *
+ * @retval NRF_SUCCESS              Store procedure successfully started.
+ * @retval NRF_ERROR_NOT_FOUND      The peer id is invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gccm_remote_db_store(pm_peer_id_t        peer_id,
+                                ble_gatt_db_srv_t * p_remote_db,
+                                uint32_t            n_services);
+
+
+/**@brief Function for retrieving a persistently stored remote database.
+ *
+ * @param[in]    peer_id       Peer to retrieve data for.
+ * @param[out]   p_remote_db  If p_n_services was large enough: Copied database values.
+ * @param[inout] p_n_services In: Size of provided p_remote_db array. Out: Size of data in flash.
+ *
+ * @note p_n_services is always updated with the size of the data to be retrieved. The data is only
+ *       copied if p_remote_db is large enough (p_n_services is large enough initially).
+ *
+ * @retval NRF_SUCCESS              Data retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID is invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gccm_remote_db_retrieve(pm_peer_id_t        peer_id,
+                                   ble_gatt_db_srv_t * p_remote_db,
+                                   uint32_t          * p_n_services);
+
+
+/** @}
+ * @endcond
+ */
+
+#endif /* GATTC_CACHE_MANAGER_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.c
new file mode 100644
index 0000000000..8cbca8e3f1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.c
@@ -0,0 +1,396 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "gatts_cache_manager.h"
+
+#include <string.h>
+#include "nrf_ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_database.h"
+#include "id_manager.h"
+#include "sdk_common.h"
+
+#define SYS_ATTR_SYS  (BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS) /**< Shorthand define for the flag for system attributes. */
+#define SYS_ATTR_USR  (BLE_GATTS_SYS_ATTR_FLAG_USR_SRVCS) /**< Shorthand define for the flag for user attributes. */
+#define SYS_ATTR_BOTH (SYS_ATTR_SYS | SYS_ATTR_USR)       /**< Shorthand define for the combined flags for system and user attributes. */
+
+
+/**@brief Structure containing the module variable(s) of the GSCM module.
+ */
+typedef struct
+{
+    gscm_evt_handler_t evt_handler; /**< The event handler to use for outbound GSCM events. */
+    pm_peer_id_t       current_sc_store_peer_id;
+} gscm_t;
+
+static gscm_t m_gscm =
+{
+    .current_sc_store_peer_id = PM_PEER_ID_INVALID,
+};  /**< Instantiation of module variable(s). */
+
+#define MODULE_INITIALIZED  (m_gscm.evt_handler != NULL)
+#include "sdk_macros.h"
+
+
+/**@brief Function for resetting the module variable(s) of the GSCM module.
+ *
+ * @param[out]  p_gscm  The instance to reset.
+ */
+static void internal_state_reset(gscm_t * p_gscm)
+{
+    memset(p_gscm, 0, sizeof(gscm_t));
+    p_gscm->current_sc_store_peer_id = PM_PEER_ID_INVALID;
+}
+
+
+//lint -save -e550
+/**@brief Function for storing service_changed_pending = true to flash for all peers, in sequence.
+ *
+ * This function aborts if it gets @ref NRF_ERROR_BUSY when trying to store. A subsequent call will
+ * continue where the last call was aborted.
+ */
+static void service_changed_pending_set(void)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+    static const bool service_changed_pending = true;
+    ret_code_t err_code;
+
+    //lint -save -e65 -e64
+    pm_peer_data_const_t peer_data =
+    {
+        .data_id                   = PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING,
+        .length_words              = PM_SC_STATE_N_WORDS(),
+        .p_service_changed_pending = &service_changed_pending,
+    };
+    //lint -restore
+
+    err_code = pdb_raw_store(m_gscm.current_sc_store_peer_id, &peer_data, NULL);
+    while((m_gscm.current_sc_store_peer_id != PM_PEER_ID_INVALID) && (err_code != NRF_ERROR_BUSY))
+    {
+        m_gscm.current_sc_store_peer_id = pdb_next_peer_id_get(m_gscm.current_sc_store_peer_id);
+        err_code = pdb_raw_store(m_gscm.current_sc_store_peer_id, &peer_data, NULL);
+    }
+}
+//lint -restore
+
+
+
+/**@brief Event handler for events from the peer_database module.
+ *
+ * @param[in]  p_event The event that has happend with peer id and flags.
+ */
+static void pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    if (p_event->evt_id == PDB_EVT_RAW_STORED)
+    {
+        if (p_event->data_id == PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING)
+        {
+            ret_code_t           err_code;
+            pm_peer_data_flash_t peer_data;
+
+            err_code = pdb_read_buf_get(p_event->peer_id, PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING, &peer_data, NULL);
+
+            if (err_code == NRF_SUCCESS)
+            {
+                gscm_evt_t gscm_evt;
+                gscm_evt.evt_id = GSCM_EVT_SC_STATE_STORED;
+                gscm_evt.peer_id = p_event->peer_id;
+                gscm_evt.params.sc_state_stored.state = &peer_data.p_service_changed_pending;
+
+                m_gscm.evt_handler(&gscm_evt);
+            }
+        }
+    }
+
+    if (m_gscm.current_sc_store_peer_id != PM_PEER_ID_INVALID)
+    {
+        service_changed_pending_set();
+    }
+}
+
+
+ret_code_t gscm_init(gscm_evt_handler_t evt_handler)
+{
+    ret_code_t err_code;
+    if (evt_handler == NULL)
+    {
+        err_code = NRF_ERROR_NULL;
+    }
+    else
+    {
+        err_code = pdb_register(pdb_evt_handler);
+        if (err_code == NRF_SUCCESS)
+        {
+            internal_state_reset(&m_gscm);
+            m_gscm.evt_handler  = evt_handler;
+        }
+    }
+    return err_code;
+}
+
+
+ret_code_t gscm_local_db_cache_update(uint16_t conn_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    pm_peer_id_t peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+    ret_code_t   err_code;
+
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+    else
+    {
+        pm_peer_data_t peer_data;
+        uint16_t       n_bufs = 1;
+        bool           retry_with_bigger_buffer = false;
+
+        do
+        {
+            retry_with_bigger_buffer = false;
+
+            err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_GATT_LOCAL, n_bufs++, &peer_data);
+            if (err_code == NRF_SUCCESS)
+            {
+                pm_peer_data_local_gatt_db_t * p_local_gatt_db = peer_data.p_local_gatt_db;
+
+                p_local_gatt_db->flags = SYS_ATTR_BOTH;
+
+                err_code = sd_ble_gatts_sys_attr_get(conn_handle, &p_local_gatt_db->data[0], &p_local_gatt_db->len, p_local_gatt_db->flags);
+
+                if (err_code == NRF_SUCCESS)
+                {
+                    err_code = pdb_write_buf_store(peer_id, PM_PEER_DATA_ID_GATT_LOCAL);
+                }
+                else
+                {
+                    if (err_code == NRF_ERROR_DATA_SIZE)
+                    {
+                        // The sys attributes are bigger than the requested write buffer.
+                        retry_with_bigger_buffer = true;
+                    }
+                    else if (err_code == NRF_ERROR_NOT_FOUND)
+                    {
+                        // There are no sys attributes in the GATT db, so nothing needs to be stored.
+                        err_code = NRF_SUCCESS;
+                    }
+
+                    ret_code_t err_code_release = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_GATT_LOCAL);
+                    if (err_code_release != NRF_SUCCESS)
+                    {
+                        err_code = NRF_ERROR_INTERNAL;
+                    }
+                }
+            }
+            else if (err_code == NRF_ERROR_INVALID_PARAM)
+            {
+                // The sys attributes are bigger than the entire write buffer.
+                err_code = NRF_ERROR_DATA_SIZE;
+            }
+        } while (retry_with_bigger_buffer);
+    }
+
+    return err_code;
+}
+
+
+ret_code_t gscm_local_db_cache_apply(uint16_t conn_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    pm_peer_id_t         peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+    ret_code_t           err_code;
+    pm_peer_data_flash_t peer_data;
+    uint8_t      const * p_sys_attr_data = NULL;
+    uint16_t             sys_attr_len    = 0;
+    uint32_t             sys_attr_flags  = (SYS_ATTR_BOTH);
+    bool                 all_attributes_applied = true;
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        err_code = pdb_read_buf_get(peer_id, PM_PEER_DATA_ID_GATT_LOCAL, &peer_data, NULL);
+        if (err_code == NRF_SUCCESS)
+        {
+            pm_peer_data_local_gatt_db_t const * p_local_gatt_db;
+
+            p_local_gatt_db = peer_data.p_local_gatt_db;
+            p_sys_attr_data = p_local_gatt_db->data;
+            sys_attr_len    = p_local_gatt_db->len;
+            sys_attr_flags  = p_local_gatt_db->flags;
+        }
+    }
+
+    do
+    {
+        err_code = sd_ble_gatts_sys_attr_set(conn_handle, p_sys_attr_data, sys_attr_len, sys_attr_flags);
+
+        if (err_code == NRF_ERROR_NO_MEM)
+        {
+            err_code = NRF_ERROR_BUSY;
+        }
+        else if (err_code == NRF_ERROR_INVALID_STATE)
+        {
+            err_code = NRF_SUCCESS;
+        }
+        else if (err_code == NRF_ERROR_INVALID_DATA)
+        {
+            all_attributes_applied = false;
+
+            if (sys_attr_flags & SYS_ATTR_USR)
+            {
+                // Try setting only system attributes.
+                sys_attr_flags = SYS_ATTR_SYS;
+            }
+            else if (p_sys_attr_data || sys_attr_len)
+            {
+                // Try reporting that none exist.
+                p_sys_attr_data = NULL;
+                sys_attr_len    = 0;
+                sys_attr_flags  = SYS_ATTR_BOTH;
+            }
+            else
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+    } while (err_code == NRF_ERROR_INVALID_DATA);
+
+    if (!all_attributes_applied)
+    {
+        err_code = NRF_ERROR_INVALID_DATA;
+    }
+
+    return err_code;
+}
+
+
+ret_code_t gscm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    pm_peer_data_const_t peer_data;
+
+    memset(&peer_data, 0, sizeof(pm_peer_data_const_t));
+    peer_data.data_id = PM_PEER_DATA_ID_GATT_LOCAL;
+    peer_data.p_local_gatt_db = p_local_db;
+
+    return pdb_raw_store(peer_id, &peer_data, NULL);
+}
+
+
+ret_code_t gscm_local_db_cache_get(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    pm_peer_data_t peer_data;
+    memset(&peer_data, 0, sizeof(pm_peer_data_t));
+    peer_data.p_local_gatt_db = p_local_db;
+
+    return pdb_raw_read(peer_id, PM_PEER_DATA_ID_GATT_LOCAL, &peer_data);
+}
+
+
+void gscm_local_database_has_changed(void)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+    m_gscm.current_sc_store_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    service_changed_pending_set();
+}
+
+
+bool gscm_service_changed_ind_needed(uint16_t conn_handle)
+{
+    ret_code_t err_code;
+    pm_peer_data_flash_t peer_data;
+    pm_peer_id_t peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+    err_code = pdb_read_buf_get(peer_id, PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING, &peer_data, NULL);
+
+    if (err_code != NRF_SUCCESS)
+    {
+        return false;
+    }
+
+    return &peer_data.p_service_changed_pending;
+}
+
+
+ret_code_t gscm_service_changed_ind_send(uint16_t conn_handle)
+{
+    static uint16_t start_handle = 0x0000;
+    const  uint16_t end_handle   = 0xFFFF;
+    ret_code_t err_code;
+
+    do
+    {
+        err_code = sd_ble_gatts_service_changed(conn_handle, start_handle, end_handle);
+        if (err_code == BLE_ERROR_INVALID_ATTR_HANDLE)
+        {
+            start_handle += 1;
+        }
+    } while (err_code == BLE_ERROR_INVALID_ATTR_HANDLE);
+
+    return err_code;
+}
+
+
+void gscm_db_change_notification_done(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+
+    static const bool service_changed_pending = false;
+
+    //lint -save -e65 -e64
+    pm_peer_data_const_t peer_data =
+    {
+        .data_id                   = PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING,
+        .length_words              = PM_SC_STATE_N_WORDS(),
+        .p_service_changed_pending = &service_changed_pending,
+    };
+    //lint -restore
+
+    // Don't need to check return code, because all error conditions can be ignored.
+    //lint -save -e550
+    (void) pdb_raw_store(peer_id, &peer_data, NULL);
+    //lint -restore
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.h
new file mode 100644
index 0000000000..6c6b3f8baa
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/gatts_cache_manager.h
@@ -0,0 +1,228 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef GATTS_CACHE_MANAGER_H__
+#define GATTS_CACHE_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup gatts_cache_manager GATT Server Cache Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for managing persistent storing of GATT
+ *        attributes pertaining to the GATT server role of the local device.
+ */
+
+
+/**@brief Events that can come from the GATT Server Cache Manager module.
+ */
+typedef enum
+{
+    GSCM_EVT_LOCAL_DB_CACHE_STORED,  /**< The persistent cache for the local database has been updated with provided values, for one peer. */
+    GSCM_EVT_LOCAL_DB_CACHE_UPDATED, /**< The persistent cache for the local database has been updated with values from the SoftDevice, for one peer. */
+    GSCM_EVT_SC_STATE_STORED,        /**< The service changed pending flag in persistent storage has been updated, for one peer. */
+} gscm_evt_id_t;
+
+
+/**@brief Structure containing an event from the GSCM module.
+ */
+typedef struct
+{
+    gscm_evt_id_t evt_id;          /**< The type of event this is. */
+    pm_peer_id_t  peer_id;         /**< The peer ID this event pertains to. */
+    union
+    {
+        struct
+        {
+            uint16_t conn_handle;  /**< The connection this event pertains to. */
+        } local_db_cache_updated;
+        struct
+        {
+            bool state;            /**< The newly stored state of the Service Changed pending flag. */
+        } sc_state_stored;
+    } params;                      /**< Event parameters specific to certain event types. */
+} gscm_evt_t;
+
+/**@brief Event handler for events from the GATT Server Cache Manager module.
+ *
+ * @param[in]  event   The event that has happened.
+ * @param[in]  peer  The id of the peer the event pertains to.
+ * @param[in]  flags   The data the event pertains to.
+ */
+typedef void (*gscm_evt_handler_t)(gscm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the GATT Server Cache Manager module.
+ *
+ * @param[in]  evt_handler  Callback for events from the GATT Server Cache Manager module.
+ *
+ * @retval NRF_SUCCESS         Initialization was successful.
+ * @retval NRF_ERROR_NULL      evt_handler was NULL.
+ */
+ret_code_t gscm_init(gscm_evt_handler_t evt_handler);
+
+
+/**@brief Function for triggering local GATT database data to be stored persistently. Values are
+ *        retrieved from the SoftDevice and written to persistent storage.
+ *
+ * @param[in]  conn_handle  Connection handle to perform update on.
+ *
+ * @retval NRF_SUCCESS                    Store operation started.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  conn_handle does not refer to an active connection with a
+ *                                        bonded peer.
+ * @retval NRF_ERROR_BUSY                 Unable to perform operation at this time. Reattempt later.
+ * @retval NRF_ERROR_DATA_SIZE            Write buffer not large enough. Call will never work with
+ *                                        this GATT database.
+ * @retval NRF_ERROR_NO_MEM               No room in persistent_storage. Free up space; the
+ *                                        operation will be automatically reattempted after the
+ *                                        next compression procedure
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ */
+ret_code_t gscm_local_db_cache_update(uint16_t conn_handle);
+
+
+/**@brief Function for applying stored local GATT database data to the SoftDevice. Values are
+ *        retrieved from persistent storage and given to the SoftDevice.
+ *
+ * @param[in]  conn_handle  Connection handle to apply values to.
+ *
+ * @retval NRF_SUCCESS                    Store operation started.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  conn_handle does not refer to an active connection with a
+ *                                        bonded peer.
+ * @retval NRF_ERROR_INVALID_DATA         The stored data was rejected by the SoftDevice, which
+ *                                        probably means that the local database has changed. The
+ *                                        system part of the sys_attributes was attempted applied,
+ *                                        so service changed indications can be sent to subscribers.
+ * @retval NRF_ERROR_BUSY                 Unable to perform operation at this time. Reattempt later.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ * @return An unexpected return value from an internal function call.
+ */
+ret_code_t gscm_local_db_cache_apply(uint16_t conn_handle);
+
+
+/**@brief Function for setting new values in the local database cache.
+ *
+ * @note If the peer is connected, the values will also be applied immediately to the connection.
+ * @note The data in the pointer must be available until the GSCM_EVT_LOCAL_DB_STORED event is
+ *       received.
+ *
+ * @param[in]  peer_id     Peer to set values for.
+ * @param[in]  p_local_db  Database values to apply. If NULL, the values will instead be cleared.
+ *
+ * @retval NRF_SUCCESS              Operation started, and values were applied (if connected).
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @return An unexpected return value from an internal function call.
+ */
+ret_code_t gscm_local_db_cache_set(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for retrieving values in the local database cache.
+ *
+ * @param[in]    peer_id     Peer to get values for.
+ * @param[inout] p_local_db  Where to store the data. The length field needs to reflect the
+ *                           available buffer space. On a successful read, the length field is
+ *                           updated to match the length of the read data.
+ *
+ * @retval NRF_SUCCESS              Values retrieved successfully.
+ * @retval NRF_ERROR_NOT_FOUND      The peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_local_db was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t gscm_local_db_cache_get(pm_peer_id_t peer_id, pm_peer_data_local_gatt_db_t * p_local_db);
+
+
+/**@brief Function for storing the fact that the local database has changed, for all currently
+ *        bonded peers.
+ *
+ * @note This will cause a later call to @ref gscm_service_changed_ind_needed to return true for
+ *       a connection with a currently bonded peer.
+ */
+void gscm_local_database_has_changed(void);
+
+
+/**@brief Function for checking if a service changed indication should be sent.
+ *
+ * @param[in]  conn_handle  The connection to check.
+ *
+ * @return true if a service changed indication should be sent, false if not.
+ */
+bool gscm_service_changed_ind_needed(uint16_t conn_handle);
+
+
+/**@brief Function for sending a service changed indication to a connected peer.
+ *
+ * @param[in]  conn_handle  The connection to send the indication on.
+ *
+ * @retval NRF_SUCCESS                       Indication sent or not needed.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE     conn_handle does not refer to an active connection.
+ * @retval NRF_ERROR_BUSY                    Unable to send indication at this time. Reattempt later.
+ * @retval BLE_ERROR_GATTS_SYS_ATTR_MISSING  Information missing. Apply local cache, then reattempt.
+ * @retval NRF_ERROR_INVALID_PARAM           From @ref sd_ble_gatts_service_changed. Unexpected.
+ * @retval NRF_ERROR_NOT_SUPPORTED           Service changed characteristic is not present.
+ * @retval NRF_ERROR_INVALID_STATE           Service changed cannot be indicated to this peer
+ *                                           because the peer has not subscribed to it.
+ */
+ret_code_t gscm_service_changed_ind_send(uint16_t conn_handle);
+
+
+/**@brief Function for specifying that a peer has been made aware of the latest local database
+ *        change.
+ *
+ * @note After calling this, a later call to @ref gscm_service_changed_ind_needed will to return
+ *       false for this peer unless @ref gscm_local_database_has_changed is called again.
+ *
+ * @param[in]  peer_id  The connection to send the indication on.
+ */
+void gscm_db_change_notification_done(pm_peer_id_t peer_id);
+
+/** @}
+ * @endcond
+*/
+
+#endif /* GATTS_CACHE_MANAGER_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.c
new file mode 100644
index 0000000000..94bc363ef6
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.c
@@ -0,0 +1,758 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "id_manager.h"
+
+#include <string.h>
+#include "nrf_soc.h"
+#include "nrf_ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+#include "nordic_common.h"
+#include "sdk_common.h"
+
+#define IM_MAX_CONN_HANDLES         8
+#define IM_NO_INVALID_CONN_HANDLES  0xFF
+#define MAX_REGISTRANTS             3
+#define WHITELIST_MAX_COUNT         MAX(BLE_GAP_WHITELIST_ADDR_MAX_COUNT, \
+                                        BLE_GAP_WHITELIST_IRK_MAX_COUNT)
+#define IM_ADDR_CLEARTEXT_LENGTH    3
+#define IM_ADDR_CIPHERTEXT_LENGTH   3
+
+typedef struct
+{
+    pm_peer_id_t   peer_id;
+    uint16_t       conn_handle;
+    ble_gap_addr_t peer_address;
+} im_connection_t;
+
+typedef struct
+{
+    im_evt_handler_t              evt_handlers[MAX_REGISTRANTS];
+    uint8_t                       n_registrants;
+    im_connection_t               connections[8];
+    pm_peer_id_t                  irk_whitelist_peer_ids[BLE_GAP_WHITELIST_IRK_MAX_COUNT];
+    ble_gap_irk_t                 whitelist_irks[BLE_GAP_WHITELIST_IRK_MAX_COUNT];
+    ble_gap_addr_t                whitelist_addrs[BLE_GAP_WHITELIST_ADDR_MAX_COUNT];
+    uint8_t                       n_irk_whitelist_peer_ids;
+    ble_conn_state_user_flag_id_t conn_state_user_flag_id;
+} im_t;
+
+static im_t m_im = {.n_registrants = 0};
+
+#define MODULE_INITIALIZED (m_im.n_registrants > 0)
+#include "sdk_macros.h"
+
+static void internal_state_reset()
+{
+    memset(&m_im, 0, sizeof(im_t));
+    m_im.n_registrants = 0;
+    m_im.n_irk_whitelist_peer_ids = 0;
+    m_im.conn_state_user_flag_id = BLE_CONN_STATE_USER_FLAG_INVALID;
+    for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+    {
+        m_im.connections[i].conn_handle = BLE_CONN_HANDLE_INVALID;
+    }
+}
+
+
+/**@brief Function for sending an event to all registered event handlers.
+ *
+ * @param[in] p_event The event to distribute.
+ */
+static void evt_send(im_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < m_im.n_registrants; i++)
+    {
+        m_im.evt_handlers[i](p_event);
+    }
+}
+
+/**@brief Function finding a free position in m_im.connections.
+ *
+ * @detail All connection handles in the m_im.connections array are checked against the connection
+ *         state module. The index of the first one that is not a connection handle for a current
+ *         connection is returned. This position in the array can safely be used for a new connection.
+ *
+ * @return Either the index of a free position in the array or IM_NO_INVALID_CONN_HANDLES if no free
+           position exists.
+ */
+uint8_t get_free_connection()
+{
+    for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+    {
+        // Query the connection state module to check if the connection handle does not belong to a
+        // valid connection.
+        if (!ble_conn_state_user_flag_get(m_im.connections[i].conn_handle, m_im.conn_state_user_flag_id))
+        {
+            return i;
+        }
+    }
+    // If all connection handles belong to a valid connection, return IM_NO_INVALID_CONN_HANDLES.
+    return IM_NO_INVALID_CONN_HANDLES;
+}
+
+
+/**@brief Function finding a particular connection handle m_im.connections.
+ *
+ * @param[in]  conn_handle  The handle to find.
+ *
+ * @return Either the index of the conn_handle in the array or IM_NO_INVALID_CONN_HANDLES if the
+ *         handle was not found.
+ */
+uint8_t get_connection_by_conn_handle(uint16_t conn_handle)
+{
+    if (ble_conn_state_user_flag_get(conn_handle, m_im.conn_state_user_flag_id))
+    {
+        for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+        {
+            if (m_im.connections[i].conn_handle == conn_handle)
+            {
+                return i;
+            }
+        }
+    }
+    // If all connection handles belong to a valid connection, return IM_NO_INVALID_CONN_HANDLES.
+    return IM_NO_INVALID_CONN_HANDLES;
+}
+
+
+/**@brief Function for registering a new connection instance.
+ *
+ * @param[in]  conn_handle  The handle of the new connection.
+ * @param[in]  p_ble_addr   The address used to connect.
+ *
+ * @return Either the index of the new connection in the array or IM_NO_INVALID_CONN_HANDLES if no
+ *         free position exists.
+ */
+uint8_t new_connection(uint16_t conn_handle, ble_gap_addr_t * p_ble_addr)
+{
+    uint8_t conn_index = IM_NO_INVALID_CONN_HANDLES;
+
+    if ((p_ble_addr != NULL) && (conn_handle != BLE_CONN_HANDLE_INVALID))
+    {
+        ble_conn_state_user_flag_set(conn_handle, m_im.conn_state_user_flag_id, true);
+
+        conn_index = get_connection_by_conn_handle(conn_handle);
+        if (conn_index == IM_NO_INVALID_CONN_HANDLES)
+        {
+            conn_index = get_free_connection();
+        }
+
+        if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+        {
+            m_im.connections[conn_index].conn_handle  = conn_handle;
+            m_im.connections[conn_index].peer_id      = PM_PEER_ID_INVALID;
+            m_im.connections[conn_index].peer_address = *p_ble_addr;
+        }
+    }
+    return conn_index;
+}
+
+
+/**@brief Function checking the validity of an IRK
+ *
+ * @detail An all-zero IRK is not valid. This function will check if a given IRK is valid.
+ *
+ * @param[in] irk The IRK for which the validity is going to be checked.
+ *
+ * @retval true  The IRK is valid.
+ * @retval false The IRK is invalid.
+ */
+bool is_valid_irk(ble_gap_irk_t const * irk)
+{
+    for (uint32_t i = 0; i < BLE_GAP_SEC_KEY_LEN; i++)
+    {
+        if (irk->irk[i] != 0)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+
+/**@brief Function for comparing two addresses to determine if they are identical
+ *
+ * @note The address type need to be identical, as well as every bit in the address itself.
+ *
+ * @param[in] p_addr1 The first address to be compared.
+ * @param[in] p_addr2 The second address to be compared.
+ *
+ * @retval true  The addresses are identical.
+ * @retval false The addresses are not identical.
+ */
+bool addr_compare(ble_gap_addr_t const * p_addr1, ble_gap_addr_t const * p_addr2)
+{
+    if ((p_addr1 == NULL) || (p_addr2 == NULL))
+    {
+        return false;
+    }
+
+    // Check that the addr type is identical, return false if it is not
+    if (p_addr1->addr_type != p_addr2->addr_type)
+    {
+        return false;
+    }
+    // Check if the addr bytes are is identical
+    return (memcmp(p_addr1->addr, p_addr2->addr, BLE_GAP_ADDR_LEN) == 0);
+}
+
+
+void im_ble_evt_handler(ble_evt_t * ble_evt)
+{
+    ret_code_t err_code;
+    switch (ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_CONNECTED:
+        {
+            pm_peer_id_t bonded_matching_peer_id = PM_PEER_ID_INVALID;
+
+            if (ble_evt->evt.gap_evt.params.connected.irk_match == 1)
+            {
+                // The peer was matched using a whitelist.
+                bonded_matching_peer_id
+                        = m_im.irk_whitelist_peer_ids[ble_evt->evt.gap_evt.params.connected.irk_match_idx];
+            }
+            else if (   ble_evt->evt.gap_evt.params.connected.peer_addr.addr_type
+                     != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE)
+            {
+                /* Search the database for bonding data matching the one that triggered the event.
+                 * Public and static addresses can be matched on address alone, while resolvable
+                 * random addresses can be resolved agains known IRKs. Non-resolvable random addresses
+                 * are never matching because they are not longterm form of identification.
+                 */
+                pm_peer_id_t compared_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+                while (   (compared_peer_id        != PM_PEER_ID_INVALID)
+                       && (bonded_matching_peer_id == PM_PEER_ID_INVALID))
+                {
+                    pm_peer_data_flash_t compared_data;
+                    switch (ble_evt->evt.gap_evt.params.connected.peer_addr.addr_type)
+                    {
+                        case BLE_GAP_ADDR_TYPE_PUBLIC:
+                            /* fall-through */
+                        case BLE_GAP_ADDR_TYPE_RANDOM_STATIC:
+                            err_code = pdb_read_buf_get(compared_peer_id,
+                                                        PM_PEER_DATA_ID_BONDING,
+                                                        &compared_data,
+                                                        NULL);
+                            if ((err_code == NRF_SUCCESS) &&
+                                addr_compare(&ble_evt->evt.gap_evt.params.connected.peer_addr,
+                                             &compared_data.p_bonding_data->peer_id.id_addr_info)
+                            )
+                            {
+                                bonded_matching_peer_id = compared_peer_id;
+                            }
+                            break;
+
+                        case BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE:
+                            err_code = pdb_read_buf_get(compared_peer_id,
+                                                        PM_PEER_DATA_ID_BONDING,
+                                                        &compared_data,
+                                                        NULL);
+                            if (err_code == NRF_SUCCESS &&
+                                im_address_resolve(&ble_evt->evt.gap_evt.params.connected.peer_addr,
+                                                   &compared_data.p_bonding_data->peer_id.id_info)
+                            )
+                            {
+                                bonded_matching_peer_id = compared_peer_id;
+                            }
+                            break;
+
+                        case BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE:
+                            // Should not happen.
+                            break;
+
+                        default:
+                            break;
+                    }
+                    compared_peer_id = pdb_next_peer_id_get(compared_peer_id);
+                }
+            }
+            uint8_t new_index = new_connection(ble_evt->evt.gap_evt.conn_handle, &ble_evt->evt.gap_evt.params.connected.peer_addr);
+            UNUSED_VARIABLE(new_index);
+
+            if (bonded_matching_peer_id != PM_PEER_ID_INVALID)
+            {
+                im_new_peer_id(ble_evt->evt.gap_evt.conn_handle, bonded_matching_peer_id);
+
+                // Send a bonded peer event
+                im_evt_t im_evt;
+                im_evt.conn_handle = ble_evt->evt.gap_evt.conn_handle;
+                im_evt.evt_id = IM_EVT_BONDED_PEER_CONNECTED;
+                evt_send(&im_evt);
+            }
+        }
+    }
+}
+
+
+/**@brief Function to compare two sets of bonding data to check if they belong to the same device.
+ * @note  Invalid irks will never match even though they are identical.
+ *
+ * @param[in]  p_bonding_data1 First bonding data for comparison
+ * @param[in]  p_bonding_data2 Second bonding data for comparison
+ *
+ * @return     True if the input matches, false if it does not.
+ */
+bool is_duplicate_bonding_data(pm_peer_data_bonding_t const * p_bonding_data1,
+                               pm_peer_data_bonding_t const * p_bonding_data2)
+{
+    bool valid_irk = is_valid_irk(&p_bonding_data1->peer_id.id_info);
+    bool duplicate_irk = valid_irk &&
+        (memcmp(p_bonding_data1->peer_id.id_info.irk,
+        p_bonding_data2->peer_id.id_info.irk,
+        BLE_GAP_SEC_KEY_LEN) == 0
+    );
+    bool duplicate_addr = addr_compare(&p_bonding_data1->peer_id.id_addr_info,
+                                       &p_bonding_data2->peer_id.id_addr_info
+    );
+    return duplicate_irk || duplicate_addr;
+}
+
+
+/**@brief Event handler for events from the peer_database module.
+ *
+ * @param[in]  p_event The event that has happend with peer id and flags.
+ */
+static void pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    ret_code_t err_code;
+    if ((p_event != NULL) && (p_event->evt_id == PDB_EVT_WRITE_BUF_STORED))
+    {
+        // If new data about peer id has been stored it is compared to other peers peer ids in
+        // search of duplicates.
+        if (p_event->data_id == PM_PEER_DATA_ID_BONDING)
+        {
+            pm_peer_data_flash_t written_data;
+            err_code = pdb_read_buf_get(p_event->peer_id, PM_PEER_DATA_ID_BONDING, &written_data, NULL);
+            if (err_code == NRF_SUCCESS)
+            {
+                pm_peer_id_t compared_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+                while (compared_peer_id != PM_PEER_ID_INVALID)
+                {
+                    pm_peer_data_flash_t compared_data;
+                    err_code = pdb_read_buf_get(compared_peer_id,
+                                                PM_PEER_DATA_ID_BONDING,
+                                                &compared_data,
+                                                NULL);
+                    if ( err_code == NRF_SUCCESS &&
+                        p_event->peer_id != compared_peer_id &&
+                        is_duplicate_bonding_data(written_data.p_bonding_data,
+                                                  compared_data.p_bonding_data)
+                    )
+                    {
+                        im_evt_t im_evt;
+                        im_evt.conn_handle = im_conn_handle_get(p_event->peer_id);
+                        im_evt.evt_id = IM_EVT_DUPLICATE_ID;
+                        im_evt.params.duplicate_id.peer_id_1 = p_event->peer_id;
+                        im_evt.params.duplicate_id.peer_id_2 = compared_peer_id;
+                        evt_send(&im_evt);
+                    }
+                    compared_peer_id = pdb_next_peer_id_get(compared_peer_id);
+                }
+            }
+        }
+    }
+}
+
+
+ret_code_t im_register(im_evt_handler_t evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!MODULE_INITIALIZED)
+    {
+        internal_state_reset();
+        m_im.conn_state_user_flag_id = ble_conn_state_user_flag_acquire();
+        if (m_im.conn_state_user_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+        {
+            err_code = NRF_ERROR_NO_MEM;
+        }
+        else
+        {
+            err_code = pdb_register(pdb_evt_handler);
+        }
+    }
+    if (err_code == NRF_SUCCESS)
+    {
+        if ((m_im.n_registrants < MAX_REGISTRANTS))
+        {
+            m_im.evt_handlers[m_im.n_registrants++] = evt_handler;
+        }
+        else
+        {
+            err_code = NRF_ERROR_NO_MEM;
+        }
+    }
+    return err_code;
+}
+
+
+pm_peer_id_t im_peer_id_get_by_conn_handle(uint16_t conn_handle)
+{
+    uint8_t conn_index = get_connection_by_conn_handle(conn_handle);
+
+    if (MODULE_INITIALIZED && (conn_index != IM_NO_INVALID_CONN_HANDLES))
+    {
+        return m_im.connections[conn_index].peer_id;
+    }
+
+    return PM_PEER_ID_INVALID;
+}
+
+
+ret_code_t im_ble_addr_get(uint16_t conn_handle, ble_gap_addr_t * p_ble_addr)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_ble_addr);
+
+    uint8_t conn_index = get_connection_by_conn_handle(conn_handle);
+    if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+    {
+        *p_ble_addr = m_im.connections[conn_index].peer_address;
+        return NRF_SUCCESS;
+    }
+
+    return NRF_ERROR_NOT_FOUND;
+}
+
+
+bool im_master_ids_compare(ble_gap_master_id_t const * p_master_id1,
+                           ble_gap_master_id_t const * p_master_id2)
+{
+    if(!im_master_id_is_valid(p_master_id1))
+    {
+        return false;
+    }
+    if (p_master_id1->ediv != p_master_id2->ediv)
+    {
+        return false;
+    }
+    return (memcmp(p_master_id1->rand, p_master_id2->rand, BLE_GAP_SEC_RAND_LEN) == 0);
+}
+
+
+pm_peer_id_t im_peer_id_get_by_master_id(ble_gap_master_id_t * p_master_id)
+{
+    ret_code_t err_code;
+    // For each stored peer, check if the master_id match p_master_id
+    pm_peer_id_t compared_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    while (compared_peer_id != PM_PEER_ID_INVALID)
+    {
+        pm_peer_data_flash_t        compared_data;
+        ble_gap_master_id_t const * p_compared_master_id;
+
+        err_code = pdb_read_buf_get(compared_peer_id, PM_PEER_DATA_ID_BONDING, &compared_data, NULL);
+        if (err_code == NRF_SUCCESS)
+        {
+            p_compared_master_id = &compared_data.p_bonding_data->own_ltk.master_id;
+            if (im_master_ids_compare(p_master_id, p_compared_master_id))
+            {
+                // If a matching master_id is found return the peer_id
+                return compared_peer_id;
+            }
+            p_compared_master_id = &compared_data.p_bonding_data->peer_ltk.master_id;
+            if (im_master_ids_compare(p_master_id, p_compared_master_id))
+            {
+                // If a matching master_id is found return the peer_id
+                return compared_peer_id;
+            }
+        }
+        compared_peer_id = pdb_next_peer_id_get(compared_peer_id);
+    }
+    // If no matching master_id is found return the PM_PEER_ID_INVALID
+    return PM_PEER_ID_INVALID;
+}
+
+
+pm_peer_id_t im_peer_id_get_by_irk_match_idx(uint8_t irk_match_idx)
+{
+    // Verify that the requested idx is within the list
+    if (irk_match_idx < m_im.n_irk_whitelist_peer_ids)
+    {
+        // Return the peer_id from the white list
+        return m_im.irk_whitelist_peer_ids[irk_match_idx];
+    }
+    else
+    {
+        // Return PM_PEER_ID_INVALID to indicate that there was no peer with the requested idx
+        return PM_PEER_ID_INVALID;
+    }
+}
+
+
+uint16_t im_conn_handle_get(pm_peer_id_t peer_id)
+{
+    for (uint32_t i = 0; i < IM_MAX_CONN_HANDLES; i++)
+    {
+        if (peer_id == m_im.connections[i].peer_id)
+        {
+            return m_im.connections[i].conn_handle;
+        }
+    }
+    return BLE_CONN_HANDLE_INVALID;
+}
+
+
+bool im_master_id_is_valid(ble_gap_master_id_t const * p_master_id)
+{
+    if (p_master_id->ediv != 0)
+    {
+        return true;
+    }
+    for (uint32_t i = 0; i < BLE_GAP_SEC_RAND_LEN; i++)
+    {
+        if (p_master_id->rand[i] != 0)
+        {
+            return true;
+        }
+    }
+    return false;
+}
+
+
+/**@brief Function to set the peer ID associated with a connection handle.
+ *
+ * @param[in]  conn_handle  The connection handle.
+ * @param[in]  peer_id      The peer ID to associate with @c conn_handle.
+ */
+static void peer_id_set(uint16_t conn_handle, pm_peer_id_t peer_id)
+{
+    uint8_t conn_index = get_connection_by_conn_handle(conn_handle);
+    if (conn_index != IM_NO_INVALID_CONN_HANDLES)
+    {
+        m_im.connections[conn_index].peer_id = peer_id;
+    }
+}
+
+
+void im_new_peer_id(uint16_t conn_handle, pm_peer_id_t peer_id)
+{
+    peer_id_set(conn_handle, peer_id);
+}
+
+
+ret_code_t im_peer_free(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    uint16_t   conn_handle = im_conn_handle_get(peer_id);
+    ret_code_t err_code    = pdb_peer_free(peer_id);
+    if ((conn_handle != BLE_CONN_HANDLE_INVALID) && (err_code == NRF_SUCCESS))
+    {
+        peer_id_set(conn_handle, PM_PEER_ID_INVALID);
+    }
+    return err_code;
+}
+
+
+ret_code_t im_whitelist_create(pm_peer_id_t *        p_peer_ids,
+                               uint8_t               n_peer_ids,
+                               ble_gap_whitelist_t * p_whitelist)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_whitelist);
+    ret_code_t err_code;
+    p_whitelist->addr_count = 0;
+    p_whitelist->irk_count = 0;
+    m_im.n_irk_whitelist_peer_ids = 0;
+    for (uint32_t peer_index = 0; peer_index < n_peer_ids; peer_index++)
+    {
+        uint16_t conn_handle = im_conn_handle_get(p_peer_ids[peer_index]);
+        if (ble_conn_state_status(conn_handle) != BLE_CONN_STATUS_CONNECTED)
+        {
+            pm_peer_data_flash_t peer_data;
+            err_code = pdb_read_buf_get(p_peer_ids[peer_index], PM_PEER_DATA_ID_BONDING, &peer_data, NULL);
+            if (err_code == NRF_ERROR_INVALID_PARAM || err_code == NRF_ERROR_NOT_FOUND)
+            {
+                return NRF_ERROR_INVALID_PARAM;
+            }
+            if (p_whitelist->pp_addrs != NULL &&
+                peer_data.p_bonding_data->peer_id.id_addr_info.addr_type
+                        != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE &&
+                peer_data.p_bonding_data->peer_id.id_addr_info.addr_type
+                        != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_NON_RESOLVABLE
+            )
+            {
+                memcpy(m_im.whitelist_addrs[peer_index].addr,
+                    peer_data.p_bonding_data->peer_id.id_addr_info.addr,
+                    BLE_GAP_ADDR_LEN
+                );
+                m_im.whitelist_addrs[peer_index].addr_type =
+                    peer_data.p_bonding_data->peer_id.id_addr_info.addr_type;
+                p_whitelist->pp_addrs[peer_index] = &m_im.whitelist_addrs[peer_index];
+                p_whitelist->addr_count++;
+            }
+            if (p_whitelist->pp_irks != NULL &&
+                is_valid_irk(&(peer_data.p_bonding_data->peer_id.id_info))
+            )
+            {
+                memcpy(m_im.whitelist_irks[peer_index].irk,
+                    peer_data.p_bonding_data->peer_id.id_info.irk,
+                    BLE_GAP_SEC_KEY_LEN
+                );
+                p_whitelist->pp_irks[peer_index] = &m_im.whitelist_irks[peer_index];
+                p_whitelist->irk_count++;
+                m_im.irk_whitelist_peer_ids[peer_index] = p_peer_ids[peer_index];
+                m_im.n_irk_whitelist_peer_ids++;
+            }
+        }
+    }
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t im_whitelist_custom(ble_gap_whitelist_t const * p_whitelist)
+{
+    ret_code_t err_code;
+
+    pm_peer_id_t new_irk_whitelist_peer_ids[BLE_GAP_WHITELIST_IRK_MAX_COUNT];
+    uint32_t n_new_irk_whitelist_peer_ids = 0;
+    VERIFY_PARAM_NOT_NULL(p_whitelist);
+    for (uint32_t i = 0; i < BLE_GAP_WHITELIST_IRK_MAX_COUNT; i++)
+    {
+        new_irk_whitelist_peer_ids[i] = PM_PEER_ID_INVALID;
+    }
+    pm_peer_id_t compared_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    while (compared_peer_id != PM_PEER_ID_INVALID)
+    {
+        pm_peer_data_flash_t compared_data;
+        err_code = pdb_read_buf_get(compared_peer_id, PM_PEER_DATA_ID_BONDING, &compared_data, NULL);
+        if (err_code == NRF_SUCCESS)
+        {
+            for (uint32_t i = 0; i < p_whitelist->irk_count; i++)
+            {
+                bool valid_irk = is_valid_irk(&compared_data.p_bonding_data->peer_id.id_info);
+                bool duplicate_irk = valid_irk &&
+                    (memcmp(p_whitelist->pp_irks[i]->irk,
+                    compared_data.p_bonding_data->peer_id.id_info.irk,
+                    BLE_GAP_SEC_KEY_LEN) == 0
+                );
+                if (duplicate_irk)
+                {
+                    new_irk_whitelist_peer_ids[i] = compared_peer_id;
+                    n_new_irk_whitelist_peer_ids++;
+                }
+            }
+        }
+        compared_peer_id = pdb_next_peer_id_get(compared_peer_id);
+    }
+    if (n_new_irk_whitelist_peer_ids != p_whitelist->irk_count)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+    else
+    {
+        for (uint32_t i = 0; i < n_new_irk_whitelist_peer_ids; i++)
+        {
+            m_im.irk_whitelist_peer_ids[i] = new_irk_whitelist_peer_ids[i];
+        }
+        m_im.n_irk_whitelist_peer_ids = n_new_irk_whitelist_peer_ids;
+        return NRF_SUCCESS;
+    }
+}
+
+
+/**@brief Function for calculating the ah() hash function described in Bluetooth core specification
+ *        4.2 section 3.H.2.2.2.
+ *
+ * @detail  BLE uses a hash function to calculate the first half of a resolvable address
+ *          from the second half of the address and an irk. This function will use the ECB
+ *          periferal to hash these data acording to the Bluetooth core specification.
+ *
+ * @note The ECB expect little endian input and output.
+ *       This function expect big endian and will reverse the data as necessary.
+ *
+ * @param[in]  p_k          The key used in the hash function.
+ *                          For address resolution this is should be the irk.
+ *                          The array must have a length of 16.
+ * @param[in]  p_r          The rand used in the hash function. For generating a new address
+ *                          this would be a random number. For resolving a resolvable address
+ *                          this would be the last half of the address being resolved.
+ *                          The array must have a length of 3.
+ * @param[out] p_local_hash The result of the hash operation. For address resolution this
+ *                          will match the first half of the address being resolved if and only
+ *                          if the irk used in the hash function is the same one used to generate
+ *                          the address.
+ *                          The array must have a length of 16.
+ */
+void ah(uint8_t const * p_k, uint8_t const * p_r, uint8_t * p_local_hash)
+{
+    ret_code_t err_code;
+    nrf_ecb_hal_data_t ecb_hal_data;
+    for (uint32_t i = 0; i < SOC_ECB_KEY_LENGTH; i++)
+    {
+        ecb_hal_data.key[i] = p_k[SOC_ECB_KEY_LENGTH - 1 - i];
+    }
+    memset(ecb_hal_data.cleartext, 0, SOC_ECB_KEY_LENGTH - IM_ADDR_CLEARTEXT_LENGTH);
+
+    for (uint32_t i = 0; i < IM_ADDR_CLEARTEXT_LENGTH; i++)
+    {
+        ecb_hal_data.cleartext[SOC_ECB_KEY_LENGTH - 1 - i] = p_r[i];
+    }
+
+    err_code = sd_ecb_block_encrypt(&ecb_hal_data); // Can only return NRF_SUCCESS.
+    UNUSED_VARIABLE(err_code);
+
+    for (uint32_t i = 0; i < IM_ADDR_CIPHERTEXT_LENGTH; i++)
+    {
+        p_local_hash[i] = ecb_hal_data.ciphertext[SOC_ECB_KEY_LENGTH - 1 - i];
+    }
+}
+
+
+bool im_address_resolve(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk)
+{
+    if (p_addr->addr_type != BLE_GAP_ADDR_TYPE_RANDOM_PRIVATE_RESOLVABLE)
+    {
+        return false;
+    }
+    uint8_t hash[IM_ADDR_CIPHERTEXT_LENGTH];
+    uint8_t local_hash[IM_ADDR_CIPHERTEXT_LENGTH];
+    uint8_t prand[IM_ADDR_CLEARTEXT_LENGTH];
+    memcpy(hash, p_addr->addr, IM_ADDR_CIPHERTEXT_LENGTH);
+    memcpy(prand, &p_addr->addr[IM_ADDR_CIPHERTEXT_LENGTH], IM_ADDR_CLEARTEXT_LENGTH);
+    ah(p_irk->irk, prand, local_hash);
+
+    return (memcmp(hash, local_hash, IM_ADDR_CIPHERTEXT_LENGTH) == 0);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.h
new file mode 100644
index 0000000000..27434bff3a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/id_manager.h
@@ -0,0 +1,301 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef PEER_ID_MANAGER_H__
+#define PEER_ID_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup id_manager ID Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for keeping track of peer identities
+ *       (IRK and peer address).
+ */
+
+
+/**@brief Events that can come from the ID Manager module.
+ */
+typedef enum
+{
+    IM_EVT_DUPLICATE_ID,          /**< The ID Manager module has detected that two stored peers represent the same peer. */
+    IM_EVT_BONDED_PEER_CONNECTED, /**< A connected peer has been identified as one of the bonded peers. This can happen immediately on connection, or at a later time. */
+} im_evt_id_t;
+
+
+typedef struct
+{
+    im_evt_id_t evt_id;
+    uint16_t    conn_handle;
+    union
+    {
+        struct
+        {
+            pm_peer_id_t peer_id_1;
+            pm_peer_id_t peer_id_2;
+        } duplicate_id;
+    } params;
+} im_evt_t;
+
+
+/**@brief Event handler for events from the ID Manager module.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+typedef void (*im_evt_handler_t)(im_evt_t const * p_event);
+
+/**@brief Function for registering for events from the ID Manager module.
+ *
+ * @note This will also initialize the module if needed.
+ *
+ * @param[in]  evt_handler  Callback for events from the ID Manager module.
+ *
+ * @retval NRF_SUCCESS       Registration was successful.
+ * @retval NRF_ERROR_NO_MEM  No more registrations possible.
+ * @retval NRF_ERROR_NULL    evt_handler was NULL.
+ */
+ret_code_t im_register(im_evt_handler_t evt_handler);
+
+
+/**@brief Function for dispatching SoftDevice events to the ID Manager module.
+ *
+ * @param[in]  p_ble_evt  The SoftDevice event.
+ */
+void im_ble_evt_handler(ble_evt_t * p_ble_evt);
+
+
+/**@brief Function for getting the corresponding peer ID from a connection handle.
+ *
+ * @param[in]  conn_handle  The connection handle.
+ *
+ * @return The corresponding peer ID, or @ref PM_PEER_ID_INVALID if none could be resolved.
+ */
+pm_peer_id_t im_peer_id_get_by_conn_handle(uint16_t conn_handle);
+
+
+/**@brief Function for getting the corresponding peer ID from a master ID (EDIV and rand).
+ *
+ * @param[in]  p_master_id  The master ID.
+ *
+ * @return The corresponding peer ID, or @ref PM_PEER_ID_INVALID if none could be resolved.
+ */
+pm_peer_id_t im_peer_id_get_by_master_id(ble_gap_master_id_t * p_master_id);
+
+
+/**@brief Function for getting the corresponding peer ID from an IRK match index, see @ref
+ *        ble_gap_evt_connected_t.
+ *
+ * @param[in]  irk_match_idx  The IRK match index.
+ *
+ * @return The corresponding peer ID, or @ref PM_PEER_ID_INVALID if none could be resolved.
+ */
+pm_peer_id_t im_peer_id_get_by_irk_match_idx(uint8_t irk_match_idx);
+
+
+/**@brief Function for getting the corresponding connection handle from a peer ID.
+ *
+ * @param[in] peer_id  The peer ID.
+ *
+ * @return The corresponding connection handle, or @ref BLE_CONN_HANDLE_INVALID if none could be
+ *         resolved.
+ */
+uint16_t im_conn_handle_get(pm_peer_id_t peer_id);
+
+
+/**@brief Function for comparing two master ids
+ * @note  Two invalid master IDs will not match.
+ *
+ * @param[in]  p_master_id1 First master id for comparison
+ * @param[in]  p_master_id2 Second master id for comparison
+ *
+ * @return     True if the input matches, false if it does not.
+ */
+bool im_master_ids_compare(ble_gap_master_id_t const * p_master_id1,
+                           ble_gap_master_id_t const * p_master_id2);
+
+
+/**@brief Function for getting the BLE address used by the peer when connecting.
+ *
+ * @param[in]  conn_handle  The connection handle.
+ * @param[out] p_ble_addr   The BLE address used by the peer when the connection specified by
+ *                          conn_handle was established.
+ *
+ * @retval NRF_SUCCESS                   The address was found and copied.
+ * @retval NRF_ERROR_INVALID_STATE       Module not initialized.
+ * @retval BLE_ERROR_CONN_HANDLE_INVALID conn_handle does not refer to an active connection.
+ * @retval NRF_ERROR_NULL                p_ble_addr was NULL.
+ */
+ret_code_t im_ble_addr_get(uint16_t conn_handle, ble_gap_addr_t * p_ble_addr);
+
+
+/**@brief Function for checking whether a master ID is valid or invalid
+ *
+ * @param[in]  p_master_id  The master ID.
+ *
+ * @retval true   The master id is valid.
+ * @retval true   The master id is invalid (i.e. all zeros).
+ */
+bool im_master_id_is_valid(ble_gap_master_id_t const * p_master_id);
+
+
+/**@brief Function for reporting that a new peer ID has been allocated for a specified connection.
+ *
+ * @param[in]  conn_handle  The connection.
+ * @param[in]  peer_id      The new peer ID.
+ */
+void im_new_peer_id(uint16_t conn_handle, pm_peer_id_t peer_id);
+
+
+/**@brief Function for deleting all of a peer's data from flash and disassociating it from any
+ *        connection handles it is associated with.
+ *
+ * @param[in]  peer_id  The peer to free.
+ *
+ * @return Any error code returned by @ref pdb_peer_free.
+ */
+ret_code_t im_peer_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for informing this module of what whitelist will be used.
+ *
+ * @details This function is meant to be used when the app wants to use a custom whitelist.
+ *          When using peer manager, this function must be used if a custom whitelist is used.
+ *          Only whitelisted IRKs are of any importance for this function.
+ *
+ * @note When using a whitelist, always use the whitelist created/set by the most recent
+ *       call to @ref im_whitelist_create or to this function, whichever happened most recently.
+ * @note Do not call this function while scanning with another whitelist.
+ * @note Do not add any irks to the whitelist that are not present in the bonding data of a peer in
+ *       the peer database.
+ * @note The whitelist is not altered in any way by calling this function. Only the internal state
+ *       of the module is changed.
+ *
+ * @param[in] p_whitelist  The whitelist.
+ *
+ * @retval NRF_SUCCESS         Whitelist successfully set.
+ * @retval NRF_ERROR_NULL      p_whitelist was NULL.
+ * @retval NRF_ERROR_NOT_FOUND One or more of the whitelists irks was not found in the peer_database.
+ */
+ret_code_t im_whitelist_custom(ble_gap_whitelist_t const * p_whitelist);
+
+
+/**
+ * @brief Function for constructing a whitelist for use when advertising.
+ *
+ * @note When advertising with whitelist, always use the whitelist created/set by the most recent
+ *       call to this function or to @ref im_whitelist_custom, whichever happened most recently.
+ * @note Do not call this function while advertising with another whitelist.
+ *
+ * @param[in]     p_peer_ids   The ids of the peers to be added to the whitelist.
+ * @param[in]     n_peer_ids   The number of peer ids in p_peer_ids.
+ * @param[in,out] p_whitelist  The constructed whitelist. Note that p_adv_whitelist->pp_addrs
+ *                             must be NULL or point to an array with size @ref
+ *                             BLE_GAP_WHITELIST_ADDR_MAX_COUNT and p_adv_whitelist->pp_irks
+ *                             must be NULL or point to an array with size @ref
+ *                             BLE_GAP_WHITELIST_IRK_MAX_COUNT.
+ *
+ * @retval NRF_SUCCESS     Whitelist successfully created.
+ * @retval NRF_ERROR_NULL  p_whitelist was NULL.
+ */
+ret_code_t im_whitelist_create(pm_peer_id_t        * p_peer_ids,
+                               uint8_t               n_peer_ids,
+                               ble_gap_whitelist_t * p_whitelist);
+
+/**
+ * @brief Function for resolving a resolvable address with an identity resolution key (IRK).
+ *
+ * @details This function will use the ECB peripheral to resolve a resolvable address.
+ *          This can be used to resolve the identity of a device distributing a random
+ *          resolvable address based on any IRKs you have received earlier. If an address is
+ *          resolved by an IRK, the device disributing the address must also know the IRK.
+ *
+ * @param[in] p_addr  A random resolvable address.
+ * @param[in] p_irk   An identity resolution key (IRK).
+ *
+ * @retval true   The irk used matched the one used to create the address.
+ * @retval false  The irk used did not match the one used to create the address, or an argument was
+ *                NULL.
+ */
+bool im_address_resolve(ble_gap_addr_t const * p_addr, ble_gap_irk_t const * p_irk);
+
+/**@brief Function for calculating the ah() hash function described in Bluetooth core specification
+ *        4.2 section 3.H.2.2.2.
+ *
+ * @detail  BLE uses a hash function to calculate the first half of a resolvable address
+ *          from the second half of the address and an irk. This function will use the ECB
+ *          periferal to hash these data acording to the Bluetooth core specification.
+ *
+ * @note The ECB expect little endian input and output.
+ *       This function expect big endian and will reverse the data as necessary.
+ *
+ * @param[in]  p_k          The key used in the hash function.
+ *                          For address resolution this is should be the irk.
+ *                          The array must have a length of 16.
+ * @param[in]  p_r          The rand used in the hash function. For generating a new address
+ *                          this would be a random number. For resolving a resolvable address
+ *                          this would be the last half of the address being resolved.
+ *                          The array must have a length of 3.
+ * @param[out] p_local_hash The result of the hash operation. For address resolution this
+ *                          will match the first half of the address being resolved if and only
+ *                          if the irk used in the hash function is the same one used to generate
+ *                          the address.
+ *                          The array must have a length of 16.
+ *
+ * @note    ====IMPORTANT====
+ *          This is a special modification to the original nRF5x SDK required by the mbed BLE API
+ *          to be able to generate BLE private resolvable addresses. This function is used by
+ *          the BLE API implementation for nRF5xSecurityManager::getAddressFromBondTable() in the
+ *          ble-nrf52832 yotta module.
+ *          =================
+ */
+void ah(uint8_t const * p_k, uint8_t const * p_r, uint8_t * p_local_hash);  
+
+/** @}
+ * @endcond
+ */
+
+#endif /* PEER_ID_MANAGER_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.c
new file mode 100644
index 0000000000..2282cc48d3
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.c
@@ -0,0 +1,92 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "peer_data.h"
+
+#include "peer_manager_types.h"
+#include "fds.h"
+#include "sdk_common.h"
+
+
+void peer_data_parts_get(pm_peer_data_const_t const * p_peer_data, fds_record_chunk_t * p_chunks, uint16_t * p_n_chunks)
+{
+    if (p_n_chunks == NULL)
+    {
+    }
+    else if ((p_peer_data == NULL) || (p_chunks == NULL))
+    {
+        *p_n_chunks = 0;
+    }
+    else
+    {
+        p_chunks[0].p_data       = p_peer_data->p_all_data;
+        p_chunks[0].length_words = p_peer_data->length_words;
+        *p_n_chunks = 1;
+    }
+}
+
+
+ret_code_t peer_data_deserialize(pm_peer_data_flash_t const * p_in_data, pm_peer_data_t * p_out_data)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if ((p_in_data == NULL) || (p_out_data == NULL))
+    {
+        err_code = NRF_ERROR_NULL;
+    }
+    else
+    {
+        if (p_out_data->length_words < p_in_data->length_words)
+        {
+            p_out_data->length_words = p_in_data->length_words;
+            err_code = NRF_ERROR_NO_MEM;
+        }
+        else
+        {
+            p_out_data->length_words = p_in_data->length_words;
+            p_out_data->data_id      = p_in_data->data_id;
+
+            memcpy(p_out_data->p_all_data, p_in_data->p_all_data, p_in_data->length_words * 4);
+        }
+    }
+    return err_code;
+}
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.h
new file mode 100644
index 0000000000..3c1f373087
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data.h
@@ -0,0 +1,84 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef PEER_DATA_H__
+#define PEER_DATA_H__
+
+#include <stdint.h>
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "fds.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_data Peer Data
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module defines the structure of the data
+ *        that is managed by the @ref peer_manager. It also provides functions for parsing the data.
+ */
+
+
+/**@brief Function for enumerating the separate (non-contiguous) parts of the peer data.
+ *
+ * @param[in]  p_peer_data  The peer data to enumerate.
+ * @param[out] p_chunks      The resulting chunks. This must be an array of at least 2 elements.
+ * @param[out] p_n_chunks    The number of chunks. If this is 0, something went wrong.
+ */
+void peer_data_parts_get(pm_peer_data_const_t const * p_peer_data, fds_record_chunk_t * p_chunks, uint16_t * p_n_chunks);
+
+
+/**@brief Function for converting @ref pm_peer_data_flash_t into @ref pm_peer_data_t.
+ *
+ * @param[in]  p_in_data   The source data.
+ * @param[out] p_out_data  The target data structure.
+ *
+ * @retval NRF_SUCCESS       Successful conversion.
+ * @retval NRF_ERROR_NULL    A parameter was NULL.
+ * @retval NRF_ERROR_NO_MEM  A buffer was not large enough.
+ */
+ret_code_t peer_data_deserialize(pm_peer_data_flash_t const * p_in_data, pm_peer_data_t * p_out_data);
+
+/** @} 
+ * @endcond
+ */
+
+#endif /* PEER_DATA_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.c
new file mode 100644
index 0000000000..1f4e05dd5b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.c
@@ -0,0 +1,787 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "peer_data_storage.h"
+
+#include <stdint.h>
+#include <string.h>
+#include "sdk_errors.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_id.h"
+#include "peer_data.h"
+#include "fds.h"
+#include "sdk_common.h"
+
+
+// The number of user that can register with the module.
+#define MAX_REGISTRANTS    6
+
+// Macro for verifying that param is not zero.
+#define VERIFY_PARAM_NOT_ZERO(param)        \
+do                                          \
+{                                           \
+    if (param == 0)                         \
+    {                                       \
+        return NRF_ERROR_NULL;              \
+    }                                       \
+} while(0)
+
+
+// Macro for verifying that the peer id is within a valid range.
+#define VERIFY_PEER_ID_IN_RANGE(id)         \
+do                                          \
+{                                           \
+    if (id >= PM_PEER_ID_N_AVAILABLE_IDS)   \
+    {                                       \
+        return NRF_ERROR_INVALID_PARAM;     \
+    }                                       \
+} while (0)
+
+
+// Macro for verifying that the peer data id is withing a valid range.
+#define VERIFY_PEER_DATA_ID_IN_RANGE(id)    \
+do                                          \
+{                                           \
+    if (!PM_PEER_DATA_ID_IS_VALID(id))      \
+    {                                       \
+        return NRF_ERROR_INVALID_PARAM;     \
+    }                                       \
+} while (0)
+
+
+// Macro for initializing the peer ID tracking system if it is not already initialized.
+#define PEER_IDS_INITIALIZE()               \
+do                                          \
+{                                           \
+    if (!m_pds.peer_ids_initialized)        \
+    {                                       \
+        peer_ids_init();                    \
+    }                                       \
+} while (0)
+
+
+typedef struct
+{
+    bool                peer_ids_initialized;
+    pds_evt_handler_t   evt_handlers[MAX_REGISTRANTS];
+    uint8_t             n_registrants;
+    bool                clearing;
+    bool                clear_queued;
+} pds_t;
+
+
+static pds_t m_pds = { .n_registrants = 0 };
+
+
+#define MODULE_INITIALIZED (m_pds.n_registrants > 0) /**< Expression which is true when the module is initialized. */
+#include "sdk_macros.h"
+
+static void internal_state_reset(pds_t * p_pds)
+{
+    memset(p_pds, 0, sizeof(pds_t));
+}
+
+
+// Function for dispatching outbound events to all registered event handlers.
+static void pds_evt_send(pds_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < m_pds.n_registrants; i++)
+    {
+        m_pds.evt_handlers[i](p_event);
+    }
+}
+
+
+// Function to convert peer IDs to file IDs.
+static uint16_t peer_id_to_file_id(pm_peer_id_t peer_id)
+{
+    return (uint16_t)(peer_id + PEER_ID_TO_FILE_ID);
+}
+
+
+// Function to convert peer data id to type id.
+static pm_peer_id_t file_id_to_peer_id(uint16_t file_id)
+{
+    return (pm_peer_id_t)(file_id + FILE_ID_TO_PEER_ID);
+}
+
+
+// Function to convert peer data IDs to record keys.
+static uint16_t peer_data_id_to_record_key(pm_peer_data_id_t peer_data_id)
+{
+    return (uint16_t)peer_data_id + (uint16_t)PEER_DATA_ID_TO_RECORD_KEY;
+}
+
+
+// Function to convert record keys to peer data IDs.
+static pm_peer_data_id_t record_key_to_peer_data_id(uint16_t record_key)
+{
+    return (pm_peer_data_id_t)(record_key + RECORD_KEY_TO_PEER_DATA_ID);
+}
+
+
+// Function for clearing all peer data of one peer.
+// These operations will be sent to FDS one at a time.
+static void peer_data_clear()
+{
+    ret_code_t        retval;
+    uint16_t          file_id;
+    fds_record_desc_t desc;
+    fds_find_token_t  token   = {0};
+    pm_peer_id_t      peer_id = peer_id_get_next_deleted(PM_PEER_ID_INVALID);
+
+    while (    (peer_id != PM_PEER_ID_INVALID)
+            && (fds_record_find_in_file(peer_id_to_file_id(peer_id), &desc, &token)
+            == FDS_ERR_NOT_FOUND))
+    {
+        peer_id_free(peer_id);
+        peer_id = peer_id_get_next_deleted(peer_id);
+    }
+
+    if (!m_pds.clearing && (peer_id != PM_PEER_ID_INVALID))
+    {
+        file_id = peer_id_to_file_id(peer_id);
+        retval  = fds_file_delete(file_id);
+
+        if (retval == FDS_SUCCESS)
+        {
+            m_pds.clearing = true;
+        }
+        else if (retval == FDS_ERR_NO_SPACE_IN_QUEUES)
+        {
+            m_pds.clear_queued = true;
+        }
+        else
+        {
+            pds_evt_t pds_evt;
+
+            pds_evt.evt_id      = PDS_EVT_ERROR_UNEXPECTED;
+            pds_evt.peer_id     = peer_id;
+            pds_evt.data_id     = PM_PEER_DATA_ID_INVALID;
+            pds_evt.store_token = PM_STORE_TOKEN_INVALID;
+            pds_evt.result      = retval;
+
+            pds_evt_send(&pds_evt);
+        }
+    }
+}
+
+
+static ret_code_t find_fds_item(pm_peer_id_t              peer_id,
+                                pm_peer_data_id_t         data_id,
+                                fds_record_desc_t * const p_desc)
+{
+    fds_find_token_t find_tok = {0};
+
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(data_id);
+    // pp_record verified by caller.
+
+    uint16_t file_id    = peer_id_to_file_id(peer_id);
+    uint16_t record_key = peer_data_id_to_record_key(data_id);
+
+    return fds_record_find(file_id, record_key, p_desc, &find_tok);
+}
+
+
+static void peer_ids_init()
+{
+    fds_record_desc_t  record_desc;
+    fds_flash_record_t record;
+    fds_find_token_t   find_tok = {0};
+
+    uint16_t const record_key = peer_data_id_to_record_key(PM_PEER_DATA_ID_BONDING);
+
+    if (!m_pds.peer_ids_initialized)
+    {
+        while(fds_record_find_by_key(record_key, &record_desc, &find_tok) == FDS_SUCCESS)
+        {
+            pm_peer_id_t peer_id;
+
+            // It is safe to ignore the return value since we just obtained
+            // this descriptor and also 'record' is different from NULL.
+            (void)fds_record_open(&record_desc, &record);
+            peer_id = file_id_to_peer_id(record.p_header->ic.file_id);
+            (void)fds_record_close(&record_desc);
+
+            (void)peer_id_allocate(peer_id);
+        }
+
+        m_pds.peer_ids_initialized = true;
+    }
+}
+
+
+static void fds_evt_handler(fds_evt_t const * const p_fds_evt)
+{
+    pds_evt_t pds_evt;
+    bool      send_event = true;
+
+    pds_evt.result = (p_fds_evt->result == FDS_SUCCESS);
+
+    switch(p_fds_evt->id)
+    {
+        case FDS_EVT_WRITE:
+            pds_evt.evt_id = (p_fds_evt->result == FDS_SUCCESS) ? PDS_EVT_STORED :
+                                                                  PDS_EVT_ERROR_STORE;
+
+            pds_evt.peer_id     = file_id_to_peer_id(p_fds_evt->write.file_id);
+            pds_evt.data_id     = record_key_to_peer_data_id(p_fds_evt->write.record_key);
+            pds_evt.result      = p_fds_evt->result;
+            pds_evt.store_token = p_fds_evt->write.record_id;
+            break;
+
+        case FDS_EVT_UPDATE:
+            pds_evt.evt_id = (p_fds_evt->result == FDS_SUCCESS) ? PDS_EVT_UPDATED :
+                                                                  PDS_EVT_ERROR_UPDATE;
+
+            pds_evt.peer_id     = file_id_to_peer_id(p_fds_evt->write.file_id);
+            pds_evt.data_id     = record_key_to_peer_data_id(p_fds_evt->write.record_key);
+            pds_evt.result      = p_fds_evt->result;
+            pds_evt.store_token = p_fds_evt->write.record_id;
+            break;
+
+        case FDS_EVT_DEL_RECORD:
+            pds_evt.evt_id = (p_fds_evt->result == FDS_SUCCESS) ? PDS_EVT_CLEARED :
+                                                                  PDS_EVT_ERROR_CLEAR;
+
+            pds_evt.peer_id     = file_id_to_peer_id(p_fds_evt->del.file_id);
+            pds_evt.data_id     = record_key_to_peer_data_id(p_fds_evt->del.record_key);
+            pds_evt.store_token = p_fds_evt->del.record_id;
+            break;
+
+        case FDS_EVT_DEL_FILE:
+            {
+                if ((p_fds_evt->del.record_key == FDS_RECORD_KEY_DIRTY) &&
+                    (p_fds_evt->del.file_id    != FDS_FILE_ID_INVALID))
+                {
+                    pds_evt.peer_id = file_id_to_peer_id(p_fds_evt->del.file_id);
+                    pds_evt.data_id = record_key_to_peer_data_id(p_fds_evt->del.record_key);
+
+                    pds_evt.data_id = PM_PEER_DATA_ID_INVALID;
+                    if (p_fds_evt->result == FDS_SUCCESS)
+                    {
+                        pds_evt.evt_id = PDS_EVT_PEER_ID_CLEAR;
+                        peer_id_free(pds_evt.peer_id);
+                    }
+                    else
+                    {
+                        pds_evt.evt_id = PDS_EVT_ERROR_PEER_ID_CLEAR;
+                    }
+                    m_pds.clearing = false;
+                    m_pds.clear_queued = false;
+
+                    peer_data_clear();
+                }
+            }
+            break;
+
+        case FDS_EVT_GC:
+            pds_evt.evt_id = PDS_EVT_COMPRESSED;
+            break;
+
+        default:
+            send_event = false;
+            break;
+    }
+
+    if (send_event)
+    {
+        pds_evt_send(&pds_evt);
+    }
+
+    if (m_pds.clear_queued)
+    {
+        m_pds.clear_queued = false;
+        peer_data_clear();
+    }
+}
+
+
+ret_code_t pds_register(pds_evt_handler_t evt_handler)
+{
+    if (m_pds.n_registrants >= MAX_REGISTRANTS)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+
+    if (!MODULE_INITIALIZED)
+    {
+        ret_code_t retval;
+        internal_state_reset(&m_pds);
+        peer_id_init();
+
+        retval = fds_register(fds_evt_handler);
+        if (retval != FDS_SUCCESS)
+        {
+            return NRF_ERROR_NO_MEM;
+        }
+
+        retval = fds_init();
+        if (retval != FDS_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    }
+
+    m_pds.evt_handlers[m_pds.n_registrants] = evt_handler;
+    m_pds.n_registrants += 1;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pds_peer_data_read_ptr_get(pm_peer_id_t            peer_id,
+                                      pm_peer_data_id_t       data_id,
+                                      pm_peer_data_flash_t  * p_data,
+                                      pm_store_token_t      * p_token)
+{
+    ret_code_t retval;
+
+    fds_flash_record_t record;
+    fds_record_desc_t  record_desc;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(data_id);
+    VERIFY_PARAM_NOT_NULL(p_data);
+
+    retval = find_fds_item(peer_id, data_id, &record_desc);
+    if (retval != FDS_SUCCESS)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    // Shouldn't fail, unless the record was deleted.
+    (void)fds_record_open(&record_desc, &record);
+
+    if (p_data != NULL)
+    {
+        p_data->data_id      = data_id;
+        p_data->length_words = record.p_header->tl.length_words;
+        p_data->p_all_data   = record.p_data;
+    }
+
+    if (p_token != NULL)
+    {
+        *p_token = (uint32_t)record.p_header->record_id;
+    }
+
+    // Shouldn't fail, unless the record was already closed.
+    (void)fds_record_close(&record_desc);
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pds_peer_data_lock(pm_store_token_t store_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_ZERO(store_token);
+
+    // TODO: Not implemented in fds yet.
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pds_peer_data_verify(pm_store_token_t store_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_ZERO(store_token);
+
+    // TODO: Not implemented in fds yet.
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pds_peer_data_read(pm_peer_id_t        peer_id,
+                              pm_peer_data_id_t   data_id,
+                              pm_peer_data_t    * p_data,
+                              uint16_t          * p_len_words)
+{
+    ret_code_t           retval;
+    pm_peer_data_flash_t peer_data_flash;
+
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(data_id);
+    VERIFY_PARAM_NOT_NULL(p_len_words);
+    VERIFY_PARAM_NOT_NULL(p_data);
+
+    retval = pds_peer_data_read_ptr_get(peer_id, data_id, &peer_data_flash, NULL);
+    if (retval != NRF_SUCCESS)
+    {
+        return retval;
+    }
+
+    if ((*p_len_words) == 0)
+    {
+        (*p_len_words) = peer_data_flash.length_words;
+        return NRF_SUCCESS;
+    }
+    else if ((*p_len_words) < peer_data_flash.length_words)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    VERIFY_PARAM_NOT_NULL(p_data->p_all_data);
+
+    retval = peer_data_deserialize(&peer_data_flash, p_data);
+
+    return retval;
+}
+
+
+ret_code_t pds_peer_data_write_prepare(pm_peer_data_const_t const * p_peer_data,
+                                       pm_prepare_token_t         * p_prepare_token)
+{
+    ret_code_t retval;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_peer_data);
+    VERIFY_PEER_DATA_ID_IN_RANGE(p_peer_data->data_id);
+    //VERIFY_PARAM_NOT_NULL(p_prepare_token);  redundant, see fds_reserve().
+
+    retval = fds_reserve((fds_reserve_token_t*)p_prepare_token, p_peer_data->length_words);
+
+    switch (retval)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_NULL_ARG:
+            return NRF_ERROR_NULL;
+
+        case FDS_ERR_RECORD_TOO_LARGE:
+            return NRF_ERROR_INVALID_LENGTH;
+
+        case FDS_ERR_NO_SPACE_IN_FLASH:
+            return NRF_ERROR_NO_MEM;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+ret_code_t pds_peer_data_write_prepare_cancel(pm_prepare_token_t prepare_token)
+{
+    ret_code_t retval;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_ZERO(prepare_token);
+
+    retval = fds_reserve_cancel((fds_reserve_token_t*)&prepare_token);
+
+    switch (retval)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_NULL_ARG:
+            return NRF_ERROR_NULL;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+ret_code_t pds_peer_data_write_prepared(pm_peer_id_t                 peer_id,
+                                        pm_peer_data_const_t const * p_peer_data,
+                                        pm_prepare_token_t           prepare_token,
+                                        pm_store_token_t           * p_store_token)
+{
+    ret_code_t         retval;
+    fds_record_t       record;
+    fds_record_desc_t  record_desc;
+    fds_record_chunk_t chunks[2];
+    uint16_t           n_chunks;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PARAM_NOT_NULL(p_peer_data);
+    VERIFY_PEER_DATA_ID_IN_RANGE(p_peer_data->data_id);
+    VERIFY_PARAM_NOT_ZERO(prepare_token);
+
+    // Create chunks.
+    peer_data_parts_get(p_peer_data, chunks, &n_chunks);
+
+    // Prepare the record to be written.
+    record.file_id         = peer_id_to_file_id(peer_id);
+    record.key             = peer_data_id_to_record_key(p_peer_data->data_id);
+    record.data.p_chunks   = chunks;
+    record.data.num_chunks = n_chunks;
+
+    retval = fds_record_write_reserved(&record_desc,
+                                       &record,
+                                       (fds_reserve_token_t*)&prepare_token);
+
+    if ((retval == FDS_SUCCESS) && (p_store_token != NULL))
+    {
+        // If fds_record_write_reserved() returned sucessfully, it is safe
+        // to ignore the return value from fds_record_id_from_desc() since
+        // the descriptor is valid, and also p_store_token is different from NULL.
+        (void)fds_record_id_from_desc(&record_desc, (uint32_t*)p_store_token);
+    }
+
+    switch (retval)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_BUSY:
+        case FDS_ERR_NO_SPACE_IN_QUEUES:
+            return NRF_ERROR_BUSY;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+ret_code_t pds_peer_data_write(pm_peer_id_t                 peer_id,
+                               pm_peer_data_const_t const * p_peer_data,
+                               pm_store_token_t           * p_store_token)
+{
+    ret_code_t         retval;
+    fds_record_t       record;
+    fds_record_desc_t  record_desc;
+    fds_record_chunk_t chunks[2];
+    uint16_t           n_chunks;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PARAM_NOT_NULL(p_peer_data);
+    VERIFY_PEER_DATA_ID_IN_RANGE(p_peer_data->data_id);
+
+    // Create chunks.
+    peer_data_parts_get(p_peer_data, chunks, &n_chunks);
+
+    // Prepare the record to be written.
+    record.file_id         = peer_id_to_file_id(peer_id);
+    record.key             = peer_data_id_to_record_key(p_peer_data->data_id);
+    record.data.p_chunks   = chunks;
+    record.data.num_chunks = n_chunks;
+
+    retval = fds_record_write(&record_desc, &record);
+
+    if ((retval == FDS_SUCCESS) && (p_store_token != NULL))
+    {
+        // If fds_record_write() returned sucessfully, it is safe
+        // to ignore the return value from fds_record_id_from_desc() since
+        // the descriptor is valid, and also p_store_token is different from NULL.
+        (void)fds_record_id_from_desc(&record_desc, (uint32_t*)p_store_token);
+    }
+
+    switch (retval)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_BUSY:
+        case FDS_ERR_NO_SPACE_IN_QUEUES:
+            return NRF_ERROR_BUSY;
+
+        case FDS_ERR_NO_SPACE_IN_FLASH:
+            return NRF_ERROR_NO_MEM;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+ret_code_t pds_peer_data_update(pm_peer_id_t                 peer_id,
+                                pm_peer_data_const_t const * p_peer_data,
+                                pm_store_token_t             old_token,
+                                pm_store_token_t           * p_store_token)
+{
+    ret_code_t         retval;
+    fds_record_t       record;
+    fds_record_desc_t  record_desc;
+    fds_record_chunk_t chunks[2];
+    uint16_t           n_chunks;
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PARAM_NOT_NULL(p_peer_data);
+    VERIFY_PEER_DATA_ID_IN_RANGE(p_peer_data->data_id);
+
+    // Create chunks.
+    peer_data_parts_get(p_peer_data, chunks, &n_chunks);
+
+    // Prepare the record to be written.
+    record.file_id         = peer_id_to_file_id(peer_id);
+    record.key             = peer_data_id_to_record_key(p_peer_data->data_id);
+    record.data.p_chunks   = chunks;
+    record.data.num_chunks = n_chunks;
+
+    // Obtain the descriptor of the record to be updated.
+    // It is safe to ignore the return value if record_desc is different from NULL.
+    (void)fds_descriptor_from_rec_id(&record_desc, (uint32_t)old_token);
+
+    retval = fds_record_update(&record_desc, &record);
+
+    if ((retval == FDS_SUCCESS) && (p_store_token != NULL))
+    {
+        // If fds_record_update() returned sucessfully, it is safe
+        // to ignore the return value from fds_record_id_from_desc() since
+        // the descriptor is valid, and also p_store_token is different from NULL.
+        (void)fds_record_id_from_desc(&record_desc, (uint32_t*)p_store_token);
+    }
+
+    switch (retval)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_BUSY:
+        case FDS_ERR_NO_SPACE_IN_QUEUES:
+            return NRF_ERROR_BUSY;
+
+        case FDS_ERR_NO_SPACE_IN_FLASH:
+            return NRF_ERROR_NO_MEM;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+ret_code_t pds_peer_data_clear(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    ret_code_t        retval;
+    uint16_t          file_id;
+    uint16_t          record_key;
+    fds_record_desc_t record_desc;
+    fds_find_token_t  find_tok = {0};
+
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    VERIFY_PEER_DATA_ID_IN_RANGE(data_id);
+
+    file_id    = peer_id_to_file_id(peer_id);
+    record_key = peer_data_id_to_record_key(data_id);
+
+    retval = fds_record_find(file_id, record_key, &record_desc, &find_tok);
+    if(retval != FDS_SUCCESS)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    retval = fds_record_delete(&record_desc);
+
+    switch (retval)
+    {
+        case FDS_SUCCESS:
+            return NRF_SUCCESS;
+
+        case FDS_ERR_NO_SPACE_IN_QUEUES:
+            return NRF_ERROR_BUSY;
+
+        default:
+            return NRF_ERROR_INTERNAL;
+    }
+}
+
+
+pm_peer_id_t pds_peer_id_allocate(void)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+    PEER_IDS_INITIALIZE();
+    return peer_id_allocate(PM_PEER_ID_INVALID);
+}
+
+
+ret_code_t pds_peer_id_free(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PEER_ID_IN_RANGE(peer_id);
+    PEER_IDS_INITIALIZE();
+
+    (void)peer_id_delete(peer_id);
+    peer_data_clear();
+
+    return NRF_SUCCESS;
+}
+
+
+bool pds_peer_id_is_allocated(pm_peer_id_t peer_id)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return false;
+    }
+    PEER_IDS_INITIALIZE();
+
+    return peer_id_is_allocated(peer_id);
+}
+
+
+pm_peer_id_t pds_next_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+    PEER_IDS_INITIALIZE();
+
+    return peer_id_get_next_used(prev_peer_id);
+}
+
+
+uint32_t pds_n_peers(void)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return 0;
+    }
+    PEER_IDS_INITIALIZE();
+    return peer_id_n_ids();
+}
+
+//lint -restore
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.h
new file mode 100644
index 0000000000..42dcacd69c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_data_storage.h
@@ -0,0 +1,381 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef PEER_DATA_STORAGE_H__
+#define PEER_DATA_STORAGE_H__
+
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_data_storage Peer Data Storage
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module provides a Peer Manager-specific API
+ *        to the persistent storage.
+ */
+
+#define PDS_PREPARE_TOKEN_INVALID   0  /**< Invalid value for prepare token. */
+
+enum
+{
+    PEER_ID_TO_FILE_ID         = 0xC000,
+    FILE_ID_TO_PEER_ID         = -PEER_ID_TO_FILE_ID,
+    PEER_DATA_ID_TO_RECORD_KEY = 0xC000,
+    RECORD_KEY_TO_PEER_DATA_ID = -PEER_DATA_ID_TO_RECORD_KEY,
+};
+
+
+/**@brief The types of events that can come from the peer_data_storage module.
+ */
+typedef enum
+{
+    PDS_EVT_STORED,                 /**< The specified data has been successfully stored. */
+    PDS_EVT_UPDATED,                /**< The specified data has been successfully updated. */
+    PDS_EVT_CLEARED,                /**< The specified data has been successfully cleared. */
+    PDS_EVT_ERROR_STORE,            /**< The specified data could not be stored. */
+    PDS_EVT_ERROR_UPDATE,           /**< The specified data could not be updated. */
+    PDS_EVT_ERROR_CLEAR,            /**< The specified data could not be cleared. */
+    PDS_EVT_PEER_ID_CLEAR,          /**< The peer id has been successfully cleared. */
+    PDS_EVT_ERROR_PEER_ID_CLEAR,    /**< The peer id has been successfully cleared. */
+    PDS_EVT_COMPRESSED,             /**< A compress procedure has finished successfully. */
+    PDS_EVT_ERROR_UNEXPECTED,       /**< An unexpected, possibly fatal error occurred. The unexpected error is included in the event structure. */
+} pds_evt_id_t;
+
+
+/**@brief Events that can come from the peer_data_storage module.
+ */
+typedef struct
+{
+    pds_evt_id_t      evt_id;      /**< The type of event. */
+    pm_peer_id_t      peer_id;     /**< The peer the event pertains to. */
+    pm_peer_data_id_t data_id;     /**< The data the event pertains to. */
+    pm_store_token_t  store_token; /**< A unique identifier for the operation. Can be compare to the token received when starting the operation. */
+    ret_code_t        result;      /**< The result of the operation, or the unexpected error. */
+} pds_evt_t;
+
+
+/**@brief Event handler for events from the peer_data_storage module.
+ *
+ * @param[in]  event    The event that has happened.
+ * @param[in]  peer_id  The id of the peer the event pertains to.
+ * @param[in]  flags    The data the event pertains to.
+ */
+typedef void (*pds_evt_handler_t)(pds_evt_t const * p_event);
+
+
+/**@brief Function for registering for events from the peer database.
+ *
+ * @note This function will initialize the module if it is not already initialized.
+ *
+ * @param[in]  evt_handler  Event handler to register.
+ *
+ * @retval NRF_SUCCESS              Registration successful.
+ * @retval NRF_ERROR_NO_MEM         No more event handlers can be registered.
+ * @retval NRF_ERROR_NULL           evt_handler was NULL.
+ * @retval NRF_ERROR_INTERNAL       An unexpected error happened.
+ * @retval NRF_ERROR_INTERNAL       Unexpected error.
+ */
+ret_code_t pds_register(pds_evt_handler_t evt_handler);
+
+
+/**@brief Function for retrieving a direct pointer to peer data in persistent storage.
+ *
+ * @param[in]  peer_id      The id of the peer whose data to read.
+ * @param[in]  data_id      Which data to get.
+ * @param[out] p_data       The peer data pointer.
+ * @param[out] p_token      Token that can be used to lock data in flash and check data validity.
+ *
+ * @retval NRF_SUCCESS              The pointer was successfully retrieved.
+ * @retval NRF_ERROR_INVALID_PARAM  Invalid data_id.
+ * @retval NRF_ERROR_NOT_FOUND      The requested data was not found in persistent storage.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pds_peer_data_read_ptr_get(pm_peer_id_t            peer_id,
+                                      pm_peer_data_id_t       data_id,
+                                      pm_peer_data_flash_t  * p_data,
+                                      pm_store_token_t      * p_token);
+
+
+#if 0
+// @TODO: Finish documentation
+/**@brief Function to lock the flash data (to defer compression from invalidating data)
+ *
+ * @param[in]   store_token     The token representing the item to lock
+ *
+ * @retval NRF_SUCCESS  Successfully locked
+ */
+ret_code_t pds_peer_data_lock(pm_store_token_t store_token);
+
+
+/**@brief Function to verify flash data integrity
+ *
+ * @param[in]   store_token     The token representing the item to lock
+ *
+ * @retval NRF_SUCCESS              The data integrity is valid.
+ * @retval NRF_ERROR_NULL           The token is invalid.
+ * @retval NRF_ERROR_INVALID_DATA   The data integrity is not valid.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t  pds_peer_data_verify(pm_store_token_t store_token);
+#endif
+
+
+/**@brief Function for retrieving peer data from persistent storage by making a copy.
+ *
+ * @param[in]       peer_id     The id of the peer whose data to read.
+ * @param[in]       data_id     Which piece of data to read.
+ * @param[out]      p_data      Pointer to the peer data.
+ * @param[in,out]   p_len_words Length available to copy to (in words).
+ *                              If set to NULL, then no copy will be made and the
+ *                              length will be reflected in p_len_words after the call returns.
+ *
+ * @retval NRF_SUCCESS              The read was successful.
+ * @retval NRF_ERROR_INVALID_PARAM  Invalid data_id or peer_id.
+ * @retval NRF_ERROR_NULL           Either \c p_data or \c p_len_words were \c NULL, or \c p_data
+ *                                  contained a NULL pointer.
+ * @retval NRF_ERROR_NOT_FOUND      The requested data was not found in persistent storage.
+ * @retval NRF_ERROR_NO_MEM         The length of stored data too large to copy out.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pds_peer_data_read(pm_peer_id_t          peer_id,
+                              pm_peer_data_id_t     data_id,
+                              pm_peer_data_t      * p_data,
+                              uint16_t            * p_len_words);
+
+
+/**@brief Function for preparing persistent storage for a write.
+ *
+ * @details If this call succeeds, space is reserved in persistent storage, so the write will fit.
+ *
+ * @note If space has already been prepared for this peer_id/data_id pair, no new space will be
+ *       reserved, unless the previous reservation had too small size.
+ *
+ * @param[in]  p_peer_data      Data to prepare for. The data needs not be ready, but length and type
+ *                              values must.
+ * @param[out] p_prepare_token  A token identifying the prepared memory area.
+ *
+ * @retval NRF_SUCCESS               The call was successful.
+ * @retval NRF_ERROR_NULL            Either \c p_peer_data or \c p_prepare code were \c NULL.
+ * @retval NRF_ERROR_INVALID_PARAM   Invalid data ID.
+ * @retval NRF_ERROR_INVALID_LENGTH  Data length exceeds the maximum length allowed.
+ * @retval NRF_ERROR_NO_MEM          No space available in persistent storage.
+ * @retval NRF_ERROR_INVALID_STATE   Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL        Internal error.
+ */
+ret_code_t pds_peer_data_write_prepare(pm_peer_data_const_t const * p_peer_data,
+                                       pm_prepare_token_t         * p_prepare_token);
+
+
+/**@brief Function for undoing a previous call to @ref pds_peer_data_write_prepare.
+ *
+ * @param[in]  prepare_token  A token identifying the prepared memory area to cancel.
+ *
+ * @retval NRF_SUCCESS               The call was successful.
+ * @retval NRF_ERROR_NULL            Invalid value for \c prepare_token.
+ * @retval NRF_ERROR_INVALID_STATE   Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL        Internal error.
+ */
+ret_code_t pds_peer_data_write_prepare_cancel(pm_prepare_token_t prepare_token);
+
+
+/**@brief Function for writing prepared (reserved) peer data to persistent storage.
+ *
+ * @details Writing happens asynchronously. Expect a @ref PDS_EVT_STORED or @ref PDS_EVT_ERROR_STORE
+ *          event.
+ *
+ * @param[in]  peer_id        The id of the peer the data pertains to.
+ * @param[in]  p_peer_data    The peer data.
+ * @param[in]  prepare_token  A token identifying the prepared memory area to write into. If
+ *                            the prepare token is invalid, e.g. PDS_PREPARE_TOKEN_INVALID, the
+ *                            prepare/write sequence will happen atomically.
+ * @param[out] p_store_token  A token identifying this particular store operation. The token can be
+ *                            used to identify events pertaining to this operation.
+ *
+ * @retval NRF_SUCCESS               The write was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM   Invalid peer ID or data ID.
+ * @retval NRF_ERROR_NULL            \c p_peer_data was \c NULL or contained a \c NULL pointer or
+ *                                   \c prepare_token was zero.
+ * @retval NRF_ERROR_NO_MEM          No space available in persistent storage. This can only happen
+ *                                   if \c p_prepare_token is \c NULL.
+ * @retval NRF_ERROR_BUSY            FDS or underlying modules are busy and can't take any
+ *                                   more requests.
+ * @retval NRF_ERROR_INVALID_STATE   Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL        Internal error.
+ */
+ret_code_t pds_peer_data_write_prepared(pm_peer_id_t                    peer_id,
+                                        pm_peer_data_const_t    const * p_peer_data,
+                                        pm_prepare_token_t              prepare_token,
+                                        pm_store_token_t              * p_store_token);
+
+
+/**@brief Function for writing peer data to persistent storage.
+ *
+ * @details Writing happens asynchronously. Expect a @ref PDS_EVT_STORED or @ref PDS_EVT_ERROR_STORE
+ *          event.
+ *
+ * @param[in]  peer_id        The id of the peer the data pertains to.
+ * @param[in]  p_peer_data    The peer data.
+ * @param[out] p_store_token  A token identifying this particular store operation. The token can be
+ *                            used to identify events pertaining to this operation.
+ *
+ * @retval NRF_SUCCESS               The write was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM   Invalid data ID or peer ID.
+ * @retval NRF_ERROR_NULL            \c p_peer_data was \c NULL or data contained a \c NULL pointer.
+ * @retval NRF_ERROR_NO_MEM          No space available in persistent storage.
+ * @retval NRF_ERROR_BUSY            FDS or underlying modules are busy and can't take any
+ *                                   more requests.
+ * @retval NRF_ERROR_INVALID_STATE   Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL        Internal error.
+ */
+ret_code_t pds_peer_data_write(pm_peer_id_t                 peer_id,
+                               pm_peer_data_const_t const * p_peer_data,
+                               pm_store_token_t           * p_store_token);
+
+
+/**@brief Function for updating currently stored peer data to a new version
+ *
+ * @details Updating happens asynchronously.
+ *          Expect a @ref PDS_EVT_STORED or @ref PDS_EVT_ERROR_STORE for the store token
+ *          and a @ref PDS_EVT_ERROR_CLEAR or @ref PDS_EVT_ERROR_CLEAR for the old token
+ *
+ * @param[in]   peer_id             The peer which the data is associated to.
+ * @param[in]   p_peer_data         New data.
+ * @param[in]   old_token           Store token for the old data.
+ * @param[out]  p_store_token       Store token for the new data.
+ *
+ * @retval NRF_SUCESS               The update was initiated successfully
+ * @retval NRF_ERROR_NULL           \c p_peer_data was \c NULL or data contained a \c NULL pointer.
+ * @retval NRF_ERROR_NO_MEM         No space available in persistent storage.
+ * @retval NRF_ERROR_BUSY           FDS or underlying modules are busy and can't take any
+ *                                  more requests at this moment.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Internal error.
+ */
+ret_code_t pds_peer_data_update(pm_peer_id_t                 peer_id,
+                                pm_peer_data_const_t const * p_peer_data,
+                                pm_store_token_t             old_token,
+                                pm_store_token_t           * p_store_token);
+
+
+/**@brief Function for clearing peer data from persistent storage.
+ *
+ * @details Clearing happens asynchronously. Expect a @ref PDS_EVT_CLEARED or @ref PDS_EVT_ERROR_CLEAR
+ *          event.
+ *
+ * @param[in]  peer_id  The id of the peer the data pertains to.
+ * @param[in]  data_id  Which data to clear.
+ *
+ * @retval NRF_SUCCESS              The clear was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or peer ID was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      Nothing to clear for this peer ID.
+ * @retval NRF_ERROR_BUSY           FDS or underlying modules are busy and can't take any
+ *                                  more requests at this moment.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Internal error.
+ */
+ret_code_t pds_peer_data_clear(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for claiming an unused peer ID.
+ *
+ * @return  The first unused peer ID.
+ * @retval  PM_PEER_ID_INVALID  If no peer ID is available or module is not initialized.
+ */
+pm_peer_id_t pds_peer_id_allocate(void);
+
+
+/**@brief Function for freeing a peer ID and clearing all data associated with it in persistent
+ *        storage.
+ *
+ * @param[in]  peer_id  Peer ID to free.
+ *
+ * @retval NRF_SUCCESS             The clear was initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE Module not initialized.
+ * @retval NRF_ERROR_INVALID_PARAM Invalid peer ID.
+ */
+ret_code_t pds_peer_id_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for finding out whether a peer ID is in use.
+ *
+ * @param[in]  peer_id  The peer ID to inquire about.
+ *
+ * @retval  true   peer_id is in use.
+ * @retval  false  peer_id is free, or the module is not initialized.
+ */
+bool pds_peer_id_is_allocated(pm_peer_id_t peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs. Can be
+ *        used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first ordinary peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID          if prev_peer_id was the last ordinary peer ID or the module
+ *                                      is not initialized.
+ */
+pm_peer_id_t pds_next_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for querying the number of valid peer IDs available. I.E the number of peers
+ *        in persistent storage.
+ *
+ * @return  The number of valid peer IDs, or 0 if module is not initialized.
+ */
+uint32_t pds_n_peers(void);
+
+
+/** @}
+ * @endcond
+ */
+
+#endif /* PEER_DATA_STORAGE_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.c
new file mode 100644
index 0000000000..fd6c30193d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.c
@@ -0,0 +1,804 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "peer_database.h"
+
+#include <string.h>
+#include "app_util.h"
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "peer_data_storage.h"
+#include "pm_buffer.h"
+#include "sdk_common.h"
+
+#define MAX_REGISTRANTS    6                         /**< The number of user that can register with the module. */
+
+#define N_WRITE_BUFFERS        8                     /**< The number of write buffers available. */
+#define N_WRITE_BUFFER_RECORDS (N_WRITE_BUFFERS)     /**< The number of write buffer records. */
+
+/**@brief Macro for verifying that the data ID is among the values eligible for using the write buffer.
+ *
+ * @param[in] data_id  The data ID to verify.
+ */
+#define VERIFY_DATA_ID_WRITE_BUF(data_id)                                                    \
+do                                                                                           \
+{                                                                                            \
+    if (((data_id) != PM_PEER_DATA_ID_BONDING) && ((data_id) != PM_PEER_DATA_ID_GATT_LOCAL)) \
+    {                                                                                        \
+        return NRF_ERROR_INVALID_PARAM;                                                      \
+    }                                                                                        \
+} while(0)
+
+
+/**@brief Struct for keeping track of one write buffer, from allocation, until it is fully written
+ *        or cancelled.
+ */
+typedef struct
+{
+    pm_peer_id_t        peer_id;               /**< The peer ID this buffer belongs to. */
+    pm_peer_data_id_t   data_id;               /**< The data ID this buffer belongs to. */
+    uint8_t             buffer_block_id;       /**< The index of the first (or only) buffer block containing peer data. */
+    uint32_t            n_bufs;                /**< The number of buffer blocks containing peer data. */
+    uint8_t             store_busy       : 1;  /**< Flag indicating that the buffer was attempted written to flash, but a busy error was returned and the operation should be retried. */
+    uint8_t             store_flash_full : 1;  /**< Flag indicating that the buffer was attempted written to flash, but a flash full error was returned and the operation should be retried after room has been made. */
+    uint8_t             store_requested  : 1;  /**< Flag indicating that the buffer is being written to flash. */
+    pm_prepare_token_t  prepare_token;         /**< Token given by Peer Data Storage if room in flash has been reserved. */
+    pm_store_token_t    store_token;           /**< Token given by Peer Data Storage when a flash write has been successfully requested. */
+} pdb_buffer_record_t;
+
+/**@brief Struct for keeping track of the state of the module.
+ */
+typedef struct
+{
+    pdb_evt_handler_t   evt_handlers[MAX_REGISTRANTS];                /**< All registered event handlers. */
+    uint8_t             n_registrants;                                /**< The number of registered event handlers. */
+    pm_buffer_t         write_buffer;                                 /**< The state of the write buffer. */
+    pdb_buffer_record_t write_buffer_records[N_WRITE_BUFFER_RECORDS]; /**< The available write buffer records. */
+    uint32_t            n_writes;                                     /**< The number of pending (Not yet successfully requested in Peer Data Storage) store operations. */
+} pdb_t;
+
+static pdb_t m_pdb = {.n_registrants = 0}; /**< The state of the module. */
+
+#define MODULE_INITIALIZED (m_pdb.n_registrants > 0) /**< Expression which is true when the module is initialized. */
+#include "sdk_macros.h"
+
+/**@brief Function for invalidating a record of a write buffer allocation.
+ *
+ * @param[in]  p_record  The record to invalidate.
+ */
+static void write_buffer_record_invalidate(pdb_buffer_record_t * p_record)
+{
+    p_record->peer_id          = PM_PEER_ID_INVALID;
+    p_record->data_id          = PM_PEER_DATA_ID_INVALID;
+    p_record->buffer_block_id  = BUFFER_INVALID_ID;
+    p_record->store_busy       = false;
+    p_record->store_flash_full = false;
+    p_record->store_requested  = false;
+    p_record->n_bufs           = 0;
+    p_record->prepare_token    = PDS_PREPARE_TOKEN_INVALID;
+    p_record->store_token      = PM_STORE_TOKEN_INVALID;
+}
+
+
+/**@brief Function for finding a record of a write buffer allocation.
+ *
+ * @param[in]    peer_id  The peer ID in the record.
+ * @param[inout] p_index  In: The starting index, out: The index of the record
+ *
+ * @return  A pointer to the matching record, or NULL if none was found.
+ */
+static pdb_buffer_record_t * write_buffer_record_find_next(pm_peer_id_t peer_id, int * p_index)
+{
+    for (uint32_t i = *p_index; i < N_WRITE_BUFFER_RECORDS; i++)
+    {
+        if ((m_pdb.write_buffer_records[i].peer_id == peer_id))
+        {
+            return &m_pdb.write_buffer_records[i];
+        }
+    }
+    return NULL;
+}
+
+
+/**@brief Function for finding a record of a write buffer allocation.
+ *
+ * @param[in]  peer_id  The peer ID in the record.
+ * @param[in]  data_id  The data ID in the record.
+ *
+ * @return  A pointer to the matching record, or NULL if none was found.
+ */
+static pdb_buffer_record_t * write_buffer_record_find(pm_peer_id_t      peer_id,
+                                                      pm_peer_data_id_t data_id)
+{
+    int index = 0;
+    pdb_buffer_record_t * p_record = write_buffer_record_find_next(peer_id, &index);
+
+    while ((p_record != NULL) && (p_record->data_id != data_id))
+    {
+        index++;
+        p_record = write_buffer_record_find_next(peer_id, &index);
+    }
+
+    return p_record;
+}
+
+
+/**@brief Function for finding an available record for write buffer allocation.
+ *
+ * @return  A pointer to the available record, or NULL if none was found.
+ */
+static pdb_buffer_record_t * write_buffer_record_find_unused(void)
+{
+    return write_buffer_record_find(PM_PEER_ID_INVALID, PM_PEER_DATA_ID_INVALID);
+}
+
+
+/**@brief Function for gracefully deactivating a write buffer record.
+ *
+ * @details This function will first release any buffers, then invalidate the record.
+ *
+ * @param[inout] p_write_buffer_record  The record to release.
+ *
+ * @return  A pointer to the matching record, or NULL if none was found.
+ */
+static void write_buffer_record_release(pdb_buffer_record_t * p_write_buffer_record)
+{
+    for (uint32_t i = 0; i < p_write_buffer_record->n_bufs; i++)
+    {
+        pm_buffer_release(&m_pdb.write_buffer, p_write_buffer_record->buffer_block_id + i);
+    }
+
+    write_buffer_record_invalidate(p_write_buffer_record);
+}
+
+
+/**@brief Function for claiming and activating a write buffer record.
+ *
+ * @param[out] pp_write_buffer_record  The claimed record.
+ * @param[in]   peer_id                 The peer ID this record should have.
+ * @param[in]  data_id                 The data ID this record should have.
+ */
+static void write_buffer_record_get(pdb_buffer_record_t ** pp_write_buffer_record, pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    if (pp_write_buffer_record == NULL)
+    {
+        return;
+    }
+    *pp_write_buffer_record = write_buffer_record_find_unused();
+    if (*pp_write_buffer_record == NULL)
+    {
+        // This also means the buffer is full.
+        return;
+    }
+    (*pp_write_buffer_record)->peer_id = peer_id;
+    (*pp_write_buffer_record)->data_id = data_id;
+}
+
+
+/**@brief Function for dispatching outbound events to all registered event handlers.
+ *
+ * @param[in]  p_event  The event to dispatch.
+ */
+static void pdb_evt_send(pdb_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < m_pdb.n_registrants; i++)
+    {
+        m_pdb.evt_handlers[i](p_event);
+    }
+}
+
+
+/**@brief Function for resetting the internal state of the Peer Database module.
+ *
+ * @param[out] p_event  The event to dispatch.
+ */
+static void internal_state_reset(pdb_t * pdb)
+{
+    memset(pdb, 0, sizeof(pdb_t));
+    for (uint32_t i = 0; i < N_WRITE_BUFFER_RECORDS; i++)
+    {
+        write_buffer_record_invalidate(&pdb->write_buffer_records[i]);
+    }
+}
+
+
+/**@brief Function for handling events from the Peer Data Storage module.
+ *
+ * @param[in]  p_event  The event to handle.
+ */
+static void pds_evt_handler(pds_evt_t const * p_event)
+{
+    ret_code_t            err_code;
+    pdb_buffer_record_t * p_write_buffer_record;
+    bool                  retry_flash_full = false;
+    pdb_evt_t             event =
+    {
+        .peer_id = p_event->peer_id,
+        .data_id = p_event->data_id,
+    };
+
+    p_write_buffer_record = write_buffer_record_find(p_event->peer_id, p_event->data_id);
+
+    switch (p_event->evt_id)
+    {
+        case PDS_EVT_STORED:
+        case PDS_EVT_UPDATED:
+            if (   (p_write_buffer_record != NULL)
+                //&& (p_write_buffer_record->store_token == p_event->store_token)
+                && (p_write_buffer_record->store_requested))
+            {
+                write_buffer_record_release(p_write_buffer_record);
+                event.evt_id = PDB_EVT_WRITE_BUF_STORED;
+                event.params.write_buf_stored_evt.update = (p_event->evt_id == PDS_EVT_UPDATED);
+                pdb_evt_send(&event);
+            }
+            else
+            {
+                event.evt_id = PDB_EVT_RAW_STORED;
+                event.params.raw_stored_evt.store_token = p_event->store_token;
+                pdb_evt_send(&event);
+            }
+            break;
+        case PDS_EVT_ERROR_STORE:
+        case PDS_EVT_ERROR_UPDATE:
+            if (   (p_write_buffer_record != NULL)
+                && (p_write_buffer_record->store_token == p_event->store_token)
+                && (p_write_buffer_record->store_requested))
+            {
+                // Retry if internal buffer.
+                m_pdb.n_writes++;
+                p_write_buffer_record->store_requested = false;
+                p_write_buffer_record->store_busy      = true;
+            }
+            else
+            {
+                event.evt_id                              = PDB_EVT_RAW_STORE_FAILED;
+                event.params.error_raw_store_evt.err_code = p_event->result;
+                pdb_evt_send(&event);
+            }
+            break;
+        case PDS_EVT_CLEARED:
+            event.evt_id = PDB_EVT_CLEARED;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_ERROR_CLEAR:
+            event.evt_id = PDB_EVT_CLEAR_FAILED;
+            event.params.clear_failed_evt.err_code = p_event->result;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_PEER_ID_CLEAR:
+            event.evt_id = PDB_EVT_PEER_FREED;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_ERROR_PEER_ID_CLEAR:
+            event.evt_id = PDB_EVT_PEER_FREE_FAILED;
+            event.params.peer_free_failed_evt.err_code = p_event->result;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_COMPRESSED:
+            retry_flash_full = true;
+            event.evt_id = PDB_EVT_COMPRESSED;
+            pdb_evt_send(&event);
+            break;
+        case PDS_EVT_ERROR_UNEXPECTED:
+            event.params.error_unexpected.err_code = p_event->result;
+            break;
+        default:
+            break;
+    }
+
+    if (m_pdb.n_writes > 0)
+    {
+        for (uint32_t i = 0; i < N_WRITE_BUFFER_RECORDS; i++)
+        {
+            if  ((m_pdb.write_buffer_records[i].store_busy)
+              || (m_pdb.write_buffer_records[i].store_flash_full && retry_flash_full))
+            {
+                err_code = pdb_write_buf_store(m_pdb.write_buffer_records[i].peer_id,
+                                               m_pdb.write_buffer_records[i].data_id);
+                if (err_code != NRF_SUCCESS)
+                {
+                    event.peer_id = m_pdb.write_buffer_records[i].peer_id;
+                    event.data_id = m_pdb.write_buffer_records[i].data_id;
+                    if (err_code == NRF_ERROR_NO_MEM)
+                    {
+                        event.evt_id = PDB_EVT_ERROR_NO_MEM;
+                    }
+                    else
+                    {
+                        event.evt_id                           = PDB_EVT_ERROR_UNEXPECTED;
+                        event.params.error_unexpected.err_code = err_code;
+                    }
+
+                    pdb_evt_send(&event);
+                    break;
+                }
+            }
+        }
+    }
+}
+
+
+ret_code_t pdb_register(pdb_evt_handler_t evt_handler)
+{
+    if (m_pdb.n_registrants >= MAX_REGISTRANTS)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+
+    if (!MODULE_INITIALIZED)
+    {
+        ret_code_t err_code;
+
+        internal_state_reset(&m_pdb);
+        err_code = pds_register(pds_evt_handler);
+        if (err_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+        PM_BUFFER_INIT(&m_pdb.write_buffer, N_WRITE_BUFFERS, PDB_WRITE_BUF_SIZE, err_code);
+        if (err_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    }
+
+    m_pdb.evt_handlers[m_pdb.n_registrants] = evt_handler;
+    m_pdb.n_registrants += 1;
+
+    return NRF_SUCCESS;
+}
+
+
+pm_peer_id_t pdb_peer_allocate(void)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+
+    return pds_peer_id_allocate();
+}
+
+
+ret_code_t pdb_peer_free(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    ret_code_t err_code_in  = NRF_SUCCESS;
+    ret_code_t err_code_out = NRF_SUCCESS;
+
+    int index = 0;
+    pdb_buffer_record_t * p_record = write_buffer_record_find_next(peer_id, &index);
+
+    while (p_record != NULL)
+    {
+        err_code_in = pdb_write_buf_release(peer_id, p_record->data_id);
+
+        if (   (err_code_in != NRF_SUCCESS)
+            && (err_code_in != NRF_ERROR_NOT_FOUND))
+        {
+            err_code_out = NRF_ERROR_INTERNAL;
+        }
+
+        index++;
+        p_record = write_buffer_record_find_next(peer_id, &index);
+    }
+
+    if (err_code_out == NRF_SUCCESS)
+    {
+        err_code_in = pds_peer_id_free(peer_id);
+
+        if (err_code_in == NRF_SUCCESS)
+        {
+            // No action needed.
+        }
+        else if (err_code_in == NRF_ERROR_INVALID_PARAM)
+        {
+            err_code_out = NRF_ERROR_INVALID_PARAM;
+        }
+        else
+        {
+            err_code_out = NRF_ERROR_INTERNAL;
+        }
+    }
+
+    return err_code_out;
+}
+
+
+ret_code_t pdb_read_buf_get(pm_peer_id_t           peer_id,
+                            pm_peer_data_id_t      data_id,
+                            pm_peer_data_flash_t * p_peer_data,
+                            pm_store_token_t     * p_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return pds_peer_data_read_ptr_get(peer_id, data_id, p_peer_data, p_token);
+}
+
+
+static void peer_data_point_to_buffer(pm_peer_data_t * p_peer_data, pm_peer_data_id_t data_id, uint8_t * p_buffer_memory, uint16_t n_bufs)
+{
+    uint16_t n_bytes = n_bufs * PDB_WRITE_BUF_SIZE;
+    p_peer_data->data_id    = data_id;
+
+    p_peer_data->p_all_data   = (pm_peer_data_bonding_t *)p_buffer_memory;
+    p_peer_data->length_words = BYTES_TO_WORDS(n_bytes);
+}
+
+
+static void peer_data_const_point_to_buffer(pm_peer_data_const_t * p_peer_data, pm_peer_data_id_t data_id,  uint8_t * p_buffer_memory, uint32_t n_bufs)
+{
+    peer_data_point_to_buffer((pm_peer_data_t*)p_peer_data, data_id, p_buffer_memory, n_bufs);
+}
+
+
+static void write_buf_length_words_set(pm_peer_data_const_t * p_peer_data)
+{
+    switch (p_peer_data->data_id)
+    {
+        case PM_PEER_DATA_ID_BONDING:
+            p_peer_data->length_words = PM_BONDING_DATA_N_WORDS();
+            break;
+        case PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING:
+            p_peer_data->length_words = PM_SC_STATE_N_WORDS();
+            break;
+        case PM_PEER_DATA_ID_PEER_RANK:
+            p_peer_data->length_words = PM_USAGE_INDEX_N_WORDS();
+            break;
+        case PM_PEER_DATA_ID_GATT_LOCAL:
+            p_peer_data->length_words = PM_LOCAL_DB_N_WORDS(p_peer_data->p_local_gatt_db->len);
+            break;
+        default:
+            // No action needed.
+            break;
+    }
+}
+
+
+ret_code_t pdb_write_buf_get(pm_peer_id_t       peer_id,
+                             pm_peer_data_id_t  data_id,
+                             uint32_t           n_bufs,
+                             pm_peer_data_t   * p_peer_data)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_peer_data);
+    VERIFY_DATA_ID_WRITE_BUF(data_id);
+    if (   (n_bufs == 0)
+        || (n_bufs > N_WRITE_BUFFERS)
+        || !pds_peer_id_is_allocated(peer_id))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    pdb_buffer_record_t * write_buffer_record;
+    uint8_t             * p_buffer_memory;
+    bool                  new_record = false;
+
+    write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if ((write_buffer_record != NULL) && (write_buffer_record->n_bufs < n_bufs))
+    {
+        // @TODO: Copy?
+        // Existing buffer is too small.
+        for (uint8_t i = 0; i < write_buffer_record->n_bufs; i++)
+        {
+            pm_buffer_release(&m_pdb.write_buffer, write_buffer_record->buffer_block_id + i);
+        }
+        write_buffer_record_invalidate(write_buffer_record);
+        write_buffer_record = NULL;
+    }
+    else if ((write_buffer_record != NULL) && write_buffer_record->n_bufs > n_bufs)
+    {
+        // Release excess blocks.
+        for (uint8_t i = n_bufs; i < write_buffer_record->n_bufs; i++)
+        {
+            pm_buffer_release(&m_pdb.write_buffer, write_buffer_record->buffer_block_id + i);
+        }
+    }
+
+    if (write_buffer_record == NULL)
+    {
+        write_buffer_record_get(&write_buffer_record, peer_id, data_id);
+        if (write_buffer_record == NULL)
+        {
+            return NRF_ERROR_BUSY;
+        }
+    }
+
+    if (write_buffer_record->buffer_block_id == BUFFER_INVALID_ID)
+    {
+        write_buffer_record->buffer_block_id = pm_buffer_block_acquire(&m_pdb.write_buffer, n_bufs);
+
+        if (write_buffer_record->buffer_block_id == BUFFER_INVALID_ID)
+        {
+            write_buffer_record_invalidate(write_buffer_record);
+            return NRF_ERROR_BUSY;
+        }
+
+        new_record = true;
+    }
+
+    write_buffer_record->n_bufs = n_bufs;
+
+    p_buffer_memory = pm_buffer_ptr_get(&m_pdb.write_buffer, write_buffer_record->buffer_block_id);
+
+    if (p_buffer_memory == NULL)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    peer_data_point_to_buffer(p_peer_data, data_id, p_buffer_memory, n_bufs);
+    if (new_record && (data_id == PM_PEER_DATA_ID_GATT_LOCAL))
+    {
+        p_peer_data->p_local_gatt_db->len = PM_LOCAL_DB_LEN(p_peer_data->length_words);
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pdb_write_buf_release(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t            err_code = NRF_SUCCESS;
+    pdb_buffer_record_t * p_write_buffer_record;
+    p_write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if (p_write_buffer_record == NULL)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (p_write_buffer_record->prepare_token != PDS_PREPARE_TOKEN_INVALID)
+    {
+        err_code = pds_peer_data_write_prepare_cancel(p_write_buffer_record->prepare_token);
+        if (err_code != NRF_SUCCESS)
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+    }
+
+    write_buffer_record_release(p_write_buffer_record);
+
+    return err_code;
+}
+
+
+ret_code_t pdb_write_buf_store_prepare(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_DATA_ID_WRITE_BUF(data_id);
+
+    ret_code_t            err_code = NRF_SUCCESS;
+    pdb_buffer_record_t * p_write_buffer_record;
+    p_write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if (p_write_buffer_record == NULL)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (p_write_buffer_record->prepare_token == PDS_PREPARE_TOKEN_INVALID)
+    {
+        uint8_t * p_buffer_memory = pm_buffer_ptr_get(&m_pdb.write_buffer, p_write_buffer_record->buffer_block_id);
+        pm_peer_data_const_t peer_data = {.data_id = data_id};
+
+        if (p_buffer_memory == NULL)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+
+        peer_data_const_point_to_buffer(&peer_data, data_id, p_buffer_memory, p_write_buffer_record->n_bufs);
+
+        write_buf_length_words_set(&peer_data);
+
+        err_code = pds_peer_data_write_prepare(&peer_data, &p_write_buffer_record->prepare_token);
+        if (err_code == NRF_ERROR_INVALID_LENGTH)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    }
+
+    return err_code;
+}
+
+
+static ret_code_t write_or_update(pm_peer_id_t           peer_id,
+                                  pm_peer_data_id_t      data_id,
+                                  pm_peer_data_const_t * p_peer_data,
+                                  pm_store_token_t     * p_store_token,
+                                  pm_prepare_token_t     prepare_token)
+{
+    pm_peer_data_flash_t old_peer_data;
+    pm_store_token_t     old_store_token;
+    ret_code_t err_code = pds_peer_data_read_ptr_get(peer_id, data_id, &old_peer_data, &old_store_token);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        err_code = pds_peer_data_write_prepare_cancel(prepare_token);
+        if ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NULL))
+        {
+            err_code = pds_peer_data_update(peer_id, p_peer_data, old_store_token, p_store_token);
+        }
+        else
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+    }
+    else if (err_code == NRF_ERROR_NOT_FOUND)
+    {
+        if (prepare_token == PDS_PREPARE_TOKEN_INVALID)
+        {
+            err_code = pds_peer_data_write(peer_id, p_peer_data, p_store_token);
+        }
+        else
+        {
+            err_code = pds_peer_data_write_prepared(peer_id, p_peer_data, prepare_token, p_store_token);
+        }
+    }
+    return err_code;
+}
+
+
+ret_code_t pdb_write_buf_store(pm_peer_id_t      peer_id,
+                               pm_peer_data_id_t data_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_DATA_ID_WRITE_BUF(data_id);
+
+    ret_code_t            err_code = NRF_SUCCESS;
+    pdb_buffer_record_t * p_write_buffer_record;
+    uint8_t             * p_buffer_memory;
+    pm_peer_data_const_t  peer_data = {.data_id = data_id};
+
+
+    p_write_buffer_record = write_buffer_record_find(peer_id, data_id);
+
+    if (p_write_buffer_record == NULL)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if (p_write_buffer_record->store_requested)
+    {
+        return NRF_SUCCESS;
+    }
+
+    p_buffer_memory = pm_buffer_ptr_get(&m_pdb.write_buffer, p_write_buffer_record->buffer_block_id);
+
+    if (p_buffer_memory == NULL)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    peer_data_const_point_to_buffer(&peer_data, data_id, p_buffer_memory, p_write_buffer_record->n_bufs);
+
+    write_buf_length_words_set(&peer_data);
+
+    err_code = write_or_update(peer_id, data_id, &peer_data, &p_write_buffer_record->store_token, p_write_buffer_record->prepare_token);
+
+    if (p_write_buffer_record->store_busy && p_write_buffer_record->store_flash_full)
+    {
+        m_pdb.n_writes--;
+    }
+
+    if (err_code == NRF_SUCCESS)
+    {
+        p_write_buffer_record->store_requested  = true;
+        p_write_buffer_record->store_busy       = false;
+        p_write_buffer_record->store_flash_full = false;
+    }
+    else
+    {
+        if (err_code == NRF_ERROR_BUSY)
+        {
+            m_pdb.n_writes++;
+            p_write_buffer_record->store_busy       = true;
+            p_write_buffer_record->store_flash_full = false;
+            err_code = NRF_SUCCESS;
+        }
+        else if (err_code == NRF_ERROR_NO_MEM)
+        {
+            m_pdb.n_writes++;
+            p_write_buffer_record->store_busy       = false;
+            p_write_buffer_record->store_flash_full = true;
+        }
+        else if ((err_code != NRF_ERROR_NO_MEM) && (err_code != NRF_ERROR_INVALID_PARAM))
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+    }
+
+    return err_code;
+}
+
+
+ret_code_t pdb_clear(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return pds_peer_data_clear(peer_id, data_id);
+}
+
+
+uint32_t pdb_n_peers(void)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return 0;
+    }
+
+    return pds_n_peers();
+}
+
+
+pm_peer_id_t pdb_next_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+
+    return pds_next_peer_id_get(prev_peer_id);
+}
+
+
+ret_code_t pdb_raw_read(pm_peer_id_t      peer_id,
+                        pm_peer_data_id_t data_id,
+                        pm_peer_data_t  * p_peer_data)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return pds_peer_data_read(peer_id, data_id, p_peer_data, &p_peer_data->length_words);
+}
+
+
+ret_code_t pdb_raw_store(pm_peer_id_t           peer_id,
+                         pm_peer_data_const_t * p_peer_data,
+                         pm_store_token_t     * p_store_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return write_or_update(peer_id, p_peer_data->data_id, p_peer_data, p_store_token, PDS_PREPARE_TOKEN_INVALID);
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.h
new file mode 100644
index 0000000000..c0eee65774
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_database.h
@@ -0,0 +1,385 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef PEER_DATABASE_H__
+#define PEER_DATABASE_H__
+
+#include <stdint.h>
+#include "peer_manager_types.h"
+#include "peer_manager_internal.h"
+#include "sdk_errors.h"
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_database Peer Database
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for simple management of reading and
+ *        writing of peer data into persistent storage.
+ *
+ */
+
+#define PDB_WRITE_BUF_SIZE (sizeof(pm_peer_data_bonding_t))
+
+/**@brief Events that can come from the peer_database module.
+ */
+typedef enum
+{
+    PDB_EVT_WRITE_BUF_STORED,   /**< A @ref pdb_write_buf_store operation has completed successfully. */
+    PDB_EVT_RAW_STORED,         /**< A @ref pdb_raw_store operation has completed successfully. */
+    PDB_EVT_RAW_STORE_FAILED,   /**< A @ref pdb_raw_store operation has failed. */
+    PDB_EVT_CLEARED,            /**< A @ref pdb_clear operation has completed successfully. */
+    PDB_EVT_CLEAR_FAILED,       /**< A @ref pdb_clear operation has failed. */
+    PDB_EVT_PEER_FREED,         /**< A @ref pdb_peer_free operation has completed successfully. All associated data has been erased. */
+    PDB_EVT_PEER_FREE_FAILED,   /**< A @ref pdb_peer_free operation has failed. */
+    PDB_EVT_COMPRESSED,         /**< A compress procedure has completed. */
+    PDB_EVT_ERROR_NO_MEM,       /**< An operation is blocked because the flash is full. It will be reattempted automatically after the next compress procedure. */
+    PDB_EVT_ERROR_UNEXPECTED,   /**< An unexpected error occurred. This is a fatal error. */
+} pdb_evt_id_t;
+
+/**@brief Events that can come from the peer_database module.
+ */
+typedef struct
+{
+    pdb_evt_id_t      evt_id;  /**< The event that has happened. */
+    pm_peer_id_t      peer_id; /**< The id of the peer the event pertains to. */
+    pm_peer_data_id_t data_id; /**< The data the event pertains to. */
+    union
+    {
+        struct
+        {
+            bool update;                   /**< If true, an existing value was overwritten. */
+        } write_buf_stored_evt;            /**< Additional information pertaining to the @ref PDB_EVT_WRITE_BUF_STORED event. */
+        struct
+        {
+            pm_store_token_t store_token;  /**< A token identifying the store operation this event pertains to. */
+        } raw_stored_evt;                  /**< Additional information pertaining to the @ref PDB_EVT_RAW_STORED event. */
+        struct
+        {
+            pm_store_token_t store_token;  /**< A token identifying the store operation this event pertains to. */
+            ret_code_t       err_code;     /**< Error code specifying what went wrong. */
+        } error_raw_store_evt;             /**< Additional information pertaining to the @ref PDB_EVT_RAW_STORE_FAILED event. */
+        struct
+        {
+            ret_code_t err_code;           /**< The error that occurred. */
+        } clear_failed_evt;                /**< Additional information pertaining to the @ref PDB_EVT_CLEAR_FAILED event. */
+        struct
+        {
+            ret_code_t err_code;           /**< The error that occurred. */
+        } peer_free_failed_evt;            /**< Additional information pertaining to the @ref PDB_EVT_PEER_FREE_FAILED event. */
+        struct
+        {
+            ret_code_t err_code;           /**< The unexpected error that occurred. */
+        } error_unexpected;                /**< Additional information pertaining to the @ref PDB_EVT_ERROR_UNEXPECTED event. */
+    } params;
+} pdb_evt_t;
+
+/**@brief Event handler for events from the peer_data_storage module.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+typedef void (*pdb_evt_handler_t)(pdb_evt_t const * p_event);
+
+
+/**@brief Function for registering for events from the peer database.
+ *
+ * @note This function will initialize the module if it is not already initialized.
+ *
+ * @param[in]  evt_handler  Event handler to register.
+ *
+ * @retval NRF_SUCCESS              Registration successful.
+ * @retval NRF_ERROR_NO_MEM         No more event handlers can be registered.
+ * @retval NRF_ERROR_NULL           evt_handler was NULL.
+ * @retval NRF_ERROR_INTERNAL       An unexpected error happened.
+ */
+ret_code_t pdb_register(pdb_evt_handler_t evt_handler);
+
+
+/**@brief Function for allocating persistent bond storage for a peer.
+ *
+ * @return  The ID of the newly allocated storage.
+ * @retval  PM_PEER_ID_INVALID  If no peer ID is available.
+ */
+pm_peer_id_t pdb_peer_allocate(void);
+
+
+/**@brief Function for freeing a peer's persistent bond storage.
+ *
+ * @note This function will call @ref pdb_write_buf_release on the data for this peer.
+ *
+ * @param[in] peer_id  ID to be freed.
+ *
+ * @retval NRF_SUCCESS              Peer ID was released and clear operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Peer ID was invalid.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_peer_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for retrieving pointers to read-only peer data.
+ *
+ * @note  Reading this pointer is not safe in the strictest sense. If a safe read is required:
+ *          - Disable interrupts
+ *          - Call this function. If the return code is @ref NRF_SUCCESS, the following read is safe.
+ *          - Read memory.
+ *          - Enable interrupts.
+ * @note  This buffer does not need to be released. It is a pointer directly to flash.
+ *
+ * @param[in]  peer_id      ID of peer to retrieve data for.
+ * @param[in]  data_id      Which piece of data to get.
+ * @param[out] p_peer_data  Pointer to immutable peer data.
+ * @param[out] p_token      Token that can be used to lock data in flash and check data validity.
+ *
+ * @retval NRF_SUCCESS              Data retrieved successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or Peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_peer_data was NULL.
+ * @retval NRF_ERROR_NOT_FOUND      This data was not found for this peer ID.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_read_buf_get(pm_peer_id_t           peer_id,
+                            pm_peer_data_id_t      data_id,
+                            pm_peer_data_flash_t * p_peer_data,
+                            pm_store_token_t     * p_token);
+
+
+/**@brief Function for retrieving pointers to a write buffer for peer data.
+ *
+ * @details This function will provide pointers to a buffer of the data. The data buffer will not be
+ *          written to persistent storage until @ref pdb_write_buf_store is called. The buffer is
+ *          released by calling either @ref pdb_write_buf_release, @ref pdb_write_buf_store, or
+ *          @ref pdb_peer_free.
+ *
+ *          When the data_id refers to a variable length data type, the available size is written
+ *          to the data, both the top-level, and any internal length fields.
+ *
+ * @note Calling this function on a peer_id/data_id pair that already has a buffer created will
+ *       give the same buffer, not create a new one. If n_bufs was increased since last time, the
+ *       buffer might be relocated to be able to provide additional room. In this case, the data
+ *       will be copied. If n_bufs was increased since last time, this function might return @ref
+ *       NRF_ERROR_BUSY. In that case, the buffer is automatically released.
+ *
+ * @param[in]  peer_id      ID of peer to get a write buffer for.
+ * @param[in]  data_id      Which piece of data to get.
+ * @param[in]  n_bufs       The number of contiguous buffers needed.
+ * @param[out] p_peer_data  Pointers to mutable peer data.
+ *
+ * @retval NRF_SUCCESS              Data retrieved successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or Peer ID was invalid or unallocated, or n_bufs was 0
+ *                                  or more than the total available buffers.
+ * @retval NRF_ERROR_NULL           p_peer_data was NULL.
+ * @retval NRF_ERROR_BUSY           Not enough buffer(s) available.
+ * @retval NRF_ERROR_INTERNAL       Unexpected internal error.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_write_buf_get(pm_peer_id_t      peer_id,
+                             pm_peer_data_id_t data_id,
+                             uint32_t          n_bufs,
+                             pm_peer_data_t  * p_peer_data);
+
+
+/**@brief Function for freeing a write buffer allocated with @ref pdb_write_buf_get.
+ *
+ * @note This function will not write peer data to persistent memory. Data in released buffer will
+ *       be lost.
+ *
+ * @note This function will undo any previous call to @ref pdb_write_buf_store_prepare for this
+ *       piece of data.
+ *
+ * @param[in]  peer_id  ID of peer to release buffer for.
+ * @param[in]  data_id  Which piece of data to release buffer for.
+ *
+ * @retval NRF_SUCCESS              Successfully released buffer.
+ * @retval NRF_ERROR_NOT_FOUND      No buffer was allocated for this peer ID/data ID pair.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Unexpected internal error.
+ */
+ret_code_t pdb_write_buf_release(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for reserving space in persistent storage for data in a buffer.
+ *
+ * @note This function only works for data which has a write buffer allocated. If the write buffer
+ *       is released, this prepare is undone.
+ *
+ * @note If space has already been reserved for this data, nothing is done.
+ *
+ * @param[in]  peer_id  The peer whose data to reserve space for.
+ * @param[in]  data_id  The type of data to reserve space for.
+ *
+ * @retval NRF_SUCCESS              Successfully reserved space in persistent storage.
+ * @retval NRF_ERROR_NO_MEM         Not enough room in persistent storage.
+ * @retval NRF_ERROR_BUSY           Could not process request at this time. Reattempt later.
+ * @retval NRF_ERROR_NOT_FOUND      No buffer has been allocated for this peer ID/data ID pair.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or Peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_write_buf_store_prepare(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for writing data into persistent storage. Writing happens asynchronously.
+ *
+ * @note This will unlock the data after it has been written.
+ *
+ * @param[in]  peer_id      ID of peer to store data for.
+ * @param[in]  data_id      Which piece of data to store.
+ *
+ * @retval NRF_SUCCESS              Data storing was successfully started.
+ * @retval NRF_ERROR_NO_MEM         No space available in persistent storage. Please clear some
+ *                                  space, the operation will be reattempted after the next compress
+ *                                  procedure. This error will not happen if
+ *                                  @ref pdb_write_buf_store_prepare is called beforehand.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      No buffer has been allocated for this peer ID/data ID pair.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Unexpected internal error.
+ */
+ret_code_t pdb_write_buf_store(pm_peer_id_t      peer_id,
+                               pm_peer_data_id_t data_id);
+
+
+/**@brief Function for clearing data from persistent storage.
+ *
+ * @param[in]  peer_id  ID of peer to clear data for.
+ * @param[in]  data_id  Which piece of data to clear.
+ *
+ * @retval NRF_SUCCESS              The clear was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or peer ID was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      Nothing to clear for this peer ID/data ID combination.
+ * @retval NRF_ERROR_BUSY           Underlying modules are busy and can't take any more requests at
+ *                                  this moment.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL       Internal error.
+ */
+ret_code_t pdb_clear(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for querying the number of valid peer IDs available. I.E the number of peers
+ *        in persistent storage.
+ *
+ * @return  The number of valid peer IDs.
+ */
+uint32_t pdb_n_peers(void);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs. Can be
+ *        used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first ordinary peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID          if prev_peer_id was the last ordinary peer ID.
+ */
+pm_peer_id_t pdb_next_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for updating currently stored peer data to a new version
+ *
+ * @details Updating happens asynchronously.
+ *          Expect a @ref PDS_EVT_STORED or @ref PDS_EVT_ERROR_STORE for the store token
+ *          and a @ref PDS_EVT_ERROR_CLEAR or @ref PDS_EVT_ERROR_CLEAR for the old token
+ *
+ * @param[in]   peer_data           New data
+ * @param[in]   old_token           Store token for the old data
+ * @param[out]  p_store_token       Store token for the new data
+ *
+ * @retval NRF_SUCESS               The update was initiated successfully
+ * @retval NRF_ERROR_NOT_FOUND      The old store token was invalid.
+ * @retval NRF_ERROR_NULL           Data contained a NULL pointer.
+ * @retval NRF_ERROR_NO_MEM         No space available in persistent storage.
+ * @retval NRF_ERROR_BUSY           FDS or underlying modules are busy and can't take any
+ *                                  more requests
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_peer_data_update(pm_peer_data_const_t        peer_data,
+                                pm_store_token_t            old_token,
+                                pm_store_token_t          * p_store_token);
+
+
+/**@brief Function for reading data directly from persistent storage to external memory.
+ *
+ * @param[in]    peer_id      ID of peer to read data for.
+ * @param[in]    data_id      Which piece of data to read.
+ * @param[inout] p_peer_data  Where to store the data. If the data to be read has variable length,
+ *                            the appropriate length field needs to reflect the available buffer
+ *                            space. On a successful read, the length field is updated to match the
+ *                            length of the read data.
+ *
+ * @retval NRF_SUCCESS              Data successfully read.
+ * @retval NRF_ERROR_INVALID_PARAM  Data ID or Peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL           p_peer_data contained a NULL pointer.
+ * @retval NRF_ERROR_NOT_FOUND      This data was not found for this peer ID.
+ * @retval NRF_ERROR_DATA_SIZE      The provided buffer was not large enough.
+ * @retval NRF_ERROR_INVALID_STATE  Module is not initialized.
+ */
+ret_code_t pdb_raw_read(pm_peer_id_t      peer_id,
+                        pm_peer_data_id_t data_id,
+                        pm_peer_data_t  * p_peer_data);
+
+
+/**@brief Function for writing data directly to persistent storage from external memory.
+ *
+ * @param[in]  peer_id        ID of peer to write data for.
+ * @param[in]  p_peer_data    Data to store.
+ * @param[out] p_store_token  A token identifying this particular store operation. The token can be
+ *                            used to identify events pertaining to this operation.
+ *
+ * @retval NRF_SUCCESS               Data successfully written.
+ * @retval NRF_ERROR_INVALID_PARAM   Data ID or Peer ID was invalid or unallocated.
+ * @retval NRF_ERROR_NULL            p_peer_data contained a NULL pointer.
+ * @retval NRF_ERROR_NO_MEM          No space available in persistent storage.
+ * @retval NRF_ERROR_INVALID_LENGTH  Data length above the maximum allowed.
+ * @retval NRF_ERROR_INVALID_STATE   Module is not initialized.
+ * @retval NRF_ERROR_BUSY            Unable to perform operation at this time.
+ */
+ret_code_t pdb_raw_store(pm_peer_id_t           peer_id,
+                         pm_peer_data_const_t * p_peer_data,
+                         pm_store_token_t     * p_store_token);
+
+/** @}
+ * @endcond
+ */
+
+#endif /* PEER_DATABASE_H__ */
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.c
new file mode 100644
index 0000000000..df7ac58e2b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.c
@@ -0,0 +1,186 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "peer_id.h"
+
+#include <stdint.h>
+#include <string.h>
+#include "sdk_errors.h"
+#include "peer_manager_types.h"
+#include "pm_mutex.h"
+
+
+typedef struct
+{
+    uint8_t active_peer_ids[MUTEX_STORAGE_SIZE(PM_PEER_ID_N_AVAILABLE_IDS)];  /**< Bitmap designating which peer IDs are in use. */
+    uint8_t deleted_peer_ids[MUTEX_STORAGE_SIZE(PM_PEER_ID_N_AVAILABLE_IDS)]; /**< Bitmap designating which peer IDs are marked for deletion. */
+} pi_t;
+
+
+static pi_t m_pi = {{0}, {0}};
+
+
+static void internal_state_reset(pi_t * p_pi)
+{
+    memset(p_pi, 0, sizeof(pi_t));
+}
+
+
+void peer_id_init(void)
+{
+    internal_state_reset(&m_pi);
+    pm_mutex_init(m_pi.active_peer_ids, PM_PEER_ID_N_AVAILABLE_IDS);
+    pm_mutex_init(m_pi.deleted_peer_ids, PM_PEER_ID_N_AVAILABLE_IDS);
+}
+
+
+static pm_peer_id_t claim(pm_peer_id_t peer_id, uint8_t * mutex_group)
+{
+    pm_peer_id_t allocated_peer_id = PM_PEER_ID_INVALID;
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        allocated_peer_id = pm_mutex_lock_first_available(mutex_group, PM_PEER_ID_N_AVAILABLE_IDS);
+        if (allocated_peer_id == PM_PEER_ID_N_AVAILABLE_IDS)
+        {
+            allocated_peer_id = PM_PEER_ID_INVALID;
+        }
+    }
+    else if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        bool lock_success = pm_mutex_lock(mutex_group, peer_id);
+        allocated_peer_id = lock_success ? peer_id : PM_PEER_ID_INVALID;
+    }
+    return allocated_peer_id;
+}
+
+
+static void release(pm_peer_id_t peer_id, uint8_t * mutex_group)
+{
+    if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        pm_mutex_unlock(mutex_group, peer_id);
+    }
+}
+
+
+pm_peer_id_t peer_id_allocate(pm_peer_id_t peer_id)
+{
+    return claim(peer_id, m_pi.active_peer_ids);
+}
+
+
+bool peer_id_delete(pm_peer_id_t peer_id)
+{
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        return false;
+    }
+    pm_peer_id_t deleted_id = claim(peer_id, m_pi.deleted_peer_ids);
+    return (deleted_id == peer_id);
+}
+
+
+void peer_id_free(pm_peer_id_t peer_id)
+{
+    release(peer_id, m_pi.active_peer_ids);
+    release(peer_id, m_pi.deleted_peer_ids);
+}
+
+
+bool peer_id_is_allocated(pm_peer_id_t peer_id)
+{
+    if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        return pm_mutex_lock_status_get(m_pi.active_peer_ids, peer_id);
+    }
+    return false;
+}
+
+
+bool peer_id_is_deleted(pm_peer_id_t peer_id)
+{
+    if (peer_id < PM_PEER_ID_N_AVAILABLE_IDS)
+    {
+        return pm_mutex_lock_status_get(m_pi.deleted_peer_ids, peer_id);
+    }
+    return false;
+}
+
+
+pm_peer_id_t next_id_get(pm_peer_id_t prev_peer_id, uint8_t * mutex_group)
+{
+    pm_peer_id_t i = (prev_peer_id == PM_PEER_ID_INVALID) ? 0 : (prev_peer_id + 1);
+    for (; i < PM_PEER_ID_N_AVAILABLE_IDS; i++)
+    {
+        if (pm_mutex_lock_status_get(mutex_group, i))
+        {
+            return i;
+        }
+    }
+
+    return PM_PEER_ID_INVALID;
+}
+
+
+pm_peer_id_t peer_id_get_next_used(pm_peer_id_t prev_peer_id)
+{
+    return next_id_get(prev_peer_id, m_pi.active_peer_ids);
+}
+
+
+pm_peer_id_t peer_id_get_next_deleted(pm_peer_id_t prev_peer_id)
+{
+    return next_id_get(prev_peer_id, m_pi.deleted_peer_ids);
+}
+
+
+uint32_t peer_id_n_ids(void)
+{
+    uint32_t n_ids = 0;
+
+    for (pm_peer_id_t i = 0; i < PM_PEER_ID_N_AVAILABLE_IDS; i++)
+    {
+        n_ids += pm_mutex_lock_status_get(m_pi.active_peer_ids, i);
+    }
+
+    return n_ids;
+}
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.h
new file mode 100644
index 0000000000..ac68851451
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_id.h
@@ -0,0 +1,159 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef PEER_ID_H__
+#define PEER_ID_H__
+
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup peer_id Peer IDs
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module keeps track of which peer IDs are in
+ *        use and which are free.
+ */
+
+
+/**@brief Function for initializing the module.
+ */
+void peer_id_init(void);
+
+
+/**@brief Function for claiming an unused peer ID.
+ *
+ * @param peer_id  The peer ID to allocate. If this is @ref PM_PEER_ID_INVALID, the first available
+ *                 will be allocated.
+ *
+ * @return  The allocated peer ID.
+ * @retval  PM_PEER_ID_INVALID  If no peer ID could be allocated or module is not initialized.
+ */
+pm_peer_id_t peer_id_allocate(pm_peer_id_t peer_id);
+
+
+/**@brief Function for marking a peer ID for deletion.
+ *
+ * @param peer_id  The peer ID to delete.
+ *
+ * @retval  true   Deletion was successful.
+ * @retval  false  Peer ID already marked for deletion, peer_id was PM_PEER_ID_INVALID, or module is
+ *                 not initialized.
+ */
+bool peer_id_delete(pm_peer_id_t peer_id);
+
+
+/**@brief Function for freeing a peer ID and clearing all data associated with it in persistent
+ *        storage.
+ *
+ * @param[in]  peer_id  Peer ID to free.
+ */
+void peer_id_free(pm_peer_id_t peer_id);
+
+
+/**@brief Function for finding out whether a peer ID is marked for deletion.
+ *
+ * @param[in]  peer_id  The peer ID to inquire about.
+ *
+ * @retval  true   peer_id is in marked for deletion.
+ * @retval  false  peer_id is not marked for deletion, or the module is not initialized.
+ */
+bool peer_id_is_deleted(pm_peer_id_t peer_id);
+
+
+/**@brief Function for finding out whether a peer ID is in use.
+ *
+ * @param[in]  peer_id  The peer ID to inquire about.
+ *
+ * @retval  true   peer_id is in use.
+ * @retval  false  peer_id is free, or the module is not initialized.
+ */
+bool peer_id_is_allocated(pm_peer_id_t peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs. Can be
+ *        used to loop through all used peer IDs.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first used peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID      if prev_peer_id was the last ordinary peer ID or the module is
+ *                                  not initialized.
+ */
+pm_peer_id_t peer_id_get_next_used(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all peer IDs marked for deletion.
+ *        Can be used to loop through all peer IDs marked for deletion.
+ *
+ * @note @ref PM_PEER_ID_INVALID is considered to be before the first and after the last ordinary
+ *       peer ID.
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID.
+ * @return  The first used peer ID  if prev_peer_id was @ref PM_PEER_ID_INVALID.
+ * @retval  PM_PEER_ID_INVALID      if prev_peer_id was the last ordinary peer ID or the module is
+ *                                  not initialized.
+ */
+pm_peer_id_t peer_id_get_next_deleted(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for querying the number of valid peer IDs available. I.E the number of peers
+ *        in persistent storage.
+ *
+ * @return  The number of valid peer IDs, or 0 if module is not initialized.
+ */
+uint32_t peer_id_n_ids(void);
+
+/** @}
+ * @endcond
+ */
+
+#endif /* PEER_ID_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.c
new file mode 100644
index 0000000000..7d11076083
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.c
@@ -0,0 +1,1039 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "peer_manager.h"
+#include <string.h>
+#include "app_util.h"
+#include "security_manager.h"
+#include "gatt_cache_manager.h"
+#include "peer_database.h"
+#include "id_manager.h"
+#include "ble_conn_state.h"
+#include "sdk_common.h"
+#include "peer_manager_internal.h"
+
+#define MODULE_INITIALIZED m_pm.initialized
+#include "sdk_macros.h"
+
+
+#define MAX_REGISTRANTS 3  /**< The number of event handlers that can be registered with the module. */
+
+
+/**@brief Internal state of the module.
+ */
+typedef struct
+{
+    uint8_t                       initialized           : 1;     /**< Whether or not @ref pm_init has been called successfully. */
+    uint8_t                       peer_rank_initialized : 1;     /**< Whether or not @ref rank_init has been called successfully. */
+    uint8_t                       deleting_all          : 1;     /**< True from when @ref pm_peers_delete is called until all peers have been deleted. */
+    pm_store_token_t              peer_rank_token;               /**< The store token of an ongoing peer rank update via a call to @ref pm_peer_rank_highest. If @ref PM_STORE_TOKEN_INVALID, there is no ongoing update. */
+    uint32_t                      current_highest_peer_rank;     /**< The current highest peer rank. Used by @ref pm_peer_rank_highest. */
+    pm_peer_id_t                  highest_ranked_peer;           /**< The peer with the highest peer rank. Used by @ref pm_peer_rank_highest. */
+    pm_evt_handler_t              evt_handlers[MAX_REGISTRANTS]; /**< The subscribers to Peer Manager events, as registered through @ref pm_register. */
+    uint8_t                       n_registrants;                 /**< The number of event handlers registered through @ref pm_register. */
+    ble_conn_state_user_flag_id_t pairing_flag_id;               /**< The flag ID for which connections are paired. */
+    ble_conn_state_user_flag_id_t bonding_flag_id;               /**< The flag ID for which connections are bonded. */
+} pm_t;
+
+
+/**@brief Instantiation of Peer Manager internal state.
+ */
+static pm_t m_pm =
+{
+    .initialized           = 0,
+    .peer_rank_initialized = 0,
+};
+
+/**@brief Function for sending a Peer Manager event to all subscribers.
+ *
+ * @param[in]  p_pm_evt  The event to send.
+ */
+static void evt_send(pm_evt_t * p_pm_evt)
+{
+    for (int i = 0; i < m_pm.n_registrants; i++)
+    {
+        m_pm.evt_handlers[i](p_pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the Peer Database module.
+ *
+ * @param[in]  p_pdb_evt  The incoming Peer Database event.
+ */
+static void pdb_evt_handler(pdb_evt_t const * p_pdb_evt)
+{
+    bool send_evt = true;
+    pm_evt_t pm_evt;
+
+    memset(&pm_evt, 0, sizeof(pm_evt_t));
+    pm_evt.peer_id = p_pdb_evt->peer_id;
+    pm_evt.conn_handle = im_conn_handle_get(pm_evt.peer_id);
+
+    switch (p_pdb_evt->evt_id)
+    {
+        case PDB_EVT_WRITE_BUF_STORED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.data_id       = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_succeeded.action        = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.token         = PM_STORE_TOKEN_INVALID;
+            pm_evt.params.peer_data_update_succeeded.flash_changed = true;
+            break;
+
+        case PDB_EVT_RAW_STORED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_succeeded.action  = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.token
+                                            = p_pdb_evt->params.raw_stored_evt.store_token;
+            pm_evt.params.peer_data_update_succeeded.flash_changed = true;
+
+            if(    (m_pm.peer_rank_token != PM_STORE_TOKEN_INVALID)
+                && (m_pm.peer_rank_token == p_pdb_evt->params.raw_stored_evt.store_token))
+            {
+                m_pm.peer_rank_token     = PM_STORE_TOKEN_INVALID;
+                m_pm.highest_ranked_peer = pm_evt.peer_id;
+
+                pm_evt.params.peer_data_update_succeeded.token = PM_STORE_TOKEN_INVALID;
+            }
+            break;
+
+        case PDB_EVT_RAW_STORE_FAILED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_FAILED;
+            pm_evt.params.peer_data_update_failed.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_failed.action  = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_failed.token
+                                            = p_pdb_evt->params.error_raw_store_evt.store_token;
+            pm_evt.params.peer_data_update_failed.error
+                                            = p_pdb_evt->params.error_raw_store_evt.err_code;
+
+            if(    (m_pm.peer_rank_token != PM_STORE_TOKEN_INVALID)
+                && (m_pm.peer_rank_token == p_pdb_evt->params.raw_stored_evt.store_token))
+            {
+                m_pm.peer_rank_token            = PM_STORE_TOKEN_INVALID;
+                m_pm.current_highest_peer_rank -= 1;
+
+                pm_evt.params.peer_data_update_succeeded.token = PM_STORE_TOKEN_INVALID;
+            }
+            break;
+
+        case PDB_EVT_CLEARED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_succeeded.action  = PM_PEER_DATA_OP_DELETE;
+            pm_evt.params.peer_data_update_succeeded.token   = PM_STORE_TOKEN_INVALID;
+            break;
+
+        case PDB_EVT_CLEAR_FAILED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_FAILED;
+            pm_evt.params.peer_data_update_failed.data_id = p_pdb_evt->data_id;
+            pm_evt.params.peer_data_update_failed.action  = PM_PEER_DATA_OP_DELETE;
+            pm_evt.params.peer_data_update_failed.error
+                                                    = p_pdb_evt->params.clear_failed_evt.err_code;
+            break;
+
+        case PDB_EVT_PEER_FREED:
+            pm_evt.evt_id = PM_EVT_PEER_DELETE_SUCCEEDED;
+            if (m_pm.deleting_all && (pdb_next_peer_id_get(PM_PEER_ID_INVALID) == PM_PEER_ID_INVALID))
+            {
+                // pm_peers_delete() has been called and this is the last peer to be deleted.
+
+                m_pm.deleting_all = false;
+
+                pm_evt_t pm_delete_all_evt;
+                memset(&pm_delete_all_evt, 0, sizeof(pm_evt_t));
+                pm_delete_all_evt.evt_id      = PM_EVT_PEERS_DELETE_SUCCEEDED;
+                pm_delete_all_evt.peer_id     = PM_PEER_ID_INVALID;
+                pm_delete_all_evt.conn_handle = BLE_CONN_HANDLE_INVALID;
+
+                evt_send(&pm_delete_all_evt);
+            }
+            break;
+
+        case PDB_EVT_PEER_FREE_FAILED:
+            pm_evt.evt_id = PM_EVT_PEER_DELETE_FAILED;
+            pm_evt.params.peer_delete_failed.error
+                                                = p_pdb_evt->params.peer_free_failed_evt.err_code;
+            if (m_pm.deleting_all)
+            {
+                // pm_peers_delete() has been called and has thus failed.
+
+                m_pm.deleting_all = false;
+
+                pm_evt_t pm_delete_all_evt;
+                memset(&pm_delete_all_evt, 0, sizeof(pm_evt_t));
+                pm_delete_all_evt.evt_id      = PM_EVT_PEERS_DELETE_FAILED;
+                pm_delete_all_evt.peer_id     = PM_PEER_ID_INVALID;
+                pm_delete_all_evt.conn_handle = BLE_CONN_HANDLE_INVALID;
+                pm_delete_all_evt.params.peers_delete_failed_evt.error
+                                              = p_pdb_evt->params.peer_free_failed_evt.err_code;
+
+                evt_send(&pm_delete_all_evt);
+            }
+            break;
+
+        case PDB_EVT_COMPRESSED:
+            send_evt = false;
+            // Do nothing
+            break;
+
+        case PDB_EVT_ERROR_NO_MEM:
+            pm_evt.evt_id = PM_EVT_STORAGE_FULL;
+            break;
+
+        case PDB_EVT_ERROR_UNEXPECTED:
+            pm_evt.evt_id = PM_EVT_ERROR_UNEXPECTED;
+            break;
+
+        default:
+            send_evt = false;
+            break;
+    }
+
+    if (send_evt)
+    {
+        evt_send(&pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the Security Manager module.
+ *
+ * @param[in]  p_sm_evt  The incoming Security Manager event.
+ */
+static void sm_evt_handler(sm_evt_t const * p_sm_evt)
+{
+    bool find_peer_id = true;
+    bool send_evt     = true;
+    pm_evt_t pm_evt;
+    memset(&pm_evt, 0, sizeof(pm_evt_t));
+    pm_evt.conn_handle = p_sm_evt->conn_handle;
+
+    switch (p_sm_evt->evt_id)
+    {
+        case SM_EVT_SLAVE_SECURITY_REQ:
+            find_peer_id = false;
+            send_evt     = false;
+            break;
+
+        case SM_EVT_SEC_PROCEDURE_START:
+        {
+            pm_evt.evt_id = PM_EVT_CONN_SEC_START;
+            bool pairing = p_sm_evt->params.sec_procedure_start.procedure
+                                != PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+            bool bonding = p_sm_evt->params.sec_procedure_start.procedure
+                                == PM_LINK_SECURED_PROCEDURE_BONDING;
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle, m_pm.pairing_flag_id, pairing);
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle, m_pm.bonding_flag_id, bonding);
+            break;
+        }
+
+        case SM_EVT_PAIRING_SUCCESS:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_SUCCEEDED;
+            pm_evt.params.conn_sec_succeeded.procedure =
+                        p_sm_evt->params.pairing_success.bonded
+                        ? PM_LINK_SECURED_PROCEDURE_BONDING
+                        : PM_LINK_SECURED_PROCEDURE_PAIRING;
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle, m_pm.pairing_flag_id, true);
+            ble_conn_state_user_flag_set(p_sm_evt->conn_handle,
+                                         m_pm.bonding_flag_id,
+                                         p_sm_evt->params.pairing_success.bonded
+            );
+            break;
+
+        case SM_EVT_PAIRING_FAIL:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_FAILED;
+            pm_evt.params.conn_sec_failed.procedure =
+                        ble_conn_state_user_flag_get(p_sm_evt->conn_handle, m_pm.bonding_flag_id)
+                        ? PM_LINK_SECURED_PROCEDURE_BONDING
+                        : PM_LINK_SECURED_PROCEDURE_PAIRING;
+            pm_evt.params.conn_sec_failed.error_src
+                = p_sm_evt->params.pairing_failed.error_src;
+            pm_evt.params.conn_sec_failed.error
+                = p_sm_evt->params.pairing_failed.error;
+            break;
+
+        case SM_EVT_LINK_ENCRYPTION_UPDATE:
+            if (!ble_conn_state_user_flag_get(p_sm_evt->conn_handle, m_pm.pairing_flag_id))
+            {
+                pm_evt.evt_id = PM_EVT_CONN_SEC_SUCCEEDED;
+                pm_evt.params.conn_sec_succeeded.procedure = PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+            }
+            else
+            {
+                find_peer_id = false;
+                send_evt     = false;
+            }
+            break;
+
+        case SM_EVT_LINK_ENCRYPTION_FAILED:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_FAILED;
+            pm_evt.params.conn_sec_failed.procedure
+                            = PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+            pm_evt.params.conn_sec_failed.error_src
+                            = p_sm_evt->params.link_encryption_failed.error_src;
+            pm_evt.params.conn_sec_failed.error
+                            = p_sm_evt->params.link_encryption_failed.error;
+            break;
+
+        case SM_EVT_BONDING_INFO_STORED:
+            pm_evt.evt_id  = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.peer_id = p_sm_evt->params.bonding_info_stored.peer_id;
+            pm_evt.params.peer_data_update_succeeded.data_id = PM_PEER_DATA_ID_BONDING;
+            pm_evt.params.peer_data_update_succeeded.action  = PM_PEER_DATA_OP_UPDATE;
+            find_peer_id = false;
+            break;
+
+        case SM_EVT_ERROR_BONDING_INFO:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_FAILED;
+            pm_evt.peer_id = p_sm_evt->params.error_bonding_info.peer_id;
+            pm_evt.params.peer_data_update_failed.data_id = PM_PEER_DATA_ID_BONDING;
+            pm_evt.params.peer_data_update_failed.action  = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_failed.error
+                = p_sm_evt->params.error_bonding_info.error;
+            find_peer_id = false;
+            break;
+
+        case SM_EVT_ERROR_UNEXPECTED:
+            pm_evt.evt_id = PM_EVT_ERROR_UNEXPECTED;
+            pm_evt.params.error_unexpected.error = p_sm_evt->params.error_unexpected.error;
+            break;
+
+        case SM_EVT_ERROR_NO_MEM:
+            pm_evt.evt_id = PM_EVT_STORAGE_FULL;
+            break;
+
+        case SM_EVT_ERROR_SMP_TIMEOUT:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_FAILED;
+            pm_evt.params.conn_sec_failed.procedure
+                        = ble_conn_state_user_flag_get(p_sm_evt->conn_handle, m_pm.bonding_flag_id)
+                        ? PM_LINK_SECURED_PROCEDURE_BONDING
+                        : PM_LINK_SECURED_PROCEDURE_PAIRING;
+            pm_evt.params.conn_sec_failed.error_src  = BLE_GAP_SEC_STATUS_SOURCE_LOCAL;
+            pm_evt.params.conn_sec_failed.error      = PM_CONN_SEC_ERROR_SMP_TIMEOUT;
+            break;
+
+        case SM_EVT_CONN_SEC_CONFIG_REQ:
+            pm_evt.evt_id = PM_EVT_CONN_SEC_CONFIG_REQ;
+            break;
+
+        default:
+            send_evt = false;
+            break;
+    }
+
+    if (find_peer_id)
+    {
+        pm_evt.peer_id = im_peer_id_get_by_conn_handle(p_sm_evt->conn_handle);
+    }
+
+    if (send_evt)
+    {
+        evt_send(&pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the GATT Cache Manager module.
+ *
+ * @param[in]  p_gcm_evt  The incoming GATT Cache Manager event.
+ */
+static void gcm_evt_handler(gcm_evt_t const * p_gcm_evt)
+{
+
+    bool send_evt = true;
+    pm_evt_t pm_evt;
+
+    memset(&pm_evt, 0, sizeof(pm_evt_t));
+    pm_evt.peer_id = p_gcm_evt->peer_id;
+    pm_evt.conn_handle = im_conn_handle_get(pm_evt.peer_id);
+
+    switch (p_gcm_evt->evt_id)
+    {
+        case GCM_EVT_LOCAL_DB_CACHE_STORED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.action = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.data_id =  PM_PEER_DATA_ID_GATT_LOCAL;
+            break;
+
+        case GCM_EVT_LOCAL_DB_CACHE_UPDATED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.action = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.data_id =  PM_PEER_DATA_ID_GATT_LOCAL;
+            break;
+
+        case GCM_EVT_LOCAL_DB_CACHE_APPLIED:
+            pm_evt.evt_id = PM_EVT_LOCAL_DB_CACHE_APPLIED;
+            break;
+
+        case GCM_EVT_ERROR_LOCAL_DB_CACHE_APPLY:
+            pm_evt.evt_id = PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED;
+            break;
+
+        case GCM_EVT_REMOTE_DB_CACHE_UPDATED:
+            pm_evt.evt_id = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.params.peer_data_update_succeeded.action = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.data_id =  PM_PEER_DATA_ID_GATT_REMOTE;
+            break;
+
+        case GCM_EVT_SERVICE_CHANGED_IND_SENT:
+            pm_evt.evt_id = PM_EVT_SERVICE_CHANGED_IND_SENT;
+            break;
+
+        case GCM_EVT_SERVICE_CHANGED_IND_CONFIRMED:
+            pm_evt.evt_id = PM_EVT_SERVICE_CHANGED_IND_CONFIRMED;
+            break;
+
+        case GCM_EVT_ERROR_DATA_SIZE:
+            send_evt = false;
+            break;
+
+        case GCM_EVT_ERROR_STORAGE_FULL:
+            pm_evt.evt_id = PM_EVT_STORAGE_FULL;
+            break;
+
+        case GCM_EVT_ERROR_UNEXPECTED:
+            pm_evt.evt_id = PM_EVT_ERROR_UNEXPECTED;
+            pm_evt.params.error_unexpected.error = p_gcm_evt->params.error_unexpected.error;
+            pm_evt.conn_handle = p_gcm_evt->params.error_unexpected.conn_handle;
+            break;
+    }
+
+    if (send_evt)
+    {
+        evt_send(&pm_evt);
+    }
+}
+
+
+/**@brief Event handler for events from the ID Manager module.
+ *
+ * @param[in]  p_im_evt  The incoming ID Manager event.
+ */
+static void im_evt_handler(im_evt_t const * p_im_evt)
+{
+    pm_evt_t pm_evt;
+    ret_code_t err_code;
+
+    switch (p_im_evt->evt_id)
+    {
+        case IM_EVT_DUPLICATE_ID:
+            // Attempt to delete the duplicate data to free space and avoid finding old data when
+            // scanning in the future
+            err_code = pm_peer_delete(p_im_evt->params.duplicate_id.peer_id_2);
+            UNUSED_VARIABLE(err_code);
+            break;
+
+        case IM_EVT_BONDED_PEER_CONNECTED:
+            ble_conn_state_user_flag_set(p_im_evt->conn_handle, m_pm.bonding_flag_id, true);
+            memset(&pm_evt, 0, sizeof(pm_evt_t));
+            pm_evt.conn_handle = p_im_evt->conn_handle;
+            pm_evt.peer_id = im_peer_id_get_by_conn_handle(p_im_evt->conn_handle);
+            pm_evt.evt_id = PM_EVT_BONDED_PEER_CONNECTED;
+            evt_send(&pm_evt);
+            break;
+    }
+}
+
+
+void pm_on_ble_evt(ble_evt_t * p_ble_evt)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+
+    im_ble_evt_handler(p_ble_evt);
+    sm_ble_evt_handler(p_ble_evt);
+    gcm_ble_evt_handler(p_ble_evt);
+}
+
+
+/**@brief Function for resetting the internal state of this module.
+ */
+static void internal_state_reset()
+{
+    memset(&m_pm, 0, sizeof(m_pm));
+    m_pm.highest_ranked_peer = PM_PEER_ID_INVALID;
+    m_pm.peer_rank_token     = PM_STORE_TOKEN_INVALID;
+    m_pm.pairing_flag_id     = BLE_CONN_STATE_USER_FLAG_INVALID;
+    m_pm.bonding_flag_id     = BLE_CONN_STATE_USER_FLAG_INVALID;
+}
+
+
+ret_code_t pm_init(void)
+{
+    ret_code_t err_code;
+
+    err_code = pdb_register(pdb_evt_handler);
+    if (err_code != NRF_SUCCESS)
+    {
+        if (err_code != NRF_ERROR_INVALID_STATE)
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+        return err_code;
+    }
+
+    err_code = sm_register(sm_evt_handler);
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = gcm_init(gcm_evt_handler);
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    err_code = im_register(im_evt_handler);
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    internal_state_reset();
+
+    m_pm.pairing_flag_id = ble_conn_state_user_flag_acquire();
+    if (m_pm.pairing_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_pm.bonding_flag_id = ble_conn_state_user_flag_acquire();
+    if (m_pm.bonding_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        return NRF_ERROR_INTERNAL;
+    }
+
+    m_pm.peer_rank_initialized = false;
+    m_pm.initialized           = true;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_register(pm_evt_handler_t event_handler)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    if (m_pm.n_registrants >= MAX_REGISTRANTS)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    m_pm.evt_handlers[m_pm.n_registrants] = event_handler;
+    m_pm.n_registrants += 1;
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_sec_params_set(ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+
+    err_code = sm_sec_params_set(p_sec_params);
+
+    if (err_code == NRF_ERROR_INVALID_STATE)
+    {
+        err_code = NRF_ERROR_INTERNAL;
+    }
+
+    return err_code;
+}
+
+
+ret_code_t pm_conn_secure(uint16_t conn_handle, bool force_repairing)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+
+    err_code = sm_link_secure(conn_handle, force_repairing);
+
+    return err_code;
+}
+
+
+void pm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config)
+{
+    sm_conn_sec_config_reply(conn_handle, p_conn_sec_config);
+}
+
+
+ret_code_t pm_sec_params_reply(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return NRF_SUCCESS;
+}
+
+
+void pm_local_database_has_changed(void)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+    gcm_local_database_has_changed();
+}
+
+
+ret_code_t pm_whitelist_create(pm_peer_id_t * p_peer_ids,
+                               uint8_t n_peer_ids,
+                               ble_gap_whitelist_t * p_whitelist)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return im_whitelist_create(p_peer_ids, n_peer_ids, p_whitelist);
+}
+
+
+ret_code_t pm_whitelist_custom(ble_gap_whitelist_t * p_whitelist)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return im_whitelist_custom(p_whitelist);
+}
+
+
+ret_code_t pm_conn_sec_status_get(uint16_t conn_handle, pm_conn_sec_status_t * p_conn_sec_status)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_conn_sec_status);
+
+    ble_conn_state_status_t status = ble_conn_state_status(conn_handle);
+
+    if (status == BLE_CONN_STATUS_INVALID)
+    {
+        return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+
+    p_conn_sec_status->connected      = (status == BLE_CONN_STATUS_CONNECTED);
+    p_conn_sec_status->bonded         = ble_conn_state_user_flag_get(conn_handle, m_pm.bonding_flag_id);
+    p_conn_sec_status->encrypted      = ble_conn_state_encrypted(conn_handle);
+    p_conn_sec_status->mitm_protected = ble_conn_state_mitm_protected(conn_handle);
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return sm_lesc_public_key_set(p_public_key);
+}
+
+
+ret_code_t pm_conn_handle_get(pm_peer_id_t peer_id, uint16_t * p_conn_handle)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_conn_handle);
+    *p_conn_handle = im_conn_handle_get(peer_id);
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_peer_id_get(uint16_t conn_handle, pm_peer_id_t * p_peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_peer_id);
+    *p_peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pm_peer_count(void)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return 0;
+    }
+    return pdb_n_peers();
+}
+
+
+pm_peer_id_t pm_next_peer_id_get(pm_peer_id_t prev_peer_id)
+{
+    if (!MODULE_INITIALIZED)
+    {
+        return PM_PEER_ID_INVALID;
+    }
+    return pdb_next_peer_id_get(prev_peer_id);
+}
+
+
+ret_code_t pm_peer_data_load(pm_peer_id_t       peer_id,
+                             pm_peer_data_id_t  data_id,
+                             void             * p_data,
+                             uint16_t         * p_length)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_data);
+    VERIFY_PARAM_NOT_NULL(p_length);
+    if (ALIGN_NUM(4, *p_length) != *p_length)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    pm_peer_data_t peer_data;
+    memset(&peer_data, 0, sizeof(peer_data));
+    peer_data.length_words = BYTES_TO_WORDS(*p_length);
+    peer_data.data_id      = data_id;
+    peer_data.p_all_data   = p_data;
+
+    ret_code_t err_code = pdb_raw_read(peer_id, data_id, &peer_data);
+
+    *p_length = peer_data.length_words * BYTES_PER_WORD;
+
+    return err_code;
+}
+
+
+ret_code_t pm_peer_data_bonding_load(pm_peer_id_t             peer_id,
+                                     pm_peer_data_bonding_t * p_data)
+{
+    uint16_t length = sizeof(pm_peer_data_bonding_t);
+    return pm_peer_data_load(peer_id,
+                             PM_PEER_DATA_ID_BONDING,
+                             p_data,
+                             &length);
+}
+
+
+ret_code_t pm_peer_data_remote_db_load(pm_peer_id_t        peer_id,
+                                       ble_gatt_db_srv_t * p_data,
+                                       uint16_t          * p_length)
+{
+    return pm_peer_data_load(peer_id,
+                             PM_PEER_DATA_ID_GATT_REMOTE,
+                             p_data,
+                             p_length);
+}
+
+
+ret_code_t pm_peer_data_app_data_load(pm_peer_id_t       peer_id,
+                                      uint8_t          * p_data,
+                                      uint16_t         * p_length)
+{
+    return pm_peer_data_load(peer_id,
+                             PM_PEER_DATA_ID_APPLICATION,
+                             p_data,
+                             p_length);
+}
+
+
+ret_code_t pm_peer_data_store(pm_peer_id_t       peer_id,
+                              pm_peer_data_id_t  data_id,
+                              void       const * p_data,
+                              uint16_t           length,
+                              pm_store_token_t * p_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_data);
+    if (ALIGN_NUM(4, length) != length)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    pm_peer_data_const_t peer_data;
+    memset(&peer_data, 0, sizeof(peer_data));
+    peer_data.length_words = BYTES_TO_WORDS(length);
+    peer_data.data_id      = data_id;
+    peer_data.p_all_data   = p_data;
+
+    return pdb_raw_store(peer_id, &peer_data, p_token);
+}
+
+
+ret_code_t pm_peer_data_bonding_store(pm_peer_id_t                   peer_id,
+                                      pm_peer_data_bonding_t const * p_data,
+                                      pm_store_token_t             * p_token)
+{
+    return pm_peer_data_store(peer_id,
+                              PM_PEER_DATA_ID_BONDING,
+                              p_data,
+                              ALIGN_NUM(4, sizeof(pm_peer_data_bonding_t)),
+                              p_token);
+}
+
+
+ret_code_t pm_peer_data_remote_db_store(pm_peer_id_t              peer_id,
+                                        ble_gatt_db_srv_t const * p_data,
+                                        uint16_t                  length,
+                                        pm_store_token_t        * p_token)
+{
+    return pm_peer_data_store(peer_id,
+                              PM_PEER_DATA_ID_GATT_REMOTE,
+                              p_data,
+                              length,
+                              p_token);
+}
+
+
+ret_code_t pm_peer_data_app_data_store(pm_peer_id_t       peer_id,
+                                       uint8_t    const * p_data,
+                                       uint16_t           length,
+                                       pm_store_token_t * p_token)
+{
+    return pm_peer_data_store(peer_id,
+                              PM_PEER_DATA_ID_APPLICATION,
+                              p_data,
+                              length,
+                              p_token);
+}
+
+
+ret_code_t pm_peer_data_delete(pm_peer_id_t peer_id, pm_peer_data_id_t data_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    if (data_id == PM_PEER_DATA_ID_BONDING)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    return pdb_clear(peer_id, data_id);
+}
+
+
+ret_code_t pm_peer_new(pm_peer_id_t           * p_new_peer_id,
+                       pm_peer_data_bonding_t * p_bonding_data,
+                       pm_store_token_t       * p_token)
+{
+    VERIFY_MODULE_INITIALIZED();
+    VERIFY_PARAM_NOT_NULL(p_bonding_data);
+    VERIFY_PARAM_NOT_NULL(p_new_peer_id);
+    ret_code_t err_code;
+
+    *p_new_peer_id = pdb_peer_allocate();
+    if (*p_new_peer_id == PM_PEER_ID_INVALID)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    pm_peer_data_const_t peer_data;
+    memset(&peer_data, 0, sizeof(pm_peer_data_const_t));
+    peer_data.length_words        = BYTES_TO_WORDS(sizeof(pm_peer_data_bonding_t));
+    peer_data.data_id             = PM_PEER_DATA_ID_BONDING;
+    peer_data.p_bonding_data      = p_bonding_data;
+
+    err_code = pm_peer_data_bonding_store(*p_new_peer_id, p_bonding_data, p_token);
+    if (err_code != NRF_SUCCESS)
+    {
+        ret_code_t err_code_free = im_peer_free(*p_new_peer_id);
+        if (err_code_free != NRF_SUCCESS)
+        {
+            err_code = NRF_ERROR_INTERNAL;
+        }
+    }
+    return err_code;
+}
+
+
+ret_code_t pm_peer_delete(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    return im_peer_free(peer_id);
+}
+
+
+ret_code_t pm_peers_delete(void)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    m_pm.deleting_all = true;
+
+    pm_peer_id_t current_peer_id = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    while (current_peer_id != PM_PEER_ID_INVALID)
+    {
+        ret_code_t err_code = pm_peer_delete(current_peer_id);
+        if (err_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+
+        current_peer_id = pdb_next_peer_id_get(current_peer_id);
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t pm_peer_ranks_get(pm_peer_id_t * p_highest_ranked_peer,
+                             uint32_t     * p_highest_rank,
+                             pm_peer_id_t * p_lowest_ranked_peer,
+                             uint32_t     * p_lowest_rank)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    pm_peer_id_t         peer_id      = pdb_next_peer_id_get(PM_PEER_ID_INVALID);
+    uint32_t             peer_rank    = 0;
+    //lint -save -e65 -e64
+    pm_peer_data_t       peer_data    = {.length_words = BYTES_TO_WORDS(sizeof(peer_rank)),
+                                         .p_peer_rank  = &peer_rank};
+    //lint -restore
+    ret_code_t           err_code     = pdb_raw_read(peer_id, PM_PEER_DATA_ID_PEER_RANK, &peer_data);
+    uint32_t             highest_rank = 0;
+    uint32_t             lowest_rank  = 0xFFFFFFFF;
+    pm_peer_id_t         highest_ranked_peer = PM_PEER_ID_INVALID;
+    pm_peer_id_t         lowest_ranked_peer  = PM_PEER_ID_INVALID;
+
+    if (err_code == NRF_ERROR_INVALID_PARAM)
+    {
+        // No peer IDs exist.
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    while ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND))
+    {
+        if (err_code == NRF_ERROR_NOT_FOUND)
+        {
+            peer_rank = 0;
+        }
+        if (peer_rank >= highest_rank)
+        {
+            highest_rank      = peer_rank;
+            highest_ranked_peer = peer_id;
+        }
+        if (peer_rank < lowest_rank)
+        {
+            lowest_rank      = peer_rank;
+            lowest_ranked_peer = peer_id;
+        }
+        peer_id = pdb_next_peer_id_get(peer_id);
+        err_code = pdb_raw_read(peer_id, PM_PEER_DATA_ID_PEER_RANK, &peer_data);
+    }
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        err_code = NRF_SUCCESS;
+        if (p_highest_ranked_peer != NULL)
+        {
+            *p_highest_ranked_peer = highest_ranked_peer;
+        }
+        if (p_highest_rank != NULL)
+        {
+            *p_highest_rank = highest_rank;
+        }
+        if (p_lowest_ranked_peer != NULL)
+        {
+            *p_lowest_ranked_peer = lowest_ranked_peer;
+        }
+        if (p_lowest_rank != NULL)
+        {
+            *p_lowest_rank = lowest_rank;
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_INTERNAL;
+    }
+    return err_code;
+}
+
+
+/**@brief Function for initializing peer rank statistics.
+ */
+static void rank_init(void)
+{
+    ret_code_t err_code = pm_peer_ranks_get(&m_pm.highest_ranked_peer,
+                                            &m_pm.current_highest_peer_rank,
+                                            NULL,
+                                            NULL);
+    if ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND))
+    {
+        m_pm.peer_rank_initialized = true;
+    }
+}
+
+
+ret_code_t pm_peer_rank_highest(pm_peer_id_t peer_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    ret_code_t err_code;
+    //lint -save -e65 -e64
+    pm_peer_data_const_t peer_data   = {.length_words = BYTES_TO_WORDS(sizeof(m_pm.current_highest_peer_rank)),
+                                        .data_id      = PM_PEER_DATA_ID_PEER_RANK,
+                                        .p_peer_rank  = &m_pm.current_highest_peer_rank};
+    //lint -restore
+
+
+    if (!m_pm.peer_rank_initialized)
+    {
+        rank_init();
+    }
+
+    if (!m_pm.peer_rank_initialized || (m_pm.peer_rank_token != PM_STORE_TOKEN_INVALID))
+    {
+        err_code = NRF_ERROR_BUSY;
+    }
+    else
+    {
+        if ((peer_id == m_pm.highest_ranked_peer) && (m_pm.current_highest_peer_rank > 0))
+        {
+            pm_evt_t pm_evt;
+
+            // The reported peer is already regarded as highest (provided it has an index at all)
+            err_code = NRF_SUCCESS;
+
+            memset(&pm_evt, 0, sizeof(pm_evt));
+            pm_evt.evt_id      = PM_EVT_PEER_DATA_UPDATE_SUCCEEDED;
+            pm_evt.conn_handle = im_conn_handle_get(peer_id);
+            pm_evt.peer_id     = peer_id;
+            pm_evt.params.peer_data_update_succeeded.data_id       = PM_PEER_DATA_ID_PEER_RANK;
+            pm_evt.params.peer_data_update_succeeded.action        = PM_PEER_DATA_OP_UPDATE;
+            pm_evt.params.peer_data_update_succeeded.token         = PM_STORE_TOKEN_INVALID;
+            pm_evt.params.peer_data_update_succeeded.flash_changed = false;
+
+            evt_send(&pm_evt);
+        }
+        else
+        {
+            m_pm.current_highest_peer_rank += 1;
+            err_code = pdb_raw_store(peer_id, &peer_data, &m_pm.peer_rank_token);
+            if (err_code != NRF_SUCCESS)
+            {
+                m_pm.peer_rank_token    = PM_STORE_TOKEN_INVALID;
+                m_pm.current_highest_peer_rank -= 1;
+                if ((err_code != NRF_ERROR_BUSY) && (err_code != NRF_ERROR_NO_MEM))
+                {
+                    err_code = NRF_ERROR_INTERNAL;
+                }
+            }
+        }
+    }
+    return err_code;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.h
new file mode 100644
index 0000000000..5618dbbd56
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager.h
@@ -0,0 +1,726 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+/**
+ * @file peer_manager.h
+ *
+ * @defgroup peer_manager Peer Manager
+ * @ingroup ble_sdk_lib
+ * @{
+ * @brief Module for managing BLE bonding, which includes controlling encryption and pairing
+ *        procedures as well as persistently storing different pieces of data that must be stored
+ *        when bonded.
+ *
+ * @details The API consists of functions for configuring the pairing and encryption behavior of the
+ *          device and functions for manipulating the stored data.
+ */
+
+
+#ifndef PEER_MANAGER_H__
+#define PEER_MANAGER_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdk_common.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+
+
+
+/**@brief Security status of a connection.
+ */
+typedef struct
+{
+    uint8_t connected      : 1; /**< @brief The connection is active (not disconnected). */
+    uint8_t encrypted      : 1; /**< @brief Communication on this link is encrypted. */
+    uint8_t mitm_protected : 1; /**< @brief The encrypted communication is also protected against man-in-the-middle attacks. */
+    uint8_t bonded         : 1; /**< @brief The peer is bonded with us. */
+} pm_conn_sec_status_t;
+
+
+/**@brief Types of events that can come from the @ref peer_manager module.
+ */
+typedef enum
+{
+    PM_EVT_BONDED_PEER_CONNECTED,           /**< @brief A connected peer has been identified as one with which we have a bond. When performing bonding with a peer for the first time, this event will not be sent until a new connection is established with the peer. When we are central, this event is always sent when the Peer Manager receives the @ref BLE_GAP_EVT_CONNECTED event. When we are peripheral, this event might in rare cases arrive later. */
+    PM_EVT_CONN_SEC_START,                  /**< @brief A security procedure has started on a link, initiated either locally or remotely. The security procedure is using the last parameters provided via @ref pm_sec_params_set. This event is always followed by either a @ref PM_EVT_CONN_SEC_SUCCEEDED or a @ref PM_EVT_CONN_SEC_FAILED event. This is an informational event; no action is needed for the procedure to proceed. */
+    PM_EVT_CONN_SEC_SUCCEEDED,              /**< @brief A link has been encrypted, either as a result of a call to @ref pm_conn_secure or a result of an action by the peer. The event structure contains more information about the circumstances. This event might contain a peer ID with the value @ref PM_PEER_ID_INVALID, which means that the peer (central) used an address that could not be identified, but it used an encryption key (LTK) that is present in the database. */
+    PM_EVT_CONN_SEC_FAILED,                 /**< @brief A pairing or encryption procedure has failed. In some cases, this means that security is not possible on this link (temporarily or permanently). How to handle this error depends on the application. */
+    PM_EVT_CONN_SEC_CONFIG_REQ,             /**< @brief The peer (central) has requested pairing, but a bond already exists with that peer. Reply by calling @ref pm_conn_sec_config_reply before the event handler returns. If no reply is sent, a default is used. */
+    PM_EVT_STORAGE_FULL,                    /**< @brief There is no more room for peer data in flash storage. To solve this problem, delete data that is not needed anymore and run a garbage collection procedure in FDS. */
+    PM_EVT_ERROR_UNEXPECTED,                /**< @brief An unrecoverable error happened inside Peer Manager. An operation failed with the provided error. */
+    PM_EVT_PEER_DATA_UPDATE_SUCCEEDED,      /**< @brief A piece of peer data was stored, updated, or cleared in flash storage. This event is sent for all successful changes to peer data, also those initiated internally in Peer Manager. To identify an operation, compare the store token in the event with the store token received during the initiating function call. Events from internally initiated changes might have invalid store tokens. */
+    PM_EVT_PEER_DATA_UPDATE_FAILED,         /**< @brief A piece of peer data could not be stored, updated, or cleared in flash storage. This event is sent instead of @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED for the failed operation. */
+    PM_EVT_PEER_DELETE_SUCCEEDED,           /**< @brief A peer was cleared from flash storage, for example because a call to @ref pm_peer_delete succeeded. This event can also be sent as part of a call to @ref pm_peers_delete or internal cleanup. */
+    PM_EVT_PEER_DELETE_FAILED,              /**< @brief A peer could not be cleared from flash storage. This event is sent instead of @ref PM_EVT_PEER_DELETE_SUCCEEDED for the failed operation. */
+    PM_EVT_PEERS_DELETE_SUCCEEDED,          /**< @brief A call to @ref pm_peers_delete has completed successfully. Flash storage now contains no peer data. */
+    PM_EVT_PEERS_DELETE_FAILED,             /**< @brief A call to @ref pm_peers_delete has failed, which means that at least one of the peers could not be deleted. Other peers might have been deleted, or might still be queued to be deleted. No more @ref PM_EVT_PEERS_DELETE_SUCCEEDED or @ref PM_EVT_PEERS_DELETE_FAILED events are sent until the next time @ref pm_peers_delete is called. */
+    PM_EVT_LOCAL_DB_CACHE_APPLIED,          /**< @brief Local database values for a peer (taken from flash storage) have been provided to the SoftDevice. */
+    PM_EVT_LOCAL_DB_CACHE_APPLY_FAILED,     /**< @brief Local database values for a peer (taken from flash storage) were rejected by the SoftDevice, which means that either the database has changed or the user has manually set the local database to an invalid value (using @ref pm_peer_data_store). */
+    PM_EVT_SERVICE_CHANGED_IND_SENT,        /**< @brief A service changed indication has been sent to a peer, as a result of a call to @ref pm_local_database_has_changed. This event will be followed by a @ref PM_EVT_SERVICE_CHANGED_IND_CONFIRMED event if the peer acknowledges the indication. */
+    PM_EVT_SERVICE_CHANGED_IND_CONFIRMED,   /**< @brief A service changed indication that was sent has been confirmed by a peer. The peer can now be considered aware that the local database has changed. */
+} pm_evt_id_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_CONN_SEC_SUCCEEDED event.
+ */
+typedef struct
+{
+    pm_conn_sec_procedure_t procedure; /**< @brief The procedure that led to securing the link. */
+} pm_conn_secured_evt_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_CONN_SEC_FAILED event.
+ */
+typedef struct
+{
+    pm_conn_sec_procedure_t  procedure; /**< @brief The procedure that failed. */
+    pm_sec_error_code_t error;          /**< @brief An error code that describes the failure. */
+    uint8_t             error_src;      /**< @brief The party that raised the error, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+} pm_conn_secure_failed_evt_t;
+
+
+/**@brief Actions that can be performed to peer data in persistent storage.
+ */
+typedef enum
+{
+    PM_PEER_DATA_OP_UPDATE, /**< @brief Writing or overwriting the data. */
+    PM_PEER_DATA_OP_DELETE, /**< @brief Removing the data. */
+} pm_peer_data_op_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED event.
+ */
+typedef struct
+{
+    pm_peer_data_id_t data_id;           /**< @brief The type of the data that was changed. */
+    pm_peer_data_op_t action;            /**< @brief What happened to the data. */
+    uint8_t           flash_changed : 1; /**< @brief If this is false, no operation was done in flash, because the value was already what it should be. Please note that in certain scenarios, this flag will be true even if the new value is the same as the old. */
+    pm_store_token_t  token;             /**< @brief Token that identifies the operation. For @ref PM_PEER_DATA_OP_DELETE actions, this token can be disregarded. For @ref PM_PEER_DATA_OP_UPDATE actions, compare this token with the token that is received from a call to a @ref PM_PEER_DATA_FUNCTIONS function. */
+} pm_peer_data_update_succeeded_evt_t;
+
+
+/**@brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_FAILED event.
+ */
+typedef struct
+{
+    pm_peer_data_id_t data_id; /**< @brief The type of the data that was supposed to be changed. */
+    pm_peer_data_op_t action;  /**< @brief The action that failed. */
+    pm_store_token_t  token;   /**< @brief Token that identifies the operation. For @ref PM_PEER_DATA_OP_DELETE actions, this token can be disregarded. For @ref PM_PEER_DATA_OP_UPDATE actions, compare this token with the token that is received from a call to a @ref PM_PEER_DATA_FUNCTIONS function. */
+    ret_code_t        error;   /**< @brief An error code that describes the failure. */
+} pm_peer_data_update_failed_t;
+
+
+/**@brief Standard parameters for failure events.
+ */
+typedef struct
+{
+    ret_code_t error; /**< @brief The error that occurred. */
+} pm_failure_evt_t;
+
+
+/**@brief An event from the @ref peer_manager module.
+ *
+ * @details The structure contains both standard parameters and parameters that are specific to some events.
+ */
+typedef struct
+{
+    pm_evt_id_t  evt_id;      /**< @brief The type of the event. */
+    uint16_t     conn_handle; /**< @brief The connection that this event pertains to, or @ref BLE_CONN_HANDLE_INVALID. */
+    pm_peer_id_t peer_id;     /**< @brief The bonded peer that this event pertains to, or @ref PM_PEER_ID_INVALID. */
+    union
+    {
+        pm_conn_secured_evt_t               conn_sec_succeeded;         /**< @brief Parameters specific to the @ref PM_EVT_CONN_SEC_SUCCEEDED event. */
+        pm_conn_secure_failed_evt_t         conn_sec_failed;            /**< @brief Parameters specific to the @ref PM_EVT_CONN_SEC_FAILED event. */
+        pm_peer_data_update_succeeded_evt_t peer_data_update_succeeded; /**< @brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED event. */
+        pm_peer_data_update_failed_t        peer_data_update_failed;    /**< @brief Parameters specific to the @ref PM_EVT_PEER_DATA_UPDATE_FAILED event. */
+        pm_failure_evt_t                    peer_delete_failed;         /**< @brief Parameters specific to the @ref PM_EVT_PEER_DELETE_FAILED event. */
+        pm_failure_evt_t                    peers_delete_failed_evt;    /**< @brief Parameters specific to the @ref PM_EVT_PEERS_DELETE_FAILED event. */
+        pm_failure_evt_t                    error_unexpected;           /**< @brief Parameters specific to the @ref PM_EVT_PEER_DELETE_FAILED event. */
+    } params;
+} pm_evt_t;
+
+
+/**@brief Event handler for events from the @ref peer_manager module.
+ *
+ * @sa pm_register
+ *
+ * @param[in]  p_event  The event that has occurred.
+ */
+typedef void (*pm_evt_handler_t)(pm_evt_t const * p_event);
+
+
+/**@brief Function for initializing the Peer Manager.
+ *
+ * @details You must initialize the Peer Manager before you can call any other Peer Manager
+ *          functions.
+ *
+ * @retval NRF_SUCCESS              If initialization was successful.
+ * @retval NRF_ERROR_INTERNAL       If another error occurred.
+ */
+ret_code_t pm_init(void);
+
+
+/**@brief Function for registering an event handler with the Peer Manager.
+ *
+ * @param[in] event_handler  Callback for events from the @ref peer_manager module. @p event_handler
+ *                           is called for every event that the Peer Manager sends after this
+ *                           function is called.
+ *
+ * @retval NRF_SUCCESS              If initialization was successful.
+ * @retval NRF_ERROR_NULL           If @p event_handler was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_register(pm_evt_handler_t event_handler);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for pairing procedures.
+ *
+ * @details Until this function is called, all bonding procedures that are initiated by the
+ *          peer are rejected.
+ *
+ *          This function can be called multiple times with different parameters, even with NULL as
+ *          @p p_sec_params, in which case the Peer Manager starts rejecting all procedures again.
+ *
+ * @param[in]  p_sec_params  Security parameters to be used for subsequent security procedures.
+ *
+ * @retval NRF_SUCCESS              If the parameters were set successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If the combination of parameters is invalid.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If another error occurred.
+ */
+ret_code_t pm_sec_params_set(ble_gap_sec_params_t * p_sec_params);
+
+
+/**@brief Function for passing BLE events to the Peer Manager.
+ *
+ * @details For the module to work as expected, this function must be called with each BLE event
+ *          from the SoftDevice. It must be called after @ref ble_conn_state_on_ble_evt, but before
+ *          the application processes the event.
+ *
+ *          Calling this function before @ref pm_init is safe, but without effect.
+ *
+ * @param[in]  p_ble_evt  BLE stack event that is dispatched to the function.
+ */
+void pm_on_ble_evt(ble_evt_t * p_ble_evt);
+
+
+/**@brief Function for establishing encryption on a connection, and optionally establishing a bond.
+ *
+ * @details This function attempts to secure the link that is specified by @p conn_handle. It uses
+ *          the parameters that were previously provided in a call to @ref pm_sec_params_set.
+ *
+ *          If the connection is a master connection, calling this function starts a security
+ *          procedure on the link. If we have keys from a previous bonding procedure with this peer
+ *          and the keys meet the security requirements in the currently active sec_params, the
+ *          function attempts to establish encryption with the existing keys. If no key exists, the
+ *          function attempts to pair and bond according to the currently active sec_params.
+ *
+ *          If the function completes successfully, a @ref PM_EVT_CONN_SEC_START event is sent.
+ *          The procedure might be queued, in which case the @ref PM_EVT_CONN_SEC_START event is
+ *          delayed until the procedure is initiated in the SoftDevice.
+ *
+ *          If the connection is a slave connection, the function sends a security request to
+ *          the peer (master). It is up to the peer then to initiate pairing or encryption.
+ *          If the peer ignores the request, a @ref BLE_GAP_EVT_TIMEOUT event occurs
+ *          with the source @ref BLE_GAP_TIMEOUT_SRC_SECURITY_REQUEST. Otherwise, the peer initiates
+ *          security, in which case things happen as if the peer had initiated security itself.
+ *          See @ref PM_EVT_CONN_SEC_START for information about peer-initiated security.
+ *
+ * @param[in]  conn_handle      Connection handle of the link as provided by the SoftDevice.
+ * @param[in]  force_repairing  Whether to force a pairing procedure even if there is an existing
+ *                              encryption key. This argument is relevant only for
+ *                              the central role. Recommended value: false.
+ *
+ * @retval NRF_SUCCESS                    If the operation completed successfully.
+ * @retval NRF_ERROR_TIMEOUT              If there was an SMP time-out, so that no more SMP
+ *                                        operations can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  If the connection handle is invalid.
+ * @retval NRF_ERROR_NOT_FOUND            If the security parameters have not been set.
+ * @retval NRF_ERROR_NO_MEM               If there is no more space in flash.
+ * @retval NRF_ERROR_INVALID_STATE        If the Peer Manager is not initialized, or the peer is
+ *                                        disconnected or in the process of disconnecting.
+ * @retval NRF_ERROR_INTERNAL             If another error occurred.
+ */
+ret_code_t pm_conn_secure(uint16_t conn_handle, bool force_repairing);
+
+
+/**@brief Function for providing security configuration for a link.
+ *
+ * @details This function is optional, and must be called in reply to a @ref
+ *          PM_EVT_CONN_SEC_CONFIG_REQ event, before the Peer Manager event handler returns. If it
+ *          is not called in time, a default configuration is used. See @ref pm_conn_sec_config_t
+ *          for the value of the default.
+ *
+ * @param[in]  conn_handle        The connection to set the configuration for.
+ * @param[in]  p_conn_sec_config  The configuration.
+ */
+void pm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config);
+
+
+/**@brief Function for manually informing that the local database has changed.
+ *
+ * @details This function sends a service changed indication to all bonded and/or connected peers
+ *          that subscribe to this indication. If a bonded peer is not connected, the indication is
+ *          sent when it reconnects. Every time an indication is sent, a @ref
+ *          PM_EVT_SERVICE_CHANGED_IND_SENT event occurs, followed by a @ref
+ *          PM_EVT_SERVICE_CHANGED_IND_CONFIRMED when the peer sends its confirmation. Peers that
+ *          are not subscribed to the service changed indication when this function is called do not
+ *          receive an indication, and no events are sent to the user. Likewise, if the service
+ *          changed characteristic is not present in the local database, this no indications are
+ *          sent peers, and no events are sent to the user.
+ */
+void pm_local_database_has_changed(void);
+
+
+/**@brief Function for getting the security status of a connection.
+ *
+ * @param[in]  conn_handle    Connection handle of the link as provided by the SoftDevice.
+ * @param[out] p_conn_sec_status  Security status of the link.
+ *
+ * @retval NRF_SUCCESS                    If pairing was initiated successfully.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  If the connection handle is invalid.
+ * @retval NRF_ERROR_NULL                 If @p p_conn_sec_status was NULL.
+ * @retval NRF_ERROR_INVALID_STATE        If the Peer Manager is not initialized.
+ */
+ret_code_t pm_conn_sec_status_get(uint16_t conn_handle, pm_conn_sec_status_t * p_conn_sec_status);
+
+
+/**@brief Experimental function for specifying the public key to use for LESC operations.
+ *
+ * @details This function can be called multiple times. The specified public key will be used for
+ *          all subsequent LESC (LE Secure Connections) operations until the next time this function
+ *          is called.
+ *
+ * @note The key must continue to reside in application memory as it is not copied by Peer Manager.
+ *
+ * @param[in]  p_public_key  The public key to use for all subsequent LESC operations.
+ *
+ * @retval NRF_SUCCESS                    Pairing initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE        Peer Manager is not initialized.
+ */
+ret_code_t pm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key);
+
+
+/**
+ * @brief Function for constructing a whitelist for use when advertising.
+ *
+ * @details This function constructs a whitelist that contains the addresses and IRKs of the
+ *          provided peer IDs. If @p p_peer_ids is NULL, the first (lowest) 8 peer IDs are chosen.
+ *          If @ref ble_gap_whitelist_t.pp_addrs in @p p_whitelist is NULL, the whitelist contains
+ *          only IRKs, and vice versa.
+ *
+ * @note When using a whitelist, always use the whitelist that was created or set by the most recent
+ *       call to this function or to @ref pm_whitelist_custom.
+ * @note Do not call this function while advertising or scanning with another whitelist.
+ *
+ * @param[in]     p_peer_ids   The IDs of the peers to be added to the whitelist, or NULL.
+ * @param[in]     n_peer_ids   The number of peer IDs in @p p_peer_ids.
+ * @param[in,out] p_whitelist  The constructed whitelist. Note that @p p_whitelist->pp_addrs
+ *                             must be NULL or point to an array with size @ref
+ *                             BLE_GAP_WHITELIST_ADDR_MAX_COUNT and @p p_whitelist->pp_irks
+ *                             must be NULL or point to an array with size @ref
+ *                             BLE_GAP_WHITELIST_IRK_MAX_COUNT.
+ *
+ * @retval NRF_SUCCESS              If the whitelist was created successfully.
+ * @retval NRF_ERROR_NULL           If @p p_whitelist was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_whitelist_create(pm_peer_id_t        * p_peer_ids,
+                           uint8_t               n_peer_ids,
+                           ble_gap_whitelist_t * p_whitelist);
+
+
+/**
+ * @brief Function for informing the Peer Manager of what whitelist should be used.
+ *
+ * @details This function should be used if the application wants to use a whitelist that is
+ *          created in the application. When using Peer Manager, this function must be called to
+ *          inform that the custom whitelist should be used instead of the one in Peer Manager.
+ *
+ * @note When using a whitelist, always use the whitelist that was created or set by the most recent
+ *       call to this function or to @ref pm_whitelist_create.
+ * @note Do not call this function while advertising or scanning with another whitelist.
+ * @note Do not add any IRKs to the whitelist that are not present in the Peer Manager's persistent
+ *       storage.
+ *
+ * @param[in] p_whitelist  The whitelist.
+ *
+ * @retval NRF_SUCCESS              If the operation completed successfully.
+ * @retval NRF_ERROR_NULL           If @p p_whitelist was NULL.
+ * @retval NRF_ERROR_NOT_FOUND      If one or more of the whitelist's IRKs was not found in the Peer
+ *                                  Manager's persistent storage.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_whitelist_custom(ble_gap_whitelist_t * p_whitelist);
+
+
+/**
+ * @brief Function for getting the connection handle of the connection with a bonded peer.
+ *
+ * @param[in]  peer_id        The peer ID of the bonded peer.
+ * @param[out] p_conn_handle  Connection handle, or @ref BLE_ERROR_INVALID_CONN_HANDLE if the peer
+ *                            is not connected.
+ *
+ * @retval NRF_SUCCESS              If the connection handle was determined successfully.
+ * @retval NRF_ERROR_NULL           If @p p_conn_handle was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_conn_handle_get(pm_peer_id_t peer_id, uint16_t * p_conn_handle);
+
+
+/**@brief Function for getting the peer ID of a connected peer.
+ *
+ * @param[in]  conn_handle  Connection handle.
+ * @param[out] p_peer_id    Peer ID, or @ref PM_PEER_ID_INVALID if the peer is not bonded or
+ *                          @p conn_handle does not refer to a connection.
+ *
+ * @retval NRF_SUCCESS              If the peer ID was retrieved successfully.
+ * @retval NRF_ERROR_NULL           If @p p_peer_id was NULL.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_id_get(uint16_t conn_handle, pm_peer_id_t * p_peer_id);
+
+
+/**@brief Function for getting the next peer ID in the sequence of all used peer IDs.
+ *
+ * @details This function can be used to loop through all used peer IDs. The order in which
+ *          peer IDs are returned should be considered unpredictable. @ref PM_PEER_ID_INVALID
+ *          is considered to be before the first and after the last used peer ID.
+ *
+ * @details To loop through all peer IDs exactly once, use the following constuct:
+ *          @code{c}
+ *              pm_peer_id_t current_peer_id = pm_next_peer_id_get(PM_PEER_ID_INVALID);
+ *              while (current_peer_id != PM_PEER_ID_INVALID)
+ *              {
+ *                  // Do something with current_peer_id.
+ *                  current_peer_id = pm_next_peer_id_get(current_peer_id)
+ *              }
+ *          @endcode
+ *
+ * @param[in]  prev_peer_id  The previous peer ID.
+ *
+ * @return  The next peer ID. If @p prev_peer_id was @ref PM_PEER_ID_INVALID, the
+ *          next peer ID is the first used peer ID. If @p prev_peer_id was the last
+ *          used peer ID, the function returns @ref PM_PEER_ID_INVALID.
+ */
+pm_peer_id_t pm_next_peer_id_get(pm_peer_id_t prev_peer_id);
+
+
+/**@brief Function for querying the number of valid peer IDs that are available.
+ *
+ * @details This function returns the number of peers for which there is data in persistent storage.
+ *
+ * @return  The number of valid peer IDs.
+ */
+uint32_t pm_peer_count(void);
+
+
+
+
+/**@anchor PM_PEER_DATA_FUNCTIONS
+ * @name Functions (Peer Data)
+ * Functions for manipulating peer data.
+ * @{
+ */
+
+/**
+ * @{
+ */
+
+/**@brief Function for retrieving stored data of a peer.
+ *
+ * @note The length of the provided buffer must be a multiple of 4.
+ *
+ * @param[in]    peer_id   Peer ID to get data for.
+ * @param[in]    data_id   Which type of data to read.
+ * @param[out]   p_data    Where to put the retrieved data.
+ * @param[inout] p_len     In: The length in bytes of @p p_data.
+ *                         Out: The length in bytes of the read data, if the read was successful.
+ *
+ * @retval NRF_SUCCESS              If the data was read successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If the the data type or the peer ID was invalid or unallocated,
+ *                                  or if the length in @p p_length was not a multiple of 4.
+ * @retval NRF_ERROR_NULL           If a pointer parameter was NULL.
+ * @retval NRF_ERROR_NOT_FOUND      If no stored data was found for this peer ID/data ID combination.
+ * @retval NRF_ERROR_DATA_SIZE      If the provided buffer was not large enough.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_data_load(pm_peer_id_t      peer_id,
+                             pm_peer_data_id_t data_id,
+                             void            * p_data,
+                             uint16_t        * p_len);
+
+/**@brief Function for reading a peer's bonding data (@ref PM_PEER_DATA_ID_BONDING).
+ * @details See @ref pm_peer_data_load for parameters and return values. */
+ret_code_t pm_peer_data_bonding_load(pm_peer_id_t             peer_id,
+                                     pm_peer_data_bonding_t * p_data);
+
+/**@brief Function for reading a peer's remote DB values. (@ref PM_PEER_DATA_ID_GATT_REMOTE).
+ * @details See @ref pm_peer_data_load for parameters and return values. */
+ret_code_t pm_peer_data_remote_db_load(pm_peer_id_t        peer_id,
+                                       ble_gatt_db_srv_t * p_data,
+                                       uint16_t          * p_len);
+
+/**@brief Function for reading a peer's application data. (@ref PM_PEER_DATA_ID_APPLICATION).
+ * @details See @ref pm_peer_data_load for parameters and return values. */
+ret_code_t pm_peer_data_app_data_load(pm_peer_id_t peer_id,
+                                      uint8_t    * p_data,
+                                      uint16_t   * p_len);
+/** @}*/
+
+
+/**
+ * @{
+ */
+
+/**@brief Function for setting or updating stored data of a peer.
+ *
+ * @note Writing the data to persistent storage happens asynchronously. Therefore, the buffer
+ *       that contains the data must be kept alive until the operation has completed.
+ *
+ * @note The data written using this function may later be overwritten as a result of internal
+ *       operations in the Peer Manager. A Peer Manager event is sent each time data is updated,
+ *       regardless of whether the operation originated internally or from action by the user.
+ *
+ * @param[in]  peer_id  Peer ID to set data for.
+ * @param[in]  data_id  Which type of data to set.
+ * @param[in]  p_data   New value to set.
+ * @param[in]  len      The length in bytes of @p p_data.
+ * @param[out] p_token  A token that identifies this particular store operation. The token can be
+ *                      used to identify events that pertain to this operation. This parameter can
+ *                      be NULL.
+ *
+ * @retval NRF_SUCCESS              If the data is scheduled to be written to persistent storage.
+ * @retval NRF_ERROR_NULL           If @p p_data is NULL.
+ * @retval NRF_ERROR_NOT_FOUND      If no peer was found for the peer ID.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_data_store(pm_peer_id_t       peer_id,
+                              pm_peer_data_id_t  data_id,
+                              void       const * p_data,
+                              uint16_t           len,
+                              pm_store_token_t * p_token);
+
+/**@brief Function for setting or updating a peer's bonding data (@ref PM_PEER_DATA_ID_BONDING).
+ * @details See @ref pm_peer_data_store for parameters and return values. */
+ret_code_t pm_peer_data_bonding_store(pm_peer_id_t                   peer_id,
+                                      pm_peer_data_bonding_t const * p_data,
+                                      pm_store_token_t             * p_token);
+
+/**@brief Function for setting or updating a peer's remote DB values. (@ref PM_PEER_DATA_ID_GATT_REMOTE).
+ * @details See @ref pm_peer_data_store for parameters and return values. */
+ret_code_t pm_peer_data_remote_db_store(pm_peer_id_t              peer_id,
+                                        ble_gatt_db_srv_t const * p_data,
+                                        uint16_t                  len,
+                                        pm_store_token_t        * p_token);
+
+/**@brief Function for setting or updating a peer's application data. (@ref PM_PEER_DATA_ID_APPLICATION).
+ * @details See @ref pm_peer_data_store for parameters and return values. */
+ret_code_t pm_peer_data_app_data_store(pm_peer_id_t       peer_id,
+                                       uint8_t    const * p_data,
+                                       uint16_t           len,
+                                       pm_store_token_t * p_token);
+/** @}*/
+
+
+/**
+ * @{
+ */
+
+/**@brief Function for deleting a peer's stored pieces of data.
+ *
+ * @details This function deletes specific data that is stored for a peer. Note that bonding data
+ *          cannot be cleared separately.
+ *
+ *          To delete all data for a peer (including bonding data), use @ref pm_peer_delete.
+ *
+ * @note Clearing data in persistent storage happens asynchronously.
+ *
+ * @param[in]  peer_id  Peer ID to clear data for.
+ * @param[in]  data_id  Which data to clear.
+ *
+ * @retval NRF_SUCCESS              If the clear procedure was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If @p data_id was PM_PEER_DATA_ID_BONDING or invalid, or
+ *                                  @p peer_id was invalid.
+ * @retval NRF_ERROR_NOT_FOUND      If there was no data to clear for this peer ID/data ID combination.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If another error occurred.
+ */
+ret_code_t pm_peer_data_delete(pm_peer_id_t peer_id, pm_peer_data_id_t data_id);
+
+
+/**@brief Function for manually adding a peer to the persistent storage.
+ *
+ * @details This function allocates a new peer ID and stores bonding data for the new peer. The
+ *          bonding data is necessary to prevent ambiguity/inconsistency in peer data.
+ *
+ * @param[in]  p_bonding_data  The bonding data of the new peer (must contain a public/static
+ *                             address or a non-zero IRK).
+ * @param[out] p_new_peer_id   Peer ID for the new peer, or an existing peer if a match was found.
+ * @param[out] p_token         A token that identifies this particular store operation (storing the
+ *                             bonding data). The token can be used to identify events that pertain
+ *                             to this operation. This parameter can be NULL.
+ *
+ * @retval NRF_SUCCESS              If the store operation for bonding data was initiated successfully.
+ * @retval NRF_ERROR_NULL           If @p p_bonding_data or @p p_new_peer_id is NULL.
+ * @retval NRF_ERROR_NO_MEM         If there is no more space in persistent storage, so that the new
+ *                                  peer cannot be allocated.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INVALID_PARAM  If the bonding data is invalid.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_new(pm_peer_id_t           * p_new_peer_id,
+                       pm_peer_data_bonding_t * p_bonding_data,
+                       pm_store_token_t       * p_token);
+
+
+/**@brief Function for freeing persistent storage for a peer.
+ *
+ * @details This function deletes every piece of data that is associated with the specified peer and
+ *          frees the peer ID to be used for another peer. The deletion happens asynchronously, and
+ *          the peer ID is not freed until the data is deleted. When the operation finishes, a @ref
+ *          PM_EVT_PEER_DELETE_SUCCEEDED or @ref PM_EVT_PEER_DELETE_FAILED event is sent.
+ *
+ * @warning Use this function only when not connected to or connectable for the peer that is being
+ *          deleted. If the peer is or becomes connected or data is manually written in flash during
+ *          this procedure (until the success or failure event happens), the behavior is undefined.
+ *
+ * @param[in]  peer_id  Peer ID to be freed and have all associated data deleted.
+ *
+ * @retval NRF_SUCCESS              If the operation was initiated successfully.
+ * @retval NRF_ERROR_INVALID_PARAM  If the peer ID was not valid.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_delete(pm_peer_id_t peer_id);
+
+
+/**@brief Function for deleting all data stored for all peers.
+ *
+ * @details This function sends either a @ref PM_EVT_PEERS_DELETE_SUCCEEDED or a @ref
+ *          PM_EVT_PEERS_DELETE_FAILED event. In addition, a @ref PM_EVT_PEER_DELETE_SUCCEEDED or
+ *          @ref PM_EVT_PEER_DELETE_FAILED event is sent for each deleted peer.
+ *
+ * @note No event is sent when there is no peer data in flash.
+ *
+ * @warning Use this function only when not connected or connectable. If a peer is or becomes
+ *          connected or a @ref PM_PEER_DATA_FUNCTIONS function is used during this procedure (until
+ *          the success or failure event happens), the behavior is undefined.
+ *
+ * @retval NRF_SUCCESS              If the deletion process was initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If another error occurred.
+ */
+ret_code_t pm_peers_delete(void);
+/** @}*/
+
+
+/**
+ * @{
+ */
+
+
+/**@brief Function for finding the highest and lowest ranked peers.
+ *
+ * @details The rank is saved in persistent storage under the data ID @ref PM_PEER_DATA_ID_PEER_RANK.
+ *
+ * @details The interpretation of rank is up to the user, because the rank is only updated by
+ *          calling @ref pm_peer_rank_highest or by manipulating the value using a @ref
+ *          PM_PEER_DATA_FUNCTIONS function.
+ *
+ * @note Any argument that is NULL is ignored.
+ *
+ * @param[out] p_highest_ranked_peer  The peer ID with the highest rank of all peers, for example,
+ *                                    the most recently used peer.
+ * @param[out] p_highest_rank         The highest rank.
+ * @param[out] p_lowest_ranked_peer   The peer ID with the lowest rank of all peers, for example,
+ *                                    the least recently used peer.
+ * @param[out] p_lowest_rank          The lowest rank.
+ *
+ * @retval NRF_SUCCESS              If the operation completed successfully.
+ * @retval NRF_ERROR_NOT_FOUND      If no peers were found.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ * @retval NRF_ERROR_INTERNAL       If another error occurred.
+ */
+ret_code_t pm_peer_ranks_get(pm_peer_id_t * p_highest_ranked_peer,
+                             uint32_t     * p_highest_rank,
+                             pm_peer_id_t * p_lowest_ranked_peer,
+                             uint32_t     * p_lowest_rank);
+
+
+/**@brief Function for updating the rank of a peer to be highest among all stored peers.
+ *
+ * @details If this function returns @ref NRF_SUCCESS, either a @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED or a
+ *          @ref PM_EVT_PEER_DATA_UPDATE_FAILED event is sent with a @ref
+ *          PM_STORE_TOKEN_INVALID store token when the operation is complete. Until the operation
+ *          is complete, this function returns @ref NRF_ERROR_BUSY.
+ *
+ *          When the operation is complete, the peer is the highest ranked peer as reported by
+ *          @ref pm_peer_ranks_get.
+ *
+ * @note The @ref PM_EVT_PEER_DATA_UPDATE_SUCCEEDED event can arrive before the function returns if the peer
+ *       is already ranked highest. In this case, the @ref pm_peer_data_update_succeeded_evt_t::flash_changed flag
+ *       in the event will be false.
+ *
+ * @param[in]  peer_id  The peer to rank highest.
+ *
+ * @retval NRF_SUCCESS              If the peer's rank is, or will be updated to be highest.
+ * @retval NRF_ERROR_BUSY           If the underlying flash handler is busy with other flash
+ *                                  operations, or if a previous call to this function has not
+ *                                  completed. Try again after receiving a Peer Manager event.
+ * @retval NRF_ERROR_INTERNAL       If another error occurred.
+ * @retval NRF_ERROR_INVALID_STATE  If the Peer Manager is not initialized.
+ */
+ret_code_t pm_peer_rank_highest(pm_peer_id_t peer_id);
+
+/** @}*/
+
+/** @} */
+
+/** @} */
+
+#endif // PEER_MANAGER_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_internal.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_internal.h
new file mode 100644
index 0000000000..df365e2e94
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_internal.h
@@ -0,0 +1,174 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef PEER_MANAGER_INTERNAL_H__
+#define PEER_MANAGER_INTERNAL_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @file peer_manager_types.h
+ *
+ * @addtogroup peer_manager
+ * @brief File containing definitions used solely inside the Peer Manager's modules.
+ * @{
+ */
+
+ANON_UNIONS_ENABLE
+
+/**@brief One piece of data associated with a peer, together with its type.
+ *
+ * @note This type is deprecated.
+ */
+typedef struct
+{
+    uint16_t              length_words; /**< @brief The length of the data in words. */
+    pm_peer_data_id_t     data_id;      /**< @brief ID that specifies the type of data (defines which member of the union is used). */
+    union
+    {
+        pm_peer_data_bonding_t       * p_bonding_data;            /**< @brief The exchanged bond information in addition to metadata of the bonding. */
+        uint32_t                     * p_peer_rank;               /**< @brief A value locally assigned to this peer. Its interpretation is up to the user. The rank is not set automatically by the Peer Manager, but it is assigned by the user using either @ref pm_peer_rank_highest or a @ref PM_PEER_DATA_FUNCTIONS function. */
+        bool                         * p_service_changed_pending; /**< @brief Whether a service changed indication should be sent to the peer. */
+        pm_peer_data_local_gatt_db_t * p_local_gatt_db;           /**< @brief Persistent information pertaining to a peer GATT client. */
+        ble_gatt_db_srv_t            * p_remote_gatt_db;          /**< @brief Persistent information pertaining to a peer GATT server. */
+        uint8_t                      * p_application_data;        /**< @brief Arbitrary data to associate with the peer. This data can be freely used by the application. */
+        void                         * p_all_data;                /**< @brief Generic access pointer to the data. It is used only to handle the data without regard to type. */
+    }; /**< @brief The data. */
+} pm_peer_data_t;
+
+
+/**@brief Immutable version of @ref pm_peer_data_t.
+ *
+ * @note This type is deprecated.
+ */
+typedef struct
+{
+    uint16_t                    length_words; /**< @brief The length of the data in words. */
+    pm_peer_data_id_t           data_id;      /**< @brief ID that specifies the type of data (defines which member of the union is used). */
+    union
+    {
+        pm_peer_data_bonding_t       const * p_bonding_data;            /**< @brief Immutable @ref pm_peer_data_t::p_bonding_data. */
+        uint32_t                     const * p_peer_rank;               /**< @brief Immutable @ref pm_peer_data_t::p_peer_rank. */
+        bool                         const * p_service_changed_pending; /**< @brief Immutable @ref pm_peer_data_t::p_service_changed_pending. */
+        pm_peer_data_local_gatt_db_t const * p_local_gatt_db;           /**< @brief Immutable @ref pm_peer_data_t::p_local_gatt_db. */
+        ble_gatt_db_srv_t            const * p_remote_gatt_db;          /**< @brief Immutable @ref pm_peer_data_t::p_remote_gatt_db. */
+        uint8_t                      const * p_application_data;        /**< @brief Immutable @ref pm_peer_data_t::p_application_data. */
+        void                         const * p_all_data;                /**< @brief Immutable @ref pm_peer_data_t::p_all_data. */
+    }; /**< @brief The data. */
+} pm_peer_data_const_t;
+
+ANON_UNIONS_DISABLE
+
+
+/**@brief Version of @ref pm_peer_data_t that reflects the structure of peer data in flash.
+ *
+ * @note This type is deprecated.
+ */
+typedef pm_peer_data_const_t pm_peer_data_flash_t;
+
+
+/**@brief Macro for calculating the flash size of bonding data.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_BONDING_DATA_N_WORDS() BYTES_TO_WORDS(sizeof(pm_peer_data_bonding_t))
+
+
+/**@brief Macro for calculating the flash size of service changed pending state.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_SC_STATE_N_WORDS() BYTES_TO_WORDS(sizeof(bool))
+
+
+/**@brief Macro for calculating the flash size of local GATT database data.
+ *
+ * @param[in]  local_db_len  The length, in bytes, of the database as reported by the SoftDevice.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_LOCAL_DB_N_WORDS(local_db_len) \
+                                    BYTES_TO_WORDS((local_db_len) + PM_LOCAL_DB_LEN_OVERHEAD_BYTES)
+
+
+/**@brief Macro for calculating the length of a local GATT database attribute array.
+ *
+ * @param[in]  n_words  The number of words that the data takes in flash.
+ *
+ * @return The length of the database attribute array.
+ */
+#define PM_LOCAL_DB_LEN(n_words) (((n_words) * BYTES_PER_WORD) - PM_LOCAL_DB_LEN_OVERHEAD_BYTES)
+
+
+/**@brief Macro for calculating the flash size of remote GATT database data.
+ *
+ * @param[in]  service_count  The number of services in the service array.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_REMOTE_DB_N_WORDS(service_count) BYTES_TO_WORDS(sizeof(ble_gatt_db_srv_t) * (service_count))
+
+
+/**@brief Macro for calculating the flash size of remote GATT database data.
+ *
+ * @param[in]  n_words  The length in number of words.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_REMOTE_DB_N_SERVICES(n_words) (((n_words) * BYTES_PER_WORD) / sizeof(ble_gatt_db_srv_t))
+
+
+/**@brief Function for calculating the flash size of the usage index.
+ *
+ * @return The number of words that the data takes in flash.
+ */
+#define PM_USAGE_INDEX_N_WORDS() BYTES_TO_WORDS(sizeof(uint32_t))
+
+/** @}
+ * @endcond
+ */
+
+#endif /* PEER_MANAGER_INTERNAL_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_types.h
new file mode 100644
index 0000000000..37a43b316b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/peer_manager_types.h
@@ -0,0 +1,202 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+/**
+ * @file peer_manager_types.h
+ *
+ * @addtogroup peer_manager
+ * @{
+ */
+
+#ifndef PEER_MANAGER_TYPES_H__
+#define PEER_MANAGER_TYPES_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "nrf.h"
+#include "nrf_ble_gap.h"
+#include "nrf_ble_hci.h"
+#include "app_util.h"
+#include "app_util_platform.h"
+#include "ble_gatt_db.h"
+
+
+/**@brief Handle to uniquely identify a peer for which we have persistently stored data.
+ */
+typedef uint16_t pm_peer_id_t;
+
+/**@brief Type that is used for write prepares (used to reserve space in flash).
+ */
+typedef uint32_t pm_prepare_token_t;
+
+/**@brief Type that is used to hold a reference to a stored item in flash.
+ */
+typedef uint32_t pm_store_token_t;
+
+/**@brief Errors from security procedures in Peer Manager.
+ *
+ * @details Possible values are defined in @ref PM_SEC_ERRORS and @ref BLE_GAP_SEC_STATUS.
+ */
+typedef uint16_t pm_sec_error_code_t;
+
+
+//lint -emacro(516,PM_LOCAL_DB_LEN_OVERHEAD_BYTES)
+
+#define PM_PEER_ID_INVALID              0xFFFF                                         /**< @brief Invalid value for @ref pm_peer_id_t. */
+#define PM_STORE_TOKEN_INVALID          0                                              /**< @brief Invalid value for store token. */
+#define PM_PEER_ID_N_AVAILABLE_IDS      256                                            /**< @brief The number of available peer IDs. */
+#define PM_LOCAL_DB_LEN_OVERHEAD_BYTES  offsetof(pm_peer_data_local_gatt_db_t, data)   /**< @brief The static-length part of the local GATT data struct. */
+
+
+#define PM_CONN_SEC_ERROR_BASE 0x1000  /**< @brief The base for Peer Manager defined errors. See @ref PM_SEC_ERRORS and @ref pm_sec_error_code_t. */
+
+
+/**@defgroup PM_SEC_ERRORS Peer Manager defined security errors
+ *
+ * @details The first 256 numbers in this range correspond to the status codes in
+ *          @ref BLE_HCI_STATUS_CODES.
+ * @{ */
+#define PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING (PM_CONN_SEC_ERROR_BASE + 0x06)  /**< @brief Encryption failed because the peripheral has lost the LTK for this bond. See also @ref BLE_HCI_STATUS_CODE_PIN_OR_KEY_MISSING and Table 3.7 ("Pairing Failed Reason Codes") in the Bluetooth Core Specification 4.2, section 3.H.3.5.5 (@linkBLEcore).  */
+#define PM_CONN_SEC_ERROR_MIC_FAILURE        (PM_CONN_SEC_ERROR_BASE + 0x3D)  /**< @brief Encryption ended with disconnection because of mismatching keys or a stray packet during a procedure. See the SoftDevice GAP Message Sequence Charts on encryption (@linkBLEMSCgap), the Bluetooth Core Specification 4.2, sections 6.B.5.1.3.1 and 3.H.3.5.5 (@linkBLEcore), and @ref BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE. */
+#define PM_CONN_SEC_ERROR_DISCONNECT         (PM_CONN_SEC_ERROR_BASE + 0x100) /**< @brief Pairing or encryption did not finish before the link disconnected for an unrelated reason. */
+#define PM_CONN_SEC_ERROR_SMP_TIMEOUT        (PM_CONN_SEC_ERROR_BASE + 0x101) /**< @brief Pairing/bonding could not start because an SMP time-out has already happened on this link. This means that no more pairing or bonding can happen on this link. To be able to pair or bond, the link must be disconnected and then reconnected. See Bluetooth Core Specification 4.2 section 3.H.3.4 (@linkBLEcore). */
+ /** @} */
+
+
+
+/**@defgroup PM_PEER_ID_VERSIONS All versions of Peer IDs.
+ * @brief The data ID for each iteration of the data formats in flash.
+ * @details Each time the format (in flash) of a piece of peer data changes, the data ID will also
+ *          be updated. This list of defines is a record of each data ID that has ever existed, and
+ *          code that caters to legacy formats can find the relevant IDs here.
+ * @{ */
+#define PM_PEER_DATA_ID_FIRST_VX                   0     /**< @brief The smallest data ID. */
+#define PM_PEER_DATA_ID_BONDING_V1                 0     /**< @brief The data ID of the first version of bonding data. */
+#define PM_PEER_DATA_ID_BONDING_V2                 7     /**< @brief The data ID of the second version of bonding data. */
+#define PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING_V1 1     /**< @brief The data ID of the first version of the service changed pending flag. */
+#define PM_PEER_DATA_ID_GATT_LOCAL_V1              2     /**< @brief The data ID of the first version of local GATT data. */
+#define PM_PEER_DATA_ID_GATT_LOCAL_V2              8     /**< @brief The data ID of the second version of local GATT data. */
+#define PM_PEER_DATA_ID_GATT_REMOTE_V1             3     /**< @brief The data ID of the first version of remote GATT data. */
+#define PM_PEER_DATA_ID_APPLICATION_V1             4     /**< @brief The data ID of the first version of application data. */
+#define PM_PEER_DATA_ID_GATT_REMOTE_V2             5     /**< @brief The data ID of the second version of remote GATT data. */
+#define PM_PEER_DATA_ID_PEER_RANK_V1               6     /**< @brief The data ID of the first version of the rank. */
+#define PM_PEER_DATA_ID_LAST_VX                    9     /**< @brief The data ID after the last valid one. */
+#define PM_PEER_DATA_ID_INVALID_VX                 0xFF  /**< @brief A data ID guaranteed to be invalid. */
+/**@}*/
+
+
+/**@brief The different types of data associated with a peer.
+ */
+typedef enum
+{
+    PM_PEER_DATA_ID_FIRST                   = PM_PEER_DATA_ID_FIRST_VX,                   /**< @brief The smallest data ID. */
+    PM_PEER_DATA_ID_BONDING                 = PM_PEER_DATA_ID_BONDING_V2,                 /**< @brief The data ID for bonding data. See @ref pm_peer_data_bonding_t. */
+    PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING = PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING_V1, /**< @brief The data ID for service changed state. */
+    PM_PEER_DATA_ID_GATT_LOCAL              = PM_PEER_DATA_ID_GATT_LOCAL_V2,              /**< @brief The data ID for local GATT data (sys attributes). See @ref pm_peer_data_local_gatt_db_t. */
+    PM_PEER_DATA_ID_GATT_REMOTE             = PM_PEER_DATA_ID_GATT_REMOTE_V2,             /**< @brief The data ID for remote GATT data. */
+    PM_PEER_DATA_ID_PEER_RANK               = PM_PEER_DATA_ID_PEER_RANK_V1,               /**< @brief The data ID for peer rank. See @ref pm_peer_rank_highest. */
+    PM_PEER_DATA_ID_APPLICATION             = PM_PEER_DATA_ID_APPLICATION_V1,             /**< @brief The data ID for application data. */
+    PM_PEER_DATA_ID_LAST                    = PM_PEER_DATA_ID_LAST_VX,                    /**< @brief One more than the highest data ID. */
+    PM_PEER_DATA_ID_INVALID                 = PM_PEER_DATA_ID_INVALID_VX,                 /**< @brief A data ID guaranteed to be invalid. */
+} pm_peer_data_id_t;
+
+
+/**@brief Different procedures that can lead to an encrypted link.
+ */
+typedef enum
+{
+    PM_LINK_SECURED_PROCEDURE_ENCRYPTION, /**< @brief Using an LTK that was shared during a previous bonding procedure to encrypt the link. */
+    PM_LINK_SECURED_PROCEDURE_BONDING,    /**< @brief A pairing procedure, followed by a bonding procedure. */
+    PM_LINK_SECURED_PROCEDURE_PAIRING,    /**< @brief A pairing procedure with no bonding. */
+} pm_conn_sec_procedure_t;
+
+
+/**@brief Configuration of a security procedure.
+ */
+typedef struct
+{
+    bool allow_repairing; /** @brief Whether to allow the peer to pair if it wants to, but is already bonded. If this is false, the procedure is rejected, and no more events are sent. Default: false. */
+} pm_conn_sec_config_t;
+
+
+/**@brief Data associated with a bond to a peer.
+ */
+typedef struct
+{
+    uint8_t           own_role; /**< @brief The role of the local device during bonding. */
+    ble_gap_id_key_t  peer_id;  /**< @brief The peer's peer address and identity resolution key. */
+    ble_gap_enc_key_t peer_ltk; /**< @brief The peer's long-term encryption key. */
+    ble_gap_enc_key_t own_ltk;  /**< @brief Locally generated long-term encryption key, distributed to the peer. */
+} pm_peer_data_bonding_t;
+
+
+
+/**@brief Data on a local GATT database.
+ */
+typedef struct
+{
+    uint32_t flags;       /**< @brief Flags that describe the database attributes. */
+    uint16_t len;         /**< @brief Size of the attribute array. */
+
+#ifdef __ICCARM__ //IAR dosen't support "flexible array member" in c++ compilation
+    uint8_t  data[1];      /**< @brief Array to hold the database attributes. */
+#else
+    uint8_t  data[];      /**< @brief Array to hold the database attributes. */
+#endif
+} pm_peer_data_local_gatt_db_t;
+
+
+/**@brief Macro to check whether a data type is valid, thus one of the valid enum values.
+ *
+ * @param[in] data_id  The data type to check.
+ */
+#define PM_PEER_DATA_ID_IS_VALID(data_id)                      \
+     (   ((data_id) == PM_PEER_DATA_ID_BONDING)                \
+      || ((data_id) == PM_PEER_DATA_ID_SERVICE_CHANGED_PENDING)\
+      || ((data_id) == PM_PEER_DATA_ID_GATT_LOCAL)             \
+      || ((data_id) == PM_PEER_DATA_ID_GATT_REMOTE)            \
+      || ((data_id) == PM_PEER_DATA_ID_PEER_RANK)              \
+      || ((data_id) == PM_PEER_DATA_ID_APPLICATION))
+
+
+ /** @} */
+
+#endif /* PEER_MANAGER_TYPES_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.c
new file mode 100644
index 0000000000..20ea66b521
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.c
@@ -0,0 +1,149 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "pm_buffer.h"
+
+#include <stdbool.h>
+#include <string.h>
+#include "nrf_error.h"
+#include "pm_mutex.h"
+
+
+#define BUFFER_IS_VALID(p_buffer) ((p_buffer != NULL)             \
+                                && (p_buffer->p_memory != NULL)   \
+                                && (p_buffer->p_mutex  != NULL))
+
+
+
+ret_code_t pm_buffer_init(pm_buffer_t * p_buffer,
+                          uint8_t     * p_buffer_memory,
+                          uint32_t      buffer_memory_size,
+                          uint8_t     * p_mutex_memory,
+                          uint32_t      mutex_memory_size,
+                          uint32_t      n_blocks,
+                          uint32_t      block_size)
+{
+    if (   (p_buffer           != NULL)
+        && (p_buffer_memory    != NULL)
+        && (p_mutex_memory     != NULL)
+        && (buffer_memory_size >= (n_blocks*block_size))
+        && (mutex_memory_size  >= MUTEX_STORAGE_SIZE(n_blocks))
+        && (n_blocks           != 0)
+        && (block_size         != 0))
+    {
+        p_buffer->p_memory   = p_buffer_memory;
+        p_buffer->p_mutex    = p_mutex_memory;
+        p_buffer->n_blocks   = n_blocks;
+        p_buffer->block_size = block_size;
+        pm_mutex_init(p_buffer->p_mutex, n_blocks);
+
+        return NRF_SUCCESS;
+    }
+    else
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+}
+
+
+uint8_t pm_buffer_block_acquire(pm_buffer_t * p_buffer, uint32_t n_blocks)
+{
+    if (!BUFFER_IS_VALID(p_buffer))
+    {
+        return ( BUFFER_INVALID_ID );
+    }
+
+    uint8_t first_locked_mutex = BUFFER_INVALID_ID;
+
+    for (uint8_t i = 0; i < p_buffer->n_blocks; i++)
+    {
+        if (pm_mutex_lock(p_buffer->p_mutex, i))
+        {
+            if (first_locked_mutex == BUFFER_INVALID_ID)
+            {
+                first_locked_mutex = i;
+            }
+            if ((i - first_locked_mutex + 1) == n_blocks)
+            {
+                return first_locked_mutex;
+            }
+        }
+        else if (first_locked_mutex != BUFFER_INVALID_ID)
+        {
+            for (uint8_t j = first_locked_mutex; j < i; j++)
+            {
+                pm_buffer_release(p_buffer, j);
+            }
+            first_locked_mutex = BUFFER_INVALID_ID;
+        }
+    }
+
+    return ( BUFFER_INVALID_ID );
+}
+
+
+uint8_t * pm_buffer_ptr_get(pm_buffer_t * p_buffer, uint8_t id)
+{
+    if (!BUFFER_IS_VALID(p_buffer))
+    {
+        return ( NULL );
+    }
+
+    if ( (id != BUFFER_INVALID_ID)
+    &&   pm_mutex_lock_status_get(p_buffer->p_mutex, id) )
+    {
+        return ( &p_buffer->p_memory[id*p_buffer->block_size] );
+    }
+    else
+    {
+        return ( NULL );
+    }
+}
+
+
+void pm_buffer_release(pm_buffer_t * p_buffer, uint8_t id)
+{
+    if (    BUFFER_IS_VALID(p_buffer)
+       &&  (id != BUFFER_INVALID_ID)
+       &&   pm_mutex_lock_status_get(p_buffer->p_mutex, id))
+    {
+        pm_mutex_unlock(p_buffer->p_mutex, id);
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.h
new file mode 100644
index 0000000000..8093ad4957
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_buffer.h
@@ -0,0 +1,142 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef BUFFER_H__
+#define BUFFER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "pm_mutex.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup pm_buffer Buffer
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module provides a simple buffer.
+ */
+
+
+#define BUFFER_INVALID_ID 0xFF
+
+#define PM_BUFFER_INIT(p_buffer, n_blocks, block_size, err_code)    \
+do                                                                  \
+{                                                                   \
+    static uint8_t buffer_memory[(n_blocks) * (block_size)];        \
+    static uint8_t mutex_memory[MUTEX_STORAGE_SIZE(n_blocks)];      \
+    err_code = pm_buffer_init((p_buffer),                           \
+                               buffer_memory,                       \
+                              (n_blocks) * (block_size),            \
+                               mutex_memory,                        \
+                               MUTEX_STORAGE_SIZE(n_blocks),        \
+                              (n_blocks),                           \
+                              (block_size));                        \
+} while(0)
+
+
+typedef struct
+{
+    uint8_t * p_memory;   /**< The storage for all buffer entries. The size of the buffer must be n_blocks*block_size. */
+    uint8_t * p_mutex;    /**< A mutex group with one mutex for each buffer entry. */
+    uint32_t  n_blocks;   /**< The number of allocatable blocks in the buffer. */
+    uint32_t  block_size; /**< The size of each block in the buffer. */
+} pm_buffer_t;
+
+/**@brief Function for initializing a buffer instance.
+ *
+ * @param[out] p_buffer            The buffer instance to initialize.
+ * @param[in]  p_buffer_memory     The memory this buffer will use.
+ * @param[in]  buffer_memory_size  The size of p_buffer_memory. This must be at least
+ *                                 n_blocks*block_size.
+ * @param[in]  p_mutex_memory      The memory for the mutexes. This must be at least
+ *                                 @ref MUTEX_STORAGE_SIZE(n_blocks).
+ * @param[in]  mutex_memory_size   The size of p_mutex_memory.
+ * @param[in]  n_blocks            The number of blocks in the buffer.
+ * @param[in]  block_size          The size of each block.
+ *
+ * @retval NRF_SUCCESS              Successfully initialized buffer instance.
+ * @retval NRF_ERROR_INVALID_PARAM  A parameter was 0 or NULL or a size was too small.
+ */
+ret_code_t pm_buffer_init(pm_buffer_t * p_buffer,
+                          uint8_t     * p_buffer_memory,
+                          uint32_t      buffer_memory_size,
+                          uint8_t     * p_mutex_memory,
+                          uint32_t      mutex_memory_size,
+                          uint32_t      n_blocks,
+                          uint32_t      block_size);
+
+
+/**@brief Function for acquiring a buffer block in a buffer.
+ *
+ * @param[in]  p_buffer  The buffer instance acquire from.
+ * @param[in]  n_blocks  The number of contiguous blocks to acquire.
+ *
+ * @return The id of the acquired block, if successful.
+ * @retval BUFFER_INVALID_ID  If unsuccessful.
+ */
+uint8_t pm_buffer_block_acquire(pm_buffer_t * p_buffer, uint32_t n_blocks);
+
+
+/**@brief Function for getting a pointer to a specific buffer block.
+ *
+ * @param[in]  p_buffer  The buffer instance get from.
+ * @param[in]  id        The id of the buffer to get the pointer for.
+ *
+ * @return A pointer to the buffer for the specified id, if the id is valid.
+ * @retval NULL  If the id is invalid.
+ */
+uint8_t * pm_buffer_ptr_get(pm_buffer_t * p_buffer, uint8_t id);
+
+
+/**@brief Function for releasing a buffer block.
+ *
+ * @param[in]  p_buffer  The buffer instance containing the block to release.
+ * @param[in]  id        The id of the block to release.
+ */
+void pm_buffer_release(pm_buffer_t * p_buffer, uint8_t id);
+
+
+#endif // BUFFER_H__
+
+/**
+ * @}
+ * @endcond
+ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.c
new file mode 100644
index 0000000000..1758108d34
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.c
@@ -0,0 +1,142 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "pm_mutex.h"
+
+#include <stdbool.h>
+#include <string.h>
+#include "nrf_error.h"
+#include "app_util_platform.h"
+
+
+
+/**@brief Locks the mutex defined by the mask.
+ *
+ * @param p_mutex pointer to the mutex storage.
+ * @param mutex_mask the mask identifying the mutex position.
+ *
+ * @retval true if the mutex could be locked.
+ * @retval false if the mutex was already locked.
+ */
+static bool lock_by_mask(uint8_t * p_mutex, uint8_t mutex_mask)
+{
+    bool success = false;
+
+    if ( (*p_mutex & mutex_mask) == 0 )
+    {
+        CRITICAL_REGION_ENTER();
+        if ( (*p_mutex & mutex_mask) == 0 )
+        {
+            *p_mutex |= mutex_mask;
+
+            success = true;
+        }
+        CRITICAL_REGION_EXIT();
+    }
+
+    return ( success );
+}
+
+
+void pm_mutex_init(uint8_t * p_mutex, uint16_t mutex_size)
+{
+    if (p_mutex != NULL)
+    {
+        memset(&p_mutex[0], 0, MUTEX_STORAGE_SIZE(mutex_size));
+    }
+}
+
+
+bool pm_mutex_lock(uint8_t * p_mutex, uint16_t mutex_id)
+{
+    if (p_mutex != NULL)
+    {
+        return ( lock_by_mask(&(p_mutex[mutex_id >> 3]), (1 << (mutex_id & 0x07))) );
+    }
+    else
+    {
+        return false;
+    }
+}
+
+
+void pm_mutex_unlock(uint8_t * p_mutex, uint16_t mutex_id)
+{
+    uint8_t mutex_base = mutex_id >> 3;
+    uint8_t mutex_mask = (1 << (mutex_id & 0x07));
+
+    if   ((p_mutex != NULL)
+       && (p_mutex[mutex_base] & mutex_mask))
+    {
+        CRITICAL_REGION_ENTER();
+        p_mutex[mutex_base] &= ~mutex_mask;
+        CRITICAL_REGION_EXIT();
+    }
+}
+
+
+uint16_t pm_mutex_lock_first_available(uint8_t * p_mutex, uint16_t mutex_size)
+{
+    if (p_mutex != NULL)
+    {
+        for ( uint16_t i = 0; i < mutex_size; i++ )
+        {
+            if ( lock_by_mask(&(p_mutex[i >> 3]), 1 << (i & 0x07)) )
+            {
+                return ( i );
+            }
+        }
+    }
+
+    return ( mutex_size );
+}
+
+
+bool pm_mutex_lock_status_get(uint8_t * p_mutex, uint16_t mutex_id)
+{
+    if (p_mutex != NULL)
+    {
+        return ( (p_mutex[mutex_id >> 3] & (1 << (mutex_id & 0x07))) );
+    }
+    else
+    {
+        return true;
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.h
new file mode 100644
index 0000000000..abc2446921
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/pm_mutex.h
@@ -0,0 +1,117 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef MUTEX_H__
+#define MUTEX_H__
+
+
+#include <stdint.h>
+#include <stdbool.h>
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup pm_mutex Mutex
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. This module provides thread-safe mutexes.
+ */
+
+
+/**@brief Defines the storage size of a specified mutex group.
+ *
+ * @param number_of_mutexes the number of mutexes in the group.
+ */
+#define MUTEX_STORAGE_SIZE(number_of_mutexes) ((7 + (number_of_mutexes)) >> 3)
+
+
+/**@brief Initializes a mutex group.
+ *
+ * @param[in] p_mutex     Pointer to the mutex group. See @ref MUTEX_STORAGE_SIZE().
+ * @param[in] mutex_size  The size of the mutex group in number of mutexes.
+ */
+void pm_mutex_init(uint8_t * p_mutex, uint16_t mutex_size);
+
+
+/**@brief Locks the mutex specified by the bit id.
+ *
+ * @param[inout] p_mutex       Pointer to the mutex group.
+ * @param[in]    mutex_bit_id  The bit id of the mutex.
+ *
+ * @retval true   if it was possible to lock the mutex.
+ * @retval false  otherwise.
+ */
+bool pm_mutex_lock(uint8_t * p_mutex, uint16_t mutex_bit_id);
+
+
+/**@brief Locks the first unlocked mutex within the mutex group.
+ *
+ * @param[in, out] p_mutex     Pointer to the mutex group.
+ * @param[in]      mutex_size  The size of the mutex group.
+ *
+ * @return The first unlocked mutex id in the group.
+ * @retval group-size  if there was no unlocked mutex available.
+ */
+uint16_t pm_mutex_lock_first_available(uint8_t * p_mutex, uint16_t mutex_size);
+
+
+/**@brief Unlocks the mutex specified by the bit id.
+ *
+ * @param[in, out] p_mutex       Pointer to the mutex group.
+ * @param[in]      mutex_bit_id  The bit id of the mutex.
+ */
+void pm_mutex_unlock(uint8_t * p_mutex, uint16_t mutex_bit_id);
+
+
+/**@brief Gets the locking status of the specified mutex.
+ *
+ * @param[in, out] p_mutex      Pointer to the mutex group.
+ * @param[in]      mutex_bit_id The bit id of the mutex.
+ *
+ * @retval true   if the mutex was locked.
+ * @retval false  otherwise.
+ */
+bool pm_mutex_lock_status_get(uint8_t * p_mutex, uint16_t mutex_bit_id);
+
+
+#endif // MUTEX_H__
+
+/** @} 
+ * @endcond  
+ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.c
new file mode 100644
index 0000000000..f35d701e79
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.c
@@ -0,0 +1,910 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "security_dispatcher.h"
+
+#include <string.h>
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "ble_conn_state.h"
+#include "peer_manager_types.h"
+#include "peer_database.h"
+#include "id_manager.h"
+#include "sdk_common.h"
+
+
+#define MAX_REGISTRANTS 3                               /**< The number of user that can register with the module. */
+
+
+typedef struct
+{
+    smd_evt_handler_t             evt_handlers[MAX_REGISTRANTS];
+    uint8_t                       n_registrants;
+    ble_conn_state_user_flag_id_t flag_id_sec_proc;
+    ble_conn_state_user_flag_id_t flag_id_sec_proc_pairing;
+    ble_conn_state_user_flag_id_t flag_id_sec_proc_new_peer;
+    ble_gap_lesc_p256_pk_t        peer_pk;
+} smd_t;
+
+
+static smd_t m_smd =
+{
+    .flag_id_sec_proc          = BLE_CONN_STATE_USER_FLAG_INVALID,
+    .flag_id_sec_proc_pairing  = BLE_CONN_STATE_USER_FLAG_INVALID,
+    .flag_id_sec_proc_new_peer = BLE_CONN_STATE_USER_FLAG_INVALID,
+};
+
+
+#define MODULE_INITIALIZED (m_smd.n_registrants > 0)    /**< Expression which is true when the module is initialized. */
+#include "sdk_macros.h"
+
+
+static void evt_send(smd_evt_t * p_event)
+{
+    for (int i = 0; i < m_smd.n_registrants; i++)
+    {
+        m_smd.evt_handlers[i](p_event);
+    }
+}
+
+
+static void sec_start_send(uint16_t conn_handle, pm_conn_sec_procedure_t procedure)
+{
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_SEC_PROCEDURE_START,
+        .conn_handle = conn_handle,
+        .params = {.sec_procedure_start = {.procedure = procedure}}
+    };
+    evt_send(&evt);
+}
+
+
+/**@brief Event handler for events from the peer_database module.
+ *
+ * @param[in]  p_event   The event that has happened.
+ */
+static void pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    if ((p_event->evt_id == PDB_EVT_WRITE_BUF_STORED) && (p_event->data_id == PM_PEER_DATA_ID_BONDING))
+    {
+        smd_evt_t evt =
+        {
+            .evt_id = SMD_EVT_BONDING_INFO_STORED,
+            .conn_handle = im_conn_handle_get(p_event->peer_id),
+            .params = {.bonding_info_stored =
+            {
+                .peer_id = p_event->peer_id,
+            }}
+        };
+        evt_send(&evt);
+    }
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_SEC_PARAMS_REQUEST event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void sec_params_request_process(ble_gap_evt_t * p_gap_evt)
+{
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_PARAMS_REQ,
+        .conn_handle = p_gap_evt->conn_handle
+    };
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for administrative actions to be taken when a security process has been attempted.
+ *
+ * @param[in]  conn_handle       The connection the security process was attempted on.
+ * @param[in]  peer_id           The peer ID given to the connected peer.
+ * @param[in]  success           Whether the process was started successfully.
+ * @param[in]  pairing           Whether the process was a pairing process.
+ * @param[in]  new_peer_created  Whether a new peer was created during the process attempt.
+ */
+static void sec_proc_start(uint16_t     conn_handle,
+                           pm_peer_id_t peer_id,
+                           bool         success,
+                           bool         pairing,
+                           bool         new_peer_created)
+{
+    ble_conn_state_user_flag_set(conn_handle, m_smd.flag_id_sec_proc, success);
+
+    if (success)
+    {
+        ble_conn_state_user_flag_set(conn_handle, m_smd.flag_id_sec_proc_pairing, pairing);
+        ble_conn_state_user_flag_set(conn_handle, m_smd.flag_id_sec_proc_new_peer, new_peer_created);
+
+        if(new_peer_created)
+        {
+            im_new_peer_id(conn_handle, peer_id);
+        }
+    }
+    else
+    {
+        if(new_peer_created)
+        {
+            ret_code_t err_code = im_peer_free(peer_id); // Attempt to free allocated peer.
+            UNUSED_VARIABLE(err_code);
+        }
+    }
+}
+
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_SEC_INFO_REQUEST event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void sec_info_request_process(ble_gap_evt_t * p_gap_evt)
+{
+    ret_code_t                 err_code;
+    ble_gap_enc_info_t const * p_enc_info = NULL;
+    pm_peer_data_flash_t       peer_data;
+    pm_peer_id_t               peer_id = im_peer_id_get_by_master_id(&p_gap_evt->params.sec_info_request.master_id);
+    smd_evt_t evt;
+
+    evt.conn_handle = p_gap_evt->conn_handle;
+
+    if (peer_id == PM_PEER_ID_INVALID)
+    {
+        peer_id = im_peer_id_get_by_conn_handle(p_gap_evt->conn_handle);
+    }
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        err_code = pdb_read_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, &peer_data, NULL);
+
+        if (err_code == NRF_SUCCESS)
+        {
+            // There is stored bonding data for this peer.
+            ble_gap_enc_key_t const * p_existing_key = &peer_data.p_bonding_data->own_ltk;
+
+            if (   p_existing_key->enc_info.lesc
+                || (im_master_ids_compare(&p_existing_key->master_id,
+                                          &p_gap_evt->params.sec_info_request.master_id)))
+            {
+                p_enc_info = &p_existing_key->enc_info;
+            }
+        }
+    }
+
+    // All return values from the following can be safely ignored.
+    err_code = sd_ble_gap_sec_info_reply(p_gap_evt->conn_handle, p_enc_info, NULL, NULL);
+
+    if (err_code != NRF_SUCCESS)
+    {
+        evt.evt_id                        = SMD_EVT_ERROR_UNEXPECTED;
+        evt.params.error_unexpected.error = err_code;
+
+        evt_send(&evt);
+    }
+    else if (p_enc_info == NULL)
+    {
+        evt.evt_id                                  = SMD_EVT_LINK_ENCRYPTION_FAILED;
+        evt.params.link_encryption_failed.error     = PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING;
+        evt.params.link_encryption_failed.error_src = BLE_GAP_SEC_STATUS_SOURCE_LOCAL;
+
+        evt_send(&evt);
+
+        sec_proc_start(p_gap_evt->conn_handle, peer_id, false, false, false);
+    }
+    else
+    {
+        sec_start_send(p_gap_evt->conn_handle, PM_LINK_SECURED_PROCEDURE_ENCRYPTION);
+
+        sec_proc_start(p_gap_evt->conn_handle, peer_id, err_code == NRF_SUCCESS, false, false);
+    }
+
+
+    return;
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_SEC_REQUEST event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void sec_request_process(ble_gap_evt_t * p_gap_evt)
+{
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_SLAVE_SECURITY_REQ,
+        .conn_handle = p_gap_evt->conn_handle,
+        .params =
+        {
+            .slave_security_req =
+            {
+                .bond = p_gap_evt->params.sec_request.bond,
+                .mitm = p_gap_evt->params.sec_request.mitm,
+            }
+        }
+    };
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_AUTH_STATUS event from the SoftDevice, when
+ *        the auth_status is success.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void auth_status_success_process(ble_gap_evt_t * p_gap_evt)
+{
+    ret_code_t           err_code   = NRF_SUCCESS;
+    uint8_t              role       = ble_conn_state_role(p_gap_evt->conn_handle);
+    pm_peer_id_t         peer_id    = im_peer_id_get_by_conn_handle(p_gap_evt->conn_handle);
+    ble_gap_sec_kdist_t  kdist_own  = p_gap_evt->params.auth_status.kdist_own;
+    ble_gap_sec_kdist_t  kdist_peer = p_gap_evt->params.auth_status.kdist_peer;
+
+    ble_conn_state_user_flag_set(p_gap_evt->conn_handle, m_smd.flag_id_sec_proc, false);
+
+    if (role == BLE_GAP_ROLE_INVALID)
+    {
+        /* Unlikely, but maybe possible? */
+        return;
+    }
+
+    if (p_gap_evt->params.auth_status.bonded)
+    {
+
+        err_code = pdb_write_buf_store(peer_id, PM_PEER_DATA_ID_BONDING);
+        if (err_code != NRF_SUCCESS)
+        {
+            /* Unexpected */
+            smd_evt_t error_evt;
+
+            error_evt.evt_id                            = SMD_EVT_ERROR_BONDING_INFO;
+            error_evt.conn_handle                       = p_gap_evt->conn_handle;
+            error_evt.params.error_bonding_info.peer_id = peer_id;
+            error_evt.params.error_bonding_info.error   = err_code;
+
+            evt_send(&error_evt);
+        }
+
+    }
+    else if (ble_conn_state_user_flag_get(p_gap_evt->conn_handle, m_smd.flag_id_sec_proc_new_peer))
+    {
+        ret_code_t err_code_free = im_peer_free(peer_id);
+        UNUSED_VARIABLE(err_code_free); // Errors can be safely ignored.
+    }
+
+    smd_evt_t pairing_success_evt;
+
+    pairing_success_evt.evt_id                            = SMD_EVT_PAIRING_SUCCESS;
+    pairing_success_evt.conn_handle                       = p_gap_evt->conn_handle;
+    pairing_success_evt.params.pairing_success.bonded     = p_gap_evt->params.auth_status.bonded;
+    pairing_success_evt.params.pairing_success.mitm       = p_gap_evt->params.auth_status.sm1_levels.lv3;
+    pairing_success_evt.params.pairing_success.kdist_own  = kdist_own;
+    pairing_success_evt.params.pairing_success.kdist_peer = kdist_peer;
+
+    evt_send(&pairing_success_evt);
+    return;
+}
+
+
+/**@brief Function for cleaning up after a failed pairing procedure.
+ *
+ * @param[in]  conn_handle  The handle of the connection the pairing procedure happens on.
+ * @param[in]  peer_id      The peer id used in the pairing procedure.
+ * @param[in]  error        The error the procedure failed with.
+ * @param[in]  error_src    The party that raised the error. See @ref BLE_GAP_SEC_STATUS_SOURCES.
+ */
+static void pairing_failure(uint16_t            conn_handle,
+                            pm_peer_id_t        peer_id,
+                            pm_sec_error_code_t error,
+                            uint8_t             error_src)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_PAIRING_FAIL,
+        .conn_handle = conn_handle,
+        .params =
+        {
+            .pairing_failed =
+            {
+                .error     = error,
+                .error_src = error_src,
+            }
+        }
+    };
+
+    if(ble_conn_state_user_flag_get(conn_handle, m_smd.flag_id_sec_proc_new_peer))
+    {
+        // The peer_id was created during the procedure, and should be freed, because no data is
+        // stored under it.
+        err_code = im_peer_free(peer_id);  // Attempt to free allocated peer.
+        UNUSED_VARIABLE(err_code);
+    }
+    else
+    {
+        err_code = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_BONDING);
+        if ((err_code != NRF_SUCCESS) && (err_code == NRF_ERROR_NOT_FOUND /* No buffer was allocated */))
+        {
+            smd_evt_t error_evt;
+            error_evt.evt_id = SMD_EVT_ERROR_UNEXPECTED;
+            error_evt.conn_handle = conn_handle;
+            error_evt.params.error_unexpected.error = err_code;
+            evt_send(&error_evt);
+        }
+    }
+
+    ble_conn_state_user_flag_set(conn_handle, m_smd.flag_id_sec_proc, false);
+
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for cleaning up after a failed encryption procedure.
+ *
+ * @param[in]  conn_handle  The handle of the connection the encryption procedure happens on.
+ * @param[in]  error        The error the procedure failed with.
+ * @param[in]  error_src    The party that raised the error. See @ref BLE_GAP_SEC_STATUS_SOURCES.
+ */
+static void encryption_failure(uint16_t            conn_handle,
+                               pm_sec_error_code_t error,
+                               uint8_t             error_src)
+{
+    smd_evt_t evt =
+    {
+        .evt_id = SMD_EVT_LINK_ENCRYPTION_FAILED,
+        .conn_handle = conn_handle,
+        .params =
+        {
+            .link_encryption_failed =
+            {
+                .error     = error,
+                .error_src = error_src,
+            }
+        }
+    };
+
+    ble_conn_state_user_flag_set(conn_handle, m_smd.flag_id_sec_proc, false);
+
+    evt_send(&evt);
+    return;
+}
+
+
+/**@brief Function for possibly cleaning up after a failed pairing or encryption procedure.
+ *
+ * @param[in]  conn_handle  The handle of the connection the pairing procedure happens on.
+ * @param[in]  peer_id      The peer id used in the pairing procedure.
+ * @param[in]  error        The error the procedure failed with.
+ * @param[in]  error_src    The party that raised the error. See @ref BLE_GAP_SEC_STATUS_SOURCES.
+ */
+static void link_secure_failure(uint16_t            conn_handle,
+                                pm_sec_error_code_t error,
+                                uint8_t             error_src)
+{
+    if (ble_conn_state_user_flag_get(conn_handle, m_smd.flag_id_sec_proc))
+    {
+        pm_peer_id_t  peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+        if (peer_id != PM_PEER_ID_INVALID)
+        {
+            if (ble_conn_state_user_flag_get(conn_handle, m_smd.flag_id_sec_proc_pairing))
+            {
+                pairing_failure(conn_handle, peer_id, error, error_src);
+            }
+            else
+            {
+                encryption_failure(conn_handle, error, error_src);
+            }
+        }
+    }
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_DISCONNECT event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void disconnect_process(ble_gap_evt_t * p_gap_evt)
+{
+    pm_sec_error_code_t error = (p_gap_evt->params.disconnected.reason
+                                        == BLE_HCI_CONN_TERMINATED_DUE_TO_MIC_FAILURE)
+                                ? PM_CONN_SEC_ERROR_MIC_FAILURE : PM_CONN_SEC_ERROR_DISCONNECT;
+
+    link_secure_failure(p_gap_evt->conn_handle, error, BLE_GAP_SEC_STATUS_SOURCE_LOCAL);
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_AUTH_STATUS event from the SoftDevice, when
+ *        the auth_status is failure.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void auth_status_failure_process(ble_gap_evt_t * p_gap_evt)
+{
+    link_secure_failure(p_gap_evt->conn_handle,
+                        p_gap_evt->params.auth_status.auth_status,
+                        p_gap_evt->params.auth_status.error_src);
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_AUTH_STATUS event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void auth_status_process(ble_gap_evt_t * p_gap_evt)
+{
+    switch (p_gap_evt->params.auth_status.auth_status)
+    {
+        case BLE_GAP_SEC_STATUS_SUCCESS:
+            auth_status_success_process(p_gap_evt);
+            break;
+
+        default:
+            auth_status_failure_process(p_gap_evt);
+            break;
+    }
+}
+
+
+/**@brief Function for processing the @ref BLE_GAP_EVT_CONN_SEC_UPDATE event from the SoftDevice.
+ *
+ * @param[in]  p_gap_evt  The event from the SoftDevice.
+ */
+static void conn_sec_update_process(ble_gap_evt_t * p_gap_evt)
+{
+    if (ble_conn_state_encrypted(p_gap_evt->conn_handle))
+    {
+        if (!ble_conn_state_user_flag_get(p_gap_evt->conn_handle, m_smd.flag_id_sec_proc_pairing))
+        {
+            ble_conn_state_user_flag_set(p_gap_evt->conn_handle, m_smd.flag_id_sec_proc, false);
+        }
+
+        smd_evt_t evt;
+
+        evt.conn_handle = p_gap_evt->conn_handle;
+        evt.evt_id = SMD_EVT_LINK_ENCRYPTION_UPDATE;
+        evt.params.link_encryption_update.mitm_protected
+                                = ble_conn_state_mitm_protected(p_gap_evt->conn_handle);
+        evt_send(&evt);
+    }
+    else
+    {
+        encryption_failure(p_gap_evt->conn_handle,
+                           PM_CONN_SEC_ERROR_PIN_OR_KEY_MISSING,
+                           BLE_GAP_SEC_STATUS_SOURCE_REMOTE);
+    }
+}
+
+
+/**@brief Funtion for initializing a BLE Connection State user flag.
+ *
+ * @param[out] flag_id  The flag to initialize.
+ */
+static void flag_id_init(ble_conn_state_user_flag_id_t * p_flag_id)
+{
+    if (*p_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        *p_flag_id = ble_conn_state_user_flag_acquire();
+    }
+}
+
+
+ret_code_t smd_register(smd_evt_handler_t evt_handler)
+{
+    ret_code_t err_code = NRF_SUCCESS;
+    if (evt_handler == NULL)
+    {
+        err_code = NRF_ERROR_NULL;
+    }
+    else
+    {
+        if (!MODULE_INITIALIZED)
+        {
+            flag_id_init(&m_smd.flag_id_sec_proc);
+            flag_id_init(&m_smd.flag_id_sec_proc_pairing);
+            flag_id_init(&m_smd.flag_id_sec_proc_new_peer);
+
+            if (m_smd.flag_id_sec_proc_new_peer == BLE_CONN_STATE_USER_FLAG_INVALID)
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+            else
+            {
+                err_code = pdb_register(pdb_evt_handler);
+            }
+        }
+        if ((err_code == NRF_SUCCESS))
+        {
+            if ((m_smd.n_registrants < MAX_REGISTRANTS))
+            {
+                m_smd.evt_handlers[m_smd.n_registrants++] = evt_handler;
+            }
+            else
+            {
+                err_code = NRF_ERROR_NO_MEM;
+            }
+        }
+    }
+    return err_code;
+}
+
+
+ret_code_t smd_params_reply(uint16_t                 conn_handle,
+                            ble_gap_sec_params_t   * p_sec_params,
+                            ble_gap_lesc_p256_pk_t * p_public_key)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    uint8_t              role = ble_conn_state_role(conn_handle);
+    pm_peer_id_t         peer_id = PM_PEER_ID_INVALID;
+    ret_code_t           err_code = NRF_SUCCESS;
+    uint8_t              sec_status = BLE_GAP_SEC_STATUS_SUCCESS;
+    ble_gap_sec_keyset_t sec_keyset;
+    bool                 new_peer_created = false;
+
+    memset(&sec_keyset, 0, sizeof(ble_gap_sec_keyset_t));
+
+    if (role == BLE_GAP_ROLE_INVALID)
+    {
+        return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+
+    if (p_sec_params == NULL)
+    {
+        // NULL params means reject pairing.
+        sec_status = BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP;
+    }
+    else if (p_sec_params->bond)
+    {
+        // Bonding is to be performed, prepare to receive bonding data.
+        pm_peer_data_t       peer_data;
+
+        peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+        if (peer_id == PM_PEER_ID_INVALID)
+        {
+            // Peer is unknown to us, allocate a new peer ID for it.
+            peer_id = pdb_peer_allocate();
+            if (peer_id != PM_PEER_ID_INVALID)
+            {
+                new_peer_created = true;
+            }
+            else
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            // Peer ID is ready, acquire a memory buffer to receive bonding data into.
+            err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, 1, &peer_data);
+            if (err_code == NRF_SUCCESS)
+            {
+                memset(peer_data.p_bonding_data, 0, sizeof(pm_peer_data_bonding_t));
+
+                peer_data.p_bonding_data->own_role = role;
+
+                sec_keyset.keys_own.p_enc_key  = &peer_data.p_bonding_data->own_ltk;
+                sec_keyset.keys_own.p_pk       = p_public_key;
+                sec_keyset.keys_peer.p_enc_key = &peer_data.p_bonding_data->peer_ltk;
+                sec_keyset.keys_peer.p_id_key  = &peer_data.p_bonding_data->peer_id;
+                sec_keyset.keys_peer.p_pk      = &m_smd.peer_pk;
+
+                ret_code_t err_code_addr = im_ble_addr_get(conn_handle, &peer_data.p_bonding_data->peer_id.id_addr_info); // Retrieve the address the peer used during connection establishment. This address will be overwritten if ID is shared. Should not fail.
+                UNUSED_VARIABLE(err_code_addr);
+
+                // Buffer is OK, reserve room in flash for the data.
+                err_code = pdb_write_buf_store_prepare(peer_id, PM_PEER_DATA_ID_BONDING);
+            }
+        }
+    }
+    else
+    {
+        // Pairing only, no action needed.
+    }
+
+    if (err_code == NRF_SUCCESS)
+    {
+        // Everything OK, reply to SoftDevice. If an error happened, the user is given an
+        // opportunity to change the parameters and retry the call.
+        if (role == BLE_GAP_ROLE_CENTRAL)
+        {
+            err_code = sd_ble_gap_sec_params_reply(conn_handle, sec_status, NULL, &sec_keyset);
+        }
+        else
+        {
+            err_code = sd_ble_gap_sec_params_reply(conn_handle, sec_status, p_sec_params, &sec_keyset);
+
+            if ((p_sec_params != NULL) && (err_code == NRF_SUCCESS))
+            {
+                pm_conn_sec_procedure_t procedure = p_sec_params->bond
+                                               ? PM_LINK_SECURED_PROCEDURE_BONDING
+                                               : PM_LINK_SECURED_PROCEDURE_PAIRING;
+                sec_start_send(conn_handle, procedure);
+            }
+        }
+    }
+
+    sec_proc_start(conn_handle,
+                   peer_id,
+                   (err_code == NRF_SUCCESS) && (sec_status != BLE_GAP_SEC_STATUS_PAIRING_NOT_SUPP),
+                   true,
+                   new_peer_created);
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_central_existing_peer(uint16_t                  conn_handle,
+                                                    ble_gap_sec_params_t    * p_sec_params,
+                                                    bool                      force_repairing,
+                                                    pm_peer_id_t              peer_id,
+                                                    pm_conn_sec_procedure_t * procedure)
+{
+    pm_peer_data_flash_t      peer_data;
+    pm_peer_data_t            dummy_peer_data;
+    ret_code_t                err_code;
+    ble_gap_enc_key_t const * p_existing_key = NULL;
+    bool                      lesc = false;
+
+    err_code = pdb_read_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, &peer_data, NULL);
+
+    if (err_code == NRF_SUCCESS)
+    {
+        // Use peer's key since they are peripheral.
+        p_existing_key = &(peer_data.p_bonding_data->peer_ltk);
+
+        lesc = peer_data.p_bonding_data->own_ltk.enc_info.lesc;
+        if  (lesc) // LESC was used during bonding.
+        {
+            // For LESC, always use own key.
+            p_existing_key = &(peer_data.p_bonding_data->own_ltk);
+        }
+    }
+
+    if     (!force_repairing
+         && (err_code == NRF_SUCCESS)
+         && (p_existing_key != NULL)
+         && (lesc || im_master_id_is_valid(&(p_existing_key->master_id)))) /* There is a valid LTK stored. */
+         //&& (p_existing_key->enc_info.auth >= p_sec_params->mitm)          /* The requested MITM security is at or below the existing level. */
+         //&& (!p_sec_params->mitm || (lesc >= p_sec_params->lesc)))         /* The requested LESC security is at or below the existing level. We only care about LESC if MITM is required. */
+    {
+        err_code = sd_ble_gap_encrypt(conn_handle, &(p_existing_key->master_id), &(p_existing_key->enc_info));
+
+        *procedure = PM_LINK_SECURED_PROCEDURE_ENCRYPTION;
+    }
+    else if ((err_code == NRF_SUCCESS) || (err_code == NRF_ERROR_NOT_FOUND))
+    {
+        /* Re-pairing is needed, because there is no LTK available or the existing key is not
+           secure enough */
+        err_code = NRF_SUCCESS;
+
+        if (p_sec_params->bond)
+        {
+            err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, 1, &dummy_peer_data);
+            if (err_code == NRF_SUCCESS)
+            {
+                err_code = pdb_write_buf_store_prepare(peer_id, PM_PEER_DATA_ID_BONDING);
+            }
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+        }
+
+        if (err_code != NRF_SUCCESS)
+        {
+            ret_code_t err_code_release = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_BONDING);
+            if ((err_code_release != NRF_SUCCESS) && (err_code_release != NRF_ERROR_NOT_FOUND))
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+    }
+
+    sec_proc_start(conn_handle,
+                   peer_id,
+                   err_code == NRF_SUCCESS,
+                   *procedure != PM_LINK_SECURED_PROCEDURE_ENCRYPTION,
+                   false);
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_central_new_peer(uint16_t               conn_handle,
+                                               ble_gap_sec_params_t * p_sec_params)
+{
+    pm_peer_id_t    peer_id = pdb_peer_allocate();
+    pm_peer_data_t  dummy_peer_data;
+    ret_code_t      err_code;
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        err_code = pdb_write_buf_get(peer_id, PM_PEER_DATA_ID_BONDING, 1, &dummy_peer_data);
+        if (err_code == NRF_SUCCESS)
+        {
+            err_code = pdb_write_buf_store_prepare(peer_id, PM_PEER_DATA_ID_BONDING);
+        }
+
+        if (err_code == NRF_SUCCESS)
+        {
+            err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+        }
+
+        if (err_code != NRF_SUCCESS)
+        {
+            ret_code_t err_code_free = pdb_write_buf_release(peer_id, PM_PEER_DATA_ID_BONDING);
+            if ((err_code_free != NRF_SUCCESS) && (err_code_free != NRF_ERROR_NOT_FOUND))
+            {
+                err_code = NRF_ERROR_INTERNAL;
+            }
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_INTERNAL;
+    }
+
+    sec_proc_start(conn_handle,
+                   peer_id,
+                   err_code == NRF_SUCCESS,
+                   true,
+                   peer_id != PM_PEER_ID_INVALID);
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_central(uint16_t               conn_handle,
+                                      ble_gap_sec_params_t * p_sec_params,
+                                      bool                   force_repairing)
+{
+    ret_code_t           err_code;
+    pm_peer_id_t         peer_id;
+
+    if (p_sec_params == NULL)
+    {
+        return sd_ble_gap_authenticate(conn_handle, NULL);
+    }
+
+    pm_conn_sec_procedure_t procedure = p_sec_params->bond ? PM_LINK_SECURED_PROCEDURE_BONDING
+                                                           : PM_LINK_SECURED_PROCEDURE_PAIRING;
+
+    peer_id = im_peer_id_get_by_conn_handle(conn_handle);
+
+    if (peer_id != PM_PEER_ID_INVALID)
+    {
+        // There is already data in flash for this peer.
+        err_code = link_secure_central_existing_peer(conn_handle,
+                                                     p_sec_params,
+                                                     force_repairing,
+                                                     peer_id,
+                                                     &procedure);
+    }
+    else if (p_sec_params->bond)
+    {
+        // New peer is required.
+        err_code = link_secure_central_new_peer(conn_handle, p_sec_params);
+    }
+    else
+    {
+        // No bonding, only pairing.
+        err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+
+        sec_proc_start(conn_handle, peer_id, err_code == NRF_SUCCESS, true, false);
+    }
+
+    if (err_code == NRF_SUCCESS)
+    {
+        sec_start_send(conn_handle, procedure);
+    }
+
+    return err_code;
+}
+
+
+static ret_code_t link_secure_peripheral(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_PARAM_NOT_NULL(p_sec_params);
+
+    ret_code_t err_code = sd_ble_gap_authenticate(conn_handle, p_sec_params);
+
+    return err_code;
+}
+
+
+ret_code_t smd_link_secure(uint16_t               conn_handle,
+                           ble_gap_sec_params_t * p_sec_params,
+                           bool                   force_repairing)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    uint8_t role = ble_conn_state_role(conn_handle);
+
+    switch (role)
+    {
+        case BLE_GAP_ROLE_CENTRAL:
+            return link_secure_central(conn_handle, p_sec_params, force_repairing);
+
+        case BLE_GAP_ROLE_PERIPH:
+            return link_secure_peripheral(conn_handle, p_sec_params);
+
+        default:
+            return BLE_ERROR_INVALID_CONN_HANDLE;
+    }
+}
+
+
+void smd_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    switch (p_ble_evt->header.evt_id)
+    {
+        case BLE_GAP_EVT_DISCONNECTED:
+            disconnect_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_SEC_PARAMS_REQUEST:
+            sec_params_request_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_SEC_INFO_REQUEST:
+            sec_info_request_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_SEC_REQUEST:
+            sec_request_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_AUTH_STATUS:
+            auth_status_process(&(p_ble_evt->evt.gap_evt));
+            break;
+
+        case BLE_GAP_EVT_CONN_SEC_UPDATE:
+            conn_sec_update_process(&(p_ble_evt->evt.gap_evt));
+            break;
+    };
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.h
new file mode 100644
index 0000000000..037158a9f7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_dispatcher.h
@@ -0,0 +1,281 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef SECURITY_DISPATCHER_H__
+#define SECURITY_DISPATCHER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup security_dispatcher Security Dispatcher
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for streamlining pairing, bonding, and
+ *        encryption, including flash storage of shared data.
+ *
+ */
+
+
+/**@brief Events that can come from the Security Dispatcher module.
+ */
+typedef enum
+{
+    SMD_EVT_PARAMS_REQ,             /**< Parameters are required for a pairing procedure on the specified connection. The user must provide them using @ref smd_params_reply. */
+    SMD_EVT_SLAVE_SECURITY_REQ,     /**< The peer (slave) has requested link encryption. Call @ref smd_link_secure to honor the request. The data in the event structure must be used in the parameters. */
+    SMD_EVT_SEC_PROCEDURE_START,    /**< A security procedure has started. */
+    SMD_EVT_PAIRING_SUCCESS,        /**< A pairing procedure (and bonding if applicable) has completed with success. */
+    SMD_EVT_PAIRING_FAIL,           /**< A pairing procedure has failed which means no encryption and no bond could be established. */
+    SMD_EVT_LINK_ENCRYPTION_UPDATE, /**< The security level of the link has been updated. The link is encrypted. */
+    SMD_EVT_LINK_ENCRYPTION_FAILED, /**< An attempt to start encryption on an unencrypted link failed because the peripheral did not have the correct keys. If the peer is the peripheral, the force_repairing flag should be set when reattempting @ref smd_link_secure. */
+    SMD_EVT_BONDING_INFO_STORED,    /**< Information exchanged during bonding with a peer has been stored persistently. */
+    SMD_EVT_ERROR_BONDING_INFO,     /**< Information exchanged during bonding with a peer could not be stored persistently, because of an unexpected error. */
+    // SMD_EVT_ERROR_NO_MEM,           /**< An operation failed because there was no available storage room in persistent storage. Please free up room, and the operation will automatically continue. */
+    SMD_EVT_ERROR_UNEXPECTED,       /**< An operation failed with an unexpected error. The error is provided. This is possibly a fatal error. */
+} smd_evt_id_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_SLAVE_SECURITY_REQ event.
+ */
+typedef struct
+{
+    bool bond;
+    bool mitm;
+} smd_evt_slave_security_req_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_SEC_PROCEDURE_START event.
+ */
+typedef struct
+{
+    pm_conn_sec_procedure_t procedure; /**< The procedure that has started. */
+} smd_evt_sec_procedure_start_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_PAIRING_SUCCESS event.
+ */
+typedef struct
+{
+    bool                bonded;     /**< Whether bonding was performed. */
+    bool                mitm;       /**< Whether MITM protection was used during pairing. */
+    ble_gap_sec_kdist_t kdist_own;  /**< Which keys were distributed to the peer. Only relevant if bonding was performed. */
+    ble_gap_sec_kdist_t kdist_peer; /**< Which keys were distributed by the peer. Only relevant if bonding was performed. */
+} smd_evt_pairing_success_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_PAIRING_FAIL event.
+ */
+typedef struct
+{
+    pm_sec_error_code_t error;     /**< What went wrong. */
+    uint8_t             error_src; /**< The party that raised the error, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+} smd_evt_pairing_failed_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_LINK_ENCRYPTION_UPDATE event.
+ */
+typedef struct
+{
+    bool mitm_protected;  /**< Whether the link is now MITM protected. */
+} smd_evt_link_encryption_update_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_LINK_ENCRYPTION_FAILED event.
+ */
+typedef struct
+{
+    pm_sec_error_code_t error;     /**< What went wrong. */
+    uint8_t             error_src; /**< The party that raised the error, see @ref BLE_GAP_SEC_STATUS_SOURCES. */
+} smd_evt_link_encryption_failed_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_BONDING_INFO_STORED event.
+ */
+typedef struct
+{
+    pm_peer_id_t peer_id; /**< The peer this event pertains to. */
+} smd_evt_bonding_info_stored_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_ERROR_BONDING_INFO event.
+ */
+typedef struct
+{
+    pm_peer_id_t peer_id; /**< The peer this event pertains to, if previously bonded. @ref PM_PEER_ID_INVALID if no successful bonding has happened with the peer before. */
+    ret_code_t   error;   /**< The unexpected error that occurred. */
+} smd_evt_error_bonding_info_t;
+
+
+// typedef struct
+// {
+    // pm_peer_id_t peer_id; /**< The peer this event pertains to. */
+// } smd_evt_error_no_mem_t;
+
+
+/**@brief Events parameters specific to the @ref SMD_EVT_ERROR_UNEXPECTED event.
+ */
+typedef struct
+{
+    ret_code_t error; /**< The unexpected error that occurred. */
+} smd_evt_error_unexpected_t;
+
+
+typedef union
+{
+    smd_evt_slave_security_req_t     slave_security_req;
+    smd_evt_sec_procedure_start_t    sec_procedure_start;
+    smd_evt_pairing_success_t        pairing_success;
+    smd_evt_pairing_failed_t         pairing_failed;
+    smd_evt_link_encryption_update_t link_encryption_update;
+    smd_evt_link_encryption_failed_t link_encryption_failed;
+    smd_evt_bonding_info_stored_t    bonding_info_stored;
+    smd_evt_error_bonding_info_t     error_bonding_info;
+    //  smd_evt_error_no_mem_t          error_no_mem;
+    smd_evt_error_unexpected_t       error_unexpected;
+} smd_evt_params_t; /**< Event specific parameters. Chosen based on evt_id. */
+
+
+/**@brief Structure describing events from the Security Dispatcher module.
+ */
+typedef struct
+{
+    smd_evt_id_t evt_id;     /**< The type of event. */
+    uint16_t conn_handle;    /**< The connection this event pertains to. */
+    smd_evt_params_t params; /**< Event specific parameters. Chosen based on evt_id. */
+} smd_evt_t;
+
+
+
+/**@brief Event handler for events from the Security Dispatcher module.
+ *
+ * @param[in]  p_event  The event that has happened.
+ */
+typedef void (*smd_evt_handler_t)(smd_evt_t const * p_event);
+
+
+/**@brief Function for registering with the Security Dispatcher module. This function also
+ *        initializes the module if uninitialized.
+ *
+ * @param[in]  evt_handler  Callback for events from the Security Dispatcher module.
+ *
+ * @retval NRF_SUCCESS       Registration was successful.
+ * @retval NRF_ERROR_NO_MEM  No more registrations possible.
+ * @retval NRF_ERROR_NULL    evt_handler was NULL.
+ */
+ret_code_t smd_register(smd_evt_handler_t evt_handler);
+
+
+/**@brief Function for dispatching SoftDevice events to the Security Dispatcher module.
+ *
+ * @param[in]  ble_evt    The SoftDevice event.
+ */
+void smd_ble_evt_handler(ble_evt_t * ble_evt);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for the current pairing
+ *        procedure on a connection.
+ *
+ * @note If this function returns an @ref NRF_ERROR_NULL, @ref NRF_ERROR_INVALID_PARAM, @ref
+ *       BLE_ERROR_INVALID_CONN_HANDLE, or @ref NRF_ERROR_NO_MEM, this function can be called again
+ *       after corrective action.
+ *
+ * @note To reject a request, call this function with NULL p_sec_params.
+ *
+ * @param[in]  conn_handle   The connection handle of the connection the pairing is happening on.
+ * @param[in]  p_sec_params  The security parameters to use for this link.
+ * @param[in]  p_public_key  A pointer to the public key to use if using LESC, or NULL.
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized, or no parameters have been
+ *                                        requested on that conn_handle, or this error originates
+ *                                        from the SoftDevice.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters (not including conn_handle).
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_NO_MEM               No more room in flash. Fix and reattempt later.
+ * @retval NRF_ERROR_BUSY                 No write buffer. Reattempt later.
+ */
+ret_code_t smd_params_reply(uint16_t                 conn_handle,
+                            ble_gap_sec_params_t   * p_sec_params,
+                            ble_gap_lesc_p256_pk_t * p_public_key);
+
+
+/**@brief Function for initiating security on the link, with the specified parameters.
+ *
+ * @note If the connection is a peripheral connection, this will send a security request to the
+ *       master, but the master is not obligated to initiate pairing or encryption in response.
+ * @note If the connection is a central connection and a key is available, the parameters will be
+ *       used to determine whether to re-pair or to encrypt using the existing key. If no key is
+ *       available, pairing will be started.
+ *
+ * @param[in]  conn_handle      Handle of the connection to initiate pairing on.
+ * @param[in]  p_sec_params     The security parameters to use for this link. As a central, this can
+ *                              be NULL to reject a slave security request.
+ * @param[in]  force_repairing  Whether to force a pairing procedure to happen regardless of whether
+ *                              an encryption key already exists. This argument is only relevant for
+ *                              the central role. Recommended value: false
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_NULL                 p_sec_params was NULL (peripheral only).
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized, or this error originates from
+ *                                        the SoftDevice.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters (not including conn_handle).
+ * @retval NRF_ERROR_BUSY                 Unable to initiate procedure at this time.
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_NO_MEM               No more room in flash.
+ * @retval NRF_ERROR_INTERNAL             No more available peer IDs.
+ */
+ret_code_t smd_link_secure(uint16_t               conn_handle,
+                           ble_gap_sec_params_t * p_sec_params,
+                           bool                   force_repairing);
+
+/** @}
+ * @endcond
+ */
+
+#endif /* SECURITY_DISPATCHER_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.c
new file mode 100644
index 0000000000..2bb3dc917d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.c
@@ -0,0 +1,580 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#include "security_manager.h"
+#include <string.h>
+#include "security_dispatcher.h"
+#include "peer_database.h"
+#include "ble_conn_state.h"
+#include "sdk_common.h"
+#include "id_manager.h"
+
+#define MAX_REGISTRANTS 3                           /**< The number of user that can register with the module. */
+
+typedef struct
+{
+    sm_evt_handler_t              evt_handlers[MAX_REGISTRANTS];
+    uint8_t                       n_registrants;
+    ble_conn_state_user_flag_id_t flag_id_link_secure_pending_busy;
+    ble_conn_state_user_flag_id_t flag_id_link_secure_pending_flash_full;
+    ble_conn_state_user_flag_id_t flag_id_link_secure_force_repairing;
+    ble_conn_state_user_flag_id_t flag_id_link_secure_null_params;
+    ble_conn_state_user_flag_id_t flag_id_params_reply_pending_busy;
+    ble_conn_state_user_flag_id_t flag_id_params_reply_pending_flash_full;
+    ble_conn_state_user_flag_id_t flag_id_reject_pairing;
+    bool                          pdb_evt_handler_registered;
+    bool                          sec_params_valid;
+    ble_gap_sec_params_t          sec_params;
+    ble_gap_lesc_p256_pk_t      * p_public_key;
+} sm_t;
+
+static sm_t m_sm = {.flag_id_link_secure_pending_busy        = BLE_CONN_STATE_USER_FLAG_INVALID,
+                    .flag_id_link_secure_pending_flash_full  = BLE_CONN_STATE_USER_FLAG_INVALID,
+                    .flag_id_link_secure_force_repairing     = BLE_CONN_STATE_USER_FLAG_INVALID,
+                    .flag_id_link_secure_null_params         = BLE_CONN_STATE_USER_FLAG_INVALID,
+                    .flag_id_params_reply_pending_busy       = BLE_CONN_STATE_USER_FLAG_INVALID,
+                    .flag_id_params_reply_pending_flash_full = BLE_CONN_STATE_USER_FLAG_INVALID,
+                    .flag_id_reject_pairing                  = BLE_CONN_STATE_USER_FLAG_INVALID};
+
+#define MODULE_INITIALIZED (m_sm.n_registrants > 0) /**< Expression which is true when the module is initialized. */
+#include "sdk_macros.h"
+
+static void evt_send(sm_evt_t * p_event)
+{
+    for (uint32_t i = 0; i < m_sm.n_registrants; i++)
+    {
+        m_sm.evt_handlers[i](p_event);
+    }
+}
+
+
+static void flags_set_from_err_code(uint16_t conn_handle, ret_code_t err_code, bool params_reply)
+{
+    bool flag_value_flash_full = false;
+    bool flag_value_busy       = false;
+
+    if (    (err_code == NRF_ERROR_NO_MEM)
+         || (err_code == NRF_ERROR_BUSY)
+         || (err_code == NRF_SUCCESS))
+    {
+        if ((err_code == NRF_ERROR_NO_MEM))
+        {
+            flag_value_busy       = false;
+            flag_value_flash_full = true;
+        }
+        else if (err_code == NRF_ERROR_BUSY)
+        {
+            flag_value_busy       = true;
+            flag_value_flash_full = false;
+        }
+        else if (err_code == NRF_SUCCESS)
+        {
+            flag_value_busy       = false;
+            flag_value_flash_full = false;
+        }
+
+        if (params_reply)
+        {
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_sm.flag_id_params_reply_pending_flash_full,
+                                         flag_value_flash_full);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_sm.flag_id_params_reply_pending_busy,
+                                         flag_value_busy);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_sm.flag_id_link_secure_pending_flash_full,
+                                         false);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_sm.flag_id_link_secure_pending_busy,
+                                         false);
+        }
+        else
+        {
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_sm.flag_id_link_secure_pending_flash_full,
+                                         flag_value_flash_full);
+            ble_conn_state_user_flag_set(conn_handle,
+                                         m_sm.flag_id_link_secure_pending_busy,
+                                         flag_value_busy);
+        }
+    }
+}
+
+
+static void events_send_from_err_code(uint16_t conn_handle, ret_code_t err_code)
+{
+     if ((err_code != NRF_SUCCESS) && (err_code != NRF_ERROR_BUSY))
+     {
+        sm_evt_t evt =
+        {
+            .conn_handle = conn_handle,
+            .params = {.error_unexpected = {
+                .error = err_code
+            }}
+        };
+        if (err_code == NRF_ERROR_TIMEOUT)
+        {
+            evt.evt_id = SM_EVT_ERROR_SMP_TIMEOUT;
+        }
+        else if (err_code == NRF_ERROR_NO_MEM)
+        {
+            evt.evt_id = SM_EVT_ERROR_NO_MEM;
+        }
+        else
+        {
+            evt.evt_id = SM_EVT_ERROR_UNEXPECTED;
+        }
+        evt_send(&evt);
+     }
+}
+
+
+static ret_code_t link_secure(uint16_t conn_handle, bool null_params, bool force_repairing, bool send_events)
+{
+    ret_code_t err_code;
+
+    if (!null_params && !m_sm.sec_params_valid)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    if(null_params)
+    {
+        err_code = smd_link_secure(conn_handle, NULL, force_repairing);
+    }
+    else
+    {
+        err_code = smd_link_secure(conn_handle, &m_sm.sec_params, force_repairing);
+    }
+
+    flags_set_from_err_code(conn_handle, err_code, false);
+
+    if (send_events)
+    {
+        events_send_from_err_code(conn_handle, err_code);
+    }
+
+    switch (err_code)
+    {
+        case NRF_ERROR_BUSY:
+            ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_link_secure_null_params, null_params);
+            ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_link_secure_force_repairing, force_repairing);
+            err_code = NRF_SUCCESS;
+            break;
+        case NRF_ERROR_NO_MEM:
+            ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_link_secure_null_params, null_params);
+            ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_link_secure_force_repairing, force_repairing);
+            break;
+        case NRF_SUCCESS:
+        case NRF_ERROR_TIMEOUT:
+        case BLE_ERROR_INVALID_CONN_HANDLE:
+        case NRF_ERROR_INVALID_STATE:
+            /* No action */
+            break;
+        default:
+            err_code = NRF_ERROR_INTERNAL;
+            break;
+    }
+
+    return err_code;
+}
+
+
+static void send_config_req(uint16_t conn_handle)
+{
+    sm_evt_t sm_evt;
+    memset(&sm_evt, 0, sizeof(sm_evt));
+
+    sm_evt.evt_id      = SM_EVT_CONN_SEC_CONFIG_REQ;
+    sm_evt.conn_handle = conn_handle;
+
+    evt_send(&sm_evt);
+}
+
+
+static void smd_params_reply_perform(uint16_t conn_handle)
+{
+    ret_code_t err_code;
+
+    if (  (ble_conn_state_role(conn_handle) == BLE_GAP_ROLE_PERIPH)
+        && im_peer_id_get_by_conn_handle(conn_handle) != PM_PEER_ID_INVALID)
+    {
+        // Bond already exists. Reject the pairing request if the user doesn't intervene.
+        ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_reject_pairing, true);
+        send_config_req(conn_handle);
+    }
+    else
+    {
+        ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_reject_pairing, false);
+    }
+
+    if (   m_sm.sec_params_valid
+        && !ble_conn_state_user_flag_get(conn_handle, m_sm.flag_id_reject_pairing))
+    {
+        err_code = smd_params_reply(conn_handle, &m_sm.sec_params, m_sm.p_public_key);
+    }
+    else
+    {
+        err_code = smd_params_reply(conn_handle, NULL, NULL);
+    }
+
+    flags_set_from_err_code(conn_handle, err_code, true);
+    events_send_from_err_code(conn_handle, err_code);
+}
+
+
+static void smd_evt_handler(smd_evt_t const * p_event)
+{
+    switch(p_event->evt_id)
+    {
+        case SMD_EVT_PARAMS_REQ:
+            smd_params_reply_perform(p_event->conn_handle);
+            break;
+        case SMD_EVT_SLAVE_SECURITY_REQ:
+        {
+            bool null_params = false;
+            if (!m_sm.sec_params_valid)
+            {
+                null_params = true;
+            }
+            else if ((bool)m_sm.sec_params.bond < (bool)p_event->params.slave_security_req.bond)
+            {
+                null_params = true;
+            }
+            else if ((bool)m_sm.sec_params.mitm < (bool)p_event->params.slave_security_req.mitm)
+            {
+                null_params = true;
+            }
+            ret_code_t err_code = link_secure(p_event->conn_handle, null_params, false, true);
+            UNUSED_VARIABLE(err_code); // It is acceptable to ignore the return code because it is
+                                       // acceptable to ignore a security request.
+        }
+        /* fallthrough */
+        case SMD_EVT_PAIRING_SUCCESS:
+        case SMD_EVT_PAIRING_FAIL:
+        case SMD_EVT_LINK_ENCRYPTION_UPDATE:
+        case SMD_EVT_LINK_ENCRYPTION_FAILED:
+        case SMD_EVT_BONDING_INFO_STORED:
+        case SMD_EVT_ERROR_BONDING_INFO:
+        case SMD_EVT_ERROR_UNEXPECTED:
+        case SMD_EVT_SEC_PROCEDURE_START:
+        {
+            sm_evt_t evt;
+            evt.evt_id = (sm_evt_id_t)p_event->evt_id;
+            evt.conn_handle = p_event->conn_handle;
+            evt.params = p_event->params;
+
+            evt_send(&evt);
+        }
+            break;
+    }
+}
+
+
+static void link_secure_pending_process(ble_conn_state_user_flag_id_t flag_id)
+{
+    sdk_mapped_flags_t flag_collection = ble_conn_state_user_flag_collection(flag_id);
+    if (sdk_mapped_flags_any_set(flag_collection))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            bool pending = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], flag_id);
+            if (pending)
+            {
+                bool force_repairing = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_sm.flag_id_link_secure_force_repairing);
+                bool null_params     = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], m_sm.flag_id_link_secure_null_params);
+
+                ret_code_t err_code = link_secure(conn_handle_list.flag_keys[i], null_params, force_repairing, true); // If this fails, it will be automatically retried.
+                UNUSED_VARIABLE(err_code);
+            }
+        }
+    }
+}
+
+
+static void params_reply_pending_process(ble_conn_state_user_flag_id_t flag_id)
+{
+    sdk_mapped_flags_t flag_collection = ble_conn_state_user_flag_collection(flag_id);
+    if (sdk_mapped_flags_any_set(flag_collection))
+    {
+        sdk_mapped_flags_key_list_t conn_handle_list = ble_conn_state_conn_handles();
+
+        for (uint32_t i = 0; i < conn_handle_list.len; i++)
+        {
+            bool pending = ble_conn_state_user_flag_get(conn_handle_list.flag_keys[i], flag_id);
+            if (pending)
+            {
+                smd_params_reply_perform(conn_handle_list.flag_keys[i]);
+            }
+        }
+    }
+}
+
+
+
+static void pdb_evt_handler(pdb_evt_t const * p_event)
+{
+    switch (p_event->evt_id)
+    {
+        case PDB_EVT_COMPRESSED:
+            params_reply_pending_process(m_sm.flag_id_params_reply_pending_flash_full);
+            link_secure_pending_process(m_sm.flag_id_link_secure_pending_flash_full);
+            /* fallthrough */
+        case PDB_EVT_WRITE_BUF_STORED:
+        case PDB_EVT_RAW_STORED:
+        case PDB_EVT_RAW_STORE_FAILED:
+        case PDB_EVT_CLEARED:
+        case PDB_EVT_CLEAR_FAILED:
+        case PDB_EVT_PEER_FREED:
+        case PDB_EVT_PEER_FREE_FAILED:
+            params_reply_pending_process(m_sm.flag_id_params_reply_pending_busy);
+            link_secure_pending_process(m_sm.flag_id_link_secure_pending_busy);
+            break;
+        case PDB_EVT_ERROR_NO_MEM:
+        case PDB_EVT_ERROR_UNEXPECTED:
+            break;
+    }
+}
+
+
+/**@brief Funtion for initializing a BLE Connection State user flag.
+ *
+ * @param[out] flag_id  The flag to initialize.
+ */
+static void flag_id_init(ble_conn_state_user_flag_id_t * p_flag_id)
+{
+    if (*p_flag_id == BLE_CONN_STATE_USER_FLAG_INVALID)
+    {
+        *p_flag_id = ble_conn_state_user_flag_acquire();
+    }
+}
+
+
+ret_code_t sm_register(sm_evt_handler_t evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(evt_handler);
+
+    ret_code_t err_code = NRF_SUCCESS;
+
+    if (!MODULE_INITIALIZED)
+    {
+        flag_id_init(&m_sm.flag_id_link_secure_pending_busy);
+        flag_id_init(&m_sm.flag_id_link_secure_pending_flash_full);
+        flag_id_init(&m_sm.flag_id_link_secure_force_repairing);
+        flag_id_init(&m_sm.flag_id_link_secure_null_params);
+        flag_id_init(&m_sm.flag_id_params_reply_pending_busy);
+        flag_id_init(&m_sm.flag_id_params_reply_pending_flash_full);
+        flag_id_init(&m_sm.flag_id_reject_pairing);
+
+        if (m_sm.flag_id_reject_pairing == BLE_CONN_STATE_USER_FLAG_INVALID)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+        if (!m_sm.pdb_evt_handler_registered)
+        {
+            err_code = pdb_register(pdb_evt_handler);
+            if (err_code != NRF_SUCCESS)
+            {
+                return NRF_ERROR_INTERNAL;
+            }
+            m_sm.pdb_evt_handler_registered = true;
+        }
+        err_code = smd_register(smd_evt_handler);
+        if (err_code != NRF_SUCCESS)
+        {
+            return NRF_ERROR_INTERNAL;
+        }
+    }
+    if (err_code == NRF_SUCCESS)
+    {
+        if ((m_sm.n_registrants < MAX_REGISTRANTS))
+        {
+            m_sm.evt_handlers[m_sm.n_registrants++] = evt_handler;
+        }
+        else
+        {
+            err_code = NRF_ERROR_NO_MEM;
+        }
+    }
+    return err_code;
+}
+
+
+void sm_ble_evt_handler(ble_evt_t * p_ble_evt)
+{
+    VERIFY_MODULE_INITIALIZED_VOID();
+
+    smd_ble_evt_handler(p_ble_evt);
+
+    link_secure_pending_process(m_sm.flag_id_link_secure_pending_busy);
+}
+
+
+static bool sec_params_verify(ble_gap_sec_params_t * p_sec_params)
+{
+    // NULL check.
+    if (p_sec_params == NULL)
+    {
+        return false;
+    }
+
+    // OOB not allowed unless MITM.
+    if (!p_sec_params->mitm && p_sec_params->oob)
+    {
+        return false;
+    }
+
+    // IO Capabilities must be one of the valid values from @ref BLE_GAP_IO_CAPS.
+    if (p_sec_params->io_caps > BLE_GAP_IO_CAPS_KEYBOARD_DISPLAY)
+    {
+        return false;
+    }
+
+    // Must have either IO capabilities or OOB if MITM.
+    if (p_sec_params->mitm && (p_sec_params->io_caps == BLE_GAP_IO_CAPS_NONE) && !p_sec_params->oob)
+    {
+        return false;
+    }
+
+    // Minimum key size cannot be larger than maximum key size.
+    if (p_sec_params->min_key_size > p_sec_params->max_key_size)
+    {
+        return false;
+    }
+
+    // Key size cannot be below 7 bytes.
+    if (p_sec_params->min_key_size < 7)
+    {
+        return false;
+    }
+
+    // Key size cannot be above 16 bytes.
+    if (p_sec_params->max_key_size > 16)
+    {
+        return false;
+    }
+
+    // Signing is not supported.
+    if (p_sec_params->kdist_own.sign || p_sec_params->kdist_peer.sign)
+    {
+        return false;
+    }
+
+    // link bit must be 0.
+    if (p_sec_params->kdist_own.link || p_sec_params->kdist_peer.link)
+    {
+        return false;
+    }
+
+    // If bonding is not enabled, no keys can be distributed.
+    if (!p_sec_params->bond && (   p_sec_params->kdist_own.enc
+                                || p_sec_params->kdist_own.id
+                                || p_sec_params->kdist_peer.enc
+                                || p_sec_params->kdist_peer.id))
+    {
+        return false;
+    }
+
+    // If bonding is enabled, one or more keys must be distributed.
+    if (    p_sec_params->bond
+        && !p_sec_params->kdist_own.enc
+        && !p_sec_params->kdist_own.id
+        && !p_sec_params->kdist_peer.enc
+        && !p_sec_params->kdist_peer.id)
+    {
+        return false;
+    }
+
+    return true;
+}
+
+
+ret_code_t sm_sec_params_set(ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+
+    if (p_sec_params == NULL)
+    {
+        m_sm.sec_params_valid = false;
+        return NRF_SUCCESS;
+    }
+    else if (sec_params_verify(p_sec_params))
+    {
+        m_sm.sec_params       = *p_sec_params;
+        m_sm.sec_params_valid = true;
+        return NRF_SUCCESS;
+    }
+    else
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+}
+
+
+void sm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config)
+{
+    ble_conn_state_user_flag_set(conn_handle, m_sm.flag_id_reject_pairing, !p_conn_sec_config->allow_repairing);
+}
+
+
+ret_code_t sm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key)
+{
+    VERIFY_MODULE_INITIALIZED();
+    m_sm.p_public_key = p_public_key;
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t sm_sec_params_reply(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params)
+{
+    VERIFY_MODULE_INITIALIZED();
+    return NRF_SUCCESS;
+}
+
+
+ret_code_t sm_link_secure(uint16_t conn_handle, bool force_repairing)
+{
+    VERIFY_MODULE_INITIALIZED();
+    ret_code_t err_code = link_secure(conn_handle, false, force_repairing, false);
+    return err_code;
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.h
new file mode 100644
index 0000000000..39b0d92ce2
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/ble/peer_manager/security_manager.h
@@ -0,0 +1,219 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef SECURITY_MANAGER_H__
+#define SECURITY_MANAGER_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_ble.h"
+#include "nrf_ble_gap.h"
+#include "peer_manager_types.h"
+#include "security_dispatcher.h"
+
+
+/**
+ * @cond NO_DOXYGEN
+ * @defgroup security_manager Security Manager
+ * @ingroup peer_manager
+ * @{
+ * @brief An internal module of @ref peer_manager. A module for streamlining pairing, bonding, and
+ *        encryption, including flash storage of shared data.
+ */
+
+
+/**@brief Events that can come from the Security Manager module.
+ */
+typedef enum
+{
+    // SM_EVT_PARAMS_REQ             = SMD_EVT_PARAMS_REQ,             /**< Parameters are required for a pairing procedure on the specified connection. The user must provide them using @ref sm_sec_params_set or @ref sm_sec_params_reply (only this procedure, currently unimplemented). */
+    SM_EVT_SLAVE_SECURITY_REQ     = SMD_EVT_SLAVE_SECURITY_REQ,     /**< The peer (peripheral) has requested link encryption, which has been enabled. */
+    SM_EVT_SEC_PROCEDURE_START    = SMD_EVT_SEC_PROCEDURE_START,    /**< A security procedure has started. */
+    SM_EVT_PAIRING_SUCCESS        = SMD_EVT_PAIRING_SUCCESS,        /**< A pairing procedure (and bonding if applicable) has completed with success. */
+    SM_EVT_PAIRING_FAIL           = SMD_EVT_PAIRING_FAIL,           /**< A pairing procedure has failed which means no encryption and no bond could be established. */
+    SM_EVT_LINK_ENCRYPTION_UPDATE = SMD_EVT_LINK_ENCRYPTION_UPDATE, /**< The security level of the link has been updated. The link is encrypted. */
+    SM_EVT_LINK_ENCRYPTION_FAILED = SMD_EVT_LINK_ENCRYPTION_FAILED, /**< An attempt to start encryption on an unencrypted link failed because the peripheral did not have the correct keys. If the peer is the peripheral, the force_repairing flag should be set when reattempting @ref sm_link_secure. */
+    SM_EVT_BONDING_INFO_STORED    = SMD_EVT_BONDING_INFO_STORED,    /**< Information exchanged during bonding with a peer has been stored persistently. */
+    SM_EVT_ERROR_BONDING_INFO     = SMD_EVT_ERROR_BONDING_INFO,     /**< Information exchanged during bonding with a peer could not be stored persistently, because of an unexpected error. */
+    SM_EVT_ERROR_UNEXPECTED       = SMD_EVT_ERROR_UNEXPECTED,       /**< An operation failed with an unexpected error. The error is provided. This is possibly a fatal error. */
+    SM_EVT_ERROR_NO_MEM           /*= SMD_EVT_ERROR_NO_MEM*/,       /**< An operation failed because there was no available storage room in persistent storage. Please free up room and the operation will automatically continue after the next compression. */
+    SM_EVT_ERROR_SMP_TIMEOUT,                                       /**< An operation failed because there has been an SMP timeout on the link, which entails that no more security operations can be performed on it. */
+    SM_EVT_CONN_SEC_CONFIG_REQ,                                     /**< The peer (central) has requested pairing, but a bond already exists with that peer. Reply by calling @ref sm_conn_sec_config_reply before the event handler returns. If no reply is sent, a default is used. */
+} sm_evt_id_t;
+
+
+typedef struct
+{
+    sm_evt_id_t      evt_id;
+    uint16_t         conn_handle;
+    smd_evt_params_t params;
+} sm_evt_t;
+
+
+
+/**@brief Event handler for events from the Security Manager module.
+ *
+ * @param[in]  event        The event that has happened.
+ * @param[in]  conn_handle  The connection handle the event pertains to.
+ */
+typedef void (*sm_evt_handler_t)(sm_evt_t const * p_event);
+
+
+/**@brief Function for registering with the Security Manager module. This function also
+ *        initializes the module if uninitialized.
+ *
+ * @param[in]  evt_handler  Callback for events from the Security Manager module.
+ *
+ * @retval NRF_SUCCESS        Registration was successful.
+ * @retval NRF_ERROR_NO_MEM   No more registrations possible.
+ * @retval NRF_ERROR_NULL     evt_handler was NULL.
+ * @retval NRF_ERROR_INTERNAL An unexpected error occurred.
+ */
+ret_code_t sm_register(sm_evt_handler_t evt_handler);
+
+
+/**@brief Function for dispatching SoftDevice events to the Security Manager module.
+ *
+ * @param[in]  ble_evt    The SoftDevice event.
+ */
+void sm_ble_evt_handler(ble_evt_t * ble_evt);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for pairing procedures.
+ *
+ * @details Until this is called, all bonding procedures initiated by the peer will be rejected.
+ *          This function can be called multiple times, even with NULL p_sec_params, in which case
+ *          it will go back to rejecting all procedures.
+ *
+ * @param[in]  p_sec_params  The security parameters to use for this link. Can be NULL to reject
+ *                           all pairing procedures.
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ */
+ret_code_t sm_sec_params_set(ble_gap_sec_params_t * p_sec_params);
+
+
+/**@brief Function for providing security configuration for a link.
+ *
+ * @details This function is optional, and must be called in reply to a @ref
+ *          SM_EVT_CONN_SEC_CONFIG_REQ event, before the Peer Manager event handler returns. If it
+ *          is not called in time, a default configuration is used. See @ref pm_conn_sec_config_t
+ *          for the value of the default.
+ *
+ * @param[in]  conn_handle        The connection to set the configuration for.
+ * @param[in]  p_conn_sec_config  The configuration.
+ */
+void sm_conn_sec_config_reply(uint16_t conn_handle, pm_conn_sec_config_t * p_conn_sec_config);
+
+
+/**@brief Experimental function for specifying the public key to use for LESC operations.
+ *
+ * @details This function can be called multiple times. The specified public key will be used for
+ *          all subsequent LESC (LE Secure Connections) operations until the next time this function
+ *          is called.
+ *
+ * @note The key must continue to reside in application memory as it is not copied by Peer Manager.
+ *
+ * @param[in]  p_public_key  The public key to use for all subsequent LESC operations.
+ *
+ * @retval NRF_SUCCESS                    Pairing initiated successfully.
+ * @retval NRF_ERROR_INVALID_STATE        Peer Manager is not initialized.
+ */
+ret_code_t sm_lesc_public_key_set(ble_gap_lesc_p256_pk_t * p_public_key);
+
+
+/**@brief Function for providing pairing and bonding parameters to use for the current pairing
+ *        procedure on a connection.
+ *
+ * @warning This function is not yet implemented.
+ *
+ * @note If this function returns an @ref NRF_ERROR_NULL, @ref NRF_ERROR_INVALID_PARAM, @ref
+ *       BLE_ERROR_INVALID_CONN_HANDLE, or @ref NRF_ERROR_NO_MEM, this function can be called again
+ *       after corrective action.
+ *
+ * @note To reject a request, call this function with NULL p_sec_params.
+ *
+ * @param[in]  conn_handle   The connection handle of the connection the pairing is happening on.
+ * @param[in]  p_sec_params  The security parameters to use for this link.
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized, or no parameters have been
+ *                                        requested on that conn_handle, or this error originates
+ *                                        from the SoftDevice.
+ * @retval NRF_ERROR_INVALID_PARAM        Invalid combination of parameters (not including conn_handle).
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_NO_MEM               No more room in flash. Fix and reattempt later.
+ * @retval NRF_ERROR_BUSY                 No write buffer. Reattempt later.
+ */
+ret_code_t sm_sec_params_reply(uint16_t conn_handle, ble_gap_sec_params_t * p_sec_params);
+
+
+/**@brief Function for initiating security on the link, with the specified parameters.
+ *
+ * @note If the connection is a peripheral connection, this will send a security request to the
+ *       master, but the master is not obligated to initiate pairing or encryption in response.
+ * @note If the connection is a central connection and a key is available, the parameters will be
+ *       used to determine whether to re-pair or to encrypt using the existing key. If no key is
+ *       available, pairing will be started.
+ *
+ * @param[in]  conn_handle      Handle of the connection to initiate pairing on.
+ * @param[in]  force_repairing  Whether to force a pairing procedure to happen regardless of whether
+ *                              an encryption key already exists. This argument is only relevant for
+ *                              the central role. Recommended value: false
+ *
+ * @retval NRF_SUCCESS                    Success.
+ * @retval NRF_ERROR_TIMEOUT              There has been an SMP timeout, so no more SMP operations
+ *                                        can be performed on this link.
+ * @retval BLE_ERROR_INVALID_CONN_HANDLE  Invalid connection handle.
+ * @retval NRF_ERROR_NOT_FOUND            Security parameters have not been set.
+ * @retval NRF_ERROR_INVALID_STATE        Module is not initialized.
+ * @retval NRF_ERROR_INTERNAL             An unexpected error occurred.
+ */
+ret_code_t sm_link_secure(uint16_t conn_handle, bool force_repairing);
+
+/** @}
+ * @endcond
+ */
+
+#endif /* SECURITY_MANAGER_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.c
new file mode 100644
index 0000000000..5d5c843f8d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.c
@@ -0,0 +1,313 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "ble_flash.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "nrf_soc.h"
+#include "nordic_common.h"
+#include "nrf_error.h"
+#include "nrf.h"
+#include "app_util.h"
+
+
+static volatile bool m_radio_active = false;  /**< TRUE if radio is active (or about to become active), FALSE otherwise. */
+
+
+uint16_t ble_flash_crc16_compute(uint8_t * p_data, uint16_t size, uint16_t * p_crc)
+{
+    uint16_t i;
+    uint16_t crc = (p_crc == NULL) ? 0xffff : *p_crc;
+
+    for (i = 0; i < size; i++)
+    {
+        crc  = (unsigned char)(crc >> 8) | (crc << 8);
+        crc ^= p_data[i];
+        crc ^= (unsigned char)(crc & 0xff) >> 4;
+        crc ^= (crc << 8) << 4;
+        crc ^= ((crc & 0xff) << 4) << 1;
+    }
+    return crc;
+}
+
+
+/**@brief Function for erasing a page in flash.
+ * 
+ * @param[in]  p_page  Pointer to first word in page to be erased.
+ */
+static void flash_page_erase(uint32_t * p_page)
+{
+    // Turn on flash erase enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Een << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    // Erase page.
+    NRF_NVMC->ERASEPAGE = (uint32_t)p_page;
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    // Turn off flash erase enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing
+    }
+}
+
+
+/**@brief Function for writing one word to flash. Unprotected write, which can interfere with radio communication.
+ *
+ * @details This function DOES NOT use the m_radio_active variable, but will force the write even
+ *          when the radio is active. To be used only from @ref ble_flash_page_write.
+ *
+ * @note Flash location to be written must have been erased previously.
+ *
+ * @param[in]  p_address   Pointer to flash location to be written.
+ * @param[in]  value       Value to write to flash.
+ */
+static void flash_word_unprotected_write(uint32_t * p_address, uint32_t value)
+{
+    // Turn on flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+    *p_address = value;
+    
+    // Wait flash write to finish
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    // Turn off flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+}
+
+
+/**@brief Function for writing one word to flash.
+ *
+ * @note Flash location to be written must have been erased previously.
+ *
+ * @param[in]  p_address   Pointer to flash location to be written.
+ * @param[in]  value       Value to write to flash.
+ */
+static void flash_word_write(uint32_t * p_address, uint32_t value)
+{
+    // If radio is active, wait for it to become inactive.
+    while (m_radio_active)
+    {
+        // Do nothing (just wait for radio to become inactive).
+        (void) sd_app_evt_wait();
+    }
+
+    // Turn on flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+
+    *p_address = value;
+    // Wait flash write to finish
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing.
+    }
+    // Turn off flash write enable and wait until the NVMC is ready.
+    NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+        // Do nothing
+    }
+}
+
+
+uint32_t ble_flash_word_write(uint32_t * p_address, uint32_t value)
+{
+    flash_word_write(p_address, value);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_block_write(uint32_t * p_address, uint32_t * p_in_array, uint16_t word_count)
+{
+    uint16_t i;
+
+    for (i = 0; i < word_count; i++)
+    {
+        flash_word_write(p_address, p_in_array[i]);
+        p_address++;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_erase(uint8_t page_num)
+{
+    uint32_t * p_page = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    flash_page_erase(p_page);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_write(uint8_t page_num, uint32_t * p_in_array, uint8_t word_count)
+{
+    int        i;
+    uint32_t * p_page;
+    uint32_t * p_curr_addr;
+    uint16_t   in_data_crc;
+    uint16_t   flash_crc;
+    uint32_t   flash_header;
+
+    p_page      = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    p_curr_addr = p_page;
+
+    // Calculate CRC of the data to write.
+    in_data_crc = ble_flash_crc16_compute((uint8_t *)p_in_array,
+                                          word_count * sizeof(uint32_t),
+                                          NULL);
+
+    // Compare the calculated to the one in flash.
+    flash_header = *p_curr_addr;
+    flash_crc    = (uint16_t)flash_header;
+
+    if (flash_crc == in_data_crc)
+    {
+        // Data is the same as the data already stored in flash, return without modifying flash.
+        return NRF_SUCCESS;
+    }
+
+    // Erase flash page
+    flash_page_erase(p_page);
+
+    // Reserve space for magic number (for detecting if flash content is valid).
+    p_curr_addr++;
+
+    // Reserve space for saving word_count.
+    p_curr_addr++;
+
+    // Write data
+    for (i = 0; i < word_count; i++)
+    {
+        flash_word_unprotected_write(p_curr_addr, p_in_array[i]);
+        p_curr_addr++;
+    }
+
+    // Write number of elements.
+    flash_word_write(p_page + 1, (uint32_t)(word_count));
+
+    // Write magic number and CRC to indicate that flash content is valid.
+    flash_header = BLE_FLASH_MAGIC_NUMBER | (uint32_t)in_data_crc;
+    flash_word_write(p_page, flash_header);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_read(uint8_t page_num, uint32_t * p_out_array, uint8_t * p_word_count)
+{
+    int        byte_count;
+    uint32_t * p_page;
+    uint32_t * p_curr_addr;
+    uint32_t   flash_header;
+    uint32_t   calc_header;
+    uint16_t   calc_crc;
+    uint32_t   tmp;
+
+    p_page      = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);    
+    p_curr_addr = p_page;
+
+    // Check if block is valid
+    flash_header = *p_curr_addr;
+    tmp = flash_header & 0xFFFF0000;
+    if (tmp != BLE_FLASH_MAGIC_NUMBER)
+    {
+        *p_word_count = 0;
+        return NRF_ERROR_NOT_FOUND;
+    }
+    p_curr_addr++;
+
+    // Read number of elements
+    *p_word_count = (uint8_t)(*(p_curr_addr));
+    p_curr_addr++;
+
+    // Read data
+    byte_count = (*p_word_count) * sizeof(uint32_t);
+    memcpy(p_out_array, p_curr_addr, byte_count);
+
+    // Check CRC
+    calc_crc = ble_flash_crc16_compute((uint8_t *)p_out_array,
+                                       (*p_word_count) * sizeof(uint32_t),
+                                       NULL);
+    calc_header = BLE_FLASH_MAGIC_NUMBER | (uint32_t)calc_crc;
+
+    if (calc_header != flash_header)
+    {
+        return NRF_ERROR_NOT_FOUND;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t ble_flash_page_addr(uint8_t page_num, uint32_t ** pp_page_addr)
+{
+    *pp_page_addr = (uint32_t *)(BLE_FLASH_PAGE_SIZE * page_num);
+    return NRF_SUCCESS;
+}
+
+
+void ble_flash_on_radio_active_evt(bool radio_active)
+{
+    m_radio_active = radio_active;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.h
new file mode 100644
index 0000000000..c3943438c1
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ble_flash/ble_flash.h
@@ -0,0 +1,169 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup ble_flash_module Flash Manager
+ * @{
+ * @ingroup ble_sdk_lib
+ * @brief Module for accessing flash memory.
+ *
+ * @details It contains functions for reading, writing and erasing one page in flash.
+ *
+ *          The module uses the first 32 bits of the flash page to write a magic number in order to
+ *          determine if the page has been written or not.
+ *
+ * @note Be careful not to use a page number in the SoftDevice area (which currently occupies the
+ *       range 0 to 127), or in your application space! In both cases, this would end up
+ *       with a hard fault.
+ */
+
+#ifndef BLE_FLASH_H__
+#define BLE_FLASH_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+
+#define BLE_FLASH_PAGE_SIZE     ((uint16_t)NRF_FICR->CODEPAGESIZE)  /**< Size of one flash page. */
+#define BLE_FLASH_MAGIC_NUMBER  0x45DE0000                          /**< Magic value to identify if flash contains valid data. */
+#define BLE_FLASH_EMPTY_MASK    0xFFFFFFFF                          /**< Bit mask that defines an empty address in flash. */
+
+
+/**@brief Macro for getting the end of the flash available for application.
+ * 
+ * @details    The result flash page number indicates the end boundary of the flash available 
+ *             to the application. If a bootloader is used, the end will be the start of the 
+ *             bootloader region. Otherwise, the end will be the size of the flash. 
+ */
+#define BLE_FLASH_PAGE_END \
+    ((NRF_UICR->NRFFW[0] != BLE_FLASH_EMPTY_MASK) \
+        ? (NRF_UICR->NRFFW[0] / BLE_FLASH_PAGE_SIZE) \
+        : NRF_FICR->CODESIZE)
+
+/**@brief Function for erasing the specified flash page, and then writes the given data to this page.
+ *
+ * @warning This operation blocks the CPU. DO NOT use while in a connection!
+ *
+ * @param[in]  page_num     Page number to update.
+ * @param[in]  p_in_array   Pointer to a RAM area containing the elements to write in flash.
+ *                          This area has to be 32 bits aligned.
+ * @param[in]  word_count   Number of 32 bits words to write in flash.
+ *
+ * @return     NRF_SUCCESS on successful flash write, otherwise an error code.
+ */
+uint32_t ble_flash_page_write(uint8_t page_num, uint32_t * p_in_array, uint8_t word_count);
+
+/**@brief Function for reading data from flash to RAM.
+ *
+ * @param[in]  page_num       Page number to read.
+ * @param[out] p_out_array    Pointer to a RAM area where the found data will be written. 
+ *                            This area has to be 32 bits aligned.
+ * @param[out] p_word_count   Number of 32 bits words read.
+ *
+ * @return     NRF_SUCCESS on successful upload, NRF_ERROR_NOT_FOUND if no valid data has been found
+ *             in flash (first 32 bits not equal to the MAGIC_NUMBER+CRC).
+ */
+uint32_t ble_flash_page_read(uint8_t page_num, uint32_t * p_out_array, uint8_t * p_word_count);
+
+/**@brief Function for erasing a flash page.
+ *
+ * @note This operation blocks the CPU, so it should not be done while the radio is running!
+ *
+ * @param[in]  page_num   Page number to erase.
+ *
+ * @return     NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t ble_flash_page_erase(uint8_t page_num);
+
+/**@brief Function for writing one word to flash.
+ *
+ * @note Flash location to be written must have been erased previously.
+ *
+ * @param[in]  p_address   Pointer to flash location to be written.
+ * @param[in]  value       Value to write to flash.
+ *
+ * @return     NRF_SUCCESS.
+ */
+uint32_t ble_flash_word_write(uint32_t * p_address, uint32_t value);
+
+/**@brief Function for writing a data block to flash.
+ *
+ * @note Flash locations to be written must have been erased previously.
+ *
+ * @param[in]  p_address    Pointer to start of flash location to be written.
+ * @param[in]  p_in_array   Pointer to start of flash block to be written.
+ * @param[in]  word_count   Number of words to be written.
+ *
+ * @return     NRF_SUCCESS.
+ */
+uint32_t ble_flash_block_write(uint32_t * p_address, uint32_t * p_in_array, uint16_t word_count);
+
+/**@brief Function for computing pointer to start of specified flash page.
+ *
+ * @param[in]  page_num       Page number.
+ * @param[out] pp_page_addr   Pointer to start of flash page.
+ *
+ * @return     NRF_SUCCESS.
+ */
+uint32_t ble_flash_page_addr(uint8_t page_num, uint32_t ** pp_page_addr);
+
+/**@brief Function for calculating a 16 bit CRC using the CRC-16-CCITT scheme.
+ * 
+ * @param[in]  p_data   Pointer to data on which the CRC is to be calulated.
+ * @param[in]  size     Number of bytes on which the CRC is to be calulated.
+ * @param[in]  p_crc    Initial CRC value (if NULL, a preset value is used as the initial value).
+ *
+ * @return     Calculated CRC.
+ */
+uint16_t ble_flash_crc16_compute(uint8_t * p_data, uint16_t size, uint16_t * p_crc);
+
+/**@brief Function for handling flashing module Radio Notification event.
+ *
+ * @note For flash writing to work safely while in a connection or while advertising, this function
+ *       MUST be called from the Radio Notification module's event handler (see
+ *       @ref ble_radio_notification for details).
+ *
+ * @param[in]  radio_active   TRUE if radio is active (or about to become active), FALSE otherwise.
+ */
+void ble_flash_on_radio_active_evt(bool radio_active);
+
+#endif // BLE_FLASH_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.c
new file mode 100644
index 0000000000..00265d60b0
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.c
@@ -0,0 +1,506 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_clock.h"
+#include "nrf_error.h"
+#include "nordic_common.h"
+
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_sdm.h"
+#include "nrf_soc.h"
+#include "app_util_platform.h"
+#else
+#include "app_util_platform.h"
+#endif // SOFTDEVICE_PRESENT
+
+/*lint -save -e652 */
+#define NRF_CLOCK_LFCLK_RC    CLOCK_LFCLKSRC_SRC_RC
+#define NRF_CLOCK_LFCLK_Xtal  CLOCK_LFCLKSRC_SRC_Xtal
+#define NRF_CLOCK_LFCLK_Synth CLOCK_LFCLKSRC_SRC_Synth
+/*lint -restore */
+
+#define INT_MAX 0xFFFFFFFF
+
+#if (CLOCK_CONFIG_LF_SRC == NRF_CLOCK_LFCLK_RC) && !defined(SOFTDEVICE_PRESENT)
+#define CALIBRATION_SUPPORT 1
+#else
+#define CALIBRATION_SUPPORT 0
+#endif
+typedef enum
+{
+    CAL_STATE_IDLE,
+    CAL_STATE_CT,
+    CAL_STATE_HFCLK_REQ,
+    CAL_STATE_CAL,
+    CAL_STATE_ABORT,
+} nrf_drv_clock_cal_state_t;
+
+/**@brief CLOCK control block. */
+typedef struct
+{
+    volatile uint32_t                       hfclk_requests;     /*< High-frequency clock request counter. */
+    volatile nrf_drv_clock_handler_item_t * p_hf_head;
+    bool                                    module_initialized; /*< Indicate the state of module */
+    volatile bool                           hfclk_on;           /*< High-frequency clock state. */
+#ifndef SOFTDEVICE_PRESENT
+    volatile bool                           lfclk_on;           /*< Low-frequency clock state. */
+    uint32_t                                lfclk_requests;     /*< Low-frequency clock request counter. */
+    volatile nrf_drv_clock_handler_item_t * p_lf_head;
+#if CALIBRATION_SUPPORT
+    nrf_drv_clock_handler_item_t            cal_hfclk_started_handler_item;
+    nrf_drv_clock_event_handler_t           cal_done_handler;
+    volatile nrf_drv_clock_cal_state_t      cal_state;
+#endif //CALIBRATION_SUPPORT
+#endif //SOFTDEVICE_PRESENT
+}nrf_drv_clock_cb_t;
+
+static nrf_drv_clock_cb_t m_clock_cb;
+
+#ifndef SOFTDEVICE_PRESENT
+/**@brief Function for starting LFCLK. This function will return immediately without waiting for start.
+ */
+static void lfclk_start(void)
+{
+    nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED);
+    nrf_clock_int_enable(NRF_CLOCK_INT_LF_STARTED_MASK);
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTART);
+}
+
+/**@brief Function for stopping LFCLK and calibration (if it was set up).
+ */
+static void lfclk_stop(void)
+{
+#if CALIBRATION_SUPPORT
+    (void)nrf_drv_clock_calibration_abort();
+#endif //CALIBRATION_SUPPORT
+
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_LFCLKSTOP);
+    while (nrf_clock_lf_is_running())
+    {}
+}
+#endif
+static void hfclk_start(void)
+{
+#ifndef SOFTDEVICE_PRESENT
+    nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
+    nrf_clock_int_enable(NRF_CLOCK_INT_HF_STARTED_MASK);
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTART);
+#else
+    UNUSED_VARIABLE(sd_clock_hfclk_request());
+#endif
+}
+
+static void hfclk_stop(void)
+{
+#ifndef SOFTDEVICE_PRESENT
+    nrf_clock_task_trigger(NRF_CLOCK_TASK_HFCLKSTOP);
+    while (nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY))
+    {}
+#else
+    UNUSED_VARIABLE(sd_clock_hfclk_release());
+#endif
+}
+
+ret_code_t nrf_drv_clock_init(void)
+{
+    uint32_t result = NRF_SUCCESS;
+
+    if (m_clock_cb.module_initialized)
+    {
+        return MODULE_ALREADY_INITIALIZED;
+    }
+
+    m_clock_cb.p_hf_head      = NULL;
+    m_clock_cb.hfclk_requests = 0;
+#ifndef SOFTDEVICE_PRESENT
+    m_clock_cb.p_lf_head      = NULL;
+    m_clock_cb.lfclk_requests = 0;
+    nrf_clock_xtalfreq_set(CLOCK_CONFIG_XTAL_FREQ);
+    nrf_clock_lf_src_set((nrf_clock_lfclk_t)CLOCK_CONFIG_LF_SRC);
+    nrf_drv_common_irq_enable(POWER_CLOCK_IRQn, CLOCK_CONFIG_IRQ_PRIORITY);
+#if CALIBRATION_SUPPORT
+    m_clock_cb.cal_state = CAL_STATE_IDLE;
+#endif // CALIBRATION_SUPPORT
+#else // SOFTDEVICE_PRESENT
+        uint8_t is_enabled;
+        result = sd_softdevice_is_enabled(&is_enabled);
+        if((result == NRF_SUCCESS) && !is_enabled)
+        {
+            result = NRF_ERROR_SOFTDEVICE_NOT_ENABLED;
+        }
+#endif // SOFTDEVICE_PRESENT
+    m_clock_cb.module_initialized = true;
+    return result;
+}
+
+void nrf_drv_clock_uninit(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+#ifndef SOFTDEVICE_PRESENT
+    nrf_drv_common_irq_disable(POWER_CLOCK_IRQn);
+    nrf_clock_int_disable(0xFFFFFFFF);
+	lfclk_stop();
+#endif
+    hfclk_stop();
+    m_clock_cb.module_initialized = false;
+}
+
+static void item_enqueue(nrf_drv_clock_handler_item_t ** p_head,
+                         nrf_drv_clock_handler_item_t * p_item)
+{
+    if (*p_head)
+    {
+        p_item->p_next = *p_head;
+        *p_head = p_item;
+    }
+    else
+    {
+        p_item->p_next = NULL;
+        *p_head = p_item;
+    }
+}
+
+static nrf_drv_clock_handler_item_t * item_dequeue(nrf_drv_clock_handler_item_t ** p_head)
+{
+    nrf_drv_clock_handler_item_t * p_item = *p_head;
+    if (p_item)
+    {
+        *p_head = p_item->p_next;
+    }
+
+    return p_item;
+}
+
+void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item)
+{
+    ASSERT(m_clock_cb.module_initialized);
+#ifndef SOFTDEVICE_PRESENT
+    ASSERT(m_clock_cb.lfclk_requests != INT_MAX);
+    CRITICAL_REGION_ENTER();
+    if (m_clock_cb.lfclk_on)
+    {
+        if (p_handler_item)
+        {
+            p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_LFCLK_STARTED);
+        }
+    }
+    else
+    {
+
+        if (p_handler_item)
+        {
+            item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head, p_handler_item);
+        }
+        if (m_clock_cb.lfclk_requests == 0)
+        {
+            lfclk_start();
+        }
+    }
+    m_clock_cb.lfclk_requests++;
+    CRITICAL_REGION_EXIT();
+#else
+    if (p_handler_item)
+    {
+        p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_LFCLK_STARTED);
+    }
+#endif // SOFTDEVICE_PRESENT
+}
+
+
+void nrf_drv_clock_lfclk_release(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+#ifndef SOFTDEVICE_PRESENT
+    ASSERT(m_clock_cb.lfclk_requests > 0);
+
+    CRITICAL_REGION_ENTER();
+    m_clock_cb.lfclk_requests--;
+    if (m_clock_cb.lfclk_requests == 0)
+    {
+        lfclk_stop();
+        m_clock_cb.lfclk_on = false;
+        m_clock_cb.p_lf_head   = NULL;
+    }
+    CRITICAL_REGION_EXIT();
+#endif // SOFTDEVICE_PRESENT
+}
+
+
+bool nrf_drv_clock_lfclk_is_running(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+    bool result;
+#ifndef SOFTDEVICE_PRESENT
+    result = nrf_clock_lf_is_running();
+#else
+    result = true;
+#endif
+    return result;
+}
+
+void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item)
+{
+    ASSERT(m_clock_cb.module_initialized);
+    ASSERT(m_clock_cb.hfclk_requests != INT_MAX);
+
+    CRITICAL_REGION_ENTER();
+    if (m_clock_cb.hfclk_on)
+    {
+        if (p_handler_item)
+        {
+            p_handler_item->event_handler(NRF_DRV_CLOCK_EVT_HFCLK_STARTED);
+        }
+    }
+    else
+    {
+        if (p_handler_item)
+        {
+            item_enqueue((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head, p_handler_item);
+        }
+        if (m_clock_cb.hfclk_requests == 0)
+        {
+            hfclk_start();
+        }
+    }
+    m_clock_cb.hfclk_requests++;
+    CRITICAL_REGION_EXIT();
+}
+
+void nrf_drv_clock_hfclk_release(void)
+{
+    ASSERT(m_clock_cb.module_initialized);
+    ASSERT(m_clock_cb.hfclk_requests > 0);
+
+    //disable interrupts CLOCK or SoftDevice events
+    CRITICAL_REGION_ENTER();
+    m_clock_cb.hfclk_requests--;
+    if (m_clock_cb.hfclk_requests == 0)
+    {
+        hfclk_stop();
+        m_clock_cb.hfclk_on = false;
+        m_clock_cb.p_hf_head   = NULL;
+    }
+    CRITICAL_REGION_EXIT();
+    //enable interrupts CLOCK or SoftDevice events
+}
+
+bool nrf_drv_clock_hfclk_is_running(void)
+{
+    bool result;
+    ASSERT(m_clock_cb.module_initialized);
+#ifndef SOFTDEVICE_PRESENT
+    result = nrf_clock_hf_is_running(NRF_CLOCK_HFCLK_HIGH_ACCURACY);
+#else
+    uint32_t is_running;
+    UNUSED_VARIABLE(sd_clock_hfclk_is_running(&is_running));
+    result = is_running ? true : false;
+#endif
+    return result;
+}
+
+#if CALIBRATION_SUPPORT
+static void clock_calibration_hf_started(nrf_drv_clock_evt_type_t event)
+{
+    if (m_clock_cb.cal_state == CAL_STATE_ABORT)
+    {
+        nrf_drv_clock_hfclk_release();
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+        if (m_clock_cb.cal_done_handler)
+        {
+            m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED);
+        }
+    }
+    else
+    {
+        nrf_clock_int_enable(NRF_CLOCK_INT_DONE_MASK);
+        m_clock_cb.cal_state = CAL_STATE_CAL;
+        nrf_clock_task_trigger(NRF_CLOCK_TASK_CAL);
+    }
+}
+#endif
+
+ret_code_t nrf_drv_clock_calibration_start(uint8_t interval, nrf_drv_clock_event_handler_t handler)
+{
+#if CALIBRATION_SUPPORT
+    ASSERT(m_clock_cb.cal_state == CAL_STATE_IDLE);
+    ret_code_t ret = NRF_SUCCESS;
+    if (m_clock_cb.lfclk_on == false)
+    {
+        ret = NRF_ERROR_INVALID_STATE;
+    }
+    else if (m_clock_cb.cal_state == CAL_STATE_IDLE)
+    {
+        m_clock_cb.cal_done_handler = handler;
+        m_clock_cb.cal_hfclk_started_handler_item.event_handler = clock_calibration_hf_started;
+        if (interval == 0)
+        {
+            m_clock_cb.cal_state = CAL_STATE_HFCLK_REQ;
+            nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item);
+        }
+        else
+        {
+            m_clock_cb.cal_state = CAL_STATE_CT;
+            nrf_clock_cal_timer_timeout_set(interval);
+            nrf_clock_int_enable(NRF_CLOCK_INT_CTTO_MASK);
+            nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTART);
+        }
+    }
+    else
+    {
+        ret = NRF_ERROR_BUSY;
+    }
+    return ret;
+#else //CALIBRATION_SUPPORT
+    return NRF_ERROR_FORBIDDEN;
+#endif
+}
+
+
+ret_code_t nrf_drv_clock_calibration_abort(void)
+{
+#if CALIBRATION_SUPPORT
+    CRITICAL_REGION_ENTER();
+    switch(m_clock_cb.cal_state)
+    {
+    case CAL_STATE_CT:
+        nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK);
+        nrf_clock_task_trigger(NRF_CLOCK_TASK_CTSTOP);
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+        if (m_clock_cb.cal_done_handler)
+        {
+            m_clock_cb.cal_done_handler(NRF_DRV_CLOCK_EVT_CAL_ABORTED);
+        }
+        break;
+    case CAL_STATE_HFCLK_REQ:
+        /* fall through. */
+    case CAL_STATE_CAL:
+        m_clock_cb.cal_state = CAL_STATE_ABORT;
+        break;
+    default:
+        break;
+    }
+    CRITICAL_REGION_EXIT();
+    return NRF_SUCCESS;
+#else //CALIBRATION_SUPPORT
+    return NRF_ERROR_FORBIDDEN;
+#endif
+}
+
+ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating)
+{
+#if CALIBRATION_SUPPORT
+    ASSERT(m_clock_cb.module_initialized);
+    *p_is_calibrating = (m_clock_cb.cal_state != CAL_STATE_IDLE);
+    return NRF_SUCCESS;
+#else //CALIBRATION_SUPPORT
+    return NRF_ERROR_FORBIDDEN;
+#endif
+}
+
+static __INLINE void clock_clk_started_notify(nrf_drv_clock_handler_item_t **p_head,
+                                                nrf_drv_clock_evt_type_t evt_type)
+{
+    while(1)
+    {
+        nrf_drv_clock_handler_item_t * p_item = item_dequeue(p_head);
+        if (p_item)
+        {
+            p_item->event_handler(evt_type);
+        }
+        else
+        {
+            break;
+        }
+    }
+}
+
+#ifndef SOFTDEVICE_PRESENT
+void POWER_CLOCK_IRQHandler(void)
+{
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_HFCLKSTARTED))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_HFCLKSTARTED);
+        nrf_clock_int_disable(NRF_CLOCK_INT_HF_STARTED_MASK);
+        m_clock_cb.hfclk_on = true;
+        clock_clk_started_notify((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head, NRF_DRV_CLOCK_EVT_HFCLK_STARTED);
+    }
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_LFCLKSTARTED))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_LFCLKSTARTED);
+        nrf_clock_int_disable(NRF_CLOCK_INT_LF_STARTED_MASK);
+        m_clock_cb.lfclk_on = true;
+        clock_clk_started_notify((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_lf_head, NRF_DRV_CLOCK_EVT_LFCLK_STARTED);
+    }
+#if CALIBRATION_SUPPORT
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_CTTO))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_CTTO);
+        nrf_clock_int_disable(NRF_CLOCK_INT_CTTO_MASK);
+        nrf_drv_clock_hfclk_request(&m_clock_cb.cal_hfclk_started_handler_item);
+    }
+
+    if (nrf_clock_event_check(NRF_CLOCK_EVENT_DONE))
+    {
+        nrf_clock_event_clear(NRF_CLOCK_EVENT_DONE);
+        nrf_clock_int_disable(NRF_CLOCK_INT_DONE_MASK);
+
+        nrf_drv_clock_hfclk_release();
+        nrf_drv_clock_evt_type_t evt_type = (m_clock_cb.cal_state == CAL_STATE_ABORT) ?
+                                       NRF_DRV_CLOCK_EVT_CAL_ABORTED : NRF_DRV_CLOCK_EVT_CAL_DONE;
+        m_clock_cb.cal_state = CAL_STATE_IDLE;
+        if (m_clock_cb.cal_done_handler)
+        {
+            m_clock_cb.cal_done_handler(evt_type);
+        }
+    }
+#endif //CALIBRATION_SUPPORT
+}
+#else
+void nrf_drv_clock_on_soc_event(uint32_t evt_id)
+{
+    if (evt_id == NRF_EVT_HFCLKSTARTED)
+    {
+        clock_clk_started_notify((nrf_drv_clock_handler_item_t **)&m_clock_cb.p_hf_head, NRF_DRV_CLOCK_EVT_HFCLK_STARTED);
+    }
+}
+#endif // SOFTDEVICE_PRESENT
+
+#undef NRF_CLOCK_LFCLK_RC
+#undef NRF_CLOCK_LFCLK_Xtal
+#undef NRF_CLOCK_LFCLK_Synth
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.h
new file mode 100644
index 0000000000..583902e4d8
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/clock/nrf_drv_clock.h
@@ -0,0 +1,273 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_CLOCK_H__
+#define NRF_DRV_CLOCK_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_assert.h"
+#include "nrf_clock.h"
+#include "nrf_drv_config.h"
+#include "nrf_drv_common.h"
+
+/**
+ *
+ * @addtogroup nrf_clock Clock HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Clock APIs.
+ * @details The clock HAL provides basic APIs for accessing the registers of the clock. 
+ * The clock driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_clock_drv Clock driver
+ * @{
+ * @ingroup nrf_clock
+ * @brief Driver for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK).
+ */
+
+/**
+ * @brief Clock events.
+ */
+typedef enum
+{
+    NRF_DRV_CLOCK_EVT_HFCLK_STARTED, ///< HFCLK has been started.
+    NRF_DRV_CLOCK_EVT_LFCLK_STARTED, ///< LFCLK has been started.
+    NRF_DRV_CLOCK_EVT_CAL_DONE,      ///< Calibration is done.
+    NRF_DRV_CLOCK_EVT_CAL_ABORTED,   ///< Calibration has been aborted.
+} nrf_drv_clock_evt_type_t;
+
+/**
+ * @brief Clock event handler.
+ *
+ * @param[in] event  Event.
+ */
+typedef void (*nrf_drv_clock_event_handler_t)(nrf_drv_clock_evt_type_t event);
+
+// Forward declaration of the nrf_drv_clock_handler_item_t type.
+typedef struct nrf_drv_clock_handler_item_s nrf_drv_clock_handler_item_t;
+
+struct nrf_drv_clock_handler_item_s
+{
+    nrf_drv_clock_handler_item_t * p_next;        ///< A pointer to the next handler that should be called when the clock is started.
+    nrf_drv_clock_event_handler_t  event_handler; ///< Function to be called when the clock is started.
+};
+
+/**
+ * @brief Function for initializing the nrf_drv_clock module.
+ *
+ * After initialization, the module is in power off state (clocks are not requested).
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     MODULE_ALREADY_INITIALIZED         If the driver was already initialized.
+ * @retval     NRF_ERROR_SOFTDEVICE_NOT_ENABLED   If the SoftDevice was not enabled.
+ */
+ret_code_t nrf_drv_clock_init(void);
+
+/**
+ * @brief Function for uninitializing the clock module.
+ *
+ */
+void nrf_drv_clock_uninit(void);
+
+/**
+ * @brief Function for requesting the LFCLK. 
+ * 
+ * The low-frequency clock can be requested by different modules
+ * or contexts. The driver ensures that the clock will be started only when it is requested
+ * the first time. If the clock is not ready but it was already started, the handler item that is
+ * provided as an input parameter is added to the list of handlers that will be notified
+ * when the clock is started. If the clock is already enabled, user callback is called from the
+ * current context.
+ *
+ * The first request will start the selected LFCLK source. If an event handler is
+ * provided, it will be called once the LFCLK is started. If the LFCLK was already started at this 
+ * time, the event handler will be called from the context of this function. Additionally,
+ * the @ref nrf_drv_clock_lfclk_is_running function can be polled to check if the clock has started.
+ *
+ * @note When a SoftDevice is enabled, the LFCLK is always running and the driver cannot control it.
+ *
+ * @note The handler item provided by the user cannot be an automatic variable.
+ *
+ * @param[in] p_handler_item A pointer to the event handler structure.
+ */
+void nrf_drv_clock_lfclk_request(nrf_drv_clock_handler_item_t * p_handler_item);
+
+/**
+ * @brief Function for releasing the LFCLK. 
+ *
+ * If there are no more requests, the LFCLK source will be stopped.
+ *
+ * @note When a SoftDevice is enabled, the LFCLK is always running.
+ */
+void nrf_drv_clock_lfclk_release(void);
+
+/**
+ * @brief Function for checking the LFCLK state.
+ *
+ * @retval true If the LFCLK is running.
+ * @retval false If the LFCLK is not running.
+ */
+bool nrf_drv_clock_lfclk_is_running(void);
+
+/**
+ * @brief Function for requesting the high-accuracy source HFCLK. 
+ *
+ * The high-accuracy source 
+ * can be requested by different modules or contexts. The driver ensures that the high-accuracy
+ * clock will be started only when it is requested the first time. If the clock is not ready
+ * but it was already started, the handler item that is provided as an input parameter is added
+ * to the list of handlers that will be notified when the clock is started.
+ *
+ * If an event handler is provided, it will be called once the clock is started. If the clock was already
+ * started at this time, the event handler will be called from the context of this function. Additionally,
+ * the @ref nrf_drv_clock_hfclk_is_running function can be polled to check if the clock has started.
+ *
+ * @note If a SoftDevice is running, the clock is managed by the SoftDevice and all requests are handled by
+ *       the SoftDevice. This function cannot be called from all interrupt priority levels in that case.
+ * @note The handler item provided by the user cannot be an automatic variable.
+ *
+ * @param[in] p_handler_item A pointer to the event handler structure.
+ */
+void nrf_drv_clock_hfclk_request(nrf_drv_clock_handler_item_t * p_handler_item);
+
+/**
+ * @brief Function for releasing the high-accuracy source HFCLK. 
+ *
+ * If there are no more requests, the high-accuracy source will be released.
+ */
+void nrf_drv_clock_hfclk_release(void);
+
+/**
+ * @brief Function for checking the HFCLK state.
+ *
+ * @retval true If the HFCLK is running (for \nRFXX XTAL source).
+ * @retval false If the HFCLK is not running.
+ */
+bool nrf_drv_clock_hfclk_is_running(void);
+
+/**
+ * @brief Function for starting a single calibration process.
+ *
+ * This function can also delay the start of calibration by a user-specified value. The delay will use
+ * a low-power timer that is part of the CLOCK module. @ref nrf_drv_clock_is_calibrating can be called to
+ * check if calibration is still in progress. If a handler is provided, the user can be notified when
+ * calibration is completed. The ext calibration can be started from the handler context.
+ *
+ * The calibration process consists of three phases:
+ * - Delay (optional)
+ * - Requesting the high-accuracy HFCLK
+ * - Hardware-supported calibration
+ *
+ * @param[in]  delay   Time after which the calibration will be started (in 0.25 s units).
+ * @param[in]  handler NULL or user function to be called when calibration is completed or aborted.
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     NRF_ERROR_FORBIDDEN                If a SoftDevice is present or the selected LFCLK source is not an RC oscillator.
+ * @retval     NRF_ERROR_INVALID_STATE            If the low-frequency clock is off.
+ * @retval     NRF_ERROR_BUSY                     If calibration is in progress.
+ */
+ret_code_t nrf_drv_clock_calibration_start(uint8_t delay, nrf_drv_clock_event_handler_t handler);
+
+/**
+ * @brief Function for aborting calibration.
+ *
+ * This function aborts on-going calibration. If calibration was started, it cannot be stopped. If a handler
+ * was provided by @ref nrf_drv_clock_calibration_start, this handler will be called once
+ * aborted calibration is completed. @ref nrf_drv_clock_is_calibrating can also be used to check
+ * if the system is calibrating.
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     NRF_ERROR_FORBIDDEN                If a SoftDevice is present or the selected LFCLK source is not an RC oscillator.
+ */
+ret_code_t nrf_drv_clock_calibration_abort(void);
+
+/**
+ * @brief Function for checking if calibration is in progress. 
+ *
+ * This function indicates that the system is
+ * in calibration if it is in any of the calibration process phases (see @ref nrf_drv_clock_calibration_start).
+ *
+ * @param[out] p_is_calibrating                   True if calibration is in progress, false if not.
+ *
+ * @retval     NRF_SUCCESS                        If the procedure was successful.
+ * @retval     NRF_ERROR_FORBIDDEN                If a SoftDevice is present or the selected LFCLK source is not an RC oscillator.
+ */
+ret_code_t nrf_drv_clock_is_calibrating(bool * p_is_calibrating);
+
+/**@brief Function for returning a requested task address for the clock driver module.
+ *
+ * @param[in]  task                               One of the peripheral tasks.
+ *
+ * @return     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task);
+
+/**@brief Function for returning a requested event address for the clock driver module.
+ *
+ * @param[in]  event                              One of the peripheral events.
+ *
+ * @return     Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event);
+
+/**
+ * @brief Function called by the SoftDevice handler if an @ref nrf_soc event is received from the SoftDevice.
+ */
+#ifdef SOFTDEVICE_PRESENT
+void nrf_drv_clock_on_soc_event(uint32_t evt_id);
+#endif
+/**
+ *@}
+ **/
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_task_addr(nrf_clock_task_t task)
+{
+    return nrf_clock_task_address_get(task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_clock_ppi_event_addr(nrf_clock_event_t event)
+{
+    return nrf_clock_event_address_get(event);
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+
+/*lint --flb "Leave library region" */
+#endif // NRF_CLOCK_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c
new file mode 100644
index 0000000000..43efd35e30
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.c
@@ -0,0 +1,235 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include <stddef.h>
+#include "nrf_drv_common.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_soc.h"
+#endif
+
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+typedef struct {
+    nrf_drv_irq_handler_t handler;
+    bool                  acquired;
+} shared_resource_t;
+
+// SPIM0, SPIS0, SPI0, TWIM0, TWIS0, TWI0
+#if (SPI0_ENABLED || SPIS0_ENABLED || TWI0_ENABLED || TWIS0_ENABLED)
+    #define SERIAL_BOX_0_IN_USE
+    // [this checking may need a different form in unit tests, hence macro]
+    #ifndef IS_SERIAL_BOX_0
+        #define IS_SERIAL_BOX_0(p_per_base)  (p_per_base == NRF_SPI0)
+    #endif
+
+    static shared_resource_t m_serial_box_0 = { .acquired = false };
+    void SPI0_TWI0_IRQHandler(void)
+    {
+        ASSERT(m_serial_box_0.handler);
+        m_serial_box_0.handler();
+    }
+#endif // (SPI0_ENABLED || SPIS0_ENABLED || TWI0_ENABLED || TWIS0_ENABLED)
+
+// SPIM1, SPIS1, SPI1, TWIM1, TWIS1, TWI1
+#if (SPI1_ENABLED || SPIS1_ENABLED || TWI1_ENABLED || TWIS1_ENABLED)
+    #define SERIAL_BOX_1_IN_USE
+    // [this checking may need a different form in unit tests, hence macro]
+    #ifndef IS_SERIAL_BOX_1
+        #define IS_SERIAL_BOX_1(p_per_base)  (p_per_base == NRF_SPI1)
+    #endif
+
+    static shared_resource_t m_serial_box_1 = { .acquired = false };
+    void SPI1_TWI1_IRQHandler(void)
+    {
+        ASSERT(m_serial_box_1.handler);
+        m_serial_box_1.handler();
+    }
+#endif // (SPI1_ENABLED || SPIS1_ENABLED || TWI1_ENABLED || TWIS1_ENABLED)
+
+// SPIM2, SPIS2, SPI2
+#if (SPI2_ENABLED || SPIS2_ENABLED)
+    #define SERIAL_BOX_2_IN_USE
+    // [this checking may need a different form in unit tests, hence macro]
+    #ifndef IS_SERIAL_BOX_2
+        #define IS_SERIAL_BOX_2(p_per_base)  (p_per_base == NRF_SPI2)
+    #endif
+
+    static shared_resource_t m_serial_box_2 = { .acquired = false };
+    void SPIM2_SPIS2_SPI2_IRQHandler(void)
+    {
+        ASSERT(m_serial_box_2.handler);
+        m_serial_box_2.handler();
+    }
+#endif // (SPI2_ENABLED || SPIS2_ENABLED)
+
+// COMP, LPCOMP
+#if (COMP_ENABLED || LPCOMP_ENABLED)
+	#define COMP_LPCOMP_IN_USE
+
+	#ifndef IS_COMP_LPCOMP
+		#define IS_COMP_LPCOMP(p_per_base)  ((p_per_base) == NRF_LPCOMP)
+	#endif
+
+    static shared_resource_t m_comp_lpcomp = { .acquired = false };
+    void LPCOMP_IRQHandler(void)
+    {
+    	ASSERT(m_comp_lpcomp.handler);
+    	m_comp_lpcomp.handler();
+    }
+#endif	// (COMP_ENABLED || LPCOMP_ENABLED)
+
+#if defined(SERIAL_BOX_0_IN_USE) || \
+    defined(SERIAL_BOX_1_IN_USE) || \
+    defined(SERIAL_BOX_2_IN_USE) || \
+	defined(COMP_LPCOMP_IN_USE)
+static ret_code_t acquire_shared_resource(shared_resource_t * p_resource,
+                                          nrf_drv_irq_handler_t handler)
+{
+    bool busy = false;
+
+    CRITICAL_REGION_ENTER();
+    if (p_resource->acquired)
+    {
+        busy = true;
+    }
+    else
+    {
+        p_resource->acquired = true;
+    }
+    CRITICAL_REGION_EXIT();
+
+    if (busy)
+    {
+        return NRF_ERROR_BUSY;
+    }
+
+    p_resource->handler = handler;
+    return NRF_SUCCESS;
+}
+#endif
+
+ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
+                                          nrf_drv_irq_handler_t handler)
+{
+#ifdef SERIAL_BOX_0_IN_USE
+    if (IS_SERIAL_BOX_0(p_per_base))
+    {
+        return acquire_shared_resource(&m_serial_box_0, handler);
+    }
+#endif
+
+#ifdef SERIAL_BOX_1_IN_USE
+    if (IS_SERIAL_BOX_1(p_per_base))
+    {
+        return acquire_shared_resource(&m_serial_box_1, handler);
+    }
+#endif
+
+#ifdef SERIAL_BOX_2_IN_USE
+    if (IS_SERIAL_BOX_2(p_per_base))
+    {
+        return acquire_shared_resource(&m_serial_box_2, handler);
+    }
+#endif
+
+#ifdef COMP_LPCOMP_IN_USE
+    if (IS_COMP_LPCOMP(p_per_base))
+    {
+    	return acquire_shared_resource(&m_comp_lpcomp, handler);
+    }
+#endif
+
+    return NRF_ERROR_INVALID_PARAM;
+}
+
+void nrf_drv_common_per_res_release(void const * p_per_base)
+{
+#ifdef SERIAL_BOX_0_IN_USE
+    if (IS_SERIAL_BOX_0(p_per_base))
+    {
+        m_serial_box_0.acquired = false;
+    }
+    else
+#endif
+
+#ifdef SERIAL_BOX_1_IN_USE
+    if (IS_SERIAL_BOX_1(p_per_base))
+    {
+        m_serial_box_1.acquired = false;
+    }
+    else
+#endif
+
+#ifdef SERIAL_BOX_2_IN_USE
+    if (IS_SERIAL_BOX_2(p_per_base))
+    {
+        m_serial_box_2.acquired = false;
+    }
+    else
+#endif
+
+#ifdef COMP_LPCOMP_IN_USE
+	if (IS_COMP_LPCOMP(p_per_base))
+    {
+        m_comp_lpcomp.acquired = false;
+    }
+	else
+#endif
+
+    {}
+}
+
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+
+void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority)
+{
+
+#ifdef SOFTDEVICE_PRESENT
+    ASSERT((priority == APP_IRQ_PRIORITY_LOW) || (priority == APP_IRQ_PRIORITY_HIGH));
+#endif
+
+    NVIC_SetPriority(IRQn, priority);
+    NVIC_ClearPendingIRQ(IRQn);
+    NVIC_EnableIRQ(IRQn);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.h
new file mode 100644
index 0000000000..1d211eaf9b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/common/nrf_drv_common.h
@@ -0,0 +1,221 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_COMMON_H__
+#define NRF_DRV_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "sdk_errors.h"
+#include "nrf_drv_config.h"
+
+
+/**
+ * @brief Offset of event registers in every peripheral instance
+ *
+ * This is the offset where event registers start in the every peripheral.
+ */
+#define NRF_DRV_COMMON_EVREGS_OFFSET 0x100U
+
+/**
+ * @brief Driver state.
+ */
+typedef enum 
+{ 
+	NRF_DRV_STATE_UNINITIALIZED, /**< Uninitialized. */
+	NRF_DRV_STATE_INITIALIZED, /**< Initialized but powered off. */
+	NRF_DRV_STATE_POWERED_ON
+} nrf_drv_state_t;
+
+/**
+ * @brief Driver power state selection.
+ */
+typedef enum
+{
+    NRF_DRV_PWR_CTRL_ON,   /**< Power on request. */
+    NRF_DRV_PWR_CTRL_OFF   /**< Power off request. */
+} nrf_drv_pwr_ctrl_t;
+
+/**
+ * @brief IRQ handler type.
+ */
+typedef void (*nrf_drv_irq_handler_t)(void);
+
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+/**
+ * @brief Function for acquiring shared peripheral resources associated with
+ *        the specified peripheral.
+ *
+ * Certain resources and registers are shared among peripherals that have
+ * the same ID (for example: SPI0, SPIM0, SPIS0, TWI0, TWIM0, and TWIS0).
+ * Only one of them can be utilized at a given time. This function reserves
+ * proper resources to be used by the specified peripheral.
+ * If PERIPHERAL_RESOURCE_SHARING_ENABLED is set to a non-zero value, IRQ
+ * handlers for peripherals that are sharing resources with others are
+ * implemented by the nrf_drv_common module instead of individual drivers.
+ * The drivers must then specify their interrupt handling routines and
+ * register them by using this function.
+ *
+ * @param[in] p_per_base Requested peripheral base pointer.
+ * @param[in] handler    Interrupt handler to register. May be NULL
+ *                       if interrupts are not used for the peripheral.
+ *
+ * @retval NRF_SUCCESS             If resources were acquired successfully.
+ * @retval NRF_ERROR_BUSY          If resources were already acquired.
+ * @retval NRF_ERROR_INVALID_PARAM If the specified peripheral is not enabled 
+ *                                 or the peripheral does not share resources 
+ *                                 with other peripherals.
+ */
+ret_code_t nrf_drv_common_per_res_acquire(void const * p_per_base,
+                                          nrf_drv_irq_handler_t handler);
+
+/**
+ * @brief Function for releasing shared resources reserved previously by
+ *        @ref nrf_drv_common_per_res_acquire() for the specified peripheral.
+ *
+ * @param[in] p_per_base Requested peripheral base pointer.
+ */
+void nrf_drv_common_per_res_release(void const * p_per_base);
+
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+
+/**
+ * @brief Function sets priority and enables NVIC interrupt
+ *
+ * @note Function checks if correct priority is used when softdevice is present
+ *
+ * @param[in] IRQn     Interrupt id
+ * @param[in] priority Interrupt priority
+ */
+void nrf_drv_common_irq_enable(IRQn_Type IRQn, uint8_t priority);
+
+/**
+ * @brief Function disables NVIC interrupt
+ *
+ * @param[in] IRQn     Interrupt id
+ */
+__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn);
+
+/**
+ * @brief Convert bit position to event code
+ *
+ * Function for converting the bit position in INTEN register to event code
+ * that is equivalent to the offset of the event register from the beginning
+ * of peripheral instance.
+ *
+ * For example the result of this function can be casted directly to
+ * the types like @ref nrf_twis_event_t or @ref nrf_rng_events_t...
+ *
+ * @param bit Bit position in INTEN register
+ * @return Event code to be casted to the right enum type or to be used in functions like
+ * @ref nrf_rng_event_get
+ *
+ * @sa nrf_drv_event_to_bitpos
+ */
+__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit);
+
+/**
+ * @brief Convert event code to bit position
+ *
+ * This function can be used to get bit position in INTEN register from event code.
+ *
+ * @param event Event code that may be casted from enum values from types like
+ * @ref nrf_twis_event_t or @ref nrf_rng_events_t
+ * @return Bit position in INTEN register that corresponds to the given code.
+ *
+ * @sa nrf_drv_bitpos_to_event
+ */
+__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event);
+
+/**
+ * @brief Get interrupt number connected with given instance
+ *
+ * Function returns interrupt number for a given instance of any peripheral.
+ * @param[in] pinst Pointer to peripheral registry
+ * @return Interrupt number
+ */
+__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst);
+
+/**
+ * @brief Check if given object is in RAM
+ *
+ * Function for analyzing if given location is placed in RAM.
+ * This function is used to determine if we have address that can be supported by EasyDMA.
+ * @param[in] ptr Pointer to the object
+ * @retval true  Object is located in RAM
+ * @retval false Object is not located in RAM
+ */
+__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_drv_common_irq_disable(IRQn_Type IRQn)
+{
+    NVIC_DisableIRQ(IRQn);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_bitpos_to_event(uint32_t bit)
+{
+    return NRF_DRV_COMMON_EVREGS_OFFSET + bit * sizeof(uint32_t);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_event_to_bitpos(uint32_t event)
+{
+    return (event - NRF_DRV_COMMON_EVREGS_OFFSET) / sizeof(uint32_t);
+}
+
+__STATIC_INLINE IRQn_Type nrf_drv_get_IRQn(void const * const pinst)
+{
+    uint8_t ret = (uint8_t)((uint32_t)pinst>>12U);
+    return (IRQn_Type) ret;
+}
+
+__STATIC_INLINE bool nrf_drv_is_in_RAM(void const * const ptr)
+{
+    return ((((uintptr_t)ptr) & 0xE0000000u) == 0x20000000u);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_DRV_COMMON_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/config/nrf_drv_config_validation.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/config/nrf_drv_config_validation.h
new file mode 100644
index 0000000000..aab66c7de2
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/config/nrf_drv_config_validation.h
@@ -0,0 +1,110 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_CONFIG_VALIDATION_H
+#define NRF_DRV_CONFIG_VALIDATION_H
+
+#ifdef NRF52
+
+#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((SPI0_ENABLED + SPIS0_ENABLED + TWI0_ENABLED + TWIS0_ENABLED) > 1)
+#error "Peripherals overlap. SPI0, SPIS0, TWI0, TWIS0 - only one of these can be enabled."
+#endif
+
+#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((SPI1_ENABLED + SPIS1_ENABLED + TWI1_ENABLED + TWIS1_ENABLED) > 1)
+#error "Peripherals overlap. SPI1, SPIS1, TWI1, TWIS1 - only one of these can be enabled."
+#endif
+
+#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((SPI2_ENABLED + SPIS2_ENABLED) > 1)
+#error "Peripherals overlap. SPI2, SPIS2 - only one of these can be enabled."
+#endif
+
+#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((COMP_ENABLED + LPCOMP_ENABLED) > 1)
+#error "COMP and LPCOMP cannot be enabled together. Peripherals overlap."
+#endif
+
+#else //NRF51
+
+#if (TWIS0_ENABLED + TWIS1_ENABLED) > 0
+#error "TWIS not present in nRF51."
+#endif
+
+#if SPIS0_ENABLED > 0
+#error "SPIS0 instance not present in nRF51."
+#endif 
+
+#if (SPI2_ENABLED + SPIS2_ENABLED) > 0
+#error "SPI2/SPIS2 instance not present in nRF51."
+#endif 
+
+#if RTC2_ENABLED
+#error "RTC2 not present in NRF51."
+#endif
+
+#if (TIMER3_ENABLED + TIMER4_ENABLED) > 0
+#error "TIMER3 and TIMER4 not present in nRF51."
+#endif
+
+#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((SPI0_ENABLED + TWI0_ENABLED) > 1)
+#error "Peripherals overlap. SPI0, TWI0 - only one of these can be enabled."
+#endif
+
+#if (!PERIPHERAL_RESOURCE_SHARING_ENABLED) && \
+    ((SPI1_ENABLED + SPIS1_ENABLED + TWI1_ENABLED) > 1)
+#error "Peripherals overlap. SPI1, SPIS1, TWI1 - only one of these can be enabled."
+#endif
+
+#if SAADC_ENABLED > 0
+#error "SAADC not present in nRF51."
+#endif
+
+#if I2S_ENABLED > 0
+#error "I2S not present in nRF51."
+#endif
+#if COMP_ENABLED > 0
+#error "COMP not present in nRF51."
+#endif
+
+#endif //NRF51
+
+#endif // NRF_DRV_CONFIG_VALIDATION_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.c
new file mode 100644
index 0000000000..28cfa1322e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.c
@@ -0,0 +1,53 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+#include <stdio.h> 
+#include "compiler_abstraction.h"
+#include "nrf.h"
+#include "nrf_delay.h"
+
+/*lint --e{438} "Variable not used" */
+void nrf_delay_ms(uint32_t volatile number_of_ms)
+{
+    while(number_of_ms != 0)
+    {
+        number_of_ms--;
+        nrf_delay_us(999);
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.h
new file mode 100644
index 0000000000..c68bd9a941
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/delay/nrf_delay.h
@@ -0,0 +1,242 @@
+#ifndef _NRF_DELAY_H
+#define _NRF_DELAY_H
+
+#include "nrf.h"
+
+/**
+ * @brief Function for delaying execution for number of microseconds.
+ *
+ * @note NRF52 has instruction cache and because of that delay is not precise.
+ *
+ * @param number_of_ms
+ */
+/*lint --e{438, 522} "Variable not used" "Function lacks side-effects" */
+#if defined ( __CC_ARM   )
+
+static __ASM void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+loop
+        SUBS    R0, R0, #1
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+#ifdef NRF52
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+        NOP
+#endif
+        BNE    loop
+        BX     LR
+}
+
+#elif defined ( __ICCARM__ )
+
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+__ASM (
+"loop:\n\t"
+       " SUBS R0, R0, #1\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+       " NOP\n\t"
+#ifdef NRF52
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+        " NOP\n\t"
+#endif
+       " BNE.n loop\n\t");
+}
+
+#elif defined ( _WIN32 ) || defined ( __unix ) || defined( __APPLE__ )
+
+__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us);
+
+#ifndef CUSTOM_NRF_DELAY_US
+__STATIC_INLINE void nrf_delay_us(uint32_t volatile number_of_us)
+{}
+#endif
+
+#elif defined ( __GNUC__ )
+
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us) __attribute__((always_inline));
+static void __INLINE nrf_delay_us(uint32_t volatile number_of_us)
+{
+register uint32_t delay __ASM ("r0") = number_of_us;
+__ASM volatile (
+#ifdef NRF51
+        ".syntax unified\n"
+#endif
+    "1:\n"
+    " SUBS %0, %0, #1\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"   
+    " NOP\n"  
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+#ifdef NRF52
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+    " NOP\n"
+#endif
+    " BNE 1b\n"
+#ifdef NRF51
+    ".syntax divided\n"
+#endif
+    : "+r" (delay));
+}
+#endif
+
+void nrf_delay_ms(uint32_t volatile number_of_ms);
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c
new file mode 100644
index 0000000000..752c89c9a7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.c
@@ -0,0 +1,607 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_gpiote.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "nrf_assert.h"
+
+#define FORBIDDEN_HANDLER_ADDRESS ((nrf_drv_gpiote_evt_handler_t)UINT32_MAX)
+#define PIN_NOT_USED              (-1)
+#define PIN_USED                  (-2)
+#define NO_CHANNELS               (-1)
+#define SENSE_FIELD_POS           (6)
+#define SENSE_FIELD_MASK          (0xC0)
+
+/**
+ * @brief Macro for conveting task-event index to an address of an event register.
+ *
+ * Macro utilizes the fact that registers are grouped together in ascending order.
+ */
+#define TE_IDX_TO_EVENT_ADDR(idx)   (nrf_gpiote_events_t)((uint32_t)NRF_GPIOTE_EVENTS_IN_0+(sizeof(uint32_t)*(idx)))
+
+/**
+ * @brief Macro for conveting task-event index to an address of a task register.
+ *
+ * Macro utilizes the fact that registers are grouped together in ascending order.
+ */
+#define TE_IDX_TO_TASK_ADDR(idx)   (nrf_gpiote_tasks_t)((uint32_t)NRF_GPIOTE_TASKS_OUT_0+(sizeof(uint32_t)*(idx)))
+
+//lint -save -e661
+typedef struct
+{
+    nrf_drv_gpiote_evt_handler_t handlers[NUMBER_OF_GPIO_TE+GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS];
+    int8_t                       pin_assignments[NUMBER_OF_PINS];
+    int8_t                       port_handlers_pins[GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS];
+    nrf_drv_state_t              state;
+} gpiote_control_block_t;
+
+static gpiote_control_block_t m_cb;
+
+__STATIC_INLINE bool pin_in_use(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] != PIN_NOT_USED);
+}
+
+__STATIC_INLINE bool pin_in_use_as_non_task_out(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] == PIN_USED);
+}
+
+__STATIC_INLINE bool pin_in_use_by_te(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] >= 0 && m_cb.pin_assignments[pin] < NUMBER_OF_GPIO_TE) ? true : false;
+}
+
+__STATIC_INLINE bool pin_in_use_by_port(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] >= NUMBER_OF_GPIO_TE);
+}
+
+__STATIC_INLINE bool pin_in_use_by_gpiote(uint32_t pin)
+{
+    return (m_cb.pin_assignments[pin] >= 0);
+}
+
+__STATIC_INLINE void pin_in_use_by_te_set(uint32_t pin,
+                                          uint32_t channel_id,
+                                          nrf_drv_gpiote_evt_handler_t handler,
+                                          bool is_channel)
+{
+    m_cb.pin_assignments[pin] = channel_id;
+    m_cb.handlers[channel_id] = handler;
+    if (!is_channel)
+    {
+        m_cb.port_handlers_pins[channel_id-NUMBER_OF_GPIO_TE] = (int8_t)pin;
+    }
+}
+
+__STATIC_INLINE void pin_in_use_set(uint32_t pin)
+{
+    m_cb.pin_assignments[pin] = PIN_USED;
+}
+
+__STATIC_INLINE void pin_in_use_clear(uint32_t pin)
+{
+    m_cb.pin_assignments[pin] = PIN_NOT_USED;
+}
+
+__STATIC_INLINE int8_t channel_port_get(uint32_t pin)
+{
+    return m_cb.pin_assignments[pin];
+}
+
+__STATIC_INLINE nrf_drv_gpiote_evt_handler_t channel_handler_get(uint32_t channel)
+{
+    return m_cb.handlers[channel];
+}
+
+static int8_t channel_port_alloc(uint32_t pin,nrf_drv_gpiote_evt_handler_t handler, bool channel)
+{
+    int8_t channel_id = NO_CHANNELS;
+    uint32_t i;
+
+    uint32_t start_idx = channel ? 0 : NUMBER_OF_GPIO_TE;
+    uint32_t end_idx = channel ? NUMBER_OF_GPIO_TE : (NUMBER_OF_GPIO_TE+GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS);
+    //critical section
+
+    for (i = start_idx; i < end_idx; i++)
+    {
+        if (m_cb.handlers[i] == FORBIDDEN_HANDLER_ADDRESS)
+        {
+            pin_in_use_by_te_set(pin, i, handler, channel);
+            channel_id = i;
+            break;
+        }
+    }
+    //critical section
+    return channel_id;
+}
+
+static void channel_free(uint8_t channel_id)
+{
+    m_cb.handlers[channel_id] = FORBIDDEN_HANDLER_ADDRESS;
+    if (channel_id >= NUMBER_OF_GPIO_TE)
+    {
+        m_cb.port_handlers_pins[channel_id-NUMBER_OF_GPIO_TE] = (int8_t)PIN_NOT_USED;
+    }
+}
+
+ret_code_t nrf_drv_gpiote_init(void)
+{
+    if (m_cb.state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    uint8_t i;
+    for (i = 0; i < NUMBER_OF_PINS; i++)
+    {
+        pin_in_use_clear(i);
+    }
+    for (i = 0; i < (NUMBER_OF_GPIO_TE+GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS); i++)
+    {
+        channel_free(i);
+    }
+
+    nrf_drv_common_irq_enable(GPIOTE_IRQn, GPIOTE_CONFIG_IRQ_PRIORITY);
+    nrf_gpiote_int_enable(GPIOTE_INTENSET_PORT_Msk);
+    m_cb.state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+bool nrf_drv_gpiote_is_init(void)
+{
+    return (m_cb.state != NRF_DRV_STATE_UNINITIALIZED) ? true : false;
+}
+
+void nrf_drv_gpiote_uninit(void)
+{
+    ASSERT(m_cb.state!=NRF_DRV_STATE_UNINITIALIZED);
+
+    uint32_t i;
+    for (i = 0; i < NUMBER_OF_PINS; i++)
+    {
+        if (pin_in_use_as_non_task_out(i))
+        {
+            nrf_drv_gpiote_out_uninit(i);
+        }
+        else if( pin_in_use_by_gpiote(i))
+        {
+            /* Disable gpiote_in is having the same effect on out pin as gpiote_out_uninit on
+             * so it can be called on all pins used by GPIOTE.
+             */
+            nrf_drv_gpiote_in_uninit(i);
+        }
+    }
+    m_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+ret_code_t nrf_drv_gpiote_out_init(nrf_drv_gpiote_pin_t pin, 
+                                   nrf_drv_gpiote_out_config_t const * p_config)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(m_cb.state == NRF_DRV_STATE_INITIALIZED);
+    ASSERT(p_config);
+
+    ret_code_t result = NRF_SUCCESS;
+
+    if (pin_in_use(pin))
+    {
+        result = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        if (p_config->task_pin)
+        {
+            int8_t channel = channel_port_alloc(pin, NULL, true);
+
+            if (channel != NO_CHANNELS)
+            {
+                nrf_gpiote_task_configure(channel, pin, p_config->action, p_config->init_state);
+            }
+            else
+            {
+                result = NRF_ERROR_NO_MEM;
+            }
+        }
+        else
+        {
+            pin_in_use_set(pin);
+        }
+
+        if (result == NRF_SUCCESS)
+        {
+            if (p_config->init_state == NRF_GPIOTE_INITIAL_VALUE_HIGH)
+            {
+                nrf_gpio_pin_set(pin);
+            }
+            else
+            {
+                nrf_gpio_pin_clear(pin);
+            }
+            
+            nrf_gpio_cfg_output(pin);
+        }
+    }
+
+    return result;
+}
+
+void nrf_drv_gpiote_out_uninit(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+
+    if (pin_in_use_by_te(pin))
+    {
+        channel_free((uint8_t)channel_port_get(pin));
+        nrf_gpiote_te_default(channel_port_get(pin));
+    }
+    pin_in_use_clear(pin);
+
+    nrf_gpio_cfg_default(pin);
+}
+
+void nrf_drv_gpiote_out_set(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(!pin_in_use_by_te(pin))
+
+    nrf_gpio_pin_set(pin);
+}
+
+void nrf_drv_gpiote_out_clear(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(!pin_in_use_by_te(pin))
+
+    nrf_gpio_pin_clear(pin);
+}
+
+void nrf_drv_gpiote_out_toggle(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(!pin_in_use_by_te(pin))
+
+    nrf_gpio_pin_toggle(pin);
+}
+
+void nrf_drv_gpiote_out_task_enable(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin))
+
+    nrf_gpiote_task_enable(m_cb.pin_assignments[pin]);
+}
+
+void nrf_drv_gpiote_out_task_disable(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin))
+
+    nrf_gpiote_task_disable(m_cb.pin_assignments[pin]);
+}
+
+uint32_t nrf_drv_gpiote_out_task_addr_get(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_te(pin));
+    
+    nrf_gpiote_tasks_t task = TE_IDX_TO_TASK_ADDR(channel_port_get(pin));
+    return nrf_gpiote_task_addr_get(task);
+}
+
+void nrf_drv_gpiote_out_task_force(nrf_drv_gpiote_pin_t pin, uint8_t state)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin));
+    
+    nrf_gpiote_outinit_t init_val = state ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW;
+    nrf_gpiote_task_force(m_cb.pin_assignments[pin], init_val);
+}
+
+void nrf_drv_gpiote_out_task_trigger(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use(pin));
+    ASSERT(pin_in_use_by_te(pin));
+
+    nrf_gpiote_tasks_t task = TE_IDX_TO_TASK_ADDR(channel_port_get(pin));;
+    nrf_gpiote_task_set(task);
+}
+
+ret_code_t nrf_drv_gpiote_in_init(nrf_drv_gpiote_pin_t pin,
+                                  nrf_drv_gpiote_in_config_t const * p_config,
+                                  nrf_drv_gpiote_evt_handler_t evt_handler)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ret_code_t result = NRF_SUCCESS;
+    /* Only one GPIOTE channel can be assigned to one physical pin. */
+    if (pin_in_use_by_gpiote(pin))
+    {
+        result = NRF_ERROR_INVALID_STATE;
+    }
+    else
+    {
+        int8_t channel = channel_port_alloc(pin, evt_handler, p_config->hi_accuracy);
+        if (channel != NO_CHANNELS)
+        {
+            if (p_config->is_watcher)
+            {
+                nrf_gpio_cfg_watcher(pin);
+            }
+            else
+            {
+                nrf_gpio_cfg_input(pin,p_config->pull);
+            }
+
+            if (p_config->hi_accuracy)
+            {
+                nrf_gpiote_event_configure(channel, pin,p_config->sense);
+            }
+            else
+            {
+                m_cb.port_handlers_pins[channel-NUMBER_OF_GPIO_TE] |= (p_config->sense)<< SENSE_FIELD_POS;
+            }
+        }
+        else
+        {
+            result = NRF_ERROR_NO_MEM;
+        }
+    }
+    return result;
+}
+
+void nrf_drv_gpiote_in_event_enable(nrf_drv_gpiote_pin_t pin, bool int_enable)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_gpiote(pin));
+    if (pin_in_use_by_port(pin))
+    {
+        uint8_t pin_and_sense = m_cb.port_handlers_pins[channel_port_get(pin)-NUMBER_OF_GPIO_TE];
+        nrf_gpiote_polarity_t polarity = (nrf_gpiote_polarity_t)(pin_and_sense >> SENSE_FIELD_POS);
+        nrf_gpio_pin_sense_t sense;
+        if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+        {
+            /* read current pin state and set for next sense to oposit */
+            sense = (nrf_gpio_pins_read() & (1 << pin)) ?
+                    NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
+        }
+        else
+        {
+            sense = (polarity == NRF_GPIOTE_POLARITY_LOTOHI) ?
+                    NRF_GPIO_PIN_SENSE_HIGH : NRF_GPIO_PIN_SENSE_LOW;
+        }
+        nrf_gpio_cfg_sense_set(pin,sense);
+    }
+    else if(pin_in_use_by_te(pin))
+    {
+        int32_t channel = (int32_t)channel_port_get(pin);
+        nrf_gpiote_events_t event = TE_IDX_TO_EVENT_ADDR(channel);
+       
+        nrf_gpiote_event_enable(channel);
+
+        nrf_gpiote_event_clear(event);
+        if (int_enable)
+        {
+            nrf_drv_gpiote_evt_handler_t handler = channel_handler_get(channel_port_get(pin));
+            // Enable the interrupt only if event handler was provided.
+            if (handler)
+            {
+                nrf_gpiote_int_enable(1 << channel);
+            }
+        }
+    }
+}
+
+void nrf_drv_gpiote_in_event_disable(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_gpiote(pin));
+    if (pin_in_use_by_port(pin))
+    {
+        nrf_gpio_cfg_sense_set(pin,NRF_GPIO_PIN_NOSENSE);
+    }
+    else if(pin_in_use_by_te(pin))
+    {
+        int32_t channel = (int32_t)channel_port_get(pin);
+        nrf_gpiote_event_disable(channel);
+        nrf_gpiote_int_disable(1 << channel);
+    }
+}
+
+void nrf_drv_gpiote_in_uninit(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_gpiote(pin));
+    nrf_drv_gpiote_in_event_disable(pin);
+    if(pin_in_use_by_te(pin))
+    {
+        nrf_gpiote_te_default(channel_port_get(pin));
+    }
+    nrf_gpio_cfg_default(pin);
+    channel_free((uint8_t)channel_port_get(pin));
+    pin_in_use_clear(pin);
+}
+
+bool nrf_drv_gpiote_in_is_set(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    return nrf_gpio_pin_read(pin) ? true : false;
+}
+
+uint32_t nrf_drv_gpiote_in_event_addr_get(nrf_drv_gpiote_pin_t pin)
+{
+    ASSERT(pin < NUMBER_OF_PINS);
+    ASSERT(pin_in_use_by_te(pin));
+    
+    nrf_gpiote_events_t event = TE_IDX_TO_EVENT_ADDR(channel_port_get(pin));
+    return nrf_gpiote_event_addr_get(event);
+}
+
+void GPIOTE_IRQHandler(void)
+{
+    uint32_t status = 0;
+    uint32_t input = 0;
+
+    /* collect status of all GPIOTE pin events. Processing is done once all are collected and cleared.*/
+    uint32_t i;
+    nrf_gpiote_events_t event = NRF_GPIOTE_EVENTS_IN_0;
+    uint32_t mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
+    for (i = 0; i < NUMBER_OF_GPIO_TE; i++)
+    {
+        if (nrf_gpiote_event_is_set(event) && nrf_gpiote_int_is_enabled(mask))
+        {
+            nrf_gpiote_event_clear(event);
+            status |= mask;
+        }
+        mask <<= 1;
+        /* Incrementing to next event, utilizing the fact that events are grouped together
+         * in ascending order. */
+        event = (nrf_gpiote_events_t)((uint32_t)event + sizeof(uint32_t));
+    }
+
+    /* collect PORT status event, if event is set read pins state. Processing is postponed to the
+     * end of interrupt. */
+    if (nrf_gpiote_event_is_set(NRF_GPIOTE_EVENTS_PORT))
+    {
+        nrf_gpiote_event_clear(NRF_GPIOTE_EVENTS_PORT);
+        status |= (uint32_t)NRF_GPIOTE_INT_PORT_MASK;
+        input = nrf_gpio_pins_read();
+    }
+
+    /* Process pin events. */
+    if (status & NRF_GPIOTE_INT_IN_MASK)
+    {
+        mask = (uint32_t)NRF_GPIOTE_INT_IN0_MASK;
+        for (i = 0; i < NUMBER_OF_GPIO_TE; i++)
+        {
+            if (mask & status)
+            {
+                nrf_drv_gpiote_pin_t pin = nrf_gpiote_event_pin_get(i);
+                nrf_gpiote_polarity_t polarity = nrf_gpiote_event_polarity_get(i);
+                nrf_drv_gpiote_evt_handler_t handler = channel_handler_get(i);
+                handler(pin,polarity);
+            }
+            mask <<= 1;
+        }
+    }
+
+    if (status & (uint32_t)NRF_GPIOTE_INT_PORT_MASK)
+    {
+        /* Process port event. */
+        uint8_t repeat = 0;
+        uint32_t toggle_mask = 0;
+        uint32_t pins_to_check = 0xFFFFFFFFuL;
+
+        do
+        {
+            repeat = 0;
+            for (i = 0; i < GPIOTE_CONFIG_NUM_OF_LOW_POWER_EVENTS; i++)
+            {
+                uint8_t pin_and_sense = m_cb.port_handlers_pins[i];
+                nrf_drv_gpiote_pin_t pin = (pin_and_sense & ~SENSE_FIELD_MASK);
+
+                if ((m_cb.port_handlers_pins[i] != PIN_NOT_USED)
+                    && ((1UL << pin) & pins_to_check))
+                {
+                    nrf_gpiote_polarity_t polarity =
+                                (nrf_gpiote_polarity_t)((pin_and_sense & SENSE_FIELD_MASK) >> SENSE_FIELD_POS);
+                    nrf_drv_gpiote_evt_handler_t handler = channel_handler_get(channel_port_get(pin));
+                    if (handler || polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+                    {
+                        mask = 1 << pin;
+                        if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+                        {
+                            toggle_mask |= mask;
+                        }
+                        nrf_gpio_pin_sense_t sense = nrf_gpio_pin_sense_get(pin);
+
+                        if (((mask & input) && (sense==NRF_GPIO_PIN_SENSE_HIGH)) ||
+                           (!(mask & input) && (sense==NRF_GPIO_PIN_SENSE_LOW))  )
+                        {
+                            if (polarity == NRF_GPIOTE_POLARITY_TOGGLE)
+                            {
+                                nrf_gpio_pin_sense_t next_sense = (sense == NRF_GPIO_PIN_SENSE_HIGH) ?
+                                        NRF_GPIO_PIN_SENSE_LOW : NRF_GPIO_PIN_SENSE_HIGH;
+                                nrf_gpio_cfg_sense_set(pin, next_sense);
+                                ++repeat;
+                            }
+                            if (handler)
+                            {
+                                handler(pin, polarity);
+                            }
+                        }
+                    }
+                }
+            }
+
+            if (repeat)
+            {
+                // When one of the pins in low-accuracy and toggle mode becomes active,
+                // it's sense mode is inverted to clear the internal SENSE signal.
+                // State of any other enabled low-accuracy input in toggle mode must be checked
+                // explicitly, because it does not trigger the interrput when SENSE signal is active.
+                // For more information about SENSE functionality, refer to Product Specification.
+                uint32_t new_input = nrf_gpio_pins_read();
+                if (new_input == input)
+                {
+                    //No change.
+                    repeat = 0;
+                }
+                else
+                {
+                    input = new_input;
+                    pins_to_check = toggle_mask;
+                }
+            }
+        }
+        while (repeat);
+    }
+}
+//lint -restore
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h
new file mode 100644
index 0000000000..2af99b056e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/gpiote/nrf_drv_gpiote.h
@@ -0,0 +1,336 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_GPIOTE__
+#define NRF_DRV_GPIOTE__
+
+/**
+ * @addtogroup nrf_gpiote GPIOTE abstraction and driver
+ * @ingroup nrf_drivers
+ * @brief GPIOTE APIs.
+ * @defgroup nrf_drv_gpiote GPIOTE driver
+ * @{
+ * @ingroup nrf_gpiote
+ * @brief GPIOTE driver for managing input and output pins.
+ */
+
+#include "nrf_gpiote.h"
+#include "nrf_gpio.h"
+#include "nrf_drv_config.h"
+#include "sdk_errors.h"
+#include <stdint.h>
+#include <stdbool.h>
+
+/**@brief Input pin configuration. */
+typedef struct
+{
+    nrf_gpiote_polarity_t sense;      /**< Transition that triggers interrupt. */
+    nrf_gpio_pin_pull_t   pull;       /**< Pulling mode. */
+    bool                  is_watcher; /**< True when the input pin is tracking an output pin. */
+    bool                  hi_accuracy;/**< True when high accuracy (IN_EVENT) is used. */
+} nrf_drv_gpiote_in_config_t;
+
+/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect low-to-high transition.
+ * @details Set hi_accu to true to use IN_EVENT. */
+#define GPIOTE_CONFIG_IN_SENSE_LOTOHI(hi_accu)     \
+    {                                            \
+        .is_watcher = false,                     \
+        .hi_accuracy = hi_accu,                  \
+        .pull = NRF_GPIO_PIN_NOPULL,             \
+        .sense = NRF_GPIOTE_POLARITY_LOTOHI,     \
+    }
+
+/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect high-to-low transition.
+ * @details Set hi_accu to true to use IN_EVENT. */
+#define GPIOTE_CONFIG_IN_SENSE_HITOLO(hi_accu)      \
+    {                                            \
+        .is_watcher = false,                     \
+        .hi_accuracy = hi_accu,                  \
+        .pull = NRF_GPIO_PIN_NOPULL,             \
+        .sense = NRF_GPIOTE_POLARITY_HITOLO,     \
+    }
+
+/**@brief Macro for configuring a pin to use a GPIO IN or PORT EVENT to detect any change on the pin.
+ * @details Set hi_accu to true to use IN_EVENT.*/
+#define GPIOTE_CONFIG_IN_SENSE_TOGGLE(hi_accu)   \
+    {                                            \
+        .is_watcher = false,                     \
+        .hi_accuracy = hi_accu,                  \
+        .pull = NRF_GPIO_PIN_NOPULL,             \
+        .sense = NRF_GPIOTE_POLARITY_TOGGLE,     \
+    }
+
+/**@brief Output pin configuration. */
+typedef struct
+{
+    nrf_gpiote_polarity_t action;    /**< Configuration of the pin task. */
+    nrf_gpiote_outinit_t  init_state; /**< Initial state of the output pin. */
+    bool                  task_pin;  /**< True if the pin is controlled by a GPIOTE task. */
+} nrf_drv_gpiote_out_config_t;
+
+/**@brief Macro for configuring a pin to use as output. GPIOTE is not used for the pin. */
+#define GPIOTE_CONFIG_OUT_SIMPLE(init_high)                                                        \
+    {                                                                                              \
+        .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW,    \
+        .task_pin = false,                                                                         \
+    }
+
+/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from high to low.
+ * @details The task will clear the pin. Therefore, the pin is set initially.  */
+#define GPIOTE_CONFIG_OUT_TASK_LOW                                                                 \
+    {                                                                                              \
+        .init_state = NRF_GPIOTE_INITIAL_VALUE_HIGH,                                               \
+        .task_pin   = true,                                                                        \
+        .action     = NRF_GPIOTE_POLARITY_HITOLO,                                                  \
+    }
+
+/**@brief Macro for configuring a pin to use the GPIO OUT TASK to change the state from low to high.
+ * @details The task will set the pin. Therefore, the pin is cleared initially.  */
+#define GPIOTE_CONFIG_OUT_TASK_HIGH                                                                \
+    {                                                                                              \
+        .init_state = NRF_GPIOTE_INITIAL_VALUE_LOW,                                                \
+        .task_pin   = true,                                                                        \
+        .action     = NRF_GPIOTE_POLARITY_LOTOHI,                                                  \
+    }
+
+/**@brief Macro for configuring a pin to use the GPIO OUT TASK to toggle the pin state.
+ * @details The initial pin state must be provided.  */
+#define GPIOTE_CONFIG_OUT_TASK_TOGGLE(init_high)                                                   \
+    {                                                                                              \
+        .init_state = init_high ? NRF_GPIOTE_INITIAL_VALUE_HIGH : NRF_GPIOTE_INITIAL_VALUE_LOW,    \
+        .task_pin   = true,                                                                        \
+        .action     = NRF_GPIOTE_POLARITY_TOGGLE,                                                  \
+    }
+
+/** @brief Pin. */
+typedef uint32_t nrf_drv_gpiote_pin_t;
+
+/**
+ * @brief Pin event handler prototype.
+ * @param pin    Pin that triggered this event.
+ * @param action Action that lead to triggering this event.
+ */
+typedef void (*nrf_drv_gpiote_evt_handler_t)(nrf_drv_gpiote_pin_t pin, nrf_gpiote_polarity_t action);
+
+/**
+ * @brief Function for initializing the GPIOTE module.
+ *
+ * @details Only static configuration is supported to prevent the shared 
+ * resource being customized by the initiator.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ */
+ret_code_t nrf_drv_gpiote_init(void);
+
+/**
+ * @brief Function for checking if the GPIOTE module is initialized.
+ *
+ * @details The GPIOTE module is a shared module. Therefore, you should check if
+ * the module is already initialized and skip initialization if it is.
+ *
+ * @retval    true  If the module is already initialized.
+ * @retval    false If the module is not initialized.
+ */
+bool nrf_drv_gpiote_is_init(void);
+
+/**
+ * @brief Function for uninitializing the GPIOTE module.
+ */
+void nrf_drv_gpiote_uninit(void);
+
+/**
+ * @brief Function for initializing a GPIOTE output pin.
+ * @details The output pin can be controlled by the CPU or by PPI. The initial 
+ * configuration specifies which mode is used. If PPI mode is used, the driver 
+ * attempts to allocate one of the available GPIOTE channels. If no channel is
+ * available, an error is returned.
+ *
+ * @param[in] pin       Pin.
+ * @param[in] p_config  Initial configuration.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used.
+ * @retval NRF_ERROR_NO_MEM        If no GPIOTE channel is available.
+ */
+ret_code_t nrf_drv_gpiote_out_init(nrf_drv_gpiote_pin_t pin,
+                                   nrf_drv_gpiote_out_config_t const * p_config);
+
+/**
+ * @brief Function for uninitializing a GPIOTE output pin.
+ * @details The driver frees the GPIOTE channel if the output pin was using one.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_uninit(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for setting a GPIOTE output pin.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_set(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for clearing a GPIOTE output pin.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_clear(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for toggling a GPIOTE output pin.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_toggle(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for enabling a GPIOTE output pin task.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_task_enable(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for disabling a GPIOTE output pin task.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_task_disable(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for getting the address of a configurable GPIOTE task.
+ *
+ * @param[in] pin       Pin. 
+ */
+uint32_t nrf_drv_gpiote_out_task_addr_get(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for initializing a GPIOTE input pin.
+ * @details The input pin can act in two ways: 
+ * - lower accuracy but low power (high frequency clock not needed)
+ * - higher accuracy (high frequency clock required)
+ *
+ * The initial configuration specifies which mode is used.
+ * If high-accuracy mode is used, the driver attempts to allocate one 
+ * of the available GPIOTE channels. If no channel is 
+ * available, an error is returned.
+ * In low accuracy mode SENSE feature is used. In this case only one active pin
+ * can be detected at a time. It can be worked around by setting all of the used
+ * low accuracy pins to toggle mode.
+ * For more information about SENSE functionality, refer to Product Specification.
+ *
+ * @param[in] pin       Pin. 
+ * @param[in] p_config    Initial configuration. 
+ * @param[in] evt_handler User function to be called when the configured transition occurs. 
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is not initialized or the pin is already used.
+ * @retval NRF_ERROR_NO_MEM        If no GPIOTE channel is available.
+ */
+ret_code_t nrf_drv_gpiote_in_init(nrf_drv_gpiote_pin_t pin, 
+                                  nrf_drv_gpiote_in_config_t const * p_config,
+                                  nrf_drv_gpiote_evt_handler_t evt_handler);
+
+/**
+ * @brief Function for uninitializing a GPIOTE input pin.
+ * @details The driver frees the GPIOTE channel if the input pin was using one.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_in_uninit(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for enabling sensing of a GPIOTE input pin.
+ *
+ * @details If the input pin is configured as high-accuracy pin, the function 
+ * enables an IN_EVENT. Otherwise, the function enables the GPIO sense mechanism.
+ * Note that a PORT event is shared between multiple pins, therefore the 
+ * interrupt is always enabled.
+ *
+ * @param[in] pin       Pin. 
+ * @param[in] int_enable  True to enable the interrupt. Always valid for a high-accuracy pin.
+ */
+void nrf_drv_gpiote_in_event_enable(nrf_drv_gpiote_pin_t pin, bool int_enable);
+
+/**
+ * @brief Function for disabling a GPIOTE input pin.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_in_event_disable(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for checking if a GPIOTE input pin is set.
+ *
+ * @param[in] pin       Pin. 
+ * @retval    true If the input pin is set.
+ * @retval    false If the input pin is not set.
+ */
+bool nrf_drv_gpiote_in_is_set(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for getting the address of a GPIOTE input pin event.
+ * @details If the pin is configured to use low-accuracy mode, the address of the PORT event is returned.
+ *
+ * @param[in] pin       Pin. 
+ */
+uint32_t nrf_drv_gpiote_in_event_addr_get(nrf_drv_gpiote_pin_t pin);
+
+/**
+ * @brief Function for forcing a specific state on the pin configured as task.
+ *
+ * @param[in] pin       Pin. 
+ * @param[in] state     Pin state.
+ */
+void nrf_drv_gpiote_out_task_force(nrf_drv_gpiote_pin_t pin, uint8_t state);
+
+/**
+ * @brief Function for triggering the task manually.
+ *
+ * @param[in] pin       Pin. 
+ */
+void nrf_drv_gpiote_out_task_trigger(nrf_drv_gpiote_pin_t pin);
+
+/**
+ *@}
+ **/
+
+#endif //NRF_DRV_GPIOTE__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.c
new file mode 100644
index 0000000000..188ac506c8
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.c
@@ -0,0 +1,105 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file
+ * @brief ADC HAL implementation
+ */
+
+#include "nrf_adc.h"
+
+#ifndef NRF52
+
+/**
+ * @brief Function for configuring ADC.
+ *
+ * This function powers on ADC and configures it. ADC is in DISABLE state after configuration,
+ * so it should be enabled before using it.
+ *
+ * @param[in] config  Requested configuration.
+ */
+void nrf_adc_configure(nrf_adc_config_t * config)
+{
+    uint32_t config_reg = 0;
+
+    config_reg |= ((uint32_t)config->resolution << ADC_CONFIG_RES_Pos) & ADC_CONFIG_RES_Msk;
+    config_reg |= ((uint32_t)config->scaling << ADC_CONFIG_INPSEL_Pos) & ADC_CONFIG_INPSEL_Msk;
+    config_reg |= ((uint32_t)config->reference << ADC_CONFIG_REFSEL_Pos) & ADC_CONFIG_REFSEL_Msk;
+
+    if (config->reference & ADC_CONFIG_EXTREFSEL_Msk)
+    {
+        config_reg |= config->reference & ADC_CONFIG_EXTREFSEL_Msk;
+    }
+
+    /* select input */
+    nrf_adc_input_select(NRF_ADC_CONFIG_INPUT_DISABLED);
+
+    /* set new configuration keeping selected input */
+    NRF_ADC->CONFIG = config_reg | (NRF_ADC->CONFIG & ADC_CONFIG_PSEL_Msk);
+}
+
+
+/**
+ * @brief Blocking function for executing single ADC conversion.
+ *
+ * This function selects the desired input, starts a single conversion,
+ * waits for it to finish, and returns the result.
+ * ADC is left in STOP state, the given input is selected.
+ * This function does not check if ADC is initialized and powered.
+ *
+ * @param[in] input Requested input to be selected.
+ *
+ * @return Conversion result
+ */
+int32_t nrf_adc_convert_single(nrf_adc_config_input_t input)
+{
+    int32_t val;
+
+    nrf_adc_input_select(input);
+    nrf_adc_start();
+
+    while (!nrf_adc_conversion_finished())
+    {
+    }
+    nrf_adc_conversion_event_clean();
+    val = nrf_adc_result_get();
+    nrf_adc_stop();
+    return val;
+}
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.h
new file mode 100644
index 0000000000..ea4e094cfa
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_adc.h
@@ -0,0 +1,443 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_ADC_H_
+#define NRF_ADC_H_
+
+/**
+ * @defgroup nrf_adc_hal ADC HAL
+ * @{
+ * @ingroup nrf_adc
+ * @brief @tagAPI51 Hardware access layer for managing the analog-to-digital converter (ADC).
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+
+#include "nrf.h"
+
+#ifndef NRF52
+/**
+ * @enum  nrf_adc_config_resolution_t
+ * @brief Resolution of the analog-to-digital converter.
+ */
+
+/**
+ * @brief ADC interrupts.
+ */
+typedef enum
+{
+    NRF_ADC_INT_END_MASK  = ADC_INTENSET_END_Msk,   /**< ADC interrupt on END event. */
+} nrf_adc_int_mask_t;
+
+typedef enum
+{
+    NRF_ADC_CONFIG_RES_8BIT  = ADC_CONFIG_RES_8bit,  /**< 8 bit resolution. */
+    NRF_ADC_CONFIG_RES_9BIT  = ADC_CONFIG_RES_9bit,  /**< 9 bit resolution. */
+    NRF_ADC_CONFIG_RES_10BIT = ADC_CONFIG_RES_10bit, /**< 10 bit resolution. */
+} nrf_adc_config_resolution_t;
+
+
+/**
+ * @enum nrf_adc_config_scaling_t
+ * @brief Scaling factor of the analog-to-digital conversion.
+ */
+typedef enum
+{
+    NRF_ADC_CONFIG_SCALING_INPUT_FULL_SCALE  = ADC_CONFIG_INPSEL_AnalogInputNoPrescaling,        /**< Full scale input. */
+    NRF_ADC_CONFIG_SCALING_INPUT_TWO_THIRDS  = ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling, /**< 2/3 scale input. */
+    NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD   = ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling,  /**< 1/3 scale input. */
+    NRF_ADC_CONFIG_SCALING_SUPPLY_TWO_THIRDS = ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling,      /**< 2/3 of supply. */
+    NRF_ADC_CONFIG_SCALING_SUPPLY_ONE_THIRD  = ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling        /**< 1/3 of supply. */
+} nrf_adc_config_scaling_t;
+
+/**
+ * @enum nrf_adc_config_reference_t
+ * @brief Reference selection of the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_ADC_CONFIG_REF_VBG              = ADC_CONFIG_REFSEL_VBG,                      /**< 1.2 V reference. */
+    NRF_ADC_CONFIG_REF_SUPPLY_ONE_HALF  = ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling,  /**< 1/2 of power supply. */
+    NRF_ADC_CONFIG_REF_SUPPLY_ONE_THIRD = ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling, /**< 1/3 of power supply. */
+    NRF_ADC_CONFIG_REF_EXT_REF0         = ADC_CONFIG_REFSEL_External |
+                                          ADC_CONFIG_EXTREFSEL_AnalogReference0 <<
+    ADC_CONFIG_EXTREFSEL_Pos, /**< External reference 0. */
+        NRF_ADC_CONFIG_REF_EXT_REF1 = ADC_CONFIG_REFSEL_External |
+                                  ADC_CONFIG_EXTREFSEL_AnalogReference1 << ADC_CONFIG_EXTREFSEL_Pos, /**< External reference 0. */
+} nrf_adc_config_reference_t;
+
+/**
+ * @enum nrf_adc_config_input_t
+ * @brief Input selection of the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_ADC_CONFIG_INPUT_DISABLED = ADC_CONFIG_PSEL_Disabled,     /**< No input selected. */
+    NRF_ADC_CONFIG_INPUT_0        = ADC_CONFIG_PSEL_AnalogInput0, /**< Input 0. */
+    NRF_ADC_CONFIG_INPUT_1        = ADC_CONFIG_PSEL_AnalogInput1, /**< Input 1. */
+    NRF_ADC_CONFIG_INPUT_2        = ADC_CONFIG_PSEL_AnalogInput2, /**< Input 2. */
+    NRF_ADC_CONFIG_INPUT_3        = ADC_CONFIG_PSEL_AnalogInput3, /**< Input 3. */
+    NRF_ADC_CONFIG_INPUT_4        = ADC_CONFIG_PSEL_AnalogInput4, /**< Input 4. */
+    NRF_ADC_CONFIG_INPUT_5        = ADC_CONFIG_PSEL_AnalogInput5, /**< Input 5. */
+    NRF_ADC_CONFIG_INPUT_6        = ADC_CONFIG_PSEL_AnalogInput6, /**< Input 6. */
+    NRF_ADC_CONFIG_INPUT_7        = ADC_CONFIG_PSEL_AnalogInput7, /**< Input 7. */
+} nrf_adc_config_input_t;
+
+/**
+ * @enum nrf_adc_task_t
+ * @brief Analog-to-digital converter tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_ADC_TASK_START = offsetof(NRF_ADC_Type, TASKS_START), /**< ADC start sampling task. */
+    NRF_ADC_TASK_STOP  = offsetof(NRF_ADC_Type, TASKS_STOP)   /**< ADC stop sampling task. */
+    /*lint -restore*/
+} nrf_adc_task_t;
+
+/**
+ * @enum nrf_adc_event_t
+ * @brief Analog-to-digital converter events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    /*lint -save -e30*/
+    NRF_ADC_EVENT_END = offsetof(NRF_ADC_Type, EVENTS_END) /**< End of conversion event. */
+    /*lint -restore*/
+} nrf_adc_event_t;
+
+/**@brief Analog-to-digital converter configuration. */
+typedef struct
+{
+    nrf_adc_config_resolution_t resolution; /**< ADC resolution. */
+    nrf_adc_config_scaling_t    scaling;    /**< ADC scaling factor. */
+    nrf_adc_config_reference_t  reference;  /**< ADC reference. */
+} nrf_adc_config_t;
+
+/** Default ADC configuration. */
+#define NRF_ADC_CONFIG_DEFAULT { NRF_ADC_CONFIG_RES_10BIT,               \
+                                 NRF_ADC_CONFIG_SCALING_INPUT_ONE_THIRD, \
+                                 NRF_ADC_CONFIG_REF_VBG }
+
+/**
+ * @brief Function for configuring ADC.
+ *
+ * This function powers on the analog-to-digital converter and configures it. 
+ * After the configuration, the ADC is in DISABLE state and must be
+ * enabled before using it.
+ *
+ * @param[in] config Configuration parameters.
+ */
+void nrf_adc_configure(nrf_adc_config_t * config);
+
+/**
+ * @brief Blocking function for executing a single ADC conversion.
+ *
+ * This function selects the desired input, starts a single conversion,
+ * waits for it to finish, and returns the result.
+ * After the input is selected, the analog-to-digital converter
+ * is left in STOP state.
+ * The function does not check if the ADC is initialized and powered.
+ *
+ * @param[in] input Input to be selected.
+ *
+ * @return Conversion result.
+ */
+int32_t nrf_adc_convert_single(nrf_adc_config_input_t input);
+
+/**
+ * @brief Function for selecting ADC input.
+ *
+ * This function selects the active input of ADC. Ensure that
+ * the ADC is powered on and in IDLE state before calling this function.
+ *
+ * @param[in] input Input to be selected.
+ */
+__STATIC_INLINE void nrf_adc_input_select(nrf_adc_config_input_t input)
+{
+    NRF_ADC->CONFIG =
+        ((uint32_t)input << ADC_CONFIG_PSEL_Pos) | (NRF_ADC->CONFIG & ~ADC_CONFIG_PSEL_Msk);
+
+    if (input != NRF_ADC_CONFIG_INPUT_DISABLED)
+    {
+        NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Enabled << ADC_ENABLE_ENABLE_Pos;
+    }
+    else
+    {
+        NRF_ADC->ENABLE = ADC_ENABLE_ENABLE_Disabled << ADC_ENABLE_ENABLE_Pos;
+    }
+}
+
+
+/**
+ * @brief Function for retrieving the ADC conversion result.
+ *
+ * This function retrieves and returns the last analog-to-digital conversion result.
+ *
+ * @return Last conversion result.
+ */
+__STATIC_INLINE int32_t nrf_adc_result_get(void)
+{
+    return (int32_t)NRF_ADC->RESULT;
+}
+
+
+/**
+ * @brief Function for checking whether the ADC is busy.
+ *
+ * This function checks whether the analog-to-digital converter is busy with a conversion.
+ *
+ * @retval true If the ADC is busy.
+ * @retval false If the ADC is not busy.
+ */
+__STATIC_INLINE bool nrf_adc_is_busy(void)
+{
+    return ( (NRF_ADC->BUSY & ADC_BUSY_BUSY_Msk) == ADC_BUSY_BUSY_Msk);
+}
+
+/**
+ * @brief Function for getting the ADC's enabled interrupts.
+ *
+ * @param[in] mask Mask of interrupts to check.
+ *
+ * @return State of the interrupts selected by the mask.
+ *
+ * @sa nrf_adc_int_enable()
+ * @sa nrf_adc_int_disable()
+ */
+__STATIC_INLINE uint32_t nrf_adc_int_get(uint32_t mask)
+{
+    return (NRF_ADC->INTENSET & mask); // when read this register will return the value of INTEN.
+}
+
+
+/**
+ * @brief Function for starting conversion.
+ *
+ * @sa nrf_adc_stop()
+ *
+ */
+__STATIC_INLINE void nrf_adc_start(void)
+{
+    NRF_ADC->TASKS_START = 1;
+}
+
+
+/**
+ * @brief Function for stopping conversion. 
+ *
+ * If the analog-to-digital converter is in inactive state, power consumption is reduced.
+ *
+ * @sa nrf_adc_start()
+ *
+ */
+__STATIC_INLINE void nrf_adc_stop(void)
+{
+    NRF_ADC->TASKS_STOP = 1;
+}
+
+
+/**
+ * @brief Function for checking if the requested ADC conversion has ended.
+ *
+ * @retval true If the task has finished.
+ * @retval false If the task is still running.
+ */
+__STATIC_INLINE bool nrf_adc_conversion_finished(void)
+{
+    return ((bool)NRF_ADC->EVENTS_END);
+}
+
+/**
+ * @brief Function for clearing the conversion END event.
+ */
+__STATIC_INLINE void nrf_adc_conversion_event_clean(void)
+{
+    NRF_ADC->EVENTS_END = 0;
+}
+
+/**
+ * @brief Function for getting the address of an ADC task register.
+ *
+ * @param[in] adc_task ADC task.
+ *
+ * @return Address of the specified ADC task.
+ */
+__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task);
+
+/**
+ * @brief Function for getting the address of a specific ADC event register.
+ *
+ * @param[in] adc_event ADC event.
+ *
+ * @return Address of the specified ADC event.
+ */
+__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event);
+
+/**
+ * @brief Function for setting the CONFIG register in ADC.
+ *
+ * @param[in] configuration Value to be written to the CONFIG register.
+ */
+__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration);
+
+/**
+ * @brief Function for clearing an ADC event.
+ *
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event);
+
+/**
+ * @brief Function for checking state of an ADC event.
+ *
+ * @param[in] event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] int_mask  Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] int_mask  Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] int_mask Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask);
+
+/**
+ * @brief Function for activating a specific ADC task.
+ *
+ * @param[in] task Task to activate.
+ */
+__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task);
+
+/**
+ * @brief Function for enabling ADC.
+ *
+ */
+__STATIC_INLINE void nrf_adc_enable(void);
+
+/**
+ * @brief Function for disabling ADC.
+ *
+ */
+__STATIC_INLINE void nrf_adc_disable(void);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t nrf_adc_task_address_get(nrf_adc_task_t adc_task)
+{
+    return (uint32_t)((uint8_t *)NRF_ADC + adc_task);
+}
+
+__STATIC_INLINE uint32_t nrf_adc_event_address_get(nrf_adc_event_t adc_event)
+{
+    return (uint32_t)((uint8_t *)NRF_ADC + adc_event);
+}
+
+__STATIC_INLINE void nrf_adc_config_set(uint32_t configuration)
+{
+    NRF_ADC->CONFIG = configuration;
+}
+
+__STATIC_INLINE void nrf_adc_event_clear(nrf_adc_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_adc_event_check(nrf_adc_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_adc_int_enable(uint32_t int_mask)
+{
+    NRF_ADC->INTENSET = int_mask;
+}
+
+__STATIC_INLINE void nrf_adc_int_disable(uint32_t int_mask)
+{
+    NRF_ADC->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE bool nrf_adc_int_enable_check(nrf_adc_int_mask_t int_mask)
+{
+    return (bool)(NRF_ADC->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_adc_task_trigger(nrf_adc_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_ADC + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE void nrf_adc_enable(void)
+{
+    NRF_ADC->ENABLE = 1;
+}
+
+__STATIC_INLINE void nrf_adc_disable(void)
+{
+    NRF_ADC->ENABLE = 0;
+}
+#endif
+#endif /* NRF52 */
+/**
+ *@}
+ **/
+
+#endif /* NRF_ADC_H_ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_clock.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_clock.h
new file mode 100644
index 0000000000..2471a317f6
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_clock.h
@@ -0,0 +1,441 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_CLOCK_H__
+#define NRF_CLOCK_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+ 
+#include "nrf.h"
+
+/**
+ * @defgroup nrf_clock_hal Clock HAL
+ * @{
+ * @ingroup nrf_clock
+ * @brief Hardware access layer for managing the low-frequency clock (LFCLK) and the high-frequency clock (HFCLK).
+ */
+
+#define NRF_CLOCK_TASK_TRIGGER (1UL)
+#define NRF_CLOCK_EVENT_CLEAR  (0UL)
+
+/**
+ * @brief Low-frequency clock sources.
+ * @details Used by LFCLKSRC, LFCLKSTAT, and LFCLKSRCCOPY registers.
+ */
+typedef enum
+{
+    NRF_CLOCK_LFCLK_RC    = CLOCK_LFCLKSRC_SRC_RC,   /**< Internal 32 kHz RC oscillator. */
+    NRF_CLOCK_LFCLK_Xtal  = CLOCK_LFCLKSRC_SRC_Xtal, /**< External 32 kHz crystal. */
+    NRF_CLOCK_LFCLK_Synth = CLOCK_LFCLKSRC_SRC_Synth /**< Internal 32 kHz synthesizer from HFCLK system clock. */
+} nrf_clock_lfclk_t;
+
+/**
+ * @brief High-frequency clock sources.
+ */
+typedef enum
+{
+    NRF_CLOCK_HFCLK_LOW_ACCURACY  = CLOCK_HFCLKSTAT_SRC_RC,  /**< Internal 16 MHz RC oscillator. */
+    NRF_CLOCK_HFCLK_HIGH_ACCURACY = CLOCK_HFCLKSTAT_SRC_Xtal /**< External 16 MHz/32 MHz crystal oscillator. */
+} nrf_clock_hfclk_t;
+
+/**
+ * @brief Trigger status of task LFCLKSTART/HFCLKSTART.
+ * @details Used by LFCLKRUN and HFCLKRUN registers.
+ */
+typedef enum
+{
+    NRF_CLOCK_START_TASK_NOT_TRIGGERED = CLOCK_LFCLKRUN_STATUS_NotTriggered, /**< Task LFCLKSTART/HFCLKSTART has not been triggered. */
+    NRF_CLOCK_START_TASK_TRIGGERED     = CLOCK_LFCLKRUN_STATUS_Triggered     /**< Task LFCLKSTART/HFCLKSTART has been triggered. */
+} nrf_clock_start_task_status_t;
+
+/**
+ * @brief Crystal frequency selection.
+ */
+typedef enum
+{
+#ifdef NRF51
+    NRF_CLOCK_XTALFREQ_Default = CLOCK_XTALFREQ_XTALFREQ_16MHz, /**< Default. 32 MHz. */
+    NRF_CLOCK_XTALFREQ_16MHz   = CLOCK_XTALFREQ_XTALFREQ_16MHz, /**< 16 MHz crystal. */
+    NRF_CLOCK_XTALFREQ_32MHz   = CLOCK_XTALFREQ_XTALFREQ_32MHz  /**< 32 MHz crystal. */
+#elif defined NRF52
+    NRF_CLOCK_XTALFREQ_Default,                                 /**< Default. 64MHz. */
+#endif
+} nrf_clock_xtalfreq_t;
+
+/**
+ * @brief Interrupts.
+ */
+typedef enum
+{
+    NRF_CLOCK_INT_HF_STARTED_MASK = CLOCK_INTENSET_HFCLKSTARTED_Msk, /**< Interrupt on HFCLKSTARTED event. */
+    NRF_CLOCK_INT_LF_STARTED_MASK = CLOCK_INTENSET_LFCLKSTARTED_Msk, /**< Interrupt on LFCLKSTARTED event. */
+    NRF_CLOCK_INT_DONE_MASK       = CLOCK_INTENSET_DONE_Msk,         /**< Interrupt on DONE event. */
+    NRF_CLOCK_INT_CTTO_MASK       = CLOCK_INTENSET_CTTO_Msk          /**< Interrupt on CTTO event. */
+} nrf_clock_int_mask_t;
+
+/**
+ * @brief Tasks.
+ *
+ * @details The NRF_CLOCK_TASK_LFCLKSTOP task cannot be set when the low-frequency clock is not running.
+ * The NRF_CLOCK_TASK_HFCLKSTOP task cannot be set when the high-frequency clock is not running.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_CLOCK_TASK_HFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTART), /**< Start HFCLK clock source.*/
+    NRF_CLOCK_TASK_HFCLKSTOP  = offsetof(NRF_CLOCK_Type, TASKS_HFCLKSTOP),  /**< Stop HFCLK clock source.*/
+    NRF_CLOCK_TASK_LFCLKSTART = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTART), /**< Start LFCLK clock source.*/
+    NRF_CLOCK_TASK_LFCLKSTOP  = offsetof(NRF_CLOCK_Type, TASKS_LFCLKSTOP),  /**< Stop LFCLK clock source.*/
+    NRF_CLOCK_TASK_CAL        = offsetof(NRF_CLOCK_Type, TASKS_CAL),        /**< Start calibration of LFCLK RC oscillator.*/
+    NRF_CLOCK_TASK_CTSTART    = offsetof(NRF_CLOCK_Type, TASKS_CTSTART),    /**< Start calibration timer.*/
+    NRF_CLOCK_TASK_CTSTOP     = offsetof(NRF_CLOCK_Type, TASKS_CTSTOP)      /**< Stop calibration timer.*/
+} nrf_clock_task_t;                                                         /*lint -restore */
+
+/**
+ * @brief Events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_CLOCK_EVENT_HFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_HFCLKSTARTED), /**< HFCLK oscillator started.*/
+    NRF_CLOCK_EVENT_LFCLKSTARTED = offsetof(NRF_CLOCK_Type, EVENTS_LFCLKSTARTED), /**< LFCLK oscillator started.*/
+    NRF_CLOCK_EVENT_DONE         = offsetof(NRF_CLOCK_Type, EVENTS_DONE),         /**< Calibration of LFCLK RC oscillator completed.*/
+    NRF_CLOCK_EVENT_CTTO         = offsetof(NRF_CLOCK_Type, EVENTS_CTTO)          /**< Calibration timer time-out.*/
+} nrf_clock_event_t;                                                               /*lint -restore */
+
+/**
+ * @brief Function for enabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask);
+
+/**
+ * @brief Function for disabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ *
+ * @retval     true                   If the interrupt is enabled.
+ * @retval     false                  If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask);
+
+/**
+ * @brief Function for retrieving the address of a specific task. 
+ * @details This function can be used by the PPI module.
+ *
+ * @param[in]  task             Task.
+ *
+ * @return     Address of the requested task register.
+ */
+__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task);
+
+/**
+ * @brief Function for setting a specific task.
+ *
+ * @param[in]  task             Task.
+ */
+__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task);
+
+/**
+ * @brief Function for retrieving the address of a specific event. 
+ * @details This function can be used by the PPI module.
+ *
+ * @param[in]  event       Event.
+ *
+ * @return     Address of the requested event register.
+ */
+__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param[in]  event       Event.
+ */
+__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event);
+
+/**
+ * @brief Function for retrieving the state of a specific event.
+ *
+ * @param[in]  event       Event.
+ *
+ * @retval     true              If the event is set.
+ * @retval     false             If the event is not set.
+ */
+__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event);
+
+/**
+ * @brief Function for changing the low-frequency clock source.
+ * @details This function cannot be called when the low-frequency clock is running.
+ *
+ * @param[in]  source            New low-frequency clock source.
+ *
+ */
+__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source);
+
+/**
+ * @brief Function for retrieving the selected source for the low-frequency clock.
+ *
+ * @retval     NRF_CLOCK_LFCLK_RC     If the internal 32 kHz RC oscillator is the selected source for the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Xtal   If an external 32 kHz crystal oscillator is the selected source for the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Synth  If the internal 32 kHz synthesizer from the HFCLK is the selected source for the low-frequency clock.
+ */
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void);
+
+/**
+ * @brief Function for retrieving the active source of the low-frequency clock.
+ *
+ * @retval     NRF_CLOCK_LFCLK_RC     If the internal 32 kHz RC oscillator is the active source of the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Xtal   If an external 32 kHz crystal oscillator is the active source of the low-frequency clock.
+ * @retval     NRF_CLOCK_LFCLK_Synth  If the internal 32 kHz synthesizer from the HFCLK is the active source of the low-frequency clock.
+ */
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void);
+
+/**
+ * @brief Function for retrieving the clock source for the LFCLK clock when the task LKCLKSTART is triggered.
+ *
+ * @retval     NRF_CLOCK_LFCLK_RC     If the internal 32 kHz RC oscillator is running and generating the LFCLK clock.
+ * @retval     NRF_CLOCK_LFCLK_Xtal   If an external 32 kHz crystal oscillator is running and generating the LFCLK clock.
+ * @retval     NRF_CLOCK_LFCLK_Synth  If the internal 32 kHz synthesizer from the HFCLK is running and generating the LFCLK clock.
+ */
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void);
+
+/**
+ * @brief Function for retrieving the state of the LFCLK clock.
+ *
+ * @retval     false                     If the LFCLK clock is not running.
+ * @retval     true                      If the LFCLK clock is running.
+ */
+__STATIC_INLINE bool nrf_clock_lf_is_running(void);
+
+/**
+ * @brief Function for retrieving the trigger status of the task LFCLKSTART.
+ *
+ * @retval     NRF_CLOCK_START_TASK_NOT_TRIGGERED     If the task LFCLKSTART has not been triggered.
+ * @retval     NRF_CLOCK_START_TASK_TRIGGERED         If the task LFCLKSTART has been triggered.
+ */
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void);
+
+/**
+ * @brief Function for retrieving the active source of the high-frequency clock.
+ *
+ * @retval     NRF_CLOCK_HFCLK_LOW_ACCURACY   If the internal 16 MHz RC oscillator is the active source of the high-frequency clock.
+ * @retval     NRF_CLOCK_HFCLK_HIGH_ACCURACY  If an external 16 MHz/32 MHz crystal oscillator is the active source of the high-frequency clock.
+ */
+__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void);
+
+/**
+ * @brief Function for retrieving the state of the HFCLK clock.
+ *
+ * @param[in]  clk_src                   Clock source to be checked.
+ *
+ * @retval     false                     If the HFCLK clock is not running.
+ * @retval     true                      If the HFCLK clock is running.
+ */
+__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src);
+
+/**
+ * @brief Function for retrieving the trigger status of the task HFCLKSTART.
+ *
+ * @retval     NRF_CLOCK_START_TASK_NOT_TRIGGERED     If the task HFCLKSTART has not been triggered.
+ * @retval     NRF_CLOCK_START_TASK_TRIGGERED         If the task HFCLKSTART has been triggered.
+ */
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void);
+
+/**
+ * @brief Function for retrieving the frequency selection of the external crystal.
+ *
+ * @retval     NRF_CLOCK_XTALFREQ_16MHz     If a 16 MHz crystal is used as source for the HFCLK oscillator.
+ * @retval     NRF_CLOCK_XTALFREQ_32MHz     If a 32 MHz crystal is used as source for the HFCLK oscillator.
+ */
+__STATIC_INLINE nrf_clock_xtalfreq_t nrf_clock_xtalfreq_get(void);
+
+/**
+ * @brief Function for changing the frequency selection of the external crystal.
+ *
+ * @param[in]  xtalfreq             New frequency selection for the external crystal.
+ */
+__STATIC_INLINE void nrf_clock_xtalfreq_set(nrf_clock_xtalfreq_t xtalfreq);
+
+/**
+ * @brief Function for changing the calibration timer interval.
+ *
+ * @param[in]  interval             New calibration timer interval in 0.25 s resolution (range: 0.25 seconds to 31.75 seconds).
+ */
+__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_clock_int_enable(uint32_t int_mask)
+{
+    NRF_CLOCK->INTENSET = int_mask;
+}
+
+__STATIC_INLINE void nrf_clock_int_disable(uint32_t int_mask)
+{
+    NRF_CLOCK->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE bool nrf_clock_int_enable_check(nrf_clock_int_mask_t int_mask)
+{
+    return (bool)(NRF_CLOCK->INTENCLR & int_mask);
+}
+
+__STATIC_INLINE uint32_t nrf_clock_task_address_get(nrf_clock_task_t task)
+{
+    return ((uint32_t )NRF_CLOCK + task);
+}
+
+__STATIC_INLINE void nrf_clock_task_trigger(nrf_clock_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + task)) = NRF_CLOCK_TASK_TRIGGER;
+}
+
+__STATIC_INLINE uint32_t nrf_clock_event_address_get(nrf_clock_event_t event)
+{
+    return ((uint32_t)NRF_CLOCK + event);
+}
+
+__STATIC_INLINE void nrf_clock_event_clear(nrf_clock_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event)) = NRF_CLOCK_EVENT_CLEAR;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_clock_event_check(nrf_clock_event_t event)
+{
+    return (bool)*((volatile uint32_t *)((uint8_t *)NRF_CLOCK + event));
+}
+
+__STATIC_INLINE void nrf_clock_lf_src_set(nrf_clock_lfclk_t source)
+{
+    NRF_CLOCK->LFCLKSRC =
+        (uint32_t)((source << CLOCK_LFCLKSRC_SRC_Pos) & CLOCK_LFCLKSRC_SRC_Msk);
+}
+
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_src_get(void)
+{
+    return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRC &
+                                CLOCK_LFCLKSRC_SRC_Msk) >> CLOCK_LFCLKSRC_SRC_Pos);
+}
+
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_actv_src_get(void)
+{
+    return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSTAT &
+                                CLOCK_LFCLKSTAT_SRC_Msk) >> CLOCK_LFCLKSTAT_SRC_Pos);
+}
+
+__STATIC_INLINE nrf_clock_lfclk_t nrf_clock_lf_srccopy_get(void)
+{
+    return (nrf_clock_lfclk_t)((NRF_CLOCK->LFCLKSRCCOPY &
+                                CLOCK_LFCLKSRCCOPY_SRC_Msk) >> CLOCK_LFCLKSRCCOPY_SRC_Pos);
+}
+
+__STATIC_INLINE bool nrf_clock_lf_is_running(void)
+{
+    return ((NRF_CLOCK->LFCLKSTAT &
+             CLOCK_LFCLKSTAT_STATE_Msk) >> CLOCK_LFCLKSTAT_STATE_Pos);
+}
+
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_lf_start_task_status_get(void)
+{
+    return (nrf_clock_start_task_status_t)((NRF_CLOCK->LFCLKRUN &
+                                            CLOCK_LFCLKRUN_STATUS_Msk) >>
+                                           CLOCK_LFCLKRUN_STATUS_Pos);
+}
+
+__STATIC_INLINE nrf_clock_hfclk_t nrf_clock_hf_src_get(void)
+{
+    return (nrf_clock_hfclk_t)((NRF_CLOCK->HFCLKSTAT &
+                                CLOCK_HFCLKSTAT_SRC_Msk) >> CLOCK_HFCLKSTAT_SRC_Pos);
+}
+
+__STATIC_INLINE bool nrf_clock_hf_is_running(nrf_clock_hfclk_t clk_src)
+{
+    return (NRF_CLOCK->HFCLKSTAT & (CLOCK_HFCLKSTAT_STATE_Msk | CLOCK_HFCLKSTAT_SRC_Msk)) ==
+            (CLOCK_HFCLKSTAT_STATE_Msk | (clk_src << CLOCK_HFCLKSTAT_SRC_Pos));
+}
+
+__STATIC_INLINE nrf_clock_start_task_status_t nrf_clock_hf_start_task_status_get(void)
+{
+    return (nrf_clock_start_task_status_t)((NRF_CLOCK->HFCLKRUN &
+                                            CLOCK_HFCLKRUN_STATUS_Msk) >>
+                                           CLOCK_HFCLKRUN_STATUS_Pos);
+}
+
+__STATIC_INLINE nrf_clock_xtalfreq_t nrf_clock_xtalfreq_get(void)
+{
+#ifdef NRF51
+    return (nrf_clock_xtalfreq_t)((NRF_CLOCK->XTALFREQ &
+                                       CLOCK_XTALFREQ_XTALFREQ_Msk) >> CLOCK_XTALFREQ_XTALFREQ_Pos);
+#elif defined NRF52
+    return NRF_CLOCK_XTALFREQ_Default;
+#endif
+}
+
+__STATIC_INLINE void nrf_clock_xtalfreq_set(nrf_clock_xtalfreq_t xtalfreq)
+{
+#ifdef NRF51
+    NRF_CLOCK->XTALFREQ =
+        (uint32_t)((xtalfreq << CLOCK_XTALFREQ_XTALFREQ_Pos) & CLOCK_XTALFREQ_XTALFREQ_Msk);
+#elif defined NRF52
+    return;
+#endif
+}
+
+__STATIC_INLINE void nrf_clock_cal_timer_timeout_set(uint32_t interval)
+{
+    NRF_CLOCK->CTIV = ((interval << CLOCK_CTIV_CTIV_Pos) & CLOCK_CTIV_CTIV_Msk);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+/**
+ *@}
+ **/
+#endif // NRF_CLOCK_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.c
new file mode 100644
index 0000000000..e66f63f07d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.c
@@ -0,0 +1,100 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+
+/** 
+ * @file
+ * @brief Implementation of AES ECB driver
+ */
+
+
+//lint -e438
+
+#include <stdlib.h>
+#include <stdbool.h>
+#include <string.h>
+#include "nrf.h" 
+#include "nrf_ecb.h"
+
+static uint8_t  ecb_data[48];   ///< ECB data structure for RNG peripheral to access.
+static uint8_t* ecb_key;        ///< Key:        Starts at ecb_data 
+static uint8_t* ecb_cleartext;  ///< Cleartext:  Starts at ecb_data + 16 bytes.
+static uint8_t* ecb_ciphertext; ///< Ciphertext: Starts at ecb_data + 32 bytes.
+
+bool nrf_ecb_init(void)
+{
+  ecb_key = ecb_data;
+  ecb_cleartext  = ecb_data + 16;
+  ecb_ciphertext = ecb_data + 32;
+
+  NRF_ECB->ECBDATAPTR = (uint32_t)ecb_data;
+  return true;
+}
+
+
+bool nrf_ecb_crypt(uint8_t * dest_buf, const uint8_t * src_buf)
+{
+   uint32_t counter = 0x1000000;
+   if(src_buf != ecb_cleartext)
+   {
+     memcpy(ecb_cleartext,src_buf,16);
+   }
+   NRF_ECB->EVENTS_ENDECB = 0;
+   NRF_ECB->TASKS_STARTECB = 1;
+   while(NRF_ECB->EVENTS_ENDECB == 0)
+   {
+    counter--;
+    if(counter == 0)
+    {
+      return false;
+    }
+   }
+   NRF_ECB->EVENTS_ENDECB = 0;
+   if(dest_buf != ecb_ciphertext)
+   {
+     memcpy(dest_buf,ecb_ciphertext,16);
+   }
+   return true;
+}
+
+void nrf_ecb_set_key(const uint8_t * key)
+{
+  memcpy(ecb_key,key,16);
+}
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.h
new file mode 100644
index 0000000000..7b4cbf1e4b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ecb.h
@@ -0,0 +1,92 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file
+ * @brief ECB driver API.
+ */
+
+#ifndef NRF_ECB_H__
+#define NRF_ECB_H__
+
+/**
+ * @defgroup nrf_ecb AES ECB encryption
+ * @{
+ * @ingroup nrf_drivers
+ * @brief Driver for the AES Electronic Code Book (ECB) peripheral.
+ *
+ * To encrypt and decrypt data, the peripheral must first be powered on
+ * using @ref nrf_ecb_init. Next, the key must be set using @ref nrf_ecb_set_key.
+ */
+
+#include <stdint.h>
+
+/**
+ * @brief Function for initializing and powering on the ECB peripheral.
+ *
+ * This function allocates memory for the ECBDATAPTR.
+ * @retval true If initialization was successful.
+ * @retval false If powering on failed.
+ */
+bool nrf_ecb_init(void);
+
+/**
+ * @brief Function for encrypting and decrypting 16-byte data using current key.
+ *
+ * This function avoids unnecessary copying of data if the parameters point to the 
+ * correct locations in the ECB data structure.
+ *
+ * @param dst Result of encryption/decryption. 16 bytes will be written. 
+ * @param src Source with 16-byte data to be encrypted/decrypted.
+ *
+ * @retval true  If the encryption operation completed.
+ * @retval false If the encryption operation did not complete.
+ */
+bool nrf_ecb_crypt(uint8_t * dst, const uint8_t * src);
+
+/**
+ * @brief Function for setting the key to be used for encryption and decryption.
+ *
+ * @param key Pointer to the key. 16 bytes will be read.
+ */
+void nrf_ecb_set_key(const uint8_t * key);
+
+#endif  // NRF_ECB_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpio.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpio.h
new file mode 100644
index 0000000000..3127568fb5
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpio.h
@@ -0,0 +1,674 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_GPIO_H__
+#define NRF_GPIO_H__
+
+#include "nrf.h"
+#include <stdbool.h>
+
+/**
+ * @defgroup nrf_gpio GPIO abstraction
+ * @{
+ * @ingroup nrf_drivers
+ * @brief GPIO pin abstraction and port abstraction for reading and writing byte-wise to GPIO ports.
+ *
+ * Here, the GPIO ports are defined as follows:
+ * - Port 0 -> pin 0-7
+ * - Port 1 -> pin 8-15
+ * - Port 2 -> pin 16-23
+ * - Port 3 -> pin 24-31
+ */
+
+#define NUMBER_OF_PINS 32
+
+/**
+ * @brief Enumerator used for selecting between port 0 - 3.
+ */
+typedef enum
+{
+    NRF_GPIO_PORT_SELECT_PORT0 = 0,           ///<  Port 0 (GPIO pin 0-7)
+    NRF_GPIO_PORT_SELECT_PORT1,               ///<  Port 1 (GPIO pin 8-15)
+    NRF_GPIO_PORT_SELECT_PORT2,               ///<  Port 2 (GPIO pin 16-23)
+    NRF_GPIO_PORT_SELECT_PORT3,               ///<  Port 3 (GPIO pin 24-31)
+} nrf_gpio_port_select_t;
+
+/**
+ * @brief Enumerator used for setting the direction of a GPIO port.
+ */
+typedef enum
+{
+    NRF_GPIO_PORT_DIR_OUTPUT,       ///<  Output
+    NRF_GPIO_PORT_DIR_INPUT         ///<  Input
+} nrf_gpio_port_dir_t;
+
+/**
+ * @brief Pin direction definitions.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_DIR_INPUT  = GPIO_PIN_CNF_DIR_Input,   ///< Input
+    NRF_GPIO_PIN_DIR_OUTPUT = GPIO_PIN_CNF_DIR_Output   ///< Output
+} nrf_gpio_pin_dir_t;
+
+/**
+ * @brief Connection of input buffer
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_INPUT_CONNECT    = GPIO_PIN_CNF_INPUT_Connect,   ///< Connect input buffer
+    NRF_GPIO_PIN_INPUT_DISCONNECT = GPIO_PIN_CNF_INPUT_Disconnect ///< Disconnect input buffer
+} nrf_gpio_pin_input_t;
+
+/**
+ * @brief Enumerator used for selecting the pin to be pulled down or up at the time of pin configuration
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_NOPULL   = GPIO_PIN_CNF_PULL_Disabled,                 ///<  Pin pullup resistor disabled
+    NRF_GPIO_PIN_PULLDOWN = GPIO_PIN_CNF_PULL_Pulldown,                 ///<  Pin pulldown resistor enabled
+    NRF_GPIO_PIN_PULLUP   = GPIO_PIN_CNF_PULL_Pullup,                   ///<  Pin pullup resistor enabled
+} nrf_gpio_pin_pull_t;
+
+/**
+ * @brief Enumerator used for selecting output drive mode
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_S0S1 = GPIO_PIN_CNF_DRIVE_S0S1, ///< !< Standard '0', standard '1'
+    NRF_GPIO_PIN_H0S1 = GPIO_PIN_CNF_DRIVE_H0S1, ///< !< High drive '0', standard '1'
+    NRF_GPIO_PIN_S0H1 = GPIO_PIN_CNF_DRIVE_S0H1, ///< !< Standard '0', high drive '1'
+    NRF_GPIO_PIN_H0H1 = GPIO_PIN_CNF_DRIVE_H0H1, ///< !< High drive '0', high 'drive '1''
+    NRF_GPIO_PIN_D0S1 = GPIO_PIN_CNF_DRIVE_D0S1, ///< !< Disconnect '0' standard '1'
+    NRF_GPIO_PIN_D0H1 = GPIO_PIN_CNF_DRIVE_D0H1, ///< !< Disconnect '0', high drive '1'
+    NRF_GPIO_PIN_S0D1 = GPIO_PIN_CNF_DRIVE_S0D1, ///< !< Standard '0'. disconnect '1'
+    NRF_GPIO_PIN_H0D1 = GPIO_PIN_CNF_DRIVE_H0D1, ///< !< High drive '0', disconnect '1'
+} nrf_gpio_pin_drive_t;
+
+/**
+ * @brief Enumerator used for selecting the pin to sense high or low level on the pin input.
+ */
+typedef enum
+{
+    NRF_GPIO_PIN_NOSENSE    = GPIO_PIN_CNF_SENSE_Disabled,              ///<  Pin sense level disabled.
+    NRF_GPIO_PIN_SENSE_LOW  = GPIO_PIN_CNF_SENSE_Low,                   ///<  Pin sense low level.
+    NRF_GPIO_PIN_SENSE_HIGH = GPIO_PIN_CNF_SENSE_High,                  ///<  Pin sense high level.
+} nrf_gpio_pin_sense_t;
+
+
+/**
+ * @brief Function for configuring the GPIO pin range as outputs with normal drive strength.
+ *        This function can be used to configure pin range as simple output with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
+ *
+ * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
+ *
+ * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
+ *
+ * @note For configuring only one pin as output use @ref nrf_gpio_cfg_output
+ *       Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
+ */
+__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end);
+
+/**
+ * @brief Function for configuring the GPIO pin range as inputs with given initial value set, hiding inner details.
+ *        This function can be used to configure pin range as simple input.
+ *
+ * @param pin_range_start specifies the start number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
+ *
+ * @param pin_range_end specifies the end number (inclusive) in the range of pin numbers to be configured (allowed values 0-30)
+ *
+ * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high)
+ *
+ * @note  For configuring only one pin as input use @ref nrf_gpio_cfg_input
+ *        Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
+ */
+__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config);
+
+/**
+ * @brief Pin configuration function
+ *
+ * The main pin configuration function.
+ * This function allows to set any aspect in PIN_CNF register.
+ * @param pin_number Specifies the pin number (allowed values 0-31).
+ * @param dir   Pin direction
+ * @param input Connect or disconnect input buffer
+ * @param pull  Pull configuration
+ * @param drive Drive configuration
+ * @param sense Pin sensing mechanism
+ */
+__STATIC_INLINE void nrf_gpio_cfg(
+        uint32_t             pin_number,
+        nrf_gpio_pin_dir_t   dir,
+        nrf_gpio_pin_input_t input,
+        nrf_gpio_pin_pull_t  pull,
+        nrf_gpio_pin_drive_t drive,
+        nrf_gpio_pin_sense_t sense);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as output with given initial value set, hiding inner details.
+ *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
+ *
+ * @param pin_number specifies the pin number (allowed values 0-31)
+ *
+ * @note  Sense capability on the pin is disabled, and input is disconnected from the buffer as the pins are configured as output.
+ */
+__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
+ *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
+ *
+ * @param pin_number Specifies the pin number (allowed values 0-30).
+ * @param pull_config State of the pin range pull resistor (no pull, pulled down or pulled high).
+ *
+ * @note  Sense capability on the pin is disabled, and input is connected to buffer so that the GPIO->IN register is readable
+ */
+__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config);
+
+/**
+ * @brief Function for reseting pin configuration to its default state.
+ *
+ * @param pin_number Specifies the pin number (allowed values 0-31).
+ */
+__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as a watcher. Only input is connected.
+ *
+ * @param pin_number Specifies the pin number (allowed values 0-31).
+ *
+ */
+__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number);
+
+/**
+ * @brief Function for disconnecting input for the given GPIO.
+ *
+ * @param pin_number Specifies the pin number (allowed values 0-31).
+ *
+ */
+__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number);
+
+/**
+ * @brief Function for configuring the given GPIO pin number as input with given initial value set, hiding inner details.
+ *        This function can be used to configure pin range as simple input with gate driving GPIO_PIN_CNF_DRIVE_S0S1 (normal cases).
+ *        Sense capability on the pin is configurable, and input is connected to buffer so that the GPIO->IN register is readable.
+ *
+ * @param pin_number   Specifies the pin number (allowed values 0-30).
+ * @param pull_config  State of the pin pull resistor (no pull, pulled down or pulled high).
+ * @param sense_config Sense level of the pin (no sense, sense low or sense high).
+ */
+__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config);
+
+/**
+ * @brief Function for configuring sense level for the given GPIO.
+ *
+ * @param pin_number   Specifies the pin number of gpio pin numbers to be configured (allowed values 0-30).
+ * @param sense_config Sense configuration.
+ *
+ */
+__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config);
+
+/**
+ * @brief Function for setting the direction for a GPIO pin.
+ *
+ * @param pin_number specifies the pin number (0-31) for which to
+ * set the direction.
+ *
+ * @param direction specifies the direction
+ */
+__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction);
+
+/**
+ * @brief Function for setting a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number Specifies the pin number (0-31) to set.
+ */
+__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number);
+
+/**
+ * @brief Function for setting GPIO pins.
+ *
+ * Note that the pins must be configured as outputs for this
+ * function to have any effect.
+ *
+ * @param pin_mask Specifies the pins to set.
+ */
+__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask);
+
+/**
+ * @brief Function for clearing a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number Specifies the pin number (0-31) to clear.
+ */
+__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number);
+
+/**
+ * @brief Function for clearing GPIO pins.
+ *
+ * Note that the pins must be configured as outputs for this
+ * function to have any effect.
+ *
+ * @param pin_mask Specifies the pins to clear.
+ */
+__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask);
+
+/**
+ * @brief Function for toggling a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number Specifies the pin number (0-31) to toggle.
+ */
+__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number);
+
+/**
+ * @brief Function for toggling GPIO pins.
+ *
+ * Note that the pins must be configured as outputs for this
+ * function to have any effect.
+ *
+ * @param pin_mask Specifies the pins to toggle.
+ */
+__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask);
+
+/**
+ * @brief Function for writing a value to a GPIO pin.
+ *
+ * Note that the pin must be configured as an output for this
+ * function to have any effect.
+ *
+ * @param pin_number specifies the pin number (0-31) to
+ * write.
+ *
+ * @param value specifies the value to be written to the pin.
+ * @arg 0 clears the pin
+ * @arg >=1 sets the pin.
+ */
+__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value);
+
+/**
+ * @brief Function for reading the input level of a GPIO pin.
+ *
+ * Note that the pin must have input connected for the value
+ * returned from this function to be valid.
+ *
+ * @param pin_number specifies the pin number (0-31) to
+ * read.
+ *
+ * @return
+ * @retval 0 if the pin input level is low.
+ * @retval 1 if the pin input level is high.
+ * @retval > 1 should never occur.
+ */
+__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number);
+
+/**
+ * @brief Function for reading the input level of all GPIO pins.
+ *
+ * Note that the pin must have input connected for the value
+ * returned from this function to be valid.
+ *
+ * @retval Status of input of all pins
+ */
+__STATIC_INLINE uint32_t nrf_gpio_pins_read(void);
+
+/**
+ * @brief Function for reading the sense configuration of a GPIO pin.
+ *
+ * @param pin_number specifies the pin number (0-31) to
+ * read.
+ *
+ * @retval Sense configuration
+ */
+__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number);
+
+/**
+ * @brief Generic function for writing a single byte of a 32 bit word at a given
+ * address.
+ *
+ * This function should not be called from outside the nrf_gpio
+ * abstraction layer.
+ *
+ * @param word_address is the address of the word to be written.
+ *
+ * @param byte_no is the word byte number (0-3) to be written.
+ *
+ * @param value is the value to be written to byte "byte_no" of word
+ * at address "word_address"
+ */
+__STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value);
+
+/**
+ * @brief Generic function for reading a single byte of a 32 bit word at a given
+ * address.
+ *
+ * This function should not be called from outside the nrf_gpio
+ * abstraction layer.
+ *
+ * @param word_address is the address of the word to be read.
+ *
+ * @param byte_no is the byte number (0-3) of the word to be read.
+ *
+ * @return byte "byte_no" of word at address "word_address".
+ */
+__STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no);
+
+/**
+ * @brief Function for setting the direction of a port.
+ *
+ * @param port is the port for which to set the direction.
+ *
+ * @param dir direction to be set for this port.
+ */
+__STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir);
+
+/**
+ * @brief Function for reading a GPIO port.
+ *
+ * @param port is the port to read.
+ *
+ * @return the input value on this port.
+ */
+__STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port);
+
+/**
+ * @brief Function for writing to a GPIO port.
+ *
+ * @param port is the port to write.
+ *
+ * @param value is the value to write to this port.
+ *
+ * @sa nrf_gpio_port_dir_set()
+ */
+__STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value);
+
+/**
+ * @brief Function for setting individual pins on GPIO port.
+ *
+ * @param port is the port for which to set the pins.
+ *
+ * @param set_mask is a mask specifying which pins to set. A bit
+ * set to 1 indicates that the corresponding port pin shall be
+ * set.
+ *
+ * @sa nrf_gpio_port_dir_set()
+ */
+__STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask);
+
+/**
+ * @brief Function for clearing individual pins on GPIO port.
+ *
+ * @param port is the port for which to clear the pins.
+ *
+ * @param clr_mask is a mask specifying which pins to clear. A bit
+ * set to 1 indicates that the corresponding port pin shall be
+ * cleared.
+ *
+ * @sa nrf_gpio_port_dir_set()
+ */
+__STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_gpio_range_cfg_output(uint32_t pin_range_start, uint32_t pin_range_end)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    for (; pin_range_start <= pin_range_end; pin_range_start++)
+    {
+        nrf_gpio_cfg_output(pin_range_start);
+    }
+}
+
+__STATIC_INLINE void nrf_gpio_range_cfg_input(uint32_t pin_range_start, uint32_t pin_range_end, nrf_gpio_pin_pull_t pull_config)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    for (; pin_range_start <= pin_range_end; pin_range_start++)
+    {
+        nrf_gpio_cfg_input(pin_range_start, pull_config);
+    }
+}
+
+__STATIC_INLINE void nrf_gpio_cfg(
+        uint32_t             pin_number,
+        nrf_gpio_pin_dir_t   dir,
+        nrf_gpio_pin_input_t input,
+        nrf_gpio_pin_pull_t  pull,
+        nrf_gpio_pin_drive_t drive,
+        nrf_gpio_pin_sense_t sense)
+{
+    NRF_GPIO->PIN_CNF[pin_number] = ((uint32_t)dir   << GPIO_PIN_CNF_DIR_Pos)
+                                  | ((uint32_t)input << GPIO_PIN_CNF_INPUT_Pos)
+                                  | ((uint32_t)pull  << GPIO_PIN_CNF_PULL_Pos)
+                                  | ((uint32_t)drive << GPIO_PIN_CNF_DRIVE_Pos)
+                                  | ((uint32_t)sense << GPIO_PIN_CNF_SENSE_Pos);
+}
+
+__STATIC_INLINE void nrf_gpio_cfg_output(uint32_t pin_number)
+{
+    nrf_gpio_cfg(
+            pin_number,
+            NRF_GPIO_PIN_DIR_OUTPUT,
+            NRF_GPIO_PIN_INPUT_DISCONNECT,
+            NRF_GPIO_PIN_NOPULL,
+            NRF_GPIO_PIN_S0S1,
+            NRF_GPIO_PIN_NOSENSE);
+}
+
+__STATIC_INLINE void nrf_gpio_cfg_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config)
+{
+    nrf_gpio_cfg(
+            pin_number,
+            NRF_GPIO_PIN_DIR_INPUT,
+            NRF_GPIO_PIN_INPUT_CONNECT,
+            pull_config,
+            NRF_GPIO_PIN_S0S1,
+            NRF_GPIO_PIN_NOSENSE);
+}
+
+__STATIC_INLINE void nrf_gpio_cfg_default(uint32_t pin_number)
+{
+    nrf_gpio_cfg(
+            pin_number,
+            NRF_GPIO_PIN_DIR_INPUT,
+            NRF_GPIO_PIN_INPUT_DISCONNECT,
+            NRF_GPIO_PIN_NOPULL,
+            NRF_GPIO_PIN_S0S1,
+            NRF_GPIO_PIN_NOSENSE);
+}
+
+__STATIC_INLINE void nrf_gpio_cfg_watcher(uint32_t pin_number)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
+    NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Connect << GPIO_PIN_CNF_INPUT_Pos);
+}
+
+__STATIC_INLINE void nrf_gpio_input_disconnect(uint32_t pin_number)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_INPUT_Msk;
+    NRF_GPIO->PIN_CNF[pin_number] = cnf | (GPIO_PIN_CNF_INPUT_Disconnect << GPIO_PIN_CNF_INPUT_Pos);
+}
+
+__STATIC_INLINE void nrf_gpio_cfg_sense_input(uint32_t pin_number, nrf_gpio_pin_pull_t pull_config, nrf_gpio_pin_sense_t sense_config)
+{
+    nrf_gpio_cfg(
+            pin_number,
+            NRF_GPIO_PIN_DIR_INPUT,
+            NRF_GPIO_PIN_INPUT_CONNECT,
+            pull_config,
+            NRF_GPIO_PIN_S0S1,
+            sense_config);
+}
+
+__STATIC_INLINE void nrf_gpio_cfg_sense_set(uint32_t pin_number, nrf_gpio_pin_sense_t sense_config)
+{
+    /*lint -e{845} // A zero has been given as right argument to operator '|'" */
+    //uint32_t cnf = NRF_GPIO->PIN_CNF[pin_number] & ~GPIO_PIN_CNF_SENSE_Msk;
+    NRF_GPIO->PIN_CNF[pin_number] &= ~GPIO_PIN_CNF_SENSE_Msk;
+    NRF_GPIO->PIN_CNF[pin_number] |= (sense_config << GPIO_PIN_CNF_SENSE_Pos);
+}
+
+__STATIC_INLINE void nrf_gpio_pin_dir_set(uint32_t pin_number, nrf_gpio_pin_dir_t direction)
+{
+    if(direction == NRF_GPIO_PIN_DIR_INPUT)
+    {
+        nrf_gpio_cfg(
+                pin_number,
+                NRF_GPIO_PIN_DIR_INPUT,
+                NRF_GPIO_PIN_INPUT_CONNECT,
+                NRF_GPIO_PIN_NOPULL,
+                NRF_GPIO_PIN_S0S1,
+                NRF_GPIO_PIN_NOSENSE);
+    }
+    else
+    {
+        NRF_GPIO->DIRSET = (1UL << pin_number);
+    }
+}
+
+__STATIC_INLINE void nrf_gpio_pin_set(uint32_t pin_number)
+{
+    NRF_GPIO->OUTSET = (1UL << pin_number);
+}
+
+__STATIC_INLINE void nrf_gpio_pins_set(uint32_t pin_mask)
+{
+    NRF_GPIO->OUTSET = pin_mask;
+}
+
+__STATIC_INLINE void nrf_gpio_pin_clear(uint32_t pin_number)
+{
+    NRF_GPIO->OUTCLR = (1UL << pin_number);
+}
+
+__STATIC_INLINE void nrf_gpio_pins_clear(uint32_t pin_mask)
+{
+    NRF_GPIO->OUTCLR = pin_mask;
+}
+
+__STATIC_INLINE void nrf_gpio_pin_toggle(uint32_t pin_number)
+{
+    nrf_gpio_pins_toggle(1UL << pin_number);
+}
+
+__STATIC_INLINE void nrf_gpio_pins_toggle(uint32_t pin_mask)
+{
+    uint32_t pins_state = NRF_GPIO->OUT;
+    NRF_GPIO->OUTSET = (~pins_state & pin_mask);
+    NRF_GPIO->OUTCLR = ( pins_state & pin_mask);
+}
+
+__STATIC_INLINE void nrf_gpio_pin_write(uint32_t pin_number, uint32_t value)
+{
+    if (value == 0)
+    {
+        nrf_gpio_pin_clear(pin_number);
+    }
+    else
+    {
+        nrf_gpio_pin_set(pin_number);
+    }
+}
+
+__STATIC_INLINE uint32_t nrf_gpio_pin_read(uint32_t pin_number)
+{
+    return  ((NRF_GPIO->IN >> pin_number) & 1UL);
+}
+
+__STATIC_INLINE uint32_t nrf_gpio_pins_read(void)
+{
+    return NRF_GPIO->IN;
+}
+
+__STATIC_INLINE nrf_gpio_pin_sense_t nrf_gpio_pin_sense_get(uint32_t pin_number)
+{
+    return (nrf_gpio_pin_sense_t)((NRF_GPIO->PIN_CNF[pin_number] & GPIO_PIN_CNF_SENSE_Msk) >> GPIO_PIN_CNF_SENSE_Pos);
+}
+
+__STATIC_INLINE void nrf_gpio_word_byte_write(volatile uint32_t * word_address, uint8_t byte_no, uint8_t value)
+{
+    *((volatile uint8_t*)(word_address) + byte_no) = value;
+}
+
+__STATIC_INLINE uint8_t nrf_gpio_word_byte_read(const volatile uint32_t* word_address, uint8_t byte_no)
+{
+    return (*((const volatile uint8_t*)(word_address) + byte_no));
+}
+
+__STATIC_INLINE void nrf_gpio_port_dir_set(nrf_gpio_port_select_t port, nrf_gpio_port_dir_t dir)
+{
+    if (dir == NRF_GPIO_PORT_DIR_OUTPUT)
+    {
+        nrf_gpio_word_byte_write(&NRF_GPIO->DIRSET, port, 0xFF);
+    }
+    else
+    {
+        nrf_gpio_range_cfg_input(port*8, (port+1)*8-1, NRF_GPIO_PIN_NOPULL);
+    }
+}
+
+__STATIC_INLINE uint8_t nrf_gpio_port_read(nrf_gpio_port_select_t port)
+{
+    return nrf_gpio_word_byte_read(&NRF_GPIO->IN, port);
+}
+
+__STATIC_INLINE void nrf_gpio_port_write(nrf_gpio_port_select_t port, uint8_t value)
+{
+    nrf_gpio_word_byte_write(&NRF_GPIO->OUT, port, value);
+}
+
+__STATIC_INLINE void nrf_gpio_port_set(nrf_gpio_port_select_t port, uint8_t set_mask)
+{
+    nrf_gpio_word_byte_write(&NRF_GPIO->OUTSET, port, set_mask);
+}
+
+__STATIC_INLINE void nrf_gpio_port_clear(nrf_gpio_port_select_t port, uint8_t clr_mask)
+{
+    nrf_gpio_word_byte_write(&NRF_GPIO->OUTCLR, port, clr_mask);
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpiote.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpiote.h
new file mode 100644
index 0000000000..7ad15e6398
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_gpiote.h
@@ -0,0 +1,418 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_GPIOTE_H__
+#define NRF_GPIOTE_H__
+
+#include "nrf.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+/**
+* @defgroup nrf_gpiote_abs GPIOTE abstraction
+* @{
+* @ingroup nrf_gpiote
+* @brief GPIOTE abstraction for configuration of channels.
+*/
+#ifdef NRF51
+#define NUMBER_OF_GPIO_TE 4
+#elif defined(NRF52)
+#define NUMBER_OF_GPIO_TE 8
+#else
+#error "Chip family not specified"
+#endif
+
+ /**
+ * @enum nrf_gpiote_polarity_t
+ * @brief Polarity for the GPIOTE channel.
+ */
+typedef enum
+{
+  NRF_GPIOTE_POLARITY_LOTOHI = GPIOTE_CONFIG_POLARITY_LoToHi,       ///<  Low to high.
+  NRF_GPIOTE_POLARITY_HITOLO = GPIOTE_CONFIG_POLARITY_HiToLo,       ///<  High to low.
+  NRF_GPIOTE_POLARITY_TOGGLE = GPIOTE_CONFIG_POLARITY_Toggle        ///<  Toggle.
+} nrf_gpiote_polarity_t;
+
+
+ /**
+ * @enum nrf_gpiote_outinit_t
+ * @brief Initial output value for the GPIOTE channel.
+ */
+typedef enum
+{
+  NRF_GPIOTE_INITIAL_VALUE_LOW  = GPIOTE_CONFIG_OUTINIT_Low,       ///<  Low to high.
+  NRF_GPIOTE_INITIAL_VALUE_HIGH = GPIOTE_CONFIG_OUTINIT_High       ///<  High to low.
+} nrf_gpiote_outinit_t;
+
+/**
+ * @brief Tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_GPIOTE_TASKS_OUT_0     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[0]), /**< Out task 0.*/
+    NRF_GPIOTE_TASKS_OUT_1     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[1]), /**< Out task 1.*/
+    NRF_GPIOTE_TASKS_OUT_2     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[2]), /**< Out task 2.*/
+    NRF_GPIOTE_TASKS_OUT_3     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[3]), /**< Out task 3.*/
+#if (NUMBER_OF_GPIO_TE == 8)
+    NRF_GPIOTE_TASKS_OUT_4     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[4]), /**< Out task 4.*/
+    NRF_GPIOTE_TASKS_OUT_5     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[5]), /**< Out task 5.*/
+    NRF_GPIOTE_TASKS_OUT_6     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[6]), /**< Out task 6.*/
+    NRF_GPIOTE_TASKS_OUT_7     = offsetof(NRF_GPIOTE_Type, TASKS_OUT[7]), /**< Out task 7.*/
+#endif
+#ifdef NRF52
+    NRF_GPIOTE_TASKS_SET_0     = offsetof(NRF_GPIOTE_Type, TASKS_SET[0]), /**< Set task 0.*/
+    NRF_GPIOTE_TASKS_SET_1     = offsetof(NRF_GPIOTE_Type, TASKS_SET[1]), /**< Set task 1.*/
+    NRF_GPIOTE_TASKS_SET_2     = offsetof(NRF_GPIOTE_Type, TASKS_SET[2]), /**< Set task 2.*/
+    NRF_GPIOTE_TASKS_SET_3     = offsetof(NRF_GPIOTE_Type, TASKS_SET[3]), /**< Set task 3.*/
+    NRF_GPIOTE_TASKS_SET_4     = offsetof(NRF_GPIOTE_Type, TASKS_SET[4]), /**< Set task 4.*/
+    NRF_GPIOTE_TASKS_SET_5     = offsetof(NRF_GPIOTE_Type, TASKS_SET[5]), /**< Set task 5.*/
+    NRF_GPIOTE_TASKS_SET_6     = offsetof(NRF_GPIOTE_Type, TASKS_SET[6]), /**< Set task 6.*/
+    NRF_GPIOTE_TASKS_SET_7     = offsetof(NRF_GPIOTE_Type, TASKS_SET[7]), /**< Set task 7.*/
+    NRF_GPIOTE_TASKS_CLR_0     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[0]), /**< Clear task 0.*/
+    NRF_GPIOTE_TASKS_CLR_1     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[1]), /**< Clear task 1.*/
+    NRF_GPIOTE_TASKS_CLR_2     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[2]), /**< Clear task 2.*/
+    NRF_GPIOTE_TASKS_CLR_3     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[3]), /**< Clear task 3.*/
+    NRF_GPIOTE_TASKS_CLR_4     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[4]), /**< Clear task 4.*/
+    NRF_GPIOTE_TASKS_CLR_5     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[5]), /**< Clear task 5.*/
+    NRF_GPIOTE_TASKS_CLR_6     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[6]), /**< Clear task 6.*/
+    NRF_GPIOTE_TASKS_CLR_7     = offsetof(NRF_GPIOTE_Type, TASKS_CLR[7]), /**< Clear task 7.*/
+#endif
+    /*lint -restore*/
+} nrf_gpiote_tasks_t;
+
+/**
+ * @brief Events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_GPIOTE_EVENTS_IN_0     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[0]), /**< In event 0.*/
+    NRF_GPIOTE_EVENTS_IN_1     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[1]), /**< In event 1.*/
+    NRF_GPIOTE_EVENTS_IN_2     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[2]), /**< In event 2.*/
+    NRF_GPIOTE_EVENTS_IN_3     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[3]), /**< In event 3.*/
+#if (NUMBER_OF_GPIO_TE == 8)
+    NRF_GPIOTE_EVENTS_IN_4     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[4]), /**< In event 4.*/
+    NRF_GPIOTE_EVENTS_IN_5     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[5]), /**< In event 5.*/
+    NRF_GPIOTE_EVENTS_IN_6     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[6]), /**< In event 6.*/
+    NRF_GPIOTE_EVENTS_IN_7     = offsetof(NRF_GPIOTE_Type, EVENTS_IN[7]), /**< In event 7.*/
+#endif
+    NRF_GPIOTE_EVENTS_PORT     = offsetof(NRF_GPIOTE_Type, EVENTS_PORT), /**<  Port event.*/
+    /*lint -restore*/
+} nrf_gpiote_events_t;
+
+/**
+ * @enum nrf_gpiote_int_t
+ * @brief GPIOTE interrupts.
+ */
+typedef enum
+{
+    NRF_GPIOTE_INT_IN0_MASK  = GPIOTE_INTENSET_IN0_Msk,  /**< GPIOTE interrupt from IN0. */
+    NRF_GPIOTE_INT_IN1_MASK  = GPIOTE_INTENSET_IN1_Msk,  /**< GPIOTE interrupt from IN1. */
+    NRF_GPIOTE_INT_IN2_MASK  = GPIOTE_INTENSET_IN2_Msk,  /**< GPIOTE interrupt from IN2. */
+    NRF_GPIOTE_INT_IN3_MASK  = GPIOTE_INTENSET_IN3_Msk,  /**< GPIOTE interrupt from IN3. */
+#if (NUMBER_OF_GPIO_TE == 8)
+    NRF_GPIOTE_INT_IN4_MASK  = GPIOTE_INTENSET_IN4_Msk,  /**< GPIOTE interrupt from IN4. */
+    NRF_GPIOTE_INT_IN5_MASK  = GPIOTE_INTENSET_IN5_Msk,  /**< GPIOTE interrupt from IN5. */
+    NRF_GPIOTE_INT_IN6_MASK  = GPIOTE_INTENSET_IN6_Msk,  /**< GPIOTE interrupt from IN6. */
+    NRF_GPIOTE_INT_IN7_MASK  = GPIOTE_INTENSET_IN7_Msk,  /**< GPIOTE interrupt from IN7. */
+#endif
+    NRF_GPIOTE_INT_PORT_MASK = (int)GPIOTE_INTENSET_PORT_Msk, /**< GPIOTE interrupt from PORT event. */
+} nrf_gpiote_int_t;
+
+#if (NUMBER_OF_GPIO_TE == 4)
+#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
+                                NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK)
+#elif (NUMBER_OF_GPIO_TE == 8)
+#define NRF_GPIOTE_INT_IN_MASK (NRF_GPIOTE_INT_IN0_MASK | NRF_GPIOTE_INT_IN1_MASK |\
+                                NRF_GPIOTE_INT_IN2_MASK | NRF_GPIOTE_INT_IN3_MASK |\
+                                NRF_GPIOTE_INT_IN4_MASK | NRF_GPIOTE_INT_IN5_MASK |\
+                                NRF_GPIOTE_INT_IN6_MASK | NRF_GPIOTE_INT_IN7_MASK)
+#else
+#error "Unexpected number of GPIO Tasks and Events"
+#endif
+/**
+ * @brief Function for activating a specific GPIOTE task.
+ *
+ * @param[in]  task Task.
+ */
+__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task);
+
+/**
+ * @brief Function for getting the address of a specific GPIOTE task.
+ *
+ * @param[in] task Task.
+ *
+ * @returns Address.
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task);
+
+/**
+ * @brief Function for getting the state of a specific GPIOTE event.
+ *
+ * @param[in] event Event.
+ */
+__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event);
+
+/**
+ * @brief Function for clearing a specific GPIOTE event.
+ *
+ * @param[in] event Event.
+ */
+__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event);
+
+/**
+ * @brief Function for getting the address of a specific GPIOTE event.
+ *
+ * @param[in] event Event.
+ *
+ * @return Address
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event);
+
+/**@brief Function for enabling interrupts.
+ *
+ * @param[in]  mask          Interrupt mask to be enabled.
+ */
+__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask);
+
+/**@brief Function for disabling interrupts.
+ *
+ * @param[in]  mask          Interrupt mask to be disabled.
+ */
+__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask);
+
+/**@brief Function for checking if interrupts are enabled.
+ *
+ * @param[in]  mask          Mask of interrupt flags to check.
+ *
+ * @return                   Mask with enabled interrupts.
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask);
+
+/**@brief Function for enabling a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx);
+
+/**@brief Function for disabling a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx);
+
+/**@brief Function for configuring a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ * @param[in]  pin        Pin associated with event.
+ * @param[in]  polarity   Transition that should generate an event.
+ */
+__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin,
+                                                nrf_gpiote_polarity_t polarity);
+
+/**@brief Function for getting the pin associated with a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ *
+ * @return Pin number.
+ */
+__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx);
+
+/**@brief Function for getting the polarity associated with a GPIOTE event.
+ *
+ * @param[in]  idx        Task-Event index.
+ *
+ * @return Polarity.
+ */
+__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx);
+
+/**@brief Function for enabling a GPIOTE task.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx);
+
+/**@brief Function for disabling a GPIOTE task.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx);
+
+/**@brief Function for configuring a GPIOTE task.
+ * @note  Function is not configuring mode field so task is disabled after this function is called.
+ *
+ * @param[in]  idx        Task-Event index.
+ * @param[in]  pin        Pin associated with event.
+ * @param[in]  polarity   Transition that should generate an event.
+ * @param[in]  init_val   Initial value of pin.
+ */
+__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
+                                               nrf_gpiote_polarity_t polarity,
+                                               nrf_gpiote_outinit_t  init_val);
+
+/**@brief Function for forcing a specific state on the pin connected to GPIOTE.
+ *
+ * @param[in]  idx        Task-Event index.
+ * @param[in]  init_val   Pin state.
+ */
+__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val);
+
+/**@brief Function for resetting a GPIOTE task event configuration to the default state.
+ *
+ * @param[in]  idx        Task-Event index.
+ */
+__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_gpiote_task_set(nrf_gpiote_tasks_t task)
+{
+    *(__IO uint32_t *)((uint32_t)NRF_GPIOTE + task) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_task_addr_get(nrf_gpiote_tasks_t task)
+{
+    return ((uint32_t)NRF_GPIOTE + task);
+}
+
+__STATIC_INLINE bool nrf_gpiote_event_is_set(nrf_gpiote_events_t event)
+{
+    return (*(uint32_t *)nrf_gpiote_event_addr_get(event) == 0x1UL) ? true : false;
+}
+
+__STATIC_INLINE void nrf_gpiote_event_clear(nrf_gpiote_events_t event)
+{
+    *(uint32_t *)nrf_gpiote_event_addr_get(event) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)nrf_gpiote_event_addr_get(event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_event_addr_get(nrf_gpiote_events_t event)
+{
+    return ((uint32_t)NRF_GPIOTE + event);
+}
+
+__STATIC_INLINE void nrf_gpiote_int_enable(uint32_t mask)
+{
+    NRF_GPIOTE->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_gpiote_int_disable(uint32_t mask)
+{
+    NRF_GPIOTE->INTENCLR = mask;
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_int_is_enabled(uint32_t mask)
+{
+    return (NRF_GPIOTE->INTENSET & mask);
+}
+
+__STATIC_INLINE void nrf_gpiote_event_enable(uint32_t idx)
+{
+   NRF_GPIOTE->CONFIG[idx] |= GPIOTE_CONFIG_MODE_Event;
+}
+
+__STATIC_INLINE void nrf_gpiote_event_disable(uint32_t idx)
+{
+   NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Event;
+}
+
+__STATIC_INLINE void nrf_gpiote_event_configure(uint32_t idx, uint32_t pin, nrf_gpiote_polarity_t polarity)
+{
+  NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PSEL_Msk | GPIOTE_CONFIG_POLARITY_Msk);
+  NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) |
+                              ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk);
+}
+
+__STATIC_INLINE uint32_t nrf_gpiote_event_pin_get(uint32_t idx)
+{
+    return ((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_PSEL_Msk) >> GPIOTE_CONFIG_PSEL_Pos);
+}
+
+__STATIC_INLINE nrf_gpiote_polarity_t nrf_gpiote_event_polarity_get(uint32_t idx)
+{
+    return (nrf_gpiote_polarity_t)((NRF_GPIOTE->CONFIG[idx] & GPIOTE_CONFIG_POLARITY_Msk) >> GPIOTE_CONFIG_POLARITY_Pos);
+}
+
+__STATIC_INLINE void nrf_gpiote_task_enable(uint32_t idx)
+{
+    uint32_t final_config = NRF_GPIOTE->CONFIG[idx] | GPIOTE_CONFIG_MODE_Task;
+    /* Workaround for the OUTINIT PAN. When nrf_gpiote_task_config() is called a glitch happens
+    on the GPIO if the GPIO in question is already assigned to GPIOTE and the pin is in the
+    correct state in GPIOTE but not in the OUT register. */
+    /* Configure channel to Pin31, not connected to the pin, and configure as a tasks that will set it to proper level */
+    NRF_GPIOTE->CONFIG[idx] = final_config | ((31 << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk);
+    __NOP();
+    __NOP();
+    __NOP();
+    NRF_GPIOTE->CONFIG[idx] = final_config;
+}
+
+__STATIC_INLINE void nrf_gpiote_task_disable(uint32_t idx)
+{
+    NRF_GPIOTE->CONFIG[idx] &= ~GPIOTE_CONFIG_MODE_Task;
+}
+
+__STATIC_INLINE void nrf_gpiote_task_configure(uint32_t idx, uint32_t pin,
+                                                nrf_gpiote_polarity_t polarity,
+                                                nrf_gpiote_outinit_t  init_val)
+{
+  NRF_GPIOTE->CONFIG[idx] &= ~(GPIOTE_CONFIG_PSEL_Msk |
+                               GPIOTE_CONFIG_POLARITY_Msk |
+                               GPIOTE_CONFIG_OUTINIT_Msk);
+
+  NRF_GPIOTE->CONFIG[idx] |= ((pin << GPIOTE_CONFIG_PSEL_Pos) & GPIOTE_CONFIG_PSEL_Msk) |
+                             ((polarity << GPIOTE_CONFIG_POLARITY_Pos) & GPIOTE_CONFIG_POLARITY_Msk) |
+                             ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
+}
+
+__STATIC_INLINE void nrf_gpiote_task_force(uint32_t idx, nrf_gpiote_outinit_t init_val)
+{
+    NRF_GPIOTE->CONFIG[idx] = (NRF_GPIOTE->CONFIG[idx] & ~GPIOTE_CONFIG_OUTINIT_Msk) 
+                              | ((init_val << GPIOTE_CONFIG_OUTINIT_Pos) & GPIOTE_CONFIG_OUTINIT_Msk);
+}
+
+__STATIC_INLINE void nrf_gpiote_te_default(uint32_t idx)
+{
+    NRF_GPIOTE->CONFIG[idx] = 0;
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.c
new file mode 100644
index 0000000000..de2a52db8c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.c
@@ -0,0 +1,143 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+ 
+
+/** 
+ *@file
+ *@brief NMVC driver implementation 
+ */
+
+#include <stdbool.h>
+#include "nrf.h"
+#include "nrf_nvmc.h"
+
+
+void nrf_nvmc_page_erase(uint32_t address)
+{ 
+  // Enable erase.
+  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Een;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+
+  // Erase the page
+  NRF_NVMC->ERASEPAGE = address;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+  
+  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+}
+
+
+void nrf_nvmc_write_byte(uint32_t address, uint8_t value)
+{
+  uint32_t byte_shift = address & (uint32_t)0x03;
+  uint32_t address32 = address & ~byte_shift; // Address to the word this byte is in.
+  uint32_t value32 = (*(uint32_t*)address32 & ~((uint32_t)0xFF << (byte_shift << (uint32_t)3)));
+  value32 = value32 + ((uint32_t)value << (byte_shift << 3));
+
+  // Enable write.
+  NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Wen << NVMC_CONFIG_WEN_Pos);
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+
+  *(uint32_t*)address32 = value32;
+  while(NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+
+  NRF_NVMC->CONFIG = (NVMC_CONFIG_WEN_Ren << NVMC_CONFIG_WEN_Pos);
+  {
+  }
+}
+
+void nrf_nvmc_write_word(uint32_t address, uint32_t value)
+{
+  // Enable write.
+  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
+  }
+
+  *(uint32_t*)address = value;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy){
+  }
+
+  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+}
+
+void nrf_nvmc_write_bytes(uint32_t address, const uint8_t * src, uint32_t num_bytes)
+{
+  uint32_t i;
+  for(i=0;i<num_bytes;i++)
+  {
+     nrf_nvmc_write_byte(address+i,src[i]);
+  }
+}
+
+void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words)
+{
+  uint32_t i;
+
+  // Enable write.
+  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Wen;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+
+  for(i=0;i<num_words;i++)
+  {
+    ((uint32_t*)address)[i] = src[i];
+    while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+    {
+    }
+  }
+
+  NRF_NVMC->CONFIG = NVMC_CONFIG_WEN_Ren;
+  while (NRF_NVMC->READY == NVMC_READY_READY_Busy)
+  {
+  }
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.h
new file mode 100644
index 0000000000..59b23f1845
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_nvmc.h
@@ -0,0 +1,116 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file
+ * @brief NMVC driver API.
+ */
+
+#ifndef NRF_NVMC_H__
+#define NRF_NVMC_H__
+
+#include <stdint.h>
+
+
+/**
+ * @defgroup nrf_nvmc Non-volatile memory controller
+ * @{
+ * @ingroup nrf_drivers
+ * @brief Driver for the NVMC peripheral.
+ *
+ * This driver allows writing to the non-volatile memory (NVM) regions
+ * of the chip. In order to write to NVM the controller must be powered
+ * on and the relevant page must be erased.
+ *
+ */
+
+
+/**
+ * @brief Erase a page in flash. This is required before writing to any
+ * address in the page.
+ *
+ * @param address Start address of the page. 
+ */
+void nrf_nvmc_page_erase(uint32_t address);
+
+
+/**
+ * @brief Write a single byte to flash.
+ *
+ * The function reads the word containing the byte, and then
+ * rewrites the entire word.
+ *
+ * @param address Address to write to.
+ * @param value   Value to write.
+ */
+void nrf_nvmc_write_byte(uint32_t address , uint8_t value);
+
+
+/**
+ * @brief Write a 32-bit word to flash. 
+ * @param address Address to write to.
+ * @param value   Value to write.
+ */
+void nrf_nvmc_write_word(uint32_t address, uint32_t value);
+
+
+/**
+ * @brief Write consecutive bytes to flash.
+ *
+ * @param address   Address to write to.
+ * @param src       Pointer to data to copy from.
+ * @param num_bytes Number of bytes in src to write.
+ */
+void nrf_nvmc_write_bytes(uint32_t  address, const uint8_t * src, uint32_t num_bytes);
+
+
+/**
+ * @brief Write consecutive words to flash.
+ * 
+ * @param address   Address to write to.
+ * @param src       Pointer to data to copy from.
+ * @param num_words Number of bytes in src to write.
+ */
+void nrf_nvmc_write_words(uint32_t address, const uint32_t * src, uint32_t num_words);
+
+
+#endif // NRF_NVMC_H__
+/** @} */
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pdm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pdm.h
new file mode 100644
index 0000000000..be41fdfae0
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pdm.h
@@ -0,0 +1,386 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef NRF_PDM_H_
+#define NRF_PDM_H_
+
+/**
+ * @defgroup nrf_pdm_hal PDM HAL
+ * @{
+ * @ingroup nrf_pdm
+ *
+ * @brief @tagAPI52 Hardware abstraction layer for accessing the pulse density modulation (PDM) peripheral.
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+
+
+#define NRF_PDM_GAIN_MINIMUM  0x00
+#define NRF_PDM_GAIN_DEFAULT  0x28
+#define NRF_PDM_GAIN_MAXIMUM  0x50
+
+typedef uint8_t nrf_pdm_gain_t;
+
+
+/**
+ * @brief PDM tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_PDM_TASK_START           = offsetof(NRF_PDM_Type, TASKS_START),           ///< Starts continuous PDM transfer.
+    NRF_PDM_TASK_STOP            = offsetof(NRF_PDM_Type, TASKS_STOP)             ///< Stops PDM transfer.
+} nrf_pdm_task_t;
+
+
+/**
+ * @brief PDM events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_PDM_EVENT_STARTED       = offsetof(NRF_PDM_Type, EVENTS_STARTED),       ///< PDM transfer has started.
+    NRF_PDM_EVENT_STOPPED       = offsetof(NRF_PDM_Type, EVENTS_STOPPED),       ///< PDM transfer has finished.
+    NRF_PDM_EVENT_END           = offsetof(NRF_PDM_Type, EVENTS_END)            ///< The PDM has written the last sample specified by SAMPLE.MAXCNT (or the last sample after a STOP task has been received) to Data RAM.
+} nrf_pdm_event_t;
+
+
+/**
+ * @brief PDM interrupt masks.
+ */
+typedef enum
+{
+    NRF_PDM_INT_STARTED = PDM_INTENSET_STARTED_Msk,   ///< Interrupt on EVENTS_STARTED event.
+    NRF_PDM_INT_STOPPED = PDM_INTENSET_STOPPED_Msk,   ///< Interrupt on EVENTS_STOPPED event.
+    NRF_PDM_INT_END     = PDM_INTENSET_END_Msk        ///< Interrupt on EVENTS_END event.
+} nrf_pdm_int_mask_t;
+
+/**
+ * @brief PDM clock frequency.
+ */
+typedef enum
+{
+    NRF_PDM_FREQ_1000K = PDM_PDMCLKCTRL_FREQ_1000K,  ///< PDM_CLK = 1.000 MHz.
+    NRF_PDM_FREQ_1032K = PDM_PDMCLKCTRL_FREQ_Default,  ///< PDM_CLK = 1.032 MHz.
+    NRF_PDM_FREQ_1067K = PDM_PDMCLKCTRL_FREQ_1067K   ///< PDM_CLK = 1.067 MHz.
+} nrf_pdm_freq_t;
+
+
+/**
+ * @brief PDM operation mode.
+ */
+typedef enum
+{
+    NRF_PDM_MODE_STEREO = PDM_MODE_OPERATION_Stereo,  ///< Sample and store one pair (Left + Right) of 16-bit samples per RAM word.
+    NRF_PDM_MODE_MONO   = PDM_MODE_OPERATION_Mono     ///< Sample and store two successive Left samples (16 bit each) per RAM word.
+} nrf_pdm_mode_t;
+
+
+/**
+ * @brief PDM sampling mode.
+ */
+typedef enum
+{
+    NRF_PDM_EDGE_LEFTFALLING = PDM_MODE_EDGE_LeftFalling,  ///< Left (or mono) is sampled on falling edge of PDM_CLK.
+    NRF_PDM_EDGE_LEFTRISING  = PDM_MODE_EDGE_LeftRising    ///< Left (or mono) is sampled on rising edge of PDM_CLK.
+} nrf_pdm_edge_t;
+
+
+/**
+ * @brief Function for triggering a PDM task.
+ *
+ * @param[in] pdm_task PDM task.
+ */
+__STATIC_INLINE void nrf_pdm_task_trigger(nrf_pdm_task_t pdm_task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_task)) = 0x1UL;
+}
+
+
+/**
+ * @brief Function for getting the address of a PDM task register.
+ *
+ * @param[in] pdm_task PDM task.
+ *
+ * @return Address of the specified PDM task.
+ */
+__STATIC_INLINE uint32_t nrf_pdm_task_address_get(nrf_pdm_task_t pdm_task)
+{
+    return (uint32_t)((uint8_t *)NRF_PDM + (uint32_t)pdm_task);
+}
+
+
+/**
+ * @brief Function for getting the state of a PDM event.
+ *
+ * @param[in] pdm_event PDM event.
+ *
+ * @return State of the specified PDM event.
+ */
+__STATIC_INLINE bool nrf_pdm_event_check(nrf_pdm_event_t pdm_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
+}
+
+
+/**
+ * @brief Function for clearing a PDM event.
+ *
+ * @param[in] pdm_event PDM event.
+ */
+__STATIC_INLINE void nrf_pdm_event_clear(nrf_pdm_event_t pdm_event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event)) = 0x0UL;
+}
+
+
+/**
+ * @brief Function for getting the address of a PDM event register.
+ *
+ * @param[in] pdm_event PDM event.
+ *
+ * @return Address of the specified PDM event.
+ */
+__STATIC_INLINE volatile uint32_t * nrf_pdm_event_address_get(nrf_pdm_event_t pdm_event)
+{
+    return (volatile uint32_t *)((uint8_t *)NRF_PDM + (uint32_t)pdm_event);
+}
+
+
+/**
+ * @brief Function for enabling PDM interrupts.
+ *
+ * @param[in] pdm_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_pdm_int_enable(uint32_t pdm_int_mask)
+{
+    NRF_PDM->INTENSET = pdm_int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of PDM interrupts.
+ *
+ * @param[in] pdm_int_mask Interrupts to check.
+ *
+ * @retval true  If all specified interrupts are enabled.
+ * @retval false If at least one of the given interrupts is not enabled.
+ */
+__STATIC_INLINE bool nrf_pdm_int_enable_check(uint32_t pdm_int_mask)
+{
+    return (bool)(NRF_PDM->INTENSET & pdm_int_mask);
+}
+
+
+/**
+ * @brief Function for disabling interrupts.
+ *
+ * @param pdm_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_pdm_int_disable(uint32_t pdm_int_mask)
+{
+    NRF_PDM->INTENCLR = pdm_int_mask;
+}
+
+
+/**
+ * @brief Function for enabling the PDM peripheral.
+ *
+ * The PDM peripheral must be enabled before use.
+ */
+__STATIC_INLINE void nrf_pdm_enable(void)
+{
+    NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for disabling the PDM peripheral.
+ */
+__STATIC_INLINE void nrf_pdm_disable(void)
+{
+    NRF_PDM->ENABLE = (PDM_ENABLE_ENABLE_Disabled << PDM_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for checking if the PDM peripheral is enabled.
+ *
+ * @retval true  If the PDM peripheral is enabled.
+ * @retval false If the PDM peripheral is not enabled.
+ */
+__STATIC_INLINE bool nrf_pdm_enable_check(void)
+{
+    return (NRF_PDM->ENABLE == (PDM_ENABLE_ENABLE_Enabled << PDM_ENABLE_ENABLE_Pos));
+}
+
+
+/**
+ * @brief Function for setting the PDM operation mode.
+ *
+ * @param[in] pdm_mode PDM operation mode.
+ * @param[in] pdm_edge PDM sampling mode.
+ */
+__STATIC_INLINE void nrf_pdm_mode_set(nrf_pdm_mode_t pdm_mode, nrf_pdm_edge_t pdm_edge)
+{
+    NRF_PDM->MODE = ((pdm_mode << PDM_MODE_OPERATION_Pos) & PDM_MODE_OPERATION_Msk)
+                    | ((pdm_edge << PDM_MODE_EDGE_Pos) & PDM_MODE_EDGE_Msk);
+}
+
+
+/**
+ * @brief Function for getting the PDM operation mode.
+ *
+ * @param[out] p_pdm_mode PDM operation mode.
+ * @param[out] p_pdm_edge PDM sampling mode.
+ */
+__STATIC_INLINE void nrf_pdm_mode_get(nrf_pdm_mode_t * p_pdm_mode, nrf_pdm_edge_t * p_pdm_edge)
+{
+    uint32_t mode = NRF_PDM->MODE;
+    *p_pdm_mode = (nrf_pdm_mode_t)((mode & PDM_MODE_OPERATION_Msk ) >> PDM_MODE_OPERATION_Pos);
+    *p_pdm_edge = (nrf_pdm_edge_t)((mode & PDM_MODE_EDGE_Msk ) >> PDM_MODE_EDGE_Pos);
+}
+
+
+/**
+ * @brief Function for setting the PDM clock frequency.
+ *
+ * @param[in] pdm_freq PDM clock frequency.
+ */
+__STATIC_INLINE void nrf_pdm_clock_set(nrf_pdm_freq_t pdm_freq)
+{
+    NRF_PDM->PDMCLKCTRL = ((pdm_freq << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
+}
+
+
+/**
+ * @brief Function for getting the PDM clock frequency.
+ */
+__STATIC_INLINE nrf_pdm_freq_t nrf_pdm_clock_get(void)
+{
+     return (nrf_pdm_freq_t) ((NRF_PDM->PDMCLKCTRL << PDM_PDMCLKCTRL_FREQ_Pos) & PDM_PDMCLKCTRL_FREQ_Msk);
+}
+
+
+/**
+ * @brief Function for setting up the PDM pins.
+ *
+ * @param[in] psel_clk CLK pin number.
+ * @param[in] psel_din DIN pin number.
+ */
+__STATIC_INLINE void nrf_pdm_psel_connect(uint32_t psel_clk, uint32_t psel_din)
+{
+    NRF_PDM->PSEL.CLK = ((psel_clk << PDM_PSEL_CLK_PIN_Pos) & PDM_PSEL_CLK_PIN_Msk)
+            | ((PDM_PSEL_CLK_CONNECT_Connected << PDM_PSEL_CLK_CONNECT_Pos) & PDM_PSEL_CLK_CONNECT_Msk);
+    NRF_PDM->PSEL.DIN = ((psel_din << PDM_PSEL_DIN_PIN_Pos) & PDM_PSEL_DIN_PIN_Msk)
+            | ((PDM_PSEL_DIN_CONNECT_Connected << PDM_PSEL_CLK_CONNECT_Pos) & PDM_PSEL_DIN_CONNECT_Msk);
+}
+
+/**
+ * @brief Function for disconnecting the PDM pins.
+ */
+__STATIC_INLINE void nrf_pdm_psel_disconnect()
+{
+    NRF_PDM->PSEL.CLK = ((PDM_PSEL_CLK_CONNECT_Disconnected << PDM_PSEL_CLK_CONNECT_Pos) 
+                         & PDM_PSEL_CLK_CONNECT_Msk);
+    NRF_PDM->PSEL.DIN = ((PDM_PSEL_DIN_CONNECT_Disconnected << PDM_PSEL_DIN_CONNECT_Pos) 
+                         & PDM_PSEL_DIN_CONNECT_Msk);
+}
+
+
+/**
+ * @brief Function for setting the PDM gain.
+ *
+ * @param[in] gain_l Left channel gain.
+ * @param[in] gain_r Right channel gain.
+ */
+__STATIC_INLINE void nrf_pdm_gain_set(nrf_pdm_gain_t gain_l, nrf_pdm_gain_t gain_r)
+{
+    NRF_PDM->GAINL = gain_l;
+    NRF_PDM->GAINR = gain_r;
+}
+
+
+/**
+ * @brief Function for getting the PDM gain.
+ *
+ * @param[out] p_gain_l Left channel gain.
+ * @param[out] p_gain_r Right channel gain.
+ */
+__STATIC_INLINE void nrf_pdm_gain_get(nrf_pdm_gain_t * p_gain_l, nrf_pdm_gain_t * p_gain_r)
+{
+    *p_gain_l = NRF_PDM->GAINL;
+    *p_gain_r = NRF_PDM->GAINR;
+}
+
+
+/**
+ * @brief Function for setting the PDM sample buffer.
+ *
+ * @param[in] p_buffer Pointer to the RAM address where samples should be written with EasyDMA.
+ * @param[in] num    Number of samples to allocate memory for in EasyDMA mode.
+ *
+ * The amount of allocated RAM depends on the operation mode.
+ * - For stereo mode: N 32-bit words.
+ * - For mono mode: Ceil(N/2) 32-bit words.
+ */
+__STATIC_INLINE void nrf_pdm_buffer_set(uint32_t * p_buffer, uint32_t num)
+{
+    NRF_PDM->SAMPLE.PTR = (uint32_t)p_buffer;
+    NRF_PDM->SAMPLE.MAXCNT = num;
+}
+
+/**
+ * @brief Function for getting the current PDM sample buffer address.
+ *
+ * @return Pointer to the current sample buffer.
+ */
+__STATIC_INLINE uint32_t * nrf_pdm_buffer_get()
+{
+    return (uint32_t *)NRF_PDM->SAMPLE.PTR;
+}
+
+
+/**
+ *@}
+ **/
+
+#endif /* NRF_PDM_H_ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ppi.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ppi.h
new file mode 100644
index 0000000000..b501240fef
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_ppi.h
@@ -0,0 +1,429 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_PPI_H__
+#define NRF_PPI_H__
+
+#include <stddef.h>
+#include "nrf.h"
+
+/**
+ * @defgroup nrf_ppi_hal PPI HAL
+ * @{
+ * @ingroup nrf_ppi
+ * @brief Hardware access layer for setting up Programmable Peripheral Interconnect (PPI) channels.
+ */
+
+#define NRF_PPI_TASK_SET    (1UL)
+
+/**
+ * @enum nrf_ppi_channel_t
+ * @brief PPI channels.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL0  = PPI_CHEN_CH0_Pos,  /**< Channel 0. */
+    NRF_PPI_CHANNEL1  = PPI_CHEN_CH1_Pos,  /**< Channel 1. */
+    NRF_PPI_CHANNEL2  = PPI_CHEN_CH2_Pos,  /**< Channel 2. */
+    NRF_PPI_CHANNEL3  = PPI_CHEN_CH3_Pos,  /**< Channel 3. */
+    NRF_PPI_CHANNEL4  = PPI_CHEN_CH4_Pos,  /**< Channel 4. */
+    NRF_PPI_CHANNEL5  = PPI_CHEN_CH5_Pos,  /**< Channel 5. */
+    NRF_PPI_CHANNEL6  = PPI_CHEN_CH6_Pos,  /**< Channel 6. */
+    NRF_PPI_CHANNEL7  = PPI_CHEN_CH7_Pos,  /**< Channel 7. */
+    NRF_PPI_CHANNEL8  = PPI_CHEN_CH8_Pos,  /**< Channel 8. */
+    NRF_PPI_CHANNEL9  = PPI_CHEN_CH9_Pos,  /**< Channel 9. */
+    NRF_PPI_CHANNEL10 = PPI_CHEN_CH10_Pos, /**< Channel 10. */
+    NRF_PPI_CHANNEL11 = PPI_CHEN_CH11_Pos, /**< Channel 11. */
+    NRF_PPI_CHANNEL12 = PPI_CHEN_CH12_Pos, /**< Channel 12. */
+    NRF_PPI_CHANNEL13 = PPI_CHEN_CH13_Pos, /**< Channel 13. */
+    NRF_PPI_CHANNEL14 = PPI_CHEN_CH14_Pos, /**< Channel 14. */
+    NRF_PPI_CHANNEL15 = PPI_CHEN_CH15_Pos, /**< Channel 15. */
+#ifdef NRF52
+    NRF_PPI_CHANNEL16 = PPI_CHEN_CH16_Pos, /**< Channel 16. */
+    NRF_PPI_CHANNEL17 = PPI_CHEN_CH17_Pos, /**< Channel 17. */
+    NRF_PPI_CHANNEL18 = PPI_CHEN_CH18_Pos, /**< Channel 18. */
+    NRF_PPI_CHANNEL19 = PPI_CHEN_CH19_Pos, /**< Channel 19. */
+#endif
+    NRF_PPI_CHANNEL20 = PPI_CHEN_CH20_Pos, /**< Channel 20. */
+    NRF_PPI_CHANNEL21 = PPI_CHEN_CH21_Pos, /**< Channel 21. */
+    NRF_PPI_CHANNEL22 = PPI_CHEN_CH22_Pos, /**< Channel 22. */
+    NRF_PPI_CHANNEL23 = PPI_CHEN_CH23_Pos, /**< Channel 23. */
+    NRF_PPI_CHANNEL24 = PPI_CHEN_CH24_Pos, /**< Channel 24. */
+    NRF_PPI_CHANNEL25 = PPI_CHEN_CH25_Pos, /**< Channel 25. */
+    NRF_PPI_CHANNEL26 = PPI_CHEN_CH26_Pos, /**< Channel 26. */
+    NRF_PPI_CHANNEL27 = PPI_CHEN_CH27_Pos, /**< Channel 27. */
+    NRF_PPI_CHANNEL28 = PPI_CHEN_CH28_Pos, /**< Channel 28. */
+    NRF_PPI_CHANNEL29 = PPI_CHEN_CH29_Pos, /**< Channel 29. */
+    NRF_PPI_CHANNEL30 = PPI_CHEN_CH30_Pos, /**< Channel 30. */
+    NRF_PPI_CHANNEL31 = PPI_CHEN_CH31_Pos  /**< Channel 31. */
+} nrf_ppi_channel_t;
+
+/**
+ * @enum nrf_ppi_channel_group_t
+ * @brief PPI channel groups.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL_GROUP0 = 0, /**< Channel group 0. */
+    NRF_PPI_CHANNEL_GROUP1 = 1, /**< Channel group 1. */
+    NRF_PPI_CHANNEL_GROUP2 = 2, /**< Channel group 2. */
+    NRF_PPI_CHANNEL_GROUP3 = 3, /**< Channel group 3. */
+#ifdef NRF52
+    NRF_PPI_CHANNEL_GROUP4 = 4, /**< Channel group 4. */
+    NRF_PPI_CHANNEL_GROUP5 = 5  /**< Channel group 5. */
+#endif
+} nrf_ppi_channel_group_t;
+
+/**
+ * @enum nrf_ppi_channel_include_t
+ * @brief Definition of which PPI channels belong to a group.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL_EXCLUDE = PPI_CHG_CH0_Excluded, /**< Channel excluded from a group. */
+    NRF_PPI_CHANNEL_INCLUDE = PPI_CHG_CH0_Included  /**< Channel included in a group. */
+} nrf_ppi_channel_include_t;
+
+/**
+ * @enum nrf_ppi_channel_enable_t
+ * @brief Definition if a PPI channel is enabled.
+ */
+typedef enum
+{
+    NRF_PPI_CHANNEL_DISABLED = PPI_CHEN_CH0_Disabled, /**< Channel disabled. */
+    NRF_PPI_CHANNEL_ENABLED  = PPI_CHEN_CH0_Enabled   /**< Channel enabled. */
+} nrf_ppi_channel_enable_t;
+
+/**
+ * @enum nrf_ppi_task_t
+ * @brief PPI tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_PPI_TASK_CHG0_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[0].EN),  /**< Task for enabling channel group 0 */
+    NRF_PPI_TASK_CHG0_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[0].DIS), /**< Task for disabling channel group 0 */
+    NRF_PPI_TASK_CHG1_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[1].EN),  /**< Task for enabling channel group 1 */
+    NRF_PPI_TASK_CHG1_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[1].DIS), /**< Task for disabling channel group 1 */
+    NRF_PPI_TASK_CHG2_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[2].EN),  /**< Task for enabling channel group 2 */
+    NRF_PPI_TASK_CHG2_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[2].DIS), /**< Task for disabling channel group 2 */
+    NRF_PPI_TASK_CHG3_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[3].EN),  /**< Task for enabling channel group 3 */
+    NRF_PPI_TASK_CHG3_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[3].DIS), /**< Task for disabling channel group 3 */
+#ifdef NRF52
+    NRF_PPI_TASK_CHG4_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[4].EN),  /**< Task for enabling channel group 4 */
+    NRF_PPI_TASK_CHG4_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[4].DIS), /**< Task for disabling channel group 4 */
+    NRF_PPI_TASK_CHG5_EN  = offsetof(NRF_PPI_Type, TASKS_CHG[5].EN),  /**< Task for enabling channel group 5 */
+    NRF_PPI_TASK_CHG5_DIS = offsetof(NRF_PPI_Type, TASKS_CHG[5].DIS)  /**< Task for disabling channel group 5 */
+#endif
+    /*lint -restore*/
+} nrf_ppi_task_t;
+
+/**
+ * @brief Function for enabling a given PPI channel.
+ *
+ * @details This function enables only one channel.
+ *
+ * @param[in] channel Channel to enable.
+ *
+ *  */
+__STATIC_INLINE void nrf_ppi_channel_enable(nrf_ppi_channel_t channel)
+{
+    NRF_PPI->CHENSET = PPI_CHENSET_CH0_Set << ((uint32_t) channel);
+}
+
+
+/**
+ * @brief Function for disabling a given PPI channel.
+ *
+ * @details This function disables only one channel.
+ *
+ * @param[in] channel Channel to disable.
+ */
+__STATIC_INLINE void nrf_ppi_channel_disable(nrf_ppi_channel_t channel)
+{
+    NRF_PPI->CHENCLR = PPI_CHENCLR_CH0_Clear << ((uint32_t) channel);
+}
+
+
+/**
+ * @brief Function for checking if a given PPI channel is enabled.
+ *
+ * @details This function checks only one channel.
+ *
+ * @param[in] channel Channel to check.
+ *
+ * @retval     NRF_PPI_CHANNEL_ENABLED     If the channel is enabled.
+ * @retval     NRF_PPI_CHANNEL_DISABLED    If the channel is not enabled.
+ *
+ */
+__STATIC_INLINE nrf_ppi_channel_enable_t nrf_ppi_channel_enable_get(nrf_ppi_channel_t channel)
+{
+    if (NRF_PPI->CHEN & (PPI_CHEN_CH0_Msk << ((uint32_t) channel)))
+    {
+        return NRF_PPI_CHANNEL_ENABLED;
+    }
+    else
+    {
+        return NRF_PPI_CHANNEL_DISABLED;
+    }
+}
+
+
+/**
+ * @brief Function for disabling all PPI channels.
+ */
+__STATIC_INLINE void nrf_ppi_channel_disable_all(void)
+{
+    NRF_PPI->CHENCLR = ((uint32_t)0xFFFFFFFFuL);
+}
+
+/**
+ * @brief Function for disabling multiple PPI channels.
+ *
+ * @param[in] mask Channel mask.
+ */
+__STATIC_INLINE void nrf_ppi_channels_disable(uint32_t mask)
+{
+    NRF_PPI->CHENCLR = mask;
+}
+
+/**
+ * @brief Function for setting up event and task endpoints for a given PPI channel.
+ *
+ * @param[in] eep Event register address.
+ *
+ * @param[in] tep Task register address.
+ *
+ * @param[in] channel Channel to which the given endpoints are assigned.
+ */
+__STATIC_INLINE void nrf_ppi_channel_endpoint_setup(nrf_ppi_channel_t channel,
+                                                    uint32_t          eep,
+                                                    uint32_t          tep)
+{
+    NRF_PPI->CH[(uint32_t) channel].EEP = eep;
+    NRF_PPI->CH[(uint32_t) channel].TEP = tep;
+}
+
+#ifdef NRF52
+/**
+ * @brief Function for setting up task endpoint for a given PPI fork.
+ *
+ * @param[in] fork_tep Task register address.
+ *
+ * @param[in] channel Channel to which the given fork endpoint is assigned.
+ */
+__STATIC_INLINE void nrf_ppi_fork_endpoint_setup(nrf_ppi_channel_t channel,
+                                                 uint32_t          fork_tep)
+{
+    NRF_PPI->FORK[(uint32_t) channel].TEP = fork_tep;
+}
+
+/**
+ * @brief Function for setting up event and task endpoints for a given PPI channel and fork.
+ *
+ * @param[in] eep Event register address.
+ *
+ * @param[in] tep Task register address.
+ *
+ * @param[in] fork_tep Fork task register address (register value).
+ *
+ * @param[in] channel Channel to which the given endpoints are assigned.
+ */
+__STATIC_INLINE void nrf_ppi_channel_and_fork_endpoint_setup(nrf_ppi_channel_t channel,
+                                                             uint32_t          eep,
+                                                             uint32_t          tep,
+                                                             uint32_t          fork_tep)
+{
+    nrf_ppi_channel_endpoint_setup(channel, eep, tep);
+    nrf_ppi_fork_endpoint_setup(channel, fork_tep);
+}
+#endif
+
+/**
+ * @brief Function for including a PPI channel in a channel group.
+ *
+ * @details This function adds only one channel to the group.
+ *
+ * @param[in] channel       Channel to be included in the group.
+ *
+ * @param[in] channel_group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_channel_include_in_group(nrf_ppi_channel_t       channel,
+                                                      nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] | (PPI_CHG_CH0_Included << ((uint32_t)  channel));
+}
+
+/**
+ * @brief Function for including multiple PPI channels in a channel group.
+ *
+ * @details This function adds all specified channels to the group.
+ *
+ * @param[in] channel_mask  Channels to be included in the group.
+ *
+ * @param[in] channel_group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_channels_include_in_group(uint32_t                channel_mask,
+                                                       nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] | (channel_mask);
+}
+
+
+/**
+ * @brief Function for removing a PPI channel from a channel group.
+ *
+ * @details This function removes only one channel from the group.
+ *
+ * @param[in] channel       Channel to be removed from the group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrf_ppi_channel_remove_from_group(nrf_ppi_channel_t       channel,
+                                                       nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] & ~(PPI_CHG_CH0_Included << ((uint32_t) channel));
+}
+
+/**
+ * @brief Function for removing multiple PPI channels from a channel group.
+ *
+ * @details This function removes all specified channels from the group.
+ *
+ * @param[in] channel_mask  Channels to be removed from the group.
+ *
+ * @param[in] channel_group Channel group.
+ */
+__STATIC_INLINE void nrf_ppi_channels_remove_from_group(uint32_t                channel_mask,
+                                                        nrf_ppi_channel_group_t channel_group)
+{
+    NRF_PPI->CHG[(uint32_t) channel_group] =
+        NRF_PPI->CHG[(uint32_t) channel_group] & ~(channel_mask);
+}
+
+
+/**
+ * @brief Function for removing all PPI channels from a channel group.
+ *
+ * @param[in] group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_channel_group_clear(nrf_ppi_channel_group_t group)
+{
+    NRF_PPI->CHG[(uint32_t) group] = 0;
+}
+
+
+/**
+ * @brief Function for enabling a channel group.
+ *
+ * @param[in] group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_group_enable(nrf_ppi_channel_group_t group)
+{
+    NRF_PPI->TASKS_CHG[(uint32_t) group].EN = NRF_PPI_TASK_SET;
+}
+
+
+/**
+ * @brief Function for disabling a channel group.
+ *
+ * @param[in] group Channel group.
+ *
+ */
+__STATIC_INLINE void nrf_ppi_group_disable(nrf_ppi_channel_group_t group)
+{
+    NRF_PPI->TASKS_CHG[(uint32_t) group].DIS = NRF_PPI_TASK_SET;
+}
+
+
+/**
+ * @brief Function for setting a PPI task.
+ *
+ * @param[in] ppi_task PPI task to set.
+ */
+__STATIC_INLINE void nrf_ppi_task_trigger(nrf_ppi_task_t ppi_task)
+{
+    *((volatile uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task)) = NRF_PPI_TASK_SET;
+}
+
+
+/**
+ * @brief Function for returning the address of a specific PPI task register.
+ *
+ * @param[in] ppi_task PPI task.
+ */
+__STATIC_INLINE uint32_t * nrf_ppi_task_address_get(nrf_ppi_task_t ppi_task)
+{
+    return (uint32_t *) ((uint8_t *) NRF_PPI_BASE + (uint32_t) ppi_task);
+}
+
+/**
+ * @brief Function for returning the PPI enable task address of a specific group.
+ *
+ * @param[in] group  PPI group.
+ */
+__STATIC_INLINE uint32_t * nrf_ppi_task_group_enable_address_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].EN;
+}
+
+/**
+ * @brief Function for returning the PPI disable task address of a specific group.
+ *
+ * @param[in] group  PPI group.
+ */
+__STATIC_INLINE uint32_t * nrf_ppi_task_group_disable_address_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t *) &NRF_PPI->TASKS_CHG[(uint32_t) group].DIS;
+}
+
+
+/**
+ *@}
+ **/
+
+/*lint --flb "Leave library region" */
+#endif // NRF_PPI_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pwm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pwm.h
new file mode 100644
index 0000000000..2dce14fd44
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_pwm.h
@@ -0,0 +1,665 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+/**
+ * @defgroup nrf_pwm_hal PWM HAL
+ * @{
+ * @ingroup nrf_pwm
+ *
+ * @brief @tagAPI52 Hardware access layer for managing the Pulse Width Modulation (PWM)
+ *        peripheral.
+ */
+
+#ifndef NRF_PWM_H__
+#define NRF_PWM_H__
+
+#ifdef NRF52
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+#include "nrf_assert.h"
+
+
+/**
+ * @brief This value can be provided as a parameter for the @ref nrf_pwm_pins_set
+ *        function call to specify that a given output channel shall not be
+ *        connected to a physical pin.
+ */
+#define NRF_PWM_PIN_NOT_CONNECTED   0xFFFFFFFF
+
+/**
+ * @brief Number of channels in each PWM instance.
+ */
+#define NRF_PWM_CHANNEL_COUNT   4
+
+
+/**
+ * @brief PWM tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_PWM_TASK_STOP      = offsetof(NRF_PWM_Type, TASKS_STOP),        ///< Stops PWM pulse generation on all channels at the end of the current PWM period, and stops the sequence playback.
+    NRF_PWM_TASK_SEQSTART0 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[0]), ///< Starts playback of sequence 0.
+    NRF_PWM_TASK_SEQSTART1 = offsetof(NRF_PWM_Type, TASKS_SEQSTART[1]), ///< Starts playback of sequence 1.
+    NRF_PWM_TASK_NEXTSTEP  = offsetof(NRF_PWM_Type, TASKS_NEXTSTEP)     ///< Steps by one value in the current sequence if the decoder is set to @ref NRF_PWM_STEP_TRIGGERED mode.
+    /*lint -restore*/
+} nrf_pwm_task_t;
+
+/**
+ * @brief PWM events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_PWM_EVENT_STOPPED      = offsetof(NRF_PWM_Type, EVENTS_STOPPED),       ///< Response to STOP task, emitted when PWM pulses are no longer generated.
+    NRF_PWM_EVENT_SEQSTARTED0  = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[0]), ///< First PWM period started on sequence 0.
+    NRF_PWM_EVENT_SEQSTARTED1  = offsetof(NRF_PWM_Type, EVENTS_SEQSTARTED[1]), ///< First PWM period started on sequence 1.
+    NRF_PWM_EVENT_SEQEND0      = offsetof(NRF_PWM_Type, EVENTS_SEQEND[0]),     ///< Emitted at the end of every sequence 0 when its last value has been read from RAM.
+    NRF_PWM_EVENT_SEQEND1      = offsetof(NRF_PWM_Type, EVENTS_SEQEND[1]),     ///< Emitted at the end of every sequence 1 when its last value has been read from RAM.
+    NRF_PWM_EVENT_PWMPERIODEND = offsetof(NRF_PWM_Type, EVENTS_PWMPERIODEND),  ///< Emitted at the end of each PWM period.
+    NRF_PWM_EVENT_LOOPSDONE    = offsetof(NRF_PWM_Type, EVENTS_LOOPSDONE)      ///< Concatenated sequences have been played the requested number of times.
+    /*lint -restore*/
+} nrf_pwm_event_t;
+
+/**
+ * @brief PWM interrupts.
+ */
+typedef enum
+{
+    NRF_PWM_INT_STOPPED_MASK      = PWM_INTENSET_STOPPED_Msk,      ///< Interrupt on STOPPED event.
+    NRF_PWM_INT_SEQSTARTED0_MASK  = PWM_INTENSET_SEQSTARTED0_Msk,  ///< Interrupt on SEQSTARTED[0] event.
+    NRF_PWM_INT_SEQSTARTED1_MASK  = PWM_INTENSET_SEQSTARTED1_Msk,  ///< Interrupt on SEQSTARTED[1] event.
+    NRF_PWM_INT_SEQEND0_MASK      = PWM_INTENSET_SEQEND0_Msk,      ///< Interrupt on SEQEND[0] event.
+    NRF_PWM_INT_SEQEND1_MASK      = PWM_INTENSET_SEQEND1_Msk,      ///< Interrupt on SEQEND[1] event.
+    NRF_PWM_INT_PWMPERIODEND_MASK = PWM_INTENSET_PWMPERIODEND_Msk, ///< Interrupt on PWMPERIODEND event.
+    NRF_PWM_INT_LOOPSDONE_MASK    = PWM_INTENSET_LOOPSDONE_Msk     ///< Interrupt on LOOPSDONE event.
+} nrf_pwm_int_mask_t;
+
+/**
+ * @brief PWM shortcuts.
+ */
+typedef enum
+{
+    NRF_PWM_SHORT_SEQEND0_STOP_MASK        = PWM_SHORTS_SEQEND0_STOP_Msk,        ///< Shortcut between SEQEND[0] event and STOP task.
+    NRF_PWM_SHORT_SEQEND1_STOP_MASK        = PWM_SHORTS_SEQEND1_STOP_Msk,        ///< Shortcut between SEQEND[1] event and STOP task.
+    NRF_PWM_SHORT_LOOPSDONE_SEQSTART0_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART0_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[0] task.
+    NRF_PWM_SHORT_LOOPSDONE_SEQSTART1_MASK = PWM_SHORTS_LOOPSDONE_SEQSTART1_Msk, ///< Shortcut between LOOPSDONE event and SEQSTART[1] task.
+    NRF_PWM_SHORT_LOOPSDONE_STOP_MASK      = PWM_SHORTS_LOOPSDONE_STOP_Msk       ///< Shortcut between LOOPSDONE event and STOP task.
+} nrf_pwm_short_mask_t;
+
+/**
+ * @brief PWM modes of operation.
+ */
+typedef enum
+{
+    NRF_PWM_MODE_UP          = PWM_MODE_UPDOWN_Up,        ///< Up counter (edge-aligned PWM duty cycle).
+    NRF_PWM_MODE_UP_AND_DOWN = PWM_MODE_UPDOWN_UpAndDown, ///< Up and down counter (center-aligned PWM duty cycle).
+} nrf_pwm_mode_t;
+
+/**
+ * @brief PWM base clock frequencies.
+ */
+typedef enum
+{
+    NRF_PWM_CLK_16MHz  = PWM_PRESCALER_PRESCALER_DIV_1,  ///< 16 MHz / 1 = 16 MHz.
+    NRF_PWM_CLK_8MHz   = PWM_PRESCALER_PRESCALER_DIV_2,  ///< 16 MHz / 2 = 8 MHz.
+    NRF_PWM_CLK_4MHz   = PWM_PRESCALER_PRESCALER_DIV_4,  ///< 16 MHz / 4 = 4 MHz.
+    NRF_PWM_CLK_2MHz   = PWM_PRESCALER_PRESCALER_DIV_8,  ///< 16 MHz / 8 = 2 MHz.
+    NRF_PWM_CLK_1MHz   = PWM_PRESCALER_PRESCALER_DIV_16, ///< 16 MHz / 16 = 1 MHz.
+    NRF_PWM_CLK_500kHz = PWM_PRESCALER_PRESCALER_DIV_32, ///< 16 MHz / 32 = 500 kHz.
+    NRF_PWM_CLK_250kHz = PWM_PRESCALER_PRESCALER_DIV_64, ///< 16 MHz / 64 = 250 kHz.
+    NRF_PWM_CLK_125kHz = PWM_PRESCALER_PRESCALER_DIV_128 ///< 16 MHz / 128 = 125 kHz.
+} nrf_pwm_clk_t;
+
+/**
+ * @brief PWM decoder load modes.
+ *
+ * The selected mode determines how the sequence data is read from RAM and
+ * spread to the compare registers.
+ */
+typedef enum
+{
+    NRF_PWM_LOAD_COMMON     = PWM_DECODER_LOAD_Common,     ///< 1st half word (16-bit) used in all PWM channels (0-3).
+    NRF_PWM_LOAD_GROUPED    = PWM_DECODER_LOAD_Grouped,    ///< 1st half word (16-bit) used in channels 0 and 1; 2nd word in channels 2 and 3.
+    NRF_PWM_LOAD_INDIVIDUAL = PWM_DECODER_LOAD_Individual, ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; 3rd in channel 2; 4th in channel 3.
+    NRF_PWM_LOAD_WAVE_FORM  = PWM_DECODER_LOAD_WaveForm    ///< 1st half word (16-bit) used in channel 0; 2nd in channel 1; ... ; 4th as the top value for the pulse generator counter.
+} nrf_pwm_dec_load_t;
+
+/**
+ * @brief PWM decoder next step modes.
+ *
+ * The selected mode determines when the next value from the active sequence
+ * is loaded.
+ */
+typedef enum
+{
+    NRF_PWM_STEP_AUTO      = PWM_DECODER_MODE_RefreshCount, ///< Automatically after the current value is played and repeated the requested number of times.
+    NRF_PWM_STEP_TRIGGERED = PWM_DECODER_MODE_NextStep      ///< When the @ref NRF_PWM_TASK_NEXTSTEP task is triggered.
+} nrf_pwm_dec_step_t;
+
+
+/**
+ * @brief Type used for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_COMMON mode.
+ */
+typedef uint16_t nrf_pwm_values_common_t;
+
+/**
+ * @brief Structure for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_GROUPED mode.
+ */
+typedef struct {
+    uint16_t group_0; ///< Duty cycle value for group 0 (channels 0 and 1).
+    uint16_t group_1; ///< Duty cycle value for group 1 (channels 2 and 3).
+} nrf_pwm_values_grouped_t;
+
+/**
+ * @brief Structure for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
+ */
+typedef struct
+{
+    uint16_t channel_0; ///< Duty cycle value for channel 0.
+    uint16_t channel_1; ///< Duty cycle value for channel 1.
+    uint16_t channel_2; ///< Duty cycle value for channel 2.
+    uint16_t channel_3; ///< Duty cycle value for channel 3.
+} nrf_pwm_values_individual_t;
+
+/**
+ * @brief Structure for defining duty cycle values for a sequence
+ *        loaded in @ref NRF_PWM_LOAD_WAVE_FORM mode.
+ */
+typedef struct {
+    uint16_t channel_0;   ///< Duty cycle value for channel 0.
+    uint16_t channel_1;   ///< Duty cycle value for channel 1.
+    uint16_t channel_2;   ///< Duty cycle value for channel 2.
+    uint16_t counter_top; ///< Top value for the pulse generator counter.
+} nrf_pwm_values_wave_form_t;
+
+/**
+ * @brief Union grouping pointers to arrays of duty cycle values applicable to
+ *        various loading modes.
+ */
+typedef union {
+    nrf_pwm_values_common_t     const * p_common;     ///< Pointer to be used in @ref NRF_PWM_LOAD_COMMON mode.
+    nrf_pwm_values_grouped_t    const * p_grouped;    ///< Pointer to be used in @ref NRF_PWM_LOAD_GROUPED mode.
+    nrf_pwm_values_individual_t const * p_individual; ///< Pointer to be used in @ref NRF_PWM_LOAD_INDIVIDUAL mode.
+    nrf_pwm_values_wave_form_t  const * p_wave_form;  ///< Pointer to be used in @ref NRF_PWM_LOAD_WAVE_FORM mode.
+    uint16_t                    const * p_raw;        ///< Pointer providing raw access to the values.
+} nrf_pwm_values_t;
+
+/**
+ * @brief Structure for defining a sequence of PWM duty cycles.
+ *
+ * When the sequence is set (by a call to @ref nrf_pwm_sequence_set), the
+ * provided duty cycle values are not copied. The @p values pointer is stored
+ * in the peripheral's internal register, and the values are loaded from RAM
+ * during the sequence playback. Therefore, you must ensure that the values
+ * do not change before and during the sequence playback (for example,
+ * the values cannot be placed in a local variable that is allocated on stack).
+ * If the sequence is played in a loop and the values should be updated
+ * before the next iteration, it is safe to modify them when the corresponding
+ * event signaling the end of sequence occurs (@ref NRF_PWM_EVENT_SEQEND0
+ * or @ref NRF_PWM_EVENT_SEQEND1, respectively).
+ *
+ * @note The @p repeats and @p end_delay values (which are written to the
+ *       SEQ[n].REFRESH and SEQ[n].ENDDELAY registers in the peripheral,
+ *       respectively) are ignored at the end of a complex sequence
+ *       playback, indicated by the LOOPSDONE event.
+ *       See the @linkProductSpecification52 for more information.
+ */
+typedef struct
+{
+    nrf_pwm_values_t values; ///< Pointer to an array with duty cycle values. This array must be in Data RAM.
+                             /**< This field is defined as an union of pointers
+                              *   to provide a convenient way to define duty
+                              *   cycle values in various loading modes
+                              *   (see @ref nrf_pwm_dec_load_t).
+                              *   In each value, the most significant bit (15)
+                              *   determines the polarity of the output and the
+                              *   others (14-0) compose the 15-bit value to be
+                              *   compared with the pulse generator counter. */
+    uint16_t length;    ///< Number of 16-bit values in the array pointed by @p values.
+    uint32_t repeats;   ///< Number of times that each duty cycle should be repeated (after being played once). Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
+    uint32_t end_delay; ///< Additional time (in PWM periods) that the last duty cycle is to be kept after the sequence is played. Ignored in @ref NRF_PWM_STEP_TRIGGERED mode.
+} nrf_pwm_sequence_t;
+
+/**
+ * @brief Helper macro for calculating the number of 16-bit values in specified
+ *        array of duty cycle values.
+ */
+#define NRF_PWM_VALUES_LENGTH(array)  (sizeof(array)/sizeof(uint16_t))
+
+
+/**
+ * @brief Function for activating a specific PWM task.
+ *
+ * @param[in] p_pwm PWM instance.
+ * @param[in] task  Task to activate.
+ */
+__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm,
+                                          nrf_pwm_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific PWM task register.
+ *
+ * @param[in] p_pwm PWM instance.
+ * @param[in] task  Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm,
+                                                  nrf_pwm_task_t task);
+
+/**
+ * @brief Function for clearing a specific PWM event.
+ *
+ * @param[in] p_pwm PWM instance.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm,
+                                         nrf_pwm_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific PWM event.
+ *
+ * @param[in] p_pwm PWM instance.
+ * @param[in] event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm,
+                                         nrf_pwm_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific PWM event register.
+ *
+ * @param[in] p_pwm PWM instance.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm,
+                                                   nrf_pwm_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_pwm           PWM instance.
+ * @param[in] pwm_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm,
+                                           uint32_t pwm_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_pwm           PWM instance.
+ * @param[in] pwm_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm,
+                                            uint32_t pwm_shorts_mask);
+
+/**
+ * @brief Function for setting the configuration of PWM shortcuts.
+ *
+ * @param[in] p_pwm           PWM instance.
+ * @param[in] pwm_shorts_mask Shortcuts configuration to set.
+ */
+__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm,
+                                        uint32_t pwm_shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_pwm        PWM instance.
+ * @param[in] pwm_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm,
+                                        uint32_t pwm_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_pwm        PWM instance.
+ * @param[in] pwm_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm,
+                                         uint32_t pwm_int_mask);
+
+/**
+ * @brief Function for setting the configuration of PWM interrupts.
+ *
+ * @param[in] p_pwm        PWM instance.
+ * @param[in] pwm_int_mask Interrupts configuration to set.
+ */
+__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm,
+                                     uint32_t pwm_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_pwm   PWM instance.
+ * @param[in] pwm_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm,
+                                              nrf_pwm_int_mask_t pwm_int);
+
+/**
+ * @brief Function for enabling the PWM peripheral.
+ *
+ * @param[in] p_pwm PWM instance.
+ */
+__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm);
+
+/**
+ * @brief Function for disabling the PWM peripheral.
+ *
+ * @param[in] p_pwm PWM instance.
+ */
+__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm);
+
+/**
+ * @brief Function for assigning pins to PWM output channels.
+ *
+ * Usage of all PWM output channels is optional. If a given channel is not
+ * needed, pass the @ref NRF_PWM_PIN_NOT_CONNECTED value instead of its pin
+ * number.
+ *
+ * @param[in] p_pwm    PWM instance.
+ * @param[in] out_pins Array with pin numbers for individual PWM output channels.
+ */
+__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm,
+                                      uint32_t out_pins[NRF_PWM_CHANNEL_COUNT]);
+
+/**
+ * @brief Function for configuring the PWM peripheral.
+ *
+ * @param[in] p_pwm      PWM instance.
+ * @param[in] base_clock Base clock frequency.
+ * @param[in] mode       Operating mode of the pulse generator counter.
+ * @param[in] top_value  Value up to which the pulse generator counter counts.
+ */
+__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm,
+                                       nrf_pwm_clk_t  base_clock,
+                                       nrf_pwm_mode_t mode,
+                                       uint16_t       top_value);
+
+/**
+ * @brief Function for defining a sequence of PWM duty cycles.
+ *
+ * @param[in] p_pwm  PWM instance.
+ * @param[in] seq_id Identifier of the sequence (0 or 1).
+ * @param[in] p_seq  Pointer to the sequence definition.
+ */
+__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm,
+                                          uint8_t                    seq_id,
+                                          nrf_pwm_sequence_t const * p_seq);
+
+/**
+ * @brief Function for modifying the pointer to the duty cycle values
+ *        in the specified sequence.
+ *
+ * @param[in] p_pwm    PWM instance.
+ * @param[in] seq_id   Identifier of the sequence (0 or 1).
+ * @param[in] p_values Pointer to an array with duty cycle values.
+ */
+__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm,
+                                         uint8_t          seq_id,
+                                         uint16_t const * p_values);
+
+/**
+ * @brief Function for modifying the total number of duty cycle values
+ *        in the specified sequence.
+ *
+ * @param[in] p_pwm  PWM instance.
+ * @param[in] seq_id Identifier of the sequence (0 or 1).
+ * @param[in] length Number of duty cycle values.
+ */
+__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm,
+                                         uint8_t  seq_id,
+                                         uint16_t length);
+
+/**
+ * @brief Function for modifying the additional number of PWM periods spent
+ *        on each duty cycle value in the specified sequence.
+ *
+ * @param[in] p_pwm   PWM instance.
+ * @param[in] seq_id  Identifier of the sequence (0 or 1).
+ * @param[in] refresh Number of additional PWM periods for each duty cycle value.
+ */
+__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm,
+                                             uint8_t  seq_id,
+                                             uint32_t refresh);
+
+/**
+ * @brief Function for modifying the additional time added after the sequence
+ *        is played.
+ *
+ * @param[in] p_pwm     PWM instance.
+ * @param[in] seq_id    Identifier of the sequence (0 or 1).
+ * @param[in] end_delay Number of PWM periods added at the end of the sequence.
+ */
+__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm,
+                                               uint8_t  seq_id,
+                                               uint32_t end_delay);
+
+/**
+ * @brief Function for setting the mode of loading sequence data from RAM
+ *        and advancing the sequence.
+ *
+ * @param[in] p_pwm    PWM instance.
+ * @param[in] dec_load Mode of loading sequence data from RAM.
+ * @param[in] dec_step Mode of advancing the active sequence.
+ */
+__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm,
+                                         nrf_pwm_dec_load_t dec_load,
+                                         nrf_pwm_dec_step_t dec_step);
+
+/**
+ * @brief Function for setting the number of times the sequence playback
+ *        should be performed.
+ *
+ * This function applies to two-sequence playback (concatenated sequence 0 and 1).
+ * A single sequence can be played back only once.
+ *
+ * @param[in] p_pwm      PWM instance.
+ * @param[in] loop_count Number of times to perform the sequence playback.
+ */
+__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm,
+                                      uint16_t loop_count);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_pwm_task_trigger(NRF_PWM_Type * p_pwm,
+                                          nrf_pwm_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_pwm_task_address_get(NRF_PWM_Type const * p_pwm,
+                                                  nrf_pwm_task_t task)
+{
+    return ((uint32_t)p_pwm + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_pwm_event_clear(NRF_PWM_Type * p_pwm,
+                                         nrf_pwm_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_pwm_event_check(NRF_PWM_Type const * p_pwm,
+                                         nrf_pwm_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_pwm + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_pwm_event_address_get(NRF_PWM_Type const * p_pwm,
+                                                   nrf_pwm_event_t event)
+{
+    return ((uint32_t)p_pwm + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_pwm_shorts_enable(NRF_PWM_Type * p_pwm,
+                                           uint32_t pwm_shorts_mask)
+{
+    p_pwm->SHORTS |= pwm_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_shorts_disable(NRF_PWM_Type * p_pwm,
+                                            uint32_t pwm_shorts_mask)
+{
+    p_pwm->SHORTS &= ~(pwm_shorts_mask);
+}
+
+__STATIC_INLINE void nrf_pwm_shorts_set(NRF_PWM_Type * p_pwm,
+                                        uint32_t pwm_shorts_mask)
+{
+    p_pwm->SHORTS = pwm_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_int_enable(NRF_PWM_Type * p_pwm,
+                                        uint32_t pwm_int_mask)
+{
+    p_pwm->INTENSET = pwm_int_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_int_disable(NRF_PWM_Type * p_pwm,
+                                         uint32_t pwm_int_mask)
+{
+    p_pwm->INTENCLR = pwm_int_mask;
+}
+
+__STATIC_INLINE void nrf_pwm_int_set(NRF_PWM_Type * p_pwm,
+                                     uint32_t pwm_int_mask)
+{
+    p_pwm->INTEN = pwm_int_mask;
+}
+
+__STATIC_INLINE bool nrf_pwm_int_enable_check(NRF_PWM_Type const * p_pwm,
+                                              nrf_pwm_int_mask_t pwm_int)
+{
+    return (bool)(p_pwm->INTENSET & pwm_int);
+}
+
+__STATIC_INLINE void nrf_pwm_enable(NRF_PWM_Type * p_pwm)
+{
+    p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Enabled << PWM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_pwm_disable(NRF_PWM_Type * p_pwm)
+{
+    p_pwm->ENABLE = (PWM_ENABLE_ENABLE_Disabled << PWM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_pwm_pins_set(NRF_PWM_Type * p_pwm,
+                                      uint32_t out_pins[NRF_PWM_CHANNEL_COUNT])
+{
+    uint8_t i;
+    for (i = 0; i < NRF_PWM_CHANNEL_COUNT; ++i)
+    {
+        p_pwm->PSEL.OUT[i] = out_pins[i];
+    }
+}
+
+__STATIC_INLINE void nrf_pwm_configure(NRF_PWM_Type * p_pwm,
+                                       nrf_pwm_clk_t  base_clock,
+                                       nrf_pwm_mode_t mode,
+                                       uint16_t       top_value)
+{
+    ASSERT(top_value <= PWM_COUNTERTOP_COUNTERTOP_Msk);
+
+    p_pwm->PRESCALER  = base_clock;
+    p_pwm->MODE       = mode;
+    p_pwm->COUNTERTOP = top_value;
+}
+
+__STATIC_INLINE void nrf_pwm_sequence_set(NRF_PWM_Type * p_pwm,
+                                          uint8_t                    seq_id,
+                                          nrf_pwm_sequence_t const * p_seq)
+{
+    ASSERT(p_seq != NULL);
+
+    nrf_pwm_seq_ptr_set(      p_pwm, seq_id, p_seq->values.p_raw);
+    nrf_pwm_seq_cnt_set(      p_pwm, seq_id, p_seq->length);
+    nrf_pwm_seq_refresh_set(  p_pwm, seq_id, p_seq->repeats);
+    nrf_pwm_seq_end_delay_set(p_pwm, seq_id, p_seq->end_delay);
+}
+
+__STATIC_INLINE void nrf_pwm_seq_ptr_set(NRF_PWM_Type * p_pwm,
+                                         uint8_t          seq_id,
+                                         uint16_t const * p_values)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(p_values != NULL);
+    p_pwm->SEQ[seq_id].PTR = (uint32_t)p_values;
+}
+
+__STATIC_INLINE void nrf_pwm_seq_cnt_set(NRF_PWM_Type * p_pwm,
+                                         uint8_t  seq_id,
+                                         uint16_t length)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(length != 0);
+    ASSERT(length <= PWM_SEQ_CNT_CNT_Msk);
+    p_pwm->SEQ[seq_id].CNT = length;
+}
+
+__STATIC_INLINE void nrf_pwm_seq_refresh_set(NRF_PWM_Type * p_pwm,
+                                             uint8_t  seq_id,
+                                             uint32_t refresh)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(refresh <= PWM_SEQ_REFRESH_CNT_Msk);
+    p_pwm->SEQ[seq_id].REFRESH  = refresh;
+}
+
+__STATIC_INLINE void nrf_pwm_seq_end_delay_set(NRF_PWM_Type * p_pwm,
+                                               uint8_t  seq_id,
+                                               uint32_t end_delay)
+{
+    ASSERT(seq_id <= 1);
+    ASSERT(end_delay <= PWM_SEQ_ENDDELAY_CNT_Msk);
+    p_pwm->SEQ[seq_id].ENDDELAY = end_delay;
+}
+
+__STATIC_INLINE void nrf_pwm_decoder_set(NRF_PWM_Type * p_pwm,
+                                         nrf_pwm_dec_load_t dec_load,
+                                         nrf_pwm_dec_step_t dec_step)
+{
+    p_pwm->DECODER = ((uint32_t)dec_load << PWM_DECODER_LOAD_Pos) |
+                     ((uint32_t)dec_step << PWM_DECODER_MODE_Pos);
+}
+
+__STATIC_INLINE void nrf_pwm_loop_set(NRF_PWM_Type * p_pwm,
+                                      uint16_t loop_count)
+{
+    p_pwm->LOOP = loop_count;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF52
+
+#endif // NRF_PWM_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_rtc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_rtc.h
new file mode 100644
index 0000000000..39e7f57281
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_rtc.h
@@ -0,0 +1,331 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @file
+ * @brief RTC HAL API.
+ */
+
+#ifndef NRF_RTC_H
+#define NRF_RTC_H
+
+/**
+ * @defgroup nrf_rtc_hal RTC HAL
+ * @{
+ * @ingroup nrf_rtc
+ * @brief Hardware access layer for managing the real time counter (RTC).
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+
+/**
+ * @brief Macro for getting the number of compare channels available
+ *        in a given RTC instance.
+ */
+#ifdef NRF51
+    #define NRF_RTC_CC_CHANNEL_COUNT(id)  4
+#else
+    #define NRF_RTC_CC_CHANNEL_COUNT(id)  ((id) == 0 ? 3 : 4)
+#endif
+
+#define RTC_INPUT_FREQ 32768 /**< Input frequency of the RTC instance. */
+
+/**< Macro for wrapping values to RTC capacity. */
+#define RTC_WRAP(val) (val & RTC_COUNTER_COUNTER_Msk)
+
+#define RTC_CHANNEL_INT_MASK(ch)    ((uint32_t)NRF_RTC_INT_COMPARE0_MASK << ch)
+#define RTC_CHANNEL_EVENT_ADDR(ch)  (nrf_rtc_event_t)(NRF_RTC_EVENT_COMPARE_0 + ch*sizeof(uint32_t))
+/**
+ * @enum nrf_rtc_task_t
+ * @brief RTC tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_RTC_TASK_START            = offsetof(NRF_RTC_Type,TASKS_START),     /**< Start. */
+    NRF_RTC_TASK_STOP             = offsetof(NRF_RTC_Type,TASKS_STOP),      /**< Stop. */
+    NRF_RTC_TASK_CLEAR            = offsetof(NRF_RTC_Type,TASKS_CLEAR),     /**< Clear. */
+    NRF_RTC_TASK_TRIGGER_OVERFLOW = offsetof(NRF_RTC_Type,TASKS_TRIGOVRFLW),/**< Trigger overflow. */
+    /*lint -restore*/
+} nrf_rtc_task_t;
+
+/**
+ * @enum nrf_rtc_event_t
+ * @brief RTC events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_RTC_EVENT_TICK        = offsetof(NRF_RTC_Type,EVENTS_TICK),       /**< Tick event. */
+    NRF_RTC_EVENT_OVERFLOW    = offsetof(NRF_RTC_Type,EVENTS_OVRFLW),     /**< Overflow event. */
+    NRF_RTC_EVENT_COMPARE_0   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[0]), /**< Compare 0 event. */
+    NRF_RTC_EVENT_COMPARE_1   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[1]), /**< Compare 1 event. */
+    NRF_RTC_EVENT_COMPARE_2   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[2]), /**< Compare 2 event. */
+    NRF_RTC_EVENT_COMPARE_3   = offsetof(NRF_RTC_Type,EVENTS_COMPARE[3])  /**< Compare 3 event. */
+    /*lint -restore*/
+} nrf_rtc_event_t;
+
+/**
+ * @enum nrf_rtc_int_t
+ * @brief RTC interrupts.
+ */
+typedef enum
+{
+    NRF_RTC_INT_TICK_MASK     = RTC_INTENSET_TICK_Msk,     /**< RTC interrupt from tick event. */
+    NRF_RTC_INT_OVERFLOW_MASK = RTC_INTENSET_OVRFLW_Msk,   /**< RTC interrupt from overflow event. */
+    NRF_RTC_INT_COMPARE0_MASK = RTC_INTENSET_COMPARE0_Msk, /**< RTC interrupt from compare event on channel 0. */
+    NRF_RTC_INT_COMPARE1_MASK = RTC_INTENSET_COMPARE1_Msk, /**< RTC interrupt from compare event on channel 1. */
+    NRF_RTC_INT_COMPARE2_MASK = RTC_INTENSET_COMPARE2_Msk, /**< RTC interrupt from compare event on channel 2. */
+    NRF_RTC_INT_COMPARE3_MASK = RTC_INTENSET_COMPARE3_Msk  /**< RTC interrupt from compare event on channel 3. */
+} nrf_rtc_int_t;
+
+/**@brief Function for setting a compare value for a channel.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  ch            Channel.
+ * @param[in]  cc_val        Compare value to set.
+ */
+__STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val);
+
+/**@brief Function for returning the compare value for a channel.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  ch            Channel.
+ *
+ * @return                   COMPARE[ch] value.
+ */
+__STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch);
+
+/**@brief Function for enabling interrupts.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  mask          Interrupt mask to be enabled.
+ */
+__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for disabling interrupts.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  mask          Interrupt mask to be disabled.
+ */
+__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for checking if interrupts are enabled.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  mask          Mask of interrupt flags to check.
+ *
+ * @return                   Mask with enabled interrupts.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for returning the status of currently enabled interrupts.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ *
+ * @return                   Value in INTEN register.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc);
+
+/**@brief Function for checking if an event is pending.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  event         Address of the event.
+ *
+ * @return                   Mask of pending events.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
+
+/**@brief Function for clearing an event.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  event         Event to clear.
+ */
+__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
+
+/**@brief Function for returning a counter value.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ *
+ * @return                   Counter value.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc);
+
+/**@brief Function for setting a prescaler value.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  val           Value to set the prescaler to.
+ */
+__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val);
+
+/**@brief Function for returning the address of an event.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  event         Requested event.
+ *
+ * @return     Address of the requested event register.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event);
+
+/**@brief Function for returning the address of a task.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  task          Requested task.
+ *
+ * @return     Address of the requested task register.
+ */
+__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
+
+/**@brief Function for starting a task.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  task          Requested task.
+ */
+__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task);
+
+/**@brief Function for enabling events.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  mask          Mask of event flags to enable.
+ */
+__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask);
+
+/**@brief Function for disabling an event.
+ *
+ * @param[in]  p_rtc         Pointer to the instance register structure.
+ * @param[in]  event         Requested event.
+ */
+__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t event);
+
+/**
+ *@}
+ **/
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE  void nrf_rtc_cc_set(NRF_RTC_Type * p_rtc, uint32_t ch, uint32_t cc_val)
+{
+    p_rtc->CC[ch] = cc_val;
+}
+
+__STATIC_INLINE  uint32_t nrf_rtc_cc_get(NRF_RTC_Type * p_rtc, uint32_t ch)
+{
+    return p_rtc->CC[ch];
+}
+
+__STATIC_INLINE void nrf_rtc_int_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->INTENSET = mask;
+}
+
+__STATIC_INLINE void nrf_rtc_int_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->INTENCLR = mask;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_int_is_enabled(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    return (p_rtc->INTENSET & mask);
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_int_get(NRF_RTC_Type * p_rtc)
+{
+    return p_rtc->INTENSET;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_event_pending(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
+{
+    return *(volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_rtc_event_clear(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event)) = 0;
+#if __CORTEX_M == 0x04
+    volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)p_rtc + (uint32_t)event));
+    (void)dummy;
+#endif
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_counter_get(NRF_RTC_Type * p_rtc)
+{
+     return p_rtc->COUNTER;
+}
+
+__STATIC_INLINE void nrf_rtc_prescaler_set(NRF_RTC_Type * p_rtc, uint32_t val)
+{
+    ASSERT(val <= (RTC_PRESCALER_PRESCALER_Msk >> RTC_PRESCALER_PRESCALER_Pos));
+    p_rtc->PRESCALER = val;
+}
+__STATIC_INLINE uint32_t rtc_prescaler_get(NRF_RTC_Type * p_rtc)
+{
+    return p_rtc->PRESCALER;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_event_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_event_t event)
+{
+    return (uint32_t)p_rtc + event;
+}
+
+__STATIC_INLINE uint32_t nrf_rtc_task_address_get(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
+{
+    return (uint32_t)p_rtc + task;
+}
+
+__STATIC_INLINE void nrf_rtc_task_trigger(NRF_RTC_Type * p_rtc, nrf_rtc_task_t task)
+{
+    *(__IO uint32_t *)((uint32_t)p_rtc + task) = 1;
+}
+
+__STATIC_INLINE void nrf_rtc_event_enable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->EVTENSET = mask;
+}
+__STATIC_INLINE void nrf_rtc_event_disable(NRF_RTC_Type * p_rtc, uint32_t mask)
+{
+    p_rtc->EVTENCLR = mask;
+}
+#endif
+
+#endif  /* NRF_RTC_H */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.c
new file mode 100644
index 0000000000..c5b88ea077
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.c
@@ -0,0 +1,62 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifdef NRF52
+/**
+ * @file
+ * @brief SAADC HAL implementation
+ */
+
+#include "nrf_saadc.h"
+
+void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config)
+{
+    NRF_SAADC->CH[channel].CONFIG = 
+            ((config->resistor_p   << SAADC_CH_CONFIG_RESP_Pos)   & SAADC_CH_CONFIG_RESP_Msk)
+            | ((config->resistor_n << SAADC_CH_CONFIG_RESN_Pos)   & SAADC_CH_CONFIG_RESN_Msk)
+            | ((config->gain       << SAADC_CH_CONFIG_GAIN_Pos)   & SAADC_CH_CONFIG_GAIN_Msk)
+            | ((config->reference  << SAADC_CH_CONFIG_REFSEL_Pos) & SAADC_CH_CONFIG_REFSEL_Msk)
+            | ((config->acq_time   << SAADC_CH_CONFIG_TACQ_Pos)   & SAADC_CH_CONFIG_TACQ_Msk)
+            | ((config->mode       << SAADC_CH_CONFIG_MODE_Pos)   & SAADC_CH_CONFIG_MODE_Msk);
+    nrf_saadc_channel_input_set(channel, config->pin_p, config->pin_n);
+    return;
+}
+
+#endif //NRF52
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.h
new file mode 100644
index 0000000000..b3ea9d7ef7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_saadc.h
@@ -0,0 +1,587 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+
+#ifndef NRF_SAADC_H_
+#define NRF_SAADC_H_
+
+#ifdef NRF52
+
+/**
+ * @defgroup nrf_saadc_hal SAADC HAL
+ * @{
+ * @ingroup nrf_saadc
+ *
+ * @brief @tagAPI52 Hardware access layer for accessing the SAADC peripheral.
+ */
+
+#include <stdbool.h>
+#include <stddef.h>
+#include "nrf.h"
+#include "nrf_assert.h"
+
+
+
+#define NRF_SAADC_CHANNEL_COUNT 8
+
+/**
+ * @brief Resolution of the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_SAADC_RESOLUTION_8BIT  = SAADC_RESOLUTION_VAL_8bit,  ///< 8 bit resolution.
+    NRF_SAADC_RESOLUTION_10BIT = SAADC_RESOLUTION_VAL_10bit, ///< 10 bit resolution.
+    NRF_SAADC_RESOLUTION_12BIT = SAADC_RESOLUTION_VAL_12bit, ///< 12 bit resolution.
+    NRF_SAADC_RESOLUTION_14BIT = SAADC_RESOLUTION_VAL_14bit  ///< 14 bit resolution.
+} nrf_saadc_resolution_t;
+
+
+/**
+ * @brief Input selection for the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_SAADC_INPUT_DISABLED = SAADC_CH_PSELP_PSELP_NC,           ///< Not connected.
+    NRF_SAADC_INPUT_AIN0     = SAADC_CH_PSELP_PSELP_AnalogInput0, ///< Analog input 0 (AIN0).
+    NRF_SAADC_INPUT_AIN1     = SAADC_CH_PSELP_PSELP_AnalogInput1, ///< Analog input 1 (AIN1).
+    NRF_SAADC_INPUT_AIN2     = SAADC_CH_PSELP_PSELP_AnalogInput2, ///< Analog input 2 (AIN2).
+    NRF_SAADC_INPUT_AIN3     = SAADC_CH_PSELP_PSELP_AnalogInput3, ///< Analog input 3 (AIN3).
+    NRF_SAADC_INPUT_AIN4     = SAADC_CH_PSELP_PSELP_AnalogInput4, ///< Analog input 4 (AIN4).
+    NRF_SAADC_INPUT_AIN5     = SAADC_CH_PSELP_PSELP_AnalogInput5, ///< Analog input 5 (AIN5).
+    NRF_SAADC_INPUT_AIN6     = SAADC_CH_PSELP_PSELP_AnalogInput6, ///< Analog input 6 (AIN6).
+    NRF_SAADC_INPUT_AIN7     = SAADC_CH_PSELP_PSELP_AnalogInput7, ///< Analog input 7 (AIN7).
+    NRF_SAADC_INPUT_VDD      = SAADC_CH_PSELP_PSELP_VDD           ///< VDD as input.
+} nrf_saadc_input_t;
+
+
+/**
+ * @brief Analog-to-digital converter oversampling mode.
+ */
+typedef enum
+{
+    NRF_SAADC_OVERSAMPLE_DISABLED = SAADC_OVERSAMPLE_OVERSAMPLE_Bypass,   ///< No oversampling.
+    NRF_SAADC_OVERSAMPLE_2X       = SAADC_OVERSAMPLE_OVERSAMPLE_Over2x,   ///< Oversample 2x.
+    NRF_SAADC_OVERSAMPLE_4X       = SAADC_OVERSAMPLE_OVERSAMPLE_Over4x,   ///< Oversample 4x.
+    NRF_SAADC_OVERSAMPLE_8X       = SAADC_OVERSAMPLE_OVERSAMPLE_Over8x,   ///< Oversample 8x.
+    NRF_SAADC_OVERSAMPLE_16X      = SAADC_OVERSAMPLE_OVERSAMPLE_Over16x,  ///< Oversample 16x.
+    NRF_SAADC_OVERSAMPLE_32X      = SAADC_OVERSAMPLE_OVERSAMPLE_Over32x,  ///< Oversample 32x.
+    NRF_SAADC_OVERSAMPLE_64X      = SAADC_OVERSAMPLE_OVERSAMPLE_Over64x,  ///< Oversample 64x.
+    NRF_SAADC_OVERSAMPLE_128X     = SAADC_OVERSAMPLE_OVERSAMPLE_Over128x, ///< Oversample 128x.
+    NRF_SAADC_OVERSAMPLE_256X     = SAADC_OVERSAMPLE_OVERSAMPLE_Over256x  ///< Oversample 256x.
+} nrf_saadc_oversample_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel resistor control.
+ */
+typedef enum
+{
+    NRF_SAADC_RESISTOR_DISABLED = SAADC_CH_CONFIG_RESP_Bypass,   ///< Bypass resistor ladder.
+    NRF_SAADC_RESISTOR_PULLDOWN = SAADC_CH_CONFIG_RESP_Pulldown, ///< Pull-down to GND.
+    NRF_SAADC_RESISTOR_PULLUP   = SAADC_CH_CONFIG_RESP_Pullup,   ///< Pull-up to VDD.
+    NRF_SAADC_RESISTOR_VDD1_2   = SAADC_CH_CONFIG_RESP_VDD1_2    ///< Set input at VDD/2.
+} nrf_saadc_resistor_t;
+
+
+/**
+ * @brief Gain factor of the analog-to-digital converter input.
+ */
+typedef enum
+{
+    NRF_SAADC_GAIN1_6 = SAADC_CH_CONFIG_GAIN_Gain1_6, ///< Gain factor 1/6.
+    NRF_SAADC_GAIN1_5 = SAADC_CH_CONFIG_GAIN_Gain1_5, ///< Gain factor 1/5.
+    NRF_SAADC_GAIN1_4 = SAADC_CH_CONFIG_GAIN_Gain1_4, ///< Gain factor 1/4.
+    NRF_SAADC_GAIN1_3 = SAADC_CH_CONFIG_GAIN_Gain1_3, ///< Gain factor 1/3.
+    NRF_SAADC_GAIN1_2 = SAADC_CH_CONFIG_GAIN_Gain1_2, ///< Gain factor 1/2.
+    NRF_SAADC_GAIN1   = SAADC_CH_CONFIG_GAIN_Gain1,   ///< Gain factor 1.
+    NRF_SAADC_GAIN2   = SAADC_CH_CONFIG_GAIN_Gain2,   ///< Gain factor 2.
+    NRF_SAADC_GAIN4   = SAADC_CH_CONFIG_GAIN_Gain4,   ///< Gain factor 4.
+} nrf_saadc_gain_t;
+
+
+/**
+ * @brief Reference selection for the analog-to-digital converter.
+ */
+typedef enum
+{
+    NRF_SAADC_REFERENCE_INTERNAL = SAADC_CH_CONFIG_REFSEL_Internal, ///< Internal reference (0.6 V).
+    NRF_SAADC_REFERENCE_VDD4     = SAADC_CH_CONFIG_REFSEL_VDD1_4    ///< VDD/4 as reference.
+} nrf_saadc_reference_t;
+
+
+/**
+ * @brief Analog-to-digital converter acquisition time.
+ */
+typedef enum
+{
+    NRF_SAADC_ACQTIME_3US  = SAADC_CH_CONFIG_TACQ_3us,  ///< 3 us.
+    NRF_SAADC_ACQTIME_5US  = SAADC_CH_CONFIG_TACQ_5us,  ///< 5 us.
+    NRF_SAADC_ACQTIME_10US = SAADC_CH_CONFIG_TACQ_10us, ///< 10 us.
+    NRF_SAADC_ACQTIME_15US = SAADC_CH_CONFIG_TACQ_15us, ///< 15 us.
+    NRF_SAADC_ACQTIME_20US = SAADC_CH_CONFIG_TACQ_20us, ///< 20 us.
+    NRF_SAADC_ACQTIME_40US = SAADC_CH_CONFIG_TACQ_40us  ///< 40 us.
+} nrf_saadc_acqtime_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel mode.
+ */
+typedef enum
+{
+    NRF_SAADC_MODE_SINGLE_ENDED = SAADC_CH_CONFIG_MODE_SE,  ///< Single ended, PSELN will be ignored, negative input to ADC shorted to GND.
+    NRF_SAADC_MODE_DIFFERENTIAL = SAADC_CH_CONFIG_MODE_Diff ///< Differential mode.
+} nrf_saadc_mode_t;
+
+
+/**
+ * @brief Analog-to-digital converter tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_SAADC_TASK_START           = offsetof(NRF_SAADC_Type, TASKS_START),           ///< Start the ADC and prepare the result buffer in RAM.
+    NRF_SAADC_TASK_SAMPLE          = offsetof(NRF_SAADC_Type, TASKS_SAMPLE),          ///< Take one ADC sample. If scan is enabled, all channels are sampled.
+    NRF_SAADC_TASK_STOP            = offsetof(NRF_SAADC_Type, TASKS_STOP),            ///< Stop the ADC and terminate any on-going conversion.
+    NRF_SAADC_TASK_CALIBRATEOFFSET = offsetof(NRF_SAADC_Type, TASKS_CALIBRATEOFFSET), ///< Starts offset auto-calibration.
+} nrf_saadc_task_t;
+
+
+/**
+ * @brief Analog-to-digital converter events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+    NRF_SAADC_EVENT_STARTED       = offsetof(NRF_SAADC_Type, EVENTS_STARTED),       ///< The ADC has started.
+    NRF_SAADC_EVENT_END           = offsetof(NRF_SAADC_Type, EVENTS_END),           ///< The ADC has filled up the result buffer.
+    NRF_SAADC_EVENT_CALIBRATEDONE = offsetof(NRF_SAADC_Type, EVENTS_CALIBRATEDONE), ///< Calibration is complete.
+    NRF_SAADC_EVENT_STOPPED       = offsetof(NRF_SAADC_Type, EVENTS_STOPPED),       ///< The ADC has stopped.
+    NRF_SAADC_EVENT_CH0_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITH),  ///< Last result is equal or above CH[0].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH0_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[0].LIMITL),  ///< Last result is equal or below CH[0].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH1_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITH),  ///< Last result is equal or above CH[1].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH1_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[1].LIMITL),  ///< Last result is equal or below CH[1].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH2_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITH),  ///< Last result is equal or above CH[2].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH2_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[2].LIMITL),  ///< Last result is equal or below CH[2].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH3_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITH),  ///< Last result is equal or above CH[3].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH3_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[3].LIMITL),  ///< Last result is equal or below CH[3].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH4_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITH),  ///< Last result is equal or above CH[4].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH4_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[4].LIMITL),  ///< Last result is equal or below CH[4].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH5_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITH),  ///< Last result is equal or above CH[5].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH5_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[5].LIMITL),  ///< Last result is equal or below CH[5].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH6_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITH),  ///< Last result is equal or above CH[6].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH6_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[6].LIMITL),  ///< Last result is equal or below CH[6].LIMIT.LOW.
+    NRF_SAADC_EVENT_CH7_LIMITH    = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITH),  ///< Last result is equal or above CH[7].LIMIT.HIGH.
+    NRF_SAADC_EVENT_CH7_LIMITL    = offsetof(NRF_SAADC_Type, EVENTS_CH[7].LIMITL)   ///< Last result is equal or below CH[7].LIMIT.LOW.
+} nrf_saadc_event_t;
+
+
+/**
+ * @brief Analog-to-digital converter interrupt masks.
+ */
+typedef enum
+{
+    NRF_SAADC_INT_STARTED   = SAADC_INTENSET_STARTED_Msk,   ///< Interrupt on EVENTS_STARTED event.
+    NRF_SAADC_INT_END       = SAADC_INTENSET_END_Msk,       ///< Interrupt on EVENTS_END event.
+    NRF_SAADC_INT_STOPPED   = SAADC_INTENSET_STOPPED_Msk,   ///< Interrupt on EVENTS_STOPPED event.
+    NRF_SAADC_INT_CH0LIMITH = SAADC_INTENSET_CH0LIMITH_Msk, ///< Interrupt on EVENTS_CH[0].LIMITH event.
+    NRF_SAADC_INT_CH0LIMITL = SAADC_INTENSET_CH0LIMITL_Msk, ///< Interrupt on EVENTS_CH[0].LIMITL event.
+    NRF_SAADC_INT_CH1LIMITH = SAADC_INTENSET_CH1LIMITH_Msk, ///< Interrupt on EVENTS_CH[1].LIMITH event.
+    NRF_SAADC_INT_CH1LIMITL = SAADC_INTENSET_CH1LIMITL_Msk, ///< Interrupt on EVENTS_CH[1].LIMITL event.
+    NRF_SAADC_INT_CH2LIMITH = SAADC_INTENSET_CH2LIMITH_Msk, ///< Interrupt on EVENTS_CH[2].LIMITH event.
+    NRF_SAADC_INT_CH2LIMITL = SAADC_INTENSET_CH2LIMITL_Msk, ///< Interrupt on EVENTS_CH[2].LIMITL event.
+    NRF_SAADC_INT_CH3LIMITH = SAADC_INTENSET_CH3LIMITH_Msk, ///< Interrupt on EVENTS_CH[3].LIMITH event.
+    NRF_SAADC_INT_CH3LIMITL = SAADC_INTENSET_CH3LIMITL_Msk, ///< Interrupt on EVENTS_CH[3].LIMITL event.
+    NRF_SAADC_INT_CH4LIMITH = SAADC_INTENSET_CH4LIMITH_Msk, ///< Interrupt on EVENTS_CH[4].LIMITH event.
+    NRF_SAADC_INT_CH4LIMITL = SAADC_INTENSET_CH4LIMITL_Msk, ///< Interrupt on EVENTS_CH[4].LIMITL event.
+    NRF_SAADC_INT_CH5LIMITH = SAADC_INTENSET_CH5LIMITH_Msk, ///< Interrupt on EVENTS_CH[5].LIMITH event.
+    NRF_SAADC_INT_CH5LIMITL = SAADC_INTENSET_CH5LIMITL_Msk, ///< Interrupt on EVENTS_CH[5].LIMITL event.
+    NRF_SAADC_INT_CH6LIMITH = SAADC_INTENSET_CH6LIMITH_Msk, ///< Interrupt on EVENTS_CH[6].LIMITH event.
+    NRF_SAADC_INT_CH6LIMITL = SAADC_INTENSET_CH6LIMITL_Msk, ///< Interrupt on EVENTS_CH[6].LIMITL event.
+    NRF_SAADC_INT_CH7LIMITH = SAADC_INTENSET_CH7LIMITH_Msk, ///< Interrupt on EVENTS_CH[7].LIMITH event.
+    NRF_SAADC_INT_CH7LIMITL = SAADC_INTENSET_CH7LIMITL_Msk, ///< Interrupt on EVENTS_CH[7].LIMITL event.
+    NRF_SAADC_INT_ALL       = 0x7FFFFFFFUL                  ///< Mask of all interrupts.
+} nrf_saadc_int_mask_t;
+
+
+/**
+ * @brief Analog-to-digital converter value limit type.
+ */
+typedef enum
+{
+    NRF_SAADC_LIMIT_LOW  = 0,
+    NRF_SAADC_LIMIT_HIGH = 1
+} nrf_saadc_limit_t;
+
+
+typedef int16_t nrf_saadc_value_t;  ///< Type of a single ADC conversion result.
+
+
+/**
+ * @brief Analog-to-digital converter configuration structure.
+ */
+typedef struct
+{
+    nrf_saadc_resolution_t resolution;
+    nrf_saadc_oversample_t oversample;
+    nrf_saadc_value_t *    buffer;
+    uint32_t               buffer_size;
+} nrf_saadc_config_t;
+
+
+/**
+ * @brief Analog-to-digital converter channel configuration structure.
+ */
+typedef struct
+{
+    nrf_saadc_resistor_t  resistor_p;
+    nrf_saadc_resistor_t  resistor_n;
+    nrf_saadc_gain_t      gain;
+    nrf_saadc_reference_t reference;
+    nrf_saadc_acqtime_t   acq_time;
+    nrf_saadc_mode_t      mode;
+    nrf_saadc_input_t     pin_p;
+    nrf_saadc_input_t     pin_n;
+} nrf_saadc_channel_config_t;
+
+
+/**
+ * @brief Function for triggering a specific SAADC task.
+ *
+ * @param[in] saadc_task SAADC task.
+ */
+__STATIC_INLINE void nrf_saadc_task_trigger(nrf_saadc_task_t saadc_task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task)) = 0x1UL;
+}
+
+
+/**
+ * @brief Function for getting the address of a specific SAADC task register.
+ *
+ * @param[in] saadc_task SAADC task.
+ *
+ * @return Address of the specified SAADC task.
+ */
+__STATIC_INLINE uint32_t nrf_saadc_task_address_get(nrf_saadc_task_t saadc_task)
+{
+    return (uint32_t)((uint8_t *)NRF_SAADC + (uint32_t)saadc_task);
+}
+
+
+/**
+ * @brief Function for getting the state of a specific SAADC event.
+ *
+ * @param[in] saadc_event SAADC event.
+ *
+ * @return State of the specified SAADC event.
+ */
+__STATIC_INLINE bool nrf_saadc_event_check(nrf_saadc_event_t saadc_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
+}
+
+
+/**
+ * @brief Function for clearing the specific SAADC event.
+ *
+ * @param[in] saadc_event SAADC event.
+ */
+__STATIC_INLINE void nrf_saadc_event_clear(nrf_saadc_event_t saadc_event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event)) = 0x0UL;
+}
+
+
+/**
+ * @brief Function for getting the address of a specific SAADC event register.
+ *
+ * @param[in] saadc_event SAADC event.
+ *
+ * @return Address of the specified SAADC event.
+ */
+__STATIC_INLINE volatile uint32_t * nrf_saadc_event_address_get(nrf_saadc_event_t saadc_event)
+{
+    return (volatile uint32_t *)((uint8_t *)NRF_SAADC + (uint32_t)saadc_event);
+}
+
+
+/**
+ * @brief Function for getting the address of a specific SAADC limit event register.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] limit_type Low limit or high limit.
+ *
+ * @return Address of the specified SAADC limit event.
+ */
+__STATIC_INLINE volatile uint32_t * nrf_saadc_event_limit_address_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+{
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
+    if (limit_type == NRF_SAADC_LIMIT_HIGH)
+    {
+        return &NRF_SAADC->EVENTS_CH[channel].LIMITH;
+    }
+    else
+    {
+        return &NRF_SAADC->EVENTS_CH[channel].LIMITL;
+    }
+}
+
+
+/**
+ * @brief Function for getting the SAADC channel monitoring limit events.
+ *
+ * @param[in] channel    Channel number.
+ * @param[in] limit_type Low limit or high limit.
+ */
+__STATIC_INLINE nrf_saadc_event_t nrf_saadc_event_limit_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+{
+    if (limit_type == NRF_SAADC_LIMIT_HIGH)
+    {
+        return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITH + 
+                        (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITH - NRF_SAADC_EVENT_CH0_LIMITH)
+                        * (uint32_t) channel );
+    }
+    else
+    {
+        return (nrf_saadc_event_t)( (uint32_t) NRF_SAADC_EVENT_CH0_LIMITL + 
+                        (uint32_t) (NRF_SAADC_EVENT_CH1_LIMITL - NRF_SAADC_EVENT_CH0_LIMITL)
+                        * (uint32_t) channel );
+    }
+}
+
+
+/**
+ * @brief Function for configuring the input pins for a specific SAADC channel.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] pselp   Positive input.
+ * @param[in] pseln   Negative input. Set to NRF_SAADC_INPUT_DISABLED in single ended mode.
+ */
+__STATIC_INLINE void nrf_saadc_channel_input_set(uint8_t channel,
+                                                 nrf_saadc_input_t pselp,
+                                                 nrf_saadc_input_t pseln)
+{
+    NRF_SAADC->CH[channel].PSELN = pseln;
+    NRF_SAADC->CH[channel].PSELP = pselp;
+}
+
+
+/**
+ * @brief Function for setting the SAADC channel monitoring limits.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] low     Low limit.
+ * @param[in] high    High limit.
+ */
+__STATIC_INLINE void nrf_saadc_channel_limits_set(uint8_t channel, int16_t low, int16_t high)
+{
+    NRF_SAADC->CH[channel].LIMIT = (
+            (((uint32_t) low << SAADC_CH_LIMIT_LOW_Pos) & SAADC_CH_LIMIT_LOW_Msk)
+          | (((uint32_t) high << SAADC_CH_LIMIT_HIGH_Pos) & SAADC_CH_LIMIT_HIGH_Msk));
+}
+
+
+/**
+ * @brief Function for enabling specified SAADC interrupts.
+ *
+ * @param[in] saadc_int_mask Interrupt(s) to enable.
+ */
+__STATIC_INLINE void nrf_saadc_int_enable(uint32_t saadc_int_mask)
+{
+    NRF_SAADC->INTENSET = saadc_int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of specified SAADC interrupts.
+ *
+ * @param[in] saadc_int_mask Interrupt(s) to check.
+ *
+ * @retval true  If all specified interrupts are enabled.
+ * @retval false If at least one of the given interrupts is not enabled.
+ */
+__STATIC_INLINE bool nrf_saadc_int_enable_check(uint32_t saadc_int_mask)
+{
+    return (bool)(NRF_SAADC->INTENSET & saadc_int_mask);
+}
+
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param saadc_int_mask Interrupt(s) to disable.
+ */
+__STATIC_INLINE void nrf_saadc_int_disable(uint32_t saadc_int_mask)
+{
+    NRF_SAADC->INTENCLR = saadc_int_mask;
+}
+
+
+/**
+ * @brief Function for generating masks for SAADC channel limit interrupts.
+ * 
+ * @param[in] channel    SAADC channel number.
+ * @param[in] limit_type Limit type.
+ *
+ * @returns Interrupt mask.
+ */
+__STATIC_INLINE uint32_t nrf_saadc_limit_int_get(uint8_t channel, nrf_saadc_limit_t limit_type)
+{
+    ASSERT(channel < NRF_SAADC_CHANNEL_COUNT);
+    uint32_t mask = (limit_type == NRF_SAADC_LIMIT_LOW) ? NRF_SAADC_INT_CH0LIMITL : NRF_SAADC_INT_CH0LIMITH;
+    return mask << (channel * 2);
+}
+
+
+/**
+ * @brief Function for checking whether the SAADC is busy.
+ *
+ * This function checks whether the analog-to-digital converter is busy with a conversion.
+ *
+ * @retval true  If the SAADC is busy.
+ * @retval false If the SAADC is not busy.
+ */
+__STATIC_INLINE bool nrf_saadc_busy_check(void)
+{
+    //return ((NRF_SAADC->STATUS & SAADC_STATUS_STATUS_Msk) == SAADC_STATUS_STATUS_Msk);
+    //simplified for performance
+    return NRF_SAADC->STATUS;
+}
+
+
+/**
+ * @brief Function for enabling the SAADC.
+ *
+ * The analog-to-digital converter must be enabled before use.
+ */
+__STATIC_INLINE void nrf_saadc_enable(void)
+{
+    NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Enabled << SAADC_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for disabling the SAADC.
+ */
+__STATIC_INLINE void nrf_saadc_disable(void)
+{
+    NRF_SAADC->ENABLE = (SAADC_ENABLE_ENABLE_Disabled << SAADC_ENABLE_ENABLE_Pos);
+}
+
+
+/**
+ * @brief Function for checking if the SAADC is enabled.
+ *
+ * @retval true  If the SAADC is enabled.
+ * @retval false If the SAADC is not enabled.
+ */
+__STATIC_INLINE bool nrf_saadc_enable_check(void)
+{
+    //simplified for performance
+    return NRF_SAADC->ENABLE;
+}
+
+
+/**
+ * @brief Function for initializing the SAADC result buffer.
+ *
+ * @param[in] buffer Pointer to the result buffer.
+ * @param[in] num    Size of buffer in words.
+ */
+__STATIC_INLINE void nrf_saadc_buffer_init(nrf_saadc_value_t * buffer, uint32_t num)
+{
+    NRF_SAADC->RESULT.PTR = (uint32_t)buffer;
+    NRF_SAADC->RESULT.MAXCNT = num;
+}
+
+/**
+ * @brief Function for getting the number of buffer words transferred since last START operation.
+ *
+ * @returns Number of words transferred.
+ */
+__STATIC_INLINE uint16_t nrf_saadc_amount_get(void)
+{
+    return NRF_SAADC->RESULT.AMOUNT;
+}
+
+
+/**
+ * @brief Function for setting the SAADC sample resolution.
+ * 
+ * @param[in] resolution Bit resolution.
+ */
+__STATIC_INLINE void nrf_saadc_resolution_set(nrf_saadc_resolution_t resolution)
+{
+    NRF_SAADC->RESOLUTION = resolution;
+}
+
+
+/**
+ * @brief Function for configuring the oversampling feature.
+ *
+ * @param[in] oversample Oversampling mode.
+ */
+__STATIC_INLINE void nrf_saadc_oversample_set(nrf_saadc_oversample_t oversample)
+{
+    NRF_SAADC->OVERSAMPLE = oversample;
+}
+
+/**
+ * @brief Function for getting the oversampling feature configuration.
+ *
+ * @return Oversampling configuration.
+ */
+__STATIC_INLINE nrf_saadc_oversample_t nrf_saadc_oversample_get(void)
+{
+    return (nrf_saadc_oversample_t)NRF_SAADC->OVERSAMPLE;
+}
+
+/**
+ * @brief Function for initializing the SAADC channel.
+ *
+ * @param[in] channel Channel number.
+ * @param[in] config  Pointer to the channel configuration structure.
+ */
+void nrf_saadc_channel_init(uint8_t channel, nrf_saadc_channel_config_t const * const config);
+
+/**
+ *@}
+ **/
+ 
+#endif //  NRF52
+
+#endif /* NRF_SAADC_H_ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spi.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spi.h
new file mode 100644
index 0000000000..20dba2d598
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spi.h
@@ -0,0 +1,361 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @defgroup nrf_spi_hal SPI HAL
+ * @{
+ * @ingroup nrf_spi_master
+ *
+ * @brief Hardware access layer for accessing the SPI peripheral.
+ */
+
+#ifndef NRF_SPI_H__
+#define NRF_SPI_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+
+/**
+ * @brief This value can be used as a parameter for the @ref nrf_spi_pins_set
+ *        function to specify that a given SPI signal (SCK, MOSI, or MISO)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_SPI_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief SPI events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPI_EVENT_READY = offsetof(NRF_SPI_Type, EVENTS_READY) ///< TXD byte sent and RXD byte received.
+    /*lint -restore*/
+} nrf_spi_event_t;
+
+/**
+ * @brief SPI interrupts.
+ */
+typedef enum
+{
+    NRF_SPI_INT_READY_MASK = SPI_INTENSET_READY_Msk ///< Interrupt on READY event.
+} nrf_spi_int_mask_t;
+
+/**
+ * @brief SPI data rates.
+ */
+typedef enum
+{
+    NRF_SPI_FREQ_125K = SPI_FREQUENCY_FREQUENCY_K125,   ///< 125 kbps.
+    NRF_SPI_FREQ_250K = SPI_FREQUENCY_FREQUENCY_K250,   ///< 250 kbps.
+    NRF_SPI_FREQ_500K = SPI_FREQUENCY_FREQUENCY_K500,   ///< 500 kbps.
+    NRF_SPI_FREQ_1M   = SPI_FREQUENCY_FREQUENCY_M1,     ///< 1 Mbps.
+    NRF_SPI_FREQ_2M   = SPI_FREQUENCY_FREQUENCY_M2,     ///< 2 Mbps.
+    NRF_SPI_FREQ_4M   = SPI_FREQUENCY_FREQUENCY_M4,     ///< 4 Mbps.
+    // [conversion to 'int' needed to prevent compilers from complaining
+    //  that the provided value (0x80000000UL) is out of range of "int"]
+    NRF_SPI_FREQ_8M   = (int)SPI_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
+} nrf_spi_frequency_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_SPI_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_spi_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_SPI_BIT_ORDER_MSB_FIRST = SPI_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
+    NRF_SPI_BIT_ORDER_LSB_FIRST = SPI_CONFIG_ORDER_LsbFirst  ///< Least significant bit shifted out first.
+} nrf_spi_bit_order_t;
+
+
+/**
+ * @brief Function for clearing a specific SPI event.
+ *
+ * @param[in] p_spi     SPI instance.
+ * @param[in] spi_event Event to clear.
+ */
+__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_spi,
+                                         nrf_spi_event_t spi_event);
+
+/**
+ * @brief Function for checking the state of a specific SPI event.
+ *
+ * @param[in] p_spi     SPI instance.
+ * @param[in] spi_event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_spi,
+                                         nrf_spi_event_t spi_event);
+
+/**
+ * @brief Function for getting the address of a specific SPI event register.
+ *
+ * @param[in] p_spi     SPI instance.
+ * @param[in] spi_event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type  * p_spi,
+                                                     nrf_spi_event_t spi_event);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_spi         SPI instance.
+ * @param[in] spi_int_mask  Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_spi,
+                                        uint32_t spi_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_spi         SPI instance.
+ * @param[in] spi_int_mask  Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_spi,
+                                         uint32_t spi_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_spi   SPI instance.
+ * @param[in] spi_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_spi,
+                                              nrf_spi_int_mask_t spi_int);
+
+/**
+ * @brief Function for enabling the SPI peripheral.
+ *
+ * @param[in] p_spi SPI instance.
+ */
+__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_spi);
+
+/**
+ * @brief Function for disabling the SPI peripheral.
+ *
+ * @param[in] p_spi SPI instance.
+ */
+__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_spi);
+
+/**
+ * @brief Function for configuring SPI pins.
+ *
+ * If a given signal is not needed, pass the @ref NRF_SPI_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_spi     SPI instance.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] mosi_pin  MOSI pin number.
+ * @param[in] miso_pin  MISO pin number.
+ */
+__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_spi,
+                                      uint32_t sck_pin,
+                                      uint32_t mosi_pin,
+                                      uint32_t miso_pin);
+
+/**
+ * @brief Function for writing data to the SPI transmitter register.
+ *
+ * @param[in] p_spi SPI instance.
+ * @param[in] data  TX data to send.
+ */
+__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_spi, uint8_t data);
+
+/**
+ * @brief Function for reading data from the SPI receiver register.
+ *
+ * @param[in] p_spi SPI instance.
+ *
+ * @return RX data received.
+ */
+__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_spi);
+
+/**
+ * @brief Function for setting the SPI master data rate.
+ *
+ * @param[in] p_spi     SPI instance.
+ * @param[in] frequency SPI frequency.
+ */
+__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_spi,
+                                           nrf_spi_frequency_t frequency);
+
+/**
+ * @brief Function for setting the SPI configuration.
+ *
+ * @param[in] p_spi         SPI instance.
+ * @param[in] spi_mode      SPI mode.
+ * @param[in] spi_bit_order SPI bit order.
+ */
+__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_spi,
+                                       nrf_spi_mode_t spi_mode,
+                                       nrf_spi_bit_order_t spi_bit_order);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_spi_event_clear(NRF_SPI_Type * p_spi,
+                                         nrf_spi_event_t spi_event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_spi_event_check(NRF_SPI_Type * p_spi,
+                                         nrf_spi_event_t spi_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event);
+}
+
+__STATIC_INLINE uint32_t * nrf_spi_event_address_get(NRF_SPI_Type * p_spi,
+                                                     nrf_spi_event_t spi_event)
+{
+    return (uint32_t *)((uint8_t *)p_spi + (uint32_t)spi_event);
+}
+
+__STATIC_INLINE void nrf_spi_int_enable(NRF_SPI_Type * p_spi,
+                                        uint32_t spi_int_mask)
+{
+    p_spi->INTENSET = spi_int_mask;
+}
+
+__STATIC_INLINE void nrf_spi_int_disable(NRF_SPI_Type * p_spi,
+                                         uint32_t spi_int_mask)
+{
+    p_spi->INTENCLR = spi_int_mask;
+}
+
+__STATIC_INLINE bool nrf_spi_int_enable_check(NRF_SPI_Type * p_spi,
+                                              nrf_spi_int_mask_t spi_int)
+{
+    return (bool)(p_spi->INTENSET & spi_int);
+}
+
+__STATIC_INLINE void nrf_spi_enable(NRF_SPI_Type * p_spi)
+{
+    p_spi->ENABLE = (SPI_ENABLE_ENABLE_Enabled << SPI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spi_disable(NRF_SPI_Type * p_spi)
+{
+    p_spi->ENABLE = (SPI_ENABLE_ENABLE_Disabled << SPI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spi_pins_set(NRF_SPI_Type * p_spi,
+                                      uint32_t sck_pin,
+                                      uint32_t mosi_pin,
+                                      uint32_t miso_pin)
+{
+    p_spi->PSELSCK  = sck_pin;
+    p_spi->PSELMOSI = mosi_pin;
+    p_spi->PSELMISO = miso_pin;
+}
+
+__STATIC_INLINE void nrf_spi_txd_set(NRF_SPI_Type * p_spi, uint8_t data)
+{
+    p_spi->TXD = data;
+}
+
+__STATIC_INLINE uint8_t nrf_spi_rxd_get(NRF_SPI_Type * p_spi)
+{
+    return p_spi->RXD;
+}
+
+__STATIC_INLINE void nrf_spi_frequency_set(NRF_SPI_Type * p_spi,
+                                           nrf_spi_frequency_t frequency)
+{
+    p_spi->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE void nrf_spi_configure(NRF_SPI_Type * p_spi,
+                                       nrf_spi_mode_t spi_mode,
+                                       nrf_spi_bit_order_t spi_bit_order)
+{
+    uint32_t config = (spi_bit_order == NRF_SPI_BIT_ORDER_MSB_FIRST ?
+        SPI_CONFIG_ORDER_MsbFirst : SPI_CONFIG_ORDER_LsbFirst);
+    switch (spi_mode)
+    {
+    default:
+    case NRF_SPI_MODE_0:
+        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Leading    << SPI_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPI_MODE_1:
+        config |= (SPI_CONFIG_CPOL_ActiveHigh << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPI_MODE_2:
+        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Leading    << SPI_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPI_MODE_3:
+        config |= (SPI_CONFIG_CPOL_ActiveLow  << SPI_CONFIG_CPOL_Pos) |
+                  (SPI_CONFIG_CPHA_Trailing   << SPI_CONFIG_CPHA_Pos);
+        break;
+    }
+    p_spi->CONFIG = config;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_SPI_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spim.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spim.h
new file mode 100644
index 0000000000..495b4dd316
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spim.h
@@ -0,0 +1,547 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @defgroup nrf_spim_hal SPIM HAL
+ * @{
+ * @ingroup nrf_spi_master
+ *
+ * @brief Hardware access layer for accessing the SPIM peripheral.
+ */
+
+#ifndef NRF_SPIM_H__
+#define NRF_SPIM_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+
+/**
+ * @brief This value can be used as a parameter for the @ref nrf_spim_pins_set
+ *        function to specify that a given SPI signal (SCK, MOSI, or MISO)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_SPIM_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief SPIM tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIM_TASK_START   = offsetof(NRF_SPIM_Type, TASKS_START),   ///< Start SPI transaction.
+    NRF_SPIM_TASK_STOP    = offsetof(NRF_SPIM_Type, TASKS_STOP),    ///< Stop SPI transaction.
+    NRF_SPIM_TASK_SUSPEND = offsetof(NRF_SPIM_Type, TASKS_SUSPEND), ///< Suspend SPI transaction.
+    NRF_SPIM_TASK_RESUME  = offsetof(NRF_SPIM_Type, TASKS_RESUME)   ///< Resume SPI transaction.
+    /*lint -restore*/
+} nrf_spim_task_t;
+
+/**
+ * @brief SPIM events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIM_EVENT_STOPPED = offsetof(NRF_SPIM_Type, EVENTS_STOPPED), ///< SPI transaction has stopped.
+    NRF_SPIM_EVENT_ENDRX   = offsetof(NRF_SPIM_Type, EVENTS_ENDRX),   ///< End of RXD buffer reached.
+#ifdef NRF52
+    NRF_SPIM_EVENT_END     = offsetof(NRF_SPIM_Type, EVENTS_END),     ///< End of RXD buffer and TXD buffer reached.
+#endif
+    NRF_SPIM_EVENT_ENDTX   = offsetof(NRF_SPIM_Type, EVENTS_ENDTX),   ///< End of TXD buffer reached.
+    NRF_SPIM_EVENT_STARTED = offsetof(NRF_SPIM_Type, EVENTS_STARTED)  ///< Transaction started.
+    /*lint -restore*/
+} nrf_spim_event_t;
+
+#ifdef NRF52
+/**
+ * @brief SPIM shortcuts.
+ */
+typedef enum
+{
+    NRF_SPIM_SHORT_END_START_MASK = SPIM_SHORTS_END_START_Msk ///< Shortcut between END event and START task.
+} nrf_spim_short_mask_t;
+#endif
+
+/**
+ * @brief SPIM interrupts.
+ */
+typedef enum
+{
+    NRF_SPIM_INT_STOPPED_MASK = SPIM_INTENSET_STOPPED_Msk, ///< Interrupt on STOPPED event.
+    NRF_SPIM_INT_ENDRX_MASK   = SPIM_INTENSET_ENDRX_Msk,   ///< Interrupt on ENDRX event.
+#ifdef NRF52
+    NRF_SPIM_INT_END_MASK     = SPIM_INTENSET_END_Msk,     ///< Interrupt on END event.
+#endif
+    NRF_SPIM_INT_ENDTX_MASK   = SPIM_INTENSET_ENDTX_Msk,   ///< Interrupt on ENDTX event.
+    NRF_SPIM_INT_STARTED_MASK = SPIM_INTENSET_STARTED_Msk  ///< Interrupt on STARTED event.
+} nrf_spim_int_mask_t;
+
+/**
+ * @brief SPI master data rates.
+ */
+typedef enum
+{
+    NRF_SPIM_FREQ_125K = SPIM_FREQUENCY_FREQUENCY_K125,   ///< 125 kbps.
+    NRF_SPIM_FREQ_250K = SPIM_FREQUENCY_FREQUENCY_K250,   ///< 250 kbps.
+    NRF_SPIM_FREQ_500K = SPIM_FREQUENCY_FREQUENCY_K500,   ///< 500 kbps.
+    NRF_SPIM_FREQ_1M   = SPIM_FREQUENCY_FREQUENCY_M1,     ///< 1 Mbps.
+    NRF_SPIM_FREQ_2M   = SPIM_FREQUENCY_FREQUENCY_M2,     ///< 2 Mbps.
+    NRF_SPIM_FREQ_4M   = SPIM_FREQUENCY_FREQUENCY_M4,     ///< 4 Mbps.
+    // [conversion to 'int' needed to prevent compilers from complaining
+    //  that the provided value (0x80000000UL) is out of range of "int"]
+    NRF_SPIM_FREQ_8M   = (int)SPIM_FREQUENCY_FREQUENCY_M8 ///< 8 Mbps.
+} nrf_spim_frequency_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_SPIM_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_SPIM_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_SPIM_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_SPIM_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_spim_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_SPIM_BIT_ORDER_MSB_FIRST = SPIM_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
+    NRF_SPIM_BIT_ORDER_LSB_FIRST = SPIM_CONFIG_ORDER_LsbFirst  ///< Least significant bit shifted out first.
+} nrf_spim_bit_order_t;
+
+
+/**
+ * @brief Function for activating a specific SPIM task.
+ *
+ * @param[in] p_spim    SPIM instance.
+ * @param[in] spim_task Task to activate.
+ */
+__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_spim,
+                                           nrf_spim_task_t spim_task);
+
+/**
+ * @brief Function for getting the address of a specific SPIM task register.
+ *
+ * @param[in] p_spim    SPIM instance.
+ * @param[in] spim_task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_spim,
+                                                   nrf_spim_task_t spim_task);
+
+/**
+ * @brief Function for clearing a specific SPIM event.
+ *
+ * @param[in] p_spim     SPIM instance.
+ * @param[in] spim_event Event to clear.
+ */
+__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_spim,
+                                          nrf_spim_event_t spim_event);
+
+/**
+ * @brief Function for checking the state of a specific SPIM event.
+ *
+ * @param[in] p_spim     SPIM instance.
+ * @param[in] spim_event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_spim,
+                                          nrf_spim_event_t spim_event);
+
+/**
+ * @brief Function for getting the address of a specific SPIM event register.
+ *
+ * @param[in] p_spim     SPIM instance.
+ * @param[in] spim_event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type  * p_spim,
+                                                    nrf_spim_event_t spim_event);
+#ifdef NRF52
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_spim           SPIM instance.
+ * @param[in] spim_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_spim,
+                                            uint32_t spim_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_spim           SPIM instance.
+ * @param[in] spim_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_spim,
+                                             uint32_t spim_shorts_mask);
+
+/**
+ * @brief Function for getting shorts setting.
+ *
+ * @param[in] p_spim           SPIM instance.
+ */
+__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_spim);
+#endif
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_spim        SPIM instance.
+ * @param[in] spim_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_spim,
+                                         uint32_t spim_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_spim        SPIM instance.
+ * @param[in] spim_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_spim,
+                                          uint32_t spim_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_spim   SPIM instance.
+ * @param[in] spim_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_spim,
+                                               nrf_spim_int_mask_t spim_int);
+
+/**
+ * @brief Function for enabling the SPIM peripheral.
+ *
+ * @param[in] p_spim SPIM instance.
+ */
+__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_spim);
+
+/**
+ * @brief Function for disabling the SPIM peripheral.
+ *
+ * @param[in] p_spim SPIM instance.
+ */
+__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_spim);
+
+/**
+ * @brief Function for configuring SPIM pins.
+ *
+ * If a given signal is not needed, pass the @ref NRF_SPIM_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_spim    SPIM instance.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] mosi_pin  MOSI pin number.
+ * @param[in] miso_pin  MISO pin number.
+ */
+__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_spim,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin);
+
+/**
+ * @brief Function for setting the SPI master data rate.
+ *
+ * @param[in] p_spim    SPIM instance.
+ * @param[in] frequency SPI frequency.
+ */
+__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_spim,
+                                            nrf_spim_frequency_t frequency);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in]  p_spim   SPIM instance.
+ * @param[in]  p_buffer Pointer to the buffer with data to send.
+ * @param[in]  length   Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_spim,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_spim   SPIM instance.
+ * @param[in] p_buffer Pointer to the buffer for received data.
+ * @param[in] length   Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_spim,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length);
+
+/**
+ * @brief Function for setting the SPI configuration.
+ *
+ * @param[in] p_spim        SPIM instance.
+ * @param[in] spi_mode      SPI mode.
+ * @param[in] spi_bit_order SPI bit order.
+ */
+__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_spim,
+                                        nrf_spim_mode_t spi_mode,
+                                        nrf_spim_bit_order_t spi_bit_order);
+
+/**
+ * @brief Function for setting the over-read character.
+ *
+ * @param[in] p_spim SPIM instance.
+ * @param[in] orc    Over-read character that is clocked out in case of
+ *                   an over-read of the TXD buffer.
+ */
+__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_spim,
+                                      uint8_t orc);
+
+#ifdef NRF52
+/**
+ * @brief Function for enabling the TX list feature.
+ *
+ * @param[in] p_spim SPIM instance.
+ */
+__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_spim);
+
+/**
+ * @brief Function for disabling the TX list feature.
+ *
+ * @param[in] p_spim SPIM instance.
+ */
+__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_spim);
+
+/**
+ * @brief Function for enabling the RX list feature.
+ *
+ * @param[in] p_spim SPIM instance.
+ */
+__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_spim);
+
+/**
+ * @brief Function for disabling the RX list feature.
+ *
+ * @param[in] p_spim SPIM instance.
+ */
+__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_spim);
+#endif
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_spim_task_trigger(NRF_SPIM_Type * p_spim,
+                                           nrf_spim_task_t spim_task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_spim_task_address_get(NRF_SPIM_Type * p_spim,
+                                                   nrf_spim_task_t spim_task)
+{
+    return (uint32_t)((uint8_t *)p_spim + (uint32_t)spim_task);
+}
+
+__STATIC_INLINE void nrf_spim_event_clear(NRF_SPIM_Type * p_spim,
+                                          nrf_spim_event_t spim_event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_spim_event_check(NRF_SPIM_Type * p_spim,
+                                          nrf_spim_event_t spim_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_spim + (uint32_t)spim_event);
+}
+
+__STATIC_INLINE uint32_t nrf_spim_event_address_get(NRF_SPIM_Type * p_spim,
+                                                    nrf_spim_event_t spim_event)
+{
+    return (uint32_t)((uint8_t *)p_spim + (uint32_t)spim_event);
+}
+
+#ifdef NRF52
+__STATIC_INLINE void nrf_spim_shorts_enable(NRF_SPIM_Type * p_spim,
+                                            uint32_t spim_shorts_mask)
+{
+    p_spim->SHORTS |= spim_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_spim_shorts_disable(NRF_SPIM_Type * p_spim,
+                                             uint32_t spim_shorts_mask)
+{
+    p_spim->SHORTS &= ~(spim_shorts_mask);
+}
+
+__STATIC_INLINE uint32_t nrf_spim_shorts_get(NRF_SPIM_Type * p_spim)
+{
+    return p_spim->SHORTS;
+}
+#endif
+__STATIC_INLINE void nrf_spim_int_enable(NRF_SPIM_Type * p_spim,
+                                         uint32_t spim_int_mask)
+{
+    p_spim->INTENSET = spim_int_mask;
+}
+
+__STATIC_INLINE void nrf_spim_int_disable(NRF_SPIM_Type * p_spim,
+                                          uint32_t spim_int_mask)
+{
+    p_spim->INTENCLR = spim_int_mask;
+}
+
+__STATIC_INLINE bool nrf_spim_int_enable_check(NRF_SPIM_Type * p_spim,
+                                               nrf_spim_int_mask_t spim_int)
+{
+    return (bool)(p_spim->INTENSET & spim_int);
+}
+
+__STATIC_INLINE void nrf_spim_enable(NRF_SPIM_Type * p_spim)
+{
+    p_spim->ENABLE = (SPIM_ENABLE_ENABLE_Enabled << SPIM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spim_disable(NRF_SPIM_Type * p_spim)
+{
+    p_spim->ENABLE = (SPIM_ENABLE_ENABLE_Disabled << SPIM_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spim_pins_set(NRF_SPIM_Type * p_spim,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin)
+{
+    p_spim->PSEL.SCK  = sck_pin;
+    p_spim->PSEL.MOSI = mosi_pin;
+    p_spim->PSEL.MISO = miso_pin;
+}
+
+__STATIC_INLINE void nrf_spim_frequency_set(NRF_SPIM_Type * p_spim,
+                                            nrf_spim_frequency_t frequency)
+{
+    p_spim->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE void nrf_spim_tx_buffer_set(NRF_SPIM_Type * p_spim,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length)
+{
+    p_spim->TXD.PTR    = (uint32_t)p_buffer;
+    p_spim->TXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_spim_rx_buffer_set(NRF_SPIM_Type * p_spim,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length)
+{
+    p_spim->RXD.PTR    = (uint32_t)p_buffer;
+    p_spim->RXD.MAXCNT = length;
+}
+
+__STATIC_INLINE void nrf_spim_configure(NRF_SPIM_Type * p_spim,
+                                        nrf_spim_mode_t spi_mode,
+                                        nrf_spim_bit_order_t spi_bit_order)
+{
+    uint32_t config = (spi_bit_order == NRF_SPIM_BIT_ORDER_MSB_FIRST ?
+        SPIM_CONFIG_ORDER_MsbFirst : SPIM_CONFIG_ORDER_LsbFirst);
+    switch (spi_mode)
+    {
+    default:
+    case NRF_SPIM_MODE_0:
+        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIM_MODE_1:
+        config |= (SPIM_CONFIG_CPOL_ActiveHigh << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIM_MODE_2:
+        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Leading    << SPIM_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIM_MODE_3:
+        config |= (SPIM_CONFIG_CPOL_ActiveLow  << SPIM_CONFIG_CPOL_Pos) |
+                  (SPIM_CONFIG_CPHA_Trailing   << SPIM_CONFIG_CPHA_Pos);
+        break;
+    }
+    p_spim->CONFIG = config;
+}
+
+__STATIC_INLINE void nrf_spim_orc_set(NRF_SPIM_Type * p_spim,
+                                      uint8_t orc)
+{
+    p_spim->ORC = orc;
+}
+
+#ifdef NRF52
+__STATIC_INLINE void nrf_spim_tx_list_enable(NRF_SPIM_Type * p_spim)
+{
+    p_spim->TXD.LIST = 1;
+}
+
+__STATIC_INLINE void nrf_spim_tx_list_disable(NRF_SPIM_Type * p_spim)
+{
+    p_spim->TXD.LIST = 0;
+}
+
+__STATIC_INLINE void nrf_spim_rx_list_enable(NRF_SPIM_Type * p_spim)
+{
+    p_spim->RXD.LIST = 1;
+}
+
+__STATIC_INLINE void nrf_spim_rx_list_disable(NRF_SPIM_Type * p_spim)
+{
+    p_spim->RXD.LIST = 0;
+}
+#endif
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_SPIM_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spis.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spis.h
new file mode 100644
index 0000000000..6312ce131c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_spis.h
@@ -0,0 +1,539 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @defgroup nrf_spis_hal SPIS HAL
+ * @{
+ * @ingroup nrf_spis
+ *
+ * @brief Hardware access layer for accessing the SPIS peripheral.
+ */
+
+#ifndef NRF_SPIS_H__
+#define NRF_SPIS_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+
+/**
+ * @brief This value can be used as a parameter for the @ref nrf_spis_pins_set
+ *        function to specify that a given SPI signal (SCK, MOSI, or MISO)
+ *        shall not be connected to a physical pin.
+ */
+#define NRF_SPIS_PIN_NOT_CONNECTED  0xFFFFFFFF
+
+
+/**
+ * @brief SPIS tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIS_TASK_ACQUIRE = offsetof(NRF_SPIS_Type, TASKS_ACQUIRE), ///< Acquire SPI semaphore.
+    NRF_SPIS_TASK_RELEASE = offsetof(NRF_SPIS_Type, TASKS_RELEASE), ///< Release SPI semaphore, enabling the SPI slave to acquire it.
+    /*lint -restore*/
+} nrf_spis_task_t;
+
+/**
+ * @brief SPIS events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_SPIS_EVENT_END      = offsetof(NRF_SPIS_Type, EVENTS_END),     ///< Granted transaction completed.
+    NRF_SPIS_EVENT_ACQUIRED = offsetof(NRF_SPIS_Type, EVENTS_ACQUIRED) ///< Semaphore acquired.
+    /*lint -restore*/
+} nrf_spis_event_t;
+
+/**
+ * @brief SPIS shortcuts.
+ */
+typedef enum
+{
+    NRF_SPIS_SHORT_END_ACQUIRE = SPIS_SHORTS_END_ACQUIRE_Msk ///< Shortcut between END event and ACQUIRE task.
+} nrf_spis_short_mask_t;
+
+/**
+ * @brief SPIS interrupts.
+ */
+typedef enum
+{
+    NRF_SPIS_INT_END_MASK      = SPIS_INTENSET_END_Msk,     ///< Interrupt on END event.
+    NRF_SPIS_INT_ACQUIRED_MASK = SPIS_INTENSET_ACQUIRED_Msk ///< Interrupt on ACQUIRED event.
+} nrf_spis_int_mask_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_SPIS_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_SPIS_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_SPIS_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_SPIS_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_spis_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_SPIS_BIT_ORDER_MSB_FIRST = SPIS_CONFIG_ORDER_MsbFirst, ///< Most significant bit shifted out first.
+    NRF_SPIS_BIT_ORDER_LSB_FIRST = SPIS_CONFIG_ORDER_LsbFirst  ///< Least significant bit shifted out first.
+} nrf_spis_bit_order_t;
+
+/**
+ * @brief SPI semaphore status.
+ */
+typedef enum
+{
+    NRF_SPIS_SEMSTAT_FREE       = 0, ///< Semaphore is free.
+    NRF_SPIS_SEMSTAT_CPU        = 1, ///< Semaphore is assigned to the CPU.
+    NRF_SPIS_SEMSTAT_SPIS       = 2, ///< Semaphore is assigned to the SPI slave.
+    NRF_SPIS_SEMSTAT_CPUPENDING = 3  ///< Semaphore is assigned to the SPI, but a handover to the CPU is pending.
+} nrf_spis_semstat_t;
+
+/**
+ * @brief SPIS status.
+ */
+typedef enum
+{
+    NRF_SPIS_STATUS_OVERREAD = SPIS_STATUS_OVERREAD_Msk, ///< TX buffer over-read detected and prevented.
+    NRF_SPIS_STATUS_OVERFLOW = SPIS_STATUS_OVERFLOW_Msk  ///< RX buffer overflow detected and prevented.
+} nrf_spis_status_mask_t;
+
+/**
+ * @brief Function for activating a specific SPIS task.
+ *
+ * @param[in] p_spis    SPIS instance.
+ * @param[in] spis_task Task to activate.
+ */
+__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_spis,
+                                           nrf_spis_task_t spis_task);
+
+/**
+ * @brief Function for getting the address of a specific SPIS task register.
+ *
+ * @param[in] p_spis    SPIS instance.
+ * @param[in] spis_task Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_spis,
+                                                   nrf_spis_task_t spis_task);
+
+/**
+ * @brief Function for clearing a specific SPIS event.
+ *
+ * @param[in] p_spis     SPIS instance.
+ * @param[in] spis_event Event to clear.
+ */
+__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type * p_spis,
+                                          nrf_spis_event_t spis_event);
+
+/**
+ * @brief Function for checking the state of a specific SPIS event.
+ *
+ * @param[in] p_spis     SPIS instance.
+ * @param[in] spis_event Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_spis,
+                                          nrf_spis_event_t spis_event);
+
+/**
+ * @brief Function for getting the address of a specific SPIS event register.
+ *
+ * @param[in] p_spis     SPIS instance.
+ * @param[in] spis_event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_spis,
+                                                    nrf_spis_event_t spis_event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_spis           SPIS instance.
+ * @param[in] spis_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_spis,
+                                            uint32_t spis_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_spis           SPIS instance.
+ * @param[in] spis_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_spis,
+                                             uint32_t spis_shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_spis        SPIS instance.
+ * @param[in] spis_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_spis,
+                                         uint32_t spis_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_spis        SPIS instance.
+ * @param[in] spis_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_spis,
+                                          uint32_t spis_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_spis   SPIS instance.
+ * @param[in] spis_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_spis,
+                                               nrf_spis_int_mask_t spis_int);
+
+/**
+ * @brief Function for enabling the SPIS peripheral.
+ *
+ * @param[in] p_spis SPIS instance.
+ */
+__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_spis);
+
+/**
+ * @brief Function for disabling the SPIS peripheral.
+ *
+ * @param[in] p_spis SPIS instance.
+ */
+__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_spis);
+
+/**
+ * @brief Function for retrieving the SPIS semaphore status.
+ *
+ * @param[in] p_spis SPIS instance.
+ *
+ * @returns Current semaphore status.
+ */
+__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_spis);
+
+/**
+ * @brief Function for retrieving the SPIS status.
+ *
+ * @param[in] p_spis SPIS instance.
+ *
+ * @returns Current SPIS status.
+ */
+__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_spis);
+
+/**
+ * @brief Function for configuring SPIS pins.
+ *
+ * If a given signal is not needed, pass the @ref NRF_SPIS_PIN_NOT_CONNECTED
+ * value instead of its pin number.
+ *
+ * @param[in] p_spis    SPIS instance.
+ * @param[in] sck_pin   SCK pin number.
+ * @param[in] mosi_pin  MOSI pin number.
+ * @param[in] miso_pin  MISO pin number.
+ * @param[in] csn_pin   CSN pin number.
+ */
+__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_spis,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin,
+                                       uint32_t csn_pin);
+
+/**
+ * @brief Function for setting the transmit buffer.
+ *
+ * @param[in]  p_spis   SPIS instance.
+ * @param[in]  p_buffer Pointer to the buffer that contains the data to send.
+ * @param[in]  length   Maximum number of data bytes to transmit.
+ */
+__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_spis,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length);
+
+/**
+ * @brief Function for setting the receive buffer.
+ *
+ * @param[in] p_spis   SPIS instance.
+ * @param[in] p_buffer Pointer to the buffer for received data.
+ * @param[in] length   Maximum number of data bytes to receive.
+ */
+__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_spis,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length);
+
+/**
+ * @brief Function for getting the number of bytes transmitted
+ *        in the last granted transaction.
+ *
+ * @param[in]  p_spis   SPIS instance.
+ *
+ * @returns Number of bytes transmitted.
+ */
+__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_spis);
+
+/**
+ * @brief Function for getting the number of bytes received
+ *        in the last granted transaction.
+ *
+ * @param[in]  p_spis   SPIS instance.
+ *
+ * @returns Number of bytes received.
+ */
+__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_spis);
+
+/**
+ * @brief Function for setting the SPI configuration.
+ *
+ * @param[in] p_spis        SPIS instance.
+ * @param[in] spi_mode      SPI mode.
+ * @param[in] spi_bit_order SPI bit order.
+ */
+__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_spis,
+                                        nrf_spis_mode_t spi_mode,
+                                        nrf_spis_bit_order_t spi_bit_order);
+
+/**
+ * @brief Function for setting the default character.
+ *
+ * @param[in] p_spis SPIS instance.
+ * @param[in] def    Default character that is clocked out in case of
+ *                   an overflow of the RXD buffer.
+ */
+__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_spis,
+                                      uint8_t def);
+
+/**
+ * @brief Function for setting the over-read character.
+ *
+ * @param[in] p_spis SPIS instance.
+ * @param[in] orc    Over-read character that is clocked out in case of
+ *                   an over-read of the TXD buffer.
+ */
+__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_spis,
+                                      uint8_t orc);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_spis_task_trigger(NRF_SPIS_Type * p_spis,
+                                           nrf_spis_task_t spis_task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_spis_task_address_get(NRF_SPIS_Type const * p_spis,
+                                                   nrf_spis_task_t spis_task)
+{
+    return (uint32_t)p_spis + (uint32_t)spis_task;
+}   
+
+__STATIC_INLINE void nrf_spis_event_clear(NRF_SPIS_Type *  p_spis,
+                                          nrf_spis_event_t spis_event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_spis_event_check(NRF_SPIS_Type const * p_spis,
+                                          nrf_spis_event_t spis_event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_spis + (uint32_t)spis_event);
+}
+
+__STATIC_INLINE uint32_t nrf_spis_event_address_get(NRF_SPIS_Type const * p_spis,
+                                                    nrf_spis_event_t spis_event)
+{
+    return (uint32_t)p_spis + (uint32_t)spis_event;
+}
+
+__STATIC_INLINE void nrf_spis_shorts_enable(NRF_SPIS_Type * p_spis,
+                                            uint32_t spis_shorts_mask)
+{
+    p_spis->SHORTS |= spis_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_spis_shorts_disable(NRF_SPIS_Type * p_spis,
+                                             uint32_t spis_shorts_mask)
+{
+    p_spis->SHORTS &= ~(spis_shorts_mask);
+}
+
+__STATIC_INLINE void nrf_spis_int_enable(NRF_SPIS_Type * p_spis,
+                                         uint32_t spis_int_mask)
+{
+    p_spis->INTENSET = spis_int_mask;
+}
+
+__STATIC_INLINE void nrf_spis_int_disable(NRF_SPIS_Type * p_spis,
+                                          uint32_t spis_int_mask)
+{
+    p_spis->INTENCLR = spis_int_mask;
+}
+
+__STATIC_INLINE bool nrf_spis_int_enable_check(NRF_SPIS_Type const * p_spis,
+                                               nrf_spis_int_mask_t spis_int)
+{
+    return (bool)(p_spis->INTENSET & spis_int);
+}
+
+__STATIC_INLINE void nrf_spis_enable(NRF_SPIS_Type * p_spis)
+{
+    p_spis->ENABLE = (SPIS_ENABLE_ENABLE_Enabled << SPIS_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_spis_disable(NRF_SPIS_Type * p_spis)
+{
+    p_spis->ENABLE = (SPIS_ENABLE_ENABLE_Disabled << SPIS_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE nrf_spis_semstat_t nrf_spis_semaphore_status_get(NRF_SPIS_Type * p_spis)
+{
+    return (nrf_spis_semstat_t) ((p_spis->SEMSTAT & SPIS_SEMSTAT_SEMSTAT_Msk) 
+                                 >> SPIS_SEMSTAT_SEMSTAT_Pos);
+}
+
+__STATIC_INLINE nrf_spis_status_mask_t nrf_spis_status_get(NRF_SPIS_Type * p_spis)
+{
+    return (nrf_spis_status_mask_t) p_spis->STATUS;
+}
+
+__STATIC_INLINE void nrf_spis_pins_set(NRF_SPIS_Type * p_spis,
+                                       uint32_t sck_pin,
+                                       uint32_t mosi_pin,
+                                       uint32_t miso_pin,
+                                       uint32_t csn_pin)
+{
+    p_spis->PSELSCK  = sck_pin;
+    p_spis->PSELMOSI = mosi_pin;
+    p_spis->PSELMISO = miso_pin;
+    p_spis->PSELCSN  = csn_pin;
+}
+
+__STATIC_INLINE void nrf_spis_tx_buffer_set(NRF_SPIS_Type * p_spis,
+                                            uint8_t const * p_buffer,
+                                            uint8_t         length)
+{
+    p_spis->TXDPTR = (uint32_t)p_buffer;
+    p_spis->MAXTX  = length;
+}
+
+__STATIC_INLINE void nrf_spis_rx_buffer_set(NRF_SPIS_Type * p_spis,
+                                            uint8_t * p_buffer,
+                                            uint8_t   length)
+{
+    p_spis->RXDPTR = (uint32_t)p_buffer;
+    p_spis->MAXRX  = length;
+}
+
+__STATIC_INLINE uint8_t nrf_spis_tx_amount_get(NRF_SPIS_Type const * p_spis)
+{
+    return (uint8_t) p_spis->AMOUNTRX;
+}
+
+__STATIC_INLINE uint8_t nrf_spis_rx_amount_get(NRF_SPIS_Type const * p_spis)
+{
+    return (uint8_t) p_spis->AMOUNTTX;
+}
+
+__STATIC_INLINE void nrf_spis_configure(NRF_SPIS_Type * p_spis,
+                                        nrf_spis_mode_t spi_mode,
+                                        nrf_spis_bit_order_t spi_bit_order)
+{
+    uint32_t config = (spi_bit_order == NRF_SPIS_BIT_ORDER_MSB_FIRST ?
+        SPIS_CONFIG_ORDER_MsbFirst : SPIS_CONFIG_ORDER_LsbFirst);
+
+    switch (spi_mode)
+    {
+    default:
+    case NRF_SPIS_MODE_0:
+        config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Leading    << SPIS_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIS_MODE_1:
+        config |= (SPIS_CONFIG_CPOL_ActiveHigh << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Trailing   << SPIS_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIS_MODE_2:
+        config |= (SPIS_CONFIG_CPOL_ActiveLow  << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Leading    << SPIS_CONFIG_CPHA_Pos);
+        break;
+
+    case NRF_SPIS_MODE_3:
+        config |= (SPIS_CONFIG_CPOL_ActiveLow  << SPIS_CONFIG_CPOL_Pos) |
+                  (SPIS_CONFIG_CPHA_Trailing   << SPIS_CONFIG_CPHA_Pos);
+        break;
+    }
+    p_spis->CONFIG = config;
+}
+
+__STATIC_INLINE void nrf_spis_orc_set(NRF_SPIS_Type * p_spis,
+                                      uint8_t orc)
+{
+    p_spis->ORC = orc;
+}
+
+__STATIC_INLINE void nrf_spis_def_set(NRF_SPIS_Type * p_spis,
+                                      uint8_t def)
+{
+    p_spis->DEF = def;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_SPIS_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_temp.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_temp.h
new file mode 100644
index 0000000000..001f7f0bc9
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_temp.h
@@ -0,0 +1,82 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_TEMP_H__
+#define NRF_TEMP_H__
+
+#include "nrf.h"
+
+/**
+* @defgroup nrf_temperature TEMP (temperature) abstraction
+* @{
+* @ingroup nrf_drivers temperature_example
+* @brief Temperature module init and read functions.
+*
+*/
+
+/**@cond NO_DOXYGEN */
+#define MASK_SIGN           (0x00000200UL)
+#define MASK_SIGN_EXTENSION (0xFFFFFC00UL)
+
+/**
+ * @brief Function for preparing the temp module for temperature measurement.
+ *
+ * This function initializes the TEMP module and writes to the hidden configuration register.
+ */
+static __INLINE void nrf_temp_init(void)
+{
+    /**@note Workaround for PAN_028 rev2.0A anomaly 31 - TEMP: Temperature offset value has to be manually loaded to the TEMP module */
+    *(uint32_t *) 0x4000C504 = 0;
+}
+
+/**
+ * @brief Function for reading temperature measurement.
+ *
+ * The function reads the 10 bit 2's complement value and transforms it to a 32 bit 2's complement value.
+ */
+static __INLINE int32_t nrf_temp_read(void)
+{    
+    /**@note Workaround for PAN_028 rev2.0A anomaly 28 - TEMP: Negative measured values are not represented correctly */
+    return ((NRF_TEMP->TEMP & MASK_SIGN) != 0) ? (NRF_TEMP->TEMP | MASK_SIGN_EXTENSION) : (NRF_TEMP->TEMP);    
+}
+/**@endcond */
+
+/** @} */
+
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_timer.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_timer.h
new file mode 100644
index 0000000000..85d4ac5a1b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_timer.h
@@ -0,0 +1,603 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @defgroup nrf_timer_hal Timer HAL
+ * @{
+ * @ingroup nrf_timer
+ *
+ * @brief Hardware access layer for accessing the timer peripheral.
+ */
+
+#ifndef NRF_TIMER_H__
+#define NRF_TIMER_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+#include "nrf_assert.h"
+
+
+/**
+ * @brief Macro for validating the correctness of the BIT_WIDTH setting.
+ */
+#ifdef NRF51
+    /**
+     * In the nRF51 Series, timer instance 0 supports all available bit widths.
+     * The other two instances support only 8 and 16 bits.
+     */
+    #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_timer, bit_width) \
+        ((p_timer == NRF_TIMER0) || (bit_width <= NRF_TIMER_BIT_WIDTH_16))
+#else
+    /**
+     * In the nRF52 Series, all timer instances support all available bit widths.
+     */
+    #define NRF_TIMER_IS_BIT_WIDTH_VALID(p_timer, bit_width) true
+#endif
+
+/**
+ * @brief Macro for getting the number of capture/compare channels available
+ *        in a given timer instance.
+ */
+#ifdef NRF51
+    #define NRF_TIMER_CC_CHANNEL_COUNT(id)  4
+#else
+    #define NRF_TIMER_CC_CHANNEL_COUNT(id)  ((id) <= 2 ? 4 : 6)
+#endif
+
+
+/**
+ * @brief Timer tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_TIMER_TASK_START    = offsetof(NRF_TIMER_Type, TASKS_START),      ///< Task for starting the timer.
+    NRF_TIMER_TASK_STOP     = offsetof(NRF_TIMER_Type, TASKS_STOP),       ///< Task for stopping the timer.
+    NRF_TIMER_TASK_COUNT    = offsetof(NRF_TIMER_Type, TASKS_COUNT),      ///< Task for incrementing the timer (in counter mode).
+    NRF_TIMER_TASK_CLEAR    = offsetof(NRF_TIMER_Type, TASKS_CLEAR),      ///< Task for resetting the timer value.
+    NRF_TIMER_TASK_SHUTDOWN = offsetof(NRF_TIMER_Type, TASKS_SHUTDOWN),   ///< Task for powering off the timer.
+    NRF_TIMER_TASK_CAPTURE0 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[0]), ///< Task for capturing the timer value on channel 0.
+    NRF_TIMER_TASK_CAPTURE1 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[1]), ///< Task for capturing the timer value on channel 1.
+    NRF_TIMER_TASK_CAPTURE2 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[2]), ///< Task for capturing the timer value on channel 2.
+    NRF_TIMER_TASK_CAPTURE3 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[3]), ///< Task for capturing the timer value on channel 3.
+#ifdef NRF52
+    NRF_TIMER_TASK_CAPTURE4 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[4]), ///< Task for capturing the timer value on channel 4.
+    NRF_TIMER_TASK_CAPTURE5 = offsetof(NRF_TIMER_Type, TASKS_CAPTURE[5]), ///< Task for capturing the timer value on channel 5.
+#endif
+    /*lint -restore*/
+} nrf_timer_task_t;
+
+/**
+ * @brief Timer events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TIMER_EVENT_COMPARE0 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[0]), ///< Event from compare channel 0.
+    NRF_TIMER_EVENT_COMPARE1 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[1]), ///< Event from compare channel 1.
+    NRF_TIMER_EVENT_COMPARE2 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[2]), ///< Event from compare channel 2.
+    NRF_TIMER_EVENT_COMPARE3 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[3]), ///< Event from compare channel 3.
+#ifdef NRF52
+    NRF_TIMER_EVENT_COMPARE4 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[4]), ///< Event from compare channel 4.
+    NRF_TIMER_EVENT_COMPARE5 = offsetof(NRF_TIMER_Type, EVENTS_COMPARE[5]), ///< Event from compare channel 5.
+#endif
+    /*lint -restore*/
+} nrf_timer_event_t;
+
+/**
+ * @brief Types of timer shortcuts.
+ */
+typedef enum
+{
+    NRF_TIMER_SHORT_COMPARE0_STOP_MASK = TIMER_SHORTS_COMPARE0_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 0.
+    NRF_TIMER_SHORT_COMPARE1_STOP_MASK = TIMER_SHORTS_COMPARE1_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 1.
+    NRF_TIMER_SHORT_COMPARE2_STOP_MASK = TIMER_SHORTS_COMPARE2_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 2.
+    NRF_TIMER_SHORT_COMPARE3_STOP_MASK = TIMER_SHORTS_COMPARE3_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 3.
+#ifdef NRF52
+    NRF_TIMER_SHORT_COMPARE4_STOP_MASK = TIMER_SHORTS_COMPARE4_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 4.
+    NRF_TIMER_SHORT_COMPARE5_STOP_MASK = TIMER_SHORTS_COMPARE5_STOP_Msk,   ///< Shortcut for stopping the timer based on compare 5.
+#endif
+    NRF_TIMER_SHORT_COMPARE0_CLEAR_MASK = TIMER_SHORTS_COMPARE0_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 0.
+    NRF_TIMER_SHORT_COMPARE1_CLEAR_MASK = TIMER_SHORTS_COMPARE1_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 1.
+    NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK = TIMER_SHORTS_COMPARE2_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 2.
+    NRF_TIMER_SHORT_COMPARE3_CLEAR_MASK = TIMER_SHORTS_COMPARE3_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 3.
+#ifdef NRF52
+    NRF_TIMER_SHORT_COMPARE4_CLEAR_MASK = TIMER_SHORTS_COMPARE4_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 4.
+    NRF_TIMER_SHORT_COMPARE5_CLEAR_MASK = TIMER_SHORTS_COMPARE5_CLEAR_Msk, ///< Shortcut for clearing the timer based on compare 5.
+#endif
+} nrf_timer_short_mask_t;
+
+/**
+ * @brief Timer modes.
+ */
+typedef enum
+{
+    NRF_TIMER_MODE_TIMER             = TIMER_MODE_MODE_Timer,           ///< Timer mode: timer.
+    NRF_TIMER_MODE_COUNTER           = TIMER_MODE_MODE_Counter,         ///< Timer mode: counter.
+#ifdef NRF52
+    NRF_TIMER_MODE_LOW_POWER_COUNTER = TIMER_MODE_MODE_LowPowerCounter, ///< Timer mode: low-power counter.
+#endif
+} nrf_timer_mode_t;
+
+/**
+ * @brief Timer bit width.
+ */
+typedef enum
+{
+    NRF_TIMER_BIT_WIDTH_8  = TIMER_BITMODE_BITMODE_08Bit, ///< Timer bit width 8 bit.
+    NRF_TIMER_BIT_WIDTH_16 = TIMER_BITMODE_BITMODE_16Bit, ///< Timer bit width 16 bit.
+    NRF_TIMER_BIT_WIDTH_24 = TIMER_BITMODE_BITMODE_24Bit, ///< Timer bit width 24 bit.
+    NRF_TIMER_BIT_WIDTH_32 = TIMER_BITMODE_BITMODE_32Bit  ///< Timer bit width 32 bit.
+} nrf_timer_bit_width_t;
+
+/**
+ * @brief Timer prescalers.
+ */
+typedef enum
+{
+    NRF_TIMER_FREQ_16MHz = 0, ///< Timer frequency 16 MHz.
+    NRF_TIMER_FREQ_8MHz,      ///< Timer frequency 8 MHz.
+    NRF_TIMER_FREQ_4MHz,      ///< Timer frequency 4 MHz.
+    NRF_TIMER_FREQ_2MHz,      ///< Timer frequency 2 MHz.
+    NRF_TIMER_FREQ_1MHz,      ///< Timer frequency 1 MHz.
+    NRF_TIMER_FREQ_500kHz,    ///< Timer frequency 500 kHz.
+    NRF_TIMER_FREQ_250kHz,    ///< Timer frequency 250 kHz.
+    NRF_TIMER_FREQ_125kHz,    ///< Timer frequency 125 kHz.
+    NRF_TIMER_FREQ_62500Hz,   ///< Timer frequency 62500 Hz.
+    NRF_TIMER_FREQ_31250Hz    ///< Timer frequency 31250 Hz.
+} nrf_timer_frequency_t;
+
+/**
+ * @brief Timer capture/compare channels.
+ */
+typedef enum
+{
+    NRF_TIMER_CC_CHANNEL0 = 0, ///< Timer capture/compare channel 0.
+    NRF_TIMER_CC_CHANNEL1,     ///< Timer capture/compare channel 1.
+    NRF_TIMER_CC_CHANNEL2,     ///< Timer capture/compare channel 2.
+    NRF_TIMER_CC_CHANNEL3,     ///< Timer capture/compare channel 3.
+#ifdef NRF52
+    NRF_TIMER_CC_CHANNEL4,     ///< Timer capture/compare channel 4.
+    NRF_TIMER_CC_CHANNEL5,     ///< Timer capture/compare channel 5.
+#endif
+} nrf_timer_cc_channel_t;
+
+/**
+ * @brief Timer interrupts.
+ */
+typedef enum
+{
+    NRF_TIMER_INT_COMPARE0_MASK = TIMER_INTENSET_COMPARE0_Msk, ///< Timer interrupt from compare event on channel 0.
+    NRF_TIMER_INT_COMPARE1_MASK = TIMER_INTENSET_COMPARE1_Msk, ///< Timer interrupt from compare event on channel 1.
+    NRF_TIMER_INT_COMPARE2_MASK = TIMER_INTENSET_COMPARE2_Msk, ///< Timer interrupt from compare event on channel 2.
+    NRF_TIMER_INT_COMPARE3_MASK = TIMER_INTENSET_COMPARE3_Msk, ///< Timer interrupt from compare event on channel 3.
+#ifdef NRF52
+    NRF_TIMER_INT_COMPARE4_MASK = TIMER_INTENSET_COMPARE4_Msk, ///< Timer interrupt from compare event on channel 4.
+    NRF_TIMER_INT_COMPARE5_MASK = TIMER_INTENSET_COMPARE5_Msk, ///< Timer interrupt from compare event on channel 5.
+#endif
+} nrf_timer_int_mask_t;
+
+
+/**
+ * @brief Function for activating a specific timer task.
+ *
+ * @param[in] p_timer Timer instance.
+ * @param[in] task    Task to activate.
+ */
+__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_timer,
+                                            nrf_timer_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific timer task register.
+ *
+ * @param[in] p_timer Timer instance.
+ * @param[in] task    Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_timer,
+                                                      nrf_timer_task_t task);
+
+/**
+ * @brief Function for clearing a specific timer event.
+ *
+ * @param[in] p_timer Timer instance.
+ * @param[in] event   Event to clear.
+ */
+__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_timer,
+                                           nrf_timer_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific timer event.
+ *
+ * @param[in] p_timer Timer instance.
+ * @param[in] event   Event to check.
+ *
+ * @retval true  If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_timer,
+                                           nrf_timer_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific timer event register.
+ *
+ * @param[in] p_timer Timer instance.
+ * @param[in] event   Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_timer,
+                                                       nrf_timer_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_timer           Timer instance.
+ * @param[in] timer_shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_timer,
+                                             uint32_t timer_shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_timer           Timer instance.
+ * @param[in] timer_shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_timer,
+                                              uint32_t timer_shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_timer        Timer instance.
+ * @param[in] timer_int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_timer,
+                                          uint32_t timer_int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_timer        Timer instance.
+ * @param[in] timer_int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_timer,
+                                           uint32_t timer_int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_timer   Timer instance.
+ * @param[in] timer_int Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_timer,
+                                                uint32_t timer_int);
+
+/**
+ * @brief Function for setting the timer mode.
+ *
+ * @param[in] p_timer Timer instance.
+ * @param[in] mode    Timer mode.
+ */
+__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_timer,
+                                        nrf_timer_mode_t mode);
+
+/**
+ * @brief Function for retrieving the timer mode.
+ *
+ * @param[in] p_timer Timer instance.
+ *
+ * @return Timer mode.
+ */
+__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_timer);
+
+/**
+ * @brief Function for setting the timer bit width.
+ *
+ * @param[in] p_timer   Timer instance.
+ * @param[in] bit_width Timer bit width.
+ */
+__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_timer,
+                                             nrf_timer_bit_width_t bit_width);
+
+/**
+ * @brief Function for retrieving the timer bit width.
+ *
+ * @param[in] p_timer Timer instance.
+ *
+ * @return Timer bit width.
+ */
+__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_timer);
+
+/**
+ * @brief Function for setting the timer frequency.
+ *
+ * @param[in] p_timer   Timer instance.
+ * @param[in] frequency Timer frequency.
+ */
+__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_timer,
+                                             nrf_timer_frequency_t frequency);
+
+/**
+ * @brief Function for retrieving the timer frequency.
+ *
+ * @param[in] p_timer Timer instance.
+ *
+ * @return Timer frequency.
+ */
+__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_timer);
+
+/**
+ * @brief Function for writing the capture/compare register for a specified channel.
+ *
+ * @param[in] p_timer    Timer instance.
+ * @param[in] cc_channel Requested capture/compare channel.
+ * @param[in] cc_value   Value to write to the capture/compare register.
+ */
+__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_timer,
+                                        nrf_timer_cc_channel_t cc_channel,
+                                        uint32_t               cc_value);
+
+/**
+ * @brief Function for retrieving the capture/compare value for a specified channel.
+ *
+ * @param[in] p_timer    Timer instance.
+ * @param[in] cc_channel Requested capture/compare channel.
+ *
+ * @return Value from the requested capture/compare register.
+ */
+__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_timer,
+                                           nrf_timer_cc_channel_t cc_channel);
+
+/**
+ * @brief Function for getting a specific timer capture task.
+ *
+ * @param[in] channel Capture channel.
+ *
+ * @return Capture task.
+ */
+__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel);
+
+/**
+ * @brief Function for getting a specific timer compare event.
+ *
+ * @param[in] channel Compare channel.
+ *
+ * @return Compare event.
+ */
+__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel);
+
+/**
+ * @brief Function for getting a specific timer compare interrupt.
+ *
+ * @param[in] channel Compare channel.
+ *
+ * @return Compare interrupt.
+ */
+__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel);
+
+/**
+ * @brief Function for calculating the number of timer ticks for a given time
+ *        (in microseconds) and timer frequency.
+ *
+ * @param[in] time_us   Time in microseconds.
+ * @param[in] frequency Timer frequency.
+ *
+ * @return Number of timer ticks.
+ */
+__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
+                                               nrf_timer_frequency_t frequency);
+
+/**
+ * @brief Function for calculating the number of timer ticks for a given time
+ *        (in milliseconds) and timer frequency.
+ *
+ * @param[in] time_ms   Time in milliseconds.
+ * @param[in] frequency Timer frequency.
+ *
+ * @return Number of timer ticks.
+ */
+__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
+                                               nrf_timer_frequency_t frequency);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_timer_task_trigger(NRF_TIMER_Type * p_timer,
+                                            nrf_timer_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t * nrf_timer_task_address_get(NRF_TIMER_Type * p_timer,
+                                                      nrf_timer_task_t task)
+{
+    return (uint32_t *)((uint8_t *)p_timer + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_timer_event_clear(NRF_TIMER_Type * p_timer,
+                                           nrf_timer_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_timer_event_check(NRF_TIMER_Type * p_timer,
+                                           nrf_timer_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_timer + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t * nrf_timer_event_address_get(NRF_TIMER_Type * p_timer,
+                                                       nrf_timer_event_t event)
+{
+    return (uint32_t *)((uint8_t *)p_timer + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_timer_shorts_enable(NRF_TIMER_Type * p_timer,
+                                             uint32_t timer_shorts_mask)
+{
+    p_timer->SHORTS |= timer_shorts_mask;
+}
+
+__STATIC_INLINE void nrf_timer_shorts_disable(NRF_TIMER_Type * p_timer,
+                                              uint32_t timer_shorts_mask)
+{
+    p_timer->SHORTS &= ~(timer_shorts_mask);
+}
+
+__STATIC_INLINE void nrf_timer_int_enable(NRF_TIMER_Type * p_timer,
+                                          uint32_t timer_int_mask)
+{
+    p_timer->INTENSET = timer_int_mask;
+}
+
+__STATIC_INLINE void nrf_timer_int_disable(NRF_TIMER_Type * p_timer,
+                                           uint32_t timer_int_mask)
+{
+    p_timer->INTENCLR = timer_int_mask;
+}
+
+__STATIC_INLINE bool nrf_timer_int_enable_check(NRF_TIMER_Type * p_timer,
+                                                uint32_t timer_int)
+{
+    return (bool)(p_timer->INTENSET & timer_int);
+}
+
+__STATIC_INLINE void nrf_timer_mode_set(NRF_TIMER_Type * p_timer,
+                                        nrf_timer_mode_t mode)
+{
+    p_timer->MODE = (p_timer->MODE & ~TIMER_MODE_MODE_Msk) |
+                    ((mode << TIMER_MODE_MODE_Pos) & TIMER_MODE_MODE_Msk);
+}
+
+__STATIC_INLINE nrf_timer_mode_t nrf_timer_mode_get(NRF_TIMER_Type * p_timer)
+{
+    return (nrf_timer_mode_t)(p_timer->MODE);
+}
+
+__STATIC_INLINE void nrf_timer_bit_width_set(NRF_TIMER_Type * p_timer,
+                                             nrf_timer_bit_width_t bit_width)
+{
+    p_timer->BITMODE = (p_timer->BITMODE & ~TIMER_BITMODE_BITMODE_Msk) |
+                       ((bit_width << TIMER_BITMODE_BITMODE_Pos) &
+                            TIMER_BITMODE_BITMODE_Msk);
+}
+
+__STATIC_INLINE nrf_timer_bit_width_t nrf_timer_bit_width_get(NRF_TIMER_Type * p_timer)
+{
+    return (nrf_timer_bit_width_t)(p_timer->BITMODE);
+}
+
+__STATIC_INLINE void nrf_timer_frequency_set(NRF_TIMER_Type * p_timer,
+                                             nrf_timer_frequency_t frequency)
+{
+    p_timer->PRESCALER = (p_timer->PRESCALER & ~TIMER_PRESCALER_PRESCALER_Msk) |
+                         ((frequency << TIMER_PRESCALER_PRESCALER_Pos) &
+                              TIMER_PRESCALER_PRESCALER_Msk);
+}
+
+__STATIC_INLINE nrf_timer_frequency_t nrf_timer_frequency_get(NRF_TIMER_Type * p_timer)
+{
+    return (nrf_timer_frequency_t)(p_timer->PRESCALER);
+}
+
+__STATIC_INLINE void nrf_timer_cc_write(NRF_TIMER_Type * p_timer,
+                                        nrf_timer_cc_channel_t cc_channel,
+                                        uint32_t               cc_value)
+{
+    p_timer->CC[cc_channel] = cc_value;
+}
+
+__STATIC_INLINE uint32_t nrf_timer_cc_read(NRF_TIMER_Type * p_timer,
+                                           nrf_timer_cc_channel_t cc_channel)
+{
+    return (uint32_t)p_timer->CC[cc_channel];
+}
+
+__STATIC_INLINE nrf_timer_task_t nrf_timer_capture_task_get(uint32_t channel)
+{
+    return (nrf_timer_task_t)
+        ((uint32_t)NRF_TIMER_TASK_CAPTURE0 + (channel * sizeof(uint32_t)));
+}
+
+__STATIC_INLINE nrf_timer_event_t nrf_timer_compare_event_get(uint32_t channel)
+{
+    return (nrf_timer_event_t)
+        ((uint32_t)NRF_TIMER_EVENT_COMPARE0 + (channel * sizeof(uint32_t)));
+}
+
+__STATIC_INLINE nrf_timer_int_mask_t nrf_timer_compare_int_get(uint32_t channel)
+{
+    return (nrf_timer_int_mask_t)
+        ((uint32_t)NRF_TIMER_INT_COMPARE0_MASK << channel);
+}
+
+__STATIC_INLINE uint32_t nrf_timer_us_to_ticks(uint32_t time_us,
+                                               nrf_timer_frequency_t frequency)
+{
+    // The "frequency" parameter here is actually the prescaler value, and the
+    // timer runs at the following frequency: f = 16 MHz / 2^prescaler.
+    uint32_t prescaler = (uint32_t)frequency;
+    ASSERT(time_us <= (UINT32_MAX / 16UL));
+    return ((time_us * 16UL) >> prescaler);
+}
+
+__STATIC_INLINE uint32_t nrf_timer_ms_to_ticks(uint32_t time_ms,
+                                               nrf_timer_frequency_t frequency)
+{
+    // The "frequency" parameter here is actually the prescaler value, and the
+    // timer runs at the following frequency: f = 16000 kHz / 2^prescaler.
+    uint32_t prescaler = (uint32_t)frequency;
+    ASSERT(time_ms <= (UINT32_MAX / 16000UL));
+    return ((time_ms * 16000UL) >> prescaler);
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_TIMER_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_twi.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_twi.h
new file mode 100644
index 0000000000..bd2198082a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_twi.h
@@ -0,0 +1,429 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_TWI_H__
+#define NRF_TWI_H__
+ 
+/**
+ * @defgroup nrf_twi_hal TWI HAL
+ * @{
+ * @ingroup nrf_twi_master
+ *
+ * @brief Hardware access layer for managing the TWI peripheral.
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+#include "nrf.h"
+
+/**
+ * @brief TWI tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWI_TASK_STARTRX = offsetof(NRF_TWI_Type, TASKS_STARTRX), ///< Start TWI receive sequence.
+    NRF_TWI_TASK_STARTTX = offsetof(NRF_TWI_Type, TASKS_STARTTX), ///< Start TWI transmit sequence.
+    NRF_TWI_TASK_STOP    = offsetof(NRF_TWI_Type, TASKS_STOP),    ///< Stop TWI transaction.
+    NRF_TWI_TASK_SUSPEND = offsetof(NRF_TWI_Type, TASKS_SUSPEND), ///< Suspend TWI transaction.
+    NRF_TWI_TASK_RESUME  = offsetof(NRF_TWI_Type, TASKS_RESUME)   ///< Resume TWI transaction.
+    /*lint -restore*/
+} nrf_twi_task_t;
+
+/**
+ * @brief TWI events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_TWI_EVENT_STOPPED   = offsetof(NRF_TWI_Type, EVENTS_STOPPED),  ///< TWI stopped.
+    NRF_TWI_EVENT_RXDREADY  = offsetof(NRF_TWI_Type, EVENTS_RXDREADY), ///< TWI RXD byte received.
+    NRF_TWI_EVENT_TXDSENT   = offsetof(NRF_TWI_Type, EVENTS_TXDSENT),  ///< TWI TXD byte sent.
+    NRF_TWI_EVENT_ERROR     = offsetof(NRF_TWI_Type, EVENTS_ERROR),    ///< TWI error.
+    NRF_TWI_EVENT_BB        = offsetof(NRF_TWI_Type, EVENTS_BB),       ///< TWI byte boundary, generated before each byte that is sent or received.
+    NRF_TWI_EVENT_SUSPENDED = offsetof(NRF_TWI_Type, EVENTS_SUSPENDED) ///< TWI entered the suspended state.
+    /*lint -restore*/
+} nrf_twi_event_t;
+
+/**
+ * @brief TWI shortcuts.
+ */
+typedef enum
+{
+    NRF_TWI_SHORT_BB_SUSPEND_MASK = TWI_SHORTS_BB_SUSPEND_Msk, ///< Shortcut between BB event and SUSPEND task.
+    NRF_TWI_SHORT_BB_STOP_MASK    = TWI_SHORTS_BB_STOP_Msk,    ///< Shortcut between BB event and STOP task.
+} nrf_twi_short_mask_t;
+
+/**
+ * @brief TWI interrupts.
+ */
+typedef enum
+{
+    NRF_TWI_INT_STOPPED_MASK    = TWI_INTENSET_STOPPED_Msk,  ///< Interrupt on STOPPED event.
+    NRF_TWI_INT_RXDREADY_MASK   = TWI_INTENSET_RXDREADY_Msk, ///< Interrupt on RXDREADY event.
+    NRF_TWI_INT_TXDSENT_MASK    = TWI_INTENSET_TXDSENT_Msk,  ///< Interrupt on TXDSENT event.
+    NRF_TWI_INT_ERROR_MASK      = TWI_INTENSET_ERROR_Msk,    ///< Interrupt on ERROR event.
+    NRF_TWI_INT_BB_MASK         = TWI_INTENSET_BB_Msk,       ///< Interrupt on BB event.
+    NRF_TWI_INT_SUSPENDED_MASK  = TWI_INTENSET_SUSPENDED_Msk ///< Interrupt on SUSPENDED event.
+} nrf_twi_int_mask_t;
+
+/**
+ * @brief TWI error source.
+ */
+typedef enum
+{
+    NRF_TWI_ERROR_ADDRESS_NACK = TWI_ERRORSRC_ANACK_Msk,  ///< NACK received after sending the address.
+    NRF_TWI_ERROR_DATA_NACK    = TWI_ERRORSRC_DNACK_Msk,  ///< NACK received after sending a data byte.
+    NRF_TWI_ERROR_OVERRUN      = TWI_ERRORSRC_OVERRUN_Msk ///< Overrun error.
+                                                          /**< A new byte was received before the previous byte was read
+                                                           *   from the RXD register (previous data is lost). */
+} nrf_twi_error_t;
+
+/**
+ * @brief TWI master clock frequency.
+ */
+typedef enum
+{
+    NRF_TWI_FREQ_100K = TWI_FREQUENCY_FREQUENCY_K100, ///< 100 kbps.
+    NRF_TWI_FREQ_250K = TWI_FREQUENCY_FREQUENCY_K250, ///< 250 kbps.
+    NRF_TWI_FREQ_400K = TWI_FREQUENCY_FREQUENCY_K400  ///< 400 kbps.
+} nrf_twi_frequency_t;
+
+
+/**
+ * @brief Function for activating a specific TWI task.
+ *
+ * @param[in] p_twi TWI instance.
+ * @param[in] task  Task to activate.
+ */
+__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_twi,
+                                          nrf_twi_task_t task);
+
+/**
+ * @brief Function for getting the address of a specific TWI task register.
+ *
+ * @param[in] p_twi TWI instance.
+ * @param[in] task  Requested task.
+ *
+ * @return Address of the specified task register.
+ */
+__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_twi,
+                                                    nrf_twi_task_t task);
+
+/**
+ * @brief Function for clearing a specific TWI event.
+ *
+ * @param[in] p_twi TWI instance.
+ * @param[in] event Event to clear.
+ */
+__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type * p_twi,
+                                         nrf_twi_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific event.
+ *
+ * @param[in] p_twi TWI instance.
+ * @param[in] event Event to check.
+ *
+ * @retval true If the event is set.
+ * @retval false If the event is not set.
+ */
+__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type  * p_twi,
+                                         nrf_twi_event_t event);
+
+/**
+ * @brief Function for getting the address of a specific TWI event register.
+ *
+ * @param[in] p_twi TWI instance.
+ * @param[in] event Requested event.
+ *
+ * @return Address of the specified event register.
+ */
+__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type  * p_twi,
+                                                     nrf_twi_event_t event);
+
+/**
+ * @brief Function for enabling specified shortcuts.
+ *
+ * @param[in] p_twi       TWI instance.
+ * @param[in] shorts_mask Shortcuts to enable.
+ */
+__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_twi,
+                                           uint32_t shorts_mask);
+
+/**
+ * @brief Function for disabling specified shortcuts.
+ *
+ * @param[in] p_twi       TWI instance.
+ * @param[in] shorts_mask Shortcuts to disable.
+ */
+__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_twi,
+                                            uint32_t shorts_mask);
+
+/**
+ * @brief Function for enabling specified interrupts.
+ *
+ * @param[in] p_twi    TWI instance.
+ * @param[in] int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_twi,
+                                        uint32_t int_mask);
+
+/**
+ * @brief Function for disabling specified interrupts.
+ *
+ * @param[in] p_twi   TWI instance.
+ * @param[in] int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_twi,
+                                         uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param[in] p_twi    TWI instance.
+ * @param[in] int_mask Interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_twi,
+                                              nrf_twi_int_mask_t int_mask);
+
+/**
+ * @brief Function for enabling the TWI peripheral.
+ *
+ * @param[in] p_twi TWI instance.
+ */
+__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_twi);
+
+/**
+ * @brief Function for disabling the TWI peripheral.
+ *
+ * @param[in] p_twi TWI instance.
+ */
+__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_twi);
+
+/**
+ * @brief Function for configuring TWI pins.
+ *
+ *
+ * @param[in] p_twi   TWI instance.
+ * @param[in] scl_pin SCL pin number.
+ * @param[in] sda_pin SDA pin number.
+ */
+__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_twi,
+                                      uint32_t scl_pin,
+                                      uint32_t sda_pin);
+
+/**
+ * @brief Function for setting the TWI master clock frequency.
+ *
+ * @param[in] p_twi     TWI instance.
+ * @param[in] frequency TWI frequency.
+ */
+__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_twi,
+                                           nrf_twi_frequency_t frequency);
+
+/**
+ * @brief Function for checking the TWI error source.
+ *
+ * The error flags are cleared after reading.
+ *
+ * @param[in] p_twi TWI instance.
+ *
+ * @return Mask with error source flags.
+ */
+__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_twi);
+
+/**
+ * @brief Function for setting the address to be used in TWI transfers.
+ *
+ * @param[in] p_twi   TWI instance.
+ * @param[in] address Address to be used in transfers.
+ */
+__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_twi, uint8_t address);
+
+/**
+ * @brief Function for reading data received by TWI.
+ *
+ * @param[in] p_twi TWI instance.
+ *
+ * @return Received data.
+ */
+__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_twi);
+
+/**
+ * @brief Function for writing data to be transmitted by TWI.
+ *
+ * @param[in] p_twi TWI instance.
+ * @param[in] data  Data to be transmitted.
+ */
+__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_twi, uint8_t data);
+
+__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_twi,
+                                        uint32_t shorts_mask);
+
+/**
+ * @}
+ */
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_twi_task_trigger(NRF_TWI_Type * p_twi,
+                                          nrf_twi_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t * nrf_twi_task_address_get(NRF_TWI_Type * p_twi,
+                                                    nrf_twi_task_t task)
+{
+    return (uint32_t *)((uint8_t *)p_twi + (uint32_t)task);
+}
+
+__STATIC_INLINE void nrf_twi_event_clear(NRF_TWI_Type  * p_twi,
+                                         nrf_twi_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)event)) = 0x0UL;
+}
+
+__STATIC_INLINE bool nrf_twi_event_check(NRF_TWI_Type  * p_twi,
+                                         nrf_twi_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_twi + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t * nrf_twi_event_address_get(NRF_TWI_Type  * p_twi,
+                                                     nrf_twi_event_t event)
+{
+    return (uint32_t *)((uint8_t *)p_twi + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_twi_shorts_enable(NRF_TWI_Type * p_twi,
+                                           uint32_t shorts_mask)
+{
+    p_twi->SHORTS |= shorts_mask;
+}
+
+__STATIC_INLINE void nrf_twi_shorts_disable(NRF_TWI_Type * p_twi,
+                                            uint32_t shorts_mask)
+{
+    p_twi->SHORTS &= ~(shorts_mask);
+}
+
+__STATIC_INLINE void nrf_twi_int_enable(NRF_TWI_Type * p_twi,
+                                        uint32_t int_mask)
+{
+    p_twi->INTENSET = int_mask;
+}
+
+__STATIC_INLINE void nrf_twi_int_disable(NRF_TWI_Type * p_twi,
+                                         uint32_t int_mask)
+{
+    p_twi->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE bool nrf_twi_int_enable_check(NRF_TWI_Type * p_twi,
+                                              nrf_twi_int_mask_t int_mask)
+{
+    return (bool)(p_twi->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_twi_enable(NRF_TWI_Type * p_twi)
+{
+    p_twi->ENABLE = (TWI_ENABLE_ENABLE_Enabled << TWI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_twi_disable(NRF_TWI_Type * p_twi)
+{
+    p_twi->ENABLE = (TWI_ENABLE_ENABLE_Disabled << TWI_ENABLE_ENABLE_Pos);
+}
+
+__STATIC_INLINE void nrf_twi_pins_set(NRF_TWI_Type * p_twi,
+                                      uint32_t scl_pin,
+                                      uint32_t sda_pin)
+{
+    p_twi->PSELSCL = scl_pin;
+    p_twi->PSELSDA = sda_pin;
+}
+
+__STATIC_INLINE void nrf_twi_frequency_set(NRF_TWI_Type * p_twi,
+                                           nrf_twi_frequency_t frequency)
+{
+    p_twi->FREQUENCY = frequency;
+}
+
+__STATIC_INLINE uint32_t nrf_twi_errorsrc_get_and_clear(NRF_TWI_Type * p_twi)
+{
+    uint32_t error_source = p_twi->ERRORSRC;
+
+    // [error flags are cleared by writing '1' on their position]
+    p_twi->ERRORSRC = error_source;
+
+    return error_source;
+}
+
+__STATIC_INLINE void nrf_twi_address_set(NRF_TWI_Type * p_twi, uint8_t address)
+{
+    p_twi->ADDRESS = address;
+}
+
+__STATIC_INLINE uint8_t nrf_twi_rxd_get(NRF_TWI_Type * p_twi)
+{
+    return (uint8_t)p_twi->RXD;
+}
+
+__STATIC_INLINE void nrf_twi_txd_set(NRF_TWI_Type * p_twi, uint8_t data)
+{
+    p_twi->TXD = data;
+}
+
+__STATIC_INLINE void nrf_twi_shorts_set(NRF_TWI_Type * p_twi,
+                                        uint32_t shorts_mask)
+{
+    p_twi->SHORTS = shorts_mask;
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_TWI_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_uart.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_uart.h
new file mode 100644
index 0000000000..1d09fe3846
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_uart.h
@@ -0,0 +1,498 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#ifndef NRF_UART_H__
+#define NRF_UART_H__
+
+#include "nrf.h"
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+
+/**
+ * @defgroup nrf_uart_hal UART HAL
+ * @{
+ * @ingroup nrf_uart
+ *
+ * @brief Hardware access layer for accessing the UART peripheral.
+ */
+
+#define NRF_UART_PSEL_DISCONNECTED 0xFFFFFFFF
+
+/**
+ * @enum nrf_uart_task_t
+ * @brief UART tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_UART_TASK_STARTRX = offsetof(NRF_UART_Type, TASKS_STARTRX), /**< Task for starting reception. */
+    NRF_UART_TASK_STOPRX  = offsetof(NRF_UART_Type, TASKS_STOPRX),  /**< Task for stopping reception. */
+    NRF_UART_TASK_STARTTX = offsetof(NRF_UART_Type, TASKS_STARTTX), /**< Task for starting transmission. */
+    NRF_UART_TASK_STOPTX  = offsetof(NRF_UART_Type, TASKS_STOPTX),  /**< Task for stopping transmission. */
+    NRF_UART_TASK_SUSPEND = offsetof(NRF_UART_Type, TASKS_SUSPEND), /**< Task for suspending UART. */
+    /*lint -restore*/
+} nrf_uart_task_t;
+
+/**
+ * @enum nrf_uart_event_t
+ * @brief UART events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_UART_EVENT_CTS    = offsetof(NRF_UART_Type, EVENTS_CTS),   /**< Event from CTS line activation. */
+    NRF_UART_EVENT_NCTS   = offsetof(NRF_UART_Type, EVENTS_NCTS),  /**< Event from CTS line deactivation. */
+    NRF_UART_EVENT_RXDRDY = offsetof(NRF_UART_Type, EVENTS_RXDRDY),/**< Event from data ready in RXD. */
+    NRF_UART_EVENT_TXDRDY = offsetof(NRF_UART_Type, EVENTS_TXDRDY),/**< Event from data sent from TXD. */
+    NRF_UART_EVENT_ERROR  = offsetof(NRF_UART_Type, EVENTS_ERROR), /**< Event from error detection. */
+    NRF_UART_EVENT_RXTO   = offsetof(NRF_UART_Type, EVENTS_RXTO)   /**< Event from receiver timeout. */
+    /*lint -restore*/
+} nrf_uart_event_t;
+
+/**
+ * @enum nrf_uart_int_mask_t
+ * @brief UART interrupts.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_UART_INT_MASK_CTS    = UART_INTENCLR_CTS_Msk,    /**< CTS line activation interrupt. */
+    NRF_UART_INT_MASK_NCTS   = UART_INTENCLR_NCTS_Msk,   /**< CTS line deactivation interrupt. */
+    NRF_UART_INT_MASK_RXDRDY = UART_INTENCLR_RXDRDY_Msk, /**< Data ready in RXD interrupt. */
+    NRF_UART_INT_MASK_TXDRDY = UART_INTENCLR_TXDRDY_Msk,  /**< Data sent from TXD interrupt. */
+    NRF_UART_INT_MASK_ERROR  = UART_INTENCLR_ERROR_Msk,  /**< Error detection interrupt. */
+    NRF_UART_INT_MASK_RXTO   = UART_INTENCLR_RXTO_Msk    /**< Receiver timeout interrupt. */
+    /*lint -restore*/
+} nrf_uart_int_mask_t;
+
+/**
+ * @enum nrf_uart_baudrate_t
+ * @brief Baudrates supported by UART.
+ */
+typedef enum
+{
+#ifdef NRF52
+    NRF_UART_BAUDRATE_1200   =  UARTE_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
+    NRF_UART_BAUDRATE_2400   =  UARTE_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
+    NRF_UART_BAUDRATE_4800   =  UARTE_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
+    NRF_UART_BAUDRATE_9600   =  UARTE_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
+    NRF_UART_BAUDRATE_14400  =  UARTE_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
+    NRF_UART_BAUDRATE_19200  =  UARTE_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
+    NRF_UART_BAUDRATE_28800  =  UARTE_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
+    NRF_UART_BAUDRATE_38400  =  UARTE_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
+    NRF_UART_BAUDRATE_57600  =  UARTE_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
+    NRF_UART_BAUDRATE_76800  =  UARTE_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
+    NRF_UART_BAUDRATE_115200 =  UARTE_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
+    NRF_UART_BAUDRATE_230400 =  UARTE_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
+    NRF_UART_BAUDRATE_250000 =  UARTE_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
+    NRF_UART_BAUDRATE_460800 =  UARTE_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
+    NRF_UART_BAUDRATE_921600 =  UARTE_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
+    NRF_UART_BAUDRATE_1000000 =  UARTE_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
+#else
+    NRF_UART_BAUDRATE_1200   =  UART_BAUDRATE_BAUDRATE_Baud1200, /**< 1200 baud. */
+    NRF_UART_BAUDRATE_2400   =  UART_BAUDRATE_BAUDRATE_Baud2400, /**< 2400 baud. */
+    NRF_UART_BAUDRATE_4800   =  UART_BAUDRATE_BAUDRATE_Baud4800, /**< 4800 baud. */
+    NRF_UART_BAUDRATE_9600   =  UART_BAUDRATE_BAUDRATE_Baud9600, /**< 9600 baud. */
+    NRF_UART_BAUDRATE_14400  =  UART_BAUDRATE_BAUDRATE_Baud14400, /**< 14400 baud. */
+    NRF_UART_BAUDRATE_19200  =  UART_BAUDRATE_BAUDRATE_Baud19200, /**< 19200 baud. */
+    NRF_UART_BAUDRATE_28800  =  UART_BAUDRATE_BAUDRATE_Baud28800, /**< 28800 baud. */
+    NRF_UART_BAUDRATE_38400  =  UART_BAUDRATE_BAUDRATE_Baud38400, /**< 38400 baud. */
+    NRF_UART_BAUDRATE_57600  =  UART_BAUDRATE_BAUDRATE_Baud57600, /**< 57600 baud. */
+    NRF_UART_BAUDRATE_76800  =  UART_BAUDRATE_BAUDRATE_Baud76800, /**< 76800 baud. */
+    NRF_UART_BAUDRATE_115200 =  UART_BAUDRATE_BAUDRATE_Baud115200, /**< 115200 baud. */
+    NRF_UART_BAUDRATE_230400 =  UART_BAUDRATE_BAUDRATE_Baud230400, /**< 230400 baud. */
+    NRF_UART_BAUDRATE_250000 =  UART_BAUDRATE_BAUDRATE_Baud250000, /**< 250000 baud. */
+    NRF_UART_BAUDRATE_460800 =  UART_BAUDRATE_BAUDRATE_Baud460800, /**< 460800 baud. */
+    NRF_UART_BAUDRATE_921600 =  UART_BAUDRATE_BAUDRATE_Baud921600, /**< 921600 baud. */
+    NRF_UART_BAUDRATE_1000000 =  UART_BAUDRATE_BAUDRATE_Baud1M, /**< 1000000 baud. */
+#endif
+} nrf_uart_baudrate_t;
+
+/**
+ * @enum nrf_uart_error_mask_t
+ * @brief Types of UART error masks.
+ */
+typedef enum
+{
+    NRF_UART_ERROR_OVERRUN_MASK = UART_ERRORSRC_OVERRUN_Msk,   /**< Overrun error. */
+    NRF_UART_ERROR_PARITY_MASK  = UART_ERRORSRC_PARITY_Msk,    /**< Parity error. */
+    NRF_UART_ERROR_FRAMING_MASK = UART_ERRORSRC_FRAMING_Msk,   /**< Framing error. */
+    NRF_UART_ERROR_BREAK_MASK   = UART_ERRORSRC_BREAK_Msk,     /**< Break error. */
+} nrf_uart_error_mask_t;
+
+/**
+ * @enum nrf_uart_parity_t
+ * @brief Types of UART parity modes.
+ */
+typedef enum
+{
+    NRF_UART_PARITY_EXCLUDED = UART_CONFIG_PARITY_Excluded << UART_CONFIG_PARITY_Pos, /**< Parity excluded. */
+    NRF_UART_PARITY_INCLUDED = UART_CONFIG_PARITY_Included << UART_CONFIG_PARITY_Pos, /**< Parity included. */
+} nrf_uart_parity_t;
+
+/**
+ * @enum nrf_uart_hwfc_t
+ * @brief Types of UART flow control modes.
+ */
+typedef enum
+{
+    NRF_UART_HWFC_DISABLED = UART_CONFIG_HWFC_Disabled, /**< HW flow control disabled. */
+    NRF_UART_HWFC_ENABLED  = UART_CONFIG_HWFC_Enabled,  /**< HW flow control enabled. */
+} nrf_uart_hwfc_t;
+
+/**
+ * @brief Function for clearing a specific UART event.
+ *
+ * @param[in] p_reg  UART instance.
+ * @param[in] event  Event to clear.
+ */
+__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event);
+
+/**
+ * @brief Function for checking the state of a specific UART event.
+ *
+ * @param[in] p_reg  UART instance.
+ * @param[in] event  Event to check.
+ *
+ * @retval True if event is set, False otherwise.
+ */
+__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event);
+
+/**
+ * @brief Function for returning the address of a specific UART event register.
+ *
+ * @param[in] p_reg  UART instance.
+ * @param[in] event  Desired event.
+ *
+ * @retval Address of specified event register.
+ */
+__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type  * p_reg,
+                                                    nrf_uart_event_t  event);
+
+/**
+ * @brief Function for enabling a specific interrupt.
+ *
+ * @param p_reg     Instance.
+ * @param int_mask Interrupts to enable.
+ */
+__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for retrieving the state of a given interrupt.
+ *
+ * @param p_reg     Instance.
+ * @param int_mask  Mask of interrupt to check.
+ *
+ * @retval true  If the interrupt is enabled.
+ * @retval false If the interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for disabling specific interrupts.
+ *
+ * @param p_reg    Instance.
+ * @param int_mask Interrupts to disable.
+ */
+__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask);
+
+/**
+ * @brief Function for getting error source mask. Function is clearing error source flags after reading.
+ *
+ * @param p_reg    Instance.
+ * @return         Mask with error source flags.
+ */
+__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for enabling UART.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for disabling UART.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for configuring TX/RX pins.
+ *
+ * @param p_reg    Instance.
+ * @param pseltxd  TXD pin number.
+ * @param pselrxd  RXD pin number.
+ */
+__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd);
+
+/**
+ * @brief Function for disconnecting TX/RX pins.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting TX pin.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting RX pin.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting RTS pin.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for getting CTS pin.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg);
+
+
+/**
+ * @brief Function for configuring flow control pins.
+ *
+ * @param p_reg    Instance.
+ * @param pselrts  RTS pin number.
+ * @param pselcts  CTS pin number.
+ */
+__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg,
+                                            uint32_t        pselrts,
+                                            uint32_t        pselcts);
+
+/**
+ * @brief Function for disconnecting flow control pins.
+ *
+ * @param p_reg    Instance.
+ */
+__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for reading RX data.
+ *
+ * @param p_reg    Instance.
+ * @return         Received byte.
+ */
+__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg);
+
+/**
+ * @brief Function for setting Tx data.
+ *
+ * @param p_reg    Instance.
+ * @param txd      Byte.
+ */
+__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd);
+
+/**
+ * @brief Function for starting an UART task.
+ *
+ * @param p_reg    Instance.
+ * @param task     Task.
+ */
+__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task);
+
+/**
+ * @brief Function for returning the address of a specific task register.
+ *
+ * @param p_reg Instance.
+ * @param task  Task.
+ *
+ * @return      Task address.
+ */
+__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task);
+
+/**
+ * @brief Function for configuring UART.
+ *
+ * @param p_reg  Instance.
+ * @param hwfc   Hardware flow control. Enabled if true.
+ * @param parity Parity. Included if true.
+ */
+__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type   * p_reg,
+                                            nrf_uart_parity_t parity,
+                                            nrf_uart_hwfc_t   hwfc);
+
+/**
+ * @brief Function for setting UART baudrate.
+ *
+ * @param p_reg    Instance.
+ * @param baudrate Baudrate.
+ */
+__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type   * p_reg, nrf_uart_baudrate_t baudrate);
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+__STATIC_INLINE void nrf_uart_event_clear(NRF_UART_Type * p_reg, nrf_uart_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event)) = 0x0UL;
+
+}
+
+__STATIC_INLINE bool nrf_uart_event_check(NRF_UART_Type * p_reg, nrf_uart_event_t event)
+{
+    return (bool)*(volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE uint32_t nrf_uart_event_address_get(NRF_UART_Type  * p_reg,
+                                                    nrf_uart_event_t  event)
+{
+    return (uint32_t)((uint8_t *)p_reg + (uint32_t)event);
+}
+
+__STATIC_INLINE void nrf_uart_int_enable(NRF_UART_Type * p_reg, uint32_t int_mask)
+{
+    p_reg->INTENSET = int_mask;
+}
+
+__STATIC_INLINE bool nrf_uart_int_enable_check(NRF_UART_Type * p_reg, uint32_t int_mask)
+{
+    return (bool)(p_reg->INTENSET & int_mask);
+}
+
+__STATIC_INLINE void nrf_uart_int_disable(NRF_UART_Type * p_reg, uint32_t int_mask)
+{
+    p_reg->INTENCLR = int_mask;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_errorsrc_get_and_clear(NRF_UART_Type * p_reg)
+{
+    uint32_t errsrc_mask = p_reg->ERRORSRC;
+    p_reg->ERRORSRC = errsrc_mask;
+    return errsrc_mask;
+}
+
+__STATIC_INLINE void nrf_uart_enable(NRF_UART_Type * p_reg)
+{
+    p_reg->ENABLE = UART_ENABLE_ENABLE_Enabled;
+}
+
+__STATIC_INLINE void nrf_uart_disable(NRF_UART_Type * p_reg)
+{
+    p_reg->ENABLE = UART_ENABLE_ENABLE_Disabled;
+}
+
+__STATIC_INLINE void nrf_uart_txrx_pins_set(NRF_UART_Type * p_reg, uint32_t pseltxd, uint32_t pselrxd)
+{
+    p_reg->PSELTXD = pseltxd;
+    p_reg->PSELRXD = pselrxd;
+}
+
+__STATIC_INLINE void nrf_uart_txrx_pins_disconnect(NRF_UART_Type * p_reg)
+{
+    nrf_uart_txrx_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
+}
+
+__STATIC_INLINE uint32_t nrf_uart_tx_pin_get(NRF_UART_Type * p_reg)
+{
+    return p_reg->PSELTXD;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_rx_pin_get(NRF_UART_Type * p_reg)
+{
+    return p_reg->PSELRXD;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_rts_pin_get(NRF_UART_Type * p_reg)
+{
+    return p_reg->PSELRTS;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_cts_pin_get(NRF_UART_Type * p_reg)
+{
+    return p_reg->PSELCTS;
+}
+
+__STATIC_INLINE void nrf_uart_hwfc_pins_set(NRF_UART_Type * p_reg, uint32_t pselrts, uint32_t pselcts)
+{
+    p_reg->PSELRTS = pselrts;
+    p_reg->PSELCTS = pselcts;
+}
+
+__STATIC_INLINE void nrf_uart_hwfc_pins_disconnect(NRF_UART_Type * p_reg)
+{
+    nrf_uart_hwfc_pins_set(p_reg, NRF_UART_PSEL_DISCONNECTED, NRF_UART_PSEL_DISCONNECTED);
+}
+
+__STATIC_INLINE uint8_t nrf_uart_rxd_get(NRF_UART_Type * p_reg)
+{
+    return p_reg->RXD;
+}
+
+__STATIC_INLINE void nrf_uart_txd_set(NRF_UART_Type * p_reg, uint8_t txd)
+{
+    p_reg->TXD = txd;
+}
+
+__STATIC_INLINE void nrf_uart_task_trigger(NRF_UART_Type * p_reg, nrf_uart_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)p_reg + (uint32_t)task)) = 0x1UL;
+}
+
+__STATIC_INLINE uint32_t nrf_uart_task_address_get(NRF_UART_Type * p_reg, nrf_uart_task_t task)
+{
+    return (uint32_t)p_reg + (uint32_t)task;
+}
+
+__STATIC_INLINE void nrf_uart_configure(NRF_UART_Type   * p_reg,
+                                            nrf_uart_parity_t parity,
+                                            nrf_uart_hwfc_t   hwfc)
+{
+    p_reg->CONFIG = (uint32_t)parity | (uint32_t)hwfc;
+}
+
+__STATIC_INLINE void nrf_uart_baudrate_set(NRF_UART_Type   * p_reg, nrf_uart_baudrate_t baudrate)
+{
+    p_reg->BAUDRATE = baudrate;
+}
+#endif //SUPPRESS_INLINE_IMPLEMENTATION
+/** @} */
+#endif //NRF_UART_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_wdt.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_wdt.h
new file mode 100644
index 0000000000..4b6f9a5609
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/hal/nrf_wdt.h
@@ -0,0 +1,326 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ * @defgroup nrf_wdt_hal WDT HAL
+ * @{
+ * @ingroup nrf_wdt
+ *
+ * @brief Hardware access layer for accessing the watchdog timer (WDT) peripheral.
+ */
+
+#ifndef NRF_WDT_H__
+#define NRF_WDT_H__
+
+#include <stddef.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf.h"
+
+#define NRF_WDT_CHANNEL_NUMBER 0x8UL
+#define NRF_WDT_RR_VALUE       0x6E524635UL /* Fixed value, shouldn't be modified.*/
+
+#define NRF_WDT_TASK_SET       1UL
+#define NRF_WDT_EVENT_CLEAR    0UL
+
+/**
+ * @enum nrf_wdt_task_t
+ * @brief WDT tasks.
+ */
+typedef enum
+{
+    /*lint -save -e30 -esym(628,__INTADDR__)*/
+    NRF_WDT_TASK_START = offsetof(NRF_WDT_Type, TASKS_START), /**< Task for starting WDT. */
+    /*lint -restore*/
+} nrf_wdt_task_t;
+
+/**
+ * @enum nrf_wdt_event_t
+ * @brief WDT events.
+ */
+typedef enum
+{
+    /*lint -save -e30*/
+    NRF_WDT_EVENT_TIMEOUT = offsetof(NRF_WDT_Type, EVENTS_TIMEOUT), /**< Event from WDT time-out. */
+    /*lint -restore*/
+} nrf_wdt_event_t;
+
+/**
+ * @enum nrf_wdt_behaviour_t
+ * @brief WDT behavior in CPU SLEEP or HALT mode.
+ */
+typedef enum
+{
+    NRF_WDT_BEHAVIOUR_RUN_SLEEP        = WDT_CONFIG_SLEEP_Msk,                       /**< WDT will run when CPU is in SLEEP mode. */
+    NRF_WDT_BEHAVIOUR_RUN_HALT         = WDT_CONFIG_HALT_Msk,                        /**< WDT will run when CPU is in HALT mode. */
+    NRF_WDT_BEHAVIOUR_RUN_SLEEP_HALT   = WDT_CONFIG_SLEEP_Msk | WDT_CONFIG_HALT_Msk, /**< WDT will run when CPU is in SLEEP or HALT mode. */
+    NRF_WDT_BEHAVIOUR_PAUSE_SLEEP_HALT = 0,                                          /**< WDT will be paused when CPU is in SLEEP or HALT mode. */
+} nrf_wdt_behaviour_t;
+
+/**
+ * @enum nrf_wdt_rr_register_t
+ * @brief WDT reload request registers.
+ */
+typedef enum
+{
+    NRF_WDT_RR0 = 0, /**< Reload request register 0. */
+    NRF_WDT_RR1,     /**< Reload request register 1. */
+    NRF_WDT_RR2,     /**< Reload request register 2. */
+    NRF_WDT_RR3,     /**< Reload request register 3. */
+    NRF_WDT_RR4,     /**< Reload request register 4. */
+    NRF_WDT_RR5,     /**< Reload request register 5. */
+    NRF_WDT_RR6,     /**< Reload request register 6. */
+    NRF_WDT_RR7      /**< Reload request register 7. */
+} nrf_wdt_rr_register_t;
+
+/**
+ * @enum nrf_wdt_int_mask_t
+ * @brief WDT interrupts.
+ */
+typedef enum
+{
+    NRF_WDT_INT_TIMEOUT_MASK = WDT_INTENSET_TIMEOUT_Msk, /**< WDT interrupt from time-out event. */
+} nrf_wdt_int_mask_t;
+
+/**
+ * @brief Function for configuring the watchdog behavior when the CPU is sleeping or halted.
+ *
+ * @param behaviour Watchdog behavior when CPU is in SLEEP or HALT mode.
+ */
+__STATIC_INLINE void nrf_wdt_behaviour_set(nrf_wdt_behaviour_t behaviour)
+{
+    NRF_WDT->CONFIG = behaviour;
+}
+
+
+/**
+ * @brief Function for starting the watchdog.
+ *
+ * @param[in]  task             Task.
+ */
+__STATIC_INLINE void nrf_wdt_task_trigger(nrf_wdt_task_t task)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_WDT + task)) = NRF_WDT_TASK_SET;
+}
+
+
+/**
+ * @brief Function for clearing the WDT event.
+ *
+ * @param[in]  event       Event.
+ */
+__STATIC_INLINE void nrf_wdt_event_clear(nrf_wdt_event_t event)
+{
+    *((volatile uint32_t *)((uint8_t *)NRF_WDT + (uint32_t)event)) = NRF_WDT_EVENT_CLEAR;
+}
+
+
+/**
+ * @brief Function for retrieving the state of the WDT event.
+ *
+ * @param[in]  event       Event.
+ *
+ * @retval     true              If the event is set.
+ * @retval     false             If the event is not set.
+ */
+__STATIC_INLINE bool nrf_wdt_event_check(nrf_wdt_event_t event)
+{
+    return (bool)*((volatile uint32_t *)((uint8_t *)NRF_WDT + event));
+}
+
+
+/**
+ * @brief Function for enabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_wdt_int_enable(uint32_t int_mask)
+{
+    NRF_WDT->INTENSET = int_mask;
+}
+
+
+/**
+ * @brief Function for retrieving the state of given interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ *
+ * @retval     true                   Interrupt is enabled.
+ * @retval     false                  Interrupt is not enabled.
+ */
+__STATIC_INLINE bool nrf_wdt_int_enable_check(uint32_t int_mask)
+{
+    return (bool)(NRF_WDT->INTENSET & int_mask);
+}
+
+
+/**
+ * @brief Function for disabling a specific interrupt.
+ *
+ * @param[in]  int_mask         Interrupt.
+ */
+__STATIC_INLINE void nrf_wdt_int_disable(uint32_t int_mask)
+{
+    NRF_WDT->INTENCLR = int_mask;
+}
+
+
+/**
+ * @brief Function for returning the address of a specific WDT task register.
+ *
+ * @param[in]  task             Task.
+ */
+__STATIC_INLINE uint32_t nrf_wdt_task_address_get(nrf_wdt_task_t task)
+{
+    return ((uint32_t)NRF_WDT + task);
+}
+
+
+/**
+ * @brief Function for returning the address of a specific WDT event register.
+ *
+ * @param[in]  event       Event.
+ *
+ * @retval     address of requested event register
+ */
+__STATIC_INLINE uint32_t nrf_wdt_event_address_get(nrf_wdt_event_t event)
+{
+    return ((uint32_t)NRF_WDT + event);
+}
+
+
+/**
+ * @brief Function for retrieving the watchdog status.
+ *
+ * @retval     true             If the watchdog is started.
+ * @retval     false            If the watchdog is not started.
+ */
+__STATIC_INLINE bool nrf_wdt_started(void)
+{
+    return (bool)(NRF_WDT->RUNSTATUS);
+}
+
+
+/**
+ * @brief Function for retrieving the watchdog reload request status.
+ *
+ * @param[in]  rr_register      Reload request register to check.
+ *
+ * @retval     true             If a reload request is running.
+ * @retval     false            If no reload request is running.
+ */
+__STATIC_INLINE bool nrf_wdt_request_status(nrf_wdt_rr_register_t rr_register)
+{
+    return (bool)(((NRF_WDT->REQSTATUS) >> rr_register) & 0x1UL);
+}
+
+
+/**
+ * @brief Function for setting the watchdog reload value.
+ *
+ * @param[in]  reload_value     Watchdog counter initial value.
+ */
+__STATIC_INLINE void nrf_wdt_reload_value_set(uint32_t reload_value)
+{
+    NRF_WDT->CRV = reload_value;
+}
+
+
+/**
+ * @brief Function for retrieving the watchdog reload value.
+ *
+ * @retval                      Reload value.
+ */
+__STATIC_INLINE uint32_t nrf_wdt_reload_value_get(void)
+{
+    return (uint32_t)NRF_WDT->CRV;
+}
+
+
+/**
+ * @brief Function for enabling a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to enable.
+ */
+__STATIC_INLINE void nrf_wdt_reload_request_enable(nrf_wdt_rr_register_t rr_register)
+{
+    NRF_WDT->RREN |= 0x1UL << rr_register;
+}
+
+
+/**
+ * @brief Function for disabling a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to disable.
+ */
+__STATIC_INLINE void nrf_wdt_reload_request_disable(nrf_wdt_rr_register_t rr_register)
+{
+    NRF_WDT->RREN &= ~(0x1UL << rr_register);
+}
+
+
+/**
+ * @brief Function for retrieving the status of a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to check.
+ *
+ * @retval     true              If the reload request register is enabled.
+ * @retval     false             If the reload request register is not enabled.
+ */
+__STATIC_INLINE bool nrf_wdt_reload_request_is_enabled(nrf_wdt_rr_register_t rr_register)
+{
+    return (bool)(NRF_WDT->RREN & (0x1UL << rr_register));
+}
+
+
+/**
+ * @brief Function for setting a specific reload request register.
+ *
+ * @param[in]  rr_register       Reload request register to set.
+ */
+__STATIC_INLINE void nrf_wdt_reload_request_set(nrf_wdt_rr_register_t rr_register)
+{
+    NRF_WDT->RR[rr_register] = NRF_WDT_RR_VALUE;
+}
+
+
+#endif
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.c
new file mode 100644
index 0000000000..12b36d1acb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.c
@@ -0,0 +1,454 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include <stdlib.h>
+
+#include "nrf.h"
+#include "nrf_drv_ppi.h"
+#include "nrf_drv_common.h"
+#include "nrf_ppi.h"
+#include "app_util_platform.h"
+#include "sdk_common.h"
+
+
+static nrf_drv_state_t     m_drv_state;            /**< Driver state */
+static uint32_t            m_channels_allocated;   /**< Bitmap representing channels availability. 1 when a channel is allocated, 0 otherwise. */
+static uint8_t             m_groups_allocated;     /**< Bitmap representing groups availability. 1 when a group is allocated, 0 otherwise.*/
+
+
+/**@brief  Compute a group mask (needed for driver internals, not used for NRF_PPI registers).
+ * @param[in]  group  Group number to transform to a mask.
+ * @retval     Group mask.
+ */
+__STATIC_INLINE uint32_t group_to_mask(nrf_ppi_channel_group_t group)
+{
+    return (1uL << (uint32_t) group);
+}
+
+
+/**@brief  Check whether a channel is a programmable channel and can be used by an application.
+ * @param[in]  channel  Channel to check.
+ * @retval     true     The channel is a programmable application channel.
+ *             false    The channel is used by a SoftDevice or is preprogrammed.
+ */
+__STATIC_INLINE bool is_programmable_app_channel(nrf_ppi_channel_t channel)
+{
+    return ((NRF_PPI_PROG_APP_CHANNELS_MASK & nrf_drv_ppi_channel_to_mask(channel)) != 0);
+}
+
+
+/**@brief  Check whether a channels can be used by an application.
+ * @param[in]  channel  Channel mask to check.
+ * @retval     true     All specified channels can be used by an application.
+ *             false    At least one specified channel is used by a SoftDevice.
+ */
+__STATIC_INLINE bool are_app_channels(uint32_t channel_mask)
+{
+    //lint -e(587)
+    return ((~(NRF_PPI_ALL_APP_CHANNELS_MASK) & channel_mask) == 0);
+}
+
+
+/**@brief  Check whether a channel can be used by an application.
+ * @param[in]  channel  Channel to check.
+ * @retval     true     The channel can be used by an application.
+ *             false    The channel is used by a SoftDevice.
+ */
+__STATIC_INLINE bool is_app_channel(nrf_ppi_channel_t channel)
+{
+    return are_app_channels(nrf_drv_ppi_channel_to_mask(channel));
+}
+
+
+/**@brief  Check whether a channel group can be used by an application.
+ * @param[in]  group    Group to check.
+ * @retval     true     The group is an application group.
+ *             false    The group is not an application group (this group either does not exist or
+ *                      it is used by a SoftDevice).
+ */
+__STATIC_INLINE bool is_app_group(nrf_ppi_channel_group_t group)
+{
+    return ((NRF_PPI_ALL_APP_GROUPS_MASK & group_to_mask(group)) != 0);
+}
+
+
+/**@brief  Check whether a channel is allocated.
+ * @param[in]  channel_num  Channel number to check.
+ * @retval     true         The channel is allocated.
+ *             false        The channel is not allocated.
+ */
+__STATIC_INLINE bool is_allocated_channel(nrf_ppi_channel_t channel)
+{
+    return ((m_channels_allocated & nrf_drv_ppi_channel_to_mask(channel)) != 0);
+}
+
+
+/**@brief  Set channel allocated indication.
+ * @param[in]  channel_num  Specifies the channel to set the "allocated" indication.
+ */
+__STATIC_INLINE void channel_allocated_set(nrf_ppi_channel_t channel)
+{
+    m_channels_allocated |= nrf_drv_ppi_channel_to_mask(channel);
+}
+
+
+/**@brief  Clear channel allocated indication.
+ * @param[in]  channel_num  Specifies the channel to clear the "allocated" indication.
+ */
+__STATIC_INLINE void channel_allocated_clr(nrf_ppi_channel_t channel)
+{
+    m_channels_allocated &= ~nrf_drv_ppi_channel_to_mask(channel);
+}
+
+
+/**@brief  Clear all allocated channels.
+ */
+__STATIC_INLINE void channel_allocated_clr_all(void)
+{
+    m_channels_allocated &= ~NRF_PPI_ALL_APP_CHANNELS_MASK;
+}
+
+
+/**@brief  Check whether a group is allocated.
+ * @param[in]  group_num    Group number to check.
+ * @retval     true         The group is allocated.
+ *             false        The group is not allocated.
+ */
+__STATIC_INLINE bool is_allocated_group(nrf_ppi_channel_group_t group)
+{
+    return ((m_groups_allocated & group_to_mask(group)) != 0);
+}
+
+
+/**@brief  Set group allocated indication.
+ * @param[in]  group_num  Specifies the group to set the "allocated" indication.
+ */
+__STATIC_INLINE void group_allocated_set(nrf_ppi_channel_group_t group)
+{
+    m_groups_allocated |= group_to_mask(group);
+}
+
+
+/**@brief  Clear group allocated indication.
+ * @param[in]  group_num  Specifies the group to clear the "allocated" indication.
+ */
+__STATIC_INLINE void group_allocated_clr(nrf_ppi_channel_group_t group)
+{
+    m_groups_allocated &= ~group_to_mask(group);
+}
+
+
+/**@brief  Clear all allocated groups.
+ */
+__STATIC_INLINE void group_allocated_clr_all()
+{
+    m_groups_allocated &= ~NRF_PPI_ALL_APP_GROUPS_MASK;
+}
+
+
+uint32_t nrf_drv_ppi_init(void)
+{
+    uint32_t err_code;
+
+    if (m_drv_state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        m_drv_state = NRF_DRV_STATE_INITIALIZED;
+        err_code    = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code = MODULE_ALREADY_INITIALIZED;
+    }
+
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_uninit(void)
+{
+    uint32_t mask = NRF_PPI_ALL_APP_GROUPS_MASK;
+    nrf_ppi_channel_group_t group;
+
+    if (m_drv_state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    
+    m_drv_state = NRF_DRV_STATE_UNINITIALIZED;
+
+    // Disable all channels and groups
+    nrf_ppi_channels_disable(NRF_PPI_ALL_APP_CHANNELS_MASK);
+
+    for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++)
+    {
+        if(mask & group_to_mask(group))
+        {
+            nrf_ppi_channel_group_clear(group);
+        }
+    }
+    channel_allocated_clr_all();
+    group_allocated_clr_all();
+    return NRF_SUCCESS;
+}
+
+
+uint32_t nrf_drv_ppi_channel_alloc(nrf_ppi_channel_t * p_channel)
+{
+    uint32_t err_code;
+    nrf_ppi_channel_t channel;
+    uint32_t mask = 0;
+
+    err_code = NRF_ERROR_NO_MEM;
+
+    mask = NRF_PPI_PROG_APP_CHANNELS_MASK;
+    for (channel = NRF_PPI_CHANNEL0; mask != 0; mask &= ~nrf_drv_ppi_channel_to_mask(channel), channel++)
+    {
+        CRITICAL_REGION_ENTER();
+        if ((mask & nrf_drv_ppi_channel_to_mask(channel)) && (!is_allocated_channel(channel)))
+        {
+            channel_allocated_set(channel);
+            *p_channel = channel;
+            err_code   = NRF_SUCCESS;
+        }
+        CRITICAL_REGION_EXIT();
+        if (err_code == NRF_SUCCESS)
+        {
+            break;
+        }
+    }
+
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_channel_free(nrf_ppi_channel_t channel)
+{
+    if (!is_programmable_app_channel(channel))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    // First disable this channel
+    nrf_ppi_channel_disable(channel);
+    CRITICAL_REGION_ENTER();
+    channel_allocated_clr(channel);
+    CRITICAL_REGION_EXIT();
+    return NRF_SUCCESS;
+}
+
+
+uint32_t nrf_drv_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep)
+{
+    VERIFY_PARAM_NOT_NULL((uint32_t *)eep);
+    VERIFY_PARAM_NOT_NULL((uint32_t *)tep);
+
+    if (!is_programmable_app_channel(channel))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_channel(channel))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    
+    nrf_ppi_channel_endpoint_setup(channel, eep, tep);
+    return NRF_SUCCESS;
+}
+
+uint32_t nrf_drv_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep)
+{
+#ifdef NRF51
+    return NRF_ERROR_NOT_SUPPORTED;
+#else
+    if (!is_programmable_app_channel(channel))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_channel(channel))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    nrf_ppi_fork_endpoint_setup(channel, fork_tep);
+    return NRF_SUCCESS;
+#endif
+}
+
+uint32_t nrf_drv_ppi_channel_enable(nrf_ppi_channel_t channel)
+{
+    if (!is_app_channel(channel))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (is_programmable_app_channel(channel) && !is_allocated_channel(channel))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    nrf_ppi_channel_enable(channel);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t nrf_drv_ppi_channel_disable(nrf_ppi_channel_t channel)
+{
+    if (!is_app_channel(channel))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (is_programmable_app_channel(channel) && !is_allocated_channel(channel))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    nrf_ppi_channel_disable(channel);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t nrf_drv_ppi_group_alloc(nrf_ppi_channel_group_t * p_group)
+{
+    uint32_t err_code;
+    uint32_t mask = 0;
+    nrf_ppi_channel_group_t group;
+
+    err_code = NRF_ERROR_NO_MEM;
+
+    mask = NRF_PPI_ALL_APP_GROUPS_MASK;
+    for (group = NRF_PPI_CHANNEL_GROUP0; mask != 0; mask &= ~group_to_mask(group), group++)
+    {
+        CRITICAL_REGION_ENTER();
+        if ((mask & group_to_mask(group)) && (!is_allocated_group(group)))
+        {
+            group_allocated_set(group);
+            *p_group = group;
+            err_code = NRF_SUCCESS;
+        }
+        CRITICAL_REGION_EXIT();
+        if (err_code == NRF_SUCCESS)
+        {
+            break;
+        }
+    }
+
+    return err_code;
+}
+
+
+uint32_t nrf_drv_ppi_group_free(nrf_ppi_channel_group_t group)
+{
+    if (!is_app_group(group))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_group(group))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    else
+    nrf_ppi_group_disable(group);
+    CRITICAL_REGION_ENTER();
+    group_allocated_clr(group);
+    CRITICAL_REGION_EXIT();
+    return NRF_SUCCESS;
+}
+
+
+uint32_t nrf_drv_ppi_group_enable(nrf_ppi_channel_group_t group)
+{
+    if (!is_app_group(group))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_group(group))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    nrf_ppi_group_enable(group);
+    return NRF_SUCCESS;
+}
+
+
+uint32_t nrf_drv_ppi_group_disable(nrf_ppi_channel_group_t group)
+{
+    if (!is_app_group(group))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    nrf_ppi_group_disable(group);
+    return NRF_SUCCESS;
+}
+
+uint32_t nrf_drv_ppi_channels_remove_from_group(uint32_t channel_mask,
+                                                nrf_ppi_channel_group_t group)
+{
+    if (!is_app_group(group))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_group(group))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (!are_app_channels(channel_mask))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    CRITICAL_REGION_ENTER();
+    nrf_ppi_channels_remove_from_group(channel_mask, group);
+    CRITICAL_REGION_EXIT();
+    return NRF_SUCCESS;
+}
+
+uint32_t nrf_drv_ppi_channels_include_in_group(uint32_t channel_mask,
+                                               nrf_ppi_channel_group_t group)
+{
+    if (!is_app_group(group))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!is_allocated_group(group))
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (!are_app_channels(channel_mask))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    CRITICAL_REGION_ENTER();
+    nrf_ppi_channels_include_in_group(channel_mask, group);
+    CRITICAL_REGION_EXIT();
+    return NRF_SUCCESS;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.h
new file mode 100644
index 0000000000..55cd93346c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/ppi/nrf_drv_ppi.h
@@ -0,0 +1,311 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef NRF_DRV_PPI_H
+#define NRF_DRV_PPI_H
+
+/*lint ++flb "Enter library region" */
+#include "sdk_errors.h"
+#include "nrf_ppi.h"
+#include <stdbool.h>
+#include <stdint.h>
+
+/** @file
+ *
+ * @addtogroup nrf_ppi PPI HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Programmable Peripheral Interconnect (PPI) APIs.
+ *
+ * @details The PPI HAL provides basic APIs for accessing the registers of the PPI. 
+ * The PPI driver provides APIs on a higher level.
+ *
+ * @defgroup lib_driver_ppi PPI driver
+ * @{
+ * @ingroup  nrf_ppi
+ *
+ * @brief Programmable Peripheral Interconnect (PPI) driver.
+ */
+
+#include "sdk_resources.h"
+
+#ifdef NRF52
+
+    #define NRF_PPI_ALL_APP_CHANNELS_MASK   ((uint32_t)0xFFFFFFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< All PPI channels available to the application. */
+    #define NRF_PPI_PROG_APP_CHANNELS_MASK  ((uint32_t)0x000FFFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< Programmable PPI channels available to the application. */
+    #define NRF_PPI_ALL_APP_GROUPS_MASK     ((uint32_t)0x0000003FuL & ~(NRF_PPI_GROUPS_USED))    /**< All PPI groups available to the application. */
+
+#else
+
+    #define NRF_PPI_ALL_APP_CHANNELS_MASK   ((uint32_t)0xFFF0FFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< All PPI channels available to the application. */
+    #define NRF_PPI_PROG_APP_CHANNELS_MASK  ((uint32_t)0x0000FFFFuL & ~(NRF_PPI_CHANNELS_USED))  /**< Programmable PPI channels available to the application. */
+    #define NRF_PPI_ALL_APP_GROUPS_MASK     ((uint32_t)0x0000000FuL & ~(NRF_PPI_GROUPS_USED))    /**< All PPI groups available to the application. */
+
+#endif
+
+
+/**@brief Function for initializing PPI module.
+ *
+ * @retval     NRF_SUCCESS                If the module was successfully initialized.
+ * @retval     MODULE_ALREADY_INITIALIZED If the module has already been initialized.
+ */
+uint32_t nrf_drv_ppi_init(void);
+
+/**@brief Function for uninitializing the PPI module. 
+ *
+ * This function also disables all channels and clears the channel groups.
+ *
+ * @retval     NRF_SUCCESS             If the module was successfully uninitialized.
+ * @retval     NRF_ERROR_INVALID_STATE If the module has not been initialized yet.
+ * @retval     NRF_ERROR_INTERNAL      If the channels or groups could not be disabled.
+ */
+uint32_t nrf_drv_ppi_uninit(void);
+
+/**@brief Function for allocating a PPI channel.
+ * @details This function allocates the first unused PPI channel.
+ *
+ * @param[out] p_channel               Pointer to the PPI channel that has been allocated.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully allocated.
+ * @retval     NRF_ERROR_NO_MEM        If there is no available channel to be used.
+ */
+uint32_t nrf_drv_ppi_channel_alloc(nrf_ppi_channel_t * p_channel);
+
+/**@brief Function for freeing a PPI channel.
+ * @details This function also disables the chosen channel.
+ *
+ * @param[in]  channel                 PPI channel to be freed.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully freed.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ */
+uint32_t nrf_drv_ppi_channel_free(nrf_ppi_channel_t channel);
+
+/**@brief Function for assigning task and event endpoints to the PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be assigned endpoints.
+ *
+ * @param[in]  eep                     Event endpoint address.
+ *
+ * @param[in]  tep                     Task endpoint address.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully assigned.
+ * @retval     NRF_ERROR_INVALID_STATE If the channel is not allocated for the user.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ */
+uint32_t nrf_drv_ppi_channel_assign(nrf_ppi_channel_t channel, uint32_t eep, uint32_t tep);
+
+/**@brief Function for assigning or clearing fork endpoint to the PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be assigned endpoints.
+ *
+ * @param[in]  fork_tep                Fork task endpoint address or 0 to clear.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully assigned.
+ * @retval     NRF_ERROR_INVALID_STATE If the channel is not allocated for the user.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel is not user-configurable.
+ * @retval     NRF_ERROR_NOT_SUPPORTED If function is not supported.
+ */
+uint32_t nrf_drv_ppi_channel_fork_assign(nrf_ppi_channel_t channel, uint32_t fork_tep);
+
+/**@brief Function for enabling a PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be enabled.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully enabled.
+ * @retval     NRF_ERROR_INVALID_STATE If the user-configurable channel is not allocated.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel cannot be enabled by the user.
+ */
+uint32_t nrf_drv_ppi_channel_enable(nrf_ppi_channel_t channel);
+
+/**@brief Function for disabling a PPI channel.
+ *
+ * @param[in]  channel                 PPI channel to be disabled.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully disabled.
+ * @retval     NRF_ERROR_INVALID_STATE If the user-configurable channel is not allocated.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel cannot be disabled by the user.
+ */
+uint32_t nrf_drv_ppi_channel_disable(nrf_ppi_channel_t channel);
+
+/**@brief Function for allocating a PPI channel group.
+ * @details This function allocates the first unused PPI group.
+ *
+ * @param[out] p_group                 Pointer to the PPI channel group that has been allocated.
+ *
+ * @retval     NRF_SUCCESS             If the channel group was successfully allocated.
+ * @retval     NRF_ERROR_NO_MEM        If there is no available channel group to be used.
+ */
+uint32_t nrf_drv_ppi_group_alloc(nrf_ppi_channel_group_t * p_group);
+
+/**@brief Function for freeing a PPI channel group.
+ * @details This function also disables the chosen group.
+ *
+ * @param[in]  group                   PPI channel group to be freed.
+ *
+ * @retval     NRF_SUCCESS             If the channel group was successfully freed.
+ * @retval     NRF_ERROR_INVALID_PARAM If the channel group is not user-configurable.
+ */
+uint32_t nrf_drv_ppi_group_free(nrf_ppi_channel_group_t group);
+
+/**@brief  Compute a channel mask for NRF_PPI registers.
+ *
+ * @param[in]  channel  Channel number to transform to a mask.
+ *
+ * @retval     Channel mask.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_channel_to_mask(nrf_ppi_channel_t channel)
+{
+    return (1uL << (uint32_t) channel);
+}
+
+/**@brief Function for including multiple PPI channels in a channel group.
+ *
+ * @param[in]  channel_mask            PPI channels to be added.
+ * @param[in]  group                   Channel group in which to include the channels.
+ *
+ * @retval     NRF_SUCCESS             If the channels was successfully included.
+ */
+uint32_t nrf_drv_ppi_channels_include_in_group(uint32_t channel_mask,
+                                               nrf_ppi_channel_group_t group);
+
+/**@brief Function for including a PPI channel in a channel group.
+ *
+ * @param[in]  channel                 PPI channel to be added.
+ * @param[in]  group                   Channel group in which to include the channel.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully included.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_channel_include_in_group(nrf_ppi_channel_t       channel,
+                                                              nrf_ppi_channel_group_t group)
+{
+    return nrf_drv_ppi_channels_include_in_group(nrf_drv_ppi_channel_to_mask(channel), group);
+}
+
+/**@brief Function for removing multiple PPI channels from a channel group.
+ *
+ * @param[in]  channel_mask            PPI channels to be removed.
+ * @param[in]  group                   Channel group from which to remove the channels.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully removed.
+ */
+uint32_t nrf_drv_ppi_channels_remove_from_group(uint32_t channel_mask,
+                                                nrf_ppi_channel_group_t group);
+
+/**@brief Function for removing a PPI channel from a channel group.
+ *
+ * @param[in]  channel                 PPI channel to be removed.
+ * @param[in]  group                   Channel group from which to remove the channel.
+ *
+ * @retval     NRF_SUCCESS             If the channel was successfully removed.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_channel_remove_from_group(nrf_ppi_channel_t       channel,
+                                                               nrf_ppi_channel_group_t group)
+{
+    return nrf_drv_ppi_channels_remove_from_group(nrf_drv_ppi_channel_to_mask(channel), group);
+}
+
+/**@brief Function for clearing a PPI channel group.
+ *
+ * @param[in]  group                   Channel group to be cleared.
+ *
+ * @retval     NRF_SUCCESS             If the group was successfully cleared.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_group_clear(nrf_ppi_channel_group_t group)
+{
+    return nrf_drv_ppi_channels_remove_from_group(NRF_PPI_ALL_APP_CHANNELS_MASK, group);
+}
+
+/**@brief Function for enabling a PPI channel group.
+ *
+ * @param[in]  group                   Channel group to be enabled.
+ *
+ * @retval     NRF_SUCCESS             If the group was successfully enabled.
+ */
+uint32_t nrf_drv_ppi_group_enable(nrf_ppi_channel_group_t group);
+
+/**@brief Function for disabling a PPI channel group.
+ *
+ * @param[in]  group                   Channel group to be disabled.
+ *
+ * @retval     NRF_SUCCESS             If the group was successfully disabled.
+ */
+uint32_t nrf_drv_ppi_group_disable(nrf_ppi_channel_group_t group);
+
+/**
+ * @brief Function for getting the address of a PPI task.
+ *
+ * @param[in]  task                      Task.
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_task_addr_get(nrf_ppi_task_t task)
+{
+    return (uint32_t) nrf_ppi_task_address_get(task);
+}
+
+/**
+ * @brief Function for getting the address of a PPI group enable task.
+ *
+ * @param[in]  group                     PPI channel group
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_task_addr_group_enable_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t) nrf_ppi_task_group_enable_address_get(group);
+}
+
+/**
+ * @brief Function for getting the address of a PPI group enable task.
+ *
+ * @param[in]  group                     PPI channel group
+ *
+ * @retval     Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_ppi_task_addr_group_disable_get(nrf_ppi_channel_group_t group)
+{
+    return (uint32_t) nrf_ppi_task_group_disable_address_get(group);
+}
+
+/**
+ *@}
+ **/
+
+/*lint --flb "Leave library region" */
+#endif // NRF_DRV_PPI_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/config/pstorage_platform.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/config/pstorage_platform.h
new file mode 100644
index 0000000000..113fd637fc
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/config/pstorage_platform.h
@@ -0,0 +1,99 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /** @cond To make doxygen skip this file */
+
+/** @file
+ *  This header contains defines with respect persistent storage that are specific to
+ *  persistent storage implementation and application use case.
+ */
+#ifndef PSTORAGE_PL_H__
+#define PSTORAGE_PL_H__
+
+#include <stdint.h>
+#include "nrf.h"
+
+static __INLINE uint16_t pstorage_flash_page_size()
+{
+  	return (uint16_t)NRF_FICR->CODEPAGESIZE;
+}
+
+#define PSTORAGE_FLASH_PAGE_SIZE     pstorage_flash_page_size()          /**< Size of one flash page. */
+#define PSTORAGE_FLASH_EMPTY_MASK    0xFFFFFFFF                          /**< Bit mask that defines an empty address in flash. */
+
+static __INLINE uint32_t pstorage_flash_page_end()
+{
+   uint32_t bootloader_addr = NRF_UICR->NRFFW[0];
+  
+   return ((bootloader_addr != PSTORAGE_FLASH_EMPTY_MASK) ?
+           (bootloader_addr/ PSTORAGE_FLASH_PAGE_SIZE) : NRF_FICR->CODESIZE);
+}
+
+#define PSTORAGE_FLASH_PAGE_END     pstorage_flash_page_end()
+
+#define PSTORAGE_NUM_OF_PAGES       1                                                           /**< Number of flash pages allocated for the pstorage module excluding the swap page, configurable based on system requirements. */
+#define PSTORAGE_MIN_BLOCK_SIZE     0x0010                                                      /**< Minimum size of block that can be registered with the module. Should be configured based on system requirements, recommendation is not have this value to be at least size of word. */
+
+#define PSTORAGE_DATA_START_ADDR    ((PSTORAGE_FLASH_PAGE_END - PSTORAGE_NUM_OF_PAGES - 1) \
+                                    * PSTORAGE_FLASH_PAGE_SIZE)                                 /**< Start address for persistent data, configurable according to system requirements. */
+#define PSTORAGE_DATA_END_ADDR      ((PSTORAGE_FLASH_PAGE_END - 1) * PSTORAGE_FLASH_PAGE_SIZE)  /**< End address for persistent data, configurable according to system requirements. */
+#define PSTORAGE_SWAP_ADDR          PSTORAGE_DATA_END_ADDR                                      /**< Top-most page is used as swap area for clear and update. */
+
+#define PSTORAGE_MAX_BLOCK_SIZE     PSTORAGE_FLASH_PAGE_SIZE                                    /**< Maximum size of block that can be registered with the module. Should be configured based on system requirements. And should be greater than or equal to the minimum size. */
+#define PSTORAGE_CMD_QUEUE_SIZE     10                                                          /**< Maximum number of flash access commands that can be maintained by the module for all applications. Configurable. */
+
+
+/** Abstracts persistently memory block identifier. */
+typedef uint32_t pstorage_block_t;
+
+typedef struct
+{
+    uint32_t            module_id;      /**< Module ID.*/
+    pstorage_block_t    block_id;       /**< Block ID.*/
+} pstorage_handle_t;
+
+typedef uint16_t pstorage_size_t;      /** Size of length and offset fields. */
+
+/**@brief Handles Flash Access Result Events. To be called in the system event dispatcher of the application. */
+void pstorage_sys_event_handler (uint32_t sys_evt);
+
+#endif // PSTORAGE_PL_H__
+
+/** @} */
+/** @endcond */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.c
new file mode 100644
index 0000000000..f39fe2c1e7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.c
@@ -0,0 +1,1599 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "pstorage.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "nordic_common.h"
+#include "nrf_error.h"
+#include "nrf_assert.h"
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "app_util.h"
+#include "app_error.h"
+
+#define INVALID_OPCODE             0x00                                /**< Invalid op code identifier. */
+#define SOC_MAX_WRITE_SIZE         PSTORAGE_FLASH_PAGE_SIZE            /**< Maximum write size allowed for a single call to \ref sd_flash_write as specified in the SoC API. */
+#define RAW_MODE_APP_ID            (PSTORAGE_NUM_OF_PAGES + 1)         /**< Application id for raw mode. */
+
+#if defined(NRF52)
+#define SD_CMD_MAX_TRIES           1000                                /**< Number of times to try a softdevice flash operatoion, specific for nRF52 to account for longest time of flash page erase*/
+#else
+#define SD_CMD_MAX_TRIES           3                                   /**< Number of times to try a softdevice flash operation when the @ref NRF_EVT_FLASH_OPERATION_ERROR sys_evt is received. */
+#endif /* defined(NRF52) */
+
+#define MASK_TAIL_SWAP_DONE        (1 << 0)                            /**< Flag for checking if the tail restore area has been written to swap page. */     
+#define MASK_SINGLE_PAGE_OPERATION (1 << 1)                            /**< Flag for checking if command is a single flash page operation. */
+#define MASK_MODULE_INITIALIZED    (1 << 2)                            /**< Flag for checking if the module has been initialized. */
+#define MASK_FLASH_API_ERR_BUSY    (1 << 3)                            /**< Flag for checking if flash API returned NRF_ERROR_BUSY. */
+
+/**
+ * @defgroup api_param_check API Parameters check macros.
+ *
+ * @details Macros that verify parameters passed to the module in the APIs. These macros
+ *          could be mapped to nothing in final code versions to save execution and size.
+ *
+ * @{
+ */
+
+/**@brief Check if the input pointer is NULL, if so it returns NRF_ERROR_NULL.
+ */
+#define NULL_PARAM_CHECK(PARAM)                                                                   \
+        if ((PARAM) == NULL)                                                                      \
+        {                                                                                         \
+            return NRF_ERROR_NULL;                                                                \
+        }
+
+/**@brief Verifies that the module identifier supplied by the application is within permissible
+ *        range.
+ */
+#define MODULE_ID_RANGE_CHECK(ID)                                                                 \
+        if ((((ID)->module_id) >= PSTORAGE_NUM_OF_PAGES) ||                                       \
+            (m_app_table[(ID)->module_id].cb == NULL))                                            \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }
+
+/**@brief Verifies that the block identifier supplied by the application is within the permissible
+ *        range.
+ */
+#define BLOCK_ID_RANGE_CHECK(ID)                                                                  \
+        if (((ID)->block_id) >= (m_app_table[(ID)->module_id].base_id +                           \
+            (m_app_table[(ID)->module_id].block_count * MODULE_BLOCK_SIZE(ID))))                  \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }
+
+/**@brief Verifies that the block size requested by the application can be supported by the module.
+ */
+#define BLOCK_SIZE_CHECK(X)                                                                       \
+        if (((X) > PSTORAGE_MAX_BLOCK_SIZE) || ((X) < PSTORAGE_MIN_BLOCK_SIZE))                   \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }
+
+/**@brief Verifies the block size requested by the application in registration API.
+ */
+#define BLOCK_COUNT_CHECK(COUNT, SIZE)                                                            \
+        if (((COUNT) == 0) ||                                                                     \
+            ((m_next_page_addr + ((COUNT) *(SIZE)) > PSTORAGE_SWAP_ADDR)))                        \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }        
+
+/**@brief Verifies the size parameter provided by the application in API.
+ */
+#define SIZE_CHECK(ID, SIZE)                                                                      \
+        if(((SIZE) == 0) || ((SIZE) > MODULE_BLOCK_SIZE(ID)))                                     \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }
+
+/**@brief Verifies the offset parameter provided by the application in API.
+ */
+#define OFFSET_CHECK(ID, OFFSET, SIZE)                                                            \
+        if(((SIZE) + (OFFSET)) > MODULE_BLOCK_SIZE(ID))                                           \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+/**@brief Verifies the module identifier supplied by the application.
+ */
+#define MODULE_RAW_HANDLE_CHECK(ID)                                                               \
+        if ((((ID)->module_id) != RAW_MODE_APP_ID))                                               \
+        {                                                                                         \
+            return NRF_ERROR_INVALID_PARAM;                                                       \
+        }
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+/**@} */
+
+
+/**@brief Verify module's initialization status.
+ *
+ * @details  Verify module's initialization status. Returns NRF_ERROR_INVALID_STATE when a
+ *           module API is called without initializing the module.
+ */
+#define VERIFY_MODULE_INITIALIZED()                                                               \
+        do                                                                                        \
+        {                                                                                         \
+            if (!(m_flags & MASK_MODULE_INITIALIZED))                                             \
+            {                                                                                     \
+                 return NRF_ERROR_INVALID_STATE;                                                  \
+            }                                                                                     \
+        } while(0)
+
+/**@brief Macro to fetch the block size registered for the module. */
+#define MODULE_BLOCK_SIZE(ID) (m_app_table[(ID)->module_id].block_size)
+
+/**@brief Main state machine of the component. */
+typedef enum
+{
+    STATE_IDLE,                                                        /**< State for being idle (no command execution in progress). */
+    STATE_STORE,                                                       /**< State for storing data when using store/update API. */
+    STATE_DATA_ERASE_WITH_SWAP,                                        /**< State for erasing the data page when using update/clear API when use of swap page is required. */
+    STATE_DATA_ERASE,                                                  /**< State for erasing the data page when using update/clear API without the need to use the swap page. */
+    STATE_ERROR                                                        /**< State entered when command processing is terminated abnormally. */
+} pstorage_state_t;  
+
+/**@brief Sub state machine contained by @ref STATE_DATA_ERASE_WITH_SWAP super state machine. */
+typedef enum
+{
+    STATE_ERASE_SWAP,                                                  /**< State for erasing the swap page when using the update/clear API. */   
+    STATE_WRITE_DATA_TO_SWAP,                                          /**< State for writing the data page into the swap page when using update/clear API. */
+    STATE_ERASE_DATA_PAGE,                                             /**< State for erasing data page when using update/clear API. */
+    STATE_RESTORE_TAIL,                                                /**< State for restoring tail (end) of backed up data from swap to data page when using update/clear API. */
+    STATE_RESTORE_HEAD,                                                /**< State for restoring head (beginning) of backed up data from swap to data page when using update/clear API. */
+    SWAP_SUB_STATE_MAX                                                 /**< Enumeration upper bound. */   
+} flash_swap_sub_state_t;
+
+/**@brief Application registration information.
+ *
+ * @details Defines application specific information that the application needs to maintain to be able 
+ *          to process requests from each one of them.
+ */
+typedef struct
+{
+    pstorage_ntf_cb_t cb;                                              /**< Callback registered with the module to be notified of result of flash access.  */
+    pstorage_block_t  base_id;                                         /**< Base block ID assigned to the module. */
+    pstorage_size_t   block_size;                                      /**< Size of block for the module. */
+    pstorage_size_t   block_count;                                     /**< Number of blocks requested by the application. */
+} pstorage_module_table_t;
+
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+/**@brief Application registration information.
+ *
+ * @details Defines application specific information that the application registered for raw mode.
+ */
+typedef struct
+{
+    pstorage_ntf_cb_t cb;                                              /**< Callback registered with the module to be notified of the result of flash access.  */
+} pstorage_raw_module_table_t;
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+
+/**@brief Defines command queue element.
+ *
+ * @details Defines command queue element. Each element encapsulates needed information to process
+ *          a flash access command.
+ */
+typedef struct
+{
+    uint8_t           op_code;                                         /**< Identifies the flash access operation being queued. Element is free if op-code is INVALID_OPCODE. */
+    pstorage_size_t   size;                                            /**< Identifies the size in bytes requested for the operation. */
+    pstorage_size_t   offset;                                          /**< Offset requested by the application for the access operation. */
+    pstorage_handle_t storage_addr;                                    /**< Address/Identifier for persistent memory. */
+    uint8_t *         p_data_addr;                                     /**< Address/Identifier for data memory. This is assumed to be resident memory. */
+} cmd_queue_element_t;
+
+
+/**@brief   Defines command queue, an element is free if the op_code field is not invalid.
+ *
+ * @details Defines commands enqueued for flash access. At any point in time, this queue has one or
+ *          more flash access operations pending if the count field is not zero. When the queue is
+ *          not empty, the rp (read pointer) field points to the flash access command in progress 
+ *          or, if none is in progress, the command to be requested next. The queue implements a 
+ *          simple first in first out algorithm. Data addresses are assumed to be resident.
+ */
+typedef struct
+{
+    uint8_t             rp;                                            /**< Read pointer, pointing to flash access that is ongoing or to be requested next. */
+    uint8_t             count;                                         /**< Number of elements in the queue.  */
+    cmd_queue_element_t cmd[PSTORAGE_CMD_QUEUE_SIZE];                  /**< Array to maintain flash access operation details. */
+} cmd_queue_t;
+
+static cmd_queue_t             m_cmd_queue;                            /**< Flash operation request queue. */
+static pstorage_size_t         m_next_app_instance;                    /**< Points to the application module instance that can be allocated next. */
+static uint32_t                m_next_page_addr;                       /**< Points to the flash address that can be allocated to a module next. This is needed as blocks of a module that can span across flash pages. */
+static pstorage_state_t        m_state;                                /**< Main state tracking variable. */
+static flash_swap_sub_state_t  m_swap_sub_state;                       /**< Flash swap erase when swap used state tracking variable. */
+static uint32_t                m_head_word_size;                       /**< Head restore area size in words. */
+static uint32_t                m_tail_word_size;                       /**< Tail restore area size in words. */
+static uint32_t                m_current_page_id;                      /**< Variable for tracking the flash page being processed. */
+static uint32_t                m_num_of_command_retries;               /**< Variable for tracking flash operation retries upon flash operation failures. */
+static pstorage_module_table_t m_app_table[PSTORAGE_NUM_OF_PAGES];     /**< Registered application information table. */
+static uint32_t                m_num_of_bytes_written;                 /**< Variable for tracking the number of bytes written by the store operation. */
+static uint32_t                m_app_data_size;                        /**< Variable for storing the application command size parameter internally. */
+static uint32_t                m_flags = 0;                            /**< Storage for boolean flags for state tracking. */
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+static pstorage_raw_module_table_t m_raw_app_table;                    /**< Registered application information table for raw mode. */
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+// Required forward declarations.
+static void cmd_process(void);
+static void store_operation_execute(void);
+static void app_notify(uint32_t result, cmd_queue_element_t * p_elem);
+static void cmd_queue_element_init(uint32_t index);
+static void cmd_queue_dequeue(void);
+static void sm_state_change(pstorage_state_t new_state);
+static void swap_sub_state_state_change(flash_swap_sub_state_t new_state); 
+
+/**@brief Function for consuming a command queue element.
+ *
+ * @details Function for consuming a command queue element, which has been fully processed.
+ */
+static void command_queue_element_consume(void)
+{
+    // Initialize/free the element as it is now processed.    
+    cmd_queue_element_init(m_cmd_queue.rp);
+
+    // Adjust command queue state tracking variables.
+    --(m_cmd_queue.count);   
+    if (++(m_cmd_queue.rp) == PSTORAGE_CMD_QUEUE_SIZE)
+    {
+        m_cmd_queue.rp = 0;
+    }    
+}
+
+
+/**@brief Function for executing the finalization procedure for the command executed.
+ *
+ * @details Function for executing the finalization procedure for command executed, which includes 
+ *          notifying the application of command completion, consuming the command queue element, 
+ *          and changing the internal state.
+ */
+static void command_end_procedure_run(void)
+{    
+    app_notify(NRF_SUCCESS, &m_cmd_queue.cmd[m_cmd_queue.rp]);
+    
+    command_queue_element_consume();
+    
+    sm_state_change(STATE_IDLE);
+}
+
+
+/**@brief Function for idle state entry actions.
+ *
+ * @details Function for idle state entry actions, which include resetting relevant state data and 
+ *          scheduling any possible queued flash access operation.
+ */
+static void state_idle_entry_run(void)
+{
+    m_num_of_command_retries = 0;
+    m_num_of_bytes_written   = 0;
+    
+    // Schedule any possible queued flash access operation.
+    cmd_queue_dequeue();
+}
+
+
+/**@brief Function for notifying an application of command completion and transitioning to an error 
+ *        state.
+ *
+ * @param[in] result Result code of the operation for the application.
+ */
+static void app_notify_error_state_transit(uint32_t result)
+{
+    app_notify(result, &m_cmd_queue.cmd[m_cmd_queue.rp]);
+    sm_state_change(STATE_ERROR);                
+}
+
+
+/**@brief Function for processing flash API error code.
+ *
+ * @param[in] err_code Error code from the flash API.
+ */
+static void flash_api_err_code_process(uint32_t err_code)
+{
+    switch (err_code)
+    {
+        case NRF_SUCCESS:
+            break;
+            
+        case NRF_ERROR_BUSY:
+            // Flash access operation was not accepted and must be reissued upon flash operation 
+            // complete event.
+            m_flags |= MASK_FLASH_API_ERR_BUSY;        
+            break;
+            
+        default:
+            // Complete the operation with appropriate result code and transit to an error state. 
+            app_notify_error_state_transit(err_code);
+            break;
+    }
+}
+
+/**@brief Function for writing data to flash.
+ *
+ * @param[in] p_dst         Pointer to start of flash location to be written.
+ * @param[in] p_src         Pointer to buffer with data to be written.
+ * @param[in] size_in_words Number of 32-bit words to write. 
+ */
+static void flash_write(uint32_t * const       p_dst, 
+                        uint32_t const * const p_src, 
+                        uint32_t               size_in_words)
+{
+    flash_api_err_code_process(sd_flash_write(p_dst, p_src, size_in_words));    
+}
+
+
+/**@brief Function for writing data to flash upon store command.
+ *
+ * @details Function for writing data to flash upon executing store command. Data is written to 
+ *          flash in reverse order, meaning starting at the end. If the data that is to be written 
+ *          is greater than the flash page size, it will be fragmented to fit the flash page size.
+ */
+static void store_cmd_flash_write_execute(void)
+{
+    const cmd_queue_element_t * p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp];
+    
+    if (p_cmd->size > SOC_MAX_WRITE_SIZE)    
+    {
+        const uint32_t offset = p_cmd->size - PSTORAGE_FLASH_PAGE_SIZE;
+        flash_write((uint32_t *)(p_cmd->storage_addr.block_id + p_cmd->offset + offset),
+                    (uint32_t *)(p_cmd->p_data_addr + offset), 
+                    PSTORAGE_FLASH_PAGE_SIZE / sizeof(uint32_t));   
+
+        m_num_of_bytes_written = PSTORAGE_FLASH_PAGE_SIZE;    
+    }
+    else
+    {
+        flash_write((uint32_t *)(p_cmd->storage_addr.block_id + p_cmd->offset),
+                    (uint32_t *)(p_cmd->p_data_addr), 
+                    p_cmd->size / sizeof(uint32_t));   
+
+        m_num_of_bytes_written = p_cmd->size;        
+    }    
+}
+
+
+/**@brief Function for store state entry action.
+ *
+ * @details Function for store state entry action, which includes writing data to a flash page.
+ */
+static void state_store_entry_run(void)
+{
+    store_cmd_flash_write_execute();    
+}
+
+
+/**@brief Function for data erase with swap state entry actions.
+ *
+ * @details Function for data erase with swap state entry actions. This includes adjusting relevant 
+ *          state and data variables and transitioning to the correct sub state.
+ */
+static void state_data_erase_swap_entry_run(void)
+{
+    m_flags &= ~MASK_TAIL_SWAP_DONE;
+    
+    const cmd_queue_element_t * p_cmd        = &m_cmd_queue.cmd[m_cmd_queue.rp];
+    const pstorage_block_t      cmd_block_id = p_cmd->storage_addr.block_id;
+    
+    const uint32_t clear_start_page_id = cmd_block_id / PSTORAGE_FLASH_PAGE_SIZE;
+    m_current_page_id                  = clear_start_page_id;      
+        
+    // @note: No need to include p_cmd->offset when calculating clear_end_page_id as:
+    // - clear API does not include offset parameter
+    // - update and store APIs are limited to operate on single block boundary thus the boolean 
+    // clause ((m_head_word_size == 0) && is_more_than_one_page) below in this function  will never 
+    // evaluate as true as if is_more_than_one_page == true m_head_word_size is always != 0        
+    const uint32_t clear_end_page_id  = (cmd_block_id + p_cmd->size - 1u) / 
+                                        PSTORAGE_FLASH_PAGE_SIZE;
+
+    if (clear_start_page_id == clear_end_page_id)
+    {
+        m_flags |= MASK_SINGLE_PAGE_OPERATION;
+    }
+    else
+    {
+        m_flags &= ~MASK_SINGLE_PAGE_OPERATION;
+    }
+                            
+    if ((m_head_word_size == 0) && !(m_flags & MASK_SINGLE_PAGE_OPERATION))
+    {        
+        // No head restore required and clear/update area is shared by multiple flash pages, which 
+        // means the current flash page does not have any tail area to restore. You can proceed with 
+        // data page erase directly as no swap is needed for the current flash page.
+        swap_sub_state_state_change(STATE_ERASE_DATA_PAGE);        
+    }
+    else
+    {     
+        swap_sub_state_state_change(STATE_ERASE_SWAP);
+    }               
+}
+
+
+/**@brief Function for erasing flash page.
+ *
+ * @param[in] page_number Page number of the page to be erased.
+ */
+static void flash_page_erase(uint32_t page_number)
+{
+    flash_api_err_code_process(sd_flash_page_erase(page_number));
+}
+
+
+/**@brief Function for data erase state entry action.
+ *
+ * @details Function for data erase state entry action, which includes erasing the data flash page.
+ */
+static void state_data_erase_entry_run(void)
+{
+    flash_page_erase(m_current_page_id);                          
+}
+
+
+/**@brief Function for dispatching the correct application main state entry action.
+ */
+static void state_entry_action_run(void)
+{
+    switch (m_state)
+    {
+        case STATE_IDLE:
+            state_idle_entry_run();
+            break;
+
+        case STATE_STORE:
+            state_store_entry_run();
+            break;
+            
+        case STATE_DATA_ERASE_WITH_SWAP:
+            state_data_erase_swap_entry_run();
+            break;
+            
+        case STATE_DATA_ERASE:
+            state_data_erase_entry_run();        
+            break;
+                        
+        default:
+            // No action needed.
+            break;
+    }
+}
+
+
+/**@brief Function for changing application main state and dispatching state entry action.
+ *
+ * @param[in] new_state New application main state to transit to.
+ */
+static void sm_state_change(pstorage_state_t new_state)
+{
+    m_state = new_state;
+    state_entry_action_run();
+}
+
+
+/**@brief Function for swap erase state entry action.
+ *
+ * @details Function for swap erase state entry action, which includes erasing swap flash 
+ *          page.
+ */
+static void state_swap_erase_entry_run(void)
+{
+    flash_page_erase(PSTORAGE_SWAP_ADDR / PSTORAGE_FLASH_PAGE_SIZE);                
+}
+
+
+/**@brief Function for write data to the swap state entry action.
+ *
+ * @details Function for write data to the swap state entry action, which includes writing the 
+ *          current data page to the swap flash page.
+ */
+static void state_write_data_swap_entry_run(void)
+{
+    // @note: There is room for further optimization here as there is only need to write the
+    // whole flash page to swap area if there is both head and tail area to be restored. In any 
+    // other case we can omit some data from the head or end of the page as that is the clear area.
+    flash_write((uint32_t *)(PSTORAGE_SWAP_ADDR), 
+                (uint32_t *)(m_current_page_id * PSTORAGE_FLASH_PAGE_SIZE), 
+                PSTORAGE_FLASH_PAGE_SIZE / sizeof(uint32_t));    
+}
+
+
+/**@brief Function for erase data page state entry action.
+ *
+ * @details Function for erase data page state entry action, which includes erasing the data flash 
+ *          page.
+ */
+static void state_erase_data_page_entry_run(void)
+{
+    flash_page_erase(m_current_page_id);
+}
+
+
+/**@brief Function for restore tail state entry action.
+ *
+ * @details Function for restore tail state entry action, which includes writing the tail section 
+ *          back from swap to the data page.
+ */
+static void state_restore_tail_entry_run(void)
+{
+    const cmd_queue_element_t * p_cmd        = &m_cmd_queue.cmd[m_cmd_queue.rp];    
+    const pstorage_block_t      cmd_block_id = p_cmd->storage_addr.block_id;                            
+    
+    const uint32_t tail_offset = (cmd_block_id + p_cmd->size + p_cmd->offset) % 
+                                 PSTORAGE_FLASH_PAGE_SIZE; 
+                                 
+    flash_write((uint32_t *)(cmd_block_id + p_cmd->size + p_cmd->offset),
+                (uint32_t *)(PSTORAGE_SWAP_ADDR + tail_offset),
+                m_tail_word_size);
+}
+
+
+/**@brief Function for restore head state entry action.
+ *
+ * @details Function for restore head state entry action, which includes writing the head section 
+ *          back from swap to the data page.
+ */
+static void state_restore_head_entry_run(void)
+{
+    flash_write((uint32_t *)((m_current_page_id - 1u) * PSTORAGE_FLASH_PAGE_SIZE),
+                (uint32_t *)PSTORAGE_SWAP_ADDR,
+                m_head_word_size);
+}
+
+
+/**@brief Function for dispatching the correct swap sub state entry action.
+ */
+static void swap_sub_state_entry_action_run(void)
+{
+    static void (* const swap_sub_state_sm_lut[SWAP_SUB_STATE_MAX])(void) = 
+    {
+        state_swap_erase_entry_run,
+        state_write_data_swap_entry_run,
+        state_erase_data_page_entry_run,
+        state_restore_tail_entry_run,
+        state_restore_head_entry_run
+    };
+    
+    swap_sub_state_sm_lut[m_swap_sub_state]();
+}
+
+
+/**@brief Function for changing the swap sub state and dispatching state entry action.
+ *
+ * @param[in] new_state New swap sub state to transit to.
+ */   
+static void swap_sub_state_state_change(flash_swap_sub_state_t new_state)
+{
+    m_swap_sub_state = new_state;
+    swap_sub_state_entry_action_run();    
+}
+
+
+/**@brief Function for initializing the command queue element.
+ *
+ * @param[in] index Index of the element to be initialized.
+ */
+static void cmd_queue_element_init(uint32_t index)
+{
+    // Internal function and checks on range of index can be avoided.
+    m_cmd_queue.cmd[index].op_code                = INVALID_OPCODE;
+    m_cmd_queue.cmd[index].size                   = 0;
+    m_cmd_queue.cmd[index].storage_addr.module_id = PSTORAGE_NUM_OF_PAGES;
+    m_cmd_queue.cmd[index].storage_addr.block_id  = 0;
+    m_cmd_queue.cmd[index].p_data_addr            = NULL;
+    m_cmd_queue.cmd[index].offset                 = 0;
+}
+
+
+/**@brief Function for initializing the command queue.
+ */
+static void cmd_queue_init(void)
+{
+    m_cmd_queue.rp    = 0;
+    m_cmd_queue.count = 0;
+
+    for (uint32_t cmd_index = 0; cmd_index < PSTORAGE_CMD_QUEUE_SIZE; ++cmd_index)
+    {
+        cmd_queue_element_init(cmd_index);
+    }
+}
+
+
+/**@brief Function for enqueuing, and possibly dispatching, a flash access operation.
+ *
+ * @param[in] opcode         Identifies the operation requested to be enqueued.
+ * @param[in] p_storage_addr Identifies the module and flash address on which the operation is 
+ *                           requested.
+ * @param[in] p_data_addr    Identifies the data address for flash access.
+ * @param[in] size           Size in bytes of data requested for the access operation.
+ * @param[in] offset         Offset within the flash memory block at which operation is requested.
+ *
+ * @retval    NRF_SUCCESS      Upon success.
+ * @retval    NRF_ERROR_NO_MEM Upon failure, when no space is available in the command queue. 
+ */
+static uint32_t cmd_queue_enqueue(uint8_t             opcode,
+                                  pstorage_handle_t * p_storage_addr,
+                                  uint8_t           * p_data_addr,
+                                  pstorage_size_t     size,
+                                  pstorage_size_t     offset)
+{
+    uint32_t err_code;
+
+    if (m_cmd_queue.count != PSTORAGE_CMD_QUEUE_SIZE)
+    {
+        // Enqueue the command if it the queue is not full.
+        uint32_t write_index = m_cmd_queue.rp + m_cmd_queue.count;
+
+        if (write_index >= PSTORAGE_CMD_QUEUE_SIZE) 
+        {
+            write_index -= PSTORAGE_CMD_QUEUE_SIZE;
+        }
+
+        m_cmd_queue.cmd[write_index].op_code      = opcode;
+        m_cmd_queue.cmd[write_index].p_data_addr  = p_data_addr;
+        m_cmd_queue.cmd[write_index].storage_addr = (*p_storage_addr);
+        m_cmd_queue.cmd[write_index].size         = size;
+        m_cmd_queue.cmd[write_index].offset       = offset;
+               
+        m_cmd_queue.count++;
+                                
+        if (m_state == STATE_IDLE)
+        {
+            cmd_process(); 
+        }            
+        
+        err_code = NRF_SUCCESS;        
+    }
+    else
+    {
+        err_code = NRF_ERROR_NO_MEM;
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for dequeing a possible pending flash access operation.
+ */
+static void cmd_queue_dequeue(void)
+{
+    if ((m_cmd_queue.count != 0)) 
+    {
+        cmd_process();
+    }
+}
+
+
+/**@brief Function for notifying an application of command completion.
+ *
+ * @param[in] result Result code of the operation for the application.
+ * @param[in] p_elem Pointer to the command queue element for which this result was received. 
+ */
+static void app_notify(uint32_t result, cmd_queue_element_t * p_elem)
+{
+    pstorage_ntf_cb_t ntf_cb;
+    const uint8_t     op_code = p_elem->op_code;
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+    if (p_elem->storage_addr.module_id == RAW_MODE_APP_ID)
+    {
+        ntf_cb = m_raw_app_table.cb;
+    }
+    else
+#endif // PSTORAGE_RAW_MODE_ENABLE
+    {
+        ntf_cb = m_app_table[p_elem->storage_addr.module_id].cb;
+    }
+
+    ntf_cb(&p_elem->storage_addr, op_code, result, p_elem->p_data_addr, m_app_data_size);
+}
+
+
+/**@brief Function for evaluating if a data page swap is required for the tail section on the 
+ *        current page.
+ *
+ * @retval true  If data page swap is required.
+ * @retval false If data page swap is not required.
+ */
+static bool is_tail_data_page_swap_required(void)
+{
+    bool ret_value;
+
+    // Extract id of the last page command is executed upon.
+    const cmd_queue_element_t * p_cmd        = &m_cmd_queue.cmd[m_cmd_queue.rp];
+    const pstorage_block_t      cmd_block_id = p_cmd->storage_addr.block_id;        
+    const uint32_t              last_page_id = (cmd_block_id + p_cmd->size + p_cmd->offset - 1u) / 
+                                               PSTORAGE_FLASH_PAGE_SIZE;    
+        
+    // If tail section area exists and the current page is the last page then tail data page swap is 
+    // required.    
+    if ((m_tail_word_size != 0) && (m_current_page_id == last_page_id))
+    {
+        ret_value = true;
+    }
+    else
+    {
+        ret_value = false;    
+    }
+    
+    return ret_value;
+}
+
+
+/**@brief Function for performing post processing for the update and clear commands.
+ *
+ * @details Function for performing post processing for the update and clear commands, which implies 
+ *          executing the correct execution path depending on the command. 
+ */
+static void clear_post_processing_run(void)
+{
+    const cmd_queue_element_t * p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp]; 
+    
+    if (p_cmd->op_code != PSTORAGE_UPDATE_OP_CODE)
+    {
+        command_end_procedure_run();    
+    }
+    else
+    {
+        store_operation_execute();                    
+    }
+}
+
+
+/**@brief Function for doing swap sub state exit action.
+ */
+static void swap_sub_sm_exit_action_run(void)
+{
+    clear_post_processing_run();
+}
+
+
+/**@brief Function for evaluating if the page erase operation is required for the current page.
+ *
+ * @retval true  If page erase is required.
+ * @retval false If page erase is not required. 
+ */
+static bool is_page_erase_required(void)
+{
+    bool ret;
+    
+    const cmd_queue_element_t * p_cmd                      = &m_cmd_queue.cmd[m_cmd_queue.rp];
+    const pstorage_block_t      cmd_block_id               = p_cmd->storage_addr.block_id;        
+    const uint32_t              id_last_page_to_be_cleared = (cmd_block_id + p_cmd->size + 
+                                                             p_cmd->offset - 1u) / 
+                                                             PSTORAGE_FLASH_PAGE_SIZE;
+
+    // True if:
+    // - current page is not the last page OR
+    // - current page is the last page AND no tail exists
+    if ((m_current_page_id < id_last_page_to_be_cleared) ||
+        ((m_current_page_id == id_last_page_to_be_cleared) && (m_tail_word_size == 0)))         
+    {
+        ret = true;
+    }
+    else
+    {
+        ret = false;
+    }
+    
+    return ret;
+}
+
+
+/**@brief Function for reissuing the last flash operation request, which was rejected by the flash 
+ *        API, in swap sub sate.
+ */
+static void swap_sub_state_err_busy_process(void)
+{
+    // Reissue the request by doing a self transition to the current state.    
+    m_flags &= ~MASK_FLASH_API_ERR_BUSY;
+    swap_sub_state_state_change(m_swap_sub_state);        
+}
+
+
+/**@brief Function for doing restore head state action upon flash operation success event.
+ *
+ * @details Function for doing restore head state action upon flash operation success event, which 
+ *          includes making a state transition depending on the current state.
+ */
+static void head_restore_state_run(void)
+{
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {            
+        if (is_tail_data_page_swap_required())
+        {
+            // Additional data page needs to be swapped for tail section as we are clearing a block, 
+            // which is shared between 2 flash pages.
+                    
+            // Adjust variables to ensure correct state transition path is taken after the tail 
+            // section swap has completed.
+            m_head_word_size = 0;   
+            m_flags         |= MASK_TAIL_SWAP_DONE;        
+                  
+            swap_sub_state_state_change(STATE_ERASE_SWAP);        
+        }
+        else if (is_page_erase_required())
+        {
+            // Additional page erase operation is required.
+                    
+            // Adjust variable to ensure correct state transition path is taken after the additional 
+            // page erase operation has completed.
+            m_head_word_size = 0;
+            swap_sub_state_state_change(STATE_ERASE_DATA_PAGE);        
+        }            
+        else if (m_tail_word_size != 0)
+        {
+            // Proceed with restoring tail from swap to data page. 
+            swap_sub_state_state_change(STATE_RESTORE_TAIL);
+        }
+        else
+        {            
+            // Swap statemachine execution end reached.
+            swap_sub_sm_exit_action_run();        
+        }
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        swap_sub_state_err_busy_process();        
+    }
+}
+
+
+/**@brief Function for doing restore tail state action upon flash operation success event.
+ */
+static void tail_restore_state_run(void)
+{
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {
+        swap_sub_sm_exit_action_run();        
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        swap_sub_state_err_busy_process();        
+    }    
+}
+
+
+/**@brief Function for doing data page erase state action upon a flash operation success event.
+ *
+ * @details Function for doing data page erase state action upon a flash operation success event, 
+ *          which includes making a state transit to a new state depending on the current state.
+ */
+static void data_page_erase_state_run(void)
+{            
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {
+        ++m_current_page_id;   
+                    
+        if (m_head_word_size != 0)
+        {            
+            swap_sub_state_state_change(STATE_RESTORE_HEAD);
+        }
+        else if (is_page_erase_required())
+        {
+            // Additional page erase operation is required.    
+            swap_sub_state_state_change(STATE_ERASE_DATA_PAGE);                
+        }                
+        else if (m_tail_word_size != 0)
+        {                    
+            if (!(m_flags & MASK_TAIL_SWAP_DONE)) 
+            {
+                // Tail area restore is required and we have not yet written the relevant data page 
+                // to swap area. Start the process of writing the data page to swap.
+                m_flags |= MASK_TAIL_SWAP_DONE;            
+
+                swap_sub_state_state_change(STATE_ERASE_SWAP);            
+            }
+            else
+            {
+                // Tail area restore is required and we have already written the relevant data page 
+                // to swap area. Proceed by restoring the tail area.
+                swap_sub_state_state_change(STATE_RESTORE_TAIL);            
+            }
+        }            
+        else
+        {
+            swap_sub_sm_exit_action_run();        
+        }        
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        swap_sub_state_err_busy_process();        
+    }
+}
+
+
+/**@brief Function for doing data to swap write state action upon flash operation success event.
+ */
+static void data_to_swap_write_state_run(void)
+{        
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {
+        // If the operation is executed only on 1 single flash page it automatically means that tail 
+        // area is written to the swap, which we store to flags.     
+        if (m_flags & MASK_SINGLE_PAGE_OPERATION)
+        {
+            m_flags |= MASK_TAIL_SWAP_DONE;        
+        }
+
+        swap_sub_state_state_change(STATE_ERASE_DATA_PAGE);    
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        swap_sub_state_err_busy_process();        
+    }        
+}
+
+
+/**@brief Function for doing swap erase state action upon flash operation success event.
+ */
+static void swap_erase_state_run(void)
+{
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {        
+        swap_sub_state_state_change(STATE_WRITE_DATA_TO_SWAP);
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        swap_sub_state_err_busy_process();        
+    }
+}
+
+
+/**@brief Function for dispatching the correct state action for data erase with a swap composite 
+*         state upon a flash operation success event.
+ */
+static void swap_sub_state_sm_run(void)
+{  
+    static void (* const swap_sub_state_sm_lut[SWAP_SUB_STATE_MAX])(void) = 
+    {
+        swap_erase_state_run,
+        data_to_swap_write_state_run,
+        data_page_erase_state_run,
+        tail_restore_state_run,
+        head_restore_state_run
+    };
+    
+    swap_sub_state_sm_lut[m_swap_sub_state]();    
+}
+
+
+/**@brief Function for reissuing the last flash operation request, which was rejected by the flash 
+ *        API, in main sate.
+ */
+static void main_state_err_busy_process(void)
+{
+    // Reissue the request by doing a self transition to the current state.    
+    m_flags &= ~MASK_FLASH_API_ERR_BUSY;
+    sm_state_change(m_state);                    
+}
+
+
+/**@brief Function for doing erase state action upon flash operation success event.
+ *
+ * @details Function for doing erase state action upon flash operation success event, which includes 
+ *          making a state transition depending on the current state.
+ */
+static void erase_sub_state_sm_run(void)
+{
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {        
+        // Clear operation request has succeeded.
+        ++m_current_page_id;                        
+                
+        if (!is_page_erase_required())
+        {
+            clear_post_processing_run();
+        }
+        else
+        {   
+            // All required flash pages have not yet been erased, issue erase by doing a self 
+            // transit. 
+            sm_state_change(m_state);        
+        }                              
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        main_state_err_busy_process();
+    }
+}
+
+
+/**@brief Function for doing store state action upon flash operation success event.
+ */
+static void store_sub_state_sm_run(void)
+{
+    if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+    {        
+        // As write operation request has succeeded, adjust the size tracking state information 
+        // accordingly.
+        cmd_queue_element_t * p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp];    
+        p_cmd->size                -= m_num_of_bytes_written;
+
+        if (p_cmd->size == 0)
+        {
+            command_end_procedure_run();
+        }
+        else
+        {
+            store_cmd_flash_write_execute();
+        }
+    }
+    else
+    {
+        // As operation request was rejected by the flash API reissue the request.
+        main_state_err_busy_process();
+    }
+}
+
+
+/**@brief Function for doing action upon flash operation success event.
+ */
+static void flash_operation_success_run(void)
+{    
+    switch (m_state)
+    {                   
+        case STATE_STORE:
+            store_sub_state_sm_run();
+            break;
+                        
+        case STATE_DATA_ERASE:
+            erase_sub_state_sm_run();
+            break;
+                        
+        case STATE_DATA_ERASE_WITH_SWAP:
+            swap_sub_state_sm_run();                        
+            break;                        
+            
+        default:
+            // No implementation needed.
+            break;
+    }                    
+}
+
+
+/**@brief Function for doing action upon flash operation failure event.
+ *
+ * @details Function for doing action upon flash operation failure event, which includes retrying 
+ *          the last operation or if retry count has been reached completing the operation with 
+ *          appropriate result code and transitioning to an error state.
+ *
+ * @note    The command is not removed from the command queue, which will result to stalling of the 
+ *          command pipeline and the appropriate application recovery procedure for this is to reset 
+ *          the system by issuing @ref pstorage_init which will also result to flushing of the 
+ *          command queue.
+ */
+static void flash_operation_failure_run(void)
+{   
+    if (++m_num_of_command_retries != SD_CMD_MAX_TRIES)
+    {
+        // Retry the last operation by doing a self transition to the current state.
+            
+        if (m_state != STATE_DATA_ERASE_WITH_SWAP)
+        {
+            sm_state_change(m_state);        
+        }
+        else
+        {
+            swap_sub_state_state_change(m_swap_sub_state);
+        }
+    }
+    else
+    {
+        // Complete the operation with appropriate result code and transit to an error state.     
+        app_notify_error_state_transit(NRF_ERROR_TIMEOUT);        
+    }   
+}
+
+
+/**@brief Function for handling flash access result events.
+ *
+ * @param[in] sys_evt System event to be handled.
+ */
+void pstorage_sys_event_handler(uint32_t sys_evt)
+{  
+    if (m_state != STATE_IDLE && m_state != STATE_ERROR)
+    {        
+        switch (sys_evt)
+        {
+            case NRF_EVT_FLASH_OPERATION_SUCCESS:
+                flash_operation_success_run();
+                break;
+            
+            case NRF_EVT_FLASH_OPERATION_ERROR:            
+                if (!(m_flags & MASK_FLASH_API_ERR_BUSY))
+                {
+                    flash_operation_failure_run();
+                }
+                else
+                {
+                    // As our last flash operation request was rejected by the flash API reissue the 
+                    // request by doing same code execution path as for flash operation sucess 
+                    // event. This will promote code reuse in the implementation.                    
+                    flash_operation_success_run();
+                }                
+                break;
+                
+            default:
+                // No implementation needed.
+                break;
+        }
+
+    }
+}
+
+
+/**@brief Function for calculating the tail area size in number of 32-bit words.
+ *
+ * @param[in] cmd_end_of_storage_address End of storage area within the scope of the command.
+ * @param[in] end_of_storage_address     End of allocated storage area for the application.
+ */
+static void tail_word_size_calculate(pstorage_size_t cmd_end_of_storage_address, 
+                                     pstorage_size_t end_of_storage_address)
+{ 
+    // Two different cases to resolve when calculating correct size for restore tail section:
+    // 1) End of storage area and command end area are in the same page.
+    // 2) End of storage area and command end area are not in the same page.
+    
+    const uint32_t end_of_storage_area_page         = end_of_storage_address     / 
+                                                      PSTORAGE_FLASH_PAGE_SIZE;
+    const uint32_t command_end_of_storage_area_page = cmd_end_of_storage_address / 
+                                                      PSTORAGE_FLASH_PAGE_SIZE;
+
+    if (end_of_storage_area_page == command_end_of_storage_area_page)
+    {
+        //lint -e{573} suppress "Signed-unsigned mix with divide".
+        m_tail_word_size = (end_of_storage_address - cmd_end_of_storage_address) / sizeof(uint32_t);                                           
+    }
+    else
+    {
+        //lint -e{573} suppress "Signed-unsigned mix with divide".    
+        m_tail_word_size = (PSTORAGE_FLASH_PAGE_SIZE - 
+                           (cmd_end_of_storage_address % PSTORAGE_FLASH_PAGE_SIZE)) / 
+                           sizeof(uint32_t);               
+    }            
+}
+
+
+/**@brief Function for executing the clear operation.
+ */
+static void clear_operation_execute(void)
+{    
+    const cmd_queue_element_t * p_cmd        = &m_cmd_queue.cmd[m_cmd_queue.rp];
+    const pstorage_block_t      cmd_block_id = p_cmd->storage_addr.block_id;
+
+    const pstorage_size_t  block_size    = m_app_table[p_cmd->storage_addr.module_id].block_size;
+    const pstorage_size_t  block_count   = m_app_table[p_cmd->storage_addr.module_id].block_count;
+    const pstorage_block_t block_base_id = m_app_table[p_cmd->storage_addr.module_id].base_id;  
+      
+    const bool is_start_address_page_aligned = (cmd_block_id % PSTORAGE_FLASH_PAGE_SIZE) == 0;
+    
+    // Calculate the end (1 beyond allocated area) for complete storage area and to the area only 
+    // within scope of this command.
+    const pstorage_block_t end_of_storage_address     = block_base_id + (block_size * block_count); 
+    const pstorage_block_t cmd_end_of_storage_address = cmd_block_id + p_cmd->size + p_cmd->offset;
+
+    // Zero tail to make sure no extra erase is done erroneously.
+    m_tail_word_size = 0;        
+        
+    // If the following is true no swap access is needed:
+    // - 1st logical test covers the case of: clear/update 1 complete single page.
+    // - 2nd logical test covers the case of: 
+    //   1) Clear/update last allocated page and page is not full (page can't be shared between 
+    //      multiple clients so the end of the page is unused area).
+    //   2) Clear/update all allocated storage.
+    if ((is_start_address_page_aligned && (p_cmd->size == PSTORAGE_FLASH_PAGE_SIZE)) ||
+        (is_start_address_page_aligned && (cmd_end_of_storage_address == end_of_storage_address) && 
+        (p_cmd->offset == 0)) || (p_cmd->storage_addr.module_id == RAW_MODE_APP_ID)) 
+    {
+        // Nothing to put to the swap and we can just erase the pages(s).         
+        
+        m_current_page_id = cmd_block_id / PSTORAGE_FLASH_PAGE_SIZE;
+        
+        sm_state_change(STATE_DATA_ERASE);                        
+    }
+    else
+    {
+        // Not all the blocks for the module can be cleared, we need to use swap page for storing 
+        // data temporarily.                        
+        
+        m_head_word_size = ((cmd_block_id + p_cmd->offset) % PSTORAGE_FLASH_PAGE_SIZE) / 
+                           sizeof(uint32_t);
+        
+        const bool is_cmd_end_address_page_aligned = ((cmd_end_of_storage_address % 
+                                                      PSTORAGE_FLASH_PAGE_SIZE) == 0);
+        if ((cmd_end_of_storage_address != end_of_storage_address) && 
+            !is_cmd_end_address_page_aligned)
+        {
+            // When command area is not equal to end of the storage allocation area and not ending 
+            // to page boundary there is a need to restore the tail area.
+            tail_word_size_calculate(cmd_end_of_storage_address, end_of_storage_address);
+        }
+
+        sm_state_change(STATE_DATA_ERASE_WITH_SWAP);         
+    }        
+}
+
+
+/**@brief Function for executing the store operation.
+ */
+static void store_operation_execute(void)
+{    
+    sm_state_change(STATE_STORE);
+}
+ 
+
+/**@brief Function for executing the update operation.
+ */ 
+static void update_operation_execute(void)
+{
+    clear_operation_execute();
+}
+
+
+/**@brief Function for dispatching the flash access operation.
+ */  
+static void cmd_process(void)
+{
+    const cmd_queue_element_t * p_cmd = &m_cmd_queue.cmd[m_cmd_queue.rp];
+    m_app_data_size                   = p_cmd->size;
+
+    switch (p_cmd->op_code)
+    {
+        case PSTORAGE_STORE_OP_CODE:                   
+            store_operation_execute();       
+            break;
+
+        case PSTORAGE_CLEAR_OP_CODE:
+            clear_operation_execute();
+            break;
+
+        case PSTORAGE_UPDATE_OP_CODE:
+            update_operation_execute();
+            break;
+
+        default:
+            // No action required.
+            break;
+    }
+}
+
+
+uint32_t pstorage_init(void)
+{
+    cmd_queue_init();
+
+    m_next_app_instance = 0;
+    m_next_page_addr    = PSTORAGE_DATA_START_ADDR;
+    m_current_page_id   = 0;
+    
+    for (uint32_t index = 0; index < PSTORAGE_NUM_OF_PAGES; index++)
+    {
+        m_app_table[index].cb           = NULL;
+        m_app_table[index].block_size   = 0;
+        m_app_table[index].block_count  = 0;
+    }
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+    m_raw_app_table.cb           = NULL;
+#endif //PSTORAGE_RAW_MODE_ENABLE
+
+    m_state                     = STATE_IDLE;
+    m_num_of_command_retries    = 0;
+    m_flags                     = 0;
+    m_num_of_bytes_written      = 0;
+    m_flags                    |= MASK_MODULE_INITIALIZED;
+       
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
+                           pstorage_handle_t       * p_block_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_module_param);
+    NULL_PARAM_CHECK(p_block_id);
+    NULL_PARAM_CHECK(p_module_param->cb);
+    BLOCK_SIZE_CHECK(p_module_param->block_size);    
+    BLOCK_COUNT_CHECK(p_module_param->block_count, p_module_param->block_size);
+
+    if (!((p_module_param->block_size % sizeof(uint32_t)) == 0))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    
+    if (m_next_app_instance == PSTORAGE_NUM_OF_PAGES)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    p_block_id->module_id = m_next_app_instance;
+    p_block_id->block_id  = m_next_page_addr;
+
+    m_app_table[m_next_app_instance].base_id     = p_block_id->block_id;
+    m_app_table[m_next_app_instance].cb          = p_module_param->cb;
+    m_app_table[m_next_app_instance].block_size  = p_module_param->block_size;
+    m_app_table[m_next_app_instance].block_count = p_module_param->block_count;
+
+    // Calculate number of flash pages allocated for the device and adjust next free page address.
+    /*lint -save -e666 */
+    const uint32_t page_count = CEIL_DIV((p_module_param->block_size * p_module_param->block_count), 
+                                         PSTORAGE_FLASH_PAGE_SIZE);
+    /*lint -restore */
+    m_next_page_addr         += page_count * PSTORAGE_FLASH_PAGE_SIZE;
+    
+    ++m_next_app_instance;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
+                                       pstorage_size_t     block_num,
+                                       pstorage_handle_t * p_block_id)
+{
+    pstorage_handle_t temp_id;
+
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_base_id);
+    NULL_PARAM_CHECK(p_block_id);
+    MODULE_ID_RANGE_CHECK(p_base_id);
+
+    temp_id           = (*p_base_id);
+    temp_id.block_id += (block_num * MODULE_BLOCK_SIZE(p_base_id));
+
+    BLOCK_ID_RANGE_CHECK(&temp_id);
+
+    (*p_block_id) = temp_id;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pstorage_store(pstorage_handle_t * p_dest,
+                        uint8_t           * p_src,
+                        pstorage_size_t     size,
+                        pstorage_size_t     offset)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_src);
+    NULL_PARAM_CHECK(p_dest);
+    MODULE_ID_RANGE_CHECK(p_dest);
+    BLOCK_ID_RANGE_CHECK(p_dest);
+    SIZE_CHECK(p_dest, size);    
+    OFFSET_CHECK(p_dest, offset, size);
+    
+    if ((!is_word_aligned(p_src))                    || 
+        (!is_word_aligned((void *)(uint32_t)offset)) || 
+        (!is_word_aligned((uint32_t *)p_dest->block_id)))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+
+    return cmd_queue_enqueue(PSTORAGE_STORE_OP_CODE, p_dest, p_src, size, offset);
+}
+
+
+uint32_t pstorage_update(pstorage_handle_t * p_dest,
+                         uint8_t           * p_src,
+                         pstorage_size_t     size,
+                         pstorage_size_t     offset)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_src);
+    NULL_PARAM_CHECK(p_dest);
+    MODULE_ID_RANGE_CHECK(p_dest);
+    BLOCK_ID_RANGE_CHECK(p_dest);
+    SIZE_CHECK(p_dest, size);
+    OFFSET_CHECK(p_dest, offset, size);
+
+    if ((!is_word_aligned(p_src))                    || 
+        (!is_word_aligned((void *)(uint32_t)offset)) || 
+        (!is_word_aligned((uint32_t *)p_dest->block_id)))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+
+    return cmd_queue_enqueue(PSTORAGE_UPDATE_OP_CODE, p_dest, p_src, size, offset);
+}
+
+
+uint32_t pstorage_load(uint8_t           * p_dest,
+                       pstorage_handle_t * p_src,
+                       pstorage_size_t     size,
+                       pstorage_size_t     offset)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_src);
+    NULL_PARAM_CHECK(p_dest);
+    MODULE_ID_RANGE_CHECK(p_src);
+    BLOCK_ID_RANGE_CHECK(p_src);
+    SIZE_CHECK(p_src, size);
+    OFFSET_CHECK(p_src, offset, size);
+
+    if ((!is_word_aligned(p_dest))                   || 
+        (!is_word_aligned((void *)(uint32_t)offset)) || 
+        (!is_word_aligned((uint32_t *)p_src->block_id)))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+
+    memcpy(p_dest, (((uint8_t *)p_src->block_id) + offset), size);
+
+    m_app_table[p_src->module_id].cb(p_src, PSTORAGE_LOAD_OP_CODE, NRF_SUCCESS, p_dest, size);
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pstorage_clear(pstorage_handle_t * p_dest, pstorage_size_t size)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_dest);
+    MODULE_ID_RANGE_CHECK(p_dest);
+    BLOCK_ID_RANGE_CHECK(p_dest);
+
+    if ((!is_word_aligned((uint32_t *)p_dest->block_id)))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+
+    // Check is the area starting from block_id multiple of block_size.
+    if (
+        !(
+            ((p_dest->block_id - m_app_table[p_dest->module_id].base_id) %
+             m_app_table[p_dest->module_id].block_size) == 0
+            )
+        )
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check is requested size multiple of registered block size or 0.
+    if (((size % m_app_table[p_dest->module_id].block_size) != 0) || (size == 0))    
+    {        
+        return NRF_ERROR_INVALID_PARAM;        
+    }
+
+    const uint32_t registered_allocation_size = m_app_table[p_dest->module_id].block_size * 
+                                                m_app_table[p_dest->module_id].block_count;
+    
+    const pstorage_block_t clear_request_end_address = p_dest->block_id + size;
+    const pstorage_block_t allocation_end_address    = m_app_table[p_dest->module_id].base_id + 
+                                                       registered_allocation_size;
+    // Check if request would lead to a buffer overrun.                                                       
+    if (clear_request_end_address > allocation_end_address)
+    {        
+        return NRF_ERROR_INVALID_PARAM;            
+    }
+    
+    return cmd_queue_enqueue(PSTORAGE_CLEAR_OP_CODE, p_dest, NULL, size, 0);
+}
+
+
+uint32_t pstorage_access_status_get(uint32_t * p_count)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_count);
+
+    (*p_count) = m_cmd_queue.count;
+
+    return NRF_SUCCESS;
+}
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
+                               pstorage_handle_t       * p_block_id)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_module_param);
+    NULL_PARAM_CHECK(p_block_id);
+    NULL_PARAM_CHECK(p_module_param->cb);
+
+    if (m_raw_app_table.cb != NULL)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+    p_block_id->module_id = RAW_MODE_APP_ID;
+    m_raw_app_table.cb    = p_module_param->cb;
+
+    return NRF_SUCCESS;
+}
+
+
+uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
+                            uint8_t           * p_src,
+                            pstorage_size_t     size,
+                            pstorage_size_t     offset)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_src);
+    NULL_PARAM_CHECK(p_dest);
+    MODULE_RAW_HANDLE_CHECK(p_dest);
+    
+    if (size == 0)
+    {
+        return NRF_ERROR_INVALID_PARAM;        
+    }
+    
+    // Verify word alignment.
+    if ((!is_word_aligned(p_src))                    || 
+        (!is_word_aligned((void *)(uint32_t)size))   ||     
+        (!is_word_aligned((void *)(uint32_t)offset)) || 
+        (!is_word_aligned((void *)(p_dest->block_id))))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+       
+    return cmd_queue_enqueue(PSTORAGE_STORE_OP_CODE, p_dest, p_src, size, offset);
+}
+
+
+uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size)
+{
+    VERIFY_MODULE_INITIALIZED();
+    NULL_PARAM_CHECK(p_dest);
+    MODULE_RAW_HANDLE_CHECK(p_dest);
+    
+    if ((!is_word_aligned((uint32_t *)p_dest->block_id)))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }    
+
+    return cmd_queue_enqueue(PSTORAGE_CLEAR_OP_CODE, p_dest, NULL, size, 0);
+}
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.h
new file mode 100644
index 0000000000..0a5884cd52
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/pstorage/pstorage.h
@@ -0,0 +1,408 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup persistent_storage Persistent Storage Interface
+ * @{
+ * @ingroup app_common
+ * @brief Abstracted flash interface.
+ *
+ * @details  An abstracted interface is provided by the module to easily port the application and 
+ *           SDK modules to an alternate option. This ensures that the SDK and application are moved 
+ *           to alternate persistent storage instead of the one provided by default.
+ */
+
+#ifndef PSTORAGE_H__
+#define PSTORAGE_H__
+
+#include "pstorage_platform.h"
+
+
+/**@defgroup ps_opcode Persistent Storage Access Operation Codes
+ * @{
+ * @brief    Persistent Storage Access Operation Codes. 
+ *
+ * @details  Persistent Storage Access Operation Codes are used by Persistent storage operation 
+ *           completion callback @ref pstorage_ntf_cb_t to identify the operation type requested by 
+ *           the application.
+ */
+#define PSTORAGE_STORE_OP_CODE    0x01  /**< Store Operation type. */
+#define PSTORAGE_LOAD_OP_CODE     0x02  /**< Load Operation type. */
+#define PSTORAGE_CLEAR_OP_CODE    0x03  /**< Clear Operation type. */
+#define PSTORAGE_UPDATE_OP_CODE   0x04  /**< Update Operation type. */
+
+/**@} */
+
+/**@defgroup pstorage_data_types Persistent Memory Interface Data Types
+ * @{
+ * @brief Data Types needed for interfacing with persistent memory.
+ *
+ * @details Data Types needed for interfacing with persistent memory.
+ */
+
+/**@brief Persistent storage operation completion callback function type.
+ *
+ * @details The persistent storage operation completion callback is used by the interface to report
+ *          success or failure of a flash operation. Since data is not copied for a store operation, 
+ *          a callback is an indication that the resident memory can now be reused or freed.
+ * 
+ * @param[in] handle   Identifies the module and block for the callback that is received.
+ * @param[in] op_code  Identifies the operation for the event that is notified.
+ * @param[in] result   Identifies the result of a flash access operation. NRF_SUCCESS implies 
+ *                     operation succeeded.
+ *
+ *                     @note Unmanaged (abnormal behaviour) error codes from the SoftDevice flash 
+ *                     access API are forwarded as is and are expected to be handled by the 
+ *                     application. For details refer to the implementation file and corresponding 
+ *                     SoftDevice flash API documentation.
+ *                     
+ * @param[in] p_data   Identifies the application data pointer. For a store operation, this points 
+ *                     to the resident source of application memory that the application can now 
+ *                     free or reuse. When there is a clear operation, this is NULL since no 
+ *                     application pointer is needed for this operation.
+ * @param[in] data_len Length data the application provided for the operation. 
+ */
+typedef void (*pstorage_ntf_cb_t)(pstorage_handle_t * p_handle,
+                                  uint8_t             op_code,
+                                  uint32_t            result,
+                                  uint8_t *           p_data,
+                                  uint32_t            data_len);
+
+/**@brief Struct containing module registration context. */
+typedef struct
+{
+    pstorage_ntf_cb_t cb;             /**< Persistent storage operation completion callback function @ref pstorage_ntf_cb_t.  */
+    pstorage_size_t   block_size;     /**< Desired block size for persistent memory storage. For example, if a module has a table with 10 entries, and each entry is 64 bytes in size,
+                                       *   it can request 10 blocks with a block size of 64 bytes. The module can also request one block that is 640 bytes depending 
+                                       *   on how it would like to access or alter the memory in persistent memory.
+                                       *   The first option is preferred when it is a single entry that needs to be updated often and doesn't impact the other entries.
+                                       *   The second option is preferred when table entries are not changed individually but have a common point of loading and storing
+                                       *   data. */
+    pstorage_size_t   block_count;    /** Number of blocks requested by the module; minimum values is 1. */
+} pstorage_module_param_t;
+
+/**@} */
+
+/**@defgroup pstorage_routines Persistent Storage Access Routines
+ * @{
+ * @brief Functions/Interface SDK modules used to persistently store data.
+ *
+ * @details Interface for the Application and SDK modules to load/store information persistently.
+ *          Note: While implementation of each of the persistent storage access functions
+ *          depends on the system and is specific to system/solution, the signature of the
+ *          interface routines should not be altered.
+ */
+
+/**@brief Function for initializing the module.
+ *
+ * @details Function for initializing the module. This function is called once before any other APIs 
+ *          of the module are used.
+ *
+ * @retval     NRF_SUCCESS             Operation success.
+ */
+uint32_t pstorage_init(void);
+
+/**@brief Function for registering with persistent storage interface.
+ *
+ * @param[in]  p_module_param Module registration parameter.
+ * @param[out] p_block_id     Block identifier to identify persistent memory blocks when 
+ *                            registration succeeds. Application is expected to use the block IDs 
+ *                            for subsequent operations on requested persistent memory. Maximum 
+ *                            registrations permitted is determined by the configuration of the 
+ *                            parameter PSTORAGE_NUM_OF_PAGES. If more than one memory block is 
+ *                            requested, the identifier provided here is the base identifier for the 
+ *                            first block and used to identify the subsequent block. The application 
+ *                            uses \@ref pstorage_block_identifier_get with this base identifier and 
+ *                            block number. Therefore if 10 blocks of size 64 are requested and the 
+ *                            application wishes to store memory in the 6th block, it shall use
+ *                            \@ref pstorage_block_identifier_get with the base ID and provide a 
+ *                            block number of 5. This way the application is only expected to 
+ *                            remember the base block identifier.
+ *
+ * @retval     NRF_SUCCESS             Operation success.
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. Additional registrations can't be 
+ *                                     supported.
+ */
+uint32_t pstorage_register(pstorage_module_param_t * p_module_param,
+                           pstorage_handle_t *       p_block_id);
+
+/**@brief Function for getting block ID with reference to base block identifier provided at the time 
+ *        of registration.
+ *
+ * @details Function to get the block ID with reference to base block identifier provided at the 
+ *          time of registration.
+ *          If more than one memory block was requested when registering, the identifier provided 
+ *          here is the base identifier for the first block which is used to identify subsequent
+ *          blocks. The application shall use this routine to get the block identifier, providing 
+ *          input as base identifier and block number. Therefore, if 10 blocks of size 64 are 
+ *          requested and the application wishes to store memory in the 6th block, it shall use
+ *          \@ref pstorage_block_identifier_get with the base ID and provide a block number of 5.
+ *          This way the application is only expected to remember the base block identifier.
+ *
+ * @param[in]  p_base_id  Base block ID received at the time of registration.
+ * @param[in]  block_num  Block Number, with first block numbered zero.
+ * @param[out] p_block_id Block identifier for the block number requested when the API succeeds.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ */
+uint32_t pstorage_block_identifier_get(pstorage_handle_t * p_base_id,
+                                       pstorage_size_t     block_num,
+                                       pstorage_handle_t * p_block_id);
+
+/**@brief Function for persistently storing data of length 'size' contained in the 'p_src' address
+ *        in the storage module at 'p_dest' address. Equivalent to Storage Write.
+ *
+ * @param[in]  p_dest Destination address where data is to be stored persistently.
+ * @param[in]  p_src  Source address containing data to be stored. API assumes this to be resident
+ *                    memory and no intermediate copy of data is made by the API. Must be word 
+ *                    aligned.
+ * @param[in]  size   Size of data to be stored expressed in bytes. Must be word aligned and size + 
+ *                    offset must be <= block size.                      
+ * @param[in]  offset Offset in bytes to be applied when writing to the block.
+ *                    For example, if within a block of 100 bytes, the application wishes to
+ *                    write 20 bytes at an offset of 12, then this field should be set to 12.
+ *                    Must be word aligned.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_ADDR  Operation failure. Parameter is not aligned.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ *
+ * @warning    No copy of the data is made, meaning memory provided for the data source that is to 
+ *             be written to flash cannot be freed or reused by the application until this procedure
+ *             is complete. The application is notified when the procedure is finished using the
+ *             notification callback registered by the application.
+ */
+uint32_t pstorage_store(pstorage_handle_t * p_dest,
+                        uint8_t *           p_src,
+                        pstorage_size_t     size,
+                        pstorage_size_t     offset);
+
+/**@brief Function for updating persistently stored data of length 'size' contained in the 'p_src' 
+ *        address in the storage module at 'p_dest' address.
+ *
+ * @param[in]  p_dest Destination address where data is to be updated.
+ * @param[in]  p_src  Source address containing data to be stored. API assumes this to be resident
+ *                    memory and no intermediate copy of data is made by the API.
+ * @param[in]  size   Size of data to be stored expressed in bytes. Must be word aligned and size + 
+ *                    offset must be <= block size.
+ * @param[in]  offset Offset in bytes to be applied when writing to the block.
+ *                    For example, if within a block of 100 bytes, the application wishes to
+ *                    write 20 bytes at an offset of 12 bytes, then this field should be set to 12.
+ *                    Must be word aligned.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_ADDR  Operation failure. Parameter is not aligned.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ *
+ * @warning    No copy of the data is made, meaning memory provided for the data source that is to 
+ *             be written to flash cannot be freed or reused by the application until this procedure
+ *             is complete. The application is notified when the procedure is finished using the
+ *             notification callback registered by the application.
+ */
+uint32_t pstorage_update(pstorage_handle_t * p_dest,
+                         uint8_t *           p_src,
+                         pstorage_size_t     size,
+                         pstorage_size_t     offset);
+
+/**@brief Function for loading persistently stored data of length 'size' from 'p_src' address
+ *        to 'p_dest' address. Equivalent to Storage Read.
+ *
+ * @param[in]  p_dest Destination address where persistently stored data is to be loaded.
+ * @param[in]  p_src  Source where data is loaded from persistent memory.
+ * @param[in]  size   Size of data to be loaded from persistent memory expressed in bytes.
+ *                    Should be word aligned.
+ * @param[in]  offset Offset in bytes, to be applied when loading from the block.
+ *                    For example, if within a block of 100 bytes, the application wishes to
+ *                    load 20 bytes from offset of 12 bytes, then this field should be set to 12.
+ *                    Should be word aligned.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_ADDR  Operation failure. Parameter is not aligned.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ */
+uint32_t pstorage_load(uint8_t *           p_dest,
+                       pstorage_handle_t * p_src,
+                       pstorage_size_t     size,
+                       pstorage_size_t     offset);
+
+/**@brief Function for clearing data in persistent memory.
+ *
+ * @param[in]  p_base_id Base block identifier in persistent memory that needs to be cleared;
+ *                       equivalent to an Erase Operation.
+ * @param[in]  size      Size of data to be cleared from persistent memory expressed in bytes.
+ *                       This parameter is to provision for clearing of certain blocks
+ *                       of memory, or all memory blocks in a registered module. If the total size 
+ *                       of the application module is used (blocks * block size) in combination with
+ *                       the identifier for the first block in the module, all blocks in the 
+ *                       module will be erased. Must be multiple of block size.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_ADDR  Operation failure. Parameter is not aligned.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ *
+ * @note       Clear operations may take time. This API however, does not block until the clear
+ *             procedure is complete. The application is notified of procedure completion using
+ *             a notification callback registered by the application. The 'result' parameter of the
+ *             callback indicates if the procedure was successful or not.
+ */
+uint32_t pstorage_clear(pstorage_handle_t * p_base_id, pstorage_size_t size);
+
+/**@brief Function for getting the number of pending operations with the module.
+ *
+ * @param[out] p_count Number of storage operations pending with the module. If 0, there are no 
+ *                     outstanding requests.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ */
+uint32_t pstorage_access_status_get(uint32_t * p_count);
+
+#ifdef PSTORAGE_RAW_MODE_ENABLE
+
+/**@brief Function for registering with the persistent storage interface.
+ *
+ * @param[in]  p_module_param Module registration parameter.
+ * @param[out] p_block_id     Block identifier used to identify persistent memory blocks upon 
+ *                            successful registration. The application is expected to use the block 
+ *                            IDs for subsequent operations on requested persistent memory. When 
+ *                            more than one memory block is requested, this identifier is the base 
+ *                            identifier for the first block and used to identify subsequent blocks. 
+ *                            The application shall use \@ref pstorage_block_identifier_get with 
+ *                            this base identifier and block number. Therefore if 10 blocks of size 
+ *                            64 are requested and the application wishes to store memory in the 6th 
+ *                            block, it shall use \@ref pstorage_block_identifier_get with the base 
+ *                            ID and provide a block number of 5. Therefore, the application is only 
+ *                            expected to remember the base block identifier.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ */
+uint32_t pstorage_raw_register(pstorage_module_param_t * p_module_param,
+                               pstorage_handle_t *       p_block_id);
+
+/**@brief Function for persistently storing data of length 'size' contained in 'p_src' address in 
+ *        storage module at 'p_dest' address. Equivalent to Storage Write.
+ *
+ * @param[in]  p_dest Destination address where data is to be stored persistently.
+ * @param[in]  p_src  Source address containing data to be stored. The API assumes this is resident
+ *                    memory and no intermediate copy of data is made by the API. Must be word 
+ *                    aligned.
+ * @param[in]  size   Size of data to be stored expressed in bytes. Must be word aligned.
+ * @param[in]  offset Offset in bytes to be applied when writing to the block.
+ *                    For example, if within a block of 100 bytes, the application wishes to
+ *                    write 20 bytes at an offset of 12 bytes, this field should be set to 12.
+ *                    Must be word aligned.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_ADDR  Operation failure. Parameter is not aligned.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ *
+ * @warning    No copy of the data is made, meaning memory provided for data source that is to be 
+ *             written to flash cannot be freed or reused by the application until this procedure
+ *             is complete. The application is notified when the procedure is finished using the
+ *             notification callback registered by the application.
+ */
+uint32_t pstorage_raw_store(pstorage_handle_t * p_dest,
+                            uint8_t *           p_src,
+                            pstorage_size_t     size,
+                            pstorage_size_t     offset);
+
+/**@brief Function for clearing data in persistent memory in raw mode.
+ *
+ * @param[in]  p_dest Base block identifier in persistent memory that needs to be cleared.
+ *                    Equivalent to an Erase Operation.
+ * @param[in]  size   Size of data to be cleared from persistent memory expressed in bytes. 
+ *                    Not used.
+ *
+ * @retval     NRF_SUCCESS             Operation success. 
+ * @retval     NRF_ERROR_INVALID_STATE Operation failure. API is called without module 
+ *                                     initialization.
+ * @retval     NRF_ERROR_NULL          Operation failure. NULL parameter has been passed.
+ * @retval     NRF_ERROR_INVALID_PARAM Operation failure. Invalid parameter has been passed.
+ * @retval     NRF_ERROR_NO_MEM        Operation failure. No storage space available.
+ *
+ * @note       Clear operations may take time. This API, however, does not block until the clear
+ *             procedure is complete. The application is notified of procedure completion using
+ *             a notification callback registered by the application. The 'result' parameter of the
+ *             callback indicates if the procedure was successful or not.
+ */
+uint32_t pstorage_raw_clear(pstorage_handle_t * p_dest, pstorage_size_t size);
+
+#endif // PSTORAGE_RAW_MODE_ENABLE
+
+/**@} */
+/**@} */
+
+#endif // PSTORAGE_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.c
new file mode 100644
index 0000000000..de1f287232
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.c
@@ -0,0 +1,715 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_spi.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+
+
+#ifndef NRF52
+    // Make sure SPIx_USE_EASY_DMA is 0 for nRF51 (if a common
+    // "nrf_drv_config.h" file is provided for nRF51 and nRF52).
+    #undef  SPI0_USE_EASY_DMA
+    #define SPI0_USE_EASY_DMA 0
+    #undef  SPI1_USE_EASY_DMA
+    #define SPI1_USE_EASY_DMA 0
+    #undef  SPI2_USE_EASY_DMA
+    #define SPI2_USE_EASY_DMA 0
+#endif
+
+// This set of macros makes it possible to exclude parts of code when one type
+// of supported peripherals is not used.
+#if ((SPI0_ENABLED && SPI0_USE_EASY_DMA) || \
+     (SPI1_ENABLED && SPI1_USE_EASY_DMA) || \
+     (SPI2_ENABLED && SPI2_USE_EASY_DMA))
+    #define SPIM_IN_USE
+#endif
+#if ((SPI0_ENABLED && !SPI0_USE_EASY_DMA) || \
+     (SPI1_ENABLED && !SPI1_USE_EASY_DMA) || \
+     (SPI2_ENABLED && !SPI2_USE_EASY_DMA))
+    #define SPI_IN_USE
+#endif
+#if defined(SPIM_IN_USE) && defined(SPI_IN_USE)
+    // SPIM and SPI combined
+    #define CODE_FOR_SPIM(code) if (p_instance->use_easy_dma) { code }
+    #define CODE_FOR_SPI(code)  else { code }
+#elif defined(SPIM_IN_USE) && !defined(SPI_IN_USE)
+    // SPIM only
+    #define CODE_FOR_SPIM(code) { code }
+    #define CODE_FOR_SPI(code)
+#elif !defined(SPIM_IN_USE) && defined(SPI_IN_USE)
+    // SPI only
+    #define CODE_FOR_SPIM(code)
+    #define CODE_FOR_SPI(code)  { code }
+#else
+    #error "Wrong configuration."
+#endif
+
+#ifdef SPIM_IN_USE
+#ifdef NRF52_PAN_23
+#define END_INT_MASK     (NRF_SPIM_INT_ENDTX_MASK | NRF_SPIM_INT_ENDRX_MASK)
+#else
+#define END_INT_MASK     NRF_SPIM_INT_END_MASK
+#endif
+#endif
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_spi_handler_t handler;
+    nrf_drv_spi_evt_t     evt;  // Keep the struct that is ready for event handler. Less memcpy.
+    nrf_drv_state_t       state;
+    volatile bool         transfer_in_progress;
+
+    // [no need for 'volatile' attribute for the following members, as they
+    //  are not concurrently used in IRQ handlers and main line code]
+    uint8_t         ss_pin;
+    uint8_t         orc;
+    uint8_t         bytes_transferred;
+
+    bool tx_done : 1;
+    bool rx_done : 1;
+    bool abort   : 1;
+} spi_control_block_t;
+static spi_control_block_t m_cb[SPI_COUNT];
+
+static nrf_drv_spi_config_t const m_default_config[SPI_COUNT] = {
+#if SPI0_ENABLED
+    NRF_DRV_SPI_DEFAULT_CONFIG(0),
+#endif
+#if SPI1_ENABLED
+    NRF_DRV_SPI_DEFAULT_CONFIG(1),
+#endif
+#if SPI2_ENABLED
+    NRF_DRV_SPI_DEFAULT_CONFIG(2),
+#endif
+};
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if SPI0_ENABLED
+        IRQ_HANDLER(0);
+    #endif
+    #if SPI1_ENABLED
+        IRQ_HANDLER(1);
+    #endif
+    #if SPI2_ENABLED
+        IRQ_HANDLER(2);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[SPI_COUNT] = {
+    #if SPI0_ENABLED
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if SPI1_ENABLED
+        IRQ_HANDLER_NAME(1),
+    #endif
+    #if SPI2_ENABLED
+        IRQ_HANDLER_NAME(2),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) void SPI##n##_IRQ_HANDLER(void)
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+
+ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance,
+                            nrf_drv_spi_config_t const * p_config,
+                            nrf_drv_spi_handler_t handler)
+{
+    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    if (nrf_drv_common_per_res_acquire(p_instance->p_registers,
+            m_irq_handlers[p_instance->drv_inst_idx]) != NRF_SUCCESS)
+    {
+        return NRF_ERROR_BUSY;
+    }
+#endif
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config[p_instance->drv_inst_idx];
+    }
+
+    p_cb->handler = handler;
+
+    uint32_t mosi_pin;
+    uint32_t miso_pin;
+    // Configure pins used by the peripheral:
+    // - SCK - output with initial value corresponding with the SPI mode used:
+    //   0 - for modes 0 and 1 (CPOL = 0), 1 - for modes 2 and 3 (CPOL = 1);
+    //   according to the reference manual guidelines this pin and its input
+    //   buffer must always be connected for the SPI to work.
+    if (p_config->mode <= NRF_DRV_SPI_MODE_1)
+    {
+        nrf_gpio_pin_clear(p_config->sck_pin);
+    }
+    else
+    {
+        nrf_gpio_pin_set(p_config->sck_pin);
+    }
+    NRF_GPIO->PIN_CNF[p_config->sck_pin] =
+        (GPIO_PIN_CNF_DIR_Output        << GPIO_PIN_CNF_DIR_Pos)
+      | (GPIO_PIN_CNF_INPUT_Connect     << GPIO_PIN_CNF_INPUT_Pos)
+      | (GPIO_PIN_CNF_PULL_Disabled     << GPIO_PIN_CNF_PULL_Pos)
+      | (GPIO_PIN_CNF_DRIVE_S0S1        << GPIO_PIN_CNF_DRIVE_Pos)
+      | (GPIO_PIN_CNF_SENSE_Disabled    << GPIO_PIN_CNF_SENSE_Pos);
+    // - MOSI (optional) - output with initial value 0,
+    if (p_config->mosi_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        mosi_pin = p_config->mosi_pin;
+        nrf_gpio_pin_clear(mosi_pin);
+        nrf_gpio_cfg_output(mosi_pin);
+    }
+    else
+    {
+        mosi_pin = NRF_SPI_PIN_NOT_CONNECTED;
+    }
+    // - MISO (optional) - input,
+    if (p_config->miso_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        miso_pin = p_config->miso_pin;
+        nrf_gpio_cfg_input(miso_pin, NRF_GPIO_PIN_NOPULL);
+    }
+    else
+    {
+        miso_pin = NRF_SPI_PIN_NOT_CONNECTED;
+    }
+    // - Slave Select (optional) - output with initial value 1 (inactive).
+    if (p_config->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        nrf_gpio_pin_set(p_config->ss_pin);
+        nrf_gpio_cfg_output(p_config->ss_pin);
+    }
+    m_cb[p_instance->drv_inst_idx].ss_pin = p_config->ss_pin;
+
+    CODE_FOR_SPIM
+    (
+        NRF_SPIM_Type * p_spim = (NRF_SPIM_Type * ) p_instance->p_registers;
+        nrf_spim_pins_set(p_spim, p_config->sck_pin, mosi_pin, miso_pin);
+        nrf_spim_frequency_set(p_spim,
+            (nrf_spim_frequency_t)p_config->frequency);
+        nrf_spim_configure(p_spim,
+            (nrf_spim_mode_t)p_config->mode,
+            (nrf_spim_bit_order_t)p_config->bit_order);
+
+        nrf_spim_orc_set(p_spim, p_config->orc);
+
+        if (p_cb->handler)
+        {
+            nrf_spim_int_enable(p_spim, END_INT_MASK | NRF_SPIM_INT_STOPPED_MASK);
+        }
+
+        nrf_spim_enable(p_spim);
+    )
+    CODE_FOR_SPI
+    (
+        NRF_SPI_Type * p_spi = (NRF_SPI_Type * ) p_instance->p_registers;
+        nrf_spi_pins_set(p_spi, p_config->sck_pin, mosi_pin, miso_pin);
+        nrf_spi_frequency_set(p_spi,
+            (nrf_spi_frequency_t)p_config->frequency);
+        nrf_spi_configure(p_spi,
+            (nrf_spi_mode_t)p_config->mode,
+            (nrf_spi_bit_order_t)p_config->bit_order);
+
+        m_cb[p_instance->drv_inst_idx].orc = p_config->orc;
+
+        if (p_cb->handler)
+        {
+            nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
+        }
+
+        nrf_spi_enable(p_spi);
+    )
+
+    if (p_cb->handler)
+    {
+        nrf_drv_common_irq_enable(p_instance->irq, p_config->irq_priority);
+    }
+
+    p_cb->transfer_in_progress = false;
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+void nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance)
+{
+    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    if (p_cb->handler)
+    {
+        nrf_drv_common_irq_disable(p_instance->irq);
+    }
+
+    #define DISABLE_ALL  0xFFFFFFFF
+
+    CODE_FOR_SPIM
+    (
+        NRF_SPIM_Type * p_spim = (NRF_SPIM_Type * ) p_instance->p_registers;
+        if (p_cb->handler)
+        {
+            nrf_spim_int_disable(p_spim, DISABLE_ALL);
+            if (p_cb->transfer_in_progress)
+            {
+                // Ensure that SPI is not performing any transfer.
+                nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
+                while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED)) {}
+                p_cb->transfer_in_progress = false;
+            }
+        }
+        nrf_spim_disable(p_spim);
+    )
+    CODE_FOR_SPI
+    (
+        NRF_SPI_Type * p_spi = (NRF_SPI_Type * ) p_instance->p_registers;
+        if (p_cb->handler)
+        {
+            nrf_spi_int_disable(p_spi, DISABLE_ALL);
+        }
+        nrf_spi_disable(p_spi);
+    )
+    #undef DISABLE_ALL
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    nrf_drv_common_per_res_release(p_instance->p_registers);
+#endif
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance,
+                                uint8_t const * p_tx_buffer,
+                                uint8_t         tx_buffer_length,
+                                uint8_t       * p_rx_buffer,
+                                uint8_t         rx_buffer_length)
+{
+    nrf_drv_spi_xfer_desc_t xfer_desc;
+    xfer_desc.p_tx_buffer = p_tx_buffer;
+    xfer_desc.p_rx_buffer = p_rx_buffer;
+    xfer_desc.tx_length   = tx_buffer_length;
+    xfer_desc.rx_length   = rx_buffer_length;
+
+    return nrf_drv_spi_xfer(p_instance, &xfer_desc, 0);
+}
+
+static void finish_transfer(spi_control_block_t * p_cb)
+{
+    // If Slave Select signal is used, this is the time to deactivate it.
+    if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        nrf_gpio_pin_set(p_cb->ss_pin);
+    }
+
+    // By clearing this flag before calling the handler we allow subsequent
+    // transfers to be started directly from the handler function.
+    p_cb->transfer_in_progress = false;
+    p_cb->evt.type = NRF_DRV_SPI_EVENT_DONE;
+    p_cb->handler(&p_cb->evt);
+}
+
+#ifdef SPI_IN_USE
+// This function is called from IRQ handler or, in blocking mode, directly
+// from the 'nrf_drv_spi_transfer' function.
+// It returns true as long as the transfer should be continued, otherwise (when
+// there is nothing more to send/receive) it returns false.
+static bool transfer_byte(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
+{
+    // Read the data byte received in this transfer and store it in RX buffer,
+    // if needed.
+    volatile uint8_t rx_data = nrf_spi_rxd_get(p_spi);
+    if (p_cb->bytes_transferred < p_cb->evt.data.done.rx_length)
+    {
+        p_cb->evt.data.done.p_rx_buffer[p_cb->bytes_transferred] = rx_data;
+    }
+
+    ++p_cb->bytes_transferred;
+
+    // Check if there are more bytes to send or receive and write proper data
+    // byte (next one from TX buffer or over-run character) to the TXD register
+    // when needed.
+    // NOTE - we've already used 'p_cb->bytes_transferred + 1' bytes from our
+    //        buffers, because we take advantage of double buffering of TXD
+    //        register (so in effect one byte is still being transmitted now);
+    //        see how the transfer is started in the 'nrf_drv_spi_transfer'
+    //        function.
+    uint16_t bytes_used = p_cb->bytes_transferred + 1;
+    
+    if (p_cb->abort)
+    {
+        if (bytes_used < p_cb->evt.data.done.tx_length)
+        {
+            p_cb->evt.data.done.tx_length = bytes_used;
+        }
+        if (bytes_used < p_cb->evt.data.done.rx_length)
+        {
+            p_cb->evt.data.done.rx_length = bytes_used;
+        }
+    }
+    
+    if (bytes_used < p_cb->evt.data.done.tx_length)
+    {
+        nrf_spi_txd_set(p_spi, p_cb->evt.data.done.p_tx_buffer[bytes_used]);
+        return true;
+    }
+    else if (bytes_used < p_cb->evt.data.done.rx_length)
+    {
+        nrf_spi_txd_set(p_spi, p_cb->orc);
+        return true;
+    }
+
+    return (p_cb->bytes_transferred < p_cb->evt.data.done.tx_length ||
+            p_cb->bytes_transferred < p_cb->evt.data.done.rx_length);
+}
+
+static void spi_xfer(NRF_SPI_Type                  * p_spi,
+                     spi_control_block_t           * p_cb,
+                     nrf_drv_spi_xfer_desc_t const * p_xfer_desc)
+{
+    nrf_spi_int_disable(p_spi, NRF_SPI_INT_READY_MASK);
+    p_cb->bytes_transferred = 0;
+
+    nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
+
+    // Start the transfer by writing some byte to the TXD register;
+    // if TX buffer is not empty, take the first byte from this buffer,
+    // otherwise - use over-run character.
+    nrf_spi_txd_set(p_spi,
+        (p_xfer_desc->tx_length > 0 ?  p_xfer_desc->p_tx_buffer[0] : p_cb->orc));
+
+    // TXD register is double buffered, so next byte to be transmitted can
+    // be written immediately, if needed, i.e. if TX or RX transfer is to
+    // be more that 1 byte long. Again - if there is something more in TX
+    // buffer send it, otherwise use over-run character.
+    if (p_xfer_desc->tx_length > 1)
+    {
+        nrf_spi_txd_set(p_spi, p_xfer_desc->p_tx_buffer[1]);
+    }
+    else if (p_xfer_desc->rx_length > 1)
+    {
+        nrf_spi_txd_set(p_spi, p_cb->orc);
+    }
+
+    // For blocking mode (user handler not provided) wait here for READY
+    // events (indicating that the byte from TXD register was transmitted
+    // and a new incoming byte was moved to the RXD register) and continue
+    // transaction until all requested bytes are transferred.
+    // In non-blocking mode - IRQ service routine will do this stuff.
+    if (p_cb->handler)
+    {
+        nrf_spi_int_enable(p_spi, NRF_SPI_INT_READY_MASK);
+    }
+    else
+    {
+        do {
+            while (!nrf_spi_event_check(p_spi, NRF_SPI_EVENT_READY)) {}
+            nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
+        } while (transfer_byte(p_spi, p_cb));
+        if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+        {
+            nrf_gpio_pin_set(p_cb->ss_pin);
+        }
+    }
+}
+#endif // SPI_IN_USE
+
+#ifdef SPIM_IN_USE
+__STATIC_INLINE void spim_int_enable(NRF_SPIM_Type * p_spim, bool enable)
+{
+    if (!enable)
+    {
+        nrf_spim_int_disable(p_spim, END_INT_MASK | NRF_SPIM_INT_STOPPED_MASK);
+    }
+    else
+    {
+        nrf_spim_int_enable(p_spim, END_INT_MASK |  NRF_SPIM_INT_STOPPED_MASK);
+    }
+}
+
+__STATIC_INLINE void spim_list_enable_handle(NRF_SPIM_Type * p_spim, uint32_t flags)
+{
+#ifndef NRF52_PAN_46
+    if (NRF_DRV_SPI_FLAG_TX_POSTINC & flags)
+    {
+        nrf_spim_tx_list_enable(p_spim);
+    }
+    else
+    {
+        nrf_spim_tx_list_disable(p_spim);
+    }
+
+    if (NRF_DRV_SPI_FLAG_RX_POSTINC & flags)
+    {
+        nrf_spim_rx_list_enable(p_spim);
+    }
+    else
+    {
+        nrf_spim_rx_list_disable(p_spim);
+    }
+#endif
+}
+
+static ret_code_t spim_xfer(NRF_SPIM_Type                * p_spim,
+                           spi_control_block_t           * p_cb,
+                           nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
+                           uint32_t                        flags)
+{
+    // EasyDMA requires that transfer buffers are placed in Data RAM region;
+    // signal error if they are not.
+    if ((p_xfer_desc->p_tx_buffer != NULL && !nrf_drv_is_in_RAM(p_xfer_desc->p_tx_buffer)) ||
+        (p_xfer_desc->p_rx_buffer != NULL && !nrf_drv_is_in_RAM(p_xfer_desc->p_rx_buffer)))
+    {
+        p_cb->transfer_in_progress = false;
+        return NRF_ERROR_INVALID_ADDR;
+    }
+
+    nrf_spim_tx_buffer_set(p_spim, p_xfer_desc->p_tx_buffer, p_xfer_desc->tx_length);
+    nrf_spim_rx_buffer_set(p_spim, p_xfer_desc->p_rx_buffer, p_xfer_desc->rx_length);
+
+#ifdef NRF52_PAN_23
+    nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_ENDTX);
+    nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_ENDRX);
+#else
+    nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END);
+#endif
+    nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_STOPPED);
+
+    spim_list_enable_handle(p_spim, flags);
+
+    if (!(flags & NRF_DRV_SPI_FLAG_HOLD_XFER))
+    {
+        nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_START);
+    }
+
+    if (!p_cb->handler)
+    {
+#ifdef NRF52_PAN_23
+        while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_ENDTX) ||
+               !nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_ENDRX)) {}
+#else
+        while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END)){}
+#endif
+        // Stop the peripheral after transaction is finished.
+        nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
+        while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED)) {}
+        if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+        {
+            nrf_gpio_pin_set(p_cb->ss_pin);
+        }
+    }
+		else
+		{
+				spim_int_enable(p_spim, !(flags & NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER));
+		}
+    return NRF_SUCCESS;
+}
+#endif
+
+ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t     const * const p_instance,
+                            nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags)
+{
+    spi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(p_xfer_desc->p_tx_buffer != NULL || p_xfer_desc->tx_length == 0);
+    ASSERT(p_xfer_desc->p_rx_buffer != NULL || p_xfer_desc->rx_length == 0);
+
+    if (p_cb->transfer_in_progress)
+    {
+        return NRF_ERROR_BUSY;
+    }
+    else
+    {
+        if (p_cb->handler && !(flags & (NRF_DRV_SPI_FLAG_REPEATED_XFER | NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER)))
+        {
+            p_cb->transfer_in_progress = true;
+        }
+    }
+
+    p_cb->evt.data.done = *p_xfer_desc;
+    p_cb->tx_done = false;
+    p_cb->rx_done = false;
+    p_cb->abort   = false;
+
+    if (p_cb->ss_pin != NRF_DRV_SPI_PIN_NOT_USED)
+    {
+        nrf_gpio_pin_clear(p_cb->ss_pin);
+    }
+    CODE_FOR_SPIM
+    (
+        return spim_xfer((NRF_SPIM_Type * ) p_instance->p_registers, p_cb,  p_xfer_desc, flags);
+    )
+    CODE_FOR_SPI
+    (
+        if (flags)
+        {
+            p_cb->transfer_in_progress = false;
+            return NRF_ERROR_NOT_SUPPORTED;
+        }
+        spi_xfer((NRF_SPI_Type * ) p_instance->p_registers, p_cb, p_xfer_desc);
+        return NRF_SUCCESS;
+    )
+}
+
+void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance)
+{
+    spi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    CODE_FOR_SPIM
+    (
+        nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
+        while (!nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED)) {}
+        p_cb->transfer_in_progress = false;
+    )
+    CODE_FOR_SPI
+    (
+        p_cb->abort = true;
+    )
+}
+
+#ifdef SPIM_IN_USE
+static void irq_handler_spim(NRF_SPIM_Type * p_spim, spi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+#ifdef NRF52_PAN_23
+    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_STOPPED))
+    {
+        nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_STOPPED);
+        finish_transfer(p_cb);
+    }
+    else
+    {
+        if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_ENDTX))
+        {
+            nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_ENDTX);
+            p_cb->tx_done = true;
+        }
+        if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_ENDRX))
+        {
+            nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_ENDRX);
+            p_cb->rx_done = true;
+        }
+        if (p_cb->tx_done && p_cb->rx_done)
+        {
+            nrf_spim_task_trigger(p_spim, NRF_SPIM_TASK_STOP);
+        }
+    }
+#else
+    if (nrf_spim_event_check(p_spim, NRF_SPIM_EVENT_END))
+    {
+        nrf_spim_event_clear(p_spim, NRF_SPIM_EVENT_END);
+        finish_transfer(p_cb);
+    }
+#endif
+}
+
+uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance)
+{
+    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_registers;
+    return nrf_spim_task_address_get(p_spim, NRF_SPIM_TASK_START);
+}
+
+uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance)
+{
+    NRF_SPIM_Type * p_spim = (NRF_SPIM_Type *)p_instance->p_registers;
+    return nrf_spim_event_address_get(p_spim, NRF_SPIM_EVENT_END);
+}
+#endif // SPIM_IN_USE
+
+#ifdef SPI_IN_USE
+static void irq_handler_spi(NRF_SPI_Type * p_spi, spi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    nrf_spi_event_clear(p_spi, NRF_SPI_EVENT_READY);
+
+    if (!transfer_byte(p_spi, p_cb))
+    {
+        finish_transfer(p_cb);
+    }
+}
+#endif // SPI_IN_USE
+
+#if SPI0_ENABLED
+IRQ_HANDLER(0)
+{
+    spi_control_block_t * p_cb  = &m_cb[SPI0_INSTANCE_INDEX];
+    #if SPI0_USE_EASY_DMA
+        irq_handler_spim(NRF_SPIM0, p_cb);
+    #else
+        irq_handler_spi(NRF_SPI0, p_cb);
+    #endif
+}
+#endif // SPI0_ENABLED
+
+#if SPI1_ENABLED
+IRQ_HANDLER(1)
+{
+    spi_control_block_t * p_cb  = &m_cb[SPI1_INSTANCE_INDEX];
+    #if SPI1_USE_EASY_DMA
+        irq_handler_spim(NRF_SPIM1, p_cb);
+    #else
+        irq_handler_spi(NRF_SPI1, p_cb);
+    #endif
+}
+#endif // SPI1_ENABLED
+
+#if SPI2_ENABLED
+IRQ_HANDLER(2)
+{
+    spi_control_block_t * p_cb  = &m_cb[SPI2_INSTANCE_INDEX];
+    #if SPI2_USE_EASY_DMA
+        irq_handler_spim(NRF_SPIM2, p_cb);
+    #else
+        irq_handler_spi(NRF_SPI2, p_cb);
+    #endif
+}
+#endif // SPI2_ENABLED
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.h
new file mode 100644
index 0000000000..17ae6536f4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_master/nrf_drv_spi.h
@@ -0,0 +1,398 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ * @addtogroup nrf_spi Serial peripheral interface (SPI)
+ * @ingroup    nrf_drivers
+ * @brief      Serial peripheral interface (SPI) APIs.
+ *
+ *
+ * @addtogroup nrf_spi_master SPI master HAL and driver
+ * @ingroup    nrf_spi
+ * @brief      SPI master APIs.
+ */
+
+#ifndef NRF_DRV_SPI_H__
+#define NRF_DRV_SPI_H__
+
+#include "nordic_common.h"
+#include "nrf_drv_config.h"
+#include "nrf_spi.h"
+#include "nrf_spim.h"
+#include "sdk_errors.h"
+
+#if defined(NRF52)
+    #define NRF_DRV_SPI_PERIPHERAL(id)           \
+        (CONCAT_3(SPI, id, _USE_EASY_DMA) == 1 ? \
+            (void *)CONCAT_2(NRF_SPIM, id)       \
+          : (void *)CONCAT_2(NRF_SPI, id))
+    #define SPI2_IRQ            SPIM2_SPIS2_SPI2_IRQn
+    #define SPI2_IRQ_HANDLER    SPIM2_SPIS2_SPI2_IRQHandler
+#else
+    #define NRF_DRV_SPI_PERIPHERAL(id)  (void *)CONCAT_2(NRF_SPI, id)
+#endif
+#define SPI0_IRQ            SPI0_TWI0_IRQn
+#define SPI0_IRQ_HANDLER    SPI0_TWI0_IRQHandler
+#define SPI1_IRQ            SPI1_TWI1_IRQn
+#define SPI1_IRQ_HANDLER    SPI1_TWI1_IRQHandler
+
+
+/**
+ * @defgroup nrf_drv_spi_master SPI master driver
+ * @{
+ * @ingroup  nrf_spi_master
+ *
+ * @brief    Multi-instance SPI master driver.
+ */
+
+/**
+ * @brief SPI master driver instance data structure.
+ */
+typedef struct
+{
+    void *    p_registers;  ///< Pointer to the structure with SPI/SPIM peripheral instance registers.
+    IRQn_Type irq;          ///< SPI/SPIM peripheral instance IRQ number.
+    uint8_t   drv_inst_idx; ///< Driver instance index.
+    bool      use_easy_dma; ///< True if the peripheral with EasyDMA (SPIM) shall be used.
+} nrf_drv_spi_t;
+
+/**
+ * @brief Macro for creating an SPI master driver instance.
+ */
+#define NRF_DRV_SPI_INSTANCE(id)                        \
+{                                                       \
+    .p_registers  = NRF_DRV_SPI_PERIPHERAL(id),         \
+    .irq          = CONCAT_3(SPI, id, _IRQ),            \
+    .drv_inst_idx = CONCAT_3(SPI, id, _INSTANCE_INDEX), \
+    .use_easy_dma = CONCAT_3(SPI, id, _USE_EASY_DMA)    \
+}
+
+/**
+ * @brief This value can be provided instead of a pin number for signals MOSI,
+ *        MISO, and Slave Select to specify that the given signal is not used and
+ *        therefore does not need to be connected to a pin.
+ */
+#define NRF_DRV_SPI_PIN_NOT_USED  0xFF
+
+/**
+ * @brief SPI data rates.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_FREQ_125K = NRF_SPI_FREQ_125K, ///< 125 kbps.
+    NRF_DRV_SPI_FREQ_250K = NRF_SPI_FREQ_250K, ///< 250 kbps.
+    NRF_DRV_SPI_FREQ_500K = NRF_SPI_FREQ_500K, ///< 500 kbps.
+    NRF_DRV_SPI_FREQ_1M   = NRF_SPI_FREQ_1M,   ///< 1 Mbps.
+    NRF_DRV_SPI_FREQ_2M   = NRF_SPI_FREQ_2M,   ///< 2 Mbps.
+    NRF_DRV_SPI_FREQ_4M   = NRF_SPI_FREQ_4M,   ///< 4 Mbps.
+    NRF_DRV_SPI_FREQ_8M   = NRF_SPI_FREQ_8M    ///< 8 Mbps.
+} nrf_drv_spi_frequency_t;
+
+/**
+ * @brief SPI modes.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_MODE_0 = NRF_SPI_MODE_0, ///< SCK active high, sample on leading edge of clock.
+    NRF_DRV_SPI_MODE_1 = NRF_SPI_MODE_1, ///< SCK active high, sample on trailing edge of clock.
+    NRF_DRV_SPI_MODE_2 = NRF_SPI_MODE_2, ///< SCK active low, sample on leading edge of clock.
+    NRF_DRV_SPI_MODE_3 = NRF_SPI_MODE_3  ///< SCK active low, sample on trailing edge of clock.
+} nrf_drv_spi_mode_t;
+
+/**
+ * @brief SPI bit orders.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_BIT_ORDER_MSB_FIRST = NRF_SPI_BIT_ORDER_MSB_FIRST, ///< Most significant bit shifted out first.
+    NRF_DRV_SPI_BIT_ORDER_LSB_FIRST = NRF_SPI_BIT_ORDER_LSB_FIRST  ///< Least significant bit shifted out first.
+} nrf_drv_spi_bit_order_t;
+
+/**
+ * @brief SPI master driver instance configuration structure.
+ */
+typedef struct
+{
+    uint8_t sck_pin;      ///< SCK pin number.
+    uint8_t mosi_pin;     ///< MOSI pin number (optional).
+                          /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t miso_pin;     ///< MISO pin number (optional).
+                          /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED
+                           *   if this signal is not needed. */
+    uint8_t ss_pin;       ///< Slave Select pin number (optional).
+                          /**< Set to @ref NRF_DRV_SPI_PIN_NOT_USED
+                           *   if this signal is not needed. The driver 
+                           *   supports only active low for this signal. 
+                           *   If the signal should be active high,
+                           *   it must be controlled externally. */
+    uint8_t irq_priority; ///< Interrupt priority.
+    uint8_t orc;          ///< Over-run character.
+                          /**< This character is used when all bytes from the TX buffer are sent,
+                               but the transfer continues due to RX. */
+    nrf_drv_spi_frequency_t frequency; ///< SPI frequency.
+    nrf_drv_spi_mode_t      mode;      ///< SPI mode.
+    nrf_drv_spi_bit_order_t bit_order; ///< SPI bit order.
+} nrf_drv_spi_config_t;
+
+/**
+ * @brief SPI master instance default configuration.
+ */
+#define NRF_DRV_SPI_DEFAULT_CONFIG(id)                       \
+{                                                            \
+    .sck_pin      = CONCAT_3(SPI, id, _CONFIG_SCK_PIN),      \
+    .mosi_pin     = CONCAT_3(SPI, id, _CONFIG_MOSI_PIN),     \
+    .miso_pin     = CONCAT_3(SPI, id, _CONFIG_MISO_PIN),     \
+    .ss_pin       = NRF_DRV_SPI_PIN_NOT_USED,                \
+    .irq_priority = CONCAT_3(SPI, id, _CONFIG_IRQ_PRIORITY), \
+    .orc          = 0xFF,                                    \
+    .frequency    = NRF_DRV_SPI_FREQ_4M,                     \
+    .mode         = NRF_DRV_SPI_MODE_0,                      \
+    .bit_order    = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST,         \
+}
+
+#define NRF_DRV_SPI_FLAG_TX_POSTINC          (1UL << 0) /**< TX buffer address incremented after transfer. */
+#define NRF_DRV_SPI_FLAG_RX_POSTINC          (1UL << 1) /**< RX buffer address incremented after transfer. */
+#define NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
+#define NRF_DRV_SPI_FLAG_HOLD_XFER           (1UL << 3) /**< Set up the transfer but do not start it. */
+#define NRF_DRV_SPI_FLAG_REPEATED_XFER       (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */
+
+/**
+ * @brief Single transfer descriptor structure.
+ */
+typedef struct
+{
+    uint8_t const * p_tx_buffer; ///< Pointer to TX buffer.
+    uint8_t         tx_length;   ///< TX buffer length.
+    uint8_t       * p_rx_buffer; ///< Pointer to RX buffer.
+    uint8_t         rx_length;   ///< RX buffer length.
+}nrf_drv_spi_xfer_desc_t;
+
+
+/**
+ * @brief Macro for setting up single transfer descriptor.
+ *
+ * This macro is for internal use only.
+ */
+#define NRF_DRV_SPI_SINGLE_XFER(p_tx, tx_len, p_rx, rx_len)  \
+    {                                                        \
+    .p_tx_buffer = (uint8_t const *)(p_tx),                  \
+    .tx_length = (tx_len),                                   \
+    .p_rx_buffer = (p_rx),                                   \
+    .rx_length = (rx_len),                                   \
+    }
+
+/**
+ * @brief Macro for setting duplex TX RX transfer.
+ */
+#define NRF_DRV_SPI_XFER_TRX(p_tx_buf, tx_length, p_rx_buf, rx_length)                    \
+        NRF_DRV_SPI_SINGLE_XFER(p_tx_buf, tx_length, p_rx_buf, rx_length)
+
+/**
+ * @brief Macro for setting TX transfer.
+ */
+#define NRF_DRV_SPI_XFER_TX(p_buf, length) \
+        NRF_DRV_SPI_SINGLE_XFER(p_buf, length, NULL, 0)
+
+/**
+ * @brief Macro for setting RX transfer.
+ */
+#define NRF_DRV_SPI_XFER_RX(p_buf, length) \
+        NRF_DRV_SPI_SINGLE_XFER(NULL, 0, p_buf, length)
+
+/**
+ * @brief SPI master driver event types, passed to the handler routine provided
+ *        during initialization.
+ */
+typedef enum
+{
+    NRF_DRV_SPI_EVENT_DONE, ///< Transfer done.
+} nrf_drv_spi_evt_type_t;
+
+typedef struct
+{
+    nrf_drv_spi_evt_type_t  type;      ///< Event type.
+    union
+    {
+        nrf_drv_spi_xfer_desc_t done;  ///< Event data for DONE event.
+    } data;
+} nrf_drv_spi_evt_t;
+
+/**
+ * @brief SPI master driver event handler type.
+ */
+typedef void (*nrf_drv_spi_handler_t)(nrf_drv_spi_evt_t const * p_event);
+
+
+/**
+ * @brief Function for initializing the SPI master driver instance.
+ *
+ * This function configures and enables the specified peripheral.
+ *
+ * @param[in] p_instance Pointer to the instance structure.
+ * @param[in] p_config   Pointer to the structure with the initial configuration.
+ *                       If NULL, the default configuration is used.
+ * @param     handler    Event handler provided by the user. If NULL, transfers
+ *                       will be performed in blocking mode.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver was already initialized.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is 
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED 
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_spi_init(nrf_drv_spi_t const * const p_instance,
+                            nrf_drv_spi_config_t const * p_config,
+                            nrf_drv_spi_handler_t handler);
+
+/**
+ * @brief Function for uninitializing the SPI master driver instance.
+ *
+ * @param[in] p_instance Pointer to the instance structure.
+ */
+void       nrf_drv_spi_uninit(nrf_drv_spi_t const * const p_instance);
+
+/**
+ * @brief Function for starting the SPI data transfer.
+ *
+ * If an event handler was provided in the @ref nrf_drv_spi_init call, this function
+ * returns immediately and the handler is called when the transfer is done.
+ * Otherwise, the transfer is performed in blocking mode, which means that this function
+ * returns when the transfer is finished.
+ *
+ * @note Peripherals using EasyDMA (for example, SPIM) require the transfer buffers
+ *       to be placed in the Data RAM region. If they are not and an SPIM instance is
+ *       used, this function will fail with the error code NRF_ERROR_INVALID_ADDR.
+ *
+ * @param[in] p_instance       Pointer to the instance structure.
+ * @param[in] p_tx_buffer      Pointer to the transmit buffer. Can be NULL
+ *                             if there is nothing to send.
+ * @param     tx_buffer_length Length of the transmit buffer.
+ * @param[in] p_rx_buffer      Pointer to the receive buffer. Can be NULL
+ *                             if there is nothing to receive.
+ * @param     rx_buffer_length Length of the receive buffer.
+ *
+ * @retval NRF_SUCCESS            If the operation was successful.
+ * @retval NRF_ERROR_BUSY         If a previously started transfer has not finished
+ *                                yet.
+ * @retval NRF_ERROR_INVALID_ADDR If the provided buffers are not placed in the Data
+ *                                RAM region.
+ */
+ret_code_t nrf_drv_spi_transfer(nrf_drv_spi_t const * const p_instance,
+                                uint8_t const * p_tx_buffer,
+                                uint8_t         tx_buffer_length,
+                                uint8_t       * p_rx_buffer,
+                                uint8_t         rx_buffer_length);
+
+
+/**
+ * @brief Function for starting the SPI data transfer with additional option flags.
+ *
+ * Function enables customizing the transfer by using option flags.
+ *
+ * Additional options are provided using the flags parameter:
+ *
+ * - @ref NRF_DRV_SPI_FLAG_TX_POSTINC and @ref NRF_DRV_SPI_FLAG_RX_POSTINC<span></span>:
+ *   Post-incrementation of buffer addresses. Supported only by SPIM.
+ * - @ref NRF_DRV_SPI_FLAG_HOLD_XFER<span></span>: Driver is not starting the transfer. Use this
+ *   flag if the transfer is triggered externally by PPI. Supported only by SPIM. Use
+ *   @ref nrf_drv_twi_start_task_get to get the address of the start task.
+ * - @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer
+ *   completion. This also means no interrupt at the end of the transfer. Supported only by SPIM.
+ *   If @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER is used, the driver does not set the instance into
+ *   busy state, so you must ensure that the next transfers are set up when SPIM is not active.
+ *   @ref nrf_drv_spi_end_event_get function can be used to detect end of transfer. Option can be used
+ *   together with @ref NRF_DRV_SPI_FLAG_REPEATED_XFER to prepare a sequence of SPI transfers
+ *   without interruptions.
+ * - @ref NRF_DRV_SPI_FLAG_REPEATED_XFER<span></span>: Prepare for repeated transfers. You can set
+ *   up a number of transfers that will be triggered externally (for example by PPI). An example is
+ *   a TXRX transfer with the options @ref NRF_DRV_SPI_FLAG_RX_POSTINC,
+ *   @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_SPI_FLAG_REPEATED_XFER. After the
+ *   transfer is set up, a set of transfers can be triggered by PPI that will read, for example,
+ *   the same register of an external component and put it into a RAM buffer without any interrupts.
+ *   @ref nrf_drv_spi_end_event_get can be used to get the address of the END event, which can be
+ *   used to count the number of transfers. If @ref NRF_DRV_SPI_FLAG_REPEATED_XFER is used,
+ *   the driver does not set the instance into busy state, so you must ensure that the next
+ *   transfers are set up when SPIM is not active. Supported only by SPIM.
+ * @note Function is intended to be used only in non-blocking mode.
+ *
+ * @param p_instance  SPI instance.
+ * @param p_xfer_desc Pointer to the transfer descriptor.
+ * @param flags       Transfer options (0 for default settings).
+ *
+ * @retval NRF_SUCCESS             If the procedure was successful.
+ * @retval NRF_ERROR_BUSY          If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
+ * @retval NRF_ERROR_INVALID_ADDR  If the provided buffers are not placed in the Data
+ *                                 RAM region.
+ */
+ret_code_t nrf_drv_spi_xfer(nrf_drv_spi_t     const * const p_instance,
+                            nrf_drv_spi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags);
+
+/**
+ * @brief Function for returning the address of a SPIM start task.
+ *
+ * This function should be used if @ref nrf_drv_spi_xfer was called with the flag @ref NRF_DRV_SPI_FLAG_HOLD_XFER.
+ * In that case, the transfer is not started by the driver, but it must be started externally by PPI.
+ *
+ * @param[in]  p_instance SPI instance.
+ *
+ * @return     Start task address.
+ */
+uint32_t nrf_drv_spi_start_task_get(nrf_drv_spi_t const * p_instance);
+
+/**
+ * @brief Function for returning the address of a END SPIM event.
+ *
+ * A END event can be used to detect the end of a transfer if the @ref NRF_DRV_SPI_FLAG_NO_XFER_EVT_HANDLER
+ * option is used.
+ *
+ * @param[in]  p_instance  SPI instance.
+ *
+ * @return     END event address.
+ */
+uint32_t nrf_drv_spi_end_event_get(nrf_drv_spi_t const * p_instance);
+
+void nrf_drv_spi_abort(nrf_drv_spi_t const * p_instance);
+
+#endif // NRF_DRV_SPI_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c
new file mode 100644
index 0000000000..75d261b69f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.c
@@ -0,0 +1,423 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+#include "nrf_drv_spis.h"
+#include <stdbool.h>
+#include <stdio.h>
+#include "nrf.h"
+#include "nrf_gpio.h"
+#include "app_error.h"
+#include "app_util_platform.h"
+#include "nrf_drv_config.h"
+#include "nrf_drv_common.h"
+#include "nordic_common.h"
+#include "sdk_common.h"
+#include "nrf_assert.h"
+
+#if !SPIS_COUNT
+    #warning No SPIS instances enabled.
+#else
+
+/**@brief States of the SPI transaction state machine. */
+typedef enum
+{
+    SPIS_STATE_INIT,                                 /**< Initialization state. In this state the module waits for a call to @ref spi_slave_buffers_set. */                                                                                             
+    SPIS_BUFFER_RESOURCE_REQUESTED,                  /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has started. */
+    SPIS_BUFFER_RESOURCE_CONFIGURED,                 /**< State where the configuration of the memory buffers, which are to be used in SPI transaction, has completed. */
+    SPIS_XFER_COMPLETED                              /**< State where SPI transaction has been completed. */
+} nrf_drv_spis_state_t;
+
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if SPIS0_ENABLED
+        IRQ_HANDLER(0);
+    #endif
+    #if SPIS1_ENABLED
+        IRQ_HANDLER(1);
+    #endif
+    #if SPIS2_ENABLED
+        IRQ_HANDLER(2);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[SPIS_COUNT] = {
+    #if SPIS0_ENABLED
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if SPIS1_ENABLED
+        IRQ_HANDLER_NAME(1),
+    #endif
+    #if SPIS2_ENABLED
+        IRQ_HANDLER_NAME(2),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) void SPIS##n##_IRQ_HANDLER(void)
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+#define SPIS_IRQHANDLER_TEMPLATE(NUM) \
+    IRQ_HANDLER(NUM)                                                        \
+    {                                                                       \
+        spis_irq_handler(NRF_SPIS##NUM, &m_cb[SPIS##NUM##_INSTANCE_INDEX]); \
+    }
+
+
+/**@brief SPIS control block - driver instance local data. */
+typedef struct
+{
+    volatile uint32_t             tx_buffer_size;  //!< SPI slave TX buffer size in bytes.
+    volatile uint32_t             rx_buffer_size;  //!< SPI slave RX buffer size in bytes.
+    nrf_drv_spis_event_handler_t  handler;         //!< SPI event handler.
+    volatile const uint8_t *      tx_buffer;       //!< SPI slave TX buffer.
+    volatile uint8_t *            rx_buffer;       //!< SPI slave RX buffer.
+    nrf_drv_state_t               state;           //!< driver initialization state.
+    volatile nrf_drv_spis_state_t spi_state;       //!< SPI slave state.
+} spis_cb_t;
+
+static spis_cb_t m_cb[SPIS_COUNT];
+
+static nrf_drv_spis_config_t const m_default_config[SPIS_COUNT] = {
+#if SPIS0_ENABLED
+    NRF_DRV_SPIS_DEFAULT_CONFIG(0),
+#endif
+#if SPIS1_ENABLED
+    NRF_DRV_SPIS_DEFAULT_CONFIG(1),
+#endif
+#if SPIS2_ENABLED
+    NRF_DRV_SPIS_DEFAULT_CONFIG(2),
+#endif
+};
+
+
+ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const  p_instance,
+                             nrf_drv_spis_config_t const * p_config,
+                             nrf_drv_spis_event_handler_t  event_handler)
+{
+    spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
+    
+    NRF_SPIS_Type * p_spis = p_instance->p_reg;
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config[p_instance->instance_id];
+    }
+    if ((uint32_t)p_config->mode > (uint32_t)NRF_DRV_SPIS_MODE_3)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+    if (!event_handler)
+    {
+        return NRF_ERROR_NULL;
+    }
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    if (nrf_drv_common_per_res_acquire(p_spis,
+            m_irq_handlers[p_instance->instance_id]) != NRF_SUCCESS)
+    {
+        return NRF_ERROR_BUSY;
+    }
+#endif
+
+    // Configure the SPI pins for input.
+    uint32_t mosi_pin;
+    uint32_t miso_pin;
+    
+    if (p_config->miso_pin != NRF_DRV_SPIS_PIN_NOT_USED)
+    {
+        nrf_gpio_cfg(p_config->miso_pin,
+                    NRF_GPIO_PIN_DIR_INPUT,
+                    NRF_GPIO_PIN_INPUT_CONNECT,
+                    NRF_GPIO_PIN_NOPULL,
+                    p_config->miso_drive,
+                    NRF_GPIO_PIN_NOSENSE);
+        miso_pin = p_config->miso_pin;
+    }
+    else
+    {
+        miso_pin = NRF_SPIS_PIN_NOT_CONNECTED;
+    }
+    
+    if (p_config->mosi_pin != NRF_DRV_SPIS_PIN_NOT_USED)
+    {
+        nrf_gpio_cfg(p_config->mosi_pin,
+                     NRF_GPIO_PIN_DIR_INPUT,
+                     NRF_GPIO_PIN_INPUT_CONNECT,
+                     NRF_GPIO_PIN_NOPULL,
+                     NRF_GPIO_PIN_S0S1,
+                     NRF_GPIO_PIN_NOSENSE);
+        mosi_pin = p_config->mosi_pin;
+    }
+    else
+    {
+        mosi_pin = NRF_SPIS_PIN_NOT_CONNECTED;
+    }
+    
+    nrf_gpio_cfg(p_config->csn_pin,
+                 NRF_GPIO_PIN_DIR_INPUT,
+                 NRF_GPIO_PIN_INPUT_CONNECT,
+                 p_config->csn_pullup,
+                 NRF_GPIO_PIN_S0S1,
+                 NRF_GPIO_PIN_NOSENSE);
+    
+    nrf_gpio_cfg(p_config->sck_pin,
+                 NRF_GPIO_PIN_DIR_INPUT,
+                 NRF_GPIO_PIN_INPUT_CONNECT,
+                 NRF_GPIO_PIN_NOPULL,
+                 NRF_GPIO_PIN_S0S1,
+                 NRF_GPIO_PIN_NOSENSE);
+
+    nrf_spis_pins_set(p_spis, p_config->sck_pin, mosi_pin, miso_pin, p_config->csn_pin);
+    
+    nrf_spis_rx_buffer_set(p_spis, NULL, 0);
+    nrf_spis_tx_buffer_set(p_spis, NULL, 0);
+    
+    // Configure SPI mode.
+    nrf_spis_configure(p_spis, (nrf_spis_mode_t) p_config->mode,
+                               (nrf_spis_bit_order_t) p_config->bit_order);
+    
+    // Configure DEF and ORC characters.
+    nrf_spis_def_set(p_spis, p_config->def);
+    nrf_spis_orc_set(p_spis, p_config->orc);
+    
+    // Clear possible pending events.
+    nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END);
+    nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED);
+    
+    // Enable END_ACQUIRE shortcut.        
+    nrf_spis_shorts_enable(p_spis, NRF_SPIS_SHORT_END_ACQUIRE);
+    
+    m_cb[p_instance->instance_id].spi_state = SPIS_STATE_INIT;
+    m_cb[p_instance->instance_id].handler = event_handler;
+
+    
+    // Enable IRQ.
+    nrf_spis_int_enable(p_spis, NRF_SPIS_INT_ACQUIRED_MASK | NRF_SPIS_INT_END_MASK);
+    nrf_drv_common_irq_enable(p_instance->irq, p_config->irq_priority);
+    
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+    
+    // Enable SPI slave device.        
+    nrf_spis_enable(p_spis);
+    
+    return NRF_SUCCESS;
+}
+
+
+void nrf_drv_spis_uninit(nrf_drv_spis_t const * const  p_instance)
+{
+    spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+    
+    NRF_SPIS_Type * p_spis = p_instance->p_reg;
+
+    #define DISABLE_ALL 0xFFFFFFFF
+    nrf_spis_disable(p_spis);
+    nrf_drv_common_irq_disable(p_instance->irq);
+    nrf_spis_int_disable(p_spis, DISABLE_ALL);
+    #undef  DISABLE_ALL
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    nrf_drv_common_per_res_release(p_spis);
+#endif
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+
+/**@brief Function for executing the state entry action. */
+static void spis_state_entry_action_execute(NRF_SPIS_Type * p_spis,
+                                                     spis_cb_t * p_cb)
+{
+    nrf_drv_spis_event_t event;
+    
+    switch (p_cb->spi_state)
+    {                             
+        case SPIS_BUFFER_RESOURCE_REQUESTED:
+            nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_ACQUIRE);
+            break;            
+     
+        case SPIS_BUFFER_RESOURCE_CONFIGURED:
+            event.evt_type  = NRF_DRV_SPIS_BUFFERS_SET_DONE;
+            event.rx_amount = 0;
+            event.tx_amount = 0;     
+            
+            APP_ERROR_CHECK_BOOL(p_cb->handler != NULL);
+            p_cb->handler(event);
+            break;
+            
+        case SPIS_XFER_COMPLETED:        
+            event.evt_type  = NRF_DRV_SPIS_XFER_DONE;
+            event.rx_amount = nrf_spis_rx_amount_get(p_spis);
+            event.tx_amount = nrf_spis_tx_amount_get(p_spis);
+            APP_ERROR_CHECK_BOOL(p_cb->handler != NULL);
+            p_cb->handler(event);
+            break;
+            
+        default:
+            // No implementation required.            
+            break;
+    }
+}
+
+/**@brief Function for changing the state of the SPI state machine.
+ *
+ * @param[in] p_spis    SPIS instance register.
+ * @param[in] p_cb      SPIS instance control block.
+ * @param[in] new_state State where the state machine transits to.
+ */
+static void spis_state_change(NRF_SPIS_Type * p_spis,
+                              spis_cb_t * p_cb,
+                              nrf_drv_spis_state_t new_state)
+{
+    p_cb->spi_state = new_state;
+    spis_state_entry_action_execute(p_spis, p_cb);
+}
+
+
+ret_code_t nrf_drv_spis_buffers_set(nrf_drv_spis_t const * const  p_instance,
+                                    const uint8_t * p_tx_buffer,
+                                    uint8_t   tx_buffer_length,
+                                    uint8_t * p_rx_buffer,
+                                    uint8_t   rx_buffer_length)
+{
+    spis_cb_t * p_cb = &m_cb[p_instance->instance_id];
+    uint32_t err_code;
+
+    VERIFY_PARAM_NOT_NULL(p_rx_buffer);
+    VERIFY_PARAM_NOT_NULL(p_tx_buffer);
+
+    // EasyDMA requires that transfer buffers are placed in Data RAM region;
+    // signal error if they are not.
+    if ((p_tx_buffer != NULL && !nrf_drv_is_in_RAM(p_tx_buffer)) ||
+        (p_rx_buffer != NULL && !nrf_drv_is_in_RAM(p_rx_buffer)))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+    
+    switch (p_cb->spi_state)
+    {
+        case SPIS_STATE_INIT:
+        case SPIS_XFER_COMPLETED:
+        case SPIS_BUFFER_RESOURCE_CONFIGURED:        
+            p_cb->tx_buffer      = p_tx_buffer;
+            p_cb->rx_buffer      = p_rx_buffer;
+            p_cb->tx_buffer_size = tx_buffer_length;
+            p_cb->rx_buffer_size = rx_buffer_length;        
+            err_code             = NRF_SUCCESS;            
+                        
+            spis_state_change(p_instance->p_reg, p_cb, SPIS_BUFFER_RESOURCE_REQUESTED);             
+            break;
+
+        case SPIS_BUFFER_RESOURCE_REQUESTED:
+            err_code = NRF_ERROR_INVALID_STATE; 
+            break;
+        
+        default:
+            // @note: execution of this code path would imply internal error in the design.
+            err_code = NRF_ERROR_INTERNAL;             
+            break;
+    }
+    
+    return err_code;
+}
+
+static void spis_irq_handler(NRF_SPIS_Type * p_spis, spis_cb_t * p_cb)
+{
+    // @note: as multiple events can be pending for processing, the correct event processing order 
+    // is as follows:
+    // - SPI semaphore acquired event.
+    // - SPI transaction complete event.
+    
+    // Check for SPI semaphore acquired event.
+    if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_ACQUIRED))
+    {
+        nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_ACQUIRED);
+        
+        switch (p_cb->spi_state)
+        {                
+            case SPIS_BUFFER_RESOURCE_REQUESTED:     
+                nrf_spis_tx_buffer_set(p_spis, (uint8_t *)p_cb->tx_buffer, p_cb->tx_buffer_size);
+                nrf_spis_rx_buffer_set(p_spis, (uint8_t *)p_cb->rx_buffer, p_cb->rx_buffer_size);
+                
+                nrf_spis_task_trigger(p_spis, NRF_SPIS_TASK_RELEASE);
+                
+                spis_state_change(p_spis, p_cb, SPIS_BUFFER_RESOURCE_CONFIGURED);                                                                       
+                break;
+                
+            default:
+                // No implementation required.
+                break;
+        }
+    }
+
+    // Check for SPI transaction complete event.
+    if (nrf_spis_event_check(p_spis, NRF_SPIS_EVENT_END))
+    {
+        nrf_spis_event_clear(p_spis, NRF_SPIS_EVENT_END);
+        
+        switch (p_cb->spi_state)
+        {
+            case SPIS_BUFFER_RESOURCE_CONFIGURED:    
+                spis_state_change(p_spis, p_cb, SPIS_XFER_COMPLETED);
+                break;
+
+            default:
+                // No implementation required.                    
+                break;                
+        }    
+    }
+}
+
+#if SPIS0_ENABLED
+    SPIS_IRQHANDLER_TEMPLATE(0)
+#endif
+
+#if SPIS1_ENABLED
+    SPIS_IRQHANDLER_TEMPLATE(1)
+#endif
+
+#if SPIS2_ENABLED
+    SPIS_IRQHANDLER_TEMPLATE(2)
+#endif
+
+#endif // SPI_COUNT > 0
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h
new file mode 100644
index 0000000000..a761f66717
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/spi_slave/nrf_drv_spis.h
@@ -0,0 +1,250 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/**@file
+ * @defgroup nrf_spis SPI slave HAL and driver
+ * @ingroup nrf_spi
+ * @brief SPI slave API.
+ * @details The SPIS HAL provides basic APIs for accessing the registers 
+ * of the SPIS. The SPIS driver provides APIs on a higher level.
+ **/
+
+#ifndef SPI_SLAVE_H__
+#define SPI_SLAVE_H__
+
+#include <stdint.h>
+#include "nrf.h"
+#include "nrf_error.h"
+#include "nrf_drv_config.h"
+#include "nrf_spis.h"
+#include "nrf_gpio.h"
+#include "sdk_common.h"
+#include "app_util_platform.h"
+
+#if defined(NRF52)
+    #define SPIS2_IRQ            SPIM2_SPIS2_SPI2_IRQn
+    #define SPIS2_IRQ_HANDLER    SPIM2_SPIS2_SPI2_IRQHandler
+    #define SPIS0_IRQ            SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQn
+    #define SPIS0_IRQ_HANDLER    SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler
+    #define SPIS1_IRQ            SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQn
+    #define SPIS1_IRQ_HANDLER    SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler
+#else
+    #define SPIS0_IRQ            SPI0_TWI0_IRQn
+    #define SPIS0_IRQ_HANDLER    SPI0_TWI0_IRQHandler
+    #define SPIS1_IRQ            SPI1_TWI1_IRQn
+    #define SPIS1_IRQ_HANDLER    SPI1_TWI1_IRQHandler
+#endif
+
+/**
+ * @defgroup nrf_drv_spi_slave SPI slave driver
+ * @{
+ * @ingroup  nrf_spis
+ *
+ * @brief    Multi-instance SPI slave driver.
+ */
+ 
+#define NRF_DRV_SPIS_DEFAULT_CSN_PULLUP NRF_GPIO_PIN_NOPULL /**< Default pull-up configuration of the SPI CS. */
+#define NRF_DRV_SPIS_DEFAULT_MISO_DRIVE NRF_GPIO_PIN_S0S1   /**< Default drive configuration of the SPI MISO. */
+#define NRF_DRV_SPIS_DEFAULT_DEF        0xFF                /**< Default DEF character. */
+#define NRF_DRV_SPIS_DEFAULT_ORC        0xFF                /**< Default ORC character. */
+ 
+/**
+* @brief This value can be provided instead of a pin number for the signals MOSI
+*        and MISO to specify that the given signal is not used and therefore
+*        does not need to be connected to a pin.
+*/
+#define NRF_DRV_SPIS_PIN_NOT_USED       0xFF
+
+/** @brief SPIS transaction bit order definitions. */
+typedef enum
+{
+    NRF_DRV_SPIS_BIT_ORDER_LSB_FIRST = NRF_SPIS_BIT_ORDER_LSB_FIRST, /**< Least significant bit shifted out first. */
+    NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST = NRF_SPIS_BIT_ORDER_MSB_FIRST  /**< Most significant bit shifted out first. */
+} nrf_drv_spis_endian_t;
+
+/** @brief SPIS mode definitions for clock polarity and phase. */
+typedef enum
+{
+    NRF_DRV_SPIS_MODE_0 = NRF_SPIS_MODE_0,       /**< (CPOL = 0, CPHA = 0). */
+    NRF_DRV_SPIS_MODE_1 = NRF_SPIS_MODE_1,       /**< (CPOL = 0, CPHA = 1). */
+    NRF_DRV_SPIS_MODE_2 = NRF_SPIS_MODE_2,       /**< (CPOL = 1, CPHA = 0). */
+    NRF_DRV_SPIS_MODE_3 = NRF_SPIS_MODE_3        /**< (CPOL = 1, CPHA = 1). */
+} nrf_drv_spis_mode_t;
+
+/** @brief Event callback function event definitions. */
+typedef enum
+{
+    NRF_DRV_SPIS_BUFFERS_SET_DONE,          /**< Memory buffer set event. Memory buffers have been set successfully to the SPI slave device, and SPI transactions can be done. */
+    NRF_DRV_SPIS_XFER_DONE,                 /**< SPI transaction event. SPI transaction has been completed. */  
+    NRF_DRV_SPIS_EVT_TYPE_MAX                    /**< Enumeration upper bound. */      
+} nrf_drv_spis_event_type_t;
+
+/** @brief Structure containing the event context from the SPI slave driver. */
+typedef struct
+{
+    nrf_drv_spis_event_type_t evt_type;     //!< Type of event.
+    uint32_t                  rx_amount;    //!< Number of bytes received in last transaction. This parameter is only valid for @ref NRF_DRV_SPIS_XFER_DONE events.
+    uint32_t                  tx_amount;    //!< Number of bytes transmitted in last transaction. This parameter is only valid for @ref NRF_DRV_SPIS_XFER_DONE events.
+} nrf_drv_spis_event_t;
+
+/** @brief SPI slave driver instance data structure. */
+typedef struct
+{
+    NRF_SPIS_Type * p_reg;          //!< SPIS instance register.
+    uint8_t         instance_id;    //!< SPIS instance ID.
+    IRQn_Type       irq;            //!< IRQ of the specific instance.
+} nrf_drv_spis_t;
+
+/** @brief Macro for creating an SPI slave driver instance. */
+#define NRF_DRV_SPIS_INSTANCE(id)                        \
+{                                                        \
+    .p_reg        = CONCAT_2(NRF_SPIS, id),              \
+    .irq          = CONCAT_3(SPIS, id, _IRQ),            \
+    .instance_id  = CONCAT_3(SPIS, id, _INSTANCE_INDEX), \
+}
+
+/** @brief SPI slave instance default configuration. */
+#define NRF_DRV_SPIS_DEFAULT_CONFIG(id)                       \
+{                                                             \
+    .sck_pin      = CONCAT_3(SPIS, id, _CONFIG_SCK_PIN),      \
+    .mosi_pin     = CONCAT_3(SPIS, id, _CONFIG_MOSI_PIN),     \
+    .miso_pin     = CONCAT_3(SPIS, id, _CONFIG_MISO_PIN),     \
+    .csn_pin      = NRF_DRV_SPIS_PIN_NOT_USED,                \
+    .miso_drive   = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE,          \
+    .csn_pullup   = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP,          \
+    .orc          = NRF_DRV_SPIS_DEFAULT_ORC,                 \
+    .def          = NRF_DRV_SPIS_DEFAULT_DEF,                 \
+    .mode         = NRF_DRV_SPIS_MODE_0,                      \
+    .bit_order    = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST,         \
+    .irq_priority = CONCAT_3(SPIS, id, _CONFIG_IRQ_PRIORITY), \
+}
+
+/** @brief SPI peripheral device configuration data. */
+typedef struct 
+{
+    uint32_t              miso_pin;            //!< SPI MISO pin (optional).
+                                               /**< Set @ref NRF_DRV_SPIS_PIN_NOT_USED
+                                                *   if this signal is not needed. */
+    uint32_t              mosi_pin;            //!< SPI MOSI pin (optional).
+                                               /**< Set @ref NRF_DRV_SPIS_PIN_NOT_USED
+                                                *   if this signal is not needed. */
+    uint32_t              sck_pin;             //!< SPI SCK pin.
+    uint32_t              csn_pin;             //!< SPI CSN pin.
+    nrf_drv_spis_mode_t   mode;                //!< SPI mode.
+    nrf_drv_spis_endian_t bit_order;           //!< SPI transaction bit order.
+    nrf_gpio_pin_pull_t   csn_pullup;          //!< CSN pin pull-up configuration.
+    nrf_gpio_pin_drive_t  miso_drive;          //!< MISO pin drive configuration.
+    uint8_t               def;                 //!< Character clocked out in case of an ignored transaction.
+    uint8_t               orc;                 //!< Character clocked out after an over-read of the transmit buffer.
+    uint8_t               irq_priority;        //!< Interrupt priority.
+} nrf_drv_spis_config_t;
+
+
+/** @brief SPI slave event callback function type.
+ *
+ * @param[in] event                 SPI slave driver event.  
+ */
+typedef void (*nrf_drv_spis_event_handler_t)(nrf_drv_spis_event_t event);
+
+/** @brief Function for initializing the SPI slave driver instance.
+ *
+ * @param[in] p_instance    Pointer to the instance structure.
+ * @param[in] p_config      Pointer to the structure with the initial configuration.
+ *                          If NULL, the default configuration will be used.
+ * @param[in] event_handler Function to be called by the SPI slave driver upon event.
+ *
+ * @retval NRF_SUCCESS             If the initialization was successful.
+ * @retval NRF_ERROR_INVALID_PARAM If an invalid parameter is supplied.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is 
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED 
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_spis_init(nrf_drv_spis_t const * const  p_instance,
+                             nrf_drv_spis_config_t const * p_config,
+                             nrf_drv_spis_event_handler_t  event_handler);
+
+/**
+ * @brief Function for uninitializing the SPI slave driver instance.
+ *
+ * @param[in] p_instance Pointer to the instance structure.
+ */
+void nrf_drv_spis_uninit(nrf_drv_spis_t const * const p_instance);
+
+/** @brief Function for preparing the SPI slave instance for a single SPI transaction.
+ * 
+ * This function prepares the SPI slave device to be ready for a single SPI transaction. It configures 
+ * the SPI slave device to use the memory supplied with the function call in SPI transactions. 
+ * 
+ * When either the memory buffer configuration or the SPI transaction has been 
+ * completed, the event callback function will be called with the appropriate event 
+ * @ref nrf_drv_spis_event_type_t. Note that the callback function can be called before returning from 
+ * this function, because it is called from the SPI slave interrupt context.
+ *
+ * @note This function can be called from the callback function context.
+ *
+ * @note Client applications must call this function after every @ref NRF_DRV_SPIS_XFER_DONE event if 
+ * the SPI slave driver should be prepared for a possible new SPI transaction. 
+ *
+ * @note Peripherals that are using EasyDMA (for example, SPIS) require the transfer buffers
+ * to be placed in the Data RAM region. Otherwise, this function will fail
+ * with the error code NRF_ERROR_INVALID_ADDR.
+ *
+ * @param[in] p_instance            SPIS instance.
+ * @param[in] p_tx_buffer           Pointer to the TX buffer.
+ * @param[in] p_rx_buffer           Pointer to the RX buffer.
+ * @param[in] tx_buffer_length      Length of the TX buffer in bytes.
+ * @param[in] rx_buffer_length      Length of the RX buffer in bytes. 
+ *
+ * @retval NRF_SUCCESS              If the operation was successful.
+ * @retval NRF_ERROR_NULL           If the operation failed because a NULL pointer was supplied.   
+ * @retval NRF_ERROR_INVALID_STATE  If the operation failed because the SPI slave device is in an incorrect state.
+ * @retval NRF_ERROR_INVALID_ADDR   If the provided buffers are not placed in the Data
+ *                                  RAM region.
+ * @retval NRF_ERROR_INTERNAL       If the operation failed because of an internal error.
+ */
+ret_code_t nrf_drv_spis_buffers_set(nrf_drv_spis_t const * const  p_instance,
+                                    const uint8_t * p_tx_buffer, 
+                                    uint8_t   tx_buffer_length, 
+                                    uint8_t * p_rx_buffer, 
+                                    uint8_t   rx_buffer_length);
+
+#endif // SPI_SLAVE_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.c
new file mode 100644
index 0000000000..2ffdd36d6c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.c
@@ -0,0 +1,307 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_timer.h"
+#include "nrf_drv_common.h"
+#include "app_util_platform.h"
+
+#if (TIMER_COUNT == 0)
+    #error "No TIMER instances enabled in the driver configuration file."
+#endif
+
+
+/**@brief Timer control block. */
+typedef struct
+{
+    nrf_timer_event_handler_t handler;
+    void *                    context;
+    nrf_drv_state_t           state;
+} timer_control_block_t;
+
+static timer_control_block_t m_cb[TIMER_COUNT];
+
+static const nrf_drv_timer_config_t m_default_config[TIMER_COUNT] = {
+#if TIMER0_ENABLED
+    NRF_DRV_TIMER_DEFAULT_CONFIG(0),
+#endif
+#if TIMER1_ENABLED
+    NRF_DRV_TIMER_DEFAULT_CONFIG(1),
+#endif
+#if TIMER2_ENABLED
+    NRF_DRV_TIMER_DEFAULT_CONFIG(2),
+#endif
+#if TIMER3_ENABLED
+    NRF_DRV_TIMER_DEFAULT_CONFIG(3),
+#endif
+#if TIMER4_ENABLED
+    NRF_DRV_TIMER_DEFAULT_CONFIG(4),
+#endif
+};
+
+
+ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
+                              nrf_drv_timer_config_t const * p_config,
+                              nrf_timer_event_handler_t timer_event_handler)
+{
+    timer_control_block_t * p_cb = &m_cb[p_instance->instance_id];
+
+#ifdef SOFTDEVICE_PRESENT
+    ASSERT(p_instance->p_reg != NRF_TIMER0);
+#endif
+    ASSERT(NRF_TIMER_IS_BIT_WIDTH_VALID(p_instance->p_reg, p_config->bit_width));
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    if (timer_event_handler == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config[p_instance->instance_id];
+    }
+
+    p_cb->handler = timer_event_handler;
+    p_cb->context = p_config->p_context;
+
+    uint8_t i;
+    for (i = 0; i < p_instance->cc_channel_count; ++i)
+    {
+        nrf_timer_event_clear(p_instance->p_reg,
+            nrf_timer_compare_event_get(i));
+    }
+
+    nrf_drv_common_irq_enable(nrf_drv_get_IRQn(p_instance->p_reg),
+        p_config->interrupt_priority);
+
+    nrf_timer_mode_set(p_instance->p_reg, p_config->mode);
+    nrf_timer_bit_width_set(p_instance->p_reg, p_config->bit_width);
+    nrf_timer_frequency_set(p_instance->p_reg, p_config->frequency);
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance)
+{
+    nrf_drv_common_irq_disable(nrf_drv_get_IRQn(p_instance->p_reg));
+
+    #define DISABLE_ALL UINT32_MAX
+    nrf_timer_shorts_disable(p_instance->p_reg, DISABLE_ALL);
+    nrf_timer_int_disable(p_instance->p_reg, DISABLE_ALL);
+    #undef DISABLE_ALL
+
+    nrf_drv_timer_disable(p_instance);
+
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_INITIALIZED);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_POWERED_ON;
+}
+
+void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_SHUTDOWN);
+    m_cb[p_instance->instance_id].state = NRF_DRV_STATE_INITIALIZED;
+}
+
+void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_START);
+}
+
+void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_STOP);
+}
+
+void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_CLEAR);
+}
+
+void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    ASSERT(nrf_timer_mode_get(p_instance->p_reg) != NRF_TIMER_MODE_TIMER);
+
+    nrf_timer_task_trigger(p_instance->p_reg, NRF_TIMER_TASK_COUNT);
+}
+
+uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
+                               nrf_timer_cc_channel_t cc_channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state == NRF_DRV_STATE_POWERED_ON);
+    ASSERT(cc_channel < p_instance->cc_channel_count);
+
+    nrf_timer_task_trigger(p_instance->p_reg,
+        nrf_timer_capture_task_get(cc_channel));
+    return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
+}
+
+void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
+                           nrf_timer_cc_channel_t cc_channel,
+                           uint32_t               cc_value,
+                           bool                   enable_int)
+{
+    nrf_timer_int_mask_t timer_int = nrf_timer_compare_int_get(cc_channel);
+
+    if (enable_int)
+    {
+        nrf_timer_int_enable(p_instance->p_reg, timer_int);
+    }
+    else
+    {
+        nrf_timer_int_disable(p_instance->p_reg, timer_int);
+    }
+
+    nrf_timer_cc_write(p_instance->p_reg, cc_channel, cc_value);
+}
+
+void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
+                                    nrf_timer_cc_channel_t cc_channel,
+                                    uint32_t               cc_value,
+                                    nrf_timer_short_mask_t timer_short_mask,
+                                    bool                   enable_int)
+{
+    nrf_timer_shorts_disable(p_instance->p_reg,
+        (TIMER_SHORTS_COMPARE0_STOP_Msk  << cc_channel) |
+        (TIMER_SHORTS_COMPARE0_CLEAR_Msk << cc_channel));
+
+    nrf_timer_shorts_enable(p_instance->p_reg, timer_short_mask);
+
+    (void)nrf_drv_timer_compare(p_instance,
+                                cc_channel,
+                                cc_value,
+                                enable_int);
+}
+
+void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
+                                      uint32_t channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel < p_instance->cc_channel_count);
+
+    nrf_timer_event_clear(p_instance->p_reg,
+        nrf_timer_compare_event_get(channel));
+    nrf_timer_int_enable(p_instance->p_reg,
+        nrf_timer_compare_int_get(channel));
+}
+
+void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel)
+{
+    ASSERT(m_cb[p_instance->instance_id].state != NRF_DRV_STATE_UNINITIALIZED);
+    ASSERT(channel < p_instance->cc_channel_count);
+
+    nrf_timer_int_disable(p_instance->p_reg,
+        nrf_timer_compare_int_get(channel));
+}
+
+static void irq_handler(NRF_TIMER_Type * p_reg,
+                        timer_control_block_t * p_cb,
+                        uint8_t channel_count)
+{
+    uint8_t i;
+    for (i = 0; i < channel_count; ++i)
+    {
+        nrf_timer_event_t event = nrf_timer_compare_event_get(i);
+        nrf_timer_int_mask_t int_mask = nrf_timer_compare_int_get(i);
+
+        if (nrf_timer_event_check(p_reg, event) &&
+            nrf_timer_int_enable_check(p_reg, int_mask))
+        {
+            nrf_timer_event_clear(p_reg, event);
+            p_cb->handler(event, p_cb->context);
+        }
+    }
+}
+
+#if TIMER0_ENABLED
+void TIMER0_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER0, &m_cb[TIMER0_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(0));
+}
+#endif
+
+#if TIMER1_ENABLED
+void TIMER1_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER1, &m_cb[TIMER1_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(1));
+}
+#endif
+
+#if TIMER2_ENABLED
+void TIMER2_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER2, &m_cb[TIMER2_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(2));
+}
+#endif
+
+#if TIMER3_ENABLED
+void TIMER3_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER3, &m_cb[TIMER3_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(3));
+}
+#endif
+
+#if TIMER4_ENABLED
+void TIMER4_IRQHandler(void)
+{
+    irq_handler(NRF_TIMER4, &m_cb[TIMER4_INSTANCE_INDEX],
+        NRF_TIMER_CC_CHANNEL_COUNT(4));
+}
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.h
new file mode 100644
index 0000000000..bc6385c84c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/timer/nrf_drv_timer.h
@@ -0,0 +1,399 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ * @addtogroup nrf_timer Timer HAL and driver
+ * @ingroup    nrf_drivers
+ * @brief      Timer APIs.
+ * @details    The timer HAL provides basic APIs for accessing the registers
+ *             of the timer. The timer driver provides APIs on a higher level.
+ *
+ * @defgroup   lib_driver_timer Timer driver
+ * @{
+ * @ingroup    nrf_timer
+ * @brief      Multi-instance timer driver.
+ */
+
+#ifndef NRF_DRV_TIMER_H__
+#define NRF_DRV_TIMER_H__
+
+#include "nordic_common.h"
+#include "nrf_drv_config.h"
+#include "nrf_timer.h"
+#include "sdk_errors.h"
+#include "nrf_assert.h"
+
+/**
+ * @brief Timer driver instance data structure.
+ */
+typedef struct
+{
+    NRF_TIMER_Type * p_reg;            ///< Pointer to the structure with TIMER peripheral instance registers.
+    uint8_t          instance_id;      ///< Driver instance index.
+    uint8_t          cc_channel_count; ///< Number of capture/compare channels.
+} nrf_drv_timer_t;
+
+/**
+ * @brief Macro for creating a timer driver instance.
+ */
+#define NRF_DRV_TIMER_INSTANCE(id) \
+{                                                             \
+    .p_reg            = CONCAT_2(NRF_TIMER, id),              \
+    .instance_id      = CONCAT_3(TIMER, id, _INSTANCE_INDEX), \
+    .cc_channel_count = NRF_TIMER_CC_CHANNEL_COUNT(id),       \
+}
+
+/**
+ * @brief Timer driver instance configuration structure.
+ */
+typedef struct
+{
+    nrf_timer_frequency_t frequency;          ///< Frequency.
+    nrf_timer_mode_t      mode;               ///< Mode of operation.
+    nrf_timer_bit_width_t bit_width;          ///< Bit width.
+    uint8_t               interrupt_priority; ///< Interrupt priority.
+    void *                p_context;          ///< Context passed to interrupt handler.
+} nrf_drv_timer_config_t;
+
+#define TIMER_CONFIG_FREQUENCY(id)    CONCAT_3(TIMER, id, _CONFIG_FREQUENCY)
+#define TIMER_CONFIG_MODE(id)         CONCAT_3(TIMER, id, _CONFIG_MODE)
+#define TIMER_CONFIG_BIT_WIDTH(id)    CONCAT_3(TIMER, id, _CONFIG_BIT_WIDTH)
+#define TIMER_CONFIG_IRQ_PRIORITY(id) CONCAT_3(TIMER, id, _CONFIG_IRQ_PRIORITY)
+
+/**
+ * @brief Timer driver instance default configuration.
+ */
+#define NRF_DRV_TIMER_DEFAULT_CONFIG(id) \
+{                                                                            \
+    .frequency          = TIMER_CONFIG_FREQUENCY(id),                        \
+    .mode               = (nrf_timer_mode_t)TIMER_CONFIG_MODE(id),           \
+    .bit_width          = (nrf_timer_bit_width_t)TIMER_CONFIG_BIT_WIDTH(id), \
+    .interrupt_priority = TIMER_CONFIG_IRQ_PRIORITY(id),                     \
+    .p_context          = NULL                                               \
+}
+
+/**
+ * @brief Timer driver event handler type.
+ *
+ * @param[in] event_type Timer event.
+ * @param[in] p_context  General purpose parameter set during initialization of
+ *                       the timer. This parameter can be used to pass 
+ *                       additional information to the handler function, for 
+ *                       example, the timer ID.
+ */
+typedef void (* nrf_timer_event_handler_t)(nrf_timer_event_t event_type,
+                                           void * p_context);
+
+/**
+ * @brief Function for initializing the timer.
+ *
+ * @param[in] p_instance          Timer instance.
+ * @param[in] p_config            Initial configuration.
+ *                                If NULL, the default configuration is used.
+ * @param[in] timer_event_handler Event handler provided by the user.
+ *                                Must not be NULL.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the instance is already initialized.
+ * @retval NRF_ERROR_INVALID_PARAM If no handler was provided.
+ */
+ret_code_t nrf_drv_timer_init(nrf_drv_timer_t const * const p_instance,
+                              nrf_drv_timer_config_t const * p_config,
+                              nrf_timer_event_handler_t timer_event_handler);
+
+/**
+ * @brief Function for uninitializing the timer.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_uninit(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for turning on the timer.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_enable(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for turning off the timer.
+ *
+ * Note that the timer will allow to enter the lowest possible SYSTEM_ON state 
+ * only after this function is called.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_disable(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for pausing the timer.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_pause(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for resuming the timer.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_resume(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for clearing the timer.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_clear(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for incrementing the timer.
+ *
+ * @param[in] p_instance Timer instance.
+ */
+void nrf_drv_timer_increment(nrf_drv_timer_t const * const p_instance);
+
+/**
+ * @brief Function for returning the address of a specific timer task.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] timer_task Timer task.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_task_t timer_task);
+
+/**
+ * @brief Function for returning the address of a specific timer capture task.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] channel    Capture channel number.
+ *
+ * @return Task address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel);
+
+/**
+ * @brief Function for returning the address of a specific timer event.
+ *
+ * @param[in] p_instance  Timer instance.
+ * @param[in] timer_event Timer event.
+ *
+ * @return Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_event_t timer_event);
+
+/**
+ * @brief Function for returning the address of a specific timer compare event.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] channel    Compare channel number.
+ *
+ * @return Event address.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel);
+
+/**
+ * @brief Function for capturing the timer value.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] cc_channel Capture channel number.
+ *
+ * @return Captured value.
+ */
+uint32_t nrf_drv_timer_capture(nrf_drv_timer_t const * const p_instance,
+                               nrf_timer_cc_channel_t cc_channel);
+
+/**
+ * @brief Function for returning the capture value from a specific channel.
+ *
+ * Use this function to read channel values when PPI is used for capturing.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] cc_channel Capture channel number.
+ *
+ * @return Captured value.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_cc_channel_t cc_channel);
+
+/**
+ * @brief Function for setting the timer channel in compare mode.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] cc_channel Compare channel number.
+ * @param[in] cc_value   Compare value.
+ * @param[in] enable_int Enable or disable the interrupt for the compare channel.
+ */
+void nrf_drv_timer_compare(nrf_drv_timer_t const * const p_instance,
+                           nrf_timer_cc_channel_t cc_channel,
+                           uint32_t               cc_value,
+                           bool                   enable_int);
+
+/**
+ * @brief Function for setting the timer channel in extended compare mode.
+ *
+ * @param[in] p_instance       Timer instance.
+ * @param[in] cc_channel       Compare channel number.
+ * @param[in] cc_value         Compare value.
+ * @param[in] timer_short_mask Shortcut between the compare event on the channel
+ *                             and the timer task (STOP or CLEAR).
+ * @param[in] enable_int       Enable or disable the interrupt for the compare
+ *                             channel.
+ */
+void nrf_drv_timer_extended_compare(nrf_drv_timer_t const * const p_instance,
+                                    nrf_timer_cc_channel_t cc_channel,
+                                    uint32_t               cc_value,
+                                    nrf_timer_short_mask_t timer_short_mask,
+                                    bool                   enable_int);
+
+/**
+ * @brief Function for converting time in microseconds to timer ticks.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] time_us    Time in microseconds.
+ *
+ * @return Number of ticks.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t time_us);
+
+/**
+ * @brief Function for converting time in milliseconds to timer ticks.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] time_ms    Time in milliseconds.
+ *
+ * @return Number of ticks.
+ */
+__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t time_ms);
+
+/**
+ * @brief Function for enabling timer compare interrupt.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] channel    Compare channel.
+ */
+void nrf_drv_timer_compare_int_enable(nrf_drv_timer_t const * const p_instance,
+                                      uint32_t channel);
+
+/**
+ * @brief Function for disabling timer compare interrupt.
+ *
+ * @param[in] p_instance Timer instance.
+ * @param[in] channel    Compare channel.
+ */
+void nrf_drv_timer_compare_int_disable(nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel);
+
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE uint32_t nrf_drv_timer_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_task_t timer_task)
+{
+    return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg, timer_task);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_task_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel)
+{
+    ASSERT(channel < p_instance->cc_channel_count);
+    return (uint32_t)nrf_timer_task_address_get(p_instance->p_reg,
+                         nrf_timer_capture_task_get(channel));
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_event_t timer_event)
+{
+    return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg, timer_event);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_compare_event_address_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t channel)
+{
+    ASSERT(channel < p_instance->cc_channel_count);
+    return (uint32_t)nrf_timer_event_address_get(p_instance->p_reg,
+                         nrf_timer_compare_event_get(channel));
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_capture_get(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       nrf_timer_cc_channel_t cc_channel)
+{
+    return nrf_timer_cc_read(p_instance->p_reg, cc_channel);
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_us_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t timer_us)
+{
+    return nrf_timer_us_to_ticks(timer_us,
+        nrf_timer_frequency_get(p_instance->p_reg));
+}
+
+__STATIC_INLINE uint32_t nrf_drv_timer_ms_to_ticks(
+                                       nrf_drv_timer_t const * const p_instance,
+                                       uint32_t timer_ms)
+{
+    return nrf_timer_ms_to_ticks(timer_ms,
+        nrf_timer_frequency_get(p_instance->p_reg));
+}
+
+#endif // SUPPRESS_INLINE_IMPLEMENTATION
+
+#endif // NRF_DRV_TIMER_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/twi_master/nrf_drv_twi.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/twi_master/nrf_drv_twi.c
new file mode 100644
index 0000000000..a70c39e73d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/twi_master/nrf_drv_twi.c
@@ -0,0 +1,1005 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "nrf_drv_twi.h"
+#include "nrf_drv_common.h"
+#include "nrf_gpio.h"
+#include "nrf_assert.h"
+#include "app_util_platform.h"
+#include "nrf_delay.h"
+
+#include <stdio.h>
+
+#define TWI0_IRQ_HANDLER    SPI0_TWI0_IRQHandler
+#define TWI1_IRQ_HANDLER    SPI1_TWI1_IRQHandler
+
+#if (defined(TWIM_IN_USE) && defined(TWI_IN_USE))
+    // TWIM and TWI combined
+    #define CODE_FOR_TWIM(code) if (p_instance->use_easy_dma) { code }
+    #define CODE_FOR_TWI(code)  else { code }
+#elif (defined(TWIM_IN_USE) && !defined(TWI_IN_USE))
+    // TWIM only
+    #define CODE_FOR_TWIM(code) { code }
+    #define CODE_FOR_TWI(code)
+#elif (!defined(TWIM_IN_USE) && defined(TWI_IN_USE))
+    // TWI only
+    #define CODE_FOR_TWIM(code)
+    #define CODE_FOR_TWI(code)  { code }
+#else
+    #error "Wrong configuration."
+#endif
+
+// All interrupt flags
+#define DISABLE_ALL  0xFFFFFFFF
+
+#define SCL_PIN_CONF        ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)    \
+                            | (GPIO_PIN_CNF_DRIVE_S0D1     << GPIO_PIN_CNF_DRIVE_Pos)   \
+                            | (GPIO_PIN_CNF_PULL_Pullup    << GPIO_PIN_CNF_PULL_Pos)    \
+                            | (GPIO_PIN_CNF_INPUT_Connect  << GPIO_PIN_CNF_INPUT_Pos)   \
+                            | (GPIO_PIN_CNF_DIR_Input      << GPIO_PIN_CNF_DIR_Pos))
+
+#define SDA_PIN_CONF        SCL_PIN_CONF
+
+#define SCL_PIN_CONF_CLR    ((GPIO_PIN_CNF_SENSE_Disabled << GPIO_PIN_CNF_SENSE_Pos)    \
+                            | (GPIO_PIN_CNF_DRIVE_S0D1     << GPIO_PIN_CNF_DRIVE_Pos)   \
+                            | (GPIO_PIN_CNF_PULL_Pullup    << GPIO_PIN_CNF_PULL_Pos)    \
+                            | (GPIO_PIN_CNF_INPUT_Connect  << GPIO_PIN_CNF_INPUT_Pos)   \
+                            | (GPIO_PIN_CNF_DIR_Output     << GPIO_PIN_CNF_DIR_Pos))
+
+#define SDA_PIN_CONF_CLR    SCL_PIN_CONF_CLR
+
+// Control block - driver instance local data.
+typedef struct
+{
+    nrf_drv_twi_evt_handler_t handler;
+    void *                    p_context;
+    volatile uint32_t         int_mask;
+    nrf_drv_twi_xfer_desc_t   xfer_desc;
+    uint32_t                  flags;
+    uint8_t *                 p_curr_buf;
+    uint8_t                   curr_length;
+    bool                      curr_no_stop;
+    nrf_drv_state_t           state;
+    bool                      error;
+    volatile bool             busy;
+    bool                      repeated;
+    uint8_t                   bytes_transferred;
+} twi_control_block_t;
+
+static twi_control_block_t m_cb[TWI_COUNT];
+
+static nrf_drv_twi_config_t const m_default_config[TWI_COUNT] = {
+#if TWI0_ENABLED
+    NRF_DRV_TWI_DEFAULT_CONFIG(0),
+#endif
+#if TWI1_ENABLED
+    NRF_DRV_TWI_DEFAULT_CONFIG(1),
+#endif
+};
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    #define IRQ_HANDLER_NAME(n) irq_handler_for_instance_##n
+    #define IRQ_HANDLER(n)      static void IRQ_HANDLER_NAME(n)(void)
+
+    #if TWI0_ENABLED
+        IRQ_HANDLER(0);
+    #endif
+    #if TWI1_ENABLED
+        IRQ_HANDLER(1);
+    #endif
+    static nrf_drv_irq_handler_t const m_irq_handlers[TWI_COUNT] = {
+    #if TWI0_ENABLED
+        IRQ_HANDLER_NAME(0),
+    #endif
+    #if TWI1_ENABLED
+        IRQ_HANDLER_NAME(1),
+    #endif
+    };
+#else
+    #define IRQ_HANDLER(n) void SPI##n##_TWI##n##_IRQHandler(void)
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+static void twi_clear_bus(nrf_drv_twi_t const * const p_instance,
+                          nrf_drv_twi_config_t const * p_config)
+{
+    NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_CONF;
+    NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_CONF;
+
+    nrf_gpio_pin_set(p_config->scl);
+    nrf_gpio_pin_set(p_config->sda);
+
+    NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_CONF_CLR;
+    NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_CONF_CLR;
+
+    nrf_delay_us(4);
+
+    for(int i = 0; i < 9; i++)
+    {
+        if (nrf_gpio_pin_read(p_config->sda))
+        {
+            if(i == 0)
+            {
+                return;
+            }
+            else
+            {
+                break;
+            }
+        }
+        nrf_gpio_pin_clear(p_config->scl);
+        nrf_delay_us(4);
+        nrf_gpio_pin_set(p_config->scl);
+        nrf_delay_us(4);
+    }
+    nrf_gpio_pin_clear(p_config->sda);
+    nrf_delay_us(4);
+    nrf_gpio_pin_set(p_config->sda);
+}
+
+ret_code_t nrf_drv_twi_init(nrf_drv_twi_t const *        p_instance,
+                            nrf_drv_twi_config_t const * p_config,
+                            nrf_drv_twi_evt_handler_t    event_handler,
+                            void *                       p_context)
+{
+    twi_control_block_t * p_cb  = &m_cb[p_instance->drv_inst_idx];
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    if (p_config == NULL)
+    {
+        p_config = &m_default_config[p_instance->drv_inst_idx];
+    }
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    if (nrf_drv_common_per_res_acquire(p_instance->reg.p_twi,
+            m_irq_handlers[p_instance->drv_inst_idx]) != NRF_SUCCESS)
+    {
+        return NRF_ERROR_BUSY;
+    }
+#endif // PERIPHERAL_RESOURCE_SHARING_ENABLED
+
+    p_cb->handler   = event_handler;
+    p_cb->p_context = p_context;
+    p_cb->int_mask  = 0;
+    p_cb->repeated  = false;
+    p_cb->busy      = false;
+
+    twi_clear_bus(p_instance, p_config);
+
+    /* To secure correct signal levels on the pins used by the TWI
+       master when the system is in OFF mode, and when the TWI master is
+       disabled, these pins must be configured in the GPIO peripheral.
+    */
+    NRF_GPIO->PIN_CNF[p_config->scl] = SCL_PIN_CONF;
+    NRF_GPIO->PIN_CNF[p_config->sda] = SDA_PIN_CONF;
+
+    CODE_FOR_TWIM
+    (
+        NRF_TWIM_Type * p_twim = p_instance->reg.p_twim;
+        nrf_twim_pins_set(p_twim, p_config->scl, p_config->sda);
+        nrf_twim_frequency_set(p_twim,
+            (nrf_twim_frequency_t)p_config->frequency);
+    )
+    CODE_FOR_TWI
+    (
+        NRF_TWI_Type * p_twi = p_instance->reg.p_twi;
+        nrf_twi_pins_set(p_twi, p_config->scl, p_config->sda);
+        nrf_twi_frequency_set(p_twi,
+            (nrf_twi_frequency_t)p_config->frequency);
+    )
+
+    if (p_cb->handler)
+    {
+        CODE_FOR_TWIM
+        (
+            nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twim),
+                p_config->interrupt_priority);
+        )
+        CODE_FOR_TWI
+        (
+            nrf_drv_common_irq_enable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twi),
+                p_config->interrupt_priority);
+        )
+    }
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+void nrf_drv_twi_uninit(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    if (p_cb->handler)
+    {
+        CODE_FOR_TWIM
+        (
+            nrf_drv_common_irq_disable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twim));
+        )
+        CODE_FOR_TWI
+        (
+            nrf_drv_common_irq_disable(nrf_drv_get_IRQn((void *)p_instance->reg.p_twi));
+        )
+    }
+    nrf_drv_twi_disable(p_instance);
+
+#if PERIPHERAL_RESOURCE_SHARING_ENABLED
+    nrf_drv_common_per_res_release(p_instance->reg.p_twi);
+#endif
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+}
+
+void nrf_drv_twi_enable(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state == NRF_DRV_STATE_INITIALIZED);
+
+    CODE_FOR_TWIM
+    (
+        NRF_TWIM_Type * p_twim = p_instance->reg.p_twim;
+
+        nrf_twim_enable(p_twim);
+    )
+    CODE_FOR_TWI
+    (
+        NRF_TWI_Type * p_twi = p_instance->reg.p_twi;
+
+        nrf_twi_enable(p_twi);
+    )
+
+    p_cb->state = NRF_DRV_STATE_POWERED_ON;
+}
+
+void nrf_drv_twi_disable(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    CODE_FOR_TWIM
+    (
+        NRF_TWIM_Type * p_twim = p_instance->reg.p_twim;
+        p_cb->int_mask = 0;
+        nrf_twim_int_disable(p_twim, DISABLE_ALL);
+        nrf_twim_shorts_disable(p_twim, DISABLE_ALL);
+        nrf_twim_disable(p_twim);
+    )
+    CODE_FOR_TWI
+    (
+        NRF_TWI_Type * p_twi = p_instance->reg.p_twi;
+        nrf_twi_int_disable(p_twi, DISABLE_ALL);
+        nrf_twi_shorts_disable(p_twi, DISABLE_ALL);
+        nrf_twi_disable(p_twi);
+    )
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+}
+
+#ifdef TWI_IN_USE
+static bool twi_send_byte(NRF_TWI_Type  * p_twi,
+                          uint8_t const * p_data,
+                          uint8_t         length,
+                          uint8_t       * p_bytes_transferred,
+                          bool            no_stop)
+{
+    if (*p_bytes_transferred < length)
+    {
+        nrf_twi_txd_set(p_twi, p_data[*p_bytes_transferred]);
+        ++(*p_bytes_transferred);
+    }
+    else
+    {
+        if (no_stop)
+        {
+            nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_SUSPEND);
+            return false;
+        }
+        else
+        {
+            nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+        }
+    }
+    return true;
+}
+
+static void twi_receive_byte(NRF_TWI_Type * p_twi,
+                             uint8_t      * p_data,
+                             uint8_t        length,
+                             uint8_t      * p_bytes_transferred)
+{
+    if (*p_bytes_transferred < length)
+    {
+        p_data[*p_bytes_transferred] = nrf_twi_rxd_get(p_twi);
+
+        ++(*p_bytes_transferred);
+
+        if (*p_bytes_transferred == length-1)
+        {
+            nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK);
+        }
+        else if (*p_bytes_transferred == length)
+        {
+            return;
+        }
+
+        nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
+    }
+}
+
+static bool twi_transfer(NRF_TWI_Type  * p_twi,
+                         bool          * p_error,
+                         uint8_t       * p_bytes_transferred,
+                         uint8_t       * p_data,
+                         uint8_t         length,
+                         bool            no_stop)
+{
+    bool do_stop_check;
+
+    if ((*p_error == true) || (*p_bytes_transferred == length))
+    {
+        do_stop_check = true;
+    }
+    else
+    {
+        do_stop_check = false;
+    }
+
+    if (*p_error)
+    {
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+    }
+    else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
+    {
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+        nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+        *p_error = true;
+    }
+    else
+    {
+        if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_TXDSENT))
+        {
+            nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+            if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
+            {
+                nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+                nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+                *p_error = true;
+            }
+            else
+            {
+                if (!twi_send_byte(p_twi, p_data, length, p_bytes_transferred, no_stop))
+                {
+                    return false;
+                }
+            }
+        }
+        else if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_RXDREADY))
+        {
+            nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+            if (nrf_twi_event_check(p_twi, NRF_TWI_EVENT_ERROR))
+            {
+                nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+                nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STOP);
+                *p_error = true;
+            }
+            else
+            {
+                twi_receive_byte(p_twi, p_data, length, p_bytes_transferred);
+            }
+        }
+    }
+
+    if (do_stop_check && nrf_twi_event_check(p_twi, NRF_TWI_EVENT_STOPPED))
+    {
+        nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+        return false;
+    }
+
+    return true;
+}
+
+static ret_code_t twi_tx_start_transfer(twi_control_block_t * p_cb,
+                                        NRF_TWI_Type *        p_twi,
+                                        uint8_t const *       p_data,
+                                        uint8_t               length,
+                                        bool                  no_stop)
+{
+    ret_code_t ret_code = NRF_SUCCESS;
+
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+    nrf_twi_shorts_set(p_twi, 0);
+
+    p_cb->bytes_transferred = 0;
+    p_cb->error             = false;
+
+    // In case TWI is suspended resume its operation.
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTTX);
+
+    (void)twi_send_byte(p_twi, p_data, length, &p_cb->bytes_transferred, no_stop);
+
+    if (p_cb->handler)
+    {
+        p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK   |
+                        NRF_TWI_INT_ERROR_MASK     |
+                        NRF_TWI_INT_TXDSENT_MASK   |
+                        NRF_TWI_INT_RXDREADY_MASK;
+        nrf_twi_int_enable(p_twi, p_cb->int_mask);
+    }
+    else
+    {
+        while (twi_transfer(p_twi, &p_cb->error, &p_cb->bytes_transferred, (uint8_t *)p_data, length, no_stop))
+        {}
+
+        if (p_cb->error)
+        {
+            ret_code = NRF_ERROR_INTERNAL;
+        }
+    }
+    return ret_code;
+}
+
+static ret_code_t twi_rx_start_transfer(twi_control_block_t * p_cb,
+                                        NRF_TWI_Type *        p_twi,
+                                        uint8_t const *       p_data,
+                                        uint8_t               length)
+{
+    ret_code_t ret_code = NRF_SUCCESS;
+
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_STOPPED);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_ERROR);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_TXDSENT);
+    nrf_twi_event_clear(p_twi, NRF_TWI_EVENT_RXDREADY);
+
+    p_cb->bytes_transferred = 0;
+    p_cb->error             = false;
+
+    if (length == 1)
+    {
+        nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_STOP_MASK);
+    }
+    else
+    {
+        nrf_twi_shorts_set(p_twi, NRF_TWI_SHORT_BB_SUSPEND_MASK);
+    }
+    // In case TWI is suspended resume its operation.
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_RESUME);
+    nrf_twi_task_trigger(p_twi, NRF_TWI_TASK_STARTRX);
+
+    if (p_cb->handler)
+    {
+        p_cb->int_mask = NRF_TWI_INT_STOPPED_MASK   |
+                        NRF_TWI_INT_ERROR_MASK     |
+                        NRF_TWI_INT_TXDSENT_MASK   |
+                        NRF_TWI_INT_RXDREADY_MASK;
+        nrf_twi_int_enable(p_twi, p_cb->int_mask);
+    }
+    else
+    {
+        while (twi_transfer(p_twi, &p_cb->error, &p_cb->bytes_transferred, (uint8_t*)p_data, length, false))
+        {}
+
+        if (p_cb->error)
+        {
+            ret_code = NRF_ERROR_INTERNAL;
+        }
+    }
+    return ret_code;
+}
+
+__STATIC_INLINE ret_code_t twi_xfer(twi_control_block_t           * p_cb,
+                                    NRF_TWI_Type                  * p_twi,
+                                    nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                                    uint32_t                        flags)
+{
+    ret_code_t ret = NRF_SUCCESS;
+
+    /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */
+    nrf_twi_int_disable(p_twi, DISABLE_ALL);
+
+    if (p_cb->busy)
+    {
+        nrf_twi_int_enable(p_twi, p_cb->int_mask);
+        return NRF_ERROR_BUSY;
+    }
+    else
+    {
+        p_cb->busy = (NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER & flags) ? false : true;
+    }
+
+    if (flags & NRF_DRV_TWI_FLAG_HOLD_XFER)
+    {
+        return NRF_ERROR_NOT_SUPPORTED;
+    }
+
+    p_cb->flags       = flags;
+    p_cb->xfer_desc   = *p_xfer_desc;
+    p_cb->curr_length = p_xfer_desc->primary_length;
+    p_cb->p_curr_buf  = p_xfer_desc->p_primary_buf;
+    nrf_twi_address_set(p_twi, p_xfer_desc->address);
+
+    if (p_xfer_desc->type != NRF_DRV_TWI_XFER_RX)
+    {
+        p_cb->curr_no_stop = ((p_xfer_desc->type == NRF_DRV_TWI_XFER_TX) &&
+                             !(flags & NRF_DRV_TWI_FLAG_TX_NO_STOP)) ? false : true;
+        ret = twi_tx_start_transfer(p_cb, p_twi, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length, p_cb->curr_no_stop);
+    }
+    else
+    {
+        p_cb->curr_no_stop = false;
+        ret = twi_rx_start_transfer(p_cb, p_twi, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+    }
+    if (p_cb->handler == NULL)
+    {
+        p_cb->busy = false;
+    }
+    return ret;
+}
+#endif
+
+#ifdef TWIM_IN_USE
+__STATIC_INLINE void twim_list_enable_handle(NRF_TWIM_Type * p_twim, uint32_t flags)
+{
+    if (NRF_DRV_TWI_FLAG_TX_POSTINC & flags)
+    {
+        nrf_twim_tx_list_enable(p_twim);
+    }
+    else
+    {
+        nrf_twim_tx_list_disable(p_twim);
+    }
+
+    if (NRF_DRV_TWI_FLAG_RX_POSTINC & flags)
+    {
+        nrf_twim_rx_list_enable(p_twim);
+    }
+    else
+    {
+        nrf_twim_rx_list_disable(p_twim);
+    }
+#ifndef NRF52_PAN_46
+#endif
+}
+__STATIC_INLINE ret_code_t twim_xfer(twi_control_block_t           * p_cb,
+                                     NRF_TWIM_Type                 * p_twim,
+                                     nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                                     uint32_t                        flags)
+{
+    ret_code_t ret = NRF_SUCCESS;
+    nrf_twim_task_t  start_task = NRF_TWIM_TASK_STARTTX;
+    nrf_twim_event_t evt_to_wait = NRF_TWIM_EVENT_STOPPED;
+
+    if (!nrf_drv_is_in_RAM(p_xfer_desc->p_primary_buf))
+    {
+        return NRF_ERROR_INVALID_ADDR;
+    }
+    /* Block TWI interrupts to ensure that function is not interrupted by TWI interrupt. */
+    nrf_twim_int_disable(p_twim, DISABLE_ALL);
+    if (p_cb->busy)
+    {
+        nrf_twim_int_enable(p_twim, p_cb->int_mask);
+        return NRF_ERROR_BUSY;
+    }
+    else
+    {
+
+        p_cb->busy = ((NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER & flags) ||
+                      (NRF_DRV_TWI_FLAG_REPEATED_XFER & flags)) ? false: true;
+    }
+
+    p_cb->xfer_desc = *p_xfer_desc;
+    p_cb->repeated = (flags & NRF_DRV_TWI_FLAG_REPEATED_XFER) ? true : false;
+    nrf_twim_address_set(p_twim, p_xfer_desc->address);
+
+    nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
+    nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+
+    twim_list_enable_handle(p_twim, flags);
+    switch (p_xfer_desc->type)
+    {
+    case NRF_DRV_TWI_XFER_TXTX:
+        ASSERT(!(flags & NRF_DRV_TWI_FLAG_REPEATED_XFER));
+        ASSERT(!(flags & NRF_DRV_TWI_FLAG_HOLD_XFER));
+        ASSERT(!(flags & NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER));
+        if (!nrf_drv_is_in_RAM(p_xfer_desc->p_secondary_buf))
+        {
+            return NRF_ERROR_INVALID_ADDR;
+        }
+        nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK);
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX);
+        while(!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_TXSTARTED))
+        {}
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_TXSTARTED);
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length);
+        p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        break;
+    case NRF_DRV_TWI_XFER_TXRX:
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_secondary_buf, p_xfer_desc->secondary_length);
+        nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STARTRX_MASK |
+                                    NRF_TWIM_SHORT_LASTRX_STOP_MASK);
+        p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        break;
+    case NRF_DRV_TWI_XFER_TX:
+        nrf_twim_tx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        if (NRF_DRV_TWI_FLAG_TX_NO_STOP & flags)
+        {
+            nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_SUSPEND_MASK);
+            p_cb->int_mask = NRF_TWIM_INT_SUSPENDED_MASK | NRF_TWIM_INT_ERROR_MASK;
+            nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+            evt_to_wait = NRF_TWIM_EVENT_SUSPENDED;
+        }
+        else
+        {
+            nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK);
+            p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        }
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+        break;
+    case NRF_DRV_TWI_XFER_RX:
+        nrf_twim_rx_buffer_set(p_twim, p_xfer_desc->p_primary_buf, p_xfer_desc->primary_length);
+        nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTRX_STOP_MASK);
+        p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+        start_task = NRF_TWIM_TASK_STARTRX;
+        nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+        break;
+    default:
+        ret = NRF_ERROR_INVALID_PARAM;
+        break;
+    }
+
+    if (!(flags & NRF_DRV_TWI_FLAG_HOLD_XFER) && (p_xfer_desc->type != NRF_DRV_TWI_XFER_TXTX))
+    {
+        nrf_twim_task_trigger(p_twim, start_task);
+    }
+
+    if (p_cb->handler)
+    {
+        if (flags & NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER)
+        {
+            p_cb->int_mask = NRF_TWIM_INT_ERROR_MASK;
+        }
+        nrf_twim_int_enable(p_twim, p_cb->int_mask);
+    }
+    else
+    {
+        while (!nrf_twim_event_check(p_twim, evt_to_wait))
+        {
+            if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR))
+            {
+                nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+                nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+                nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+                evt_to_wait = NRF_TWIM_EVENT_STOPPED;
+            }
+        }
+
+        uint32_t errorsrc =  nrf_twim_errorsrc_get_and_clear(p_twim);
+
+        p_cb->busy = false;
+
+        if (errorsrc)
+        {
+            ret = NRF_ERROR_INTERNAL;
+        }
+    }
+    return ret;
+}
+#endif
+
+ret_code_t nrf_drv_twi_xfer(nrf_drv_twi_t           const * p_instance,
+                            nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags)
+{
+    ret_code_t ret = NRF_SUCCESS;
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+
+    // TXRX and TXTX transfers are support only in non-blocking mode.
+    ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRF_DRV_TWI_XFER_TXRX)));
+    ASSERT( !((p_cb->handler == NULL) && (p_xfer_desc->type == NRF_DRV_TWI_XFER_TXTX)));
+
+    CODE_FOR_TWIM
+    (
+        ret = twim_xfer(p_cb, (NRF_TWIM_Type *)p_instance->reg.p_twim, p_xfer_desc, flags);
+    )
+    CODE_FOR_TWI
+    (
+        if ( (NRF_DRV_TWI_FLAG_TX_POSTINC | NRF_DRV_TWI_FLAG_RX_POSTINC) & flags)
+        {
+            return NRF_ERROR_NOT_SUPPORTED;
+        }
+        ret = twi_xfer(p_cb, (NRF_TWI_Type  *)p_instance->reg.p_twi, p_xfer_desc, flags);
+    )
+    return ret;
+}
+
+bool nrf_drv_twi_is_busy(nrf_drv_twi_t const * p_instance)
+{
+    twi_control_block_t * p_cb = &m_cb[p_instance->drv_inst_idx];
+    return p_cb->busy;
+}
+
+ret_code_t nrf_drv_twi_tx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t const *       p_data,
+                          uint8_t               length,
+                          bool                  no_stop)
+{
+    nrf_drv_twi_xfer_desc_t xfer = NRF_DRV_TWI_XFER_DESC_TX(address, (uint8_t*)p_data, length);
+
+    return nrf_drv_twi_xfer(p_instance, &xfer, no_stop ? NRF_DRV_TWI_FLAG_TX_NO_STOP : 0);
+}
+
+ret_code_t nrf_drv_twi_rx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t *             p_data,
+                          uint8_t               length)
+{
+    nrf_drv_twi_xfer_desc_t xfer = NRF_DRV_TWI_XFER_DESC_RX(address, p_data, length);
+    return nrf_drv_twi_xfer(p_instance, &xfer, 0);
+}
+
+uint32_t nrf_drv_twi_data_count_get(nrf_drv_twi_t const * const p_instance)
+{
+    CODE_FOR_TWIM
+    (
+        ASSERT(false);
+        return 0;
+    )
+    CODE_FOR_TWI
+    (
+        return m_cb[p_instance->drv_inst_idx].bytes_transferred;
+    )
+}
+uint32_t nrf_drv_twi_start_task_get(nrf_drv_twi_t const * p_instance, nrf_drv_twi_xfer_type_t xfer_type)
+{
+    CODE_FOR_TWIM
+    (
+        return (uint32_t)nrf_twim_task_address_get(p_instance->reg.p_twim,
+            (xfer_type != NRF_DRV_TWI_XFER_RX) ? NRF_TWIM_TASK_STARTTX : NRF_TWIM_TASK_STARTRX);
+    )
+    CODE_FOR_TWI
+    (
+        return (uint32_t)nrf_twi_task_address_get(p_instance->reg.p_twi,
+                (xfer_type != NRF_DRV_TWI_XFER_RX) ? NRF_TWI_TASK_STARTTX : NRF_TWI_TASK_STARTRX);
+    )
+}
+
+uint32_t nrf_drv_twi_stopped_event_get(nrf_drv_twi_t const * p_instance)
+{
+    CODE_FOR_TWIM
+    (
+        return (uint32_t)nrf_twim_event_address_get(p_instance->reg.p_twim, NRF_TWIM_EVENT_STOPPED);
+    )
+    CODE_FOR_TWI
+    (
+        return (uint32_t)nrf_twi_event_address_get(p_instance->reg.p_twi, NRF_TWI_EVENT_STOPPED);
+    )
+}
+
+#ifdef TWIM_IN_USE
+static void irq_handler_twim(NRF_TWIM_Type * p_twim, twi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_ERROR))
+    {
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_ERROR);
+        if (!nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED))
+        {
+            nrf_twim_int_disable(p_twim, p_cb->int_mask);
+            p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK;
+            nrf_twim_int_enable(p_twim, p_cb->int_mask);
+
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STOP);
+            return;
+        }
+    }
+
+    nrf_drv_twi_evt_t event;
+
+    if (nrf_twim_event_check(p_twim, NRF_TWIM_EVENT_STOPPED))
+    {
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_STOPPED);
+        event.xfer_desc = p_cb->xfer_desc;
+        if (p_cb->error)
+        {
+
+            event.xfer_desc.primary_length = (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_RX) ?
+                (uint8_t)nrf_twim_rxd_amount_get(p_twim) : (uint8_t)nrf_twim_txd_amount_get(p_twim);
+            event.xfer_desc.secondary_length = (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXRX) ?
+                (uint8_t)nrf_twim_rxd_amount_get(p_twim) : (uint8_t)nrf_twim_txd_amount_get(p_twim);
+
+        }
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTTX);
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_LASTRX);
+        if (!p_cb->repeated || p_cb->error)
+        {
+            nrf_twim_shorts_set(p_twim, 0);
+            p_cb->int_mask = 0;
+            nrf_twim_int_disable(p_twim, DISABLE_ALL);
+        }
+    }
+    else
+    {
+        nrf_twim_event_clear(p_twim, NRF_TWIM_EVENT_SUSPENDED);
+        if (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TX)
+        {
+            event.xfer_desc = p_cb->xfer_desc;
+            if (!p_cb->repeated)
+            {
+                nrf_twim_shorts_set(p_twim, 0);
+                p_cb->int_mask = 0;
+                nrf_twim_int_disable(p_twim, DISABLE_ALL);
+            }
+        }
+        else
+        {
+            nrf_twim_shorts_set(p_twim, NRF_TWIM_SHORT_LASTTX_STOP_MASK);
+            p_cb->int_mask = NRF_TWIM_INT_STOPPED_MASK | NRF_TWIM_INT_ERROR_MASK;
+            nrf_twim_int_disable(p_twim, DISABLE_ALL);
+            nrf_twim_int_enable(p_twim, p_cb->int_mask);
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_STARTTX);
+            nrf_twim_task_trigger(p_twim, NRF_TWIM_TASK_RESUME);
+            return;
+        }
+    }
+
+    uint32_t errorsrc = nrf_twim_errorsrc_get_and_clear(p_twim);
+    if (errorsrc & NRF_TWIM_ERROR_ADDRESS_NACK)
+    {
+        event.type = NRF_DRV_TWI_EVT_ADDRESS_NACK;
+    }
+    else if (errorsrc & NRF_TWIM_ERROR_DATA_NACK)
+    {
+        event.type = NRF_DRV_TWI_EVT_DATA_NACK;
+    }
+    else
+    {
+        event.type = NRF_DRV_TWI_EVT_DONE;
+    }
+
+    if (!p_cb->repeated)
+    {
+        p_cb->busy = false;
+    }
+    p_cb->handler(&event, p_cb->p_context);
+}
+#endif // TWIM_IN_USE
+
+#ifdef TWI_IN_USE
+static void irq_handler_twi(NRF_TWI_Type * p_twi, twi_control_block_t * p_cb)
+{
+    ASSERT(p_cb->handler);
+
+    if (twi_transfer(p_twi, &p_cb->error, &p_cb->bytes_transferred, p_cb->p_curr_buf, p_cb->curr_length, p_cb->curr_no_stop ))
+    {
+        return;
+    }
+
+    if (!p_cb->error &&
+        ((p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXRX) ||
+         (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXTX)) &&
+        p_cb->p_curr_buf == p_cb->xfer_desc.p_primary_buf)
+    {
+        p_cb->p_curr_buf   = p_cb->xfer_desc.p_secondary_buf;
+        p_cb->curr_length  = p_cb->xfer_desc.secondary_length;
+        p_cb->curr_no_stop = (p_cb->flags & NRF_DRV_TWI_FLAG_TX_NO_STOP);
+
+        if (p_cb->xfer_desc.type == NRF_DRV_TWI_XFER_TXTX)
+        {
+            (void)twi_tx_start_transfer(p_cb, p_twi, p_cb->p_curr_buf, p_cb->curr_length, p_cb->curr_no_stop);
+        }
+        else
+        {
+            (void)twi_rx_start_transfer(p_cb, p_twi, p_cb->p_curr_buf, p_cb->curr_length);
+        }
+    }
+    else
+    {
+        nrf_drv_twi_evt_t event;
+        event.xfer_desc = p_cb->xfer_desc;
+
+        if (p_cb->error)
+        {
+            uint32_t errorsrc = nrf_twi_errorsrc_get_and_clear(p_twi);
+            if (errorsrc & NRF_TWI_ERROR_ADDRESS_NACK)
+            {
+                event.type = NRF_DRV_TWI_EVT_ADDRESS_NACK;
+            }
+            else if (errorsrc & NRF_TWI_ERROR_DATA_NACK)
+            {
+                event.type = NRF_DRV_TWI_EVT_DATA_NACK;
+            }
+        }
+        else
+        {
+            event.type = NRF_DRV_TWI_EVT_DONE;
+        }
+
+        p_cb->busy = false;
+
+        if (!(NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER & p_cb->flags))
+        {
+            p_cb->handler(&event, p_cb->p_context);
+        }
+    }
+
+}
+#endif // TWI_IN_USE
+
+#if TWI0_ENABLED
+IRQ_HANDLER(0)
+{
+    #if (TWI0_USE_EASY_DMA == 1) && defined(NRF52)
+        irq_handler_twim(NRF_TWIM0,
+    #else
+        irq_handler_twi(NRF_TWI0,
+    #endif
+            &m_cb[TWI0_INSTANCE_INDEX]);
+}
+#endif // TWI0_ENABLED
+
+#if TWI1_ENABLED
+IRQ_HANDLER(1)
+{
+    #if (TWI1_USE_EASY_DMA == 1)
+        irq_handler_twim(NRF_TWIM1,
+    #else
+        irq_handler_twi(NRF_TWI1,
+    #endif
+            &m_cb[TWI1_INSTANCE_INDEX]);
+}
+#endif // TWI1_ENABLED
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/twi_master/nrf_drv_twi.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/twi_master/nrf_drv_twi.h
new file mode 100644
index 0000000000..83f37ea4be
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/drivers_nrf/twi_master/nrf_drv_twi.h
@@ -0,0 +1,421 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**
+ *
+ * @defgroup nrf_twi Two-wire interface (TWI)
+ * @ingroup nrf_drivers
+ * @brief Two-wire interface (TWI) APIs.
+ *
+ * @defgroup nrf_twi_master TWI master HAL and driver
+ * @ingroup nrf_twi
+ * @brief TWI master APIs.
+ * @details The TWI and TWIM HALs provide basic APIs for accessing the registers of the TWI and TWIM peripherals, respectively. 
+ *
+ * The TWI master driver provides APIs on a higher level.
+ *
+ */
+
+#ifndef NRF_DRV_TWI_H__
+#define NRF_DRV_TWI_H__
+
+#include "nordic_common.h"
+#include "nrf_drv_config.h"
+
+// This set of macros makes it possible to exclude parts of code when one type
+// of supported peripherals is not used.
+#if ((TWI0_ENABLED == 1 && TWI0_USE_EASY_DMA == 1) || \
+     (TWI1_ENABLED == 1 && TWI1_USE_EASY_DMA == 1))
+    #define TWIM_IN_USE
+#endif
+#if ((TWI0_ENABLED == 1 && TWI0_USE_EASY_DMA != 1) || \
+     (TWI1_ENABLED == 1 && TWI1_USE_EASY_DMA != 1))
+    #define TWI_IN_USE
+#endif
+
+#include "nrf_twi.h"
+#ifdef TWIM_IN_USE
+    #include "nrf_twim.h"
+#endif
+#include "sdk_errors.h"
+
+#if defined(NRF52)
+    #define NRF_DRV_TWI_PERIPHERAL(id)           \
+        (CONCAT_3(TWI, id, _USE_EASY_DMA) == 1 ? \
+            (void *)CONCAT_2(NRF_TWIM, id)       \
+          : (void *)CONCAT_2(NRF_TWI, id))
+#else
+    #define NRF_DRV_TWI_PERIPHERAL(id)  (void *)CONCAT_2(NRF_TWI, id)
+#endif
+
+/**
+ * @defgroup nrf_drv_twi TWI master driver
+ * @{
+ * @ingroup nrf_twi_master
+ * @brief   Multi-instance TWI master driver.
+ */
+
+/**
+ * @brief Structure for the TWI master driver instance.
+ */
+typedef struct
+{
+    union
+    {
+#ifdef TWIM_IN_USE
+        NRF_TWIM_Type * p_twim; ///< Pointer to a structure with TWIM registers.
+#endif
+        NRF_TWI_Type  * p_twi;  ///< Pointer to a structure with TWI registers.
+    } reg;
+    uint8_t drv_inst_idx; ///< Driver instance index.
+    bool    use_easy_dma; ///< True if the peripheral with EasyDMA (TWIM) shall be used.
+} nrf_drv_twi_t;
+
+/**
+ * @brief Macro for creating a TWI master driver instance.
+ */
+#define NRF_DRV_TWI_INSTANCE(id)                        \
+{                                                       \
+    .reg          = {NRF_DRV_TWI_PERIPHERAL(id)},       \
+    .drv_inst_idx = CONCAT_3(TWI, id, _INSTANCE_INDEX), \
+    .use_easy_dma = CONCAT_3(TWI, id, _USE_EASY_DMA)    \
+}
+
+/**
+ * @brief Structure for the TWI master driver instance configuration.
+ */
+typedef struct
+{
+    uint32_t            scl;                ///< SCL pin number.
+    uint32_t            sda;                ///< SDA pin number.
+    nrf_twi_frequency_t frequency;          ///< TWI frequency.
+    uint8_t             interrupt_priority; ///< Interrupt priority.
+} nrf_drv_twi_config_t;
+
+/**
+ * @brief TWI master driver instance default configuration.
+ */
+#define NRF_DRV_TWI_DEFAULT_CONFIG(id)                            \
+{                                                                 \
+    .frequency          = CONCAT_3(TWI, id, _CONFIG_FREQUENCY),   \
+    .scl                = CONCAT_3(TWI, id, _CONFIG_SCL),         \
+    .sda                = CONCAT_3(TWI, id, _CONFIG_SDA),         \
+    .interrupt_priority = CONCAT_3(TWI, id, _CONFIG_IRQ_PRIORITY) \
+}
+
+#define NRF_DRV_TWI_FLAG_TX_POSTINC          (1UL << 0) /**< TX buffer address incremented after transfer. */
+#define NRF_DRV_TWI_FLAG_RX_POSTINC          (1UL << 1) /**< RX buffer address incremented after transfer. */
+#define NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER (1UL << 2) /**< Interrupt after each transfer is suppressed, and the event handler is not called. */
+#define NRF_DRV_TWI_FLAG_HOLD_XFER           (1UL << 3) /**< Set up the transfer but do not start it. */
+#define NRF_DRV_TWI_FLAG_REPEATED_XFER       (1UL << 4) /**< Flag indicating that the transfer will be executed multiple times. */
+#define NRF_DRV_TWI_FLAG_TX_NO_STOP          (1UL << 5) /**< Flag indicating that the TX transfer will not end with a stop condition. */
+
+/**
+ * @brief TWI master driver event types.
+ */
+typedef enum
+{
+    NRF_DRV_TWI_EVT_DONE,         ///< Transfer completed event.
+    NRF_DRV_TWI_EVT_ADDRESS_NACK, ///< Error event: NACK received after sending the address.
+    NRF_DRV_TWI_EVT_DATA_NACK     ///< Error event: NACK received after sending a data byte.
+} nrf_drv_twi_evt_type_t;
+
+/**
+ * @brief TWI master driver transfer types.
+ */
+typedef enum
+{
+    NRF_DRV_TWI_XFER_TX,          ///< TX transfer.
+    NRF_DRV_TWI_XFER_RX,          ///< RX transfer.
+    NRF_DRV_TWI_XFER_TXRX,        ///< TX transfer followed by RX transfer with repeated start.
+    NRF_DRV_TWI_XFER_TXTX         ///< TX transfer followed by TX transfer with repeated start.
+} nrf_drv_twi_xfer_type_t;
+
+/**
+ * @brief Structure for a TWI transfer descriptor.
+ */
+typedef struct
+{
+    nrf_drv_twi_xfer_type_t type;             ///< Type of transfer.
+    uint8_t                 address;          ///< Slave address.
+    uint8_t                 primary_length;   ///< Number of bytes transferred.
+    uint8_t                 secondary_length; ///< Number of bytes transferred.
+    uint8_t *               p_primary_buf;    ///< Pointer to transferred data.
+    uint8_t *               p_secondary_buf;  ///< Pointer to transferred data.
+} nrf_drv_twi_xfer_desc_t;
+
+
+/**@brief Macro for setting the TX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_TX(addr, p_data, length)                 \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_TX,                                   \
+        .address = addr,                                               \
+        .primary_length = length,                                      \
+        .p_primary_buf  = p_data,                                      \
+    }
+
+/**@brief Macro for setting the RX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_RX(addr, p_data, length)                 \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_RX,                                   \
+        .address = addr,                                               \
+        .primary_length = length,                                      \
+        .p_primary_buf  = p_data,                                      \
+    }
+
+/**@brief Macro for setting the TXRX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_TXRX(addr, p_tx, tx_len, p_rx, rx_len)   \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_TXRX,                                 \
+        .address = addr,                                               \
+        .primary_length   = tx_len,                                    \
+        .secondary_length = rx_len,                                    \
+        .p_primary_buf    = p_tx,                                      \
+        .p_secondary_buf  = p_rx,                                      \
+    }
+
+/**@brief Macro for setting the TXTX transfer descriptor. */
+#define NRF_DRV_TWI_XFER_DESC_TXTX(addr, p_tx, tx_len, p_tx2, tx_len2) \
+    {                                                                  \
+        .type = NRF_DRV_TWI_XFER_TXTX,                                 \
+        .address = addr,                                               \
+        .primary_length   = tx_len,                                    \
+        .secondary_length = tx_len2,                                   \
+        .p_primary_buf    = p_tx,                                      \
+        .p_secondary_buf  = p_tx2,                                     \
+    }
+
+/**
+ * @brief Structure for a TWI event.
+ */
+typedef struct
+{
+    nrf_drv_twi_evt_type_t  type;      ///< Event type.
+    nrf_drv_twi_xfer_desc_t xfer_desc; ///< Transfer details.
+} nrf_drv_twi_evt_t;
+
+/**
+ * @brief TWI event handler prototype.
+ */
+typedef void (* nrf_drv_twi_evt_handler_t)(nrf_drv_twi_evt_t const * p_event,
+                                           void *                    p_context);
+
+/**
+ * @brief Function for initializing the TWI instance.
+ *
+ * @param[in] p_instance      TWI instance.
+ * @param[in] p_config        Initial configuration. If NULL, the default configuration is used.
+ * @param[in] event_handler   Event handler provided by the user. If NULL, blocking mode is enabled.
+ * @param[in] p_context       Context passed to event handler.
+ *
+ * @retval NRF_SUCCESS             If initialization was successful.
+ * @retval NRF_ERROR_INVALID_STATE If the driver is in invalid state.
+ * @retval NRF_ERROR_BUSY          If some other peripheral with the same
+ *                                 instance ID is already in use. This is 
+ *                                 possible only if PERIPHERAL_RESOURCE_SHARING_ENABLED 
+ *                                 is set to a value other than zero.
+ */
+ret_code_t nrf_drv_twi_init(nrf_drv_twi_t const *        p_instance,
+                            nrf_drv_twi_config_t const * p_config,
+                            nrf_drv_twi_evt_handler_t    event_handler,
+                            void *                       p_context);
+
+/**
+ * @brief Function for uninitializing the TWI instance.
+ *
+ * @param[in] p_instance  TWI instance.
+ */
+void nrf_drv_twi_uninit(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for enabling the TWI instance.
+ *
+ * @param[in] p_instance  TWI instance.
+ */
+void nrf_drv_twi_enable(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for disabling the TWI instance.
+ *
+ * @param[in] p_instance  TWI instance.
+ */
+void nrf_drv_twi_disable(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for sending data to a TWI slave.
+ *
+ * The transmission will be stopped when an error occurs. If a transfer is ongoing,
+ * the function returns the error code @ref NRF_ERROR_BUSY.
+ *
+ * @param[in] p_instance TWI instance.
+ * @param[in] address    Address of a specific slave device (only 7 LSB).
+ * @param[in] p_data     Pointer to a transmit buffer.
+ * @param[in] length     Number of bytes to send.
+ * @param[in] no_stop    If set, the stop condition is not generated on the bus
+ *                       after the transfer has completed successfully (allowing
+ *                       for a repeated start in the next transfer).
+ *
+ * @retval NRF_SUCCESS        If the procedure was successful.
+ * @retval NRF_ERROR_BUSY     If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_INTERNAL If an error was detected by hardware.
+ */
+ret_code_t nrf_drv_twi_tx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t const *       p_data,
+                          uint8_t               length,
+                          bool                  no_stop);
+
+/**
+ * @brief Function for reading data from a TWI slave.
+ *
+ * The transmission will be stopped when an error occurs. If a transfer is ongoing,
+ * the function returns the error code @ref NRF_ERROR_BUSY. 
+ *
+ * @param[in] p_instance TWI instance.
+ * @param[in] address    Address of a specific slave device (only 7 LSB).
+ * @param[in] p_data     Pointer to a receive buffer.
+ * @param[in] length     Number of bytes to be received.
+ *
+ * @retval NRF_SUCCESS             If the procedure was successful.
+ * @retval NRF_ERROR_BUSY          If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_INTERNAL      If an error was detected by hardware.
+ */
+ret_code_t nrf_drv_twi_rx(nrf_drv_twi_t const * p_instance,
+                          uint8_t               address,
+                          uint8_t *             p_data,
+                          uint8_t               length);
+
+/**
+ * @brief Function for preparing a TWI transfer.
+ *
+ * The following transfer types can be configured (@ref nrf_drv_twi_xfer_desc_t::type):
+ * - @ref NRF_DRV_TWI_XFER_TXRX<span></span>: Write operation followed by a read operation (without STOP condition in between).
+ * - @ref NRF_DRV_TWI_XFER_TXTX<span></span>: Write operation followed by a write operation (without STOP condition in between).
+ * - @ref NRF_DRV_TWI_XFER_TX<span></span>:   Write operation (with or without STOP condition).
+ * - @ref NRF_DRV_TWI_XFER_RX<span></span>:   Read operation  (with STOP condition).
+ *
+ * Additional options are provided using the flags parameter:
+ * - @ref NRF_DRV_TWI_FLAG_TX_POSTINC and @ref NRF_DRV_TWI_FLAG_RX_POSTINC<span></span>: Post-incrementation of buffer addresses. Supported only by TWIM.
+ * - @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER<span></span>: No user event handler after transfer completion. In most cases, this also means no interrupt at the end of the transfer.
+ * - @ref NRF_DRV_TWI_FLAG_HOLD_XFER<span></span>: Driver is not starting the transfer. Use this flag if the transfer is triggered externally by PPI. Supported only by TWIM.
+ *   Use @ref nrf_drv_twi_start_task_get to get the address of the start task.
+ * - @ref NRF_DRV_TWI_FLAG_REPEATED_XFER<span></span>: Prepare for repeated transfers. You can set up a number of transfers that will be triggered externally (for example by PPI).
+ *   An example is a TXRX transfer with the options @ref NRF_DRV_TWI_FLAG_RX_POSTINC, @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER, and @ref NRF_DRV_TWI_FLAG_REPEATED_XFER.
+ *   After the transfer is set up, a set of transfers can be triggered by PPI that will read, for example, the same register of an
+ *   external component and put it into a RAM buffer without any interrupts. @ref nrf_drv_twi_stopped_event_get can be used to get the
+ *   address of the STOPPED event, which can be used to count the number of transfers. If @ref NRF_DRV_TWI_FLAG_REPEATED_XFER is used,
+ *   the driver does not set the instance into busy state, so you must ensure that the next transfers are set up
+ *   when TWIM is not active. Supported only by TWIM.
+ * - @ref NRF_DRV_TWI_FLAG_TX_NO_STOP<span></span>: No stop condition after TX transfer.
+ *
+ * @note
+ * Some flag combinations are invalid:
+ * - @ref NRF_DRV_TWI_FLAG_TX_NO_STOP with @ref nrf_drv_twi_xfer_desc_t::type different than @ref NRF_DRV_TWI_XFER_TX
+ * - @ref NRF_DRV_TWI_FLAG_REPEATED_XFER with @ref nrf_drv_twi_xfer_desc_t::type set to @ref NRF_DRV_TWI_XFER_TXTX
+ *
+ * If @ref nrf_drv_twi_xfer_desc_t::type is set to @ref NRF_DRV_TWI_XFER_TX and the @ref NRF_DRV_TWI_FLAG_TX_NO_STOP and @ref NRF_DRV_TWI_FLAG_REPEATED_XFER
+ * flags are set, two tasks must be used to trigger a transfer: TASKS_RESUME followed by TASKS_STARTTX. If no stop condition is generated,
+ * TWIM is in SUSPENDED state. Therefore, it must be resumed before the transfer can be started.
+ *
+ * @note
+ * This function should be used only if the instance is configured to work in non-blocking mode. If the function is used in blocking mode, the driver asserts.
+ * @note If you are using this function with TWI, the only supported flag is @ref NRF_DRV_TWI_FLAG_TX_NO_STOP. All other flags require TWIM.
+  *
+ * @param[in] p_instance        TWI instance.
+ * @param[in] p_xfer_desc       Pointer to the transfer descriptor.
+ * @param[in] flags             Transfer options (0 for default settings).
+ *
+ * @retval NRF_SUCCESS             If the procedure was successful.
+ * @retval NRF_ERROR_BUSY          If the driver is not ready for a new transfer.
+ * @retval NRF_ERROR_NOT_SUPPORTED If the provided parameters are not supported.
+ */
+ret_code_t nrf_drv_twi_xfer(nrf_drv_twi_t           const * p_instance,
+                            nrf_drv_twi_xfer_desc_t const * p_xfer_desc,
+                            uint32_t                        flags);
+
+/**
+ * @brief Function for checking the TWI driver state.
+ *
+ * @param[in] p_instance TWI instance.
+ *
+ * @retval true  If the TWI driver is currently busy performing a transfer.
+ * @retval false If the TWI driver is ready for a new transfer.
+ */
+bool nrf_drv_twi_is_busy(nrf_drv_twi_t const * p_instance);
+
+/**
+ * @brief Function for getting the transferred data count.
+ *
+ * This function provides valid results only in legacy mode.
+ *
+ * @param[in] p_instance TWI instance.
+ *
+ * @return     Data count.
+ */
+uint32_t nrf_drv_twi_data_count_get(nrf_drv_twi_t const * const p_instance);
+
+/**
+ * @brief Function for returning the address of a TWI/TWIM start task.
+ *
+ * This function should be used if @ref nrf_drv_twi_xfer was called with the flag @ref NRF_DRV_TWI_FLAG_HOLD_XFER.
+ * In that case, the transfer is not started by the driver, but it must be started externally by PPI.
+ *
+ * @param[in]  p_instance TWI instance.
+ * @param[in]  xfer_type  Transfer type used in the last call of the @ref nrf_drv_twi_xfer function.
+ *
+ * @return     Start task address (TX or RX) depending on the value of xfer_type.
+ */
+uint32_t nrf_drv_twi_start_task_get(nrf_drv_twi_t const * p_instance, nrf_drv_twi_xfer_type_t xfer_type);
+
+/**
+ * @brief Function for returning the address of a STOPPED TWI/TWIM event.
+ *
+ * A STOPPED event can be used to detect the end of a transfer if the @ref NRF_DRV_TWI_FLAG_NO_XFER_EVT_HANDLER
+ * option is used.
+ *
+ * @param[in]  p_instance  TWI instance.
+ *
+ * @return     STOPPED event address.
+ */
+uint32_t nrf_drv_twi_stopped_event_get(nrf_drv_twi_t const * p_instance);
+/**
+ *@}
+ **/
+
+#endif // NRF_DRV_TWI_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader.h
new file mode 100644
index 0000000000..f2f35bee60
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader.h
@@ -0,0 +1,124 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/**@file
+ *
+ * @defgroup nrf_bootloader Bootloader API.
+ * @{     
+ *
+ * @brief Bootloader module interface.
+ */
+
+#ifndef BOOTLOADER_H__
+#define BOOTLOADER_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+#include "bootloader_types.h"
+#include <dfu_types.h>
+
+/**@brief Function for initializing the Bootloader.
+ * 
+ * @retval     NRF_SUCCESS If bootloader was succesfully initialized. 
+ */
+uint32_t bootloader_init(void);
+
+/**@brief Function for validating application region in flash.
+ * 
+ * @param[in]  app_addr      Address to the region in flash where the application is stored.
+ * 
+ * @retval     true          If Application region is valid.
+ * @retval     false         If Application region is not valid.
+ */
+bool bootloader_app_is_valid(uint32_t app_addr);
+
+/**@brief Function for starting the Device Firmware Update.
+ * 
+ * @retval     NRF_SUCCESS If new application image was successfully transferred.
+ */
+uint32_t bootloader_dfu_start(void);
+
+/**@brief Function for exiting bootloader and booting into application.
+ *
+ * @details This function will disable SoftDevice and all interrupts before jumping to application.
+ *          The SoftDevice vector table base for interrupt forwarding will be set the application
+ *          address.
+ *
+ * @param[in]  app_addr      Address to the region where the application is stored.
+ */
+void bootloader_app_start(uint32_t app_addr);
+
+/**@brief Function for retrieving the bootloader settings.
+ *
+ * @param[out] p_settings    A copy of the current bootloader settings is returned in the structure
+ *                           provided.
+ */
+void bootloader_settings_get(bootloader_settings_t * const p_settings);
+
+/**@brief Function for processing DFU status update.
+ *
+ * @param[in]  update_status DFU update status.
+ */
+void bootloader_dfu_update_process(dfu_update_status_t update_status);
+
+/**@brief Function getting state of SoftDevice update in progress.
+ *        After a successfull SoftDevice transfer the system restarts in orderto disable SoftDevice
+ *        and complete the update.
+ *
+ * @retval     true          A SoftDevice update is in progress. This indicates that second stage 
+ *                           of a SoftDevice update procedure can be initiated.
+ * @retval     false         No SoftDevice update is in progress.
+ */
+bool bootloader_dfu_sd_in_progress(void);
+
+/**@brief Function for continuing the Device Firmware Update of a SoftDevice.
+ * 
+ * @retval     NRF_SUCCESS If the final stage of SoftDevice update was successful. 
+ */
+uint32_t bootloader_dfu_sd_update_continue(void);
+
+/**@brief Function for finalizing the Device Firmware Update of a SoftDevice.
+ * 
+ * @retval     NRF_SUCCESS If the final stage of SoftDevice update was successful. 
+ */
+uint32_t bootloader_dfu_sd_update_finalize(void);
+
+#endif // BOOTLOADER_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_settings.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_settings.h
new file mode 100644
index 0000000000..c8964f42dc
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_settings.h
@@ -0,0 +1,62 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /**@file
+ *
+ * @defgroup nrf_bootloader_settings Bootloader settings API.
+ * @{     
+ *  
+ * @brief Bootloader settings module interface.
+ */
+ 
+#ifndef BOOTLOADER_SETTINGS_H__
+#define BOOTLOADER_SETTINGS_H__
+
+#include <stdint.h>
+#include "bootloader_types.h"
+
+/**@brief Function for getting the bootloader settings.
+ * 
+ * @param[out] pp_bootloader_settings Bootloader settings. 
+ */
+void bootloader_util_settings_get(const bootloader_settings_t ** pp_bootloader_settings);
+
+#endif // BOOTLOADER_SETTINGS_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_types.h
new file mode 100644
index 0000000000..5d342b0ade
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_types.h
@@ -0,0 +1,86 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/**@file
+ *
+ * @defgroup nrf_bootloader_types Types and definitions.
+ * @{     
+ *  
+ * @ingroup nrf_bootloader
+ * 
+ * @brief Bootloader module type and definitions.
+ */
+ 
+#ifndef BOOTLOADER_TYPES_H__
+#define BOOTLOADER_TYPES_H__
+
+#include <stdint.h>
+
+#define BOOTLOADER_DFU_START 0xB1
+
+#define BOOTLOADER_SVC_APP_DATA_PTR_GET 0x02
+
+/**@brief DFU Bank state code, which indicates wether the bank contains: A valid image, invalid image, or an erased flash.
+  */
+typedef enum
+{
+    BANK_VALID_APP   = 0x01,
+    BANK_VALID_SD    = 0xA5,
+    BANK_VALID_BOOT  = 0xAA,
+    BANK_ERASED      = 0xFE,
+    BANK_INVALID_APP = 0xFF,
+} bootloader_bank_code_t;
+
+/**@brief Structure holding bootloader settings for application and bank data.
+ */
+typedef struct
+{
+    bootloader_bank_code_t bank_0;          /**< Variable to store if bank 0 contains a valid application. */
+    uint16_t               bank_0_crc;      /**< If bank is valid, this field will contain a valid CRC of the total image. */
+    bootloader_bank_code_t bank_1;          /**< Variable to store if bank 1 has been erased/prepared for new image. Bank 1 is only used in Banked Update scenario. */
+    uint32_t               bank_0_size;     /**< Size of active image in bank0 if present, otherwise 0. */
+    uint32_t               sd_image_size;   /**< Size of SoftDevice image in bank0 if bank_0 code is BANK_VALID_SD. */
+    uint32_t               bl_image_size;   /**< Size of Bootloader image in bank0 if bank_0 code is BANK_VALID_SD. */
+    uint32_t               app_image_size;  /**< Size of Application image in bank0 if bank_0 code is BANK_VALID_SD. */
+    uint32_t               sd_image_start;  /**< Location in flash where SoftDevice image is stored for SoftDevice update. */
+} bootloader_settings_t;
+
+#endif // BOOTLOADER_TYPES_H__ 
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.c
new file mode 100644
index 0000000000..39eb64efbc
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.c
@@ -0,0 +1,179 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "bootloader_util.h"
+#include <stdint.h>
+#include <string.h>
+
+
+/**
+ * @brief Function for aborting current application/bootloader jump to to other app/bootloader.
+ *
+ * @details This functions will use the address provide to swap the stack pointer and then load 
+ *          the address of the reset handler to be executed. It will check current system mode 
+ *          (thread/handler) and if in thread mode it will reset into other application.
+ *          If in handler mode \ref isr_abort will be executed to ensure correct exit of handler 
+ *          mode and jump into reset handler of other application.
+ *
+ * @param[in]  start_addr  Start address of other application. This address must point to the 
+               initial stack pointer of the application.
+ *
+ * @note This function will never return but issue a reset into provided application.
+ */
+#if defined ( __CC_ARM )
+__asm static void bootloader_util_reset(uint32_t start_addr)
+{
+    LDR   R5, [R0]              ; Get App initial MSP for bootloader.
+    MSR   MSP, R5               ; Set the main stack pointer to the applications MSP.
+    LDR   R0, [R0, #0x04]       ; Load Reset handler into R0. This will be first argument to branch instruction (BX).
+
+    MOVS  R4, #0xFF             ; Load ones to R4.
+    SXTB  R4, R4                ; Sign extend R4 to obtain 0xFFFFFFFF instead of 0xFF.
+    MRS   R5, IPSR              ; Load IPSR to R5 to check for handler or thread mode.
+    CMP   R5, #0x00             ; Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader.
+    BNE   isr_abort             ; If not zero we need to exit current ISR and jump to reset handler of bootloader.
+
+    MOV   LR, R4                ; Clear the link register and set to ones to ensure no return, R4 = 0xFFFFFFFF.
+    BX    R0                    ; Branch to reset handler of bootloader.
+
+isr_abort
+                                ; R4 contains ones from line above. Will be popped as R12 when exiting ISR (Cleaning up the registers).
+    MOV   R5, R4                ; Fill with ones before jumping to reset handling. We be popped as LR when exiting ISR. Ensures no return to application.
+    MOV   R6, R0                ; Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR.
+    MOVS  r7, #0x21             ; Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21.
+    REV   r7, r7                ; Reverse byte order to put 0x21 as MSB.
+    PUSH  {r4-r7}               ; Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR.
+
+    MOVS  R4, #0x00             ; Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers).
+    MOVS  R5, #0x00             ; Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers).
+    MOVS  R6, #0x00             ; Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers).
+    MOVS  R7, #0x00             ; Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers).
+    PUSH  {r4-r7}               ; Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine.
+
+    MOVS  R0, #0xF9             ; Move the execution return command into register, 0xFFFFFFF9.
+    SXTB  R0, R0                ; Sign extend R0 to obtain 0xFFFFFFF9 instead of 0xF9.
+    BX    R0                    ; No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application.
+    ALIGN
+}
+#elif defined ( __GNUC__ )
+static inline void bootloader_util_reset(uint32_t start_addr)
+{
+    __asm volatile(
+        "ldr   r0, [%0]\t\n"            // Get App initial MSP for bootloader.
+        "msr   msp, r0\t\n"             // Set the main stack pointer to the applications MSP.
+        "ldr   r0, [%0, #0x04]\t\n"     // Load Reset handler into R0.
+
+        "movs  r4, #0xFF\t\n"           // Move ones to R4.
+        "sxtb  r4, r4\t\n"              // Sign extend R4 to obtain 0xFFFFFFFF instead of 0xFF.
+
+        "mrs   r5, IPSR\t\n"            // Load IPSR to R5 to check for handler or thread mode.
+        "cmp   r5, #0x00\t\n"           // Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader.
+        "bne   isr_abort\t\n"           // If not zero we need to exit current ISR and jump to reset handler of bootloader.
+
+        "mov   lr, r4\t\n"              // Clear the link register and set to ones to ensure no return.
+        "bx    r0\t\n"                  // Branch to reset handler of bootloader.
+
+        "isr_abort:  \t\n"
+
+        "mov   r5, r4\t\n"              // Fill with ones before jumping to reset handling. Will be popped as LR when exiting ISR. Ensures no return to application.
+        "mov   r6, r0\t\n"              // Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR.
+        "movs  r7, #0x21\t\n"           // Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21.
+        "rev   r7, r7\t\n"              // Reverse byte order to put 0x21 as MSB.
+        "push  {r4-r7}\t\n"             // Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR.
+
+        "movs  r4, #0x00\t\n"           // Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers).
+        "movs  r5, #0x00\t\n"           // Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers).
+        "movs  r6, #0x00\t\n"           // Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers).
+        "movs  r7, #0x00\t\n"           // Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers).
+        "push  {r4-r7}\t\n"             // Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine.
+
+        "movs  r0, #0xF9\t\n"           // Move the execution return command into register, 0xFFFFFFF9.
+        "sxtb  r0, r0\t\n"              // Sign extend R0 to obtain 0xFFFFFFF9 instead of 0xF9.
+        "bx    r0\t\n"                  // No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application.
+        ".align\t\n"
+        :: "r" (start_addr)             // Argument list for the gcc assembly. start_addr is %0.
+        :  "r0", "r4", "r5", "r6", "r7" // List of register maintained manually.
+    );
+}
+#elif defined ( __ICCARM__ )
+static inline void bootloader_util_reset(uint32_t start_addr)
+{
+    asm("ldr   r5, [%0]\n"                    // Get App initial MSP for bootloader.
+        "msr   msp, r5\n"                     // Set the main stack pointer to the applications MSP.
+        "ldr   r0, [%0, #0x04]\n"             // Load Reset handler into R0.
+
+        "movs  r4, #0x00\n"                   // Load zero into R4.
+        "mvns  r4, r4\n"                      // Invert R4 to ensure it contain ones.
+
+        "mrs   r5, IPSR\n"                    // Load IPSR to R5 to check for handler or thread mode 
+        "cmp   r5, #0x00\n"                   // Compare, if 0 then we are in thread mode and can continue to reset handler of bootloader.
+        "bne.n isr_abort\n"                   // If not zero we need to exit current ISR and jump to reset handler of bootloader.
+
+        "mov   lr, r4\n"                      // Clear the link register and set to ones to ensure no return.
+        "bx    r0\n"                          // Branch to reset handler of bootloader.
+
+        "isr_abort: \n"
+                                              // R4 contains ones from line above. We be popped as R12 when exiting ISR (Cleaning up the registers).
+        "mov   r5, r4\n"                      // Fill with ones before jumping to reset handling. Will be popped as LR when exiting ISR. Ensures no return to application.
+        "mov   r6, r0\n"                      // Move address of reset handler to R6. Will be popped as PC when exiting ISR. Ensures the reset handler will be executed when exist ISR.
+        "movs  r7, #0x21\n"                   // Move MSB reset value of xPSR to R7. Will be popped as xPSR when exiting ISR. xPSR is 0x21000000 thus MSB is 0x21.
+        "rev   r7, r7\n"                      // Reverse byte order to put 0x21 as MSB.
+        "push  {r4-r7}\n"                     // Push everything to new stack to allow interrupt handler to fetch it on exiting the ISR.
+
+        "movs  r4, #0x00\n"                   // Fill with zeros before jumping to reset handling. We be popped as R0 when exiting ISR (Cleaning up of the registers).
+        "movs  r5, #0x00\n"                   // Fill with zeros before jumping to reset handling. We be popped as R1 when exiting ISR (Cleaning up of the registers).
+        "movs  r6, #0x00\n"                   // Fill with zeros before jumping to reset handling. We be popped as R2 when exiting ISR (Cleaning up of the registers).
+        "movs  r7, #0x00\n"                   // Fill with zeros before jumping to reset handling. We be popped as R3 when exiting ISR (Cleaning up of the registers).
+        "push  {r4-r7}\n"                     // Push zeros (R4-R7) to stack to prepare for exiting the interrupt routine.
+
+        "movs  r0, #0x06\n"                   // Load 0x06 into R6 to prepare for exec return command.
+        "mvns  r0, r0\n"                      // Invert 0x06 to obtain EXEC_RETURN, 0xFFFFFFF9.
+        "bx    r0\n"                          // No return - Handler mode will be exited. Stack will be popped and execution will continue in reset handler initializing other application.
+        :: "r" (start_addr)                   // Argument list for the IAR assembly. start_addr is %0.
+        :  "r0", "r4", "r5", "r6", "r7");     // List of register maintained manually.
+}
+#else
+#error Compiler not supported.
+#endif
+
+
+void bootloader_util_app_start(uint32_t start_addr)
+{
+    bootloader_util_reset(start_addr);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.h
new file mode 100644
index 0000000000..a1d3f4e47d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/bootloader_util.h
@@ -0,0 +1,65 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /**@file
+ *
+ * @defgroup nrf_bootloader_util Bootloader util API.
+ * @{     
+ *  
+ * @brief Bootloader util module interface.
+ */
+ 
+#ifndef BOOTLOADER_UTIL_H__
+#define BOOTLOADER_UTIL_H__
+
+#include <stdint.h>
+#include "bootloader_types.h"
+
+/**@brief Function for starting the application (or bootloader) at the provided address.
+ * 
+ * @param[in]  start_addr             Start address.
+ *
+ * @note This function will never retrun. Instead it will reset into the application of the 
+ *       provided address.
+ */
+void bootloader_util_app_start(uint32_t start_addr);
+
+#endif // BOOTLOADER_UTIL_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu.h
new file mode 100644
index 0000000000..e0dda11040
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu.h
@@ -0,0 +1,161 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/**@file
+ *
+ * @defgroup nrf_dfu Device Firmware Update API.
+ * @{     
+ *
+ * @brief Device Firmware Update module interface.
+ */
+
+#ifndef DFU_H__
+#define DFU_H__
+
+#include <dfu_types.h>
+#include <stdbool.h>
+#include <stdint.h>
+
+
+/**@brief DFU event callback for asynchronous calls.
+ *
+ * @param[in] packet  Packet type for which this callback is related. START_PACKET, DATA_PACKET.
+ * @param[in] result  Operation result code. NRF_SUCCESS when a queued operation was successful.
+ * @param[in] p_data  Pointer to the data to which the operation is related.
+ */
+typedef void (*dfu_callback_t)(uint32_t packet, uint32_t  result, uint8_t * p_data);
+
+/**@brief Function for initializing the Device Firmware Update module.
+ * 
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_init(void);
+
+/**@brief Function for registering a callback listener for \ref dfu_data_pkt_handle callbacks.
+ *
+ * @param[in] callback_handler  Callback handler for receiving DFU events on completed operations
+ *                              of DFU packets.
+ */
+void dfu_register_callback(dfu_callback_t callback_handler);
+
+/**@brief Function for setting the DFU image size. 
+ *
+ * @details Function sets the DFU image size. This function must be called when an update is started 
+ *          in order to notify the DFU of the new image size. If multiple images are to be 
+ *          transferred within the same update context then this function must be called with size 
+ *          information for each image being transfered.
+ *          If an image type is not being transfered, e.g. SoftDevice but no Application , then the
+ *          image size for application must be zero.
+ * 
+ * @param[in] p_packet   Pointer to the DFU packet containing information on DFU update process to
+ *                       be started.
+ *
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_start_pkt_handle(dfu_update_packet_t * p_packet);
+
+/**@brief Function for handling DFU data packets.
+ *
+ * @param[in] p_packet   Pointer to the DFU packet.
+ *
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_data_pkt_handle(dfu_update_packet_t * p_packet);
+
+/**@brief Function for handling DFU init packets.
+ *
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_init_pkt_handle(dfu_update_packet_t * p_packet);
+
+/**@brief Function for validating a transferred image after the transfer has completed.
+ * 
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_image_validate(void);
+
+/**@brief Function for activating the transfered image after validation has successfully completed.
+ *
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_image_activate(void);
+
+/**@brief Function for reseting the current update procedure and return to initial state.
+ *        
+ * @details This function call will result in a system reset to ensure correct system behavior.
+ *          The reset will might be scheduled to execute at a later point in time to ensure pending 
+ *          flash operations has completed.
+ */
+void dfu_reset(void);
+
+/**@brief Function for validating that new bootloader has been correctly installed.
+ *        
+ * @return NRF_SUCCESS if install was successful. NRF_ERROR_NULL if the images differs.
+ */
+uint32_t dfu_bl_image_validate(void);
+
+/**@brief Function for validating that new SoftDevicehas been correctly installed.
+ *        
+ * @return NRF_SUCCESS if install was successful. NRF_ERROR_NULL if the images differs.
+ */
+uint32_t dfu_sd_image_validate(void);
+
+/**@brief Function for swapping existing bootloader with newly received.
+ *        
+ * @return NRF_SUCCESS on succesfull swapping. For error code please refer to 
+ *         \ref sd_mbr_command_copy_bl_t.
+ */
+uint32_t dfu_bl_image_swap(void);
+
+/**@brief Function for swapping existing SoftDevice with newly received.
+ *        
+ * @return NRF_SUCCESS on succesfull swapping. For error code please refer to 
+ *         \ref sd_mbr_command_copy_sd_t.
+ */
+uint32_t dfu_sd_image_swap(void);
+
+/**@brief Function for handling DFU init packet complete.
+ *
+ * @return    NRF_SUCCESS on success, an error_code otherwise.
+ */
+uint32_t dfu_init_pkt_complete(void);
+
+#endif // DFU_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.c
new file mode 100644
index 0000000000..38b3ca4770
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.c
@@ -0,0 +1,219 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "dfu_app_handler.h"
+#include <string.h>
+#include "bootloader_util.h"
+#include "nrf.h"
+#include "nrf_sdm.h"
+#include "nrf_ble_gatt.h"
+#include "nrf_ble_gatts.h"
+#include "app_error.h"
+#include "dfu_ble_svc.h"
+#include "device_manager.h"
+#include "nrf_delay.h"
+
+#define IRQ_ENABLED            0x01                                     /**< Field that identifies if an interrupt is enabled. */
+#define MAX_NUMBER_INTERRUPTS  32                                       /**< Maximum number of interrupts available. */
+
+static void                    dfu_app_reset_prepare(void);             /**< Forward declaration of default reset handler. */
+static dfu_app_reset_prepare_t m_reset_prepare = dfu_app_reset_prepare; /**< Callback function to application to prepare for system reset. Allows application to clean up service and memory before reset. */
+static dfu_ble_peer_data_t     m_peer_data;                             /**< Peer data to be used for data exchange when resetting into DFU mode. */
+static dm_handle_t             m_dm_handle;                             /**< Device Manager handle with instance IDs of current BLE connection. */
+
+
+/**@brief Function for reset_prepare handler if the application has not registered a handler.
+ */
+static void dfu_app_reset_prepare(void)
+{
+    // Reset prepare should be handled by application.
+    // This function can be extended to include default handling if application does not implement
+    // own handler.
+}
+
+
+/**@brief Function for disabling all interrupts before jumping from bootloader to application.
+ */
+static void interrupts_disable(void)
+{
+    uint32_t interrupt_setting_mask;
+    uint32_t irq;
+
+    // Fetch the current interrupt settings.
+    interrupt_setting_mask = NVIC->ISER[0];
+
+    // Loop from interrupt 0 for disabling of all interrupts.
+    for (irq = 0; irq < MAX_NUMBER_INTERRUPTS; irq++)
+    {
+        if (interrupt_setting_mask & (IRQ_ENABLED << irq))
+        {
+            // The interrupt was enabled, hence disable it.
+            NVIC_DisableIRQ((IRQn_Type)irq);
+        }
+    }
+}
+
+
+/**@brief Function for providing peer information to DFU for re-establishing a bonded connection in
+ *        DFU mode.
+ *
+ * @param[in] conn_handle   Connection handle for the connection requesting DFU mode.
+ */
+static void dfu_app_peer_data_set(uint16_t conn_handle)
+{
+    uint32_t                 err_code;
+    dm_sec_keyset_t          key_set;
+    uint32_t                 app_context_data = 0;
+    dm_application_context_t app_context;
+
+
+/** [DFU bond sharing] */
+    err_code = dm_handle_get(conn_handle, &m_dm_handle);
+    if (err_code == NRF_SUCCESS)
+    {
+        err_code = dm_distributed_keys_get(&m_dm_handle, &key_set);
+        if (err_code == NRF_SUCCESS)
+        {
+            APP_ERROR_CHECK(err_code);
+
+            m_peer_data.addr              = key_set.keys_central.p_id_key->id_addr_info;
+            m_peer_data.irk               = key_set.keys_central.p_id_key->id_info;
+            m_peer_data.enc_key.enc_info  = key_set.keys_periph.enc_key.p_enc_key->enc_info;
+            m_peer_data.enc_key.master_id = key_set.keys_periph.enc_key.p_enc_key->master_id;
+
+            err_code = dfu_ble_svc_peer_data_set(&m_peer_data);
+            APP_ERROR_CHECK(err_code);
+
+            app_context_data   = (DFU_APP_ATT_TABLE_CHANGED << DFU_APP_ATT_TABLE_POS);
+            app_context.len    = sizeof(app_context_data);
+            app_context.p_data = (uint8_t *)&app_context_data;
+            app_context.flags  = 0;
+
+            err_code = dm_application_context_set(&m_dm_handle, &app_context);
+            APP_ERROR_CHECK(err_code);
+        }
+        else
+        {
+            // Keys were not available, thus we have a non-encrypted connection.
+            err_code = dm_peer_addr_get(&m_dm_handle, &m_peer_data.addr);
+            APP_ERROR_CHECK(err_code);
+
+            err_code = dfu_ble_svc_peer_data_set(&m_peer_data);
+            APP_ERROR_CHECK(err_code);
+        }
+    }
+/** [DFU bond sharing] */
+}
+
+
+/**@brief Function for preparing the reset, disabling SoftDevice, and jumping to the bootloader.
+ *
+ * @param[in] conn_handle Connection handle for peer requesting to enter DFU mode.
+ */
+static void bootloader_start(uint16_t conn_handle)
+{
+    uint32_t err_code;
+    uint16_t sys_serv_attr_len = sizeof(m_peer_data.sys_serv_attr);
+
+    err_code = sd_ble_gatts_sys_attr_get(conn_handle,
+                                         m_peer_data.sys_serv_attr,
+                                         &sys_serv_attr_len,
+                                         BLE_GATTS_SYS_ATTR_FLAG_SYS_SRVCS);
+    if (err_code != NRF_SUCCESS)
+    {
+        // Any error at this stage means the system service attributes could not be fetched.
+        // This means the service changed indication cannot be sent in DFU mode, but connection
+        // is still possible to establish.
+    }
+
+    m_reset_prepare();
+
+    err_code = sd_power_gpregret_set(BOOTLOADER_DFU_START);
+    APP_ERROR_CHECK(err_code);
+
+    err_code = sd_softdevice_disable();
+    APP_ERROR_CHECK(err_code);
+
+    err_code = sd_softdevice_vector_table_base_set(NRF_UICR->NRFFW[0]);
+    APP_ERROR_CHECK(err_code);
+
+    dfu_app_peer_data_set(conn_handle);
+
+    NVIC_ClearPendingIRQ(SWI2_IRQn);
+    interrupts_disable();
+    bootloader_util_app_start(NRF_UICR->NRFFW[0]);
+}
+
+
+void dfu_app_on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt)
+{
+    switch (p_evt->ble_dfu_evt_type)
+    {
+        case BLE_DFU_START:
+            // Starting the bootloader - will cause reset.
+            bootloader_start(p_dfu->conn_handle);
+            break;
+
+        default:
+            {
+                // Unsupported event received from DFU Service.
+                // Send back BLE_DFU_RESP_VAL_NOT_SUPPORTED message to peer.
+                uint32_t err_code = ble_dfu_response_send(p_dfu,
+                                                          BLE_DFU_START_PROCEDURE,
+                                                          BLE_DFU_RESP_VAL_NOT_SUPPORTED);
+                APP_ERROR_CHECK(err_code);
+            }
+            break;
+    }
+}
+
+
+void dfu_app_reset_prepare_set(dfu_app_reset_prepare_t reset_prepare_func)
+{
+    m_reset_prepare = reset_prepare_func;
+}
+
+
+void dfu_app_dm_appl_instance_set(dm_application_instance_t app_instance)
+{
+    uint32_t err_code;
+
+    err_code = dm_application_instance_set(&app_instance, &m_dm_handle);
+    APP_ERROR_CHECK(err_code);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.h
new file mode 100644
index 0000000000..6f208f1d43
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_app_handler.h
@@ -0,0 +1,113 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+  
+/** @file
+ *
+ * @defgroup nrf_dfu_app_handler DFU BLE packet handling in application
+ * @{
+ *
+ * @brief Handling of DFU BLE packets in the application.
+ *
+ * @details This module implements the handling of DFU packets for switching 
+ *          from an application to the bootloader and start DFU mode. The DFU
+ *          packets are transmitted over BLE. 
+ *          This module handles only the StartDFU packet, which allows a BLE 
+ *          application to expose support for the DFU Service.
+ *          The actual DFU Service runs in a dedicated environment after a BLE 
+ *          disconnect and reset of the \nRFXX device. 
+ *          The host must reconnect and continue the update procedure with 
+ *          access to the full DFU Service.
+ *
+ * @note The application must propagate DFU events to this module by calling
+ *       @ref dfu_app_on_dfu_evt from the @ref ble_dfu_evt_handler_t callback.
+ */
+ 
+#ifndef DFU_APP_HANDLER_H__
+#define DFU_APP_HANDLER_H__
+
+#include "ble_dfu.h"
+#include "nrf_svc.h"
+#include "bootloader_types.h"
+#include "device_manager.h"
+
+#define DFU_APP_ATT_TABLE_POS     0                     /**< Position for the ATT table changed setting. */
+#define DFU_APP_ATT_TABLE_CHANGED 1                     /**< Value indicating that the ATT table might have changed. This value will be set in the application-specific context in Device Manager when entering DFU mode. */
+
+/**@brief DFU application reset_prepare function. This function is a callback that allows the 
+ *        application to prepare for an upcoming application reset. 
+ */
+typedef void (*dfu_app_reset_prepare_t)(void);
+
+/**@brief   Function for handling events from the DFU Service. 
+ *
+ * @details The application must inject this function into the DFU Service or propagate DFU events 
+ *          to the dfu_app_handler module by calling this function in the application-specific DFU event 
+ *          handler.
+ * 
+ * @param[in] p_dfu  Pointer to the DFU Service structure to which the include event relates.
+ * @param[in] p_evt  Pointer to the DFU event.
+ */
+void dfu_app_on_dfu_evt(ble_dfu_t * p_dfu, ble_dfu_evt_t * p_evt);
+
+/**@brief Function for registering a function to prepare a reset.
+ *
+ * @details The provided function is executed before resetting the system into bootloader/DFU
+ *          mode. By registering this function, the caller is notified before the reset and can
+ *          thus prepare the application for reset. For example, the application can gracefully
+ *          disconnect any peers on BLE, turn of LEDS, ensure that all pending flash operations
+ *          have completed, and so on.
+ *
+ * @param[in] reset_prepare_func  Function to be executed before a reset.
+ */
+void dfu_app_reset_prepare_set(dfu_app_reset_prepare_t reset_prepare_func);
+
+/**@brief Function for setting the Device Manager application instance.
+ *
+ * @details This function allows to set the @ref dm_application_instance_t value that is returned by the 
+ *          Device Manager when the application registers using @ref dm_register.
+ *          If this function is not called, it is not be possible to share bonding information
+ *          from the application to the bootloader/DFU when entering DFU mode.
+ *
+ * @param[in] app_instance Value for the application instance in use.
+ */
+void dfu_app_dm_appl_instance_set(dm_application_instance_t app_instance);
+
+#endif // DFU_APP_HANDLER_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_bank_internal.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_bank_internal.h
new file mode 100644
index 0000000000..a2dbb80b09
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_bank_internal.h
@@ -0,0 +1,114 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/**@file
+ *
+ * @defgroup dfu_bank_internal Device Firmware Update internal header for bank handling in DFU.
+ * @{     
+ *
+ * @brief Device Firmware Update Bank handling module interface.
+ *
+ * @details This header is intended for shared definition and functions between single and dual bank 
+ *         implementations used for DFU support. It is not supposed to be used for external access 
+ *         to the DFU module.
+ *  
+ */
+#ifndef DFU_BANK_INTERNAL_H__
+#define DFU_BANK_INTERNAL_H__
+
+#include <dfu_types.h>
+
+/**@brief States of the DFU state machine. */
+typedef enum
+{
+    DFU_STATE_INIT_ERROR,                                                           /**< State for: dfu_init(...) error. */
+    DFU_STATE_IDLE,                                                                 /**< State for: idle. */
+    DFU_STATE_PREPARING,                                                            /**< State for: preparing, indicates that the flash is being erased and no data packets can be processed. */
+    DFU_STATE_RDY,                                                                  /**< State for: ready. */
+    DFU_STATE_RX_INIT_PKT,                                                          /**< State for: receiving initialization packet. */
+    DFU_STATE_RX_DATA_PKT,                                                          /**< State for: receiving data packet. */
+    DFU_STATE_VALIDATE,                                                             /**< State for: validate. */
+    DFU_STATE_WAIT_4_ACTIVATE                                                       /**< State for: waiting for dfu_image_activate(). */
+} dfu_state_t;
+
+#define APP_TIMER_PRESCALER         0                                               /**< Value of the RTC1 PRESCALER register. */
+#define DFU_TIMEOUT_INTERVAL        APP_TIMER_TICKS(120000, APP_TIMER_PRESCALER)    /**< DFU timeout interval in units of timer ticks. */     
+
+#define IS_UPDATING_SD(START_PKT)   ((START_PKT).dfu_update_mode & DFU_UPDATE_SD)   /**< Macro for determining if a SoftDevice update is ongoing. */
+#define IS_UPDATING_BL(START_PKT)   ((START_PKT).dfu_update_mode & DFU_UPDATE_BL)   /**< Macro for determining if a Bootloader update is ongoing. */
+#define IS_UPDATING_APP(START_PKT)  ((START_PKT).dfu_update_mode & DFU_UPDATE_APP)  /**< Macro for determining if a Application update is ongoing. */
+#define IMAGE_WRITE_IN_PROGRESS()   (m_data_received > 0)                           /**< Macro for determining if an image write is in progress. */
+#define IS_WORD_SIZED(SIZE)         ((SIZE & (sizeof(uint32_t) - 1)) == 0)          /**< Macro for checking that the provided is word sized. */
+
+/**@cond NO_DOXYGEN */
+static uint32_t                     m_data_received;                                /**< Amount of received data. */
+/**@endcond */
+
+/**@brief     Type definition of function used for preparing of the bank before receiving of a
+ *            software image.
+ *
+ * @param[in] image_size  Size of software image being received.
+ */
+typedef void (*dfu_bank_prepare_t)(uint32_t image_size);
+
+/**@brief     Type definition of function used for handling clear complete of the bank before 
+ *            receiving of a software image.
+ */
+typedef void (*dfu_bank_cleared_t)(void);
+
+/**@brief    Type definition of function used for activating of the software image received.
+ *
+ * @return  NRF_SUCCESS If the image has been successfully activated any other NRF_ERROR code in
+ *          case of a failure.
+ */
+typedef uint32_t (*dfu_bank_activate_t)(void);
+
+/**@brief Structure for holding of function pointers for needed prepare and activate procedure for
+ *        the requested update procedure. 
+ */
+typedef struct
+{
+    dfu_bank_prepare_t  prepare;                                                    /**< Function pointer to the prepare function called on start of update procedure. */
+    dfu_bank_cleared_t  cleared;                                                    /**< Function pointer to the cleared function called after prepare function completes. */
+    dfu_bank_activate_t activate;                                                   /**< Function pointer to the activate function called on finalizing the update procedure. */
+} dfu_bank_func_t;
+
+#endif // DFU_BANK_INTERNAL_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc.h
new file mode 100644
index 0000000000..fe44c98e1a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc.h
@@ -0,0 +1,107 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup nrf_dfu_ble_svc DFU BLE SVC
+ * @{
+ *
+ * @brief DFU BLE SVC in bootloader. The DFU BLE SuperVisor Calls allow an application to execute
+ *        functions in the installed bootloader.
+ *
+ * @details This module implements handling of SuperVisor Calls in the bootloader.
+ *          SuperVisor Calls allow for an application to execute calls into the bootloader.
+ *          Currently, it is possible to exchange bonding information (like keys) from the
+ *          application to a bootloader supporting DFU OTA using BLE, so the update process can be
+ *          done through an already existing bond.
+ *
+ * @note The application must make sure that all SuperVisor Calls (SVC) are forwarded to the
+ *       bootloader to ensure correct behavior. Forwarding of SVCs to the bootloader is
+ *       done using the SoftDevice SVC @ref sd_softdevice_vector_table_base_set with the value
+ *       present in @c NRF_UICR->NRFFW[0].
+ */
+
+#ifndef DFU_BLE_SVC_H__
+#define DFU_BLE_SVC_H__
+
+#include "nrf_svc.h"
+#include <stdint.h>
+#include "nrf_ble_gap.h"
+#include "nrf.h"
+#include "nrf_soc.h"
+#include "nrf_error_sdm.h"
+
+#define BOOTLOADER_SVC_BASE     0x0     /**< The number of the lowest SVC number reserved for the bootloader. */
+#define SYSTEM_SERVICE_ATT_SIZE 8       /**< Size of the system service attribute length including CRC-16 at the end. */
+
+/**@brief The SVC numbers used by the SVC functions in the SoC library. */
+enum BOOTLOADER_SVCS
+{
+    DFU_BLE_SVC_PEER_DATA_SET = BOOTLOADER_SVC_BASE,    /**< SVC number for the setting of peer data call. */
+    BOOTLOADER_SVC_LAST
+};
+
+/**@brief   DFU Peer data structure.
+ *
+ * @details This structure contains peer data needed for connection to a bonded device during DFU.
+ *          The peer data must be provided by the application to the bootloader during buttonless
+ *          update. See @ref dfu_ble_svc_peer_data_set. It contains bond information about the
+ *          desired DFU peer.
+ */
+typedef struct
+{
+    ble_gap_addr_t      addr;                                   /**< BLE GAP address of the device that initiated the DFU process. */
+    ble_gap_irk_t       irk;                                    /**< IRK of the device that initiated the DFU process if this device uses Private Resolvable Addresses. */
+    ble_gap_enc_key_t   enc_key;                                /**< Encryption key structure containing encrypted diversifier and LTK for re-establishing the bond. */
+    uint8_t             sys_serv_attr[SYSTEM_SERVICE_ATT_SIZE]; /**< System service attributes for restoring of Service Changed Indication setting in DFU mode. */
+} dfu_ble_peer_data_t;
+
+/**@brief   SVC Function for setting peer data containing address, IRK, and LTK to establish bonded
+ *          connection in DFU mode.
+ *
+ * @param[in] p_peer_data  Pointer to the peer data containing keys for the connection.
+ *
+ * @retval NRF_ERROR_NULL If a NULL pointer was provided as argument.
+ * @retval NRF_SUCCESS    If the function completed successfully.
+ */
+SVCALL(DFU_BLE_SVC_PEER_DATA_SET, uint32_t, dfu_ble_svc_peer_data_set(dfu_ble_peer_data_t * p_peer_data));
+
+#endif // DFU_BLE_SVC_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc_internal.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc_internal.h
new file mode 100644
index 0000000000..e737a2ef1e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_ble_svc_internal.h
@@ -0,0 +1,70 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+  
+/** @file
+ *
+ * @defgroup nrf_dfu_ble_svc_internal DFU BLE SVC internal
+ * @{
+ *
+ * @brief DFU BLE SVC internal functions in bootloader. The DFU BLE SuperVisor Calls allow an 
+ *        application to execute functions in the installed bootloader. This interface provides 
+ *        internal Bootloader DFU functions for retrieving data exchanged through SuperVisor Calls.
+ *
+ */
+
+#ifndef DFU_BLE_SVC_INTERNAL_H__
+#define DFU_BLE_SVC_INTERNAL_H__
+
+#include <stdint.h>
+#include "dfu_ble_svc.h"
+#include "ble_gap.h"
+
+/**@brief Internal bootloader/DFU function for retrieving peer data provided from application.
+ *
+ * @param[out] p_peer_data Peer data set by application to be used for DFU connection.
+ *
+ * @retval NRF_SUCCESS            If peer data is valid and can be used for connection.
+ * @retval NRF_ERROR_NULL         If p_peer_data is a NULL pointer.
+ * @retval NRF_ERROR_INVALID_DATA If peer data is not available or invalid.
+ */
+uint32_t dfu_ble_peer_data_get(dfu_ble_peer_data_t * p_peer_data);
+
+#endif // DFU_BLE_SVC_INTERNAL_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init.h
new file mode 100644
index 0000000000..a567576d4e
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init.h
@@ -0,0 +1,161 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup nrf_dfu_init Init packet handling in DFU
+ * @{
+ *
+ * @brief Device Firmware Update module type and function declaration for init packet handling.
+ *
+ * @details This header contains basic functionality for performing safety checks on software 
+ *          updates for \nRFXX based devices. It provides a skeleton for pre-checking an init packet
+ *          to ensure the following image is compatible with this device. A safety check should 
+ *          always be performed to prevent accidental flashing of unsupported applications or a
+ *          wrong combination of application and SoftDevice.
+ *          The device information contains information such as:
+ *          - Device type (2 bytes), for example Heart Rate. The device type is a number defined by
+ *            the customer. It can be located in UICR or FICR.
+ *          - Device revision (2 bytes), for example major revision 1, minor revision 0. The device
+ *            revision is a number defined by the customer. It can be located in UICR or FICR.
+ *          - List of SoftDevices supported by this application, for example 
+ *              0x0049 = S110v6_0_0 
+ *              0xFFFE = S110 development (any SoftDevice accepted),
+ *          - CRC or hash of firmware image
+ *
+ * @note This module does not support security features such as image signing, but the corresponding
+ *       implementation allows for such extensions.
+ *       If the init packet is signed by a trusted source, it must be decrypted before it can be 
+ *       processed.
+ */
+
+#ifndef DFU_INIT_H__
+#define DFU_INIT_H__
+
+#include <stdint.h>
+#include "nrf.h"
+
+/**@brief Structure contained in an init packet. Contains information on device type, revision, and 
+ *        supported SoftDevices.
+ */
+typedef struct
+{
+    uint16_t device_type;                                                                   /**< Device type (2 bytes), for example Heart Rate. This number must be defined by the customer before production. It can be located in UICR or FICR. */
+    uint16_t device_rev;                                                                    /**< Device revision (2 bytes), for example major revision 1, minor revision 0. This number must be defined by the customer before production. It can be located in UICR or FICR. */
+    uint32_t app_version;                                                                   /**< Application version for the image software. This field allows for additional checking, for example ensuring that a downgrade is not allowed. */
+    uint16_t softdevice_len;                                                                /**< Number of different SoftDevice revisions compatible with this application. The list of SoftDevice firmware IDs is defined in @ref softdevice. */
+    uint16_t softdevice[1];                                                                 /**< Variable length array of SoftDevices compatible with this application. The length of the array is specified in the length field. SoftDevice firmware id 0xFFFE indicates any SoftDevice. */
+} dfu_init_packet_t;
+
+/**@brief Structure holding basic device information settings.
+ */
+typedef struct
+{
+    uint16_t device_type;                                                                   /**< Device type (2 bytes), for example Heart Rate. This number must be defined by the customer before production. It can be located in UICR or FICR. */
+    uint16_t device_rev;                                                                    /**< Device revision (2 bytes), for example major revision 1, minor revision 0. This number must be defined by the customer before production. It can be located in UICR or FICR. */
+} dfu_device_info_t;
+
+/** The device info offset can be modified to place the device info settings at a different location.
+  * If the customer reserved UICR location is used for other application specific data, the offset
+  * must be updated to avoid collision with that data.
+  */
+/** [DFU UICR DEV offset] */
+#define UICR_CUSTOMER_DEVICE_INFO_OFFSET    0x0                                             /**< Device info offset inside the customer UICR reserved area. Customers may change this value to place the device information in a user-preferred location. */
+/** [DFU UICR DEV offset] */
+
+#define UICR_CUSTOMER_RESERVED_OFFSET       0x80                                            /**< Customer reserved area in the UICR. The area from UICR + 0x80 is reserved for customer usage. */
+#define DFU_DEVICE_INFO_BASE                (NRF_UICR_BASE + \
+                                             UICR_CUSTOMER_RESERVED_OFFSET + \
+                                             UICR_CUSTOMER_DEVICE_INFO_OFFSET)              /**< The device information base address inside of UICR. */
+#define DFU_DEVICE_INFO                     ((dfu_device_info_t *)DFU_DEVICE_INFO_BASE)     /**< The memory mapped structure for device information data. */
+
+#define DFU_DEVICE_TYPE_EMPTY               ((uint16_t)0xFFFF)                              /**< Mask indicating no device type is present in UICR. 0xFFFF is default flash pattern when not written with data. */
+#define DFU_DEVICE_REVISION_EMPTY           ((uint16_t)0xFFFF)                              /**< Mask indicating no device revision is present in UICR. 0xFFFF is default flash pattern when not written with data. */
+#define DFU_SOFTDEVICE_ANY                  ((uint16_t)0xFFFE)                              /**< Mask indicating that any SoftDevice is allowed for updating this application. Allows for easy development. Not to be used in production images. */
+
+
+/**@brief DFU prevalidate call for pre-checking the received init packet.
+ *
+ * @details  Pre-validation will safety check the firmware image to be transfered in second stage.
+ *           The function currently checks the device type, device revision, application firmware 
+ *           version, and supported SoftDevices. More checks should be added according to 
+ *           customer-specific requirements.
+ * 
+ * @param[in] p_init_data    Pointer to the init packet. If the init packet is encrypted or signed,
+ *                           it must first be decrypted before being checked.
+ * @param[in] init_data_len  Length of the init data.
+ *
+ * @retval NRF_SUCCESS              If the pre-validation succeeded, that means the image is 
+ *                                  supported by the device and it is considered to come from a 
+ *                                  trusted source (signing).
+ * @retval NRF_ERROR_INVALID_DATA   If the pre-validation failed, that means the image is not 
+ *                                  supported by the device or comes from an un-trusted source 
+ *                                  (signing).
+ * @retval NRF_ERROR_INVALID_LENGTH If the size of the init packet is not within the limits of 
+ *                                  the init packet handler.
+ */
+uint32_t dfu_init_prevalidate(uint8_t * p_init_data, uint32_t init_data_len);
+
+/**@brief DFU postvalidate call for post-checking the received image using the init packet.
+ *
+ * @details  Post-validation can verify the integrity check the firmware image received before 
+ *           activating the image.
+ *           Checks performed can be: 
+ *           - A simple CRC as shown in the corresponding implementation of this API in the file
+ *             dfu_init_template.c
+ *           - A hash for better verification of the image.
+ *           - A signature to ensure the image originates from a trusted source.
+ *           Checks are intended to be expanded for customer-specific requirements.
+ * 
+ * @param[in] p_image    Pointer to the received image. The init data provided in the call 
+ *                       \ref dfu_init_prevalidate will be used for validating the image.
+ * @param[in] image_len  Length of the image data.
+ *
+ * @retval NRF_SUCCESS             If the post-validation succeeded, that meant the integrity of the
+ *                                 image has been verified and the image originates from a trusted 
+ *                                 source (signing).
+ * @retval NRF_ERROR_INVALID_DATA  If the post-validation failed, that meant the post check of the 
+ *                                 image failed such as the CRC is not matching the image transfered
+ *                                 or the verification of the image fails (signing).
+ */
+uint32_t dfu_init_postvalidate(uint8_t * p_image, uint32_t image_len);
+
+#endif // DFU_INIT_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init_template.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init_template.c
new file mode 100644
index 0000000000..cb9e145455
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_init_template.c
@@ -0,0 +1,182 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup nrf_dfu_init_template Template file with an DFU init packet handling example.
+ * @{
+ *
+ * @ingroup nrf_dfu
+ *
+ * @brief This file contains a template on how to implement DFU init packet handling.
+ *
+ * @details The template shows how device type and revision can be used for a safety check of the 
+ *          received image. It shows how validation can be performed in two stages:
+ *          - Stage 1: Pre-check of firmware image before transfer to ensure the firmware matches:
+ *                     - Device Type.
+ *                     - Device Revision.
+ *                     Installed SoftDevice.
+ *                     This template can be extended with additional checks according to needs.
+ *                     For example, such a check could be the origin of the image (trusted source) 
+ *                     based on a signature scheme.
+ *          - Stage 2: Post-check of the image after image transfer but before installing firmware.
+ *                     For example, such a check could be an integrity check in form of hashing or 
+ *                     verification of a signature.
+ *                     In this template, a simple CRC check is carried out.
+ *                     The CRC check can be replaced with other mechanisms, like signing.
+ *
+ * @note This module does not support security features such as image signing, but the 
+ *       implementation allows for such extension.
+ *       If the init packet is signed by a trusted source, it must be decrypted before it can be
+ *       processed.
+ */
+
+#include "dfu_init.h"
+#include <stdint.h>
+#include <string.h>
+#include <dfu_types.h>
+#include "nrf_error.h"
+#include "crc16.h"
+
+#define DFU_INIT_PACKET_EXT_LENGTH_MIN      2                       //< Minimum length of the extended init packet. The extended init packet may contain a CRC, a HASH, or other data. This value must be changed according to the requirements of the system. The template uses a minimum value of two in order to hold a CRC. */
+#define DFU_INIT_PACKET_EXT_LENGTH_MAX      10                      //< Maximum length of the extended init packet. The extended init packet may contain a CRC, a HASH, or other data. This value must be changed according to the requirements of the system. The template uses a maximum value of 10 in order to hold a CRC and any padded data on transport layer without overflow. */
+
+static uint8_t m_extended_packet[DFU_INIT_PACKET_EXT_LENGTH_MAX];   //< Data array for storage of the extended data received. The extended data follows the normal init data of type \ref dfu_init_packet_t. Extended data can be used for a CRC, hash, signature, or other data. */
+static uint8_t m_extended_packet_length;                            //< Length of the extended data received with init packet. */
+
+
+uint32_t dfu_init_prevalidate(uint8_t * p_init_data, uint32_t init_data_len)
+{
+    uint32_t i = 0;
+    
+    // In order to support signing or encryption then any init packet decryption function / library
+    // should be called from here or implemented at this location.
+
+    // Length check to ensure valid data are parsed.
+    if (init_data_len < sizeof(dfu_init_packet_t))
+    {
+        return NRF_ERROR_INVALID_LENGTH;
+    }
+
+    // Current template uses clear text data so they can be casted for pre-check.
+    dfu_init_packet_t * p_init_packet = (dfu_init_packet_t *)p_init_data;
+
+    m_extended_packet_length = ((uint32_t)p_init_data + init_data_len) -
+                               (uint32_t)&p_init_packet->softdevice[p_init_packet->softdevice_len];
+    if (m_extended_packet_length < DFU_INIT_PACKET_EXT_LENGTH_MIN)
+    {
+        return NRF_ERROR_INVALID_LENGTH;
+    }
+
+    if (((uint32_t)p_init_data + init_data_len) < 
+        (uint32_t)&p_init_packet->softdevice[p_init_packet->softdevice_len])
+    {
+        return NRF_ERROR_INVALID_LENGTH;
+    }
+
+    memcpy(m_extended_packet,
+           &p_init_packet->softdevice[p_init_packet->softdevice_len],
+           m_extended_packet_length);
+
+/** [DFU init application version] */
+    // To support application versioning, this check should be updated.
+    // This template allows for any application to be installed. However, 
+    // customers can place a revision number at the bottom of the application 
+    // to be verified by the bootloader. This can be done at a location 
+    // relative to the application, for example the application start 
+    // address + 0x0100.
+/** [DFU init application version] */
+    
+    // First check to verify the image to be transfered matches the device type.
+    // If no Device type is present in DFU_DEVICE_INFO then any image will be accepted.
+    if ((DFU_DEVICE_INFO->device_type != DFU_DEVICE_TYPE_EMPTY) &&
+        (p_init_packet->device_type != DFU_DEVICE_INFO->device_type))
+    {
+        return NRF_ERROR_INVALID_DATA;
+    }
+    
+    // Second check to verify the image to be transfered matches the device revision.
+    // If no Device revision is present in DFU_DEVICE_INFO then any image will be accepted.
+    if ((DFU_DEVICE_INFO->device_rev != DFU_DEVICE_REVISION_EMPTY) &&
+        (p_init_packet->device_rev != DFU_DEVICE_INFO->device_rev))
+    {
+        return NRF_ERROR_INVALID_DATA;
+    }
+
+    // Third check: Check the array of supported SoftDevices by this application.
+    //              If the installed SoftDevice does not match any SoftDevice in the list then an
+    //              error is returned.
+    while (i < p_init_packet->softdevice_len)
+    {
+        if (p_init_packet->softdevice[i]   == DFU_SOFTDEVICE_ANY ||
+            p_init_packet->softdevice[i++] == SD_FWID_GET(MBR_SIZE))
+        {
+            return NRF_SUCCESS;
+        }
+    }
+    
+    // No matching SoftDevice found - Return NRF_ERROR_INVALID_DATA.
+    return NRF_ERROR_INVALID_DATA;
+}
+
+
+uint32_t dfu_init_postvalidate(uint8_t * p_image, uint32_t image_len)
+{
+    uint16_t image_crc;
+    uint16_t received_crc;
+    
+    // In order to support hashing (and signing) then the (decrypted) hash should be fetched and
+    // the corresponding hash should be calculated over the image at this location.
+    // If hashing (or signing) is added to the system then the CRC validation should be removed.
+
+    // calculate CRC from active block.
+    image_crc = crc16_compute(p_image, image_len, NULL);
+
+    // Decode the received CRC from extended data.    
+    received_crc = uint16_decode((uint8_t *)&m_extended_packet[0]);
+
+    // Compare the received and calculated CRC.
+    if (image_crc != received_crc)
+    {
+        return NRF_ERROR_INVALID_DATA;
+    }
+
+    return NRF_SUCCESS;
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_transport.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_transport.h
new file mode 100644
index 0000000000..20fe4c81ba
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_transport.h
@@ -0,0 +1,67 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup nrf_dfu_transport DFU transport API.
+ * @{     
+ *  
+ * @brief DFU transport module interface.
+ */
+ 
+#ifndef DFU_TRANSPORT_H__
+#define DFU_TRANSPORT_H__
+
+#include <stdint.h>
+
+/**@brief Function for starting the update of Device Firmware.
+ *
+ * @retval NRF_SUCCESS Operation success.   
+ */
+uint32_t dfu_transport_update_start(void);
+
+/**@brief Function for closing the transport layer.
+ *
+ * @retval NRF_SUCCESS Operation success.    
+ */
+uint32_t dfu_transport_close(void);
+
+#endif // DFU_TRANSPORT_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_types.h
new file mode 100644
index 0000000000..7a7421d878
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/dfu_types.h
@@ -0,0 +1,195 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup nrf_dfu_types Types and definitions.
+ * @{
+ *
+ * @ingroup nrf_dfu
+ *
+ * @brief Device Firmware Update module type and definitions.
+ */
+
+#ifndef DFU_TYPES_H__
+#define DFU_TYPES_H__
+
+#include <stdint.h>
+#include "nrf_sdm.h"
+#include "nrf_mbr.h"
+#include "nrf.h"
+#include "app_util.h"
+
+#define NRF_UICR_BOOT_START_ADDRESS         (NRF_UICR_BASE + 0x14)      /**< Register where the bootloader start address is stored in the UICR register. */
+
+#if defined(NRF52)                                                  
+#define NRF_UICR_MBR_PARAMS_PAGE_ADDRESS    (NRF_UICR_BASE + 0x18)      /**< Register where the mbr params page is stored in the UICR register. (Only in use in nRF52 MBR).*/
+#endif                                                              
+
+#define CODE_REGION_1_START                 SD_SIZE_GET(MBR_SIZE)       /**< This field should correspond to the size of Code Region 0, (which is identical to Start of Code Region 1), found in UICR.CLEN0 register. This value is used for compile safety, as the linker will fail if application expands into bootloader. Runtime, the bootloader will use the value found in UICR.CLEN0. */
+#define SOFTDEVICE_REGION_START             MBR_SIZE                    /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
+
+#ifdef NRF51        
+
+#define CODE_PAGE_SIZE                      0x0400                      /**< Size of a flash codepage. Used for size of the reserved flash space in the bootloader region. Will be runtime checked against NRF_UICR->CODEPAGESIZE to ensure the region is correct. */
+
+#ifdef SIGNING      
+
+#define BOOTLOADER_REGION_START             0x00039C00                  /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
+#define BOOTLOADER_SETTINGS_ADDRESS         0x0003D800                  /**< The field specifies the page location of the bootloader settings address. */
+
+#else       
+
+#define BOOTLOADER_REGION_START             0x0003C000                  /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
+#define BOOTLOADER_SETTINGS_ADDRESS         0x0003FC00                  /**< The field specifies the page location of the bootloader settings address. */
+
+#endif      
+
+
+        
+#elif NRF52     
+        
+#define BOOTLOADER_REGION_START             0x0007A000                  /**< This field should correspond to start address of the bootloader, found in UICR.RESERVED, 0x10001014, register. This value is used for sanity check, so the bootloader will fail immediately if this value differs from runtime value. The value is used to determine max application size for updating. */
+#define BOOTLOADER_SETTINGS_ADDRESS         0x0007F000                  /**< The field specifies the page location of the bootloader settings address. */
+#define BOOTLOADER_MBR_PARAMS_PAGE_ADDRESS  0x0007E000                  /**< The field specifies the page location of the mbr params page address. */
+        
+#define CODE_PAGE_SIZE                      0x1000                      /**< Size of a flash codepage. Used for size of the reserved flash space in the bootloader region. Will be runtime checked against NRF_UICR->CODEPAGESIZE to ensure the region is correct. */
+
+#else
+
+#error No target defined
+
+#endif
+
+#define DFU_REGION_TOTAL_SIZE           (BOOTLOADER_REGION_START - CODE_REGION_1_START)                 /**< Total size of the region between SD and Bootloader. */
+
+#ifndef DFU_APP_DATA_RESERVED
+#define DFU_APP_DATA_RESERVED           CODE_PAGE_SIZE * 0                                              /**< Size of Application Data that must be preserved between application updates. This value must be a multiple of page size. Page size is 0x400 (1024d) bytes, thus this value must be 0x0000, 0x0400, 0x0800, 0x0C00, 0x1000, etc. */
+#endif
+
+#define DFU_IMAGE_MAX_SIZE_FULL         (DFU_REGION_TOTAL_SIZE - DFU_APP_DATA_RESERVED)                 /**< Maximum size of an application, excluding save data from the application. */
+                                          
+#define DFU_IMAGE_MAX_SIZE_BANKED       (((DFU_IMAGE_MAX_SIZE_FULL) - \
+                                        (DFU_IMAGE_MAX_SIZE_FULL % (2 * CODE_PAGE_SIZE)))/2)            /**< Maximum size of an application, excluding save data from the application. */
+
+#define DFU_BL_IMAGE_MAX_SIZE           (BOOTLOADER_SETTINGS_ADDRESS - BOOTLOADER_REGION_START)         /**< Maximum size of a bootloader, excluding save data from the current bootloader. */
+
+#define DFU_BANK_0_REGION_START         CODE_REGION_1_START                                             /**< Bank 0 region start. */
+#define DFU_BANK_1_REGION_START         (DFU_BANK_0_REGION_START + DFU_IMAGE_MAX_SIZE_BANKED)           /**< Bank 1 region start. */
+
+#define EMPTY_FLASH_MASK                0xFFFFFFFF                                                      /**< Bit mask that defines an empty address in flash. */
+
+#define INVALID_PACKET                  0x00                                                            /**< Invalid packet identifies. */
+#define INIT_PACKET                     0x01                                                            /**< Packet identifies for initialization packet. */
+#define STOP_INIT_PACKET                0x02                                                            /**< Packet identifies for stop initialization packet. Used when complete init packet has been received so that the init packet can be used for pre validaiton. */
+#define START_PACKET                    0x03                                                            /**< Packet identifies for the Data Start Packet. */
+#define DATA_PACKET                     0x04                                                            /**< Packet identifies for a Data Packet. */
+#define STOP_DATA_PACKET                0x05                                                            /**< Packet identifies for the Data Stop Packet. */
+
+#define DFU_UPDATE_SD                   0x01                                                            /**< Bit field indicating update of SoftDevice is ongoing. */
+#define DFU_UPDATE_BL                   0x02                                                            /**< Bit field indicating update of bootloader is ongoing. */
+#define DFU_UPDATE_APP                  0x04                                                            /**< Bit field indicating update of application is ongoing. */
+
+#define DFU_INIT_RX                     0x00                                                            /**< Op Code identifies for receiving init packet. */
+#define DFU_INIT_COMPLETE               0x01                                                            /**< Op Code identifies for transmission complete of init packet. */
+
+// Safe guard to ensure during compile time that the DFU_APP_DATA_RESERVED is a multiple of page size.
+STATIC_ASSERT((((DFU_APP_DATA_RESERVED) & (CODE_PAGE_SIZE - 1)) == 0x00));
+
+/**@brief Structure holding a start packet containing update mode and image sizes.
+ */
+typedef struct
+{
+    uint8_t  dfu_update_mode;                                                                           /**< Packet type, used to identify the content of the received packet referenced by data packet. */
+    uint32_t sd_image_size;                                                                             /**< Size of the SoftDevice image to be transferred. Zero if no SoftDevice image will be transfered. */
+    uint32_t bl_image_size;                                                                             /**< Size of the Bootloader image to be transferred. Zero if no Bootloader image will be transfered. */
+    uint32_t app_image_size;                                                                            /**< Size of the application image to be transmitted. Zero if no Bootloader image will be transfered. */
+} dfu_start_packet_t;
+
+/**@brief Structure holding a bootloader init/data packet received.
+ */
+typedef struct
+{
+    uint32_t   packet_length;                                                                           /**< Packet length of the data packet. Each data is word size, meaning length of 4 is 4 words, not bytes. */
+    uint32_t * p_data_packet;                                                                           /**< Data Packet received. Each data is a word size entry. */
+} dfu_data_packet_t;
+
+/**@brief Structure for holding dfu update packet. Packet type indicate the type of packet.
+ */
+typedef struct
+{
+    uint32_t   packet_type;                                                                             /**< Packet type, used to identify the content of the received packet referenced by data packet. */
+    union
+    {
+        dfu_data_packet_t    data_packet;                                                               /**< Used when packet type is INIT_PACKET or DATA_PACKET. Packet contains data received for init or data. */
+        dfu_start_packet_t * start_packet;                                                              /**< Used when packet type is START_DATA_PACKET. Will contain information on software to be updtaed, i.e. SoftDevice, Bootloader and/or Application along with image sizes. */
+    } params;
+} dfu_update_packet_t;
+
+/**@brief DFU status error codes.
+*/
+typedef enum
+{
+    DFU_UPDATE_APP_COMPLETE,                                                                            /**< Status update of application complete.*/
+    DFU_UPDATE_SD_COMPLETE,                                                                             /**< Status update of SoftDevice update complete. Note that this solely indicates that a new SoftDevice has been received and stored in bank 0 and 1. */
+    DFU_UPDATE_SD_SWAPPED,                                                                              /**< Status update of SoftDevice update complete. Note that this solely indicates that a new SoftDevice has been received and stored in bank 0 and 1. */
+    DFU_UPDATE_BOOT_COMPLETE,                                                                           /**< Status update complete.*/
+    DFU_BANK_0_ERASED,                                                                                  /**< Status bank 0 erased.*/
+    DFU_TIMEOUT,                                                                                        /**< Status timeout.*/
+    DFU_RESET                                                                                           /**< Status Reset to indicate current update procedure has been aborted and system should reset. */
+} dfu_update_status_code_t;
+
+/**@brief Structure holding DFU complete event.
+*/
+typedef struct
+{
+    dfu_update_status_code_t status_code;                                                               /**< Device Firmware Update status. */
+    uint16_t                 app_crc;                                                                   /**< CRC of the recieved application. */
+    uint32_t                 sd_size;                                                                   /**< Size of the recieved SoftDevice. */
+    uint32_t                 bl_size;                                                                   /**< Size of the recieved BootLoader. */
+    uint32_t                 app_size;                                                                  /**< Size of the recieved Application. */
+    uint32_t                 sd_image_start;                                                            /**< Location in flash where the received SoftDevice image is stored. */
+} dfu_update_status_t;
+
+/**@brief Update complete handler type. */
+typedef void (*dfu_complete_handler_t)(dfu_update_status_t dfu_update_status);
+
+#endif // DFU_TYPES_H__
+
+/**@} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h
new file mode 100644
index 0000000000..8f5d83ba0c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_mem_pool_internal.h
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+ 
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE       32u    /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE       600u   /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 2u     /**< RX buffer element size. */
+ 
+#endif // MEM_POOL_INTERNAL_H__
+ 
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_transport_config.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_transport_config.h
new file mode 100644
index 0000000000..8b7a4f41c2
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/bootloader_dfu/hci_transport/hci_transport_config.h
@@ -0,0 +1,72 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup ble_sdk_bootloader_hci_congfig HCI Transport Layer Configuration
+ * @{
+ * @ingroup dfu_bootloader_api
+ * @brief Definition of HCI Transport Layer configurable parameters
+ */
+
+#ifndef HCI_TRANSPORT_CONFIG_H__
+#define HCI_TRANSPORT_CONFIG_H__
+
+#include "boards.h"                                                     /**< Default include for boards.h which means that default pin numbers will be used for RX, TX, CTS, and RTS on the UART. Other pin number can be used if desired. */
+
+/** This section covers configurable parameters for the HCI Transport SLIP layer. */
+#define HCI_SLIP_UART_RX_PIN_NUMBER  RX_PIN_NUMBER                      /**< Defines the UART RX pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_TX_PIN_NUMBER  TX_PIN_NUMBER                      /**< Defines the UART TX pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_RTS_PIN_NUMBER RTS_PIN_NUMBER                     /**< Defines the UART RTS pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_CTS_PIN_NUMBER CTS_PIN_NUMBER                     /**< Defines the UART CTS pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_MODE           APP_UART_FLOW_CONTROL_DISABLED     /**< Defines the UART mode to be used. Use UART Low Power with Flow Control - Valid values are defined in \ref app_uart_flow_control_t. For further information on the UART Low Power mode, please refer to: \ref app_uart . */
+
+#define HCI_SLIP_UART_BAUDRATE       UART_BAUDRATE_BAUDRATE_Baud38400   /**< Defines the UART Baud rate. Default is 38400 baud. */
+
+/** This section covers configurable parameters for the HCI Transport layer that are used for calculating correct value for the retransmission timer timeout. */
+#define MAX_PACKET_SIZE_IN_BITS      8000u                              /**< Maximum size of a single application packet in bits. */      
+#define USED_BAUD_RATE               38400u                             /**< The used uart baudrate. */
+
+#endif // HCI_TRANSPORT_CONFIG_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.c
new file mode 100644
index 0000000000..76180a86e8
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.c
@@ -0,0 +1,58 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "crc16.h"
+
+#include <stdlib.h>
+
+uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc)
+{
+    uint16_t crc = (p_crc == NULL) ? 0xFFFF : *p_crc;
+
+    for (uint32_t i = 0; i < size; i++)
+    {
+        crc  = (uint8_t)(crc >> 8) | (crc << 8);
+        crc ^= p_data[i];
+        crc ^= (uint8_t)(crc & 0xFF) >> 4;
+        crc ^= (crc << 8) << 4;
+        crc ^= ((crc & 0xFF) << 4) << 1;
+    }
+
+    return crc;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.h
new file mode 100644
index 0000000000..d57197ed9c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/crc16/crc16.h
@@ -0,0 +1,71 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/** @file
+ *
+ * @defgroup crc_compute CRC compute
+ * @{
+ * @ingroup hci_transport
+ *
+ * @brief    This module implements CRC-16-CCITT (polynomial 0x1021) with 0xFFFF initial value.
+ *           The data can be passed in multiple blocks.
+ */
+ 
+#ifndef CRC16_H__
+#define CRC16_H__
+
+#include <stdint.h>
+
+/**@brief Function for calculating CRC-16 in blocks.
+ *
+ * Feed each consecutive data block into this function, along with the current value of p_crc as
+ * returned by the previous call of this function. The first call of this function should pass NULL
+ * as the initial value of the crc in p_crc.
+ *
+ * @param[in] p_data The input data block for computation.
+ * @param[in] size   The size of the input data block in bytes.
+ * @param[in] p_crc  The previous calculated CRC-16 value or NULL if first call.
+ *
+ * @return The updated CRC-16 value, based on the input supplied.
+ */
+uint16_t crc16_compute(uint8_t const * p_data, uint32_t size, uint16_t const * p_crc);
+
+#endif // CRC16_H__
+ 
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/experimental_section_vars/section_vars.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/experimental_section_vars/section_vars.h
new file mode 100644
index 0000000000..abd489b06c
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/experimental_section_vars/section_vars.h
@@ -0,0 +1,290 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SECTION_VARS_H__
+#define SECTION_VARS_H__
+
+
+/**
+ * @defgroup section_vars Section variables
+ * @ingroup app_common
+ * @{
+ *
+ * @brief Section variables.
+ */
+
+#if defined(__ICCARM__)
+// Enable IAR language extensions
+#pragma language=extended
+#endif
+
+
+// Macro to delay macro expansion.
+#define NRF_PRAGMA(x)       _Pragma(#x)
+
+
+/**@brief   Macro to register a named section.
+ *
+ * @param[in]   section_name    Name of the section to register.
+ */
+#if defined(__CC_ARM)
+
+// Not required by this compiler.
+#define NRF_SECTION_VARS_REGISTER_SECTION(section_name)
+
+#elif defined(__GNUC__)
+
+// Not required by this compiler.
+#define NRF_SECTION_VARS_REGISTER_SECTION(section_name)
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_REGISTER_SECTION(section_name)     NRF_PRAGMA(section = #section_name)
+
+#endif
+
+
+/*lint -save -e27 */
+
+/**@brief   Macro to obtain the linker symbol for the beginning of a given section.
+ *
+ * @details The symbol that this macro resolves to is used to obtain a section start address.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_START_SYMBOL(section_name)         section_name ## $$Base
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_START_SYMBOL(section_name)         __start_ ## section_name
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_START_SYMBOL(section_name)         __section_begin(#section_name)
+
+#endif
+
+
+/**@brief   Macro to obtain the linker symbol for the end of a given section.
+ *
+ * @details The symbol that this macro resolves to is used to obtain a section end address.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_END_SYMBOL(section_name)           section_name ## $$Limit
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_END_SYMBOL(section_name)           __stop_ ## section_name
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_END_SYMBOL(section_name)           __section_end(#section_name)
+
+#endif
+
+/*lint -restore */
+
+
+/**@brief   Macro for retrieving the length of a given section, in bytes.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_LENGTH(section_name) \
+    ((uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name))
+
+#elif defined(__GNUC__)
+
+ #define NRF_SECTION_VARS_LENGTH(section_name) \
+    ((uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name))
+
+#elif defined(__ICCARM__)
+
+ #define NRF_SECTION_VARS_LENGTH(section_name) \
+    ((uint32_t)NRF_SECTION_VARS_END_SYMBOL(section_name) - (uint32_t)NRF_SECTION_VARS_START_SYMBOL(section_name))
+
+#endif
+      
+
+/**@brief   Macro to obtain the start address of a named section.
+ *
+ * param[in]    section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_START_ADDR(section_name)       (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name)
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_START_ADDR(section_name)       (uint32_t)&NRF_SECTION_VARS_START_SYMBOL(section_name)
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_START_ADDR(section_name)       (uint32_t)iar_ ## section_name ## _start
+
+#endif
+
+      
+/*@brief    Macro to obtain the end address of a named section.
+ *
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_END_ADDR(section_name)         (uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_END_ADDR(section_name)         (uint32_t)&NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_END_ADDR(section_name)         (uint32_t)iar_ ## section_name ## _end
+
+#endif
+
+
+/**@brief   Macro to extern a named section start and stop symbols.
+ *
+ * @note    These declarations are required for GCC and Keil linkers (but not for IAR's).
+ *
+ * @param[in]   type_name       Name of the type stored in the section.
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_REGISTER_SYMBOLS(type_name, section_name)  \
+    extern type_name * NRF_SECTION_VARS_START_SYMBOL(section_name); \
+    extern void      * NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_REGISTER_SYMBOLS(type_name, section_name)  \
+    extern type_name * NRF_SECTION_VARS_START_SYMBOL(section_name); \
+    extern void      * NRF_SECTION_VARS_END_SYMBOL(section_name)
+
+#elif defined(__ICCARM__)
+
+// No symbol registration required for IAR.
+#define NRF_SECTION_VARS_REGISTER_SYMBOLS(type_name, section_name)                  \
+    extern void * iar_ ## section_name ## _start = __section_begin(#section_name);  \
+    extern void * iar_ ## section_name ## _end   = __section_end(#section_name)
+
+#endif
+
+
+/**@brief   Macro to declare a variable to be placed in a named section.
+ *
+ * @details Declares a variable to be placed in a named section. This macro ensures that its symbol
+ *          is not stripped by the linker because of optimizations.
+ *
+ * @warning The order with which variables are placed in a section is implementation dependant.
+ *          Generally, variables are placed in a section depending on the order with which they
+ *          are found by the linker.
+ *
+ * @warning The symbols added in the named section must be word aligned to prevent padding.
+ *
+ * @param[in]   section_name    Name of the section.
+ * @param[in]   type_def        Datatype of the variable to place in the given section.
+ */
+#if defined(__CC_ARM)
+    
+#define NRF_SECTION_VARS_ADD(section_name, type_def) \
+    static type_def __attribute__ ((section(#section_name))) __attribute__((used))
+
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_ADD(section_name, type_def) \
+    static type_def __attribute__ ((section("."#section_name))) __attribute__((used))
+
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_ADD(section_name, type_def) \
+    __root type_def @ #section_name
+
+#endif
+
+
+/**@brief   Macro to get symbol from named section.
+ *
+ * @warning     The stored symbol can only be resolved using this macro if the 
+ *              type of the data is word aligned. The operation of acquiring 
+ *              the stored symbol relies on sizeof of the stored type, no 
+ *              padding can exist in the named section in between individual 
+ *              stored items or this macro will fail.
+ *
+ * @param[in]   i               Index of item in section.
+ * @param[in]   type_name       Type name of item in section.
+ * @param[in]   section_name    Name of the section.
+ */
+#if defined(__CC_ARM)
+
+#define NRF_SECTION_VARS_GET(i, type_name, section_name) \
+    (type_name*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(type_name))
+      
+#elif defined(__GNUC__)
+
+#define NRF_SECTION_VARS_GET(i, type_name, section_name) \
+    (type_name*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(type_name))
+      
+#elif defined(__ICCARM__)
+
+#define NRF_SECTION_VARS_GET(i, type_name, section_name) \
+    (type_name*)(NRF_SECTION_VARS_START_ADDR(section_name) + i * sizeof(type_name))
+
+#endif
+
+
+/**@brief   Macro to get number of items in named section.
+ *
+ * @param[in]   type_name       Type name of item in section.
+ * @param[in]   section_name    Name of the section.
+ */
+#define NRF_SECTION_VARS_COUNT(type_name, section_name) \
+    NRF_SECTION_VARS_LENGTH(section_name) / sizeof(type_name)
+
+/** @} */
+
+#endif // SECTION_VARS_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/config/fds_config.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/config/fds_config.h
new file mode 100644
index 0000000000..dbcf872748
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/config/fds_config.h
@@ -0,0 +1,90 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef FDS_CONFIG_H__
+#define FDS_CONFIG_H__
+
+ /**
+ * @file fds_config.h
+ *
+ * @defgroup flash_data_storage_config Configuration options
+ * @ingroup flash_data_storage
+ * @{
+ * @brief   Configuration options for FDS.
+ */
+
+/**@brief   Configures the size of the internal queue. */
+#define FDS_OP_QUEUE_SIZE           (4)
+
+/**@brief   Determines how many @ref fds_record_chunk_t structures can be buffered at any time. */
+#define FDS_CHUNK_QUEUE_SIZE        (8)
+
+/**@brief   Configures the maximum number of callbacks that can be registered. */
+#define FDS_MAX_USERS               (3)
+
+/**@brief   Configures the number of virtual flash pages to use.
+ *
+ * The total amount of flash memory that is used by FDS amounts to
+ * @ref FDS_VIRTUAL_PAGES * @ref FDS_VIRTUAL_PAGE_SIZE * 4 bytes.
+ * On nRF51 ICs, this defaults to 3 * 256 * 4 bytes = 3072 bytes.
+ * On nRF52 ICs, it defaults to 3 * 1024 * 4 bytes = 12288 bytes.
+ *
+ * One of the virtual pages is reserved by the system for garbage collection. Therefore, the
+ * minimum is two virtual pages: one page to store data and one page to be used by the system for
+ * garbage collection.
+ */
+#define FDS_VIRTUAL_PAGES           (3)
+
+/**@brief   Configures the size of a virtual page of flash memory, expressed in number of
+ *          4-byte words.
+ *
+ * By default, a virtual page is the same size as a physical page. Therefore, the default size
+ * is 1024 bytes for nRF51 ICs and 4096 bytes for nRF52 ICs.
+ *
+ * The size of a virtual page must be a multiple of the size of a physical page.
+ */
+#if   defined(NRF51)
+    #define FDS_VIRTUAL_PAGE_SIZE   (256)
+#elif defined(NRF52)
+    #define FDS_VIRTUAL_PAGE_SIZE   (1024)
+#endif
+
+/** @} */
+
+#endif // FDS_CONFIG_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.c
new file mode 100644
index 0000000000..309a306d0d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.c
@@ -0,0 +1,2085 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "fds.h"
+#include "fds_config.h"
+#include "fds_internal_defs.h"
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include "fstorage.h"
+#include "app_util.h"
+#include "nrf_error.h"
+
+#if defined(FDS_CRC_ENABLED)
+    #include "crc16.h"
+#endif
+
+
+static void fs_event_handler(fs_evt_t const * const evt, fs_ret_t result);
+
+// Our fstorage configuration.
+FS_REGISTER_CFG(fs_config_t fs_config) =
+{
+    .callback  = fs_event_handler,
+    .num_pages = FDS_PHY_PAGES,
+    // We register with the highest priority in order to be assigned
+    // the pages with the highest memory address (closest to the bootloader).
+    .priority  = 0xFF
+};
+
+// Used to flag a record as dirty, i.e. ready for garbage collection.
+static fds_tl_t const m_fds_tl_dirty =
+{
+    .record_key   = FDS_RECORD_KEY_DIRTY,
+    .length_words = 0xFFFF  // Leave the record length field unchanged in flash.
+};
+
+// Internal status flags.
+static uint8_t              m_flags;
+
+// The number of registered users and their callback functions.
+static uint8_t              m_users;
+static fds_cb_t             m_cb_table[FDS_MAX_USERS];
+
+// The latest (largest) record ID written so far.
+static uint32_t             m_latest_rec_id;
+
+// The internal queues.
+static fds_op_queue_t       m_op_queue;
+static fds_chunk_queue_t    m_chunk_queue;
+
+// Structures used to hold informations about virtual pages.
+static fds_page_t           m_pages[FDS_MAX_PAGES];
+static fds_swap_page_t      m_swap_page;
+
+// Garbage collection data.
+static fds_gc_data_t        m_gc;
+
+
+static void flag_set(fds_flags_t flag)
+{
+    CRITICAL_SECTION_ENTER();
+    m_flags |= flag;
+    CRITICAL_SECTION_EXIT();
+}
+
+
+static void flag_clear(fds_flags_t flag)
+{
+    CRITICAL_SECTION_ENTER();
+    m_flags &= ~(flag);
+    CRITICAL_SECTION_EXIT();
+}
+
+
+static bool flag_is_set(fds_flags_t flag)
+{
+    return (m_flags & flag);
+}
+
+
+static void event_send(fds_evt_t const * const p_evt)
+{
+    for (uint32_t user = 0; user < FDS_MAX_USERS; user++)
+    {
+        if (m_cb_table[user] != NULL)
+        {
+            m_cb_table[user](p_evt);
+        }
+    }
+}
+
+
+static void event_prepare(fds_op_t const * const p_op, fds_evt_t * const p_evt)
+{
+    switch (p_op->op_code)
+    {
+        case FDS_OP_INIT:
+            p_evt->id = FDS_EVT_INIT;
+            break;
+
+        case FDS_OP_WRITE:
+            p_evt->id               = FDS_EVT_WRITE;
+            p_evt->write.file_id    = p_op->write.header.ic.file_id;
+            p_evt->write.record_key = p_op->write.header.tl.record_key;
+            p_evt->write.record_id  = p_op->write.header.record_id;
+            break;
+
+        case FDS_OP_UPDATE:
+            p_evt->id                      = FDS_EVT_UPDATE;
+            p_evt->write.file_id           = p_op->write.header.ic.file_id;
+            p_evt->write.record_key        = p_op->write.header.tl.record_key;
+            p_evt->write.record_id         = p_op->write.header.record_id;
+            p_evt->write.is_record_updated = (p_op->write.step == FDS_OP_WRITE_DONE);
+            break;
+
+        case FDS_OP_DEL_RECORD:
+            p_evt->id             = FDS_EVT_DEL_RECORD;
+            p_evt->del.file_id    = p_op->del.file_id;
+            p_evt->del.record_key = p_op->del.record_key;
+            p_evt->del.record_id  = p_op->del.record_to_delete;
+            break;
+
+        case FDS_OP_DEL_FILE:
+            p_evt->id             = FDS_EVT_DEL_FILE;
+            p_evt->del.file_id    = p_op->del.file_id;
+            p_evt->del.record_key = FDS_RECORD_KEY_DIRTY;
+            break;
+
+        case FDS_OP_GC:
+            p_evt->id = FDS_EVT_GC;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+}
+
+
+static bool header_is_valid(fds_header_t const * const p_header)
+{
+    return ((p_header->ic.file_id    != FDS_FILE_ID_INVALID) &&
+            (p_header->tl.record_key != FDS_RECORD_KEY_DIRTY));
+}
+
+
+static bool address_is_valid(uint32_t const * const p_addr)
+{
+    return ((p_addr != NULL) &&
+            (p_addr >= fs_config.p_start_addr) &&
+            (p_addr <= fs_config.p_end_addr)   &&
+            (is_word_aligned(p_addr)));
+}
+
+
+static bool chunk_is_aligned(fds_record_chunk_t const * const p_chunk, uint32_t num_chunks)
+{
+    for (uint32_t i = 0; i < num_chunks; i++)
+    {
+        if (!is_word_aligned(p_chunk[i].p_data))
+        {
+            return false;
+        }
+    }
+    return true;
+}
+
+
+// Reads a page tag, and determines if the page is used to store data or as swap.
+static fds_page_type_t page_identify(uint32_t const * const p_page_addr)
+{
+    if (p_page_addr[FDS_PAGE_TAG_WORD_0] != FDS_PAGE_TAG_MAGIC)
+    {
+        return FDS_PAGE_UNDEFINED;
+    }
+
+    switch (p_page_addr[FDS_PAGE_TAG_WORD_1])
+    {
+        case FDS_PAGE_TAG_SWAP:
+            return FDS_PAGE_SWAP;
+
+        case FDS_PAGE_TAG_DATA:
+            return FDS_PAGE_DATA;
+
+        default:
+            return FDS_PAGE_UNDEFINED;
+    }
+}
+
+
+static bool page_is_erased(uint32_t const * const p_page_addr)
+{
+    for (uint32_t i = 0; i < FDS_PAGE_SIZE; i++)
+    {
+        if (*(p_page_addr + i) != FDS_ERASED_WORD)
+        {
+            return false;
+        }
+    }
+
+    return true;
+}
+
+
+// NOTE: Must be called from within a critical section.
+static bool page_has_space(uint16_t page, uint16_t length_words)
+{
+    length_words += m_pages[page].write_offset;
+    length_words += m_pages[page].words_reserved;
+    return (length_words < FDS_PAGE_SIZE);
+}
+
+
+// Given a pointer to a record, find the index of the page on which it is stored.
+// Returns FDS_SUCCESS if the page is found, FDS_ERR_NOT_FOUND otherwise.
+static ret_code_t page_from_record(uint16_t * const p_page, uint32_t const * const p_rec)
+{
+    ret_code_t ret = FDS_ERR_NOT_FOUND;
+
+    CRITICAL_SECTION_ENTER();
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        if ((p_rec > m_pages[i].p_addr) &&
+            (p_rec < m_pages[i].p_addr + FDS_PAGE_SIZE))
+        {
+            ret     = FDS_SUCCESS;
+            *p_page = i;
+            break;
+        }
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+// Scan a page to determine how many words have been written to it.
+// This information is used to set the page write offset during initialization.
+// Additionally, this function updates the latest record ID as it proceeds.
+// If an invalid record header is found, the can_gc argument is set to true.
+static void page_scan(uint32_t const *       p_addr,
+                      uint16_t       * const words_written,
+                      bool           * const can_gc)
+{
+    uint32_t const * const p_end_addr          = p_addr + FDS_PAGE_SIZE;
+    bool                   dirty_record_found  = false;
+
+    p_addr         += FDS_PAGE_TAG_SIZE;
+    *words_written  = FDS_PAGE_TAG_SIZE;
+
+    while ((p_addr < p_end_addr) && (*p_addr != FDS_ERASED_WORD))
+    {
+        // NOTE: Skip records with a dirty key or with a missing file ID.
+        fds_header_t const * const p_header = (fds_header_t*)p_addr;
+
+        if (!header_is_valid(p_header))
+        {
+            dirty_record_found = true;
+        }
+        else
+        {
+            // Update the latest (largest) record ID.
+            if (p_header->record_id > m_latest_rec_id)
+            {
+               m_latest_rec_id = p_header->record_id;
+            }
+        }
+
+        // Jump to the next record.
+        p_addr         += (FDS_HEADER_SIZE + p_header->tl.length_words);
+        *words_written += (FDS_HEADER_SIZE + p_header->tl.length_words);
+    }
+
+    if (can_gc != NULL)
+    {
+        *can_gc = dirty_record_found;
+    }
+}
+
+
+static void page_offsets_update(fds_page_t * const p_page, uint16_t length_words)
+{
+    p_page->write_offset   += (FDS_HEADER_SIZE + length_words);
+    p_page->words_reserved -= (FDS_HEADER_SIZE + length_words);
+}
+
+
+// Tags a page as swap, i.e., reserved for GC.
+static ret_code_t page_tag_write_swap()
+{
+    // Needs to be statically allocated since it will be written to flash.
+    static uint32_t const page_tag_swap[] = {FDS_PAGE_TAG_MAGIC, FDS_PAGE_TAG_SWAP};
+    return fs_store(&fs_config, m_swap_page.p_addr, page_tag_swap, FDS_PAGE_TAG_SIZE);
+}
+
+
+// Tags a page as data, i.e, ready for storage.
+static ret_code_t page_tag_write_data(uint32_t const * const p_page_addr)
+{
+    // Needs to be statically allocated since it will be written to flash.
+    static uint32_t const page_tag_data[] = {FDS_PAGE_TAG_MAGIC, FDS_PAGE_TAG_DATA};
+    return fs_store(&fs_config, p_page_addr, page_tag_data, FDS_PAGE_TAG_SIZE);
+}
+
+
+// Reserve space on a page.
+// NOTE: this function takes into the account the space required for the record header.
+static ret_code_t write_space_reserve(uint16_t length_words, uint16_t * p_page)
+{
+    bool           space_reserved  = false;
+    uint16_t const total_len_words = length_words + FDS_HEADER_SIZE;
+
+    if (total_len_words >= FDS_PAGE_SIZE - FDS_PAGE_TAG_SIZE)
+    {
+        return FDS_ERR_RECORD_TOO_LARGE;
+    }
+
+    CRITICAL_SECTION_ENTER();
+    for (uint16_t page = 0; page < FDS_MAX_PAGES; page++)
+    {
+        if ((m_pages[page].page_type == FDS_PAGE_DATA) &&
+            (page_has_space(page, total_len_words)))
+        {
+            space_reserved = true;
+            *p_page        = page;
+
+            m_pages[page].words_reserved += total_len_words;
+            break;
+        }
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return (space_reserved) ? FDS_SUCCESS : FDS_ERR_NO_SPACE_IN_FLASH;
+}
+
+
+// Undo a write_space_reserve() call.
+// NOTE: Must be called within a critical section.
+static void write_space_free(uint16_t length_words, uint16_t page)
+{
+    m_pages[page].words_reserved -= (length_words + FDS_HEADER_SIZE);
+}
+
+
+static uint32_t record_id_new(void)
+{
+    CRITICAL_SECTION_ENTER();
+    m_latest_rec_id++;
+    CRITICAL_SECTION_EXIT();
+    return m_latest_rec_id;
+}
+
+
+// Given a page and a record, finds the next valid record on that page. If p_record is NULL,
+// search from the beginning of the page, otherwise, resume searching from the address
+// pointed by p_record. Returns true if a record is found, returns false otherwise.
+// If no record is found, p_record is unchanged.
+static bool record_find_next(uint16_t page, uint32_t const ** p_record)
+{
+    fds_header_t const * p_header;
+    uint32_t     const * p_next_rec = (*p_record);
+
+    // If this is not the first invocation on this page, then jump to the next record.
+    // Otherwise, start searching from the beginning of the page.
+    if (p_next_rec != NULL)
+    {
+        p_header    = ((fds_header_t*)p_next_rec);
+        p_next_rec += (FDS_HEADER_SIZE + p_header->tl.length_words);
+    }
+    else
+    {
+        p_next_rec = m_pages[page].p_addr + FDS_PAGE_TAG_SIZE;
+    }
+
+    // Read records from the page, until a valid record is found or the end of the page is
+    // reached. The argument p_record is only updated if a valid record is found.
+    while ((p_next_rec < (m_pages[page].p_addr + FDS_PAGE_SIZE) &&
+           *p_next_rec != FDS_ERASED_WORD))
+    {
+        p_header = (fds_header_t*)p_next_rec;
+
+        if (header_is_valid(p_header))
+        {
+            *p_record = p_next_rec;
+            return true;
+        }
+        else
+        {
+            // The record is not valid, jump to the next.
+            p_next_rec += (FDS_HEADER_SIZE + (p_header->tl.length_words));
+        }
+    }
+
+    // No more valid records on this page.
+    return false;
+}
+
+
+// Find a record given its descriptor and retrive the page in which the record is stored.
+// NOTE: Do not pass NULL as an argument for p_page.
+static bool record_find_by_desc(fds_record_desc_t * const p_desc, uint16_t * const p_page)
+{
+    // If the gc_run_count field in the descriptor matches our counter, then the record has
+    // not been moved. If the address is valid, and the record ID matches, there is no need
+    // to find the record again. Only lookup the page in which the record is stored.
+
+    if ((address_is_valid(p_desc->p_record))     &&
+        (p_desc->gc_run_count == m_gc.run_count) &&
+        (p_desc->record_id    == ((fds_header_t*)p_desc->p_record)->record_id))
+    {
+        return (page_from_record(p_page, p_desc->p_record) == FDS_SUCCESS);
+    }
+
+    // Otherwise, find the record in flash.
+    for (*p_page = 0; *p_page < FDS_MAX_PAGES; (*p_page)++)
+    {
+        // Set p_record to NULL to make record_find_next() search from the beginning of the page.
+        uint32_t const * p_record = NULL;
+
+        while (record_find_next(*p_page, &p_record))
+        {
+            fds_header_t const * const p_header = (fds_header_t*)p_record;
+            if (p_header->record_id == p_desc->record_id)
+            {
+                p_desc->p_record     = p_record;
+                p_desc->gc_run_count = m_gc.run_count;
+                return true;
+            }
+        }
+    }
+
+    return false;
+}
+
+
+// Search for a record and return its descriptor.
+// If p_file_id is NULL, only the record key will be used for matching.
+// If p_record_key is NULL, only the file ID will be used for matching.
+// If both are NULL, it will iterate through all records.
+static ret_code_t record_find(uint16_t          const * const p_file_id,
+                              uint16_t          const * const p_record_key,
+                              fds_record_desc_t       * const p_desc,
+                              fds_find_token_t        * const p_token)
+{
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_desc == NULL || p_token == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    // Begin (or resume) searching for a record.
+    for (; p_token->page < FDS_MAX_PAGES; p_token->page++)
+    {
+        if (m_pages[p_token->page].page_type != FDS_PAGE_DATA)
+        {
+            // Skip this page.
+            continue;
+        }
+
+        while (record_find_next(p_token->page, &p_token->p_addr))
+        {
+            fds_header_t const * const p_header = (fds_header_t*)p_token->p_addr;
+
+            // A valid record was found, check its header for a match.
+            if ((p_file_id != NULL) &&
+                (p_header->ic.file_id != *p_file_id))
+            {
+                continue;
+            }
+
+            if ((p_record_key != NULL) &&
+                (p_header->tl.record_key != *p_record_key))
+            {
+                continue;
+            }
+
+            // Record found; update the descriptor.
+            p_desc->record_id    = p_header->record_id;
+            p_desc->p_record     = p_token->p_addr;
+            p_desc->gc_run_count = m_gc.run_count;
+
+            return FDS_SUCCESS;
+        }
+
+        // We have scanned an entire page. Set the address in the token to NULL
+        // so that it will be updated in the next iteration.
+        p_token->p_addr = NULL;
+    }
+
+    return FDS_ERR_NOT_FOUND;
+}
+
+
+// Retrieve basic statistics about dirty records on a page.
+static void dirty_records_stat(uint16_t         page,
+                               uint16_t * const p_dirty_records,
+                               uint16_t * const p_word_count)
+{
+    fds_header_t const * p_header;
+    uint32_t     const * p_rec;
+
+    p_rec = m_pages[page].p_addr + FDS_PAGE_TAG_SIZE;
+
+    while ((p_rec < (m_pages[page].p_addr + FDS_PAGE_SIZE)) &&
+           (*p_rec != FDS_ERASED_WORD))
+    {
+        p_header = (fds_header_t*)p_rec;
+
+        if (!header_is_valid(p_header))
+        {
+            (*p_dirty_records) += 1;
+            (*p_word_count)    += p_header->tl.length_words;
+        }
+        else
+        {
+            p_rec += (FDS_HEADER_SIZE + (p_header->tl.length_words));
+        }
+    }
+}
+
+
+// Advances one position in the queue.
+// Returns true if the queue is not empty.
+static bool queue_advance(void)
+{
+    // Reset the current element.
+    memset(&m_op_queue.op[m_op_queue.rp], 0x00, sizeof(fds_op_t));
+
+    if (m_op_queue.count != 0)
+    {
+        // Advance in the queue, wrapping around if necessary.
+        m_op_queue.rp = (m_op_queue.rp + 1) % FDS_OP_QUEUE_SIZE;
+        m_op_queue.count--;
+    }
+
+    return (m_op_queue.count != 0);
+}
+
+
+// Given a pointer to an element in the chunk queue, computes the pointer to
+// the next element in the queue. Handles wrap around.
+void chunk_queue_next(fds_record_chunk_t ** pp_chunk)
+{
+    if ((*pp_chunk) != &m_chunk_queue.chunk[FDS_CHUNK_QUEUE_SIZE - 1])
+    {
+        (*pp_chunk)++;
+        return;
+    }
+
+    *pp_chunk = &m_chunk_queue.chunk[0];
+}
+
+
+// Retrieve the current chunk, and advance the queue.
+static void chunk_queue_get_and_advance(fds_record_chunk_t ** pp_chunk)
+{
+    if (m_chunk_queue.count != 0)
+    {
+        // Point to the current chunk and advance the queue.
+        *pp_chunk = &m_chunk_queue.chunk[m_chunk_queue.rp];
+
+        m_chunk_queue.rp = (m_chunk_queue.rp + 1) % FDS_CHUNK_QUEUE_SIZE;
+        m_chunk_queue.count--;
+    }
+}
+
+
+static void chunk_queue_skip(fds_op_t const * const p_op)
+{
+    if ((p_op->op_code == FDS_OP_WRITE) ||
+        (p_op->op_code == FDS_OP_UPDATE))
+    {
+        m_chunk_queue.rp    += p_op->write.chunk_count;
+        m_chunk_queue.count -= p_op->write.chunk_count;
+    }
+}
+
+
+// Enqueue an operation.
+static bool op_enqueue(fds_op_t           const * const p_op,
+                       uint32_t                         num_chunks,
+                       fds_record_chunk_t const * const p_chunk)
+{
+    uint32_t idx;
+    bool     ret = false;
+
+    CRITICAL_SECTION_ENTER();
+    if  ((m_op_queue.count    <= FDS_OP_QUEUE_SIZE - 1) &&
+         (m_chunk_queue.count <= FDS_CHUNK_QUEUE_SIZE - num_chunks))
+    {
+        idx = (m_op_queue.count + m_op_queue.rp) % FDS_OP_QUEUE_SIZE;
+
+        m_op_queue.op[idx] = *p_op;
+        m_op_queue.count++;
+
+        if (num_chunks != 0)
+        {
+            idx = (m_chunk_queue.count + m_chunk_queue.rp) % FDS_CHUNK_QUEUE_SIZE;
+
+            fds_record_chunk_t * p_chunk_dst;
+            p_chunk_dst = &m_chunk_queue.chunk[idx];
+
+            for (uint32_t i = 0; i < num_chunks; i++)
+            {
+                *p_chunk_dst = p_chunk[i];
+                chunk_queue_next(&p_chunk_dst);
+            }
+
+            m_chunk_queue.count += num_chunks;
+        }
+
+        ret = true;
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+// This function is called during initialization to setup the page structure (m_pages) and
+// provide additional information regarding eventual further initialization steps.
+static fds_init_opts_t pages_init()
+{
+    uint32_t ret = NO_PAGES;
+    // The index of the page being initialized in m_pages[].
+    uint16_t page = 0;
+
+    for (uint16_t i = 0; i < FDS_VIRTUAL_PAGES; i++)
+    {
+        uint32_t        const * const p_page_addr = fs_config.p_start_addr + (i * FDS_PAGE_SIZE);
+        fds_page_type_t const         page_type   = page_identify(p_page_addr);
+
+        switch (page_type)
+        {
+            case FDS_PAGE_UNDEFINED:
+                if (page_is_erased(p_page_addr))
+                {
+                    if (m_swap_page.p_addr != NULL)
+                    {
+                        // If a swap page is already set, flag the page as erased (in m_pages)
+                        // and try to tag it as data (in flash) later on during initialization.
+                        m_pages[page].page_type    = FDS_PAGE_ERASED;
+                        m_pages[page].p_addr       = p_page_addr;
+                        m_pages[page].write_offset = FDS_PAGE_TAG_SIZE;
+
+                        // This is a candidate for a potential new swap page, in case the
+                        // current swap is going to be promoted to complete a GC instance.
+                        m_gc.cur_page = page;
+                        page++;
+                    }
+                    else
+                    {
+                        // If there is no swap page yet, use this one.
+                        m_swap_page.p_addr       = p_page_addr;
+                        m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+                    }
+
+                    ret |= PAGE_ERASED;
+                }
+                break;
+
+            case FDS_PAGE_DATA:
+                m_pages[page].page_type = FDS_PAGE_DATA;
+                m_pages[page].p_addr    = p_page_addr;
+                // Scan the page to compute its write offset and determine whether or not the page
+                // can be garbage collected. Additionally, update the latest kwown record ID.
+                page_scan(p_page_addr, &m_pages[page].write_offset, &m_pages[page].can_gc);
+
+                ret |= PAGE_DATA;
+                page++;
+
+                break;
+
+            case FDS_PAGE_SWAP:
+                m_swap_page.p_addr = p_page_addr;
+                // If the swap is promoted, this offset should be kept, otherwise,
+                // it should be set to FDS_PAGE_TAG_SIZE.
+                page_scan(p_page_addr, &m_swap_page.write_offset, NULL);
+
+                ret |= (m_swap_page.write_offset == FDS_PAGE_TAG_SIZE) ?
+                        SWAP_EMPTY : SWAP_DIRTY;
+                break;
+
+            default:
+                // Shouldn't happen.
+                break;
+        }
+    }
+
+    return (fds_init_opts_t)ret;
+}
+
+
+// Write the first part of a record header (the key and length).
+static ret_code_t record_header_write_begin(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t ret;
+    ret = fs_store(&fs_config, p_addr + FDS_OFFSET_TL,
+                  (uint32_t*)&p_op->write.header.tl, FDS_HEADER_SIZE_TL);
+
+    // Write the record ID next.
+    p_op->write.step = FDS_OP_WRITE_RECORD_ID;
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_header_write_id(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t ret;
+    ret = fs_store(&fs_config, p_addr + FDS_OFFSET_ID,
+                   (uint32_t*)&p_op->write.header.record_id, FDS_HEADER_SIZE_ID);
+
+    // If this record has zero chunk, write the last part of the header directly.
+    // Otherwise, write the record chunks next.
+    p_op->write.step = (p_op->write.chunk_count != 0) ? FDS_OP_WRITE_CHUNKS :
+                                                        FDS_OP_WRITE_HEADER_FINALIZE;
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_header_write_finalize(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t ret;
+    ret = fs_store(&fs_config, p_addr + FDS_OFFSET_IC,
+                   (uint32_t*)&p_op->write.header.ic, FDS_HEADER_SIZE_IC);
+
+    // If this is a simple write operation, then this is the last step.
+    // If this is an update instead, delete the old record next.
+    p_op->write.step = (p_op->op_code == FDS_OP_UPDATE) ? FDS_OP_WRITE_FLAG_DIRTY :
+                                                          FDS_OP_WRITE_DONE;
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_header_flag_dirty(uint32_t * const p_record)
+{
+    // Flag the record as dirty.
+    fs_ret_t ret = fs_store(&fs_config, p_record,
+                            (uint32_t*)&m_fds_tl_dirty, FDS_HEADER_SIZE_TL);
+
+    return (ret == FS_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+static ret_code_t record_find_and_delete(fds_op_t * const p_op)
+{
+    ret_code_t        ret; 
+    uint16_t          page;
+    fds_record_desc_t desc = {0};
+
+    desc.record_id = p_op->del.record_to_delete;
+
+    if (record_find_by_desc(&desc, &page))
+    {
+        fds_header_t const * const p_header = (fds_header_t const *)desc.p_record;
+
+        // Copy the record key and file ID, so that they can be returned in the event.
+        // In case this function is run as part of an update, there is no need to copy
+        // the file ID and record key since they are present in the header stored
+        // in the queue element.
+
+        p_op->del.file_id    = p_header->ic.file_id;
+        p_op->del.record_key = p_header->tl.record_key;
+
+        // Flag the record as dirty.
+        ret = record_header_flag_dirty((uint32_t*)desc.p_record);
+
+        // This page can now be garbage collected.
+        m_pages[page].can_gc = true;
+    }
+    else
+    {
+        // The record never existed, or it has already been deleted.
+        ret = FDS_ERR_NOT_FOUND;
+    }
+
+    return ret;
+}
+
+
+// Finds a record within a file and flags it as dirty.
+static ret_code_t file_find_and_delete(fds_op_t * const p_op)
+{
+    ret_code_t        ret;
+    fds_record_desc_t desc;
+
+    // This token must persist across calls.
+    static fds_find_token_t tok = {0};
+
+    // Pass NULL to ignore the record key.
+    ret = record_find(&p_op->del.file_id, NULL, &desc, &tok);
+
+    if (ret == FDS_SUCCESS)
+    {
+         // A record was found: flag it as dirty.
+        ret = record_header_flag_dirty((uint32_t*)desc.p_record);
+
+        // This page can now be garbage collected.
+        m_pages[tok.page].can_gc = true;
+    }
+    else // FDS_ERR_NOT_FOUND
+    {
+        // No more records were found. Zero the token, so that it can be reused.
+        memset(&tok, 0x00, sizeof(fds_find_token_t));
+    }
+
+    return ret;
+}
+
+
+// Writes a record chunk to flash and advances the chunk queue. Additionally, decrements
+// the number of chunks left to write for this operation and accumulates the offset.
+static ret_code_t record_write_chunk(fds_op_t * const p_op, uint32_t * const p_addr)
+{
+    ret_code_t           ret;
+    fds_record_chunk_t * p_chunk = NULL;
+
+    // Retrieve the next chunk to be written.
+    chunk_queue_get_and_advance(&p_chunk);
+
+    ret = fs_store(&fs_config, p_addr + p_op->write.chunk_offset,
+                   p_chunk->p_data, p_chunk->length_words);
+
+    // Accumulate the offset.
+    p_op->write.chunk_offset += p_chunk->length_words;
+
+    // Decrement the number of chunks left to write.
+    // NOTE: If chunk_count is initially zero, this function is not called
+    // because this step is skipped entirely. See record_header_write_id().
+    p_op->write.chunk_count--;
+
+    if (p_op->write.chunk_count == 0)
+    {
+        // All record chunks have been written; write the last part of
+        // the record header to finalize the write operation.
+        p_op->write.step = FDS_OP_WRITE_HEADER_FINALIZE;
+    }
+
+    return (ret == NRF_SUCCESS) ? FDS_SUCCESS : FDS_ERR_BUSY;
+}
+
+
+#if defined(FDS_CRC_ENABLED)
+
+static bool crc_verify_success(uint16_t crc, uint16_t len_words, uint32_t const * const p_data)
+{
+    uint16_t computed_crc;
+
+    // The CRC is computed on the entire record, except the CRC field itself.
+    // The record header is 12 bytes, out of these we have to skip bytes 6 to 8 where the
+    // CRC itself is stored. Then we compute the CRC for the rest of the record, from byte 8 of
+    // the header (where the record ID begins) to the end of the record data.
+    computed_crc = crc16_compute((uint8_t const *)p_data,  6, NULL);
+    computed_crc = crc16_compute((uint8_t const *)p_data + 8,
+                                 (FDS_HEADER_SIZE_ID + len_words) * sizeof(uint32_t),
+                                 &computed_crc);
+
+    return (computed_crc == crc);
+}
+
+#endif
+
+
+static void gc_init(void)
+{
+    m_gc.run_count++;
+    m_gc.cur_page = 0;
+    m_gc.resume   = false;
+
+    // Setup which pages to GC. Defer checking for open records and the can_gc flag,
+    // as other operations might change those while GC is running.
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        m_gc.do_gc_page[i] = (m_pages[i].page_type == FDS_PAGE_DATA);
+    }
+}
+
+
+// Obtain the next page to be garbage collected.
+// Returns true if there are pages left to garbage collect, returns false otherwise.
+static bool gc_page_next(uint16_t * const p_next_page)
+{
+    bool ret = false;
+
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        if (m_gc.do_gc_page[i])
+        {
+            // Do not attempt to GC this page again.
+            m_gc.do_gc_page[i] = false;
+
+            // Only GC pages with no open records and with some records which have been deleted.
+            if ((m_pages[i].records_open == 0) && (m_pages[i].can_gc == true))
+            {
+                *p_next_page = i;
+                ret = true;
+                break;
+            }
+        }
+    }
+
+    return ret;
+}
+
+
+static ret_code_t gc_swap_erase(void)
+{
+    m_gc.state               = GC_DISCARD_SWAP;
+    m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+
+    return fs_erase(&fs_config, m_swap_page.p_addr, FDS_PHY_PAGES_IN_VPAGE);
+}
+
+
+// Erase the page being garbage collected, or erase the swap in case there are any open
+// records on the page being garbage collected.
+static ret_code_t gc_page_erase(void)
+{
+    uint32_t       ret;
+    uint16_t const gc = m_gc.cur_page;
+
+    if (m_pages[gc].records_open == 0)
+    {
+        ret = fs_erase(&fs_config, m_pages[gc].p_addr, FDS_PHY_PAGES_IN_VPAGE);
+        m_gc.state = GC_ERASE_PAGE;
+    }
+    else
+    {
+        // If there are open records, stop garbage collection on this page.
+        // Discard the swap and try to garbage collect another page.
+        ret = gc_swap_erase();
+    }
+
+    return ret;
+}
+
+
+// Copy the current record to swap.
+static ret_code_t gc_record_copy(void)
+{
+    fds_header_t const * const p_header   = (fds_header_t*)m_gc.p_record_src;
+    uint32_t     const * const p_dest     = m_swap_page.p_addr + m_swap_page.write_offset;
+    uint16_t     const         record_len = FDS_HEADER_SIZE + p_header->tl.length_words;
+
+    m_gc.state = GC_COPY_RECORD;
+
+    // Copy the record to swap; it is guaranteed to fit in the destination page,
+    // so there is no need to check its size. This will either succeed or timeout.
+    return fs_store(&fs_config, p_dest, m_gc.p_record_src, record_len);
+}
+
+
+static ret_code_t gc_record_find_next(void)
+{
+    ret_code_t ret;
+
+    // Find the next valid record to copy.
+    if (record_find_next(m_gc.cur_page, &m_gc.p_record_src))
+    {
+        ret = gc_record_copy();
+    }
+    else
+    {
+        // No more records left to copy on this page; swap pages.
+        ret = gc_page_erase();
+    }
+
+    return ret;
+}
+
+
+// Promote the swap by tagging it as a data page.
+static ret_code_t gc_swap_promote(void)
+{
+    m_gc.state = GC_PROMOTE_SWAP;
+    return page_tag_write_data(m_pages[m_gc.cur_page].p_addr);
+}
+
+
+// Tag the page just garbage collected as swap.
+static ret_code_t gc_tag_new_swap(void)
+{
+    m_gc.state        = GC_TAG_NEW_SWAP;
+    m_gc.p_record_src = NULL;
+    return page_tag_write_swap();
+}
+
+
+static ret_code_t gc_next_page(void)
+{
+    if (!gc_page_next(&m_gc.cur_page))
+    {
+        // No pages left to GC; GC has terminated. Reset the state.
+        m_gc.state        = GC_BEGIN;
+        m_gc.cur_page     = 0;
+        m_gc.p_record_src = NULL;
+
+        return FDS_OP_COMPLETED;
+    }
+
+    return gc_record_find_next();
+}
+
+
+// Update the swap page offeset after a record has been successfully copied to it.
+static void gc_update_swap_offset(void)
+{
+    fds_header_t const * const p_header   = (fds_header_t*)m_gc.p_record_src;
+    uint16_t     const         record_len = FDS_HEADER_SIZE + p_header->tl.length_words;
+
+    m_swap_page.write_offset += record_len;
+}
+
+
+static void gc_swap_pages(void)
+{
+    // The page being garbage collected will be the new swap page,
+    // and the current swap will be used as a data page (promoted).
+    uint32_t const * const p_addr = m_swap_page.p_addr;
+
+    m_swap_page.p_addr            = m_pages[m_gc.cur_page].p_addr;
+    m_pages[m_gc.cur_page].p_addr = p_addr;
+
+    // Keep the offset for this page, but reset it for the swap.
+    m_pages[m_gc.cur_page].write_offset = m_swap_page.write_offset;
+    m_swap_page.write_offset            = FDS_PAGE_TAG_SIZE;
+}
+
+
+static void gc_state_advance(void)
+{
+    switch (m_gc.state)
+    {
+        case GC_BEGIN:
+            gc_init();
+            m_gc.state = GC_NEXT_PAGE;
+            break;
+
+        // A record was successfully copied.
+        case GC_COPY_RECORD:
+            gc_update_swap_offset();
+            m_gc.state = GC_FIND_NEXT_RECORD;
+            break;
+
+        // A page was successfully erased. Prepare to promote the swap.
+        case GC_ERASE_PAGE:
+            gc_swap_pages();
+            m_gc.state = GC_PROMOTE_SWAP;
+            break;
+
+        // Swap was discarded because the page being GC'ed had open records.
+        case GC_DISCARD_SWAP:
+        // Swap was sucessfully promoted.
+        case GC_PROMOTE_SWAP:
+            // Prepare to tag the page just GC'ed as swap.
+            m_gc.state = GC_TAG_NEW_SWAP;
+            break;
+
+        case GC_TAG_NEW_SWAP:
+            m_gc.state = GC_NEXT_PAGE;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+}
+
+
+// Initialize the filesystem.
+static ret_code_t init_execute(uint32_t prev_ret, fds_op_t * const p_op)
+{
+    ret_code_t ret = FDS_ERR_INTERNAL;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        // A previous operation has timed out.
+        flag_clear(FDS_FLAG_INITIALIZING);
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    switch (p_op->init.step)
+    {
+        case FDS_OP_INIT_TAG_SWAP:
+            // The page write offset was determined previously by pages_init().
+            ret             = page_tag_write_swap();
+            p_op->init.step = FDS_OP_INIT_TAG_DATA;
+            break;
+
+        case FDS_OP_INIT_TAG_DATA:
+        {
+            // Tag remaining erased pages as data.
+            bool write_reqd = false;
+            for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+            {
+                if (m_pages[i].page_type == FDS_PAGE_ERASED)
+                {
+                    ret = page_tag_write_data(m_pages[i].p_addr);
+                    m_pages[i].page_type = FDS_PAGE_DATA;
+                    write_reqd           = true;
+                    break;
+                }
+            }
+            if (!write_reqd)
+            {
+                flag_set(FDS_FLAG_INITIALIZED);
+                flag_clear(FDS_FLAG_INITIALIZING);
+                return FDS_OP_COMPLETED;
+            }
+        }
+        break;
+
+        case FDS_OP_INIT_ERASE_SWAP:
+            ret = fs_erase(&fs_config, m_swap_page.p_addr, FDS_PHY_PAGES_IN_VPAGE);
+            // If the swap is going to be discarded then reset its write_offset.
+            m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+            p_op->init.step          = FDS_OP_INIT_TAG_SWAP;
+            break;
+
+        case FDS_OP_INIT_PROMOTE_SWAP:
+        {
+            // When promoting the swap, keep the write_offset set by pages_init().
+            ret = page_tag_write_data(m_swap_page.p_addr);
+        
+            uint16_t const         gc         = m_gc.cur_page;
+            uint32_t const * const p_old_swap = m_swap_page.p_addr;
+
+            // Execute the swap.
+            m_swap_page.p_addr = m_pages[gc].p_addr;
+            m_pages[gc].p_addr = p_old_swap;
+
+            // Copy the offset from the swap to the new page.
+            m_pages[gc].write_offset = m_swap_page.write_offset;
+            m_swap_page.write_offset = FDS_PAGE_TAG_SIZE;
+
+            m_pages[gc].page_type = FDS_PAGE_DATA;
+            p_op->init.step       = FDS_OP_INIT_TAG_SWAP;
+        }
+        break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+
+    if (ret != FDS_SUCCESS)
+    {
+        // fstorage queue was full.
+        flag_clear(FDS_FLAG_INITIALIZING);
+        return FDS_ERR_BUSY;
+    }
+
+    return FDS_OP_EXECUTING;
+}
+
+
+// Executes write and update operations.
+static ret_code_t write_execute(uint32_t prev_ret, fds_op_t * const p_op)
+{
+    ret_code_t         ret;
+    uint32_t   *       p_write_addr;
+    fds_page_t * const p_page = &m_pages[p_op->write.page];
+
+    // This must persist across calls.
+    static fds_record_desc_t desc = {0};
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        // The previous operation has timed out, update offsets.
+        page_offsets_update(p_page, p_op->write.header.tl.length_words);
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    // Compute the address where to write data.
+    p_write_addr = (uint32_t*)(p_page->p_addr + p_page->write_offset);
+
+    // Execute the current step of the operation, and set one to be executed next.
+    switch (p_op->write.step)
+    {
+        case FDS_OP_WRITE_FIND_RECORD:
+        {
+            // The first step of updating a record constists of locating the copy to be deleted.
+            // If the old copy couldn't be found for any reason then the update should fail.
+            // This prevents duplicates when queuing multiple updates of the same record.
+
+            uint16_t page;
+            desc.p_record  = NULL;
+            desc.record_id = p_op->write.record_to_delete;
+
+            if (!record_find_by_desc(&desc, &page))
+            {
+                return FDS_ERR_NOT_FOUND;
+            }
+            // Setting the step is redundant since we are falling through.
+        }
+        // Fallthrough to FDS_OP_WRITE_HEADER_BEGIN.
+
+        case FDS_OP_WRITE_HEADER_BEGIN:
+            ret = record_header_write_begin(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_RECORD_ID:
+            ret = record_header_write_id(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_CHUNKS:
+            ret = record_write_chunk(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_HEADER_FINALIZE:
+            ret = record_header_write_finalize(p_op, p_write_addr);
+            break;
+
+        case FDS_OP_WRITE_FLAG_DIRTY:
+            ret = record_header_flag_dirty((uint32_t*)desc.p_record);
+            p_op->write.step = FDS_OP_WRITE_DONE;
+            break;
+
+        case FDS_OP_WRITE_DONE:
+            ret = FDS_OP_COMPLETED;
+
+#if defined(FDS_CRC_ENABLED)
+            if (flag_is_set(FDS_FLAG_VERIFY_CRC))
+            {
+                if (!crc_verify_success(p_op->write.header.ic.crc16,
+                                        p_op->write.header.tl.length_words,
+                                        p_write_addr))
+                {
+                    ret = FDS_ERR_CRC_CHECK_FAILED;
+                }
+            }
+#endif
+            break;
+
+        default:
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    // An operation has either completed or failed. It may have failed because fstorage
+    // ran out of memory, or because the user tried to delete a record which did not exist.
+    if (ret != FDS_OP_EXECUTING)
+    {
+        // There won't be another callback for this operation, so update the page offset now.
+        page_offsets_update(p_page, p_op->write.header.tl.length_words);
+    }
+
+    return ret;
+}
+
+
+static ret_code_t delete_execute(uint32_t prev_ret, fds_op_t * const p_op)
+{
+    ret_code_t ret;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    switch (p_op->del.step)
+    {
+        case FDS_OP_DEL_RECORD_FLAG_DIRTY:
+            ret = record_find_and_delete(p_op);
+            p_op->del.step = FDS_OP_DEL_DONE;
+            break;
+
+        case FDS_OP_DEL_FILE_FLAG_DIRTY:
+            ret = file_find_and_delete(p_op);
+            if (ret == FDS_ERR_NOT_FOUND)
+            {
+                // No more records could be found.
+                // There won't be another callback for this operation, so return now.
+                ret = FDS_OP_COMPLETED;
+            }
+            break;
+
+        case FDS_OP_DEL_DONE:
+            ret = FDS_OP_COMPLETED;
+            break;
+
+        default:
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    return ret;
+}
+
+
+static ret_code_t gc_execute(uint32_t prev_ret)
+{
+    ret_code_t ret;
+
+    if (prev_ret != FS_SUCCESS)
+    {
+        return FDS_ERR_OPERATION_TIMEOUT;
+    }
+
+    if (m_gc.resume)
+    {
+        m_gc.resume = false;
+    }
+    else
+    {
+        gc_state_advance();
+    }
+
+    switch (m_gc.state)
+    {
+        case GC_NEXT_PAGE:
+            ret = gc_next_page();
+            break;
+
+        case GC_FIND_NEXT_RECORD:
+            ret = gc_record_find_next();
+            break;
+
+        case GC_COPY_RECORD:
+            ret = gc_record_copy();
+            break;
+
+        case GC_ERASE_PAGE:
+            ret = gc_page_erase();
+            break;
+
+        case GC_PROMOTE_SWAP:
+            ret = gc_swap_promote();
+            break;
+
+        case GC_TAG_NEW_SWAP:
+            ret = gc_tag_new_swap();
+            break;
+
+        default:
+            // Should not happen.
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    // Either FDS_OP_EXECUTING, FDS_OP_COMPLETED, FDS_ERR_BUSY or FDS_ERR_INTERNAL.
+    return ret;
+}
+
+
+static void queue_process(fs_ret_t result)
+{
+    ret_code_t         ret;
+    fds_op_t   * const p_op = &m_op_queue.op[m_op_queue.rp];
+
+    switch (p_op->op_code)
+    {
+        case FDS_OP_INIT:
+            ret = init_execute(result, p_op);
+            break;
+
+        case FDS_OP_WRITE:
+        case FDS_OP_UPDATE:
+            ret = write_execute(result, p_op);
+            break;
+
+        case FDS_OP_DEL_RECORD:
+        case FDS_OP_DEL_FILE:
+            ret = delete_execute(result, p_op);
+            break;
+
+        case FDS_OP_GC:
+            ret = gc_execute(result);
+            break;
+
+        default:
+            ret = FDS_ERR_INTERNAL;
+            break;
+    }
+
+    if (ret != FDS_OP_EXECUTING)
+    {
+        fds_evt_t evt;
+
+        if (ret == FDS_OP_COMPLETED)
+        {
+            evt.result = FDS_SUCCESS;
+        }
+        else
+        {
+            // Either FDS_ERR_BUSY, FDS_ERR_OPERATION_TIMEOUT,
+            // FDS_ERR_CRC_CHECK_FAILED or FDS_ERR_NOT_FOUND.
+            evt.result = ret;
+
+            // If this operation had any chunks in the queue, skip them.
+            chunk_queue_skip(p_op);
+        }
+
+        event_prepare(p_op, &evt);
+        event_send(&evt);
+
+        // Advance the queue, and if there are any queued operations, process them.
+        if (queue_advance())
+        {
+            queue_process(FS_SUCCESS);
+        }
+        else
+        {
+            // No more elements in the queue. Clear the FDS_FLAG_PROCESSING flag,
+            // so that new operation can start processing the queue.
+            flag_clear(FDS_FLAG_PROCESSING);
+        }
+    }
+}
+
+
+static void queue_start(void)
+{
+    if (!flag_is_set(FDS_FLAG_PROCESSING))
+    {
+        flag_set(FDS_FLAG_PROCESSING);
+        queue_process(FS_SUCCESS);
+    }
+}
+
+
+static void fs_event_handler(fs_evt_t const * const p_evt, fs_ret_t result)
+{
+    queue_process(result);
+}
+
+
+// Enqueues write and update operations.
+static ret_code_t write_enqueue(fds_record_desc_t         * const p_desc,
+                                fds_record_t        const * const p_record,
+                                fds_reserve_token_t const * const p_tok,
+                                fds_op_code_t                     op_code)
+{
+    ret_code_t ret;
+    fds_op_t   op;
+    uint16_t   page;
+    uint16_t   crc          = 0;
+    uint16_t   length_words = 0;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_record == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    if ((p_record->file_id == FDS_FILE_ID_INVALID) ||
+        (p_record->key     == FDS_RECORD_KEY_DIRTY))
+    {
+        return FDS_ERR_INVALID_ARG;
+    }
+
+    if (!chunk_is_aligned(p_record->data.p_chunks,
+                          p_record->data.num_chunks))
+    {
+        return FDS_ERR_UNALIGNED_ADDR;
+    }
+
+    // No space was previously reserved for this operation.
+    if (p_tok == NULL)
+    {
+        // Compute the total length of the record.
+        for (uint32_t i = 0; i < p_record->data.num_chunks; i++)
+        {
+            length_words += p_record->data.p_chunks[i].length_words;
+        }
+
+        // Find a page where to write data.
+        ret = write_space_reserve(length_words, &page);
+
+        if (ret != FDS_SUCCESS)
+        {
+            // There is either not enough flash space available (FDS_ERR_NO_SPACE_IN_FLASH) or
+            // the record exceeds the virtual page size (FDS_ERR_RECORD_TOO_LARGE).
+            return ret;
+        }
+    }
+    else
+    {
+        page         = p_tok->page;
+        length_words = p_tok->length_words;
+    }
+
+    // Initialize the operation.
+    op.op_code                      = op_code;
+    op.write.step                   = FDS_OP_WRITE_HEADER_BEGIN;
+    op.write.page                   = page;
+    op.write.chunk_count            = p_record->data.num_chunks;
+    op.write.chunk_offset           = FDS_OFFSET_DATA;
+    op.write.header.record_id       = record_id_new();
+    op.write.header.ic.file_id      = p_record->file_id;
+    op.write.header.tl.record_key   = p_record->key;
+    op.write.header.tl.length_words = length_words;
+
+    if (op_code == FDS_OP_UPDATE)
+    {
+        op.write.step             = FDS_OP_WRITE_FIND_RECORD;
+        // Save the record ID of the record to be updated.
+        op.write.record_to_delete = p_desc->record_id;
+    }
+
+#if defined (FDS_CRC_ENABLED)
+    // First, compute the CRC for the first 6 bytes of the header which contain the
+    // record key, length and file ID, then, compute the CRC of the record ID (4 bytes).
+    crc = crc16_compute((uint8_t*)&op.write.header,           6, NULL);
+    crc = crc16_compute((uint8_t*)&op.write.header.record_id, 4, &crc);
+
+    for (uint32_t i = 0; i < p_record->data.num_chunks; i++)
+    {
+        // Compute the CRC for the record data.
+        crc = crc16_compute((uint8_t*)p_record->data.p_chunks[i].p_data,
+                            p_record->data.p_chunks[i].length_words * sizeof(uint32_t), &crc);
+    }
+#endif
+
+    op.write.header.ic.crc16 = crc;
+
+    // Attempt to enqueue the operation.
+    if (!op_enqueue(&op, p_record->data.num_chunks, p_record->data.p_chunks))
+    {
+        // No space availble in the queues. Cancel the reservation of flash space.
+        CRITICAL_SECTION_ENTER();
+        write_space_free(length_words, page);
+        CRITICAL_SECTION_EXIT();
+
+        return FDS_ERR_NO_SPACE_IN_QUEUES;
+    }
+
+     // Initialize the record descriptor, if provided.
+    if (p_desc != NULL)
+    {
+        p_desc->p_record       = NULL;
+        // Don't invoke record_id_new() again !
+        p_desc->record_id      = op.write.header.record_id;
+        p_desc->record_is_open = false;
+        p_desc->gc_run_count   = m_gc.run_count;
+    }
+
+    // Start processing the queue, if necessary.
+    queue_start();
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_register(fds_cb_t cb)
+{
+    ret_code_t ret;
+
+    CRITICAL_SECTION_ENTER();
+    if (m_users == FDS_MAX_USERS)
+    {
+        ret = FDS_ERR_USER_LIMIT_REACHED;
+    }
+    else
+    {
+        m_cb_table[m_users] = cb;
+        m_users++;
+
+        ret = FDS_SUCCESS;
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+ret_code_t fds_init(void)
+{
+    fds_evt_t const evt_success = { .id = FDS_EVT_INIT, .result = FDS_SUCCESS };
+
+    // No initialization is necessary. Notify the application immediately.
+    if (flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        event_send(&evt_success);
+        return FDS_SUCCESS;
+    }
+
+    if (flag_is_set(FDS_FLAG_INITIALIZING))
+    {
+        return FDS_SUCCESS;
+    }
+
+    flag_set(FDS_FLAG_INITIALIZING);
+
+    (void)fs_init();
+
+    // Initialize the page structure (m_pages), and determine which
+    // initialization steps are required given the current state of the filesystem.
+    fds_init_opts_t init_opts = pages_init();
+
+    if (init_opts == NO_PAGES)
+    {
+        return FDS_ERR_NO_PAGES;
+    }
+
+    if (init_opts == ALREADY_INSTALLED)
+    {
+        // No initialization is necessary. Notify the application immediately.
+        flag_set(FDS_FLAG_INITIALIZED);
+        flag_clear(FDS_FLAG_INITIALIZING);
+
+        event_send(&evt_success);
+        return FDS_SUCCESS;
+    }
+
+    fds_op_t op;
+    op.op_code = FDS_OP_INIT;
+
+    switch (init_opts)
+    {
+        case FRESH_INSTALL:
+        case TAG_SWAP:
+            op.init.step = FDS_OP_INIT_TAG_SWAP;
+            break;
+
+        case PROMOTE_SWAP:
+        case PROMOTE_SWAP_INST:
+            op.init.step = FDS_OP_INIT_PROMOTE_SWAP;
+            break;
+
+        case DISCARD_SWAP:
+            op.init.step = FDS_OP_INIT_ERASE_SWAP;
+            break;
+
+        case TAG_DATA:
+        case TAG_DATA_INST:
+            op.init.step = FDS_OP_INIT_TAG_DATA;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+
+    // This cannot fail since it will be the first operation in the queue.
+    (void)op_enqueue(&op, 0, NULL);
+
+    queue_start();
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_record_open(fds_record_desc_t  * const p_desc,
+                           fds_flash_record_t * const p_flash_rec)
+{
+    uint16_t page;
+
+    if ((p_desc == NULL) || (p_flash_rec == NULL))
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    // Find the record if necessary.
+    if (record_find_by_desc(p_desc, &page))
+    {
+        fds_header_t const * const p_header = (fds_header_t*)p_desc->p_record;
+
+#if defined(FDS_CRC_ENABLED)
+        if (!crc_verify_success(p_header->ic.crc16,
+                                p_header->tl.length_words,
+                                p_desc->p_record))
+        {
+            return FDS_ERR_CRC_CHECK_FAILED;
+        }
+#endif
+
+        CRITICAL_SECTION_ENTER();
+        m_pages[page].records_open++;
+        CRITICAL_SECTION_EXIT();
+
+        // Initialize p_flash_rec.
+        p_flash_rec->p_header = p_header;
+        p_flash_rec->p_data   = (p_desc->p_record + FDS_HEADER_SIZE);
+
+        // Set the record as open in the descriptor.
+        p_desc->record_is_open = true;
+
+        return FDS_SUCCESS;
+    }
+
+    // The record could not be found.
+    // It either never existed or it has been deleted.
+    return FDS_ERR_NOT_FOUND;
+}
+
+
+ret_code_t fds_record_close(fds_record_desc_t * const p_desc)
+{
+    ret_code_t ret;
+    uint16_t   page;
+
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    if (record_find_by_desc((fds_record_desc_t*)p_desc, &page))
+    {
+        CRITICAL_SECTION_ENTER();
+        if ((m_pages[page].records_open > 0) && (p_desc->record_is_open))
+        {
+
+            m_pages[page].records_open--;
+            p_desc->record_is_open = false;
+
+            ret = FDS_SUCCESS;
+        }
+        else
+        {
+            ret = FDS_ERR_NO_OPEN_RECORDS;
+        }
+        CRITICAL_SECTION_EXIT();
+    }
+    else
+    {
+        ret = FDS_ERR_NOT_FOUND;
+    }
+
+    return ret;
+}
+
+
+ret_code_t fds_reserve(fds_reserve_token_t * const p_tok, uint16_t length_words)
+{
+    ret_code_t ret;
+    uint16_t   page;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_tok == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    ret = write_space_reserve(length_words, &page);
+
+    if (ret == FDS_SUCCESS)
+    {
+        p_tok->page         = page;
+        p_tok->length_words = length_words;
+    }
+
+    return ret;
+}
+
+
+ret_code_t fds_reserve_cancel(fds_reserve_token_t * const p_tok)
+{
+    ret_code_t ret;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_tok == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    if (p_tok->page > FDS_MAX_PAGES)
+    {
+        // The page does not exist. This shouldn't happen.
+        return FDS_ERR_INVALID_ARG;
+    }
+
+    fds_page_t const * const p_page = &m_pages[p_tok->page];
+
+    CRITICAL_SECTION_ENTER();
+    if (p_page->words_reserved - (FDS_HEADER_SIZE + p_tok->length_words) >= 0)
+    {
+        // Free reserved space.
+        write_space_free(p_tok->length_words, p_tok->page);
+
+        // Clean the token.
+        p_tok->page         = 0;
+        p_tok->length_words = 0;
+        ret = FDS_SUCCESS;
+    }
+    else
+    {
+        // We are trying to cancel a reservation of more words than how many are
+        // currently reserved on the page. Clearly, this shouldn't happen.
+        ret = FDS_ERR_INVALID_ARG;
+    }
+    CRITICAL_SECTION_EXIT();
+
+    return ret;
+}
+
+
+ret_code_t fds_record_write(fds_record_desc_t       * const p_desc,
+                            fds_record_t      const * const p_record)
+{
+    return write_enqueue(p_desc, p_record, NULL, FDS_OP_WRITE);
+}
+
+
+ret_code_t fds_record_write_reserved(fds_record_desc_t         * const p_desc,
+                                     fds_record_t        const * const p_record,
+                                     fds_reserve_token_t const * const p_tok)
+{
+    // A NULL token is not allowed when writing to a reserved space.
+    if (p_tok == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    return write_enqueue(p_desc, p_record, p_tok, FDS_OP_WRITE);
+}
+
+
+ret_code_t fds_record_update(fds_record_desc_t       * const p_desc,
+                             fds_record_t      const * const p_record)
+{
+    // A NULL descriptor is not allowed when updating a record.
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    return write_enqueue(p_desc, p_record, NULL, FDS_OP_UPDATE);
+}
+
+
+ret_code_t fds_record_delete(fds_record_desc_t * const p_desc)
+{
+    fds_op_t op;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    op.op_code              = FDS_OP_DEL_RECORD;
+    op.del.step             = FDS_OP_DEL_RECORD_FLAG_DIRTY;
+    op.del.record_to_delete = p_desc->record_id;
+
+    if (op_enqueue(&op, 0, NULL))
+    {
+        queue_start();
+        return FDS_SUCCESS;
+    }
+
+   return FDS_ERR_NO_SPACE_IN_QUEUES;
+}
+
+
+ret_code_t fds_file_delete(uint16_t file_id)
+{
+    fds_op_t op;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (file_id == FDS_FILE_ID_INVALID)
+    {
+        return FDS_ERR_INVALID_ARG;
+    }
+
+    op.op_code      = FDS_OP_DEL_FILE;
+    op.del.step     = FDS_OP_DEL_FILE_FLAG_DIRTY;
+    op.del.file_id  = file_id;
+
+    if (op_enqueue(&op, 0, NULL))
+    {
+        queue_start();
+        return FDS_SUCCESS;
+    }
+
+    return FDS_ERR_NO_SPACE_IN_QUEUES;
+}
+
+
+ret_code_t fds_gc(void)
+{
+    fds_op_t op;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    op.op_code = FDS_OP_GC;
+
+    if (op_enqueue(&op, 0, NULL))
+    {
+        if (m_gc.state != GC_BEGIN)
+        {
+            // Resume GC by retrying the last step.
+            m_gc.resume = true;
+        }
+
+        queue_start();
+        return FDS_SUCCESS;
+    }
+
+    return FDS_ERR_NO_SPACE_IN_QUEUES;
+}
+
+
+ret_code_t fds_record_iterate(fds_record_desc_t * const p_desc,
+                              fds_find_token_t  * const p_token)
+{
+    return record_find(NULL, NULL, p_desc, p_token);
+}
+
+
+ret_code_t fds_record_find(uint16_t                  file_id,
+                           uint16_t                  record_key,
+                           fds_record_desc_t * const p_desc,
+                           fds_find_token_t  * const p_token)
+{
+    return record_find(&file_id, &record_key, p_desc, p_token);
+}
+
+
+ret_code_t fds_record_find_by_key(uint16_t                  record_key,
+                                  fds_record_desc_t * const p_desc,
+                                  fds_find_token_t  * const p_token)
+{
+    return record_find(NULL, &record_key, p_desc, p_token);
+}
+
+
+ret_code_t fds_record_find_in_file(uint16_t                  file_id,
+                                   fds_record_desc_t * const p_desc,
+                                   fds_find_token_t  * const p_token)
+{
+    return record_find(&file_id, NULL, p_desc, p_token);
+}
+
+
+ret_code_t fds_descriptor_from_rec_id(fds_record_desc_t * const p_desc,
+                                      uint32_t                  record_id)
+{
+    if (p_desc == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    // Zero the descriptor and set the record_id field.
+    memset(p_desc, 0x00, sizeof(fds_record_desc_t));
+    p_desc->record_id = record_id;
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_record_id_from_desc(fds_record_desc_t const * const p_desc,
+                                   uint32_t                * const p_record_id)
+{
+    if ((p_desc == NULL) || (p_record_id == NULL))
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    *p_record_id = p_desc->record_id;
+
+    return FDS_SUCCESS;
+}
+
+
+ret_code_t fds_stat(fds_stat_t * const p_stat)
+{
+    uint16_t const words_in_page = FDS_PAGE_SIZE - FDS_PAGE_TAG_SIZE;
+    // The largest number of free contiguous words on any page.
+    uint16_t       contig_words  = 0;
+
+    if (!flag_is_set(FDS_FLAG_INITIALIZED))
+    {
+        return FDS_ERR_NOT_INITIALIZED;
+    }
+
+    if (p_stat == NULL)
+    {
+        return FDS_ERR_NULL_ARG;
+    }
+
+    memset(p_stat, 0x00, sizeof(fds_stat_t));
+
+    for (uint16_t i = 0; i < FDS_MAX_PAGES; i++)
+    {
+        uint32_t const * p_record   = NULL;
+        uint16_t const   words_used = m_pages[i].write_offset + m_pages[i].words_reserved;
+
+        p_stat->open_records += m_pages[i].records_open;
+        p_stat->words_used   += words_used;
+        contig_words         =  (words_in_page - words_used);
+
+        if (contig_words > p_stat->largest_contig)
+        {
+            p_stat->largest_contig = contig_words;
+        }
+
+        while (record_find_next(i, &p_record))
+        {
+            p_stat->valid_records++;
+        }
+
+        dirty_records_stat(i, &p_stat->dirty_records, &p_stat->freeable_words);
+    }
+
+    return FDS_SUCCESS;
+}
+
+
+#if defined(FDS_CRC_ENABLED)
+
+ret_code_t fds_verify_crc_on_writes(bool enable)
+{
+    if (enable)
+    {
+        flag_set(FDS_FLAG_VERIFY_CRC);
+    }
+    else
+    {
+        flag_clear(FDS_FLAG_VERIFY_CRC);
+    }
+
+    return FDS_SUCCESS;
+}
+
+#endif
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.h
new file mode 100644
index 0000000000..b655566fab
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds.h
@@ -0,0 +1,760 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef FDS_H__
+#define FDS_H__
+
+/**
+ * @defgroup flash_data_storage Flash Data Storage
+ * @ingroup app_common
+ * @{
+ *
+ * @brief   Flash Data Storage (FDS).
+ *
+ * @details Flash Data Storage is a minimalistic, record-oriented file system for the on-chip
+ *          flash. Files are stored as a collection of  records of variable length. FDS supports
+ *          synchronous read operations and asynchronous write operations (write, update,
+ *          and delete). FDS can be used from multiple threads.
+ */
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "sdk_errors.h"
+
+
+/**@brief   Invalid file ID.
+ *
+ * This value must not be used as a file ID by the application.
+ */
+#define FDS_FILE_ID_INVALID     (0xFFFF)
+
+
+/**@brief   Record key for deleted records.
+ *
+ * This key is used to flag a record as "dirty", which means that it should be removed during
+ * the next garbage collection. This value must not be used as a record key by the application.
+ */
+#define FDS_RECORD_KEY_DIRTY    (0x0000)
+
+
+/**@brief   FDS return values.
+ */
+enum
+{
+    FDS_SUCCESS = NRF_SUCCESS,  //!< The operation completed successfully.
+    FDS_ERR_OPERATION_TIMEOUT,  //!< Error. The operation timed out.
+    FDS_ERR_NOT_INITIALIZED,    //!< Error. The module has not been initialized.
+    FDS_ERR_UNALIGNED_ADDR,     //!< Error. The input data is not aligned to a word boundary.
+    FDS_ERR_INVALID_ARG,        //!< Error. The parameter contains invalid data.
+    FDS_ERR_NULL_ARG,           //!< Error. The parameter is NULL.
+    FDS_ERR_NO_OPEN_RECORDS,    //!< Error. The record is not open, so it cannot be closed.
+    FDS_ERR_NO_SPACE_IN_FLASH,  //!< Error. There is no space in flash memory.
+    FDS_ERR_NO_SPACE_IN_QUEUES, //!< Error. There is no space in the internal queues.
+    FDS_ERR_RECORD_TOO_LARGE,   //!< Error. The record exceeds the maximum allowed size.
+    FDS_ERR_NOT_FOUND,          //!< Error. The record was not found.
+    FDS_ERR_NO_PAGES,           //!< Error. No flash pages are available.
+    FDS_ERR_USER_LIMIT_REACHED, //!< Error. The maximum number of users has been reached.
+    FDS_ERR_CRC_CHECK_FAILED,   //!< Error. The CRC check failed.
+    FDS_ERR_BUSY,               //!< Error. The underlying flash subsystem was busy.
+    FDS_ERR_INTERNAL,           //!< Error. An internal error occurred.
+};
+
+
+/**@brief   Part of the record metadata.
+ *
+ * Contains the record key and the length of the record data.
+ */
+typedef struct
+{
+    uint16_t record_key;    //!< The record key (must be in the range 0x0001 - 0xBFFF).
+    uint16_t length_words;  //!< The length of the record data (in 4-byte words).
+} fds_tl_t;
+
+
+/**@brief   Part of the record metadata.
+ *
+ * Contains the ID of the file that the record belongs to and the CRC16 check value of the record.
+ */
+typedef struct
+{
+    uint16_t file_id;   //!< The ID of the file that the record belongs to.
+
+    /**@brief   CRC16 check value.
+     *
+     * The CRC is calculated over the entire record as stored in flash (including the record
+     * metadata except the CRC field itself). The CRC standard employed is CRC-16-CCITT.
+     */
+    uint16_t crc16;
+} fds_ic_t;
+
+
+/**@brief   The record metadata as stored in flash.
+ */
+typedef struct
+{
+    fds_tl_t tl;        //!< See @ref fds_tl_t.
+    fds_ic_t ic;        //!< See @ref fds_ic_t.
+    uint32_t record_id; //!< The unique record ID (32 bits).
+} fds_header_t;
+
+
+/**@brief   The record descriptor structure that is used to manipulate records.
+ *
+ * This structure is used by the FDS module. You must provide the descriptor to the module when
+ * you manipulate existing records. However, you should never modify it or use any of its fields.
+ *
+ * @note Never reuse the same descriptor for different records.
+ */
+typedef struct
+{
+    uint32_t         record_id;         //!< The unique record ID.
+    uint32_t const * p_record;          //!< The last known location of the record in flash.
+    uint16_t         gc_run_count;      //!< Number of times garbage collection has been run.
+    bool             record_is_open;    //!< Whether the record is currently open.
+} fds_record_desc_t;
+
+
+/**@brief   Structure that can be used to read the contents of a record stored in flash.
+ *
+ * This structure does not reflect the physical layout of a record in flash, but it points 
+ * to the locations where the record header (metadata) and the record data are stored.
+ */
+typedef struct
+{
+    fds_header_t const * p_header;  //!< Location of the record header in flash.
+    void         const * p_data;    //!< Location of the record data in flash.
+} fds_flash_record_t;
+
+
+/**@brief   A chunk of record data to be written to flash.
+ *
+ * @p p_data must be aligned to a word boundary. Make sure to keep it in 
+ * memory until the operation has completed, which is indicated by the respective FDS event.
+ */
+typedef struct
+{
+    void     const * p_data;        //!< Pointer to the data to store. Must be word-aligned.
+    uint16_t         length_words;  //!< Length of data pointed to by @p p_data (in 4-byte words).
+} fds_record_chunk_t;
+
+
+/**@brief   A record to be written to flash.
+ */
+typedef struct
+{
+    uint16_t file_id;                           //!< The ID of the file that the record belongs to.
+    uint16_t key;                               //!< The record key.
+    struct
+    {
+        fds_record_chunk_t const * p_chunks;    //!< The chunks that make up the record data.
+        uint16_t                   num_chunks;  //!< The number of chunks that make up the data.
+    } data;
+} fds_record_t;
+
+
+/**@brief   A token to a reserved space in flash, created by @ref fds_reserve.
+ *
+ * This token can be used to write the record in the reserved space (@ref fds_record_write_reserved)
+ * or to cancel the reservation (@ref fds_reserve_cancel).
+ */
+typedef struct
+{
+    uint16_t page;           //!< The logical ID of the page where space was reserved.
+    uint16_t length_words;   //!< The amount of space reserved (in 4-byte words).
+} fds_reserve_token_t;
+
+
+/**@brief   A token to keep information about the progress of @ref fds_record_find,
+ *          @ref fds_record_find_by_key, and @ref fds_record_find_in_file.
+ *
+ * @note    Always zero-initialize the token before using it for the first time.
+ * @note    Never reuse the same token to search for different records.
+ */
+typedef struct
+{
+    uint32_t const * p_addr;
+    uint16_t         page;
+} fds_find_token_t;
+
+
+/**@brief   FDS event IDs.
+ */
+typedef enum
+{
+    FDS_EVT_INIT,       //!< Event for @ref fds_init.
+    FDS_EVT_WRITE,      //!< Event for @ref fds_record_write and @ref fds_record_write_reserved.
+    FDS_EVT_UPDATE,     //!< Event for @ref fds_record_update.
+    FDS_EVT_DEL_RECORD, //!< Event for @ref fds_record_delete.
+    FDS_EVT_DEL_FILE,   //!< Event for @ref fds_file_delete.
+    FDS_EVT_GC          //!< Event for @ref fds_gc.
+} fds_evt_id_t;
+
+
+#if defined(__CC_ARM)
+    #pragma push
+    #pragma anon_unions
+#elif defined(__ICCARM__)
+    #pragma language=extended
+#elif defined(__GNUC__)
+    /* anonymous unions are enabled by default */
+#endif
+
+/**@brief   An FDS event.
+ */
+typedef struct
+{
+    fds_evt_id_t id;        //!< The event ID. See @ref fds_evt_id_t.
+    ret_code_t   result;    //!< The result of the operation related to this event.
+    union
+    {
+        struct
+        {
+            /* Currently not used. */
+            uint16_t pages_not_mounted;
+        } init;
+        struct
+        {
+            uint32_t record_id;
+            uint16_t file_id;
+            uint16_t record_key;
+            bool     is_record_updated;
+        } write; //!< Information for @ref FDS_EVT_WRITE and @ref FDS_EVT_UPDATE events.
+        struct
+        {
+            uint32_t record_id;
+            uint16_t file_id;
+            uint16_t record_key;
+            uint16_t records_deleted_count;
+        } del; //!< Information for @ref FDS_EVT_DEL_RECORD and @ref FDS_EVT_DEL_FILE events.
+        struct
+        {
+            /* Currently not used. */
+            uint16_t pages_skipped;
+            uint16_t space_reclaimed;
+        } gc;
+    };
+} fds_evt_t;
+
+#if defined(__CC_ARM)
+    #pragma pop
+#elif defined(__ICCARM__)
+    /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+    /* anonymous unions are enabled by default */
+#endif
+
+
+/**@brief   File system statistics. */
+typedef struct
+{
+    uint16_t open_records;      //!< The number of open records.
+    uint16_t valid_records;     //!< The number of valid records.
+    uint16_t dirty_records;     //!< The number of deleted ("dirty") records.
+    uint16_t words_reserved;    //!< The number of words reserved by @ref fds_reserve().
+
+    /**@brief The number of words written to flash, including those reserved for future writes.
+     */
+    uint16_t words_used;
+
+    /**@brief The largest number of free contiguous words in the file system.
+     *
+     * This number determines the largest record that can be stored by FDS.
+     * It takes into account all reservations for future writes.
+     */
+    uint16_t largest_contig;
+
+    /**@brief The largest number of words that can be reclaimed by garbage collection.
+     *
+     * The actual amount of space freed by garbage collection might be less than this value if
+     * records are open while garbage collection is run.
+     */
+    uint16_t freeable_words;
+} fds_stat_t;
+
+
+/**@brief   FDS event handler function prototype.
+ *
+ * @param   p_evt   The event.
+ */
+typedef void (*fds_cb_t)(fds_evt_t const * const p_evt);
+
+
+/**@brief   Function for registering an FDS event handler.
+ *
+ * The maximum amount of handlers that can be registered can be configured by changing the value
+ * of @ref FDS_MAX_USERS in fds_config.h.
+ * 
+ * @param[in]   cb  The event handler function.
+ *
+ * @retval  FDS_SUCCESS                 If the event handler was registered successfully.
+ * @retval  FDS_ERR_USER_LIMIT_REACHED  If the maximum number of registered callbacks is reached.
+ */
+ret_code_t fds_register(fds_cb_t cb);
+
+
+/**@brief   Function for initializing the module.
+ *
+ * This function initializes the module and installs the file system (unless it is installed
+ * already).
+ *
+ * This function is asynchronous. Completion is reported through an event. Make sure to call
+ * @ref fds_register before calling @ref fds_init so that you receive the completion event.
+ *
+ * @retval  FDS_SUCCESS         If the operation was queued successfully.
+ * @retval  FDS_ERR_NO_PAGES    If there is no space available in flash memory to install the
+ *                              file system.
+ */
+ret_code_t fds_init(void);
+
+
+/**@brief   Function for writing a record to flash.
+ *
+ * There are no restrictions on the file ID and the record key, except that the record key must be
+ * different from @ref FDS_RECORD_KEY_DIRTY and the file ID must be different from
+ * @ref FDS_FILE_ID_INVALID. In particular, no restrictions are made regarding the uniqueness of
+ * the file ID or the record key. All records with the same file ID are grouped into one file.
+ * If no file with the specified ID exists, it is created. There can be multiple records with the
+ * same record key in a file.
+ *
+ * Record data can consist of multiple chunks. The data must be aligned to a 4 byte boundary, and
+ * because it is not buffered internally, it must be kept in memory until the callback for the
+ * operation has been received. The length of the data must not exceed @ref FDS_VIRTUAL_PAGE_SIZE
+ * words minus 14 bytes.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to
+ * the registered event handler function.
+ *
+ * @param[out]  p_desc      The descriptor of the record that was written. Pass NULL if you do not
+ *                          need the descriptor.
+ * @param[in]   p_record    The record to be written to flash.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_record is NULL.
+ * @retval  FDS_ERR_INVALID_ARG         If the file ID or the record key is invalid.
+ * @retval  FDS_ERR_UNALIGNED_ADDR      If the record data is not aligned to a 4 byte boundary.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record data exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full or there are more record
+ *                                      chunks than can be buffered.
+ * @retval  FDS_ERR_NO_SPACE_IN_FLASH   If there is not enough free space in flash to store the
+ *                                      record.
+ */
+ret_code_t fds_record_write(fds_record_desc_t       * const p_desc,
+                            fds_record_t      const * const p_record);
+
+
+/**@brief   Function for reserving space in flash.
+ *
+ * This function can be used to reserve space in flash memory. To write a record into the reserved
+ * space, use @ref fds_record_write_reserved. Alternatively, use @ref fds_reserve_cancel to cancel
+ * a reservation.
+ *
+ * Note that this function does not write any data to flash.
+ *
+ * @param[out]  p_token         A token that can be used to write a record in the reserved space or
+ *                              cancel the reservation.
+ * @param[in]   length_words    The length of the record data (in 4-byte words).
+ *
+ * @retval  FDS_SUCCESS                 If the flash space was reserved successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_token is NULL instead of a valid token address.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record length exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_FLASH   If there is not enough free space in flash to store the
+ *                                      record.
+ */
+ret_code_t fds_reserve(fds_reserve_token_t * const p_token, uint16_t length_words);
+
+
+/**@brief   Function for canceling an @ref fds_reserve operation.
+ *
+ * @param[in]   p_token     The token that identifies the reservation, produced by @ref fds_reserve.
+ *
+ * @retval  FDS_SUCCESS             If the reservation was canceled.
+ * @retval  FDS_ERR_NOT_INITIALIZED If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG        If @p p_token is NULL instead of a valid token address.
+ * @retval  FDS_ERR_INVALID_ARG     If @p p_token contains invalid data.
+ */
+ret_code_t fds_reserve_cancel(fds_reserve_token_t * const p_token);
+
+
+/**@brief   Function for writing a record to a space in flash that was reserved using
+ *          @ref fds_reserve.
+ *
+ * There are no restrictions on the file ID and the record key, except that the record key must be
+ * different from @ref FDS_RECORD_KEY_DIRTY and the file ID must be different from
+ * @ref FDS_FILE_ID_INVALID. In particular, no restrictions are made regarding the uniqueness of
+ * the file ID or the record key. All records with the same file ID are grouped into one file.
+ * If no file with the specified ID exists, it is created. There can be multiple records with the
+ * same record key in a file.
+ *
+ * Record data can consist of multiple chunks. The data must be aligned to a 4 byte boundary, and
+ * because it is not buffered internally, it must be kept in memory until the callback for the
+ * operation has been received. The length of the data must not exceed @ref FDS_VIRTUAL_PAGE_SIZE
+ * words minus 14 bytes.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @note
+ * This function behaves similarly to @ref fds_record_write, with the exception that it never
+ * fails with the error @ref FDS_ERR_NO_SPACE_IN_FLASH.
+ *
+ * @param[out]  p_desc      The descriptor of the record that was written. Pass NULL if you do not
+ *                          need the descriptor.
+ * @param[in]   p_record    The record to be written to flash.
+ * @param[in]   p_token     The token that identifies the space reserved in flash.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_token is NULL instead of a valid token address.
+ * @retval  FDS_ERR_INVALID_ARG         If the file ID or the record key is invalid.
+ * @retval  FDS_ERR_UNALIGNED_ADDR      If the record data is not aligned to a 4 byte boundary.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record data exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full or there are more record
+ *                                      chunks than can be buffered.
+ */
+ret_code_t fds_record_write_reserved(fds_record_desc_t         * const p_desc,
+                                     fds_record_t        const * const p_record,
+                                     fds_reserve_token_t const * const p_token);
+
+
+/**@brief   Function for deleting a record.
+ *
+ * Deleted records cannot be located using @ref fds_record_find, @ref fds_record_find_by_key, or
+ * @ref fds_record_find_in_file. Additionally, they can no longer be opened using
+ * @ref fds_record_open.
+ *
+ * Note that deleting a record does not free the space it occupies in flash memory.
+ * To reclaim flash space used by deleted records, call @ref fds_gc to run garbage collection.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @param[in]   p_desc      The descriptor of the record that should be deleted.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If the specified record descriptor @p p_desc is NULL.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full.
+ */
+ret_code_t fds_record_delete(fds_record_desc_t * const p_desc);
+
+
+/**@brief   Function for deleting all records in a file.
+ *
+ * This function deletes a file, including all its records. Deleted records cannot be located
+ * using @ref fds_record_find, @ref fds_record_find_by_key, or @ref fds_record_find_in_file.
+ * Additionally, they can no longer be opened using @ref fds_record_open.
+ *
+ * Note that deleting records does not free the space they occupy in flash memory.
+ * To reclaim flash space used by deleted records, call @ref fds_gc to run garbage collection.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @param[in]   file_id     The ID of the file to be deleted.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_INVALID_ARG         If the specified @p file_id is invalid.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full.
+ */
+ret_code_t fds_file_delete(uint16_t file_id);
+
+
+/**@brief   Function for updating a record.
+ *
+ * Updating a record first writes a new record (@p p_record) to flash and then deletes the
+ * old record (identified by @p p_desc).
+ *
+ * There are no restrictions on the file ID and the record key, except that the record key must be
+ * different from @ref FDS_RECORD_KEY_DIRTY and the file ID must be different from
+ * @ref FDS_FILE_ID_INVALID. In particular, no restrictions are made regarding the uniqueness of
+ * the file ID or the record key. All records with the same file ID are grouped into one file.
+ * If no file with the specified ID exists, it is created. There can be multiple records with the
+ * same record key in a file.
+ *
+ * Record data can consist of multiple chunks. The data must be aligned to a 4 byte boundary, and
+ * because it is not buffered internally, it must be kept in memory until the callback for the
+ * operation has been received. The length of the data must not exceed @ref FDS_VIRTUAL_PAGE_SIZE
+ * words minus 14 bytes.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ * 
+ * @param[in, out]  p_desc      The descriptor of the record to update. When the function 
+ *                              returns with FDS_SUCCESS, this parameter contains the
+ *                              descriptor of the newly written record.
+ * @param[in]       p_record    The updated record to be written to flash.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_INVALID_ARG         If the file ID or the record key is invalid.
+ * @retval  FDS_ERR_UNALIGNED_ADDR      If the record data is not aligned to a 4 byte boundary.
+ * @retval  FDS_ERR_RECORD_TOO_LARGE    If the record data exceeds the maximum length.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full or there are more record
+ *                                      chunks than can be buffered.
+ * @retval  FDS_ERR_NO_SPACE_IN_FLASH   If there is not enough free space in flash to store the
+ *                                      updated record.
+ */
+ret_code_t fds_record_update(fds_record_desc_t       * const p_desc,
+                             fds_record_t      const * const p_record);
+
+
+/**@brief   Function for iterating through all records in flash.
+ *
+ * To search for the next record, call the function again and supply the same @ref fds_find_token_t
+ * structure to resume searching from the last record that was found.
+ *
+ * Note that the order with which records are iterated is not defined.
+ *
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no matching record was found.
+ */
+ret_code_t fds_record_iterate(fds_record_desc_t * const p_desc,
+                              fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for searching for records with a given record key in a file.
+ *
+ * This function finds the first record in a file that has the given record key. To search for the
+ * next record with the same key in the file, call the function again and supply the same
+ * @ref fds_find_token_t structure to resume searching from the last record that was found.
+ *
+ * @param[in]   file_id     The file ID.
+ * @param[in]   record_key  The record key.
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no matching record was found.
+ */
+ret_code_t fds_record_find(uint16_t                  file_id,
+                           uint16_t                  record_key,
+                           fds_record_desc_t * const p_desc,
+                           fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for searching for records with a given record key.
+ *
+ * This function finds the first record with a given record key, independent of the file it
+ * belongs to. To search for the next record with the same key, call the function again and supply
+ * the same @ref fds_find_token_t structure to resume searching from the last record that was found.
+ *
+ * @param[in]   record_key  The record key.
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no record with the given key was found.
+ */
+ret_code_t fds_record_find_by_key(uint16_t                  record_key,
+                                  fds_record_desc_t * const p_desc,
+                                  fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for searching for any record in a file.
+ *
+ * This function finds the first record in a file, independent of its record key.
+ * To search for the next record in the same file, call the function again and supply the same
+ * @ref fds_find_token_t structure to resume searching from the last record that was found.
+ *
+ * @param[in]   file_id     The file ID.
+ * @param[out]  p_desc      The descriptor of the record that was found.
+ * @param[out]  p_token     A token containing information about the progress of the operation.
+ *
+ * @retval  FDS_SUCCESS                 If a record was found.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_token is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If no matching record was found.
+ */
+ret_code_t fds_record_find_in_file(uint16_t                  file_id,
+                                   fds_record_desc_t * const p_desc,
+                                   fds_find_token_t  * const p_token);
+
+
+/**@brief   Function for opening a record for reading.
+ *
+ * This function opens a record that is stored in flash, so that it can be read. The function
+ * initializes an @ref fds_flash_record_t structure, which can be used to access the record data as
+ * well as its associated metadata. The pointers provided in the @ref fds_flash_record_t structure
+ * are pointers to flash memory.
+ *
+ * Opening a record with @ref fds_record_open prevents garbage collection to run on the virtual
+ * flash page in which record is stored, so that the contents of the memory pointed by fields in
+ * @ref fds_flash_record_t are guaranteed to remain unmodified as long as the record is kept open.
+ *
+ * When you are done reading a record, call @ref fds_record_close to close it. Garbage collection
+ * can then reclaim space on the virtual page where the record is stored. Note that you must
+ * provide the same descriptor for @ref fds_record_close as you did for this function.
+ *
+ * @param[in]   p_desc          The descriptor of the record to open.
+ * @param[out]  p_flash_record  The record, as stored in flash.
+ *
+ * @retval  FDS_SUCCESS                 If the record was opened successfully.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_desc or @p p_flash_record is NULL.
+ * @retval  FDS_ERR_NOT_FOUND           If the record was not found. It might have been deleted, or
+ *                                      it might not have been written yet.
+ * @retval  FDS_ERR_CRC_CHECK_FAILED    If the CRC check for the record failed.
+ */
+ret_code_t fds_record_open(fds_record_desc_t  * const p_desc,
+                           fds_flash_record_t * const p_flash_record);
+
+
+/**@brief   Function for closing a record.
+ *
+ * Closing a record allows garbage collection to run on the virtual page in which the record is
+ * stored (if no other records remain open on that page). The descriptor passed as an argument
+ * must be the same as the one used to open the record using @ref fds_record_open.
+ *
+ * Note that closing a record does not invalidate its descriptor. You can still supply the
+ * descriptor to all functions that accept a record descriptor as a parameter.
+ *
+ * @param[in]   p_desc  The descriptor of the record to close.
+ *
+ * @retval  FDS_SUCCESS             If the record was closed successfully.
+ * @retval  FDS_ERR_NULL_ARG        If @p p_desc is NULL.
+ * @retval  FDS_ERR_NO_OPEN_RECORDS If the record is not open.
+ * @retval  FDS_ERR_NOT_FOUND       If the record could not be found.
+ */
+ret_code_t fds_record_close(fds_record_desc_t * const p_desc);
+
+
+/**@brief   Function for running garbage collection.
+ *
+ * Garbage collection reclaims the flash space that is occupied by records that have been deleted,
+ * or that failed to be completely written due to, for example, a power loss.
+ *
+ * This function is asynchronous. Completion is reported through an event that is sent to the
+ * registered event handler function.
+ *
+ * @retval  FDS_SUCCESS                 If the operation was queued successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NO_SPACE_IN_QUEUES  If the operation queue is full.
+ */
+ret_code_t fds_gc(void);
+
+
+/**@brief   Function for obtaining a descriptor from a record ID.
+ *
+ * This function can be used to reconstruct a descriptor from a record ID, like the one that is
+ * passed to the callback function.
+ *
+ * @note
+ * This function does not check whether a record with the given record ID exists.
+ * If a non-existing record ID is supplied, the resulting descriptor is invalid and will cause
+ * other functions to fail when it is supplied as parameter.
+ *
+ * @param[out]  p_desc      The descriptor of the record with the given record ID.
+ * @param[in]   record_id   The record ID for which a descriptor should be returned.
+ *
+ * @retval  FDS_SUCCESS         If a descriptor was returned.
+ * @retval  FDS_ERR_NULL_ARG    If @p p_desc is NULL.
+ */
+ret_code_t fds_descriptor_from_rec_id(fds_record_desc_t * const p_desc,
+                                      uint32_t                  record_id);
+
+
+/**@brief   Function for obtaining a record ID from a record descriptor.
+ *
+ * This function can be used to extract a record ID from a descriptor. For example, you could use
+ * it in the callback function to compare the record ID of an event to the record IDs of the
+ * records for which you have a descriptor.
+ *
+ * @warning
+ * This function does not check whether the record descriptor is valid. If the descriptor is not
+ * initialized or has been tampered with, the resulting record ID might be invalid.
+ *
+ * @param[in]   p_desc          The descriptor from which the record ID should be extracted.
+ * @param[out]  p_record_id     The record ID that is contained in the given descriptor.
+ *
+ * @retval  FDS_SUCCESS         If a record ID was returned.
+ * @retval  FDS_ERR_NULL_ARG    If @p p_desc or @p p_record_id is NULL.
+ */
+ret_code_t fds_record_id_from_desc(fds_record_desc_t const * const p_desc,
+                                   uint32_t                * const p_record_id);
+
+
+/**@brief   Function for retrieving file system statistics.
+ *
+ * This function retrieves file system statistics, such as the number of open records, the space
+ * that can be reclaimed by garbage collection, and others.
+ *
+ * @param[out]  p_stat      File system statistics.
+ *
+ * @retval  FDS_SUCCESS                 If the statistics were returned successfully.
+ * @retval  FDS_ERR_NOT_INITIALIZED     If the module is not initialized.
+ * @retval  FDS_ERR_NULL_ARG            If @p p_stat is NULL.
+ */
+ret_code_t fds_stat(fds_stat_t * const p_stat);
+
+
+#if defined(FDS_CRC_ENABLED)
+
+/**@brief   Function for enabling and disabling CRC verification for write operations.
+ *
+ * CRC verification ensures that data that is queued for writing does not change before the write
+ * actually happens. Use this function to enable or disable CRC verification. If verification is
+ * enabled, the error @ref FDS_ERR_CRC_CHECK_FAILED is returned in the event for
+ * @ref fds_record_write, @ref fds_record_write_reserved, or @ref fds_record_update if
+ * verification fails.
+ *
+ * @note
+ * CRC verification is enabled or disabled globally, thus for all users of the FDS module.
+ *
+ * @param[in]   enabled     1 to enable CRC verification. 0 to disable CRC verification.
+ *
+ * @retval  FDS_SUCCESS     If CRC verification was enabled or disabled successfully.
+ */
+ret_code_t fds_verify_crc_on_writes(bool enabled);
+
+#endif
+
+/** @} */
+
+#endif // FDS_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds_internal_defs.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds_internal_defs.h
new file mode 100644
index 0000000000..b7c2e3a3d5
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fds/fds_internal_defs.h
@@ -0,0 +1,332 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef FDS_INTERNAL_DEFS_H__
+#define FDS_INTERNAL_DEFS_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "fds_config.h"
+
+#if defined (FDS_THREADS)
+    #include "nrf_soc.h"
+    #include "app_util_platform.h"
+#endif
+
+#define FDS_PAGE_TAG_SIZE       (2) // Page tag size, in 4-byte words.
+#define FDS_PAGE_TAG_WORD_0     (0) // Offset of the first word in the page tag from the page address.
+#define FDS_PAGE_TAG_WORD_1     (1) // Offset of the second word in the page tag from the page address.
+
+// Page tag constants
+#define FDS_PAGE_TAG_MAGIC      (0xDEADC0DE)
+#define FDS_PAGE_TAG_SWAP       (0xF11E01FF)
+#define FDS_PAGE_TAG_DATA       (0xF11E01FE)
+
+#define FDS_ERASED_WORD         (0xFFFFFFFF)
+
+#define FDS_OFFSET_TL           (0) // Offset of TL from the record base address, in 4-byte words.
+#define FDS_OFFSET_IC           (1) // Offset of IC from the record base address, in 4-byte words.
+#define FDS_OFFSET_ID           (2) // Offset of ID from the record base address, in 4-byte words.
+#define FDS_OFFSET_DATA         (3) // Offset of the data (chunks) from the record base address, in 4-byte words.
+
+#define FDS_HEADER_SIZE_TL      (1) // Size of the TL part of the header, in 4-byte words.
+#define FDS_HEADER_SIZE_IC      (1) // Size of the IC part of the header, in 4-byte words.
+#define FDS_HEADER_SIZE_ID      (1) // Size of the record ID in the header, in 4-byte words.
+#define FDS_HEADER_SIZE         (3) // Size of the whole header, in 4-byte words.
+
+#define FDS_OP_EXECUTING        (FS_SUCCESS)
+#define FDS_OP_COMPLETED        (0x1D1D)
+
+// The size of a physical page, in 4-byte words.
+#if   defined(NRF51)
+    #define FDS_PHY_PAGE_SIZE   (256)
+#elif defined(NRF52)
+    #define FDS_PHY_PAGE_SIZE   (1024)
+#endif
+
+// The number of physical pages to be used. This value is configured indirectly.
+#define FDS_PHY_PAGES               ((FDS_VIRTUAL_PAGES * FDS_VIRTUAL_PAGE_SIZE) / FDS_PHY_PAGE_SIZE)
+
+// The size of a virtual page, in number of physical pages.
+#define FDS_PHY_PAGES_IN_VPAGE      (FDS_VIRTUAL_PAGE_SIZE / FDS_PHY_PAGE_SIZE)
+
+// The number of pages available to store data; which is the total minus one (the swap).
+#define FDS_MAX_PAGES               (FDS_VIRTUAL_PAGES - 1)
+
+ // Just a shorter name for the size, in words, of a virtual page.
+#define FDS_PAGE_SIZE               (FDS_VIRTUAL_PAGE_SIZE)
+
+
+#if (FDS_VIRTUAL_PAGE_SIZE % FDS_PHY_PAGE_SIZE != 0)
+    #error "FDS_VIRTUAL_PAGE_SIZE must be a multiple of the size of a physical page."
+#endif
+
+#if (FDS_VIRTUAL_PAGES < 2)
+    #error "FDS requires at least two virtual pages."
+#endif
+
+
+// FDS internal status flags.
+typedef enum
+{
+    FDS_FLAG_INITIALIZING   = (1 << 0),  // The module is initializing.
+    FDS_FLAG_INITIALIZED    = (1 << 1),  // The module is initialized.
+    FDS_FLAG_PROCESSING     = (1 << 2),  // The queue is being processed.
+    FDS_FLAG_VERIFY_CRC     = (1 << 3),  // Verify CRC upon writing a record.
+} fds_flags_t;
+
+
+// Page types.
+typedef enum
+{
+    FDS_PAGE_DATA,      // Page is ready for storage.
+    FDS_PAGE_SWAP,      // Page is reserved for garbage collection.
+    FDS_PAGE_ERASED,    // Page is erased.
+    FDS_PAGE_UNDEFINED, // Undefined page type.
+} fds_page_type_t;
+
+
+typedef struct
+{
+    fds_page_type_t         page_type;      // The page type.
+    uint32_t        const * p_addr;         // The address of the page.
+    uint16_t                write_offset;   // The page write offset, in 4-byte words.
+    uint16_t                words_reserved; // The amount of words reserved by fds_write_reserve().
+    uint16_t                records_open;   // The number of records opened using fds_open().
+    bool                    can_gc;         // Indicates that there are some records that have been deleted.
+} fds_page_t;
+
+
+typedef struct
+{
+    uint32_t const * p_addr;
+    uint16_t         write_offset;
+} fds_swap_page_t;
+
+
+// FDS op-codes.
+typedef enum
+{
+    FDS_OP_NONE,
+    FDS_OP_INIT,        // Initialize the module.
+    FDS_OP_WRITE,       // Write a record to flash.
+    FDS_OP_UPDATE,      // Update a record.
+    FDS_OP_DEL_RECORD,  // Delete a record.
+    FDS_OP_DEL_FILE,    // Delete a file.
+    FDS_OP_GC           // Run garbage collection.
+} fds_op_code_t;
+
+
+typedef enum
+{
+    FDS_OP_INIT_TAG_SWAP,
+    FDS_OP_INIT_TAG_DATA,
+    FDS_OP_INIT_ERASE_SWAP,
+    FDS_OP_INIT_PROMOTE_SWAP,
+} fds_init_step_t;
+
+
+typedef enum
+{
+    FDS_OP_WRITE_HEADER_BEGIN,      // Write the record key and length.
+    FDS_OP_WRITE_HEADER_FINALIZE,   // Write the file ID and CRC.
+    FDS_OP_WRITE_RECORD_ID,         // Write the record ID.
+    FDS_OP_WRITE_CHUNKS,            // Write the record data.
+    FDS_OP_WRITE_FIND_RECORD,
+    FDS_OP_WRITE_FLAG_DIRTY,        // Flag a record as dirty (as part of an update operation).
+    FDS_OP_WRITE_DONE,
+} fds_write_step_t;
+
+
+typedef enum
+{
+    FDS_OP_DEL_RECORD_FLAG_DIRTY,   // Flag a record as dirty.
+    FDS_OP_DEL_FILE_FLAG_DIRTY,     // Flag multiple records as dirty.
+    FDS_OP_DEL_DONE,
+} fds_delete_step_t;
+
+
+#if defined(__CC_ARM)
+    #pragma push
+    #pragma anon_unions
+#elif defined(__ICCARM__)
+    #pragma language=extended
+#elif defined(__GNUC__)
+    // anonymous unions are enabled by default
+#endif
+
+typedef struct
+{
+    fds_op_code_t op_code;                      // The opcode for the operation.
+    union
+    {
+        struct
+        {
+            fds_init_step_t step;               // The current step the operation is at.
+        } init;
+        struct
+        {
+            fds_header_t     header;
+            fds_write_step_t step;              // The current step the operation is at.
+            uint16_t         page;              // The page the flash space for this command was reserved.
+            uint16_t         chunk_offset;      // Offset used for writing record chunks, in 4-byte words.
+            uint8_t          chunk_count;       // Number of chunks to be written.
+            uint32_t         record_to_delete;  // The record to delete in case this is an update.
+        } write;
+        struct
+        {
+            fds_delete_step_t step;
+            uint16_t          file_id;
+            uint16_t          record_key;
+            uint32_t          record_to_delete;
+        } del;
+    };
+} fds_op_t;
+
+#if defined(__CC_ARM)
+    #pragma pop
+#elif defined(__ICCARM__)
+    // leave anonymous unions enabled
+#elif defined(__GNUC__)
+    // anonymous unions are enabled by default
+#endif
+
+
+typedef struct
+{
+    fds_op_t op[FDS_OP_QUEUE_SIZE];    // Queued flash operations.
+    uint32_t rp;                       // The index of the command being executed.
+    uint32_t count;                    // Number of elements in the queue.
+} fds_op_queue_t;
+
+
+typedef struct
+{
+    fds_record_chunk_t chunk[FDS_CHUNK_QUEUE_SIZE];
+    uint32_t           rp;
+    uint32_t           count;
+} fds_chunk_queue_t;
+
+
+enum
+{
+    PAGE_ERASED = 0x1,
+    PAGE_DATA   = 0x2,
+    SWAP_EMPTY  = 0x4,
+    SWAP_DIRTY  = 0x8,
+};
+
+
+typedef enum
+{
+    // This is a fatal error.
+    NO_PAGES,
+
+    // All pages are erased. Perform a fresh installation.
+    FRESH_INSTALL     = (PAGE_ERASED),
+
+    // Swap is missing. Tag an erased page as swap.
+    TAG_SWAP          = (PAGE_ERASED | PAGE_DATA),
+
+    // Swap is empty. Tag all erased pages as data.
+    TAG_DATA         = (PAGE_ERASED | SWAP_EMPTY),
+
+    // Swap is empty. Tag all remaining erased pages as data.
+    TAG_DATA_INST    = (PAGE_ERASED | PAGE_DATA | SWAP_EMPTY),
+
+    // The swap is dirty. This indicates that the device powered off during GC. However, since there
+    // is also an erased page, it is possible to assume that that page had been entirely garbage
+    // collected. Hence, tag the swap as data, one erased page as swap and any remaining pages as data.
+    PROMOTE_SWAP      = (PAGE_ERASED | SWAP_DIRTY),
+
+    // Similar to the above. Tag the swap as data, one erased page as swap, and any remain
+    // pages as data.
+    PROMOTE_SWAP_INST = (PAGE_ERASED | PAGE_DATA | SWAP_DIRTY),
+
+    // The swap is dirty (written) and there are no erased pages. This indicates that the device
+    // was powered off during GC. It is safe to discard (erase) the swap, since data that was
+    // swapped out lies in one of the valid pages.
+    DISCARD_SWAP      = (PAGE_DATA  | SWAP_DIRTY),
+
+    // Do nothing.
+    ALREADY_INSTALLED = (PAGE_DATA  | SWAP_EMPTY),
+
+} fds_init_opts_t;
+
+
+typedef enum
+{
+    GC_BEGIN,               // Begin GC.
+    GC_NEXT_PAGE,           // GC a page.
+    GC_FIND_NEXT_RECORD,    // Find a valid record to copy.
+    GC_COPY_RECORD,         // Copy a valid record to swap.
+    GC_ERASE_PAGE,          // Erase the page being garbage collected.
+    GC_DISCARD_SWAP,        // Erase (discard) the swap page.
+    GC_PROMOTE_SWAP,        // Tag the swap as valid.
+    GC_TAG_NEW_SWAP         // Tag a freshly erased (GCed) page as swap.
+} fds_gc_state_t;
+
+
+// Holds garbage collection status and related data.
+typedef struct
+{
+    fds_gc_state_t   state;                     // The current GC step.
+    uint16_t         cur_page;                  // The current page being garbage collected.
+    uint32_t const * p_record_src;              // The current record being copied to swap.
+    uint16_t         run_count;                 // Total number of times GC was run.
+    bool             do_gc_page[FDS_MAX_PAGES]; // Controls which pages to garbage collect.
+    bool             resume;                    // Whether or not GC should be resumed.
+} fds_gc_data_t;
+
+
+// Macros to enable and disable application interrupts.
+#if defined (FDS_THREADS)
+
+    #define CRITICAL_SECTION_ENTER()    CRITICAL_REGION_ENTER()
+    #define CRITICAL_SECTION_EXIT()     CRITICAL_REGION_EXIT()
+
+#else
+
+    #define CRITICAL_SECTION_ENTER()
+    #define CRITICAL_SECTION_EXIT()
+
+#endif
+
+
+#endif // FDS_INTERNAL_DEFS_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/config/fstorage_config.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/config/fstorage_config.h
new file mode 100644
index 0000000000..9ff7550997
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/config/fstorage_config.h
@@ -0,0 +1,86 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef FS_CONFIG_H__
+#define FS_CONFIG_H__
+
+/**
+ * @defgroup fstorage_config fstorage configuration
+ * @ingroup fstorage
+ * @{
+ *
+ * @brief fstorage configuration options.
+ */
+
+
+/**@brief   Configures the size of fstorage internal queue.
+ * @details Increase this if there are many users, or if it is likely that many operation will be
+ *          queued at once without waiting for the previous operations to complete. In general,
+ *          increase the queue size if you frequently receive @ref FS_ERR_QUEUE_FULL errors when
+ *          calling @ref fs_store or @ref fs_erase.
+ */
+#define FS_QUEUE_SIZE       (4)
+
+/**@brief   Configures how many times should fstorage attempt to execute an operation if
+ *          the SoftDevice fails to schedule flash access due to high BLE activity.
+ * @details Increase this value if fstorage events return the @ref FS_ERR_OPERATION_TIMEOUT error
+ *          often.
+ */
+#define FS_OP_MAX_RETRIES   (3)
+
+
+/**@brief   Configures the maximum number of words to be written to flash in a single operation.
+ *          If data length exceeds this value, the data will be written down in several chunks,
+ *          as necessary.
+ *
+ * @details Tweaking this value can increase the chances of the SoftDevice being able to fit
+ *          flash operations in between radio activity. This value is bound by the maximum number
+ *          of words which the SoftDevice can write to flash in a single call to
+ *          @ref sd_flash_write, which is 256 words for nRF51 ICs and 1024 words for nRF52 ICs.
+ */
+#if   defined (NRF51)
+    #define FS_MAX_WRITE_SIZE_WORDS     (256)
+#elif defined (NRF52)
+    #define FS_MAX_WRITE_SIZE_WORDS     (1024)
+#endif
+
+/** @} */
+
+#endif // FS_CONFIG_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.c
new file mode 100644
index 0000000000..5cf3d8d426
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.c
@@ -0,0 +1,521 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "fstorage.h"
+#include "fstorage_config.h"
+#include "fstorage_internal_defs.h"
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include "nrf_error.h"
+#include "nrf_soc.h"
+
+
+static uint8_t       m_flags;       // fstorage status flags.
+static fs_op_queue_t m_queue;       // Queue of requested operations.
+static uint8_t       m_retry_count; // Number of times the last flash operation was retried.
+
+
+// Sends events to the application.
+static void send_event(fs_op_t const * const p_op, fs_ret_t result)
+{
+    fs_evt_t evt;
+    memset(&evt, 0x00, sizeof(fs_evt_t));
+
+    switch (p_op->op_code)
+    {
+        case FS_OP_STORE:
+            evt.id                 = FS_EVT_STORE;
+            evt.store.p_data       = p_op->store.p_dest;
+            evt.store.length_words = p_op->store.length_words;
+            break;
+
+        case FS_OP_ERASE:
+            evt.id               = FS_EVT_ERASE;
+            evt.erase.first_page = p_op->erase.page - p_op->erase.pages_erased;
+            evt.erase.last_page  = p_op->erase.page;
+            break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+
+    p_op->p_config->callback(&evt, result);
+}
+
+
+// Checks that a configuration is non-NULL and within section variable bounds.
+static bool check_config(fs_config_t const * const config)
+{
+    if ((config != NULL) &&
+        (FS_SECTION_VARS_START_ADDR <= (uint32_t)config) &&
+        (FS_SECTION_VARS_END_ADDR   >  (uint32_t)config))
+    {
+        return true;
+    }
+   
+    return false;
+}
+
+
+// Executes a store operation.
+static uint32_t store_execute(fs_op_t const * const p_op)
+{
+    uint16_t chunk_len;
+
+    if ((p_op->store.length_words - p_op->store.offset) < FS_MAX_WRITE_SIZE_WORDS)
+    {
+        chunk_len = p_op->store.length_words - p_op->store.offset;
+    }
+    else
+    {
+        chunk_len = FS_MAX_WRITE_SIZE_WORDS;
+    }
+
+    return sd_flash_write((uint32_t*)p_op->store.p_dest + p_op->store.offset,
+                          (uint32_t*)p_op->store.p_src  + p_op->store.offset,
+                          chunk_len);
+}
+
+
+// Executes an erase operation.
+static uint32_t erase_execute(fs_op_t const * const p_op)
+{
+    return sd_flash_page_erase(p_op->erase.page);
+}
+
+
+// Advances the queue, wrapping around if necessary.
+// If no elements are left in the queue, clears the FS_FLAG_PROCESSING flag.
+static void queue_advance(void)
+{
+    if (--m_queue.count == 0)
+    {
+        m_flags &= ~FS_FLAG_PROCESSING;
+    }
+
+    if (++m_queue.rp == FS_QUEUE_SIZE)
+    {
+        m_queue.rp = 0;
+    }
+}
+
+
+// Processes the current element in the queue. If the queue is empty, does nothing.
+static void queue_process(void)
+{
+    uint32_t         ret;
+    fs_op_t  * const p_op = &m_queue.op[m_queue.rp];
+
+    if (m_queue.count > 0)
+    {
+        switch (p_op->op_code)
+        {
+            case FS_OP_STORE:
+                ret = store_execute(p_op);
+                break;
+
+            case FS_OP_ERASE:
+                ret = erase_execute(p_op);
+                break;
+
+             default:
+                ret = FS_ERR_INTERNAL;
+                break;
+        }
+
+        // There is a pending flash operation which was not initiated by this module.
+        // Stop processing the queue and wait for a system event.
+        if (ret == NRF_ERROR_BUSY)
+        {
+            m_flags &= ~FS_FLAG_PROCESSING;
+            m_flags |= FS_FLAG_FLASH_REQ_PENDING;
+        }
+        else if (ret != NRF_SUCCESS)
+        {
+            // An error has occurred.
+            send_event(p_op, FS_ERR_INTERNAL);
+        }
+        else
+        {
+            // Operation is executing.
+        }
+    }
+}
+
+
+// Starts processing the queue if there are no pending flash operations, both inside and
+// outside this module. Returns immediately otherwise.
+static void queue_start(void)
+{
+    if (!(m_flags & FS_FLAG_PROCESSING) &&
+        !(m_flags & FS_FLAG_FLASH_REQ_PENDING))
+    {
+        m_flags |= FS_FLAG_PROCESSING;
+        queue_process();
+    }
+}
+
+
+// Flash operation success callback handler. Keeps track of the progress of an operation.
+// If it has finished, advances the queue and notifies the application.
+static void on_operation_success(fs_op_t * const p_op)
+{
+    m_retry_count = 0;
+
+    switch (p_op->op_code)
+    {
+        case FS_OP_STORE:
+        {
+            uint16_t chunk_len;
+
+            if ((p_op->store.length_words - p_op->store.offset) < FS_MAX_WRITE_SIZE_WORDS)
+            {
+                chunk_len = p_op->store.length_words - p_op->store.offset;
+            }
+            else
+            {
+                chunk_len = FS_MAX_WRITE_SIZE_WORDS;
+            }
+
+            p_op->store.offset += chunk_len;
+
+            if (p_op->store.offset == p_op->store.length_words)
+            {
+                // The operation has finished.
+                send_event(p_op, FS_SUCCESS);
+                queue_advance();
+            }
+        }
+        break;
+
+        case FS_OP_ERASE:
+        {
+            p_op->erase.page++;
+            p_op->erase.pages_erased++;
+
+            if (p_op->erase.pages_erased == p_op->erase.pages_to_erase)
+            {
+                send_event(p_op, FS_SUCCESS);
+                queue_advance();
+            }
+        }
+        break;
+
+        default:
+            // Should not happen.
+            break;
+    }
+}
+
+
+// Flash operation failure callback handler. If the maximum number of retries has
+// been reached, notifies the application and advances the queue.
+static void on_operation_failure(fs_op_t const * const p_op)
+{
+    if (++m_retry_count > FS_OP_MAX_RETRIES)
+    {
+        m_retry_count = 0;
+
+        send_event(p_op, FS_ERR_OPERATION_TIMEOUT);
+        queue_advance();
+    }
+}
+
+
+// Retrieves a pointer to the next free element in the queue.
+// Additionally, increases the number of elements stored in the queue.
+static bool queue_get_next_free(fs_op_t ** p_op)
+{
+    uint32_t idx;
+
+    if (m_queue.count == FS_QUEUE_SIZE)
+    {
+        return false;
+    }
+
+    idx = ((m_queue.rp + m_queue.count) < FS_QUEUE_SIZE) ?
+           (m_queue.rp + m_queue.count) : 0;
+
+    m_queue.count++;
+
+    // Zero the element so that unassigned fields will be zero.
+    memset(&m_queue.op[idx], 0x00, sizeof(fs_op_t));
+
+    *p_op = &m_queue.op[idx];
+
+    return true;
+}
+
+
+fs_ret_t fs_init(void)
+{
+    uint32_t const   users         = FS_SECTION_VARS_COUNT;
+    uint32_t const * p_current_end = FS_PAGE_END_ADDR;
+    uint32_t         index_max     = 0x00;
+    uint32_t         index_last    = 0xFFFFFFFF;
+
+    if (m_flags & FS_FLAG_INITIALIZED)
+    {
+        return FS_SUCCESS;
+    }
+
+    #if 0
+    // Check for configurations with duplicate priority.
+    for (uint32_t i = 0; i < users; i++)
+    {
+        for (uint32_t j = i + 1; j < users; j++)
+        {
+            fs_config_t const * const p_config_i = FS_SECTION_VARS_GET(i);
+            fs_config_t const * const p_config_j = FS_SECTION_VARS_GET(j);
+
+            if (p_config_i->page_order == p_config_j->page_order)
+            {
+                // Error.
+                return FS_ERR_INVALID_CFG;
+            }
+        }
+    }
+    #endif
+
+    // Assign pages to registered users, beginning with the ones with the highest
+    // priority, which will be assigned pages with the highest memory address.
+
+    for (uint32_t i = 0; i < users; i++)
+    {
+        uint8_t max_priority  = 0x00;
+
+        for (uint32_t j = 0; j < users; j++)
+        {
+            fs_config_t * const p_config = FS_SECTION_VARS_GET(j);
+
+            // Skip the one assigned during last iteration.
+            if (j == index_last)
+            {
+                continue;
+            }
+
+            if (p_config->priority >= max_priority)
+            {
+                max_priority = p_config->priority;
+                index_max    = j;
+            }
+        }
+
+        fs_config_t * const p_config = FS_SECTION_VARS_GET(index_max);
+
+        p_config->p_end_addr   = p_current_end;
+        p_config->p_start_addr = p_current_end - (p_config->num_pages * FS_PAGE_SIZE_WORDS);
+
+        p_current_end = p_config->p_start_addr;
+
+        index_last = index_max;
+    }
+
+    m_flags |= FS_FLAG_INITIALIZED;
+
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_store(fs_config_t const * const p_config,
+                  uint32_t    const * const p_dest,
+                  uint32_t    const * const p_src,
+                  uint16_t    const         length_words)
+{
+    fs_op_t * p_op;
+
+    if (!(m_flags & FS_FLAG_INITIALIZED))
+    {
+        return FS_ERR_NOT_INITIALIZED;
+    }
+
+    if (!check_config(p_config))
+    {
+        return FS_ERR_INVALID_CFG;
+    }
+
+    if ((p_src == NULL) || (p_dest == NULL))
+    {
+        return FS_ERR_NULL_ARG;
+    }
+
+    // Check that both pointers are word aligned.
+    if (((uint32_t)p_src  & 0x03) ||
+        ((uint32_t)p_dest & 0x03))
+    {
+        return FS_ERR_UNALIGNED_ADDR;
+    }
+
+    // Check that the operation doesn't go outside the client's memory boundaries.
+    if ((p_config->p_start_addr > p_dest) ||
+        (p_config->p_end_addr   < (p_dest + length_words)))
+    {
+        return FS_ERR_INVALID_ADDR;
+    }
+
+    if (length_words == 0)
+    {
+        return FS_ERR_INVALID_ARG;
+    }
+
+    if (!queue_get_next_free(&p_op))
+    {
+        return FS_ERR_QUEUE_FULL;
+    }
+
+    // Initialize the operation.
+    p_op->p_config           = p_config;
+    p_op->op_code            = FS_OP_STORE;
+    p_op->store.p_src        = p_src;
+    p_op->store.p_dest       = p_dest;
+    p_op->store.length_words = length_words;
+
+    queue_start();
+
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_erase(fs_config_t const * const p_config,
+                  uint32_t    const * const p_page_addr,
+                  uint16_t    const         num_pages)
+{
+    fs_op_t * p_op;
+
+    if (!(m_flags & FS_FLAG_INITIALIZED))
+    {
+        return FS_ERR_NOT_INITIALIZED;
+    }
+
+    if (!check_config(p_config))
+    {
+        return FS_ERR_INVALID_CFG;
+    }
+
+    if (p_page_addr == NULL)
+    {
+        return FS_ERR_NULL_ARG;
+    }
+
+    // Check that the page is aligned to a page boundary.
+    if (((uint32_t)p_page_addr % FS_PAGE_SIZE) != 0)
+    {
+        return FS_ERR_UNALIGNED_ADDR;
+    }
+
+    // Check that the operation doesn't go outside the client's memory boundaries.
+    if ((p_page_addr < p_config->p_start_addr) ||
+        (p_page_addr + (FS_PAGE_SIZE_WORDS * num_pages) > p_config->p_end_addr))
+    {
+        return FS_ERR_INVALID_ADDR;
+    }
+
+    if (num_pages == 0)
+    {
+        return FS_ERR_INVALID_ARG;
+    }
+
+    if (!queue_get_next_free(&p_op))
+    {
+        return FS_ERR_QUEUE_FULL;
+    }
+
+    // Initialize the operation.
+    p_op->p_config             = p_config;
+    p_op->op_code              = FS_OP_ERASE;
+    p_op->erase.page           = ((uint32_t)p_page_addr / FS_PAGE_SIZE);
+    p_op->erase.pages_to_erase = num_pages;
+
+    queue_start();
+
+    return FS_SUCCESS;
+}
+
+
+fs_ret_t fs_queued_op_count_get(uint32_t * const p_op_count)
+{
+    if (p_op_count == NULL)
+    {
+        return FS_ERR_NULL_ARG;
+    }
+
+    *p_op_count = m_queue.count;
+
+    return FS_SUCCESS;
+}
+
+
+void fs_sys_event_handler(uint32_t sys_evt)
+{
+    fs_op_t * const p_op = &m_queue.op[m_queue.rp];
+    
+    if (m_flags & FS_FLAG_PROCESSING)
+    {
+        // A flash operation was initiated by this module. Handle the result.
+        switch (sys_evt)
+        {
+            case NRF_EVT_FLASH_OPERATION_SUCCESS:
+                on_operation_success(p_op);
+                break;
+
+            case NRF_EVT_FLASH_OPERATION_ERROR:
+                on_operation_failure(p_op);
+                break;
+        }
+    }
+    else if ((m_flags & FS_FLAG_FLASH_REQ_PENDING))
+    {
+        // A flash operation was initiated outside this module.
+        // A callback which indicates that it has finished was received.
+        m_flags &= ~FS_FLAG_FLASH_REQ_PENDING;
+
+        // If there are any elements left in the queue, set FS_FLAG_PROCESSING.
+        if (m_queue.count > 0)
+        {
+           m_flags |= FS_FLAG_PROCESSING;
+        }
+    }
+
+    // Resume processing the queue, if necessary.
+    queue_process();
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.h
new file mode 100644
index 0000000000..718406abf0
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage.h
@@ -0,0 +1,262 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef FSTORAGE_H__
+#define FSTORAGE_H__
+
+/**
+ * @defgroup fstorage fstorage
+ * @ingroup app_common
+ * @{
+ *
+ * @brief   Module which provides functionality to store data to flash and erase flash pages.
+ */
+
+#include <stdint.h>
+#include "section_vars.h"
+
+
+/**@brief   fstorage return values. */
+typedef enum
+{
+    FS_SUCCESS,
+    FS_ERR_NOT_INITIALIZED,     //!< Error. The module is not initialized.
+    FS_ERR_INVALID_CFG,         //!< Error. Invalid fstorage configuration.
+    FS_ERR_NULL_ARG,            //!< Error. Argument is NULL.
+    FS_ERR_INVALID_ARG,         //!< Error. Argument contains invalid data.
+    FS_ERR_INVALID_ADDR,        //!< Error. Address out of bounds.
+    FS_ERR_UNALIGNED_ADDR,      //!< Error. Unaligned address.
+    FS_ERR_QUEUE_FULL,          //!< Error. Queue is full.
+    FS_ERR_OPERATION_TIMEOUT,   //!< Error. The operation has timed out.
+    FS_ERR_INTERNAL,            //!< Error. Internal error.
+} fs_ret_t;
+
+
+/**@brief   fstorage event IDs. */
+typedef enum
+{
+    FS_EVT_STORE,   //!< Event for @ref fs_store.
+    FS_EVT_ERASE    //!< Event for @ref fs_erase.
+} fs_evt_id_t;
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+/**@brief   An fstorage event. */
+typedef struct
+{
+    fs_evt_id_t id;                         //!< The event ID.
+    union
+    {
+        struct
+        {
+            uint32_t const * p_data;        //!< Pointer to the data stored in flash.
+            uint16_t         length_words;  //!< Length of the data, in 4-byte words.
+        } store;
+        struct
+        {
+            uint16_t first_page;            //!< First page erased.
+            uint16_t last_page;             //!< Last page erased.
+        } erase;
+    };
+} fs_evt_t;
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  /* leave anonymous unions enabled */
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#endif
+
+
+/**@brief   fstorage event handler function prototype.
+ *
+ * @param[in]   evt     The event.
+ * @param[in]   result  The result of the operation.
+ */
+typedef void (*fs_cb_t)(fs_evt_t const * const evt, fs_ret_t result);
+
+
+/**@brief   fstorage application-specific configuration.
+ *
+ * @details Specifies the callback to invoke when an operation completes, the number of flash pages
+ *          requested by the application and the priority with which these are to be assigned, with
+ *          respect to other applications. Additionally, the configuration specifies the boundaries
+ *          of the flash space assigned to an application. The configuration must be provided as an
+ *          argument when invoking @ref fs_store and @ref fs_erase.
+ *
+ * @note    The fields @p p_start_addr and @p p_end_address are set by @ref fs_init, based on the
+ *          value of the field @p priority.
+ */
+typedef struct
+{
+    /**@brief   The beginning of the flash space assigned to the application which registered this
+     *          configuration. This field is set by @ref fs_init.
+     */
+    uint32_t const * p_start_addr;
+
+    /**@brief   The end of the flash space assigned to the application which registered this
+     *          configuration. This field is set by @ref fs_init.
+     */
+    uint32_t const * p_end_addr;
+
+    fs_cb_t  const   callback;    //!< Callback to run when a flash operation has completed.
+    uint8_t  const   num_pages;   //!< The number of flash pages requested.
+
+    /**@brief   The priority with which fstorage should assign flash pages to this application,
+     *          with respect to other applications. Applications with higher priority will be
+     *          assigned flash pages with a higher memory address. The highest priority is
+     *          reserved. Must be unique among configurations.
+     */
+    uint8_t  const   priority;
+} fs_config_t;
+
+
+/**@brief   Macro for registering with an fstorage configuration.
+ *          Applications which use fstorage must register with the module using this macro.
+ *          Registering involves defining a variable which holds the configuration of fstorage
+ *          specific to the application which invokes the macro.
+ *
+ * @details This macro places the configuration variable in a section named "fs_data" that
+ *          fstorage uses during initialization and regular operation.
+ *
+ * @param[in]   cfg_var     A @e definition of a @ref fs_config_t variable.
+ */
+#define FS_REGISTER_CFG(cfg_var) NRF_SECTION_VARS_ADD(fs_data, cfg_var)
+
+
+/**@brief   Function for initializing the module.
+ *
+ * @details This functions assigns pages in flash according to all registered configurations.
+ *
+ * @retval  FS_SUCCESS    If the module was successfully initialized.
+ */
+fs_ret_t fs_init(void);
+
+
+/**@brief   Function for storing data in flash.
+ *
+ * @details Copies @p length_words words from @p p_src to the location pointed by @p p_dest.
+ *          If the length of the data exceeds @ref FS_MAX_WRITE_SIZE_WORDS, the data will be
+ *          written down in several chunks, as necessary. Only one event will be sent to the
+ *          application upon completion. Both the source and the destination of the data must be
+ *          word aligned. This function is asynchronous, completion is reported via an event sent
+ *          the the callback function specified in the supplied configuration.
+ *
+ * @warning The data to be written to flash has to be kept in memory until the operation has
+ *          terminated, i.e., an event is received.
+ *
+ * @param[in]   p_config        fstorage configuration registered by the application.
+ * @param[in]   p_dest          The address in flash memory where to store the data.
+ * @param[in]   p_src           Pointer to the data to store in flash.
+ * @param[in]   length_words    Length of the data to store, in words.
+ *
+ * @retval  FS_SUCCESS              If the operation was queued successfully.
+ * @retval  FS_ERR_NOT_INITIALIZED  If the module is not initialized.
+ * @retval  FS_ERR_INVALID_CFG      If @p p_config is NULL or contains invalid data.
+ * @retval  FS_ERR_NULL_ARG         If @p p_dest or @p p_src are NULL.
+ * @retval  FS_ERR_INVALID_ARG      If @p length_words is zero.
+ * @retval  FS_ERR_INVALID_ADDR     If @p p_dest or @p p_src are outside of the flash memory
+ *                                  boundaries specified in @p p_config.
+ * @retval  FS_ERR_UNALIGNED_ADDR   If @p p_dest or @p p_src are not aligned to a word boundary.
+ * @retval  FS_ERR_QUEUE_FULL       If the internal operation queue is full.
+ */
+fs_ret_t fs_store(fs_config_t const * const p_config,
+                  uint32_t    const * const p_dest,
+                  uint32_t    const * const p_src,
+                  uint16_t                  length_words);
+
+
+/**@brief   Function for erasing flash pages.
+ *
+ * @details Starting from the page at @p p_page_addr, erases @p num_pages flash pages.
+ *          @p p_page_addr must be aligned to a page boundary. All pages to be erased must be
+ *          within the bounds specified in the supplied fstorage configuration.
+ *          This function is asynchronous. Completion is reported via an event.
+ *
+ * @param[in]   p_config        fstorage configuration registered by the application.
+ * @param[in]   p_page_addr     Address of the page to erase. Must be aligned to a page boundary.
+ * @param[in]   num_pages       Number of pages to erase. May not be zero.
+ *
+ * @retval  FS_SUCCESS              If the operation was queued successfully.
+ * @retval  FS_ERR_NOT_INITIALIZED  If the module is not initialized.
+ * @retval  FS_ERR_INVALID_CFG      If @p p_config is NULL or contains invalid data.
+ * @retval  FS_ERR_NULL_ARG         If @p p_page_addr is NULL.
+ * @retval  FS_ERR_INVALID_ARG      If @p num_pages is zero.
+ * @retval  FS_ERR_INVALID_ADDR     If the operation would go beyond the flash memory boundaries
+ *                                  specified in @p p_config.
+ * @retval  FS_ERR_UNALIGNED_ADDR   If @p p_page_addr is not aligned to a page boundary.
+ * @retval  FS_ERR_QUEUE_FULL       If the internal operation queue is full.
+ */
+fs_ret_t fs_erase(fs_config_t const * const p_config,
+                  uint32_t    const * const p_page_addr,
+                  uint16_t                  num_pages);
+
+
+/**@brief Function for retrieving the number of queued flash operations.
+ *
+ * @param[out]  p_op_count    The number of queued flash operations.
+ *
+ * @retval  FS_SUCCESS          If the number of queued operations was retrieved successfully.
+ * @retval  FS_ERR_NULL_ARG     If @p p_op_count is NULL.
+ */
+fs_ret_t fs_queued_op_count_get(uint32_t * const p_op_count);
+
+
+/**@brief   Function for handling system events from the SoftDevice.
+ *
+ * @details If any of the modules used by the application rely on fstorage, the application should
+ *          dispatch system events to fstorage using this function.
+ *
+ * @param[in]   sys_evt     System event from the SoftDevice.
+ */
+void fs_sys_event_handler(uint32_t sys_evt);
+
+
+/** @} */
+
+#endif // FSTORAGE_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_internal_defs.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_internal_defs.h
new file mode 100644
index 0000000000..8f8e4bbea2
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_internal_defs.h
@@ -0,0 +1,162 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef FSTORAGE_INTERNAL_DEFS_H__
+#define FSTORAGE_INTERNAL_DEFS_H__
+
+#include "nrf.h"
+
+
+#define FS_FLAG_INITIALIZED         (1 << 0)  // The module has been initialized.
+#define FS_FLAG_PROCESSING          (1 << 1)  // The module is processing flash operations.
+// The module is waiting for a flash operation initiated by another module to complete.
+#define FS_FLAG_FLASH_REQ_PENDING   (1 << 2)
+
+#define FS_ERASED_WORD              (0xFFFFFFFF)
+
+// Helper macros for section variables.
+#define FS_SECTION_VARS_GET(i)          NRF_SECTION_VARS_GET((i), fs_config_t, fs_data)
+#define FS_SECTION_VARS_COUNT           NRF_SECTION_VARS_COUNT(fs_config_t, fs_data)
+#define FS_SECTION_VARS_START_ADDR      NRF_SECTION_VARS_START_ADDR(fs_data)
+#define FS_SECTION_VARS_END_ADDR        NRF_SECTION_VARS_END_ADDR(fs_data)
+
+
+// Register the section 'fs_data'.
+//lint -save -e19
+NRF_SECTION_VARS_REGISTER_SECTION(fs_data);
+//lint -restore
+
+// Declare symbols into the 'fs_data' section.
+NRF_SECTION_VARS_REGISTER_SYMBOLS(fs_config_t, fs_data);
+//lint -esym(526,fs_dataBase)
+//lint -esym(526,fs_dataLimit)
+
+
+// fstorage op-codes.
+typedef enum
+{
+    FS_OP_NONE,   // No operation.
+    FS_OP_STORE,  // Store data.
+    FS_OP_ERASE   // Erase one or more flash pages.
+} fs_op_code_t;
+
+
+#if defined(__CC_ARM)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__ICCARM__)
+  #pragma language=extended
+#elif defined(__GNUC__)
+  // anonymous unions are enabled by default.
+#endif
+
+// fstorage operation.
+// Encapsulates details of a flash operation to be executed by this module.
+typedef struct
+{
+    fs_config_t  const * p_config;          // Application-specific fstorage configuration.
+    fs_op_code_t         op_code;           // ID of the operation.
+    union
+    {
+        struct
+        {
+            uint32_t const * p_src;         // Pointer to the data to be written to flash.
+            uint32_t const * p_dest;        // Destination of the data in flash.
+            uint16_t         length_words;  // Length of the data to be written, in words.
+            uint16_t         offset;        // Write offset.
+        } store;
+        struct
+        {
+            uint16_t page;
+            uint16_t pages_erased;
+            uint16_t pages_to_erase;
+        } erase;
+    };
+} fs_op_t;
+
+#if defined(__CC_ARM)
+  #pragma pop
+#elif defined(__ICCARM__)
+  // leave anonymous unions enabled.
+#elif defined(__GNUC__)
+  // anonymous unions are enabled by default.
+#endif
+
+
+// Queue of requested operations.
+// This queue holds flash operations requested to the module.
+// The data to be written to flash must be kept in memory until the write operation
+// is completed, i.e., an event indicating completion is received.
+typedef struct
+{
+    fs_op_t  op[FS_QUEUE_SIZE];  // Queue elements.
+    uint32_t rp;                 // Index of the operation being processed.
+    uint32_t count;              // Number of elements in the queue.
+} fs_op_queue_t;
+
+
+// Size of a flash page in bytes.
+#if   defined (NRF51)
+    #define FS_PAGE_SIZE    (1024)
+#elif defined (NRF52)
+    #define FS_PAGE_SIZE    (4096)
+#endif
+
+
+// Size of a flash page in words.
+#define FS_PAGE_SIZE_WORDS  (FS_PAGE_SIZE / sizeof(uint32_t))
+
+
+// Function to obtain the end of the flash space available to fstorage.
+static uint32_t const * fs_flash_page_end_addr()
+{
+    uint32_t const bootloader_addr = NRF_UICR->NRFFW[0];
+
+    return  (uint32_t*)((bootloader_addr != FS_ERASED_WORD) ? bootloader_addr :
+                                                              NRF_FICR->CODESIZE * FS_PAGE_SIZE);
+}
+
+
+// Macro to obtain the address of the last page.
+// If there is a bootloader present the bootloader address read from UICR
+// will act as the page beyond the end of the available flash storage.
+#define FS_PAGE_END_ADDR    (fs_flash_page_end_addr())
+
+
+#endif //__FSTORAGE_INTERNAL_DEFS_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_nosd.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/fstorage/fstorage_nosd.c
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_mem_pool_internal.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_mem_pool_internal.h
new file mode 100644
index 0000000000..92594915ac
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_mem_pool_internal.h
@@ -0,0 +1,59 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/** @file
+ *
+ * @defgroup memory_pool_internal Memory Pool Internal
+ * @{
+ * @ingroup memory_pool
+ *
+ * @brief Memory pool internal definitions
+ */
+ 
+#ifndef MEM_POOL_INTERNAL_H__
+#define MEM_POOL_INTERNAL_H__
+
+#define TX_BUF_SIZE       600u         /**< TX buffer size in bytes. */
+#define RX_BUF_SIZE       TX_BUF_SIZE  /**< RX buffer size in bytes. */
+
+#define RX_BUF_QUEUE_SIZE 4u           /**< RX buffer element size. */
+
+#endif // MEM_POOL_INTERNAL_H__
+ 
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_transport_config.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_transport_config.h
new file mode 100644
index 0000000000..fdff490056
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/config/hci_transport_config.h
@@ -0,0 +1,67 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @brief Definition of HCI Transport Layer configurable parameters
+ */
+
+#ifndef HCI_TRANSPORT_CFG_H__
+#define HCI_TRANSPORT_CFG_H__
+
+/** This section covers configurable parameters for the HCI Transport SLIP layer. */
+#define HCI_SLIP_UART_RX_PIN_NUMBER  1                      /**< Defines the UART RX pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_TX_PIN_NUMBER  2                      /**< Defines the UART TX pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_RTS_PIN_NUMBER 3                     /**< Defines the UART RTS pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_CTS_PIN_NUMBER 4                     /**< Defines the UART CTS pin number. The default pin for the board is chosen, but can be overwritten. */
+
+#define HCI_SLIP_UART_MODE           APP_UART_FLOW_CONTROL_ENABLED      /**< Defines the UART mode to be used. Use UART Low Power with Flow Control - Valid values are defined in \ref app_uart_flow_control_t. For further information on the UART Low Power mode, please refer to: \ref app_uart . */
+
+#define HCI_SLIP_UART_BAUDRATE       UART_BAUDRATE_BAUDRATE_Baud38400   /**< Defines the UART Baud rate. Default is 38400 baud. */
+
+/** This section covers configurable parameters for the HCI Transport layer that are used for calculating correct value for the retransmission timer timeout. */
+#define MAX_PACKET_SIZE_IN_BITS      8000u                              /**< Maximum size of a single application packet in bits. */      
+#define USED_BAUD_RATE               38400u                             /**< The used uart baudrate. */
+
+#endif // HCI_TRANSPORT_CFG_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.c
new file mode 100644
index 0000000000..cefb91eb2f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.c
@@ -0,0 +1,262 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+#include "hci_mem_pool.h"
+#include "hci_mem_pool_internal.h"
+#include <stdbool.h>
+#include <stdio.h>
+
+/**@brief RX buffer element instance structure. 
+ */
+typedef struct 
+{
+    uint8_t  rx_buffer[RX_BUF_SIZE];                                /**< RX buffer memory array. */  
+    uint32_t length;                                                /**< Length of the RX buffer memory array. */
+} rx_buffer_elem_t;
+
+/**@brief RX buffer queue element instance structure. 
+ */
+typedef struct 
+{
+    rx_buffer_elem_t * p_buffer;                                    /**< Pointer to RX buffer element. */
+    uint32_t           free_window_count;                           /**< Free space element count. */
+    uint32_t           free_available_count;                        /**< Free area element count. */
+    uint32_t           read_available_count;                        /**< Read area element count. */
+    uint32_t           write_index;                                 /**< Write position index. */                                      
+    uint32_t           read_index;                                  /**< Read position index. */                                                                            
+    uint32_t           free_index;                                  /**< Free position index. */                                                                                                                  
+} rx_buffer_queue_t;
+
+static bool              m_is_tx_allocated;                         /**< Boolean value to determine if the TX buffer is allocated. */
+static rx_buffer_elem_t  m_rx_buffer_elem_queue[RX_BUF_QUEUE_SIZE]; /**< RX buffer element instances. */
+static rx_buffer_queue_t m_rx_buffer_queue;                         /**< RX buffer queue element instance. */
+
+
+uint32_t hci_mem_pool_open(void)
+{
+    m_is_tx_allocated                      = false;    
+    m_rx_buffer_queue.p_buffer             = m_rx_buffer_elem_queue;
+    m_rx_buffer_queue.free_window_count    = RX_BUF_QUEUE_SIZE;
+    m_rx_buffer_queue.free_available_count = 0;
+    m_rx_buffer_queue.read_available_count = 0;
+    m_rx_buffer_queue.write_index          = 0;    
+    m_rx_buffer_queue.read_index           = 0;        
+    m_rx_buffer_queue.free_index           = 0;            
+    
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_close(void)
+{    
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer)
+{
+    static uint8_t tx_buffer[TX_BUF_SIZE];  
+
+    uint32_t err_code;
+    
+    if (pp_buffer == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }
+    
+    if (!m_is_tx_allocated)
+    {        
+            m_is_tx_allocated = true;
+            *pp_buffer        = tx_buffer;
+            err_code          = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code              = NRF_ERROR_NO_MEM;
+    }
+    
+    return err_code;
+}
+
+
+uint32_t hci_mem_pool_tx_free(void)
+{
+    m_is_tx_allocated = false;
+    
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer)
+{
+    uint32_t err_code; 
+
+    if (pp_buffer == NULL)
+    {
+        return NRF_ERROR_NULL;
+    }    
+    *pp_buffer = NULL;
+    
+    if (m_rx_buffer_queue.free_window_count != 0)
+    {    
+        if (length <= RX_BUF_SIZE)
+        {    
+            --(m_rx_buffer_queue.free_window_count);            
+            ++(m_rx_buffer_queue.read_available_count);            
+
+            *pp_buffer                    = 
+                    m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.write_index].rx_buffer;
+
+            m_rx_buffer_queue.free_index |= (1u << m_rx_buffer_queue.write_index);
+
+            // @note: Adjust the write_index making use of the fact that the buffer size is of 
+            // power of two and two's complement arithmetic. For details refer example to book 
+            // "Making embedded systems: Elicia White".
+            m_rx_buffer_queue.write_index = 
+                    (m_rx_buffer_queue.write_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+            
+            err_code                      = NRF_SUCCESS;
+        }
+        else
+        {
+            err_code = NRF_ERROR_DATA_SIZE;    
+        }        
+    }
+    else
+    {
+        err_code = NRF_ERROR_NO_MEM;    
+    }
+    
+    return err_code;
+}
+
+
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer)
+{
+    uint32_t err_code;
+    uint32_t consume_index;
+    uint32_t start_index;
+    
+    if (m_rx_buffer_queue.free_available_count != 0)
+    {
+        // Find the buffer that has been freed -
+        // Start at read_index minus free_available_count and then increment until read index.
+        err_code      = NRF_ERROR_INVALID_ADDR;
+        consume_index = (m_rx_buffer_queue.read_index - m_rx_buffer_queue.free_available_count) & 
+                        (RX_BUF_QUEUE_SIZE - 1u);
+        start_index   = consume_index;
+        
+        do
+        {
+            if (m_rx_buffer_queue.p_buffer[consume_index].rx_buffer == p_buffer)
+            {
+                m_rx_buffer_queue.free_index ^= (1u << consume_index);
+                err_code = NRF_SUCCESS;
+                break;
+            }
+            else
+            {
+                consume_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+            }
+        }
+        while (consume_index != m_rx_buffer_queue.read_index);
+
+        while (!(m_rx_buffer_queue.free_index & (1 << start_index)) && 
+                (m_rx_buffer_queue.free_available_count != 0))
+        {
+            --(m_rx_buffer_queue.free_available_count);
+            ++(m_rx_buffer_queue.free_window_count);            
+            start_index = (consume_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_NO_MEM;
+    }
+        
+    return err_code;    
+}
+
+
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length)
+{
+    // @note: Adjust the write_index making use of the fact that the buffer size is of power
+    // of two and two's complement arithmetic. For details refer example to book 
+    // "Making embedded systems: Elicia White".
+    const uint32_t index = (m_rx_buffer_queue.write_index - 1u) & (RX_BUF_QUEUE_SIZE - 1u);
+    m_rx_buffer_queue.p_buffer[index].length = length;    
+    
+    return NRF_SUCCESS;
+}
+
+
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length)
+{
+    uint32_t err_code;
+    
+    if ((pp_buffer == NULL) || (p_length == NULL))
+    {
+        return NRF_ERROR_NULL;
+    }
+    
+    if (m_rx_buffer_queue.read_available_count != 0)
+    {
+        --(m_rx_buffer_queue.read_available_count);
+        ++(m_rx_buffer_queue.free_available_count);        
+        
+        *pp_buffer                   = 
+            m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].rx_buffer;
+        *p_length                    = 
+            m_rx_buffer_queue.p_buffer[m_rx_buffer_queue.read_index].length;
+        
+        // @note: Adjust the write_index making use of the fact that the buffer size is of power
+        // of two and two's complement arithmetic. For details refer example to book 
+        // "Making embedded systems: Elicia White".            
+        m_rx_buffer_queue.read_index = 
+            (m_rx_buffer_queue.read_index + 1u) & (RX_BUF_QUEUE_SIZE - 1u); 
+        
+        err_code                     = NRF_SUCCESS;
+    }
+    else
+    {
+        err_code                     = NRF_ERROR_NO_MEM;        
+    }
+    
+    return err_code;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.h
new file mode 100644
index 0000000000..e4f7358b8f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/hci/hci_mem_pool.h
@@ -0,0 +1,159 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+ 
+/** @file
+ *
+ * @defgroup memory_pool Memory pool
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Memory pool implementation
+ *
+ * Memory pool implementation, based on circular buffer data structure, which supports asynchronous 
+ * processing of RX data. The current default implementation supports 1 TX buffer and 4 RX buffers.
+ * The memory managed by the pool is allocated from static storage instead of heap. The internal 
+ * design of the circular buffer implementing the RX memory layout is illustrated in the picture 
+ * below. 
+ *
+ * @image html memory_pool.png "Circular buffer design"
+ *
+ * The expected call order for the RX APIs is as follows:
+ * - hci_mem_pool_rx_produce
+ * - hci_mem_pool_rx_data_size_set
+ * - hci_mem_pool_rx_extract
+ * - hci_mem_pool_rx_consume
+ *
+ * @warning If the above mentioned expected call order is violated the end result can be undefined.
+ *
+ * \par Component specific configuration options
+ *
+ * The following compile time configuration options are available to suit various implementations:
+ * - TX_BUF_SIZE TX buffer size in bytes. 
+ * - RX_BUF_SIZE RX buffer size in bytes. 
+ * - RX_BUF_QUEUE_SIZE RX buffer element size.
+ */
+ 
+#ifndef HCI_MEM_POOL_H__
+#define HCI_MEM_POOL_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**@brief Function for opening the module.
+ *
+ * @retval NRF_SUCCESS          Operation success. 
+ */
+uint32_t hci_mem_pool_open(void);
+
+/**@brief Function for closing the module.
+ *
+ * @retval NRF_SUCCESS          Operation success. 
+ */
+uint32_t hci_mem_pool_close(void);
+
+/**@brief Function for allocating requested amount of TX memory.
+ *
+ * @param[out] pp_buffer        Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS          Operation success. Memory was allocated.
+ * @retval NRF_ERROR_NO_MEM     Operation failure. No memory available for allocation.
+ * @retval NRF_ERROR_NULL       Operation failure. NULL pointer supplied.  
+ */
+uint32_t hci_mem_pool_tx_alloc(void ** pp_buffer);
+ 
+/**@brief Function for freeing previously allocated TX memory.
+ *
+ * @note Memory management follows the FIFO principle meaning that free() order must match the 
+ *       alloc(...) order, which is the reason for omitting exact memory block identifier as an 
+ *       input parameter.
+ *
+ * @retval NRF_SUCCESS          Operation success. Memory was freed.
+ */
+uint32_t hci_mem_pool_tx_free(void);
+ 
+/**@brief Function for producing a free RX memory block for usage.
+ *
+ * @note Upon produce request amount being 0, NRF_SUCCESS is returned.   
+ *
+ * @param[in]  length           Amount, in bytes, of free memory to be produced.
+ * @param[out] pp_buffer        Pointer to the allocated memory.
+ *
+ * @retval NRF_SUCCESS          Operation success. Free RX memory block produced.
+ * @retval NRF_ERROR_NO_MEM     Operation failure. No suitable memory available for allocation.
+ * @retval NRF_ERROR_DATA_SIZE  Operation failure. Request size exceeds limit.  
+ * @retval NRF_ERROR_NULL       Operation failure. NULL pointer supplied.   
+ */
+uint32_t hci_mem_pool_rx_produce(uint32_t length, void ** pp_buffer);
+
+/**@brief Function for setting the length of the last produced RX memory block.
+ *
+ * @warning If call to this API is omitted the end result is that the following call to 
+ *          mem_pool_rx_extract will return incorrect data in the p_length output parameter.
+ *
+ * @param[in]  length           Amount, in bytes, of actual memory used.
+ *
+ * @retval NRF_SUCCESS          Operation success. Length was set.
+ */
+uint32_t hci_mem_pool_rx_data_size_set(uint32_t length);
+ 
+/**@brief Function for extracting a packet, which has been filled with read data, for further 
+ * processing.
+ *
+ * @param[out] pp_buffer        Pointer to the packet data.
+ * @param[out] p_length         Length of packet data in bytes.  
+ *
+ * @retval NRF_SUCCESS          Operation success. 
+ * @retval NRF_ERROR_NO_MEM     Operation failure. No packet available to extract.
+ * @retval NRF_ERROR_NULL       Operation failure. NULL pointer supplied.    
+ */
+uint32_t hci_mem_pool_rx_extract(uint8_t ** pp_buffer, uint32_t * p_length);
+ 
+/**@brief Function for freeing previously extracted packet, which has been filled with read data.
+ *
+ * @param[in] p_buffer             Pointer to consumed buffer.
+ *
+ * @retval NRF_SUCCESS             Operation success. 
+ * @retval NRF_ERROR_NO_MEM        Operation failure. No packet available to free. 
+ * @retval NRF_ERROR_INVALID_ADDR  Operation failure. Not a valid pointer. 
+ */
+uint32_t hci_mem_pool_rx_consume(uint8_t * p_buffer);
+ 
+#endif // HCI_MEM_POOL_H__
+ 
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c
new file mode 100644
index 0000000000..83ad686cbb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.c
@@ -0,0 +1,903 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "app_pwm.h"
+#include "nrf_drv_timer.h"
+#include "nrf_drv_ppi.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_gpiote.h"
+#include "nrf_gpiote.h"
+#include "nrf_gpio.h"
+#include "app_util.h"
+#include "app_util_platform.h"
+#include "nrf_assert.h"
+
+#define APP_PWM_CHANNEL_INITIALIZED                1
+#define APP_PWM_CHANNEL_UNINITIALIZED              0
+
+#define APP_PWM_CHANNEL_ENABLED                    1
+#define APP_PWM_CHANNEL_DISABLED                   0
+
+#define TIMER_PRESCALER_MAX                        9
+#define TIMER_MAX_PULSEWIDTH_US_ON_16M             4095
+
+#define APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE 2
+#define APP_PWM_REQUIRED_PPI_CHANNELS_PER_CHANNEL  2
+
+#define UNALLOCATED                                0xFFFFFFFFUL
+#define BUSY_STATE_CHANGING                        0xFE
+#define BUSY_STATE_IDLE                            0xFF
+
+#define PWM_MAIN_CC_CHANNEL                        2
+#define PWM_SECONDARY_CC_CHANNEL                   3
+
+#ifdef NRF52
+    static bool m_use_ppi_delay_workaround;
+#endif
+
+
+/**
+ * @brief PWM busy status
+ *
+ * Stores the number of a channel being currently updated.
+ *
+ */
+static volatile uint8_t  m_pwm_busy[TIMER_COUNT];
+
+
+/**
+ * @brief New duty cycle value
+ *
+ * When the channel duty cycle reaches this value, the update process is complete.
+ */
+static volatile uint32_t m_pwm_target_value[TIMER_COUNT];
+
+
+/**
+ * @brief PWM ready counter
+ *
+ * The value in this counter is decremented in every PWM cycle after initiating the update.
+ * If an event handler function was specified by the user, it is being called
+ * after two cycle events (at least one full PWM cycle).
+ */
+volatile uint8_t m_pwm_ready_counter[TIMER_COUNT][APP_PWM_CHANNELS_PER_INSTANCE];
+
+/**
+ * @brief Pointers to instances
+ *
+ * This array connects any active timer instance number with the pointer to the PWM instance.
+ * It is used by the interrupt runtime.
+ */
+static const app_pwm_t * m_instances[TIMER_COUNT];
+
+// Macros for getting the polarity of given instance/channel.
+#define POLARITY_ACTIVE(INST,CH)   (( ((INST)->p_cb)->channels_cb[(CH)].polarity == \
+                 APP_PWM_POLARITY_ACTIVE_LOW)?(0):(1))
+#define POLARITY_INACTIVE(INST,CH) (( ((INST)->p_cb)->channels_cb[(CH)].polarity == \
+                 APP_PWM_POLARITY_ACTIVE_LOW)?(1):(0))
+
+//lint -save -e534
+
+/**
+ * @brief Workaround for PAN-73.
+ *
+ * @param[in] timer     Timer.
+ * @param[in] enable    Enable or disable.
+ */
+static void pan73_workaround(NRF_TIMER_Type * p_timer, bool enable)
+{
+#ifdef NRF51
+    if (p_timer == NRF_TIMER0)
+    {
+        *(uint32_t *)0x40008C0C = (enable ? 1 : 0);
+    }
+    else if (p_timer == NRF_TIMER1)
+    {
+        *(uint32_t *)0x40009C0C = (enable ? 1 : 0);
+    }
+    else if (p_timer == NRF_TIMER2)
+    {
+        *(uint32_t *)0x4000AC0C = (enable ? 1 : 0);
+    }
+#endif
+    return;
+}
+
+bool app_pwm_busy_check(app_pwm_t const * const p_instance)
+{
+    uint8_t busy_state = (m_pwm_busy[p_instance->p_timer->instance_id]);
+    bool busy = true;
+    if (busy_state != BUSY_STATE_IDLE)
+    {
+        if (busy_state != BUSY_STATE_CHANGING)
+        {
+            if (nrf_drv_timer_capture_get(p_instance->p_timer, (nrf_timer_cc_channel_t) busy_state) 
+                == m_pwm_target_value[p_instance->p_timer->instance_id])
+            {
+                m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+                busy = false;
+            }
+        }
+    }
+    else
+    {
+        busy = false;
+    }
+    return busy;
+}
+
+
+/**
+ * @brief Function for enabling the IRQ for a given PWM instance.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_irq_enable(app_pwm_t const * const p_instance)
+{
+    nrf_drv_timer_compare_int_enable(p_instance->p_timer, PWM_MAIN_CC_CHANNEL);
+}
+
+
+/**
+ * @brief Function for disabling the IRQ for a given PWM instance.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_irq_disable(app_pwm_t const * const p_instance)
+{
+    nrf_drv_timer_compare_int_disable(p_instance->p_timer, PWM_MAIN_CC_CHANNEL);
+}
+
+
+/**
+ * @brief Function for disabling PWM channel PPI.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_channel_ppi_disable(app_pwm_t const * const p_instance, uint8_t channel)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    nrf_drv_ppi_channel_disable(p_cb->channels_cb[channel].ppi_channels[0]);
+    nrf_drv_ppi_channel_disable(p_cb->channels_cb[channel].ppi_channels[1]);
+}
+
+
+/**
+ * @brief Function for disabling PWM PPI.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+__STATIC_INLINE void pwm_ppi_disable(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    nrf_drv_ppi_channel_disable(p_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_disable(p_cb->ppi_channels[1]);
+}
+
+
+/**
+ * @brief This function is called on interrupt after duty set.
+ *
+ * @param[in] timer                 Timer used by PWM.
+ * @param[in] timer_instance_id     Timer index.
+ */
+void pwm_ready_tick(nrf_timer_event_t event_type, void * p_context)
+{
+    uint32_t timer_instance_id = (uint32_t)p_context;
+    uint8_t disable = 1;
+    
+    for (uint8_t channel = 0; channel < APP_PWM_CHANNELS_PER_INSTANCE; ++channel)
+    {
+        if (m_pwm_ready_counter[timer_instance_id][channel])
+        {
+            --m_pwm_ready_counter[timer_instance_id][channel];
+            if (!m_pwm_ready_counter[timer_instance_id][channel])
+            {
+                app_pwm_cb_t * p_cb = m_instances[timer_instance_id]->p_cb;
+                p_cb->p_ready_callback(timer_instance_id);
+            }
+            else
+            {
+                disable = 0;
+            }
+        }
+    }
+    
+    if (disable)
+    {
+        pwm_irq_disable(m_instances[timer_instance_id]);
+    }
+}
+
+
+/**
+ * @brief Function for resource de-allocation.
+ *
+ * @param[in] p_instance       PWM instance.
+ */
+//lint -e{650}
+static void pwm_dealloc(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE; ++i)
+    {
+        if (p_cb->ppi_channels[i] != (nrf_ppi_channel_t)(uint8_t)(UNALLOCATED))
+        {
+            nrf_drv_ppi_channel_free(p_cb->ppi_channels[i]);
+        }
+    }
+    if (p_cb->ppi_group != (nrf_ppi_channel_group_t)UNALLOCATED)
+    {
+        nrf_drv_ppi_group_free(p_cb->ppi_group);
+    }
+
+    for (uint8_t ch = 0; ch < APP_PWM_CHANNELS_PER_INSTANCE; ++ch)
+    {
+        for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_CHANNEL; ++i)
+        {
+            if (p_cb->channels_cb[ch].ppi_channels[i] != (nrf_ppi_channel_t)UNALLOCATED)
+            {
+                nrf_drv_ppi_channel_free(p_cb->channels_cb[ch].ppi_channels[i]);
+                p_cb->channels_cb[ch].ppi_channels[i] = (nrf_ppi_channel_t)UNALLOCATED;
+            }
+        }
+        if (p_cb->channels_cb[ch].gpio_pin != UNALLOCATED)
+        {
+            nrf_drv_gpiote_out_uninit(p_cb->channels_cb[ch].gpio_pin);
+            p_cb->channels_cb[ch].gpio_pin = UNALLOCATED;
+        }
+        p_cb->channels_cb[ch].initialized = APP_PWM_CHANNEL_UNINITIALIZED;
+    }
+    nrf_drv_timer_uninit(p_instance->p_timer);
+    return;
+}
+
+
+/**
+ * @brief PWM state transition from (0%, 100%) to 0% or 100%.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_n_to_0or100(app_pwm_t const * const p_instance,
+                                       uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb     = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb  = &p_cb->channels_cb[channel];
+    nrf_ppi_channel_group_t   p_ppigrp = p_cb->ppi_group;
+
+    pwm_ppi_disable(p_instance);
+    nrf_drv_ppi_group_clear(p_ppigrp);
+    nrf_drv_ppi_channels_include_in_group(
+            nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[0]) | 
+            nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[1]),
+            p_ppigrp);
+
+    if (!ticks)
+    {
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_ppi_task_addr_group_disable_get(p_ppigrp));
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 0, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] =
+            nrf_drv_timer_capture_get(p_instance->p_timer, (nrf_timer_cc_channel_t) channel);
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+    }
+    else
+    {
+        ticks = p_cb->period;
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_ppi_task_addr_group_disable_get(p_ppigrp));
+        // Set secondary CC channel to non-zero value:
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 1, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] = 0;
+        // The captured value will be equal to 0, because timer clear on main PWM CC channel compare is enabled.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+    }
+    
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[1]);
+    
+    p_ch_cb->pulsewidth = ticks;
+    m_pwm_busy[p_instance->p_timer->instance_id] = PWM_SECONDARY_CC_CHANNEL;
+}
+
+
+/**
+ * @brief PWM state transition from (0%, 100%) to (0%, 100%).
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_n_to_m(app_pwm_t const * const p_instance,
+                                  uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb     = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb  = &p_cb->channels_cb[channel];
+    nrf_ppi_channel_group_t   p_ppigrp = p_cb->ppi_group;
+
+    pwm_ppi_disable(p_instance);
+    nrf_drv_ppi_group_clear(p_ppigrp);
+    nrf_drv_ppi_channels_include_in_group(
+        nrf_drv_ppi_channel_to_mask(p_cb->ppi_channels[0]) | 
+        nrf_drv_ppi_channel_to_mask(p_cb->ppi_channels[1]),
+        p_ppigrp);
+
+    nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL),
+                nrf_drv_timer_capture_task_address_get(p_instance->p_timer, channel));
+
+#ifdef NRF52
+    if (ticks + ((nrf_timer_frequency_get(p_instance->p_timer->p_reg) == 
+        (m_use_ppi_delay_workaround ? NRF_TIMER_FREQ_8MHz : NRF_TIMER_FREQ_16MHz) ) ? 1 : 0)
+        < p_ch_cb->pulsewidth)
+#else
+    if (ticks + ((nrf_timer_frequency_get(p_instance->p_timer->p_reg) == NRF_TIMER_FREQ_16MHz) ? 1 : 0)
+        < p_ch_cb->pulsewidth)
+#endif
+    {
+        // For lower value, we need one more transition. Timer task delay is included.
+        // If prescaler is disabled, one tick must be added because of 1 PCLK16M clock cycle delay.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL),
+                nrf_drv_gpiote_out_task_addr_get(p_ch_cb->gpio_pin));
+    }
+    else
+    {
+        nrf_drv_ppi_channel_remove_from_group(p_cb->ppi_channels[1], p_ppigrp);
+    }
+    p_ch_cb->pulsewidth = ticks;
+    nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, ticks, false);
+    nrf_drv_ppi_group_enable(p_ppigrp);
+    
+    m_pwm_target_value[p_instance->p_timer->instance_id] = ticks;
+    m_pwm_busy[p_instance->p_timer->instance_id] = channel;
+}
+
+
+/**
+ * @brief PWM state transition from 0% or 100% to (0%, 100%).
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_0or100_to_n(app_pwm_t const * const p_instance,
+                                       uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t            * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t    * p_ch_cb   = &p_cb->channels_cb[channel];
+    nrf_ppi_channel_group_t   p_ppigrp  = p_cb->ppi_group;
+    nrf_timer_cc_channel_t    pwm_ch_cc = (nrf_timer_cc_channel_t)(channel);
+
+    pwm_ppi_disable(p_instance);
+    pwm_channel_ppi_disable(p_instance, channel);
+
+    nrf_drv_timer_compare(p_instance->p_timer, pwm_ch_cc, ticks, false);
+    nrf_drv_ppi_group_clear(p_ppigrp);
+    nrf_drv_ppi_channels_include_in_group(
+        nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[0])|
+        nrf_drv_ppi_channel_to_mask(p_ch_cb->ppi_channels[1]),
+        p_ppigrp);
+
+    if (!p_ch_cb->pulsewidth)
+    {
+        // Channel is at 0%.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_ppi_task_addr_group_enable_get(p_ppigrp));
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 0, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] = 
+            nrf_drv_timer_capture_get(p_instance->p_timer, (nrf_timer_cc_channel_t) channel);
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+       
+    }
+    else
+    {
+        // Channel is at 100%.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[0],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_ppi_task_addr_group_enable_get(p_ppigrp));
+        // Set secondary CC channel to non-zero value:
+        nrf_drv_timer_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_SECONDARY_CC_CHANNEL, 1, false);
+        m_pwm_target_value[p_instance->p_timer->instance_id] = 0;
+        // The captured value will be equal to 0, because timer clear on main PWM CC channel compare is enabled.
+        nrf_drv_ppi_channel_assign(p_cb->ppi_channels[1],
+                    nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                    nrf_drv_timer_capture_task_address_get(p_instance->p_timer, PWM_SECONDARY_CC_CHANNEL));
+    }
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_enable(p_cb->ppi_channels[1]);
+    
+    p_ch_cb->pulsewidth = ticks;
+    m_pwm_busy[p_instance->p_timer->instance_id] = PWM_SECONDARY_CC_CHANNEL;
+}
+
+
+/**
+ * @brief PWM state transition from 0% or 100% to 0% or 100%.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          PWM channel number.
+ * @param[in] ticks            Number of clock ticks.
+ */
+static void pwm_transition_0or100_to_0or100(app_pwm_t const * const p_instance,
+                                            uint8_t channel, uint16_t ticks)
+{
+    app_pwm_cb_t         * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb   = &p_cb->channels_cb[channel];
+    nrf_timer_cc_channel_t pwm_ch_cc = (nrf_timer_cc_channel_t)(channel);
+
+    pwm_ppi_disable(p_instance);
+    pwm_channel_ppi_disable(p_instance, channel);
+    if (!ticks)
+    {
+        // Set to 0%.
+        nrf_drv_gpiote_out_task_force(p_ch_cb->gpio_pin, POLARITY_INACTIVE(p_instance, channel));
+    }
+    else if (ticks >= p_cb->period)
+    {
+        // Set to 100%.
+        ticks = p_cb->period;
+        nrf_drv_gpiote_out_task_force(p_ch_cb->gpio_pin, POLARITY_ACTIVE(p_instance, channel));
+    }
+    nrf_drv_timer_compare(p_instance->p_timer, pwm_ch_cc, ticks, false);
+    p_ch_cb->pulsewidth = ticks;
+    
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    return;
+}
+
+
+ret_code_t app_pwm_channel_duty_ticks_set(app_pwm_t const * const p_instance,
+                                          uint8_t           channel,
+                                          uint16_t          ticks)
+{
+    app_pwm_cb_t         * p_cb    = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb = &p_cb->channels_cb[channel];
+
+    ASSERT(channel < APP_PWM_CHANNELS_PER_INSTANCE);
+    ASSERT(p_ch_cb->initialized == APP_PWM_CHANNEL_INITIALIZED);
+
+    if (p_cb->state != NRF_DRV_STATE_POWERED_ON)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    if (ticks == p_ch_cb->pulsewidth)
+    {
+        if (p_cb->p_ready_callback)
+        {
+            p_cb->p_ready_callback(p_instance->p_timer->instance_id);
+        }
+        return NRF_SUCCESS;     // No action required.
+    }
+    if (app_pwm_busy_check(p_instance))
+    {
+        return NRF_ERROR_BUSY;  // PPI channels for synchronization are still in use.
+    }
+    
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_CHANGING;
+
+    // Pulse width change sequence:
+    if (!p_ch_cb->pulsewidth || p_ch_cb->pulsewidth >= p_cb->period)
+    {
+        // Channel is disabled (0%) or at 100%.
+        if (!ticks || ticks >= p_cb->period)
+        {
+            // Set to 0 or 100%.
+            pwm_transition_0or100_to_0or100(p_instance, channel, ticks);
+        }
+        else
+        {
+            // Other value.
+            pwm_transition_0or100_to_n(p_instance, channel, ticks);
+        }
+    }
+    else
+    {
+        // Channel is at other value.
+        if (!ticks || ticks >= p_cb->period)
+        {
+            // Disable channel (set to 0%) or set to 100%.
+            pwm_transition_n_to_0or100(p_instance, channel, ticks);
+        }
+        else
+        {
+            // Set to any other value.
+            pwm_transition_n_to_m(p_instance, channel, ticks);
+        }
+    }
+    if (p_instance->p_cb->p_ready_callback)
+    {
+        //PWM ready interrupt handler will be called after one full period.
+        m_pwm_ready_counter[p_instance->p_timer->instance_id][channel] = 2;
+        pwm_irq_enable(p_instance);
+    }
+    return NRF_SUCCESS;
+}
+
+uint16_t app_pwm_channel_duty_ticks_get(app_pwm_t const * const p_instance, uint8_t channel)
+{
+    app_pwm_cb_t         * p_cb      = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_ch_cb   = &p_cb->channels_cb[channel];
+
+    return p_ch_cb->pulsewidth;
+}
+
+uint16_t app_pwm_cycle_ticks_get(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    return (uint16_t)p_cb->period;
+}
+
+ret_code_t app_pwm_channel_duty_set(app_pwm_t const * const p_instance,
+                                  uint8_t channel, app_pwm_duty_t duty)
+{
+    uint32_t ticks = ((uint32_t)app_pwm_cycle_ticks_get(p_instance) * (uint32_t)duty) / 100UL;
+    return app_pwm_channel_duty_ticks_set(p_instance, channel, ticks);
+}
+
+
+app_pwm_duty_t app_pwm_channel_duty_get(app_pwm_t const * const p_instance, uint8_t channel)
+{
+    uint32_t value = ((uint32_t)app_pwm_channel_duty_ticks_get(p_instance, channel) * 100UL) \
+                     / (uint32_t)app_pwm_cycle_ticks_get(p_instance);
+
+    return (app_pwm_duty_t)value;
+}
+
+
+/**
+ * @brief Function for initializing the PWM channel.
+ *
+ * @param[in] p_instance       PWM instance.
+ * @param[in] channel          Channel number.
+ * @param[in] pin              GPIO pin number.
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_NO_MEM If there were not enough free resources.
+ * @retval    NRF_ERROR_INVALID_STATE If the timer is already in use or initialization failed.
+ */
+static ret_code_t app_pwm_channel_init(app_pwm_t const * const p_instance, uint8_t channel,
+                                     uint32_t pin, app_pwm_polarity_t polarity)
+{
+    ASSERT(channel < APP_PWM_CHANNELS_PER_INSTANCE);
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+    app_pwm_channel_cb_t * p_channel_cb = &p_cb->channels_cb[channel];
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    p_channel_cb->pulsewidth = 0;
+    p_channel_cb->polarity   = polarity;
+    ret_code_t err_code;
+
+    /* GPIOTE setup: */
+    nrf_drv_gpiote_out_config_t out_cfg = GPIOTE_CONFIG_OUT_TASK_TOGGLE( POLARITY_INACTIVE(p_instance, channel) );
+    err_code = nrf_drv_gpiote_out_init((nrf_drv_gpiote_pin_t)pin,&out_cfg);
+    if (err_code != NRF_SUCCESS)
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+    p_cb->channels_cb[channel].gpio_pin = pin;
+
+    // Set output to inactive state.
+    if (polarity)
+    {
+        nrf_gpio_pin_clear(pin);
+    }
+    else
+    {
+        nrf_gpio_pin_set(pin);
+    }
+
+    /* PPI setup: */
+    for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_CHANNEL; ++i)
+    {
+        if (nrf_drv_ppi_channel_alloc(&p_channel_cb->ppi_channels[i]) != NRF_SUCCESS)
+        {
+            return NRF_ERROR_NO_MEM; // Resource de-allocation is done by callee.
+        }
+    }
+
+    nrf_drv_ppi_channel_disable(p_channel_cb->ppi_channels[0]);
+    nrf_drv_ppi_channel_disable(p_channel_cb->ppi_channels[1]);
+    nrf_drv_ppi_channel_assign(p_channel_cb->ppi_channels[0],
+                               nrf_drv_timer_compare_event_address_get(p_instance->p_timer, channel),
+                               nrf_drv_gpiote_out_task_addr_get(p_channel_cb->gpio_pin));
+    nrf_drv_ppi_channel_assign(p_channel_cb->ppi_channels[1],
+                               nrf_drv_timer_compare_event_address_get(p_instance->p_timer, PWM_MAIN_CC_CHANNEL),
+                               nrf_drv_gpiote_out_task_addr_get(p_channel_cb->gpio_pin));
+
+    p_channel_cb->initialized = APP_PWM_CHANNEL_INITIALIZED;
+    m_pwm_ready_counter[p_instance->p_timer->instance_id][channel] = 0;
+
+    return NRF_SUCCESS;
+}
+
+
+/**
+ * @brief Function for calculating target timer frequency, which will allow to set given period length.
+ *
+ * @param[in] period_us       Desired period in microseconds.
+ *
+ * @retval    Timer frequency.
+ */
+__STATIC_INLINE nrf_timer_frequency_t pwm_calculate_timer_frequency(uint32_t period_us)
+{
+    uint32_t f   = (uint32_t) NRF_TIMER_FREQ_16MHz;
+    uint32_t min = (uint32_t) NRF_TIMER_FREQ_31250Hz;
+
+    while ((period_us > TIMER_MAX_PULSEWIDTH_US_ON_16M) && (f < min))
+    {
+        period_us >>= 1;
+        ++f;
+    }
+
+#ifdef NRF52
+    if ((m_use_ppi_delay_workaround) && (f == (uint32_t) NRF_TIMER_FREQ_16MHz))
+    {
+        f = (uint32_t) NRF_TIMER_FREQ_8MHz;
+    }
+#endif
+
+    return (nrf_timer_frequency_t) f;
+}
+
+
+ret_code_t app_pwm_init(app_pwm_t const * const p_instance, app_pwm_config_t const * const p_config,
+                        app_pwm_callback_t p_ready_callback)
+{
+    ASSERT(p_instance);
+
+    if (!p_config)
+    {
+        return NRF_ERROR_INVALID_DATA;
+    }
+
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    if (p_cb->state != NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    uint32_t err_code = nrf_drv_ppi_init();
+    if ((err_code != NRF_SUCCESS) && (err_code != MODULE_ALREADY_INITIALIZED))
+    {
+        return NRF_ERROR_NO_MEM;
+    }
+
+
+    if (!nrf_drv_gpiote_is_init())
+    {
+        err_code = nrf_drv_gpiote_init();
+        if (err_code != NRF_SUCCESS)
+		{
+			return NRF_ERROR_INTERNAL;
+		}
+    }
+
+#ifdef NRF52
+    if (((*(uint32_t *)0xF0000FE8) & 0x000000F0) == 0x30)
+    {
+        m_use_ppi_delay_workaround = false;
+    }
+    else
+    {
+        m_use_ppi_delay_workaround = true;
+    }
+#endif
+    
+    // Innitialize resource status:
+    p_cb->ppi_channels[0] = (nrf_ppi_channel_t)UNALLOCATED;
+    p_cb->ppi_channels[1] = (nrf_ppi_channel_t)UNALLOCATED;
+    p_cb->ppi_group       = (nrf_ppi_channel_group_t)UNALLOCATED;
+
+    for (uint8_t i = 0; i < APP_PWM_CHANNELS_PER_INSTANCE; ++i)
+    {
+        p_cb->channels_cb[i].initialized     = APP_PWM_CHANNEL_UNINITIALIZED;
+        p_cb->channels_cb[i].ppi_channels[0] = (nrf_ppi_channel_t)UNALLOCATED;
+        p_cb->channels_cb[i].ppi_channels[1] = (nrf_ppi_channel_t)UNALLOCATED;
+        p_cb->channels_cb[i].gpio_pin        = UNALLOCATED;
+    }
+
+    // Allocate PPI channels and groups:
+    for (uint8_t i = 0; i < APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE; ++i)
+    {
+        if (nrf_drv_ppi_channel_alloc(&p_cb->ppi_channels[i]) != NRF_SUCCESS)
+        {
+            pwm_dealloc(p_instance);
+            return NRF_ERROR_NO_MEM;
+        }
+    }
+    if (nrf_drv_ppi_group_alloc(&p_cb->ppi_group) != NRF_SUCCESS)
+    {
+        pwm_dealloc(p_instance);
+        return NRF_ERROR_NO_MEM;
+    }
+
+    // Initialize channels:
+    for (uint8_t i = 0; i < APP_PWM_CHANNELS_PER_INSTANCE; ++i)
+    {
+        if (p_config->pins[i] != APP_PWM_NOPIN)
+        {
+            err_code = app_pwm_channel_init(p_instance, i, p_config->pins[i], p_config->pin_polarity[i]);
+            if (err_code != NRF_SUCCESS)
+            {
+                pwm_dealloc(p_instance);
+                return err_code;
+            }
+            app_pwm_channel_duty_ticks_set(p_instance, i, 0);
+        }
+    }
+
+    // Initialize timer:
+    nrf_timer_frequency_t  timer_freq = pwm_calculate_timer_frequency(p_config->period_us);
+    nrf_drv_timer_config_t timer_cfg  = {
+        .frequency          = timer_freq,
+        .mode               = NRF_TIMER_MODE_TIMER,
+        .bit_width          = NRF_TIMER_BIT_WIDTH_16,
+        .interrupt_priority = APP_IRQ_PRIORITY_LOW,
+        .p_context          = (void *) (uint32_t) p_instance->p_timer->instance_id
+    };
+    err_code = nrf_drv_timer_init(p_instance->p_timer, &timer_cfg,
+                                  pwm_ready_tick);
+    if (err_code != NRF_SUCCESS)
+    {
+        pwm_dealloc(p_instance);
+        return err_code;
+    }
+
+    uint32_t ticks = nrf_drv_timer_us_to_ticks(p_instance->p_timer, p_config->period_us);
+    p_cb->period = ticks;
+    nrf_drv_timer_clear(p_instance->p_timer);
+    nrf_drv_timer_extended_compare(p_instance->p_timer, (nrf_timer_cc_channel_t) PWM_MAIN_CC_CHANNEL,
+                                    ticks, NRF_TIMER_SHORT_COMPARE2_CLEAR_MASK, true);
+    nrf_drv_timer_compare_int_disable(p_instance->p_timer, PWM_MAIN_CC_CHANNEL);
+
+    p_cb->p_ready_callback = p_ready_callback;
+    m_instances[p_instance->p_timer->instance_id] = p_instance;
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+
+    return NRF_SUCCESS;
+}
+
+
+void app_pwm_enable(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    for (uint32_t channel = 0; channel < APP_PWM_CHANNELS_PER_INSTANCE; ++channel)
+    {
+        app_pwm_channel_cb_t * p_ch_cb = &p_cb->channels_cb[channel];
+        m_pwm_ready_counter[p_instance->p_timer->instance_id][channel] = 0;
+        if (p_ch_cb->initialized)
+        {
+            nrf_drv_gpiote_out_task_force(p_ch_cb->gpio_pin, POLARITY_INACTIVE(p_instance, channel));
+            nrf_drv_gpiote_out_task_enable(p_ch_cb->gpio_pin);
+            p_ch_cb->pulsewidth = 0;
+        }
+    }
+    m_pwm_busy[p_instance->p_timer->instance_id] = BUSY_STATE_IDLE;
+    pan73_workaround(p_instance->p_timer->p_reg, true);
+    nrf_drv_timer_clear(p_instance->p_timer);
+    nrf_drv_timer_enable(p_instance->p_timer);
+
+    p_cb->state = NRF_DRV_STATE_POWERED_ON;
+    return;
+}
+
+
+void app_pwm_disable(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    ASSERT(p_cb->state != NRF_DRV_STATE_UNINITIALIZED);
+
+    nrf_drv_timer_disable(p_instance->p_timer);
+    pwm_irq_disable(p_instance);
+    for (uint8_t ppi_channel = 0; ppi_channel < APP_PWM_REQUIRED_PPI_CHANNELS_PER_INSTANCE; ++ppi_channel)
+    {
+        nrf_drv_ppi_channel_disable(p_cb->ppi_channels[ppi_channel]);
+    }
+    for (uint8_t channel = 0; channel < APP_PWM_CHANNELS_PER_INSTANCE; ++channel)
+    {
+        app_pwm_channel_cb_t * p_ch_cb = &p_cb->channels_cb[channel];
+        if (p_ch_cb->initialized)
+        {
+            uint8_t polarity = POLARITY_INACTIVE(p_instance, channel);
+            if (polarity)
+            {
+                nrf_gpio_pin_set(p_ch_cb->gpio_pin);
+            }
+            else
+            {
+                nrf_gpio_pin_clear(p_ch_cb->gpio_pin);
+            }
+            nrf_drv_gpiote_out_task_disable(p_ch_cb->gpio_pin);
+            nrf_drv_ppi_channel_disable(p_ch_cb->ppi_channels[0]);
+            nrf_drv_ppi_channel_disable(p_ch_cb->ppi_channels[1]);
+        }
+    }
+    pan73_workaround(p_instance->p_timer->p_reg, false);
+
+    p_cb->state = NRF_DRV_STATE_INITIALIZED;
+    return;
+}
+
+
+ret_code_t app_pwm_uninit(app_pwm_t const * const p_instance)
+{
+    app_pwm_cb_t * p_cb = p_instance->p_cb;
+
+    if (p_cb->state == NRF_DRV_STATE_POWERED_ON)
+    {
+        app_pwm_disable(p_instance);
+    }
+    else if (p_cb->state == NRF_DRV_STATE_UNINITIALIZED)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+    pwm_dealloc(p_instance);
+
+    p_cb->state = NRF_DRV_STATE_UNINITIALIZED;
+    return NRF_SUCCESS;
+}
+
+
+//lint -restore
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.h
new file mode 100644
index 0000000000..de9c8e0fad
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/pwm/app_pwm.h
@@ -0,0 +1,322 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup app_pwm Pulse-width modulation (PWM)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Module for generating a pulse-width modulated output signal.
+ *
+ * @details This module provides a PWM implementation using timers, GPIOTE, and PPI.
+ *
+ * Resource usage:
+ * - 2 PPI channels per instance + 2 PPI channels per PWM channel.
+ * - 1 PPI group per instance.
+ * - 1 GPIOTE channel per PWM channel.
+ *
+ * For example, a PWM instance with two channels will consume 2+4 PPI channels, 1 PPI group, and 2 GPIOTE channels.
+ *
+ * The maximum number of PWM channels per instance is 2.
+ */
+
+#ifndef APP_PWM_H__
+#define APP_PWM_H__
+
+#include <stdint.h>
+#include "sdk_errors.h"
+#include "nrf_drv_timer.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_ppi.h"
+
+
+#define APP_PWM_NOPIN                 0xFFFFFFFF
+
+/** @brief Number of channels for one timer instance (fixed to 2 due to timer properties).*/
+#define APP_PWM_CHANNELS_PER_INSTANCE 2
+
+/**@brief Macro for creating a PWM instance. */
+#define APP_PWM_INSTANCE(name, num)                                           \
+    const nrf_drv_timer_t m_pwm_##name##_timer = NRF_DRV_TIMER_INSTANCE(num); \
+    app_pwm_cb_t m_pwm_##name##_cb;                                           \
+    /*lint -e{545}*/                                                          \
+    const app_pwm_t name = {                                                  \
+        .p_cb    = &m_pwm_##name##_cb,                                        \
+        .p_timer = &m_pwm_##name##_timer,                                     \
+    }
+
+
+/**@brief PWM instance default configuration (1 channel). */
+#define APP_PWM_DEFAULT_CONFIG_1CH(period_in_us, pin)                                  \
+    {                                                                                  \
+        .pins            = {pin, APP_PWM_NOPIN},                                       \
+        .pin_polarity    = {APP_PWM_POLARITY_ACTIVE_LOW, APP_PWM_POLARITY_ACTIVE_LOW}, \
+        .num_of_channels = 1,                                                          \
+        .period_us       = period_in_us                                                \
+    }
+
+/**@brief PWM instance default configuration (2 channels). */
+#define APP_PWM_DEFAULT_CONFIG_2CH(period_in_us, pin0, pin1)                           \
+    {                                                                                  \
+        .pins            = {pin0, pin1},                                               \
+        .pin_polarity    = {APP_PWM_POLARITY_ACTIVE_LOW, APP_PWM_POLARITY_ACTIVE_LOW}, \
+        .num_of_channels = 2,                                                          \
+        .period_us       = period_in_us                                                \
+    }
+
+typedef uint16_t app_pwm_duty_t;
+
+/**
+ * @brief PWM callback that is executed when a PWM duty change has been completed.
+ *
+ * @param[in] pwm_id  PWM instance ID.
+ */
+typedef void (* app_pwm_callback_t)(uint32_t);
+
+/**
+ * @brief Channel polarity.
+ */
+typedef enum
+{
+    APP_PWM_POLARITY_ACTIVE_LOW  = 0,
+    APP_PWM_POLARITY_ACTIVE_HIGH = 1
+} app_pwm_polarity_t;
+
+/**@brief PWM configuration structure used for initialization. */
+typedef struct
+{
+    uint32_t           pins[APP_PWM_CHANNELS_PER_INSTANCE];         //!< Pins configured as PWM output.
+    app_pwm_polarity_t pin_polarity[APP_PWM_CHANNELS_PER_INSTANCE]; //!< Polarity of active state on pin.
+    uint32_t           num_of_channels;                             //!< Number of channels that can be used.
+    uint32_t           period_us;                                   //!< PWM signal output period to configure (in microseconds).
+} app_pwm_config_t;
+
+
+/**
+ * @cond (NODOX)
+ * @defgroup app_pwm_internal Auxiliary internal types declarations
+ * @{
+ * @internal
+ *
+ * @brief Module for internal usage inside the library only
+ *
+ * There are some definitions that must be included in the header file because 
+ * of the way the library is set up. In this way, the are accessible to the user.
+ * However, any functions and variables defined here may change at any time 
+ * without a warning, so you should not access them directly.
+ */
+
+    /**
+     * @brief PWM channel instance
+     *
+     * This structure holds all data needed by a single PWM channel.
+     */
+    typedef struct
+    {
+        uint32_t           gpio_pin;        //!< Pin that is used by this PWM channel.
+        uint32_t           pulsewidth;      //!< The copy of duty currently set (in ticks).
+        nrf_ppi_channel_t  ppi_channels[2]; //!< PPI channels used by the PWM channel to clear and set the output.
+        app_pwm_polarity_t polarity;        //!< The active state of the pin.
+        uint8_t            initialized;     //!< The internal information if the selected channel was initialized.
+    } app_pwm_channel_cb_t;
+
+    /**
+     * @brief Variable part of PWM instance
+     *
+     * This structure holds instance data that may change.
+     */
+    typedef struct
+    {
+        app_pwm_channel_cb_t    channels_cb[APP_PWM_CHANNELS_PER_INSTANCE]; //!< Channels data
+        uint32_t                period;                                     //!< Selected period in ticks
+        app_pwm_callback_t      p_ready_callback;                           //!< Callback function called on PWM readiness
+        nrf_ppi_channel_t       ppi_channels[2];                            //!< PPI channels used temporary while changing duty
+        nrf_ppi_channel_group_t ppi_group;                                  //!< PPI group used to synchronize changes on channels
+        nrf_drv_state_t         state;                                      //!< Current driver status
+    } app_pwm_cb_t;
+/** @}
+ * @endcond
+ */
+
+
+/**@brief PWM instance structure. */
+typedef struct
+{
+    app_pwm_cb_t *p_cb;                    //!< Pointer to control block internals.
+    nrf_drv_timer_t const * const p_timer; //!< Timer used by this PWM instance.
+} app_pwm_t;
+
+/**
+ * @brief Function for checking if the PWM instance is busy updating the duty cycle.
+ *
+ * @param[in] p_instance  PWM instance.
+ *
+ * @retval True  If the PWM instance is ready for duty cycle changes.
+ * @retval False If a change operation is in progress.
+ */
+bool app_pwm_busy_check(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for initializing a PWM instance.
+ *
+ * @param[in] p_instance        PWM instance.
+ * @param[in] p_config          Initial configuration.
+ * @param[in] p_ready_callback  Pointer to ready callback function (or NULL to disable).
+ *
+ * @retval    NRF_SUCCESS If initialization was successful.
+ * @retval    NRF_ERROR_NO_MEM If there were not enough free resources.
+ * @retval    NRF_ERROR_INVALID_PARAM If an invalid configuration structure was passed.
+ * @retval    NRF_ERROR_INVALID_STATE If the timer/PWM is already in use or if initialization failed.
+ */
+ret_code_t app_pwm_init(app_pwm_t const * const p_instance, app_pwm_config_t const * const p_config,
+                        app_pwm_callback_t p_ready_callback);
+
+
+/**
+ * @brief Function for uninitializing a PWM instance and releasing the allocated resources.
+ *
+ * @param[in] p_instance  PWM instance.
+ *
+ * @retval    NRF_SUCCESS If uninitialization was successful.
+ * @retval    NRF_ERROR_INVALID_STATE If the given instance was not initialized.
+ */
+ret_code_t app_pwm_uninit(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for enabling a PWM instance after initialization.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+void app_pwm_enable(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for disabling a PWM instance after initialization.
+ *
+ * @param[in] p_instance  PWM instance.
+ */
+void app_pwm_disable(app_pwm_t const * const p_instance);
+
+/**
+ * @brief Function for setting the PWM channel duty cycle in percents.
+ *
+ * A duty cycle change requires one full PWM clock period to finish.
+ * If another change is attempted for any channel of given instance before
+ * the current change is complete, the new attempt will result in the error
+ * NRF_ERROR_BUSY.
+ *
+ * @param[in] p_instance  PWM instance.
+ * @param[in] channel     Channel number.
+ * @param[in] duty        Duty cycle (0 - 100).
+ *
+ * @retval    NRF_SUCCESS If the operation was successful.
+ * @retval    NRF_ERROR_BUSY If the PWM is not ready yet.
+ * @retval    NRF_ERROR_INVALID_STATE If the given instance was not initialized.
+ *
+ */
+ret_code_t app_pwm_channel_duty_set(app_pwm_t const * const p_instance,
+                                  uint8_t channel, app_pwm_duty_t duty);
+
+/**
+ * @brief Function for retrieving the PWM channel duty cycle in percents.
+ *
+ * @param[in] p_instance  PWM instance.
+ * @param[in] channel     Channel number.
+ *
+ * @return    Duty cycle value.
+ */
+app_pwm_duty_t app_pwm_channel_duty_get(app_pwm_t const * const p_instance, uint8_t channel);
+
+
+/**
+ * @name Functions accessing values in ticks
+ *
+ * Auxiliary functions that allow to get values in actual timer ticks.
+ * @{
+ */
+
+    /**
+     * @brief Function for setting PWM channel duty cycle in clock ticks.
+     *
+     * @note      Duty cycle changes require one full PWM clock period to finish.
+     *            Until that, the next change attempt (for any channel of given instance)
+     *            will result in an NRF_ERROR_BUSY error.
+     *
+     * @param[in] p_instance  PWM instance.
+     * @param[in] channel     Channel number.
+     * @param[in] ticks       Number of PWM clock ticks.
+     *
+     * @retval    NRF_SUCCESS If the operation was successful.
+     * @retval    NRF_ERROR_BUSY If PWM is not ready yet.
+     * @retval    NRF_ERROR_INVALID_STATE If the given instance was not initialized.
+     */
+    ret_code_t app_pwm_channel_duty_ticks_set(app_pwm_t const * const p_instance,
+                                              uint8_t           channel,
+                                              uint16_t          ticks);
+
+
+    /**
+     * @brief Function for retrieving the PWM channel duty cycle in ticks.
+     *
+     * This function retrieves the real, currently set duty cycle in ticks.
+     * For one full PWM cycle the value might be different than the value set by the last
+     * @ref app_pwm_channel_duty_ticks_set function call.
+     *
+     * @param[in] p_instance  PWM instance.
+     * @param[in] channel     Channel number.
+     *
+     * @return    Number of ticks set for selected channel.
+     *
+     */
+    uint16_t app_pwm_channel_duty_ticks_get(app_pwm_t const * const p_instance, uint8_t channel);
+
+    /**
+     * @brief Function for returning the number of ticks in a whole cycle.
+     *
+     * @param[in] p_instance  PWM instance.
+     *
+     * @return    Number of ticks that corresponds to 100% of the duty cycle.
+     */
+    uint16_t app_pwm_cycle_ticks_get(app_pwm_t const * const p_instance);
+/** @} */
+
+
+#endif
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.c
new file mode 100644
index 0000000000..d927ead696
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.c
@@ -0,0 +1,254 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "app_scheduler.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <string.h>
+#include "nrf_soc.h"
+#include "nrf_assert.h"
+#include "app_util.h"
+#include "app_util_platform.h"
+
+/**@brief Structure for holding a scheduled event header. */
+typedef struct
+{
+    app_sched_event_handler_t handler;          /**< Pointer to event handler to receive the event. */
+    uint16_t                  event_data_size;  /**< Size of event data. */
+} event_header_t;
+
+STATIC_ASSERT(sizeof(event_header_t) <= APP_SCHED_EVENT_HEADER_SIZE);
+
+static event_header_t * m_queue_event_headers;  /**< Array for holding the queue event headers. */
+static uint8_t        * m_queue_event_data;     /**< Array for holding the queue event data. */
+static volatile uint8_t m_queue_start_index;    /**< Index of queue entry at the start of the queue. */
+static volatile uint8_t m_queue_end_index;      /**< Index of queue entry at the end of the queue. */
+static uint16_t         m_queue_event_size;     /**< Maximum event size in queue. */
+static uint16_t         m_queue_size;           /**< Number of queue entries. */
+
+#ifdef APP_SCHEDULER_WITH_PROFILER
+static uint16_t m_max_queue_utilization;    /**< Maximum observed queue utilization. */
+#endif
+
+/**@brief Function for incrementing a queue index, and handle wrap-around.
+ *
+ * @param[in]   index   Old index.
+ *
+ * @return      New (incremented) index.
+ */
+static __INLINE uint8_t next_index(uint8_t index)
+{
+    return (index < m_queue_size) ? (index + 1) : 0;
+}
+
+
+static __INLINE uint8_t app_sched_queue_full()
+{
+  uint8_t tmp = m_queue_start_index;
+  return next_index(m_queue_end_index) == tmp;
+}
+
+/**@brief Macro for checking if a queue is full. */
+#define APP_SCHED_QUEUE_FULL() app_sched_queue_full()
+
+
+static __INLINE uint8_t app_sched_queue_empty()
+{
+  uint8_t tmp = m_queue_start_index;
+  return m_queue_end_index == tmp;
+}
+
+/**@brief Macro for checking if a queue is empty. */
+#define APP_SCHED_QUEUE_EMPTY() app_sched_queue_empty()
+
+
+uint32_t app_sched_init(uint16_t event_size, uint16_t queue_size, void * p_event_buffer)
+{
+    uint16_t data_start_index = (queue_size + 1) * sizeof(event_header_t);
+
+    // Check that buffer is correctly aligned
+    if (!is_word_aligned(p_event_buffer))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Initialize event scheduler
+    m_queue_event_headers = p_event_buffer;
+    m_queue_event_data    = &((uint8_t *)p_event_buffer)[data_start_index];
+    m_queue_end_index     = 0;
+    m_queue_start_index   = 0;
+    m_queue_event_size    = event_size;
+    m_queue_size          = queue_size;
+
+#ifdef APP_SCHEDULER_WITH_PROFILER
+    m_max_queue_utilization = 0;
+#endif
+
+    return NRF_SUCCESS;
+}
+
+
+#ifdef APP_SCHEDULER_WITH_PROFILER
+static void queue_utilization_check(void)
+{
+    uint16_t start = m_queue_start_index;
+    uint16_t end   = m_queue_end_index;
+    uint16_t queue_utilization = (end >= start) ? (end - start) :
+        (m_queue_size + 1 - start + end);
+
+    if (queue_utilization > m_max_queue_utilization)
+    {
+        m_max_queue_utilization = queue_utilization;
+    }
+}
+
+uint16_t app_sched_queue_utilization_get(void)
+{
+    return m_max_queue_utilization;
+}
+#endif
+
+
+uint32_t app_sched_event_put(void                    * p_event_data,
+                             uint16_t                  event_data_size,
+                             app_sched_event_handler_t handler)
+{
+    uint32_t err_code;
+
+    if (event_data_size <= m_queue_event_size)
+    {
+        uint16_t event_index = 0xFFFF;
+
+        CRITICAL_REGION_ENTER();
+
+        if (!APP_SCHED_QUEUE_FULL())
+        {
+            event_index       = m_queue_end_index;
+            m_queue_end_index = next_index(m_queue_end_index);
+
+        #ifdef APP_SCHEDULER_WITH_PROFILER
+            // This function call must be protected with critical region because
+            // it modifies 'm_max_queue_utilization'.
+            queue_utilization_check();
+        #endif
+        }
+
+        CRITICAL_REGION_EXIT();
+
+        if (event_index != 0xFFFF)
+        {
+            // NOTE: This can be done outside the critical region since the event consumer will
+            //       always be called from the main loop, and will thus never interrupt this code.
+            m_queue_event_headers[event_index].handler = handler;
+            if ((p_event_data != NULL) && (event_data_size > 0))
+            {
+                memcpy(&m_queue_event_data[event_index * m_queue_event_size],
+                       p_event_data,
+                       event_data_size);
+                m_queue_event_headers[event_index].event_data_size = event_data_size;
+            }
+            else
+            {
+                m_queue_event_headers[event_index].event_data_size = 0;
+            }
+
+            err_code = NRF_SUCCESS;
+        }
+        else
+        {
+            err_code = NRF_ERROR_NO_MEM;
+        }
+    }
+    else
+    {
+        err_code = NRF_ERROR_INVALID_LENGTH;
+    }
+
+    return err_code;
+}
+
+
+/**@brief Function for reading the next event from specified event queue.
+ *
+ * @param[out]  pp_event_data       Pointer to pointer to event data.
+ * @param[out]  p_event_data_size   Pointer to size of event data.
+ * @param[out]  p_event_handler     Pointer to event handler function pointer.
+ *
+ * @return      NRF_SUCCESS if new event, NRF_ERROR_NOT_FOUND if event queue is empty.
+ */
+static uint32_t app_sched_event_get(void                     ** pp_event_data,
+                                    uint16_t *                  p_event_data_size,
+                                    app_sched_event_handler_t * p_event_handler)
+{
+    uint32_t err_code = NRF_ERROR_NOT_FOUND;
+
+    if (!APP_SCHED_QUEUE_EMPTY())
+    {
+        uint16_t event_index;
+
+        // NOTE: There is no need for a critical region here, as this function will only be called
+        //       from app_sched_execute() from inside the main loop, so it will never interrupt
+        //       app_sched_event_put(). Also, updating of (i.e. writing to) the start index will be
+        //       an atomic operation.
+        event_index         = m_queue_start_index;
+        m_queue_start_index = next_index(m_queue_start_index);
+
+        *pp_event_data     = &m_queue_event_data[event_index * m_queue_event_size];
+        *p_event_data_size = m_queue_event_headers[event_index].event_data_size;
+        *p_event_handler   = m_queue_event_headers[event_index].handler;
+
+        err_code = NRF_SUCCESS;
+    }
+
+    return err_code;
+}
+
+
+void app_sched_execute(void)
+{
+    void                    * p_event_data;
+    uint16_t                  event_data_size;
+    app_sched_event_handler_t event_handler;
+
+    // Get next event (if any), and execute handler
+    while ((app_sched_event_get(&p_event_data, &event_data_size, &event_handler) == NRF_SUCCESS))
+    {
+        event_handler(p_event_data, event_data_size);
+    }
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.h
new file mode 100644
index 0000000000..82c90b9180
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/scheduler/app_scheduler.h
@@ -0,0 +1,190 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup app_scheduler Scheduler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief The scheduler is used for transferring execution from the interrupt context to the main
+ *        context.
+ *
+ * @details See @ref seq_diagrams_sched for sequence diagrams illustrating the flow of events
+ *          when using the Scheduler.
+ *
+ * @section app_scheduler_req Requirements:
+ *
+ * @subsection main_context_logic Logic in main context:
+ *
+ *   - Define an event handler for each type of event expected.
+ *   - Initialize the scheduler by calling the APP_SCHED_INIT() macro before entering the
+ *     application main loop.
+ *   - Call app_sched_execute() from the main loop each time the application wakes up because of an
+ *     event (typically when sd_app_evt_wait() returns).
+ *
+ * @subsection int_context_logic Logic in interrupt context:
+ *
+ *   - In the interrupt handler, call app_sched_event_put()
+ *     with the appropriate data and event handler. This will insert an event into the
+ *     scheduler's queue. The app_sched_execute() function will pull this event and call its
+ *     handler in the main context.
+ *
+ * @if (PERIPHERAL)
+ * For an example usage of the scheduler, see the implementations of
+ * @ref ble_sdk_app_hids_mouse and @ref ble_sdk_app_hids_keyboard.
+ * @endif
+ *
+ * @image html scheduler_working.jpg The high level design of the scheduler
+ */
+
+#ifndef APP_SCHEDULER_H__
+#define APP_SCHEDULER_H__
+
+#include <stdint.h>
+#include "app_error.h"
+#include "app_util.h"
+
+#define APP_SCHED_EVENT_HEADER_SIZE 8       /**< Size of app_scheduler.event_header_t (only for use inside APP_SCHED_BUF_SIZE()). */
+
+/**@brief Compute number of bytes required to hold the scheduler buffer.
+ *
+ * @param[in] EVENT_SIZE   Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE   Number of entries in scheduler queue (i.e. the maximum number of events
+ *                         that can be scheduled for execution).
+ *
+ * @return    Required scheduler buffer size (in bytes).
+ */
+#define APP_SCHED_BUF_SIZE(EVENT_SIZE, QUEUE_SIZE)                                                 \
+            (((EVENT_SIZE) + APP_SCHED_EVENT_HEADER_SIZE) * ((QUEUE_SIZE) + 1))
+            
+/**@brief Scheduler event handler type. */
+typedef void (*app_sched_event_handler_t)(void * p_event_data, uint16_t event_size);
+
+/**@brief Macro for initializing the event scheduler.
+ *
+ * @details It will also handle dimensioning and allocation of the memory buffer required by the
+ *          scheduler, making sure the buffer is correctly aligned.
+ *
+ * @param[in] EVENT_SIZE   Maximum size of events to be passed through the scheduler.
+ * @param[in] QUEUE_SIZE   Number of entries in scheduler queue (i.e. the maximum number of events
+ *                         that can be scheduled for execution).
+ *
+ * @note Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ *       several times as long as it is from the same location, e.g. to do a reinitialization).
+ */
+#define APP_SCHED_INIT(EVENT_SIZE, QUEUE_SIZE)                                                     \
+    do                                                                                             \
+    {                                                                                              \
+        static uint32_t APP_SCHED_BUF[CEIL_DIV(APP_SCHED_BUF_SIZE((EVENT_SIZE), (QUEUE_SIZE)),     \
+                                               sizeof(uint32_t))];                                 \
+        uint32_t ERR_CODE = app_sched_init((EVENT_SIZE), (QUEUE_SIZE), APP_SCHED_BUF);             \
+        APP_ERROR_CHECK(ERR_CODE);                                                                 \
+    } while (0)
+
+/**@brief Function for initializing the Scheduler.
+ *
+ * @details It must be called before entering the main loop.
+ *
+ * @param[in]   max_event_size   Maximum size of events to be passed through the scheduler.
+ * @param[in]   queue_size       Number of entries in scheduler queue (i.e. the maximum number of
+ *                               events that can be scheduled for execution).
+ * @param[in]   p_evt_buffer   Pointer to memory buffer for holding the scheduler queue. It must
+ *                               be dimensioned using the APP_SCHED_BUFFER_SIZE() macro. The buffer
+ *                               must be aligned to a 4 byte boundary.
+ *
+ * @note Normally initialization should be done using the APP_SCHED_INIT() macro, as that will both
+ *       allocate the scheduler buffer, and also align the buffer correctly.
+ *
+ * @retval      NRF_SUCCESS               Successful initialization.
+ * @retval      NRF_ERROR_INVALID_PARAM   Invalid parameter (buffer not aligned to a 4 byte
+ *                                        boundary).
+ */
+uint32_t app_sched_init(uint16_t max_event_size, uint16_t queue_size, void * p_evt_buffer);
+
+/**@brief Function for executing all scheduled events.
+ *
+ * @details This function must be called from within the main loop. It will execute all events
+ *          scheduled since the last time it was called.
+ */
+void app_sched_execute(void);
+
+/**@brief Function for scheduling an event.
+ *
+ * @details Puts an event into the event queue.
+ *
+ * @param[in]   p_event_data   Pointer to event data to be scheduled.
+ * @param[in]   event_size   Size of event data to be scheduled.
+ * @param[in]   handler        Event handler to receive the event.
+ *
+ * @return      NRF_SUCCESS on success, otherwise an error code.
+ */
+uint32_t app_sched_event_put(void *                    p_event_data,
+                             uint16_t                  event_size,
+                             app_sched_event_handler_t handler);
+
+#ifdef APP_SCHEDULER_WITH_PROFILER
+/**@brief Function for getting the maximum observed queue utilization.
+ *
+ * Function for tuning the module and determining QUEUE_SIZE value and thus module RAM usage.
+ *
+ * @return Maximum number of events in queue observed so far.
+ */
+uint16_t app_sched_queue_utilization_get(void);
+#endif
+
+#ifdef APP_SCHEDULER_WITH_PAUSE
+/**@brief A function to pause the scheduler.
+ *
+ * @details When the scheduler is paused events are not pulled from the scheduler queue for
+ *          processing. The function can be called multiple times. To unblock the scheduler the
+ *          function @ref app_sched_resume has to be called the same number of times.
+ */
+void app_sched_pause(void);
+
+/**@brief A function to resume a scheduler.
+ *
+ * @details To unblock the scheduler this function has to be called the same number of times as
+ *          @ref app_sched_pause function.
+ */
+void app_sched_resume(void);
+#endif
+#endif // APP_SCHEDULER_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.c
new file mode 100644
index 0000000000..d4804f5348
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.c
@@ -0,0 +1,70 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include <stdio.h>
+#include <stdint.h>
+#include <string.h>
+#include <stdarg.h>
+
+
+#ifdef ENABLE_DEBUG_LOG_SUPPORT
+#include "app_trace.h"
+#include "nrf_log.h"
+
+void app_trace_init(void)
+{
+    (void)NRF_LOG_INIT();
+}
+
+void app_trace_dump(uint8_t * p_buffer, uint32_t len)
+{
+    app_trace_log("\r\n");
+    for (uint32_t index = 0; index <  len; index++)
+    {
+        app_trace_log("0x%02X ", p_buffer[index]);
+    }
+    app_trace_log("\r\n");
+}
+
+#endif // ENABLE_DEBUG_LOG_SUPPORT
+
+/**
+ *@}
+ **/
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.h
new file mode 100644
index 0000000000..bdf439ab36
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/trace/app_trace.h
@@ -0,0 +1,56 @@
+#ifndef __DEBUG_H_
+#define __DEBUG_H_
+
+#include <stdint.h>
+#include <stdio.h>
+
+/**
+ * @defgroup app_trace Debug Logger
+ * @ingroup app_common
+ * @{
+ * @brief Enables debug logs/ trace over UART.
+ * @details Enables debug logs/ trace over UART. Tracing is enabled only if 
+ *          ENABLE_DEBUG_LOG_SUPPORT is defined in the project.
+ */
+#ifdef ENABLE_DEBUG_LOG_SUPPORT
+#include "nrf_log.h"
+/**
+ * @brief Module Initialization.
+ *
+ * @details Initializes the module to use UART as trace output.
+ * 
+ * @warning This function will configure UART using default board configuration. 
+ *          Do not call this function if UART is configured from a higher level in the application. 
+ */
+void app_trace_init(void);
+
+/**
+ * @brief Log debug messages.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ *
+ * @note Though this is currently a macro, it should be used used and treated as function.
+ */
+#define app_trace_log NRF_LOG_PRINTF
+
+/**
+ * @brief Dump auxiliary byte buffer to the debug trace.
+ *
+ * @details This API logs messages over UART. The module must be initialized before using this API.
+ * 
+ * @param[in] p_buffer  Buffer to be dumped on the debug trace.
+ * @param[in] len       Size of the buffer.
+ */
+void app_trace_dump(uint8_t * p_buffer, uint32_t len);
+
+#else // ENABLE_DEBUG_LOG_SUPPORT
+
+#define app_trace_init(...)
+#define app_trace_log(...)
+#define app_trace_dump(...)
+
+#endif // ENABLE_DEBUG_LOG_SUPPORT
+
+/** @} */
+
+#endif //__DEBUG_H_
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.c
new file mode 100644
index 0000000000..986e711fbd
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.c
@@ -0,0 +1,153 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler.
+ */
+
+#include "nrf.h"
+#include <stdio.h>
+#include "app_error.h"
+#include "nordic_common.h"
+#include "sdk_errors.h"
+#include "nrf_log.h"
+
+#ifdef DEBUG
+#include "bsp.h"
+#endif
+
+
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @warning This handler is an example only and does not fit a final product. You need to analyze
+ *          how your product is supposed to react in case of error.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ * @param[in] line_num    Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+
+/*lint -save -e14 */
+#if 0
+void app_error_handler(ret_code_t error_code, uint32_t line_num, const uint8_t * p_file_name)
+{
+    error_info_t error_info =
+    {
+        .line_num    = line_num,
+        .p_file_name = p_file_name,
+        .err_code    = error_code,
+    };
+    app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info));
+
+    UNUSED_VARIABLE(error_info);
+}
+#endif
+
+/*lint -save -e14 */
+void app_error_handler_bare(ret_code_t error_code)
+{
+    error_info_t error_info =
+    {
+        .line_num    = 0,
+        .p_file_name = NULL,
+        .err_code    = error_code,
+    };
+    app_error_fault_handler(NRF_FAULT_ID_SDK_ERROR, 0, (uint32_t)(&error_info));
+
+    UNUSED_VARIABLE(error_info);
+}
+
+
+void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info)
+{
+    /* static error variables - in order to prevent removal by optimizers */
+    static volatile struct
+    {
+        uint32_t        fault_id;
+        uint32_t        pc;
+        uint32_t        error_info;
+        assert_info_t * p_assert_info;
+        error_info_t  * p_error_info;
+        ret_code_t      err_code;
+        uint32_t        line_num;
+        const uint8_t * p_file_name;
+    } m_error_data = {0};
+
+    // The following variable helps Keil keep the call stack visible, in addition, it can be set to
+    // 0 in the debugger to continue executing code after the error check.
+    volatile bool loop = true;
+    UNUSED_VARIABLE(loop);
+
+    m_error_data.fault_id   = id;
+    m_error_data.pc         = pc;
+    m_error_data.error_info = info;
+
+    switch (id)
+    {
+        case NRF_FAULT_ID_SDK_ASSERT:
+            m_error_data.p_assert_info = (assert_info_t *)info;
+            m_error_data.line_num      = m_error_data.p_assert_info->line_num;
+            m_error_data.p_file_name   = m_error_data.p_assert_info->p_file_name;
+            break;
+
+        case NRF_FAULT_ID_SDK_ERROR:
+            m_error_data.p_error_info = (error_info_t *)info;
+            m_error_data.err_code     = m_error_data.p_error_info->err_code;
+            m_error_data.line_num     = m_error_data.p_error_info->line_num;
+            m_error_data.p_file_name  = m_error_data.p_error_info->p_file_name;
+            break;
+    }
+
+    UNUSED_VARIABLE(m_error_data);
+
+    // If printing is disrupted, remove the irq calls, or set the loop variable to 0 in the debugger.
+    __disable_irq();
+
+    while(loop);
+
+    __enable_irq();
+}
+
+/*lint -restore */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.h
new file mode 100644
index 0000000000..66cd551d53
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error.h
@@ -0,0 +1,228 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler and macros for utilizing a common error handler.
+ */
+
+#ifndef APP_ERROR_H__
+#define APP_ERROR_H__
+
+#include <stdint.h>
+#include <stdio.h>
+#include <stdbool.h>
+#include "nrf.h"
+#include "sdk_errors.h"
+#include "nordic_common.h"
+#include "nrf_log.h"
+#include "app_error_weak.h"
+
+#define NRF_FAULT_ID_SDK_RANGE_START 0x00004000 /**< The start of the range of error IDs defined in the SDK. */
+
+/**@defgroup APP_ERROR_FAULT_IDS Fault ID types
+ * @{ */
+#define NRF_FAULT_ID_SDK_ERROR       NRF_FAULT_ID_SDK_RANGE_START + 1 /**< An error stemming from a call to @ref APP_ERROR_CHECK or @ref APP_ERROR_CHECK_BOOL. The info parameter is a pointer to an @ref error_info_t variable. */
+#define NRF_FAULT_ID_SDK_ASSERT      NRF_FAULT_ID_SDK_RANGE_START + 2 /**< An error stemming from a call to ASSERT (nrf_assert.h). The info parameter is a pointer to an @ref assert_info_t variable. */
+/**@} */
+
+/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ERROR.
+ */
+typedef struct
+{
+    uint16_t        line_num;    /**< The line number where the error occurred. */
+    uint8_t const * p_file_name; /**< The file in which the error occurred. */
+    uint32_t        err_code;    /**< The error code representing the error that occurred. */
+} error_info_t;
+
+/**@brief Structure containing info about an error of the type @ref NRF_FAULT_ID_SDK_ASSERT.
+ */
+typedef struct
+{
+    uint16_t        line_num;    /**< The line number where the error occurred. */
+    uint8_t const * p_file_name; /**< The file in which the error occurred. */
+} assert_info_t;
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ * @param[in] line_num    Line number where the handler is called.
+ * @param[in] p_file_name Pointer to the file name.
+ */
+void app_error_handler(uint32_t error_code, uint32_t line_num, const uint8_t * p_file_name);
+
+/**@brief Function for error handling, which is called when an error has occurred.
+ *
+ * @param[in] error_code  Error code supplied to the handler.
+ */
+void app_error_handler_bare(ret_code_t error_code);
+
+/**@brief       Function for saving the parameters and entering an eternal loop, for debug purposes.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+void app_error_save_and_stop(uint32_t id, uint32_t pc, uint32_t info);
+
+/**@brief       Function for printing all error info (using nrf_log).
+ *
+ * @details     Nrf_log library must be initialized using NRF_LOG_INIT macro before calling
+ *              this function.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+static __INLINE void app_error_log(uint32_t id, uint32_t pc, uint32_t info)
+{
+    switch (id)
+    {
+        case NRF_FAULT_ID_SDK_ASSERT:
+            NRF_LOG(NRF_LOG_COLOR_RED "\n*** ASSERTION FAILED ***\n");
+            if (((assert_info_t *)(info))->p_file_name)
+            {
+                NRF_LOG_PRINTF(NRF_LOG_COLOR_WHITE "Line Number: %u\n", (unsigned int) ((assert_info_t *)(info))->line_num);
+                NRF_LOG_PRINTF("File Name:   %s\n", ((assert_info_t *)(info))->p_file_name);
+            }
+            NRF_LOG_PRINTF(NRF_LOG_COLOR_DEFAULT "\n");
+            break;
+
+        case NRF_FAULT_ID_SDK_ERROR:
+            NRF_LOG(NRF_LOG_COLOR_RED "\n*** APPLICATION ERROR *** \n" NRF_LOG_COLOR_WHITE);
+            if (((error_info_t *)(info))->p_file_name)
+            {
+                NRF_LOG_PRINTF("Line Number: %u\n", (unsigned int) ((error_info_t *)(info))->line_num);
+                NRF_LOG_PRINTF("File Name:   %s\n", ((error_info_t *)(info))->p_file_name);
+            }
+            NRF_LOG_PRINTF("Error Code:  0x%X\n" NRF_LOG_COLOR_DEFAULT "\n", (unsigned int) ((error_info_t *)(info))->err_code);
+            break;
+    }
+}
+
+/**@brief       Function for printing all error info (using printf).
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+//lint -save -e438
+static __INLINE void app_error_print(uint32_t id, uint32_t pc, uint32_t info)
+{
+    unsigned int tmp = id;
+    printf("app_error_print():\r\n");
+    printf("Fault identifier:  0x%X\r\n", tmp);
+    printf("Program counter:   0x%X\r\n", tmp = pc);
+    printf("Fault information: 0x%X\r\n", tmp = info);
+
+    switch (id)
+    {
+        case NRF_FAULT_ID_SDK_ASSERT:
+            printf("Line Number: %u\r\n", tmp = ((assert_info_t *)(info))->line_num);
+            printf("File Name:   %s\r\n",       ((assert_info_t *)(info))->p_file_name);
+            break;
+
+        case NRF_FAULT_ID_SDK_ERROR:
+            printf("Line Number: %u\r\n",   tmp = ((error_info_t *)(info))->line_num);
+            printf("File Name:   %s\r\n",         ((error_info_t *)(info))->p_file_name);
+            printf("Error Code:  0x%X\r\n", tmp = ((error_info_t *)(info))->err_code);
+            break;
+    }
+}
+//lint -restore
+
+
+/**@brief Macro for calling error handler function.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#ifdef DEBUG
+#define APP_ERROR_HANDLER(ERR_CODE)                                    \
+    do                                                                 \
+    {                                                                  \
+        app_error_handler((ERR_CODE), __LINE__, (uint8_t*) __FILE__);  \
+    } while (0)
+#else
+#define APP_ERROR_HANDLER(ERR_CODE)                                    \
+    do                                                                 \
+    {                                                                  \
+        app_error_handler_bare((ERR_CODE));                            \
+    } while (0)
+#endif
+/**@brief Macro for calling error handler function if supplied error code any other than NRF_SUCCESS.
+ *
+ * @param[in] ERR_CODE Error code supplied to the error handler.
+ */
+#define APP_ERROR_CHECK(ERR_CODE)                           \
+    do                                                      \
+    {                                                       \
+        const uint32_t LOCAL_ERR_CODE = (ERR_CODE);         \
+        if (LOCAL_ERR_CODE != NRF_SUCCESS)                  \
+        {                                                   \
+            APP_ERROR_HANDLER(LOCAL_ERR_CODE);              \
+        }                                                   \
+    } while (0)
+
+/**@brief Macro for calling error handler function if supplied boolean value is false.
+ *
+ * @param[in] BOOLEAN_VALUE Boolean value to be evaluated.
+ */
+#define APP_ERROR_CHECK_BOOL(BOOLEAN_VALUE)                   \
+    do                                                        \
+    {                                                         \
+        const uint32_t LOCAL_BOOLEAN_VALUE = (BOOLEAN_VALUE); \
+        if (!LOCAL_BOOLEAN_VALUE)                             \
+        {                                                     \
+            APP_ERROR_HANDLER(0);                             \
+        }                                                     \
+    } while (0)
+
+#endif // APP_ERROR_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.c
new file mode 100644
index 0000000000..65351d9e65
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.c
@@ -0,0 +1,80 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "app_error.h"
+
+#ifdef DEBUG
+#include "bsp.h"
+#endif
+ 
+/*lint -save -e14 */
+
+/**
+ * Function is implemented as weak so that it can be overwritten by custom application error handler
+ * when needed.
+ */
+__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info)
+{
+    // On assert, the system can only recover with a reset.
+#ifndef DEBUG
+    NVIC_SystemReset();
+#else
+
+#ifdef BSP_DEFINES_ONLY
+    LEDS_ON(LEDS_MASK);
+#else
+    UNUSED_VARIABLE(bsp_indication_set(BSP_INDICATE_FATAL_ERROR));
+    // This call can be used for debug purposes during application development.
+    // @note CAUTION: Activating this code will write the stack to flash on an error.
+    //                This function should NOT be used in a final product.
+    //                It is intended STRICTLY for development/debugging purposes.
+    //                The flash write will happen EVEN if the radio is active, thus interrupting
+    //                any communication.
+    //                Use with care. Uncomment the line below to use.
+    //ble_debug_assert_handler(error_code, line_num, p_file_name);
+#endif // BSP_DEFINES_ONLY
+
+    app_error_save_and_stop(id, pc, info);
+
+#endif // DEBUG
+}
+
+/*lint -restore */
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.h
new file mode 100644
index 0000000000..1bc784acde
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_error_weak.h
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2016 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef APP_ERROR_WEAK_H__
+#define APP_ERROR_WEAK_H__
+
+/** @file
+ *
+ * @defgroup app_error Common application error handler
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Common application error handler.
+ */
+ 
+/**@brief       Callback function for asserts in the SoftDevice.
+ *
+ * @details     A pointer to this function will be passed to the SoftDevice. This function will be
+ *              called by the SoftDevice if certain unrecoverable errors occur within the
+ *              application or SoftDevice.
+ *
+ *              See @ref nrf_fault_handler_t for more details.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault, or 0 if
+ *                  unavailable.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ *
+ * @remarks Function is implemented as weak so that it can be overwritten by custom application
+ *          error handler when needed.
+ */
+#ifdef __CC_ARM
+	     void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info);
+#else
+__WEAK void app_error_fault_handler(uint32_t id, uint32_t pc, uint32_t info);
+#endif
+
+
+/** @} */
+
+#endif // APP_ERROR_WEAK_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util.h
new file mode 100644
index 0000000000..146bff37a6
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util.h
@@ -0,0 +1,520 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_H__
+#define APP_UTIL_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+#include "nrf.h"
+
+//lint -save -e27 -e10 -e19
+#if defined ( __CC_ARM )
+extern char STACK$$Base;
+extern char STACK$$Length;
+#define STACK_BASE    &STACK$$Base
+#define STACK_TOP    ((void*)((uint32_t)STACK_BASE + (uint32_t)&STACK$$Length))
+#elif defined ( __ICCARM__ )
+extern char CSTACK$$Base;
+extern char CSTACK$$Length;
+#define STACK_BASE    &CSTACK$$Base
+#define STACK_TOP    ((void*)((uint32_t)STACK_BASE + (uint32_t)&CSTACK$$Length))
+#elif defined   ( __GNUC__ )
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+#define STACK_BASE    &__StackLimit
+#define STACK_TOP     &__StackTop
+#endif
+//lint -restore
+
+enum
+{
+    UNIT_0_625_MS = 625,                                /**< Number of microseconds in 0.625 milliseconds. */
+    UNIT_1_25_MS  = 1250,                               /**< Number of microseconds in 1.25 milliseconds. */
+    UNIT_10_MS    = 10000                               /**< Number of microseconds in 10 milliseconds. */
+};
+
+
+/**@brief Implementation specific macro for delayed macro expansion used in string concatenation
+*
+* @param[in]   lhs   Left hand side in concatenation
+* @param[in]   rhs   Right hand side in concatenation
+*/
+#define STRING_CONCATENATE_IMPL(lhs, rhs) lhs ## rhs
+
+
+/**@brief Macro used to concatenate string using delayed macro expansion
+*
+* @note This macro will delay concatenation until the expressions have been resolved
+*
+* @param[in]   lhs   Left hand side in concatenation
+* @param[in]   rhs   Right hand side in concatenation
+*/
+#define STRING_CONCATENATE(lhs, rhs) STRING_CONCATENATE_IMPL(lhs, rhs)
+
+
+// Disable lint-warnings/errors for STATIC_ASSERT
+//lint --emacro(10,STATIC_ASSERT)
+//lint --emacro(18,STATIC_ASSERT)
+//lint --emacro(19,STATIC_ASSERT)
+//lint --emacro(30,STATIC_ASSERT)
+//lint --emacro(37,STATIC_ASSERT)
+//lint --emacro(42,STATIC_ASSERT)
+//lint --emacro(26,STATIC_ASSERT)
+//lint --emacro(102,STATIC_ASSERT)
+//lint --emacro(533,STATIC_ASSERT)
+//lint --emacro(534,STATIC_ASSERT)
+//lint --emacro(132,STATIC_ASSERT)
+//lint --emacro(414,STATIC_ASSERT)
+//lint --emacro(578,STATIC_ASSERT)
+//lint --emacro(628,STATIC_ASSERT)
+//lint --emacro(648,STATIC_ASSERT)
+//lint --emacro(830,STATIC_ASSERT)
+
+
+/**@brief Macro for doing static (i.e. compile time) assertion.
+*
+* @note If the EXPR isn't resolvable, then the error message won't be shown.
+*
+* @note The output of STATIC_ASSERT will be different across different compilers.
+*
+* @param[in] EXPR Constant expression to be verified.
+*/
+#if defined ( __COUNTER__ )
+
+#define STATIC_ASSERT(EXPR) \
+    ;enum { STRING_CONCATENATE(static_assert_, __COUNTER__) = 1/(!!(EXPR)) }
+
+#else
+
+#define STATIC_ASSERT(EXPR) \
+    ;enum { STRING_CONCATENATE(assert_line_, __LINE__) = 1/(!!(EXPR)) }
+
+#endif
+
+
+/**@brief Implementation details for NUM_VAR_ARGS */
+#define NUM_VA_ARGS_IMPL(                              \
+    _0, _1, _2, _3, _4, _5, _6, _7, _8, _9, _10,       \
+    _11, _12, _13, _14, _15, _16, _17, _18, _19, _20,  \
+    _21, _22, _23, _24, _25, _26, _27, _28, _29, _30,  \
+    _31, _32, _33, _34, _35, _36, _37, _38, _39, _40,  \
+    _41, _42, _43, _44, _45, _46, _47, _48, _49, _50,  \
+    _51, _52, _53, _54, _55, _56, _57, _58, _59, _60,  \
+    _61, _62, N, ...) N
+
+
+/**@brief Macro to get the number of arguments in a call variadic macro call
+ *
+ * param[in]    ...     List of arguments
+ *
+ * @retval  Number of variadic arguments in the argument list
+ */
+#define NUM_VA_ARGS(...) NUM_VA_ARGS_IMPL(__VA_ARGS__, 63, 62, 61,  \
+    60, 59, 58, 57, 56, 55, 54, 53, 52, 51,                         \
+    50, 49, 48, 47, 46, 45, 44, 43, 42, 41,                         \
+    40, 39, 38, 37, 36, 35, 34, 33, 32, 31,                         \
+    30, 29, 28, 27, 26, 25, 24, 23, 22, 21,                         \
+    20, 19, 18, 17, 16, 15, 14, 13, 12, 11,                         \
+    10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0)
+
+
+/**@brief type for holding an encoded (i.e. little endian) 16 bit unsigned integer. */
+typedef uint8_t uint16_le_t[2];
+
+/**@brief Type for holding an encoded (i.e. little endian) 32 bit unsigned integer. */
+typedef uint8_t uint32_le_t[4];
+
+/**@brief Byte array type. */
+typedef struct
+{
+    uint16_t  size;                 /**< Number of array entries. */
+    uint8_t * p_data;               /**< Pointer to array entries. */
+} uint8_array_t;
+
+
+/**@brief Macro for performing rounded integer division (as opposed to truncating the result).
+ *
+ * @param[in]   A   Numerator.
+ * @param[in]   B   Denominator.
+ *
+ * @return      Rounded (integer) result of dividing A by B.
+ */
+#define ROUNDED_DIV(A, B) (((A) + ((B) / 2)) / (B))
+
+
+/**@brief Macro for checking if an integer is a power of two.
+ *
+ * @param[in]   A   Number to be tested.
+ *
+ * @return      true if value is power of two.
+ * @return      false if value not power of two.
+ */
+#define IS_POWER_OF_TWO(A) ( ((A) != 0) && ((((A) - 1) & (A)) == 0) )
+
+
+/**@brief Macro for converting milliseconds to ticks.
+ *
+ * @param[in] TIME          Number of milliseconds to convert.
+ * @param[in] RESOLUTION    Unit to be converted to in [us/ticks].
+ */
+#define MSEC_TO_UNITS(TIME, RESOLUTION) (((TIME) * 1000) / (RESOLUTION))
+
+
+/**@brief Macro for performing integer division, making sure the result is rounded up.
+ *
+ * @details One typical use for this is to compute the number of objects with size B is needed to
+ *          hold A number of bytes.
+ *
+ * @param[in]   A   Numerator.
+ * @param[in]   B   Denominator.
+ *
+ * @return      Integer result of dividing A by B, rounded up.
+ */
+#define CEIL_DIV(A, B)      \
+    (((A) + (B) - 1) / (B))
+
+
+/**@brief Macro for creating a buffer aligned to 4 bytes.
+ *
+ * @param[in]   NAME        Name of the buffor.
+ * @param[in]   MIN_SIZE    Size of this buffor (it will be rounded up to multiples of 4 bytes).
+ */
+#define WORD_ALIGNED_MEM_BUFF(NAME, MIN_SIZE) static uint32_t NAME[CEIL_DIV(MIN_SIZE, sizeof(uint32_t))]
+
+
+/**@brief Macro for calculating the number of words that are needed to hold a number of bytes.
+ *
+ * @details Adds 3 and divides by 4.
+ *
+ * @param[in]  n_bytes  The number of bytes.
+ *
+ * @return The number of words that @p n_bytes take up (rounded up).
+ */
+#define BYTES_TO_WORDS(n_bytes) (((n_bytes) + 3) >> 2)
+
+
+/**@brief The number of bytes in a word.
+ */
+#define BYTES_PER_WORD (4)
+
+
+/**@brief Macro for increasing a number to the nearest (larger) multiple of another number.
+ *
+ * @param[in]  alignment  The number to align to.
+ * @param[in]  number     The number to align (increase).
+ *
+ * @return The aligned (increased) @p number.
+ */
+#define ALIGN_NUM(alignment, number) ((number - 1) + alignment - ((number - 1) % alignment))
+
+
+/**@brief Function for changing the value unit.
+ *
+ * @param[in]   value               Value to be rescaled.
+ * @param[in]   old_unit_reversal   Reversal of the incoming unit.
+ * @param[in]   new_unit_reversal   Reversal of the desired unit.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint64_t value_rescale(uint32_t value, uint32_t old_unit_reversal, uint16_t new_unit_reversal)
+{
+    return (uint64_t)ROUNDED_DIV((uint64_t)value * new_unit_reversal, old_unit_reversal);
+}
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint16_encode(uint16_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x00FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0xFF00) >> 8);
+    return sizeof(uint16_t);
+}
+
+/**@brief Function for encoding a three-byte value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint24_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+    return 3;
+}
+
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint32_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((value & 0x00FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((value & 0xFF000000) >> 24);
+    return sizeof(uint32_t);
+}
+
+/**@brief Function for encoding a uint48 value.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint48_encode(uint64_t value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((value & 0x0000000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((value & 0x00000000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((value & 0x000000FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((value & 0x0000FF000000) >> 24);
+    p_encoded_data[4] = (uint8_t) ((value & 0x00FF00000000) >> 32);
+    p_encoded_data[5] = (uint8_t) ((value & 0xFF0000000000) >> 40);
+    return 6;
+}
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint16_t uint16_decode(const uint8_t * p_encoded_data)
+{
+        return ( (((uint16_t)((uint8_t *)p_encoded_data)[0])) |
+                 (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 ));
+}
+
+/**@brief Function for decoding a uint16 value in big-endian format.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint16_t uint16_big_decode(const uint8_t * p_encoded_data)
+{
+        return ( (((uint16_t)((uint8_t *)p_encoded_data)[0]) << 8 ) |
+                 (((uint16_t)((uint8_t *)p_encoded_data)[1])) );
+}
+
+/**@brief Function for decoding a three-byte value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value (uint32_t).
+ */
+static __INLINE uint32_t uint24_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16));
+}
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint32_t uint32_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+             (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 ));
+}
+
+/**@brief Function for decoding a uint32 value in big-endian format.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value.
+ */
+static __INLINE uint32_t uint32_big_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 24) |
+             (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 16) |
+             (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 8)  |
+             (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 0) );
+}
+
+/**@brief Function for encoding a uint32 value in big-endian format.
+ *
+ * @param[in]   value            Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data will be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t uint32_big_encode(uint32_t value, uint8_t * p_encoded_data)
+{
+#ifdef NRF51
+    p_encoded_data[0] = (uint8_t) ((value & 0xFF000000) >> 24);
+    p_encoded_data[1] = (uint8_t) ((value & 0x00FF0000) >> 16);
+    p_encoded_data[2] = (uint8_t) ((value & 0x0000FF00) >> 8);
+    p_encoded_data[3] = (uint8_t) ((value & 0x000000FF) >> 0);
+#elif NRF52
+    *(uint32_t *)p_encoded_data = __REV(value);
+#endif
+    return sizeof(uint32_t);
+}
+
+/**@brief Function for decoding a uint48 value.
+ *
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ *
+ * @return      Decoded value. (uint64_t)
+ */
+static __INLINE uint64_t uint48_decode(const uint8_t * p_encoded_data)
+{
+    return ( (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+             (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+             (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+             (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24) |
+             (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32) |
+             (((uint64_t)((uint8_t *)p_encoded_data)[5]) << 40 ));
+}
+
+/** @brief Function for converting the input voltage (in milli volts) into percentage of 3.0 Volts.
+ *
+ *  @details The calculation is based on a linearized version of the battery's discharge
+ *           curve. 3.0V returns 100% battery level. The limit for power failure is 2.1V and
+ *           is considered to be the lower boundary.
+ *
+ *           The discharge curve for CR2032 is non-linear. In this model it is split into
+ *           4 linear sections:
+ *           - Section 1: 3.0V - 2.9V = 100% - 42% (58% drop on 100 mV)
+ *           - Section 2: 2.9V - 2.74V = 42% - 18% (24% drop on 160 mV)
+ *           - Section 3: 2.74V - 2.44V = 18% - 6% (12% drop on 300 mV)
+ *           - Section 4: 2.44V - 2.1V = 6% - 0% (6% drop on 340 mV)
+ *
+ *           These numbers are by no means accurate. Temperature and
+ *           load in the actual application is not accounted for!
+ *
+ *  @param[in] mvolts The voltage in mV
+ *
+ *  @return    Battery level in percent.
+*/
+static __INLINE uint8_t battery_level_in_percent(const uint16_t mvolts)
+{
+    uint8_t battery_level;
+
+    if (mvolts >= 3000)
+    {
+        battery_level = 100;
+    }
+    else if (mvolts > 2900)
+    {
+        battery_level = 100 - ((3000 - mvolts) * 58) / 100;
+    }
+    else if (mvolts > 2740)
+    {
+        battery_level = 42 - ((2900 - mvolts) * 24) / 160;
+    }
+    else if (mvolts > 2440)
+    {
+        battery_level = 18 - ((2740 - mvolts) * 12) / 300;
+    }
+    else if (mvolts > 2100)
+    {
+        battery_level = 6 - ((2440 - mvolts) * 6) / 340;
+    }
+    else
+    {
+        battery_level = 0;
+    }
+
+    return battery_level;
+}
+
+/**@brief Function for checking if a pointer value is aligned to a 4 byte boundary.
+ *
+ * @param[in]   p   Pointer value to be checked.
+ *
+ * @return      TRUE if pointer is aligned to a 4 byte boundary, FALSE otherwise.
+ */
+static __INLINE bool is_word_aligned(void const* p)
+{
+    return (((uintptr_t)p & 0x03) == 0);
+}
+
+/**
+ * @brief Function for checking if provided address is located in stack space.
+ *
+ * @param[in]   ptr Pointer to be checked.
+ *
+ * @return      true if address is in stack space, false otherwise.
+ */
+static __INLINE bool is_address_from_stack(void * ptr)
+{
+    if (((uint32_t)ptr >= (uint32_t)STACK_BASE) &&
+        ((uint32_t)ptr <  (uint32_t)STACK_TOP) )
+    {
+        return true;
+    }
+    else
+    {
+        return false;
+    }
+}
+
+#endif // APP_UTIL_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_bds.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_bds.h
new file mode 100644
index 0000000000..96467e3d89
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_bds.h
@@ -0,0 +1,440 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup app_util Utility Functions and Definitions
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications.
+ */
+
+#ifndef APP_UTIL_BDS_H__
+#define APP_UTIL_BDS_H__
+
+#include <stdint.h>
+#include <string.h>
+#include <stdbool.h>
+#include "compiler_abstraction.h"
+#include "app_util.h"
+#include "ble_srv_common.h"
+#include "nordic_common.h"
+    
+typedef uint8_t nibble_t;
+typedef uint32_t uint24_t;
+typedef uint64_t uint40_t;
+
+/**@brief IEEE 11073-20601 Regulatory Certification Data List Structure */
+typedef struct
+{
+    uint8_t *  p_list;                                          /**< Pointer the byte array containing the encoded opaque structure based on IEEE 11073-20601 specification. */
+    uint8_t    list_len;                                        /**< Length of the byte array. */
+} regcertdatalist_t;
+
+/**@brief SFLOAT format (IEEE-11073 16-bit FLOAT, meaning 4 bits for exponent (base 10) and 12 bits mantissa) */
+typedef struct
+{
+  int8_t exponent;                                             /**< Base 10 exponent, should be using only 4 bits */
+  int16_t mantissa;                                            /**< Mantissa, should be using only 12 bits */
+} sfloat_t;
+
+/**@brief Date and Time structure. */
+typedef struct
+{
+    uint16_t year;
+    uint8_t  month;
+    uint8_t  day;
+    uint8_t  hours;
+    uint8_t  minutes;
+    uint8_t  seconds;
+} ble_date_time_t;
+
+
+/**@brief Function for encoding a uint16 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint16_encode(const uint16_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x00FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0xFF00) >> 8);
+    return sizeof(uint16_t);
+}
+
+static __INLINE uint8_t bds_int16_encode(const int16_t * p_value, uint8_t * p_encoded_data)
+{
+    uint16_t tmp = *p_value;
+    return bds_uint16_encode(&tmp, p_encoded_data);
+}
+
+/**@brief Function for encoding a uint24 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint24_encode(const uint32_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16);
+    return (3);
+}
+
+    
+/**@brief Function for encoding a uint32 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint32_encode(const uint32_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0x0000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((*p_value & 0x00FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((*p_value & 0xFF000000) >> 24);
+    return sizeof(uint32_t);
+}
+
+    
+/**@brief Function for encoding a uint40 value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_uint40_encode(const uint64_t * p_value, uint8_t * p_encoded_data)
+{
+    p_encoded_data[0] = (uint8_t) ((*p_value & 0x00000000000000FF) >> 0);
+    p_encoded_data[1] = (uint8_t) ((*p_value & 0x000000000000FF00) >> 8);
+    p_encoded_data[2] = (uint8_t) ((*p_value & 0x0000000000FF0000) >> 16);
+    p_encoded_data[3] = (uint8_t) ((*p_value & 0x00000000FF000000) >> 24);
+    p_encoded_data[4] = (uint8_t) ((*p_value & 0x000000FF00000000) >> 32);
+    return 5;
+}
+
+/**@brief Function for encoding a sfloat value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ *
+ * @return      Number of bytes written.
+ */
+static __INLINE uint8_t bds_sfloat_encode(const sfloat_t * p_value, uint8_t * p_encoded_data)
+{
+    uint16_t encoded_val;
+
+    encoded_val = ((p_value->exponent << 12) & 0xF000) |
+                            ((p_value->mantissa <<  0) & 0x0FFF);
+
+    return(bds_uint16_encode(&encoded_val, p_encoded_data));
+}
+
+
+/**@brief Function for encoding a uint8_array value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+ */
+static __INLINE uint8_t bds_uint8_array_encode(const uint8_array_t * p_value, 
+                                               uint8_t             * p_encoded_data)
+{
+    memcpy(p_encoded_data, p_value->p_data, p_value->size);
+    return p_value->size;
+}    
+
+
+/**@brief Function for encoding a utf8_str value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+
+ */
+static __INLINE uint8_t bds_ble_srv_utf8_str_encode(const ble_srv_utf8_str_t * p_value,
+                                                    uint8_t                  * p_encoded_data)
+{
+    memcpy(p_encoded_data, p_value->p_str, p_value->length);
+    return p_value->length;
+}    
+
+/**@brief Function for encoding a regcertdatalist value.
+ *
+ * @param[in]   p_value          Value to be encoded.
+ * @param[out]  p_encoded_data   Buffer where the encoded data is to be written.
+
+ */
+static __INLINE uint8_t bds_regcertdatalist_encode(const regcertdatalist_t * p_value, 
+                                                   uint8_t                 * p_encoded_data)
+{
+    memcpy(p_encoded_data, p_value->p_list, p_value->list_len);
+    return p_value->list_len;
+}    
+
+
+/**@brief Function for decoding a date_time value.
+ *
+ * @param[in]   p_date_time    pointer to the date_time structure to encode.
+ * @param[in]   p_encoded_data pointer to the encoded data
+ * @return      length of the encoded field.
+ */
+static __INLINE uint8_t bds_ble_date_time_encode(const ble_date_time_t * p_date_time,
+                                                 uint8_t               * p_encoded_data)
+{
+    uint8_t len = bds_uint16_encode(&p_date_time->year, &p_encoded_data[0]);
+    
+    p_encoded_data[len++] = p_date_time->month;
+    p_encoded_data[len++] = p_date_time->day;
+    p_encoded_data[len++] = p_date_time->hours;
+    p_encoded_data[len++] = p_date_time->minutes;
+    p_encoded_data[len++] = p_date_time->seconds;
+    
+    return len;
+}
+
+
+/**@brief Function for decoding a uint16 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint16_decode(const uint8_t len, 
+                                          const uint8_t * p_encoded_data, 
+                                          uint16_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint16_t)((uint8_t *)p_encoded_data)[0])) | 
+                     (((uint16_t)((uint8_t *)p_encoded_data)[1]) << 8 );
+    return (sizeof(uint16_t));
+}
+
+
+/**@brief Function for decoding a int16 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_int16_decode(const uint8_t len, 
+                                         const uint8_t * p_encoded_data, 
+                                         int16_t       * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    uint16_t tmp = 0;
+    uint8_t retval = bds_uint16_decode(len, p_encoded_data, &tmp);
+    *p_decoded_val = (int16_t)tmp;
+    return retval;
+}
+
+
+/**@brief Function for decoding a uint24 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint24_decode(const uint8_t len, 
+                                          const uint8_t * p_encoded_data, 
+                                          uint32_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16);
+    return (3);
+}
+
+
+/**@brief Function for decoding a uint32 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint32_decode(const uint8_t len, 
+                                          const uint8_t * p_encoded_data, 
+                                          uint32_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint32_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+                     (((uint32_t)((uint8_t *)p_encoded_data)[3]) << 24 );
+    return (sizeof(uint32_t));
+}
+
+
+/**@brief Function for decoding a uint40 value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint40_decode(const uint8_t len, 
+                                          const uint8_t * p_encoded_data, 
+                                          uint64_t      * p_decoded_val)
+{
+    UNUSED_VARIABLE(len);
+    *p_decoded_val = (((uint64_t)((uint8_t *)p_encoded_data)[0]) << 0)  |
+                     (((uint64_t)((uint8_t *)p_encoded_data)[1]) << 8)  |
+                     (((uint64_t)((uint8_t *)p_encoded_data)[2]) << 16) |
+                     (((uint64_t)((uint8_t *)p_encoded_data)[3]) << 24 )|
+                     (((uint64_t)((uint8_t *)p_encoded_data)[4]) << 32 );
+    return (40);
+}
+
+
+/**@brief Function for decoding a sfloat value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+
+ */
+static __INLINE uint8_t bds_sfloat_decode(const uint8_t len, 
+                                          const uint8_t * p_encoded_data, 
+                                          sfloat_t      * p_decoded_val)
+{
+    
+    p_decoded_val->exponent = 0;
+    bds_uint16_decode(len, p_encoded_data, (uint16_t*)&p_decoded_val->mantissa);
+    p_decoded_val->exponent = (uint8_t)((p_decoded_val->mantissa & 0xF000) >> 12);
+    p_decoded_val->mantissa &= 0x0FFF;
+    return len;
+}
+
+
+/**@brief Function for decoding a uint8_array value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_uint8_array_decode(const uint8_t len, 
+                                               const uint8_t * p_encoded_data,
+                                               uint8_array_t * p_decoded_val)
+{
+    memcpy(p_decoded_val->p_data, p_encoded_data, len);
+    p_decoded_val->size = len;
+    return p_decoded_val->size;
+}   
+
+
+/**@brief Function for decoding a utf8_str value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_ble_srv_utf8_str_decode(const uint8_t      len, 
+                                                    const uint8_t      * p_encoded_data, 
+                                                    ble_srv_utf8_str_t * p_decoded_val)
+{
+    p_decoded_val->p_str = (uint8_t*)p_encoded_data;
+    p_decoded_val->length = len;
+    return p_decoded_val->length;
+}   
+
+
+/**@brief Function for decoding a regcertdatalist value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_decoded_val    pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_regcertdatalist_decode(const uint8_t     len, 
+                                                   const uint8_t     * p_encoded_data, 
+                                                   regcertdatalist_t * p_decoded_val)
+{
+    memcpy(p_decoded_val->p_list, p_encoded_data, len);
+    p_decoded_val->list_len = len;
+    return p_decoded_val->list_len;
+}    
+
+
+/**@brief Function for decoding a date_time value.
+ *
+ * @param[in]   len              length of the field to be decoded.
+ * @param[in]   p_encoded_data   Buffer where the encoded data is stored.
+ * @param[in]   p_date_time      pointer to the decoded value
+ *
+ * @return      length of the decoded field.
+ */
+static __INLINE uint8_t bds_ble_date_time_decode(const uint8_t   len, 
+                                                 const uint8_t   * p_encoded_data, 
+                                                 ble_date_time_t * p_date_time)
+{
+    UNUSED_VARIABLE(len);
+    uint8_t pos          = bds_uint16_decode(len, &p_encoded_data[0], &p_date_time->year);
+    p_date_time->month   = p_encoded_data[pos++];
+    p_date_time->day     = p_encoded_data[pos++];
+    p_date_time->hours   = p_encoded_data[pos++];
+    p_date_time->minutes = p_encoded_data[pos++];
+    p_date_time->seconds = p_encoded_data[pos++];
+
+    return pos;
+}
+
+#endif // APP_UTIL_BDS_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.c
new file mode 100644
index 0000000000..8683b50efc
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.c
@@ -0,0 +1,87 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "app_util_platform.h"
+
+static uint32_t m_in_critical_region = 0;
+
+void app_util_disable_irq(void)
+{
+    __disable_irq();    
+    m_in_critical_region++;    
+}
+
+void app_util_enable_irq(void)
+{
+    m_in_critical_region--;    
+    if (m_in_critical_region == 0)
+    {
+        __enable_irq();
+    }
+}
+
+void app_util_critical_region_enter(uint8_t *p_nested)
+{
+#ifdef NRF52
+    ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
+#endif
+
+#if defined(SOFTDEVICE_PRESENT)
+    /* return value can be safely ignored */
+    (void) sd_nvic_critical_region_enter(p_nested);
+#else
+    app_util_disable_irq();
+#endif
+}
+
+void app_util_critical_region_exit(uint8_t nested)
+{
+#ifdef NRF52
+    ASSERT(APP_LEVEL_PRIVILEGED == privilege_level_get())
+#endif
+
+#if defined(SOFTDEVICE_PRESENT)
+    /* return value can be safely ignored */
+    (void) sd_nvic_critical_region_exit(nested);
+#else
+    app_util_enable_irq();
+#endif
+}
+
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.h
new file mode 100644
index 0000000000..a01b26d0e7
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/app_util_platform.h
@@ -0,0 +1,238 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup app_util_platform Utility Functions and Definitions (Platform)
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Various types and definitions available to all applications when using SoftDevice.
+ */
+
+#ifndef APP_UTIL_PLATFORM_H__
+#define APP_UTIL_PLATFORM_H__
+
+#include <stdint.h>
+#include "compiler_abstraction.h"
+#include "nrf.h"
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_soc.h"
+#include "nrf_nvic.h"
+#endif
+#include "nrf_assert.h"
+#include "app_error.h"
+
+#if defined(NRF51)
+#define _PRIO_SD_HIGH       0
+#define _PRIO_APP_HIGH      1
+#define _PRIO_APP_MID       1
+#define _PRIO_SD_LOW        2
+#define _PRIO_APP_LOW       3
+#define _PRIO_APP_LOWEST    3
+#define _PRIO_THREAD        4
+#elif defined(NRF52)
+#define _PRIO_SD_HIGH       0
+#define _PRIO_SD_MID        1
+#define _PRIO_APP_HIGH      2
+#define _PRIO_APP_MID       3
+#define _PRIO_SD_LOW        4
+#define _PRIO_SD_LOWEST     5
+#define _PRIO_APP_LOW       6
+#define _PRIO_APP_LOWEST    7
+#define _PRIO_THREAD        15
+#else
+    #error "No platform defined"
+#endif
+
+/**@brief The interrupt priorities available to the application while the SoftDevice is active. */
+typedef enum
+{
+#ifdef SOFTDEVICE_PRESENT
+    APP_IRQ_PRIORITY_HIGHEST = _PRIO_SD_HIGH,
+#else
+    APP_IRQ_PRIORITY_HIGHEST = _PRIO_APP_HIGH,
+#endif
+    APP_IRQ_PRIORITY_HIGH    = _PRIO_APP_HIGH,
+#ifndef SOFTDEVICE_PRESENT
+    APP_IRQ_PRIORITY_MID     = _PRIO_SD_LOW,
+#else
+    APP_IRQ_PRIORITY_MID     = _PRIO_APP_MID,
+#endif
+    APP_IRQ_PRIORITY_LOW     = _PRIO_APP_LOW,
+    APP_IRQ_PRIORITY_LOWEST  = _PRIO_APP_LOWEST,
+    APP_IRQ_PRIORITY_THREAD  = _PRIO_THREAD     /**< "Interrupt level" when running in Thread Mode. */
+} app_irq_priority_t;
+
+/*@brief The privilege levels available to applications in Thread Mode */
+typedef enum
+{
+    APP_LEVEL_UNPRIVILEGED,
+    APP_LEVEL_PRIVILEGED
+} app_level_t;
+
+/**@cond NO_DOXYGEN */
+#define EXTERNAL_INT_VECTOR_OFFSET 16
+/**@endcond */
+
+#define PACKED(TYPE) __packed TYPE
+
+void app_util_critical_region_enter (uint8_t *p_nested);
+void app_util_critical_region_exit (uint8_t nested);
+
+/**@brief Macro for entering a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ *       CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ *       in the same scope.
+ */
+#ifdef SOFTDEVICE_PRESENT
+#define CRITICAL_REGION_ENTER()                                                             \
+    {                                                                                       \
+        uint8_t __CR_NESTED = 0;                                                            \
+        app_util_critical_region_enter(&__CR_NESTED);
+#else
+#define CRITICAL_REGION_ENTER() app_util_critical_region_enter(NULL)
+#endif
+
+/**@brief Macro for leaving a critical region.
+ *
+ * @note Due to implementation details, there must exist one and only one call to
+ *       CRITICAL_REGION_EXIT() for each call to CRITICAL_REGION_ENTER(), and they must be located
+ *       in the same scope.
+ */
+#ifdef SOFTDEVICE_PRESENT
+#define CRITICAL_REGION_EXIT()                                                              \
+        app_util_critical_region_exit(__CR_NESTED);                                         \
+    }
+#else
+#define CRITICAL_REGION_EXIT() app_util_critical_region_exit(0)
+#endif 
+
+/* Workaround for Keil 4 */
+#ifndef IPSR_ISR_Msk
+#define IPSR_ISR_Msk                       (0x1FFUL /*<< IPSR_ISR_Pos*/)                  /*!< IPSR: ISR Mask */
+#endif
+       
+
+
+/**@brief Macro to enable anonymous unions from a certain point in the code.
+ */
+#if defined(__CC_ARM)
+    #define ANON_UNIONS_ENABLE _Pragma("push") \
+                               _Pragma("anon_unions")
+#elif defined(__ICCARM__)
+    #define ANON_UNIONS_ENABLE _Pragma("language=extended")
+#else
+    #define ANON_UNIONS_ENABLE
+    // No action will be taken.
+    // For GCC anonymous unions are enabled by default.
+#endif
+
+/**@brief Macro to disable anonymous unions from a certain point in the code.
+ * @note Call only after first calling @ref ANON_UNIONS_ENABLE.
+ */
+#if defined(__CC_ARM)
+    #define ANON_UNIONS_DISABLE _Pragma("pop")
+#elif defined(__ICCARM__)
+    #define ANON_UNIONS_DISABLE
+    // for IAR leave anonymous unions enabled
+#else
+    #define ANON_UNIONS_DISABLE
+    // No action will be taken.
+    // For GCC anonymous unions are enabled by default.
+#endif
+
+
+/* Workaround for Keil 4 */
+#ifndef CONTROL_nPRIV_Msk
+#define CONTROL_nPRIV_Msk                  (1UL /*<< CONTROL_nPRIV_Pos*/)                 /*!< CONTROL: nPRIV Mask */
+#endif
+
+/**@brief Function for finding the current interrupt level.
+ *
+ * @return   Current interrupt level.
+ * @retval   APP_IRQ_PRIORITY_HIGH    We are running in Application High interrupt level.
+ * @retval   APP_IRQ_PRIORITY_LOW     We are running in Application Low interrupt level.
+ * @retval   APP_IRQ_PRIORITY_THREAD  We are running in Thread Mode.
+ */
+static __INLINE uint8_t current_int_priority_get(void)
+{
+    uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
+    if (isr_vector_num > 0)
+    {
+        int32_t irq_type = ((int32_t)isr_vector_num - EXTERNAL_INT_VECTOR_OFFSET);
+        return (NVIC_GetPriority((IRQn_Type)irq_type) & 0xFF);
+    }
+    else
+    {
+        return APP_IRQ_PRIORITY_THREAD;
+    }
+}
+
+/**@brief Function for finding out the current privilege level.
+ *
+ * @return   Current privilege level.
+ * @retval   APP_LEVEL_UNPRIVILEGED    We are running in unprivileged level.
+ * @retval   APP_LEVEL_PRIVILEGED    We are running in privileged level.
+ */
+static __INLINE uint8_t privilege_level_get(void)
+{
+#if defined(NRF51)
+    /* the Cortex-M0 has no concept of privilege */
+    return APP_LEVEL_PRIVILEGED;
+#elif defined(NRF52)
+    uint32_t isr_vector_num = __get_IPSR() & IPSR_ISR_Msk ;
+    if (0 == isr_vector_num)
+    {
+        /* Thread Mode, check nPRIV */
+        int32_t control = __get_CONTROL();
+        return control & CONTROL_nPRIV_Msk ? APP_LEVEL_UNPRIVILEGED : APP_LEVEL_PRIVILEGED;
+    }
+    else
+    {
+        /* Handler Mode, always privileged */
+        return APP_LEVEL_PRIVILEGED;
+    }
+#endif
+}
+
+#endif // APP_UTIL_PLATFORM_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/common.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/common.h
new file mode 100644
index 0000000000..acd5a9c5df
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/common.h
@@ -0,0 +1,65 @@
+ /* 
+ * Copyright (c) 2009 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef COMMON_H
+#define COMMON_H
+
+/*lint ++flb "Enter library region" */
+
+#include <stdbool.h>
+#include <stdint.h>
+
+/* @file
+* @brief Common header file for generic macros and definitions
+ *
+ */
+
+/*
+ * GPIO glue macros, this can be used to define a pin number in source/header file and use that macro for pin
+ * configuration using this expansion.
+ * example:
+ * #define RESET_PIN    8
+ * NRF_GPIO->PINCNF(RESET_PIN) = XXX  ;  // Expanded NRF_GPIO->PIN_CNF[8] = XXX
+ */
+#define PINX_GLUE(x, y, z)       x##y##_##z            /*!< first level glue for pin macros */
+#define PINCNF(p)                PINX_GLUE(PIN,p,CNF)  /*!< gpio configure pin number 'p' */
+#define PINOUT(p)                PINX_GLUE(PIN,p,OUT)  /*!< gpio out pin number 'p' */
+
+/*lint --flb "Leave library region" */
+#endif
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nordic_common.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nordic_common.h
new file mode 100644
index 0000000000..f0e725bc06
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nordic_common.h
@@ -0,0 +1,136 @@
+/* 
+ * Copyright (c) 2008 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ * @brief Common defines and macros for firmware developed by Nordic Semiconductor.
+ */
+
+#ifndef NORDIC_COMMON_H__
+#define NORDIC_COMMON_H__
+
+/** The upper 8 bits of a 32 bit value */
+//lint -emacro(572,MSB) // Suppress warning 572 "Excessive shift value"
+#define MSB_32(a) (((a) & 0xFF000000) >> 24)
+/** The lower 8 bits (of a 32 bit value) */
+#define LSB_32(a) ((a) & 0x000000FF)
+
+/** The upper 8 bits of a 16 bit value */
+//lint -emacro(572,MSB_16) // Suppress warning 572 "Excessive shift value"
+#define MSB_16(a) (((a) & 0xFF00) >> 8)
+/** The lower 8 bits (of a 16 bit value) */
+#define LSB_16(a) ((a) & 0x00FF)
+
+/** Leaves the minimum of the two 32-bit arguments */
+/*lint -emacro(506, MIN) */ /* Suppress "Constant value Boolean */
+#define MIN(a, b) ((a) < (b) ? (a) : (b))
+/** Leaves the maximum of the two 32-bit arguments */
+/*lint -emacro(506, MAX) */ /* Suppress "Constant value Boolean */
+#define MAX(a, b) ((a) < (b) ? (b) : (a))
+
+/** Concatenates two parameters. Useful as a second level of indirection,
+ *  when a parameter can be macro itself. */
+#define CONCAT_2(p1, p2)      p1##p2
+/** Concatenates three parameters. Useful as a second level of indirection,
+ *  when a parameter can be macro itself. */
+#define CONCAT_3(p1, p2, p3)  p1##p2##p3
+
+/**@brief Set a bit in the uint32 word.
+ *
+ * @param[in] W  Word whose bit is being set.
+ * @param[in] B  Bit number in the word to be set.
+ */
+#define SET_BIT(W,B)  ((W) |= (uint32_t)(1U << (B)))
+
+
+/**@brief Clears a bit in the uint32 word.
+ *
+ * @param[in] W   Word whose bit is to be cleared.
+ * @param[in] B   Bit number in the word to be cleared.
+ */
+#define CLR_BIT(W, B) ((W) &= (~((uint32_t)1 << (B))))
+
+
+/**@brief Checks if a bit is set.
+ *
+ * @param[in] W   Word whose bit is to be checked.
+ * @param[in] B   Bit number in the word to be checked.
+ *
+ * @retval 1 if bit is set.
+ * @retval 0 if bit is not set.
+ */
+#define IS_SET(W,B) (((W) >> (B)) & 1)
+
+#define BIT_0 0x01 /**< The value of bit 0 */
+#define BIT_1 0x02 /**< The value of bit 1 */
+#define BIT_2 0x04 /**< The value of bit 2 */
+#define BIT_3 0x08 /**< The value of bit 3 */
+#define BIT_4 0x10 /**< The value of bit 4 */
+#define BIT_5 0x20 /**< The value of bit 5 */
+#define BIT_6 0x40 /**< The value of bit 6 */
+#define BIT_7 0x80 /**< The value of bit 7 */
+#define BIT_8 0x0100 /**< The value of bit 8 */
+#define BIT_9 0x0200 /**< The value of bit 9 */
+#define BIT_10 0x0400 /**< The value of bit 10 */
+#define BIT_11 0x0800 /**< The value of bit 11 */
+#define BIT_12 0x1000 /**< The value of bit 12 */
+#define BIT_13 0x2000 /**< The value of bit 13 */
+#define BIT_14 0x4000 /**< The value of bit 14 */
+#define BIT_15 0x8000 /**< The value of bit 15 */
+#define BIT_16 0x00010000 /**< The value of bit 16 */
+#define BIT_17 0x00020000 /**< The value of bit 17 */
+#define BIT_18 0x00040000 /**< The value of bit 18 */
+#define BIT_19 0x00080000 /**< The value of bit 19 */
+#define BIT_20 0x00100000 /**< The value of bit 20 */
+#define BIT_21 0x00200000 /**< The value of bit 21 */
+#define BIT_22 0x00400000 /**< The value of bit 22 */
+#define BIT_23 0x00800000 /**< The value of bit 23 */
+#define BIT_24 0x01000000 /**< The value of bit 24 */
+#define BIT_25 0x02000000 /**< The value of bit 25 */
+#define BIT_26 0x04000000 /**< The value of bit 26 */
+#define BIT_27 0x08000000 /**< The value of bit 27 */
+#define BIT_28 0x10000000 /**< The value of bit 28 */
+#define BIT_29 0x20000000 /**< The value of bit 29 */
+#define BIT_30 0x40000000 /**< The value of bit 30 */
+#define BIT_31 0x80000000 /**< The value of bit 31 */
+
+#define UNUSED_VARIABLE(X)  ((void)(X))
+#define UNUSED_PARAMETER(X) UNUSED_VARIABLE(X)
+#define UNUSED_RETURN_VALUE(X) UNUSED_VARIABLE(X)
+
+#endif // NORDIC_COMMON_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.c
new file mode 100644
index 0000000000..23ba8f76cb
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.c
@@ -0,0 +1,55 @@
+/* 
+ * Copyright (c) 2006 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "nrf_assert.h"
+#include "app_error.h"
+#include "nordic_common.h"
+
+#if defined(DEBUG_NRF)
+void assert_nrf_callback(uint16_t line_num, const uint8_t * file_name)
+{
+    assert_info_t assert_info =
+    {
+        .line_num    = line_num,
+        .p_file_name = file_name,
+    };
+    app_error_fault_handler(NRF_FAULT_ID_SDK_ASSERT, 0, (uint32_t)(&assert_info));
+
+    UNUSED_VARIABLE(assert_info);
+}
+#endif /* DEBUG_NRF */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.h
new file mode 100644
index 0000000000..8ef5a5d501
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_assert.h
@@ -0,0 +1,100 @@
+/* 
+ * Copyright (c) 2006 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ * @brief Utilities for verifying program logic
+ */
+
+#ifndef NRF_ASSERT_H_
+#define NRF_ASSERT_H_
+
+#include <stdint.h>
+#include "nrf.h"
+#include "app_error.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if defined(DEBUG_NRF) || defined(DEBUG_NRF_USER)
+
+/** @brief Function for handling assertions.
+ *
+ *
+ * @note
+ * This function is called when an assertion has triggered.
+ *
+ *
+ * @post
+ * All hardware is put into an idle non-emitting state (in particular the radio is highly
+ * important to switch off since the radio might be in a state that makes it send
+ * packets continiously while a typical final infinit ASSERT loop is executing).
+ *
+ *
+ * @param line_num The line number where the assertion is called
+ * @param file_name Pointer to the file name
+ */
+void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name);
+
+/*lint -emacro(506, ASSERT) */ /* Suppress "Constant value Boolean */
+/*lint -emacro(774, ASSERT) */ /* Suppress "Boolean within 'if' always evaluates to True" */ \
+
+/** @brief Function for checking intended for production code.
+ *
+ * Check passes if "expr" evaluates to true. */
+#define ASSERT(expr) \
+if (expr)                                                                     \
+{                                                                             \
+}                                                                             \
+else                                                                          \
+{                                                                             \
+    assert_nrf_callback((uint16_t)__LINE__, (uint8_t *)__FILE__);             \
+}
+#else
+#ifndef ASSERT
+#define ASSERT(expr) //!< Assert empty when disabled
+__WEAK void assert_nrf_callback(uint16_t line_num, const uint8_t *file_name);
+#endif
+#endif /* defined(DEBUG_NRF) || defined(DEBUG_NRF_USER) */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_ASSERT_H_ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c
new file mode 100644
index 0000000000..e3d1600387
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.c
@@ -0,0 +1,425 @@
+#include "nrf.h"
+#include "nrf_log.h"
+#include "nrf_error.h"
+#include <stdarg.h>
+#include <string.h>
+#include <stdio.h>
+
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+
+#include <SEGGER_RTT_Conf.h>
+#include <SEGGER_RTT.h>
+
+static char buf_normal_up[BUFFER_SIZE_UP];
+static char buf_down[BUFFER_SIZE_DOWN];
+
+uint32_t log_rtt_init(void)
+{
+    static bool initialized = false;
+    if (initialized)
+    {
+        return NRF_SUCCESS;
+    }
+
+    if (SEGGER_RTT_ConfigUpBuffer(LOG_TERMINAL_NORMAL,
+                                  "Normal",
+                                  buf_normal_up,
+                                  BUFFER_SIZE_UP,
+                                  SEGGER_RTT_MODE_NO_BLOCK_TRIM
+                                 )
+        != 0)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    if (SEGGER_RTT_ConfigDownBuffer(LOG_TERMINAL_INPUT,
+                                   "Input",
+                                   buf_down,
+                                   BUFFER_SIZE_DOWN,
+                                   SEGGER_RTT_MODE_NO_BLOCK_SKIP
+                                  )
+        != 0)
+    {
+        return NRF_ERROR_INVALID_STATE;
+    }
+
+    initialized = true;
+
+    return NRF_SUCCESS;
+}
+
+// Forward declaration of SEGGER RTT vprintf function
+int SEGGER_RTT_vprintf(unsigned BufferIndex, const char * sFormat, va_list * pParamList);
+
+void log_rtt_printf(int terminal_index, char * format_msg, ...)
+{
+    //lint -save -e526 -e628 -e530
+    va_list p_args;
+    va_start(p_args, format_msg);
+    (void)SEGGER_RTT_vprintf(terminal_index, format_msg, &p_args);
+    va_end(p_args);
+    //lint -restore
+}
+
+__INLINE void log_rtt_write_string(int terminal_index, int num_args, ...)
+{
+    const char* msg;
+    //lint -save -e516 -e530
+    va_list p_args;
+    va_start(p_args, num_args);
+    //lint -restore
+
+    for (int i = 0; i < num_args; i++)
+    {
+        //lint -save -e26 -e10 -e64 -e526 -e628 -e530
+        msg = va_arg(p_args, const char*);
+        //lint -restore
+        (void)SEGGER_RTT_WriteString(terminal_index, msg);
+    }
+    va_end(p_args);
+}
+
+void log_rtt_write_hex(int terminal_index, uint32_t value)
+{
+    char temp[11];
+    temp[0] = '0';
+    temp[1] = 'x';
+    temp[10] = 0; // Null termination
+    uint8_t nibble;
+    uint8_t i = 8;
+
+    while(i-- != 0)
+    {
+        nibble = (value >> (4 * i)) & 0x0F;
+        temp[9-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble);
+    }
+
+    (void)SEGGER_RTT_WriteString(terminal_index, temp);
+}
+
+void log_rtt_write_hex_char(int terminal_index, uint8_t value)
+{
+    char temp[3];
+    temp[2] = 0; // Null termination
+    uint8_t nibble;
+    uint8_t i = 2;
+
+    while(i-- != 0)
+    {
+        nibble = (value >> (4 * i)) & 0x0F;
+        temp[1-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble);
+    }
+
+    (void)SEGGER_RTT_WriteString(terminal_index, temp);
+}
+
+__INLINE int log_rtt_has_input()
+{
+    return SEGGER_RTT_HasKey();
+}
+
+uint32_t log_rtt_read_input(char * c)
+{
+    int r;
+
+    r = SEGGER_RTT_Read(LOG_TERMINAL_INPUT, c, 1);
+    if (r == 1)
+        return NRF_SUCCESS;
+    else
+        return NRF_ERROR_NULL;
+}
+
+#elif defined(NRF_LOG_USES_UART) && NRF_LOG_USES_UART == 1
+
+#include "app_uart.h"
+#include "app_error.h"
+#include <stdio.h>
+#include <string.h>
+#include "nrf.h"
+#include "bsp.h"
+
+#define MAX_TEST_DATA_BYTES     (15U)                /**< max number of test bytes to be used for tx and rx. */
+#define UART_TX_BUF_SIZE 512                         /**< UART TX buffer size. */
+#define UART_RX_BUF_SIZE 1                           /**< UART RX buffer size. */
+
+static uint8_t m_uart_data;
+static bool m_uart_has_input;
+
+void uart_error_cb(app_uart_evt_t * p_event)
+{
+    if (p_event->evt_type == APP_UART_COMMUNICATION_ERROR)
+    {
+        APP_ERROR_HANDLER(p_event->data.error_communication);
+    }
+    else if (p_event->evt_type == APP_UART_FIFO_ERROR)
+    {
+        APP_ERROR_HANDLER(p_event->data.error_code);
+    }
+}
+
+uint32_t log_uart_init()
+{
+    static bool initialized = false;
+    if (initialized)
+    {
+        return NRF_SUCCESS;
+    }
+
+    uint32_t err_code;
+    const app_uart_comm_params_t comm_params =
+    {
+        RX_PIN_NUMBER,
+        TX_PIN_NUMBER,
+        RTS_PIN_NUMBER,
+        CTS_PIN_NUMBER,
+        APP_UART_FLOW_CONTROL_ENABLED,
+        false,
+        UART_BAUDRATE_BAUDRATE_Baud115200
+    };
+
+    APP_UART_FIFO_INIT(&comm_params,
+                         UART_RX_BUF_SIZE,
+                         UART_TX_BUF_SIZE,
+                         uart_error_cb,
+                         APP_IRQ_PRIORITY_LOW,
+                         err_code);
+
+    initialized = true;
+
+    return err_code;
+}
+
+//lint -save -e530 -e64
+void log_uart_printf(const char * format_msg, ...)
+{
+    va_list p_args;
+    va_start(p_args, format_msg);
+    (void)vprintf(format_msg, p_args);
+    va_end(p_args);
+}
+
+__INLINE void log_uart_write_string_many(int num_args, ...)
+{
+    const char* msg;
+    va_list p_args;
+    va_start(p_args, num_args);
+
+    for (int i = 0; i < num_args; i++)
+    {
+        msg = va_arg(p_args, const char*);
+        log_uart_write_string(msg);
+    }
+    va_end(p_args);
+}
+
+__INLINE void log_uart_write_string(const char* msg)
+{
+    while( *msg )
+    {
+        (void)app_uart_put(*msg++);
+    }
+}
+//lint -restore
+
+void log_uart_write_hex(uint32_t value)
+{
+    uint8_t nibble;
+    uint8_t i = 8;
+
+    (void)app_uart_put('0');
+    (void)app_uart_put('x');
+    while( i-- != 0 )
+    {
+        nibble = (value >> (4 * i)) & 0x0F;
+        (void)app_uart_put( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) );
+    }
+}
+
+void log_uart_write_hex_char(uint8_t c)
+{
+    uint8_t nibble;
+    uint8_t i = 2;
+
+    while( i-- != 0 )
+    {
+        nibble = (c >> (4 * i)) & 0x0F;
+        (void)app_uart_put( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) );
+    }
+}
+
+__INLINE int log_uart_has_input()
+{
+    if (m_uart_has_input) return 1;
+    if (app_uart_get(&m_uart_data) == NRF_SUCCESS)
+    {
+        m_uart_has_input = true;
+        return 1;
+    }
+    return 0;
+}
+
+uint32_t log_uart_read_input(char * c)
+{
+    if (m_uart_has_input)
+    {
+        *c = (char)m_uart_data;
+        m_uart_has_input = false;
+        return NRF_SUCCESS;
+    }
+    if (app_uart_get((uint8_t *)c) == NRF_SUCCESS)
+    {
+        return NRF_SUCCESS;
+    }
+    return NRF_ERROR_NULL;
+}
+
+#elif defined(NRF_LOG_USES_RAW_UART) && NRF_LOG_USES_RAW_UART == 1
+
+#include "app_uart.h"
+#include <stdio.h>
+#include <string.h>
+#include "bsp.h"
+
+uint32_t log_raw_uart_init()
+{
+    // Disable UART
+    NRF_UART0->ENABLE = UART_ENABLE_ENABLE_Disabled;
+
+    // Configure RX/TX pins
+    nrf_gpio_cfg_output( TX_PIN_NUMBER );
+    nrf_gpio_cfg_input(RX_PIN_NUMBER, NRF_GPIO_PIN_NOPULL);
+
+    // Set a default baud rate of UART0_CONFIG_BAUDRATE
+    NRF_UART0->PSELTXD  = TX_PIN_NUMBER;
+    NRF_UART0->BAUDRATE = UART0_CONFIG_BAUDRATE;
+
+    NRF_UART0->PSELRTS  = 0xFFFFFFFF;
+    NRF_UART0->PSELCTS  = 0xFFFFFFFF;
+
+    // Disable parity and interrupt
+    NRF_UART0->CONFIG   = (UART_CONFIG_PARITY_Excluded  << UART_CONFIG_PARITY_Pos );
+    NRF_UART0->CONFIG  |= (UART_CONFIG_HWFC_Disabled    << UART_CONFIG_HWFC_Pos   );
+
+    // Re-enable the UART
+    NRF_UART0->ENABLE           = UART_ENABLE_ENABLE_Enabled;
+    NRF_UART0->INTENSET         = 0;
+    NRF_UART0->TASKS_STARTTX    = 1;
+    NRF_UART0->TASKS_STARTRX    = 1;
+
+    return NRF_SUCCESS;
+}
+
+void log_raw_uart_printf(const char * format_msg, ...)
+{
+    static char buffer[256];
+
+    va_list p_args;
+    va_start(p_args, format_msg);
+    sprintf(buffer, format_msg, p_args);
+    va_end(p_args);
+
+    log_raw_uart_write_string(buffer);
+}
+
+__INLINE void log_raw_uart_write_char(const char c)
+{
+    NRF_UART0->TXD = c;
+    while( NRF_UART0->EVENTS_TXDRDY != 1 );
+    NRF_UART0->EVENTS_TXDRDY = 0;
+}
+
+__INLINE void log_raw_uart_write_string_many(int num_args, ...)
+{
+
+    const char* msg;
+    va_list p_args;
+    va_start(p_args, num_args);
+
+    for (int i = 0; i < num_args; i++)
+    {
+        msg = va_arg(p_args, const char*);
+        log_raw_uart_write_string(msg);
+    }
+    va_end(p_args);
+}
+
+__INLINE void log_raw_uart_write_string(const char* msg)
+{
+    while( *msg )
+    {
+        NRF_UART0->TXD = *msg++;
+        while( NRF_UART0->EVENTS_TXDRDY != 1 );
+        NRF_UART0->EVENTS_TXDRDY = 0;
+    }
+}
+
+void log_raw_uart_write_hex(uint32_t value)
+{
+    uint8_t nibble;
+    uint8_t i = 8;
+
+    log_raw_uart_write_string( "0x" );
+    while( i-- != 0 )
+    {
+        nibble = (value >> (4 * i)) & 0x0F;
+        log_raw_uart_write_char( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) );
+    }
+}
+
+void log_raw_uart_write_hex_char(uint8_t c)
+{
+    uint8_t nibble;
+    uint8_t i = 2;
+
+    while( i-- != 0 )
+    {
+        nibble = (c >> (4 * i)) & 0x0F;
+        log_raw_uart_write_hex( (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble) );
+    }
+}
+
+__INLINE int log_raw_uart_has_input()
+{
+    return 0;
+}
+
+uint32_t log_raw_uart_read_input(char * c)
+{
+    return NRF_ERROR_NULL;
+}
+
+#endif // NRF_LOG_USES_RAW_UART == 1
+
+
+const char* log_hex_char(const char c)
+{
+    static volatile char hex_string[3];
+    hex_string[2] = 0; // Null termination
+    uint8_t nibble;
+    uint8_t i = 2;
+    while(i-- != 0)
+    {
+        nibble = (c >> (4 * i)) & 0x0F;
+        hex_string[1-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble);
+    }
+    return (const char*) hex_string;
+}
+
+const char* log_hex(uint32_t value)
+{
+    static volatile char hex_string[11];
+    hex_string[0] = '0';
+    hex_string[1] = 'x';
+    hex_string[10] = 0;
+    uint8_t nibble;
+    uint8_t i = 8;
+
+    while(i-- != 0)
+    {
+        nibble = (value >> (4 * i)) & 0x0F;
+        hex_string[9-i] = (nibble > 9) ? ('A' + nibble - 10) : ('0' + nibble);
+    }
+
+    return (const char*)hex_string;
+}
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.h
new file mode 100644
index 0000000000..2019e81b3b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/nrf_log.h
@@ -0,0 +1,699 @@
+#ifndef NRF_LOG_H_
+#define NRF_LOG_H_
+
+#ifndef DOXYGEN
+
+#include <stdint.h>
+#include <stdarg.h>
+#include <app_util.h>
+
+#ifndef NRF_LOG_USES_RTT
+#define NRF_LOG_USES_RTT 0
+#endif
+
+#ifndef NRF_LOG_USES_UART
+#define NRF_LOG_USES_UART 0
+#endif
+
+#ifndef NRF_LOG_USES_RAW_UART
+#define NRF_LOG_USES_RAW_UART 0
+#endif
+
+#ifndef NRF_LOG_USES_COLORS
+    #define NRF_LOG_USES_COLORS 1
+#endif
+
+#if NRF_LOG_USES_COLORS == 1
+    #define NRF_LOG_COLOR_DEFAULT  "\x1B[0m"
+    #define NRF_LOG_COLOR_BLACK    "\x1B[1;30m"
+    #define NRF_LOG_COLOR_RED      "\x1B[1;31m"
+    #define NRF_LOG_COLOR_GREEN    "\x1B[1;32m"
+    #define NRF_LOG_COLOR_YELLOW   "\x1B[1;33m"
+    #define NRF_LOG_COLOR_BLUE     "\x1B[1;34m"
+    #define NRF_LOG_COLOR_MAGENTA  "\x1B[1;35m"
+    #define NRF_LOG_COLOR_CYAN     "\x1B[1;36m"
+    #define NRF_LOG_COLOR_WHITE    "\x1B[1;37m"
+#else
+    #define NRF_LOG_COLOR_DEFAULT
+    #define NRF_LOG_COLOR_BLACK
+    #define NRF_LOG_COLOR_RED
+    #define NRF_LOG_COLOR_GREEN
+    #define NRF_LOG_COLOR_YELLOW
+    #define NRF_LOG_COLOR_BLUE
+    #define NRF_LOG_COLOR_MAGENTA
+    #define NRF_LOG_COLOR_CYAN
+    #define NRF_LOG_COLOR_WHITE
+#endif
+
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+
+#define LOG_TERMINAL_NORMAL         (0)
+#define LOG_TERMINAL_ERROR          (1)
+#define LOG_TERMINAL_INPUT          (0)
+
+/**@brief Function for initializing the SEGGER RTT logger.
+ *
+ * @details See <a href="https://www.segger.com/jlink-rtt.html" target="_blank">segger.com</a>
+ *          for information about SEGGER Real Time Transfer (RTT).
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use the macro @ref NRF_LOG_INIT instead.
+ *
+ * @retval     NRF_SUCCESS     If initialization was successful.
+ * @retval     NRF_ERROR       Otherwise.
+ */
+uint32_t log_rtt_init(void);
+
+/**@brief Function for writing a printf string using RTT.
+ *
+ * @details The printf implementation in SEGGER's RTT is more efficient than
+ * the standard implementation. However, printf requires more processor time
+ * than other logging functions. Therefore, applications that require logging
+ * but need it to interfere as little as possible with the execution, should
+ * avoid using printf.
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_PRINTF
+ * - @ref NRF_LOG_PRINTF_DEBUG
+ * - @ref NRF_LOG_PRINTF_ERROR
+ *
+ * @param   terminal_index  Segger RTT terminal index to use as output.
+ * @param   format_msg      Printf format string.
+ */
+void log_rtt_printf(int terminal_index, char * format_msg, ...);
+
+/**@brief Function for writing a string using RTT.
+ *
+ * @details The string to write must be null-terminated, but the null termination will not be stored
+ *          in the ring buffer.
+ *          The impact of running this function should be very low compared to writing to UART.
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG
+ * - @ref NRF_LOG_DEBUG
+ * - @ref NRF_LOG_ERROR
+ *
+ * @param   terminal_index  Segger RTT terminal index to use as output.
+ * @param   num_args        Number of arguments.
+ */
+void log_rtt_write_string(int terminal_index, int num_args, ...);
+
+/**@brief Function for writing an integer as HEX using RTT.
+ *
+ * The output data is formatted as, for example, 0x89ABCDEF.
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_HEX
+ * - @ref NRF_LOG_HEX_DEBUG
+ * - @ref NRF_LOG_HEX_ERROR
+ *
+ * @param   terminal_index  Segger RTT terminal index to use as output.
+ * @param   value           Integer value to be printed as HEX.
+ */
+void log_rtt_write_hex(int terminal_index, uint32_t value);
+
+/**@brief Function for writing a single character as HEX using RTT.
+ *
+ * The output string is formatted as, for example, AA.
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_HEX_CHAR
+ * - @ref NRF_LOG_HEX_CHAR_DEBUG
+ * - @ref NRF_LOG_HEX_CHAR_ERROR
+ *
+ * @param   terminal_index  Segger RTT terminal index to use as output.
+ * @param   value           Character to print as HEX.
+ */
+void log_rtt_write_hex_char(int terminal_index, uint8_t value);
+
+/**@brief Function for checking if data is available in the input buffer.
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use @ref NRF_LOG_HAS_INPUT instead.
+ *
+ * @retval      1 If characters are available to read.
+ * @retval      0 If no characters are available.
+ */
+int log_rtt_has_input(void);
+
+/**@brief Function for reading one character from the input buffer.
+ *
+ * @param[out] p_char  Pointer where to store the character.
+ *
+ * This function is available only when NRF_LOG_USES_RTT is defined as 1.
+ *
+ * @note Do not call this function directly. Use @ref NRF_LOG_READ_INPUT instead.
+ *
+ * @retval      NRF_SUCCESS If the character was read out.
+ * @retval      NRF_ERROR_INVALID_DATA If no character could be read.
+ */
+uint32_t log_rtt_read_input(char* p_char);
+
+#define NRF_LOG_INIT()                  log_rtt_init()                                                                          /*!< Initialize the module. */
+
+#define NRF_LOG_PRINTF(...)             log_rtt_printf(LOG_TERMINAL_NORMAL, ##__VA_ARGS__)                                      /*!< Print a log message using printf. */
+#define NRF_LOG_PRINTF_DEBUG(...)       log_rtt_printf(LOG_TERMINAL_NORMAL, ##__VA_ARGS__)                                      /*!< If DEBUG is set, print a log message using printf. */
+#define NRF_LOG_PRINTF_ERROR(...)       log_rtt_printf(LOG_TERMINAL_ERROR, ##__VA_ARGS__)                                       /*!< Print a log message using printf to the error stream. */
+
+#define NRF_LOG(...)                    log_rtt_write_string(LOG_TERMINAL_NORMAL, NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)      /*!< Print a log message. The input string must be null-terminated. */
+#define NRF_LOG_DEBUG(...)              log_rtt_write_string(LOG_TERMINAL_NORMAL, NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)      /*!< If DEBUG is set, print a log message. The input string must be null-terminated. */
+#define NRF_LOG_ERROR(...)              log_rtt_write_string(LOG_TERMINAL_ERROR, NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)       /*!< Print a log message to the error stream. The input string must be null-terminated. */
+
+#define NRF_LOG_HEX(val)                log_rtt_write_hex(LOG_TERMINAL_NORMAL, val)                                             /*!< Log an integer as HEX value (example output: 0x89ABCDEF). */
+#define NRF_LOG_HEX_DEBUG(val)          log_rtt_write_hex(LOG_TERMINAL_NORMAL, val)                                             /*!< If DEBUG is set, log an integer as HEX value (example output: 0x89ABCDEF). */
+#define NRF_LOG_HEX_ERROR(val)          log_rtt_write_hex(LOG_TERMINAL_ERROR, val)                                              /*!< Log an integer as HEX value to the error stream (example output: 0x89ABCDEF). */
+
+#define NRF_LOG_HEX_CHAR(val)           log_rtt_write_hex_char(LOG_TERMINAL_NORMAL, val)                                        /*!< Log a character as HEX value (example output: AA). */
+#define NRF_LOG_HEX_CHAR_DEBUG(val)     log_rtt_write_hex_char(LOG_TERMINAL_NORMAL, val)                                        /*!< If DEBUG is set, log a character as HEX value (example output: AA). */
+#define NRF_LOG_HEX_CHAR_ERROR(val)     log_rtt_write_hex_char(LOG_TERMINAL_ERROR, val)                                         /*!< Log a character as HEX value to the error stream (example output: AA). */
+
+#define NRF_LOG_HAS_INPUT()             log_rtt_has_input()                                                                     /*!< Check if the input buffer has unconsumed characters. */
+#define NRF_LOG_READ_INPUT(p_char)      log_rtt_read_input(p_char)                                                              /*!< Consume a character from the input buffer. */
+
+#if !defined(DEBUG) && !defined(DOXYGEN)
+
+#undef NRF_LOG_DEBUG
+#define NRF_LOG_DEBUG(...)
+
+#undef NRF_LOG_STR_DEBUG
+#define NRF_LOG_STR_DEBUG(...)
+
+#undef NRF_LOG_HEX_DEBUG
+#define NRF_LOG_HEX_DEBUG(...)
+
+#undef NRF_LOG_HEX_CHAR_DEBUG
+#define NRF_LOG_HEX_CHAR_DEBUG(...)
+
+#endif // !defined(DEBUG) && !defined(DOXYGEN)
+
+#elif defined(NRF_LOG_USES_UART) && NRF_LOG_USES_UART == 1
+
+/**@brief Function for initializing the UART logger.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use the macro @ref NRF_LOG_INIT instead.
+ *
+ * @retval     NRF_SUCCESS     If initialization was successful.
+ * @retval     NRF_ERROR       Otherwise.
+ */
+uint32_t log_uart_init(void);
+
+/**@brief Function for logging a printf string to UART.
+ *
+ * @details  Printf requires more processor time
+ * than other logging functions. Therefore, applications that require logging
+ * but need it to interfere as little as possible with the execution, should
+ * avoid using printf.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note This function is non-blocking. If too much data is sent to the UART,
+ *          some characters might be skipped.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_PRINTF
+ * - @ref NRF_LOG_PRINTF_DEBUG
+ * - @ref NRF_LOG_PRINTF_ERROR
+ *
+ * @param  format_msg      Printf format string.
+ */
+void log_uart_printf(const char * format_msg, ...);
+
+/**@brief Function for logging a single character to UART.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @param  c     Character.
+ */
+void log_uart_write_char(const char c);
+
+/**@brief Function for logging null-terminated strings to UART.
+ *
+ * @details This function is more efficient than using printf.
+ *          The null termination will not be logged.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG
+ * - @ref NRF_LOG_DEBUG
+ * - @ref NRF_LOG_ERROR
+ *
+ * @param  num_args     Number of arguments.
+ */
+void log_uart_write_string_many(int num_args, ...);
+
+
+/**@brief Function for logging a null-terminated string to UART.
+ *
+ * @details This function is more efficient than using printf.
+ *          The null termination will not be logged.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG
+ * - @ref NRF_LOG_DEBUG
+ * - @ref NRF_LOG_ERROR
+ *
+ * @param  msg     Null-terminated string.
+ */
+void log_uart_write_string(const char* msg);
+
+
+/**@brief Function for logging an integer value as HEX to UART.
+ *
+ * @details The output data is formatted as, for example, 0x89ABCDEF.
+ * This function is more efficient than printf.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note This function is non-blocking. If too much data is sent to the UART,
+ *          some characters might be skipped.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_HEX
+ * - @ref NRF_LOG_HEX_DEBUG
+ * - @ref NRF_LOG_HEX_ERROR
+ *
+ * @param   value   Integer value to be printed as HEX.
+ */
+void log_uart_write_hex(uint32_t value);
+
+/**@brief Function for logging a single character as HEX to UART.
+ *
+ * @details The output string is formatted as, for example, AA.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note This function is non-blocking. If too much data is sent to the UART,
+ *          some characters might be skipped.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_HEX_CHAR
+ * - @ref NRF_LOG_HEX_CHAR_DEBUG
+ * - @ref NRF_LOG_HEX_CHAR_ERROR
+ *
+ * @param c Character.
+  */
+void log_uart_write_hex_char(uint8_t c);
+
+/**@brief Function for checking if data is available in the input buffer.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use @ref NRF_LOG_HAS_INPUT instead.
+ *
+ * @retval      1 If characters are available to read.
+ * @retval      0 If no characters are available.
+ */
+int log_uart_has_input(void);
+
+/**@brief Function for reading one character from the input buffer.
+ *
+ * @param[out]   p_char  Pointer where to store the character.
+ *
+ * This function is available only when NRF_LOG_USES_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use NRF_LOG_READ_INPUT instead.
+ *
+ * @retval      NRF_SUCCESS If the character was read out.
+ * @retval      NRF_ERROR_INVALID_DATA If no character could be read.
+ */
+uint32_t log_uart_read_input(char* p_char);
+
+
+#define NRF_LOG_INIT()                  log_uart_init()                                                         /*!< Initialize the module. */
+
+#define NRF_LOG_PRINTF(...)             log_uart_printf(__VA_ARGS__)                                            /*!< Print a log message using printf. */
+#define NRF_LOG_PRINTF_DEBUG(...)       log_uart_printf(__VA_ARGS__)                                            /*!< If DEBUG is set, print a log message using printf. */
+#define NRF_LOG_PRINTF_ERROR(...)       log_uart_printf(__VA_ARGS__)                                            /*!< Print a log message using printf to the error stream. */
+
+#define NRF_LOG(...)                    log_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)     /*!< Print a log message. The input string must be null-terminated. */
+#define NRF_LOG_DEBUG(...)              log_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)     /*!< If DEBUG is set, print a log message. The input string must be null-terminated. */
+#define NRF_LOG_ERROR(...)              log_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)     /*!< Print a log message to the error stream. The input string must be null-terminated. */
+
+#define NRF_LOG_HEX(val)                log_uart_write_hex(val)                                                 /*!< Log an integer as HEX value (example output: 0x89ABCDEF). */
+#define NRF_LOG_HEX_DEBUG(val)          log_uart_write_hex(val)                                                 /*!< If DEBUG is set, log an integer as HEX value (example output: 0x89ABCDEF). */
+#define NRF_LOG_HEX_ERROR(val)          log_uart_write_hex(val)                                                 /*!< Log an integer as HEX value to the error stream (example output: 0x89ABCDEF). */
+
+#define NRF_LOG_HEX_CHAR(val)           log_uart_write_hex_char(val)                                            /*!< Log a character as HEX value (example output: AA). */
+#define NRF_LOG_HEX_CHAR_DEBUG(val)     log_uart_write_hex_char(val)                                            /*!< If DEBUG is set, log a character as HEX value (example output: AA). */
+#define NRF_LOG_HEX_CHAR_ERROR(val)     log_uart_write_hex_char(val)                                            /*!< Log a character as HEX value to the error stream (example output: AA). */
+
+#define NRF_LOG_HAS_INPUT()             log_uart_has_input()                                                    /*!< Check if the input buffer has unconsumed characters. */
+#define NRF_LOG_READ_INPUT(p_char)      log_uart_read_input(p_char)                                             /*!< Consume a character from the input buffer. */
+
+#if !defined(DEBUG) && !defined(DOXYGEN)
+
+#undef NRF_LOG_DEBUG
+#define NRF_LOG_DEBUG(...)
+
+#undef NRF_LOG_PRINTF_DEBUG
+#define NRF_LOG_PRINTF_DEBUG(...)
+
+#undef NRF_LOG_STR_DEBUG
+#define NRF_LOG_STR_DEBUG(...)
+
+#undef NRF_LOG_HEX_DEBUG
+#define NRF_LOG_HEX_DEBUG(...)
+
+#undef NRF_LOG_HEX_CHAR_DEBUG
+#define NRF_LOG_HEX_CHAR_DEBUG(...)
+
+#endif // !defined(DEBUG) && !defined(DOXYGEN)
+
+#elif defined(NRF_LOG_USES_RAW_UART) && NRF_LOG_USES_RAW_UART == 1
+
+/**@brief Function for initializing the raw UART logger.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use the macro @ref NRF_LOG_INIT instead.
+ *
+ * @retval     NRF_SUCCESS     If initialization was successful.
+ * @retval     NRF_ERROR       Otherwise.
+ */
+uint32_t log_raw_uart_init(void);
+
+/**@brief Function for logging a printf string to raw UART.
+ *
+ * @details  Printf requires more processor time
+ * than other logging functions. Therefore, applications that require logging
+ * but need it to interfere as little as possible with the execution, should
+ * avoid using printf.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note This function is non-blocking. If too much data is sent to the UART,
+ *          some characters might be skipped.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_PRINTF
+ * - @ref NRF_LOG_PRINTF_DEBUG
+ * - @ref NRF_LOG_PRINTF_ERROR
+ *
+ * @param  format_msg      Printf format string.
+ */
+void log_raw_uart_printf(const char * format_msg, ...);
+
+/**@brief Function for logging a single character to raw UART.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @param  c     Character.
+ */
+void log_raw_uart_write_char(const char c);
+
+/**@brief Function for logging null-terminated strings to raw UART.
+ *
+ * @details This function is more efficient than using printf.
+ *          The null termination will not be logged.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG
+ * - @ref NRF_LOG_DEBUG
+ * - @ref NRF_LOG_ERROR
+ *
+ * @param  num_args     Number of arguments.
+ */
+void log_raw_uart_write_string_many(int num_args, ...);
+
+
+/**@brief Function for logging a null-terminated string to raw UART.
+ *
+ * @details This function is more efficient than using printf.
+ *          The null termination will not be logged.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG
+ * - @ref NRF_LOG_DEBUG
+ * - @ref NRF_LOG_ERROR
+ *
+ * @param  str     Null-terminated string.
+ */
+void log_raw_uart_write_string(const char * str);
+
+/**@brief Function for logging an integer value as HEX to raw UART.
+ *
+ * @details The output data is formatted as, for example, 0x89ABCDEF.
+ * This function is more efficient than printf.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note This function is non-blocking. If too much data is sent to the UART,
+ *          some characters might be skipped.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_HEX
+ * - @ref NRF_LOG_HEX_DEBUG
+ * - @ref NRF_LOG_HEX_ERROR
+ *
+ * @param   value   Integer value to be printed as HEX.
+ */
+void log_raw_uart_write_hex(uint32_t value);
+
+/**@brief Function for logging a single character as HEX to raw UART.
+ *
+ * @details The output string is formatted as, for example, AA.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note This function is non-blocking. If too much data is sent to the UART,
+ *          some characters might be skipped.
+ *
+ * @note Do not call this function directly. Use one of the following macros instead:
+ * - @ref NRF_LOG_HEX_CHAR
+ * - @ref NRF_LOG_HEX_CHAR_DEBUG
+ * - @ref NRF_LOG_HEX_CHAR_ERROR
+ *
+ * @param c Character.
+  */
+void log_raw_uart_write_hex_char(uint8_t c);
+
+/**@brief Function for checking if data is available in the input buffer.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use @ref NRF_LOG_HAS_INPUT instead.
+ *
+ * @retval      1 If characters are available to read.
+ * @retval      0 If no characters are available.
+ */
+int log_raw_uart_has_input(void);
+
+/**@brief Function for reading one character from the input buffer.
+ *
+ * @param[out]   p_char  Pointer where to store the character.
+ *
+ * This function is available only when NRF_LOG_USES_RAW_UART is defined as 1.
+ *
+ * @note Do not call this function directly. Use NRF_LOG_READ_INPUT instead.
+ *
+ * @retval      NRF_SUCCESS If the character was read out.
+ * @retval      NRF_ERROR_INVALID_DATA If no character could be read.
+ */
+
+uint32_t log_raw_uart_read_input(char* p_char);
+
+#define NRF_LOG_INIT()                  log_raw_uart_init()                                                         /*!< nitialize the module. */
+
+#define NRF_LOG_PRINTF(...)             log_raw_uart_printf(__VA_ARGS__)                                            /*!< Print a log message using printf. */
+#define NRF_LOG_PRINTF_DEBUG(...)       log_raw_uart_printf(__VA_ARGS__)                                            /*!< If DEBUG is set, print a log message using printf. */
+#define NRF_LOG_PRINTF_ERROR(...)       log_raw_uart_printf(__VA_ARGS__)                                            /*!< Print a log message using printf to the error stream. */
+
+#define NRF_LOG(...)                    log_raw_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)     /*!< Print a log message. The input string must be null-terminated. */
+#define NRF_LOG_DEBUG(...)              log_raw_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)     /*!< If DEBUG is set, print a log message. The input string must be null-terminated. */
+#define NRF_LOG_ERROR(...)              log_raw_uart_write_string_many(NUM_VA_ARGS(__VA_ARGS__), ##__VA_ARGS__)     /*!< Print a log message to the error stream. The input string must be null-terminated. */
+
+#define NRF_LOG_HEX(val)                log_raw_uart_write_hex(val)                                                 /*!< Log an integer as HEX value (example output: 0x89ABCDEF). */
+#define NRF_LOG_HEX_DEBUG(val)          log_raw_uart_write_hex(val)                                                 /*!< If DEBUG is set, log an integer as HEX value (example output: 0x89ABCDEF). */
+#define NRF_LOG_HEX_ERROR(val)          log_raw_uart_write_hex(val)                                                 /*!< Log an integer as HEX value to the error stream (example output: 0x89ABCDEF). */
+
+#define NRF_LOG_HEX_CHAR(val)           log_raw_uart_write_hex_char(val)                                            /*!< Log a character as HEX value (example output: AA). */
+#define NRF_LOG_HEX_CHAR_DEBUG(val)     log_raw_uart_write_hex_char(val)                                            /*!< If DEBUG is set, log a character as HEX value (example output: AA). */
+#define NRF_LOG_HEX_CHAR_ERROR(val)     log_raw_uart_write_hex_char(val)                                            /*!< Log a character as HEX value to the error stream (example output: AA). */
+
+#define NRF_LOG_HAS_INPUT()             log_raw_uart_has_input()                                                    /*!< Check if the input buffer has unconsumed characters. */
+#define NRF_LOG_READ_INPUT(p_char)      log_raw_uart_read_input(p_char)                                             /*!< Consume a character from the input buffer. */
+
+#if !defined(DEBUG) && !defined(DOXYGEN)
+
+#undef NRF_LOG_DEBUG
+#define NRF_LOG_DEBUG(...)
+
+#undef NRF_LOG_PRINTF_DEBUG
+#define NRF_LOG_PRINTF_DEBUG(...)
+
+#undef NRF_LOG_STR_DEBUG
+#define NRF_LOG_STR_DEBUG(...)
+
+#undef NRF_LOG_HEX_DEBUG
+#define NRF_LOG_HEX_DEBUG(...)
+
+#undef NRF_LOG_HEX_CHAR_DEBUG
+#define NRF_LOG_HEX_CHAR_DEBUG(...)
+
+#endif // !defined(DEBUG) && !defined(DOXYGEN)
+
+#else
+
+#include "nrf_error.h"
+#include "nordic_common.h"
+
+// Empty definitions
+
+#define NRF_LOG_INIT()                 NRF_SUCCESS
+#define NRF_LOG(...)
+#define NRF_LOG_DEBUG(...)
+#define NRF_LOG_ERROR(...)
+
+#define NRF_LOG_PRINTF(...)
+#define NRF_LOG_PRINTF_DEBUG(...)
+#define NRF_LOG_PRINTF_ERROR(...)
+
+#define NRF_LOG_HEX(val)
+#define NRF_LOG_HEX_DEBUG(val)
+#define NRF_LOG_HEX_ERROR(val)
+
+#define NRF_LOG_HEX_CHAR(val)
+#define NRF_LOG_HEX_CHAR_DEBUG(val)
+#define NRF_LOG_HEX_CHAR_ERROR(val)
+
+#define NRF_LOG_HAS_INPUT()              0
+#define NRF_LOG_READ_INPUT(ignore)       NRF_SUCCESS
+
+#endif
+
+/**@brief Function for writing HEX values.
+ *
+ * @note This function not thread-safe. It is written for convenience.
+ *          If you log from different application contexts, you might get different results.
+ *
+ * @retval NULL By default.
+ */
+const char* log_hex(uint32_t value);
+
+/**@brief Function for writing HEX characters.
+ *
+ * @note This function not thread-safe. It is written for convenience.
+ *          If you log from different application contexts, you might get different results.
+ *
+ * @retval NULL By default.
+ */
+const char* log_hex_char(const char value);
+
+
+
+
+#else // DOXYGEN
+
+/** @defgroup nrf_log UART/RTT logging
+ * @{
+ * @ingroup app_common
+ *
+ * @brief Library to output logging information over SEGGER's Real Time Transfer
+ *       (RTT), UART, or raw UART.
+ *
+ * This library provides macros that call the respective functions depending on
+ * which protocol is used. Define LOG_USES_RTT=1 to enable logging over RTT,
+ * NRF_LOG_USES_UART=1 to enable logging over UART, or NRF_LOG_USES_RAW_UART=1
+ * to enable logging over raw UART. One of these defines must be set for any of
+ * the macros to have effect. If you choose to not output information, all
+ * logging macros can be left in the code without any cost; they will just be
+ * ignored.
+ */
+
+
+
+/**@brief Macro for initializing the logger.
+ *
+ * @retval     NRF_SUCCESS     If initialization was successful.
+ * @retval     NRF_ERROR       Otherwise.
+ */
+uint32_t NRF_LOG_INIT(void);
+
+/**@brief Macro for logging null-terminated strings.
+ *
+ * @details This function is more efficient than using printf.
+ *          The null termination will not be logged.
+ *
+ * @param  msg  Null-terminated string.
+ */
+void NRF_LOG(const char* msg);
+
+/**@brief Macro for logging a printf string.
+ *
+ * @details  Printf requires more processor time
+ * than other logging functions. Therefore, applications that require logging
+ * but need it to interfere as little as possible with the execution, should
+ * avoid using printf.
+ *
+ * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking.
+ *       If too much data is sent, some characters might be skipped.
+ *
+ * @param  format_msg      Printf format string.
+ * @param  ...             Additional arguments replacing format specifiers in format_msg.
+ */
+void NRF_LOG_PRINTF(const char * format_msg, ...);
+
+/**@brief Macro for logging an integer value as HEX.
+ *
+ * @details The output data is formatted as, for example, 0x89ABCDEF.
+ * This function is more efficient than printf.
+ *
+ * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking.
+ *       If too much data is sent, some characters might be skipped.
+ *
+ * @param   value   Integer value to be printed as HEX.
+ */
+void NRF_LOG_HEX(uint32_t value);
+
+/**@brief Macro for logging a single character as HEX.
+ *
+ * @details The output string is formatted as, for example, AA.
+ *
+ * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking.
+ *       If too much data is sent, some characters might be skipped.
+ *
+ * @param c Character.
+  */
+void NRF_LOG_HEX_CHAR(uint8_t c);
+
+/**@brief Macro for checking if data is available in the input buffer.
+ *
+ * @note When NRF_LOG_USES_UART is set to 1, this macro is non-blocking.
+ *       If too much data is sent, some characters might be skipped.
+ *
+ * @retval      1 If characters are available to read.
+ * @retval      0 If no characters are available.
+ */
+int NRF_LOG_HAS_INPUT(void);
+
+/**@brief Macro for reading one character from the input buffer.
+ *
+ * @param[out]   p_char  Pointer where to store the character.
+ *
+ * @retval      NRF_SUCCESS If the character was read out.
+ * @retval      NRF_ERROR_INVALID_DATA If no character could be read.
+ */
+uint32_t NRF_LOG_READ_INPUT(char* p_char);
+
+/** @} */
+#endif // DOXYGEN
+#endif // NRF_LOG_H_
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_common.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_common.h
new file mode 100644
index 0000000000..f7e8302973
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_common.h
@@ -0,0 +1,201 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @cond */
+/**@file
+ *
+ * @ingroup experimental_api
+ * @defgroup sdk_common SDK Common Header
+ * @breif All common headers needed for SDK examples will be included here so that application
+ *       developer does not have to include headers on him/herself.
+ * @{
+ */
+
+#ifndef SDK_COMMON_H__
+#define SDK_COMMON_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include <string.h>
+#include "nordic_common.h"
+#include "compiler_abstraction.h"
+#include "sdk_os.h"
+#include "sdk_errors.h"
+#include "app_util.h"
+
+/**@brief Macro for verifying that the module is initialized. It will cause the function to return
+ *        if not.
+ *
+ * @param[in] param  The variable to check if is NULL.
+ */
+#ifndef DISABLE_PARAM_CHECK
+#define VERIFY_PARAM_NOT_NULL(param)                \
+do                                                  \
+{                                                   \
+    if (param == NULL)                              \
+    {                                               \
+        return NRF_ERROR_NULL;                      \
+    }                                               \
+} while(0)
+#else
+#define VERIFY_PARAM_NOT_NULL()
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that the module is initialized. It will cause the function to return
+ *        if not.
+ *
+ * @param[in] param  The variable to check if is NULL.
+ */
+#ifndef DISABLE_PARAM_CHECK
+#define VERIFY_PARAM_NOT_NULL_VOID(param)           \
+do                                                  \
+{                                                   \
+    if (param == NULL)                              \
+    {                                               \
+        return;                                     \
+    }                                               \
+} while(0)
+#else
+#define VERIFY_PARAM_NOT_NULL_VOID()
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that a function returned NRF_SUCCESS. Will return the err code
+ * if not.
+ *
+ * @param[in] err_code The error code to check.
+ */
+#ifndef DISABLE_PARAM_CHECK
+#define VERIFY_SUCCESS(err_code)            \
+do                                          \
+{                                           \
+    if (err_code != NRF_SUCCESS)            \
+    {                                       \
+        return err_code;                    \
+    }                                       \
+} while(0)
+#else
+#define VERIFY_SUCCESS()
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that a function returned NRF_SUCCESS. Will return if not.
+ *
+ * @param[in] err_code The error code to check.
+ */
+#ifndef DISABLE_PARAM_CHECK
+#define VERIFY_SUCCESS_VOID(err_code)       \
+do                                          \
+{                                           \
+    if (err_code != NRF_SUCCESS)            \
+    {                                       \
+        return;                             \
+    }                                       \
+} while(0)
+#else
+#define VERIFY_SUCCESS_VOID()
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying statement to be true. Will return err_code if not.
+*
+* @param[in]   statement   Statement to test.
+* @param[in]   err_code     Error value to return if test was invalid.
+*
+* @retval      err_code if test fails.
+*/
+#define VERIFY_TRUE(statement, err_code)    \
+do                                          \
+{                                           \
+    if (!(statement))                       \
+    {                                       \
+        return err_code;                    \
+    }                                       \
+} while(0)
+
+
+/**@brief Macro for verifying statement to be true. Will return if not.
+*
+* @param[in]   statement   Statement to test.
+*/
+#define VERIFY_TRUE_VOID(statement)         \
+do                                          \
+{                                           \
+    if (!(statement))                       \
+    {                                       \
+        return;                             \
+    }                                       \
+} while(0)
+
+
+/**@brief Macro for verifying statement to be false. Will return err_code if not.
+*
+* @param[in]   statement   Statement to test.
+* @param[in]   err_code     Error value to return if test was invalid.
+*
+* @retval      err_code if test fails.
+*/
+#define VERIFY_FALSE(statement, err_code)   \
+do                                          \
+{                                           \
+    if ((statement))                        \
+    {                                       \
+        return err_code;                    \
+    }                                       \
+} while(0)
+
+
+/**@brief Macro for verifying statement to be false. Will return if not.
+*
+* @param[in]   statement    Statement to test.
+*/
+#define VERIFY_FALSE_VOID(statement)        \
+do                                          \
+{                                           \
+    if ((statement))                        \
+    {                                       \
+        return;                             \
+    }                                       \
+} while(0)
+
+/** @} */
+/** @endcond */
+#endif // SDK_COMMON_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_errors.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_errors.h
new file mode 100644
index 0000000000..dc7ef99ae4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_errors.h
@@ -0,0 +1,142 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup sdk_error SDK Error codes
+ * @{
+ * @ingroup app_common
+ * @{
+ * @details Error codes are 32-bit unsigned integers with the most significant 16-bit reserved for
+ *          identifying the module where the error occurred while the least least significant LSB
+ *          are used to provide the cause or nature of error. Each module is assigned a 16-bit
+ *          unsigned integer. Which it will use to identify all errors that occurred in it. 16-bit
+ *          LSB range is with module id as the MSB in the 32-bit error code is reserved for the
+ *          module. As an example, if 0x8800 identifies a certain SDK module, all values from 
+ *          0x88000000 - 0x8800FFFF are reserved for this module.
+ *          It should be noted that common error reasons have been assigned values to make it 
+ *          possible to decode error reason easily. As an example, lets module uninitialized has
+ *          been assigned an error code 0x000A0. Then, if application encounters an error code
+ *          0xZZZZ00A0, it knows that it accessing a certain module without initializing it.
+ *          Apart from this, each module is allowed to define error codes that are not covered by
+ *          the common ones, however, these values are defined in a range that does not conflict
+ *          with common error values. For module, specific error however, it is possible that the
+ *          same error value is used by two different modules to indicated errors of very different
+ *          nature. If error is already defined by the NRF common error codes, these are reused.
+ *          A range is reserved for application as well, it can use this range for defining
+ *          application specific errors.
+ *
+ * @note Success code, NRF_SUCCESS, does not include any module identifier.          
+
+ */
+
+#ifndef SDK_ERRORS_H__
+#define SDK_ERRORS_H__
+
+#include <stdint.h>
+#include "nrf_error.h"
+
+/**
+ * @defgroup sdk_err_base Base defined for SDK Modules
+ * @{
+ */
+#define SDK_ERROR_BASE         (NRF_ERROR_BASE_NUM + 0x8000)   /**< Base value defined for SDK module identifiers. */
+#define SDK_COMMON_ERROR_BASE  (NRF_ERROR_BASE_NUM + 0x0080)   /**< Base error value to be used for SDK error values. */
+/* @} */
+
+/**
+ * @defgroup sdk_module_codes Codes reserved as identification for module where the error occurred.
+ * @{
+ */
+#define DEVICE_MANAGER_ERR_BASE   (0x8000)
+#define MEMORY_MANAGER_ERR_BASE   (0x8100)
+/* @} */
+
+
+/**
+ * @defgroup sdk_iot_errors Codes reserved as identification for IoT errors.
+ * @{
+ */
+#define IOT_ERR_BASE_START        (0xA000)
+#define IOT_ERR_BASE_STOP         (0xAFFF)
+/* @} */
+ 
+
+/**
+ * @defgroup sdk_common_errors Codes reserved as identification for common errors.
+ * @{
+ */
+#define MODULE_NOT_INITIALZED      (SDK_COMMON_ERROR_BASE + 0x0000)
+#define MUTEX_INIT_FAILED          (SDK_COMMON_ERROR_BASE + 0x0001)
+#define MUTEX_LOCK_FAILED          (SDK_COMMON_ERROR_BASE + 0x0002)
+#define MUTEX_UNLOCK_FAILED        (SDK_COMMON_ERROR_BASE + 0x0003)
+#define MUTEX_COND_INIT_FAILED     (SDK_COMMON_ERROR_BASE + 0x0004)
+#define MODULE_ALREADY_INITIALIZED (SDK_COMMON_ERROR_BASE + 0x0005)
+#define API_NOT_IMPLEMENTED        (SDK_COMMON_ERROR_BASE + 0x0010)
+#define FEATURE_NOT_ENABLED        (SDK_COMMON_ERROR_BASE + 0x0011)
+/* @} */
+
+
+/**
+ * @defgroup dm_specific_errors Error / status codes specific to device manager.
+ * @{
+ */
+#define DM_NO_APP_CONTEXT                (DEVICE_MANAGER_ERR_BASE + 0x0040)
+#define DM_SERVICE_CONTEXT_NOT_APPLIED   (DEVICE_MANAGER_ERR_BASE + 0x0041)
+#define DM_CONTEXT_INFO_LOST             (DEVICE_MANAGER_ERR_BASE + 0x0042)
+#define DM_DEVICE_CONTEXT_FULL           (DEVICE_MANAGER_ERR_BASE + 0x0043)
+/* @} */
+
+/**
+ * @brief API Result.
+ *
+ * @details Indicates success or failure of an API procedure. In case of failure, a comprehensive
+ *          error code indicating cause or reason for failure is provided.
+ *
+ *          Though called an API result, it could used in Asynchronous notifications callback along
+ *          with asynchronous callback as event result. This mechanism is employed when an event
+ *          marks the end of procedure initiated using API. API result, in this case, will only be
+ *          an indicative of whether the procedure has been requested successfully.
+ */
+typedef uint32_t ret_code_t;
+/** @} */
+/** @} */
+
+#endif // SDK_ERRORS_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_macros.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_macros.h
new file mode 100644
index 0000000000..166073e579
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_macros.h
@@ -0,0 +1,99 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @cond */
+/**@file
+ *
+ * @ingroup sdk_util
+ * @defgroup sdk_common_macros SDK Common Header
+ * @breif Macros for parameter checking and similar tasks
+ * @{
+ */
+
+#ifndef SDK_MACROS_H__
+#define SDK_MACROS_H__
+
+/**@brief Macro for verifying that the module is initialized. It will cause the function to return
+ *        @ref NRF_ERROR_INVALID_STATE if not.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_MODULE_INITIALIZED()
+#else
+#ifdef MODULE_INITIALIZED
+#define VERIFY_MODULE_INITIALIZED()                 \
+do                                          \
+{                                           \
+    if (!MODULE_INITIALIZED)                \
+    {                                       \
+        return NRF_ERROR_INVALID_STATE;     \
+    }                                       \
+} while(0)
+#else
+#define VERIFY_MODULE_INITIALIZED()
+#endif /* MODULE_INITIALIZED  */
+#endif /* DISABLE_PARAM_CHECK */
+
+
+/**@brief Macro for verifying that the module is initialized. It will cause the function to return
+ *        if not.
+ */
+#ifdef DISABLE_PARAM_CHECK
+#define VERIFY_MODULE_INITIALIZED_VOID()
+#else
+#ifdef MODULE_INITIALIZED
+#define VERIFY_MODULE_INITIALIZED_VOID()            \
+do                                                  \
+{                                                   \
+    if (!MODULE_INITIALIZED)                        \
+    {                                               \
+        return;                                     \
+    }                                               \
+} while(0)
+#else
+#define VERIFY_MODULE_INITIALIZED_VOID()
+#endif /* MODULE_INITIALIZED  */
+#endif /* DISABLE_PARAM_CHECK */
+
+
+
+
+/** @} */
+/** @endcond */
+#endif // SDK_MACROS_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.c
new file mode 100644
index 0000000000..c92dbc973f
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.c
@@ -0,0 +1,188 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "sdk_mapped_flags.h"
+#include <stdint.h>
+#include <stdbool.h>
+#include <stddef.h>
+#include "compiler_abstraction.h"
+
+
+/**@brief Function for setting the state of a flag to true.
+ *
+ * @note This function does not check whether the index is valid.
+ *
+ * @param[in]  p_flags  The collection of flags to modify.
+ * @param[in]  index    The index of the flag to modify.
+ */
+static __INLINE void sdk_mapped_flags_set_by_index(sdk_mapped_flags_t * p_flags, uint16_t index)
+{
+    *p_flags |= (1U << index);
+}
+
+
+/**@brief Function for setting the state of a flag to false.
+ *
+ * @note This function does not check whether the index is valid.
+ *
+ * @param[in]  p_flags  The collection of flags to modify.
+ * @param[in]  index    The index of the flag to modify.
+ */
+static __INLINE void sdk_mapped_flags_clear_by_index(sdk_mapped_flags_t * p_flags, uint16_t index)
+{
+    *p_flags &= ~(1U << index);
+}
+
+
+/**@brief Function for getting the state of a flag.
+ *
+ * @note This function does not check whether the index is valid.
+ *
+ * @param[in]  p_flags  The collection of flags to read.
+ * @param[in]  index    The index of the flag to get.
+ */
+static __INLINE bool sdk_mapped_flags_get_by_index(sdk_mapped_flags_t flags, uint16_t index)
+{
+    return ((flags & (1 << index)) != 0);
+}
+
+
+
+uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags)
+{
+    for (uint16_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+    {
+        if (sdk_mapped_flags_get_by_index(flags, i))
+        {
+            return i;
+        }
+    }
+    return SDK_MAPPED_FLAGS_INVALID_INDEX;
+}
+
+
+void sdk_mapped_flags_update_by_key(uint16_t           * p_keys,
+                                    sdk_mapped_flags_t * p_flags,
+                                    uint16_t             key,
+                                    bool                 value)
+{
+    sdk_mapped_flags_bulk_update_by_key(p_keys, p_flags, 1, key, value);
+}
+
+
+void sdk_mapped_flags_bulk_update_by_key(uint16_t           * p_keys,
+                                         sdk_mapped_flags_t * p_flags,
+                                         uint32_t             n_flag_collections,
+                                         uint16_t             key,
+                                         bool                 value)
+{
+    if ((p_keys != NULL) && (p_flags != NULL) && (n_flag_collections > 0))
+    {
+        for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+        {
+            if (p_keys[i] == key)
+            {
+                for (uint32_t j = 0; j < n_flag_collections; j++)
+                {
+                    if (value)
+                    {
+                        sdk_mapped_flags_set_by_index(&p_flags[j], i);
+                    }
+                    else
+                    {
+                        sdk_mapped_flags_clear_by_index(&p_flags[j], i);
+                    }
+                }
+                return;
+            }
+        }
+    }
+}
+
+
+bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key)
+{
+    if (p_keys != NULL)
+    {
+        for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+        {
+            if (p_keys[i] == key)
+            {
+                return sdk_mapped_flags_get_by_index(flags, i);
+            }
+        }
+    }
+    return false;
+}
+
+
+sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t           * p_keys,
+                                                          sdk_mapped_flags_t   flags)
+{
+    sdk_mapped_flags_key_list_t key_list;
+    key_list.len = 0;
+
+    if (p_keys != NULL)
+    {
+        for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+        {
+            if (sdk_mapped_flags_get_by_index(flags, i))
+            {
+                key_list.flag_keys[key_list.len++] = p_keys[i];
+            }
+        }
+    }
+
+    return key_list;
+}
+
+
+uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags)
+{
+    uint32_t n_flags_set = 0;
+
+    for (uint32_t i = 0; i < SDK_MAPPED_FLAGS_N_KEYS; i++)
+    {
+        if (sdk_mapped_flags_get_by_index(flags, i))
+        {
+            n_flags_set += 1;
+        }
+    }
+    return n_flags_set;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.h
new file mode 100644
index 0000000000..780a9b61e3
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_mapped_flags.h
@@ -0,0 +1,180 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SDK_MAPPED_FLAGS_H__
+#define SDK_MAPPED_FLAGS_H__
+
+#include <stdint.h>
+#include <stdbool.h>
+#include "app_util.h"
+#include "compiler_abstraction.h"
+
+/**
+ * @file
+ * @defgroup sdk_mapped_flags Mapped flags
+ * @ingroup app_common
+ * @{
+ * @brief Module for writing and reading flags that are associated
+ *        with keys.
+ *
+ * @details The flags are represented as bits in a bitmap called a <i>flag collection</i>. The keys
+ *          are uint16_t. Each flag collection contains all flags of the same type, one flag for
+ *          each key.
+ *
+ *          The mapped flags module does not keep the flag states, nor the list of keys. These are
+ *          provided in the API calls. A key's index in the key list determines which bit in the
+ *          flag collection is associated with it. This module does not ever edit the key list, and
+ *          does not edit flags except in function calls that take the flag collection as a pointer.
+ *
+ */
+
+#define SDK_MAPPED_FLAGS_N_KEYS          8       /**< The number of keys to keep flags for. This is also the number of flags in a flag collection. If changing this value, you might also need change the width of the sdk_mapped_flags_t type. */
+#define SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE 8       /**< The number of flags that fit in one byte. */
+#define SDK_MAPPED_FLAGS_INVALID_INDEX   0xFFFF  /**< A flag index guaranteed to be invalid. */
+
+typedef uint8_t sdk_mapped_flags_t; /**< The bitmap to hold flags. Each flag is one bit, and each bit represents the flag state associated with one key. */
+
+
+// Test whether the flag collection type is large enough to hold all the flags. If this fails,
+// reduce SDK_MAPPED_FLAGS_N_KEYS or increase the size of sdk_mapped_flags_t.
+STATIC_ASSERT((
+    sizeof(sdk_mapped_flags_t)*SDK_MAPPED_FLAGS_N_KEYS_PER_BYTE) >= SDK_MAPPED_FLAGS_N_KEYS);
+
+
+/**@brief Type used to present a subset of the registered keys.
+ */
+typedef struct
+{
+    uint32_t len;                                 /**< The length of the list. */
+    uint16_t flag_keys[SDK_MAPPED_FLAGS_N_KEYS];  /**< The list of keys. */
+} sdk_mapped_flags_key_list_t;
+
+
+/**@brief Function for getting the first index at which the flag is true in the provided
+ *        collection.
+ *
+ * @param[in]  flags   The flag collection to search for a flag set to true.
+ *
+ * @return  The first index that has its flag set to true. If none were found, the
+ *          function returns @ref SDK_MAPPED_FLAGS_INVALID_INDEX.
+ */
+uint16_t sdk_mapped_flags_first_key_index_get(sdk_mapped_flags_t flags);
+
+
+/**@brief Function for updating the state of a flag.
+ *
+ * @param[in]  p_keys   The list of associated keys (assumed to have a length of
+ *                      @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[out] p_flags  The flag collection to modify.
+ * @param[in]  key      The key to modify the flag of.
+ * @param[in]  value    The state to set the flag to.
+ */
+void sdk_mapped_flags_update_by_key(uint16_t           * p_keys,
+                                    sdk_mapped_flags_t * p_flags,
+                                    uint16_t             key,
+                                    bool                 value);
+
+
+/**@brief Function for updating the state of the same flag in multiple flag collections.
+ *
+ * @details The key and value are the same for all flag collections in the p_flags array.
+ *
+ * @param[in]  p_keys              The list of associated keys (assumed to have a length of
+ *                                 @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[out] p_flags             The flag collections to modify.
+ * @param[out] n_flag_collections  The number of flag collections in p_flags.
+ * @param[in]  key                 The key to modify the flag of.
+ * @param[in]  value               The state to set the flag to.
+ */
+void sdk_mapped_flags_bulk_update_by_key(uint16_t           * p_keys,
+                                         sdk_mapped_flags_t * p_flags,
+                                         uint32_t             n_flag_collections,
+                                         uint16_t             key,
+                                         bool                 value);
+
+
+/**@brief Function for getting the state of a specific flag.
+ *
+ * @param[in]  p_keys  The list of associated keys (assumed to have a length of
+ *                     @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[in]  flags   The flag collection to read from.
+ * @param[in]  key     The key to get the flag for.
+ *
+ * @return  The state of the flag.
+ */
+bool sdk_mapped_flags_get_by_key(uint16_t * p_keys, sdk_mapped_flags_t flags, uint16_t key);
+
+
+/**@brief Function for getting a list of all keys that have a specific flag set to true.
+ *
+ * @param[in]  p_keys  The list of associated keys (assumed to have a length of
+ *                     @ref SDK_MAPPED_FLAGS_N_KEYS).
+ * @param[in]  flags   The flag collection to search.
+ *
+ * @return  The list of keys.
+ */
+sdk_mapped_flags_key_list_t sdk_mapped_flags_key_list_get(uint16_t           * p_keys,
+                                                          sdk_mapped_flags_t   flags);
+
+
+/**@brief Function for getting the number of keys that have a specific flag set to true.
+ *
+ * @param[in]  flags  The flag collection to search.
+ *
+ * @return  The number of keys.
+ */
+uint32_t sdk_mapped_flags_n_flags_set(sdk_mapped_flags_t flags);
+
+
+/**@brief Function for querying whether any flags in the collection are set.
+ *
+ * @param[in]  flags  The flag collection to query.
+ *
+ * @retval  true If one or more flags are set to true.
+ * @retval  false Otherwise.
+ */
+static __INLINE bool sdk_mapped_flags_any_set(sdk_mapped_flags_t flags)
+{
+    return (flags != 0);
+}
+
+
+/** @} */
+
+#endif /* SDK_MAPPED_FLAGS_H__ */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_os.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_os.h
new file mode 100644
index 0000000000..760822ff35
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_os.h
@@ -0,0 +1,67 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+ /** @cond */
+/**@file
+ *
+ * @defgroup sdk_os SDK OS Abstraction
+ * @ingroup experimental_api
+ * @details In order to made SDK modules independent of use of an embedded OS, and permit
+ *          application with varied task architecture, SDK abstracts the OS specific
+ *          elements here in order to make all other modules agnostic to the OS or task
+ *          architecture.
+ * @{
+ */
+
+#ifndef SDK_OS_H__
+#define SDK_OS_H__
+
+#define SDK_MUTEX_DEFINE(X)
+#define SDK_MUTEX_INIT(X)
+#define SDK_MUTEX_LOCK(X)
+#define SDK_MUTEX_UNLOCK(X)
+
+/**
+ * @defgroup os_data_type Data types.
+ */
+ 
+/** @} */
+/** @endcond */
+#endif // SDK_OS_H__
+
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_resources.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_resources.h
new file mode 100644
index 0000000000..27b0863856
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/libraries/util/sdk_resources.h
@@ -0,0 +1,78 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ * @brief Definition file for resource usage by SoftDevice, ESB and Gazell.
+ */
+
+#ifndef APP_RESOURCES_H__
+#define APP_RESOURCES_H__
+
+#ifdef SOFTDEVICE_PRESENT
+	#include "nrf_sd_def.h"
+#else
+	#define SD_PPI_RESTRICTED	      0uL /**< 1 if PPI peripheral is restricted, 0 otherwise. */
+	#define SD_PPI_CHANNELS_USED      0uL /**< PPI channels utilized by SotfDevice (not available to th spplication). */
+	#define SD_PPI_GROUPS_USED        0uL /**< PPI groups utilized by SotfDevice (not available to th spplication). */
+	#define SD_TIMERS_USED            0uL /**< Timers used by SoftDevice. */
+	#define SD_SWI_USED               0uL /**< Software interrupts used by SoftDevice. */
+#endif
+
+#ifdef GAZELL_PRESENT
+	#include "nrf_gzll_resources.h"
+#else
+	#define GZLL_PPI_CHANNELS_USED    0uL /**< PPI channels utilized by Gazell (not available to th spplication). */
+	#define GZLL_TIMERS_USED          0uL /**< Timers used by Gazell. */
+	#define GZLL_SWI_USED             0uL /**< Software interrupts used by Gazell */
+#endif
+
+#ifdef ESB_PRESENT
+	#include "nrf_esb_resources.h"
+#else
+	#define ESB_PPI_CHANNELS_USED    0uL /**< PPI channels utilized by ESB (not available to th spplication). */
+	#define ESB_TIMERS_USED          0uL /**< Timers used by ESB. */
+	#define ESB_SWI_USED             0uL /**< Software interrupts used by ESB */
+#endif
+
+#define NRF_PPI_CHANNELS_USED (SD_PPI_CHANNELS_USED | GZLL_PPI_CHANNELS_USED | ESB_PPI_CHANNELS_USED)
+#define NRF_PPI_GROUPS_USED   (SD_PPI_GROUPS_USED)
+#define NRF_SWI_USED          (SD_SWI_USED | GZLL_SWI_USED | ESB_SWI_USED)
+#define NRF_TIMERS_USED       (SD_TIMERS_USED | GZLL_TIMERS_USED | ESB_TIMERS_USED)
+
+#endif // APP_RESOURCES_H__
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h
new file mode 100644
index 0000000000..a74ed1800d
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ant_stack_handler_types.h
@@ -0,0 +1,100 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup ant_stack_handler_types Types definitions for ANT support in SoftDevice handler.
+ * @{
+ * @ingroup  softdevice_handler
+ * @brief    This file contains the declarations of types required for ANT stack support. These
+ *           types will be defined when the preprocessor define ANT_STACK_SUPPORT_REQD is defined.
+ */
+
+#ifndef ANT_STACK_HANDLER_TYPES_H__
+#define ANT_STACK_HANDLER_TYPES_H__
+
+#ifdef ANT_STACK_SUPPORT_REQD
+
+#include <stdlib.h>
+
+#define ANT_STACK_EVT_MSG_BUF_SIZE      32                                                /**< Size of ANT event message buffer. This will be provided to the SoftDevice while fetching an event. */
+#define ANT_STACK_EVT_STRUCT_SIZE       (sizeof(ant_evt_t))                               /**< Size of the @ref ant_evt_t structure. This will be used by the @ref softdevice_handler to internal event buffer size needed. */
+
+/**@brief ANT stack event type. */
+typedef struct
+{
+    union
+    {
+        uint32_t ulForceAlign;                           ///< force the evt_buffer to be 4-byte aligned, required for some casting to ANT_MESSAGE.
+        uint8_t  evt_buffer[ANT_STACK_EVT_MSG_BUF_SIZE]; ///< Event message buffer.
+    } msg;
+    uint8_t channel;                                     ///< Channel number.
+    uint8_t event;                                       ///< Event code.
+} ant_evt_t;
+
+/**@brief Application ANT stack event handler type. */
+typedef void (*ant_evt_handler_t) (ant_evt_t * p_ant_evt);
+
+/**@brief     Function for registering for ANT events.
+ *
+ * @details   The application should use this function to register for receiving ANT events from
+ *            the SoftDevice. If the application does not call this function, then any ANT event
+ *            that may be generated by the SoftDevice will NOT be fetched. Once the application has
+ *            registered for the events, it is not possible to  possible to cancel the registration.
+ *            However, it is possible to register a different function for handling the events at
+ *            any point of time.
+ *
+ * @param[in] ant_evt_handler Function to be called for each received ANT event.
+ *
+ * @retval    NRF_SUCCESS     Successful registration.
+ * @retval    NRF_ERROR_NULL  Null pointer provided as input.
+ */
+uint32_t softdevice_ant_evt_handler_set(ant_evt_handler_t ant_evt_handler);
+
+#else
+
+// The ANT Stack support is not required.
+
+#define ANT_STACK_EVT_STRUCT_SIZE       0                                                 /**< Since the ANT stack support is not required, this is equated to 0, so that the @ref softdevice_handler.h can compute the internal event buffer size without having to care for ANT events.*/
+
+#endif // ANT_STACK_SUPPORT_REQD
+
+#endif // ANT_STACK_HANDLER_TYPES_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/app_ram_base.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/app_ram_base.h
new file mode 100644
index 0000000000..5722bfd97b
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/app_ram_base.h
@@ -0,0 +1,203 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+// ble_enable param app_ram_base
+
+#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20001870
+#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20001870
+#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20001fe8
+#define APP_RAM_BASE_CENTRAL_LINKS_0_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20001fe8
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20001ce0
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20001c98
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20001eb0
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20001e68
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20002418
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x200023d0
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x200025e0
+#define APP_RAM_BASE_CENTRAL_LINKS_1_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x200025a0
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002110
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002080
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x200022d8
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002250
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x200024a8
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002418
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20002840
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x200027b8
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20002a10
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20002980
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20002bd8
+#define APP_RAM_BASE_CENTRAL_LINKS_2_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20002b50
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002538
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002468
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20002708
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002638
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x200028d0
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002800
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20002aa0
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x200029d0
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20002c70
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20002ba0
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20002e40
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20002d68
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003008
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20002f38
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x200031d8
+#define APP_RAM_BASE_CENTRAL_LINKS_3_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x20003100
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002968
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002850
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20002b30
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002a18
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20002d00
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002be8
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20002ec8
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20002db0
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x20003098
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20002f80
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x200030a0
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20002f88
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003268
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003150
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003438
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003320
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20003600
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x200034e8
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x200037d0
+#define APP_RAM_BASE_CENTRAL_LINKS_4_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x200036b8
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20002d98
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20002c38
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20002f60
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x20002e00
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003130
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20002fd0
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x200032f8
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003198
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x200034c8
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003368
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20003690
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x20003530
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x200034c8
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20003370
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003698
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003538
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003860
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003708
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20003a30
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x200038d0
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x20003bf8
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x20003aa0
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_5_MID_BW 0x20003dc8
+#define APP_RAM_BASE_CENTRAL_LINKS_5_PERIPH_LINKS_1_SEC_COUNT_5_LOW_BW 0x20003c68
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x200031c0
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20003020
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20003390
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x200031e8
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003558
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x200033b8
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20003728
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003580
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x200038f0
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003750
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20003ac0
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x20003918
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_6_MID_BW 0x20003c88
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_0_SEC_COUNT_6_LOW_BW 0x20003ae8
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x200038f8
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20003750
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003ac0
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003920
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x20003c90
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003ae8
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20003e58
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x20003cb8
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x20004028
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x20003e80
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_5_MID_BW 0x200041f0
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_5_LOW_BW 0x20004050
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_6_MID_BW 0x200043c0
+#define APP_RAM_BASE_CENTRAL_LINKS_6_PERIPH_LINKS_1_SEC_COUNT_6_LOW_BW 0x20004218
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x200035f0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x20003408
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x200037b8
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x200035d0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003988
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x200037a0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20003b50
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003968
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x20003d20
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003b38
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20003ee8
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x20003d00
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_6_MID_BW 0x200040b8
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_6_LOW_BW 0x20003ed0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_7_MID_BW 0x20004280
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_0_SEC_COUNT_7_LOW_BW 0x20004098
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_MID_BW 0x20003d28
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_0_LOW_BW 0x20003b38
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_MID_BW 0x20003ef0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_1_LOW_BW 0x20003d08
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_2_MID_BW 0x200040c0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_2_LOW_BW 0x20003ed0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_3_MID_BW 0x20004288
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_3_LOW_BW 0x200040a0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_4_MID_BW 0x20004458
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_4_LOW_BW 0x20004268
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_5_MID_BW 0x20004620
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_5_LOW_BW 0x20004438
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_6_MID_BW 0x200047f0
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_6_LOW_BW 0x20004600
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_7_MID_BW 0x200049b8
+#define APP_RAM_BASE_CENTRAL_LINKS_7_PERIPH_LINKS_1_SEC_COUNT_7_LOW_BW 0x200047d0
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_MID_BW 0x20003a18
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_0_LOW_BW 0x200037e8
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_MID_BW 0x20003be8
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_1_LOW_BW 0x200039b8
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_2_MID_BW 0x20003db0
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_2_LOW_BW 0x20003b80
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_3_MID_BW 0x20003f80
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_3_LOW_BW 0x20003d50
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_4_MID_BW 0x20004148
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_4_LOW_BW 0x20003f18
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_5_MID_BW 0x20004318
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_5_LOW_BW 0x200040e8
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_6_MID_BW 0x200044e0
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_6_LOW_BW 0x200042b0
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_7_MID_BW 0x200046b0
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_7_LOW_BW 0x20004480
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_8_MID_BW 0x20004878
+#define APP_RAM_BASE_CENTRAL_LINKS_8_PERIPH_LINKS_0_SEC_COUNT_8_LOW_BW 0x20004648
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h
new file mode 100644
index 0000000000..f40e4576e2
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/ble_stack_handler_types.h
@@ -0,0 +1,91 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/**@file
+ *
+ * @defgroup ble_stack_handler_types Types definitions for BLE support in SoftDevice handler.
+ * @{
+ * @ingroup  softdevice_handler
+ * @brief    This file contains the declarations of types required for BLE stack support. These
+ *           types will be defined when the preprocessor define BLE_STACK_SUPPORT_REQD is defined.
+ */
+
+#ifndef BLE_STACK_HANDLER_TYPES_H__
+#define BLE_STACK_HANDLER_TYPES_H__
+
+#ifdef BLE_STACK_SUPPORT_REQD
+
+#include <stdlib.h>
+#include "nrf_ble.h"
+#include "nrf_sdm.h"
+#include "app_error.h"
+#include "app_util.h"
+
+#define BLE_STACK_EVT_MSG_BUF_SIZE       (sizeof(ble_evt_t) + (GATT_MTU_SIZE_DEFAULT))     /**< Size of BLE event message buffer. This will be provided to the SoftDevice while fetching an event. */
+#define BLE_STACK_HANDLER_SCHED_EVT_SIZE 0                                                 /**< The size of the scheduler event used by SoftDevice handler when passing BLE events using the @ref app_scheduler. */
+
+/**@brief Application stack event handler type. */
+typedef void (*ble_evt_handler_t) (ble_evt_t * p_ble_evt);
+
+/**@brief     Function for registering for BLE events.
+ *
+ * @details   The application should use this function to register for receiving BLE events from
+ *            the SoftDevice. If the application does not call this function, then any BLE event
+ *            that may be generated by the SoftDevice will NOT be fetched. Once the application has
+ *            registered for the events, it is not possible to cancel the registration.
+ *            However, it is possible to register a different function for handling the events at
+ *            any point of time.
+ *
+ * @param[in] ble_evt_handler Function to be called for each received BLE event.
+ *
+ * @retval    NRF_SUCCESS     Successful registration.
+ * @retval    NRF_ERROR_NULL  Null pointer provided as input.
+ */
+uint32_t softdevice_ble_evt_handler_set(ble_evt_handler_t ble_evt_handler);
+
+#else
+
+#define BLE_STACK_EVT_MSG_BUF_SIZE        0                                                /**< Since the BLE stack support is not required, this is equated to 0, so that the @ref softdevice_handler.h can compute the internal event buffer size without having to care for BLE events.*/
+#define BLE_STACK_HANDLER_SCHED_EVT_SIZE  0
+
+#endif // BLE_STACK_SUPPORT_REQD
+
+#endif // BLE_STACK_HANDLER_TYPES_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.c
new file mode 100644
index 0000000000..5534ae6dae
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.c
@@ -0,0 +1,517 @@
+/* 
+ * Copyright (c) 2012 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "softdevice_handler.h"
+#include <stdlib.h>
+#include <stdint.h>
+#include <stdio.h>
+#include <string.h>
+#include "nordic_common.h"
+#include "app_error.h"
+#include "nrf_assert.h"
+#include "nrf_nvic.h"
+#include "nrf.h"
+#include "nrf_log.h"
+#include "sdk_common.h"
+#include "nrf_drv_config.h"
+#if CLOCK_ENABLED
+#include "nrf_drv_clock.h"
+#endif
+
+#if defined(ANT_STACK_SUPPORT_REQD) && defined(BLE_STACK_SUPPORT_REQD)
+    #include "ant_interface.h"
+#elif defined(ANT_STACK_SUPPORT_REQD)
+    #include "ant_interface.h"
+#elif defined(BLE_STACK_SUPPORT_REQD)
+    #include "nrf_ble.h"
+#endif
+
+
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+#define SD_HANDLER_LOG(...) NRF_LOG_PRINTF(__VA_ARGS__)
+#else
+#define SD_HANDLER_LOG(...)
+#endif
+
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+#define SD_HANDLER_LOG_INIT() NRF_LOG_INIT()
+#else
+#define SD_HANDLER_LOG_INIT()
+#endif
+
+
+
+#define RAM_START_ADDRESS         0x20000000
+#define SOFTDEVICE_EVT_IRQ        SD_EVT_IRQn       /**< SoftDevice Event IRQ number. Used for both protocol events and SoC events. */
+#define SOFTDEVICE_EVT_IRQHandler SD_EVT_IRQHandler
+#define RAM_TOTAL_SIZE            ((NRF_FICR->INFO.RAM)*1024)
+#define RAM_END_ADDRESS           (RAM_START_ADDRESS + RAM_TOTAL_SIZE)
+
+
+#define SOFTDEVICE_VS_UUID_COUNT       0
+#define SOFTDEVICE_GATTS_ATTR_TAB_SIZE BLE_GATTS_ATTR_TAB_SIZE_DEFAULT
+#define SOFTDEVICE_GATTS_SRV_CHANGED   0
+#define SOFTDEVICE_PERIPH_CONN_COUNT   1
+#define SOFTDEVICE_CENTRAL_CONN_COUNT  4
+#define SOFTDEVICE_CENTRAL_SEC_COUNT   1
+
+/* Global nvic state instance, required by nrf_nvic.h */
+nrf_nvic_state_t nrf_nvic_state;
+
+static softdevice_evt_schedule_func_t m_evt_schedule_func;              /**< Pointer to function for propagating SoftDevice events to the scheduler. */
+
+static volatile bool                  m_softdevice_enabled = false;     /**< Variable to indicate whether the SoftDevice is enabled. */
+
+#ifdef BLE_STACK_SUPPORT_REQD
+// The following three definitions is needed only if BLE events are needed to be pulled from the stack.
+static uint8_t                      * mp_ble_evt_buffer;                /**< Buffer for receiving BLE events from the SoftDevice. */
+static uint16_t                       m_ble_evt_buffer_size;            /**< Size of BLE event buffer. */
+static ble_evt_handler_t              m_ble_evt_handler;                /**< Application event handler for handling BLE events. */
+#endif
+
+#ifdef ANT_STACK_SUPPORT_REQD
+// The following two definition is needed only if ANT events are needed to be pulled from the stack.
+static ant_evt_t                      m_ant_evt_buffer;                 /**< Buffer for receiving ANT events from the SoftDevice. */
+static ant_evt_handler_t              m_ant_evt_handler;                /**< Application event handler for handling ANT events.  */
+#endif
+
+static sys_evt_handler_t              m_sys_evt_handler;                /**< Application event handler for handling System (SOC) events.  */
+
+
+/**@brief       Callback function for asserts in the SoftDevice.
+ *
+ * @details     A pointer to this function will be passed to the SoftDevice. This function will be
+ *              called by the SoftDevice if certain unrecoverable errors occur within the
+ *              application or SoftDevice.
+ *
+ *              See @ref nrf_fault_handler_t for more details.
+ *
+ * @param[in] id    Fault identifier. See @ref NRF_FAULT_IDS.
+ * @param[in] pc    The program counter of the instruction that triggered the fault.
+ * @param[in] info  Optional additional information regarding the fault. Refer to each fault
+ *                  identifier for details.
+ */
+void softdevice_fault_handler(uint32_t id, uint32_t pc, uint32_t info)
+{
+    app_error_fault_handler(id, pc, info);
+}
+
+
+void intern_softdevice_events_execute(void)
+{
+    if (!m_softdevice_enabled)
+    {
+        // SoftDevice not enabled. This can be possible if the SoftDevice was enabled by the
+        // application without using this module's API (i.e softdevice_handler_init)
+
+        return;
+    }
+#if CLOCK_ENABLED
+    bool no_more_soc_evts = false;
+#else
+    bool no_more_soc_evts = (m_sys_evt_handler == NULL);
+#endif
+#ifdef BLE_STACK_SUPPORT_REQD
+    bool no_more_ble_evts = (m_ble_evt_handler == NULL);
+#endif
+#ifdef ANT_STACK_SUPPORT_REQD
+    bool no_more_ant_evts = (m_ant_evt_handler == NULL);
+#endif
+
+    for (;;)
+    {
+        uint32_t err_code;
+
+        if (!no_more_soc_evts)
+        {
+            uint32_t evt_id;
+
+            // Pull event from SOC.
+            err_code = sd_evt_get(&evt_id);
+
+            if (err_code == NRF_ERROR_NOT_FOUND)
+            {
+                no_more_soc_evts = true;
+            }
+            else if (err_code != NRF_SUCCESS)
+            {
+                APP_ERROR_HANDLER(err_code);
+            }
+            else
+            {
+                // Call application's SOC event handler.
+#if CLOCK_ENABLED
+                nrf_drv_clock_on_soc_event(evt_id);
+                if (m_sys_evt_handler)
+                {
+                    m_sys_evt_handler(evt_id);
+                }
+#else
+                m_sys_evt_handler(evt_id);
+#endif
+            }
+        }
+
+#ifdef BLE_STACK_SUPPORT_REQD
+        // Fetch BLE Events.
+        if (!no_more_ble_evts)
+        {
+            // Pull event from stack
+            uint16_t evt_len = m_ble_evt_buffer_size;
+
+            err_code = sd_ble_evt_get(mp_ble_evt_buffer, &evt_len);
+            if (err_code == NRF_ERROR_NOT_FOUND)
+            {
+                no_more_ble_evts = true;
+            }
+            else if (err_code != NRF_SUCCESS)
+            {
+                APP_ERROR_HANDLER(err_code);
+            }
+            else
+            {
+                // Call application's BLE stack event handler.
+                m_ble_evt_handler((ble_evt_t *)mp_ble_evt_buffer);
+            }
+        }
+#endif
+
+#ifdef ANT_STACK_SUPPORT_REQD
+        // Fetch ANT Events.
+        if (!no_more_ant_evts)
+        {
+            // Pull event from stack
+            err_code = sd_ant_event_get(&m_ant_evt_buffer.channel,
+                                        &m_ant_evt_buffer.event,
+                                        m_ant_evt_buffer.msg.evt_buffer);
+            if (err_code == NRF_ERROR_NOT_FOUND)
+            {
+                no_more_ant_evts = true;
+            }
+            else if (err_code != NRF_SUCCESS)
+            {
+                APP_ERROR_HANDLER(err_code);
+            }
+            else
+            {
+                // Call application's ANT stack event handler.
+                m_ant_evt_handler(&m_ant_evt_buffer);
+            }
+        }
+#endif
+
+        if (no_more_soc_evts)
+        {
+            // There are no remaining System (SOC) events to be fetched from the SoftDevice.
+#if defined(ANT_STACK_SUPPORT_REQD) && defined(BLE_STACK_SUPPORT_REQD)
+            // Check if there are any remaining BLE and ANT events.
+            if (no_more_ble_evts && no_more_ant_evts)
+            {
+                break;
+            }
+#elif defined(BLE_STACK_SUPPORT_REQD)
+            // Check if there are any remaining BLE events.
+            if (no_more_ble_evts)
+            {
+                break;
+            }
+#elif defined(ANT_STACK_SUPPORT_REQD)
+            // Check if there are any remaining ANT events.
+            if (no_more_ant_evts)
+            {
+                break;
+            }
+#else
+            // No need to check for BLE or ANT events since there is no support for BLE and ANT
+            // required.
+            break;
+#endif
+        }
+    }
+}
+
+bool softdevice_handler_isEnabled(void)
+{
+    return m_softdevice_enabled;
+}
+
+uint32_t softdevice_handler_init(nrf_clock_lf_cfg_t	*           p_clock_lf_cfg,
+                                 void *                         p_ble_evt_buffer,
+                                 uint16_t                       ble_evt_buffer_size,
+                                 softdevice_evt_schedule_func_t evt_schedule_func)
+{
+    uint32_t err_code;
+
+    SD_HANDLER_LOG_INIT();
+
+    // Save configuration.
+#if defined (BLE_STACK_SUPPORT_REQD)
+    // Check that buffer is not NULL.
+    if (p_ble_evt_buffer == NULL)
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    // Check that buffer is correctly aligned.
+    if (!is_word_aligned(p_ble_evt_buffer))
+    {
+        return NRF_ERROR_INVALID_PARAM;
+    }
+
+    mp_ble_evt_buffer     = (uint8_t *)p_ble_evt_buffer;
+    m_ble_evt_buffer_size = ble_evt_buffer_size;
+#else
+    // The variables p_ble_evt_buffer and ble_evt_buffer_size is not needed if BLE Stack support
+    // is not required.
+    UNUSED_PARAMETER(p_ble_evt_buffer);
+    UNUSED_PARAMETER(ble_evt_buffer_size);
+#endif
+
+    m_evt_schedule_func = evt_schedule_func;
+
+    // Initialize SoftDevice.
+#if defined(S212) || defined(S332)
+    err_code = sd_softdevice_enable(p_clock_lf_cfg, softdevice_fault_handler, ANT_LICENSE_KEY);
+#else
+    err_code = sd_softdevice_enable(p_clock_lf_cfg, softdevice_fault_handler);
+#endif
+    if (err_code != NRF_SUCCESS)
+    {
+        return err_code;
+    }
+
+    m_softdevice_enabled = true;
+
+    // Enable BLE event interrupt (interrupt priority has already been set by the stack).
+#ifdef SOFTDEVICE_PRESENT
+    return sd_nvic_EnableIRQ((IRQn_Type)SOFTDEVICE_EVT_IRQ);
+#else
+    //In case of Serialization NVIC must be accessed directly.
+    NVIC_EnableIRQ(SOFTDEVICE_EVT_IRQ);
+    return NRF_SUCCESS;
+#endif
+}
+
+
+uint32_t softdevice_handler_sd_disable(void)
+{
+    uint32_t err_code = sd_softdevice_disable();
+
+    m_softdevice_enabled = !(err_code == NRF_SUCCESS);
+
+    return err_code;
+}
+
+
+#ifdef BLE_STACK_SUPPORT_REQD
+uint32_t softdevice_ble_evt_handler_set(ble_evt_handler_t ble_evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(ble_evt_handler);
+
+    m_ble_evt_handler = ble_evt_handler;
+
+    return NRF_SUCCESS;
+}
+#endif
+
+
+#ifdef ANT_STACK_SUPPORT_REQD
+uint32_t softdevice_ant_evt_handler_set(ant_evt_handler_t ant_evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(ant_evt_handler);
+
+    m_ant_evt_handler = ant_evt_handler;
+
+    return NRF_SUCCESS;
+}
+#endif
+
+
+uint32_t softdevice_sys_evt_handler_set(sys_evt_handler_t sys_evt_handler)
+{
+    VERIFY_PARAM_NOT_NULL(sys_evt_handler);
+
+    m_sys_evt_handler = sys_evt_handler;
+
+    return NRF_SUCCESS;
+}
+
+
+/**@brief   Function for handling the Application's BLE Stack events interrupt.
+ *
+ * @details This function is called whenever an event is ready to be pulled.
+ */
+void SOFTDEVICE_EVT_IRQHandler(void)
+{
+    if (m_evt_schedule_func != NULL)
+    {
+        uint32_t err_code = m_evt_schedule_func();
+        APP_ERROR_CHECK(err_code);
+    }
+    else
+    {
+        intern_softdevice_events_execute();
+    }
+}
+
+#if defined(BLE_STACK_SUPPORT_REQD)
+uint32_t softdevice_enable_get_default_config(uint8_t central_links_count,
+                                              uint8_t periph_links_count,
+                                              ble_enable_params_t * p_ble_enable_params)
+{
+    memset(p_ble_enable_params, 0, sizeof(ble_enable_params_t));
+    p_ble_enable_params->common_enable_params.vs_uuid_count   = 1;
+    p_ble_enable_params->gatts_enable_params.attr_tab_size    = SOFTDEVICE_GATTS_ATTR_TAB_SIZE;
+    p_ble_enable_params->gatts_enable_params.service_changed  = SOFTDEVICE_GATTS_SRV_CHANGED;
+    p_ble_enable_params->gap_enable_params.periph_conn_count  = periph_links_count;
+    p_ble_enable_params->gap_enable_params.central_conn_count = central_links_count;
+    if (p_ble_enable_params->gap_enable_params.central_conn_count != 0)
+    {
+        p_ble_enable_params->gap_enable_params.central_sec_count  = SOFTDEVICE_CENTRAL_SEC_COUNT;
+    }
+
+    return NRF_SUCCESS;
+}
+
+
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+static inline uint32_t ram_total_size_get(void)
+{
+#ifdef NRF51
+    uint32_t size_ram_blocks = (uint32_t)NRF_FICR->SIZERAMBLOCKS;
+    uint32_t total_ram_size = size_ram_blocks;
+    total_ram_size = total_ram_size*(NRF_FICR->NUMRAMBLOCK);
+    return total_ram_size;
+#elif defined (NRF52)
+    return RAM_TOTAL_SIZE;
+#endif /* NRF51 */
+}
+
+/*lint --e{528} -save suppress 528: symbol not referenced */
+/**@brief   Function for finding the end address of the RAM.
+ *
+ * @retval  ram_end_address  Address of the end of the RAM.
+ */
+static inline uint32_t ram_end_address_get(void)
+{
+    uint32_t ram_end_address = (uint32_t)RAM_START_ADDRESS;
+    ram_end_address+= ram_total_size_get();
+    return ram_end_address;
+}
+/*lint -restore*/
+#endif  //ENABLE_DEBUG_LOG_SUPPORT
+
+/*lint --e{10} --e{19} --e{27} --e{40} --e{529} -save suppress Error 27: Illegal character */
+uint32_t sd_check_ram_start(uint32_t sd_req_ram_start)
+{
+#if (defined(S130) || defined(S132) || defined(S332))
+#if defined ( __CC_ARM )
+    extern uint32_t Image$$RW_IRAM1$$Base;
+    const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base;
+#elif defined ( __ICCARM__ )
+    extern uint32_t __ICFEDIT_region_RAM_start__;
+    volatile uint32_t ram_start = (uint32_t) &__ICFEDIT_region_RAM_start__;
+#elif defined   ( __GNUC__ )
+    extern uint32_t __data_start__;
+    volatile uint32_t ram_start = (uint32_t) &__data_start__;
+#endif//__CC_ARM
+    if (ram_start != sd_req_ram_start)
+    {
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+        uint32_t app_ram_size= ram_end_address_get();
+        SD_HANDLER_LOG("RAM START ADDR 0x%x should be adjusted to 0x%x\r\n",
+                  ram_start,
+                  sd_req_ram_start);
+        app_ram_size -= sd_req_ram_start;
+        SD_HANDLER_LOG("RAM SIZE should be adjusted to 0x%x \r\n",
+                  app_ram_size);
+#endif //NRF_LOG_USES_RTT
+        return NRF_SUCCESS;
+    }
+#endif//defined(S130) || defined(S132) || defined(S332)
+    return NRF_SUCCESS;
+}
+
+uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params)
+{
+#if (defined(S130) || defined(S132) || defined(S332))
+    uint32_t err_code;
+    uint32_t app_ram_base;
+
+#if defined ( __CC_ARM )
+    extern uint32_t Image$$RW_IRAM1$$Base;
+    const volatile uint32_t ram_start = (uint32_t) &Image$$RW_IRAM1$$Base;
+#elif defined ( __ICCARM__ )
+    extern uint32_t __ICFEDIT_region_RAM_start__;
+    volatile uint32_t ram_start = (uint32_t) &__ICFEDIT_region_RAM_start__;
+#elif defined   ( __GNUC__ )
+    extern uint32_t __data_start__;
+    volatile uint32_t ram_start = (uint32_t) &__data_start__;
+#endif
+
+    app_ram_base = ram_start;
+    SD_HANDLER_LOG("sd_ble_enable: RAM START at 0x%x\r\n",
+                    app_ram_base);
+    err_code = sd_ble_enable(p_ble_enable_params, &app_ram_base);
+
+#if defined(NRF_LOG_USES_RTT) && NRF_LOG_USES_RTT == 1
+    if (app_ram_base != ram_start)
+    {
+        uint32_t app_ram_size= ram_end_address_get();
+        SD_HANDLER_LOG("sd_ble_enable: app_ram_base should be adjusted to 0x%x\r\n",
+                  app_ram_base);
+        app_ram_size -= app_ram_base;
+        SD_HANDLER_LOG("ram size should be adjusted to 0x%x \r\n",
+                  app_ram_size);
+    }
+    else if (err_code != NRF_SUCCESS)
+    {
+        SD_HANDLER_LOG("sd_ble_enable: error 0x%x\r\n", err_code);
+        while(1);
+    }
+#endif   // NRF_LOG_USES_RTT
+    return err_code;
+#else
+    return NRF_SUCCESS;
+#endif   //defined(S130) || defined(S132) || defined(S332)
+
+}
+/*lint -restore*/
+
+#endif //BLE_STACK_SUPPORT_REQD
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.h
new file mode 100644
index 0000000000..588ce1626a
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler.h
@@ -0,0 +1,240 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+/** @file
+ *
+ * @defgroup softdevice_handler SoftDevice Event Handler
+ * @{
+ * @ingroup  app_common
+ * @brief    API for initializing and disabling the SoftDevice
+ *
+ * @details  This API contains the functions and defines exposed by the @ref lib_softdevice_handler.
+ *           For more information on the library and how the application should use it, please refer
+ *           @ref lib_softdevice_handler.
+ *
+ * @note     Use the USE_SCHEDULER parameter of the SOFTDEVICE_HANDLER_INIT() macro to select if
+ *           the @ref app_scheduler is to be used or not.
+ *
+ * @note     Even if the scheduler is not used, softdevice_handler.h will include app_scheduler.h.
+ *           So when compiling, app_scheduler.h must be available in one of the compiler include
+ *           paths.
+ */
+
+#ifndef SOFTDEVICE_HANDLER_H__
+#define SOFTDEVICE_HANDLER_H__
+
+#include <stdlib.h>
+#include "nordic_common.h"
+#include "nrf_sdm.h"
+#include "app_error.h"
+#include "app_util.h"
+#include "ble_stack_handler_types.h"
+#include "ant_stack_handler_types.h"
+#if defined(BLE_STACK_SUPPORT_REQD)
+    #include "nrf_ble.h"
+#endif
+#include "app_ram_base.h"
+#define SOFTDEVICE_SCHED_EVT_SIZE       0                                                 /**< Size of button events being passed through the scheduler (is to be used for computing the maximum size of scheduler events). For SoftDevice events, this size is 0, since the events are being pulled in the event handler. */
+#define SYS_EVT_MSG_BUF_SIZE            sizeof(uint32_t)                                  /**< Size of System (SOC) event message buffer. */
+
+
+#define CHECK_RAM_START_ADDR_INTERN(CENTRAL_LINK_COUNT, PERIPHERAL_LINK_COUNT)              \
+    do{                                                                                     \
+        uint32_t app_ram_start_addr = APP_RAM_BASE_CENTRAL_LINKS_##CENTRAL_LINK_COUNT##_PERIPH_LINKS_##PERIPHERAL_LINK_COUNT##_SEC_COUNT_0_MID_BW; \
+        err_code = sd_check_ram_start(app_ram_start_addr);                                  \
+        APP_ERROR_CHECK(err_code);                                                          \
+    } while (0)
+
+/** @brief Macro for checking the RAM requirement of the SoftDevice */
+#define CHECK_RAM_START_ADDR(C_LINK_CNT, P_LINK_CNT) CHECK_RAM_START_ADDR_INTERN(C_LINK_CNT, P_LINK_CNT)
+
+
+/**@brief     Function for checking the RAM requirement of the SoftDevice.
+ *
+ * @details   Call this function to check if the project settings have the correct RAM start address in respect to what the SoftDevice requires.
+ *
+ * @note      This function is called using the CHECK_RAM_START_ADDR_INTERN macro and should not be called directly.
+ */
+uint32_t sd_check_ram_start(uint32_t sd_req_ram_start);
+
+/**@brief Type of function for passing events from the stack handler module to the scheduler. */
+typedef uint32_t (*softdevice_evt_schedule_func_t) (void);
+
+/**@brief Application System (SOC) event handler type. */
+typedef void (*sys_evt_handler_t) (uint32_t evt_id);
+
+
+/**@brief     Macro for initializing the stack event handler.
+ *
+ * @details   It will handle dimensioning and allocation of the memory buffer required for reading
+ *            events from the stack, making sure the buffer is correctly aligned. It will also
+ *            connect the stack event handler to the scheduler/RTOS (if specified).
+ *
+ * @param[in] CLOCK_SOURCE     Low frequency clock source and accuracy (type nrf_clock_lf_cfg_t_t,
+ *                             see sd_softdevice_enable() for details).
+ * @param[in] EVT_HANDLER      scheduler/RTOS event handler function.
+ *
+ * @note      Since this macro allocates a buffer, it must only be called once (it is OK to call it
+ *            several times as long as it is from the same location, that is to do a
+ *            reinitialization).
+ */
+/*lint -emacro(506, SOFTDEVICE_HANDLER_INIT) */ /* Suppress "Constant value Boolean */
+#define SOFTDEVICE_HANDLER_INIT(CLOCK_SOURCE,                                                      \
+                                EVT_HANDLER)                                                       \
+    do                                                                                             \
+    {                                                                                              \
+        static uint32_t BLE_EVT_BUFFER[CEIL_DIV(BLE_STACK_EVT_MSG_BUF_SIZE, sizeof(uint32_t))];    \
+        uint32_t ERR_CODE;                                                                         \
+        ERR_CODE = softdevice_handler_init((CLOCK_SOURCE),                                         \
+                                           BLE_EVT_BUFFER,                                         \
+                                           sizeof(BLE_EVT_BUFFER),                                 \
+                                           EVT_HANDLER);                                           \
+        APP_ERROR_CHECK(ERR_CODE);                                                                 \
+    } while (0)
+
+/**
+ * @brief Function for retrieving the information about SD state
+ *
+ * The information about current state of softdevice.
+ * @retval false SD is not initialized and SD commands should not be called.
+ * @retval true  SD is already initialized
+ */
+bool softdevice_handler_isEnabled(void);
+
+/**@brief      Function for initializing the stack handler module.
+ *
+ * @details    Enables the SoftDevice and the stack event interrupt handler.
+ *
+ * @note       This function must be called before calling any function in the SoftDevice API.
+ *
+ * @note       Normally initialization should be done using the SOFTDEVICE_HANDLER_INIT() macro,
+ *             as that will both allocate the event buffer, and also align the buffer correctly.
+ *
+ * @param[in]  p_clock_lf_cfg      Low frequency clock source to be used by the SoftDevice.
+ * @param[in]  p_ble_evt_buffer    Buffer for holding one BLE stack event. Since heap is not being
+ *                                 used, this buffer must be provided by the application. The
+ *                                 buffer must be large enough to hold the biggest stack event the
+ *                                 application is supposed to handle. The buffer must be aligned to
+ *                                 a 4 byte boundary. This parameter is unused if BLE stack support
+ *                                 is not required.
+ * @param[in]  ble_evt_buffer_size Size of SoftDevice BLE event buffer. This parameter is unused if
+ *                                 BLE stack support is not required.
+ * @param[in]  evt_schedule_func   Function for passing events to the scheduler. Point to
+ *                                 ble_ant_stack_evt_schedule() to connect to the scheduler.
+ *                                 Set to NULL to make the stack handler module call the event
+ *                                 handler directly from the stack event interrupt handler.
+ *
+ * @retval     NRF_SUCCESS               Successful initialization.
+ * @retval     NRF_ERROR_INVALID_PARAM   Invalid parameter (buffer not aligned to a 4 byte
+ *                                       boundary) or NULL.
+ */
+uint32_t softdevice_handler_init(nrf_clock_lf_cfg_t *              p_clock_lf_cfg,
+                                 void *                            p_ble_evt_buffer,
+                                 uint16_t                          ble_evt_buffer_size,
+                                 softdevice_evt_schedule_func_t    evt_schedule_func);
+
+
+/**@brief     Function for disabling the SoftDevice.
+ *
+ * @details   This function will disable the SoftDevice. It will also update the internal state
+ *            of this module.
+ */
+uint32_t softdevice_handler_sd_disable(void);
+
+
+/**@brief     Function for registering for System (SOC) events.
+ *
+ * @details   The application should use this function to register for receiving System (SOC)
+ *            events from the SoftDevice. If the application does not call this function, then any
+ *            System (SOC) events that may be generated by the SoftDevice will NOT be fetched. Once
+ *            the application has registered for the events, it is not possible to  possible to
+ *            cancel the registration. However, it is possible to register a different function for
+ *            handling the events at any point of time.
+ *
+ * @param[in] sys_evt_handler Function to be called for each received System (SOC) event.
+ *
+ * @retval    NRF_SUCCESS     Successful registration.
+ * @retval    NRF_ERROR_NULL  Null pointer provided as input.
+ */
+uint32_t softdevice_sys_evt_handler_set(sys_evt_handler_t sys_evt_handler);
+
+#if defined(BLE_STACK_SUPPORT_REQD)
+/**@brief     Function for fetching the default enable parameters for the SoftDevice.
+ *
+ * @details   The default enable parameters will work for most projects in the SDK.
+ *            They are not optimized with regards to RAM use. This function is meant as a way to abstract the
+ *            details of p_ble_enable_params needed by @ref softdevice_enable. You might want to tweak
+ *            the struct returned by this function or fill in the entire ble_enable_params_t
+ *            instead of fetching it from this function.
+ *
+ * @param[in]  central_links_count Number of central links used by the application.
+ * @param[in]  periph_links_count Number of peripheral links used by the application.
+ * @param[out] p_ble_enable_params Default ble_enable_params_t to be used by @ref softdevice_enable.
+ *
+ * @retval    NRF_SUCCESS     If the operation was successful.
+ */
+uint32_t softdevice_enable_get_default_config(uint8_t central_links_count,
+                                              uint8_t periph_links_count,
+                                              ble_enable_params_t * p_ble_enable_params);
+
+/**@brief     Function for enabling the SoftDevice.
+ *
+ * @details   This function calls the @ref sd_ble_enable SVC call. It has been abstracted to give
+ *            feedback on the app_ram_base. If the app_ram_base is too low, this function will
+ *            return an error. Using a app_ram_base that is too high will not fail, but will
+ *            result in RAM that is never used. If the DEBUG macro is enabled, this
+ *            function will provide the correct app_ram_base as mandated by the SoftDevice.
+ *            This is useful to tweak the RAM use of your application.
+ *
+ * @param[in]  p_ble_enable_params Parameters for configuring links and bandwidths.
+ *
+ * @retval    NRF_SUCCESS     If the operation was successful.
+ */
+uint32_t softdevice_enable(ble_enable_params_t * p_ble_enable_params);
+#endif //BLE_STACK_SUPPORT_REQD
+// Functions for connecting the Stack Event Handler to the scheduler:
+/**@cond NO_DOXYGEN */
+void intern_softdevice_events_execute(void);
+
+
+/**@endcond */
+
+#endif // SOFTDEVICE_HANDLER_H__
+
+/** @} */
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c
new file mode 100644
index 0000000000..bb4c2f95d4
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.c
@@ -0,0 +1,53 @@
+/* 
+ * Copyright (c) 2015 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "softdevice_handler_appsh.h"
+#include "app_scheduler.h"
+#include <string.h>
+
+void softdevice_evt_get(void * p_event_data, uint16_t event_size)
+{
+    APP_ERROR_CHECK_BOOL(event_size == 0);
+    intern_softdevice_events_execute();
+}
+
+uint32_t softdevice_evt_schedule(void)
+{
+    return app_sched_event_put(NULL, 0, softdevice_evt_get);
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h
new file mode 100644
index 0000000000..dcde1c9b96
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sdk/softdevice/common/softdevice_handler/softdevice_handler_appsh.h
@@ -0,0 +1,51 @@
+/* 
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#ifndef SOFTDEVICE_HANDLER_APPSH_H
+#define SOFTDEVICE_HANDLER_APPSH_H
+
+#include "softdevice_handler.h"
+#include <stdint.h>
+
+#define SOFTDEVICE_HANDLER_APPSH_INIT(CLOCK_SOURCE,USE_SCHEDULER) \
+    SOFTDEVICE_HANDLER_INIT(CLOCK_SOURCE,(USE_SCHEDULER) ? softdevice_evt_schedule : NULL)
+
+uint32_t softdevice_evt_schedule(void);
+
+#endif //SOFTDEVICE_HANDLER_APPSH_H
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/serial_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/serial_api.c
new file mode 100644
index 0000000000..58a8754b76
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/serial_api.c
@@ -0,0 +1,642 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include <string.h>
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "nrf_uart.h"
+#include "nrf_drv_common.h"
+#include "nrf_drv_config.h"
+#include "app_util_platform.h"
+#include "nrf_gpio.h"
+
+#define UART_INSTANCE_COUNT 1
+#define UART_INSTANCE       NRF_UART0
+#define UART_IRQn           UART0_IRQn
+#define UART_IRQ_HANDLER    UART0_IRQHandler
+#define UART_INSTANCE_ID    0
+#define UART_CB uart_cb[UART_INSTANCE_ID]
+
+#define UART_DEFAULT_BAUDRATE   UART0_CONFIG_BAUDRATE
+#define UART_DEFAULT_PARITY     UART0_CONFIG_PARITY
+#define UART_DEFAULT_HWFC       UART0_CONFIG_HWFC
+#define UART_DEFAULT_CTS        UART0_CONFIG_PSEL_CTS
+#define UART_DEFAULT_RTS        UART0_CONFIG_PSEL_RTS
+
+// Required by "retarget.cpp".
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+typedef struct {
+    bool                initialized;
+    uint32_t            irq_context;
+    uart_irq_handler    irq_handler;
+
+    uint32_t            pselrxd;
+    uint32_t            pseltxd;
+    uint32_t            pselcts;
+    uint32_t            pselrts;
+    nrf_uart_hwfc_t     hwfc;
+    nrf_uart_parity_t   parity;
+    nrf_uart_baudrate_t baudrate;
+
+#if DEVICE_SERIAL_ASYNCH
+    bool volatile       rx_active;
+    uint8_t            *rx_buffer;
+    size_t              rx_length;
+    size_t              rx_pos;
+    void              (*rx_asynch_handler)();
+    uint8_t             char_match;
+
+    bool volatile       tx_active;
+    const uint8_t      *tx_buffer;
+    size_t              tx_length;
+    size_t              tx_pos;
+    void              (*tx_asynch_handler)();
+
+    uint32_t            events_wanted;
+    uint32_t            events_occured;
+
+    #define UART_IRQ_TX 1
+    #define UART_IRQ_RX 2
+    uint8_t             irq_enabled;
+#endif // DEVICE_SERIAL_ASYNCH
+} uart_ctlblock_t;
+
+static uart_ctlblock_t uart_cb[UART_INSTANCE_COUNT];
+
+
+#if DEVICE_SERIAL_ASYNCH
+static void end_asynch_rx(void)
+{
+    // If RX interrupt is activated for synchronous operations,
+    // don't disable it, just stop handling it here.
+    if (!(UART_CB.irq_enabled & UART_IRQ_RX)) {
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
+    }
+    UART_CB.rx_active = false;
+}
+static void end_asynch_tx(void)
+{
+    // If TX interrupt is activated for synchronous operations,
+    // don't disable it, just stop handling it here.
+    if (!(UART_CB.irq_enabled & UART_IRQ_TX)) {
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
+    }
+    UART_CB.tx_active = false;
+}
+#endif // DEVICE_SERIAL_ASYNCH
+
+void UART_IRQ_HANDLER(void)
+{
+    if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY) &&
+        nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY)) {
+
+    #if DEVICE_SERIAL_ASYNCH
+        if (UART_CB.rx_active) {
+            nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
+
+            uint8_t rx_data = nrf_uart_rxd_get(UART_INSTANCE);
+            UART_CB.rx_buffer[UART_CB.rx_pos] = rx_data;
+
+            bool end_rx = false;
+            // If character matching should be performed, check if the current
+            // data matches the given one.
+            if (UART_CB.char_match != SERIAL_RESERVED_CHAR_MATCH &&
+                rx_data == UART_CB.char_match) {
+                // If it does, report the match and abort further receiving.
+                UART_CB.events_occured |= SERIAL_EVENT_RX_CHARACTER_MATCH;
+                if (UART_CB.events_wanted & SERIAL_EVENT_RX_CHARACTER_MATCH) {
+                    end_rx = true;
+                }
+            }
+            if (++UART_CB.rx_pos >= UART_CB.rx_length) {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_COMPLETE;
+                end_rx = true;
+            }
+            if (end_rx) {
+                end_asynch_rx();
+
+                if (UART_CB.rx_asynch_handler) {
+                    // Use local variable to make it possible to start a next
+                    // transfer from callback routine.
+                    void (*handler)() = UART_CB.rx_asynch_handler;
+                    UART_CB.rx_asynch_handler = NULL;
+                    handler();
+                }
+            }
+        }
+        else
+    #endif
+
+        if (UART_CB.irq_handler) {
+            UART_CB.irq_handler(UART_CB.irq_context, RxIrq);
+        }
+    }
+
+    if (nrf_uart_int_enable_check(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY) &&
+        nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) {
+
+    #if DEVICE_SERIAL_ASYNCH
+        if (UART_CB.tx_active) {
+            if (++UART_CB.tx_pos <= UART_CB.tx_length) {
+                // When there is still something to send, clear the TXDRDY event
+                // and put next byte to transmitter.
+                nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
+                nrf_uart_txd_set(UART_INSTANCE,
+                    UART_CB.tx_buffer[UART_CB.tx_pos]);
+            }
+            else {
+                // When the TXDRDY event is set after the last byte to be sent
+                // has been passed to the transmitter, the job is done and TX
+                // complete can be indicated.
+                // Don't clear the TXDRDY event, it needs to remain set for the
+                // 'serial_writable' function to work properly.
+                end_asynch_tx();
+
+                UART_CB.events_occured |= SERIAL_EVENT_TX_COMPLETE;
+                if (UART_CB.tx_asynch_handler) {
+                    // Use local variable to make it possible to start a next
+                    // transfer from callback routine.
+                    void (*handler)() = UART_CB.tx_asynch_handler;
+                    UART_CB.tx_asynch_handler = NULL;
+                    handler();
+                }
+            }
+        }
+        else
+    #endif
+
+        if (UART_CB.irq_handler) {
+            UART_CB.irq_handler(UART_CB.irq_context, TxIrq);
+        }
+    }
+
+#if DEVICE_SERIAL_ASYNCH
+    if (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_ERROR)) {
+        nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_ERROR);
+
+        uint8_t errorsrc = nrf_uart_errorsrc_get_and_clear(UART_INSTANCE);
+        if (UART_CB.rx_asynch_handler) {
+            UART_CB.events_occured |= SERIAL_EVENT_ERROR;
+            if (errorsrc & NRF_UART_ERROR_PARITY_MASK) {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_PARITY_ERROR;
+            }
+            if (errorsrc & NRF_UART_ERROR_FRAMING_MASK) {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_FRAMING_ERROR;
+            }
+            if (errorsrc & NRF_UART_ERROR_OVERRUN_MASK) {
+                UART_CB.events_occured |= SERIAL_EVENT_RX_OVERRUN_ERROR;
+            }
+            UART_CB.rx_asynch_handler();
+        }
+    }
+#endif // DEVICE_SERIAL_ASYNCH
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx) {
+    UART_CB.pseltxd =
+        (tx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)tx;
+    UART_CB.pselrxd =
+        (rx == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rx;
+    if (UART_CB.pseltxd != NRF_UART_PSEL_DISCONNECTED) {
+        nrf_gpio_pin_set(UART_CB.pseltxd);
+        nrf_gpio_cfg_output(UART_CB.pseltxd);
+    }
+    if (UART_CB.pselrxd != NRF_UART_PSEL_DISCONNECTED) {
+        nrf_gpio_cfg_input(UART_CB.pselrxd, NRF_GPIO_PIN_NOPULL);
+    }
+
+    // UART pins must only be configured when the peripheral is disabled.
+    nrf_uart_disable(UART_INSTANCE);
+
+    if (UART_CB.initialized) {
+        // Reconfigure RX/TX pins only.
+        nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
+        nrf_uart_enable(UART_INSTANCE);
+    }
+    else {
+        UART_CB.baudrate = UART_DEFAULT_BAUDRATE;
+        UART_CB.parity   = UART_DEFAULT_PARITY;
+        UART_CB.hwfc     = UART_DEFAULT_HWFC;
+        UART_CB.pselcts  = UART_DEFAULT_CTS;
+        UART_CB.pselrts  = UART_DEFAULT_RTS;
+
+        nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
+        nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
+        nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX);
+        nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX);
+
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY |
+                                            NRF_UART_INT_MASK_TXDRDY);
+    #if DEVICE_SERIAL_ASYNCH
+        nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_ERROR);
+    #endif
+        nrf_drv_common_irq_enable(UART_IRQn, APP_IRQ_PRIORITY_LOW);
+
+        // TX interrupt needs to be signaled when transmitter buffer is empty,
+        // so a dummy transmission is needed to get the TXDRDY event initially
+        // set.
+        nrf_uart_configure(UART_INSTANCE,
+            NRF_UART_PARITY_EXCLUDED, NRF_UART_HWFC_DISABLED);
+        // Use maximum baud rate, so this dummy transmission takes as little
+        // time as possible.
+        nrf_uart_baudrate_set(UART_INSTANCE, NRF_UART_BAUDRATE_1000000);
+        // Perform it with disconnected TX pin, so nothing actually comes out
+        // of the device.
+        nrf_uart_txrx_pins_disconnect(UART_INSTANCE);
+        nrf_uart_hwfc_pins_disconnect(UART_INSTANCE);
+        nrf_uart_enable(UART_INSTANCE);
+        nrf_uart_txd_set(UART_INSTANCE, 0);
+        while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) {
+        }
+        nrf_uart_disable(UART_INSTANCE);
+
+        // Now everything is prepared to set the default configuration and
+        // connect the peripheral to actual pins.
+        nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
+        nrf_uart_baudrate_set(UART_INSTANCE, UART_CB.baudrate);
+        nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc);
+        if (UART_CB.hwfc == NRF_UART_HWFC_ENABLED) {
+            serial_set_flow_control(obj, FlowControlRTSCTS,
+                UART_CB.pselrts, UART_CB.pselcts);
+        }
+        nrf_uart_enable(UART_INSTANCE);
+
+        UART_CB.initialized = true;
+    }
+
+    if (tx == STDIO_UART_TX && rx == STDIO_UART_RX) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+    else {
+        stdio_uart_inited = 0;
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    (void)obj;
+
+    if (UART_CB.initialized) {
+        nrf_uart_disable(UART_INSTANCE);
+        nrf_uart_int_disable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY |
+                                            NRF_UART_INT_MASK_TXDRDY |
+                                            NRF_UART_INT_MASK_ERROR);
+        nrf_drv_common_irq_disable(UART_IRQn);
+        UART_CB.initialized = false;
+
+        // There is only one UART instance, thus at this point the stdio UART
+        // can no longer be initialized.
+        stdio_uart_inited = 0;
+    }
+}
+
+static nrf_uart_baudrate_t baud_translate(int rate)
+{
+    nrf_uart_baudrate_t baud;
+
+    if (rate < 57600) {
+        if (rate < 14400) {
+            if (rate < 2400) {
+                baud = NRF_UART_BAUDRATE_1200;
+            } else if (rate < 4800) {
+                baud = NRF_UART_BAUDRATE_2400;
+            } else if (rate < 9600) {
+                baud = NRF_UART_BAUDRATE_4800;
+            } else {
+                baud = NRF_UART_BAUDRATE_9600;
+            }
+        } else {
+            if (rate < 19200) {
+                baud = NRF_UART_BAUDRATE_14400;
+            } else if (rate < 28800) {
+                baud = NRF_UART_BAUDRATE_19200;
+            } else if (rate < 38400) {
+                baud = NRF_UART_BAUDRATE_28800;
+            } else {
+                baud = NRF_UART_BAUDRATE_38400;
+            }
+        }
+    } else {
+        if (rate < 250000) {
+            if (rate < 76800) {
+                baud = NRF_UART_BAUDRATE_57600;
+            } else if (rate < 115200) {
+                baud = NRF_UART_BAUDRATE_76800;
+            } else if (rate < 230400) {
+                baud = NRF_UART_BAUDRATE_115200;
+            } else {
+                baud = NRF_UART_BAUDRATE_230400;
+            }
+        } else {
+            if (rate < 460800) {
+                baud = NRF_UART_BAUDRATE_250000;
+            } else if (rate < 921600) {
+                baud = NRF_UART_BAUDRATE_460800;
+            } else if (rate < 1000000) {
+                baud = NRF_UART_BAUDRATE_921600;
+            } else {
+                baud = NRF_UART_BAUDRATE_1000000;
+            }
+        }
+    }
+    return baud;
+}
+void serial_baud(serial_t *obj, int baudrate)
+{
+    (void)obj;
+    UART_CB.baudrate = baud_translate(baudrate);
+
+    // Reconfigure UART peripheral.
+    nrf_uart_baudrate_set(UART_INSTANCE, UART_CB.baudrate);
+}
+
+void serial_format(serial_t *obj,
+                   int data_bits, SerialParity parity, int stop_bits)
+{
+    (void)obj;
+
+    if (data_bits != 8) {
+        error("UART supports only 8 data bits.\r\n");
+    }
+    if (stop_bits != 1) {
+        error("UART supports only 1 stop bits.\r\n");
+    }
+    if (parity == ParityNone) {
+        UART_CB.parity = NRF_UART_PARITY_EXCLUDED;
+    } else if (parity == ParityEven) {
+        UART_CB.parity = NRF_UART_PARITY_INCLUDED;
+    } else {
+        error("UART supports only even parity.\r\n");
+    }
+
+    // Reconfigure UART peripheral.
+    nrf_uart_configure(UART_INSTANCE, UART_CB.parity, UART_CB.hwfc);
+}
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    (void)obj;
+    UART_CB.irq_handler = handler;
+    UART_CB.irq_context = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    (void)obj;
+    if (enable) {
+        switch (irq) {
+            case RxIrq:
+            #if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled |= UART_IRQ_RX;
+            #endif
+                nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
+                break;
+
+            case TxIrq:
+            #if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled |= UART_IRQ_TX;
+            #endif
+                nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
+                break;
+        }
+    } else {
+        switch (irq) {
+            case RxIrq:
+            #if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled &= ~UART_IRQ_RX;
+                if (!UART_CB.rx_active)
+            #endif
+                {
+                    nrf_uart_int_disable(UART_INSTANCE,
+                        NRF_UART_INT_MASK_RXDRDY);
+                }
+                break;
+
+            case TxIrq:
+            #if DEVICE_SERIAL_ASYNCH
+                UART_CB.irq_enabled &= ~UART_IRQ_TX;
+                if (!UART_CB.tx_active)
+            #endif
+                {
+                    nrf_uart_int_disable(UART_INSTANCE,
+                        NRF_UART_INT_MASK_TXDRDY);
+                }
+                break;
+        }
+    }
+}
+
+int serial_getc(serial_t *obj)
+{
+    while (!serial_readable(obj)) {
+    }
+
+    nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_RXDRDY);
+    return nrf_uart_rxd_get(UART_INSTANCE);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    while (!serial_writable(obj)) {
+    }
+
+    nrf_uart_event_clear(UART_INSTANCE, NRF_UART_EVENT_TXDRDY);
+    nrf_uart_txd_set(UART_INSTANCE, (uint8_t)c);
+    // Wait until sending is completed.
+    while (!nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY)) {
+    }
+}
+
+int serial_readable(serial_t *obj)
+{
+    (void)obj;
+#if DEVICE_SERIAL_ASYNCH
+    if (UART_CB.rx_active) {
+        return 0;
+    }
+#endif
+    return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_RXDRDY));
+}
+
+int serial_writable(serial_t *obj)
+{
+    (void)obj;
+#if DEVICE_SERIAL_ASYNCH
+    if (UART_CB.tx_active) {
+        return 0;
+    }
+#endif
+    return (nrf_uart_event_check(UART_INSTANCE, NRF_UART_EVENT_TXDRDY));
+}
+
+void serial_break_set(serial_t *obj)
+{
+    (void)obj;
+    nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_SUSPEND);
+    nrf_uart_txrx_pins_disconnect(UART_INSTANCE);
+    nrf_gpio_pin_clear(UART_CB.pseltxd);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+    (void)obj;
+    nrf_gpio_pin_set(UART_CB.pseltxd);
+    nrf_uart_txrx_pins_set(UART_INSTANCE, UART_CB.pseltxd, UART_CB.pselrxd);
+    nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTRX);
+    nrf_uart_task_trigger(UART_INSTANCE, NRF_UART_TASK_STARTTX);
+}
+
+void serial_set_flow_control(serial_t *obj, FlowControl type,
+                             PinName rxflow, PinName txflow)
+{
+    (void)obj;
+
+    UART_CB.pselrts =
+        (rxflow == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)rxflow;
+    UART_CB.pselcts =
+        (txflow == NC) ? NRF_UART_PSEL_DISCONNECTED : (uint32_t)txflow;
+
+    if (UART_CB.pselrts != NRF_UART_PSEL_DISCONNECTED) {
+        nrf_gpio_pin_set(UART_CB.pselrts);
+        nrf_gpio_cfg_output(UART_CB.pselrts);
+    }
+    if (UART_CB.pselcts != NRF_UART_PSEL_DISCONNECTED) {
+        nrf_gpio_cfg_input(UART_CB.pselcts, NRF_GPIO_PIN_NOPULL);
+    }
+    nrf_uart_disable(UART_INSTANCE);
+    nrf_uart_hwfc_pins_set(UART_INSTANCE, UART_CB.pselrts, UART_CB.pselcts);
+    nrf_uart_enable(UART_INSTANCE);
+}
+
+void serial_clear(serial_t *obj) {
+    (void)obj;
+}
+
+#if DEVICE_SERIAL_ASYNCH
+
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length,
+                     uint8_t tx_width, uint32_t handler, uint32_t event,
+                     DMAUsage hint)
+{
+    (void)obj;
+    (void)tx_width;
+    (void)hint;
+    if (UART_CB.tx_active || !tx_length) {
+        return 0;
+    }
+
+    UART_CB.tx_buffer = tx;
+    UART_CB.tx_length = tx_length;
+    UART_CB.tx_pos    = 0;
+    UART_CB.tx_asynch_handler = (void(*)())handler;
+    UART_CB.events_wanted &= ~SERIAL_EVENT_TX_ALL;
+    UART_CB.events_wanted |= event;
+
+    UART_CB.tx_active = true;
+    nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_TXDRDY);
+
+    return 0;
+}
+
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length,
+                      uint8_t rx_width, uint32_t handler, uint32_t event,
+                      uint8_t char_match, DMAUsage hint)
+{
+    (void)obj;
+    (void)rx_width;
+    (void)hint;
+    if (UART_CB.rx_active || !rx_length) {
+        return;
+    }
+
+    UART_CB.rx_buffer = rx;
+    UART_CB.rx_length = rx_length;
+    UART_CB.rx_pos    = 0;
+    UART_CB.rx_asynch_handler = (void(*)())handler;
+    UART_CB.events_wanted &= ~SERIAL_EVENT_RX_ALL;
+    UART_CB.events_wanted |= event;
+    UART_CB.char_match = char_match;
+
+    UART_CB.rx_active = true;
+    nrf_uart_int_enable(UART_INSTANCE, NRF_UART_INT_MASK_RXDRDY);
+}
+
+uint8_t serial_tx_active(serial_t *obj)
+{
+    (void)obj;
+    return UART_CB.tx_active;
+}
+
+uint8_t serial_rx_active(serial_t *obj)
+{
+    (void)obj;
+    return UART_CB.rx_active;
+}
+
+int serial_irq_handler_asynch(serial_t *obj)
+{
+    (void)obj;
+    uint32_t events_to_report = UART_CB.events_wanted & UART_CB.events_occured;
+    UART_CB.events_occured &= (~events_to_report);
+    return events_to_report;
+}
+
+void serial_tx_abort_asynch(serial_t *obj)
+{
+    (void)obj;
+    end_asynch_tx();
+    UART_CB.tx_asynch_handler = NULL;
+}
+
+void serial_rx_abort_asynch(serial_t *obj)
+{
+    (void)obj;
+    end_asynch_rx();
+    UART_CB.rx_asynch_handler = NULL;
+}
+
+#endif // DEVICE_SERIAL_ASYNCH
+
+#endif // DEVICE_SERIAL
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sleep.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sleep.c
new file mode 100644
index 0000000000..3c5ab7dbae
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/sleep.c
@@ -0,0 +1,32 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "sleep_api.h"
+#include "cmsis.h"
+#include "mbed_interface.h"
+
+void sleep(void)
+{
+    // ensure debug is disconnected if semihost is enabled....
+    NRF_POWER->TASKS_LOWPWR = 1;
+    // wait for interrupt
+    __WFE();
+}
+
+void deepsleep(void)
+{
+    sleep();
+    //   NRF_POWER->SYSTEMOFF=1;
+}
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/spi_api.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/spi_api.c
new file mode 100644
index 0000000000..00be918087
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/spi_api.c
@@ -0,0 +1,507 @@
+/* 
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ * 
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 
+ *   1. Redistributions of source code must retain the above copyright notice, this list 
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA 
+ *      integrated circuit in a product or a software update for such product, must reproduce 
+ *      the above copyright notice, this list of conditions and the following disclaimer in 
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be 
+ *      used to endorse or promote products derived from this software without specific prior 
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a 
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse 
+ *      engineered, decompiled, modified and/or disassembled. 
+ * 
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * 
+ */
+
+
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_assert.h"
+#include "mbed_error.h"
+#include "nrf_drv_spi.h"
+#include "nrf_drv_spis.h"
+#include "app_util_platform.h"
+
+#if DEVICE_SPI_ASYNCH
+    #define SPI_IDX(obj)    ((obj)->spi.spi_idx)
+#else
+    #define SPI_IDX(obj)    ((obj)->spi_idx)
+#endif
+#define SPI_INFO(obj)       (&m_spi_info[SPI_IDX(obj)])
+#define MASTER_INST(obj)    (&m_instances[SPI_IDX(obj)].master)
+#define SLAVE_INST(obj)     (&m_instances[SPI_IDX(obj)].slave)
+
+typedef struct {
+    bool    initialized;
+    bool    master;
+    uint8_t sck_pin;
+    uint8_t mosi_pin;
+    uint8_t miso_pin;
+    uint8_t ss_pin;
+    uint8_t spi_mode;
+    nrf_drv_spi_frequency_t frequency;
+    volatile union {
+        bool busy;     // master
+        bool readable; // slave
+    } flag;
+    volatile uint8_t tx_buf;
+    volatile uint8_t rx_buf;
+
+#if DEVICE_SPI_ASYNCH
+    uint32_t handler;
+    uint32_t event;
+#endif
+} spi_info_t;
+static spi_info_t m_spi_info[SPI_COUNT];
+
+typedef struct {
+    nrf_drv_spi_t  master;
+    nrf_drv_spis_t slave;
+} sdk_driver_instances_t;
+static sdk_driver_instances_t m_instances[SPI_COUNT] = {
+    #if SPI0_ENABLED
+    {
+        NRF_DRV_SPI_INSTANCE(0),
+        NRF_DRV_SPIS_INSTANCE(0)
+    },
+    #endif
+    #if SPI1_ENABLED
+    {
+        NRF_DRV_SPI_INSTANCE(1),
+        NRF_DRV_SPIS_INSTANCE(1)
+    },
+    #endif
+    #if SPI2_ENABLED
+    {
+        NRF_DRV_SPI_INSTANCE(2),
+        NRF_DRV_SPIS_INSTANCE(2)
+    },
+    #endif
+};
+
+static void master_event_handler(uint8_t spi_idx,
+                                 nrf_drv_spi_evt_t const *p_event)
+{
+    spi_info_t *p_spi_info = &m_spi_info[spi_idx];
+
+    if (p_event->type == NRF_DRV_SPI_EVENT_DONE) {
+        p_spi_info->flag.busy = false;
+        if (p_spi_info->handler) {
+            void (*handler)(void) = (void (*)(void))p_spi_info->handler;
+            p_spi_info->handler = 0;
+            handler();
+        }
+    }
+}
+#define MASTER_EVENT_HANDLER(idx) \
+    static void master_event_handler_##idx(nrf_drv_spi_evt_t const *p_event) { \
+        master_event_handler(SPI##idx##_INSTANCE_INDEX, p_event); \
+    }
+#if SPI0_ENABLED
+    MASTER_EVENT_HANDLER(0)
+#endif
+#if SPI1_ENABLED
+    MASTER_EVENT_HANDLER(1)
+#endif
+#if SPI2_ENABLED
+    MASTER_EVENT_HANDLER(2)
+#endif
+
+static nrf_drv_spi_handler_t const m_master_event_handlers[SPI_COUNT] = {
+#if SPI0_ENABLED
+    master_event_handler_0,
+#endif
+#if SPI1_ENABLED
+    master_event_handler_1,
+#endif
+#if SPI2_ENABLED
+    master_event_handler_2,
+#endif
+};
+
+
+static void slave_event_handler(uint8_t spi_idx,
+                                nrf_drv_spis_event_t event)
+{
+    spi_info_t *p_spi_info = &m_spi_info[spi_idx];
+
+    if (event.evt_type == NRF_DRV_SPIS_XFER_DONE) {
+        // Signal that there is some data received that could be read.
+        p_spi_info->flag.readable = true;
+
+        // And prepare for the next transfer.
+        // Previous data set in 'spi_slave_write' (if any) has been transmitted,
+        // now use the default one, until some new is set by 'spi_slave_write'.
+        p_spi_info->tx_buf = NRF_DRV_SPIS_DEFAULT_ORC;
+        nrf_drv_spis_buffers_set(&m_instances[spi_idx].slave,
+            (uint8_t const *)&p_spi_info->tx_buf, 1,
+            (uint8_t *)&p_spi_info->rx_buf, 1);
+    }
+}
+#define SLAVE_EVENT_HANDLER(idx) \
+    static void slave_event_handler_##idx(nrf_drv_spis_event_t event) { \
+        slave_event_handler(SPIS##idx##_INSTANCE_INDEX, event); \
+    }
+#if SPIS0_ENABLED
+    SLAVE_EVENT_HANDLER(0)
+#endif
+#if SPIS1_ENABLED
+    SLAVE_EVENT_HANDLER(1)
+#endif
+#if SPIS2_ENABLED
+    SLAVE_EVENT_HANDLER(2)
+#endif
+
+static nrf_drv_spis_event_handler_t const m_slave_event_handlers[SPIS_COUNT] = {
+#if SPIS0_ENABLED
+    slave_event_handler_0,
+#endif
+#if SPIS1_ENABLED
+    slave_event_handler_1,
+#endif
+#if SPIS2_ENABLED
+    slave_event_handler_2,
+#endif
+};
+
+static void prepare_master_config(nrf_drv_spi_config_t *p_config,
+                                  spi_info_t const *p_spi_info)
+{
+    p_config->sck_pin   = p_spi_info->sck_pin;
+    p_config->mosi_pin  = p_spi_info->mosi_pin;
+    p_config->miso_pin  = p_spi_info->miso_pin;
+    p_config->ss_pin    = p_spi_info->ss_pin;
+    p_config->frequency = p_spi_info->frequency;
+    p_config->mode      = (nrf_drv_spi_mode_t)p_spi_info->spi_mode;
+
+    p_config->irq_priority = APP_IRQ_PRIORITY_LOW;
+    p_config->orc          = 0xFF;
+    p_config->bit_order    = NRF_DRV_SPI_BIT_ORDER_MSB_FIRST;
+}
+
+static void prepare_slave_config(nrf_drv_spis_config_t *p_config,
+                                 spi_info_t const *p_spi_info)
+{
+    p_config->sck_pin   = p_spi_info->sck_pin;
+    p_config->mosi_pin  = p_spi_info->mosi_pin;
+    p_config->miso_pin  = p_spi_info->miso_pin;
+    p_config->csn_pin   = p_spi_info->ss_pin;
+    p_config->mode      = (nrf_drv_spis_mode_t)p_spi_info->spi_mode;
+
+    p_config->irq_priority = APP_IRQ_PRIORITY_LOW;
+    p_config->orc          = NRF_DRV_SPIS_DEFAULT_ORC;
+    p_config->def          = NRF_DRV_SPIS_DEFAULT_DEF;
+    p_config->bit_order    = NRF_DRV_SPIS_BIT_ORDER_MSB_FIRST;
+    p_config->csn_pullup   = NRF_DRV_SPIS_DEFAULT_CSN_PULLUP;
+    p_config->miso_drive   = NRF_DRV_SPIS_DEFAULT_MISO_DRIVE;
+}
+
+void spi_init(spi_t *obj,
+              PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    int i;
+    for (i = 0; i < SPI_COUNT; ++i) {
+        spi_info_t *p_spi_info = &m_spi_info[i];
+        if (!p_spi_info->initialized) {
+            p_spi_info->sck_pin   = (uint8_t)sclk;
+            p_spi_info->mosi_pin  = (mosi != NC) ?
+                (uint8_t)mosi : NRF_DRV_SPI_PIN_NOT_USED;
+            p_spi_info->miso_pin  = (miso != NC) ?
+                (uint8_t)miso : NRF_DRV_SPI_PIN_NOT_USED;
+            p_spi_info->ss_pin    = (ssel != NC) ?
+                (uint8_t)ssel : NRF_DRV_SPI_PIN_NOT_USED;
+            p_spi_info->spi_mode  = (uint8_t)NRF_DRV_SPI_MODE_0;
+            p_spi_info->frequency = NRF_DRV_SPI_FREQ_1M;
+
+            // By default each SPI instance is initialized to work as a master.
+            // Should the slave mode be used, the instance will be reconfigured
+            // appropriately in 'spi_format'.
+            nrf_drv_spi_config_t config;
+            prepare_master_config(&config, p_spi_info);
+
+            nrf_drv_spi_t const *p_spi = &m_instances[i].master;
+            ret_code_t ret_code = nrf_drv_spi_init(p_spi,
+                &config, m_master_event_handlers[i]);
+            if (ret_code == NRF_SUCCESS) {
+                p_spi_info->initialized = true;
+                p_spi_info->master      = true;
+                p_spi_info->flag.busy   = false;
+            #if DEVICE_SPI_ASYNCH
+                p_spi_info->handler     = 0;
+            #endif
+                SPI_IDX(obj) = i;
+
+                return;
+            }
+        }
+    }
+
+    // No available peripheral
+    error("No available SPI peripheral\r\n");
+}
+
+void spi_free(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    if (p_spi_info->master) {
+        nrf_drv_spi_uninit(MASTER_INST(obj));
+    }
+    else {
+        nrf_drv_spis_uninit(SLAVE_INST(obj));
+    }
+    p_spi_info->initialized = false;
+}
+
+int spi_busy(spi_t *obj)
+{
+    return (int)(SPI_INFO(obj)->flag.busy);
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    if (bits != 8) {
+        error("Only 8-bits SPI is supported\r\n");
+    }
+    if (mode > 3) {
+        error("SPI format error\r\n");
+    }
+
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+
+    if (slave)
+    {
+        nrf_drv_spis_mode_t spi_modes[4] = {
+            NRF_DRV_SPIS_MODE_0,
+            NRF_DRV_SPIS_MODE_1,
+            NRF_DRV_SPIS_MODE_2,
+            NRF_DRV_SPIS_MODE_3,
+        };
+        nrf_drv_spis_mode_t new_mode = spi_modes[mode];
+
+        // If the peripheral is currently working as a master, the SDK driver
+        // it uses needs to be switched from SPI to SPIS.
+        if (p_spi_info->master) {
+            nrf_drv_spi_uninit(MASTER_INST(obj));
+        }
+        // I the SPI mode has to be changed, the SDK's SPIS driver needs to be
+        // re-initialized (there is no other way to change its configuration).
+        else if (p_spi_info->spi_mode != (uint8_t)new_mode) {
+            nrf_drv_spis_uninit(SLAVE_INST(obj));
+        }
+        else {
+            return;
+        }
+
+        p_spi_info->spi_mode = (uint8_t)new_mode;
+        p_spi_info->master = false;
+        p_spi_info->flag.readable = false;
+
+        // Initialize SDK's SPIS driver with the new configuration.
+        nrf_drv_spis_config_t config;
+        prepare_slave_config(&config, p_spi_info);
+        (void)nrf_drv_spis_init(SLAVE_INST(obj), &config,
+            m_slave_event_handlers[SPI_IDX(obj)]);
+
+        // Prepare the slave for transfer.
+        p_spi_info->tx_buf = NRF_DRV_SPIS_DEFAULT_ORC;
+        nrf_drv_spis_buffers_set(SLAVE_INST(obj),
+            (uint8_t const *)&p_spi_info->tx_buf, 1,
+            (uint8_t *)&p_spi_info->rx_buf, 1);
+    }
+    else // master
+    {
+        nrf_drv_spi_mode_t spi_modes[4] = {
+            NRF_DRV_SPI_MODE_0,
+            NRF_DRV_SPI_MODE_1,
+            NRF_DRV_SPI_MODE_2,
+            NRF_DRV_SPI_MODE_3,
+        };
+        nrf_drv_spi_mode_t new_mode = spi_modes[mode];
+
+        // If the peripheral is currently working as a slave, the SDK driver
+        // it uses needs to be switched from SPIS to SPI.
+        if (!p_spi_info->master) {
+            nrf_drv_spis_uninit(SLAVE_INST(obj));
+        }
+        // I the SPI mode has to be changed, the SDK's SPI driver needs to be
+        // re-initialized (there is no other way to change its configuration).
+        else if (p_spi_info->spi_mode != (uint8_t)new_mode) {
+            nrf_drv_spi_uninit(MASTER_INST(obj));
+        }
+        else {
+            return;
+        }
+
+        p_spi_info->spi_mode = (uint8_t)new_mode;
+        p_spi_info->master = true;
+        p_spi_info->flag.busy = false;
+
+        // Initialize SDK's SPI driver with the new configuration.
+        nrf_drv_spi_config_t config;
+        prepare_master_config(&config, p_spi_info);
+        (void)nrf_drv_spi_init(MASTER_INST(obj), &config,
+            m_master_event_handlers[SPI_IDX(obj)]);
+    }
+}
+
+static nrf_drv_spi_frequency_t freq_translate(int hz)
+{
+    nrf_drv_spi_frequency_t frequency;
+    if (hz<250000) { //125Kbps
+        frequency = NRF_DRV_SPI_FREQ_125K;
+    } else if (hz<500000) { //250Kbps
+        frequency = NRF_DRV_SPI_FREQ_250K;
+    } else if (hz<1000000) { //500Kbps
+        frequency = NRF_DRV_SPI_FREQ_500K;
+    } else if (hz<2000000) { //1Mbps
+        frequency = NRF_DRV_SPI_FREQ_1M;
+    } else if (hz<4000000) { //2Mbps
+        frequency = NRF_DRV_SPI_FREQ_2M;
+    } else if (hz<8000000) { //4Mbps
+        frequency = NRF_DRV_SPI_FREQ_4M;
+    } else { //8Mbps
+        frequency = NRF_DRV_SPI_FREQ_8M;
+    }
+    return frequency;
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    nrf_drv_spi_frequency_t new_frequency = freq_translate(hz);
+
+    if (p_spi_info->master)
+    {
+        if (p_spi_info->frequency != new_frequency) {
+            p_spi_info->frequency = new_frequency;
+
+            nrf_drv_spi_config_t config;
+            prepare_master_config(&config, p_spi_info);
+
+            nrf_drv_spi_t const *p_spi = MASTER_INST(obj);
+            nrf_drv_spi_uninit(p_spi);
+            (void)nrf_drv_spi_init(p_spi, &config,
+                m_master_event_handlers[SPI_IDX(obj)]);
+        }
+    }
+    // There is no need to set anything in slaves when it comes to frequency,
+    // since slaves just synchronize with the clock provided by a master.
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+
+#if DEVICE_SPI_ASYNCH
+    while (p_spi_info->flag.busy) {
+    }
+#endif
+
+    p_spi_info->tx_buf = value;
+    p_spi_info->flag.busy = true;
+    (void)nrf_drv_spi_transfer(MASTER_INST(obj),
+        (uint8_t const *)&p_spi_info->tx_buf, 1,
+        (uint8_t *)&p_spi_info->rx_buf, 1);
+    while (p_spi_info->flag.busy) {
+    }
+
+    return p_spi_info->rx_buf;
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(!p_spi_info->master);
+    return p_spi_info->flag.readable;
+;
+}
+
+int spi_slave_read(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(!p_spi_info->master);
+    while (!p_spi_info->flag.readable) {
+    }
+    p_spi_info->flag.readable = false;
+    return p_spi_info->rx_buf;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(!p_spi_info->master);
+
+    p_spi_info->tx_buf = (uint8_t)value;
+}
+
+#if DEVICE_SPI_ASYNCH
+
+void spi_master_transfer(spi_t *obj,
+                         const void *tx, size_t tx_length,
+                         void *rx, size_t rx_length, uint8_t bit_width,
+                         uint32_t handler, uint32_t event, DMAUsage hint)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(p_spi_info->master);
+    (void)hint;
+    (void)bit_width;
+
+    p_spi_info->handler = handler;
+    p_spi_info->event   = event;
+
+    p_spi_info->flag.busy = true;
+    (void)nrf_drv_spi_transfer(MASTER_INST(obj),
+        (uint8_t const *)tx, tx_length,
+        (uint8_t *)rx, rx_length);
+}
+
+uint32_t spi_irq_handler_asynch(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(p_spi_info->master);
+    return p_spi_info->event & SPI_EVENT_COMPLETE;
+}
+
+uint8_t spi_active(spi_t *obj)
+{
+    spi_info_t *p_spi_info = SPI_INFO(obj);
+    MBED_ASSERT(p_spi_info->master);
+    return p_spi_info->flag.busy;
+}
+
+void spi_abort_asynch(spi_t *obj)
+{
+    MBED_ASSERT(SPI_INFO(obj)->master);
+    nrf_drv_spi_abort(MASTER_INST(obj));
+}
+
+#endif // DEVICE_SPI_ASYNCH
+
+#endif // DEVICE_SPI
diff --git a/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/us_ticker.c b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/us_ticker.c
new file mode 100644
index 0000000000..0aeaa70068
--- /dev/null
+++ b/hal/targets/hal/TARGET_NORDIC/TARGET_NRF5/us_ticker.c
@@ -0,0 +1,562 @@
+/*
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ *   1. Redistributions of source code must retain the above copyright notice, this list
+ *      of conditions and the following disclaimer.
+ *
+ *   2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ *      integrated circuit in a product or a software update for such product, must reproduce
+ *      the above copyright notice, this list of conditions and the following disclaimer in
+ *      the documentation and/or other materials provided with the distribution.
+ *
+ *   3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ *      used to endorse or promote products derived from this software without specific prior
+ *      written permission.
+ *
+ *   4. This software, with or without modification, must only be used with a
+ *      Nordic Semiconductor ASA integrated circuit.
+ *
+ *   5. Any software provided in binary or object form under this license must not be reverse
+ *      engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#include "us_ticker_api.h"
+#include "common_rtc.h"
+#include "app_util.h"
+#include "nrf_drv_common.h"
+#include "lp_ticker_api.h"
+
+
+//------------------------------------------------------------------------------
+// Common stuff used also by lp_ticker and rtc_api (see "common_rtc.h").
+//
+#include "app_util_platform.h"
+
+bool              m_common_rtc_enabled = false;
+uint32_t volatile m_common_rtc_overflows = 0;
+
+#if defined(TARGET_MCU_NRF51822)
+void common_rtc_irq_handler(void)
+#else
+void COMMON_RTC_IRQ_HANDLER(void)
+#endif
+{
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
+        us_ticker_irq_handler();
+    }
+
+#if DEVICE_LOWPOWERTIMER
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
+
+        lp_ticker_irq_handler();
+    }
+#endif
+
+    if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
+        nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
+        // Don't disable this event. It shall occur periodically.
+
+        ++m_common_rtc_overflows;
+    }
+}
+
+void common_rtc_init(void)
+{
+    if (m_common_rtc_enabled) {
+        return;
+    }
+
+    // RTC is driven by the low frequency (32.768 kHz) clock, a proper request
+    // must be made to have it running.
+    // Currently this clock is started in 'SystemInit' (see "system_nrf51.c"
+    // or "system_nrf52.c", respectively).
+
+    nrf_rtc_prescaler_set(COMMON_RTC_INSTANCE, 0);
+
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
+#if defined(TARGET_MCU_NRF51822)
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
+#endif
+#if DEVICE_LOWPOWERTIMER
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, LP_TICKER_EVENT);
+#endif
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW);
+
+    // Interrupts on all related events are enabled permanently. Particular
+    // events will be enabled or disabled as needed (such approach is more
+    // energy efficient).
+    nrf_rtc_int_enable(COMMON_RTC_INSTANCE,
+    #if defined(TARGET_MCU_NRF51822)
+        OS_TICK_INT_MASK |
+    #endif
+    #if DEVICE_LOWPOWERTIMER
+        LP_TICKER_INT_MASK |
+    #endif
+        US_TICKER_INT_MASK |
+        NRF_RTC_INT_OVERFLOW_MASK);
+
+    // This event is enabled permanently, since overflow indications are needed
+    // continuously.
+    nrf_rtc_event_enable(COMMON_RTC_INSTANCE, NRF_RTC_INT_OVERFLOW_MASK);
+    // All other relevant events are initially disabled.
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE,
+    #if defined(TARGET_MCU_NRF51822)
+        OS_TICK_INT_MASK |
+    #endif
+    #if DEVICE_LOWPOWERTIMER
+        LP_TICKER_INT_MASK |
+    #endif
+        US_TICKER_INT_MASK);
+
+    nrf_drv_common_irq_enable(nrf_drv_get_IRQn(COMMON_RTC_INSTANCE),
+        APP_IRQ_PRIORITY_LOW);
+
+    nrf_rtc_task_trigger(COMMON_RTC_INSTANCE, NRF_RTC_TASK_START);
+
+    m_common_rtc_enabled = true;
+}
+
+uint32_t common_rtc_32bit_ticks_get(void)
+{
+    uint32_t ticks = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+    // The counter used for time measurements is less than 32 bit wide,
+    // so its value is complemented with the number of registered overflows
+    // of the counter.
+    ticks += (m_common_rtc_overflows << RTC_COUNTER_BITS);
+    return ticks;
+}
+
+uint64_t common_rtc_64bit_us_get(void)
+{
+    uint32_t ticks = common_rtc_32bit_ticks_get();
+    // [ticks -> microseconds]
+    return ROUNDED_DIV(((uint64_t)ticks) * 1000000, RTC_INPUT_FREQ);
+}
+
+void common_rtc_set_interrupt(uint32_t us_timestamp, uint32_t cc_channel,
+                              uint32_t int_mask)
+{
+    // The internal counter is clocked with a frequency that cannot be easily
+    // multiplied to 1 MHz, therefore besides the translation of values
+    // (microsecond <-> ticks) a special care of overflows handling must be
+    // taken. Here the 32-bit timestamp value is complemented with information
+    // about current the system up time of (ticks + number of overflows of tick
+    // counter on upper bits, converted to microseconds), and such 64-bit value
+    // is then translated to counter ticks. Finally, the lower 24 bits of thus
+    // calculated value is written to the counter compare register to prepare
+    // the interrupt generation.
+    uint64_t current_time64 = common_rtc_64bit_us_get();
+    // [add upper 32 bits from the current time to the timestamp value]
+    uint64_t timestamp64 = us_timestamp +
+        (current_time64 & ~(uint64_t)0xFFFFFFFF);
+    // [if the original timestamp value happens to be after the 32 bit counter
+    //  of microsends overflows, correct the upper 32 bits accordingly]
+    if (us_timestamp < (uint32_t)(current_time64 & 0xFFFFFFFF)) {
+        timestamp64 += ((uint64_t)1 << 32);
+    }
+    // [microseconds -> ticks, always round the result up to avoid too early
+    //  interrupt generation]
+    uint32_t compare_value =
+        (uint32_t)CEIL_DIV((timestamp64) * RTC_INPUT_FREQ, 1000000);
+
+    // The COMPARE event occurs when the value in compare register is N and
+    // the counter value changes from N-1 to N. Therefore, the minimal safe
+    // difference between the compare value to be set and the current counter
+    // value is 2 ticks. This guarantees that the compare trigger is properly
+    // setup before the compare condition occurs.
+    uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
+    if ((int)(compare_value - closest_safe_compare) <= 0) {
+        compare_value = closest_safe_compare;
+    }
+
+    nrf_rtc_cc_set(COMMON_RTC_INSTANCE, cc_channel, RTC_WRAP(compare_value));
+    nrf_rtc_event_enable(COMMON_RTC_INSTANCE, int_mask);
+}
+//------------------------------------------------------------------------------
+
+
+void us_ticker_init(void)
+{
+    common_rtc_init();
+}
+
+uint32_t us_ticker_read()
+{
+    us_ticker_init();
+    return (uint32_t)common_rtc_64bit_us_get();
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    common_rtc_set_interrupt(timestamp,
+        US_TICKER_CC_CHANNEL, US_TICKER_INT_MASK);
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
+}
+
+
+// Since there is no SysTick on NRF51, the RTC1 channel 1 is used as an
+// alternative source of RTOS ticks.
+#if defined(TARGET_MCU_NRF51822)
+
+#include "toolchain.h"
+
+
+#define MAX_RTC_COUNTER_VAL     ((1uL << RTC_COUNTER_BITS) - 1)
+
+/**
+ * The value previously set in the capture compare register of channel 1
+ */
+static uint32_t previous_tick_cc_value = 0;
+
+/*
+ RTX provide the following definitions which are used by the tick code:
+   * os_trv: The number (minus 1) of clock cycle between two tick.
+   * os_clockrate: Time duration between two ticks (in us).
+   * OS_Tick_Handler: The function which handle a tick event.
+     This function is special because it never returns.
+ Those definitions are used by the code which handle the os tick.
+ To allow compilation of us_ticker programs without RTOS, those symbols are
+ exported from this module as weak ones.
+ */
+MBED_WEAK uint32_t const os_trv;
+MBED_WEAK uint32_t const os_clockrate;
+MBED_WEAK void OS_Tick_Handler() { }
+
+
+#if defined (__CC_ARM)         /* ARMCC Compiler */
+
+__asm void COMMON_RTC_IRQ_HANDLER(void)
+{
+    IMPORT  OS_Tick_Handler
+    IMPORT  common_rtc_irq_handler
+
+    /**
+     * Chanel 1 of RTC1 is used by RTX as a systick.
+     * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
+     * Otherwise, just execute common_rtc_irq_handler.
+     * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
+     * will never return.
+     * A c function would put lr on the stack before calling OS_Tick_Handler and this value
+     * would never been dequeued.
+     *
+     * \code
+     * void COMMON_RTC_IRQ_HANDLER(void) {
+         if(NRF_RTC1->EVENTS_COMPARE[1]) {
+             // never return...
+             OS_Tick_Handler();
+         } else {
+             common_rtc_irq_handler();
+         }
+       }
+     * \endcode
+     */
+    ldr r0,=0x40011144
+    ldr r1, [r0, #0]
+    cmp r1, #0
+    beq US_TICKER_HANDLER
+    bl OS_Tick_Handler
+US_TICKER_HANDLER
+    push {r3, lr}
+    bl common_rtc_irq_handler
+    pop {r3, pc}
+    nop /* padding */
+}
+
+#elif defined (__GNUC__)        /* GNU Compiler */
+
+__attribute__((naked)) void COMMON_RTC_IRQ_HANDLER(void)
+{
+    /**
+     * Chanel 1 of RTC1 is used by RTX as a systick.
+     * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
+     * Otherwise, just execute common_rtc_irq_handler.
+     * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
+     * will never return.
+     * A c function would put lr on the stack before calling OS_Tick_Handler and this value
+     * would never been dequeued.
+     *
+     * \code
+     * void COMMON_RTC_IRQ_HANDLER(void) {
+         if(NRF_RTC1->EVENTS_COMPARE[1]) {
+             // never return...
+             OS_Tick_Handler();
+         } else {
+             common_rtc_irq_handler();
+         }
+       }
+     * \endcode
+     */
+    __asm__ (
+        "ldr r0,=0x40011144\n"
+        "ldr r1, [r0, #0]\n"
+        "cmp r1, #0\n"
+        "beq US_TICKER_HANDLER\n"
+        "bl OS_Tick_Handler\n"
+    "US_TICKER_HANDLER:\n"
+        "push {r3, lr}\n"
+        "bl common_rtc_irq_handler\n"
+        "pop {r3, pc}\n"
+        "nop"
+    );
+}
+
+#elif defined (__ICCARM__)//IAR
+void common_rtc_irq_handler(void);
+
+__stackless __task void COMMON_RTC_IRQ_HANDLER(void)
+{
+    uint32_t temp;
+
+    __asm volatile(
+    "   ldr  %[temp], [%[reg2check]] \n"
+    "   cmp  %[temp], #0             \n"
+    "   beq  1f                      \n"
+    "   bl.w OS_Tick_Handler            \n"
+    "1:                             \n"
+    "   push {r3, lr}\n"
+    "   blx %[rtc_irq] \n"
+    "   pop {r3, pc}\n"
+
+    : /* Outputs */
+    [temp] "=&r"(temp)
+    : /* Inputs */
+    [reg2check] "r"(0x40011144),
+    [rtc_irq] "r"(common_rtc_irq_handler)
+    : /* Clobbers */
+    "cc"
+    );
+    (void)temp;
+}
+
+
+#else
+
+#error Compiler not supported.
+#error Provide a definition of COMMON_RTC_IRQ_HANDLER.
+
+/*
+ * Chanel 1 of RTC1 is used by RTX as a systick.
+ * If the compare event on channel 1 is set, then branch to OS_Tick_Handler.
+ * Otherwise, just execute common_rtc_irq_handler.
+ * This function has to be written in assembly and tagged as naked because OS_Tick_Handler
+ * will never return.
+ * A c function would put lr on the stack before calling OS_Tick_Handler and this value
+ * will never been dequeued. After a certain time a stack overflow will happen.
+ *
+ * \code
+ * void COMMON_RTC_IRQ_HANDLER(void) {
+     if(NRF_RTC1->EVENTS_COMPARE[1]) {
+         // never return...
+         OS_Tick_Handler();
+     } else {
+         common_rtc_irq_handler();
+     }
+   }
+ * \endcode
+ */
+
+#endif
+
+/**
+ * Return the next number of clock cycle needed for the next tick.
+ * @note This function has been carrefuly optimized for a systick occuring every 1000us.
+ */
+static uint32_t get_next_tick_cc_delta() {
+    uint32_t delta = 0;
+
+    if (os_clockrate != 1000) {
+        // In RTX, by default SYSTICK is is used.
+        // A tick event is generated  every os_trv + 1 clock cycles of the system timer.
+        delta = os_trv + 1;
+    } else {
+        // If the clockrate is set to 1000us then 1000 tick should happen every second.
+        // Unfortunatelly, when clockrate is set to 1000, os_trv is equal to 31.
+        // If (os_trv + 1) is used as the delta value between two ticks, 1000 ticks will be
+        // generated in 32000 clock cycle instead of 32768 clock cycles.
+        // As a result, if a user schedule an OS timer to start in 100s, the timer will start
+        // instead after 97.656s
+        // The code below fix this issue, a clock rate of 1000s will generate 1000 ticks in 32768
+        // clock cycles.
+        // The strategy is simple, for 1000 ticks:
+        //   * 768 ticks will occur 33 clock cycles after the previous tick
+        //   * 232 ticks will occur 32 clock cycles after the previous tick
+        // By default every delta is equal to 33.
+        // Every five ticks (20%, 200 delta in one second), the delta is equal to 32
+        // The remaining (32) deltas equal to 32 are distributed using primes numbers.
+        static uint32_t counter = 0;
+        if ((counter % 5) == 0 || (counter % 31) == 0 || (counter % 139) == 0 || (counter == 503)) {
+            delta = 32;
+        } else {
+            delta = 33;
+        }
+        ++counter;
+        if (counter == 1000) {
+            counter = 0;
+        }
+    }
+    return delta;
+}
+
+static inline void clear_tick_interrupt() {
+    nrf_rtc_event_clear(COMMON_RTC_INSTANCE, OS_TICK_EVENT);
+    nrf_rtc_event_disable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
+}
+
+/**
+ * Indicate if a value is included in a range which can be wrapped.
+ * @param  begin start of the range
+ * @param  end   end of the range
+ * @param  val   value to check
+ * @return       true if the value is included in the range and false otherwise.
+ */
+static inline bool is_in_wrapped_range(uint32_t begin, uint32_t end, uint32_t val) {
+    // regular case, begin < end
+    // return true if  begin <= val < end
+    if (begin < end) {
+        if (begin <= val && val < end) {
+            return true;
+        } else {
+            return false;
+        }
+    } else {
+        // In this case end < begin because it has wrap around the limits
+        // return false if end < val < begin
+        if (end < val && val < begin)  {
+            return false;
+        } else {
+            return true;
+        }
+    }
+
+}
+
+/**
+ * Register the next tick.
+ */
+static void register_next_tick() {
+    previous_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
+    uint32_t delta = get_next_tick_cc_delta();
+    uint32_t new_compare_value = (previous_tick_cc_value + delta) & MAX_RTC_COUNTER_VAL;
+
+    // Disable irq directly for few cycles,
+    // Validation of the new CC value against the COUNTER,
+    // Setting the new CC value and enabling CC IRQ should be an atomic operation
+    // Otherwise, there is a possibility to set an invalid CC value because
+    // the RTC1 keeps running.
+    // This code is very short 20-38 cycles in the worst case, it shouldn't
+    // disturb softdevice.
+    __disable_irq();
+    uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+
+    // If an overflow occur, set the next tick in COUNTER + delta clock cycles
+    if (is_in_wrapped_range(previous_tick_cc_value, new_compare_value, current_counter) == false) {
+        new_compare_value = current_counter + delta;
+    }
+    nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, new_compare_value);
+    // Enable generation of the compare event for the value set above (this
+    // event will trigger the interrupt).
+    nrf_rtc_event_enable(COMMON_RTC_INSTANCE, OS_TICK_INT_MASK);
+    __enable_irq();
+}
+
+/**
+ * Initialize alternative hardware timer as RTX kernel timer
+ * This function is directly called by RTX.
+ * @note this function shouldn't be called directly.
+ * @return  IRQ number of the alternative hardware timer
+ */
+int os_tick_init (void)
+{
+    common_rtc_init();
+
+    nrf_rtc_cc_set(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL, 0);
+    register_next_tick();
+
+    return nrf_drv_get_IRQn(COMMON_RTC_INSTANCE);
+}
+
+/**
+ * Acknowledge the tick interrupt.
+ * This function is called by the function OS_Tick_Handler of RTX.
+ * @note this function shouldn't be called directly.
+ */
+void os_tick_irqack(void)
+{
+    clear_tick_interrupt();
+    register_next_tick();
+}
+
+/**
+ * Returns the overflow flag of the alternative hardware timer.
+ * @note This function is exposed by RTX kernel.
+ * @return 1 if the timer has overflowed and 0 otherwise.
+ */
+uint32_t os_tick_ovf(void) {
+    uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+    uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
+
+    return is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter) ? 0 : 1;
+}
+
+/**
+ * Return the value of the alternative hardware timer.
+ * @note The documentation is not very clear about what is expected as a result,
+ * is it an ascending counter, a descending one ?
+ * None of this is specified.
+ * The default systick is a descending counter and this function return values in
+ * descending order, even if the internal counter used is an ascending one.
+ * @return the value of the alternative hardware timer.
+ */
+uint32_t os_tick_val(void) {
+    uint32_t current_counter = nrf_rtc_counter_get(COMMON_RTC_INSTANCE);
+    uint32_t next_tick_cc_value = nrf_rtc_cc_get(COMMON_RTC_INSTANCE, OS_TICK_CC_CHANNEL);
+
+    // do not use os_tick_ovf because its counter value can be different
+    if(is_in_wrapped_range(previous_tick_cc_value, next_tick_cc_value, current_counter)) {
+        if (next_tick_cc_value > previous_tick_cc_value) {
+            return next_tick_cc_value - current_counter;
+        } else if(current_counter <= next_tick_cc_value) {
+            return next_tick_cc_value - current_counter;
+        } else {
+            return next_tick_cc_value + (MAX_RTC_COUNTER_VAL - current_counter);
+        }
+    } else {
+        // use (os_trv + 1) has the base step, can be totally inacurate ...
+        uint32_t clock_cycles_by_tick = os_trv + 1;
+
+        // if current counter has wrap arround, add the limit to it.
+        if (current_counter < next_tick_cc_value) {
+            current_counter = current_counter + MAX_RTC_COUNTER_VAL;
+        }
+
+        return clock_cycles_by_tick - ((current_counter - next_tick_cc_value) % clock_cycles_by_tick);
+    }
+
+}
+
+#endif // defined(TARGET_MCU_NRF51822)
diff --git a/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h b/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
index 4be67e76fe..6e0742088c 100755
--- a/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
+++ b/rtos/rtx/TARGET_CORTEX_M/RTX_CM_lib.h
@@ -526,6 +526,9 @@ extern uint32_t __StackTop[];
 #elif defined(TARGET_MCU_NORDIC_16K)
 #define INITIAL_SP            (0x20004000UL)
 
+#elif defined(TARGET_MCU_NRF52832)
+#define INITIAL_SP            (0x20010000UL)
+
 #elif (defined(TARGET_STM32F767ZI))
 #define INITIAL_SP            (0x20080000UL)
 
diff --git a/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c b/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
index f95fc19474..d5a66f7772 100755
--- a/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
+++ b/rtos/rtx/TARGET_CORTEX_M/RTX_Conf_CM.c
@@ -59,7 +59,7 @@
    || defined(TARGET_STM32F103RB) || defined(TARGET_LPC824) || defined(TARGET_STM32F302R8) || defined(TARGET_STM32F334R8) || defined(TARGET_STM32F334C8) \
    || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) || defined(TARGET_STM32F072RB) || defined(TARGET_STM32F091RC) || defined(TARGET_NZ32_SC151) \
    || defined(TARGET_SSCI824)  || defined(TARGET_STM32F030R8) || defined(TARGET_STM32F070RB) \
-   || defined(TARGET_EFM32HG_STK3400) || defined(TARGET_MCU_NRF51822) || defined(TARGET_BEETLE)
+   || defined(TARGET_EFM32HG_STK3400) || defined(TARGET_MCU_NRF51822) || defined(TARGET_BEETLE) || defined(TARGET_MCU_NRF52832)
 #    define OS_TASKCNT         6
 #  else
 #    error "no target defined"
@@ -99,7 +99,7 @@
    || defined(TARGET_STM32L031K6) || defined(TARGET_STM32L053R8) || defined(TARGET_STM32L053C8) || defined(TARGET_STM32L073RZ) \
    || defined(TARGET_EFM32HG_STK3400) || defined(TARGET_BEETLE)
 #      define OS_MAINSTKSIZE    112
-#  elif defined(TARGET_MCU_NRF51822)
+#  elif defined(TARGET_MCU_NRF51822) ||  defined(TARGET_MCU_NRF52832)
 #      define OS_MAINSTKSIZE    512
 #  else
 #    error "no target defined"
@@ -262,6 +262,9 @@
 #elif defined(TARGET_MCU_NRF51822)
 #    define OS_CLOCK        32768
 
+#elif defined(TARGET_MCU_NRF52832)
+#    define OS_CLOCK        64000000
+
 #  else
 #    error "no target defined"
 #  endif