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Implement SystemCoreClockUpdate () function

pull/1848/head
tomoyuki yamanaka 2016-06-10 16:16:06 +09:00
parent 0a9e5fa3d6
commit 8f3e72f01c
1 changed files with 22 additions and 1 deletions
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21
hal/targets/cmsis/TARGET_RENESAS/TARGET_VK_RZ_A1H/system_VKRZA1H.c
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@ -49,6 +49,12 @@ void FPUEnable(void);
#endif
#define FRQCR_IFC_MSK (0x0030)
#define FRQCR_IFC_SHFT (8)
#define FRQCR_IFC_1P1 (0) /* x1/1 */
#define FRQCR_IFC_2P3 (1) /* x2/3 */
#define FRQCR_IFC_1P3 (3) /* x1/3 */
uint32_t IRQNestLevel;
unsigned char seen_id0_active = 0; // single byte to hold a flag used in the workaround for GIC errata 733075
uint32_t SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK; /*!< System Clock Frequency (Core Clock) */
@ -209,7 +215,22 @@ uint32_t InterruptHandlerUnregister (IRQn_Type irq)
*/
void SystemCoreClockUpdate (void)
{
uint32_t frqcr_ifc = ((uint32_t)CPG.FRQCR & (uint32_t)FRQCR_IFC_MSK) >> FRQCR_IFC_SHFT;
switch (frqcr_ifc) {
case FRQCR_IFC_1P1:
SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK;
break;
case FRQCR_IFC_2P3:
SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK * 2 / 3;
break;
case FRQCR_IFC_1P3:
SystemCoreClock = CM0_RENESAS_RZ_A1_I_CLK / 3;
break;
default:
/* do nothing */
break;
}
}