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[STM32L0] Change back AHBPresc table name

pull/1072/head
bcostm 2015-04-28 17:12:52 +02:00
parent 6fa2506672
commit 8e9e89f5d7
3 changed files with 6 additions and 6 deletions
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4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c
View File

@ -146,7 +146,7 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable_2[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/**
@ -303,7 +303,7 @@ void SystemCoreClockUpdate (void)
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable_2[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c
View File

@ -146,7 +146,7 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable_2[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/**
@ -303,7 +303,7 @@ void SystemCoreClockUpdate (void)
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable_2[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}

4
libraries/mbed/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c
View File

@ -146,7 +146,7 @@
variable is updated automatically.
*/
uint32_t SystemCoreClock = 32000000;
const uint8_t AHBPrescTable_2[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
/**
@ -303,7 +303,7 @@ void SystemCoreClockUpdate (void)
}
/* Compute HCLK clock frequency --------------------------------------------*/
/* Get HCLK prescaler */
tmp = AHBPrescTable_2[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
/* HCLK clock frequency */
SystemCoreClock >>= tmp;
}