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Merge pull request #12404 from OpenNuvoton/nuvoton_m2351_bsp 

M2351: Update BSP and bugfix
pull/12411/head
Martin Kojtal 2020-02-11 15:43:10 +00:00 committed by GitHub
parent bb86c0e4d0 3d9c7b2519
commit 8e522056a0
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
129 changed files with 46505 additions and 47388 deletions
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146
targets/TARGET_NUVOTON/TARGET_M2351/PeripheralNames.h
View File

@ -38,7 +38,7 @@ extern "C" {
#if 0 #if 0
typedef enum { typedef enum {
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 0)) #if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 0))
GPIO_A = (int) NU_MODNAME(GPIOA_BASE + NS_OFFSET, 0, 0), GPIO_A = (int) NU_MODNAME(GPIOA_BASE + NS_OFFSET, 0, 0),
#else #else
@ -76,143 +76,152 @@ typedef enum {
#endif #endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 6)) #if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 6))
GPIO_G = (int) NU_MODNAME(GPIOF_BASE + NS_OFFSET, 6, 0) GPIO_G = (int) NU_MODNAME(GPIOG_BASE + NS_OFFSET, 6, 0),
#else #else
GPIO_G = (int) NU_MODNAME(GPIOF_BASE, 6, 0) GPIO_G = (int) NU_MODNAME(GPIOG_BASE, 6, 0),
#endif
#if defined(SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & (1 << 7))
GPIO_H = (int) NU_MODNAME(GPIOH_BASE + NS_OFFSET, 7, 0),
#else
GPIO_H = (int) NU_MODNAME(GPIOH_BASE, 7, 0),
#endif #endif
} GPIOName; } GPIOName;
#endif #endif
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 3)) #if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 3))
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 0), ADC_0_0 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 1), ADC_0_1 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 2), ADC_0_2 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 3), ADC_0_3 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 4), ADC_0_4 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 5), ADC_0_5 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 6), ADC_0_6 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 7), ADC_0_7 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 8), ADC_0_8 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 9), ADC_0_9 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 10), ADC_0_10 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 11), ADC_0_11 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 12), ADC_0_12 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 13), ADC_0_13 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 14), ADC_0_14 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE + NS_OFFSET, 0, 15) ADC_0_15 = (int) NU_MODNAME(EADC_BASE + NS_OFFSET, 0, 15),
#else #else
ADC_0_0 = (int) NU_MODNAME(EADC0_BASE, 0, 0), ADC_0_0 = (int) NU_MODNAME(EADC_BASE, 0, 0),
ADC_0_1 = (int) NU_MODNAME(EADC0_BASE, 0, 1), ADC_0_1 = (int) NU_MODNAME(EADC_BASE, 0, 1),
ADC_0_2 = (int) NU_MODNAME(EADC0_BASE, 0, 2), ADC_0_2 = (int) NU_MODNAME(EADC_BASE, 0, 2),
ADC_0_3 = (int) NU_MODNAME(EADC0_BASE, 0, 3), ADC_0_3 = (int) NU_MODNAME(EADC_BASE, 0, 3),
ADC_0_4 = (int) NU_MODNAME(EADC0_BASE, 0, 4), ADC_0_4 = (int) NU_MODNAME(EADC_BASE, 0, 4),
ADC_0_5 = (int) NU_MODNAME(EADC0_BASE, 0, 5), ADC_0_5 = (int) NU_MODNAME(EADC_BASE, 0, 5),
ADC_0_6 = (int) NU_MODNAME(EADC0_BASE, 0, 6), ADC_0_6 = (int) NU_MODNAME(EADC_BASE, 0, 6),
ADC_0_7 = (int) NU_MODNAME(EADC0_BASE, 0, 7), ADC_0_7 = (int) NU_MODNAME(EADC_BASE, 0, 7),
ADC_0_8 = (int) NU_MODNAME(EADC0_BASE, 0, 8), ADC_0_8 = (int) NU_MODNAME(EADC_BASE, 0, 8),
ADC_0_9 = (int) NU_MODNAME(EADC0_BASE, 0, 9), ADC_0_9 = (int) NU_MODNAME(EADC_BASE, 0, 9),
ADC_0_10 = (int) NU_MODNAME(EADC0_BASE, 0, 10), ADC_0_10 = (int) NU_MODNAME(EADC_BASE, 0, 10),
ADC_0_11 = (int) NU_MODNAME(EADC0_BASE, 0, 11), ADC_0_11 = (int) NU_MODNAME(EADC_BASE, 0, 11),
ADC_0_12 = (int) NU_MODNAME(EADC0_BASE, 0, 12), ADC_0_12 = (int) NU_MODNAME(EADC_BASE, 0, 12),
ADC_0_13 = (int) NU_MODNAME(EADC0_BASE, 0, 13), ADC_0_13 = (int) NU_MODNAME(EADC_BASE, 0, 13),
ADC_0_14 = (int) NU_MODNAME(EADC0_BASE, 0, 14), ADC_0_14 = (int) NU_MODNAME(EADC_BASE, 0, 14),
ADC_0_15 = (int) NU_MODNAME(EADC0_BASE, 0, 15) ADC_0_15 = (int) NU_MODNAME(EADC_BASE, 0, 15),
#endif #endif
} ADCName; } ADCName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 7)) #if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 7))
DAC_0_0 = (int) NU_MODNAME(DAC0_BASE + NS_OFFSET, 0, 0), DAC_0_0 = (int) NU_MODNAME(DAC0_BASE + NS_OFFSET, 0, 0),
DAC_1_0 = (int) NU_MODNAME(DAC1_BASE + NS_OFFSET, 1, 0) DAC_1_0 = (int) NU_MODNAME(DAC1_BASE + NS_OFFSET, 1, 0),
#else #else
DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0), DAC_0_0 = (int) NU_MODNAME(DAC0_BASE, 0, 0),
DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0) DAC_1_0 = (int) NU_MODNAME(DAC1_BASE, 1, 0),
#endif #endif
} DACName; } DACName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<16)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 16))
UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0), UART_0 = (int) NU_MODNAME(UART0_BASE + NS_OFFSET, 0, 0),
#else #else
UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0), UART_0 = (int) NU_MODNAME(UART0_BASE, 0, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<17)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 17))
UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0), UART_1 = (int) NU_MODNAME(UART1_BASE + NS_OFFSET, 1, 0),
#else #else
UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0), UART_1 = (int) NU_MODNAME(UART1_BASE, 1, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1<<18)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 18))
UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0), UART_2 = (int) NU_MODNAME(UART2_BASE + NS_OFFSET, 2, 0),
#else #else
UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0), UART_2 = (int) NU_MODNAME(UART2_BASE, 2, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<19)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 19))
UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0), UART_3 = (int) NU_MODNAME(UART3_BASE + NS_OFFSET, 3, 0),
#else #else
UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0), UART_3 = (int) NU_MODNAME(UART3_BASE, 3, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<20)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 20))
UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0), UART_4 = (int) NU_MODNAME(UART4_BASE + NS_OFFSET, 4, 0),
#else #else
UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0), UART_4 = (int) NU_MODNAME(UART4_BASE, 4, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (0x01<<21)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 21))
UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0), UART_5 = (int) NU_MODNAME(UART5_BASE + NS_OFFSET, 5, 0),
#else #else
UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0), UART_5 = (int) NU_MODNAME(UART5_BASE, 5, 0),
#endif #endif
// NOTE: board-specific // NOTE: board-specific
STDIO_UART = UART_0 STDIO_UART = UART_0,
} UARTName; } UARTName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 0)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 1))
SPI_0 = (int) NU_MODNAME(SPI0_BASE + NS_OFFSET, 0, 0), SPI_0 = (int) NU_MODNAME(SPI0_BASE + NS_OFFSET, 0, 0),
#else #else
SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0), SPI_0 = (int) NU_MODNAME(SPI0_BASE, 0, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 1)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 2))
SPI_1 = (int) NU_MODNAME(SPI1_BASE + NS_OFFSET, 1, 0), SPI_1 = (int) NU_MODNAME(SPI1_BASE + NS_OFFSET, 1, 0),
#else #else
SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0), SPI_1 = (int) NU_MODNAME(SPI1_BASE, 1, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 2)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 3))
SPI_2 = (int) NU_MODNAME(SPI2_BASE + NS_OFFSET, 2, 0), SPI_2 = (int) NU_MODNAME(SPI2_BASE + NS_OFFSET, 2, 0),
#else #else
SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0), SPI_2 = (int) NU_MODNAME(SPI2_BASE, 2, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 3)) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 4))
SPI_3 = (int) NU_MODNAME(SPI3_BASE + NS_OFFSET, 3, 0), SPI_3 = (int) NU_MODNAME(SPI3_BASE + NS_OFFSET, 3, 0),
#else #else
SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0), SPI_3 = (int) NU_MODNAME(SPI3_BASE, 3, 0),
#endif #endif
#if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 5)) /* No SPI4 H/W, degrade QSPI0 H/W to SPI_4 for standard SPI usage */
SPI_5 = (int) NU_MODNAME(SPI5_BASE + NS_OFFSET, 5, 0) #if defined(SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & (1 << 0))
SPI_4 = (int) NU_MODNAME(QSPI0_BASE + NS_OFFSET, 4, 0),
#else #else
SPI_5 = (int) NU_MODNAME(SPI5_BASE, 5, 0) SPI_4 = (int) NU_MODNAME(QSPI0_BASE, 4, 0),
#endif #endif
} SPIName; } SPIName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 0)) #if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 0))
I2C_0 = (int) NU_MODNAME(I2C0_BASE + NS_OFFSET, 0, 0), I2C_0 = (int) NU_MODNAME(I2C0_BASE + NS_OFFSET, 0, 0),
#else #else
@ -226,9 +235,9 @@ typedef enum {
#endif #endif
#if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 2)) #if defined(SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & (1 << 2))
I2C_2 = (int) NU_MODNAME(I2C2_BASE + NS_OFFSET, 2, 0) I2C_2 = (int) NU_MODNAME(I2C2_BASE + NS_OFFSET, 2, 0),
#else #else
I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0) I2C_2 = (int) NU_MODNAME(I2C2_BASE, 2, 0),
#endif #endif
} I2CName; } I2CName;
@ -274,7 +283,7 @@ typedef enum {
/* TMR0/1 are hard-wired to Secure mode */ /* TMR0/1 are hard-wired to Secure mode */
TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0), TIMER_0 = (int) NU_MODNAME(TMR01_BASE, 0, 0),
TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0), TIMER_1 = (int) NU_MODNAME(TMR01_BASE + 0x100, 1, 0),
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 17)) #if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 17))
TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0), TIMER_2 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET, 2, 0),
TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0), TIMER_3 = (int) NU_MODNAME(TMR23_BASE + NS_OFFSET + 0x100, 3, 0),
@ -286,11 +295,11 @@ typedef enum {
} TIMERName; } TIMERName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 1)) #if defined(SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & (1 << 1))
RTC_0 = (int) NU_MODNAME(RTC_BASE + NS_OFFSET, 0, 0) RTC_0 = (int) NU_MODNAME(RTC_BASE + NS_OFFSET, 0, 0),
#else #else
RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0) RTC_0 = (int) NU_MODNAME(RTC_BASE, 0, 0),
#endif #endif
} RTCName; } RTCName;
@ -301,9 +310,9 @@ typedef enum {
DMA_0 = (int) NU_MODNAME(PDMA0_BASE, 0, 0), DMA_0 = (int) NU_MODNAME(PDMA0_BASE, 0, 0),
#if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 24)) #if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 24))
DMA_1 = (int) NU_MODNAME(PDMA1_BASE + NS_OFFSET, 1, 0) DMA_1 = (int) NU_MODNAME(PDMA1_BASE + NS_OFFSET, 1, 0),
#else #else
DMA_1 = (int) NU_MODNAME(PDMA1_BASE, 1, 0) DMA_1 = (int) NU_MODNAME(PDMA1_BASE, 1, 0),
#endif #endif
} DMAName; } DMAName;
@ -311,28 +320,29 @@ typedef enum {
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 13)) #if defined(SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & (1 << 13))
SD_0 = (int) NU_MODNAME(SDH0_BASE + NS_OFFSET, 0, 0) SD_0 = (int) NU_MODNAME(SDH0_BASE + NS_OFFSET, 0, 0),
#else #else
SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0) SD_0 = (int) NU_MODNAME(SDH0_BASE, 0, 0),
#endif #endif
} SDName; } SDName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 0)) #if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 0))
CAN_0 = (int) NU_MODNAME(CAN0_BASE + NS_OFFSET, 0, 0) CAN_0 = (int) NU_MODNAME(CAN0_BASE + NS_OFFSET, 0, 0),
#else #else
CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0) CAN_0 = (int) NU_MODNAME(CAN0_BASE, 0, 0),
#endif #endif
} CANName; } CANName;
typedef enum { typedef enum {
#if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 25)) #if defined(SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & (1 << 25))
TRNG_0 = (int) NU_MODNAME(TRNG_BASE + NS_OFFSET, 0, 0) TRNG_0 = (int) NU_MODNAME(TRNG_BASE + NS_OFFSET, 0, 0),
#else #else
TRNG_0 = (int) NU_MODNAME(TRNG_BASE, 0, 0) TRNG_0 = (int) NU_MODNAME(TRNG_BASE, 0, 0),
#endif #endif
} TRNGName; } TRNGName;

90
targets/TARGET_NUVOTON/TARGET_M2351/PeripheralPins.c
View File

@ -42,7 +42,7 @@ const PinMap PinMap_GPIO[] = {
{PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO}, {PA_13, GPIO_A, SYS_GPA_MFPH_PA13MFP_GPIO},
{PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO}, {PA_14, GPIO_A, SYS_GPA_MFPH_PA14MFP_GPIO},
{PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO}, {PA_15, GPIO_A, SYS_GPA_MFPH_PA15MFP_GPIO},
// GPIO B MFP // GPIO B MFP
{PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO}, {PB_0, GPIO_B, SYS_GPB_MFPL_PB0MFP_GPIO},
{PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO}, {PB_1, GPIO_B, SYS_GPB_MFPL_PB1MFP_GPIO},
@ -60,7 +60,7 @@ const PinMap PinMap_GPIO[] = {
{PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO}, {PB_13, GPIO_B, SYS_GPB_MFPH_PB13MFP_GPIO},
{PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO}, {PB_14, GPIO_B, SYS_GPB_MFPH_PB14MFP_GPIO},
{PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO}, {PB_15, GPIO_B, SYS_GPB_MFPH_PB15MFP_GPIO},
// GPIO C MFP // GPIO C MFP
{PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO}, {PC_0, GPIO_C, SYS_GPC_MFPL_PC0MFP_GPIO},
{PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO}, {PC_1, GPIO_C, SYS_GPC_MFPL_PC1MFP_GPIO},
@ -76,7 +76,7 @@ const PinMap PinMap_GPIO[] = {
{PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO}, {PC_11, GPIO_C, SYS_GPC_MFPH_PC11MFP_GPIO},
{PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO}, {PC_12, GPIO_C, SYS_GPC_MFPH_PC12MFP_GPIO},
{PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO}, {PC_13, GPIO_C, SYS_GPC_MFPH_PC13MFP_GPIO},
// GPIO D MFP // GPIO D MFP
{PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO}, {PD_0, GPIO_D, SYS_GPD_MFPL_PD0MFP_GPIO},
{PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO}, {PD_1, GPIO_D, SYS_GPD_MFPL_PD1MFP_GPIO},
@ -93,7 +93,7 @@ const PinMap PinMap_GPIO[] = {
{PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO}, {PD_12, GPIO_D, SYS_GPD_MFPH_PD12MFP_GPIO},
{PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO}, {PD_13, GPIO_D, SYS_GPD_MFPH_PD13MFP_GPIO},
{PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO}, {PD_14, GPIO_D, SYS_GPD_MFPH_PD14MFP_GPIO},
// GPIO E MFP // GPIO E MFP
{PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO}, {PE_0, GPIO_E, SYS_GPE_MFPL_PE0MFP_GPIO},
{PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO}, {PE_1, GPIO_E, SYS_GPE_MFPL_PE1MFP_GPIO},
@ -126,7 +126,7 @@ const PinMap PinMap_GPIO[] = {
{PF_10, GPIO_F, SYS_GPF_MFPH_PF10MFP_GPIO}, {PF_10, GPIO_F, SYS_GPF_MFPH_PF10MFP_GPIO},
{PF_11, GPIO_F, SYS_GPF_MFPH_PF11MFP_GPIO}, {PF_11, GPIO_F, SYS_GPF_MFPH_PF11MFP_GPIO},
// GPIO G/H MFP // GPIO G MFP
{PG_2, GPIO_G, SYS_GPG_MFPL_PG2MFP_GPIO}, {PG_2, GPIO_G, SYS_GPG_MFPL_PG2MFP_GPIO},
{PG_3, GPIO_G, SYS_GPG_MFPL_PG3MFP_GPIO}, {PG_3, GPIO_G, SYS_GPG_MFPL_PG3MFP_GPIO},
{PG_4, GPIO_G, SYS_GPG_MFPL_PG4MFP_GPIO}, {PG_4, GPIO_G, SYS_GPG_MFPL_PG4MFP_GPIO},
@ -137,6 +137,8 @@ const PinMap PinMap_GPIO[] = {
{PG_13, GPIO_G, SYS_GPG_MFPH_PG13MFP_GPIO}, {PG_13, GPIO_G, SYS_GPG_MFPH_PG13MFP_GPIO},
{PG_14, GPIO_G, SYS_GPG_MFPH_PG14MFP_GPIO}, {PG_14, GPIO_G, SYS_GPG_MFPH_PG14MFP_GPIO},
{PG_15, GPIO_G, SYS_GPG_MFPH_PG15MFP_GPIO}, {PG_15, GPIO_G, SYS_GPG_MFPH_PG15MFP_GPIO},
// GPIO H MFP
{PH_4, GPIO_H, SYS_GPH_MFPL_PH4MFP_GPIO}, {PH_4, GPIO_H, SYS_GPH_MFPL_PH4MFP_GPIO},
{PH_5, GPIO_H, SYS_GPH_MFPL_PH5MFP_GPIO}, {PH_5, GPIO_H, SYS_GPH_MFPL_PH5MFP_GPIO},
{PH_6, GPIO_H, SYS_GPH_MFPL_PH6MFP_GPIO}, {PH_6, GPIO_H, SYS_GPH_MFPL_PH6MFP_GPIO},
@ -145,6 +147,7 @@ const PinMap PinMap_GPIO[] = {
{PH_9, GPIO_H, SYS_GPH_MFPH_PH9MFP_GPIO}, {PH_9, GPIO_H, SYS_GPH_MFPH_PH9MFP_GPIO},
{PH_10, GPIO_H, SYS_GPH_MFPH_PH10MFP_GPIO}, {PH_10, GPIO_H, SYS_GPH_MFPH_PH10MFP_GPIO},
{PH_11, GPIO_H, SYS_GPH_MFPH_PH11MFP_GPIO}, {PH_11, GPIO_H, SYS_GPH_MFPH_PH11MFP_GPIO},
{NC, NC, 0} {NC, NC, 0}
}; };
#endif #endif
@ -168,7 +171,7 @@ const PinMap PinMap_ADC[] = {
{PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13}, {PB_13, ADC_0_13, SYS_GPB_MFPH_PB13MFP_EADC0_CH13},
{PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14}, {PB_14, ADC_0_14, SYS_GPB_MFPH_PB14MFP_EADC0_CH14},
{PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15}, {PB_15, ADC_0_15, SYS_GPB_MFPH_PB15MFP_EADC0_CH15},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -208,7 +211,7 @@ const PinMap PinMap_I2C_SDA[] = {
{PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA}, {PF_2, I2C_0, SYS_GPF_MFPL_PF2MFP_I2C0_SDA},
{PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA}, {PG_3, I2C_1, SYS_GPG_MFPL_PG3MFP_I2C1_SDA},
{PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA}, {PH_9, I2C_2, SYS_GPH_MFPH_PH9MFP_I2C2_SDA},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -237,7 +240,7 @@ const PinMap PinMap_I2C_SCL[] = {
{PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL}, {PF_3, I2C_0, SYS_GPF_MFPL_PF3MFP_I2C0_SCL},
{PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL}, {PG_2, I2C_1, SYS_GPG_MFPL_PG2MFP_I2C1_SCL},
{PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL}, {PH_8, I2C_2, SYS_GPH_MFPH_PH8MFP_I2C2_SCL},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -354,7 +357,7 @@ const PinMap PinMap_UART_TX[] = {
{NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD}, {NU_PINNAME_BIND(PH_10, UART_0), UART_0, SYS_GPH_MFPH_PH10MFP_UART0_TXD},
{PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD}, {PH_10, UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
{NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD}, {NU_PINNAME_BIND(PH_10, UART_4), UART_4, SYS_GPH_MFPH_PH10MFP_UART4_TXD},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -406,7 +409,7 @@ const PinMap PinMap_UART_RX[] = {
{NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD}, {NU_PINNAME_BIND(PH_11, UART_0), UART_0, SYS_GPH_MFPH_PH11MFP_UART0_RXD},
{PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD}, {PH_11, UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
{NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD}, {NU_PINNAME_BIND(PH_11, UART_4), UART_4, SYS_GPH_MFPH_PH11MFP_UART4_RXD},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -427,7 +430,7 @@ const PinMap PinMap_UART_RTS[] = {
{PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS}, {PE_13, UART_4, SYS_GPE_MFPH_PE13MFP_UART4_nRTS},
{PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS}, {PF_4, UART_2, SYS_GPF_MFPL_PF4MFP_UART2_nRTS},
{PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS}, {PH_8, UART_3, SYS_GPH_MFPH_PH8MFP_UART3_nRTS},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -448,96 +451,105 @@ const PinMap PinMap_UART_CTS[] = {
{PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS}, {PE_11, UART_1, SYS_GPE_MFPH_PE11MFP_UART1_nCTS},
{PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS}, {PF_5, UART_2, SYS_GPF_MFPL_PF5MFP_UART2_nCTS},
{PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS}, {PH_9, UART_3, SYS_GPH_MFPH_PH9MFP_UART3_nCTS},
{NC, NC, 0} {NC, NC, 0}
}; };
//*** SPI *** //*** SPI ***
const PinMap PinMap_SPI_MOSI[] = { const PinMap PinMap_SPI_MOSI[] = {
{PA_0, SPI_4, SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0},
{NU_PINNAME_BIND(PA_0, SPI_4), SPI_4, SYS_GPA_MFPL_PA0MFP_QSPI0_MOSI0},
{PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI}, {PA_0, SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI},
{NU_PINNAME_BIND(PA_0, SPI_0), SPI_0, SYS_GPA_MFPL_PA0MFP_SPI0_MOSI},
{PA_8, SPI_2, SYS_GPA_MFPH_PA8MFP_SPI2_MOSI}, {PA_8, SPI_2, SYS_GPA_MFPH_PA8MFP_SPI2_MOSI},
{PA_15, SPI_2, SYS_GPA_MFPH_PA15MFP_SPI2_MOSI}, {PA_15, SPI_2, SYS_GPA_MFPH_PA15MFP_SPI2_MOSI},
{PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_MOSI}, {PB_4, SPI_1, SYS_GPB_MFPL_PB4MFP_SPI1_MOSI},
{PB_8, SPI_3, SYS_GPB_MFPH_PB8MFP_SPI3_MOSI}, {PB_8, SPI_3, SYS_GPB_MFPH_PB8MFP_SPI3_MOSI},
{PB_12, SPI_0, SYS_GPB_MFPH_PB12MFP_SPI0_MOSI}, {PB_12, SPI_0, SYS_GPB_MFPH_PB12MFP_SPI0_MOSI},
{PC_0, SPI_5, SYS_GPC_MFPL_PC0MFP_SPI5_MOSI}, {PC_0, SPI_4, SYS_GPC_MFPL_PC0MFP_QSPI0_MOSI0},
{PC_2, SPI_1, SYS_GPC_MFPL_PC2MFP_SPI1_MOSI}, {PC_2, SPI_1, SYS_GPC_MFPL_PC2MFP_SPI1_MOSI},
{PC_6, SPI_1, SYS_GPC_MFPL_PC6MFP_SPI1_MOSI}, {PC_6, SPI_1, SYS_GPC_MFPL_PC6MFP_SPI1_MOSI},
{PC_11, SPI_3, SYS_GPC_MFPH_PC11MFP_SPI3_MOSI}, {PC_11, SPI_3, SYS_GPC_MFPH_PC11MFP_SPI3_MOSI},
{PD_0, SPI_0, SYS_GPD_MFPL_PD0MFP_SPI0_MOSI}, {PD_0, SPI_0, SYS_GPD_MFPL_PD0MFP_SPI0_MOSI},
{PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_MOSI}, {PD_6, SPI_1, SYS_GPD_MFPL_PD6MFP_SPI1_MOSI},
{PE_0, SPI_4, SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0},
{NU_PINNAME_BIND(PE_0, SPI_4), SPI_4, SYS_GPE_MFPL_PE0MFP_QSPI0_MOSI0},
{PE_0, SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI}, {PE_0, SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI},
{NU_PINNAME_BIND(PE_0, SPI_1), SPI_1, SYS_GPE_MFPL_PE0MFP_SPI1_MOSI},
{PE_2, SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI}, {PE_2, SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI},
{NU_PINNAME_BIND(PE_2, SPI_3), SPI_3, SYS_GPE_MFPL_PE2MFP_SPI3_MOSI},
{PE_2, SPI_5, SYS_GPE_MFPL_PE2MFP_SPI5_MOSI},
{NU_PINNAME_BIND(PE_2, SPI_5), SPI_5, SYS_GPE_MFPL_PE2MFP_SPI5_MOSI},
{PE_10, SPI_2, SYS_GPE_MFPH_PE10MFP_SPI2_MOSI}, {PE_10, SPI_2, SYS_GPE_MFPH_PE10MFP_SPI2_MOSI},
{PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI}, {PF_6, SPI_0, SYS_GPF_MFPL_PF6MFP_SPI0_MOSI},
{PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MOSI}, {PF_11, SPI_2, SYS_GPF_MFPH_PF11MFP_SPI2_MOSI},
{PG_10, SPI_5, SYS_GPG_MFPH_PG10MFP_SPI5_MOSI},
{PH_5, SPI_1, SYS_GPH_MFPL_PH5MFP_SPI1_MOSI}, {PH_5, SPI_1, SYS_GPH_MFPL_PH5MFP_SPI1_MOSI},
{NC, NC, 0} {NC, NC, 0}
}; };
const PinMap PinMap_SPI_MISO[] = { const PinMap PinMap_SPI_MISO[] = {
{PA_1, SPI_4, SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0},
{NU_PINNAME_BIND(PA_1, SPI_4), SPI_4, SYS_GPA_MFPL_PA1MFP_QSPI0_MISO0},
{PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO}, {PA_1, SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO},
{NU_PINNAME_BIND(PA_1, SPI_0), SPI_0, SYS_GPA_MFPL_PA1MFP_SPI0_MISO},
{PA_9, SPI_2, SYS_GPA_MFPH_PA9MFP_SPI2_MISO}, {PA_9, SPI_2, SYS_GPA_MFPH_PA9MFP_SPI2_MISO},
{PA_14, SPI_2, SYS_GPA_MFPH_PA14MFP_SPI2_MISO}, {PA_14, SPI_2, SYS_GPA_MFPH_PA14MFP_SPI2_MISO},
{PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MISO}, {PB_5, SPI_1, SYS_GPB_MFPL_PB5MFP_SPI1_MISO},
{PB_9, SPI_3, SYS_GPB_MFPH_PB9MFP_SPI3_MISO}, {PB_9, SPI_3, SYS_GPB_MFPH_PB9MFP_SPI3_MISO},
{PB_13, SPI_0, SYS_GPB_MFPH_PB13MFP_SPI0_MISO}, {PB_13, SPI_0, SYS_GPB_MFPH_PB13MFP_SPI0_MISO},
{PC_1, SPI_5, SYS_GPC_MFPL_PC1MFP_SPI5_MISO}, {PC_1, SPI_4, SYS_GPC_MFPL_PC1MFP_QSPI0_MISO0},
{PC_3, SPI_1, SYS_GPC_MFPL_PC3MFP_SPI1_MISO}, {PC_3, SPI_1, SYS_GPC_MFPL_PC3MFP_SPI1_MISO},
{PC_7, SPI_1, SYS_GPC_MFPL_PC7MFP_SPI1_MISO}, {PC_7, SPI_1, SYS_GPC_MFPL_PC7MFP_SPI1_MISO},
{PC_12, SPI_3, SYS_GPC_MFPH_PC12MFP_SPI3_MISO}, {PC_12, SPI_3, SYS_GPC_MFPH_PC12MFP_SPI3_MISO},
{PD_1, SPI_0, SYS_GPD_MFPL_PD1MFP_SPI0_MISO}, {PD_1, SPI_0, SYS_GPD_MFPL_PD1MFP_SPI0_MISO},
{PD_7, SPI_1, SYS_GPD_MFPL_PD7MFP_SPI1_MISO}, {PD_7, SPI_1, SYS_GPD_MFPL_PD7MFP_SPI1_MISO},
{PE_1, SPI_4, SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0},
{NU_PINNAME_BIND(PE_1, SPI_4), SPI_4, SYS_GPE_MFPL_PE1MFP_QSPI0_MISO0},
{PE_1, SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO}, {PE_1, SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO},
{NU_PINNAME_BIND(PE_1, SPI_1), SPI_1, SYS_GPE_MFPL_PE1MFP_SPI1_MISO},
{PE_3, SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO}, {PE_3, SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO},
{NU_PINNAME_BIND(PE_3, SPI_3), SPI_3, SYS_GPE_MFPL_PE3MFP_SPI3_MISO},
{PE_3, SPI_5, SYS_GPE_MFPL_PE3MFP_SPI5_MISO},
{NU_PINNAME_BIND(PE_3, SPI_5), SPI_5, SYS_GPE_MFPL_PE3MFP_SPI5_MISO},
{PE_9, SPI_2, SYS_GPE_MFPH_PE9MFP_SPI2_MISO}, {PE_9, SPI_2, SYS_GPE_MFPH_PE9MFP_SPI2_MISO},
{PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO}, {PF_7, SPI_0, SYS_GPF_MFPL_PF7MFP_SPI0_MISO},
{PG_4, SPI_2, SYS_GPG_MFPL_PG4MFP_SPI2_MISO}, {PG_4, SPI_2, SYS_GPG_MFPL_PG4MFP_SPI2_MISO},
{PG_9, SPI_5, SYS_GPG_MFPH_PG9MFP_SPI5_MISO},
{PH_4, SPI_1, SYS_GPH_MFPL_PH4MFP_SPI1_MISO}, {PH_4, SPI_1, SYS_GPH_MFPL_PH4MFP_SPI1_MISO},
{NC, NC, 0} {NC, NC, 0}
}; };
const PinMap PinMap_SPI_SCLK[] = { const PinMap PinMap_SPI_SCLK[] = {
{PA_2, SPI_4, SYS_GPA_MFPL_PA2MFP_QSPI0_CLK},
{NU_PINNAME_BIND(PA_2, SPI_4), SPI_4, SYS_GPA_MFPL_PA2MFP_QSPI0_CLK},
{PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK}, {PA_2, SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
{NU_PINNAME_BIND(PA_2, SPI_0), SPI_0, SYS_GPA_MFPL_PA2MFP_SPI0_CLK},
{PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK}, {PA_7, SPI_1, SYS_GPA_MFPL_PA7MFP_SPI1_CLK},
{PA_10, SPI_2, SYS_GPA_MFPH_PA10MFP_SPI2_CLK}, {PA_10, SPI_2, SYS_GPA_MFPH_PA10MFP_SPI2_CLK},
{PA_13, SPI_2, SYS_GPA_MFPH_PA13MFP_SPI2_CLK}, {PA_13, SPI_2, SYS_GPA_MFPH_PA13MFP_SPI2_CLK},
{PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_CLK}, {PB_3, SPI_1, SYS_GPB_MFPL_PB3MFP_SPI1_CLK},
{PB_11, SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK}, {PB_11, SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK},
{NU_PINNAME_BIND(PB_11, SPI_3), SPI_3, SYS_GPB_MFPH_PB11MFP_SPI3_CLK},
{PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK}, {PB_14, SPI_0, SYS_GPB_MFPH_PB14MFP_SPI0_CLK},
{PC_1, SPI_1, SYS_GPC_MFPL_PC1MFP_SPI1_CLK}, {PC_1, SPI_1, SYS_GPC_MFPL_PC1MFP_SPI1_CLK},
{PC_2, SPI_5, SYS_GPC_MFPL_PC2MFP_SPI5_CLK}, {PC_2, SPI_4, SYS_GPC_MFPL_PC2MFP_QSPI0_CLK},
{PC_10, SPI_3, SYS_GPC_MFPH_PC10MFP_SPI3_CLK}, {PC_10, SPI_3, SYS_GPC_MFPH_PC10MFP_SPI3_CLK},
{PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK}, {PD_2, SPI_0, SYS_GPD_MFPL_PD2MFP_SPI0_CLK},
{PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_CLK}, {PD_5, SPI_1, SYS_GPD_MFPL_PD5MFP_SPI1_CLK},
{PE_4, SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK}, {PE_4, SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK},
{NU_PINNAME_BIND(PE_4, SPI_3), SPI_3, SYS_GPE_MFPL_PE4MFP_SPI3_CLK},
{PE_4, SPI_5, SYS_GPE_MFPL_PE4MFP_SPI5_CLK},
{NU_PINNAME_BIND(PE_4, SPI_5), SPI_5, SYS_GPE_MFPL_PE4MFP_SPI5_CLK},
{PE_8, SPI_2, SYS_GPE_MFPH_PE8MFP_SPI2_CLK}, {PE_8, SPI_2, SYS_GPE_MFPH_PE8MFP_SPI2_CLK},
{PF_2, SPI_4, SYS_GPF_MFPL_PF2MFP_QSPI0_CLK},
{PF_8, SPI_0, SYS_GPF_MFPH_PF8MFP_SPI0_CLK}, {PF_8, SPI_0, SYS_GPF_MFPH_PF8MFP_SPI0_CLK},
{PG_3, SPI_2, SYS_GPG_MFPL_PG3MFP_SPI2_CLK}, {PG_3, SPI_2, SYS_GPG_MFPL_PG3MFP_SPI2_CLK},
{PG_11, SPI_5, SYS_GPG_MFPH_PG11MFP_SPI5_CLK},
{PH_6, SPI_1, SYS_GPH_MFPL_PH6MFP_SPI1_CLK}, {PH_6, SPI_1, SYS_GPH_MFPL_PH6MFP_SPI1_CLK},
{PH_8, SPI_4, SYS_GPH_MFPH_PH8MFP_QSPI0_CLK},
{NU_PINNAME_BIND(PH_8, SPI_4), SPI_4, SYS_GPH_MFPH_PH8MFP_QSPI0_CLK},
{PH_8, SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK}, {PH_8, SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK},
{NU_PINNAME_BIND(PH_8, SPI_1), SPI_1, SYS_GPH_MFPH_PH8MFP_SPI1_CLK},
{NC, NC, 0} {NC, NC, 0}
}; };
const PinMap PinMap_SPI_SSEL[] = { const PinMap PinMap_SPI_SSEL[] = {
{PA_3, SPI_4, SYS_GPA_MFPL_PA3MFP_QSPI0_SS},
{NU_PINNAME_BIND(PA_3, SPI_4), SPI_4, SYS_GPA_MFPL_PA3MFP_QSPI0_SS},
{PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS}, {PA_3, SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
{NU_PINNAME_BIND(PA_3, SPI_0), SPI_0, SYS_GPA_MFPL_PA3MFP_SPI0_SS},
{PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_SS}, {PA_6, SPI_1, SYS_GPA_MFPL_PA6MFP_SPI1_SS},
{PA_11, SPI_2, SYS_GPA_MFPH_PA11MFP_SPI2_SS}, {PA_11, SPI_2, SYS_GPA_MFPH_PA11MFP_SPI2_SS},
{PA_12, SPI_2, SYS_GPA_MFPH_PA12MFP_SPI2_SS}, {PA_12, SPI_2, SYS_GPA_MFPH_PA12MFP_SPI2_SS},
@ -545,21 +557,20 @@ const PinMap PinMap_SPI_SSEL[] = {
{PB_10, SPI_3, SYS_GPB_MFPH_PB10MFP_SPI3_SS}, {PB_10, SPI_3, SYS_GPB_MFPH_PB10MFP_SPI3_SS},
{PB_15, SPI_0, SYS_GPB_MFPH_PB15MFP_SPI0_SS}, {PB_15, SPI_0, SYS_GPB_MFPH_PB15MFP_SPI0_SS},
{PC_0, SPI_1, SYS_GPC_MFPL_PC0MFP_SPI1_SS}, {PC_0, SPI_1, SYS_GPC_MFPL_PC0MFP_SPI1_SS},
{PC_3, SPI_5, SYS_GPC_MFPL_PC3MFP_SPI5_SS}, {PC_3, SPI_4, SYS_GPC_MFPL_PC3MFP_QSPI0_SS},
{PC_9, SPI_3, SYS_GPC_MFPH_PC9MFP_SPI3_SS}, {PC_9, SPI_3, SYS_GPC_MFPH_PC9MFP_SPI3_SS},
{PD_3, SPI_0, SYS_GPD_MFPL_PD3MFP_SPI0_SS}, {PD_3, SPI_0, SYS_GPD_MFPL_PD3MFP_SPI0_SS},
{PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_SS}, {PD_4, SPI_1, SYS_GPD_MFPL_PD4MFP_SPI1_SS},
{PE_5, SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS}, {PE_5, SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS},
{NU_PINNAME_BIND(PE_5, SPI_3), SPI_3, SYS_GPE_MFPL_PE5MFP_SPI3_SS},
{PE_5, SPI_5, SYS_GPE_MFPL_PE5MFP_SPI5_SS},
{NU_PINNAME_BIND(PE_5, SPI_5), SPI_5, SYS_GPE_MFPL_PE5MFP_SPI5_SS},
{PE_11, SPI_2, SYS_GPE_MFPH_PE11MFP_SPI2_SS}, {PE_11, SPI_2, SYS_GPE_MFPH_PE11MFP_SPI2_SS},
{PF_9, SPI_0, SYS_GPF_MFPH_PF9MFP_SPI0_SS}, {PF_9, SPI_0, SYS_GPF_MFPH_PF9MFP_SPI0_SS},
{PG_2, SPI_2, SYS_GPG_MFPL_PG2MFP_SPI2_SS}, {PG_2, SPI_2, SYS_GPG_MFPL_PG2MFP_SPI2_SS},
{PG_12, SPI_5, SYS_GPG_MFPH_PG12MFP_SPI5_SS},
{PH_7, SPI_1, SYS_GPH_MFPL_PH7MFP_SPI1_SS}, {PH_7, SPI_1, SYS_GPH_MFPL_PH7MFP_SPI1_SS},
{PH_9, SPI_4, SYS_GPH_MFPH_PH9MFP_QSPI0_SS},
{NU_PINNAME_BIND(PH_9, SPI_4), SPI_4, SYS_GPH_MFPH_PH9MFP_QSPI0_SS},
{PH_9, SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS}, {PH_9, SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS},
{NU_PINNAME_BIND(PH_9, SPI_1), SPI_1, SYS_GPH_MFPH_PH9MFP_SPI1_SS},
{NC, NC, 0} {NC, NC, 0}
}; };
@ -621,10 +632,10 @@ const PinMap PinMap_CAN_TD[] = {
{PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD}, {PC_5, CAN_0, SYS_GPC_MFPL_PC5MFP_CAN0_TXD},
{PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD}, {PD_11, CAN_0, SYS_GPD_MFPH_PD11MFP_CAN0_TXD},
{PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD}, {PE_14, CAN_0, SYS_GPE_MFPH_PE14MFP_CAN0_TXD},
{NC, NC, 0} {NC, NC, 0}
}; };
const PinMap PinMap_CAN_RD[] = { const PinMap PinMap_CAN_RD[] = {
{PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD}, {PA_4, CAN_0, SYS_GPA_MFPL_PA4MFP_CAN0_RXD},
{PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD}, {PA_13, CAN_0, SYS_GPA_MFPH_PA13MFP_CAN0_RXD},
@ -635,3 +646,4 @@ const PinMap PinMap_CAN_RD[] = {
{NC, NC, 0} {NC, NC, 0}
}; };

4
targets/TARGET_NUVOTON/TARGET_M2351/PinNames.h
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@ -66,7 +66,7 @@ __STATIC_INLINE uint32_t NU_GET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN)
} }
#endif #endif
return GPIO_PIN_DATA(PORT, PIN); return GPIO_PIN_DATA_S(PORT, PIN);
} }
/* TrustZone-aware version of GPIO_PIN_DATA to set GPIO pin data */ /* TrustZone-aware version of GPIO_PIN_DATA to set GPIO pin data */
@ -79,7 +79,7 @@ __STATIC_INLINE void NU_SET_GPIO_PIN_DATA(uint32_t PORT, uint32_t PIN, uint32_t
} }
#endif #endif
GPIO_PIN_DATA(PORT, PIN) = VALUE; GPIO_PIN_DATA_S(PORT, PIN) = VALUE;
} }
// LEGACY // LEGACY

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targets/TARGET_NUVOTON/TARGET_M2351/TARGET_M23_NS/TARGET_NU_PFM_M2351_NPSA_NS/TARGET_NU_PREBUILD_SECURE/NuMaker-mbed-TZ-secure-example.hex
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targets/TARGET_NUVOTON/TARGET_M2351/device/M2351.h
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@ -1,6 +1,6 @@
/**************************************************************************//** /**************************************************************************//**
* @file M2351.h * @file M2351.h
* @version V1.0 * @version V1.1
* @brief Peripheral Access Layer Header File * @brief Peripheral Access Layer Header File
* *
* @note * @note
@ -24,13 +24,89 @@
* *
* <b>Copyright Notice</b> * <b>Copyright Notice</b>
* *
* Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2019 Nuvoton Technology Corp. All rights reserved.
*/ */
#ifndef __M2351_H__ #ifndef __M2351_H__
#define __M2351_H__ #define __M2351_H__
/*=============================================================================*/
typedef volatile unsigned char vu8;
typedef volatile unsigned int vu32;
typedef volatile unsigned short vu16;
#define M8(adr) (*((vu8 *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))
#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
#define inpw(port) ((*((volatile unsigned int *)(port))))
#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
#define inpb(port) ((*((volatile unsigned char *)(port))))
#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
#define inps(port) ((*((volatile unsigned short *)(port))))
#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
#define inp32(port) ((*((volatile unsigned int *)(port))))
#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
#define inp8(port) ((*((volatile unsigned char *)(port))))
#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
#define inp16(port) ((*((volatile unsigned short *)(port))))
#define E_SUCCESS 0
#define TRUE (1L)
#define FALSE (0L)
#define ENABLE 1
#define DISABLE 0
/* Bit Mask Definitions */
#define BIT0 0x00000001UL
#define BIT1 0x00000002UL
#define BIT2 0x00000004UL
#define BIT3 0x00000008UL
#define BIT4 0x00000010UL
#define BIT5 0x00000020UL
#define BIT6 0x00000040UL
#define BIT7 0x00000080UL
#define BIT8 0x00000100UL
#define BIT9 0x00000200UL
#define BIT10 0x00000400UL
#define BIT11 0x00000800UL
#define BIT12 0x00001000UL
#define BIT13 0x00002000UL
#define BIT14 0x00004000UL
#define BIT15 0x00008000UL
#define BIT16 0x00010000UL
#define BIT17 0x00020000UL
#define BIT18 0x00040000UL
#define BIT19 0x00080000UL
#define BIT20 0x00100000UL
#define BIT21 0x00200000UL
#define BIT22 0x00400000UL
#define BIT23 0x00800000UL
#define BIT24 0x01000000UL
#define BIT25 0x02000000UL
#define BIT26 0x04000000UL
#define BIT27 0x08000000UL
#define BIT28 0x10000000UL
#define BIT29 0x20000000UL
#define BIT30 0x40000000UL
#define BIT31 0x80000000UL
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL)
#define BYTE1_Msk (0x0000FF00UL)
#define BYTE2_Msk (0x00FF0000UL)
#define BYTE3_Msk (0xFF000000UL)
#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -142,8 +218,6 @@ typedef enum IRQn
ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */ ECAP1_IRQn = 87, /*!< ECAP1 Interrupt */
GPH_IRQn = 88, /*!< GPIO Port H Interrupt */ GPH_IRQn = 88, /*!< GPIO Port H Interrupt */
EINT7_IRQn = 89, /*!< External Input 7 Interrupt */ EINT7_IRQn = 89, /*!< External Input 7 Interrupt */
SPI5_IRQn = 96, /*!< SPI5 Interrupt */
DSRC_IRQn = 97, /*!< DSRC Interrupt */
PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */ PDMA1_IRQn = 98, /*!< Peripheral DMA 1 Interrupt */
SCU_IRQn = 99, /*!< SCU Interrupt */ SCU_IRQn = 99, /*!< SCU Interrupt */
TRNG_IRQn = 101 /*!< TRNG interrupt */ TRNG_IRQn = 101 /*!< TRNG interrupt */
@ -187,6 +261,7 @@ typedef enum IRQn
#include "core_cm23.h" /* Processor and core peripherals */ #include "core_cm23.h" /* Processor and core peripherals */
#include "system_M2351.h" /* System Header */ #include "system_M2351.h" /* System Header */
#include "partition_M2351.h"
/** /**
* Initialize the system clock * Initialize the system clock
@ -204,11 +279,6 @@ extern void SystemInit(void);
/* Device Specific Peripheral registers structures */ /* Device Specific Peripheral registers structures */
/******************************************************************************/ /******************************************************************************/
/** @addtogroup REGISTER Control Register
@{
*/
#include "acmp_reg.h" #include "acmp_reg.h"
#include "bpwm_reg.h" #include "bpwm_reg.h"
@ -233,7 +303,6 @@ extern void SystemInit(void);
#include "sdh_reg.h" #include "sdh_reg.h"
#include "qspi_reg.h" #include "qspi_reg.h"
#include "spi_reg.h" #include "spi_reg.h"
#include "spi5_reg.h"
#include "sys_reg.h" #include "sys_reg.h"
#include "timer_reg.h" #include "timer_reg.h"
#include "trng_reg.h" #include "trng_reg.h"
@ -248,8 +317,6 @@ extern void SystemInit(void);
#include "wdt_reg.h" #include "wdt_reg.h"
#include "wwdt_reg.h" #include "wwdt_reg.h"
/**@}*/ /* end of REGISTER group */
/******************************************************************************/ /******************************************************************************/
/* Peripheral memory map */ /* Peripheral memory map */
@ -284,7 +351,6 @@ extern void SystemInit(void);
#define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL) #define GPIOH_BASE (AHBPERIPH_BASE + 0x041C0UL)
#define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL) #define GPIO_DBCTL_BASE (AHBPERIPH_BASE + 0x04440UL)
#define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL) #define GPIO_PIN_DATA_BASE (AHBPERIPH_BASE + 0x04800UL)
#define PDMA_BASE (AHBPERIPH_BASE + 0x08000UL)
#define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL) #define PDMA0_BASE (AHBPERIPH_BASE + 0x08000UL)
#define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL) #define PDMA1_BASE (AHBPERIPH_BASE + 0x18000UL)
#define USBH_BASE (AHBPERIPH_BASE + 0x09000UL) #define USBH_BASE (AHBPERIPH_BASE + 0x09000UL)
@ -292,16 +358,15 @@ extern void SystemInit(void);
#define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL) #define SDH0_BASE (AHBPERIPH_BASE + 0x0D000UL)
#define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL) #define SDH1_BASE (AHBPERIPH_BASE + 0x0E000UL)
#define EBI_BASE (AHBPERIPH_BASE + 0x10000UL) #define EBI_BASE (AHBPERIPH_BASE + 0x10000UL)
#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL)
#define CRC_BASE (AHBPERIPH_BASE + 0x31000UL) #define CRC_BASE (AHBPERIPH_BASE + 0x31000UL)
#define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL) #define CRPT_BASE (AHBPERIPH_BASE + 0x32000UL)
#define SCU_BASE (AHBPERIPH_BASE + 0x2F000UL)
/*!< APB peripherals */ /*!< APB peripherals */
#define WDT_BASE (APBPERIPH_BASE + 0x00000UL) #define WDT_BASE (APBPERIPH_BASE + 0x00000UL)
#define WWDT_BASE (APBPERIPH_BASE + 0x00100UL) #define WWDT_BASE (APBPERIPH_BASE + 0x00100UL)
#define RTC_BASE (APBPERIPH_BASE + 0x01000UL) #define RTC_BASE (APBPERIPH_BASE + 0x01000UL)
#define EADC_BASE (APBPERIPH_BASE + 0x03000UL) #define EADC_BASE (APBPERIPH_BASE + 0x03000UL)
#define EADC0_BASE (APBPERIPH_BASE + 0x03000UL)
#define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL) #define ACMP01_BASE (APBPERIPH_BASE + 0x05000UL)
#define DAC0_BASE (APBPERIPH_BASE + 0x07000UL) #define DAC0_BASE (APBPERIPH_BASE + 0x07000UL)
#define DAC1_BASE (APBPERIPH_BASE + 0x07040UL) #define DAC1_BASE (APBPERIPH_BASE + 0x07040UL)
@ -318,7 +383,6 @@ extern void SystemInit(void);
#define SPI1_BASE (APBPERIPH_BASE + 0x22000UL) #define SPI1_BASE (APBPERIPH_BASE + 0x22000UL)
#define SPI2_BASE (APBPERIPH_BASE + 0x23000UL) #define SPI2_BASE (APBPERIPH_BASE + 0x23000UL)
#define SPI3_BASE (APBPERIPH_BASE + 0x24000UL) #define SPI3_BASE (APBPERIPH_BASE + 0x24000UL)
#define SPI5_BASE (APBPERIPH_BASE + 0x25000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) #define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART0_BASE (APBPERIPH_BASE + 0x30000UL) #define UART0_BASE (APBPERIPH_BASE + 0x30000UL)
#define UART1_BASE (APBPERIPH_BASE + 0x31000UL) #define UART1_BASE (APBPERIPH_BASE + 0x31000UL)
@ -337,7 +401,6 @@ extern void SystemInit(void);
#define QEI1_BASE (APBPERIPH_BASE + 0x71000UL) #define QEI1_BASE (APBPERIPH_BASE + 0x71000UL)
#define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL) #define ECAP0_BASE (APBPERIPH_BASE + 0x74000UL)
#define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL) #define ECAP1_BASE (APBPERIPH_BASE + 0x75000UL)
#define DSRC_BASE (APBPERIPH_BASE + 0x77000UL)
#define TRNG_BASE (APBPERIPH_BASE + 0x79000UL) #define TRNG_BASE (APBPERIPH_BASE + 0x79000UL)
#define USBD_BASE (APBPERIPH_BASE + 0x80000UL) #define USBD_BASE (APBPERIPH_BASE + 0x80000UL)
#define USCI0_BASE (APBPERIPH_BASE + 0x90000UL) #define USCI0_BASE (APBPERIPH_BASE + 0x90000UL)
@ -361,106 +424,105 @@ extern void SystemInit(void);
*/ */
#define PA ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */ #define PA_S ((GPIO_T *) GPIOA_BASE) /*!< GPIO PORTA Pointer */
#define PB ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */ #define PB_S ((GPIO_T *) GPIOB_BASE) /*!< GPIO PORTB Pointer */
#define PC ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */ #define PC_S ((GPIO_T *) GPIOC_BASE) /*!< GPIO PORTC Pointer */
#define PD ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */ #define PD_S ((GPIO_T *) GPIOD_BASE) /*!< GPIO PORTD Pointer */
#define PE ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */ #define PE_S ((GPIO_T *) GPIOE_BASE) /*!< GPIO PORTE Pointer */
#define PF ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */ #define PF_S ((GPIO_T *) GPIOF_BASE) /*!< GPIO PORTF Pointer */
#define PG ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */ #define PG_S ((GPIO_T *) GPIOG_BASE) /*!< GPIO PORTG Pointer */
#define PH ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */ #define PH_S ((GPIO_T *) GPIOH_BASE) /*!< GPIO PORTH Pointer */
#define UART0 ((UART_T *) UART0_BASE) /*!< UART0 Pointer */ #define UART0_S ((UART_T *) UART0_BASE) /*!< UART0 Pointer */
#define UART1 ((UART_T *) UART1_BASE) /*!< UART1 Pointer */ #define UART1_S ((UART_T *) UART1_BASE) /*!< UART1 Pointer */
#define UART2 ((UART_T *) UART2_BASE) /*!< UART2 Pointer */ #define UART2_S ((UART_T *) UART2_BASE) /*!< UART2 Pointer */
#define UART3 ((UART_T *) UART3_BASE) /*!< UART3 Pointer */ #define UART3_S ((UART_T *) UART3_BASE) /*!< UART3 Pointer */
#define UART4 ((UART_T *) UART4_BASE) /*!< UART4 Pointer */ #define UART4_S ((UART_T *) UART4_BASE) /*!< UART4 Pointer */
#define UART5 ((UART_T *) UART5_BASE) /*!< UART5 Pointer */ #define UART5_S ((UART_T *) UART5_BASE) /*!< UART5 Pointer */
#define TIMER0 ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */ #define TIMER0_S ((TIMER_T *) TMR01_BASE) /*!< TIMER0 Pointer */
#define TIMER1 ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */ #define TIMER1_S ((TIMER_T *) (TMR01_BASE + 0x100UL)) /*!< TIMER1 Pointer */
#define TIMER2 ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */ #define TIMER2_S ((TIMER_T *) TMR23_BASE) /*!< TIMER2 Pointer */
#define TIMER3 ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */ #define TIMER3_S ((TIMER_T *) (TMR23_BASE + 0x100UL)) /*!< TIMER3 Pointer */
#define WDT ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */ #define WDT_S ((WDT_T *) WDT_BASE) /*!< Watch Dog Timer Pointer */
#define WWDT_S ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */
#define QSPI0_S ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */
#define SPI0_S ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */
#define SPI1_S ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */
#define SPI2_S ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */
#define SPI3_S ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */
#define I2S0_S ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */
#define I2C0_S ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */
#define I2C1_S ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */
#define I2C2_S ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */
#define QEI0_S ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */
#define QEI1_S ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */
#define RTC_S ((RTC_T *) RTC_BASE) /*!< RTC Pointer */
#define ACMP01_S ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */
#define CLK_S ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */
#define DAC0_S ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */
#define DAC1_S ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */
#define EADC_S ((EADC_T *) EADC_BASE) /*!< EADC Pointer */
#define SYS_S ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */
#define WWDT ((WWDT_T *) WWDT_BASE) /*!< Window Watch Dog Timer Pointer */ #define SYSINT_S ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */
#define QSPI0 ((QSPI_T *) QSPI0_BASE) /*!< QSPI0 Pointer */ #define FMC_S ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */
#define SPI0 ((SPI_T *) SPI0_BASE) /*!< SPI0 Pointer */
#define SPI1 ((SPI_T *) SPI1_BASE) /*!< SPI1 Pointer */
#define SPI2 ((SPI_T *) SPI2_BASE) /*!< SPI2 Pointer */
#define SPI3 ((SPI_T *) SPI3_BASE) /*!< SPI3 Pointer */
#define SPI5 ((SPI5_T *) SPI5_BASE) /*!< SPI5 Pointer */
#define I2S0 ((I2S_T *) I2S0_BASE) /*!< I2S0 Pointer */ #define SDH0_S ((SDH_T *) SDH0_BASE) /*!< SD Host Controller */
#define I2C0 ((I2C_T *) I2C0_BASE) /*!< I2C0 Pointer */ #define CRPT_S ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */
#define I2C1 ((I2C_T *) I2C1_BASE) /*!< I2C1 Pointer */ #define TRNG_S ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */
#define I2C2 ((I2C_T *) I2C2_BASE) /*!< I2C1 Pointer */
#define QEI0 ((QEI_T *) QEI0_BASE) /*!< QEI0 Pointer */ #define BPWM0_S ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */
#define QEI1 ((QEI_T *) QEI1_BASE) /*!< QEI1 Pointer */ #define BPWM1_S ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */
#define RTC ((RTC_T *) RTC_BASE) /*!< RTC Pointer */ #define EPWM0_S ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */
#define EPWM1_S ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */
#define ACMP01 ((ACMP_T *) ACMP01_BASE) /*!< ACMP01 Pointer */ #define SC0_S ((SC_T *) SC0_BASE) /*!< SC0 Pointer */
#define SC1_S ((SC_T *) SC1_BASE) /*!< SC1 Pointer */
#define SC2_S ((SC_T *) SC2_BASE) /*!< SC2 Pointer */
#define CLK ((CLK_T *) CLK_BASE) /*!< System Clock Controller Pointer */ #define EBI_S ((EBI_T *) EBI_BASE) /*!< EBI Pointer */
#define DAC0 ((DAC_T *) DAC0_BASE) /*!< DAC0 Pointer */ #define CRC_S ((CRC_T *) CRC_BASE) /*!< CRC Pointer */
#define DAC1 ((DAC_T *) DAC1_BASE) /*!< DAC1 Pointer */
#define EADC ((EADC_T *) EADC_BASE) /*!< EADC Pointer */ #define USBD_S ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */
#define USBH_S ((USBH_T *) USBH_BASE) /*!< USBH Pointer */
#define OTG_S ((OTG_T *) OTG_BASE) /*!< OTG Pointer */
#define SYS ((SYS_T *) SYS_BASE) /*!< System Global Controller Pointer */ #define PDMA0_S ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */
#define PDMA1_S ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */
#define SYSINT ((SYS_INT_T *) INT_BASE) /*!< Interrupt Source Controller Pointer */ #define UI2C0_S ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */
#define UI2C1_S ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */
#define UI2C2_S ((UI2C_T *) USCI2_BASE) /*!< UI2C2 Pointer */
#define FMC ((FMC_T *) FMC_BASE) /*!< Flash Memory Controller */ #define USPI0_S ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */
#define USPI1_S ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */
#define SDH0 ((SDH_T *) SDH0_BASE) #define UUART0_S ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */
#define UUART1_S ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */
#define CRPT ((CRPT_T *) CRPT_BASE) /*!< Crypto Accelerator Pointer */ #define SCU_S ((SCU_T *) SCU_BASE) /*!< SCU Pointer */
#define TRNG ((TRNG_T *)TRNG_BASE) /*!< True Random Number Pointer */ #define ECAP0_S ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */
#define ECAP1_S ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */
#define BPWM0 ((BPWM_T *) BPWM0_BASE) /*!< BPWM0 Pointer */ #define CAN0_S ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */
#define BPWM1 ((BPWM_T *) BPWM1_BASE) /*!< BPWM1 Pointer */
#define EPWM0 ((EPWM_T *) EPWM0_BASE) /*!< EPWM0 Pointer */
#define EPWM1 ((EPWM_T *) EPWM1_BASE) /*!< EPWM1 Pointer */
#define SC0 ((SC_T *) SC0_BASE) /*!< SC0 Pointer */
#define SC1 ((SC_T *) SC1_BASE) /*!< SC1 Pointer */
#define SC2 ((SC_T *) SC2_BASE) /*!< SC2 Pointer */
#define EBI ((EBI_T *) EBI_BASE) /*!< EBI Pointer */
#define CRC ((CRC_T *) CRC_BASE) /*!< CRC Pointer */
#define USBD ((USBD_T *) USBD_BASE) /*!< USB Device Pointer */
#define USBH ((USBH_T *) USBH_BASE) /*!< USBH Pointer */
#define OTG ((OTG_T *) OTG_BASE) /*!< OTG Pointer */
#define PDMA0 ((PDMA_T *) PDMA0_BASE) /*!< PDMA0 Pointer */
#define PDMA1 ((PDMA_T *) PDMA1_BASE) /*!< PDMA1 Pointer */
#define UI2C0 ((UI2C_T *) USCI0_BASE) /*!< UI2C0 Pointer */
#define UI2C1 ((UI2C_T *) USCI1_BASE) /*!< UI2C1 Pointer */
#define UI2C2 ((UI2C_T *) USCI2_BASE) /*!< UI2C2 Pointer */
#define USPI0 ((USPI_T *) USCI0_BASE) /*!< USPI0 Pointer */
#define USPI1 ((USPI_T *) USCI1_BASE) /*!< USPI1 Pointer */
#define UUART0 ((UUART_T *) USCI0_BASE) /*!< UUART0 Pointer */
#define UUART1 ((UUART_T *) USCI1_BASE) /*!< UUART1 Pointer */
#define SCU ((SCU_T *) SCU_BASE) /*!< SCU Pointer */
#define ECAP0 ((ECAP_T *) ECAP0_BASE) /*!< ECAP0 Pointer */
#define ECAP1 ((ECAP_T *) ECAP1_BASE) /*!< ECAP1 Pointer */
#define CAN0 ((CAN_T *)CAN0_BASE) /*!< CAN0 Pointer */
@ -473,14 +535,14 @@ extern void SystemInit(void);
*/ */
#define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */ #define PA_NS ((GPIO_T *) (GPIOA_BASE+NS_OFFSET)) /*!< GPIO PORTA Pointer */
#define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */ #define PB_NS ((GPIO_T *) (GPIOB_BASE+NS_OFFSET)) /*!< GPIO PORTB Pointer */
#define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */ #define PC_NS ((GPIO_T *) (GPIOC_BASE+NS_OFFSET)) /*!< GPIO PORTC Pointer */
#define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */ #define PD_NS ((GPIO_T *) (GPIOD_BASE+NS_OFFSET)) /*!< GPIO PORTD Pointer */
#define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */ #define PE_NS ((GPIO_T *) (GPIOE_BASE+NS_OFFSET)) /*!< GPIO PORTE Pointer */
#define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */ #define PF_NS ((GPIO_T *) (GPIOF_BASE+NS_OFFSET)) /*!< GPIO PORTF Pointer */
#define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */ #define PG_NS ((GPIO_T *) (GPIOG_BASE+NS_OFFSET)) /*!< GPIO PORTG Pointer */
#define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */ #define PH_NS ((GPIO_T *) (GPIOH_BASE+NS_OFFSET)) /*!< GPIO PORTH Pointer */
#define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */ #define UART0_NS ((UART_T *) (UART0_BASE+NS_OFFSET)) /*!< UART0 Pointer */
#define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */ #define UART1_NS ((UART_T *) (UART1_BASE+NS_OFFSET)) /*!< UART1 Pointer */
#define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */ #define UART2_NS ((UART_T *) (UART2_BASE+NS_OFFSET)) /*!< UART2 Pointer */
@ -489,52 +551,385 @@ extern void SystemInit(void);
#define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */ #define UART5_NS ((UART_T *) (UART5_BASE+NS_OFFSET)) /*!< UART5 Pointer */
#define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */ #define TIMER2_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET)) /*!< TIMER2 Pointer */
#define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */ #define TIMER3_NS ((TIMER_T *) (TMR23_BASE+NS_OFFSET+0x100UL)) /*!< TIMER3 Pointer */
#define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */ #define QSPI0_NS ((QSPI_T *) (QSPI0_BASE+NS_OFFSET)) /*!< QSPI0 Pointer */
#define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */ #define SPI0_NS ((SPI_T *) (SPI0_BASE+NS_OFFSET)) /*!< SPI0 Pointer */
#define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */ #define SPI1_NS ((SPI_T *) (SPI1_BASE+NS_OFFSET)) /*!< SPI1 Pointer */
#define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */ #define SPI2_NS ((SPI_T *) (SPI2_BASE+NS_OFFSET)) /*!< SPI2 Pointer */
#define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */ #define SPI3_NS ((SPI_T *) (SPI3_BASE+NS_OFFSET)) /*!< SPI3 Pointer */
#define SPI5_NS ((SPI5_T *) (SPI5_BASE+NS_OFFSET)) /*!< SPI5 Pointer */ #define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */
#define I2S0_NS ((I2S_T *) (I2S0_BASE+NS_OFFSET)) /*!< I2S0 Pointer */ #define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */
#define I2C0_NS ((I2C_T *) (I2C0_BASE+NS_OFFSET)) /*!< I2C0 Pointer */ #define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */
#define I2C1_NS ((I2C_T *) (I2C1_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ #define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */
#define I2C2_NS ((I2C_T *) (I2C2_BASE+NS_OFFSET)) /*!< I2C1 Pointer */ #define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */
#define QEI0_NS ((QEI_T *) (QEI0_BASE+NS_OFFSET)) /*!< QEI0 Pointer */ #define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */
#define QEI1_NS ((QEI_T *) (QEI1_BASE+NS_OFFSET)) /*!< QEI1 Pointer */ #define RTC_NS ((RTC_T *) (RTC_BASE +NS_OFFSET)) /*!< RTC Pointer */
#define RTC_NS ((RTC_T *) (RTC_BASE +NS_OFFSET)) /*!< RTC Pointer */
#define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */ #define ACMP01_NS ((ACMP_T *) (ACMP01_BASE+NS_OFFSET)) /*!< ACMP01 Pointer */
#define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */ #define DAC0_NS ((DAC_T *) (DAC0_BASE+NS_OFFSET)) /*!< DAC0 Pointer */
#define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */ #define DAC1_NS ((DAC_T *) (DAC1_BASE+NS_OFFSET)) /*!< DAC1 Pointer */
#define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */ #define EADC_NS ((EADC_T *) (EADC_BASE+NS_OFFSET)) /*!< EADC Pointer */
#define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET)) #define SDH0_NS ((SDH_T *) (SDH0_BASE +NS_OFFSET))
#define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET)) #define CRPT_NS ((CRPT_T *) (CRPT_BASE +NS_OFFSET))
#define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */ #define TRNG_NS ((TRNG_T *) (TRNG_BASE +NS_OFFSET)) /*!< Random Number Generator Pointer */
#define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */ #define BPWM0_NS ((BPWM_T *) (BPWM0_BASE+NS_OFFSET)) /*!< BPWM0 Pointer */
#define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */ #define BPWM1_NS ((BPWM_T *) (BPWM1_BASE+NS_OFFSET)) /*!< BPWM1 Pointer */
#define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */ #define EPWM0_NS ((EPWM_T *) (EPWM0_BASE+NS_OFFSET)) /*!< EPWM0 Pointer */
#define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */ #define EPWM1_NS ((EPWM_T *) (EPWM1_BASE+NS_OFFSET)) /*!< EPWM1 Pointer */
#define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */ #define SC0_NS ((SC_T *) (SC0_BASE +NS_OFFSET)) /*!< SC0 Pointer */
#define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */ #define SC1_NS ((SC_T *) (SC1_BASE +NS_OFFSET)) /*!< SC1 Pointer */
#define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */ #define SC2_NS ((SC_T *) (SC2_BASE +NS_OFFSET)) /*!< SC2 Pointer */
#define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */ #define EBI_NS ((EBI_T *) (EBI_BASE +NS_OFFSET)) /*!< EBI Pointer */
#define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */ #define CRC_NS ((CRC_T *) (CRC_BASE +NS_OFFSET)) /*!< CRC Pointer */
#define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */ #define USBD_NS ((USBD_T *) (USBD_BASE +NS_OFFSET)) /*!< USB Device Pointer */
#define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */ #define USBH_NS ((USBH_T *) (USBH_BASE +NS_OFFSET)) /*!< USBH Pointer */
#define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */ #define OTG_NS ((OTG_T *) (OTG_BASE +NS_OFFSET)) /*!< OTG Pointer */
#define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */ #define PDMA1_NS ((PDMA_T *) (PDMA1_BASE +NS_OFFSET)) /*!< PDMA1 Pointer */
#define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */ #define UI2C0_NS ((UI2C_T *) (USCI0_BASE +NS_OFFSET)) /*!< UI2C0 Pointer */
#define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */ #define UI2C1_NS ((UI2C_T *) (USCI1_BASE +NS_OFFSET)) /*!< UI2C1 Pointer */
#define UI2C2_NS ((UI2C_T *) (USCI2_BASE +NS_OFFSET)) /*!< UI2C2 Pointer */ #define UI2C2_NS ((UI2C_T *) (USCI2_BASE +NS_OFFSET)) /*!< UI2C2 Pointer */
#define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */ #define USPI0_NS ((USPI_T *) (USCI0_BASE +NS_OFFSET)) /*!< USPI0 Pointer */
#define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */ #define USPI1_NS ((USPI_T *) (USCI1_BASE +NS_OFFSET)) /*!< USPI1 Pointer */
#define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */ #define UUART0_NS ((UUART_T *) (USCI0_BASE+NS_OFFSET)) /*!< UUART0 Pointer */
#define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */ #define UUART1_NS ((UUART_T *) (USCI1_BASE+NS_OFFSET)) /*!< UUART1 Pointer */
#define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */ #define SCU_NS ((SCU_T *) (SCU_BASE +NS_OFFSET)) /*!< SCU Pointer */
#define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */ #define ECAP0_NS ((ECAP_T *) (ECAP0_BASE+NS_OFFSET)) /*!< ECAP0 Pointer */
#define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */ #define ECAP1_NS ((ECAP_T *) (ECAP1_BASE+NS_OFFSET)) /*!< ECAP1 Pointer */
#define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */ #define CAN0_NS ((CAN_T *) (CAN0_BASE +NS_OFFSET)) /*!< CAN0 Pointer */
/**@}*/ /* end of group PMODULE_NS */ /**@}*/ /* end of group PMODULE_NS */
/* Always Secure Modules */
#define SYS SYS_S
#define CLK CLK_S
#define FMC FMC_S
#define SCU SCU_S
#define PDMA0 PDMA0_S
#define WDT WDT_S
#define WWDT WWDT_S
#define TIMER0 TIMER0_S
#define TIMER1 TIMER1_S
#define RTC RTC_S
#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT9 )
# define USBH USBH_NS
#else
# define USBH USBH_S
#endif
#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT13)
# define SDH0 SDH0_NS
#else
# define SDH0 SDH0_S
#endif
#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT16)
# define EBI EBI_NS
#else
# define EBI EBI_S
#endif
#if defined (SCU_INIT_PNSSET0_VAL) && (SCU_INIT_PNSSET0_VAL & BIT24)
# define PDMA1 PDMA1_NS
#else
# define PDMA1 PDMA1_S
#endif
#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT17)
# define CRC CRC_NS
#else
# define CRC CRC_S
#endif
#if defined (SCU_INIT_PNSSET1_VAL) && (SCU_INIT_PNSSET1_VAL & BIT18)
# define CRPT CRPT_NS
#else
# define CRPT CRPT_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT3 )
# define EADC EADC_NS
#else
# define EADC EADC_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT5 )
# define ACMP01 ACMP01_NS
#else
# define ACMP01 ACMP01_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT7 )
# define DAC0 DAC0_NS
# define DAC1 DAC1_NS
#else
# define DAC0 DAC0_S
# define DAC1 DAC1_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT8 )
# define I2S0 I2S0_NS
#else
# define I2S0 I2S0_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT13)
# define OTG OTG_NS
#else
# define OTG OTG_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT17)
# define TIMER2 TIMER2_NS
# define TIMER3 TIMER3_NS
#else
# define TIMER2 TIMER2_S
# define TIMER3 TIMER3_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT24)
# define EPWM0 EPWM0_NS
#else
# define EPWM0 EPWM0_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT25)
# define EPWM1 EPWM1_NS
#else
# define EPWM1 EPWM1_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT26)
# define BPWM0 BPWM0_NS
#else
# define BPWM0 BPWM0_S
#endif
#if defined (SCU_INIT_PNSSET2_VAL) && (SCU_INIT_PNSSET2_VAL & BIT27)
# define BPWM1 BPWM1_NS
#else
# define BPWM1 BPWM1_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT0 )
# define QSPI0 QSPI0_NS
#else
# define QSPI0 QSPI0_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT1 )
# define SPI0 SPI0_NS
#else
# define SPI0 SPI0_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT2 )
# define SPI1 SPI1_NS
#else
# define SPI1 SPI1_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT3 )
# define SPI2 SPI2_NS
#else
# define SPI2 SPI2_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT4 )
# define SPI3 SPI3_NS
#else
# define SPI3 SPI3_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT16)
# define UART0 UART0_NS
#else
# define UART0 UART0_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT17)
# define UART1 UART1_NS
#else
# define UART1 UART1_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT18)
# define UART2 UART2_NS
#else
# define UART2 UART2_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT19)
# define UART3 UART3_NS
#else
# define UART3 UART3_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT20)
# define UART4 UART4_NS
#else
# define UART4 UART4_S
#endif
#if defined (SCU_INIT_PNSSET3_VAL) && (SCU_INIT_PNSSET3_VAL & BIT21)
# define UART5 UART5_NS
#else
# define UART5 UART5_S
#endif
#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT0 )
# define I2C0 I2C0_NS
#else
# define I2C0 I2C0_S
#endif
#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT1 )
# define I2C1 I2C1_NS
#else
# define I2C1 I2C1_S
#endif
#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT2 )
# define I2C2 I2C2_NS
#else
# define I2C2 I2C2_S
#endif
#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT16)
# define SC0 SC0_NS
#else
# define SC0 SC0_S
#endif
#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT17)
# define SC1 SC1_NS
#else
# define SC1 SC1_S
#endif
#if defined (SCU_INIT_PNSSET4_VAL) && (SCU_INIT_PNSSET4_VAL & BIT18)
# define SC2 SC2_NS
#else
# define SC2 SC2_S
#endif
#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT0 )
# define CAN0 CAN0_NS
#else
# define CAN0 CAN0_S
#endif
#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT16)
# define QEI0 QEI0_NS
#else
# define QEI0 QEI0_S
#endif
#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT17)
# define QEI1 QEI1_NS
#else
# define QEI1 QEI1_S
#endif
#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT20)
# define ECAP0 ECAP0_NS
#else
# define ECAP0 ECAP0_S
#endif
#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT21)
# define ECAP1 ECAP1_NS
#else
# define ECAP1 ECAP1_S
#endif
#if defined (SCU_INIT_PNSSET5_VAL) && (SCU_INIT_PNSSET5_VAL & BIT25)
# define TRNG TRNG_NS
#else
# define TRNG TRNG_S
#endif
#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT0 )
# define USBD USBD_NS
#else
# define USBD USBD_S
#endif
#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT16)
# define USCI0 USCI0_NS
# define UI2C0 UI2C0_NS
# define USPI0 USPI0_NS
# define UUART0 UUART0_NS
#else
# define USCI0 USCI0_S
# define UI2C0 UI2C0_S
# define USPI0 USPI0_S
# define UUART0 UUART0_S
#endif
#if defined (SCU_INIT_PNSSET6_VAL) && (SCU_INIT_PNSSET6_VAL & BIT17)
# define USCI1 USCI1_NS
# define UI2C1 UI2C1_NS
# define USPI1 USPI1_NS
# define UUART1 UUART1_NS
#else
# define USCI1 USCI1_S
# define UI2C1 UI2C1_S
# define USPI1 USPI1_S
# define UUART1 UUART1_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT0 )
# define PA PA_NS
#else
# define PA PA_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT1 )
# define PB PB_NS
#else
# define PB PB_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT2 )
# define PC PC_NS
#else
# define PC PC_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT3 )
# define PD PD_NS
#else
# define PD PD_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT4 )
# define PE PE_NS
#else
# define PE PE_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT5 )
# define PF PF_NS
#else
# define PF PF_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT6 )
# define PG PG_NS
#else
# define PG PG_S
#endif
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT7 )
# define PH PH_NS
#else
# define PH PH_S
#endif
/**@}*/ /* end of group PMODULE */ /**@}*/ /* end of group PMODULE */
/* -------------------- End of section using anonymous unions ------------------- */ /* -------------------- End of section using anonymous unions ------------------- */
@ -561,84 +956,6 @@ extern void SystemInit(void);
#endif #endif
/*=============================================================================*/
typedef volatile unsigned char vu8;
typedef volatile unsigned long vu32;
typedef volatile unsigned short vu16;
#define M8(adr) (*((vu8 *) (adr)))
#define M16(adr) (*((vu16 *) (adr)))
#define M32(adr) (*((vu32 *) (adr)))
#define outpw(port,value) (*((volatile unsigned int *)(port))=(value))
#define inpw(port) ((*((volatile unsigned int *)(port))))
#define outpb(port,value) (*((volatile unsigned char *)(port))=(value))
#define inpb(port) ((*((volatile unsigned char *)(port))))
#define outps(port,value) (*((volatile unsigned short *)(port))=(value))
#define inps(port) ((*((volatile unsigned short *)(port))))
#define outp32(port,value) (*((volatile unsigned int *)(port))=(value))
#define inp32(port) ((*((volatile unsigned int *)(port))))
#define outp8(port,value) (*((volatile unsigned char *)(port))=(value))
#define inp8(port) ((*((volatile unsigned char *)(port))))
#define outp16(port,value) (*((volatile unsigned short *)(port))=(value))
#define inp16(port) ((*((volatile unsigned short *)(port))))
#define E_SUCCESS 0
#define TRUE (1L)
#define FALSE (0L)
#define ENABLE 1
#define DISABLE 0
/* Bit Mask Definitions */
#define BIT0 0x00000001UL
#define BIT1 0x00000002UL
#define BIT2 0x00000004UL
#define BIT3 0x00000008UL
#define BIT4 0x00000010UL
#define BIT5 0x00000020UL
#define BIT6 0x00000040UL
#define BIT7 0x00000080UL
#define BIT8 0x00000100UL
#define BIT9 0x00000200UL
#define BIT10 0x00000400UL
#define BIT11 0x00000800UL
#define BIT12 0x00001000UL
#define BIT13 0x00002000UL
#define BIT14 0x00004000UL
#define BIT15 0x00008000UL
#define BIT16 0x00010000UL
#define BIT17 0x00020000UL
#define BIT18 0x00040000UL
#define BIT19 0x00080000UL
#define BIT20 0x00100000UL
#define BIT21 0x00200000UL
#define BIT22 0x00400000UL
#define BIT23 0x00800000UL
#define BIT24 0x01000000UL
#define BIT25 0x02000000UL
#define BIT26 0x04000000UL
#define BIT27 0x08000000UL
#define BIT28 0x10000000UL
#define BIT29 0x20000000UL
#define BIT30 0x40000000UL
#define BIT31 0x80000000UL
/* Byte Mask Definitions */
#define BYTE0_Msk (0x000000FFUL)
#define BYTE1_Msk (0x0000FF00UL)
#define BYTE2_Msk (0x00FF0000UL)
#define BYTE3_Msk (0xFF000000UL)
#define _GET_BYTE0(u32Param) (((u32Param) & BYTE0_Msk) ) /*!< Extract Byte 0 (Bit 0~ 7) from parameter u32Param */
#define _GET_BYTE1(u32Param) (((u32Param) & BYTE1_Msk) >> 8UL) /*!< Extract Byte 1 (Bit 8~15) from parameter u32Param */
#define _GET_BYTE2(u32Param) (((u32Param) & BYTE2_Msk) >> 16UL) /*!< Extract Byte 2 (Bit 16~23) from parameter u32Param */
#define _GET_BYTE3(u32Param) (((u32Param) & BYTE3_Msk) >> 24UL) /*!< Extract Byte 3 (Bit 24~31) from parameter u32Param */
/******************************************************************************/ /******************************************************************************/
/* Peripheral header files */ /* Peripheral header files */
/******************************************************************************/ /******************************************************************************/
@ -656,7 +973,6 @@ typedef volatile unsigned short vu16;
#include "m2351_epwm.h" #include "m2351_epwm.h"
#include "m2351_qspi.h" #include "m2351_qspi.h"
#include "m2351_spi.h" #include "m2351_spi.h"
#include "m2351_spi5.h"
#include "m2351_timer.h" #include "m2351_timer.h"
#include "m2351_timer_pwm.h" #include "m2351_timer_pwm.h"
#include "m2351_wdt.h" #include "m2351_wdt.h"

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/acmp_reg.h
View File

@ -8,6 +8,13 @@
#ifndef __ACMP_REG_H__ #ifndef __ACMP_REG_H__
#define __ACMP_REG_H__ #define __ACMP_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Analog Comparator Controller -------------------------*/ /*---------------------- Analog Comparator Controller -------------------------*/
/** /**
@addtogroup ACMP Analog Comparator Controller(ACMP) @addtogroup ACMP Analog Comparator Controller(ACMP)
@ -251,5 +258,6 @@ typedef struct
/**@}*/ /* ACMP_CONST */ /**@}*/ /* ACMP_CONST */
/**@}*/ /* end of ACMP register group */ /**@}*/ /* end of ACMP register group */
/**@}*/ /* end of REGISTER group */
#endif /* __ACMP_REG_H__ */ #endif /* __ACMP_REG_H__ */

91
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/bpwm_reg.h
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@ -8,6 +8,12 @@
#ifndef __BPWM_REG_H__ #ifndef __BPWM_REG_H__
#define __BPWM_REG_H__ #define __BPWM_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Basic Pulse Width Modulation Controller -------------------------*/ /*---------------------- Basic Pulse Width Modulation Controller -------------------------*/
/** /**
@ -979,90 +985,6 @@ typedef struct
* | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1 * | | |This flag indicates if falling latch happened when the corresponding CAPFIF is 1
* | | |Each bit n controls the corresponding BPWM channel n. * | | |Each bit n controls the corresponding BPWM channel n.
* | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF. * | | |Note: This bit will be cleared automatically when user clear corresponding CAPFIF.
* @var BPWM_T::RCAPDAT0
* Offset: 0x20C BPWM Rising Capture Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT0
* Offset: 0x210 BPWM Falling Capture Data Register 0
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT1
* Offset: 0x214 BPWM Rising Capture Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT1
* Offset: 0x218 BPWM Falling Capture Data Register 1
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT2
* Offset: 0x21C BPWM Rising Capture Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT2
* Offset: 0x220 BPWM Falling Capture Data Register 2
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT3
* Offset: 0x224 BPWM Rising Capture Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT3
* Offset: 0x228 BPWM Falling Capture Data Register 3
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT4
* Offset: 0x22C BPWM Rising Capture Data Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT4
* Offset: 0x230 BPWM Falling Capture Data Register 4
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::RCAPDAT5
* Offset: 0x234 BPWM Rising Capture Data Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |RCAPDAT |BPWM Rising Capture Data Register (Read Only)
* | | |When rising capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::FCAPDAT5
* Offset: 0x238 BPWM Falling Capture Data Register 5
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[15:0] |FCAPDAT |BPWM Falling Capture Data Register (Read Only)
* | | |When falling capture condition happened, the BPWM counter value will be saved in this register.
* @var BPWM_T::CAPIEN * @var BPWM_T::CAPIEN
* Offset: 0x250 BPWM Capture Interrupt Enable Register * Offset: 0x250 BPWM Capture Interrupt Enable Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
@ -1869,6 +1791,7 @@ typedef struct
/**@}*/ /* BPWM_CONST */ /**@}*/ /* BPWM_CONST */
/**@}*/ /* end of BPWM register group */ /**@}*/ /* end of BPWM register group */
/**@}*/ /* end of REGISTER group */
#endif /* __BPWM_REG_H__ */ #endif /* __BPWM_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/can_reg.h
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@ -8,6 +8,13 @@
#ifndef __CAN_REG_H__ #ifndef __CAN_REG_H__
#define __CAN_REG_H__ #define __CAN_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Controller Area Network Controller -------------------------*/ /*---------------------- Controller Area Network Controller -------------------------*/
/** /**
@addtogroup CAN Controller Area Network Controller(CAN) @addtogroup CAN Controller Area Network Controller(CAN)
@ -774,6 +781,7 @@ typedef struct
/**@}*/ /* CAN_CONST */ /**@}*/ /* CAN_CONST */
/**@}*/ /* end of CAN register group */ /**@}*/ /* end of CAN register group */
/**@}*/ /* end of REGISTER group */
#endif /* __CAN_REG_H__ */ #endif /* __CAN_REG_H__ */

237
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/clk_reg.h
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@ -8,6 +8,13 @@
#ifndef __CLK_REG_H__ #ifndef __CLK_REG_H__
#define __CLK_REG_H__ #define __CLK_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- System Clock Controller -------------------------*/ /*---------------------- System Clock Controller -------------------------*/
/** /**
@addtogroup CLK System Clock Controller(CLK) @addtogroup CLK System Clock Controller(CLK)
@ -46,16 +53,16 @@ typedef struct
* | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note1: This bit is write protected. Refer to the SYS_REGLCTL register.
* | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC. * | | |Note2: LIRC cannot be disabled and LIRCEN will always read as 1 if HCLK clock source is selected from LIRC.
* | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]). * | | |Note3: If CWDTEN(CONFIG[31,4:3]) is set to 111, LIRC clock can be enabled or disabled by setting LIRCEN(CLK_PWRCTL[3]).
* | | |If CWDTEN([31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1 * | | |If CWDTEN(CONFIG0[31,4:3]) is not set to 111, LIRC cannot be disabled in normal mode and LIRCEN will always read as 1
* | | |In Power-down mode, LIRC clock is control by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG[30]) setting. * | | |In Power-down mode, LIRC clock is controlled by LIRCEN(CLK_PWRCTL[3]) and CWDTPDEN (CONFIG0[30]) setting.
* |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect) * |[5] |PDWKIEN |Power-down Mode Wake-up Interrupt Enable Bit (Write Protect)
* | | |0 = Power-down mode wake-up interrupt Disabled. * | | |0 = Power-down mode wake-up interrupt Disabled.
* | | |1 = Power-down mode wake-up interrupt Enabled. * | | |1 = Power-down mode wake-up interrupt Enabled.
* | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from power-down mode. * | | |Note1: The interrupt will occur when both PDWKIF and PDWKIEN are high, after resume from Power-down mode.
* | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note2: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status * |[6] |PDWKIF |Power-down Mode Wake-up Interrupt Status
* | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode * | | |Set by Power-down wake-up event, it indicates that resume from Power-down mode.
* | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, SPI5, DSRC, RTC wake-up occurred. * | | |The flag is set if the EINT7~0, GPIO, UART0~5, USBH, USBD, OTG, CAN0, BOD, ACMP, WDT, SDH0, TMR0~3, I2C0~2, USCI0~1, RTC wake-up occurred.
* | | |Note1: Write 1 to clear the bit to 0. * | | |Note1: Write 1 to clear the bit to 0.
* | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1. * | | |Note2: This bit works only if PDWKIEN (CLK_PWRCTL[5]) set to 1.
* |[7] |PDEN |System Power-down Enable (Write Protect) * |[7] |PDEN |System Power-down Enable (Write Protect)
@ -91,11 +98,11 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure) * |[0] |PDMA0CKEN |PDMA0 Controller Clock Enable Bit (Secure)
* | | |0 = PDMA peripheral clock Disabled. * | | |0 = PDMA0 peripheral clock Disabled.
* | | |1 = PDMA peripheral clock Enabled. * | | |1 = PDMA0 peripheral clock Enabled.
* |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit * |[1] |PDMA1CKEN |PDMA1 Controller Clock Enable Bit
* | | |0 = PDMA peripheral clock Disabled. * | | |0 = PDMA1 peripheral clock Disabled.
* | | |1 = PDMA peripheral clock Enabled. * | | |1 = PDMA1 peripheral clock Enabled.
* |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit * |[2] |ISPCKEN |Flash ISP Controller Clock Enable Bit
* | | |0 = Flash ISP peripheral clock Disabled. * | | |0 = Flash ISP peripheral clock Disabled.
* | | |1 = Flash ISP peripheral clock Enabled. * | | |1 = Flash ISP peripheral clock Enabled.
@ -127,7 +134,7 @@ typedef struct
* | | |1 = Watchdog timer clock Enabled. * | | |1 = Watchdog timer clock Enabled.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit * |[1] |RTCCKEN |Real-time-clock APB Interface Clock Enable Bit
* | | |This bit is used to control the RTC APB clock only * | | |This bit is used to control the RTC APB clock only.
* | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8]) * | | |The RTC peripheral clock source is selected from RTCSEL(CLK_CLKSEL3[8])
* | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC). * | | |It can be selected to 32.768 kHz external low speed crystal (LXT) or 10 kHz internal low speed RC oscillator (LIRC).
* | | |0 = RTC clock Disabled. * | | |0 = RTC clock Disabled.
@ -189,9 +196,6 @@ typedef struct
* |[21] |UART5CKEN |UART5 Clock Enable Bit * |[21] |UART5CKEN |UART5 Clock Enable Bit
* | | |0 = UART5 clock Disabled. * | | |0 = UART5 clock Disabled.
* | | |1 = UART5 clock Enabled. * | | |1 = UART5 clock Enabled.
* |[23] |DSRCCKEN |DSRC Clock Enable Bit
* | | |0 = DSRC clock Disabled.
* | | |1 = DSRC clock Enabled.
* |[24] |CAN0CKEN |CAN0 Clock Enable Bit * |[24] |CAN0CKEN |CAN0 Clock Enable Bit
* | | |0 = CAN0 clock Disabled. * | | |0 = CAN0 clock Disabled.
* | | |1 = CAN0 clock Enabled. * | | |1 = CAN0 clock Enabled.
@ -224,9 +228,6 @@ typedef struct
* |[6] |SPI3CKEN |SPI3 Clock Enable Bit * |[6] |SPI3CKEN |SPI3 Clock Enable Bit
* | | |0 = SPI3 clock Disabled. * | | |0 = SPI3 clock Disabled.
* | | |1 = SPI3 clock Enabled. * | | |1 = SPI3 clock Enabled.
* |[7] |SPI5CKEN |SPI5 Clock Enable Bit
* | | |0 = SPI5 clock Disabled.
* | | |1 = SPI5 clock Enabled.
* |[8] |USCI0CKEN |USCI0 Clock Enable Bit * |[8] |USCI0CKEN |USCI0 Clock Enable Bit
* | | |0 = USCI0 clock Disabled. * | | |0 = USCI0 clock Disabled.
* | | |1 = USCI0 clock Enabled. * | | |1 = USCI0 clock Enabled.
@ -237,11 +238,11 @@ typedef struct
* | | |0 = DAC clock Disabled. * | | |0 = DAC clock Disabled.
* | | |1 = DAC clock Enabled. * | | |1 = DAC clock Enabled.
* |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit * |[16] |EPWM0CKEN |EPWM0 Clock Enable Bit
* | | |0 = PWM0 clock Disabled. * | | |0 = EPWM0 clock Disabled.
* | | |1 = PWM0 clock Enabled. * | | |1 = EPWM0 clock Enabled.
* |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit * |[17] |EPWM1CKEN |EPWM1 Clock Enable Bit
* | | |0 = PWM1 clock Disabled. * | | |0 = EPWM1 clock Disabled.
* | | |1 = PWM1 clock Enabled. * | | |1 = EPWM1 clock Enabled.
* |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit * |[18] |BPWM0CKEN |BPWM0 Clock Enable Bit
* | | |0 = BPWM0 clock Disabled. * | | |0 = BPWM0 clock Disabled.
* | | |1 = BPWM0 clock Enabled. * | | |1 = BPWM0 clock Enabled.
@ -286,11 +287,10 @@ typedef struct
* | | |011 = Clock source from HCLK/2. * | | |011 = Clock source from HCLK/2.
* | | |111 = Clock source from HIRC/2. * | | |111 = Clock source from HIRC/2.
* | | |Others = Reserved. * | | |Others = Reserved.
* | | |Note1: if SysTick clock source is not from HCLK (i.e * | | |Note1: if SysTick clock source is not from HCLK (i.e SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
* | | |SYST_CTRL[2] = 0), SysTick clock source must less than or equal to HCLK/2.
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[8] |USBSEL |USB Clock Source Selection (Write Protect) * |[8] |USBSEL |USB Clock Source Selection (Write Protect)
* | | |0 = Reserved. * | | |0 = Clock source from HIRC48.
* | | |1 = Clock source from PLL. * | | |1 = Clock source from PLL.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect) * |[21:20] |SDH0SEL |SDHOST0 Peripheral Clock Source Selection (Write Protect)
@ -310,9 +310,6 @@ typedef struct
* | | |10 = Clock source from HCLK/2048. * | | |10 = Clock source from HCLK/2048.
* | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC). * | | |11 = Clock source from 10 kHz internal low speed RC oscillator (LIRC).
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[3] |DSRCSEL |DSRC Clock Source Selection
* | | |0 = Reserved.
* | | |1 = Clock source from HIRC.
* |[10:8] |TMR0SEL |TIMER0 Clock Source Selection * |[10:8] |TMR0SEL |TIMER0 Clock Source Selection
* | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT). * | | |000 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT). * | | |001 = Clock source from 32.768 kHz external low speed crystal oscillator (LXT).
@ -407,11 +404,6 @@ typedef struct
* | | |01 = Clock source from PLL. * | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK0. * | | |10 = Clock source from PCLK0.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC). * | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* |[15:14] |SPI5SEL |SPI5 Clock Source Selection
* | | |00 = Clock source from 4~24 MHz external high speed crystal oscillator (HXT).
* | | |01 = Clock source from PLL.
* | | |10 = Clock source from PCLK1.
* | | |11 = Clock source from 12 MHz internal high speed RC oscillator (HIRC).
* @var CLK_T::CLKSEL3 * @var CLK_T::CLKSEL3
* Offset: 0x1C Clock Source Select Control Register 3 * Offset: 0x1C Clock Source Select Control Register 3
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
@ -465,43 +457,41 @@ typedef struct
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[3:0] |HCLKDIV |HCLK Clock Divide Number From HCLK Clock Source * |[3:0] |HCLKDIV |HCLK Clock Divide Number from HCLK Clock Source
* | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1). * | | |HCLK clock frequency = (HCLK clock source frequency) / (HCLKDIV + 1).
* |[7:4] |USBDIV |USB Clock Divide Number From PLL Clock * |[7:4] |USBDIV |USB Clock Divide Number from PLL Clock
* | | |USB clock frequency = (PLL frequency) / (USBDIV + 1). * | | |USB clock frequency = (PLL frequency) / (USBDIV + 1).
* |[11:8] |UART0DIV |UART0 Clock Divide Number From UART0 Clock Source * |[11:8] |UART0DIV |UART0 Clock Divide Number from UART0 Clock Source
* | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1). * | | |UART0 clock frequency = (UART0 clock source frequency) / (UART0DIV + 1).
* |[15:12] |UART1DIV |UART1 Clock Divide Number From UART1 Clock Source * |[15:12] |UART1DIV |UART1 Clock Divide Number from UART1 Clock Source
* | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1). * | | |UART1 clock frequency = (UART1 clock source frequency) / (UART1DIV + 1).
* |[23:16] |EADCDIV |EADC Clock Divide Number From EADC Clock Source * |[23:16] |EADCDIV |EADC Clock Divide Number from EADC Clock Source
* | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1). * | | |EADC clock frequency = (EADC clock source frequency) / (EADCDIV + 1).
* |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number From SDHOST0 Clock Source * |[31:24] |SDH0DIV |SDHOST0 Clock Divide Number from SDHOST0 Clock Source
* | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1). * | | |SDHOST0 clock frequency = (SDHOST0 clock source frequency) / (SDH0DIV + 1).
* @var CLK_T::CLKDIV1 * @var CLK_T::CLKDIV1
* Offset: 0x24 Clock Divider Number Register 1 * Offset: 0x24 Clock Divider Number Register 1
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number From SC0 Clock Source * |[7:0] |SC0DIV |Smart Card 0 (SC0) Clock Divide Number from SC0 Clock Source
* | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1). * | | |SC0 clock frequency = (SC0 clock source frequency) / (SC0DIV + 1).
* |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number From SC1 Clock Source * |[15:8] |SC1DIV |Smart Card 1 (SC1) Clock Divide Number from SC1 Clock Source
* | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1). * | | |SC1 clock frequency = (SC1 clock source frequency) / (SC1DIV + 1).
* |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number From SC2 Clock Source * |[23:16] |SC2DIV |Smart Card 2 (SC2) Clock Divide Number from SC2 Clock Source
* | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1). * | | |SC2 clock frequency = (SC2 clock source frequency) / (SC2DIV + 1).
* |[28:24] |DSRCDIV |DSRC Clock Divide Number From DSRC Clock Source
* | | |DSRC clock frequency = (DSRC clock source frequency) / (DSRCDIV + 1).
* @var CLK_T::CLKDIV4 * @var CLK_T::CLKDIV4
* Offset: 0x30 Clock Divider Number Register 4 * Offset: 0x30 Clock Divider Number Register 4
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[3:0] |UART2DIV |UART2 Clock Divide Number From UART2 Clock Source * |[3:0] |UART2DIV |UART2 Clock Divide Number from UART2 Clock Source
* | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1). * | | |UART2 clock frequency = (UART2 clock source frequency) / (UART2DIV + 1).
* |[7:4] |UART3DIV |UART3 Clock Divide Number From UART3 Clock Source * |[7:4] |UART3DIV |UART3 Clock Divide Number from UART3 Clock Source
* | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1). * | | |UART3 clock frequency = (UART3 clock source frequency) / (UART3DIV + 1).
* |[11:8] |UART4DIV |UART4 Clock Divide Number From UART4 Clock Source * |[11:8] |UART4DIV |UART4 Clock Divide Number from UART4 Clock Source
* | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1). * | | |UART4 clock frequency = (UART4 clock source frequency) / (UART4DIV + 1).
* |[15:12] |UART5DIV |UART5 Clock Divide Number From UART5 Clock Source * |[15:12] |UART5DIV |UART5 Clock Divide Number from UART5 Clock Source
* | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1). * | | |UART5 clock frequency = (UART5 clock source frequency) / (UART5DIV + 1).
* @var CLK_T::PCLKDIV * @var CLK_T::PCLKDIV
* Offset: 0x34 APB Clock Divider Register * Offset: 0x34 APB Clock Divider Register
@ -533,13 +523,13 @@ typedef struct
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect) * |[8:0] |FBDIV |PLL Feedback Divider Control (Write Protect)
* | | |Refer to the PLL formulas. * | | |Refer to the PLL formulas.
* | | |Note1: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[13:9] |INDIV |PLL Input Divider Control (Write Protect) * |[13:9] |INDIV |PLL Input Divider Control (Write Protect)
* | | |Refer to the PLL formulas. * | | |Refer to the PLL formulas.
* | | |Note1: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect) * |[15:14] |OUTDIV |PLL Output Divider Control (Write Protect)
* | | |Refer to the PLL formulas. * | | |Refer to the PLL formulas.
* | | |Note1: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[16] |PD |Power-down Mode (Write Protect) * |[16] |PD |Power-down Mode (Write Protect)
* | | |0 = PLL is enable (in normal mode). * | | |0 = PLL is enable (in normal mode).
* | | |1 = PLL is disable (in Power-down mode) (default). * | | |1 = PLL is disable (in Power-down mode) (default).
@ -570,7 +560,9 @@ typedef struct
* | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled. * | | |0 = 4~24 MHz external high speed crystal oscillator (HXT) clock is not stable or disabled.
* | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled. * | | |1 = 4~24 MHz external high speed crystal oscillator (HXT) clock is stable and enabled.
* |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only) * |[1] |LXTSTB |LXT Clock Source Stable Flag (Read Only)
* | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]). If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable. If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable. * | | |LXT clock source can be selected as extLXT or LIRC32 by setting C32KS(RTC_LXTCTL[7]).
* | | |If C32KS is set to 0 the LXT stable flag is set when extLXT clock source is stable.
* | | |If C32KS is set to 1 the LXT stable flag is set when LIRC32 clock source is stable.
* | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled. * | | |0 = 32.768 kHz external low speed crystal oscillator (LXT) clock is not stable or disabled.
* | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled. * | | |1 = 32.768 kHz external low speed crystal oscillator (LXT) clock is stabled and enabled.
* |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only) * |[2] |PLLSTB |Internal PLL Clock Source Stable Flag (Read Only)
@ -602,7 +594,7 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[3:0] |FREQSEL |Clock Output Frequency Selection * |[3:0] |FREQSEL |Clock Output Frequency Selection
* | | |The formula of output frequency is Fout = Fin/2(N+1). * | | |The formula of output frequency is Fout = Fin/2^(N+1).
* | | |Fin is the input clock frequency. * | | |Fin is the input clock frequency.
* | | |Fout is the frequency of divider output clock. * | | |Fout is the frequency of divider output clock.
* | | |N is the 4-bit value of FREQSEL[3:0]. * | | |N is the 4-bit value of FREQSEL[3:0].
@ -680,7 +672,7 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect) * |[2:0] |PDMSEL |Power-down Mode Selection (Write Protect)
* | | |These bits control chip power-down mode grade selection when CPU execute WFI/WFE instruction. * | | |These bits control chip Power-down mode grade selection when CPU execute WFI/WFE instruction.
* | | |000 = Power-down mode is selected (PD). * | | |000 = Power-down mode is selected (PD).
* | | |001 = Low leakage Power-down mode is selected (LLPD). * | | |001 = Low leakage Power-down mode is selected (LLPD).
* | | |010 = Fast wake-up Power-down (FWPD). * | | |010 = Fast wake-up Power-down (FWPD).
@ -690,35 +682,35 @@ typedef struct
* | | |110 = Deep Power-down mode is selected (DPD). * | | |110 = Deep Power-down mode is selected (DPD).
* | | |111 = Reserved. * | | |111 = Reserved.
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[8] |WKTMREN |Wake-up Timer Enable (Write Protect) * |[8] |WKTMREN |Wake-up Timer Enable Bit (Write Protect)
* | | |0 = Wake-up timer disable at Deep Power-down mode or Standby Power-down mode. * | | |0 = Wake-up timer Disable in Deep Power-down mode or Standby Power-down mode.
* | | |1 = Wake-up timer enabled at Deep Power-down mode or Standby Power-down mode. * | | |1 = Wake-up timer Enabled in Deep Power-down mode or Standby Power-down mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect) * |[11:9] |WKTMRIS |Wake-up Timer Time-out Interval Select (Write Protect)
* | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode. * | | |These bits control wake-up timer time-out interval when chip under Deep Power-down mode or Standby Power-down mode.
* | | |000 = Time-out interval is 128 OSC10K clocks (12.8ms). * | | |000 = Time-out interval is 128 LIRC clocks (12.8ms).
* | | |001 = Time-out interval is 256 OSC10K clocks (25.6ms). * | | |001 = Time-out interval is 256 LIRC clocks (25.6ms).
* | | |010 = Time-out interval is 512 OSC10K clocks (51.2ms). * | | |010 = Time-out interval is 512 LIRC clocks (51.2ms).
* | | |011 = Time-out interval is 1024 OSC10K clocks (102.4ms). * | | |011 = Time-out interval is 1024 LIRC clocks (102.4ms).
* | | |100 = Time-out interval is 4096 OSC10K clocks (409.6ms). * | | |100 = Time-out interval is 4096 LIRC clocks (409.6ms).
* | | |101 = Time-out interval is 8192 OSC10K clocks (819.2ms). * | | |101 = Time-out interval is 8192 LIRC clocks (819.2ms).
* | | |110 = Time-out interval is 16384 OSC10K clocks (1638.4ms). * | | |110 = Time-out interval is 16384 LIRC clocks (1638.4ms).
* | | |111 = Time-out interval is 65536 OSC10K clocks (6553.6ms). * | | |111 = Time-out interval is 65536 LIRC clocks (6553.6ms).
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect) * |[17:16] |WKPINEN |Wake-up Pin Enable (Write Protect)
* | | |00 = Wake-up pin disable at Deep Power-down mode. * | | |00 = Wake-up pin Disable in Deep Power-down mode.
* | | |01 = Wake-up pin rising edge enabled at Deep Power-down mode. * | | |01 = Wake-up pin rising edge Enabled in Deep Power-down mode.
* | | |10 = Wake-up pin falling edge enabled at Deep Power-down mode. * | | |10 = Wake-up pin falling edge Enabled in Deep Power-down mode.
* | | |11 = Wake-up pin both edge enabled at Deep Power-down mode. * | | |11 = Wake-up pin both edge Enabled in Deep Power-down mode.
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect) * |[18] |ACMPSPWK |ACMP Standby Power-down Mode Wake-up Enable (Write Protect)
* | | |0 = ACMP wake-up disable at Standby Power-down mode. * | | |0 = ACMP wake-up Disable in Standby Power-down mode.
* | | |1 = ACMP wake-up enabled at Standby Power-down mode. * | | |1 = ACMP wake-up Enabled in Standby Power-down mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect) * |[23] |RTCWKEN |RTC Wake-up Enable (Write Protect)
* | | |This is a protected register. Please refer to open lock sequence to program it. * | | |This is a protected register. Please refer to open lock sequence to program it.
* | | |0 = RTC wake-up disable at Deep Power-down mode or Standby Power-down mode. * | | |0 = RTC wake-up Disable in Deep Power-down mode or Standby Power-down mode.
* | | |1 = RTC wake-up enabled at Deep Power-down mode or Standby Power-down mode. * | | |1 = RTC wake-up Enabled in Deep Power-down mode or Standby Power-down mode.
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* @var CLK_T::PMUSTS * @var CLK_T::PMUSTS
* @var CLK_T::PMUSTS * @var CLK_T::PMUSTS
@ -727,7 +719,7 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |PINWK |Pin Wake-up Flag (Read Only) * |[0] |PINWK |Pin Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the WAKEUP pin (GPC.0). * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) was requested by a transition of the Wake-up pin (GPC.0).
* | | |This flag is cleared when DPD mode is entered. * | | |This flag is cleared when DPD mode is entered.
* |[1] |TMRWK |Timer Wake-up Flag (Read Only) * |[1] |TMRWK |Timer Wake-up Flag (Read Only)
* | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out. * | | |This flag indicates that wake-up of chip from Deep Power-down mode (DPD) or Standby Power-down (SPD) mode was requested by wakeup timer time-out.
@ -748,13 +740,13 @@ typedef struct
* | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins. * | | |This flag indicates that wake-up of chip from Standby Power-down mode (SPD) was requested by a transition of selected one GPD group pins.
* | | |This flag is cleared when SPD mode is entered. * | | |This flag is cleared when SPD mode is entered.
* |[12] |LVRWK |LVR Wake-up Flag (Read Only) * |[12] |LVRWK |LVR Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a LVR happened. * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a LVR happened.
* | | |This flag is cleared when SPD mode is entered. * | | |This flag is cleared when SPD mode is entered.
* |[13] |BODWK |BOD Wake-up Flag (Read Only) * |[13] |BODWK |BOD Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a BOD happened. * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a BOD happened.
* | | |This flag is cleared when SPD mode is entered. * | | |This flag is cleared when SPD mode is entered.
* |[14] |ACMPWK |ACMP Wake-up Flag (Read Only) * |[14] |ACMPWK |ACMP Wake-up Flag (Read Only)
* | | |This flag indicates that wakeup of device from Standby Power-down mode (SPD) was requested with a ACMP transition. * | | |This flag indicates that wake-up of device from Standby Power-down mode (SPD) was requested with a ACMP transition.
* | | |This flag is cleared when SPD mode is entered. * | | |This flag is cleared when SPD mode is entered.
* |[31] |CLRWK |Clear Wake-up Flag * |[31] |CLRWK |Clear Wake-up Flag
* | | |0 = No clear. * | | |0 = No clear.
@ -789,14 +781,14 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPA group pin wake-up function disabled. * | | |0 = GPA group pin wake-up function ddisabled.
* | | |1 = GPA group pin wake-up function enabled. * | | |1 = GPA group pin wake-up function Enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPA group pin rising edge wake-up function disabled. * | | |0 = GPA group pin rising edge wake-up function Disabled.
* | | |1 = GPA group pin rising edge wake-up function enabled. * | | |1 = GPA group pin rising edge wake-up function Enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPA group pin falling edge wake-up function disabled. * | | |0 = GPA group pin falling edge wake-up function Disabled.
* | | |1 = GPA group pin falling edge wake-up function enabled. * | | |1 = GPA group pin falling edge wake-up function Enabled.
* |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select * |[7:4] |WKPSEL |GPA Standby Power-down Wake-up Pin Select
* | | |0000 = GPA.0 wake-up function enabled. * | | |0000 = GPA.0 wake-up function enabled.
* | | |0001 = GPA.1 wake-up function enabled. * | | |0001 = GPA.1 wake-up function enabled.
@ -816,9 +808,10 @@ typedef struct
* | | |1111 = GPA.15 wake-up function enabled. * | | |1111 = GPA.15 wake-up function enabled.
* |[8] |DBEN |GPA Input Signal De-bounce Enable Bit * |[8] |DBEN |GPA Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
* | | |0 = Standby power-down wake-up pin De-bounce function disable. * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* | | |1 = Standby power-down wake-up pin De-bounce function enable. * | | |0 = Standby power-down wake-up pin De-bounce function Disable.
* | | |1 = Standby power-down wake-up pin De-bounce function Enable.
* | | |The de-bounce function is valid only for edge triggered. * | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::PBSWKCTL * @var CLK_T::PBSWKCTL
* Offset: 0xA4 GPB Standby Power-down Wake-up Control Register * Offset: 0xA4 GPB Standby Power-down Wake-up Control Register
@ -826,14 +819,14 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPB group pin wake-up function disabled. * | | |0 = GPB group pin wake-up function Disabled.
* | | |1 = GPB group pin wake-up function enabled. * | | |1 = GPB group pin wake-up function Enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPB group pin rising edge wake-up function disabled. * | | |0 = GPB group pin rising edge wake-up function Disabled.
* | | |1 = GPB group pin rising edge wake-up function enabled. * | | |1 = GPB group pin rising edge wake-up function Enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPB group pin falling edge wake-up function disabled. * | | |0 = GPB group pin falling edge wake-up function Disabled.
* | | |1 = GPB group pin falling edge wake-up function enabled. * | | |1 = GPB group pin falling edge wake-up function Enabled.
* |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select * |[7:4] |WKPSEL |GPB Standby Power-down Wake-up Pin Select
* | | |0000 = GPB.0 wake-up function enabled. * | | |0000 = GPB.0 wake-up function enabled.
* | | |0001 = GPB.1 wake-up function enabled. * | | |0001 = GPB.1 wake-up function enabled.
@ -853,10 +846,10 @@ typedef struct
* | | |1111 = GPB.15 wake-up function enabled. * | | |1111 = GPB.15 wake-up function enabled.
* |[8] |DBEN |GPB Input Signal De-bounce Enable Bit * |[8] |DBEN |GPB Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
* | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* | | |0 = Standby power-down wake-up pin De-bounce function disable. * | | |0 = Standby power-down wake-up pin De-bounce function Disable.
* | | |1 = Standby power-down wake-up pin De-bounce function enable. * | | |1 = Standby power-down wake-up pin De-bounce function Enable.
* | | |The de-bounce function is valid only for edge triggered. * | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::PCSWKCTL * @var CLK_T::PCSWKCTL
* Offset: 0xA8 GPC Standby Power-down Wake-up Control Register * Offset: 0xA8 GPC Standby Power-down Wake-up Control Register
@ -864,14 +857,14 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPC group pin wake-up function disabled. * | | |0 = GPC group pin wake-up function Disabled.
* | | |1 = GPC group pin wake-up function enabled. * | | |1 = GPC group pin wake-up function Enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPC group pin rising edge wake-up function disabled. * | | |0 = GPC group pin rising edge wake-up function Disabled.
* | | |1 = GPC group pin rising edge wake-up function enabled. * | | |1 = GPC group pin rising edge wake-up function Enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPC group pin falling edge wake-up function disabled. * | | |0 = GPC group pin falling edge wake-up function Disabled.
* | | |1 = GPC group pin falling edge wake-up function enabled. * | | |1 = GPC group pin falling edge wake-up function Enabled.
* |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select * |[7:4] |WKPSEL |GPC Standby Power-down Wake-up Pin Select
* | | |0000 = GPC.0 wake-up function enabled. * | | |0000 = GPC.0 wake-up function enabled.
* | | |0001 = GPC.1 wake-up function enabled. * | | |0001 = GPC.1 wake-up function enabled.
@ -891,9 +884,10 @@ typedef struct
* | | |1111 = Reserved. * | | |1111 = Reserved.
* |[8] |DBEN |GPC Input Signal De-bounce Enable Bit * |[8] |DBEN |GPC Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
* | | |0 = Standby power-down wake-up pin De-bounce function disable. * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* | | |1 = Standby power-down wake-up pin De-bounce function enable. * | | |0 = Standby power-down wake-up pin De-bounce function Disable.
* | | |1 = Standby power-down wake-up pin De-bounce function Enable.
* | | |The de-bounce function is valid only for edge triggered. * | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::PDSWKCTL * @var CLK_T::PDSWKCTL
* Offset: 0xAC GPD Standby Power-down Wake-up Control Register * Offset: 0xAC GPD Standby Power-down Wake-up Control Register
@ -901,14 +895,14 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit * |[0] |WKEN |Standby Power-down Pin Wake-up Enable Bit
* | | |0 = GPD group pin wake-up function disabled. * | | |0 = GPD group pin wake-up function Disabled.
* | | |1 = GPD group pin wake-up function enabled. * | | |1 = GPD group pin wake-up function Enabled.
* |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit * |[1] |PRWKEN |Pin Rising Edge Wake-up Enable Bit
* | | |0 = GPD group pin rising edge wake-up function disabled. * | | |0 = GPD group pin rising edge wake-up function Disabled.
* | | |1 = GPD group pin rising edge wake-up function enabled. * | | |1 = GPD group pin rising edge wake-up function Enabled.
* |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit * |[2] |PFWKEN |Pin Falling Edge Wake-up Enable Bit
* | | |0 = GPD group pin falling edge wake-up function disabled. * | | |0 = GPD group pin falling edge wake-up function Disabled.
* | | |1 = GPD group pin falling edge wake-up function enabled. * | | |1 = GPD group pin falling edge wake-up function Enabled.
* |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select * |[7:4] |WKPSEL |GPD Standby Power-down Wake-up Pin Select
* | | |0000 = GPD.0 wake-up function enabled. * | | |0000 = GPD.0 wake-up function enabled.
* | | |0001 = GPD.1 wake-up function enabled. * | | |0001 = GPD.1 wake-up function enabled.
@ -928,9 +922,10 @@ typedef struct
* | | |1111 = Reserved. * | | |1111 = Reserved.
* |[8] |DBEN |GPD Input Signal De-bounce Enable Bit * |[8] |DBEN |GPD Input Signal De-bounce Enable Bit
* | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO. * | | |The DBEN bit is used to enable the de-bounce function for each corresponding IO.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC). * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the wakeup.
* | | |0 = Standby power-down wake-up pin De-bounce function disable. * | | |The de-bounce clock source is the 10 kHz internal low speed RC oscillator (LIRC).
* | | |1 = Standby power-down wake-up pin De-bounce function enable. * | | |0 = Standby power-down wake-up pin De-bounce function Disable.
* | | |1 = Standby power-down wake-up pin De-bounce function Enable.
* | | |The de-bounce function is valid only for edge triggered. * | | |The de-bounce function is valid only for edge triggered.
* @var CLK_T::IOPDCTL * @var CLK_T::IOPDCTL
* Offset: 0xB0 GPIO Standby Power-down Control Register * Offset: 0xB0 GPIO Standby Power-down Control Register
@ -938,8 +933,8 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[0] |IOHR |GPIO Hold Release * |[0] |IOHR |GPIO Hold Release
* | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status * | | |When GPIO enter standby power-down mode, all I/O status are hold to keep normal operating status.
* | | |After chip was waked up from standby power-down mode, the I/O are still keep hold status until user set this bit to release I/O hold status. * | | |After chip was waked up from standby Power-down mode, the I/O still keeps hold status until user sets this bit to release I/O hold status.
* | | |Note: This bit is auto cleared by hardware. * | | |Note: This bit is auto cleared by hardware.
* @var CLK_T::HXTFSEL * @var CLK_T::HXTFSEL
* Offset: 0xB4 HXT Filter Select Control Register * Offset: 0xB4 HXT Filter Select Control Register
@ -1119,9 +1114,6 @@ typedef struct
#define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */ #define CLK_APBCLK0_UART5CKEN_Pos (21) /*!< CLK_T::APBCLK0: UART5CKEN Position */
#define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */ #define CLK_APBCLK0_UART5CKEN_Msk (0x1ul << CLK_APBCLK0_UART5CKEN_Pos) /*!< CLK_T::APBCLK0: UART5CKEN Mask */
#define CLK_APBCLK0_DSRCCKEN_Pos (23) /*!< CLK_T::APBCLK0: DSRCCKEN Position */
#define CLK_APBCLK0_DSRCCKEN_Msk (0x1ul << CLK_APBCLK0_DSRCCKEN_Pos) /*!< CLK_T::APBCLK0: DSRCCKEN Mask */
#define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */ #define CLK_APBCLK0_CAN0CKEN_Pos (24) /*!< CLK_T::APBCLK0: CAN0CKEN Position */
#define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */ #define CLK_APBCLK0_CAN0CKEN_Msk (0x1ul << CLK_APBCLK0_CAN0CKEN_Pos) /*!< CLK_T::APBCLK0: CAN0CKEN Mask */
@ -1152,9 +1144,6 @@ typedef struct
#define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */ #define CLK_APBCLK1_SPI3CKEN_Pos (6) /*!< CLK_T::APBCLK1: SPI3CKEN Position */
#define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */ #define CLK_APBCLK1_SPI3CKEN_Msk (0x1ul << CLK_APBCLK1_SPI3CKEN_Pos) /*!< CLK_T::APBCLK1: SPI3CKEN Mask */
#define CLK_APBCLK1_SPI5CKEN_Pos (7) /*!< CLK_T::APBCLK1: SPI5CKEN Position */
#define CLK_APBCLK1_SPI5CKEN_Msk (0x1ul << CLK_APBCLK1_SPI5CKEN_Pos) /*!< CLK_T::APBCLK1: SPI5CKEN Mask */
#define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */ #define CLK_APBCLK1_USCI0CKEN_Pos (8) /*!< CLK_T::APBCLK1: USCI0CKEN Position */
#define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */ #define CLK_APBCLK1_USCI0CKEN_Msk (0x1ul << CLK_APBCLK1_USCI0CKEN_Pos) /*!< CLK_T::APBCLK1: USCI0CKEN Mask */
@ -1206,9 +1195,6 @@ typedef struct
#define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */ #define CLK_CLKSEL1_WDTSEL_Pos (0) /*!< CLK_T::CLKSEL1: WDTSEL Position */
#define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */ #define CLK_CLKSEL1_WDTSEL_Msk (0x3ul << CLK_CLKSEL1_WDTSEL_Pos) /*!< CLK_T::CLKSEL1: WDTSEL Mask */
#define CLK_CLKSEL1_DSRCSEL_Pos (3) /*!< CLK_T::CLKSEL1: DSRCSEL Position */
#define CLK_CLKSEL1_DSRCSEL_Msk (0x1ul << CLK_CLKSEL1_DSRCSEL_Pos) /*!< CLK_T::CLKSEL1: DSRCSEL Mask */
#define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */ #define CLK_CLKSEL1_TMR0SEL_Pos (8) /*!< CLK_T::CLKSEL1: TMR0SEL Position */
#define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */ #define CLK_CLKSEL1_TMR0SEL_Msk (0x7ul << CLK_CLKSEL1_TMR0SEL_Pos) /*!< CLK_T::CLKSEL1: TMR0SEL Mask */
@ -1260,9 +1246,6 @@ typedef struct
#define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */ #define CLK_CLKSEL2_SPI3SEL_Pos (12) /*!< CLK_T::CLKSEL2: SPI3SEL Position */
#define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */ #define CLK_CLKSEL2_SPI3SEL_Msk (0x3ul << CLK_CLKSEL2_SPI3SEL_Pos) /*!< CLK_T::CLKSEL2: SPI3SEL Mask */
#define CLK_CLKSEL2_SPI5SEL_Pos (14) /*!< CLK_T::CLKSEL2: SPI5SEL Position */
#define CLK_CLKSEL2_SPI5SEL_Msk (0x3ul << CLK_CLKSEL2_SPI5SEL_Pos) /*!< CLK_T::CLKSEL2: SPI5SEL Mask */
#define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */ #define CLK_CLKSEL3_SC0SEL_Pos (0) /*!< CLK_T::CLKSEL3: SC0SEL Position */
#define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */ #define CLK_CLKSEL3_SC0SEL_Msk (0x3ul << CLK_CLKSEL3_SC0SEL_Pos) /*!< CLK_T::CLKSEL3: SC0SEL Mask */
@ -1317,9 +1300,6 @@ typedef struct
#define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */ #define CLK_CLKDIV1_SC2DIV_Pos (16) /*!< CLK_T::CLKDIV1: SC2DIV Position */
#define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */ #define CLK_CLKDIV1_SC2DIV_Msk (0xfful << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLK_T::CLKDIV1: SC2DIV Mask */
#define CLK_CLKDIV1_DSRCDIV_Pos (24) /*!< CLK_T::CLKDIV1: DSRCDIV Position */
#define CLK_CLKDIV1_DSRCDIV_Msk (0xfful << CLK_CLKDIV1_DSRCDIV_Pos) /*!< CLK_T::CLKDIV1: DSRCDIV Mask */
#define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */ #define CLK_CLKDIV4_UART2DIV_Pos (0) /*!< CLK_T::CLKDIV4: UART2DIV Position */
#define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */ #define CLK_CLKDIV4_UART2DIV_Msk (0xful << CLK_CLKDIV4_UART2DIV_Pos) /*!< CLK_T::CLKDIV4: UART2DIV Mask */
@ -1557,5 +1537,6 @@ typedef struct
/**@}*/ /* CLK_CONST */ /**@}*/ /* CLK_CONST */
/**@}*/ /* end of CLK register group */ /**@}*/ /* end of CLK register group */
/**@}*/ /* end of REGISTER group */
#endif /* __CLK_REG_H__ */ #endif /* __CLK_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/crc_reg.h
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@ -8,6 +8,13 @@
#ifndef __CRC_REG_H__ #ifndef __CRC_REG_H__
#define __CRC_REG_H__ #define __CRC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Cyclic Redundancy Check Controller -------------------------*/ /*---------------------- Cyclic Redundancy Check Controller -------------------------*/
/** /**
@addtogroup CRC Cyclic Redundancy Check Controller(CRC) @addtogroup CRC Cyclic Redundancy Check Controller(CRC)
@ -138,5 +145,6 @@ typedef struct
/**@}*/ /* CRC_CONST */ /**@}*/ /* CRC_CONST */
/**@}*/ /* end of CRC register group */ /**@}*/ /* end of CRC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __CLK_REG_H__ */ #endif /* __CLK_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/crpt_reg.h
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@ -9,6 +9,11 @@
#define __CRPT_REG_H__ #define __CRPT_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Cryptographic Accelerator -------------------------*/ /*---------------------- Cryptographic Accelerator -------------------------*/
@ -2177,6 +2182,7 @@ typedef struct
/**@}*/ /* CRPT_CONST */ /**@}*/ /* CRPT_CONST */
/**@}*/ /* end of CRPT register group */ /**@}*/ /* end of CRPT register group */
/**@}*/ /* end of REGISTER group */
#endif /* __CRPT_REG_H__ */ #endif /* __CRPT_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/dac_reg.h
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@ -8,6 +8,13 @@
#ifndef __DAC_REG_H__ #ifndef __DAC_REG_H__
#define __DAC_REG_H__ #define __DAC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Digital to Analog Converter -------------------------*/ /*---------------------- Digital to Analog Converter -------------------------*/
/** /**
@addtogroup DAC Digital to Analog Converter(DAC) @addtogroup DAC Digital to Analog Converter(DAC)
@ -193,5 +200,6 @@ typedef struct
/**@}*/ /* DAC_CONST */ /**@}*/ /* DAC_CONST */
/**@}*/ /* end of DAC register group */ /**@}*/ /* end of DAC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __DAC_REG_H__ */ #endif /* __DAC_REG_H__ */

7
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/eadc_reg.h
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@ -8,6 +8,12 @@
#ifndef __EADC_REG_H__ #ifndef __EADC_REG_H__
#define __EADC_REG_H__ #define __EADC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Enhanced Analog to Digital Converter -------------------------*/ /*---------------------- Enhanced Analog to Digital Converter -------------------------*/
/** /**
@addtogroup EADC Enhanced Analog to Digital Converter(EADC) @addtogroup EADC Enhanced Analog to Digital Converter(EADC)
@ -1691,6 +1697,7 @@ typedef struct
/**@}*/ /* EADC_CONST */ /**@}*/ /* EADC_CONST */
/**@}*/ /* end of EADC register group */ /**@}*/ /* end of EADC register group */
/**@}*/ /* end of REGISTER group */

63
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/ebi_reg.h
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@ -8,6 +8,12 @@
#ifndef __EBI_REG_H__ #ifndef __EBI_REG_H__
#define __EBI_REG_H__ #define __EBI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- External Bus Interface Controller -------------------------*/ /*---------------------- External Bus Interface Controller -------------------------*/
/** /**
@ -20,7 +26,7 @@ typedef struct
/** /**
* @var EBI_T::CTL * @var EBI_T::CTL0
* Offset: 0x00 External Bus Interface Control Register * Offset: 0x00 External Bus Interface Control Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -58,7 +64,7 @@ typedef struct
* | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE. * | | |The EBI_ALE high pulse period (tALE) to latch the address can be controlled by TALE.
* | | |tALE = (TALE+1)*EBI_MCLK. * | | |tALE = (TALE+1)*EBI_MCLK.
* | | |Note: This field only available in EBI_CTL0 register * | | |Note: This field only available in EBI_CTL0 register
* @var EBI_T::TCTL * @var EBI_T::TCTL0
* Offset: 0x04 External Bus Interface Timing Control Register * Offset: 0x04 External Bus Interface Timing Control Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -100,47 +106,48 @@ typedef struct
Constant Definitions for EBI Controller Constant Definitions for EBI Controller
@{ */ @{ */
#define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL: EN Position */ #define EBI_CTL_EN_Pos (0) /*!< EBI_T::CTL0: EN Position */
#define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL: EN Mask */ #define EBI_CTL_EN_Msk (0x1ul << EBI_CTL_EN_Pos) /*!< EBI_T::CTL0: EN Mask */
#define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL: DW16 Position */ #define EBI_CTL_DW16_Pos (1) /*!< EBI_T::CTL0: DW16 Position */
#define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL: DW16 Mask */ #define EBI_CTL_DW16_Msk (0x1ul << EBI_CTL_DW16_Pos) /*!< EBI_T::CTL0: DW16 Mask */
#define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL: CSPOLINV Position */ #define EBI_CTL_CSPOLINV_Pos (2) /*!< EBI_T::CTL0: CSPOLINV Position */
#define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL: CSPOLINV Mask */ #define EBI_CTL_CSPOLINV_Msk (0x1ul << EBI_CTL_CSPOLINV_Pos) /*!< EBI_T::CTL0: CSPOLINV Mask */
#define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL: ADSEPEN Position */ #define EBI_CTL_ADSEPEN_Pos (3) /*!< EBI_T::CTL0: ADSEPEN Position */
#define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL: ADSEPEN Mask */ #define EBI_CTL_ADSEPEN_Msk (0x1ul << EBI_CTL_ADSEPEN_Pos) /*!< EBI_T::CTL0: ADSEPEN Mask */
#define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL: CACCESS Position */ #define EBI_CTL_CACCESS_Pos (4) /*!< EBI_T::CTL0: CACCESS Position */
#define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL: CACCESS Mask */ #define EBI_CTL_CACCESS_Msk (0x1ul << EBI_CTL_CACCESS_Pos) /*!< EBI_T::CTL0: CACCESS Mask */
#define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL: MCLKDIV Position */ #define EBI_CTL_MCLKDIV_Pos (8) /*!< EBI_T::CTL0: MCLKDIV Position */
#define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL: MCLKDIV Mask */ #define EBI_CTL_MCLKDIV_Msk (0x7ul << EBI_CTL_MCLKDIV_Pos) /*!< EBI_T::CTL0: MCLKDIV Mask */
#define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL: TALE Position */ #define EBI_CTL_TALE_Pos (16) /*!< EBI_T::CTL0: TALE Position */
#define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL: TALE Mask */ #define EBI_CTL_TALE_Msk (0x7ul << EBI_CTL_TALE_Pos) /*!< EBI_T::CTL0: TALE Mask */
#define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL: TACC Position */ #define EBI_TCTL_TACC_Pos (3) /*!< EBI_T::TCTL0: TACC Position */
#define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL: TACC Mask */ #define EBI_TCTL_TACC_Msk (0x1ful << EBI_TCTL_TACC_Pos) /*!< EBI_T::TCTL0: TACC Mask */
#define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL: TAHD Position */ #define EBI_TCTL_TAHD_Pos (8) /*!< EBI_T::TCTL0: TAHD Position */
#define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL: TAHD Mask */ #define EBI_TCTL_TAHD_Msk (0x7ul << EBI_TCTL_TAHD_Pos) /*!< EBI_T::TCTL0: TAHD Mask */
#define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL: W2X Position */ #define EBI_TCTL_W2X_Pos (12) /*!< EBI_T::TCTL0: W2X Position */
#define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL: W2X Mask */ #define EBI_TCTL_W2X_Msk (0xful << EBI_TCTL_W2X_Pos) /*!< EBI_T::TCTL0: W2X Mask */
#define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL: RAHDOFF Position */ #define EBI_TCTL_RAHDOFF_Pos (22) /*!< EBI_T::TCTL0: RAHDOFF Position */
#define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL: RAHDOFF Mask */ #define EBI_TCTL_RAHDOFF_Msk (0x1ul << EBI_TCTL_RAHDOFF_Pos) /*!< EBI_T::TCTL0: RAHDOFF Mask */
#define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL: WAHDOFF Position */ #define EBI_TCTL_WAHDOFF_Pos (23) /*!< EBI_T::TCTL0: WAHDOFF Position */
#define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL: WAHDOFF Mask */ #define EBI_TCTL_WAHDOFF_Msk (0x1ul << EBI_TCTL_WAHDOFF_Pos) /*!< EBI_T::TCTL0: WAHDOFF Mask */
#define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL: R2R Position */ #define EBI_TCTL_R2R_Pos (24) /*!< EBI_T::TCTL0: R2R Position */
#define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL: R2R Mask */ #define EBI_TCTL_R2R_Msk (0xful << EBI_TCTL_R2R_Pos) /*!< EBI_T::TCTL0: R2R Mask */
/**@}*/ /* EBI_CONST */ /**@}*/ /* EBI_CONST */
/**@}*/ /* end of EBI register group */ /**@}*/ /* end of EBI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __EBI_REG_H__ */ #endif /* __EBI_REG_H__ */

7
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/ecap_reg.h
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@ -8,6 +8,12 @@
#ifndef __ECAP_REG_H__ #ifndef __ECAP_REG_H__
#define __ECAP_REG_H__ #define __ECAP_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Enhanced Input Capture Timer -------------------------*/ /*---------------------- Enhanced Input Capture Timer -------------------------*/
/** /**
@addtogroup ECAP Enhanced Input Capture Timer(ECAP) @addtogroup ECAP Enhanced Input Capture Timer(ECAP)
@ -372,6 +378,7 @@ typedef struct
/**@}*/ /* ECAP_CONST */ /**@}*/ /* ECAP_CONST */
/**@}*/ /* end of ECAP register group */ /**@}*/ /* end of ECAP register group */
/**@}*/ /* end of REGISTER group */
#endif /* __ECAP_REG_H__ */ #endif /* __ECAP_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/epwm_reg.h
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@ -8,6 +8,11 @@
#ifndef __EPWM_REG_H__ #ifndef __EPWM_REG_H__
#define __EPWM_REG_H__ #define __EPWM_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/ /*---------------------- Enhanced Pulse Width Modulation Controller -------------------------*/
@ -3720,6 +3725,7 @@ typedef struct
/**@}*/ /* EPWM_CONST */ /**@}*/ /* EPWM_CONST */
/**@}*/ /* end of EPWM register group */ /**@}*/ /* end of EPWM register group */
/**@}*/ /* end of REGISTER group */

34
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/fmc_reg.h
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@ -8,6 +8,13 @@
#ifndef __FMC_REG_H__ #ifndef __FMC_REG_H__
#define __FMC_REG_H__ #define __FMC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Flash Memory Controller -------------------------*/ /*---------------------- Flash Memory Controller -------------------------*/
/** /**
@addtogroup FMC Flash Memory Controller(FMC) @addtogroup FMC Flash Memory Controller(FMC)
@ -212,25 +219,13 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect) * |[3:0] |CYCLE |Flash Access Cycle Control (Write Protect)
* | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1) * | | |This register is updated automatically by hardware while FCYCDIS (FMC_ISPSTS[4]) is 0, and updated by software while auto-tuning function disabled ( FADIS (FMC_CYCTL[8]) is 1).
* | | |0000 = CPU access with zero wait cycle ; flash access cycle is 1;. * | | |When auto-tuning function disabled, user needs to check the speed of HCLK and set the cycle >0.
* | | |The HCLK working frequency range is <27MHz; Cache is disabled by hardware. * | | |0000 = CPU access with zero wait cycle ; Flash access cycle is 1. The HCLK working frequency range is <27MHz; Cache is disabled by hardware.
* | | |0001 = CPU access with one wait cycle if cache miss; flash access cycle is 1;. * | | |0001 = CPU access with one wait cycle if cache miss; Flash access cycle is 1. The HCLK working frequency range range is<27MHz.
* | | |The HCLK working frequency range range is<27MHz * | | |0010 = CPU access with two wait cycles if cache miss; Flash access cycle is 2. The optimized HCLK working frequency range is 25~52 MHz.
* | | |0010 = CPU access with two wait cycles if cache miss; flash access cycle is 2;. * | | |0011 = CPU access with three wait cycles if cache miss; Flash access cycle is 3. The optimized HCLK working frequency range is 49~79MHz.
* | | | The optimized HCLK working frequency range is 27~54 MHz * | | |Others = Reserved.
* | | |0011 = CPU access with three wait cycles if cache miss; flash access cycle is 3;.
* | | |The optimized HCLK working frequency range is 54~81MHz
* | | |0100 = CPU access with four wait cycles if cache miss; flash access cycle is 4;.
* | | | The optimized HCLK working frequency range is81~108MHz
* | | |0101 = CPU access with five wait cycles if cache miss; flash access cycle is 5;.
* | | |The optimized HCLK working frequency range is 108~135MHz
* | | |0110 = CPU access with six wait cycles if cache miss; flash access cycle is 6;.
* | | | The optimized HCLK working frequency range is 135~162MHz
* | | |0111 = CPU access with seven wait cycles if cache miss; flash access cycle is 7;.
* | | | The optimized HCLK working frequency range is 162~192MHz
* | | |1000 = CPU access with eight wait cycles if cache miss; flash access cycle is 8;.
* | | |The optimized HCLK working frequency range is >192MHz
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect) * |[8] |FADIS |Flash Access Cycle Auto-tuning Disabled Control (Write Protect)
* | | |Set this bit to disable flash access cycle auto-tuning function * | | |Set this bit to disable flash access cycle auto-tuning function
@ -728,5 +723,6 @@ typedef struct
/**@}*/ /* FMC_CONST */ /**@}*/ /* FMC_CONST */
/**@}*/ /* end of FMC register group */ /**@}*/ /* end of FMC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __FMC_REG_H__ */ #endif /* __FMC_REG_H__ */

44
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/gpio_reg.h
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@ -8,6 +8,11 @@
#ifndef __GPIO_REG_H__ #ifndef __GPIO_REG_H__
#define __GPIO_REG_H__ #define __GPIO_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- General Purpose Input/Output Controller -------------------------*/ /*---------------------- General Purpose Input/Output Controller -------------------------*/
/** /**
@ -80,8 +85,8 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask * |[n] |DATMSKn |Port A-H Pin[n] Data Output Write Mask
* | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit * | | |These bits are used to protect the corresponding DOUT (Px_DOUT[n]) bit.
* | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected * | | |When the DATMSK (Px_DATMSK[n]) bit is set to 1, the corresponding DOUT (Px_DOUT[n]) bit is protected.
* | | |If the write signal is masked, writing data to the protect bit is ignored. * | | |If the write signal is masked, writing data to the protect bit is ignored.
* | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated. * | | |0 = Corresponding DOUT (Px_DOUT[n]) bit can be updated.
* | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected. * | | |1 = Corresponding DOUT (Px_DOUT[n]) bit protected.
@ -99,7 +104,7 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[n] |PINn |Port A-H Pin[n] Pin Value * |[n] |PINn |Port A-H Pin[n] Pin Value
* | | |Each bit of the register reflects the actual status of the respective Px.n pin * | | |Each bit of the register reflects the actual status of the respective Px.n pin.
* | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low. * | | |If the bit is 1, it indicates the corresponding pin status is high; else the pin status is low.
* | | |Note: * | | |Note:
* | | |Max. n=15 for port A/B/E. * | | |Max. n=15 for port A/B/E.
@ -114,12 +119,12 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit * |[n] |DBENn |Port A-H Pin[n] Input Signal De-bounce Enable Bit
* | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit * | | |The DBEN[n] bit is used to enable the de-bounce function for each corresponding bit.
* | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt * | | |If the input signal pulse width cannot be sampled by continuous two de-bounce sample cycle, the input signal transition is seen as the signal bounce and will not trigger the interrupt.
* | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]). * | | |The de-bounce clock source is controlled by DBCLKSRC (Px_DBCTL [4]), one de-bounce sample cycle period is controlled by DBCLKSEL (Px_DBCTL [3:0]).
* | | |0 = Px.n de-bounce function Disabled. * | | |0 = Px.n de-bounce function Disabled.
* | | |1 = Px.n de-bounce function Enabled. * | | |1 = Px.n de-bounce function Enabled.
* | | |The de-bounce function is valid only for edge triggered interrupt * | | |The de-bounce function is valid only for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: * | | |Note:
* | | |Max. n=15 for port A/B/E. * | | |Max. n=15 for port A/B/E.
@ -134,14 +139,14 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control * |[n] |TYPEn |Port A-H Pin[n] Edge or Level Detection Interrupt Trigger Type Control
* | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger * | | |TYPE (Px_INTTYPE[n]) bit is used to control the triggered interrupt is by level trigger or by edge trigger.
* | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce * | | |If the interrupt is by edge trigger, the trigger source can be controlled by de-bounce.
* | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt. * | | |If the interrupt is by level trigger, the input source is sampled by one HCLK clock and generates the interrupt.
* | | |0 = Edge trigger interrupt. * | | |0 = Edge trigger interrupt.
* | | |1 = Level trigger interrupt. * | | |1 = Level trigger interrupt.
* | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]) * | | |If the pin is set as the level trigger interrupt, only one level can be set on the registers RHIEN (Px_INTEN[n+16])/FLIEN (Px_INTEN[n]).
* | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur. * | | |If both levels to trigger interrupt are set, the setting is ignored and no interrupt will occur.
* | | |The de-bounce function is valid only for edge triggered interrupt * | | |The de-bounce function is valid only for edge triggered interrupt.
* | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored. * | | |If the interrupt mode is level triggered, the de-bounce enable bit is ignored.
* | | |Note: * | | |Note:
* | | |Max. n=15 for port A/B/E. * | | |Max. n=15 for port A/B/E.
@ -156,7 +161,7 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit * |[n] |FLIENn |Port A-H Pin[n] Falling Edge or Low Level Interrupt Trigger Type Enable Bit
* | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin * | | |The FLIEN (Px_INTEN[n]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function. * | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 : * | | |When setting the FLIEN (Px_INTEN[n]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level. * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at low level.
@ -170,8 +175,8 @@ typedef struct
* | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored. * | | |Max. n=12 for port F. The PF.12/ PF.13/ PF.14/ PF.15 is ignored.
* | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored. * | | |Max. n=15 for port G. The PG.0/ PG.1/ PG.5/ PG.6/ PG.7/ PG.8 is ignored.
* | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored. * | | |Max. n=11 for port H. The PH.0/ PH.1/ PH.2/ PH.3/ PH.12/ PH.13/ PH.14/ PH.15 is ignored.
* |[n+16] |RHIENn |Port A-G Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit * |[n+16] |RHIENn |Port A-H Pin[n] Rising Edge or High Level Interrupt Trigger Type Enable Bit
* | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin * | | |The RHIEN (Px_INTEN[n+16]) bit is used to enable the interrupt for each of the corresponding input Px.n pin.
* | | |Set bit to 1 also enable the pin wake-up function. * | | |Set bit to 1 also enable the pin wake-up function.
* | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 : * | | |When setting the RHIEN (Px_INTEN[n+16]) bit to 1 :
* | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level. * | | |If the interrupt is level trigger (TYPE (Px_INTTYPE[n]) bit is set to 1), the input Px.n pin will generate the interrupt while this pin state is at high level.
@ -241,18 +246,18 @@ typedef struct
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[2n+1:2n]|PUSEL0 |Port A-H Pin[n] Pull-up and Pull-down Enable Register * |[2n+1:2n]|PUSELn |Port A-H Pin[n] Pull-up and Pull-down Enable Register
* | | |Determine each I/O Pull-up/pull-down of Px.n pins. * | | |Determine each I/O Pull-up/pull-down of Px.n pins.
* | | |00 = Px.n pull-up and pull-down disable. * | | |00 = Px.n pull-up and pull-down disable.
* | | |01 = Px.n pull-up enable. * | | |01 = Px.n pull-up enable.
* | | |10 = Px.n pull-down enable. * | | |10 = Px.n pull-down enable.
* | | |11 = Px.n pull-up and pull-down disable. * | | |11 = Px.n pull-up and pull-down disable.
* | | |Note1: * | | |Note1:
* | | |Basically, the pull-up control and pull-down control has following behavior limitation * | | |Basically, the pull-up control and pull-down control has following behavior limitation.
* | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode * | | |The independent pull-up control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state and open-drain mode.
* | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode * | | |The independent pull-down control register only valid when MODEn (Px_MODE[2n+1:2n]) set as tri-state mode.
* | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode * | | |When both pull-up pull-down is set as 1 at tri-state mode, keep I/O in tri-state mode.
* | | |Note: * | | |Note:2
* | | |Max. n=15 for port A/B/E. * | | |Max. n=15 for port A/B/E.
* | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored. * | | |Max. n=13 for port C. The PC.14/ PC.15 is ignored.
* | | |Max. n=14 for port D. The PD.15 is ignored. * | | |Max. n=14 for port D. The PD.15 is ignored.
@ -951,6 +956,7 @@ typedef struct
/**@}*/ /* GPIO_CONST */ /**@}*/ /* GPIO_CONST */
/**@}*/ /* end of GPIO register group */ /**@}*/ /* end of GPIO register group */
/**@}*/ /* end of REGISTER group */
#endif /* __GPIO_REG_H__ */ #endif /* __GPIO_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/hdiv_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __HDIV_REG_H__ #ifndef __HDIV_REG_H__
#define __HDIV_REG_H__ #define __HDIV_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Hardware Divider --------------------------------*/ /*---------------------- Hardware Divider --------------------------------*/
/** /**
@ -100,6 +105,7 @@ typedef struct
/**@}*/ /* HDIV_CONST */ /**@}*/ /* HDIV_CONST */
/**@}*/ /* end of HDIV register group */ /**@}*/ /* end of HDIV register group */
/**@}*/ /* end of REGISTER group */
#endif /* __HDIV_REG_H__ */ #endif /* __HDIV_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/i2c_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __I2C_REG_H__ #ifndef __I2C_REG_H__
#define __I2C_REG_H__ #define __I2C_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Inter-IC Bus Controller -------------------------*/ /*---------------------- Inter-IC Bus Controller -------------------------*/
/** /**
@ -703,6 +708,7 @@ typedef struct
/**@}*/ /* I2C_CONST */ /**@}*/ /* I2C_CONST */
/**@}*/ /* end of I2C register group */ /**@}*/ /* end of I2C register group */
/**@}*/ /* end of REGISTER group */
#endif /* __I2C_REG_H__ */ #endif /* __I2C_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/i2s_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __I2S_REG_H__ #ifndef __I2S_REG_H__
#define __I2S_REG_H__ #define __I2S_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- I2S Interface Controller -------------------------*/ /*---------------------- I2S Interface Controller -------------------------*/
/** /**
@ -688,6 +693,7 @@ typedef struct
/**@}*/ /* I2S_CONST */ /**@}*/ /* I2S_CONST */
/**@}*/ /* end of I2S register group */ /**@}*/ /* end of I2S register group */
/**@}*/ /* end of REGISTER group */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/otg_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __OTG_REG_H__ #ifndef __OTG_REG_H__
#define __OTG_REG_H__ #define __OTG_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- USB On-The-Go Controller -------------------------*/ /*---------------------- USB On-The-Go Controller -------------------------*/
@ -382,6 +387,7 @@ typedef struct
/**@}*/ /* OTG_CONST */ /**@}*/ /* OTG_CONST */
/**@}*/ /* end of OTG register group */ /**@}*/ /* end of OTG register group */
/**@}*/ /* end of REGISTER group */

14
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/pdma_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __PDMA_REG_H__ #ifndef __PDMA_REG_H__
#define __PDMA_REG_H__ #define __PDMA_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Peripheral Direct Memory Access Controller -------------------------*/ /*---------------------- Peripheral Direct Memory Access Controller -------------------------*/
/** /**
@ -94,7 +99,7 @@ typedef struct
* |[31:0] |DA |PDMA Transfer Destination Address Register * |[31:0] |DA |PDMA Transfer Destination Address Register
* | | |This field indicates a 32-bit destination address of PDMA controller. * | | |This field indicates a 32-bit destination address of PDMA controller.
* | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection. * | | |Note: The PDMA transfer destination address should be aligned with the TXWIDTH(PDMA_DSCTn_CTL[13:12], n=0,1..7) selection.
* @var DSCT_T::FIRST * @var DSCT_T::NEXT
* Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7 * Offset: 0x0C/0x1C/0x2C/0x3C/0x4C/0x5C/0x6C/0x7C First Scatter-Gather Descriptor Table Offset of PDMA Channel 0~7
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -360,7 +365,7 @@ typedef struct
* | | |This controls the period of time-out function for channel 1 * | | |This controls the period of time-out function for channel 1
* | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock * | | |The calculation unit is based on TOUTPSC1 (PDMA_TOUTPSC[5:3]) clock
* | | |The example of time-out period can refer TOC0 bit description. * | | |The example of time-out period can refer TOC0 bit description.
* @var PDMA_T::RESET * @var PDMA_T::CHRST
* Offset: 0x460 PDMA Channel Reset Control Register * Offset: 0x460 PDMA Channel Reset Control Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -406,8 +411,6 @@ typedef struct
* | | |27 = Channel connects to SPI2_RX. * | | |27 = Channel connects to SPI2_RX.
* | | |28 = Channel connects to SPI3_TX. * | | |28 = Channel connects to SPI3_TX.
* | | |29 = Channel connects to SPI3_RX. * | | |29 = Channel connects to SPI3_RX.
* | | |30 = Channel connects to SPI5_TX.
* | | |31 = Channel connects to SPI5_RX.
* | | |32 = Channel connects to EPWM0_P1_RX. * | | |32 = Channel connects to EPWM0_P1_RX.
* | | |33 = Channel connects to EPWM0_P2_RX. * | | |33 = Channel connects to EPWM0_P2_RX.
* | | |34 = Channel connects to EPWM0_P3_RX. * | | |34 = Channel connects to EPWM0_P3_RX.
@ -766,8 +769,7 @@ typedef struct
/**@}*/ /* PDMA_CONST */ /**@}*/ /* PDMA_CONST */
/**@}*/ /* end of PDMA register group */ /**@}*/ /* end of PDMA register group */
/**@}*/ /* end of REGISTER group */
#endif /* __PDMA_REG_H__ */ #endif /* __PDMA_REG_H__ */

7
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/qei_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __QEI_REG_H__ #ifndef __QEI_REG_H__
#define __QEI_REG_H__ #define __QEI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Quadrature Encoder Interface -------------------------*/ /*---------------------- Quadrature Encoder Interface -------------------------*/
/** /**
@ -294,7 +299,7 @@ typedef struct
/**@}*/ /* QEI_CONST */ /**@}*/ /* QEI_CONST */
/**@}*/ /* end of QEI register group */ /**@}*/ /* end of QEI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __QEI_REG_H__ */ #endif /* __QEI_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/qspi_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __QSPI_REG_H__ #ifndef __QSPI_REG_H__
#define __QSPI_REG_H__ #define __QSPI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/ /*---------------------- Quad Serial Peripheral Interface Controller -------------------------*/
/** /**
@addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI) @addtogroup QSPI Quad Serial Peripheral Interface Controller(QSPI)
@ -574,6 +580,6 @@ typedef struct
/**@}*/ /* QSPI_CONST */ /**@}*/ /* QSPI_CONST */
/**@}*/ /* end of QSPI register group */ /**@}*/ /* end of QSPI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __QSPI_REG_H__ */ #endif /* __QSPI_REG_H__ */

9
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/rtc_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __RTC_REG_H__ #ifndef __RTC_REG_H__
#define __RTC_REG_H__ #define __RTC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Real Time Clock Controller -------------------------*/ /*---------------------- Real Time Clock Controller -------------------------*/
/** /**
@addtogroup RTC Real Time Clock Controller(RTC) @addtogroup RTC Real Time Clock Controller(RTC)
@ -1314,7 +1320,6 @@ typedef struct
/**@}*/ /* RTC_CONST */ /**@}*/ /* RTC_CONST */
/**@}*/ /* end of RTC register group */ /**@}*/ /* end of RTC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __RTC_REG_H__ */ #endif /* __RTC_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/sc_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __SC_REG_H__ #ifndef __SC_REG_H__
#define __SC_REG_H__ #define __SC_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Smart Card Host Interface Controller -------------------------*/ /*---------------------- Smart Card Host Interface Controller -------------------------*/
/** /**
@ -967,7 +972,6 @@ typedef struct
/**@}*/ /* SC_CONST */ /**@}*/ /* SC_CONST */
/**@}*/ /* end of SC register group */ /**@}*/ /* end of SC register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SC_REG_H__ */ #endif /* __SC_REG_H__ */

27
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/scu_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __SCU_REG_H__ #ifndef __SCU_REG_H__
#define __SCU_REG_H__ #define __SCU_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Secure configuration Unit -------------------------*/ /*---------------------- Secure configuration Unit -------------------------*/
@ -21,7 +26,7 @@ typedef struct
/** /**
* @var SCU_T::PNSSET0 * @var SCU_T::PNSSET[0]
* Offset: 0x00 Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF) * Offset: 0x00 Peripheral Non-secure Attribution Set Register0 (0x4000_0000~0x4001_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -42,7 +47,7 @@ typedef struct
* | | |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect. * | | |Write 1 to set PDMA1 to non-secure state. Write 0 has no effect.
* | | |0 = PDMA1 is a secure module (default). * | | |0 = PDMA1 is a secure module (default).
* | | |1 = PDMA1 is a non-secure module. * | | |1 = PDMA1 is a non-secure module.
* @var SCU_T::PNSSET1 * @var SCU_T::PNSSET[1]
* Offset: 0x04 Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF) * Offset: 0x04 Peripheral Non-secure Attribution Set Register1 (0x4002_0000~0x4003_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -55,7 +60,7 @@ typedef struct
* | | |Write 1 to set CRPT to non-secure state. Write 0 has no effect. * | | |Write 1 to set CRPT to non-secure state. Write 0 has no effect.
* | | |0 = CRPT is a secure module (default). * | | |0 = CRPT is a secure module (default).
* | | |1 = CRPT is a non-secure module. * | | |1 = CRPT is a non-secure module.
* @var SCU_T::PNSSET2 * @var SCU_T::PNSSET[2]
* Offset: 0x08 Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF) * Offset: 0x08 Peripheral Non-secure Attribution Set Register2 (0x4004_0000~0x4005_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -104,7 +109,7 @@ typedef struct
* | | |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect. * | | |Write 1 to set BPWM1 to non-secure state. Write 0 has no effect.
* | | |0 = BPWM1 is a secure module (default). * | | |0 = BPWM1 is a secure module (default).
* | | |1 = BPWM1 is a non-secure module. * | | |1 = BPWM1 is a non-secure module.
* @var SCU_T::PNSSET3 * @var SCU_T::PNSSET[3]
* Offset: 0x0C Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF) * Offset: 0x0C Peripheral Non-secure Attribution Set Register3 (0x4006_0000~0x4007_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -153,7 +158,7 @@ typedef struct
* | | |Write 1 to set UART5 to non-secure state. Write 0 has no effect. * | | |Write 1 to set UART5 to non-secure state. Write 0 has no effect.
* | | |0 = UART5 is a secure module (default). * | | |0 = UART5 is a secure module (default).
* | | |1 = UART5 is a non-secure module. * | | |1 = UART5 is a non-secure module.
* @var SCU_T::PNSSET4 * @var SCU_T::PNSSET[4]
* Offset: 0x10 Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF) * Offset: 0x10 Peripheral Non-secure Attribution Set Register4 (0x4008_0000~0x4009_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -182,7 +187,7 @@ typedef struct
* | | |Write 1 to set SC2 to non-secure state. Write 0 has no effect. * | | |Write 1 to set SC2 to non-secure state. Write 0 has no effect.
* | | |0 = SC2 is a secure module (default). * | | |0 = SC2 is a secure module (default).
* | | |1 = SC2 is a non-secure module. * | | |1 = SC2 is a non-secure module.
* @var SCU_T::PNSSET5 * @var SCU_T::PNSSET[5]
* Offset: 0x14 Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF) * Offset: 0x14 Peripheral Non-secure Attribution Set Register5 (0x400A_0000~0x400B_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -207,15 +212,11 @@ typedef struct
* | | |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect. * | | |Write 1 to set ECAP1 to non-secure state. Write 0 has no effect.
* | | |0 = ECAP1 is a secure module (default). * | | |0 = ECAP1 is a secure module (default).
* | | |1 = ECAP1 is a non-secure module. * | | |1 = ECAP1 is a non-secure module.
* |[23] |DSRC |Set DSRC to Non-secure State
* | | |Write 1 to set DSRC to non-secure state. Write 0 has no effect.
* | | |0 = DSRC is a secure module (default).
* | | |1 = DSRC is a non-secure module.
* |[25] |TRNG |Set TRNG to Non-secure State * |[25] |TRNG |Set TRNG to Non-secure State
* | | |Write 1 to set TRNG to non-secure state. Write 0 has no effect. * | | |Write 1 to set TRNG to non-secure state. Write 0 has no effect.
* | | |0 = TRNG is a secure module (default). * | | |0 = TRNG is a secure module (default).
* | | |1 = TRNG is a non-secure module. * | | |1 = TRNG is a non-secure module.
* @var SCU_T::PNSSET6 * @var SCU_T::PNSSET[6]
* Offset: 0x18 Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF) * Offset: 0x18 Peripheral Non-secure Attribution Set Register6 (0x400C_0000~0x400D_FFFF)
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -972,9 +973,6 @@ typedef struct
#define SCU_PNSSET5_ECAP1_Pos (21) /*!< SCU_T::PNSSET5: ECAP1 Position */ #define SCU_PNSSET5_ECAP1_Pos (21) /*!< SCU_T::PNSSET5: ECAP1 Position */
#define SCU_PNSSET5_ECAP1_Msk (0x1ul << SCU_PNSSET5_ECAP1_Pos) /*!< SCU_T::PNSSET5: ECAP1 Mask */ #define SCU_PNSSET5_ECAP1_Msk (0x1ul << SCU_PNSSET5_ECAP1_Pos) /*!< SCU_T::PNSSET5: ECAP1 Mask */
#define SCU_PNSSET5_DSRC_Pos (23) /*!< SCU_T::PNSSET5: DSRC Position */
#define SCU_PNSSET5_DSRC_Msk (0x1ul << SCU_PNSSET5_DSRC_Pos) /*!< SCU_T::PNSSET5: DSRC Mask */
#define SCU_PNSSET5_TRNG_Pos (25) /*!< SCU_T::PNSSET5: TRNG Position */ #define SCU_PNSSET5_TRNG_Pos (25) /*!< SCU_T::PNSSET5: TRNG Position */
#define SCU_PNSSET5_TRNG_Msk (0x1ul << SCU_PNSSET5_TRNG_Pos) /*!< SCU_T::PNSSET5: TRNG Mask */ #define SCU_PNSSET5_TRNG_Msk (0x1ul << SCU_PNSSET5_TRNG_Pos) /*!< SCU_T::PNSSET5: TRNG Mask */
@ -1241,6 +1239,7 @@ typedef struct
/**@}*/ /* SCU_CONST */ /**@}*/ /* SCU_CONST */
/**@}*/ /* end of SCU register group */ /**@}*/ /* end of SCU register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SCU_REG_H__ */ #endif /* __SCU_REG_H__ */

7
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/sdh_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __SDH_REG_H__ #ifndef __SDH_REG_H__
#define __SDH_REG_H__ #define __SDH_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- SD Card Host Interface -------------------------*/ /*---------------------- SD Card Host Interface -------------------------*/
/** /**
@addtogroup SDH SD Card Host Interface(SDH) @addtogroup SDH SD Card Host Interface(SDH)
@ -513,6 +519,7 @@ typedef struct
/**@}*/ /* SDH_CONST */ /**@}*/ /* SDH_CONST */
/**@}*/ /* end of SDH register group */ /**@}*/ /* end of SDH register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SDH_REG_H__ */ #endif /* __SDH_REG_H__ */

523
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/spi5_reg.h
View File

@ -1,523 +0,0 @@
/**************************************************************************//**
* @file spi5_reg.h
* @version V1.00
* @brief SPI5 register definition header file
*
* @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI5_REG_H__
#define __SPI5_REG_H__
/*---------------------- DSRC Serial Peripheral Interface Controller -------------------------*/
/**
@addtogroup SPI5 DSRC Serial Peripheral Interface Controller(SPI5)
Memory Mapped Structure for SPI5 Controller
@{ */
typedef struct
{
/**
* @var SPI5_T::CTL
* Offset: 0x00 SPI Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |GOBUSY |SPI Transfer Control Bit and Busy Status
* | | |0 = Writing this bit 0 will stop data transfer if SPI is transferring.
* | | |1 = In Master mode, writing 1 to this bit will start the SPI data transfer; In Slave mode, writing u20181' to this bit indicates that the slave is ready to communicate with a master.
* | | |If the FIFO mode is disabled, during the data transfer, this bit keeps the value of u20181'
* | | |As the transfer is finished, this bit will be cleared automatically
* | | |Software can read this bit to check if the SPI is in busy status.
* | | |In FIFO mode, this bit will be controlled by hardware
* | | |Software should not modify this bit
* | | |In slave mode, this bit always returns 1 when software reads this register
* | | |In master mode, this bit reflects the busy or idle status of SPI.
* | | |Note:
* | | |1.When FIFO mode is disabled, all configurations should be set before writing 1 to the GOBUSY bit in the SPI_CTL register.
* | | |2
* | | |When FIFO bit is disabled and the software uses TX or RX PDMA function to transfer data, this bit will be cleared after the PDMA controller finishes the data transfer.
* |[1] |RXNEG |Receive on Negative Edge
* | | |0 = The received data is latched on the rising edge of SPI_CLK.
* | | |1 = The received data is latched on the falling edge of SPI_CLK.
* | | |Note: Refer to Edge section.
* | | |Note:
* |[2] |TXNEG |Transmit on Negative Edge
* | | |0 = The transmitted data output is changed on the rising edge of SPI_CLK.
* | | |1 = The transmitted data output is changed on the falling edge of SPI_CLK.
* | | |Note: Refer to Edge section.
* | | |Note:
* |[7:3] |DWIDTH |Data Width
* | | |This field specifies how many bits can be transmitted / received in one transaction
* | | |The minimum bit length is 8 bits and can be up to 32 bits.
* | | |0x1~0x7: reserved
* | | |0x8 = 8 bits are transmitted in one transaction.
* | | |0x9 = 9 bits are transmitted in one transaction.
* | | |0xA = 10 bits are transmitted in one transaction.
* | | |u2026
* | | |0x1F = 31 bits are transmitted in one transaction.
* | | |0x0 = 32 bits are transmitted in one transaction.
* | | |Note:
* |[10] |LSB |Send LSB First
* | | |0 = The MSB, which bit of transmit/receive register depends on the setting of DWIDTH (SPI_CTL[7:3]), is transmitted/received first.
* | | |1 = The LSB, bit 0 of the SPI_TX, is sent first to the the SPI data output pin, and the first bit received from the SPI data input pin will be put in the LSB position of the RX register (SPI_RX
* | | |Note: Refer to LSB first section.
* |[11] |CLKPOL |Clock Polarity
* | | |0 = The default level of SPI_CLK is low.
* | | |1 = The default level of SPI_CLK is high.
* | | |Note: Refer to Clock Parity section.
* | | |Note:
* |[15:12] |SUSPITV |Suspend Interval (Master Only)
* | | |These four bits provide configurable suspend interval between two successive transmit/receive transaction in a transfer
* | | |The suspend interval is from the last falling clock edge of the current transaction to the first rising clock edge of the successive transaction if CLKPOL = 0
* | | |If CLKPOL = 1, the interval is from the rising clock edge to the falling clock edge.
* | | |The default value is 0x3
* | | |The desired suspend interval is obtained according to the following equation: (SUSPITV[3:0] + 0.5) * period of SPI_CLK
* | | |For example,
* | | |SUSPITV = 0x0 u2026. 0.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0x1 u2026. 1.5 SPI_CLK clock cycle.
* | | |u2026u2026
* | | |SUSPITV = 0xE u2026. 14.5 SPI_CLK clock cycle.
* | | |SUSPITV = 0xF u2026. 15.5 SPI_CLK clock cycle.
* | | |Note:
* |[17] |UNITIEN |Unit Transfer Interrupt Enable Bit
* | | |0 = SPI unit transfer interrupt Disabled.
* | | |1 = SPI unit transfer interrupt Enabled.
* |[18] |SLAVE |Slave Mode Selection
* | | |0 = SPI controller set as Master mode.
* | | |1 = SPI controller set as Slave mode.
* | | |Note: Refer to Slave Selection section
* | | |Note:
* |[19] |REORDER |Byte Reorder Function Enable Bit
* | | |0 = Byte reorder function Disabled.
* | | |1 = Enable byte reorder function and insert a byte suspend interval among each byte
* | | |The byte reorder function is only available when DWIDTH is configured as 16, 24, and 32 bits.
* | | |Note: The suspend interval is defined in SUSPITV. Refer to Byte Reorder section.
* | | |Note: Byte Suspend is only used in SPI Byte Reorder mode.
* |[21] |FIFOM |FIFO Mode Enable Bit
* | | |0 = FIFO mode Disabled (in Normal mode).
* | | |1 = FIFO mode Enabled.
* | | |Note: Refer to FIFO Mode section.
* | | |Note:
* |[30] |WKSSEN |Wake-up by Slave Select Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* | | |Note: The Slave select wake-up function is only available in SPI Slave mode
* | | |When the system enters power-down mode, the system can be wake-up from the SPI controller if this bit and PDWKIEN (CLK_PWRCTL[5]) are enabled and there is any toggle on the SPI_SS port
* | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
* | | |Note: The wake up event will not assert the SPI interrupt, but user can read the corresponding status bit to check its occurrence.
* |[31] |WKCLKEN |Wake-up by SPI Clock Enable Bit
* | | |0 = Wake-up function Disabled.
* | | |1 = Wake-up function Enabled.
* | | |Note: When the system enters power-down mode, the system can be wake-up from the SPI controller if this bit and PDWKIEN (CLK_PWRCTL[5]) are enabled and there is any toggle on the SPI_CLK port
* | | |After the system wake-up, this bit must be cleared by user to disable the wake-up requirement.
* | | |Note: The wake up event will not assert the SPI interrupt, but user can read the corresponding status bit to check its occurrence.
* @var SPI5_T::STATUS
* Offset: 0x04 SPI Status Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXEMPTY |Receive FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Received data FIFO is not empty in the FIFO mode.
* | | |1 = Received data FIFO is empty in the FIFO mode.
* |[1] |RXFULL |Receive FIFO Buffer Full Indicator (Read Only)
* | | |0 = Received data FIFO is not full in FIFO mode.
* | | |1 = Received data FIFO is full in the FIFO mode.
* |[2] |TXEMPTY |Transmit FIFO Buffer Empty Indicator (Read Only)
* | | |0 = Transmitted data FIFO is not empty in the FIFO mode.
* | | |1 =Transmitted data FIFO is empty in the FIFO mode.
* |[3] |TXFULL |Transmit FIFO Buffer Full Indicator (Read Only)
* | | |0 = Transmitted data FIFO is not full in the FIFO mode.
* | | |1 = Transmitted data FIFO is full in the FIFO mode.
* |[4] |LTRIGF |Level Trigger Accomplish Flag (Read Only)
* | | |In Slave mode, this bit indicates whether the received bit number meets the requirement or not after the current transaction done.
* | | |0 = The transferred bit length of one transaction does not meet the specified requirement.
* | | |1 = The transferred bit length meets the specified requirement which defined in DWIDTH.
* | | |Note: This bit is read only
* | | |As the software sets the GOBUSY bit to 1, the LTRIGF will be cleared to 0 after 4 SPI peripheral clock periods plus 1 system clock period
* | | |In FIFO mode, this bit is unmeaning.
* |[6] |SLVSTAIF |Slave Start Interrupt Flag
* | | |It is used to dedicate that the transfer has started in Slave mode with no slave select.
* | | |0 = Slave started transfer no active.
* | | |1 = Transfer has started in Slave mode with no slave select
* | | |It is automatically cleared by transfer done or writing u20181'.
* |[7] |UNITIF |Unit Transfer Interrupt Flag
* | | |0 = No transaction has been finished since this bit was cleared to 0.
* | | |1 = SPI controller has finished one unit transfer.
* | | |Note 1: If SSINAIEN (SPI_SSCTL[16]) is set to 1, this bit will be asserted again when transfer is done and the slave select signal becomes inactive from active condition.
* | | |Note 2: This bit will be cleared by writing 1 to it.
* |[8] |RXTHIF |RX FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = RX valid data counts are less than or equal to RXTH (SPI_FIFOCTL[26:24]).
* | | |1 = RX valid data counts are larger than RXTH.
* | | |Note: If RXTHIEN (SPI_FIFOCTL[2]) = 1 and RXTHIF = 1, SPI will generate interrupt.
* |[9] |RXOVIF |Receive FIFO Overrun Interrupt Flag
* | | |0 = No FIFO overrun.
* | | |1 = Receive FIFO overrun.
* | | |Note 1: If SPI receives data when RX FIFO is full, this bit will set to 1, and the received data will be dropped.
* | | |Note 2: This bit will be cleared by writing 1 to it.
* |[10] |TXTHIF |Transmit FIFO Threshold Interrupt Flag (Read Only)
* | | |0 = TX valid data counts are larger than TXTH (SPI_FIFOCTL[30:28]).
* | | |1 = TX valid data counts are less than or equal to TXTH.
* |[12] |RXTOIF |Receive Time-out Interrupt Flag
* | | |0 = There is not time-out event on the received buffer.
* | | |1 = Time-out event active in RX FIFO is not empty.
* | | |Refer to Time Out section.
* | | |Note: This bit will be cleared by writing 1 to it.
* |[13] |SLVTOIF |Slave Time-out Interrupt Flag
* | | |If SLVTOIEN (SPI_SSCTL[6]) is set to 1, this bit will be asserted when slave time-out event occur
* | | |Software can clear this bit by setting RXFBCLR (SPI_FIFOCTL[0]) or writing 1 to clear this bit.
* | | |0 = Slave time-out does not occur yet.
* | | |1 = Slave time-out has occurred.
* |[15] |SLVTXSKE |Slave Mode Transmit Skew Buffer Empty Status
* | | |This bit indicates the empty status of transmit skew buffer which is used in Slave mode.
* |[19:16] |RXCNT |Receive FIFO Data Counts (Read Only)
* | | |This bit field indicates the valid data count of receive FIFO buffer.
* |[23:20] |TXCNT |Transmit FIFO Data Counts (Read Only)
* | | |This bit field indicates the valid data count of transmit FIFO buffer.
* |[30] |WKSSIF |Wake-up by Slave Select Interrupt Flag
* | | |When chip is woken up from power-down mode by the toggle event on SPI_SS port, this bit is set to 1
* | | |This bit can be cleared by writing u20181' to it.
* |[31] |WKCLKIF |Wake-up by SPI Clock Interrupt Flag
* | | |When chip is woken up from power-down mode by the toggle event on SPI_CLK port, this bit is set to 1
* | | |This bit can be cleared by writing u20181' to it.
* @var SPI5_T::CLKDIV
* Offset: 0x08 SPI Clock Divider Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[7:0] |DIVIDER |Clock Divider
* | | |The value is the 1th frequency divider of the PCLK to generate the serial clock of SPI_CLK
* | | |The desired frequency is obtained according to the following equation:
* | | |Where
* | | |is the SPI peripheral clock source
* | | |It is defined in the CLK_CLKSEL2[15:14] in Clock control section (CLK_BA + 0x18).
* | | |Note:
* @var SPI5_T::SSCTL
* Offset: 0x0C SPI Slave Select Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |SS |Slave Selection Control (Master Only)
* | | |If AUTOSS bit (SPI_SSCTL[3]) is cleared, writing 1 to SS (SPI_SSCTL[0]) bit sets the SPI_SS line to an active state and writing 0 sets the line back to inactive state
* | | |If AUTOSS = 0,.
* | | |0 = SPI_SS is inactive.
* | | |1 =SPI_SS is active.
* | | |If AUTOSS bit is set, writing 1 to this field will select appropriate SPI_SS line to be automatically driven to active state for the duration of the transaction, and will be driven to inactive state for the rest of the time
* | | |(The active level of SPI_SS is specified in SSACTPOL).
* | | |If AUTOSS =1,.
* | | |0 = SPI_SS is inactive.
* | | |1 = SPI_SS is active on the duration of transaction.
* | | |Note:
* | | |1
* | | |This interface can only drive one device/slave at a given time
* | | |Therefore, the slaves select of the selected device must be set to its active level before starting any read or write transfer.
* | | |2
* | | |SPI_SS is also defined as device/slave select input in Slave mode
* | | |And that the slave select input must be driven by edge active trigger which level depend on the SSACTPOL setting, otherwise the SPI slave core will go into dead path until the edge active triggers again or reset the SPI core by software
* |[2] |SSACTPOL |Slave Selection Active Polarity
* | | |It defines the active polarity of slave selection signal (SPI_SS).
* | | |0 = The SPI_SS slave select signal is active Low.
* | | |1 = The SPI_SS slave select signal is active High.
* |[3] |AUTOSS |Automatic Slave Selection Function Enable Bit (Master Only)
* | | |0 = If this bit is set as 0, slave select signals are asserted and de-asserted by setting and clearing related bits in SS (SPI_SSCTL[0]).
* | | |1 = If this bit is set as 1, SPI_SS signals are generated automatically
* | | |It means that device/slave select signal, which is set in SS (SPI_SSCTL[0]) is asserted by the SPI controller when transmit/receive is started, and is de-asserted after each transaction is done.
* |[4] |SSLTRIG |Slave Select Level Trigger Control
* | | |0 = The input slave select signal is edge-trigger.
* | | |1 = The slave select signal will be level-trigger
* | | |It depends on SSACTPOL to decide the signal is active low or active high.
* |[5] |SLV3WIRE |Slave 3-wire Mode Enable Bit
* | | |This bit is used to ignore the slave select signal in Slave mode
* | | |The SPI controller can work with 3-wire interface including SPI_CLK, SPI_MISO, and SPI_MOSI when it is set as a slave device.
* | | |0 = The controller is 4-wire bi-direction interface.
* | | |1 = The controller is 3-wire bi-direction interface in Slave mode
* | | |When this bit is set as 1, the controller start to transmit/receive data after the GOBUSY bit active and the SPI clock input.
* | | |Note 1: Refer to No Slave Select Mode.
* | | |Note 2: In no slave select signal mode, hardware will set the SSLTRIG (SPI_SSCTL[4]) as 1 automatically.
* |[6] |SLVTOIEN |Slave Time-out Interrupt Enable Bit
* | | |This bit is used to enable the slave time-out function in slave mode and there will be an interrupt if slave time-out event occur
* | | |0 = Slave time-out function and interrupt both Disabled.
* | | |1 = Slave time-out function and interrupt both Enabled.
* |[8] |SLVABORT |Abort in Slave Mode with No Slave Selected
* | | |0 = No force the slave abort.
* | | |1 = Force the current transfer done in no slave select mode.
* | | |Refer to No Slave Select Mode.
* | | |Note: It is auto cleared to 0 by hardware when the abort event is active.
* |[9] |SSTAIEN |Slave Start Interrupt Enable Bit
* | | |0 = Transfer start interrupt Disabled in no slave select mode.
* | | |1 = Transaction start interrupt Enabled in no slave select mode
* | | |It is cleared when the current transfer done or the SLVSTAIF bit cleared (write 1 clear).
* | | |Refer to No Slave Select Mode.
* |[16] |SSINAIEN |Slave Select Inactive Interrupt Enable Bit
* | | |It is used to enable the interrupt when the transfer has done in slave mode.
* | | |0 = No any interrupt, even there is slave select inactive event.
* | | |1 = There is interrupt event when the slave select signal becomes inactive from active condition
* | | |It is used to inform the user to know that the transaction has finished and the slave select into the inactive state.
* |[29:20] |SLVTOCNT |Slave Mode Time-out Period
* | | |In Slave mode, these bits indicate the time-out period when there is bus clock input during slave select active
* | | |The clock source of the time-out counter is Slave peripheral clock
* | | |If the value is 0, it indicates the slave mode time-out function is disabled.
* @var SPI5_T::RX
* Offset: 0x10 SPI Receive Data FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |RX |Receive Data Register (Read Only)
* | | |The received data can be read on it
* | | |If the FIFO bit is set as 1, the user also checks the RXEMPTY (SPI_STATUS[0]), to check if there is any more received data or not.
* @var SPI5_T::TX
* Offset: 0x20 SPI Transmit Data FIFO Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[31:0] |TX |Transmit Data Register (Write Only)
* | | |The Data Transmit Registers hold the data to be transmitted in the next transfer
* | | |The number of valid bits depends on the setting of transmit bit length field of the SPI_CTL register.
* | | |For example, if DWIDTH is set to 0x8, the bit SPI_TX[7:0] will be transmitted in next transfer
* | | |If DWIDTH is set to 0x0, the SPI controller will perform a 32-bit transfer.
* | | |Note:
* | | |If the SPI controller operates as slave device and FIFO mode is disabled, software must update the transmit data register before setting the GOBUSY bit to 1
* @var SPI5_T::PDMACTL
* Offset: 0x38 SPI PDMA Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |TXPDMAEN |Transmit PDMA Enable Bit
* | | |0 = Transmit PDMA function Disabled.
* | | |1 = Transmit PDMA function Enabled.
* | | |Refer to PDMA section for more detail information.
* | | |Note:
* | | |1
* | | |Two transaction need minimal 18 APB clock + 8 SPI peripheral clocks suspend interval in master mode for edge mode and 18 APB clock + 9.5 SPI peripheral clocks for level mode.
* | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
* |[1] |RXPDMAEN |Receiving PDMA Enable Bit
* | | |0 = Receiver PDMA function Disabled.
* | | |1 = Receiver PDMA function Enabled.
* | | |Refer to PDMA section for more detail information.
* | | |Note:
* | | |Hardware will clear this bit to 0 automatically after PDMA transfer done.
* | | |In Slave mode and the FIFO bit is disabled, if the receive PDMA is enabled but the transmit PDMA is disabled, the minimal suspend interval between two successive transactions input is need to be larger than 9 SPI peripheral clock + 4 APB clock for edge mode and 9.5 SPI peripheral clock + 4 APB clock
* |[2] |PDMARST |PDMA Reset
* | | |It is used to reset the SPI PDMA function into default state.
* | | |0 = After reset PDMA function or in normal operation.
* | | |1 = Reset PDMA function.
* | | |Note: It is auto cleared to 0 after the reset function has done.
* @var SPI5_T::FIFOCTL
* Offset: 0x3C SPI FIFO Control Register
* ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions
* | :----: | :----: | :---- |
* |[0] |RXFBCLR |Receive FIFO Buffer Clear
* | | |0 = No clear the received FIFO.
* | | |1 = Clear the received FIFO.
* | | |Note: This bit is used to clear the receiver counter in FIFO Mode
* | | |This bit can be written 1 to clear the receiver counter and this bit will be cleared to 0 automatically after clearing receiving counter
* | | |After the clear operation, the flag of RXEMPTY in SPI_STATUS[0] will be set to 1.
* |[1] |TXFBCLR |Transmit FIFO Buffer Clear
* | | |0 = Not clear the transmitted FIFO.
* | | |1 = Clear the transmitted FIFO.
* | | |Note: This bit is used to clear the transmit counter in FIFO Mode
* | | |This bit can be written 1 to clear the transmitting counter and this bit will be cleared to 0 automatically after clearing transmitting counter
* | | |After the clear operation, the flag of TXEMPTY in SPI_STATUS[2] will be set to 1.
* |[2] |RXTHIEN |Receive Threshold Interrupt Enable Bit
* | | |0 = RX threshold interrupt Disabled.
* | | |1 = RX threshold interrupt Enabled.
* |[3] |TXTHIEN |Transmit Threshold Interrupt Enable Bit
* | | |0 = TX threshold interrupt Disabled.
* | | |1 = TX threshold interrupt Enabled.
* |[4] |RXOVIEN |Receive FIFO Overrun Interrupt Enable Bit
* | | |0 = RX FIFO overrun interrupt Disabled.
* | | |1 = RX FIFO overrun interrupt Enabled.
* |[7] |RXTOIEN |RX Read Time Out Interrupt Enable Bit
* | | |0 = RX read Timeout Interrupt Disabled.
* | | |1 = RX read Timeout Interrupt Enabled.
* |[26:24] |RXTH |Received FIFO Threshold
* | | |If RX valid data counts are larger than RXTH, RXTHIF (SPI_STATUS[8]) will be set to 1..
* |[30:28] |TXTH |Transmit FIFO Threshold
* | | |If TX valid data counts are less than or equal to TXTH, TXTHIF (SPI_STATUS[10]) will be set to 1.
*/
__IO uint32_t CTL; /*!< [0x0000] SPI Control Register */
__IO uint32_t STATUS; /*!< [0x0004] SPI Status Register */
__IO uint32_t CLKDIV; /*!< [0x0008] SPI Clock Divider Register */
__IO uint32_t SSCTL; /*!< [0x000c] SPI Slave Select Control Register */
__I uint32_t RX; /*!< [0x0010] SPI Receive Data FIFO Register */
__I uint32_t RESERVE0[3];
__O uint32_t TX; /*!< [0x0020] SPI Transmit Data FIFO Register */
__I uint32_t RESERVE1[5];
__IO uint32_t PDMACTL; /*!< [0x0038] SPI PDMA Control Register */
__IO uint32_t FIFOCTL; /*!< [0x003c] SPI FIFO Control Register */
} SPI5_T;
/**
@addtogroup SPI5_CONST SPI5 Bit Field Definition
Constant Definitions for SPI5 Controller
@{ */
#define SPI5_CTL_GOBUSY_Pos (0) /*!< SPI5_T::CTL: GOBUSY Position */
#define SPI5_CTL_GOBUSY_Msk (0x1ul << SPI5_CTL_GOBUSY_Pos) /*!< SPI5_T::CTL: GOBUSY Mask */
#define SPI5_CTL_RXNEG_Pos (1) /*!< SPI5_T::CTL: RXNEG Position */
#define SPI5_CTL_RXNEG_Msk (0x1ul << SPI5_CTL_RXNEG_Pos) /*!< SPI5_T::CTL: RXNEG Mask */
#define SPI5_CTL_TXNEG_Pos (2) /*!< SPI5_T::CTL: TXNEG Position */
#define SPI5_CTL_TXNEG_Msk (0x1ul << SPI5_CTL_TXNEG_Pos) /*!< SPI5_T::CTL: TXNEG Mask */
#define SPI5_CTL_DWIDTH_Pos (3) /*!< SPI5_T::CTL: DWIDTH Position */
#define SPI5_CTL_DWIDTH_Msk (0x1ful << SPI5_CTL_DWIDTH_Pos) /*!< SPI5_T::CTL: DWIDTH Mask */
#define SPI5_CTL_LSB_Pos (10) /*!< SPI5_T::CTL: LSB Position */
#define SPI5_CTL_LSB_Msk (0x1ul << SPI5_CTL_LSB_Pos) /*!< SPI5_T::CTL: LSB Mask */
#define SPI5_CTL_CLKPOL_Pos (11) /*!< SPI5_T::CTL: CLKPOL Position */
#define SPI5_CTL_CLKPOL_Msk (0x1ul << SPI5_CTL_CLKPOL_Pos) /*!< SPI5_T::CTL: CLKPOL Mask */
#define SPI5_CTL_SUSPITV_Pos (12) /*!< SPI5_T::CTL: SUSPITV Position */
#define SPI5_CTL_SUSPITV_Msk (0xful << SPI5_CTL_SUSPITV_Pos) /*!< SPI5_T::CTL: SUSPITV Mask */
#define SPI5_CTL_UNITIEN_Pos (17) /*!< SPI5_T::CTL: UNITIEN Position */
#define SPI5_CTL_UNITIEN_Msk (0x1ul << SPI5_CTL_UNITIEN_Pos) /*!< SPI5_T::CTL: UNITIEN Mask */
#define SPI5_CTL_SLAVE_Pos (18) /*!< SPI5_T::CTL: SLAVE Position */
#define SPI5_CTL_SLAVE_Msk (0x1ul << SPI5_CTL_SLAVE_Pos) /*!< SPI5_T::CTL: SLAVE Mask */
#define SPI5_CTL_REORDER_Pos (19) /*!< SPI5_T::CTL: REORDER Position */
#define SPI5_CTL_REORDER_Msk (0x1ul << SPI5_CTL_REORDER_Pos) /*!< SPI5_T::CTL: REORDER Mask */
#define SPI5_CTL_FIFOM_Pos (21) /*!< SPI5_T::CTL: FIFOM Position */
#define SPI5_CTL_FIFOM_Msk (0x1ul << SPI5_CTL_FIFOM_Pos) /*!< SPI5_T::CTL: FIFOM Mask */
#define SPI5_CTL_WKSSEN_Pos (30) /*!< SPI5_T::CTL: WKSSEN Position */
#define SPI5_CTL_WKSSEN_Msk (0x1ul << SPI5_CTL_WKSSEN_Pos) /*!< SPI5_T::CTL: WKSSEN Mask */
#define SPI5_CTL_WKCLKEN_Pos (31) /*!< SPI5_T::CTL: WKCLKEN Position */
#define SPI5_CTL_WKCLKEN_Msk (0x1ul << SPI5_CTL_WKCLKEN_Pos) /*!< SPI5_T::CTL: WKCLKEN Mask */
#define SPI5_STATUS_RXEMPTY_Pos (0) /*!< SPI5_T::STATUS: RXEMPTY Position */
#define SPI5_STATUS_RXEMPTY_Msk (0x1ul << SPI5_STATUS_RXEMPTY_Pos) /*!< SPI5_T::STATUS: RXEMPTY Mask */
#define SPI5_STATUS_RXFULL_Pos (1) /*!< SPI5_T::STATUS: RXFULL Position */
#define SPI5_STATUS_RXFULL_Msk (0x1ul << SPI5_STATUS_RXFULL_Pos) /*!< SPI5_T::STATUS: RXFULL Mask */
#define SPI5_STATUS_TXEMPTY_Pos (2) /*!< SPI5_T::STATUS: TXEMPTY Position */
#define SPI5_STATUS_TXEMPTY_Msk (0x1ul << SPI5_STATUS_TXEMPTY_Pos) /*!< SPI5_T::STATUS: TXEMPTY Mask */
#define SPI5_STATUS_TXFULL_Pos (3) /*!< SPI5_T::STATUS: TXFULL Position */
#define SPI5_STATUS_TXFULL_Msk (0x1ul << SPI5_STATUS_TXFULL_Pos) /*!< SPI5_T::STATUS: TXFULL Mask */
#define SPI5_STATUS_LTRIGF_Pos (4) /*!< SPI5_T::STATUS: LTRIGF Position */
#define SPI5_STATUS_LTRIGF_Msk (0x1ul << SPI5_STATUS_LTRIGF_Pos) /*!< SPI5_T::STATUS: LTRIGF Mask */
#define SPI5_STATUS_SLVSTAIF_Pos (6) /*!< SPI5_T::STATUS: SLVSTAIF Position */
#define SPI5_STATUS_SLVSTAIF_Msk (0x1ul << SPI5_STATUS_SLVSTAIF_Pos) /*!< SPI5_T::STATUS: SLVSTAIF Mask */
#define SPI5_STATUS_UNITIF_Pos (7) /*!< SPI5_T::STATUS: UNITIF Position */
#define SPI5_STATUS_UNITIF_Msk (0x1ul << SPI5_STATUS_UNITIF_Pos) /*!< SPI5_T::STATUS: UNITIF Mask */
#define SPI5_STATUS_RXTHIF_Pos (8) /*!< SPI5_T::STATUS: RXTHIF Position */
#define SPI5_STATUS_RXTHIF_Msk (0x1ul << SPI5_STATUS_RXTHIF_Pos) /*!< SPI5_T::STATUS: RXTHIF Mask */
#define SPI5_STATUS_RXOVIF_Pos (9) /*!< SPI5_T::STATUS: RXOVIF Position */
#define SPI5_STATUS_RXOVIF_Msk (0x1ul << SPI5_STATUS_RXOVIF_Pos) /*!< SPI5_T::STATUS: RXOVIF Mask */
#define SPI5_STATUS_TXTHIF_Pos (10) /*!< SPI5_T::STATUS: TXTHIF Position */
#define SPI5_STATUS_TXTHIF_Msk (0x1ul << SPI5_STATUS_TXTHIF_Pos) /*!< SPI5_T::STATUS: TXTHIF Mask */
#define SPI5_STATUS_RXTOIF_Pos (12) /*!< SPI5_T::STATUS: RXTOIF Position */
#define SPI5_STATUS_RXTOIF_Msk (0x1ul << SPI5_STATUS_RXTOIF_Pos) /*!< SPI5_T::STATUS: RXTOIF Mask */
#define SPI5_STATUS_SLVTOIF_Pos (13) /*!< SPI5_T::STATUS: SLVTOIF Position */
#define SPI5_STATUS_SLVTOIF_Msk (0x1ul << SPI5_STATUS_SLVTOIF_Pos) /*!< SPI5_T::STATUS: SLVTOIF Mask */
#define SPI5_STATUS_SLVTXSKE_Pos (15) /*!< SPI5_T::STATUS: SLVTXSKE Position */
#define SPI5_STATUS_SLVTXSKE_Msk (0x1ul << SPI5_STATUS_SLVTXSKE_Pos) /*!< SPI5_T::STATUS: SLVTXSKE Mask */
#define SPI5_STATUS_RXCNT_Pos (16) /*!< SPI5_T::STATUS: RXCNT Position */
#define SPI5_STATUS_RXCNT_Msk (0xful << SPI5_STATUS_RXCNT_Pos) /*!< SPI5_T::STATUS: RXCNT Mask */
#define SPI5_STATUS_TXCNT_Pos (20) /*!< SPI5_T::STATUS: TXCNT Position */
#define SPI5_STATUS_TXCNT_Msk (0xful << SPI5_STATUS_TXCNT_Pos) /*!< SPI5_T::STATUS: TXCNT Mask */
#define SPI5_STATUS_WKSSIF_Pos (30) /*!< SPI5_T::STATUS: WKSSIF Position */
#define SPI5_STATUS_WKSSIF_Msk (0x1ul << SPI5_STATUS_WKSSIF_Pos) /*!< SPI5_T::STATUS: WKSSIF Mask */
#define SPI5_STATUS_WKCLKIF_Pos (31) /*!< SPI5_T::STATUS: WKCLKIF Position */
#define SPI5_STATUS_WKCLKIF_Msk (0x1ul << SPI5_STATUS_WKCLKIF_Pos) /*!< SPI5_T::STATUS: WKCLKIF Mask */
#define SPI5_CLKDIV_DIVIDER_Pos (0) /*!< SPI5_T::CLKDIV: DIVIDER Position */
#define SPI5_CLKDIV_DIVIDER_Msk (0xfful << SPI5_CLKDIV_DIVIDER_Pos) /*!< SPI5_T::CLKDIV: DIVIDER Mask */
#define SPI5_SSCTL_SS_Pos (0) /*!< SPI5_T::SSCTL: SS Position */
#define SPI5_SSCTL_SS_Msk (0x1ul << SPI5_SSCTL_SS_Pos) /*!< SPI5_T::SSCTL: SS Mask */
#define SPI5_SSCTL_SSACTPOL_Pos (2) /*!< SPI5_T::SSCTL: SSACTPOL Position */
#define SPI5_SSCTL_SSACTPOL_Msk (0x1ul << SPI5_SSCTL_SSACTPOL_Pos) /*!< SPI5_T::SSCTL: SSACTPOL Mask */
#define SPI5_SSCTL_AUTOSS_Pos (3) /*!< SPI5_T::SSCTL: AUTOSS Position */
#define SPI5_SSCTL_AUTOSS_Msk (0x1ul << SPI5_SSCTL_AUTOSS_Pos) /*!< SPI5_T::SSCTL: AUTOSS Mask */
#define SPI5_SSCTL_SSLTRIG_Pos (4) /*!< SPI5_T::SSCTL: SSLTRIG Position */
#define SPI5_SSCTL_SSLTRIG_Msk (0x1ul << SPI5_SSCTL_SSLTRIG_Pos) /*!< SPI5_T::SSCTL: SSLTRIG Mask */
#define SPI5_SSCTL_SLV3WIRE_Pos (5) /*!< SPI5_T::SSCTL: SLV3WIRE Position */
#define SPI5_SSCTL_SLV3WIRE_Msk (0x1ul << SPI5_SSCTL_SLV3WIRE_Pos) /*!< SPI5_T::SSCTL: SLV3WIRE Mask */
#define SPI5_SSCTL_SLVTOIEN_Pos (6) /*!< SPI5_T::SSCTL: SLVTOIEN Position */
#define SPI5_SSCTL_SLVTOIEN_Msk (0x1ul << SPI5_SSCTL_SLVTOIEN_Pos) /*!< SPI5_T::SSCTL: SLVTOIEN Mask */
#define SPI5_SSCTL_SLVABORT_Pos (8) /*!< SPI5_T::SSCTL: SLVABORT Position */
#define SPI5_SSCTL_SLVABORT_Msk (0x1ul << SPI5_SSCTL_SLVABORT_Pos) /*!< SPI5_T::SSCTL: SLVABORT Mask */
#define SPI5_SSCTL_SSTAIEN_Pos (9) /*!< SPI5_T::SSCTL: SSTAIEN Position */
#define SPI5_SSCTL_SSTAIEN_Msk (0x1ul << SPI5_SSCTL_SSTAIEN_Pos) /*!< SPI5_T::SSCTL: SSTAIEN Mask */
#define SPI5_SSCTL_SSINAIEN_Pos (16) /*!< SPI5_T::SSCTL: SSINAIEN Position */
#define SPI5_SSCTL_SSINAIEN_Msk (0x1ul << SPI5_SSCTL_SSINAIEN_Pos) /*!< SPI5_T::SSCTL: SSINAIEN Mask */
#define SPI5_SSCTL_SLVTOCNT_Pos (20) /*!< SPI5_T::SSCTL: SLVTOCNT Position */
#define SPI5_SSCTL_SLVTOCNT_Msk (0x3fful << SPI5_SSCTL_SLVTOCNT_Pos) /*!< SPI5_T::SSCTL: SLVTOCNT Mask */
#define SPI5_RX_RX_Pos (0) /*!< SPI5_T::RX: RX Position */
#define SPI5_RX_RX_Msk (0xfffffffful << SPI5_RX_RX_Pos) /*!< SPI5_T::RX: RX Mask */
#define SPI5_TX_TX_Pos (0) /*!< SPI5_T::TX: TX Position */
#define SPI5_TX_TX_Msk (0xfffffffful << SPI5_TX_TX_Pos) /*!< SPI5_T::TX: TX Mask */
#define SPI5_PDMACTL_TXPDMAEN_Pos (0) /*!< SPI5_T::PDMACTL: TXPDMAEN Position */
#define SPI5_PDMACTL_TXPDMAEN_Msk (0x1ul << SPI5_PDMACTL_TXPDMAEN_Pos) /*!< SPI5_T::PDMACTL: TXPDMAEN Mask */
#define SPI5_PDMACTL_RXPDMAEN_Pos (1) /*!< SPI5_T::PDMACTL: RXPDMAEN Position */
#define SPI5_PDMACTL_RXPDMAEN_Msk (0x1ul << SPI5_PDMACTL_RXPDMAEN_Pos) /*!< SPI5_T::PDMACTL: RXPDMAEN Mask */
#define SPI5_PDMACTL_PDMARST_Pos (2) /*!< SPI5_T::PDMACTL: PDMARST Position */
#define SPI5_PDMACTL_PDMARST_Msk (0x1ul << SPI5_PDMACTL_PDMARST_Pos) /*!< SPI5_T::PDMACTL: PDMARST Mask */
#define SPI5_FIFOCTL_RXFBCLR_Pos (0) /*!< SPI5_T::FIFOCTL: RXFBCLR Position */
#define SPI5_FIFOCTL_RXFBCLR_Msk (0x1ul << SPI5_FIFOCTL_RXFBCLR_Pos) /*!< SPI5_T::FIFOCTL: RXFBCLR Mask */
#define SPI5_FIFOCTL_TXFBCLR_Pos (1) /*!< SPI5_T::FIFOCTL: TXFBCLR Position */
#define SPI5_FIFOCTL_TXFBCLR_Msk (0x1ul << SPI5_FIFOCTL_TXFBCLR_Pos) /*!< SPI5_T::FIFOCTL: TXFBCLR Mask */
#define SPI5_FIFOCTL_RXTHIEN_Pos (2) /*!< SPI5_T::FIFOCTL: RXTHIEN Position */
#define SPI5_FIFOCTL_RXTHIEN_Msk (0x1ul << SPI5_FIFOCTL_RXTHIEN_Pos) /*!< SPI5_T::FIFOCTL: RXTHIEN Mask */
#define SPI5_FIFOCTL_TXTHIEN_Pos (3) /*!< SPI5_T::FIFOCTL: TXTHIEN Position */
#define SPI5_FIFOCTL_TXTHIEN_Msk (0x1ul << SPI5_FIFOCTL_TXTHIEN_Pos) /*!< SPI5_T::FIFOCTL: TXTHIEN Mask */
#define SPI5_FIFOCTL_RXOVIEN_Pos (4) /*!< SPI5_T::FIFOCTL: RXOVIEN Position */
#define SPI5_FIFOCTL_RXOVIEN_Msk (0x1ul << SPI5_FIFOCTL_RXOVIEN_Pos) /*!< SPI5_T::FIFOCTL: RXOVIEN Mask */
#define SPI5_FIFOCTL_RXTOIEN_Pos (7) /*!< SPI5_T::FIFOCTL: RXTOIEN Position */
#define SPI5_FIFOCTL_RXTOIEN_Msk (0x1ul << SPI5_FIFOCTL_RXTOIEN_Pos) /*!< SPI5_T::FIFOCTL: RXTOIEN Mask */
#define SPI5_FIFOCTL_RXTH_Pos (24) /*!< SPI5_T::FIFOCTL: RXTH Position */
#define SPI5_FIFOCTL_RXTH_Msk (0x7ul << SPI5_FIFOCTL_RXTH_Pos) /*!< SPI5_T::FIFOCTL: RXTH Mask */
#define SPI5_FIFOCTL_TXTH_Pos (28) /*!< SPI5_T::FIFOCTL: TXTH Position */
#define SPI5_FIFOCTL_TXTH_Msk (0x7ul << SPI5_FIFOCTL_TXTH_Pos) /*!< SPI5_T::FIFOCTL: TXTH Mask */
/**@}*/ /* SPI5_CONST */
/**@}*/ /* end of SPI5 register group */
#endif /* __SPI5_REG_H__ */

7
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/spi_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __SPI_REG_H__ #ifndef __SPI_REG_H__
#define __SPI_REG_H__ #define __SPI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Serial Peripheral Interface Controller -------------------------*/ /*---------------------- Serial Peripheral Interface Controller -------------------------*/
/** /**
@addtogroup SPI Serial Peripheral Interface Controller(SPI) @addtogroup SPI Serial Peripheral Interface Controller(SPI)
@ -776,6 +782,7 @@ typedef struct
/**@}*/ /* SPI_CONST */ /**@}*/ /* SPI_CONST */
/**@}*/ /* end of SPI register group */ /**@}*/ /* end of SPI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SPI_REG_H__ */ #endif /* __SPI_REG_H__ */

88
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/sys_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __SYS_REG_H__ #ifndef __SYS_REG_H__
#define __SYS_REG_H__ #define __SYS_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- System Manger Controller -------------------------*/ /*---------------------- System Manger Controller -------------------------*/
/** /**
@ -196,9 +201,6 @@ typedef struct
* |[21] |UART5RST |UART5 Controller Reset * |[21] |UART5RST |UART5 Controller Reset
* | | |0 = UART5 controller normal operation. * | | |0 = UART5 controller normal operation.
* | | |1 = UART5 controller reset. * | | |1 = UART5 controller reset.
* |[23] |DSRCRST |DSRC Controller Reset
* | | |0 = DSRC controller normal operation.
* | | |1 = DSRC controller reset.
* |[24] |CAN0RST |CAN0 Controller Reset * |[24] |CAN0RST |CAN0 Controller Reset
* | | |0 = CAN0 controller normal operation. * | | |0 = CAN0 controller normal operation.
* | | |1 = CAN0 controller reset. * | | |1 = CAN0 controller reset.
@ -234,9 +236,6 @@ typedef struct
* |[6] |SPI3RST |SPI3 Controller Reset * |[6] |SPI3RST |SPI3 Controller Reset
* | | |0 = SPI3 controller normal operation. * | | |0 = SPI3 controller normal operation.
* | | |1 = SPI3 controller reset. * | | |1 = SPI3 controller reset.
* |[7] |SPI5RST |SPI5 Controller Reset
* | | |0 = SPI5 controller normal operation.
* | | |1 = SPI5 controller reset.
* |[8] |USCI0RST |USCI0 Controller Reset * |[8] |USCI0RST |USCI0 Controller Reset
* | | |0 = USCI0 controller normal operation. * | | |0 = USCI0 controller normal operation.
* | | |1 = USCI0 controller reset. * | | |1 = USCI0 controller reset.
@ -602,7 +601,7 @@ typedef struct
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[n] |MFOSn |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select * |[n] |MFOSn |GPIOA-H Pin[n] Multiple Function Pin Output Mode Select
* | | |This bit used to select multiple function pin output mode type for Px.n pin * | | |This bit used to select multiple function pin output mode type for Px.n pin.
* | | |0 = Multiple function pin output mode type is Push-pull mode. * | | |0 = Multiple function pin output mode type is Push-pull mode.
* | | |1 = Multiple function pin output mode type is Open-drain mode. * | | |1 = Multiple function pin output mode type is Open-drain mode.
* | | |Note: * | | |Note:
@ -646,29 +645,29 @@ typedef struct
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[5:4] |RETCNT |SRAM Retention Count (Write Protect) * |[5:4] |RETCNT |SRAM Retention Count (Write Protect)
* | | |This field can configure SRAM macro retention time in unit of HIRC period. * | | |This field can configure SRAM macro retention time in unit of HIRC period.
* | | |00 = one HIRC period. * | | |00 = One HIRC period.
* | | |01 = two HIRC periods. * | | |01 = Two HIRC periods.
* | | |10 = three HIRC periods. * | | |10 = Three HIRC periods.
* | | |11 = four HIRC periods. * | | |11 = Four HIRC periods.
* | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[9:8] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect) * |[9:8] |SRAM0PM0 |Bank0 SRAM Power Mode Select 0 (Write Protect)
* | | |This field can control bank0 SRAM (32k) power mode in system power down mode for range 0x2000_0000 - 0x2000_1FFF * | | |This field can control bank0 SRAM (32k) power mode in system power down mode for range 0x2000_0000 - 0x2000_1FFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD). * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[11:10] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect) * |[11:10] |SRAM0PM1 |Bank0 SRAM Power Mode Select 1 (Write Protect)
* | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2000_2000 - 0x2000_3FFF * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2000_2000 - 0x2000_3FFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD). * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[13:12] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect) * |[13:12] |SRAM0PM2 |Bank0 SRAM Power Mode Select 2 (Write Protect)
* | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2004_0000 - 0x2000_5FFF * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2004_0000 - 0x2000_5FFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
@ -676,35 +675,35 @@ typedef struct
* | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD). * | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[15:14] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect) * |[15:14] |SRAM0PM3 |Bank0 SRAM Power Mode Select 3 (Write Protect)
* | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2006_0000 - 0x2000_7FFF * | | |This field can control bank0 SRAM (32k) power mode in system enter power down mode for range 0x2006_0000 - 0x2000_7FFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Bank 0 SRAM is always operating in power shut down mode for system enter Deep Power-down Mode (DPD). * | | |Note1: Bank0 SRAM is always operating in power shut down mode for system enter Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[17:16] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect) * |[17:16] |SRAM1PM0 |Bank1 SRAM Power Mode Select 0 (Write Protect)
* | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_8000 - 0x2000_BFFF * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_8000 - 0x2000_BFFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[19:18] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect) * |[19:18] |SRAM1PM1 |Bank1 SRAM Power Mode Select 1 (Write Protect)
* | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_C000 - 0x2000_FFFF * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2000_C000 - 0x2000_FFFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |Note1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[21:20] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect) * |[21:20] |SRAM1PM2 |Bank1 SRAM Power Mode Select 2 (Write Protect)
* | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_0000 - 0x2001_3FFF * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_0000 - 0x2001_3FFF.
* | | |00 = Normal mode. * | | |00 = Normal mode.
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[23:22] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect) * |[23:22] |SRAM1PM3 |Bank1 SRAM Power Mode Select 3 (Write Protect)
* | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_4000 - 0x2001_7FFF * | | |This field can control bank1 SRAM (64k) power mode in system enter power down mode for range 0x2001_4000 - 0x2001_7FFF
@ -712,7 +711,7 @@ typedef struct
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Bank 1 SRAM is always operating in power shut down mode for system enter StandbyPower-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Bank1 SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* @var SYS_T::SRAMPPCT * @var SYS_T::SRAMPPCT
* Offset: 0xE0 Peripheral SRAM Power Mode Control Register * Offset: 0xE0 Peripheral SRAM Power Mode Control Register
@ -725,7 +724,7 @@ typedef struct
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore).. * | | |11 = Reserved (Write Ignore)..
* | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[3:2] |USBD |USB Device SRAM Power Mode Select (Write Protect) * |[3:2] |USBD |USB Device SRAM Power Mode Select (Write Protect)
* | | |This field can control USB device SRAM power mode for system enter power down mode. * | | |This field can control USB device SRAM power mode for system enter power down mode.
@ -733,7 +732,7 @@ typedef struct
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[5:4] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect) * |[5:4] |PDMA0 |PDMA SRAM Power Mode Select (Write Protect)
* | | |This field can control PDMA0 (always secure) SRAM power mode for system enter power down mode. * | | |This field can control PDMA0 (always secure) SRAM power mode for system enter power down mode.
@ -741,7 +740,7 @@ typedef struct
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[7:6] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect) * |[7:6] |PDMA1 |PDMA SRAM Power Mode Select (Write Protect)
* | | |This field can control PDMA1 SRAM power mode for system enter power down mode. * | | |This field can control PDMA1 SRAM power mode for system enter power down mode.
@ -749,7 +748,7 @@ typedef struct
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* |[9:8] |FMC |FMC SRAM Power Mode Select (Write Protect) * |[9:8] |FMC |FMC SRAM Power Mode Select (Write Protect)
* | | |This field can control FMC cache SRAM power mode for system enter power down mode. * | | |This field can control FMC cache SRAM power mode for system enter power down mode.
@ -757,7 +756,7 @@ typedef struct
* | | |01 = Retention mode. * | | |01 = Retention mode.
* | | |10 = Power shut down mode. * | | |10 = Power shut down mode.
* | | |11 = Reserved (Write Ignore). * | | |11 = Reserved (Write Ignore).
* | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down Mode (SPD) and Deep Power-down Mode (DPD). * | | |Note1: Peripheral SRAM is always operating in power shut down mode for system enter Standby Power-down mode (SPD) and Deep Power-down mode (DPD).
* | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register. * | | |Note2: These bits are write protected. Refer to the SYS_REGLCTL register.
* @var SYS_T::TCTL48M * @var SYS_T::TCTL48M
* Offset: 0xE4 HIRC 48M Trim Control Register * Offset: 0xE4 HIRC 48M Trim Control Register
@ -790,8 +789,8 @@ typedef struct
* | | |0 = The trim operation is keep going if clock is inaccuracy. * | | |0 = The trim operation is keep going if clock is inaccuracy.
* | | |1 = The trim operation is stopped if clock is inaccuracy. * | | |1 = The trim operation is stopped if clock is inaccuracy.
* |[10] |REFCKSEL |Reference Clock Selection * |[10] |REFCKSEL |Reference Clock Selection
* | | |0 = HIRC trim 48M reference clock is from LXT (32.768 kHz). * | | |0 = HIRC trim 48M reference clock is from external 32.768 kHz crystal oscillator.
* | | |1 = HIRC trim 48M reference clock is from USB SOF (Start-Of-Frame) packet. * | | |1 = HIRC trim 48M reference clock is from internal USB synchronous mode.
* @var SYS_T::TIEN48M * @var SYS_T::TIEN48M
* Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register * Offset: 0xE8 HIRC 48M Trim Interrupt Enable Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
@ -864,8 +863,8 @@ typedef struct
* | | |0 = The trim operation is keep going if clock is inaccuracy. * | | |0 = The trim operation is keep going if clock is inaccuracy.
* | | |1 = The trim operation is stopped if clock is inaccuracy. * | | |1 = The trim operation is stopped if clock is inaccuracy.
* |[10] |REFCKSEL |Reference Clock Selection * |[10] |REFCKSEL |Reference Clock Selection
* | | |0 = HIRC trim reference clock is from LXT (32.768 kHz). * | | |0 = HIRC trim reference clock is from external 32.768 kHz crystal oscillator.
* | | |1 = HIRC trim reference clock is from USB SOF (Start-Of-Frame) packet. * | | |1 = HIRC trim reference clock is from internal USB synchronous mode.
* @var SYS_T::TIEN12M * @var SYS_T::TIEN12M
* Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register * Offset: 0xF4 HIRC 12M Trim Interrupt Enable Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
@ -913,10 +912,10 @@ typedef struct
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[7:0] |REGLCTL |Register Lock Control Code (Write Only) * |[7:0] |REGLCTL |Register Lock Control Code (Write Only)
* | | |Some registers have write-protection function * | | |Some registers have write-protection function
* | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field * | | |Writing these registers have to disable the protected function by writing the sequence value 59h, 16h, 88h to this field.
* | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write. * | | |After this sequence is completed, the REGLCTL bit will be set to 1 and write-protection registers can be normal write.
* |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only) * |[0] |REGLCTL[0]|Register Lock Control Disable Index (Read Only)
* | | |0 = Write-protection Enabled for writing protected registers * | | |0 = Write-protection Enabled for writing protected registers.
* | | |Any write to the protected register is ignored. * | | |Any write to the protected register is ignored.
* | | |1 = Write-protection Disabled for writing protected registers. * | | |1 = Write-protection Disabled for writing protected registers.
* @var SYS_T::PORCTL1 * @var SYS_T::PORCTL1
@ -970,8 +969,8 @@ typedef struct
* | | |0 = Main voltage regulator type change is completed. * | | |0 = Main voltage regulator type change is completed.
* | | |1 = Main voltage regulator type change is ongoing. * | | |1 = Main voltage regulator type change is ongoing.
* |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect) * |[2] |MVRCERR |Main Voltage Regulator Type Change Error Bit (Write Protect)
* | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors * | | |This bit is set to 1 when main voltage regulator type change from LDO to DCDC error, the following conditions will cause change errors:
* | | |1.System change to DC-DC mode but LDO change voltage process not finish * | | |1.System change to DC-DC mode but LDO change voltage process not finish.
* | | |2.Detect inductor fail. * | | |2.Detect inductor fail.
* | | |Read: * | | |Read:
* | | |0 = No main voltage regulator type change error. * | | |0 = No main voltage regulator type change error.
@ -982,12 +981,12 @@ typedef struct
* | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register. * | | |Note: This bit is write protected. Refer to the SYS_REGLCTL register.
* |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only) * |[3] |LCONS |Inductor for DC-DC Connect Status (Read Only)
* | | |0 = Inductor connect between Vsw and LDO_CAP pin. * | | |0 = Inductor connect between Vsw and LDO_CAP pin.
* | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0) this bit is set to 1. * | | |This bit is valid when current main voltage regulator type is DCDC (CURMVRS (SYS_PLSTS[12])=1). If current main voltage regulator type is LDO (CURMVRS (SYS_PLSTS[12])=0), this bit is set to 1.
* | | |0 = Inductor connect between Vsw and LDO_CAP pin. * | | |0 = Inductor connect between Vsw and LDO_CAP pin.
* | | |1 = No Inductor connect between Vsw and LDO_CAP pin. * | | |1 = No Inductor connect between Vsw and LDO_CAP pin.
* | | |Note: This bit is 1 when main viltage regulator is LDO. * | | |Note: This bit is 1 when main viltage regulator is LDO.
* |[4] |PDINVTRF |Power-down Mode Invalid Transition Flag (Write Protect) * |[4] |PDINVTRF |Power-down Mode Invalid Transition Flag (Write Protect)
* | | |This bit is set by hardware if the requested Active DCDC mode to Power-down mode transition is invalid. * | | |This bit is set by hardware if the requested active DCDC mode to Power-down mode transition is invalid.
* | | |This transition request will be aborted by hardware. * | | |This transition request will be aborted by hardware.
* | | |The bit can be cleared by software. * | | |The bit can be cleared by software.
* | | |Read: * | | |Read:
@ -1197,9 +1196,6 @@ typedef struct
#define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */ #define SYS_IPRST1_UART5RST_Pos (21) /*!< SYS_T::IPRST1: UART5RST Position */
#define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */ #define SYS_IPRST1_UART5RST_Msk (0x1ul << SYS_IPRST1_UART5RST_Pos) /*!< SYS_T::IPRST1: UART5RST Mask */
#define SYS_IPRST1_DSRCRST_Pos (23) /*!< SYS_T::IPRST1: CAN0RST Position */
#define SYS_IPRST1_DSRCRST_Msk (0x1ul << SYS_IPRST1_DSRCRST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
#define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */ #define SYS_IPRST1_CAN0RST_Pos (24) /*!< SYS_T::IPRST1: CAN0RST Position */
#define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */ #define SYS_IPRST1_CAN0RST_Msk (0x1ul << SYS_IPRST1_CAN0RST_Pos) /*!< SYS_T::IPRST1: CAN0RST Mask */
@ -1230,9 +1226,6 @@ typedef struct
#define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */ #define SYS_IPRST2_SPI3RST_Pos (6) /*!< SYS_T::IPRST2: SPI3RST Position */
#define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */ #define SYS_IPRST2_SPI3RST_Msk (0x1ul << SYS_IPRST2_SPI3RST_Pos) /*!< SYS_T::IPRST2: SPI3RST Mask */
#define SYS_IPRST2_SPI5RST_Pos (7) /*!< SYS_T::IPRST2: SPI5RST Position */
#define SYS_IPRST2_SPI5RST_Msk (0x1ul << SYS_IPRST2_SPI5RST_Pos) /*!< SYS_T::IPRST2: SPI5RST Mask */
#define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */ #define SYS_IPRST2_USCI0RST_Pos (8) /*!< SYS_T::IPRST2: USCI0RST Position */
#define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */ #define SYS_IPRST2_USCI0RST_Msk (0x1ul << SYS_IPRST2_USCI0RST_Pos) /*!< SYS_T::IPRST2: USCI0RST Mask */
@ -2053,7 +2046,7 @@ typedef struct
#define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */ #define SYS_TCTL12M_LOOPSEL_Msk (0x3ul << SYS_TCTL12M_LOOPSEL_Pos) /*!< SYS_T::TCTL12M: LOOPSEL Mask */
#define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */ #define SYS_TCTL12M_RETRYCNT_Pos (6) /*!< SYS_T::TCTL12M: RETRYCNT Position */
#define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12MM_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */ #define SYS_TCTL12M_RETRYCNT_Msk (0x3ul << SYS_TCTL12M_RETRYCNT_Pos) /*!< SYS_T::TCTL12M: RETRYCNT Mask */
#define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */ #define SYS_TCTL12M_CESTOPEN_Pos (8) /*!< SYS_T::TCTL12M: CESTOPEN Position */
#define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */ #define SYS_TCTL12M_CESTOPEN_Msk (0x1ul << SYS_TCTL12M_CESTOPEN_Pos) /*!< SYS_T::TCTL12M: CESTOPEN Mask */
@ -2369,6 +2362,7 @@ typedef struct
/**@}*/ /* INT_CONST */ /**@}*/ /* INT_CONST */
/**@}*/ /* end of SYS register group */ /**@}*/ /* end of SYS register group */
/**@}*/ /* end of REGISTER group */
#endif /* __SYS_REG_H__ */ #endif /* __SYS_REG_H__ */

10
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/timer_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __TIMER_REG_H__ #ifndef __TIMER_REG_H__
#define __TIMER_REG_H__ #define __TIMER_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Timer Controller -------------------------*/ /*---------------------- Timer Controller -------------------------*/
/** /**
@ -617,7 +622,7 @@ typedef struct
* | | |0 = PWMx_CH1 level-detect brake state is released. * | | |0 = PWMx_CH1 level-detect brake state is released.
* | | |1 = PWMx_CH1 at level-detect brake state. * | | |1 = PWMx_CH1 at level-detect brake state.
* | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period. * | | |Note: If TIMERx_PWM level-detect brake source has released, both PWMx_CH0 and PWMx_CH1 will release brake state when current PWM period finished and resume PWMx_CH0 and PWMx_CH1 output waveform start from next full PWM period.
* @var TIMER_T::PWMADCTS * @var TIMER_T::PWMEADCTS
* Offset: 0x90 Timer PWM ADC Trigger Source Select Register * Offset: 0x90 Timer PWM ADC Trigger Source Select Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
@ -1053,7 +1058,6 @@ typedef struct
/**@}*/ /* TIMER_CONST */ /**@}*/ /* TIMER_CONST */
/**@}*/ /* end of TIMER register group */ /**@}*/ /* end of TIMER register group */
/**@}*/ /* end of REGISTER group */
#endif /* __TIMER_REG_H__ */ #endif /* __TIMER_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/trng_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __TRNG_REG_H__ #ifndef __TRNG_REG_H__
#define __TRNG_REG_H__ #define __TRNG_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- True Random Number Generator -------------------------*/ /*---------------------- True Random Number Generator -------------------------*/
/** /**
@ -124,6 +129,7 @@ typedef struct
/**@}*/ /* TRNG_CONST */ /**@}*/ /* TRNG_CONST */
/**@}*/ /* end of TRNG register group */ /**@}*/ /* end of TRNG register group */
/**@}*/ /* end of REGISTER group */
#endif /* __TRNG_REG_H__ */ #endif /* __TRNG_REG_H__ */

31
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/uart_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __UART_REG_H__ #ifndef __UART_REG_H__
#define __UART_REG_H__ #define __UART_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/ /*---------------------- Universal Asynchronous Receiver/Transmitter Controller -------------------------*/
/** /**
@ -87,8 +93,8 @@ typedef struct
* | | |This bit can enable or disable RX PDMA service. * | | |This bit can enable or disable RX PDMA service.
* | | |0 = RX PDMA Disabled. * | | |0 = RX PDMA Disabled.
* | | |1 = RX PDMA Enabled. * | | |1 = RX PDMA Enabled.
* | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused * | | |Note: If RLSIEN (UART_INTEN[2]) is enabled and HWRLSINT (UART_INTSTS[26]) is set to 1, the RLS (Receive Line Status) Interrupt is caused.
* | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]) , UART PDMA receive request operation is stop. * | | |If RLS interrupt is caused by Break Error Flag BIF(UART_FIFOSTS[6]), Frame Error Flag FEF(UART_FIFO[5]) or Parity Error Flag PEF(UART_FIFOSTS[4]), UART PDMA receive request operation is stop.
* | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue. * | | |Clear Break Error Flag BIF or Frame Error Flag FEF or Parity Error Flag PEF by writing 1 to corresponding BIF, FEF and PEF to make UART PDMA receive request operation continue.
* |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit * |[18] |ABRIEN |Auto-baud Rate Interrupt Enable Bit
* | | |0 = Auto-baud rate interrupt Disabled. * | | |0 = Auto-baud rate interrupt Disabled.
@ -201,9 +207,7 @@ typedef struct
* | | |This bit defines the active level state of nRTS pin output. * | | |This bit defines the active level state of nRTS pin output.
* | | |0 = nRTS pin output is high level active. * | | |0 = nRTS pin output is high level active.
* | | |1 = nRTS pin output is low level active. (Default) * | | |1 = nRTS pin output is low level active. (Default)
* | | |Note1: Refer to Figure 6.16-13 and Figure 6.16-14 for UART function mode. * | | |Note: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
* | | |Note2: Refer to Figure 6.16-24 and Figure 6.16-25 for RS-485 function mode.
* | | |Note3: Before setting this bit, TXRXDIS (UART_FUNCSEL[3]) should be set then waited for TXRXACT (UART_FIFOSTS[31]) is cleared.
* | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller. * | | |When the configuration is done, cleared TXRXDIS (UART_FUNCSEL[3]) to activate UART controller.
* |[13] |RTSSTS |nRTS Pin Status (Read Only) * |[13] |RTSSTS |nRTS Pin Status (Read Only)
* | | |This bit mirror from nRTS pin output of voltage logic status. * | | |This bit mirror from nRTS pin output of voltage logic status.
@ -379,11 +383,11 @@ typedef struct
* | | |1 = UART wake-up interrupt flag is generated. * | | |1 = UART wake-up interrupt flag is generated.
* | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag. * | | |Note: This bit is cleared if all of TOUTWKF, RS485WKF, RFRTWKF, DATWKF and CTSWKF are cleared to 0 by writing 1 to the corresponding interrupt flag.
* |[7] |LINIF |LIN Bus Interrupt Flag * |[7] |LINIF |LIN Bus Interrupt Flag
* | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0] =1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1])) * | | |This bit is set when LIN slave header detect (SLVHDETF (UART_LINSTS[0]=1)), LIN break detect (BRKDETF(UART_LINSTS[8]=1)), bit error detect (BITEF(UART_LINSTS[9]=1)), LIN slave ID parity error (SLVIDPEF(UART_LINSTS[2] = 1)) or LIN slave header error detect (SLVHEF (UART_LINSTS[1]))
* | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated. * | | |If LINIEN (UART_INTEN [8]) is enabled the LIN interrupt will be generated.
* | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. * | | |0 = None of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
* | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated. * | | |1 = At least one of SLVHDETF, BRKDETF, BITEF, SLVIDPEF and SLVHEF is generated.
* | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing u20181' to LINIF(UART_INTSTS[7]). * | | |Note: This bit is cleared when SLVHDETF(UART_LINSTS[0]), BRKDETF(UART_LINSTS[8]), BITEF(UART_LINSTS[9]), SLVIDPEF (UART_LINSTS[2]) and SLVHEF(UART_LINSTS[1]) all are cleared and software writing 1 to LINIF(UART_INTSTS[7]).
* |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only) * |[8] |RDAINT |Receive Data Available Interrupt Indicator (Read Only)
* | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1. * | | |This bit is set if RDAIEN (UART_INTEN[0]) and RDAIF (UART_INTSTS[0]) are both set to 1.
* | | |0 = No RDA interrupt is generated. * | | |0 = No RDA interrupt is generated.
@ -425,7 +429,7 @@ typedef struct
* | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared. * | | |Note2: In UART function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]) , FEF(UART_FIFOSTS[5]) and PEF(UART_FIFOSTS[4]) are cleared.
* | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared. * | | |Note3: In RS-485 function mode, this bit is read only and reset to 0 when all bits of BIF(UART_FIFOSTS[6]), FEF(UART_FIFOSTS[5]), PEF(UART_FIFOSTS[4]) and ADDRDETF (UART_FIFOSTS[3]) are cleared.
* |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only) * |[19] |HWMODIF |PDMA Mode MODEM Interrupt Flag (Read Only)
* | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS [0] =1)). * | | |This bit is set when the nCTS pin has state change (CTSDETF (UART_MODEMSTS[0]=1)).
* | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated. * | | |If MODEMIEN (UART_INTEN [3]) is enabled, the Modem interrupt will be generated.
* | | |0 = No Modem interrupt flag is generated in PDMA mode. * | | |0 = No Modem interrupt flag is generated in PDMA mode.
* | | |1 = Modem interrupt flag is generated in PDMA mode. * | | |1 = Modem interrupt flag is generated in PDMA mode.
@ -563,7 +567,7 @@ typedef struct
* | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated. * | | |This bit is set when auto-baud rate detection function finished or the auto-baud rate counter was overflow and if ABRIEN(UART_INTEN [18]) is set then the auto-baud rate interrupt will be generated.
* | | |0 = No auto-baud rate interrupt flag is generated. * | | |0 = No auto-baud rate interrupt flag is generated.
* | | |1 = Auto-baud rate interrupt flag is generated. * | | |1 = Auto-baud rate interrupt flag is generated.
* | | |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]) * | | |Note: This bit is read only, but it can be cleared by writing 1 to ABRDTOIF (UART_FIFOSTS[2]) and ABRDIF(UART_FIFOSTS[1]).
* |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit * |[18] |ABRDEN |Auto-baud Rate Detect Enable Bit
* | | |0 = Auto-baud rate detect function Disabled. * | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled. * | | |1 = Auto-baud rate detect function Enabled.
@ -695,7 +699,7 @@ typedef struct
* | | |0 = No active. * | | |0 = No active.
* | | |1 = Receipted frame ID parity is not correct. * | | |1 = Receipted frame ID parity is not correct.
* | | |Note1: This bit can be cleared by writing 1 to it. * | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0])= 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]). * | | |Note2: This bit is only valid when in LIN slave mode (SLVEN (UART_LINCTL [0]) = 1) and enable LIN frame ID parity check function IDPEN (UART_LINCTL [9]).
* |[3] |SLVSYNCF |LIN Slave Sync Field * |[3] |SLVSYNCF |LIN Slave Sync Field
* | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode. * | | |This bit indicates that the LIN sync field is being analyzed in Automatic Resynchronization mode.
* | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit. * | | |When the receiver header have some error been detect, user must reset the internal circuit to re-search new frame header by writing 1 to this bit.
@ -709,7 +713,7 @@ typedef struct
* | | |0 = LIN break not detected. * | | |0 = LIN break not detected.
* | | |1 = LIN break detected. * | | |1 = LIN break detected.
* | | |Note1: This bit can be cleared by writing 1 to it. * | | |Note1: This bit can be cleared by writing 1 to it.
* | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) =1). * | | |Note2: This bit is only valid when LIN break detection function is enabled (BRKDETEN (UART_LINCTL[10]) = 1).
* |[9] |BITEF |Bit Error Detect Status Flag * |[9] |BITEF |Bit Error Detect Status Flag
* | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set. * | | |At TX transfer state, hardware will monitor the bus state, if the input pin (UART_RXD) state not equals to the output pin (UART_TXD) state, BITEF (UART_LINSTS[9]) will be set.
* | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated. * | | |When occur bit error, if the LINIEN (UART_INTEN[8]) = 1, an interrupt will be generated.
@ -724,7 +728,7 @@ typedef struct
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
* |[8:0] |BRCOMP |Baud Rate Compensation Patten * |[8:0] |BRCOMP |Baud Rate Compensation Patten
* | | |These 9-bits are used to define the relative bit is compensated or not. * | | |These 9-bits are used to define the relative bit is compensated or not.
* | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOM[8] is used to define the parity bit. * | | |BRCOMP[7:0] is used to define the compensation of UART_DAT[7:0] and BRCOMP[8] is used to define the parity bit.
* |[31] |BRCOMPDEC |Baud Rate Compensation Decrease * |[31] |BRCOMPDEC |Baud Rate Compensation Decrease
* | | |0 = Positive (increase one module clock) compensation for each compensated bit. * | | |0 = Positive (increase one module clock) compensation for each compensated bit.
* | | |1 = Negative (decrease one module clock) compensation for each compensated bit. * | | |1 = Negative (decrease one module clock) compensation for each compensated bit.
@ -1238,7 +1242,6 @@ typedef struct
/**@}*/ /* UART_CONST */ /**@}*/ /* UART_CONST */
/**@}*/ /* end of UART register group */ /**@}*/ /* end of UART register group */
/**@}*/ /* end of REGISTER group */
#endif /* __UART_REG_H__ */ #endif /* __UART_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/ui2c_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __UI2C_REG_H__ #ifndef __UI2C_REG_H__
#define __UI2C_REG_H__ #define __UI2C_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- I2C Mode of USCI Controller -------------------------*/ /*---------------------- I2C Mode of USCI Controller -------------------------*/
/** /**
@ -555,7 +560,6 @@ typedef struct
/**@}*/ /* UI2C_CONST */ /**@}*/ /* UI2C_CONST */
/**@}*/ /* end of UI2C register group */ /**@}*/ /* end of UI2C register group */
/**@}*/ /* end of REGISTER group */
#endif /* __UI2C_REG_H__ */ #endif /* __UI2C_REG_H__ */

8
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/usbd_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __USBD_REG_H__ #ifndef __USBD_REG_H__
#define __USBD_REG_H__ #define __USBD_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- USB Device Controller -------------------------*/ /*---------------------- USB Device Controller -------------------------*/
/** /**
@ -649,7 +654,6 @@ typedef struct
/**@}*/ /* USBD_CONST */ /**@}*/ /* USBD_CONST */
/**@}*/ /* end of USBD register group */ /**@}*/ /* end of USBD register group */
/**@}*/ /* end of REGISTER group */
#endif /* __USBD_REG_H__ */ #endif /* __USBD_REG_H__ */

91
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/usbh_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __USBH_REG_H__ #ifndef __USBH_REG_H__
#define __USBH_REG_H__ #define __USBH_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- USB Host Controller -------------------------*/ /*---------------------- USB Host Controller -------------------------*/
/** /**
@ -122,9 +128,9 @@ typedef struct
* | | |0 = The bit 15 of Frame Number didn't change. * | | |0 = The bit 15 of Frame Number didn't change.
* | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1. * | | |1 = The bit 15 of Frame Number changes from 1 to 0 or from 0 to 1.
* |[6] |RHSC |Root Hub Status Change * |[6] |RHSC |Root Hub Status Change
* | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus1 register has changed. * | | |This bit is set when the content of HcRhStatus or the content of HcRhPortStatus register has changed.
* | | |0 = The content of HcRhStatus and the content of HcRhPortStatus1 register didn't change. * | | |0 = The content of HcRhStatus and the content of HcRhPortStatus register didn't change.
* | | |1 = The content of HcRhStatus or the content of HcRhPortStatus1 register has changed. * | | |1 = The content of HcRhStatus or the content of HcRhPortStatus register has changed.
* @var USBH_T::HcInterruptEnable * @var USBH_T::HcInterruptEnable
* Offset: 0x10 Host Controller Interrupt Enable Register * Offset: 0x10 Host Controller Interrupt Enable Register
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
@ -408,8 +414,8 @@ typedef struct
* | | |Write Operation: * | | |Write Operation:
* | | |0 = No effect. * | | |0 = No effect.
* | | |1 = Clear DRWE (HcRhStatus[15]). * | | |1 = Clear DRWE (HcRhStatus[15]).
* @var USBH_T::HcRhPortStatus1 * @var USBH_T::HcRhPortStatus[2]
* Offset: 0x54 Host Controller Root Hub Port Status [1] * Offset: 0x54 Host Controller Root Hub Port Status
* --------------------------------------------------------------------------------------------------- * ---------------------------------------------------------------------------------------------------
* |Bits |Field |Descriptions * |Bits |Field |Descriptions
* | :----: | :----: | :---- | * | :----: | :----: | :---- |
@ -463,34 +469,34 @@ typedef struct
* | | |1 = Port power is Enabled. * | | |1 = Port power is Enabled.
* |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write) * |[9] |LSDA |Low Speed Device Attached (Read) or Clear Port Power (Write)
* | | |This bit defines the speed (and bud idle) of the attached device * | | |This bit defines the speed (and bud idle) of the attached device
* | | |It is only valid when CCS (HcRhPortStatus1[0]) is set. * | | |It is only valid when CCS (HcRhPortStatus[0]) is set.
* | | |This bit is also used to clear port power. * | | |This bit is also used to clear port power.
* | | |Write Operation: * | | |Write Operation:
* | | |0 = No effect. * | | |0 = No effect.
* | | |1 = Clear PPS (HcRhPortStatus1[8]). * | | |1 = Clear PPS (HcRhPortStatus[8]).
* | | |Read Operation: * | | |Read Operation:
* | | |0 = Full Speed device. * | | |0 = Full Speed device.
* | | |1 = Low-speed device. * | | |1 = Low-speed device.
* |[16] |CSC |Connect Status Change * |[16] |CSC |Connect Status Change
* | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus1[0]) changed). * | | |This bit indicates connect or disconnect event has been detected (CCS (HcRhPortStatus[0]) changed).
* | | |Write 1 to clear this bit to zero. * | | |Write 1 to clear this bit to zero.
* | | |0 = No connect/disconnect event (CCS (HcRhPortStatus1[0]) didn't change). * | | |0 = No connect/disconnect event (CCS (HcRhPortStatus[0]) didn't change).
* | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus1[0]) changed). * | | |1 = Hardware detection of connect/disconnect event (CCS (HcRhPortStatus[0]) changed).
* |[17] |PESC |Port Enable Status Change * |[17] |PESC |Port Enable Status Change
* | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus1[1]) cleared) due to a hardware event. * | | |This bit indicates that the port has been disabled (PES (HcRhPortStatus[1]) cleared) due to a hardware event.
* | | |Write 1 to clear this bit to zero. * | | |Write 1 to clear this bit to zero.
* | | |0 = PES (HcRhPortStatus1[1]) didn't change. * | | |0 = PES (HcRhPortStatus[1]) didn't change.
* | | |1 = PES (HcRhPortStatus1[1]) changed. * | | |1 = PES (HcRhPortStatus[1]) changed.
* |[18] |PSSC |Port Suspend Status Change * |[18] |PSSC |Port Suspend Status Change
* | | |This bit indicates the completion of the selective resume sequence for the port. * | | |This bit indicates the completion of the selective resume sequence for the port.
* | | |Write 1 to clear this bit to zero. * | | |Write 1 to clear this bit to zero.
* | | |0 = Port resume is not completed. * | | |0 = Port resume is not completed.
* | | |1 = Port resume completed. * | | |1 = Port resume completed.
* |[19] |OCIC |Port over Current Indicator Change * |[19] |OCIC |Port over Current Indicator Change
* | | |This bit is set when POCI (HcRhPortStatus1[3]) changes. * | | |This bit is set when POCI (HcRhPortStatus[3]) changes.
* | | |Write 1 to clear this bit to zero. * | | |Write 1 to clear this bit to zero.
* | | |0 = POCI (HcRhPortStatus1[3]) didn't change. * | | |0 = POCI (HcRhPortStatus[3]) didn't change.
* | | |1 = POCI (HcRhPortStatus1[3]) changes. * | | |1 = POCI (HcRhPortStatus[3]) changes.
* |[20] |PRSC |Port Reset Status Change * |[20] |PRSC |Port Reset Status Change
* | | |This bit indicates that the port reset signal has completed. * | | |This bit indicates that the port reset signal has completed.
* | | |Write 1 to clear this bit to zero. * | | |Write 1 to clear this bit to zero.
@ -546,8 +552,8 @@ typedef struct
__IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */ __IO uint32_t HcRhDescriptorA; /*!< [0x0048] Host Controller Root Hub Descriptor A Register */
__IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */ __IO uint32_t HcRhDescriptorB; /*!< [0x004c] Host Controller Root Hub Descriptor B Register */
__IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */ __IO uint32_t HcRhStatus; /*!< [0x0050] Host Controller Root Hub Status Register */
__IO uint32_t HcRhPortStatus1; /*!< [0x0054] Host Controller Root Hub Port Status [1] */ __IO uint32_t HcRhPortStatus[2]; /*!< [0x0054] Host Controller Root Hub Port Status */
__I uint32_t RESERVE0[106]; __I uint32_t RESERVE0[105];
__IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */ __IO uint32_t HcPhyControl; /*!< [0x0200] Host Controller PHY Control Register */
__IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */ __IO uint32_t HcMiscControl; /*!< [0x0204] Host Controller Miscellaneous Control Register */
@ -729,41 +735,41 @@ typedef struct
#define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */ #define USBH_HcRhStatus_CRWE_Pos (31) /*!< USBH_T::HcRhStatus: CRWE Position */
#define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */ #define USBH_HcRhStatus_CRWE_Msk (0x1ul << USBH_HcRhStatus_CRWE_Pos) /*!< USBH_T::HcRhStatus: CRWE Mask */
#define USBH_HcRhPortStatus1_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus1: CCS Position */ #define USBH_HcRhPortStatus_CCS_Pos (0) /*!< USBH_T::HcRhPortStatus: CCS Position */
#define USBH_HcRhPortStatus1_CCS_Msk (0x1ul << USBH_HcRhPortStatus1_CCS_Pos) /*!< USBH_T::HcRhPortStatus1: CCS Mask */ #define USBH_HcRhPortStatus_CCS_Msk (0x1ul << USBH_HcRhPortStatus_CCS_Pos) /*!< USBH_T::HcRhPortStatus: CCS Mask */
#define USBH_HcRhPortStatus1_PES_Pos (1) /*!< USBH_T::HcRhPortStatus1: PES Position */ #define USBH_HcRhPortStatus_PES_Pos (1) /*!< USBH_T::HcRhPortStatus: PES Position */
#define USBH_HcRhPortStatus1_PES_Msk (0x1ul << USBH_HcRhPortStatus1_PES_Pos) /*!< USBH_T::HcRhPortStatus1: PES Mask */ #define USBH_HcRhPortStatus_PES_Msk (0x1ul << USBH_HcRhPortStatus_PES_Pos) /*!< USBH_T::HcRhPortStatus: PES Mask */
#define USBH_HcRhPortStatus1_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus1: PSS Position */ #define USBH_HcRhPortStatus_PSS_Pos (2) /*!< USBH_T::HcRhPortStatus: PSS Position */
#define USBH_HcRhPortStatus1_PSS_Msk (0x1ul << USBH_HcRhPortStatus1_PSS_Pos) /*!< USBH_T::HcRhPortStatus1: PSS Mask */ #define USBH_HcRhPortStatus_PSS_Msk (0x1ul << USBH_HcRhPortStatus_PSS_Pos) /*!< USBH_T::HcRhPortStatus: PSS Mask */
#define USBH_HcRhPortStatus1_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus1: POCI Position */ #define USBH_HcRhPortStatus_POCI_Pos (3) /*!< USBH_T::HcRhPortStatus: POCI Position */
#define USBH_HcRhPortStatus1_POCI_Msk (0x1ul << USBH_HcRhPortStatus1_POCI_Pos) /*!< USBH_T::HcRhPortStatus1: POCI Mask */ #define USBH_HcRhPortStatus_POCI_Msk (0x1ul << USBH_HcRhPortStatus_POCI_Pos) /*!< USBH_T::HcRhPortStatus: POCI Mask */
#define USBH_HcRhPortStatus1_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus1: PRS Position */ #define USBH_HcRhPortStatus_PRS_Pos (4) /*!< USBH_T::HcRhPortStatus: PRS Position */
#define USBH_HcRhPortStatus1_PRS_Msk (0x1ul << USBH_HcRhPortStatus1_PRS_Pos) /*!< USBH_T::HcRhPortStatus1: PRS Mask */ #define USBH_HcRhPortStatus_PRS_Msk (0x1ul << USBH_HcRhPortStatus_PRS_Pos) /*!< USBH_T::HcRhPortStatus: PRS Mask */
#define USBH_HcRhPortStatus1_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus1: PPS Position */ #define USBH_HcRhPortStatus_PPS_Pos (8) /*!< USBH_T::HcRhPortStatus: PPS Position */
#define USBH_HcRhPortStatus1_PPS_Msk (0x1ul << USBH_HcRhPortStatus1_PPS_Pos) /*!< USBH_T::HcRhPortStatus1: PPS Mask */ #define USBH_HcRhPortStatus_PPS_Msk (0x1ul << USBH_HcRhPortStatus_PPS_Pos) /*!< USBH_T::HcRhPortStatus: PPS Mask */
#define USBH_HcRhPortStatus1_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus1: LSDA Position */ #define USBH_HcRhPortStatus_LSDA_Pos (9) /*!< USBH_T::HcRhPortStatus: LSDA Position */
#define USBH_HcRhPortStatus1_LSDA_Msk (0x1ul << USBH_HcRhPortStatus1_LSDA_Pos) /*!< USBH_T::HcRhPortStatus1: LSDA Mask */ #define USBH_HcRhPortStatus_LSDA_Msk (0x1ul << USBH_HcRhPortStatus_LSDA_Pos) /*!< USBH_T::HcRhPortStatus: LSDA Mask */
#define USBH_HcRhPortStatus1_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus1: CSC Position */ #define USBH_HcRhPortStatus_CSC_Pos (16) /*!< USBH_T::HcRhPortStatus: CSC Position */
#define USBH_HcRhPortStatus1_CSC_Msk (0x1ul << USBH_HcRhPortStatus1_CSC_Pos) /*!< USBH_T::HcRhPortStatus1: CSC Mask */ #define USBH_HcRhPortStatus_CSC_Msk (0x1ul << USBH_HcRhPortStatus_CSC_Pos) /*!< USBH_T::HcRhPortStatus: CSC Mask */
#define USBH_HcRhPortStatus1_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus1: PESC Position */ #define USBH_HcRhPortStatus_PESC_Pos (17) /*!< USBH_T::HcRhPortStatus: PESC Position */
#define USBH_HcRhPortStatus1_PESC_Msk (0x1ul << USBH_HcRhPortStatus1_PESC_Pos) /*!< USBH_T::HcRhPortStatus1: PESC Mask */ #define USBH_HcRhPortStatus_PESC_Msk (0x1ul << USBH_HcRhPortStatus_PESC_Pos) /*!< USBH_T::HcRhPortStatus: PESC Mask */
#define USBH_HcRhPortStatus1_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus1: PSSC Position */ #define USBH_HcRhPortStatus_PSSC_Pos (18) /*!< USBH_T::HcRhPortStatus: PSSC Position */
#define USBH_HcRhPortStatus1_PSSC_Msk (0x1ul << USBH_HcRhPortStatus1_PSSC_Pos) /*!< USBH_T::HcRhPortStatus1: PSSC Mask */ #define USBH_HcRhPortStatus_PSSC_Msk (0x1ul << USBH_HcRhPortStatus_PSSC_Pos) /*!< USBH_T::HcRhPortStatus: PSSC Mask */
#define USBH_HcRhPortStatus1_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus1: OCIC Position */ #define USBH_HcRhPortStatus_OCIC_Pos (19) /*!< USBH_T::HcRhPortStatus: OCIC Position */
#define USBH_HcRhPortStatus1_OCIC_Msk (0x1ul << USBH_HcRhPortStatus1_OCIC_Pos) /*!< USBH_T::HcRhPortStatus1: OCIC Mask */ #define USBH_HcRhPortStatus_OCIC_Msk (0x1ul << USBH_HcRhPortStatus_OCIC_Pos) /*!< USBH_T::HcRhPortStatus: OCIC Mask */
#define USBH_HcRhPortStatus1_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus1: PRSC Position */ #define USBH_HcRhPortStatus_PRSC_Pos (20) /*!< USBH_T::HcRhPortStatus: PRSC Position */
#define USBH_HcRhPortStatus1_PRSC_Msk (0x1ul << USBH_HcRhPortStatus1_PRSC_Pos) /*!< USBH_T::HcRhPortStatus1: PRSC Mask */ #define USBH_HcRhPortStatus_PRSC_Msk (0x1ul << USBH_HcRhPortStatus_PRSC_Pos) /*!< USBH_T::HcRhPortStatus: PRSC Mask */
#define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */ #define USBH_HcPhyControl_STBYEN_Pos (27) /*!< USBH_T::HcPhyControl: STBYEN Position */
#define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */ #define USBH_HcPhyControl_STBYEN_Msk (0x1ul << USBH_HcPhyControl_STBYEN_Pos) /*!< USBH_T::HcPhyControl: STBYEN Mask */
@ -779,5 +785,6 @@ typedef struct
/**@}*/ /* USBH_CONST */ /**@}*/ /* USBH_CONST */
/**@}*/ /* end of USBH register group */ /**@}*/ /* end of USBH register group */
/**@}*/ /* end of REGISTER group */
#endif /* __USBH_REG_H__ */ #endif /* __USBH_REG_H__ */

7
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/uspi_reg.h
View File

@ -8,6 +8,12 @@
#ifndef __USPI_REG_H__ #ifndef __USPI_REG_H__
#define __USPI_REG_H__ #define __USPI_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- SPI Mode of USCI Controller -------------------------*/ /*---------------------- SPI Mode of USCI Controller -------------------------*/
/** /**
@ -652,6 +658,7 @@ typedef struct
/**@}*/ /* USPI_CONST */ /**@}*/ /* USPI_CONST */
/**@}*/ /* end of USPI register group */ /**@}*/ /* end of USPI register group */
/**@}*/ /* end of REGISTER group */
#endif /* __USPI_REG_H__ */ #endif /* __USPI_REG_H__ */

12
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/uuart_reg.h
View File

@ -8,6 +8,11 @@
#ifndef __UUART_REG_H__ #ifndef __UUART_REG_H__
#define __UUART_REG_H__ #define __UUART_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- UART Mode of USCI Controller -------------------------*/ /*---------------------- UART Mode of USCI Controller -------------------------*/
@ -304,7 +309,7 @@ typedef struct
* | | |0 = Auto-baud rate detect function Disabled. * | | |0 = Auto-baud rate detect function Disabled.
* | | |1 = Auto-baud rate detect function Enabled. * | | |1 = Auto-baud rate detect function Enabled.
* | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit. * | | |Note: When the auto - baud rate detect operation finishes, hardware will clear this bit.
* | | |The associated interrupt ABRDETIF (UUART_PROTST[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled). * | | |The associated interrupt ABRDETIF (UUART_PROTSTS[9]) will be generated (If ARBIEN (UUART_PROTIEN [1]) is enabled).
* |[9] |DATWKEN |Data Wake-up Mode Enable Bit * |[9] |DATWKEN |Data Wake-up Mode Enable Bit
* | | |0 = Data wake-up mode Disabled. * | | |0 = Data wake-up mode Disabled.
* | | |1 = Data wake-up mode Enabled. * | | |1 = Data wake-up mode Enabled.
@ -318,7 +323,7 @@ typedef struct
* | | |The order of the bus shall be 1 and 0 step by step (e.g * | | |The order of the bus shall be 1 and 0 step by step (e.g
* | | |the input data pattern shall be 0x55) * | | |the input data pattern shall be 0x55)
* | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set. * | | |The user can read the value to know the current input baud rate of the bus whenever the ABRDETIF (UUART_PROTCTL[9]) is set.
* | | |Note: This bit can be cleared to 0 by software writing u20180' to the BRDETITV. * | | |Note: This bit can be cleared to 0 by software writing 1 to the BRDETITV.
* |[26] |STICKEN |Stick Parity Enable Bit * |[26] |STICKEN |Stick Parity Enable Bit
* | | |0 = Stick parity Disabled. * | | |0 = Stick parity Disabled.
* | | |1 = Stick parity Enabled. * | | |1 = Stick parity Enabled.
@ -649,7 +654,6 @@ typedef struct
/**@}*/ /* UUART_CONST */ /**@}*/ /* UUART_CONST */
/**@}*/ /* end of UUART register group */ /**@}*/ /* end of UUART register group */
/**@}*/ /* end of REGISTER group */
#endif /* __UUART_REG_H__ */ #endif /* __UUART_REG_H__ */

9
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/wdt_reg.h
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@ -8,6 +8,12 @@
#ifndef __WDT_REG_H__ #ifndef __WDT_REG_H__
#define __WDT_REG_H__ #define __WDT_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Watch Dog Timer Controller -------------------------*/ /*---------------------- Watch Dog Timer Controller -------------------------*/
/** /**
@ -162,7 +168,6 @@ typedef struct
/**@}*/ /* WDT_CONST */ /**@}*/ /* WDT_CONST */
/**@}*/ /* end of WDT register group */ /**@}*/ /* end of WDT register group */
/**@}*/ /* end of REGISTER group */
#endif /* __WDT_REG_H__ */ #endif /* __WDT_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/Reg/wwdt_reg.h
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@ -8,6 +8,11 @@
#ifndef __WWDT_REG_H__ #ifndef __WWDT_REG_H__
#define __WWDT_REG_H__ #define __WWDT_REG_H__
/** @addtogroup REGISTER Control Register
@{
*/
/*---------------------- Window Watchdog Timer -------------------------*/ /*---------------------- Window Watchdog Timer -------------------------*/
@ -135,5 +140,6 @@ typedef struct
/**@}*/ /* WWDT_CONST */ /**@}*/ /* WWDT_CONST */
/**@}*/ /* end of WWDT register group */ /**@}*/ /* end of WWDT register group */
/**@}*/ /* end of REGISTER group */
#endif /* __WWDT_REG_H__ */ #endif /* __WWDT_REG_H__ */

6
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_acmp.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_acmp.h
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@ -1,9 +1,7 @@
/**************************************************************************//** /**************************************************************************//**
* @file ACMP.h * @file ACMP.h
* @version V0.10 * @version V3.00
* $Revision: 1 $ * @brief M2351 Series ACMP Driver Header File
* $Date: 16/07/07 7:50p $
* @brief M0564 Series ACMP Driver Header File
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.

12
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_bpwm.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_bpwm.h
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@ -4,7 +4,7 @@
* @brief M2351 series BPWM driver header file * @brief M2351 series BPWM driver header file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#ifndef __BPWM_H__ #ifndef __BPWM_H__
#define __BPWM_H__ #define __BPWM_H__
@ -83,14 +83,14 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* Duty Interrupt Type Constant Definitions */ /* Duty Interrupt Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPDIENn_Pos) /*!< BPWM duty interrupt triggered if down count match comparator \hideinitializer */ #define BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPDIEN0_Pos) /*!< BPWM duty interrupt triggered if down count match comparator \hideinitializer */
#define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPUIENn_Pos) /*!< BPWM duty interrupt triggered if up down match comparator \hideinitializer */ #define BPWM_DUTY_INT_UP_COUNT_MATCH_CMP (1 << BPWM_INTEN_CMPUIEN0_Pos) /*!< BPWM duty interrupt triggered if up down match comparator \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* Load Mode Constant Definitions */ /* Load Mode Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define BPWM_LOAD_MODE_IMMEDIATE (1 << BPWM_CTL0_IMMLDENn_Pos) /*!< BPWM immediately load mode \hideinitializer */ #define BPWM_LOAD_MODE_IMMEDIATE (1 << BPWM_CTL0_IMMLDEN0_Pos) /*!< BPWM immediately load mode \hideinitializer */
#define BPWM_LOAD_MODE_CENTER (1 << BPWM_CTL0_CTRLDn_Pos) /*!< BPWM center load mode \hideinitializer */ #define BPWM_LOAD_MODE_CENTER (1 << BPWM_CTL0_CTRLD0_Pos) /*!< BPWM center load mode \hideinitializer */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* Clock Source Select Constant Definitions */ /* Clock Source Select Constant Definitions */
@ -359,4 +359,4 @@ void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum);
#endif /* __BPWM_H__ */ #endif /* __BPWM_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

8
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_can.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_can.h
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@ -45,10 +45,10 @@ extern "C"
#define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */ #define CAN_REMOTE_FRAME 0 /*!< CAN frame select remote frame */
#define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */ #define CAN_DATA_FRAME 1 /*!< CAN frame select data frame */
/*@}*/ /* end of group M2351_CAN_EXPORTED_CONSTANTS */ /*@}*/ /* end of group CAN_EXPORTED_CONSTANTS */
/** @addtogroup M2351_CAN_EXPORTED_STRUCTS CAN Exported Structs /** @addtogroup CAN_EXPORTED_STRUCTS CAN Exported Structs
@{ @{
*/ */
/** /**
@ -74,13 +74,13 @@ typedef struct
uint8_t u8IdType; /*!< ID type*/ uint8_t u8IdType; /*!< ID type*/
} STR_CANMASK_T; } STR_CANMASK_T;
/*@}*/ /* end of group M2351_CAN_EXPORTED_STRUCTS */ /*@}*/ /* end of group CAN_EXPORTED_STRUCTS */
/** @cond HIDDEN_SYMBOLS */ /** @cond HIDDEN_SYMBOLS */
#define MSG(id) (id) #define MSG(id) (id)
/** @endcond HIDDEN_SYMBOLS */ /** @endcond HIDDEN_SYMBOLS */
/** @addtogroup M2351_CAN_EXPORTED_FUNCTIONS CAN Exported Functions /** @addtogroup CAN_EXPORTED_FUNCTIONS CAN Exported Functions
@{ @{
*/ */

109
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_clk.h
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@ -75,8 +75,6 @@ extern "C"
#define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */ #define CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 (0x2UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as HCLK/2048 */
#define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LIRC */ #define CLK_CLKSEL1_WDTSEL_LIRC (0x3UL<<CLK_CLKSEL1_WDTSEL_Pos) /*!< Setting WDT clock source as LIRC */
#define CLK_CLKSEL1_DSRCSEL_HIRC (0x1UL<<CLK_CLKSEL1_DSRCSEL_Pos) /*!< Setting DSRC clock source as HIRC */
#define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */ #define CLK_CLKSEL1_TMR0SEL_HXT (0x0UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as HXT */
#define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */ #define CLK_CLKSEL1_TMR0SEL_LXT (0x1UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as LXT */
#define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */ #define CLK_CLKSEL1_TMR0SEL_PCLK0 (0x2UL<<CLK_CLKSEL1_TMR0SEL_Pos) /*!< Setting Timer 0 clock source as PCLK0 */
@ -158,11 +156,6 @@ extern "C"
#define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK0 */ #define CLK_CLKSEL2_SPI3SEL_PCLK0 (0x2UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as PCLK0 */
#define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HIRC */ #define CLK_CLKSEL2_SPI3SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI3SEL_Pos) /*!< Setting SPI3 clock source as HIRC */
#define CLK_CLKSEL2_SPI5SEL_HXT (0x0UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as HXT */
#define CLK_CLKSEL2_SPI5SEL_PLL (0x1UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as PLL */
#define CLK_CLKSEL2_SPI5SEL_PCLK1 (0x2UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as PCLK1 */
#define CLK_CLKSEL2_SPI5SEL_HIRC (0x3UL<<CLK_CLKSEL2_SPI5SEL_Pos) /*!< Setting SPI5 clock source as HIRC */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* CLKSEL3 constant definitions. */ /* CLKSEL3 constant definitions. */
@ -228,7 +221,6 @@ extern "C"
#define CLK_CLKDIV1_SC0(x) (((x)-1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */ #define CLK_CLKDIV1_SC0(x) (((x)-1UL) << CLK_CLKDIV1_SC0DIV_Pos) /*!< CLKDIV1 Setting for SC0 clock divider. It could be 1~256 */
#define CLK_CLKDIV1_SC1(x) (((x)-1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 */ #define CLK_CLKDIV1_SC1(x) (((x)-1UL) << CLK_CLKDIV1_SC1DIV_Pos) /*!< CLKDIV1 Setting for SC1 clock divider. It could be 1~256 */
#define CLK_CLKDIV1_SC2(x) (((x)-1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 */ #define CLK_CLKDIV1_SC2(x) (((x)-1UL) << CLK_CLKDIV1_SC2DIV_Pos) /*!< CLKDIV1 Setting for SC2 clock divider. It could be 1~256 */
#define CLK_CLKDIV1_DSRC(x) (((x)-1UL) << CLK_CLKDIV1_DSRCDIV_Pos) /*!< CLKDIV1 Setting for DSRC clock divider. It could be 1~64 */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
@ -243,17 +235,31 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* PCLKDIV constant definitions. */ /* PCLKDIV constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define CLK_PCLKDIV_APB0DIV_HCLK (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK */ #define CLK_PCLKDIV_APB0DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK */ #define CLK_PCLKDIV_APB0DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK */
#define CLK_PCLKDIV_APB0DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK */
#define CLK_PCLKDIV_APB0DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK */
#define CLK_PCLKDIV_APB0DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK */
#define CLK_PCLKDIV_APB0DIV_DIV32 (0x5UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/32 HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK (0x0UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK_DIV2 (0x1UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/2 HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK */ #define CLK_PCLKDIV_APB0DIV_HCLK_DIV4 (0x2UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/4 HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK */ #define CLK_PCLKDIV_APB0DIV_HCLK_DIV8 (0x3UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/8 HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK */ #define CLK_PCLKDIV_APB0DIV_HCLK_DIV16 (0x4UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/16 HCLK */
#define CLK_PCLKDIV_APB0DIV_HCLK_DIV32 (0x5UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/32 HCLK */ #define CLK_PCLKDIV_APB0DIV_HCLK_DIV32 (0x5UL << CLK_PCLKDIV_APB0DIV_Pos) /*!< PCLKDIV Setting for PCLK0 = 1/32 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK */ #define CLK_PCLKDIV_APB1DIV_DIV1 (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK */ #define CLK_PCLKDIV_APB1DIV_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK */ #define CLK_PCLKDIV_APB1DIV_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK */ #define CLK_PCLKDIV_APB1DIV_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK */
#define CLK_PCLKDIV_APB1DIV_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK */
#define CLK_PCLKDIV_APB1DIV_DIV32 (0x5UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/32 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK (0x0UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV2 (0x1UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/2 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV4 (0x2UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/4 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV8 (0x3UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/8 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK */ #define CLK_PCLKDIV_APB1DIV_HCLK_DIV16 (0x4UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/16 HCLK */
#define CLK_PCLKDIV_APB1DIV_HCLK_DIV32 (0x5UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/32 HCLK */ #define CLK_PCLKDIV_APB1DIV_HCLK_DIV32 (0x5UL << CLK_PCLKDIV_APB1DIV_Pos) /*!< PCLKDIV Setting for PCLK1 = 1/32 HCLK */
@ -280,6 +286,9 @@ extern "C"
#define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT */ #define CLK_PLLCTL_96MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HXT */
#define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HIRC */ #define CLK_PLLCTL_96MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(2UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_2) /*!< Predefined PLLCTL setting for 96MHz PLL output with HIRC */
#define CLK_PLLCTL_128MHz_HXT (CLK_PLLCTL_PLLSRC_HXT | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 128MHz PLL output with HXT */
#define CLK_PLLCTL_128MHz_HIRC (CLK_PLLCTL_PLLSRC_HIRC | CLK_PLLCTL_NR(3UL) | CLK_PLLCTL_NF(16UL) | CLK_PLLCTL_NO_1) /*!< Predefined PLLCTL setting for 128MHz PLL output with HIRC */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* MODULE constant definitions. */ /* MODULE constant definitions. */
@ -330,12 +339,16 @@ extern "C"
#define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\ #define CRC_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRCCKEN_Pos)|\
MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRC Module */
#define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\ #define CRPT_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_CRPTCKEN_Pos)|\
MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CRPT Module */
#define FMCIDLE_MODULE (MODULE_APBCLK_ENC( 0)|MODULE_IP_EN_Pos_ENC(CLK_AHBCLK_FMCIDLE_Pos)|\
MODULE_CLKSEL_ENC(NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC(NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< FMCIDLE Module */
#define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\ #define USBH_MODULE (MODULE_APBCLK_ENC( 0UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_AHBCLK_USBHCKEN_Pos)|\
MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\ MODULE_CLKSEL_ENC( 0UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 8UL)|\
MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */ MODULE_CLKDIV_ENC( 0UL)|MODULE_CLKDIV_Msk_ENC(0xFUL)|MODULE_CLKDIV_Pos_ENC( 4UL)) /*!< USBH Module */
@ -429,10 +442,6 @@ extern "C"
MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\ MODULE_CLKSEL_ENC( 3UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(30UL)|\
MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */ MODULE_CLKDIV_ENC( 3UL)|MODULE_CLKDIV_Msk_ENC(0x0FUL)|MODULE_CLKDIV_Pos_ENC(12UL)) /*!< UART5 Module */
#define DSRC_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_DSRCCKEN_Pos)|\
MODULE_CLKSEL_ENC( 1UL)|MODULE_CLKSEL_Msk_ENC( 1UL)|MODULE_CLKSEL_Pos_ENC( 3UL)|\
MODULE_CLKDIV_ENC( 1UL)|MODULE_CLKDIV_Msk_ENC(0x1FUL)|MODULE_CLKDIV_Pos_ENC(24UL)) /*!< DSRC Module */
#define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\ #define CAN0_MODULE (MODULE_APBCLK_ENC( 1UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK0_CAN0CKEN_Pos)|\
MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< CAN0 Module */
@ -470,10 +479,6 @@ extern "C"
MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\ MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(12UL)|\
MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI3 Module */
#define SPI5_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_SPI5CKEN_Pos)|\
MODULE_CLKSEL_ENC( 2UL)|MODULE_CLKSEL_Msk_ENC( 3UL)|MODULE_CLKSEL_Pos_ENC(14UL)|\
MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< SPI5 Module */
#define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\ #define USCI0_MODULE (MODULE_APBCLK_ENC( 2UL)|MODULE_IP_EN_Pos_ENC((uint32_t)CLK_APBCLK1_USCI0CKEN_Pos)|\
MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\ MODULE_CLKSEL_ENC( NA)|MODULE_CLKSEL_Msk_ENC(NA)|MODULE_CLKSEL_Pos_ENC(NA)|\
MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */ MODULE_CLKDIV_ENC( NA)|MODULE_CLKDIV_Msk_ENC(NA)|MODULE_CLKDIV_Pos_ENC(NA)) /*!< USCI0 Module */
@ -526,24 +531,24 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* PDMSEL constant definitions. */ /* PDMSEL constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Power-down mode */ #define CLK_PMUCTL_PDMSEL_PD (0x0UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Power-down mode */
#define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Low leakage Power-down mode */ #define CLK_PMUCTL_PDMSEL_LLPD (0x1UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Low leakage Power-down mode */
#define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Fast Wake-up Power-down mode */ #define CLK_PMUCTL_PDMSEL_FWPD (0x2UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Fast Wake-up Power-down mode */
#define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Ultra Low leakage Power-down mode */ #define CLK_PMUCTL_PDMSEL_ULLPD (0x3UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Ultra Low leakage Power-down mode */
#define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Standby Power-down mode */ #define CLK_PMUCTL_PDMSEL_SPD (0x4UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Standby Power-down mode */
#define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select power down mdoe is Deep Power-down mode */ #define CLK_PMUCTL_PDMSEL_DPD (0x6UL << CLK_PMUCTL_PDMSEL_Pos) /*!< Select Power-down mode is Deep Power-down mode */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* WKTMRIS constant definitions. */ /* WKTMRIS constant definitions. */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 OSC10K clocks (12.8 ms) */ #define CLK_PMUCTL_WKTMRIS_128 (0x0UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 128 LIRC clocks (12.8 ms) */
#define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 OSC10K clocks (25.6 ms) */ #define CLK_PMUCTL_WKTMRIS_256 (0x1UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 256 LIRC clocks (25.6 ms) */
#define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 OSC10K clocks (51.2 ms) */ #define CLK_PMUCTL_WKTMRIS_512 (0x2UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 512 LIRC clocks (51.2 ms) */
#define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 OSC10K clocks (102.4ms) */ #define CLK_PMUCTL_WKTMRIS_1024 (0x3UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 1024 LIRC clocks (102.4ms) */
#define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 OSC10K clocks (409.6ms) */ #define CLK_PMUCTL_WKTMRIS_4096 (0x4UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 4096 LIRC clocks (409.6ms) */
#define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 OSC10K clocks (819.2ms) */ #define CLK_PMUCTL_WKTMRIS_8192 (0x5UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 8192 LIRC clocks (819.2ms) */
#define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 OSC10K clocks (1638.4ms) */ #define CLK_PMUCTL_WKTMRIS_16384 (0x6UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 16384 LIRC clocks (1638.4ms) */
#define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 OSC10K clocks (6553.6ms) */ #define CLK_PMUCTL_WKTMRIS_65536 (0x7UL << CLK_PMUCTL_WKTMRIS_Pos) /*!< Select Wake-up Timer Time-out Interval is 65536 LIRC clocks (6553.6ms) */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* SWKDBCLKSEL constant definitions. */ /* SWKDBCLKSEL constant definitions. */
@ -601,7 +606,7 @@ extern "C"
/** /**
* @brief Set Wake-up Timer Time-out Interval * @brief Set Wake-up Timer Time-out Interval
* *
* @param[in] u32Interval The de-bounce sampling cycle selection. It could be * @param[in] u32Interval The Wake-up Timer Time-out Interval selection. It could be
* - \ref CLK_PMUCTL_WKTMRIS_128 * - \ref CLK_PMUCTL_WKTMRIS_128
* - \ref CLK_PMUCTL_WKTMRIS_256 * - \ref CLK_PMUCTL_WKTMRIS_256
* - \ref CLK_PMUCTL_WKTMRIS_512 * - \ref CLK_PMUCTL_WKTMRIS_512
@ -642,7 +647,7 @@ extern "C"
* *
* @return None * @return None
* *
* @details This function set Set De-bounce Sampling Cycle Time. * @details This function set Set De-bounce Sampling Cycle Time for Standby Power-down pin wake-up.
* *
* *
*/ */
@ -721,24 +726,24 @@ __STATIC_INLINE void CLK_SysTickDelay_NS(uint32_t us)
*/ */
__STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us) __STATIC_INLINE void CLK_SysTickLongDelay(uint32_t us)
{ {
uint32_t delay; uint32_t u32Delay;
/* It should <= 65536us for each delay loop */ /* It should <= 65536us for each delay loop */
delay = 65536UL; u32Delay = 65536UL;
do do
{ {
if(us > delay) if(us > u32Delay)
{ {
us -= delay; us -= u32Delay;
} }
else else
{ {
delay = us; u32Delay = us;
us = 0UL; us = 0UL;
} }
SysTick->LOAD = delay * CyclesPerUs; SysTick->LOAD = u32Delay * CyclesPerUs;
SysTick->VAL = (0x0UL); SysTick->VAL = (0x0UL);
SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;
@ -767,24 +772,24 @@ __STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us);
*/ */
__STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us) __STATIC_INLINE void CLK_SysTickLongDelay_NS(uint32_t us)
{ {
uint32_t delay; uint32_t u32Delay;
/* It should <= 65536us for each delay loop */ /* It should <= 65536us for each delay loop */
delay = 65536UL; u32Delay = 65536UL;
do do
{ {
if(us > delay) if(us > u32Delay)
{ {
us -= delay; us -= u32Delay;
} }
else else
{ {
delay = us; u32Delay = us;
us = 0UL; us = 0UL;
} }
SysTick_NS->LOAD = delay * CyclesPerUs; SysTick_NS->LOAD = u32Delay * CyclesPerUs;
SysTick_NS->VAL = (0x0UL); SysTick_NS->VAL = (0x0UL);
SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk; SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | SysTick_CTRL_ENABLE_Msk;

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_crc.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_crc.h
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0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_crypto.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_crypto.h
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4
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_dac.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_dac.h
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@ -4,7 +4,7 @@
* @brief M2351 series DAC driver header file * @brief M2351 series DAC driver header file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#ifndef __DAC_H__ #ifndef __DAC_H__
#define __DAC_H__ #define __DAC_H__
@ -253,4 +253,4 @@ uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay);
#endif /* __DAC_H__ */ #endif /* __DAC_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

4
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_eadc.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_eadc.h
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@ -4,7 +4,7 @@
* @brief M2351 series EADC driver header file * @brief M2351 series EADC driver header file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#ifndef __EADC_H__ #ifndef __EADC_H__
#define __EADC_H__ #define __EADC_H__
@ -551,4 +551,4 @@ void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32E
#endif /* __EADC_H__ */ #endif /* __EADC_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

1
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_ebi.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_ebi.h
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@ -264,6 +264,7 @@ extern "C"
/** /**
* @brief Write 8-bit data to EBI bank2 * @brief Write 8-bit data to EBI bank2
* *
* @param[in] ebi The pointer of EBI module.
* @param[in] u32Addr The data address on EBI bank2. * @param[in] u32Addr The data address on EBI bank2.
* @param[in] u32Data Specify data to be written. * @param[in] u32Data Specify data to be written.
* *

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_ecap.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_ecap.h
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8
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_epwm.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_epwm.h
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@ -4,7 +4,7 @@
* @brief M2351 series EPWM driver header file * @brief M2351 series EPWM driver header file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#ifndef __EPWM_H__ #ifndef __EPWM_H__
#define __EPWM_H__ #define __EPWM_H__
@ -95,7 +95,7 @@ extern "C"
#define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */ #define EPWM_FB_EDGE_ACMP1 (EPWM_BRKCTL0_1_CPO1EBEN_Msk) /*!< Comparator 1 as edge-detect fault brake source */
#define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */ #define EPWM_FB_EDGE_BKP0 (EPWM_BRKCTL0_1_BRKP0EEN_Msk) /*!< BKP0 pin as edge-detect fault brake source */
#define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */ #define EPWM_FB_EDGE_BKP1 (EPWM_BRKCTL0_1_BRKP1EEN_Msk) /*!< BKP1 pin as edge-detect fault brake source */
#define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_ADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source */ #define EPWM_FB_EDGE_ADCRM (EPWM_BRKCTL0_1_EADCEBEN_Msk) /*!< ADC Result Monitor (ADCRM) as edge-detect fault brake source */
#define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */ #define EPWM_FB_EDGE_SYS_CSS (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as edge-detect fault brake source */
#define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */ #define EPWM_FB_EDGE_SYS_BOD (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as edge-detect fault brake source */
#define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */ #define EPWM_FB_EDGE_SYS_RAM (EPWM_BRKCTL0_1_SYSEBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as edge-detect fault brake source */
@ -105,7 +105,7 @@ extern "C"
#define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */ #define EPWM_FB_LEVEL_ACMP1 (EPWM_BRKCTL0_1_CPO1LBEN_Msk) /*!< Comparator 1 as level-detect fault brake source */
#define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */ #define EPWM_FB_LEVEL_BKP0 (EPWM_BRKCTL0_1_BRKP0LEN_Msk) /*!< BKP0 pin as level-detect fault brake source */
#define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */ #define EPWM_FB_LEVEL_BKP1 (EPWM_BRKCTL0_1_BRKP1LEN_Msk) /*!< BKP1 pin as level-detect fault brake source */
#define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_ADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source */ #define EPWM_FB_LEVEL_ADCRM (EPWM_BRKCTL0_1_EADCLBEN_Msk) /*!< ADC Result Monitor (ADCRM) as level-detect fault brake source */
#define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */ #define EPWM_FB_LEVEL_SYS_CSS (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_CSSBRKEN_Msk) /*!< System fail condition: clock security system detection as level-detect fault brake source */
#define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */ #define EPWM_FB_LEVEL_SYS_BOD (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_BODBRKEN_Msk) /*!< System fail condition: brown-out detection as level-detect fault brake source */
#define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */ #define EPWM_FB_LEVEL_SYS_RAM (EPWM_BRKCTL0_1_SYSLBEN_Msk | EPWM_FAILBRK_RAMBRKEN_Msk) /*!< System fail condition: SRAM parity error detection as level-detect fault brake source */
@ -627,4 +627,4 @@ void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum);
#endif /* __EPWM_H__ */ #endif /* __EPWM_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

2
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_fmc.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_fmc.h
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@ -474,7 +474,7 @@ extern int32_t FMC_CompareSPKey(uint32_t key[3]);
extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM); extern int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, const int32_t lock_CONFIG, const int32_t lock_SPROM);
extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data); extern void FMC_Write(uint32_t u32Addr, uint32_t u32Data);
extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1); extern int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1);
extern int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count); extern int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count);
extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); extern int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);
extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word); extern int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word);
extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len); extern int32_t FMC_WriteMultipleA(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len);

375
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_gpio.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_gpio.h
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@ -60,7 +60,7 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* GPIO Slew Rate Type Constant Definitions */ /* GPIO Slew Rate Type Constant Definitions */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for nornal Mode */ #define GPIO_SLEWCTL_NORMAL 0x0UL /*!< GPIO slew setting for normal Mode */
#define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */ #define GPIO_SLEWCTL_HIGH 0x1UL /*!< GPIO slew setting for high Mode */
#define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */ #define GPIO_SLEWCTL_FAST 0x2UL /*!< GPIO slew setting for fast Mode */
@ -114,114 +114,270 @@ extern "C"
* *
* If PA.0 pin status is high, then set PA.0 data output to low. * If PA.0 pin status is high, then set PA.0 data output to low.
*/ */
#define GPIO_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2)))) #if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT0 )
#define PA0 GPIO_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */ # define PA_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#define PA1 GPIO_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */ #else
#define PA2 GPIO_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */ # define PA_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PA3 GPIO_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */ #endif
#define PA4 GPIO_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */ #define PA0 PA_PIN_DATA(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
#define PA5 GPIO_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */ #define PA1 PA_PIN_DATA(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
#define PA6 GPIO_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */ #define PA2 PA_PIN_DATA(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
#define PA7 GPIO_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */ #define PA3 PA_PIN_DATA(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
#define PA8 GPIO_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */ #define PA4 PA_PIN_DATA(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
#define PA9 GPIO_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */ #define PA5 PA_PIN_DATA(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
#define PA10 GPIO_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */ #define PA6 PA_PIN_DATA(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
#define PA11 GPIO_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */ #define PA7 PA_PIN_DATA(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
#define PA12 GPIO_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */ #define PA8 PA_PIN_DATA(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
#define PA13 GPIO_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */ #define PA9 PA_PIN_DATA(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
#define PA14 GPIO_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */ #define PA10 PA_PIN_DATA(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
#define PA15 GPIO_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */ #define PA11 PA_PIN_DATA(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
#define PB0 GPIO_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */ #define PA12 PA_PIN_DATA(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
#define PB1 GPIO_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */ #define PA13 PA_PIN_DATA(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
#define PB2 GPIO_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */ #define PA14 PA_PIN_DATA(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
#define PB3 GPIO_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */ #define PA15 PA_PIN_DATA(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
#define PB4 GPIO_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
#define PB5 GPIO_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */ #if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT1 )
#define PB6 GPIO_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */ # define PB_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#define PB7 GPIO_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */ #else
#define PB8 GPIO_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */ # define PB_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PB9 GPIO_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */ #endif
#define PB10 GPIO_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */ #define PB0 PB_PIN_DATA(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
#define PB11 GPIO_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */ #define PB1 PB_PIN_DATA(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
#define PB12 GPIO_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */ #define PB2 PB_PIN_DATA(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
#define PB13 GPIO_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */ #define PB3 PB_PIN_DATA(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
#define PB14 GPIO_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */ #define PB4 PB_PIN_DATA(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
#define PB15 GPIO_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */ #define PB5 PB_PIN_DATA(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
#define PC0 GPIO_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */ #define PB6 PB_PIN_DATA(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
#define PC1 GPIO_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */ #define PB7 PB_PIN_DATA(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
#define PC2 GPIO_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */ #define PB8 PB_PIN_DATA(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
#define PC3 GPIO_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */ #define PB9 PB_PIN_DATA(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
#define PC4 GPIO_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */ #define PB10 PB_PIN_DATA(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
#define PC5 GPIO_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */ #define PB11 PB_PIN_DATA(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
#define PC6 GPIO_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */ #define PB12 PB_PIN_DATA(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
#define PC7 GPIO_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */ #define PB13 PB_PIN_DATA(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
#define PC8 GPIO_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */ #define PB14 PB_PIN_DATA(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
#define PC9 GPIO_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */ #define PB15 PB_PIN_DATA(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
#define PC10 GPIO_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
#define PC11 GPIO_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */ #if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT2 )
#define PC12 GPIO_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */ # define PC_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#define PC13 GPIO_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */ #else
#define PD0 GPIO_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */ # define PC_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PD1 GPIO_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */ #endif
#define PD2 GPIO_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */ #define PC0 PC_PIN_DATA(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
#define PD3 GPIO_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */ #define PC1 PC_PIN_DATA(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
#define PD4 GPIO_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */ #define PC2 PC_PIN_DATA(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
#define PD5 GPIO_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */ #define PC3 PC_PIN_DATA(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
#define PD6 GPIO_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */ #define PC4 PC_PIN_DATA(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
#define PD7 GPIO_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */ #define PC5 PC_PIN_DATA(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
#define PD8 GPIO_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */ #define PC6 PC_PIN_DATA(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
#define PD9 GPIO_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */ #define PC7 PC_PIN_DATA(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
#define PD10 GPIO_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */ #define PC8 PC_PIN_DATA(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
#define PD11 GPIO_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */ #define PC9 PC_PIN_DATA(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
#define PD12 GPIO_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */ #define PC10 PC_PIN_DATA(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
#define PD13 GPIO_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */ #define PC11 PC_PIN_DATA(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
#define PD14 GPIO_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */ #define PC12 PC_PIN_DATA(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
#define PE0 GPIO_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */ #define PC13 PC_PIN_DATA(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
#define PE1 GPIO_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
#define PE2 GPIO_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */ #if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT3 )
#define PE3 GPIO_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */ # define PD_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#define PE4 GPIO_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */ #else
#define PE5 GPIO_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */ # define PD_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PE6 GPIO_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */ #endif
#define PE7 GPIO_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */ #define PD0 PD_PIN_DATA(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
#define PE8 GPIO_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */ #define PD1 PD_PIN_DATA(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
#define PE9 GPIO_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */ #define PD2 PD_PIN_DATA(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
#define PE10 GPIO_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */ #define PD3 PD_PIN_DATA(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
#define PE11 GPIO_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */ #define PD4 PD_PIN_DATA(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
#define PE12 GPIO_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */ #define PD5 PD_PIN_DATA(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
#define PE13 GPIO_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */ #define PD6 PD_PIN_DATA(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
#define PE14 GPIO_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */ #define PD7 PD_PIN_DATA(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
#define PE15 GPIO_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */ #define PD8 PD_PIN_DATA(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
#define PF0 GPIO_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */ #define PD9 PD_PIN_DATA(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
#define PF1 GPIO_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */ #define PD10 PD_PIN_DATA(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
#define PF2 GPIO_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */ #define PD11 PD_PIN_DATA(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
#define PF3 GPIO_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */ #define PD12 PD_PIN_DATA(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
#define PF4 GPIO_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */ #define PD13 PD_PIN_DATA(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
#define PF5 GPIO_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */ #define PD14 PD_PIN_DATA(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
#define PF6 GPIO_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
#define PF7 GPIO_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */ #if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT4 )
#define PF8 GPIO_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */ # define PE_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#define PF9 GPIO_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */ #else
#define PF10 GPIO_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output */ # define PE_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PF11 GPIO_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output */ #endif
#define PG2 GPIO_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */ #define PE0 PE_PIN_DATA(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
#define PG3 GPIO_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */ #define PE1 PE_PIN_DATA(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
#define PG4 GPIO_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */ #define PE2 PE_PIN_DATA(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
#define PG9 GPIO_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */ #define PE3 PE_PIN_DATA(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
#define PG10 GPIO_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output */ #define PE4 PE_PIN_DATA(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
#define PG11 GPIO_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output */ #define PE5 PE_PIN_DATA(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
#define PG12 GPIO_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output */ #define PE6 PE_PIN_DATA(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
#define PG13 GPIO_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output */ #define PE7 PE_PIN_DATA(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
#define PG14 GPIO_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output */ #define PE8 PE_PIN_DATA(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
#define PG15 GPIO_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output */ #define PE9 PE_PIN_DATA(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
#define PH4 GPIO_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */ #define PE10 PE_PIN_DATA(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
#define PH5 GPIO_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */ #define PE11 PE_PIN_DATA(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
#define PH6 GPIO_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */ #define PE12 PE_PIN_DATA(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
#define PH7 GPIO_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */ #define PE13 PE_PIN_DATA(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
#define PH8 GPIO_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */ #define PE14 PE_PIN_DATA(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
#define PH9 GPIO_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */ #define PE15 PE_PIN_DATA(4, 15) /*!< Specify PE.15 Pin Data Input/Output */
#define PH10 GPIO_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output */
#define PH11 GPIO_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ #if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT5 )
# define PF_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#else
# define PF_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#endif
#define PF0 PF_PIN_DATA(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
#define PF1 PF_PIN_DATA(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
#define PF2 PF_PIN_DATA(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
#define PF3 PF_PIN_DATA(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
#define PF4 PF_PIN_DATA(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
#define PF5 PF_PIN_DATA(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
#define PF6 PF_PIN_DATA(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
#define PF7 PF_PIN_DATA(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
#define PF8 PF_PIN_DATA(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */
#define PF9 PF_PIN_DATA(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */
#define PF10 PF_PIN_DATA(5, 10) /*!< Specify PF.10 Pin Data Input/Output */
#define PF11 PF_PIN_DATA(5, 11) /*!< Specify PF.11 Pin Data Input/Output */
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT6 )
# define PG_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#else
# define PG_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#endif
#define PG2 PG_PIN_DATA(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */
#define PG3 PG_PIN_DATA(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */
#define PG4 PG_PIN_DATA(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */
#define PG9 PG_PIN_DATA(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */
#define PG10 PG_PIN_DATA(6, 10) /*!< Specify PG.10 Pin Data Input/Output */
#define PG11 PG_PIN_DATA(6, 11) /*!< Specify PG.11 Pin Data Input/Output */
#define PG12 PG_PIN_DATA(6, 12) /*!< Specify PG.12 Pin Data Input/Output */
#define PG13 PG_PIN_DATA(6, 13) /*!< Specify PG.13 Pin Data Input/Output */
#define PG14 PG_PIN_DATA(6, 14) /*!< Specify PG.14 Pin Data Input/Output */
#define PG15 PG_PIN_DATA(6, 15) /*!< Specify PG.15 Pin Data Input/Output */
#if defined (SCU_INIT_IONSSET_VAL) && (SCU_INIT_IONSSET_VAL & BIT7 )
# define PH_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
#else
# define PH_PIN_DATA(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#endif
#define PH4 PH_PIN_DATA(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */
#define PH5 PH_PIN_DATA(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */
#define PH6 PH_PIN_DATA(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */
#define PH7 PH_PIN_DATA(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */
#define PH8 PH_PIN_DATA(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */
#define PH9 PH_PIN_DATA(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */
#define PH10 PH_PIN_DATA(7, 10) /*!< Specify PH.10 Pin Data Input/Output */
#define PH11 PH_PIN_DATA(7, 11) /*!< Specify PH.11 Pin Data Input/Output */
/* GPIO bit definitions for secure */
#define GPIO_PIN_DATA_S(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+(0x40*(port))) + ((pin)<<2))))
#define PA0_S GPIO_PIN_DATA_S(0, 0 ) /*!< Specify PA.0 Pin Data Input/Output */
#define PA1_S GPIO_PIN_DATA_S(0, 1 ) /*!< Specify PA.1 Pin Data Input/Output */
#define PA2_S GPIO_PIN_DATA_S(0, 2 ) /*!< Specify PA.2 Pin Data Input/Output */
#define PA3_S GPIO_PIN_DATA_S(0, 3 ) /*!< Specify PA.3 Pin Data Input/Output */
#define PA4_S GPIO_PIN_DATA_S(0, 4 ) /*!< Specify PA.4 Pin Data Input/Output */
#define PA5_S GPIO_PIN_DATA_S(0, 5 ) /*!< Specify PA.5 Pin Data Input/Output */
#define PA6_S GPIO_PIN_DATA_S(0, 6 ) /*!< Specify PA.6 Pin Data Input/Output */
#define PA7_S GPIO_PIN_DATA_S(0, 7 ) /*!< Specify PA.7 Pin Data Input/Output */
#define PA8_S GPIO_PIN_DATA_S(0, 8 ) /*!< Specify PA.8 Pin Data Input/Output */
#define PA9_S GPIO_PIN_DATA_S(0, 9 ) /*!< Specify PA.9 Pin Data Input/Output */
#define PA10_S GPIO_PIN_DATA_S(0, 10) /*!< Specify PA.10 Pin Data Input/Output */
#define PA11_S GPIO_PIN_DATA_S(0, 11) /*!< Specify PA.11 Pin Data Input/Output */
#define PA12_S GPIO_PIN_DATA_S(0, 12) /*!< Specify PA.12 Pin Data Input/Output */
#define PA13_S GPIO_PIN_DATA_S(0, 13) /*!< Specify PA.13 Pin Data Input/Output */
#define PA14_S GPIO_PIN_DATA_S(0, 14) /*!< Specify PA.14 Pin Data Input/Output */
#define PA15_S GPIO_PIN_DATA_S(0, 15) /*!< Specify PA.15 Pin Data Input/Output */
#define PB0_S GPIO_PIN_DATA_S(1, 0 ) /*!< Specify PB.0 Pin Data Input/Output */
#define PB1_S GPIO_PIN_DATA_S(1, 1 ) /*!< Specify PB.1 Pin Data Input/Output */
#define PB2_S GPIO_PIN_DATA_S(1, 2 ) /*!< Specify PB.2 Pin Data Input/Output */
#define PB3_S GPIO_PIN_DATA_S(1, 3 ) /*!< Specify PB.3 Pin Data Input/Output */
#define PB4_S GPIO_PIN_DATA_S(1, 4 ) /*!< Specify PB.4 Pin Data Input/Output */
#define PB5_S GPIO_PIN_DATA_S(1, 5 ) /*!< Specify PB.5 Pin Data Input/Output */
#define PB6_S GPIO_PIN_DATA_S(1, 6 ) /*!< Specify PB.6 Pin Data Input/Output */
#define PB7_S GPIO_PIN_DATA_S(1, 7 ) /*!< Specify PB.7 Pin Data Input/Output */
#define PB8_S GPIO_PIN_DATA_S(1, 8 ) /*!< Specify PB.8 Pin Data Input/Output */
#define PB9_S GPIO_PIN_DATA_S(1, 9 ) /*!< Specify PB.9 Pin Data Input/Output */
#define PB10_S GPIO_PIN_DATA_S(1, 10) /*!< Specify PB.10 Pin Data Input/Output */
#define PB11_S GPIO_PIN_DATA_S(1, 11) /*!< Specify PB.11 Pin Data Input/Output */
#define PB12_S GPIO_PIN_DATA_S(1, 12) /*!< Specify PB.12 Pin Data Input/Output */
#define PB13_S GPIO_PIN_DATA_S(1, 13) /*!< Specify PB.13 Pin Data Input/Output */
#define PB14_S GPIO_PIN_DATA_S(1, 14) /*!< Specify PB.14 Pin Data Input/Output */
#define PB15_S GPIO_PIN_DATA_S(1, 15) /*!< Specify PB.15 Pin Data Input/Output */
#define PC0_S GPIO_PIN_DATA_S(2, 0 ) /*!< Specify PC.0 Pin Data Input/Output */
#define PC1_S GPIO_PIN_DATA_S(2, 1 ) /*!< Specify PC.1 Pin Data Input/Output */
#define PC2_S GPIO_PIN_DATA_S(2, 2 ) /*!< Specify PC.2 Pin Data Input/Output */
#define PC3_S GPIO_PIN_DATA_S(2, 3 ) /*!< Specify PC.3 Pin Data Input/Output */
#define PC4_S GPIO_PIN_DATA_S(2, 4 ) /*!< Specify PC.4 Pin Data Input/Output */
#define PC5_S GPIO_PIN_DATA_S(2, 5 ) /*!< Specify PC.5 Pin Data Input/Output */
#define PC6_S GPIO_PIN_DATA_S(2, 6 ) /*!< Specify PC.6 Pin Data Input/Output */
#define PC7_S GPIO_PIN_DATA_S(2, 7 ) /*!< Specify PC.7 Pin Data Input/Output */
#define PC8_S GPIO_PIN_DATA_S(2, 8 ) /*!< Specify PC.8 Pin Data Input/Output */
#define PC9_S GPIO_PIN_DATA_S(2, 9 ) /*!< Specify PC.9 Pin Data Input/Output */
#define PC10_S GPIO_PIN_DATA_S(2, 10) /*!< Specify PC.10 Pin Data Input/Output */
#define PC11_S GPIO_PIN_DATA_S(2, 11) /*!< Specify PC.11 Pin Data Input/Output */
#define PC12_S GPIO_PIN_DATA_S(2, 12) /*!< Specify PC.12 Pin Data Input/Output */
#define PC13_S GPIO_PIN_DATA_S(2, 13) /*!< Specify PC.13 Pin Data Input/Output */
#define PD0_S GPIO_PIN_DATA_S(3, 0 ) /*!< Specify PD.0 Pin Data Input/Output */
#define PD1_S GPIO_PIN_DATA_S(3, 1 ) /*!< Specify PD.1 Pin Data Input/Output */
#define PD2_S GPIO_PIN_DATA_S(3, 2 ) /*!< Specify PD.2 Pin Data Input/Output */
#define PD3_S GPIO_PIN_DATA_S(3, 3 ) /*!< Specify PD.3 Pin Data Input/Output */
#define PD4_S GPIO_PIN_DATA_S(3, 4 ) /*!< Specify PD.4 Pin Data Input/Output */
#define PD5_S GPIO_PIN_DATA_S(3, 5 ) /*!< Specify PD.5 Pin Data Input/Output */
#define PD6_S GPIO_PIN_DATA_S(3, 6 ) /*!< Specify PD.6 Pin Data Input/Output */
#define PD7_S GPIO_PIN_DATA_S(3, 7 ) /*!< Specify PD.7 Pin Data Input/Output */
#define PD8_S GPIO_PIN_DATA_S(3, 8 ) /*!< Specify PD.8 Pin Data Input/Output */
#define PD9_S GPIO_PIN_DATA_S(3, 9 ) /*!< Specify PD.9 Pin Data Input/Output */
#define PD10_S GPIO_PIN_DATA_S(3, 10) /*!< Specify PD.10 Pin Data Input/Output */
#define PD11_S GPIO_PIN_DATA_S(3, 11) /*!< Specify PD.11 Pin Data Input/Output */
#define PD12_S GPIO_PIN_DATA_S(3, 12) /*!< Specify PD.12 Pin Data Input/Output */
#define PD13_S GPIO_PIN_DATA_S(3, 13) /*!< Specify PD.13 Pin Data Input/Output */
#define PD14_S GPIO_PIN_DATA_S(3, 14) /*!< Specify PD.14 Pin Data Input/Output */
#define PE0_S GPIO_PIN_DATA_S(4, 0 ) /*!< Specify PE.0 Pin Data Input/Output */
#define PE1_S GPIO_PIN_DATA_S(4, 1 ) /*!< Specify PE.1 Pin Data Input/Output */
#define PE2_S GPIO_PIN_DATA_S(4, 2 ) /*!< Specify PE.2 Pin Data Input/Output */
#define PE3_S GPIO_PIN_DATA_S(4, 3 ) /*!< Specify PE.3 Pin Data Input/Output */
#define PE4_S GPIO_PIN_DATA_S(4, 4 ) /*!< Specify PE.4 Pin Data Input/Output */
#define PE5_S GPIO_PIN_DATA_S(4, 5 ) /*!< Specify PE.5 Pin Data Input/Output */
#define PE6_S GPIO_PIN_DATA_S(4, 6 ) /*!< Specify PE.6 Pin Data Input/Output */
#define PE7_S GPIO_PIN_DATA_S(4, 7 ) /*!< Specify PE.7 Pin Data Input/Output */
#define PE8_S GPIO_PIN_DATA_S(4, 8 ) /*!< Specify PE.8 Pin Data Input/Output */
#define PE9_S GPIO_PIN_DATA_S(4, 9 ) /*!< Specify PE.9 Pin Data Input/Output */
#define PE10_S GPIO_PIN_DATA_S(4, 10) /*!< Specify PE.10 Pin Data Input/Output */
#define PE11_S GPIO_PIN_DATA_S(4, 11) /*!< Specify PE.11 Pin Data Input/Output */
#define PE12_S GPIO_PIN_DATA_S(4, 12) /*!< Specify PE.12 Pin Data Input/Output */
#define PE13_S GPIO_PIN_DATA_S(4, 13) /*!< Specify PE.13 Pin Data Input/Output */
#define PE14_S GPIO_PIN_DATA_S(4, 14) /*!< Specify PE.14 Pin Data Input/Output */
#define PE15_S GPIO_PIN_DATA_S(4, 15) /*!< Specify PE.15 Pin Data Input/Output */
#define PF0_S GPIO_PIN_DATA_S(5, 0 ) /*!< Specify PF.0 Pin Data Input/Output */
#define PF1_S GPIO_PIN_DATA_S(5, 1 ) /*!< Specify PF.1 Pin Data Input/Output */
#define PF2_S GPIO_PIN_DATA_S(5, 2 ) /*!< Specify PF.2 Pin Data Input/Output */
#define PF3_S GPIO_PIN_DATA_S(5, 3 ) /*!< Specify PF.3 Pin Data Input/Output */
#define PF4_S GPIO_PIN_DATA_S(5, 4 ) /*!< Specify PF.4 Pin Data Input/Output */
#define PF5_S GPIO_PIN_DATA_S(5, 5 ) /*!< Specify PF.5 Pin Data Input/Output */
#define PF6_S GPIO_PIN_DATA_S(5, 6 ) /*!< Specify PF.6 Pin Data Input/Output */
#define PF7_S GPIO_PIN_DATA_S(5, 7 ) /*!< Specify PF.7 Pin Data Input/Output */
#define PF8_S GPIO_PIN_DATA_S(5, 8 ) /*!< Specify PF.8 Pin Data Input/Output */
#define PF9_S GPIO_PIN_DATA_S(5, 9 ) /*!< Specify PF.9 Pin Data Input/Output */
#define PF10_S GPIO_PIN_DATA_S(5, 10) /*!< Specify PF.10 Pin Data Input/Output */
#define PF11_S GPIO_PIN_DATA_S(5, 11) /*!< Specify PF.11 Pin Data Input/Output */
#define PG2_S GPIO_PIN_DATA_S(6, 2 ) /*!< Specify PG.2 Pin Data Input/Output */
#define PG3_S GPIO_PIN_DATA_S(6, 3 ) /*!< Specify PG.3 Pin Data Input/Output */
#define PG4_S GPIO_PIN_DATA_S(6, 4 ) /*!< Specify PG.4 Pin Data Input/Output */
#define PG9_S GPIO_PIN_DATA_S(6, 9 ) /*!< Specify PG.9 Pin Data Input/Output */
#define PG10_S GPIO_PIN_DATA_S(6, 10) /*!< Specify PG.10 Pin Data Input/Output */
#define PG11_S GPIO_PIN_DATA_S(6, 11) /*!< Specify PG.11 Pin Data Input/Output */
#define PG12_S GPIO_PIN_DATA_S(6, 12) /*!< Specify PG.12 Pin Data Input/Output */
#define PG13_S GPIO_PIN_DATA_S(6, 13) /*!< Specify PG.13 Pin Data Input/Output */
#define PG14_S GPIO_PIN_DATA_S(6, 14) /*!< Specify PG.14 Pin Data Input/Output */
#define PG15_S GPIO_PIN_DATA_S(6, 15) /*!< Specify PG.15 Pin Data Input/Output */
#define PH4_S GPIO_PIN_DATA_S(7, 4 ) /*!< Specify PH.4 Pin Data Input/Output */
#define PH5_S GPIO_PIN_DATA_S(7, 5 ) /*!< Specify PH.5 Pin Data Input/Output */
#define PH6_S GPIO_PIN_DATA_S(7, 6 ) /*!< Specify PH.6 Pin Data Input/Output */
#define PH7_S GPIO_PIN_DATA_S(7, 7 ) /*!< Specify PH.7 Pin Data Input/Output */
#define PH8_S GPIO_PIN_DATA_S(7, 8 ) /*!< Specify PH.8 Pin Data Input/Output */
#define PH9_S GPIO_PIN_DATA_S(7, 9 ) /*!< Specify PH.9 Pin Data Input/Output */
#define PH10_S GPIO_PIN_DATA_S(7, 10) /*!< Specify PH.10 Pin Data Input/Output */
#define PH11_S GPIO_PIN_DATA_S(7, 11) /*!< Specify PH.11 Pin Data Input/Output */
/* GPIO bit definitions for non-secure */ /* GPIO bit definitions for non-secure */
#define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2)))) #define GPIO_PIN_DATA_NS(port, pin) (*((volatile uint32_t *)((GPIO_PIN_DATA_BASE+NS_OFFSET+(0x40*(port))) + ((pin)<<2))))
@ -333,7 +489,6 @@ extern "C"
#define PH10_NS GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */ #define PH10_NS GPIO_PIN_DATA_NS(7, 10) /*!< Specify PH.10 Pin Data Input/Output */
#define PH11_NS GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */ #define PH11_NS GPIO_PIN_DATA_NS(7, 11) /*!< Specify PH.11 Pin Data Input/Output */
/*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */ /*@}*/ /* end of group GPIO_EXPORTED_CONSTANTS */

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_hdiv.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_hdiv.h
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20
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_i2c.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_i2c.h
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@ -489,18 +489,18 @@ void I2C_DisableTimeout(I2C_T *i2c);
void I2C_EnableWakeup(I2C_T *i2c); void I2C_EnableWakeup(I2C_T *i2c);
void I2C_DisableWakeup(I2C_T *i2c); void I2C_DisableWakeup(I2C_T *i2c);
void I2C_SetData(I2C_T *i2c, uint8_t u8Data); void I2C_SetData(I2C_T *i2c, uint8_t u8Data);
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data); uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data);
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen); uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen);
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data); uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data);
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen); uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen);
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data); uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data);
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen); uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen);
uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr); uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr);
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen); uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen);
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr); uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr);
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen); uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen);
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr); uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr);
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen); uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen);
uint32_t I2C_SMBusGetStatus(I2C_T *i2c); uint32_t I2C_SMBusGetStatus(I2C_T *i2c);
void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag); void I2C_SMBusClearInterruptFlag(I2C_T *i2c, uint8_t u8ClrSMBusIntFlag);
void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize); void I2C_SMBusSetPacketByteCount(I2C_T *i2c, uint32_t u32PktSize);
@ -508,7 +508,7 @@ void I2C_SMBusOpen(I2C_T *i2c, uint8_t u8HostDevice);
void I2C_SMBusClose(I2C_T *i2c); void I2C_SMBusClose(I2C_T *i2c);
void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn); void I2C_SMBusPECTxEnable(I2C_T *i2c, uint8_t u8PECTxEn);
uint8_t I2C_SMBusGetPECValue(I2C_T *i2c); uint8_t I2C_SMBusGetPECValue(I2C_T *i2c);
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk); void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk);
void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); void I2C_SMBusTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);
void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk); void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk);

3
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_i2s.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_i2s.h
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@ -33,7 +33,7 @@ extern "C"
/* Audio Format */ /* Audio Format */
#define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */ #define I2S_ENABLE_MONO I2S_CTL0_MONO_Msk /*!< Mono channel \hideinitializer */
#define I2S_DISABLE_MONO (0UL) /*!< Stereo channel \hideinitializer */ #define I2S_DISABLE_MONO (0UL) /*!< Stereo channel \hideinitializer */
#define I2S_MONO I2S_ENABLE_MONO #define I2S_MONO I2S_ENABLE_MONO
#define I2S_STEREO I2S_DISABLE_MONO #define I2S_STEREO I2S_DISABLE_MONO
@ -360,4 +360,3 @@ void I2S_ConfigureTDM(I2S_T *i2s, uint32_t u32ChannelWidth, uint32_t u32ChannelN
#endif /* __I2S_H__ */ #endif /* __I2S_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_mkromlib.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_mkromlib.h
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105
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_otg.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_otg.h
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@ -61,12 +61,7 @@ extern "C"
* @return None * @return None
* @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function. * @details This macro will set OTGEN bit of OTG_CTL register to enable OTG function.
*/ */
#define OTG_ENABLE() (OTG->CTL |= OTG_CTL_OTGEN_Msk) #define OTG_ENABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk):(OTG->CTL |= OTG_CTL_OTGEN_Msk))
/**
* @brief This macro is used to enable OTG function Macro for Non-Secure
*/
#define OTG_ENABLE_NS() (OTG_NS->CTL |= OTG_CTL_OTGEN_Msk)
/** /**
* @brief This macro is used to disable OTG function * @brief This macro is used to disable OTG function
@ -74,12 +69,7 @@ extern "C"
* @return None * @return None
* @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function. * @details This macro will clear OTGEN bit of OTG_CTL register to disable OTG function.
*/ */
#define OTG_DISABLE() (OTG->CTL &= ~OTG_CTL_OTGEN_Msk) #define OTG_DISABLE() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk):(OTG->CTL &= ~OTG_CTL_OTGEN_Msk))
/**
* @brief This macro is used to disable OTG function Macro for Non-Secure
*/
#define OTG_DISABLE_NS() (OTG_NS->CTL &= ~OTG_CTL_OTGEN_Msk)
/** /**
* @brief This macro is used to enable USB PHY * @brief This macro is used to enable USB PHY
@ -88,12 +78,7 @@ extern "C"
* @details When the USB role is selected as OTG device, use this macro to enable USB PHY. * @details When the USB role is selected as OTG device, use this macro to enable USB PHY.
* This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY. * This macro will set OTGPHYEN bit of OTG_PHYCTL register to enable USB PHY.
*/ */
#define OTG_ENABLE_PHY() (OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk) #define OTG_ENABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk))
/**
* @brief This macro is used to enable USB PHY Macro for Non-Secure
*/
#define OTG_ENABLE_PHY_NS() (OTG_NS->PHYCTL |= OTG_PHYCTL_OTGPHYEN_Msk)
/** /**
* @brief This macro is used to disable USB PHY * @brief This macro is used to disable USB PHY
@ -101,12 +86,7 @@ extern "C"
* @return None * @return None
* @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY. * @details This macro will clear OTGPHYEN bit of OTG_PHYCTL register to disable USB PHY.
*/ */
#define OTG_DISABLE_PHY() (OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk) #define OTG_DISABLE_PHY() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk))
/**
* @brief This macro is used to disable USB PHY Macro for Non-Secure
*/
#define OTG_DISABLE_PHY_NS() (OTG_NS->PHYCTL &= ~OTG_PHYCTL_OTGPHYEN_Msk)
/** /**
* @brief This macro is used to enable ID detection function * @brief This macro is used to enable ID detection function
@ -114,12 +94,7 @@ extern "C"
* @return None * @return None
* @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function. * @details This macro will set IDDETEN bit of OTG_PHYCTL register to enable ID detection function.
*/ */
#define OTG_ENABLE_ID_DETECT() (OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk) #define OTG_ENABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk))
/**
* @brief This macro is used to enable ID detection function Macro for Non-Secure
*/
#define OTG_ENABLE_ID_DETECT_NS() (OTG_NS->PHYCTL |= OTG_PHYCTL_IDDETEN_Msk)
/** /**
* @brief This macro is used to disable ID detection function * @brief This macro is used to disable ID detection function
@ -127,12 +102,7 @@ extern "C"
* @return None * @return None
* @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function. * @details This macro will clear IDDETEN bit of OTG_PHYCTL register to disable ID detection function.
*/ */
#define OTG_DISABLE_ID_DETECT() (OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk) #define OTG_DISABLE_ID_DETECT() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk):(OTG->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk))
/**
* @brief This macro is used to disable ID detection function Macro for Non-Secure
*/
#define OTG_DISABLE_ID_DETECT_NS() (OTG_NS->PHYCTL &= ~OTG_PHYCTL_IDDETEN_Msk)
/** /**
* @brief This macro is used to enable OTG wake-up function * @brief This macro is used to enable OTG wake-up function
@ -140,12 +110,7 @@ extern "C"
* @return None * @return None
* @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function. * @details This macro will set WKEN bit of OTG_CTL register to enable OTG wake-up function.
*/ */
#define OTG_ENABLE_WAKEUP() (OTG->CTL |= OTG_CTL_WKEN_Msk) #define OTG_ENABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL |= OTG_CTL_WKEN_Msk):(OTG->CTL |= OTG_CTL_WKEN_Msk))
/**
* @brief This macro is used to enable OTG wake-up function Macro for Non-Secure
*/
#define OTG_ENABLE_WAKEUP_NS() (OTG_NS->CTL |= OTG_CTL_WKEN_Msk)
/** /**
* @brief This macro is used to disable OTG wake-up function * @brief This macro is used to disable OTG wake-up function
@ -153,12 +118,7 @@ extern "C"
* @return None * @return None
* @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function. * @details This macro will clear WKEN bit of OTG_CTL register to disable OTG wake-up function.
*/ */
#define OTG_DISABLE_WAKEUP() (OTG->CTL &= ~OTG_CTL_WKEN_Msk) #define OTG_DISABLE_WAKEUP() (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk):(OTG->CTL &= ~OTG_CTL_WKEN_Msk))
/**
* @brief This macro is used to disable OTG wake-up function Macro for Non-Secure
*/
#define OTG_DISABLE_WAKEUP_NS() (OTG_NS->CTL &= ~OTG_CTL_WKEN_Msk)
/** /**
* @brief This macro is used to set the polarity of USB_VBUS_EN pin * @brief This macro is used to set the polarity of USB_VBUS_EN pin
@ -168,12 +128,7 @@ extern "C"
* @return None * @return None
* @details This macro is used to set the polarity of external USB VBUS power switch enable signal. * @details This macro is used to set the polarity of external USB VBUS power switch enable signal.
*/ */
#define OTG_SET_VBUS_EN_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos)) #define OTG_SET_VBUS_EN_POL(u32Pol) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos)):(OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos)))
/**
* @brief This macro is used to set the polarity of USB_VBUS_EN pin Macro for Non-Secure
*/
#define OTG_SET_VBUS_EN_POL_NS(u32Pol) (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBENPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBENPOL_Pos))
/** /**
* @brief This macro is used to set the polarity of USB_VBUS_ST pin * @brief This macro is used to set the polarity of USB_VBUS_ST pin
@ -183,12 +138,7 @@ extern "C"
* @return None * @return None
* @details This macro is used to set the polarity of external USB VBUS power switch status signal. * @details This macro is used to set the polarity of external USB VBUS power switch status signal.
*/ */
#define OTG_SET_VBUS_STS_POL(u32Pol) (OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos)) #define OTG_SET_VBUS_STS_POL(u32Pol) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos)):(OTG->PHYCTL = (OTG->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos)))
/**
* @brief This macro is used to set the polarity of USB_VBUS_ST pin Macro for Non-Secure
*/
#define OTG_SET_VBUS_STS_POL_NS(u32Pol) (OTG_NS->PHYCTL = (OTG_NS->PHYCTL & (~OTG_PHYCTL_VBSTSPOL_Msk)) | ((u32Pol)<<OTG_PHYCTL_VBSTSPOL_Pos))
/** /**
* @brief This macro is used to enable OTG related interrupts * @brief This macro is used to enable OTG related interrupts
@ -209,12 +159,7 @@ extern "C"
* @return None * @return None
* @details This macro will enable OTG related interrupts specified by u32Mask parameter. * @details This macro will enable OTG related interrupts specified by u32Mask parameter.
*/ */
#define OTG_ENABLE_INT(u32Mask) (OTG->INTEN |= (u32Mask)) #define OTG_ENABLE_INT(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTEN |= (u32Mask)):(OTG->INTEN |= (u32Mask)))
/**
* @brief This macro is used to enable OTG related interrupts Macro for Non-Secure
*/
#define OTG_ENABLE_INT_NS(u32Mask) (OTG_NS->INTEN |= (u32Mask))
/** /**
* @brief This macro is used to disable OTG related interrupts * @brief This macro is used to disable OTG related interrupts
@ -235,12 +180,7 @@ extern "C"
* @return None * @return None
* @details This macro will disable OTG related interrupts specified by u32Mask parameter. * @details This macro will disable OTG related interrupts specified by u32Mask parameter.
*/ */
#define OTG_DISABLE_INT(u32Mask) (OTG->INTEN &= ~(u32Mask)) #define OTG_DISABLE_INT(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTEN &= ~(u32Mask)):(OTG->INTEN &= ~(u32Mask)))
/**
* @brief This macro is used to disable OTG related interrupts Macro for Non-Secure
*/
#define OTG_DISABLE_INT_NS(u32Mask) (OTG_NS->INTEN &= ~(u32Mask))
/** /**
* @brief This macro is used to get OTG related interrupt flags * @brief This macro is used to get OTG related interrupt flags
@ -261,12 +201,7 @@ extern "C"
* @return Interrupt flags of selected sources. * @return Interrupt flags of selected sources.
* @details This macro will return OTG related interrupt flags specified by u32Mask parameter. * @details This macro will return OTG related interrupt flags specified by u32Mask parameter.
*/ */
#define OTG_GET_INT_FLAG(u32Mask) (OTG->INTSTS & (u32Mask)) #define OTG_GET_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS & (u32Mask)):(OTG->INTSTS & (u32Mask)))
/**
* @brief This macro is used to get OTG related interrupt flags Macro for Non-Secure
*/
#define OTG_GET_INT_FLAG_NS(u32Mask) (OTG_NS->INTSTS & (u32Mask))
/** /**
* @brief This macro is used to clear OTG related interrupt flags * @brief This macro is used to clear OTG related interrupt flags
@ -287,12 +222,7 @@ extern "C"
* @return None * @return None
* @details This macro will clear OTG related interrupt flags specified by u32Mask parameter. * @details This macro will clear OTG related interrupt flags specified by u32Mask parameter.
*/ */
#define OTG_CLR_INT_FLAG(u32Mask) (OTG->INTSTS = (u32Mask)) #define OTG_CLR_INT_FLAG(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->INTSTS = (u32Mask)):(OTG->INTSTS = (u32Mask)))
/**
* @brief This macro is used to clear OTG related interrupt flags Macro for Non-Secure
*/
#define OTG_CLR_INT_FLAG_NS(u32Mask) (OTG_NS->INTSTS = (u32Mask))
/** /**
* @brief This macro is used to get OTG related status * @brief This macro is used to get OTG related status
@ -306,12 +236,7 @@ extern "C"
* @return The user specified status. * @return The user specified status.
* @details This macro will return OTG related status specified by u32Mask parameter. * @details This macro will return OTG related status specified by u32Mask parameter.
*/ */
#define OTG_GET_STATUS(u32Mask) (OTG->STATUS & (u32Mask)) #define OTG_GET_STATUS(u32Mask) (((__PC() & NS_OFFSET) == NS_OFFSET)? (OTG_NS->STATUS & (u32Mask)):(OTG->STATUS & (u32Mask)))
/**
* @brief This macro is used to get OTG related status Macro for Non-Secure
*/
#define OTG_GET_STATUS_NS(u32Mask) (OTG_NS->STATUS & (u32Mask))

6
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_pdma.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_pdma.h
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@ -4,7 +4,7 @@
* @brief M2351 series PDMA driver header file * @brief M2351 series PDMA driver header file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#ifndef __PDMA_H__ #ifndef __PDMA_H__
#define __PDMA_H__ #define __PDMA_H__
@ -103,8 +103,6 @@ extern "C"
#define PDMA_SPI2_RX 0x0000001BUL /*!<DMA Connect to SPI2 RX \hideinitializer */ #define PDMA_SPI2_RX 0x0000001BUL /*!<DMA Connect to SPI2 RX \hideinitializer */
#define PDMA_SPI3_TX 0x0000001CUL /*!<DMA Connect to SPI3 TX \hideinitializer */ #define PDMA_SPI3_TX 0x0000001CUL /*!<DMA Connect to SPI3 TX \hideinitializer */
#define PDMA_SPI3_RX 0x0000001DUL /*!<DMA Connect to SPI3 RX \hideinitializer */ #define PDMA_SPI3_RX 0x0000001DUL /*!<DMA Connect to SPI3 RX \hideinitializer */
#define PDMA_SPI5_TX 0x0000001EUL /*!<DMA Connect to SPI5 TX \hideinitializer */
#define PDMA_SPI5_RX 0x0000001FUL /*!<DMA Connect to SPI5 RX \hideinitializer */
#define PDMA_EPWM0_P1_RX 0x00000020UL /*!<DMA Connect to EPWM0 P1 RX \hideinitializer */ #define PDMA_EPWM0_P1_RX 0x00000020UL /*!<DMA Connect to EPWM0 P1 RX \hideinitializer */
#define PDMA_EPWM0_P2_RX 0x00000021UL /*!<DMA Connect to EPWM0 P2 RX \hideinitializer */ #define PDMA_EPWM0_P2_RX 0x00000021UL /*!<DMA Connect to EPWM0 P2 RX \hideinitializer */
#define PDMA_EPWM0_P3_RX 0x00000022UL /*!<DMA Connect to EPWM0 P3 RX \hideinitializer */ #define PDMA_EPWM0_P3_RX 0x00000022UL /*!<DMA Connect to EPWM0 P3 RX \hideinitializer */
@ -378,4 +376,4 @@ void PDMA_DisableInt(PDMA_T *pdma, uint32_t u32Ch, uint32_t u32Mask);
#endif /* __PDMA_H__ */ #endif /* __PDMA_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_qei.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_qei.h
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0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_qspi.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_qspi.h
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11
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_rtc.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_rtc.h
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@ -144,7 +144,7 @@ typedef struct
/** /**
* @brief Clear RTC Alarm Interrupt Flag * @brief Clear RTC Alarm Interrupt Flag
* *
* @param None * @param[in] rtc The pointer of RTC module.
* *
* @return None * @return None
* *
@ -311,14 +311,7 @@ __STATIC_INLINE void RTC_WaitAccessEnable(void);
*/ */
__STATIC_INLINE void RTC_WaitAccessEnable(void) __STATIC_INLINE void RTC_WaitAccessEnable(void)
{ {
if((__PC()&NS_OFFSET) == NS_OFFSET) while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0UL) {}
{
while((RTC_NS->RWEN & RTC_RWEN_RWENF_Msk) == 0x0UL) {}
}
else
{
while((RTC->RWEN & RTC_RWEN_RWENF_Msk) == 0x0UL) {}
}
} }
void RTC_Open(S_RTC_TIME_DATA_T *sPt); void RTC_Open(S_RTC_TIME_DATA_T *sPt);

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_sc.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_sc.h
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21
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_scu.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_scu.h
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@ -53,8 +53,8 @@ typedef enum NSATTR
I2S0_Attr = 64 + 8, I2S0_Attr = 64 + 8,
OTG_Attr = 64 + 13, OTG_Attr = 64 + 13,
TMR23_Attr = 64 + 17, TMR23_Attr = 64 + 17,
PWM0_Attr = 64 + 24, EPWM0_Attr = 64 + 24,
PWM1_Attr = 64 + 25, EPWM1_Attr = 64 + 25,
BPWM0_Attr = 64 + 26, BPWM0_Attr = 64 + 26,
BPWM1_Attr = 64 + 27, BPWM1_Attr = 64 + 27,
/****** PNNSET3 **********************************************************************************/ /****** PNNSET3 **********************************************************************************/
@ -63,7 +63,6 @@ typedef enum NSATTR
SPI1_Attr = 96 + 2, SPI1_Attr = 96 + 2,
SPI2_Attr = 96 + 3, SPI2_Attr = 96 + 3,
SPI3_Attr = 96 + 4, SPI3_Attr = 96 + 4,
SPI5_Attr = 96 + 5,
UART0_Attr = 96 + 16, UART0_Attr = 96 + 16,
UART1_Attr = 96 + 17, UART1_Attr = 96 + 17,
UART2_Attr = 96 + 18, UART2_Attr = 96 + 18,
@ -85,7 +84,7 @@ typedef enum NSATTR
QEI1_Attr = 160 + 17, QEI1_Attr = 160 + 17,
ECAP0_Attr = 160 + 20, ECAP0_Attr = 160 + 20,
ECAP1_Attr = 160 + 21, ECAP1_Attr = 160 + 21,
DSRC_Attr = 160 + 23, TRNG_Attr = 160 + 25,
/****** PNNSET6 **********************************************************************************/ /****** PNNSET6 **********************************************************************************/
USBD_Attr = 192 + 0, USBD_Attr = 192 + 0,
@ -99,14 +98,15 @@ typedef enum NSATTR
/*@}*/ /* end of group SCU_EXPORTED_CONSTANTS */ /*@}*/ /* end of group SCU_EXPORTED_CONSTANTS */
/** @addtogroup CRC_EXPORTED_FUNCTIONS CRC Exported Functions /** @addtogroup SCU_EXPORTED_FUNCTIONS SCU Exported Functions
@{ @{
*/ */
/** /**
* @brief Set peripheral non-secure attribution * @brief Set peripheral non-secure attribution
* *
* @param[in] module The module which needs to set to non-secure. * @param[in] nsattr The secure/non-secure attribution of specified module.
The possible value could be refer to \ref NSATTR.
* *
* @return None * @return None
* *
@ -118,7 +118,8 @@ typedef enum NSATTR
/** /**
* @brief Get peripheral secure/non-secure attribution * @brief Get peripheral secure/non-secure attribution
* *
* @param[in] module The peripheral which needs to get its secure/non-secure attribution. * @param[in] nsattr The secure/non-secure attribution of specified module.
The possible value could be refer to \ref NSATTR.
* *
* @return The secure/non-secure attribution of specified peripheral. * @return The secure/non-secure attribution of specified peripheral.
* @retval 0 The peripheral is secure * @retval 0 The peripheral is secure
@ -151,7 +152,7 @@ typedef enum NSATTR
/** /**
* @brief Get secure/non-secure attribution of specified GPIO ports * @brief Get secure/non-secure attribution of specified GPIO ports
* *
* @param[in] mask The port mask of each GPIO port * @param[in] port The port mask of each GPIO port
* - \ref SCU_IONSSET_PA_Msk * - \ref SCU_IONSSET_PA_Msk
* - \ref SCU_IONSSET_PB_Msk * - \ref SCU_IONSSET_PB_Msk
* - \ref SCU_IONSSET_PC_Msk * - \ref SCU_IONSSET_PC_Msk
@ -195,7 +196,7 @@ typedef enum NSATTR
* @details This macro is used to enable secure violation interrupt of SCU. * @details This macro is used to enable secure violation interrupt of SCU.
* The secure violation interrupt could be used to detect attack of secure elements. * The secure violation interrupt could be used to detect attack of secure elements.
*/ */
#define SCU_ENABLE_INT(int_mask) (SCU->SVIOIEN |= (int_mask)) #define SCU_ENABLE_INT(mask) (SCU->SVIOIEN |= (mask))
/** /**
@ -224,7 +225,7 @@ typedef enum NSATTR
* @details This macro is used to disable secure violation interrupt of SCU. * @details This macro is used to disable secure violation interrupt of SCU.
* *
*/ */
#define SCU_DISABLE_INT(int_mask) (SCU->SVIOIEN &= (~(int_mask))) #define SCU_DISABLE_INT(mask) (SCU->SVIOIEN &= (~(mask)))
/** /**

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_scuart.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_scuart.h
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24
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_sdh.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_sdh.h
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@ -3,7 +3,7 @@
* @version V1.00 * @version V1.00
* @brief M2351 SDH driver header file * @brief M2351 SDH driver header file
* *
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * @copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#ifndef __SDH_H__ #ifndef __SDH_H__
#define __SDH_H__ #define __SDH_H__
@ -93,8 +93,8 @@ extern SDH_INFO_T SD0;
* *
* @param[in] sdh The pointer of the specified SDH module. * @param[in] sdh The pointer of the specified SDH module.
* @param[in] u32IntMask Interrupt type mask: * @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk / * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
* \ref SDH_INTEN_CDSRC0_Msk / \ref SDH_INTEN_CDSRC1_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / * \ref SDH_INTEN_CDSRC_Msk / \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk /
* \ref SDH_INTEN_WKIEN_Msk * \ref SDH_INTEN_WKIEN_Msk
* *
* @return None. * @return None.
@ -107,9 +107,8 @@ extern SDH_INFO_T SD0;
* *
* @param[in] sdh The pointer of the specified SDH module. * @param[in] sdh The pointer of the specified SDH module.
* @param[in] u32IntMask Interrupt type mask: * @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN0_Msk / \ref SDH_INTEN_CDIEN1_Msk / * \ref SDH_INTEN_BLKDIEN_Msk / \ref SDH_INTEN_CRCIEN_Msk / \ref SDH_INTEN_CDIEN_Msk /
* \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC0_Msk / * \ref SDH_INTEN_RTOIEN_Msk / \ref SDH_INTEN_DITOIEN_Msk / \ref SDH_INTEN_WKIEN_Msk / \ref SDH_INTEN_CDSRC_Msk /
* \ref SDH_INTEN_CDSRC1_Msk
* *
* @return None. * @return None.
* \hideinitializer * \hideinitializer
@ -123,8 +122,8 @@ extern SDH_INFO_T SD0;
* @param[in] u32IntMask Interrupt type mask: * @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk / * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CRC7_Msk /
* \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk / * \ref SDH_INTSTS_CRC16_Msk / \ref SDH_INTSTS_CRCSTS_Msk / \ref SDH_INTSTS_DAT0STS_Msk /
* \ref SDH_INTSTS_CDIF0_Msk / \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_RTOIF_Msk / * \ref SDH_INTSTS_CDIF_Msk / \ref SDH_INTSTS_RTOIF_Msk /
* \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS0_Msk / \ref SDH_INTSTS_CDSTS1_Msk / * \ref SDH_INTSTS_DITOIF_Msk / \ref SDH_INTSTS_CDSTS_Msk /
* \ref SDH_INTSTS_DAT1STS_Msk * \ref SDH_INTSTS_DAT1STS_Msk
* *
* *
@ -140,8 +139,8 @@ extern SDH_INFO_T SD0;
* *
* @param[in] sdh The pointer of the specified SDH module. * @param[in] sdh The pointer of the specified SDH module.
* @param[in] u32IntMask Interrupt type mask: * @param[in] u32IntMask Interrupt type mask:
* \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF0_Msk / * \ref SDH_INTSTS_BLKDIF_Msk / \ref SDH_INTSTS_CRCIF_Msk / \ref SDH_INTSTS_CDIF_Msk /
* \ref SDH_INTSTS_CDIF1_Msk / \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk * \ref SDH_INTSTS_RTOIF_Msk / \ref SDH_INTSTS_DITOIF_Msk
* *
* *
* @return None. * @return None.
@ -171,6 +170,9 @@ extern SDH_INFO_T SD0;
*/ */
#define SDH_GET_CARD_CAPACITY(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0) #define SDH_GET_CARD_CAPACITY(sdh) ((((sdh) == SDH0)||((sdh) == SDH0_NS))? SD0.diskSize : 0)
extern uint8_t g_u8R3Flag;
extern uint8_t volatile g_u8SDDataReadyFlag;
extern int SDH_ok;
void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc); void SDH_Open(SDH_T *sdh, uint32_t u32CardDetSrc);
uint32_t SDH_Probe(SDH_T *sdh); uint32_t SDH_Probe(SDH_T *sdh);
@ -192,4 +194,4 @@ void SDH_Close_Disk(SDH_T *sdh);
#endif #endif
#endif /* end of __SDH_H__ */ #endif /* end of __SDH_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_spi.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_spi.h
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100
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_sys.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_sys.h
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@ -58,7 +58,6 @@ extern "C"
#define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */ #define UART3_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART3RST_Pos) /*!< UART3 reset is one of the SYS_ResetModule parameter */
#define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */ #define UART4_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART4RST_Pos) /*!< UART4 reset is one of the SYS_ResetModule parameter */
#define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */ #define UART5_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_UART5RST_Pos) /*!< UART5 reset is one of the SYS_ResetModule parameter */
#define DSRC_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_DSRCRST_Pos) /*!< DSRC reset is one of the SYS_ResetModule parameter */
#define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */ #define CAN0_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_CAN0RST_Pos) /*!< CAN0 reset is one of the SYS_ResetModule parameter */
#define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */ #define OTG_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_OTGRST_Pos) /*!< OTG reset is one of the SYS_ResetModule parameter */
#define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */ #define USBD_RST ((0x4UL<<24)|(uint32_t)SYS_IPRST1_USBDRST_Pos) /*!< USBD reset is one of the SYS_ResetModule parameter */
@ -70,7 +69,6 @@ extern "C"
#define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */ #define SC1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC1RST_Pos) /*!< SC1 reset is one of the SYS_ResetModule parameter */
#define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */ #define SC2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SC2RST_Pos) /*!< SC2 reset is one of the SYS_ResetModule parameter */
#define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */ #define SPI3_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI3RST_Pos) /*!< SPI3 reset is one of the SYS_ResetModule parameter */
#define SPI5_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_SPI5RST_Pos) /*!< SPI5 reset is one of the SYS_ResetModule parameter */
#define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */ #define USCI0_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI0RST_Pos) /*!< USCI0 reset is one of the SYS_ResetModule parameter */
#define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */ #define USCI1_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI1RST_Pos) /*!< USCI1 reset is one of the SYS_ResetModule parameter */
#define USCI2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI2RST_Pos) /*!< USCI2 reset is one of the SYS_ResetModule parameter */ #define USCI2_RST ((0x8UL<<24)|(uint32_t)SYS_IPRST2_USCI2RST_Pos) /*!< USCI2 reset is one of the SYS_ResetModule parameter */
@ -117,7 +115,7 @@ extern "C"
#define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */ #define SYS_USBPHY_USBROLE_STD_USBD (0x0UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB device */
#define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */ #define SYS_USBPHY_USBROLE_STD_USBH (0x1UL<<SYS_USBPHY_USBROLE_Pos) /*!< Standard USB host */
#define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */ #define SYS_USBPHY_USBROLE_ID_DEPH (0x2UL<<SYS_USBPHY_USBROLE_Pos) /*!< ID dependent device */
#define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */ #define SYS_USBPHY_USBROLE_ON_THE_GO (0x3UL<<SYS_USBPHY_USBROLE_Pos) /*!< On-The-Go device */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
@ -139,14 +137,14 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* SRAM_PWRCTL constant definitions. (Write-Protection Register) */ /* SRAMPCTL constant definitions. (Write-Protection Register) */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define SYS_SRAMPCTL_SRAM_NORMAL 0x0UL /*!< Select system SRAM power mode to normal mode */ #define SYS_SRAMPCTL_SRAM_NORMAL 0x0UL /*!< Select system SRAM power mode to normal mode */
#define SYS_SRAMPCTL_SRAM_RETENTION 0x1UL /*!< Select system SRAM power mode to retention mode */ #define SYS_SRAMPCTL_SRAM_RETENTION 0x1UL /*!< Select system SRAM power mode to retention mode */
#define SYS_SRAMPCTL_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select system SRAM power mode to power shut down mode */ #define SYS_SRAMPCTL_SRAM_POWER_SHUT_DOWN 0x2UL /*!< Select system SRAM power mode to power shut down mode */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* SRAM_PPWRCTL constant definitions. (Write-Protection Register) */ /* SRAMPPCTL constant definitions. (Write-Protection Register) */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define SYS_SRAMPPCT_SRAM_NORMAL 0x0UL /*!< Select peripheral SRAM power mode to normal mode */ #define SYS_SRAMPPCT_SRAM_NORMAL 0x0UL /*!< Select peripheral SRAM power mode to normal mode */
#define SYS_SRAMPPCT_SRAM_RETENTION 0x1UL /*!< Select peripheral SRAM power mode to retention mode */ #define SYS_SRAMPPCT_SRAM_RETENTION 0x1UL /*!< Select peripheral SRAM power mode to retention mode */
@ -367,7 +365,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC0_CH0 */ #define SYS_GPB_MFPL_PB0MFP_EADC0_CH0 (0x01UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EADC0_CH0 */
#define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_ADR9 */ #define SYS_GPB_MFPL_PB0MFP_EBI_ADR9 (0x02UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for EBI_ADR9 */
#define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SD0_CMD */ #define SYS_GPB_MFPL_PB0MFP_SD0_CMD (0x03UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SD0_CMD */
#define SYS_GPB_MFPL_PB0MFP_DSRC_WAKEUP (0x06UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for DSRC_WAKEUP */
#define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD */ #define SYS_GPB_MFPL_PB0MFP_UART2_RXD (0x07UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for UART2_RXD */
#define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/ #define SYS_GPB_MFPL_PB0MFP_SPI0_I2SMCLK (0x08UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for SPI0_I2SMCLK*/
#define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C1_SDA */ #define SYS_GPB_MFPL_PB0MFP_I2C1_SDA (0x09UL<<SYS_GPB_MFPL_PB0MFP_Pos) /*!< GPB_MFPL PB0 setting for I2C1_SDA */
@ -602,7 +599,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_RXD */ #define SYS_GPC_MFPL_PC0MFP_UART2_RXD (0x08UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for UART2_RXD */
#define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2C0_SDA */ #define SYS_GPC_MFPL_PC0MFP_I2C0_SDA (0x09UL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for I2C0_SDA */
#define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0cUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EPWM1_CH5 */ #define SYS_GPC_MFPL_PC0MFP_EPWM1_CH5 (0x0cUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for EPWM1_CH5 */
#define SYS_GPC_MFPL_PC0MFP_SPI5_MOSI (0x0dUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for SPI5_MOSI */
#define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0eUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for ACMP1_O */ #define SYS_GPC_MFPL_PC0MFP_ACMP1_O (0x0eUL<<SYS_GPC_MFPL_PC0MFP_Pos) /*!< GPC_MFPL PC0 setting for ACMP1_O */
/* PC.1 MFP */ /* PC.1 MFP */
@ -615,7 +611,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_TXD */ #define SYS_GPC_MFPL_PC1MFP_UART2_TXD (0x08UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for UART2_TXD */
#define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2C0_SCL */ #define SYS_GPC_MFPL_PC1MFP_I2C0_SCL (0x09UL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for I2C0_SCL */
#define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0cUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EPWM1_CH4 */ #define SYS_GPC_MFPL_PC1MFP_EPWM1_CH4 (0x0cUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for EPWM1_CH4 */
#define SYS_GPC_MFPL_PC1MFP_SPI5_MISO (0x0dUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for SPI5_MISO */
#define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0eUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ACMP0_O */ #define SYS_GPC_MFPL_PC1MFP_ACMP0_O (0x0eUL<<SYS_GPC_MFPL_PC1MFP_Pos) /*!< GPC_MFPL PC1 setting for ACMP0_O */
/* PC.2 MFP */ /* PC.2 MFP */
@ -629,7 +624,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS */ #define SYS_GPC_MFPL_PC2MFP_I2C0_SMBSUS (0x09UL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for I2C0_SMBSUS */
#define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0bUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART3_RXD */ #define SYS_GPC_MFPL_PC2MFP_UART3_RXD (0x0bUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for UART3_RXD */
#define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0cUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EPWM1_CH3 */ #define SYS_GPC_MFPL_PC2MFP_EPWM1_CH3 (0x0cUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for EPWM1_CH3 */
#define SYS_GPC_MFPL_PC2MFP_SPI5_CLK (0x0dUL<<SYS_GPC_MFPL_PC2MFP_Pos) /*!< GPC_MFPL PC2 setting for SPI5_CLK */
/* PC.3 MFP */ /* PC.3 MFP */
#define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO */ #define SYS_GPC_MFPL_PC3MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for GPIO */
@ -642,7 +636,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2C0_SMBAL */ #define SYS_GPC_MFPL_PC3MFP_I2C0_SMBAL (0x09UL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for I2C0_SMBAL */
#define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0bUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART3_TXD */ #define SYS_GPC_MFPL_PC3MFP_UART3_TXD (0x0bUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for UART3_TXD */
#define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0cUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EPWM1_CH2 */ #define SYS_GPC_MFPL_PC3MFP_EPWM1_CH2 (0x0cUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for EPWM1_CH2 */
#define SYS_GPC_MFPL_PC3MFP_SPI5_SS (0x0dUL<<SYS_GPC_MFPL_PC3MFP_Pos) /*!< GPC_MFPL PC3 setting for SPI5_SS */
/* PC.4 MFP */ /* PC.4 MFP */
#define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO */ #define SYS_GPC_MFPL_PC4MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for GPIO */
@ -656,7 +649,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0aUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for CAN0_RXD */ #define SYS_GPC_MFPL_PC4MFP_CAN0_RXD (0x0aUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for CAN0_RXD */
#define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0bUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART4_RXD */ #define SYS_GPC_MFPL_PC4MFP_UART4_RXD (0x0bUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for UART4_RXD */
#define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0cUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EPWM1_CH1 */ #define SYS_GPC_MFPL_PC4MFP_EPWM1_CH1 (0x0cUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for EPWM1_CH1 */
#define SYS_GPC_MFPL_PC4MFP_DSRC_RXON (0x0dUL<<SYS_GPC_MFPL_PC4MFP_Pos) /*!< GPC_MFPL PC4 setting for DSRC_RXON */
/* PC.5 MFP */ /* PC.5 MFP */
#define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO */ #define SYS_GPC_MFPL_PC5MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for GPIO */
@ -667,7 +659,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0aUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CAN0_TXD */ #define SYS_GPC_MFPL_PC5MFP_CAN0_TXD (0x0aUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for CAN0_TXD */
#define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0bUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART4_TXD */ #define SYS_GPC_MFPL_PC5MFP_UART4_TXD (0x0bUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for UART4_TXD */
#define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0cUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EPWM1_CH0 */ #define SYS_GPC_MFPL_PC5MFP_EPWM1_CH0 (0x0cUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for EPWM1_CH0 */
#define SYS_GPC_MFPL_PC5MFP_DSRC_TXON (0x0dUL<<SYS_GPC_MFPL_PC5MFP_Pos) /*!< GPC_MFPL PC5 setting for DSRC_TXON */
/* PC.6 MFP */ /* PC.6 MFP */
#define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO */ #define SYS_GPC_MFPL_PC6MFP_GPIO (0x00UL<<SYS_GPC_MFPL_PC6MFP_Pos) /*!< GPC_MFPL PC6 setting for GPIO */
@ -827,7 +818,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_AD6 */ #define SYS_GPD_MFPH_PD8MFP_EBI_AD6 (0x02UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for EBI_AD6 */
#define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C2_SDA */ #define SYS_GPD_MFPH_PD8MFP_I2C2_SDA (0x03UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for I2C2_SDA */
#define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART2_nRTS */ #define SYS_GPD_MFPH_PD8MFP_UART2_nRTS (0x04UL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for UART2_nRTS */
#define SYS_GPD_MFPH_PD8MFP_DSRC_WAKEUP (0x0dUL<<SYS_GPD_MFPH_PD8MFP_Pos) /*!< GPD_MFPH PD8 setting for DSRC_WAKEUP */
/* PD.9 MFP */ /* PD.9 MFP */
#define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO */ #define SYS_GPD_MFPH_PD9MFP_GPIO (0x00UL<<SYS_GPD_MFPH_PD9MFP_Pos) /*!< GPD_MFPH PD9 setting for GPIO */
@ -899,7 +889,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART3_TXD */ #define SYS_GPE_MFPL_PE1MFP_UART3_TXD (0x07UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART3_TXD */
#define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2C1_SCL */ #define SYS_GPE_MFPL_PE1MFP_I2C1_SCL (0x08UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for I2C1_SCL */
#define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART4_nCTS */ #define SYS_GPE_MFPL_PE1MFP_UART4_nCTS (0x09UL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for UART4_nCTS */
#define SYS_GPE_MFPL_PE1MFP_DSRC_WAKEUP (0x0aUL<<SYS_GPE_MFPL_PE1MFP_Pos) /*!< GPE_MFPL PE1 setting for DSRC_WAKEUP */
/* PE.2 MFP */ /* PE.2 MFP */
#define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO */ #define SYS_GPE_MFPL_PE2MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for GPIO */
@ -908,7 +897,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI3_MOSI */ #define SYS_GPE_MFPL_PE2MFP_SPI3_MOSI (0x05UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI3_MOSI */
#define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SC0_CLK */ #define SYS_GPE_MFPL_PE2MFP_SC0_CLK (0x06UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SC0_CLK */
#define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for USCI0_CLK */ #define SYS_GPE_MFPL_PE2MFP_USCI0_CLK (0x07UL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for USCI0_CLK */
#define SYS_GPE_MFPL_PE2MFP_SPI5_MOSI (0x0aUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for SPI5_MOSI */
#define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0bUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for QEI0_B */ #define SYS_GPE_MFPL_PE2MFP_QEI0_B (0x0bUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for QEI0_B */
#define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0cUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EPWM0_CH5 */ #define SYS_GPE_MFPL_PE2MFP_EPWM0_CH5 (0x0cUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for EPWM0_CH5 */
#define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0dUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for BPWM0_CH0 */ #define SYS_GPE_MFPL_PE2MFP_BPWM0_CH0 (0x0dUL<<SYS_GPE_MFPL_PE2MFP_Pos) /*!< GPE_MFPL PE2 setting for BPWM0_CH0 */
@ -920,7 +908,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI3_MISO */ #define SYS_GPE_MFPL_PE3MFP_SPI3_MISO (0x05UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI3_MISO */
#define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SC0_DAT */ #define SYS_GPE_MFPL_PE3MFP_SC0_DAT (0x06UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SC0_DAT */
#define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for USCI0_DAT0 */ #define SYS_GPE_MFPL_PE3MFP_USCI0_DAT0 (0x07UL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for USCI0_DAT0 */
#define SYS_GPE_MFPL_PE3MFP_SPI5_MISO (0x0aUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for SPI5_MISO */
#define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0bUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for QEI0_A */ #define SYS_GPE_MFPL_PE3MFP_QEI0_A (0x0bUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for QEI0_A */
#define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0cUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EPWM0_CH4 */ #define SYS_GPE_MFPL_PE3MFP_EPWM0_CH4 (0x0cUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for EPWM0_CH4 */
#define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0dUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for BPWM0_CH1 */ #define SYS_GPE_MFPL_PE3MFP_BPWM0_CH1 (0x0dUL<<SYS_GPE_MFPL_PE3MFP_Pos) /*!< GPE_MFPL PE3 setting for BPWM0_CH1 */
@ -932,7 +919,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI3_CLK */ #define SYS_GPE_MFPL_PE4MFP_SPI3_CLK (0x05UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI3_CLK */
#define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_RST */ #define SYS_GPE_MFPL_PE4MFP_SC0_RST (0x06UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SC0_RST */
#define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for USCI0_DAT1 */ #define SYS_GPE_MFPL_PE4MFP_USCI0_DAT1 (0x07UL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for USCI0_DAT1 */
#define SYS_GPE_MFPL_PE4MFP_SPI5_CLK (0x0aUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for SPI5_CLK */
#define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0bUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for QEI0_INDEX */ #define SYS_GPE_MFPL_PE4MFP_QEI0_INDEX (0x0bUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for QEI0_INDEX */
#define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0cUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EPWM0_CH3 */ #define SYS_GPE_MFPL_PE4MFP_EPWM0_CH3 (0x0cUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for EPWM0_CH3 */
#define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0dUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for BPWM0_CH2 */ #define SYS_GPE_MFPL_PE4MFP_BPWM0_CH2 (0x0dUL<<SYS_GPE_MFPL_PE4MFP_Pos) /*!< GPE_MFPL PE4 setting for BPWM0_CH2 */
@ -944,7 +930,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI3_SS */ #define SYS_GPE_MFPL_PE5MFP_SPI3_SS (0x05UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI3_SS */
#define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_PWR */ #define SYS_GPE_MFPL_PE5MFP_SC0_PWR (0x06UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SC0_PWR */
#define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for USCI0_CTL1 */ #define SYS_GPE_MFPL_PE5MFP_USCI0_CTL1 (0x07UL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for USCI0_CTL1 */
#define SYS_GPE_MFPL_PE5MFP_SPI5_SS (0x0aUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for SPI5_SS */
#define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0bUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for QEI1_B */ #define SYS_GPE_MFPL_PE5MFP_QEI1_B (0x0bUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for QEI1_B */
#define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0cUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EPWM0_CH2 */ #define SYS_GPE_MFPL_PE5MFP_EPWM0_CH2 (0x0cUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for EPWM0_CH2 */
#define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0dUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for BPWM0_CH3 */ #define SYS_GPE_MFPL_PE5MFP_BPWM0_CH3 (0x0dUL<<SYS_GPE_MFPL_PE5MFP_Pos) /*!< GPE_MFPL PE5 setting for BPWM0_CH3 */
@ -956,7 +941,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SC0_nCD */ #define SYS_GPE_MFPL_PE6MFP_SC0_nCD (0x06UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for SC0_nCD */
#define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for USCI0_CTL0 */ #define SYS_GPE_MFPL_PE6MFP_USCI0_CTL0 (0x07UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for USCI0_CTL0 */
#define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for UART5_RXD */ #define SYS_GPE_MFPL_PE6MFP_UART5_RXD (0x08UL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for UART5_RXD */
#define SYS_GPE_MFPL_PE6MFP_DSRC_RXON (0x0aUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for DSRC_RXON */
#define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0bUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for QEI1_A */ #define SYS_GPE_MFPL_PE6MFP_QEI1_A (0x0bUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for QEI1_A */
#define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0cUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EPWM0_CH1 */ #define SYS_GPE_MFPL_PE6MFP_EPWM0_CH1 (0x0cUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for EPWM0_CH1 */
#define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0dUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for BPWM0_CH4 */ #define SYS_GPE_MFPL_PE6MFP_BPWM0_CH4 (0x0dUL<<SYS_GPE_MFPL_PE6MFP_Pos) /*!< GPE_MFPL PE6 setting for BPWM0_CH4 */
@ -965,7 +949,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO */ #define SYS_GPE_MFPL_PE7MFP_GPIO (0x00UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for GPIO */
#define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CMD */ #define SYS_GPE_MFPL_PE7MFP_SD0_CMD (0x03UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for SD0_CMD */
#define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for UART5_TXD */ #define SYS_GPE_MFPL_PE7MFP_UART5_TXD (0x08UL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for UART5_TXD */
#define SYS_GPE_MFPL_PE7MFP_DSRC_TXON (0x0aUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for DSRC_TXON */
#define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0bUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for QEI1_INDEX */ #define SYS_GPE_MFPL_PE7MFP_QEI1_INDEX (0x0bUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for QEI1_INDEX */
#define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0cUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for EPWM0_CH0 */ #define SYS_GPE_MFPL_PE7MFP_EPWM0_CH0 (0x0cUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for EPWM0_CH0 */
#define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0dUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for BPWM0_CH5 */ #define SYS_GPE_MFPL_PE7MFP_BPWM0_CH5 (0x0dUL<<SYS_GPE_MFPL_PE7MFP_Pos) /*!< GPE_MFPL PE7 setting for BPWM0_CH5 */
@ -980,7 +963,7 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0aUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_CH0 */ #define SYS_GPE_MFPH_PE8MFP_EPWM0_CH0 (0x0aUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_CH0 */
#define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0bUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/ #define SYS_GPE_MFPH_PE8MFP_EPWM0_BRAKE0 (0x0bUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for EPWM0_BRAKE0*/
#define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0cUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ECAP0_IC0 */ #define SYS_GPE_MFPH_PE8MFP_ECAP0_IC0 (0x0cUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for ECAP0_IC0 */
#define SYS_GPE_MFPH_PE8MFP_TRACE_CLK (0x0eUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TRACE_CLK */ #define SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 (0x0eUL<<SYS_GPE_MFPH_PE8MFP_Pos) /*!< GPE_MFPH PE8 setting for TRACE_DATA3 */
/* PE.9 MFP */ /* PE.9 MFP */
#define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO */ #define SYS_GPE_MFPH_PE9MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for GPIO */
@ -992,7 +975,7 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0aUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_CH1 */ #define SYS_GPE_MFPH_PE9MFP_EPWM0_CH1 (0x0aUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_CH1 */
#define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/ #define SYS_GPE_MFPH_PE9MFP_EPWM0_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for EPWM0_BRAKE1*/
#define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0cUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ECAP0_IC1 */ #define SYS_GPE_MFPH_PE9MFP_ECAP0_IC1 (0x0cUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for ECAP0_IC1 */
#define SYS_GPE_MFPH_PE9MFP_TRACE_DATA0 (0x0eUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for TRACE_DATA0 */ #define SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 (0x0eUL<<SYS_GPE_MFPH_PE9MFP_Pos) /*!< GPE_MFPH PE9 setting for TRACE_DATA2 */
/* PE.10 MFP */ /* PE.10 MFP */
#define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for GPIO */ #define SYS_GPE_MFPH_PE10MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE10MFP_Pos)/*!< GPE_MFPH PE10 setting for GPIO */
@ -1017,7 +1000,7 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0aUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM0_CH3 */ #define SYS_GPE_MFPH_PE11MFP_EPWM0_CH3 (0x0aUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM0_CH3 */
#define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/ #define SYS_GPE_MFPH_PE11MFP_EPWM1_BRAKE1 (0x0bUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for EPWM1_BRAKE1*/
#define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0dUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for ECAP1_IC2 */ #define SYS_GPE_MFPH_PE11MFP_ECAP1_IC2 (0x0dUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for ECAP1_IC2 */
#define SYS_GPE_MFPH_PE11MFP_TRACE_DATA2 (0x0eUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for TRACE_DATA2*/ #define SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 (0x0eUL<<SYS_GPE_MFPH_PE11MFP_Pos)/*!< GPE_MFPH PE11 setting for TRACE_DATA0*/
/* PE.12 MFP */ /* PE.12 MFP */
#define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for GPIO */ #define SYS_GPE_MFPH_PE12MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for GPIO */
@ -1028,7 +1011,7 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for UART1_nRTS */ #define SYS_GPE_MFPH_PE12MFP_UART1_nRTS (0x08UL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for UART1_nRTS */
#define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0aUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EPWM0_CH4 */ #define SYS_GPE_MFPH_PE12MFP_EPWM0_CH4 (0x0aUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for EPWM0_CH4 */
#define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0dUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for ECAP1_IC1 */ #define SYS_GPE_MFPH_PE12MFP_ECAP1_IC1 (0x0dUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for ECAP1_IC1 */
#define SYS_GPE_MFPH_PE12MFP_TRACE_DATA3 (0x0eUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for TRACE_DATA3*/ #define SYS_GPE_MFPH_PE12MFP_TRACE_CLK (0x0eUL<<SYS_GPE_MFPH_PE12MFP_Pos)/*!< GPE_MFPH PE12 setting for TRACE_CLK */
/* PE.13 MFP */ /* PE.13 MFP */
#define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for GPIO */ #define SYS_GPE_MFPH_PE13MFP_GPIO (0x00UL<<SYS_GPE_MFPH_PE13MFP_Pos)/*!< GPE_MFPH PE13 setting for GPIO */
@ -1175,42 +1158,35 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
/* PG.9 MFP */ /* PG.9 MFP */
#define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO */ #define SYS_GPG_MFPH_PG9MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for GPIO */
#define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for EBI_AD0 */ #define SYS_GPG_MFPH_PG9MFP_EBI_AD0 (0x02UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for EBI_AD0 */
#define SYS_GPG_MFPH_PG9MFP_SPI5_MISO (0x04UL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for SPI5_MISO */
#define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0cUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for BPWM0_CH5 */ #define SYS_GPG_MFPH_PG9MFP_BPWM0_CH5 (0x0cUL<<SYS_GPG_MFPH_PG9MFP_Pos) /*!< GPG_MFPH PG9 setting for BPWM0_CH5 */
/* PG.10 MFP */ /* PG.10 MFP */
#define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for GPIO */ #define SYS_GPG_MFPH_PG10MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for GPIO */
#define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for EBI_AD1 */ #define SYS_GPG_MFPH_PG10MFP_EBI_AD1 (0x02UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for EBI_AD1 */
#define SYS_GPG_MFPH_PG10MFP_SPI5_MOSI (0x04UL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for SPI5_MOSI */
#define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0cUL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for BPWM0_CH4 */ #define SYS_GPG_MFPH_PG10MFP_BPWM0_CH4 (0x0cUL<<SYS_GPG_MFPH_PG10MFP_Pos)/*!< GPG_MFPH PG10 setting for BPWM0_CH4 */
/* PG.11 MFP */ /* PG.11 MFP */
#define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for GPIO */ #define SYS_GPG_MFPH_PG11MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for GPIO */
#define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for EBI_AD2 */ #define SYS_GPG_MFPH_PG11MFP_EBI_AD2 (0x02UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for EBI_AD2 */
#define SYS_GPG_MFPH_PG11MFP_SPI5_CLK (0x04UL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for SPI5_CLK */
#define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0cUL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for BPWM0_CH3 */ #define SYS_GPG_MFPH_PG11MFP_BPWM0_CH3 (0x0cUL<<SYS_GPG_MFPH_PG11MFP_Pos)/*!< GPG_MFPH PG11 setting for BPWM0_CH3 */
/* PG.12 MFP */ /* PG.12 MFP */
#define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for GPIO */ #define SYS_GPG_MFPH_PG12MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for GPIO */
#define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for EBI_AD3 */ #define SYS_GPG_MFPH_PG12MFP_EBI_AD3 (0x02UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for EBI_AD3 */
#define SYS_GPG_MFPH_PG12MFP_SPI5_SS (0x04UL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for SPI5_SS */
#define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0cUL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for BPWM0_CH2 */ #define SYS_GPG_MFPH_PG12MFP_BPWM0_CH2 (0x0cUL<<SYS_GPG_MFPH_PG12MFP_Pos)/*!< GPG_MFPH PG12 setting for BPWM0_CH2 */
/* PG.13 MFP */ /* PG.13 MFP */
#define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for GPIO */ #define SYS_GPG_MFPH_PG13MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for GPIO */
#define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for EBI_AD4 */ #define SYS_GPG_MFPH_PG13MFP_EBI_AD4 (0x02UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for EBI_AD4 */
#define SYS_GPG_MFPH_PG13MFP_DSRC_TXON (0x04UL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for DSRC_TXON */
#define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0cUL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for BPWM0_CH1 */ #define SYS_GPG_MFPH_PG13MFP_BPWM0_CH1 (0x0cUL<<SYS_GPG_MFPH_PG13MFP_Pos)/*!< GPG_MFPH PG13 setting for BPWM0_CH1 */
/* PG.14 MFP */ /* PG.14 MFP */
#define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for GPIO */ #define SYS_GPG_MFPH_PG14MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for GPIO */
#define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for EBI_AD5 */ #define SYS_GPG_MFPH_PG14MFP_EBI_AD5 (0x02UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for EBI_AD5 */
#define SYS_GPG_MFPH_PG14MFP_DSRC_RXON (0x04UL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for DSRC_RXON */
#define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0cUL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for BPWM0_CH0 */ #define SYS_GPG_MFPH_PG14MFP_BPWM0_CH0 (0x0cUL<<SYS_GPG_MFPH_PG14MFP_Pos)/*!< GPG_MFPH PG14 setting for BPWM0_CH0 */
/* PG.15 MFP */ /* PG.15 MFP */
#define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for GPIO */ #define SYS_GPG_MFPH_PG15MFP_GPIO (0x00UL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for GPIO */
#define SYS_GPG_MFPH_PG15MFP_DSRC_WAKEUP (0x04UL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for DSRC_WAKEUP*/
#define SYS_GPG_MFPH_PG15MFP_CLKO (0x0eUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for CLKO */ #define SYS_GPG_MFPH_PG15MFP_CLKO (0x0eUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for CLKO */
#define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0fUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for EADC0_ST */ #define SYS_GPG_MFPH_PG15MFP_EADC0_ST (0x0fUL<<SYS_GPG_MFPH_PG15MFP_Pos)/*!< GPG_MFPH PG15 setting for EADC0_ST */
@ -1367,16 +1343,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define DAC1_OUT_PB13 SYS_GPB_MFPH_PB13MFP_DAC1_OUT /*!< GPB_MFPH PB13 setting for DAC1_OUT*/ #define DAC1_OUT_PB13 SYS_GPB_MFPH_PB13MFP_DAC1_OUT /*!< GPB_MFPH PB13 setting for DAC1_OUT*/
#define DAC1_ST_PA1 SYS_GPA_MFPL_PA1MFP_DAC1_ST /*!< GPA_MFPL PA1 setting for DAC1_ST*/ #define DAC1_ST_PA1 SYS_GPA_MFPL_PA1MFP_DAC1_ST /*!< GPA_MFPL PA1 setting for DAC1_ST*/
#define DAC1_ST_PA11 SYS_GPA_MFPH_PA11MFP_DAC1_ST /*!< GPA_MFPH PA11 setting for DAC1_ST*/ #define DAC1_ST_PA11 SYS_GPA_MFPH_PA11MFP_DAC1_ST /*!< GPA_MFPH PA11 setting for DAC1_ST*/
#define DSRC_RXON_PG14 SYS_GPG_MFPH_PG14MFP_DSRC_RXON /*!< GPG_MFPH PG14 setting for DSRC_RXON*/
#define DSRC_RXON_PC4 SYS_GPC_MFPL_PC4MFP_DSRC_RXON /*!< GPC_MFPL PC4 setting for DSRC_RXON*/
#define DSRC_RXON_PE6 SYS_GPE_MFPL_PE6MFP_DSRC_RXON /*!< GPE_MFPL PE6 setting for DSRC_RXON*/
#define DSRC_TXON_PE7 SYS_GPE_MFPL_PE7MFP_DSRC_TXON /*!< GPE_MFPL PE7 setting for DSRC_TXON*/
#define DSRC_TXON_PG13 SYS_GPG_MFPH_PG13MFP_DSRC_TXON /*!< GPG_MFPH PG13 setting for DSRC_TXON*/
#define DSRC_TXON_PC5 SYS_GPC_MFPL_PC5MFP_DSRC_TXON /*!< GPC_MFPL PC5 setting for DSRC_TXON*/
#define DSRC_WAKEUP_PE1 SYS_GPE_MFPL_PE1MFP_DSRC_WAKEUP /*!< GPE_MFPL PE1 setting for DSRC_WAKEUP*/
#define DSRC_WAKEUP_PB0 SYS_GPB_MFPL_PB0MFP_DSRC_WAKEUP /*!< GPB_MFPL PB0 setting for DSRC_WAKEUP*/
#define DSRC_WAKEUP_PG15 SYS_GPG_MFPH_PG15MFP_DSRC_WAKEUP /*!< GPG_MFPH PG15 setting for DSRC_WAKEUP*/
#define DSRC_WAKEUP_PD8 SYS_GPD_MFPH_PD8MFP_DSRC_WAKEUP /*!< GPD_MFPH PD8 setting for DSRC_WAKEUP*/
#define EADC0_CH0_PB0 SYS_GPB_MFPL_PB0MFP_EADC0_CH0 /*!< GPB_MFPL PB0 setting for EADC0_CH0*/ #define EADC0_CH0_PB0 SYS_GPB_MFPL_PB0MFP_EADC0_CH0 /*!< GPB_MFPL PB0 setting for EADC0_CH0*/
#define EADC0_CH1_PB1 SYS_GPB_MFPL_PB1MFP_EADC0_CH1 /*!< GPB_MFPL PB1 setting for EADC0_CH1*/ #define EADC0_CH1_PB1 SYS_GPB_MFPL_PB1MFP_EADC0_CH1 /*!< GPB_MFPL PB1 setting for EADC0_CH1*/
#define EADC0_CH10_PB10 SYS_GPB_MFPH_PB10MFP_EADC0_CH10 /*!< GPB_MFPH PB10 setting for EADC0_CH10*/ #define EADC0_CH10_PB10 SYS_GPB_MFPH_PB10MFP_EADC0_CH10 /*!< GPB_MFPH PB10 setting for EADC0_CH10*/
@ -1860,18 +1826,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SPI3_SS_PE5 SYS_GPE_MFPL_PE5MFP_SPI3_SS /*!< GPE_MFPL PE5 setting for SPI3_SS*/ #define SPI3_SS_PE5 SYS_GPE_MFPL_PE5MFP_SPI3_SS /*!< GPE_MFPL PE5 setting for SPI3_SS*/
#define SPI3_SS_PB10 SYS_GPB_MFPH_PB10MFP_SPI3_SS /*!< GPB_MFPH PB10 setting for SPI3_SS*/ #define SPI3_SS_PB10 SYS_GPB_MFPH_PB10MFP_SPI3_SS /*!< GPB_MFPH PB10 setting for SPI3_SS*/
#define SPI3_SS_PC9 SYS_GPC_MFPH_PC9MFP_SPI3_SS /*!< GPC_MFPH PC9 setting for SPI3_SS*/ #define SPI3_SS_PC9 SYS_GPC_MFPH_PC9MFP_SPI3_SS /*!< GPC_MFPH PC9 setting for SPI3_SS*/
#define SPI5_CLK_PC2 SYS_GPC_MFPL_PC2MFP_SPI5_CLK /*!< GPC_MFPL PC2 setting for SPI5_CLK*/
#define SPI5_CLK_PE4 SYS_GPE_MFPL_PE4MFP_SPI5_CLK /*!< GPE_MFPL PE4 setting for SPI5_CLK*/
#define SPI5_CLK_PG11 SYS_GPG_MFPH_PG11MFP_SPI5_CLK /*!< GPG_MFPH PG11 setting for SPI5_CLK*/
#define SPI5_MISO_PG9 SYS_GPG_MFPH_PG9MFP_SPI5_MISO /*!< GPG_MFPH PG9 setting for SPI5_MISO*/
#define SPI5_MISO_PC1 SYS_GPC_MFPL_PC1MFP_SPI5_MISO /*!< GPC_MFPL PC1 setting for SPI5_MISO*/
#define SPI5_MISO_PE3 SYS_GPE_MFPL_PE3MFP_SPI5_MISO /*!< GPE_MFPL PE3 setting for SPI5_MISO*/
#define SPI5_MOSI_PE2 SYS_GPE_MFPL_PE2MFP_SPI5_MOSI /*!< GPE_MFPL PE2 setting for SPI5_MOSI*/
#define SPI5_MOSI_PC0 SYS_GPC_MFPL_PC0MFP_SPI5_MOSI /*!< GPC_MFPL PC0 setting for SPI5_MOSI*/
#define SPI5_MOSI_PG10 SYS_GPG_MFPH_PG10MFP_SPI5_MOSI /*!< GPG_MFPH PG10 setting for SPI5_MOSI*/
#define SPI5_SS_PE5 SYS_GPE_MFPL_PE5MFP_SPI5_SS /*!< GPE_MFPL PE5 setting for SPI5_SS*/
#define SPI5_SS_PG12 SYS_GPG_MFPH_PG12MFP_SPI5_SS /*!< GPG_MFPH PG12 setting for SPI5_SS*/
#define SPI5_SS_PC3 SYS_GPC_MFPL_PC3MFP_SPI5_SS /*!< GPC_MFPL PC3 setting for SPI5_SS*/
#define TAMPER0_PF6 SYS_GPF_MFPL_PF6MFP_TAMPER0 /*!< GPF_MFPL PF6 setting for TAMPER0*/ #define TAMPER0_PF6 SYS_GPF_MFPL_PF6MFP_TAMPER0 /*!< GPF_MFPL PF6 setting for TAMPER0*/
#define TAMPER1_PF7 SYS_GPF_MFPL_PF7MFP_TAMPER1 /*!< GPF_MFPL PF7 setting for TAMPER1*/ #define TAMPER1_PF7 SYS_GPF_MFPL_PF7MFP_TAMPER1 /*!< GPF_MFPL PF7 setting for TAMPER1*/
#define TAMPER2_PF8 SYS_GPF_MFPH_PF8MFP_TAMPER2 /*!< GPF_MFPH PF8 setting for TAMPER2*/ #define TAMPER2_PF8 SYS_GPF_MFPH_PF8MFP_TAMPER2 /*!< GPF_MFPH PF8 setting for TAMPER2*/
@ -1899,11 +1853,11 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define TM3_PB2 SYS_GPB_MFPL_PB2MFP_TM3 /*!< GPB_MFPL PB2 setting for TM3*/ #define TM3_PB2 SYS_GPB_MFPL_PB2MFP_TM3 /*!< GPB_MFPL PB2 setting for TM3*/
#define TM3_EXT_PA8 SYS_GPA_MFPH_PA8MFP_TM3_EXT /*!< GPA_MFPH PA8 setting for TM3_EXT*/ #define TM3_EXT_PA8 SYS_GPA_MFPH_PA8MFP_TM3_EXT /*!< GPA_MFPH PA8 setting for TM3_EXT*/
#define TM3_EXT_PB12 SYS_GPB_MFPH_PB12MFP_TM3_EXT /*!< GPB_MFPH PB12 setting for TM3_EXT*/ #define TM3_EXT_PB12 SYS_GPB_MFPH_PB12MFP_TM3_EXT /*!< GPB_MFPH PB12 setting for TM3_EXT*/
#define TRACE_CLK_PE8 SYS_GPE_MFPH_PE8MFP_TRACE_CLK /*!< GPE_MFPH PE8 setting for TRACE_CLK*/ #define TRACE_CLK_PE12 SYS_GPE_MFPH_PE12MFP_TRACE_CLK /*!< GPE_MFPH PE12 setting for TRACE_CLK*/
#define TRACE_DATA0_PE9 SYS_GPE_MFPH_PE9MFP_TRACE_DATA0 /*!< GPE_MFPH PE9 setting for TRACE_DATA0*/ #define TRACE_DATA0_PE11 SYS_GPE_MFPH_PE11MFP_TRACE_DATA0 /*!< GPE_MFPH PE11 setting for TRACE_DATA0*/
#define TRACE_DATA1_PE10 SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 /*!< GPE_MFPH PE10 setting for TRACE_DATA1*/ #define TRACE_DATA1_PE10 SYS_GPE_MFPH_PE10MFP_TRACE_DATA1 /*!< GPE_MFPH PE10 setting for TRACE_DATA1*/
#define TRACE_DATA2_PE11 SYS_GPE_MFPH_PE11MFP_TRACE_DATA2 /*!< GPE_MFPH PE11 setting for TRACE_DATA2*/ #define TRACE_DATA2_PE9 SYS_GPE_MFPH_PE9MFP_TRACE_DATA2 /*!< GPE_MFPH PE9 setting for TRACE_DATA2*/
#define TRACE_DATA3_PE12 SYS_GPE_MFPH_PE12MFP_TRACE_DATA3 /*!< GPE_MFPH PE12 setting for TRACE_DATA3*/ #define TRACE_DATA3_PE8 SYS_GPE_MFPH_PE8MFP_TRACE_DATA3 /*!< GPE_MFPH PE8 setting for TRACE_DATA3*/
#define UART0_RXD_PD2 SYS_GPD_MFPL_PD2MFP_UART0_RXD /*!< GPD_MFPL PD2 setting for UART0_RXD*/ #define UART0_RXD_PD2 SYS_GPD_MFPL_PD2MFP_UART0_RXD /*!< GPD_MFPL PD2 setting for UART0_RXD*/
#define UART0_RXD_PB8 SYS_GPB_MFPH_PB8MFP_UART0_RXD /*!< GPB_MFPH PB8 setting for UART0_RXD*/ #define UART0_RXD_PB8 SYS_GPB_MFPH_PB8MFP_UART0_RXD /*!< GPB_MFPH PB8 setting for UART0_RXD*/
#define UART0_RXD_PA0 SYS_GPA_MFPL_PA0MFP_UART0_RXD /*!< GPA_MFPL PA0 setting for UART0_RXD*/ #define UART0_RXD_PA0 SYS_GPA_MFPL_PA0MFP_UART0_RXD /*!< GPA_MFPL PA0 setting for UART0_RXD*/
@ -2163,16 +2117,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define DAC1_OUT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! DAC1_OUT PB13 MFP Mask */ #define DAC1_OUT_PB13_Msk SYS_GPB_MFPH_PB13MFP_Msk /*<! DAC1_OUT PB13 MFP Mask */
#define DAC1_ST_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! DAC1_ST PA1 MFP Mask */ #define DAC1_ST_PA1_Msk SYS_GPA_MFPL_PA1MFP_Msk /*<! DAC1_ST PA1 MFP Mask */
#define DAC1_ST_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! DAC1_ST PA11 MFP Mask */ #define DAC1_ST_PA11_Msk SYS_GPA_MFPH_PA11MFP_Msk /*<! DAC1_ST PA11 MFP Mask */
#define DSRC_RXON_PG14_Msk SYS_GPG_MFPH_PG14MFP_Msk /*<! DSRC_RXON PG14 MFP Mask */
#define DSRC_RXON_PC4_Msk SYS_GPC_MFPL_PC4MFP_Msk /*<! DSRC_RXON PC4 MFP Mask */
#define DSRC_RXON_PE6_Msk SYS_GPE_MFPL_PE6MFP_Msk /*<! DSRC_RXON PE6 MFP Mask */
#define DSRC_TXON_PE7_Msk SYS_GPE_MFPL_PE7MFP_Msk /*<! DSRC_TXON PE7 MFP Mask */
#define DSRC_TXON_PG13_Msk SYS_GPG_MFPH_PG13MFP_Msk /*<! DSRC_TXON PG13 MFP Mask */
#define DSRC_TXON_PC5_Msk SYS_GPC_MFPL_PC5MFP_Msk /*<! DSRC_TXON PC5 MFP Mask */
#define DSRC_WAKEUP_PE1_Msk SYS_GPE_MFPL_PE1MFP_Msk /*<! DSRC_WAKEUP PE1 MFP Mask */
#define DSRC_WAKEUP_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! DSRC_WAKEUP PB0 MFP Mask */
#define DSRC_WAKEUP_PG15_Msk SYS_GPG_MFPH_PG15MFP_Msk /*<! DSRC_WAKEUP PG15 MFP Mask */
#define DSRC_WAKEUP_PD8_Msk SYS_GPD_MFPH_PD8MFP_Msk /*<! DSRC_WAKEUP PD8 MFP Mask */
#define EADC0_CH0_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EADC0_CH0 PB0 MFP Mask */ #define EADC0_CH0_PB0_Msk SYS_GPB_MFPL_PB0MFP_Msk /*<! EADC0_CH0 PB0 MFP Mask */
#define EADC0_CH1_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EADC0_CH1 PB1 MFP Mask */ #define EADC0_CH1_PB1_Msk SYS_GPB_MFPL_PB1MFP_Msk /*<! EADC0_CH1 PB1 MFP Mask */
#define EADC0_CH10_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EADC0_CH10 PB10 MFP Mask */ #define EADC0_CH10_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! EADC0_CH10 PB10 MFP Mask */
@ -2656,18 +2600,6 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define SPI3_SS_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SPI3_SS PE5 MFP Mask */ #define SPI3_SS_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SPI3_SS PE5 MFP Mask */
#define SPI3_SS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! SPI3_SS PB10 MFP Mask */ #define SPI3_SS_PB10_Msk SYS_GPB_MFPH_PB10MFP_Msk /*<! SPI3_SS PB10 MFP Mask */
#define SPI3_SS_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! SPI3_SS PC9 MFP Mask */ #define SPI3_SS_PC9_Msk SYS_GPC_MFPH_PC9MFP_Msk /*<! SPI3_SS PC9 MFP Mask */
#define SPI5_CLK_PC2_Msk SYS_GPC_MFPL_PC2MFP_Msk /*<! SPI5_CLK PC2 MFP Mask */
#define SPI5_CLK_PE4_Msk SYS_GPE_MFPL_PE4MFP_Msk /*<! SPI5_CLK PE4 MFP Mask */
#define SPI5_CLK_PG11_Msk SYS_GPG_MFPH_PG11MFP_Msk /*<! SPI5_CLK PG11 MFP Mask */
#define SPI5_MISO_PG9_Msk SYS_GPG_MFPH_PG9MFP_Msk /*<! SPI5_MISO PG9 MFP Mask */
#define SPI5_MISO_PC1_Msk SYS_GPC_MFPL_PC1MFP_Msk /*<! SPI5_MISO PC1 MFP Mask */
#define SPI5_MISO_PE3_Msk SYS_GPE_MFPL_PE3MFP_Msk /*<! SPI5_MISO PE3 MFP Mask */
#define SPI5_MOSI_PE2_Msk SYS_GPE_MFPL_PE2MFP_Msk /*<! SPI5_MOSI PE2 MFP Mask */
#define SPI5_MOSI_PC0_Msk SYS_GPC_MFPL_PC0MFP_Msk /*<! SPI5_MOSI PC0 MFP Mask */
#define SPI5_MOSI_PG10_Msk SYS_GPG_MFPH_PG10MFP_Msk /*<! SPI5_MOSI PG10 MFP Mask */
#define SPI5_SS_PE5_Msk SYS_GPE_MFPL_PE5MFP_Msk /*<! SPI5_SS PE5 MFP Mask */
#define SPI5_SS_PG12_Msk SYS_GPG_MFPH_PG12MFP_Msk /*<! SPI5_SS PG12 MFP Mask */
#define SPI5_SS_PC3_Msk SYS_GPC_MFPL_PC3MFP_Msk /*<! SPI5_SS PC3 MFP Mask */
#define TAMPER0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! TAMPER0 PF6 MFP Mask */ #define TAMPER0_PF6_Msk SYS_GPF_MFPL_PF6MFP_Msk /*<! TAMPER0 PF6 MFP Mask */
#define TAMPER1_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! TAMPER1 PF7 MFP Mask */ #define TAMPER1_PF7_Msk SYS_GPF_MFPL_PF7MFP_Msk /*<! TAMPER1 PF7 MFP Mask */
#define TAMPER2_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! TAMPER2 PF8 MFP Mask */ #define TAMPER2_PF8_Msk SYS_GPF_MFPH_PF8MFP_Msk /*<! TAMPER2 PF8 MFP Mask */
@ -2695,11 +2627,11 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
#define TM3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! TM3 PB2 MFP Mask */ #define TM3_PB2_Msk SYS_GPB_MFPL_PB2MFP_Msk /*<! TM3 PB2 MFP Mask */
#define TM3_EXT_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! TM3_EXT PA8 MFP Mask */ #define TM3_EXT_PA8_Msk SYS_GPA_MFPH_PA8MFP_Msk /*<! TM3_EXT PA8 MFP Mask */
#define TM3_EXT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! TM3_EXT PB12 MFP Mask */ #define TM3_EXT_PB12_Msk SYS_GPB_MFPH_PB12MFP_Msk /*<! TM3_EXT PB12 MFP Mask */
#define TRACE_CLK_PE8_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! TRACE_CLK PE8 MFP Mask */ #define TRACE_CLK_PE12_Msk SYS_GPE_MFPH_PE8MFP_Msk /*<! TRACE_CLK PE12 MFP Mask */
#define TRACE_DATA0_PE9_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! TRACE_DATA0 PE9 MFP Mask */ #define TRACE_DATA0_PE11_Msk SYS_GPE_MFPH_PE9MFP_Msk /*<! TRACE_DATA0 PE11 MFP Mask */
#define TRACE_DATA1_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! TRACE_DATA1 PE10 MFP Mask */ #define TRACE_DATA1_PE10_Msk SYS_GPE_MFPH_PE10MFP_Msk /*<! TRACE_DATA1 PE10 MFP Mask */
#define TRACE_DATA2_PE11_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! TRACE_DATA2 PE11 MFP Mask */ #define TRACE_DATA2_PE9_Msk SYS_GPE_MFPH_PE11MFP_Msk /*<! TRACE_DATA2 PE9 MFP Mask */
#define TRACE_DATA3_PE12_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! TRACE_DATA3 PE12 MFP Mask */ #define TRACE_DATA3_PE8_Msk SYS_GPE_MFPH_PE12MFP_Msk /*<! TRACE_DATA3 PE8 MFP Mask */
#define UART0_RXD_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART0_RXD PD2 MFP Mask */ #define UART0_RXD_PD2_Msk SYS_GPD_MFPL_PD2MFP_Msk /*<! UART0_RXD PD2 MFP Mask */
#define UART0_RXD_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART0_RXD PB8 MFP Mask */ #define UART0_RXD_PB8_Msk SYS_GPB_MFPH_PB8MFP_Msk /*<! UART0_RXD PB8 MFP Mask */
#define UART0_RXD_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART0_RXD PA0 MFP Mask */ #define UART0_RXD_PA0_Msk SYS_GPA_MFPL_PA0MFP_Msk /*<! UART0_RXD PA0 MFP Mask */
@ -3082,7 +3014,7 @@ Example: If user want to set PA.1 as UART0_TXD and PA.0 as UART0_RXD in initial
* - \ref SYS_RSTSTS_WDTRF_Msk * - \ref SYS_RSTSTS_WDTRF_Msk
* - \ref SYS_RSTSTS_LVRF_Msk * - \ref SYS_RSTSTS_LVRF_Msk
* - \ref SYS_RSTSTS_BODRF_Msk * - \ref SYS_RSTSTS_BODRF_Msk
* - \ref SYS_RSTSTS_MCURF_Msk * - \ref SYS_RSTSTS_SYSRF_Msk
* - \ref SYS_RSTSTS_CPURF_Msk * - \ref SYS_RSTSTS_CPURF_Msk
* - \ref SYS_RSTSTS_CPULKRF_Msk * - \ref SYS_RSTSTS_CPULKRF_Msk
* @return None * @return None

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_timer.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_timer.h
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0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_timer_pwm.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_timer_pwm.h
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12
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_uart.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_uart.h
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@ -66,8 +66,8 @@ extern "C"
#define UART_PARITY_MARK (0x5UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */ #define UART_PARITY_MARK (0x5UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '1' */
#define UART_PARITY_SPACE (0x7UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */ #define UART_PARITY_SPACE (0x7UL << UART_LINE_PBE_Pos) /*!< UART_LINE setting to keep parity bit as '0' */
#define UART_STOP_BIT_1 (0x0UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */ #define UART_STOP_BIT_1 (0x0UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for one stop bit */
#define UART_STOP_BIT_1_5 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */ #define UART_STOP_BIT_1_5 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for 1.5 stop bit when 5-bit word length */
#define UART_STOP_BIT_2 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */ #define UART_STOP_BIT_2 (0x1UL << UART_LINE_NSB_Pos) /*!< UART_LINE setting for two stop bit when 6, 7, 8-bit word length */
@ -88,10 +88,10 @@ extern "C"
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
/* UART_FUNCSEL constants definitions */ /* UART_FUNCSEL constants definitions */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/
#define UART_FUNCSEL_UART (0x0UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */ #define UART_FUNCSEL_UART (0x0UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set UART Function (Default) */
#define UART_FUNCSEL_LIN (0x1UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */ #define UART_FUNCSEL_LIN (0x1UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set LIN Function */
#define UART_FUNCSEL_IrDA (0x2UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */ #define UART_FUNCSEL_IrDA (0x2UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set IrDA Function */
#define UART_FUNCSEL_RS485 (0x3UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */ #define UART_FUNCSEL_RS485 (0x3UL << UART_FUNCSEL_FUNCSEL_Pos) /*!< UART_FUNCSEL setting to set RS485 Function */
/*---------------------------------------------------------------------------------------------------------*/ /*---------------------------------------------------------------------------------------------------------*/

46
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_usbd.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_usbd.h
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@ -3,11 +3,13 @@
* @version V3.00 * @version V3.00
* @brief M2351 series USBD driver header file * @brief M2351 series USBD driver header file
* *
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * @copyright (C) 2018 Nuvoton Technology Corp. All rights reserved.
******************************************************************************/ ******************************************************************************/
#ifndef __USBD_H__ #ifndef __USBD_H__
#define __USBD_H__ #define __USBD_H__
#define SUPPORT_LPM // define to support LPM
#ifdef __cplusplus #ifdef __cplusplus
extern "C" extern "C"
{ {
@ -135,6 +137,7 @@ extern const S_USBD_INFO_T gsInfo;
#define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable */ #define USBD_WAKEUP_EN USBD_INTEN_WKEN_Msk /*!< USB Wake-up Enable */
#define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 */ #define USBD_DRVSE0 USBD_SE0_SE0_Msk /*!< Drive SE0 */
#define USBD_LPMACK USBD_ATTR_LPMACK_Msk /*!< LPM Enable */
#define USBD_BYTEM USBD_ATTR_BYTEM_Msk /*!< Access Size Mode Selection */ #define USBD_BYTEM USBD_ATTR_BYTEM_Msk /*!< Access Size Mode Selection */
#define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable */ #define USBD_DPPU_EN USBD_ATTR_DPPUEN_Msk /*!< USB D+ Pull-up Enable */
#define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable */ #define USBD_USB_EN USBD_ATTR_USBEN_Msk /*!< USB Enable */
@ -168,6 +171,8 @@ extern const S_USBD_INFO_T gsInfo;
#define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend */ #define USBD_STATE_SUSPEND USBD_ATTR_SUSPEND_Msk /*!< USB Bus Suspend */
#define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume */ #define USBD_STATE_RESUME USBD_ATTR_RESUME_Msk /*!< USB Bus Resume */
#define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout */ #define USBD_STATE_TIMEOUT USBD_ATTR_TOUT_Msk /*!< USB Bus Timeout */
#define USBD_STATE_L1SUSPEND USBD_ATTR_L1SUSPEND_Msk /*!< USB Bus L1SUSPEND */
#define USBD_STATE_L1RESUME USBD_ATTR_L1RESUME_Msk /*!< USB Bus L1RESUME */
#define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall */ #define USBD_CFGP_SSTALL USBD_CFGP_SSTALL_Msk /*!< Set Stall */
#define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */ #define USBD_CFG_CSTALL USBD_CFG_CSTALL_Msk /*!< Clear Stall */
@ -366,16 +371,18 @@ extern const S_USBD_INFO_T gsInfo;
* *
* @param None * @param None
* *
* @return The value of USB_ATTR[3:0]. * @return The value of USB_ATTR[13:12] and USB_ATTR[3:0].
* Bit 0 indicates USB bus reset status. * Bit 0 indicates USB bus reset status.
* Bit 1 indicates USB bus suspend status. * Bit 1 indicates USB bus suspend status.
* Bit 2 indicates USB bus resume status. * Bit 2 indicates USB bus resume status.
* Bit 3 indicates USB bus time-out status. * Bit 3 indicates USB bus time-out status.
* Bit 12 indicates USB bus LPM L1 suspend status.
* Bit 13 indicates USB bus LPM L1 resume status.
* *
* @details Return USB_ATTR[3:0] for USB bus events. * @details Return USB_ATTR[13:12] and USB_ATTR[3:0] for USB bus events.
* *
*/ */
#define USBD_GET_BUS_STATE() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0xF)):((uint32_t)(USBD->ATTR & 0xF))) #define USBD_GET_BUS_STATE() (((__PC() & NS_OFFSET) == NS_OFFSET)? ((uint32_t)(USBD_NS->ATTR & 0x300F)):((uint32_t)(USBD->ATTR & 0x300F)))
/** /**
* @brief Check cable connection state * @brief Check cable connection state
@ -530,12 +537,6 @@ extern const S_USBD_INFO_T gsInfo;
*/ */
#define USBD_GET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk)) #define USBD_GET_EP_STALL(ep) (((__PC() & NS_OFFSET) == NS_OFFSET)? (*((__IO uint32_t *) ((uint32_t)&USBD_NS->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk):(*((__IO uint32_t *) ((uint32_t)&USBD->EP[0].CFGP + (uint32_t)((ep) << 4))) & USBD_CFGP_SSTALL_Msk))
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size);
__STATIC_INLINE void USBD_SetStall(uint8_t epnum);
__STATIC_INLINE void USBD_ClearStall(uint8_t epnum);
__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum);
/** /**
* @brief To support byte access between USB SRAM and system SRAM * @brief To support byte access between USB SRAM and system SRAM
* *
@ -553,12 +554,10 @@ __STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum);
__STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size) __STATIC_INLINE void USBD_MemCopy(uint8_t dest[], uint8_t src[], uint32_t size)
{ {
uint32_t volatile i = 0UL; uint32_t volatile i = 0UL;
uint8_t u8SrcTmp;
while(size--) while(size--)
{ {
u8SrcTmp = src[i]; dest[i] = src[i];
dest[i] = u8SrcTmp;
i++; i++;
} }
} }
@ -660,7 +659,7 @@ __STATIC_INLINE void USBD_ClearStall(uint8_t epnum)
*/ */
__STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum) __STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)
{ {
uint32_t u32CfgAddr; uint32_t u32CfgAddr = 0;
uint32_t u32Cfg; uint32_t u32Cfg;
uint32_t i; uint32_t i;
@ -689,7 +688,8 @@ __STATIC_INLINE uint32_t USBD_GetStall(uint8_t epnum)
return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL); return ((*((__IO uint32_t *)(u32CfgAddr))) & USBD_CFGP_SSTALL);
} }
extern volatile uint8_t g_usbd_RemoteWakeupEn; extern volatile uint8_t g_USBD_u8RemoteWakeupEn;
extern uint8_t g_USBD_au8SetupPacket[8];
typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */ typedef void (*VENDOR_REQ)(void); /*!< Functional pointer type definition for Vendor class */
@ -697,6 +697,12 @@ typedef void (*CLASS_REQ)(void); /*!< Functional pointer type declara
typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */ typedef void (*SET_INTERFACE_REQ)(uint32_t u32AltInterface); /*!< Functional pointer type declaration for USB set interface request callback handler */
typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */ typedef void (*SET_CONFIG_CB)(void); /*!< Functional pointer type declaration for USB set configuration request callback handler */
extern const S_USBD_INFO_T *g_USBD_sInfo; /*!< A pointer for USB information structure */
extern VENDOR_REQ g_USBD_pfnVendorRequest; /*!< USB Vendor Request Functional Pointer */
extern CLASS_REQ g_USBD_pfnClassRequest; /*!< USB Class Request Functional Pointer */
extern SET_INTERFACE_REQ g_USBD_pfnSetInterface; /*!< USB Set Interface Functional Pointer */
extern SET_CONFIG_CB g_USBD_pfnSetConfigCallback; /*!< USB Set configuration callback function pointer */
extern uint32_t g_USBD_u32EpStallLock; /*!< Bit map flag to lock specified EP when SET_FEATURE */
/*--------------------------------------------------------------------*/ /*--------------------------------------------------------------------*/
void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface); void USBD_Open(const S_USBD_INFO_T *param, CLASS_REQ pfnClassReq, SET_INTERFACE_REQ pfnSetInterface);
@ -725,4 +731,4 @@ void USBD_LockEpStall(uint32_t u32EpBitmap);
#endif /* __USBD_H__ */ #endif /* __USBD_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2018 Nuvoton Technology Corp. ***/

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_usci_i2c.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_usci_i2c.h
View File

6
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_usci_spi.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_usci_spi.h
View File

@ -137,8 +137,8 @@ extern "C"
*/ */
#define USPI_SET_SS_HIGH(uspi) \ #define USPI_SET_SS_HIGH(uspi) \
do{ \ do{ \
(uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ (uspi)->LINECTL &= ~USPI_LINECTL_CTLOINV_Msk; \
(uspi)->PROTCTL = ((uspi)->PROTCTL & ~(USPI_PROTCTL_AUTOSS_Msk | USPI_PROTCTL_SS_Msk)); \ (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
}while(0) }while(0)
/** /**
@ -150,7 +150,7 @@ extern "C"
*/ */
#define USPI_SET_SS_LOW(uspi) \ #define USPI_SET_SS_LOW(uspi) \
do{ \ do{ \
(uspi)->LINECTL |= (USPI_LINECTL_CTLOINV_Msk); \ (uspi)->LINECTL |= USPI_LINECTL_CTLOINV_Msk; \
(uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \ (uspi)->PROTCTL = (((uspi)->PROTCTL & ~USPI_PROTCTL_AUTOSS_Msk) | USPI_PROTCTL_SS_Msk); \
}while(0) }while(0)

3
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_usci_uart.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_usci_uart.h
View File

@ -82,7 +82,7 @@ extern "C"
/** /**
* @brief Read USCI_UART data * @brief Read USCI_UART data
* *
* @param[in] usci The pointer of the specified USCI_UART module * @param[in] uuart The pointer of the specified USCI_UART module
* *
* @return The oldest data byte in RX buffer. * @return The oldest data byte in RX buffer.
* *
@ -320,7 +320,6 @@ extern "C"
* @param[in] u32IntTypeFlag Interrupt Type Flag, should be * @param[in] u32IntTypeFlag Interrupt Type Flag, should be
* - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator * - \ref UUART_PROTSTS_ABERRSTS_Msk : Auto-baud Rate Error Interrupt Indicator
* - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag * - \ref UUART_PROTSTS_ABRDETIF_Msk : Auto-baud Rate Detected Interrupt Flag
* - \ref UUART_PROTSTS_BRKDETIF_Msk : LIN Break Detected Interrupt Flag
* - \ref UUART_PROTSTS_BREAK_Msk : Break Flag * - \ref UUART_PROTSTS_BREAK_Msk : Break Flag
* - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag * - \ref UUART_PROTSTS_FRMERR_Msk : Framing Error Flag
* - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag * - \ref UUART_PROTSTS_PARITYERR_Msk : Parity Error Flag

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_wdt.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_wdt.h
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0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_wwdt.h → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/inc/m2351_wwdt.h
View File

397
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_spi5.c
View File

@ -1,397 +0,0 @@
/**************************************************************************//**
* @file spi5.c
* @version V3.00
* @brief M2351 series SPI5 driver source file
*
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#include "NuMicro.h"
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SPI5_Driver SPI5 Driver
@{
*/
/** @addtogroup SPI5_EXPORTED_FUNCTIONS SPI5 Exported Functions
@{
*/
/**
* @brief This function make SPI5 module be ready to transfer.
* By default, the SPI5 transfer sequence is MSB first and
* the automatic slave select function is disabled. In
* Slave mode, the u32BusClock must be NULL and the SPI5 clock
* divider setting will be 0.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32MasterSlave decides the SPI5 module is operating in master mode or in slave mode. Valid values are:
* - \ref SPI5_MASTER
* - \ref SPI5_SLAVE
* @param[in] u32SPI5Mode decides the transfer timing. Valid values are:
* - \ref SPI5_MODE_0
* - \ref SPI5_MODE_1
* - \ref SPI5_MODE_2
* - \ref SPI5_MODE_3
* @param[in] u32DataWidth decides the data width of a SPI5 transaction.
* @param[in] u32BusClock is the expected frequency of SPI5 bus clock in Hz.
* @return Actual frequency of SPI5 peripheral clock.
*/
uint32_t SPI5_Open(SPI5_T *spi,
uint32_t u32MasterSlave,
uint32_t u32SPI5Mode,
uint32_t u32DataWidth,
uint32_t u32BusClock)
{
if(u32DataWidth == 32UL)
{
u32DataWidth = 0UL;
}
spi->CTL = u32MasterSlave | (u32DataWidth << SPI5_CTL_DWIDTH_Pos) | (u32SPI5Mode);
return (SPI5_SetBusClock(spi, u32BusClock));
}
/**
* @brief Reset SPI5 module.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_Close(SPI5_T *spi)
{
if(!(__PC() & (1UL << 28UL)))
{
if(spi == SPI5)
{
/* Reset SPI5 */
SYS->IPRST2 |= SYS_IPRST2_SPI5RST_Msk;
SYS->IPRST2 &= ~SYS_IPRST2_SPI5RST_Msk;
}
}
}
/**
* @brief Clear RX FIFO buffer.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_ClearRxFIFO(SPI5_T *spi)
{
spi->FIFOCTL |= SPI5_FIFOCTL_RXFBCLR_Msk;
}
/**
* @brief Clear TX FIFO buffer.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_ClearTxFIFO(SPI5_T *spi)
{
spi->FIFOCTL |= SPI5_FIFOCTL_TXFBCLR_Msk;
}
/**
* @brief Disable the automatic slave select function.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_DisableAutoSS(SPI5_T *spi)
{
spi->SSCTL &= ~SPI5_SSCTL_AUTOSS_Msk;
}
/**
* @brief Enable the automatic slave select function. Only available in Master mode.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32SSPinMask specifies slave select pins. (SPI5_SS)
* @param[in] u32ActiveLevel specifies the active level of slave select signal. Valid values are:
* - \ref SPI5_SS0_ACTIVE_HIGH
* - \ref SPI5_SS0_ACTIVE_LOW
* @return none
*/
void SPI5_EnableAutoSS(SPI5_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel)
{
spi->SSCTL = (spi->SSCTL & ~(SPI5_SSCTL_SSACTPOL_Msk | SPI5_SSCTL_SS_Msk)) | (u32SSPinMask | u32ActiveLevel) | SPI5_SSCTL_AUTOSS_Msk;
}
/**
* @brief Set the SPI5 bus clock. Only available in Master mode.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32BusClock is the expected frequency of SPI5 bus clock.
* @return Actual frequency of SPI5 peripheral clock.
* @note If u32BusClock >= system clock frequency for Secure, SPI peripheral clock source will be set to APB clock and DIVIDER will be set to 0.
* @note If u32BusClock >= system clock frequency for Non-Secure, this function does not do anything to avoid the situation that the frequency of
* SPI bus clock cannot be faster than the system clock rate. User should set up carefully.
*/
uint32_t SPI5_SetBusClock(SPI5_T *spi, uint32_t u32BusClock)
{
uint32_t u32ClkSrc, u32HCLKFreq;
uint32_t u32Div, u32RetValue;
/* Get system clock frequency */
u32HCLKFreq = CLK_GetHCLKFreq();
if(u32BusClock >= u32HCLKFreq)
{
if(!(__PC() & (1UL << 28UL)))
{
/* Select PCLK as the clock source of SPI5 */
if(spi == SPI5)
{
CLK->CLKSEL2 = (CLK->CLKSEL2 & (~CLK_CLKSEL2_SPI5SEL_Msk)) | CLK_CLKSEL2_SPI5SEL_PCLK1;
}
}
}
/* Check clock source of SPI5 */
if((spi == SPI5) || (spi == SPI5_NS))
{
if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PCLK1)
{
u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
}
else
{
u32ClkSrc = __HIRC; /* Clock source is HIRC */
}
}
if(u32BusClock >= u32HCLKFreq)
{
/* Set DIVIDER = 0 */
spi->CLKDIV = 0UL;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if(u32BusClock >= u32ClkSrc)
{
/* Set DIVIDER = 0 */
spi->CLKDIV = 0UL;
/* Return master peripheral clock rate */
u32RetValue = u32ClkSrc;
}
else if(u32BusClock == 0UL)
{
/* Set DIVIDER to the maximum value 0xFF. f_spi = f_spi_clk_src / (DIVIDER + 1) */
spi->CLKDIV |= SPI5_CLKDIV_DIVIDER_Msk;
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (0xFFUL + 1UL));
}
else
{
u32Div = (((u32ClkSrc * 10UL) / u32BusClock + 5UL) / 10UL) - 1UL; /* Round to the nearest integer */
if(u32Div > 0xFFUL)
{
u32Div = 0xFFUL;
spi->CLKDIV |= SPI5_CLKDIV_DIVIDER_Msk;
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (0xFFUL + 1UL));
}
else
{
spi->CLKDIV = (spi->CLKDIV & (~SPI5_CLKDIV_DIVIDER_Msk)) | (u32Div << SPI5_CLKDIV_DIVIDER_Pos);
/* Return master peripheral clock rate */
u32RetValue = (u32ClkSrc / (u32Div + 1UL));
}
}
return u32RetValue;
}
/**
* @brief Enable FIFO mode with user-specified TX FIFO threshold and RX FIFO threshold configurations.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32TxThreshold decides the TX FIFO threshold.
* @param[in] u32RxThreshold decides the RX FIFO threshold.
* @return none
*/
void SPI5_EnableFIFO(SPI5_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold)
{
spi->FIFOCTL = ((spi->FIFOCTL & ~(SPI5_FIFOCTL_TXTH_Msk | SPI5_FIFOCTL_RXTH_Msk)) |
(u32TxThreshold << SPI5_FIFOCTL_TXTH_Pos) |
(u32RxThreshold << SPI5_FIFOCTL_RXTH_Pos));
spi->CTL |= SPI5_CTL_FIFOM_Msk;
}
/**
* @brief Disable FIFO mode.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_DisableFIFO(SPI5_T *spi)
{
spi->CTL &= ~SPI5_CTL_FIFOM_Msk;
}
/**
* @brief Get the actual frequency of SPI5 bus clock. Only available in Master mode.
* @param[in] spi is the base address of SPI5 module.
* @return Actual SPI5 bus clock frequency.
*/
uint32_t SPI5_GetBusClock(SPI5_T *spi)
{
uint32_t u32Div;
uint32_t u32ClkSrc;
/* Get DIVIDER setting */
u32Div = (spi->CLKDIV & SPI5_CLKDIV_DIVIDER_Msk) >> SPI5_CLKDIV_DIVIDER_Pos;
/* Check clock source of SPI5 */
if((spi == SPI5) || (spi == SPI5_NS))
{
if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_HXT)
{
u32ClkSrc = __HXT; /* Clock source is HXT */
}
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PLL)
{
u32ClkSrc = CLK_GetPLLClockFreq(); /* Clock source is PLL */
}
else if((CLK_GetModuleClockSource(SPI5_MODULE) << CLK_CLKSEL2_SPI5SEL_Pos) == CLK_CLKSEL2_SPI5SEL_PCLK1)
{
u32ClkSrc = CLK_GetPCLK1Freq(); /* Clock source is PCLK1 */
}
else
{
u32ClkSrc = __HIRC; /* Clock source is HIRC */
}
}
/* Return SPI bus clock rate */
return (u32ClkSrc / (u32Div + 1UL));
}
/**
* @brief Enable FIFO related interrupts specified by u32Mask parameter.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32Mask is the combination of all related interrupt enable bits.
* Each bit corresponds to a interrupt bit.
* This parameter decides which interrupts will be enabled. Valid values are:
* - \ref SPI5_IE_MASK
* - \ref SPI5_SSTAIEN_MASK
* - \ref SPI5_FIFO_TXTHIEN_MASK
* - \ref SPI5_FIFO_RXTHIEN_MASK
* - \ref SPI5_FIFO_RXOVIEN_MASK
* - \ref SPI5_FIFO_TIMEOUIEN_MASK
* @return none
*/
void SPI5_EnableInt(SPI5_T *spi, uint32_t u32Mask)
{
if((u32Mask & SPI5_IE_MASK) == SPI5_IE_MASK)
{
spi->CTL |= SPI5_CTL_UNITIEN_Msk;
}
if((u32Mask & SPI5_SSTAIEN_MASK) == SPI5_SSTAIEN_MASK)
{
spi->SSCTL |= SPI5_SSCTL_SSTAIEN_Msk;
}
if((u32Mask & SPI5_FIFO_TXTHIEN_MASK) == SPI5_FIFO_TXTHIEN_MASK)
{
spi->FIFOCTL |= SPI5_FIFOCTL_TXTHIEN_Msk;
}
if((u32Mask & SPI5_FIFO_RXTHIEN_MASK) == SPI5_FIFO_RXTHIEN_MASK)
{
spi->FIFOCTL |= SPI5_FIFOCTL_RXTHIEN_Msk;
}
if((u32Mask & SPI5_FIFO_RXOVIEN_MASK) == SPI5_FIFO_RXOVIEN_MASK)
{
spi->FIFOCTL |= SPI5_FIFOCTL_RXOVIEN_Msk;
}
if((u32Mask & SPI5_FIFO_TIMEOUIEN_MASK) == SPI5_FIFO_TIMEOUIEN_MASK)
{
spi->FIFOCTL |= SPI5_FIFOCTL_RXTOIEN_Msk;
}
}
/**
* @brief Disable FIFO related interrupts specified by u32Mask parameter.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32Mask is the combination of all related interrupt enable bits.
* Each bit corresponds to a interrupt bit.
* This parameter decides which interrupts will be enabled. Valid values are:
* - \ref SPI5_IE_MASK
* - \ref SPI5_SSTAIEN_MASK
* - \ref SPI5_FIFO_TXTHIEN_MASK
* - \ref SPI5_FIFO_RXTHIEN_MASK
* - \ref SPI5_FIFO_RXOVIEN_MASK
* - \ref SPI5_FIFO_TIMEOUIEN_MASK
* @return none
*/
void SPI5_DisableInt(SPI5_T *spi, uint32_t u32Mask)
{
if((u32Mask & SPI5_IE_MASK) == SPI5_IE_MASK)
{
spi->CTL &= ~SPI5_CTL_UNITIEN_Msk;
}
if((u32Mask & SPI5_SSTAIEN_MASK) == SPI5_SSTAIEN_MASK)
{
spi->SSCTL &= ~SPI5_SSCTL_SSTAIEN_Msk;
}
if((u32Mask & SPI5_FIFO_TXTHIEN_MASK) == SPI5_FIFO_TXTHIEN_MASK)
{
spi->FIFOCTL &= ~SPI5_FIFOCTL_TXTHIEN_Msk;
}
if((u32Mask & SPI5_FIFO_RXTHIEN_MASK) == SPI5_FIFO_RXTHIEN_MASK)
{
spi->FIFOCTL &= ~SPI5_FIFOCTL_RXTHIEN_Msk;
}
if((u32Mask & SPI5_FIFO_RXOVIEN_MASK) == SPI5_FIFO_RXOVIEN_MASK)
{
spi->FIFOCTL &= ~SPI5_FIFOCTL_RXOVIEN_Msk;
}
if((u32Mask & SPI5_FIFO_TIMEOUIEN_MASK) == SPI5_FIFO_TIMEOUIEN_MASK)
{
spi->FIFOCTL &= ~SPI5_FIFOCTL_RXTOIEN_Msk;
}
}
/**
* @brief Enable wake-up function.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_EnableWakeup(SPI5_T *spi)
{
spi->CTL |= SPI5_CTL_WKCLKEN_Msk;
}
/**
* @brief Disable wake-up function.
* @param[in] spi is the base address of SPI5 module.
* @return none
*/
void SPI5_DisableWakeup(SPI5_T *spi)
{
spi->CTL &= ~SPI5_CTL_WKCLKEN_Msk;
}
/*@}*/ /* end of group SPI5_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SPI5_Driver */
/*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

309
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_spi5.h
View File

@ -1,309 +0,0 @@
/****************************************************************************//**
* @file spi5.h
* @version V3.00
* @brief M2351 series SPI5 driver header file
*
* @copyright (C) 2016 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/
#ifndef __SPI5_H__
#define __SPI5_H__
#ifdef __cplusplus
extern "C"
{
#endif
/** @addtogroup Standard_Driver Standard Driver
@{
*/
/** @addtogroup SPI5_Driver SPI5 Driver
@{
*/
/** @addtogroup SPI5_EXPORTED_CONSTANTS SPI5 Exported Constants
@{
*/
#define SPI5_MODE_0 (SPI5_CTL_TXNEG_Msk) /*!< CLKP=0; RX_NEG=0; TX_NEG=1 */
#define SPI5_MODE_1 (SPI5_CTL_RXNEG_Msk) /*!< CLKP=0; RX_NEG=1; TX_NEG=0 */
#define SPI5_MODE_2 (SPI5_CTL_CLKPOL_Msk | SPI5_CTL_RXNEG_Msk) /*!< CLKP=1; RX_NEG=1; TX_NEG=0 */
#define SPI5_MODE_3 (SPI5_CTL_CLKPOL_Msk | SPI5_CTL_TXNEG_Msk) /*!< CLKP=1; RX_NEG=0; TX_NEG=1 */
#define SPI5_SLAVE (SPI5_CTL_SLAVE_Msk) /*!< Set as slave */
#define SPI5_MASTER (0x0UL) /*!< Set as master */
#define SPI5_SS (0x1UL) /*!< Set SS */
#define SPI5_SS_ACTIVE_HIGH (SPI5_SSCTL_SSACTPOL_Msk) /*!< SS active high */
#define SPI5_SS_ACTIVE_LOW (0x0UL) /*!< SS active low */
#define SPI5_IE_MASK (0x01UL) /*!< Interrupt enable mask */
#define SPI5_SSTAIEN_MASK (0x04UL) /*!< Slave 3-Wire mode start interrupt enable mask */
#define SPI5_FIFO_TXTHIEN_MASK (0x08UL) /*!< FIFO TX interrupt mask */
#define SPI5_FIFO_RXTHIEN_MASK (0x10UL) /*!< FIFO RX interrupt mask */
#define SPI5_FIFO_RXOVIEN_MASK (0x20UL) /*!< FIFO RX overrun interrupt mask */
#define SPI5_FIFO_TIMEOUIEN_MASK (0x40UL) /*!< FIFO timeout interrupt mask */
/*@}*/ /* end of group SPI5_EXPORTED_CONSTANTS */
/** @addtogroup SPI5_EXPORTED_FUNCTIONS SPI5 Exported Functions
@{
*/
/**
* @brief Abort the current transfer in slave 3-wire mode.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_ABORT_3WIRE_TRANSFER(spi) ( (spi)->SSCTL |= SPI5_SSCTL_SLVABORT_Msk )
/**
* @brief Clear the slave 3-wire mode start interrupt flag.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_CLR_3WIRE_START_INT_FLAG(spi) ( (spi)->STATUS = SPI5_STATUS_SLVSTAIF_Msk )
/**
* @brief Clear the unit transfer interrupt flag.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_CLR_UNIT_TRANS_INT_FLAG(spi) ( (spi)->STATUS = SPI5_STATUS_UNITIF_Msk )
/**
* @brief Disable slave 3-wire mode.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_DISABLE_3WIRE_MODE(spi) ( (spi)->SSCTL &= ~SPI5_SSCTL_SLV3WIRE_Msk )
/**
* @brief Enable slave 3-wire mode.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_ENABLE_3WIRE_MODE(spi) ( (spi)->SSCTL |= SPI5_SSCTL_SLV3WIRE_Msk )
/**
* @brief Get the count of available data in RX FIFO.
* @param[in] spi is the base address of SPI5 module.
* @return The count of available data in RX FIFO.
* \hideinitializer
*/
#define SPI5_GET_RX_FIFO_COUNT(spi) ( (((spi)->STATUS & SPI5_STATUS_RXCNT_Msk) >> SPI5_STATUS_RXCNT_Pos) & 0xF )
/**
* @brief Get the RX FIFO empty flag.
* @param[in] spi is the base address of SPI5 module.
* @return RX FIFO flag
* @retval 0 RX FIFO is not empty
* @retval 1 RX FIFO is empty
* \hideinitializer
*/
#define SPI5_GET_RX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI5_STATUS_RXEMPTY_Msk) == SPI5_STATUS_RXEMPTY_Msk ? 1:0 )
/**
* @brief Get the TX FIFO empty flag.
* @param[in] spi is the base address of SPI5 module.
* @return TX FIFO flag
* @retval 0 TX FIFO is not empty
* @retval 1 TX FIFO is empty
* \hideinitializer
*/
#define SPI5_GET_TX_FIFO_EMPTY_FLAG(spi) ( ((spi)->STATUS & SPI5_STATUS_TXEMPTY_Msk) == SPI5_STATUS_TXEMPTY_Msk ? 1:0 )
/**
* @brief Get the TX FIFO full flag.
* @param[in] spi is the base address of SPI5 module.
* @return TX FIFO flag
* @retval 0 TX FIFO is not full
* @retval 1 TX FIFO is full
* \hideinitializer
*/
#define SPI5_GET_TX_FIFO_FULL_FLAG(spi) ( ((spi)->STATUS & SPI5_STATUS_TXFULL_Msk) == SPI5_STATUS_TXFULL_Msk ? 1:0 )
/**
* @brief Get the datum read from RX FIFO.
* @param[in] spi is the base address of SPI5 module.
* @return Data in RX register.
* \hideinitializer
*/
#define SPI5_READ_RX(spi) ( (spi)->RX )
/**
* @brief Write datum to TX register.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32TxData is the datum which user attempt to transfer through SPI5 bus.
* @return none
* \hideinitializer
*/
#define SPI5_WRITE_TX(spi, u32TxData) ( (spi)->TX = (u32TxData) )
/**
* @brief Set SPI5_SS pin to high state.
* @param[in] spi The pointer of the specified SPI5 module.
* @return None.
* @details Disable automatic slave selection function and set SPI5_SS pin to high state. Only available in Master mode.
* \hideinitializer
*/
#define SPI5_SET_SS_HIGH(spi) ( (spi)->SSCTL = ((spi)->SSCTL & ~(SPI5_SSCTL_AUTOSS_Msk | SPI5_SSCTL_SSACTPOL_Msk | SPI5_SS)) )
/**
* @brief Set SPI5_SS pin to low state.
* @param[in] spi The pointer of the specified SPI5 module.
* @return None.
* @details Disable automatic slave selection function and set SPI5_SS pin to low state. Only available in Master mode.
* \hideinitializer
*/
#define SPI5_SET_SS_LOW(spi) ( (spi)->SSCTL = ((spi)->SSCTL & ~(SPI5_SSCTL_AUTOSS_Msk | SPI5_SSCTL_SSACTPOL_Msk | SPI5_SS)) | SPI5_SS )
/**
* @brief Set SPI5_SS pin to high or low state.
* @param[in] spi The pointer of the specified SPI5 module.
* @param[in] ss 0 = Set SPI5_SS to low. 1 = Set SPI5_SS to high.
* @return None.
* @details Disable automatic slave selection function and set SPI5_SS pin to specified high/low state.
* Only available in Master mode.
*/
#define SPI5_SET_SS_LEVEL(spi, ss) ( (spi)->SSCTL = ((spi)->SSCTL & ~(SPI5_SSCTL_AUTOSS_Msk | SPI5_SSCTL_SSACTPOL_Msk | SPI5_SSCTL_SS_Msk)) | ((ss)^1) )
/**
* @brief Enable byte reorder function.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_ENABLE_BYTE_REORDER(spi) ( (spi)->CTL |= SPI5_CTL_REORDER_Msk )
/**
* @brief Disable byte reorder function.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_DISABLE_BYTE_REORDER(spi) ( (spi)->CTL &= ~SPI5_CTL_REORDER_Msk )
/**
* @brief Set the length of suspend interval.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32SuspCycle decides the length of suspend interval.
* @return none
* \hideinitializer
*/
#define SPI5_SET_SUSPEND_CYCLE(spi, u32SuspCycle) ( (spi)->CTL = ((spi)->CTL & ~SPI5_CTL_SUSPITV_Msk) | ((u32SuspCycle) << SPI5_CTL_SUSPITV_Pos) )
/**
* @brief Set the SPI5 transfer sequence with LSB first.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_SET_LSB_FIRST(spi) ( (spi)->CTL |= SPI5_CTL_LSB_Msk )
/**
* @brief Set the SPI5 transfer sequence with MSB first.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_SET_MSB_FIRST(spi) ( (spi)->CTL &= ~SPI5_CTL_LSB_Msk )
/* Declare these inline functions here to avoid MISRA C 2004 rule 8.1 error */
__STATIC_INLINE void SPI5_SET_DATA_WIDTH(SPI5_T *spi, uint32_t u32Width);
/**
* @brief Set the data width of a SPI5 transaction.
* @param[in] spi is the base address of SPI5 module.
* @param[in] u32Width is the data width (from 8-32 bits).
* @return none
* \hideinitializer
*/
__STATIC_INLINE void SPI5_SET_DATA_WIDTH(SPI5_T *spi, uint32_t u32Width)
{
if(u32Width == 32UL)
{
u32Width = 0UL;
}
(spi)->CTL = ((spi)->CTL & ~SPI5_CTL_DWIDTH_Msk) | ((u32Width) << SPI5_CTL_DWIDTH_Pos);
}
/**
* @brief Get the SPI5 busy state.
* @param[in] spi is the base address of SPI5 module.
* @return SPI5 busy status
* @retval 0 SPI5 module is not busy
* @retval 1 SPI5 module is busy
* \hideinitializer
*/
#define SPI5_IS_BUSY(spi) ( ((spi)->CTL & SPI5_CTL_GOBUSY_Msk) == SPI5_CTL_GOBUSY_Msk ? 1:0 )
/**
* @brief Set the GOBUSY bit to trigger SPI5 transfer.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_TRIGGER(spi) ( (spi)->CTL |= SPI5_CTL_GOBUSY_Msk )
/**
* @brief Trigger RX PDMA transfer.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_TRIGGER_RX_PDMA(spi) ( (spi)->PDMACTL |= SPI5_PDMACTL_RXPDMAEN_Msk )
/**
* @brief Trigger TX PDMA transfer.
* @param[in] spi is the base address of SPI5 module.
* @return none
* \hideinitializer
*/
#define SPI5_TRIGGER_TX_PDMA(spi) ( (spi)->PDMACTL |= SPI5_PDMACTL_TXPDMAEN_Msk )
/**
* @brief Get the status register value.
* @param[in] spi is the base address of SPI5 module.
* @return status value.
* \hideinitializer
*/
#define SPI5_GET_STATUS(spi) ( (spi)->STATUS )
uint32_t SPI5_Open(SPI5_T *spi, uint32_t u32MasterSlave, uint32_t u32SPI5Mode, uint32_t u32DataWidth, uint32_t u32BusClock);
void SPI5_Close(SPI5_T *spi);
void SPI5_ClearRxFIFO(SPI5_T *spi);
void SPI5_ClearTxFIFO(SPI5_T *spi);
void SPI5_DisableAutoSS(SPI5_T *spi);
void SPI5_EnableAutoSS(SPI5_T *spi, uint32_t u32SSPinMask, uint32_t u32ActiveLevel);
uint32_t SPI5_SetBusClock(SPI5_T *spi, uint32_t u32BusClock);
void SPI5_EnableFIFO(SPI5_T *spi, uint32_t u32TxThreshold, uint32_t u32RxThreshold);
void SPI5_DisableFIFO(SPI5_T *spi);
uint32_t SPI5_GetBusClock(SPI5_T *spi);
void SPI5_EnableInt(SPI5_T *spi, uint32_t u32Mask);
void SPI5_DisableInt(SPI5_T *spi, uint32_t u32Mask);
void SPI5_EnableWakeup(SPI5_T *spi);
void SPI5_DisableWakeup(SPI5_T *spi);
/*@}*/ /* end of group SPI5_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group SPI5_Driver */
/*@}*/ /* end of group Standard_Driver */
#ifdef __cplusplus
}
#endif
#endif /* __SPI5_H__ */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/

4
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_acmp.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_acmp.c
View File

@ -33,8 +33,8 @@ extern "C"
/** /**
* @brief Configure the specified ACMP module * @brief Configure the specified ACMP module
* *
* @param[in] Acmp The pointer of the specified ACMP module * @param[in] acmp The pointer of the specified ACMP module
* @param[in] u32ChNum Comparator number. * @param[in] u32ChNum Comparator number.
* @param[in] u32NegSrc Comparator negative input selection. Including: * @param[in] u32NegSrc Comparator negative input selection. Including:
* - \ref ACMP_CTL_NEGSEL_PIN * - \ref ACMP_CTL_NEGSEL_PIN
* - \ref ACMP_CTL_NEGSEL_CRV * - \ref ACMP_CTL_NEGSEL_CRV

46
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_bpwm.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_bpwm.c
View File

@ -4,7 +4,7 @@
* @brief M2351 series BPWM driver source file * @brief M2351 series BPWM driver source file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#include "NuMicro.h" #include "NuMicro.h"
@ -35,8 +35,8 @@
uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
{ {
uint32_t u32PWMClockSrc; uint32_t u32PWMClockSrc;
uint32_t u32NearestUnitTimeNsec; uint32_t u32NearestUnitTimeNsec = 0U;
uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
uint8_t u8BreakLoop = 0U; uint8_t u8BreakLoop = 0U;
/* clock source is from PCLK */ /* clock source is from PCLK */
@ -50,17 +50,17 @@ uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_
} }
u32PWMClockSrc /= 1000UL; u32PWMClockSrc /= 1000UL;
for(u16Prescale = 1U; u16Prescale <= 0x1000UL; u16Prescale++) for(u32Prescale = 1U; u32Prescale <= 0x1000UL; u32Prescale++)
{ {
u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc; u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc;
if(u32NearestUnitTimeNsec < u32UnitTimeNsec) if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
{ {
if(u16Prescale == 0x1000U) if(u32Prescale == 0x1000U)
{ {
/* limit to the maximum unit time(nano second) */ /* limit to the maximum unit time(nano second) */
u8BreakLoop = 1U; u8BreakLoop = 1U;
} }
if(!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
{ {
u8BreakLoop = 1U; u8BreakLoop = 1U;
} }
@ -76,14 +76,14 @@ uint32_t BPWM_ConfigCaptureChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_
} }
/* convert to real register value */ /* convert to real register value */
u16Prescale = u16Prescale - 1U; u32Prescale = u32Prescale - 1U;
/* all channels share a prescaler */ /* all channels share a prescaler */
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale); BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
/* set BPWM to down count type(edge aligned) */ /* set BPWM to down count type(edge aligned) */
(bpwm)->CTL1 = (1UL); (bpwm)->CTL1 = (1UL);
BPWM_SET_CNR(bpwm, u32ChannelNum, u16CNR); BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
return (u32NearestUnitTimeNsec); return (u32NearestUnitTimeNsec);
} }
@ -106,7 +106,7 @@ uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t
{ {
uint32_t u32PWMClockSrc; uint32_t u32PWMClockSrc;
uint32_t i; uint32_t i;
uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
/* clock source is from PCLK */ /* clock source is from PCLK */
if(((uint32_t)bpwm == BPWM0_BASE) || ((uint32_t)bpwm == BPWM0_BASE + NS_OFFSET)) if(((uint32_t)bpwm == BPWM0_BASE) || ((uint32_t)bpwm == BPWM0_BASE + NS_OFFSET))
@ -118,29 +118,29 @@ uint32_t BPWM_ConfigOutputChannel(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t
u32PWMClockSrc = CLK_GetPCLK1Freq(); u32PWMClockSrc = CLK_GetPCLK1Freq();
} }
for(u16Prescale = 1U; u16Prescale < 0xFFFU; u16Prescale++)/* prescale could be 0~0xFFF */ for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */
{ {
i = (u32PWMClockSrc / u32Frequency) / u16Prescale; i = (u32PWMClockSrc / u32Frequency) / u32Prescale;
/* If target value is larger than CNR, need to use a larger prescaler */ /* If target value is larger than CNR, need to use a larger prescaler */
if(i <= (0x10000U)) if(i <= (0x10000U))
{ {
u16CNR = (uint16_t)i; u32CNR = i;
break; break;
} }
} }
/* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */
i = u32PWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR); i = u32PWMClockSrc / (u32Prescale * u32CNR);
/* convert to real register value */ /* convert to real register value */
u16Prescale = u16Prescale - 1U; u32Prescale = u32Prescale - 1U;
/* all channels share a prescaler */ /* all channels share a prescaler */
BPWM_SET_PRESCALER(bpwm, u32ChannelNum, (uint32_t)u16Prescale); BPWM_SET_PRESCALER(bpwm, u32ChannelNum, u32Prescale);
/* set BPWM to up counter type(edge aligned) */ /* set BPWM to up counter type(edge aligned) */
(bpwm)->CTL1 = BPWM_UP_COUNTER; (bpwm)->CTL1 = BPWM_UP_COUNTER;
u16CNR = u16CNR - 1U; u32CNR = u32CNR - 1U;
BPWM_SET_CNR(bpwm, u32ChannelNum, (uint32_t)u16CNR); BPWM_SET_CNR(bpwm, u32ChannelNum, u32CNR);
BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * ((uint32_t)u16CNR + 1UL) / 100UL); BPWM_SET_CMR(bpwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
(bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ (bpwm)->WGCTL0 = ((bpwm)->WGCTL0 & ~((BPWM_WGCTL0_PRDPCTL0_Msk | BPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
@ -439,7 +439,7 @@ void BPWM_EnableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum, uint32_t u32IntDut
*/ */
void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum) void BPWM_DisableDutyInt(BPWM_T *bpwm, uint32_t u32ChannelNum)
{ {
(bpwm)->INTEN &= ~((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum); (bpwm)->INTEN &= ~(uint32_t)((BPWM_DUTY_INT_DOWN_COUNT_MATCH_CMP | BPWM_DUTY_INT_UP_COUNT_MATCH_CMP) << u32ChannelNum);
} }
/** /**
@ -691,4 +691,4 @@ void BPWM_ClearWrapAroundFlag(BPWM_T *bpwm, uint32_t u32ChannelNum)
/*@}*/ /* end of group Standard_Driver */ /*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

6
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_can.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_can.c
View File

@ -27,9 +27,9 @@
/** @cond HIDDEN_SYMBOLS */ /** @cond HIDDEN_SYMBOLS */
#if defined(CAN1) #if defined(CAN1)
static uint8_t gu8LockCanIf[2][2] = {0U}; /* The chip has two CANs. */ static uint8_t gu8LockCanIf[2][2] = {{0U}}; /* The chip has two CANs. */
#elif defined(CAN0) || defined(CAN) #elif defined(CAN0) || defined(CAN)
static uint8_t gu8LockCanIf[1][2] = {0U}; /* The chip only has one CAN. */ static uint8_t gu8LockCanIf[1][2] = {{0U}}; /* The chip only has one CAN. */
#endif #endif
#define RETRY_COUNTS (0x10000000UL) #define RETRY_COUNTS (0x10000000UL)
@ -121,7 +121,7 @@ static uint32_t LockIF(CAN_T *tCAN)
static uint32_t LockIF_TL(CAN_T *tCAN) static uint32_t LockIF_TL(CAN_T *tCAN)
{ {
uint32_t u32Count; uint32_t u32Count;
uint32_t u32FreeIfNo; uint32_t u32FreeIfNo = 0U;
for(u32Count = 0U; u32Count < (uint32_t)RETRY_COUNTS; u32Count++) for(u32Count = 0U; u32Count < (uint32_t)RETRY_COUNTS; u32Count++)
{ {

136
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_clk.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_clk.c
View File

@ -112,7 +112,6 @@ void CLK_Idle(void)
* @return External high frequency crystal frequency * @return External high frequency crystal frequency
* @details This function get external high frequency crystal frequency. The frequency unit is Hz. * @details This function get external high frequency crystal frequency. The frequency unit is Hz.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetHXTFreq(void) uint32_t CLK_GetHXTFreq(void)
@ -140,7 +139,6 @@ uint32_t CLK_GetHXTFreq(void)
* @details This function get external low frequency crystal frequency. The frequency unit is Hz. * @details This function get external low frequency crystal frequency. The frequency unit is Hz.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetLXTFreq(void) uint32_t CLK_GetLXTFreq(void)
@ -160,6 +158,7 @@ uint32_t CLK_GetLXTFreq(void)
return u32Freq; return u32Freq;
} }
#endif #endif
/** /**
* @brief Get HCLK frequency * @brief Get HCLK frequency
* @param None * @param None
@ -167,7 +166,6 @@ uint32_t CLK_GetLXTFreq(void)
* @details This function get HCLK frequency. The frequency unit is Hz. * @details This function get HCLK frequency. The frequency unit is Hz.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetHCLKFreq(void) uint32_t CLK_GetHCLKFreq(void)
@ -175,7 +173,6 @@ uint32_t CLK_GetHCLKFreq(void)
SystemCoreClockUpdate(); SystemCoreClockUpdate();
return SystemCoreClock; return SystemCoreClock;
} }
#endif
/** /**
* @brief Get PCLK0 frequency * @brief Get PCLK0 frequency
@ -183,8 +180,8 @@ uint32_t CLK_GetHCLKFreq(void)
* @return PCLK0 frequency * @return PCLK0 frequency
* @details This function get PCLK0 frequency. The frequency unit is Hz. * @details This function get PCLK0 frequency. The frequency unit is Hz.
*/ */
#endif
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetPCLK0Freq(void) uint32_t CLK_GetPCLK0Freq(void)
@ -201,7 +198,6 @@ uint32_t CLK_GetPCLK0Freq(void)
* @details This function get PCLK1 frequency. The frequency unit is Hz. * @details This function get PCLK1 frequency. The frequency unit is Hz.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetPCLK1Freq(void) uint32_t CLK_GetPCLK1Freq(void)
@ -218,13 +214,12 @@ uint32_t CLK_GetPCLK1Freq(void)
* @details This function get CPU frequency. The frequency unit is Hz. * @details This function get CPU frequency. The frequency unit is Hz.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetCPUFreq(void) uint32_t CLK_GetCPUFreq(void)
{ {
uint32_t u32Freq, u32HclkSrc, u32HclkDiv; uint32_t u32Freq, u32HclkSrc, u32HclkDiv;
uint32_t u32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, 0UL, __HIRC}; uint32_t au32ClkTbl[] = {__HXT, __LXT, 0UL, __LIRC, 0UL, __HIRC48, 0UL, __HIRC};
uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO; uint32_t u32PllReg, u32FIN, u32NF, u32NR, u32NO;
uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U}; uint8_t au8NoTbl[4] = {1U, 2U, 2U, 4U};
uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk; uint32_t u32RTCCKEN = CLK->APBCLK0 & CLK_APBCLK0_RTCCKEN_Msk;
@ -249,7 +244,7 @@ uint32_t CLK_GetCPUFreq(void)
u32FIN = __HXT; /* PLL source clock from HXT */ u32FIN = __HXT; /* PLL source clock from HXT */
} }
/* Caculate PLL frequency */ /* Calculate PLL frequency */
if(u32PllReg & CLK_PLLCTL_BP_Msk) if(u32PllReg & CLK_PLLCTL_BP_Msk)
{ {
PllClock = u32FIN; /* PLL is in bypass mode */ PllClock = u32FIN; /* PLL is in bypass mode */
@ -298,7 +293,7 @@ uint32_t CLK_GetCPUFreq(void)
} }
else else
{ {
u32Freq = u32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */ u32Freq = au32ClkTbl[u32HclkSrc]; /* Use the clock sources directly */
} }
/* HCLK clock source divider */ /* HCLK clock source divider */
@ -353,6 +348,9 @@ uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk; CLK->CLKSEL0 |= CLK_CLKSEL0_HCLKSEL_Msk;
CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk); CLK->CLKDIV0 &= (~CLK_CLKDIV0_HCLKDIV_Msk);
/* Enable Flash access cycle auto-tuning function */
FMC->CYCCTL &= (~FMC_CYCCTL_FADIS_Msk);
/* Configure PLL setting if HXT clock is stable */ /* Configure PLL setting if HXT clock is stable */
if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk) if(CLK->STATUS & CLK_STATUS_HXTSTB_Msk)
{ {
@ -372,7 +370,7 @@ uint32_t CLK_SetCoreClock(uint32_t u32Hclk)
and update system core clock and update system core clock
*/ */
CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL)); CLK_SetHCLK(CLK_CLKSEL0_HCLKSEL_PLL, CLK_CLKDIV0_HCLK(1UL));
/* Disable HIRC if HIRC is disabled before setting core clock */ /* Disable HIRC if HIRC is disabled before setting core clock */
if(u32HIRCSTB == 0UL) if(u32HIRCSTB == 0UL)
{ {
@ -411,9 +409,18 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk); CLK_WaitClockReady(CLK_STATUS_HIRCSTB_Msk);
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC; CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | CLK_CLKSEL0_HCLKSEL_HIRC;
/* Enable Flash access cycle auto-tuning function */
FMC->CYCCTL &= (~FMC_CYCCTL_FADIS_Msk);
/* Apply new Divider */ /* Apply new Divider */
CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv; CLK->CLKDIV0 = (CLK->CLKDIV0 & (~CLK_CLKDIV0_HCLKDIV_Msk)) | u32ClkDiv;
/* Disable Flash access cycle auto-tuning function and set Flash access cycle if HCLK switches to HIRC48 */
if(u32ClkSrc == CLK_CLKSEL0_HCLKSEL_HIRC48)
{
FMC->CYCCTL = (FMC->CYCCTL & (~FMC_CYCCTL_CYCLE_Msk)) | FMC_CYCCTL_FADIS_Msk | (3UL);
}
/* Switch HCLK to new HCLK source */ /* Switch HCLK to new HCLK source */
CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc; CLK->CLKSEL0 = (CLK->CLKSEL0 & (~CLK_CLKSEL0_HCLKSEL_Msk)) | u32ClkSrc;
@ -443,7 +450,6 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LXT | x |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_HCLK_DIV2048 | x |
* |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x | * |\ref WDT_MODULE |\ref CLK_CLKSEL1_WDTSEL_LIRC | x |
* |\ref DSRC_MODULE |\ref CLK_CLKSEL1_DSRCSEL_HIRC |\ref CLK_CLKDIV1_DSRC(x) |
* |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) | * |\ref EADC_MODULE | x |\ref CLK_CLKDIV0_EADC(x) |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_HXT | x |
* |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x | * |\ref TMR0_MODULE |\ref CLK_CLKSEL1_TMR0SEL_LXT | x |
@ -525,10 +531,6 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
* |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x | * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PLL | x |
* |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x | * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_PCLK0 | x |
* |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x | * |\ref SPI3_MODULE |\ref CLK_CLKSEL2_SPI3SEL_HIRC | x |
* |\ref SPI5_MODULE |\ref CLK_CLKSEL2_SPI5SEL_HXT | x |
* |\ref SPI5_MODULE |\ref CLK_CLKSEL2_SPI5SEL_PLL | x |
* |\ref SPI5_MODULE |\ref CLK_CLKSEL2_SPI5SEL_PCLK1 | x |
* |\ref SPI5_MODULE |\ref CLK_CLKSEL2_SPI5SEL_HIRC | x |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_HXT |\ref CLK_CLKDIV1_SC0(x) |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PLL |\ref CLK_CLKDIV1_SC0(x) |
* |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) | * |\ref SC0_MODULE |\ref CLK_CLKSEL3_SC0SEL_PCLK0 |\ref CLK_CLKDIV1_SC0(x) |
@ -539,32 +541,35 @@ void CLK_SetHCLK(uint32_t u32ClkSrc, uint32_t u32ClkDiv)
* |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) | * |\ref SC1_MODULE |\ref CLK_CLKSEL3_SC1SEL_HIRC |\ref CLK_CLKDIV1_SC1(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HXT |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PLL |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK1 |\ref CLK_CLKDIV1_SC2(x) | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_PCLK0 |\ref CLK_CLKDIV1_SC2(x) |
* |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) | * |\ref SC2_MODULE |\ref CLK_CLKSEL3_SC2SEL_HIRC |\ref CLK_CLKDIV1_SC2(x) |
* |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |
* |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | * |\ref USBH_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
* |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |
* |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | * |\ref OTG_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
* |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_HIRC48 |\ref CLK_CLKDIV0_USB(x) |
* |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) | * |\ref USBD_MODULE |\ref CLK_CLKSEL0_USBSEL_PLL |\ref CLK_CLKDIV0_USB(x) |
*/ */
void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv) void CLK_SetModuleClock(uint32_t u32ModuleIdx, uint32_t u32ClkSrc, uint32_t u32ClkDiv)
{ {
uint32_t u32sel = 0UL, u32div = 0UL; uint32_t u32Sel = 0UL, u32Div = 0UL;
uint32_t u32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};
uint32_t u32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};
if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
{ {
/* Get clock divider control register address */ /* Get clock divider control register address */
u32div = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); u32Div = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
/* Apply new divider */ /* Apply new divider */
M32(u32div) = (M32(u32div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv; M32(u32Div) = (M32(u32Div) & (~(MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx)))) | u32ClkDiv;
} }
if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
{ {
/* Get clock select control register address */ /* Get clock select control register address */
u32sel = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); u32Sel = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
/* Set new clock selection setting */ /* Set new clock selection setting */
M32(u32sel) = (M32(u32sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc; M32(u32Sel) = (M32(u32Sel) & (~(MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx)))) | u32ClkSrc;
} }
} }
@ -629,6 +634,7 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
* - \ref SDH0_MODULE * - \ref SDH0_MODULE
* - \ref CRC_MODULE * - \ref CRC_MODULE
* - \ref CRPT_MODULE * - \ref CRPT_MODULE
* - \ref FMCIDLE_MODULE
* - \ref USBH_MODULE * - \ref USBH_MODULE
* - \ref WDT_MODULE * - \ref WDT_MODULE
* - \ref WWDT_MODULE * - \ref WWDT_MODULE
@ -647,14 +653,12 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
* - \ref SPI1_MODULE * - \ref SPI1_MODULE
* - \ref SPI2_MODULE * - \ref SPI2_MODULE
* - \ref SPI3_MODULE * - \ref SPI3_MODULE
* - \ref SPI5_MODULE
* - \ref UART0_MODULE * - \ref UART0_MODULE
* - \ref UART1_MODULE * - \ref UART1_MODULE
* - \ref UART2_MODULE * - \ref UART2_MODULE
* - \ref UART3_MODULE * - \ref UART3_MODULE
* - \ref UART4_MODULE * - \ref UART4_MODULE
* - \ref UART5_MODULE * - \ref UART5_MODULE
* - \ref DSRC_MODULE
* - \ref CAN0_MODULE * - \ref CAN0_MODULE
* - \ref OTG_MODULE * - \ref OTG_MODULE
* - \ref USBD_MODULE * - \ref USBD_MODULE
@ -681,13 +685,13 @@ void CLK_DisableXtalRC(uint32_t u32ClkMask)
*/ */
void CLK_EnableModuleClock(uint32_t u32ModuleIdx) void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
{ {
uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
u32tmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); u32TmpVal = (1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
u32tmpAddr = (uint32_t)&CLK->AHBCLK; u32TmpAddr = (uint32_t)&CLK->AHBCLK;
u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
*(volatile uint32_t *)u32tmpAddr |= u32tmpVal; *(volatile uint32_t *)u32TmpAddr |= u32TmpVal;
} }
/** /**
@ -700,6 +704,7 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
* - \ref SDH0_MODULE * - \ref SDH0_MODULE
* - \ref CRC_MODULE * - \ref CRC_MODULE
* - \ref CRPT_MODULE * - \ref CRPT_MODULE
* - \ref FMCIDLE_MODULE
* - \ref USBH_MODULE * - \ref USBH_MODULE
* - \ref WDT_MODULE * - \ref WDT_MODULE
* - \ref WWDT_MODULE * - \ref WWDT_MODULE
@ -718,14 +723,12 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
* - \ref SPI1_MODULE * - \ref SPI1_MODULE
* - \ref SPI2_MODULE * - \ref SPI2_MODULE
* - \ref SPI3_MODULE * - \ref SPI3_MODULE
* - \ref SPI5_MODULE
* - \ref UART0_MODULE * - \ref UART0_MODULE
* - \ref UART1_MODULE * - \ref UART1_MODULE
* - \ref UART2_MODULE * - \ref UART2_MODULE
* - \ref UART3_MODULE * - \ref UART3_MODULE
* - \ref UART4_MODULE * - \ref UART4_MODULE
* - \ref UART5_MODULE * - \ref UART5_MODULE
* - \ref DSRC_MODULE
* - \ref CAN0_MODULE * - \ref CAN0_MODULE
* - \ref OTG_MODULE * - \ref OTG_MODULE
* - \ref USBD_MODULE * - \ref USBD_MODULE
@ -752,13 +755,13 @@ void CLK_EnableModuleClock(uint32_t u32ModuleIdx)
*/ */
void CLK_DisableModuleClock(uint32_t u32ModuleIdx) void CLK_DisableModuleClock(uint32_t u32ModuleIdx)
{ {
uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
u32tmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx)); u32TmpVal = ~(1UL << MODULE_IP_EN_Pos(u32ModuleIdx));
u32tmpAddr = (uint32_t)&CLK->AHBCLK; u32TmpAddr = (uint32_t)&CLK->AHBCLK;
u32tmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL)); u32TmpAddr += ((MODULE_APBCLK(u32ModuleIdx) * 4UL));
*(uint32_t *)u32tmpAddr &= u32tmpVal; *(uint32_t *)u32TmpAddr &= u32TmpVal;
} }
@ -1043,32 +1046,32 @@ uint32_t CLK_GetPMUWKSrc(void)
} }
/** /**
* @brief Set specified GPIO as wake up source at Stand-by Power down mode * @brief Set specified GPIO as wake up source at Standby Power-down mode
* @param[in] u32Port GPIO port. It could be 0~3. * @param[in] u32Port GPIO port. It could be 0~3.
* @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15. * @param[in] u32Pin The pin of specified GPIO port. It could be 0 ~ 15.
* @param[in] u32TriggerType Wake-up pin trigger type * @param[in] u32TriggerType Wake-up pin trigger type
* - \ref CLK_SPDWKPIN_RISING * - \ref CLK_SPDWKPIN_RISING
* - \ref CLK_SPDWKPIN_FALLING * - \ref CLK_SPDWKPIN_FALLING
* @param[in] u32DebounceEn Standby power-down mode wake-up pin de-bounce function * @param[in] u32DebounceEn Standby Power-down mode wake-up pin de-bounce function
* - \ref CLK_SPDWKPIN_DEBOUNCEEN * - \ref CLK_SPDWKPIN_DEBOUNCEEN
* - \ref CLK_SPDWKPIN_DEBOUNCEDIS * - \ref CLK_SPDWKPIN_DEBOUNCEDIS
* @return None * @return None
* @details This function is used to set specified GPIO as wake up source at Stand-by Power down mode. * @details This function is used to set specified GPIO as wake up source at Standby Power-down mode.
*/ */
void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn) void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerType, uint32_t u32DebounceEn)
{ {
uint32_t u32tmpAddr = 0UL; uint32_t u32TmpAddr = 0UL;
uint32_t u32tmpVal = 0UL; uint32_t u32TmpVal = 0UL;
/* GPx Stand-by Power-down Wake-up Pin Select */ /* GPx Stand-by Power-down Wake-up Pin Select */
u32tmpAddr = (uint32_t)&CLK->PASWKCTL; u32TmpAddr = (uint32_t)&CLK->PASWKCTL;
u32tmpAddr += (0x4UL * u32Port); u32TmpAddr += (0x4UL * u32Port);
u32tmpVal = inpw((uint32_t *)u32tmpAddr); u32TmpVal = inpw((uint32_t *)u32TmpAddr);
u32tmpVal = (u32tmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) | u32TmpVal = (u32TmpVal & ~(CLK_PASWKCTL_WKPSEL_Msk | CLK_PASWKCTL_PRWKEN_Msk | CLK_PASWKCTL_PFWKEN_Msk | CLK_PASWKCTL_DBEN_Msk | CLK_PASWKCTL_WKEN_Msk)) |
(u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE; (u32Pin << CLK_PASWKCTL_WKPSEL_Pos) | u32TriggerType | u32DebounceEn | CLK_SPDWKPIN_ENABLE;
outpw((uint32_t *)u32tmpAddr, u32tmpVal); outpw((uint32_t *)u32TmpAddr, u32TmpVal);
} }
/** /**
@ -1078,7 +1081,6 @@ void CLK_EnableSPDWKPin(uint32_t u32Port, uint32_t u32Pin, uint32_t u32TriggerTy
* @details This function get PLL frequency. The frequency unit is Hz. * @details This function get PLL frequency. The frequency unit is Hz.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetPLLClockFreq(void) uint32_t CLK_GetPLLClockFreq(void)
@ -1106,7 +1108,7 @@ uint32_t CLK_GetPLLClockFreq(void)
u32FIN = __HXT; /* PLL source clock from HXT */ u32FIN = __HXT; /* PLL source clock from HXT */
} }
/* Caculate PLL frequency */ /* Calculate PLL frequency */
if(u32PllReg & CLK_PLLCTL_BP_Msk) if(u32PllReg & CLK_PLLCTL_BP_Msk)
{ {
u32PllFreq = u32FIN; /* PLL is in bypass mode */ u32PllFreq = u32FIN; /* PLL is in bypass mode */
@ -1145,14 +1147,12 @@ uint32_t CLK_GetPLLClockFreq(void)
* - \ref SPI1_MODULE * - \ref SPI1_MODULE
* - \ref SPI2_MODULE * - \ref SPI2_MODULE
* - \ref SPI3_MODULE * - \ref SPI3_MODULE
* - \ref SPI5_MODULE
* - \ref UART0_MODULE * - \ref UART0_MODULE
* - \ref UART1_MODULE * - \ref UART1_MODULE
* - \ref UART2_MODULE * - \ref UART2_MODULE
* - \ref UART3_MODULE * - \ref UART3_MODULE
* - \ref UART4_MODULE * - \ref UART4_MODULE
* - \ref UART5_MODULE * - \ref UART5_MODULE
* - \ref DSRC_MODULE
* - \ref OTG_MODULE * - \ref OTG_MODULE
* - \ref USBD_MODULE * - \ref USBD_MODULE
* - \ref I2S0_MODULE * - \ref I2S0_MODULE
@ -1167,41 +1167,40 @@ uint32_t CLK_GetPLLClockFreq(void)
* @details This function get selected module clock source. * @details This function get selected module clock source.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx) uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
{ {
uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
uint32_t u32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL}; uint32_t au32SelTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0xCUL};
/* Get clock source selection setting */ /* Get clock source selection setting */
if(u32ModuleIdx == EPWM0_MODULE) if(u32ModuleIdx == EPWM0_MODULE)
{ {
u32tmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos); u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM0SEL_Msk) >> CLK_CLKSEL2_EPWM0SEL_Pos);
} }
else if(u32ModuleIdx == EPWM1_MODULE) else if(u32ModuleIdx == EPWM1_MODULE)
{ {
u32tmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos); u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_EPWM1SEL_Msk) >> CLK_CLKSEL2_EPWM1SEL_Pos);
} }
else if(u32ModuleIdx == BPWM0_MODULE) else if(u32ModuleIdx == BPWM0_MODULE)
{ {
u32tmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos); u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM0SEL_Msk) >> CLK_CLKSEL2_BPWM0SEL_Pos);
} }
else if(u32ModuleIdx == BPWM1_MODULE) else if(u32ModuleIdx == BPWM1_MODULE)
{ {
u32tmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos); u32TmpVal = ((CLK->CLKSEL2 & CLK_CLKSEL2_BPWM1SEL_Msk) >> CLK_CLKSEL2_BPWM1SEL_Pos);
} }
else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk) else if(MODULE_CLKSEL_Msk(u32ModuleIdx) != MODULE_NoMsk)
{ {
/* Get clock select control register address */ /* Get clock select control register address */
u32tmpAddr = (uint32_t)&CLK->CLKSEL0 + (u32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]); u32TmpAddr = (uint32_t)&CLK->CLKSEL0 + (au32SelTbl[MODULE_CLKSEL(u32ModuleIdx)]);
/* Get clock source selection setting */ /* Get clock source selection setting */
u32tmpVal = ((inpw((uint32_t *)u32tmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx)); u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKSEL_Msk(u32ModuleIdx) << MODULE_CLKSEL_Pos(u32ModuleIdx))) >> MODULE_CLKSEL_Pos(u32ModuleIdx));
} }
return u32tmpVal; return u32TmpVal;
} }
#endif #endif
@ -1216,7 +1215,6 @@ uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
* - \ref UART3_MODULE * - \ref UART3_MODULE
* - \ref UART4_MODULE * - \ref UART4_MODULE
* - \ref UART5_MODULE * - \ref UART5_MODULE
* - \ref DSRC_MODULE
* - \ref OTG_MODULE * - \ref OTG_MODULE
* - \ref USBD_MODULE * - \ref USBD_MODULE
* - \ref SC0_MODULE * - \ref SC0_MODULE
@ -1227,27 +1225,25 @@ uint32_t CLK_GetModuleClockSource(uint32_t u32ModuleIdx)
* @details This function get selected module clock divider number. * @details This function get selected module clock divider number.
*/ */
//__NONSECURE_ENTRY_WEAK
#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
__NONSECURE_ENTRY __NONSECURE_ENTRY
uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx) uint32_t CLK_GetModuleClockDivider(uint32_t u32ModuleIdx)
{ {
uint32_t u32tmpVal = 0UL, u32tmpAddr = 0UL; uint32_t u32TmpVal = 0UL, u32TmpAddr = 0UL;
uint32_t u32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL}; uint32_t au32DivTbl[4] = {0x0UL, 0x4UL, 0x8UL, 0x10UL};
if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk) if(MODULE_CLKDIV_Msk(u32ModuleIdx) != MODULE_NoMsk)
{ {
/* Get clock divider control register address */ /* Get clock divider control register address */
u32tmpAddr = (uint32_t)&CLK->CLKDIV0 + (u32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]); u32TmpAddr = (uint32_t)&CLK->CLKDIV0 + (au32DivTbl[MODULE_CLKDIV(u32ModuleIdx)]);
/* Get clock divider number setting */ /* Get clock divider number setting */
u32tmpVal = ((inpw((uint32_t *)u32tmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx)); u32TmpVal = ((inpw((uint32_t *)u32TmpAddr) & (MODULE_CLKDIV_Msk(u32ModuleIdx) << MODULE_CLKDIV_Pos(u32ModuleIdx))) >> MODULE_CLKDIV_Pos(u32ModuleIdx));
} }
return u32tmpVal; return u32TmpVal;
} }
#endif #endif
/*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */ /*@}*/ /* end of group CLK_EXPORTED_FUNCTIONS */
/*@}*/ /* end of group CLK_Driver */ /*@}*/ /* end of group CLK_Driver */

10
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_crc.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_crc.c
View File

@ -76,7 +76,7 @@ void CRC_Open(uint32_t u32Mode, uint32_t u32Attribute, uint32_t u32Seed, uint32_
uint32_t CRC_GetChecksum(void) uint32_t CRC_GetChecksum(void)
{ {
CRC_T *pCRC; CRC_T *pCRC;
uint32_t u332Checksum = 0UL; uint32_t u32Checksum = 0UL;
if((__PC()&NS_OFFSET) == NS_OFFSET) if((__PC()&NS_OFFSET) == NS_OFFSET)
{ {
@ -91,22 +91,22 @@ uint32_t CRC_GetChecksum(void)
{ {
case CRC_CCITT: case CRC_CCITT:
case CRC_16: case CRC_16:
u332Checksum = (pCRC->CHECKSUM & 0xFFFFUL); u32Checksum = (pCRC->CHECKSUM & 0xFFFFUL);
break; break;
case CRC_32: case CRC_32:
u332Checksum = pCRC->CHECKSUM; u32Checksum = pCRC->CHECKSUM;
break; break;
case CRC_8: case CRC_8:
u332Checksum = (pCRC->CHECKSUM & 0xFFUL); u32Checksum = (pCRC->CHECKSUM & 0xFFUL);
break; break;
default: default:
break; break;
} }
return u332Checksum; return u32Checksum;
} }
/*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */ /*@}*/ /* end of group CRC_EXPORTED_FUNCTIONS */

44
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_crypto.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_crypto.c
View File

@ -475,7 +475,7 @@ enum
/* Define elliptic curve (EC): */ /* Define elliptic curve (EC): */
/*-----------------------------------------------------*/ /*-----------------------------------------------------*/
#if !XOM_SUPPORT // Replace with XOM ready curve table #if !XOM_SUPPORT // Replace with XOM ready curve table
const ECC_CURVE _Curve[] = static const ECC_CURVE _Curve[] =
{ {
{ {
/* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */ /* NIST: Curve P-192 : y^2=x^3-ax+b (mod p) */
@ -760,7 +760,7 @@ static void run_ecc_codec(CRPT_T *crpt, uint32_t mode);
static char temp_hex_str[160]; static char temp_hex_str[160];
volatile uint32_t g_ECC_done, g_ECCERR_done; static volatile uint32_t g_ECC_done, g_ECCERR_done;
void ECC_DriverISR(CRPT_T *crpt) void ECC_DriverISR(CRPT_T *crpt)
{ {
@ -1757,7 +1757,7 @@ int32_t ECC_VerifySignature(CRPT_T *crpt, E_ECC_CURVE ecc_curve, char *message,
#if XOM_SUPPORT // To support XOM ready curve table #if XOM_SUPPORT // To support XOM ready curve table
int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id) static int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
{ {
int32_t i; int32_t i;
@ -1851,7 +1851,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000002; p32[238] = 0x00000002;
p32[239] = 0x00000001; p32[239] = 0x00000001;
p32[240] = 0x00000000; p32[240] = 0x00000000;
break; return 0;
case CURVE_P_224: case CURVE_P_224:
p32[ 0] = 0x00000001; p32[ 0] = 0x00000001;
p32[ 1] = 0x00000038; p32[ 1] = 0x00000038;
@ -1947,7 +1947,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000008; p32[238] = 0x00000008;
p32[239] = 0x00000003; p32[239] = 0x00000003;
p32[240] = 0x00000000; p32[240] = 0x00000000;
break; return 0;
case CURVE_P_256: case CURVE_P_256:
p32[ 0] = 0x00000002; p32[ 0] = 0x00000002;
p32[ 1] = 0x00000040; p32[ 1] = 0x00000040;
@ -2060,7 +2060,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000005; p32[238] = 0x00000005;
p32[239] = 0x00000002; p32[239] = 0x00000002;
p32[240] = 0x00000000; p32[240] = 0x00000000;
break; return 0;
case CURVE_P_384: case CURVE_P_384:
p32[ 0] = 0x00000003; p32[ 0] = 0x00000003;
p32[ 1] = 0x00000060; p32[ 1] = 0x00000060;
@ -2198,7 +2198,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000003; p32[238] = 0x00000003;
p32[239] = 0x00000002; p32[239] = 0x00000002;
p32[240] = 0x00000000; p32[240] = 0x00000000;
break; return 0;
case CURVE_P_521: case CURVE_P_521:
p32[ 0] = 0x00000004; p32[ 0] = 0x00000004;
p32[ 1] = 0x00000083; p32[ 1] = 0x00000083;
@ -2357,7 +2357,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000020; p32[238] = 0x00000020;
p32[239] = 0x00000020; p32[239] = 0x00000020;
p32[240] = 0x00000000; p32[240] = 0x00000000;
break; return 0;
case CURVE_B_163: case CURVE_B_163:
p32[ 0] = 0x0000000a; p32[ 0] = 0x0000000a;
p32[ 1] = 0x00000029; p32[ 1] = 0x00000029;
@ -2440,7 +2440,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000006; p32[238] = 0x00000006;
p32[239] = 0x00000003; p32[239] = 0x00000003;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_B_233: case CURVE_B_233:
p32[ 0] = 0x0000000b; p32[ 0] = 0x0000000b;
p32[ 1] = 0x0000003b; p32[ 1] = 0x0000003b;
@ -2537,7 +2537,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x0000004a; p32[238] = 0x0000004a;
p32[239] = 0x0000004a; p32[239] = 0x0000004a;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_B_283: case CURVE_B_283:
p32[ 0] = 0x0000000c; p32[ 0] = 0x0000000c;
p32[ 1] = 0x00000047; p32[ 1] = 0x00000047;
@ -2645,7 +2645,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000007; p32[238] = 0x00000007;
p32[239] = 0x00000005; p32[239] = 0x00000005;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_B_409: case CURVE_B_409:
p32[ 0] = 0x0000000d; p32[ 0] = 0x0000000d;
p32[ 1] = 0x00000067; p32[ 1] = 0x00000067;
@ -2780,7 +2780,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000057; p32[238] = 0x00000057;
p32[239] = 0x00000057; p32[239] = 0x00000057;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_B_571: case CURVE_B_571:
p32[ 0] = 0x0000000e; p32[ 0] = 0x0000000e;
p32[ 1] = 0x0000008f; p32[ 1] = 0x0000008f;
@ -2939,7 +2939,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000005; p32[238] = 0x00000005;
p32[239] = 0x00000002; p32[239] = 0x00000002;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_K_163: case CURVE_K_163:
p32[ 0] = 0x00000005; p32[ 0] = 0x00000005;
p32[ 1] = 0x00000029; p32[ 1] = 0x00000029;
@ -3015,7 +3015,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000006; p32[238] = 0x00000006;
p32[239] = 0x00000003; p32[239] = 0x00000003;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_K_233: case CURVE_K_233:
p32[ 0] = 0x00000006; p32[ 0] = 0x00000006;
p32[ 1] = 0x0000003b; p32[ 1] = 0x0000003b;
@ -3101,7 +3101,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x0000004a; p32[238] = 0x0000004a;
p32[239] = 0x0000004a; p32[239] = 0x0000004a;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_K_283: case CURVE_K_283:
p32[ 0] = 0x00000007; p32[ 0] = 0x00000007;
p32[ 1] = 0x00000047; p32[ 1] = 0x00000047;
@ -3195,7 +3195,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000007; p32[238] = 0x00000007;
p32[239] = 0x00000005; p32[239] = 0x00000005;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_K_409: case CURVE_K_409:
p32[ 0] = 0x00000008; p32[ 0] = 0x00000008;
p32[ 1] = 0x00000067; p32[ 1] = 0x00000067;
@ -3309,7 +3309,7 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000057; p32[238] = 0x00000057;
p32[239] = 0x00000057; p32[239] = 0x00000057;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
case CURVE_K_571: case CURVE_K_571:
p32[ 0] = 0x00000009; p32[ 0] = 0x00000009;
p32[ 1] = 0x0000008f; p32[ 1] = 0x0000008f;
@ -3436,22 +3436,16 @@ int32_t CurveCpy(unsigned int *p32, E_ECC_CURVE id)
p32[238] = 0x00000005; p32[238] = 0x00000005;
p32[239] = 0x00000002; p32[239] = 0x00000002;
p32[240] = 0x00000001; p32[240] = 0x00000001;
break; return 0;
default:
return -1;
} }
return 0; return -1;
} }
static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve) static ECC_CURVE * get_curve(E_ECC_CURVE ecc_curve)
{ {
uint32_t i;
ECC_CURVE *ret = NULL;
if(CurveCpy((unsigned int *)&Curve_Copy, ecc_curve)) if(CurveCpy((unsigned int *)&Curve_Copy, ecc_curve))
return NULL; return NULL;
else else

4
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_dac.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_dac.c
View File

@ -4,7 +4,7 @@
* @brief M2351 series DAC driver source file * @brief M2351 series DAC driver source file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#include "NuMicro.h" #include "NuMicro.h"
@ -88,4 +88,4 @@ uint32_t DAC_SetDelayTime(DAC_T *dac, uint32_t u32Delay)
/*@}*/ /* end of group Standard_Driver */ /*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

4
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_eadc.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_eadc.c
View File

@ -4,7 +4,7 @@
* @brief M2351 series EADC driver source file * @brief M2351 series EADC driver source file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#include "NuMicro.h" #include "NuMicro.h"
@ -141,4 +141,4 @@ void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32E
/*@}*/ /* end of group Standard_Driver */ /*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_ebi.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_ebi.c
View File

0
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_ecap.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_ecap.c
View File

44
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_epwm.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_epwm.c
View File

@ -4,7 +4,7 @@
* @brief M2351 series EPWM driver source file * @brief M2351 series EPWM driver source file
* *
* @note * @note
* Copyright (C) 2016 Nuvoton Technology Corp. All rights reserved. * Copyright (C) 2017 Nuvoton Technology Corp. All rights reserved.
*****************************************************************************/ *****************************************************************************/
#include "NuMicro.h" #include "NuMicro.h"
@ -35,8 +35,8 @@
uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge) uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_t u32UnitTimeNsec, uint32_t u32CaptureEdge)
{ {
uint32_t u32PWMClockSrc; uint32_t u32PWMClockSrc;
uint32_t u32NearestUnitTimeNsec; uint32_t u32NearestUnitTimeNsec = 0U;
uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
uint8_t u8BreakLoop = 0U; uint8_t u8BreakLoop = 0U;
/* clock source is from PCLK */ /* clock source is from PCLK */
@ -50,16 +50,16 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
} }
u32PWMClockSrc /= 1000UL; u32PWMClockSrc /= 1000UL;
for(u16Prescale = 1U; u16Prescale <= 0x1000U; u16Prescale++) for(u32Prescale = 1U; u32Prescale <= 0x1000U; u32Prescale++)
{ {
u32NearestUnitTimeNsec = (1000000UL * u16Prescale) / u32PWMClockSrc; u32NearestUnitTimeNsec = (1000000UL * u32Prescale) / u32PWMClockSrc;
if(u32NearestUnitTimeNsec < u32UnitTimeNsec) if(u32NearestUnitTimeNsec < u32UnitTimeNsec)
{ {
if(u16Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */ if(u32Prescale == 0x1000U) /* limit to the maximum unit time(nano second) */
{ {
u8BreakLoop = 1U; u8BreakLoop = 1U;
} }
if(!((1000000UL * (u16Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc)))) if(!((1000000UL * (u32Prescale + 1UL) > (u32NearestUnitTimeNsec * u32PWMClockSrc))))
{ {
u8BreakLoop = 1U; u8BreakLoop = 1U;
} }
@ -75,15 +75,15 @@ uint32_t EPWM_ConfigCaptureChannel(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
} }
/* convert to real register value */ /* convert to real register value */
u16Prescale = u16Prescale - 1U; u32Prescale = u32Prescale - 1U;
/* every two channels share a prescaler */ /* every two channels share a prescaler */
EPWM_SET_PRESCALER(epwm, u32ChannelNum, (uint32_t)u16Prescale); EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
/* set EPWM to down count type(edge aligned) */ /* set EPWM to down count type(edge aligned) */
(epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1))) | (1UL << (u32ChannelNum << 1)); (epwm)->CTL1 = ((epwm)->CTL1 & ~(EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1))) | (1UL << (u32ChannelNum << 1));
/* set EPWM to auto-reload mode */ /* set EPWM to auto-reload mode */
(epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum); (epwm)->CTL1 &= ~(EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum);
EPWM_SET_CNR(epwm, u32ChannelNum, u16CNR); EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
return (u32NearestUnitTimeNsec); return (u32NearestUnitTimeNsec);
} }
@ -126,7 +126,7 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
{ {
uint32_t u32PWMClockSrc; uint32_t u32PWMClockSrc;
uint32_t i; uint32_t i;
uint16_t u16Prescale = 1U, u16CNR = 0xFFFFU; uint32_t u32Prescale = 1U, u32CNR = 0xFFFFU;
/* clock source is from PCLK */ /* clock source is from PCLK */
if((epwm == EPWM0) || (epwm == EPWM0_NS)) if((epwm == EPWM0) || (epwm == EPWM0_NS))
@ -138,30 +138,30 @@ uint32_t EPWM_ConfigOutputChannel2(EPWM_T *epwm, uint32_t u32ChannelNum, uint32_
u32PWMClockSrc = CLK_GetPCLK1Freq(); u32PWMClockSrc = CLK_GetPCLK1Freq();
} }
for(u16Prescale = 1U; u16Prescale < 0xFFFU; u16Prescale++)/* prescale could be 0~0xFFF */ for(u32Prescale = 1U; u32Prescale < 0xFFFU; u32Prescale++)/* prescale could be 0~0xFFF */
{ {
// Note: Support frequency < 1 // Note: Support frequency < 1
i = (uint64_t) u32PWMClockSrc * u32Frequency2 / u32Frequency / u16Prescale; i = (uint64_t) u32PWMClockSrc * u32Frequency2 / u32Frequency / u32Prescale;
/* If target value is larger than CNR, need to use a larger prescaler */ /* If target value is larger than CNR, need to use a larger prescaler */
if(i <= (0x10000U)) if(i <= (0x10000U))
{ {
u16CNR = (uint16_t)i; u32CNR = i;
break; break;
} }
} }
/* Store return value here 'cos we're gonna change u16Prescale & u16CNR to the real value to fill into register */ /* Store return value here 'cos we're gonna change u32Prescale & u32CNR to the real value to fill into register */
i = u32PWMClockSrc / ((uint32_t)u16Prescale * (uint32_t)u16CNR); i = u32PWMClockSrc / (u32Prescale * u32CNR);
/* convert to real register value */ /* convert to real register value */
u16Prescale = u16Prescale - 1U; u32Prescale = u32Prescale - 1U;
/* every two channels share a prescaler */ /* every two channels share a prescaler */
EPWM_SET_PRESCALER(epwm, u32ChannelNum, (uint32_t)u16Prescale); EPWM_SET_PRESCALER(epwm, u32ChannelNum, u32Prescale);
/* set EPWM to up counter type(edge aligned) and auto-reload mode */ /* set EPWM to up counter type(edge aligned) and auto-reload mode */
(epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1)) | (EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum))); (epwm)->CTL1 = ((epwm)->CTL1 & ~((EPWM_CTL1_CNTTYPE0_Msk << (u32ChannelNum << 1)) | (EPWM_CTL1_CNTMODE0_Msk << u32ChannelNum)));
u16CNR = u16CNR - 1U; u32CNR = u32CNR - 1U;
EPWM_SET_CNR(epwm, u32ChannelNum, (uint32_t)u16CNR); EPWM_SET_CNR(epwm, u32ChannelNum, u32CNR);
EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u16CNR + 1UL) / 100UL); EPWM_SET_CMR(epwm, u32ChannelNum, u32DutyCycle * (u32CNR + 1UL) / 100UL);
(epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \ (epwm)->WGCTL0 = ((epwm)->WGCTL0 & ~((EPWM_WGCTL0_PRDPCTL0_Msk | EPWM_WGCTL0_ZPCTL0_Msk) << (u32ChannelNum << 1))) | \
(EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos)); (EPWM_OUTPUT_HIGH << (u32ChannelNum << 1UL << EPWM_WGCTL0_ZPCTL0_Pos));
@ -1410,4 +1410,4 @@ void EPWM_ClearWrapAroundFlag(EPWM_T *epwm, uint32_t u32ChannelNum)
/*@}*/ /* end of group Standard_Driver */ /*@}*/ /* end of group Standard_Driver */
/*** (C) COPYRIGHT 2016 Nuvoton Technology Corp. ***/ /*** (C) COPYRIGHT 2017 Nuvoton Technology Corp. ***/

159
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_fmc.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_fmc.c
View File

@ -87,9 +87,9 @@ void FMC_Close(void)
/** /**
* @brief Config XOM Region * @brief Config XOM Region
* @param[in] xom_num The XOM number(0~3) * @param[in] u32XomNum The XOM number(0~3)
* @param[in] xom_base The XOM region base address. * @param[in] u32XomBase The XOM region base address.
* @param[in] xom_page The XOM page number of region size. * @param[in] u8XomPage The XOM page number of region size.
* *
* @retval 0 Success * @retval 0 Success
* @retval 1 XOM is has already actived. * @retval 1 XOM is has already actived.
@ -98,25 +98,25 @@ void FMC_Close(void)
* *
* @details Program XOM base address and XOM size(page) * @details Program XOM base address and XOM size(page)
*/ */
int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page) int32_t FMC_ConfigXOM(uint32_t u32XomNum, uint32_t u32XomBase, uint8_t u8XomPage)
{ {
int32_t ret = 0; int32_t ret = 0;
if(xom_num >= 4UL) if(u32XomNum >= 4UL)
{ {
ret = -2; ret = -2;
} }
if(ret == 0) if(ret == 0)
{ {
ret = FMC_GetXOMState(xom_num); ret = FMC_GetXOMState(u32XomNum);
} }
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u); FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u);
FMC->ISPDAT = xom_base; FMC->ISPDAT = u32XomBase;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
@ -130,8 +130,8 @@ int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u + 0x04u); FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x04u);
FMC->ISPDAT = xom_page; FMC->ISPDAT = u8XomPage;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
@ -145,7 +145,7 @@ int32_t FMC_ConfigXOM(uint32_t xom_num, uint32_t xom_base, uint8_t xom_page)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_XOM_BASE + (xom_num * 0x10u + 0x08u); FMC->ISPADDR = FMC_XOM_BASE + (u32XomNum * 0x10u + 0x08u);
FMC->ISPDAT = 0u; FMC->ISPDAT = 0u;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {} while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) {}
@ -255,7 +255,7 @@ int32_t FMC_Erase_Block(uint32_t u32BlockAddr)
/** /**
* @brief Execute Erase XOM Region * @brief Execute Erase XOM Region
* *
* @param[in] xom_num The XOMRn(n=0~3) * @param[in] u32XomNum The XOMRn(n=0~3)
* *
* @return XOM erase success or not. * @return XOM erase success or not.
* @retval 0 Success * @retval 0 Success
@ -264,39 +264,24 @@ int32_t FMC_Erase_Block(uint32_t u32BlockAddr)
* *
* @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM. * @details Execute FMC_ISPCMD_PAGE_ERASE command to erase XOM.
*/ */
int32_t FMC_EraseXOM(uint32_t xom_num) int32_t FMC_EraseXOM(uint32_t u32XomNum)
{ {
uint32_t u32Addr; uint32_t u32Addr;
int32_t i32Active, err = 0; int32_t i32Active, err = 0;
if(xom_num >= 4UL) if(u32XomNum >= 4UL)
{ {
err = -2; err = -2;
} }
if(err == 0) if(err == 0)
{ {
i32Active = FMC_GetXOMState(xom_num); i32Active = FMC_GetXOMState(u32XomNum);
if(i32Active) if(i32Active)
{ {
switch(xom_num) u32Addr = ( ( (uint32_t)(&FMC->XOMR0STS)[u32XomNum] ) & 0xFFFFFF00u ) >> 8u;
{
case 0u:
u32Addr = (FMC->XOMR0STS & 0xFFFFFF00u) >> 8u;
break;
case 1u:
u32Addr = (FMC->XOMR1STS & 0xFFFFFF00u) >> 8u;
break;
case 2u:
u32Addr = (FMC->XOMR2STS & 0xFFFFFF00u) >> 8u;
break;
case 3u:
u32Addr = (FMC->XOMR3STS & 0xFFFFFF00u) >> 8u;
break;
default:
break;
}
FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE; FMC->ISPCMD = FMC_ISPCMD_PAGE_ERASE;
FMC->ISPADDR = u32Addr; FMC->ISPADDR = u32Addr;
FMC->ISPDAT = 0x55aa03u; FMC->ISPDAT = 0x55aa03u;
@ -389,7 +374,7 @@ uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
/** /**
* @brief Check the OTP is locked or not. * @brief Check the OTP is locked or not.
* *
* @param[in] otp_num The OTP number. * @param[in] u32OtpNum The OTP number.
* *
* @retval 1 OTP is locked. * @retval 1 OTP is locked.
* @retval 0 OTP is not locked. * @retval 0 OTP is not locked.
@ -398,11 +383,11 @@ uint32_t FMC_GetChkSum(uint32_t u32addr, uint32_t u32count)
* *
* @details To get specify OTP lock status * @details To get specify OTP lock status
*/ */
int32_t FMC_Is_OTP_Locked(uint32_t otp_num) int32_t FMC_Is_OTP_Locked(uint32_t u32OtpNum)
{ {
int32_t ret = 0; int32_t ret = 0;
if(otp_num > 255UL) if(u32OtpNum > 255UL)
{ {
ret = -2; ret = -2;
} }
@ -410,7 +395,7 @@ int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_READ; FMC->ISPCMD = FMC_ISPCMD_READ;
FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
@ -434,7 +419,7 @@ int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
/** /**
* @brief Check the XOM is actived or not. * @brief Check the XOM is actived or not.
* *
* @param[in] xom_num The xom number(0~3). * @param[in] u32XomNum The xom number(0~3).
* *
* @retval 1 XOM is actived. * @retval 1 XOM is actived.
* @retval 0 XOM is not actived. * @retval 0 XOM is not actived.
@ -442,19 +427,19 @@ int32_t FMC_Is_OTP_Locked(uint32_t otp_num)
* *
* @details To get specify XOMRn(n=0~3) active status * @details To get specify XOMRn(n=0~3) active status
*/ */
int32_t FMC_GetXOMState(uint32_t xom_num) int32_t FMC_GetXOMState(uint32_t u32XomNum)
{ {
uint32_t u32act; uint32_t u32act;
int32_t ret = 0; int32_t ret = 0;
if(xom_num >= 4UL) if(u32XomNum >= 4UL)
{ {
ret = -2; ret = -2;
} }
if(ret >= 0) if(ret >= 0)
{ {
u32act = (((FMC->XOMSTS) & 0xful) & (1ul << xom_num)) >> xom_num; u32act = (((FMC->XOMSTS) & 0xful) & (1ul << u32XomNum)) >> u32XomNum;
ret = (int32_t)u32act; ret = (int32_t)u32act;
} }
return ret; return ret;
@ -463,7 +448,7 @@ int32_t FMC_GetXOMState(uint32_t xom_num)
/** /**
* @brief Lock the specified OTP. * @brief Lock the specified OTP.
* *
* @param[in] otp_num The OTP number. * @param[in] u32OtpNum The OTP number.
* *
* @retval 0 Success * @retval 0 Success
* @retval -1 Failed to write OTP lock bits. * @retval -1 Failed to write OTP lock bits.
@ -471,11 +456,11 @@ int32_t FMC_GetXOMState(uint32_t xom_num)
* *
* @details To lock specified OTP number * @details To lock specified OTP number
*/ */
int32_t FMC_Lock_OTP(uint32_t otp_num) int32_t FMC_Lock_OTP(uint32_t u32OtpNum)
{ {
int32_t ret = 0; int32_t ret = 0;
if(otp_num > 255UL) if(u32OtpNum > 255UL)
{ {
ret = -2; ret = -2;
} }
@ -483,7 +468,7 @@ int32_t FMC_Lock_OTP(uint32_t otp_num)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + otp_num * 4UL; FMC->ISPADDR = FMC_OTP_BASE + 0x800UL + u32OtpNum * 4UL;
FMC->ISPDAT = 0UL; FMC->ISPDAT = 0UL;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
@ -578,9 +563,9 @@ int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1)
/** /**
* @brief Read data from OTP * @brief Read data from OTP
* *
* @param[in] otp_num The OTP number(0~255). * @param[in] u32OtpNum The OTP number(0~255).
* @param[in] low_word Low word of the 64-bits data. * @param[in] u32LowWord Low word of the 64-bits data.
* @param[in] high_word High word of the 64-bits data. * @param[in] u32HighWord High word of the 64-bits data.
* *
* @retval 0 Success * @retval 0 Success
* @retval -1 Read failed. * @retval -1 Read failed.
@ -588,11 +573,11 @@ int32_t FMC_Read_64(uint32_t u32addr, uint32_t * u32data0, uint32_t * u32data1)
* *
* @details Read the 64-bits data from the specified OTP. * @details Read the 64-bits data from the specified OTP.
*/ */
int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word) int32_t FMC_Read_OTP(uint32_t u32OtpNum, uint32_t *u32LowWord, uint32_t *u32HighWord)
{ {
int32_t ret = 0; int32_t ret = 0;
if(otp_num > 255UL) if(u32OtpNum > 255UL)
{ {
ret = -2; ret = -2;
} }
@ -600,7 +585,7 @@ int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_READ_64; FMC->ISPCMD = FMC_ISPCMD_READ_64;
FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL ; FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL ;
FMC->ISPDAT = 0x0UL; FMC->ISPDAT = 0x0UL;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
@ -613,8 +598,8 @@ int32_t FMC_Read_OTP(uint32_t otp_num, uint32_t *low_word, uint32_t *high_word)
} }
else else
{ {
*low_word = FMC->MPDAT0; *u32LowWord = FMC->MPDAT0;
*high_word = FMC->MPDAT1; *u32HighWord = FMC->MPDAT1;
} }
} }
return ret; return ret;
@ -728,11 +713,11 @@ int32_t FMC_CompareSPKey(uint32_t key[3])
/** /**
* @brief Setup Security Key. * @brief Setup Security Key.
* *
* @param[in] key Key 0~2 to be setup. * @param[in] au32Key Key 0~2 to be setup.
* @param[in] kpmax Maximum unmatched power-on counting number. * @param[in] u32Kpmax Maximum unmatched power-on counting number.
* @param[in] kemax Maximum unmatched counting number. * @param[in] u32Kemax Maximum unmatched counting number.
* @param[in] lock_CONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG. * @param[in] i32LockCONFIG 1: Security key lock CONFIG to write-protect. 0: Don't lock CONFIG.
* @param[in] lock_SPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. (This param is not supported on M2351) * @param[in] i32LockSPROM 1: Security key lock SPROM to write-protect. 0: Don't lock SPROM. (This param is not supported on M2351)
* *
* @retval 0 Success. * @retval 0 Success.
* @retval -1 Key is locked. Cannot overwrite the current key. * @retval -1 Key is locked. Cannot overwrite the current key.
@ -746,8 +731,8 @@ int32_t FMC_CompareSPKey(uint32_t key[3])
* *
* @details Set secure keys and setup key compare count. The secure key also can protect user config. * @details Set secure keys and setup key compare count. The secure key also can protect user config.
*/ */
int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax, int32_t FMC_SetSPKey(uint32_t au32Key[3], uint32_t u32Kpmax, uint32_t u32Kemax,
const int32_t lock_CONFIG, const int32_t lock_SPROM) const int32_t i32LockCONFIG, const int32_t i32LockSPROM)
{ {
uint32_t lock_ctrl = 0UL; uint32_t lock_ctrl = 0UL;
uint32_t u32KeySts; uint32_t u32KeySts;
@ -768,23 +753,23 @@ int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax,
ret = -3; ret = -3;
} }
if(!lock_CONFIG) if(!i32LockCONFIG)
{ {
lock_ctrl |= 0x1UL; lock_ctrl |= 0x1UL;
} }
if(!lock_SPROM) if(!i32LockSPROM)
{ {
lock_ctrl |= 0x2UL; lock_ctrl |= 0x2UL;
} }
if(ret == 0) if(ret == 0)
{ {
FMC_Write(FMC_KPROM_BASE, key[0]); FMC_Write(FMC_KPROM_BASE, au32Key[0]);
FMC_Write(FMC_KPROM_BASE + 0x4UL, key[1]); FMC_Write(FMC_KPROM_BASE + 0x4UL, au32Key[1]);
FMC_Write(FMC_KPROM_BASE + 0x8UL, key[2]); FMC_Write(FMC_KPROM_BASE + 0x8UL, au32Key[2]);
FMC_Write(FMC_KPROM_BASE + 0xCUL, kpmax); FMC_Write(FMC_KPROM_BASE + 0xCUL, u32Kpmax);
FMC_Write(FMC_KPROM_BASE + 0x10UL, kemax); FMC_Write(FMC_KPROM_BASE + 0x10UL, u32Kemax);
FMC_Write(FMC_KPROM_BASE + 0x14UL, lock_ctrl); FMC_Write(FMC_KPROM_BASE + 0x14UL, lock_ctrl);
while(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { } while(FMC->KPKEYSTS & FMC_KPKEYSTS_KEYBUSY_Msk) { }
@ -796,18 +781,18 @@ int32_t FMC_SetSPKey(uint32_t key[3], uint32_t kpmax, uint32_t kemax,
/* Security key lock failed! */ /* Security key lock failed! */
ret = -4; ret = -4;
} }
else if((lock_CONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) || else if((i32LockCONFIG && (!(u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ||
((!lock_CONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk))) ((!i32LockCONFIG) && (u32KeySts & FMC_KPKEYSTS_CFGFLAG_Msk)))
{ {
/* CONFIG lock failed! */ /* CONFIG lock failed! */
ret = -5; ret = -5;
} }
else if(((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != kpmax) else if(((FMC->KPCNT & FMC_KPCNT_KPMAX_Msk) >> FMC_KPCNT_KPMAX_Pos) != u32Kpmax)
{ {
/* KPMAX failed! */ /* KPMAX failed! */
ret = -7; ret = -7;
} }
else if(((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != kemax) else if(((FMC->KPKEYCNT & FMC_KPKEYCNT_KPKEMAX_Msk) >> FMC_KPKEYCNT_KPKEMAX_Pos) != u32Kemax)
{ {
/* KEMAX failed! */ /* KEMAX failed! */
ret = -8; ret = -8;
@ -872,7 +857,7 @@ int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
/** /**
* @brief Write User Configuration * @brief Write User Configuration
* *
* @param[in] u32Config[] The word buffer to store the User Configuration data. * @param[in] au32Config[] The word buffer to store the User Configuration data.
* @param[in] u32Count The word count to program to User Configuration. * @param[in] u32Count The word count to program to User Configuration.
* *
* @retval 0 Success * @retval 0 Success
@ -883,7 +868,7 @@ int32_t FMC_Write8Bytes(uint32_t u32addr, uint32_t u32data0, uint32_t u32data1)
* User Configuration is also be page erase. User needs to backup necessary data * User Configuration is also be page erase. User needs to backup necessary data
* before erase User Configuration. * before erase User Configuration.
*/ */
int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count) int32_t FMC_WriteConfig(uint32_t au32Config[], uint32_t u32Count)
{ {
int32_t ret = 0; int32_t ret = 0;
uint32_t i; uint32_t i;
@ -891,8 +876,8 @@ int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
FMC_ENABLE_CFG_UPDATE(); FMC_ENABLE_CFG_UPDATE();
for(i = 0u; i < u32Count; i++) for(i = 0u; i < u32Count; i++)
{ {
FMC_Write(FMC_CONFIG_BASE + i * 4u, u32Config[i]); FMC_Write(FMC_CONFIG_BASE + i * 4u, au32Config[i]);
if(FMC_Read(FMC_CONFIG_BASE + i * 4u) != u32Config[i]) if(FMC_Read(FMC_CONFIG_BASE + i * 4u) != au32Config[i])
{ {
ret = -1; ret = -1;
} }
@ -912,14 +897,14 @@ int32_t FMC_WriteConfig(uint32_t u32Config[], uint32_t u32Count)
* @retval >=0 Number of data bytes were programmed. * @retval >=0 Number of data bytes were programmed.
* @return -1 Invalid address. * @return -1 Invalid address.
* *
* @detail Program Multi-Word data into specified address of flash. * @details Program Multi-Word data into specified address of flash.
*/ */
int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len) int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
{ {
uint32_t i, idx, u32OnProg, retval = 0; uint32_t i, idx, u32OnProg;
int32_t err; int32_t err, retval = 0;
if((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0)) if((u32Addr >= FMC_APROM_END) || ((u32Addr % 8) != 0))
{ {
@ -941,7 +926,7 @@ int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
FMC->ISPTRG = 0x1u; FMC->ISPTRG = 0x1u;
idx += 4u; idx += 4u;
for(i = idx; i < (FMC_MULTI_WORD_PROG_LEN / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/ for(i = idx; i < (u32Len / 4u); i += 4u) /* Max data length is 256 bytes (512/4 words)*/
{ {
__set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/ __set_PRIMASK(1u); /* Mask interrupt to avoid status check coherence error*/
do do
@ -1006,9 +991,9 @@ int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
/** /**
* @brief Write data to OTP * @brief Write data to OTP
* *
* @param[in] otp_num The OTP number(0~255). * @param[in] u32OtpNum The OTP number(0~255).
* @param[in] low_word Low word of the 64-bits data. * @param[in] u32LowWord Low word of the 64-bits data.
* @param[in] high_word High word of the 64-bits data. * @param[in] u32HighWord High word of the 64-bits data.
* *
* @retval 0 Success * @retval 0 Success
* @retval -1 Program failed. * @retval -1 Program failed.
@ -1016,11 +1001,11 @@ int32_t FMC_WriteMultiple(uint32_t u32Addr, uint32_t pu32Buf[], uint32_t u32Len)
* *
* @details Program a 64-bits data to the specified OTP. * @details Program a 64-bits data to the specified OTP.
*/ */
int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word) int32_t FMC_Write_OTP(uint32_t u32OtpNum, uint32_t u32LowWord, uint32_t u32HighWord)
{ {
int32_t ret = 0; int32_t ret = 0;
if(otp_num > 255UL) if(u32OtpNum > 255UL)
{ {
ret = -2; ret = -2;
} }
@ -1028,8 +1013,8 @@ int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL; FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL;
FMC->ISPDAT = low_word; FMC->ISPDAT = u32LowWord;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }
@ -1044,8 +1029,8 @@ int32_t FMC_Write_OTP(uint32_t otp_num, uint32_t low_word, uint32_t high_word)
if(ret == 0) if(ret == 0)
{ {
FMC->ISPCMD = FMC_ISPCMD_PROGRAM; FMC->ISPCMD = FMC_ISPCMD_PROGRAM;
FMC->ISPADDR = FMC_OTP_BASE + otp_num * 8UL + 4UL; FMC->ISPADDR = FMC_OTP_BASE + u32OtpNum * 8UL + 4UL;
FMC->ISPDAT = high_word; FMC->ISPDAT = u32HighWord;
FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk; FMC->ISPTRG = FMC_ISPTRG_ISPGO_Msk;
while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { } while(FMC->ISPTRG & FMC_ISPTRG_ISPGO_Msk) { }

28
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_gpio.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_gpio.c
View File

@ -44,13 +44,13 @@
*/ */
void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{ {
uint32_t i; uint32_t u32Idx;
for(i = 0ul; i < GPIO_PIN_MAX; i++) for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
{ {
if((u32PinMask & (1ul << i)) == (1ul << i)) if((u32PinMask & (1ul << u32Idx)) == (1ul << u32Idx))
{ {
port->MODE = (port->MODE & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); port->MODE = (port->MODE & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
} }
} }
} }
@ -80,10 +80,10 @@ void GPIO_SetMode(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs) void GPIO_EnableInt(GPIO_T *port, uint32_t u32Pin, uint32_t u32IntAttribs)
{ {
/* Configure interrupt mode of specified pin */ /* Configure interrupt mode of specified pin */
port->INTTYPE |= (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin); port->INTTYPE = (port->INTTYPE & ~(1ul << u32Pin)) | (((u32IntAttribs >> 24) & 0xFFUL) << u32Pin);
/* Enable interrupt function of specified pin */ /* Enable interrupt function of specified pin */
port->INTEN |= ((u32IntAttribs & 0xFFFFFFUL) << u32Pin); port->INTEN = (port->INTEN & ~(0x00010001ul << u32Pin)) | ((u32IntAttribs & 0xFFFFFFUL) << u32Pin);
} }
@ -136,13 +136,13 @@ void GPIO_DisableInt(GPIO_T *port, uint32_t u32Pin)
*/ */
void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{ {
uint32_t i; uint32_t u32Idx;
for(i = 0ul; i < GPIO_PIN_MAX; i++) for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
{ {
if(u32PinMask & (1ul << i)) if(u32PinMask & (1ul << u32Idx))
{ {
port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); port->SLEWCTL = (port->SLEWCTL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
} }
} }
} }
@ -170,13 +170,13 @@ void GPIO_SetSlewCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
*/ */
void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode) void GPIO_SetPullCtl(GPIO_T *port, uint32_t u32PinMask, uint32_t u32Mode)
{ {
uint32_t i; uint32_t u32Idx;
for(i = 0ul; i < GPIO_PIN_MAX; i++) for(u32Idx = 0ul; u32Idx < GPIO_PIN_MAX; u32Idx++)
{ {
if(u32PinMask & (1ul << i)) if(u32PinMask & (1ul << u32Idx))
{ {
port->PUSEL = (port->PUSEL & ~(0x3ul << (i << 1))) | (u32Mode << (i << 1)); port->PUSEL = (port->PUSEL & ~(0x3ul << (u32Idx << 1))) | (u32Mode << (u32Idx << 1));
} }
} }
} }

150
targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/m2351_i2c.c → targets/TARGET_NUVOTON/TARGET_M2351/device/StdDriver/src/m2351_i2c.c
View File

@ -72,23 +72,25 @@ uint32_t I2C_Open(I2C_T *i2c, uint32_t u32BusClock)
void I2C_Close(I2C_T *i2c) void I2C_Close(I2C_T *i2c)
{ {
/* Reset I2C Controller */ if(!(__PC() & NS_OFFSET))
if(i2c == I2C0)
{ {
SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk; /* Reset I2C Controller */
SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk; if(i2c == I2C0)
{
SYS->IPRST1 |= SYS_IPRST1_I2C0RST_Msk;
SYS->IPRST1 &= ~SYS_IPRST1_I2C0RST_Msk;
}
else if(i2c == I2C1)
{
SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
}
else if(i2c == I2C2)
{
SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;
SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;
}
} }
else if(i2c == I2C1)
{
SYS->IPRST1 |= SYS_IPRST1_I2C1RST_Msk;
SYS->IPRST1 &= ~SYS_IPRST1_I2C1RST_Msk;
}
else if(i2c == I2C2)
{
SYS->IPRST1 |= SYS_IPRST1_I2C2RST_Msk;
SYS->IPRST1 &= ~SYS_IPRST1_I2C2RST_Msk;
}
/* Disable I2C */ /* Disable I2C */
i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk; i2c->CTL0 &= ~I2C_CTL0_I2CEN_Msk;
} }
@ -560,7 +562,7 @@ uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
* @brief Calculate Time-out of SMBus idle period * @brief Calculate Time-out of SMBus idle period
* *
* @param[in] i2c Specify I2C port * @param[in] i2c Specify I2C port
* @param[in] us Time-out length(us) * @param[in] u32Us Time-out length(us)
* @param[in] u32Hclk I2C peripheral clock frequency * @param[in] u32Hclk I2C peripheral clock frequency
* *
* @return None * @return None
@ -569,13 +571,13 @@ uint8_t I2C_SMBusGetPECValue(I2C_T *i2c)
* *
*/ */
void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t us, uint32_t u32Hclk) void I2C_SMBusIdleTimeout(I2C_T *i2c, uint32_t u32Us, uint32_t u32Hclk)
{ {
uint32_t u32Div, u32Hclk_kHz; uint32_t u32Div, u32HclkKHz;
i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk; i2c->BUSCTL |= I2C_BUSCTL_TIDLE_Msk;
u32Hclk_kHz = u32Hclk / 1000U; u32HclkKHz = u32Hclk / 1000U;
u32Div = (((us * u32Hclk_kHz) / 1000U) >> 2U) - 1U; u32Div = (((u32Us * u32HclkKHz) / 1000U) >> 2U) - 1U;
if(u32Div > 255U) if(u32Div > 255U)
{ {
i2c->BUSTOUT = 0xFFU; i2c->BUSTOUT = 0xFFU;
@ -664,7 +666,7 @@ void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
* *
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] data Write a byte data to Slave * @param[in] u8Data Write a byte data to Slave
* *
* @retval 0 Write data success * @retval 0 Write data success
* @retval 1 Write data fail, or bus occurs error events * @retval 1 Write data fail, or bus occurs error events
@ -673,7 +675,7 @@ void I2C_SMBusClockLoTimeout(I2C_T *i2c, uint32_t ms, uint32_t u32Pclk)
* *
*/ */
uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data) uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Data)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
@ -684,11 +686,11 @@ uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
I2C_SET_DATA(i2c, data); /* Write data to I2CDAT */ I2C_SET_DATA(i2c, u8Data); /* Write data to I2CDAT */
break; break;
case 0x20u: /* Slave Address NACK */ case 0x20u: /* Slave Address NACK */
case 0x30u: /* Master transmit data NACK */ case 0x30u: /* Master transmit data NACK */
@ -715,7 +717,7 @@ uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
* *
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] *data Pointer to array to write data to Slave * @param[in] *au8Data Pointer to array to write data to Slave
* @param[in] u32wLen How many bytes need to write to Slave * @param[in] u32wLen How many bytes need to write to Slave
* *
* @return A length of how many bytes have been transmitted. * @return A length of how many bytes have been transmitted.
@ -724,7 +726,7 @@ uint8_t I2C_WriteByte(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data)
* *
*/ */
uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], uint32_t u32wLen) uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Data[], uint32_t u32wLen)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
uint32_t u32txLen = 0u; uint32_t u32txLen = 0u;
@ -736,14 +738,14 @@ uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], ui
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
case 0x28u: case 0x28u:
if(u32txLen < u32wLen) if(u32txLen < u32wLen)
{ {
I2C_SET_DATA(i2c, data[u32txLen++]); /* Write Data to I2CDAT */ I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write Data to I2CDAT */
} }
else else
{ {
@ -773,7 +775,7 @@ uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], ui
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] u8DataAddr Specify a address (1 byte) of data write to * @param[in] u8DataAddr Specify a address (1 byte) of data write to
* @param[in] data A byte data to write it to Slave * @param[in] u8Data A byte data to write it to Slave
* *
* @retval 0 Write data success * @retval 0 Write data success
* @retval 1 Write data fail, or bus occurs error events * @retval 1 Write data fail, or bus occurs error events
@ -782,7 +784,7 @@ uint32_t I2C_WriteMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t data[], ui
* *
*/ */
uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data) uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t u8Data)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
uint32_t u32txLen = 0u; uint32_t u32txLen = 0u;
@ -794,7 +796,7 @@ uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr,
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Send Slave address with write bit */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Send Slave address with write bit */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -808,7 +810,7 @@ uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr,
case 0x28u: case 0x28u:
if(u32txLen < 1u) if(u32txLen < 1u)
{ {
I2C_SET_DATA(i2c, data); I2C_SET_DATA(i2c, u8Data);
u32txLen++; u32txLen++;
} }
else else
@ -835,7 +837,7 @@ uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr,
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] u8DataAddr Specify a address (1 byte) of data write to * @param[in] u8DataAddr Specify a address (1 byte) of data write to
* @param[in] *data Pointer to array to write data to Slave * @param[in] *au8Data Pointer to array to write data to Slave
* @param[in] u32wLen How many bytes need to write to Slave * @param[in] u32wLen How many bytes need to write to Slave
* *
* @return A length of how many bytes have been transmitted. * @return A length of how many bytes have been transmitted.
@ -844,7 +846,7 @@ uint8_t I2C_WriteByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr,
* *
*/ */
uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t data[], uint32_t u32wLen) uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Data[], uint32_t u32wLen)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
uint32_t u32txLen = 0u; uint32_t u32txLen = 0u;
@ -856,7 +858,7 @@ uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Da
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; u8Ctrl = I2C_CTL_SI;
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -870,7 +872,7 @@ uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Da
case 0x28u: case 0x28u:
if(u32txLen < u32wLen) if(u32txLen < u32wLen)
{ {
I2C_SET_DATA(i2c, data[u32txLen++]); I2C_SET_DATA(i2c, au8Data[u32txLen++]);
} }
else else
{ {
@ -896,7 +898,7 @@ uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Da
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] u16DataAddr Specify a address (2 byte) of data write to * @param[in] u16DataAddr Specify a address (2 byte) of data write to
* @param[in] data Write a byte data to Slave * @param[in] u8Data Write a byte data to Slave
* *
* @retval 0 Write data success * @retval 0 Write data success
* @retval 1 Write data fail, or bus occurs error events * @retval 1 Write data fail, or bus occurs error events
@ -905,7 +907,7 @@ uint32_t I2C_WriteMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Da
* *
*/ */
uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data) uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t u8Data)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
uint32_t u32txLen = 0u; uint32_t u32txLen = 0u;
@ -917,7 +919,7 @@ uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAd
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -936,7 +938,7 @@ uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAd
} }
else if((u32txLen < 1u) && (u8Addr == 0u)) else if((u32txLen < 1u) && (u8Addr == 0u))
{ {
I2C_SET_DATA(i2c, data); I2C_SET_DATA(i2c, u8Data);
u32txLen++; u32txLen++;
} }
else else
@ -963,7 +965,7 @@ uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAd
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] u16DataAddr Specify a address (2 bytes) of data write to * @param[in] u16DataAddr Specify a address (2 bytes) of data write to
* @param[in] data[] A data array for write data to Slave * @param[in] au8Data[] A data array for write data to Slave
* @param[in] u32wLen How many bytes need to write to Slave * @param[in] u32wLen How many bytes need to write to Slave
* *
* @return A length of how many bytes have been transmitted. * @return A length of how many bytes have been transmitted.
@ -972,7 +974,7 @@ uint8_t I2C_WriteByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAd
* *
*/ */
uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t data[], uint32_t u32wLen) uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Data[], uint32_t u32wLen)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
uint32_t u32txLen = 0u; uint32_t u32txLen = 0u;
@ -984,7 +986,7 @@ uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u1
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -1003,7 +1005,7 @@ uint32_t I2C_WriteMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u1
} }
else if((u32txLen < u32wLen) && (u8Addr == 0u)) else if((u32txLen < u32wLen) && (u8Addr == 0u))
{ {
I2C_SET_DATA(i2c, data[u32txLen++]); /* Write data to Register I2CDAT*/ I2C_SET_DATA(i2c, au8Data[u32txLen++]); /* Write data to Register I2CDAT*/
} }
else else
{ {
@ -1044,7 +1046,7 @@ uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x40u: /* Slave Address ACK */ case 0x40u: /* Slave Address ACK */
@ -1080,7 +1082,7 @@ uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
* *
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[out] rdata[] A data array to store data from Slave * @param[out] au8Rdata[] A data array to store data from Slave
* @param[in] u32rLen How many bytes need to read from Slave * @param[in] u32rLen How many bytes need to read from Slave
* *
* @return A length of how many bytes have been received * @return A length of how many bytes have been received
@ -1089,7 +1091,7 @@ uint8_t I2C_ReadByte(I2C_T *i2c, uint8_t u8SlaveAddr)
* *
* *
*/ */
uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], uint32_t u32rLen) uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t au8Rdata[], uint32_t u32rLen)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
uint32_t u32rxLen = 0u; uint32_t u32rxLen = 0u;
@ -1101,7 +1103,7 @@ uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], ui
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x40u: /* Slave Address ACK */ case 0x40u: /* Slave Address ACK */
@ -1112,7 +1114,7 @@ uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], ui
u8Err = 1u; u8Err = 1u;
break; break;
case 0x50u: case 0x50u:
rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
if(u32rxLen < (u32rLen - 1u)) if(u32rxLen < (u32rLen - 1u))
{ {
u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
@ -1123,7 +1125,7 @@ uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], ui
} }
break; break;
case 0x58u: case 0x58u:
rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
u8Xfering = 0u; u8Xfering = 0u;
break; break;
@ -1154,7 +1156,7 @@ uint32_t I2C_ReadMultiBytes(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t rdata[], ui
*/ */
uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr) uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Ctrl = 0u;
I2C_START(i2c); /* Send START */ I2C_START(i2c); /* Send START */
while(u8Xfering && (u8Err == 0u)) while(u8Xfering && (u8Err == 0u))
@ -1163,7 +1165,7 @@ uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -1178,7 +1180,7 @@ uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
break; break;
case 0x10u: case 0x10u:
I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x40u: /* Slave Address ACK */ case 0x40u: /* Slave Address ACK */
@ -1189,7 +1191,7 @@ uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
u8Err = 1u; u8Err = 1u;
break; break;
case 0x58u: case 0x58u:
rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ u8Rdata = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
u8Xfering = 0u; u8Xfering = 0u;
break; break;
@ -1203,9 +1205,9 @@ uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
} }
if(u8Err) if(u8Err)
{ {
rdata = 0u; /* If occurs error, return 0 */ u8Rdata = 0u; /* If occurs error, return 0 */
} }
return rdata; /* Return read data */ return u8Rdata; /* Return read data */
} }
/** /**
@ -1214,7 +1216,7 @@ uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] u8DataAddr Specify a address (1 bytes) of data read from * @param[in] u8DataAddr Specify a address (1 bytes) of data read from
* @param[out] rdata[] A data array to store data from Slave * @param[out] au8Rdata[] A data array to store data from Slave
* @param[in] u32rLen How many bytes need to read from Slave * @param[in] u32rLen How many bytes need to read from Slave
* *
* @return A length of how many bytes have been received * @return A length of how many bytes have been received
@ -1223,7 +1225,7 @@ uint8_t I2C_ReadByteOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr)
* *
* *
*/ */
uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t rdata[], uint32_t u32rLen) uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8DataAddr, uint8_t au8Rdata[], uint32_t u32rLen)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Ctrl = 0u;
uint32_t u32rxLen = 0u; uint32_t u32rxLen = 0u;
@ -1235,7 +1237,7 @@ uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Dat
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -1250,7 +1252,7 @@ uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Dat
u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */ u8Ctrl = I2C_CTL_STA_SI; /* Send repeat START */
break; break;
case 0x10u: case 0x10u:
I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x40u: /* Slave Address ACK */ case 0x40u: /* Slave Address ACK */
@ -1261,7 +1263,7 @@ uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Dat
u8Err = 1u; u8Err = 1u;
break; break;
case 0x50u: case 0x50u:
rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
if(u32rxLen < (u32rLen - 1u)) if(u32rxLen < (u32rLen - 1u))
{ {
u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
@ -1272,7 +1274,7 @@ uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Dat
} }
break; break;
case 0x58u: case 0x58u:
rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */ au8Rdata[u32rxLen++] = (uint8_t) I2C_GET_DATA(i2c); /* Receive Data */
u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
u8Xfering = 0u; u8Xfering = 0u;
break; break;
@ -1302,7 +1304,7 @@ uint32_t I2C_ReadMultiBytesOneReg(I2C_T *i2c, uint8_t u8SlaveAddr, uint8_t u8Dat
*/ */
uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr) uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, rdata = 0u, u8Addr = 1u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Rdata = 0u, u8Addr = 1u, u8Ctrl = 0u;
I2C_START(i2c); /* Send START */ I2C_START(i2c); /* Send START */
while(u8Xfering && (u8Err == 0u)) while(u8Xfering && (u8Err == 0u))
@ -1311,7 +1313,7 @@ uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAdd
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -1334,7 +1336,7 @@ uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAdd
} }
break; break;
case 0x10u: case 0x10u:
I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x40u: /* Slave Address ACK */ case 0x40u: /* Slave Address ACK */
@ -1345,7 +1347,7 @@ uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAdd
u8Err = 1u; u8Err = 1u;
break; break;
case 0x58u: case 0x58u:
rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ u8Rdata = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
u8Xfering = 0u; u8Xfering = 0u;
break; break;
@ -1359,9 +1361,9 @@ uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAdd
} }
if(u8Err) if(u8Err)
{ {
rdata = 0u; /* If occurs error, return 0 */ u8Rdata = 0u; /* If occurs error, return 0 */
} }
return rdata; /* Return read data */ return u8Rdata; /* Return read data */
} }
/** /**
@ -1370,7 +1372,7 @@ uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAdd
* @param[in] *i2c Point to I2C peripheral * @param[in] *i2c Point to I2C peripheral
* @param[in] u8SlaveAddr Access Slave address(7-bit) * @param[in] u8SlaveAddr Access Slave address(7-bit)
* @param[in] u16DataAddr Specify a address (2 bytes) of data read from * @param[in] u16DataAddr Specify a address (2 bytes) of data read from
* @param[out] rdata[] A data array to store data from Slave * @param[out] au8Rdata[] A data array to store data from Slave
* @param[in] u32rLen How many bytes need to read from Slave * @param[in] u32rLen How many bytes need to read from Slave
* *
* @return A length of how many bytes have been received * @return A length of how many bytes have been received
@ -1379,7 +1381,7 @@ uint8_t I2C_ReadByteTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAdd
* *
* *
*/ */
uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t rdata[], uint32_t u32rLen) uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16DataAddr, uint8_t au8Rdata[], uint32_t u32rLen)
{ {
uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u; uint8_t u8Xfering = 1u, u8Err = 0u, u8Addr = 1u, u8Ctrl = 0u;
uint32_t u32rxLen = 0u; uint32_t u32rxLen = 0u;
@ -1391,7 +1393,7 @@ uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16
switch(I2C_GET_STATUS(i2c)) switch(I2C_GET_STATUS(i2c))
{ {
case 0x08u: case 0x08u:
I2C_SET_DATA(i2c, (uint8_t)(u8SlaveAddr << 1u | 0x00u)); /* Write SLA+W to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x00u)); /* Write SLA+W to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x18u: /* Slave Address ACK */ case 0x18u: /* Slave Address ACK */
@ -1414,7 +1416,7 @@ uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16
} }
break; break;
case 0x10u: case 0x10u:
I2C_SET_DATA(i2c, (uint8_t)((u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */ I2C_SET_DATA(i2c, ((uint8_t)(u8SlaveAddr << 1u) | 0x01u)); /* Write SLA+R to Register I2CDAT */
u8Ctrl = I2C_CTL_SI; /* Clear SI */ u8Ctrl = I2C_CTL_SI; /* Clear SI */
break; break;
case 0x40u: /* Slave Address ACK */ case 0x40u: /* Slave Address ACK */
@ -1425,7 +1427,7 @@ uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16
u8Err = 1u; u8Err = 1u;
break; break;
case 0x50u: case 0x50u:
rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
if(u32rxLen < (u32rLen - 1u)) if(u32rxLen < (u32rLen - 1u))
{ {
u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */ u8Ctrl = I2C_CTL_SI_AA; /* Clear SI and set ACK */
@ -1436,7 +1438,7 @@ uint32_t I2C_ReadMultiBytesTwoRegs(I2C_T *i2c, uint8_t u8SlaveAddr, uint16_t u16
} }
break; break;
case 0x58u: case 0x58u:
rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */ au8Rdata[u32rxLen++] = (unsigned char) I2C_GET_DATA(i2c); /* Receive Data */
u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */ u8Ctrl = I2C_CTL_STO_SI; /* Clear SI and send STOP */
u8Xfering = 0u; u8Xfering = 0u;
break; break;

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