mirror of https://github.com/ARMmbed/mbed-os.git
Update CMSDK_CM3DS.h
This patch updates CMSDK_CM3DS.h to remove the DMA peripheral memory map and defines, as that peripheral is not present in the system. In addition, some define names where updated concerning rtc. RTC_api was updated accordingly. This patch also updates SMM_MPS2 to align defines and comments. Signed-off-by: Marc Moreno <marc.morenoberengue@arm.com>pull/4557/head
Marc Moreno Berengue
parent
fabfc85d31
commit
8de4c5323f
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@ -93,8 +93,8 @@ typedef enum IRQn
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MPS2_SPI0_IRQn = 49, /* SPI Interrupt (spi header) */
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MPS2_SPI1_IRQn = 50, /* SPI Interrupt (clcd) */
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MPS2_SPI2_IRQn = 51, /* SPI Interrupt (spi 1 ADC replacement) */
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MPS2_SPI3_IRQn = 52, /* SPI Interrupt (spi 0 shield 0 replacement) */
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MPS2_SPI4_IRQn = 53, /* SPI Interrupt (shield 1) */
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MPS2_SPI3_IRQn = 52, /* SPI Interrupt (shield 0) */
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MPS2_SPI4_IRQn = 53, /* SPI Interrupt (shield 1) */
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PORT4_ALL_IRQn = 54, /* GPIO Port 4 combined Interrupt */
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PORT5_ALL_IRQn = 55, /* GPIO Port 5 combined Interrupt */
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UART4_IRQn = 56 /* UART 4 RX and TX Combined Interrupt */
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@ -635,104 +635,7 @@ typedef struct
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#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos 2
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#define CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Msk (0x00001ul << CMSDK_SYSCON_RSTINFO_LOCKUPRESET_Pos) /* CMSDK_SYSCON RSTINFO: LOCKUPRESET Mask */
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/*------------- PL230 uDMA (PL230) --------------------------------------*/
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typedef struct
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{
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__I uint32_t DMA_STATUS; /* Offset: 0x000 (R/W) DMA status Register */
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__O uint32_t DMA_CFG; /* Offset: 0x004 ( /W) DMA configuration Register */
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__IO uint32_t CTRL_BASE_PTR; /* Offset: 0x008 (R/W) Channel Control Data Base Pointer Register */
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__I uint32_t ALT_CTRL_BASE_PTR; /* Offset: 0x00C (R/ ) Channel Alternate Control Data Base Pointer Register */
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__I uint32_t DMA_WAITONREQ_STATUS; /* Offset: 0x010 (R/ ) Channel Wait On Request Status Register */
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__O uint32_t CHNL_SW_REQUEST; /* Offset: 0x014 ( /W) Channel Software Request Register */
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__IO uint32_t CHNL_USEBURST_SET; /* Offset: 0x018 (R/W) Channel UseBurst Set Register */
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__O uint32_t CHNL_USEBURST_CLR; /* Offset: 0x01C ( /W) Channel UseBurst Clear Register */
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__IO uint32_t CHNL_REQ_MASK_SET; /* Offset: 0x020 (R/W) Channel Request Mask Set Register */
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__O uint32_t CHNL_REQ_MASK_CLR; /* Offset: 0x024 ( /W) Channel Request Mask Clear Register */
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__IO uint32_t CHNL_ENABLE_SET; /* Offset: 0x028 (R/W) Channel Enable Set Register */
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__O uint32_t CHNL_ENABLE_CLR; /* Offset: 0x02C ( /W) Channel Enable Clear Register */
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__IO uint32_t CHNL_PRI_ALT_SET; /* Offset: 0x030 (R/W) Channel Primary-Alterante Set Register */
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__O uint32_t CHNL_PRI_ALT_CLR; /* Offset: 0x034 ( /W) Channel Primary-Alterante Clear Register */
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__IO uint32_t CHNL_PRIORITY_SET; /* Offset: 0x038 (R/W) Channel Priority Set Register */
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__O uint32_t CHNL_PRIORITY_CLR; /* Offset: 0x03C ( /W) Channel Priority Clear Register */
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uint32_t RESERVED0[3];
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__IO uint32_t ERR_CLR; /* Offset: 0x04C Bus Error Clear Register (R/W) */
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} CMSDK_PL230_TypeDef;
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#define PL230_DMA_CHNL_BITS 0
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#define CMSDK_PL230_DMA_STATUS_MSTREN_Pos 0 /* CMSDK_PL230 DMA STATUS: MSTREN Position */
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#define CMSDK_PL230_DMA_STATUS_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_MSTREN_Pos) /* CMSDK_PL230 DMA STATUS: MSTREN Mask */
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#define CMSDK_PL230_DMA_STATUS_STATE_Pos 0 /* CMSDK_PL230 DMA STATUS: STATE Position */
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#define CMSDK_PL230_DMA_STATUS_STATE_Msk (0x0000000Ful << CMSDK_PL230_DMA_STATUS_STATE_Pos) /* CMSDK_PL230 DMA STATUS: STATE Mask */
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#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos 0 /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Position */
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#define CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Msk (0x0000001Ful << CMSDK_PL230_DMA_STATUS_CHNLS_MINUS1_Pos) /* CMSDK_PL230 DMA STATUS: CHNLS_MINUS1 Mask */
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#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos 0 /* CMSDK_PL230 DMA STATUS: TEST_STATUS Position */
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#define CMSDK_PL230_DMA_STATUS_TEST_STATUS_Msk (0x00000001ul << CMSDK_PL230_DMA_STATUS_TEST_STATUS_Pos) /* CMSDK_PL230 DMA STATUS: TEST_STATUS Mask */
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#define CMSDK_PL230_DMA_CFG_MSTREN_Pos 0 /* CMSDK_PL230 DMA CFG: MSTREN Position */
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#define CMSDK_PL230_DMA_CFG_MSTREN_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_MSTREN_Pos) /* CMSDK_PL230 DMA CFG: MSTREN Mask */
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#define CMSDK_PL230_DMA_CFG_CPCCACHE_Pos 2 /* CMSDK_PL230 DMA CFG: CPCCACHE Position */
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#define CMSDK_PL230_DMA_CFG_CPCCACHE_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCCACHE_Pos) /* CMSDK_PL230 DMA CFG: CPCCACHE Mask */
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#define CMSDK_PL230_DMA_CFG_CPCBUF_Pos 1 /* CMSDK_PL230 DMA CFG: CPCBUF Position */
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#define CMSDK_PL230_DMA_CFG_CPCBUF_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCBUF_Pos) /* CMSDK_PL230 DMA CFG: CPCBUF Mask */
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#define CMSDK_PL230_DMA_CFG_CPCPRIV_Pos 0 /* CMSDK_PL230 DMA CFG: CPCPRIV Position */
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#define CMSDK_PL230_DMA_CFG_CPCPRIV_Msk (0x00000001ul << CMSDK_PL230_DMA_CFG_CPCPRIV_Pos) /* CMSDK_PL230 DMA CFG: CPCPRIV Mask */
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#define CMSDK_PL230_CTRL_BASE_PTR_Pos PL230_DMA_CHNL_BITS + 5 /* CMSDK_PL230 STATUS: BASE_PTR Position */
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#define CMSDK_PL230_CTRL_BASE_PTR_Msk (0x0FFFFFFFul << CMSDK_PL230_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: BASE_PTR Mask */
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#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos 0 /* CMSDK_PL230 STATUS: MSTREN Position */
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#define CMSDK_PL230_ALT_CTRL_BASE_PTR_Msk (0xFFFFFFFFul << CMSDK_PL230_ALT_CTRL_BASE_PTR_Pos) /* CMSDK_PL230 STATUS: MSTREN Mask */
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#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos 0 /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Position */
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#define CMSDK_PL230_DMA_WAITONREQ_STATUS_Msk (0xFFFFFFFFul << CMSDK_PL230_DMA_WAITONREQ_STATUS_Pos) /* CMSDK_PL230 DMA_WAITONREQ_STATUS: DMA_WAITONREQ_STATUS Mask */
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#define CMSDK_PL230_CHNL_SW_REQUEST_Pos 0 /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Position */
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#define CMSDK_PL230_CHNL_SW_REQUEST_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_SW_REQUEST_Pos) /* CMSDK_PL230 CHNL_SW_REQUEST: CHNL_SW_REQUEST Mask */
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#define CMSDK_PL230_CHNL_USEBURST_SET_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: SET Position */
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#define CMSDK_PL230_CHNL_USEBURST_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_SET_Pos) /* CMSDK_PL230 CHNL_USEBURST: SET Mask */
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#define CMSDK_PL230_CHNL_USEBURST_CLR_Pos 0 /* CMSDK_PL230 CHNL_USEBURST: CLR Position */
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#define CMSDK_PL230_CHNL_USEBURST_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_USEBURST_CLR_Pos) /* CMSDK_PL230 CHNL_USEBURST: CLR Mask */
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#define CMSDK_PL230_CHNL_REQ_MASK_SET_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: SET Position */
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#define CMSDK_PL230_CHNL_REQ_MASK_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_SET_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: SET Mask */
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#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos 0 /* CMSDK_PL230 CHNL_REQ_MASK: CLR Position */
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#define CMSDK_PL230_CHNL_REQ_MASK_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_REQ_MASK_CLR_Pos) /* CMSDK_PL230 CHNL_REQ_MASK: CLR Mask */
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#define CMSDK_PL230_CHNL_ENABLE_SET_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: SET Position */
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#define CMSDK_PL230_CHNL_ENABLE_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_SET_Pos) /* CMSDK_PL230 CHNL_ENABLE: SET Mask */
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#define CMSDK_PL230_CHNL_ENABLE_CLR_Pos 0 /* CMSDK_PL230 CHNL_ENABLE: CLR Position */
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#define CMSDK_PL230_CHNL_ENABLE_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_ENABLE_CLR_Pos) /* CMSDK_PL230 CHNL_ENABLE: CLR Mask */
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#define CMSDK_PL230_CHNL_PRI_ALT_SET_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: SET Position */
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#define CMSDK_PL230_CHNL_PRI_ALT_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_SET_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: SET Mask */
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#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRI_ALT: CLR Position */
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#define CMSDK_PL230_CHNL_PRI_ALT_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRI_ALT_CLR_Pos) /* CMSDK_PL230 CHNL_PRI_ALT: CLR Mask */
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#define CMSDK_PL230_CHNL_PRIORITY_SET_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: SET Position */
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#define CMSDK_PL230_CHNL_PRIORITY_SET_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_SET_Pos) /* CMSDK_PL230 CHNL_PRIORITY: SET Mask */
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#define CMSDK_PL230_CHNL_PRIORITY_CLR_Pos 0 /* CMSDK_PL230 CHNL_PRIORITY: CLR Position */
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#define CMSDK_PL230_CHNL_PRIORITY_CLR_Msk (0xFFFFFFFFul << CMSDK_PL230_CHNL_PRIORITY_CLR_Pos) /* CMSDK_PL230 CHNL_PRIORITY: CLR Mask */
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#define CMSDK_PL230_ERR_CLR_Pos 0 /* CMSDK_PL230 ERR: CLR Position */
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#define CMSDK_PL230_ERR_CLR_Msk (0x00000001ul << CMSDK_PL230_ERR_CLR_Pos) /* CMSDK_PL230 ERR: CLR Mask */
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/*------------------- Watchdog ----------------------------------------------*/
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/*------------------- WATCHDOG ----------------------------------------------*/
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typedef struct
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{
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@ -749,35 +652,35 @@ typedef struct
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__O uint32_t ITOP; /* Offset: 0xF04 ( /W) Watchdog Integration Test Output Set Register */
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}CMSDK_WATCHDOG_TypeDef;
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#define CMSDK_Watchdog_LOAD_Pos 0 /* CMSDK_Watchdog LOAD: LOAD Position */
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#define CMSDK_Watchdog_LOAD_Msk (0xFFFFFFFFul << CMSDK_Watchdog_LOAD_Pos) /* CMSDK_Watchdog LOAD: LOAD Mask */
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#define CMSDK_WATCHDOG_LOAD_Pos 0 /* CMSDK_WATCHDOG LOAD: LOAD Position */
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#define CMSDK_WATCHDOG_LOAD_Msk (0xFFFFFFFFul << CMSDK_WATCHDOG_LOAD_Pos) /* CMSDK_WATCHDOG LOAD: LOAD Mask */
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#define CMSDK_Watchdog_VALUE_Pos 0 /* CMSDK_Watchdog VALUE: VALUE Position */
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#define CMSDK_Watchdog_VALUE_Msk (0xFFFFFFFFul << CMSDK_Watchdog_VALUE_Pos) /* CMSDK_Watchdog VALUE: VALUE Mask */
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#define CMSDK_WATCHDOG_VALUE_Pos 0 /* CMSDK_WATCHDOG VALUE: VALUE Position */
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#define CMSDK_WATCHDOG_VALUE_Msk (0xFFFFFFFFul << CMSDK_WATCHDOG_VALUE_Pos) /* CMSDK_WATCHDOG VALUE: VALUE Mask */
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#define CMSDK_Watchdog_CTRL_RESEN_Pos 1 /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Position */
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#define CMSDK_Watchdog_CTRL_RESEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_RESEN_Pos) /* CMSDK_Watchdog CTRL_RESEN: Enable Reset Output Mask */
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#define CMSDK_WATCHDOG_CTRL_RESEN_Pos 1 /* CMSDK_WATCHDOG CTRL_RESEN: Enable Reset Output Position */
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#define CMSDK_WATCHDOG_CTRL_RESEN_Msk (0x1ul << CMSDK_WATCHDOG_CTRL_RESEN_Pos) /* CMSDK_WATCHDOG CTRL_RESEN: Enable Reset Output Mask */
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#define CMSDK_Watchdog_CTRL_INTEN_Pos 0 /* CMSDK_Watchdog CTRL_INTEN: Int Enable Position */
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#define CMSDK_Watchdog_CTRL_INTEN_Msk (0x1ul << CMSDK_Watchdog_CTRL_INTEN_Pos) /* CMSDK_Watchdog CTRL_INTEN: Int Enable Mask */
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#define CMSDK_WATCHDOG_CTRL_INTEN_Pos 0 /* CMSDK_WATCHDOG CTRL_INTEN: Int Enable Position */
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#define CMSDK_WATCHDOG_CTRL_INTEN_Msk (0x1ul << CMSDK_WATCHDOG_CTRL_INTEN_Pos) /* CMSDK_WATCHDOG CTRL_INTEN: Int Enable Mask */
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#define CMSDK_Watchdog_INTCLR_Pos 0 /* CMSDK_Watchdog INTCLR: Int Clear Position */
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#define CMSDK_Watchdog_INTCLR_Msk (0x1ul << CMSDK_Watchdog_INTCLR_Pos) /* CMSDK_Watchdog INTCLR: Int Clear Mask */
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#define CMSDK_WATCHDOG_INTCLR_Pos 0 /* CMSDK_WATCHDOG INTCLR: Int Clear Position */
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#define CMSDK_WATCHDOG_INTCLR_Msk (0x1ul << CMSDK_WATCHDOG_INTCLR_Pos) /* CMSDK_WATCHDOG INTCLR: Int Clear Mask */
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#define CMSDK_Watchdog_RAWINTSTAT_Pos 0 /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Position */
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#define CMSDK_Watchdog_RAWINTSTAT_Msk (0x1ul << CMSDK_Watchdog_RAWINTSTAT_Pos) /* CMSDK_Watchdog RAWINTSTAT: Raw Int Status Mask */
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#define CMSDK_WATCHDOG_RAWINTSTAT_Pos 0 /* CMSDK_WATCHDOG RAWINTSTAT: Raw Int Status Position */
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#define CMSDK_WATCHDOG_RAWINTSTAT_Msk (0x1ul << CMSDK_WATCHDOG_RAWINTSTAT_Pos) /* CMSDK_WATCHDOG RAWINTSTAT: Raw Int Status Mask */
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#define CMSDK_Watchdog_MASKINTSTAT_Pos 0 /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Position */
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#define CMSDK_Watchdog_MASKINTSTAT_Msk (0x1ul << CMSDK_Watchdog_MASKINTSTAT_Pos) /* CMSDK_Watchdog MASKINTSTAT: Mask Int Status Mask */
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#define CMSDK_WATCHDOG_MASKINTSTAT_Pos 0 /* CMSDK_WATCHDOG MASKINTSTAT: Mask Int Status Position */
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#define CMSDK_WATCHDOG_MASKINTSTAT_Msk (0x1ul << CMSDK_WATCHDOG_MASKINTSTAT_Pos) /* CMSDK_WATCHDOG MASKINTSTAT: Mask Int Status Mask */
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#define CMSDK_Watchdog_LOCK_Pos 0 /* CMSDK_Watchdog LOCK: LOCK Position */
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#define CMSDK_Watchdog_LOCK_Msk (0x1ul << CMSDK_Watchdog_LOCK_Pos) /* CMSDK_Watchdog LOCK: LOCK Mask */
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#define CMSDK_WATCHDOG_LOCK_Pos 0 /* CMSDK_WATCHDOG LOCK: LOCK Position */
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#define CMSDK_WATCHDOG_LOCK_Msk (0x1ul << CMSDK_WATCHDOG_LOCK_Pos) /* CMSDK_WATCHDOG LOCK: LOCK Mask */
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#define CMSDK_Watchdog_INTEGTESTEN_Pos 0 /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Position */
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#define CMSDK_Watchdog_INTEGTESTEN_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTEN_Pos) /* CMSDK_Watchdog INTEGTESTEN: Integration Test Enable Mask */
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#define CMSDK_WATCHDOG_INTEGTESTEN_Pos 0 /* CMSDK_WATCHDOG INTEGTESTEN: Integration Test Enable Position */
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#define CMSDK_WATCHDOG_INTEGTESTEN_Msk (0x1ul << CMSDK_WATCHDOG_INTEGTESTEN_Pos) /* CMSDK_WATCHDOG INTEGTESTEN: Integration Test Enable Mask */
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#define CMSDK_Watchdog_INTEGTESTOUTSET_Pos 1 /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Position */
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#define CMSDK_Watchdog_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_Watchdog_INTEGTESTOUTSET_Pos) /* CMSDK_Watchdog INTEGTESTOUTSET: Integration Test Output Set Mask */
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#define CMSDK_WATCHDOG_INTEGTESTOUTSET_Pos 1 /* CMSDK_WATCHDOG INTEGTESTOUTSET: Integration Test Output Set Position */
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#define CMSDK_WATCHDOG_INTEGTESTOUTSET_Msk (0x1ul << CMSDK_WATCHDOG_INTEGTESTOUTSET_Pos) /* CMSDK_WATCHDOG INTEGTESTOUTSET: Integration Test Output Set Mask */
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/*------------------------- Real Time Clock(RTC) ----------------------------------------------*/
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typedef struct
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__O uint32_t RTCICR; /* 0x1C WO RTC Interrupt Clear Register */
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} CMSDK_RTC_TypeDef;
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#define CMSDK_RTC_Enable_Pos 0 /* CMSDK_RTC Enable: Real Time Clock Enable Position */
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#define CMSDK_RTC_Enable_Msk (0x1ul << CMSDK_RTC_Enable_Pos) /* CMSDK_RTC Enable: Real Time Clock Enable Mask */
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#define CMSDK_RTC_ENABLE_Pos 0 /* CMSDK_RTC Enable: Real Time Clock Enable Position */
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#define CMSDK_RTC_ENABLE_Msk (0x1ul << CMSDK_RTC_ENABLE_Pos) /* CMSDK_RTC Enable: Real Time Clock Enable Mask */
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/* -------------------- End of section using anonymous unions ------------------- */
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#if defined ( __CC_ARM )
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@ -810,9 +713,6 @@ typedef struct
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#warning Not supported compiler type
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#endif
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/* ================================================================================ */
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/* ================ Peripheral memory map ================ */
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/* ================================================================================ */
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/* ================ Peripheral declaration ================ */
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/* ================================================================================ */
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#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
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#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
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#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
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#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
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#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
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#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
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#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
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#define CMSDK_UART0 ((CMSDK_UART_TypeDef *) CMSDK_UART0_BASE )
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#define CMSDK_UART1 ((CMSDK_UART_TypeDef *) CMSDK_UART1_BASE )
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#define CMSDK_UART2 ((CMSDK_UART_TypeDef *) CMSDK_UART2_BASE )
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#define CMSDK_UART3 ((CMSDK_UART_TypeDef *) CMSDK_UART3_BASE )
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#define CMSDK_UART4 ((CMSDK_UART_TypeDef *) CMSDK_UART4_BASE )
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#define CMSDK_TIMER0 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER0_BASE )
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#define CMSDK_TIMER1 ((CMSDK_TIMER_TypeDef *) CMSDK_TIMER1_BASE )
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#define CMSDK_DUALTIMER ((CMSDK_DUALTIMER_BOTH_TypeDef *) CMSDK_DUALTIMER_BASE )
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#define CMSDK_DUALTIMER1 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_1_BASE )
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#define CMSDK_DUALTIMER2 ((CMSDK_DUALTIMER_SINGLE_TypeDef *) CMSDK_DUALTIMER_2_BASE )
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#define CMSDK_RTC ((CMSDK_RTC_TypeDef *) CMSDK_RTC_BASE )
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#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
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#define CMSDK_DMA ((CMSDK_PL230_TypeDef *) CMSDK_PL230_BASE )
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#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
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#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
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#define CMSDK_WATCHDOG ((CMSDK_WATCHDOG_TypeDef *) CMSDK_WATCHDOG_BASE )
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#define CMSDK_GPIO0 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO0_BASE )
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#define CMSDK_GPIO1 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO1_BASE )
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#define CMSDK_GPIO2 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO2_BASE )
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#define CMSDK_GPIO3 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO3_BASE )
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#define CMSDK_GPIO4 ((CMSDK_GPIO_TypeDef *) CMSDK_GPIO4_BASE )
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@ -547,20 +547,20 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
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/* Peripheral memory map */
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/******************************************************************************/
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#define MPS2_SSP0_BASE (0x40020000ul) /* User SSP Base Address */
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#define MPS2_SSP1_BASE (0x40021000ul) /* CLCD SSP Base Address */
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#define MPS2_SSP0_BASE (0x40020000ul) /* User SSP Base Address */
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#define MPS2_SSP1_BASE (0x40021000ul) /* CLCD SSP Base Address */
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#define MPS2_TSC_I2C_BASE (0x40022000ul) /* Touch Screen I2C Base Address */
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#define MPS2_AAIC_I2C_BASE (0x40023000ul) /* Audio Interface I2C Base Address */
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#define MPS2_AAIC_I2S_BASE (0x40024000ul) /* Audio Interface I2S Base Address */
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#define MPS2_SSP2_BASE (0x40025000ul) /* adc SSP Base Address */
|
||||
#define MPS2_SSP3_BASE (0x40026000ul) /* shield 0 SSP Base Address */
|
||||
#define MPS2_SSP4_BASE (0x40027000ul) /* shield 1 SSP Base Address */
|
||||
#define MPS2_SSP2_BASE (0x40025000ul) /* ADC SSP Base Address */
|
||||
#define MPS2_SSP3_BASE (0x40026000ul) /* Shield 0 SSP Base Address */
|
||||
#define MPS2_SSP4_BASE (0x40027000ul) /* Shield 1 SSP Base Address */
|
||||
#define MPS2_FPGAIO_BASE (0x40028000ul) /* FPGAIO Base Address */
|
||||
#define MPS2_SHIELD0_I2C_BASE (0x40029000ul) /* I2C shield 0 Base Address */
|
||||
#define MPS2_SHIELD1_I2C_BASE (0x4002A000ul) /* I2C shield 1 Base Address */
|
||||
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
|
||||
#define MPS2_SCC_BASE (0x4002F000ul) /* SCC Base Address */
|
||||
|
||||
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
|
||||
#define SMSC9220_BASE (0x40200000ul) /* Ethernet SMSC9220 Base Address */
|
||||
|
||||
#define MPS2_VGA_TEXT_BUFFER (0x41000000ul) /* VGA Text Buffer Address */
|
||||
#define MPS2_VGA_BUFFER (0x41100000ul) /* VGA Buffer Base Address */
|
||||
|
|
@ -569,19 +569,19 @@ __IO uint32_t E2P_DATA; // EEPROM Data (offset 0xB4)
|
|||
/* Peripheral declaration */
|
||||
/******************************************************************************/
|
||||
|
||||
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
|
||||
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
|
||||
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
|
||||
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
|
||||
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
|
||||
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
|
||||
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
|
||||
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
|
||||
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
|
||||
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
|
||||
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
|
||||
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
|
||||
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
|
||||
#define SMSC9220 ((SMSC9220_TypeDef *) SMSC9220_BASE )
|
||||
#define MPS2_TS_I2C ((MPS2_I2C_TypeDef *) MPS2_TSC_I2C_BASE )
|
||||
#define MPS2_AAIC_I2C ((MPS2_I2C_TypeDef *) MPS2_AAIC_I2C_BASE )
|
||||
#define MPS2_SHIELD0_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD0_I2C_BASE )
|
||||
#define MPS2_SHIELD1_I2C ((MPS2_I2C_TypeDef *) MPS2_SHIELD1_I2C_BASE )
|
||||
#define MPS2_AAIC_I2S ((MPS2_I2S_TypeDef *) MPS2_AAIC_I2S_BASE )
|
||||
#define MPS2_FPGAIO ((MPS2_FPGAIO_TypeDef *) MPS2_FPGAIO_BASE )
|
||||
#define MPS2_SCC ((MPS2_SCC_TypeDef *) MPS2_SCC_BASE )
|
||||
#define MPS2_SSP0 ((MPS2_SSP_TypeDef *) MPS2_SSP0_BASE )
|
||||
#define MPS2_SSP1 ((MPS2_SSP_TypeDef *) MPS2_SSP1_BASE )
|
||||
#define MPS2_SSP2 ((MPS2_SSP_TypeDef *) MPS2_SSP2_BASE )
|
||||
#define MPS2_SSP3 ((MPS2_SSP_TypeDef *) MPS2_SSP3_BASE )
|
||||
#define MPS2_SSP4 ((MPS2_SSP_TypeDef *) MPS2_SSP4_BASE )
|
||||
|
||||
/******************************************************************************/
|
||||
/* General Function Definitions */
|
||||
|
|
|
|||
|
|
@ -31,7 +31,7 @@
|
|||
*/
|
||||
void rtc_init(void)
|
||||
{
|
||||
CMSDK_RTC->RTCCR |= (1 << CMSDK_RTC_Enable_Pos);
|
||||
CMSDK_RTC->RTCCR |= (1 << CMSDK_RTC_ENABLE_Pos);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
@ -51,7 +51,7 @@ void rtc_free(void)
|
|||
*/
|
||||
int rtc_isenabled(void)
|
||||
{
|
||||
return (CMSDK_RTC->RTCCR & CMSDK_RTC_Enable_Msk);
|
||||
return (CMSDK_RTC->RTCCR & CMSDK_RTC_ENABLE_Msk);
|
||||
}
|
||||
|
||||
/**
|
||||
|
|
|
|||
Loading…
Reference in New Issue