mirror of https://github.com/ARMmbed/mbed-os.git
Cruz Monrreal
GitHub
commit
8d014bcce6
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# Example RF driver for STM 802.15.4 transceivers #
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Support for:
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* S2-LP
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This driver is used with 6LoWPAN and Wi-SUN stacks.
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{
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"name": "s2lp",
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"config": {
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"provide-default": {
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"help": "Provide default NanostackRfpy. [true/false]",
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"value": false
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
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/*
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* Copyright (c) 2018 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "ns_types.h"
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#include "rf_configuration.h"
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#include "mbed_trace.h"
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#define TRACE_GROUP "rfcf"
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// Note that F_XO and F_DIG depends on the used clock frequency
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#define F_XO 50000000
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#define F_DIG 25000000
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// Note that reference divider depends on REFDIV field in XO_RCO_CONF0 register
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#define REF_DIVIDER 1
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// Note that band selector depends on BS field in SYNT3 register
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#define BAND_SELECTOR 4
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#define DEF_2EXP33 8589934592
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#define DEF_2EXP20 1048576
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#define DEF_2EXP19 524288
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#define DEF_2EXP16 65536
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#define DEF_2EXP15 32768
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// Use multiplier for better resolution
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#define RESOLUTION_MULTIPLIER 1000000
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void rf_conf_calculate_datarate_registers(uint32_t datarate, uint16_t *datarate_mantissa, uint8_t *datarate_exponent)
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{
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uint64_t datarate_m = (uint64_t)datarate * DEF_2EXP33;
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uint8_t datarate_e = 1;
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while (datarate_m >= DEF_2EXP16) {
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datarate_e++;
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uint16_t var_2exp_datarate_e = (uint32_t)2 << (datarate_e - 1);
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datarate_m = (uint64_t)datarate * DEF_2EXP33;
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datarate_m = datarate_m / ((uint64_t)var_2exp_datarate_e * F_DIG);
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datarate_m -= DEF_2EXP16;
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}
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*datarate_mantissa = datarate_m;
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*datarate_exponent = datarate_e;
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}
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void rf_conf_calculate_base_frequency_registers(uint32_t frequency, uint8_t *synt3, uint8_t *synt2, uint8_t *synt1, uint8_t *synt0)
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{
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uint64_t freq_tmp = (uint64_t)frequency * RESOLUTION_MULTIPLIER;
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freq_tmp = (freq_tmp / (F_XO / ((BAND_SELECTOR / 2) * REF_DIVIDER)));
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freq_tmp *= DEF_2EXP20;
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freq_tmp /= RESOLUTION_MULTIPLIER;
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*synt3 = (uint8_t)(freq_tmp >> 24);
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*synt2 = (uint8_t)(freq_tmp >> 16);
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*synt1 = (uint8_t)(freq_tmp >> 8);
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*synt0 = (uint8_t)freq_tmp;
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}
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void rf_conf_calculate_deviation_registers(uint32_t deviation, uint8_t *fdev_m, uint8_t *fdev_e)
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{
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uint64_t fdev_m_tmp = 0xffff;
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uint8_t fdev_e_tmp = 1;
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while (fdev_m_tmp > 255) {
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fdev_e_tmp++;
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uint16_t var_2exp_datarate_e_minus_1 = (uint16_t)2 << ((fdev_e_tmp - 1) - 1);
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fdev_m_tmp = (uint64_t)deviation * RESOLUTION_MULTIPLIER;
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fdev_m_tmp = (((fdev_m_tmp / F_XO) * DEF_2EXP19 * BAND_SELECTOR * REF_DIVIDER * (8 / BAND_SELECTOR)) / var_2exp_datarate_e_minus_1);
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fdev_m_tmp += RESOLUTION_MULTIPLIER / 2;
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fdev_m_tmp /= RESOLUTION_MULTIPLIER;
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fdev_m_tmp -= 256;
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}
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*fdev_m = (uint8_t)fdev_m_tmp;
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*fdev_e = fdev_e_tmp;
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}
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int rf_conf_calculate_channel_spacing_registers(uint32_t channel_spacing, uint8_t *ch_space)
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{
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uint64_t ch_space_tmp = (uint64_t)channel_spacing * RESOLUTION_MULTIPLIER;
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ch_space_tmp /= F_XO;
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ch_space_tmp *= DEF_2EXP15;
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ch_space_tmp += RESOLUTION_MULTIPLIER / 2;
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ch_space_tmp /= RESOLUTION_MULTIPLIER;
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// Check if channel spacing is too high
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if (ch_space_tmp > 255) {
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return -1;
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}
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*ch_space = (uint8_t)ch_space_tmp;
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return 0;
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}
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/* Note: This function doesn't necessarily give the optimal RX filter settings.
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* When accurate chflt_m and chflt_e settings are needed they must be computed manually.
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* Function uses undefined values (900000, 852000, ...)
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* to find the chflt_m and chflt_e settings from the RX filter table (see. S2-LP datasheet).
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*/
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void rf_conf_calculate_rx_filter_bandwidth_registers(uint32_t rx_bandwidth, uint8_t *chflt_m, uint8_t *chflt_e)
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{
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uint8_t chflt_e_tmp = 0;
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uint8_t chflt_m_tmp = 0;
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while (rx_bandwidth < 900000 / (2 << chflt_e_tmp)) {
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chflt_e_tmp++;
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}
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uint32_t rx_bandwidth_tmp = rx_bandwidth;
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if (chflt_e_tmp > 0) {
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rx_bandwidth_tmp = rx_bandwidth * (2 << (chflt_e_tmp - 1));
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}
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if (852000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (806000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (760000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (724000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (682000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (650000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (588000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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if (542000 > rx_bandwidth_tmp) {
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chflt_m_tmp++;
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}
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*chflt_m = chflt_m_tmp;
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*chflt_e = chflt_e_tmp;
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}
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void rf_conf_calculate_rssi_threshold_registers(int16_t rssi_threshold, uint8_t *rssi_th)
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{
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*rssi_th = rssi_threshold + RSSI_OFFSET;
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}
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/*
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* Copyright (c) 2018 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef RF_CONF_H_
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#define RF_CONF_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RSSI_OFFSET 146
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void rf_conf_calculate_datarate_registers(uint32_t datarate, uint16_t *datarate_mantissa, uint8_t *datarate_exponent);
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void rf_conf_calculate_base_frequency_registers(uint32_t frequency, uint8_t *synt3, uint8_t *synt2, uint8_t *synt1, uint8_t *synt0);
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void rf_conf_calculate_deviation_registers(uint32_t deviation, uint8_t *fdev_m, uint8_t *fdev_e);
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int rf_conf_calculate_channel_spacing_registers(uint32_t channel_spacing, uint8_t *ch_space);
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void rf_conf_calculate_rx_filter_bandwidth_registers(uint32_t rx_bandwidth, uint8_t *chflt_m, uint8_t *chflt_e);
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void rf_conf_calculate_rssi_threshold_registers(int16_t rssi_threshold, uint8_t *rssi_th);
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#ifdef __cplusplus
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}
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#endif
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#endif /* RF_CONF_H_ */
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/*
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* Copyright (c) 2018 ARM Limited. All rights reserved.
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* SPDX-License-Identifier: Apache-2.0
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef S2LPREG_H_
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#define S2LPREG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define RF_MTU 2047
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#define PARTNUM 0x03
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#define VERSION 0xC1
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#define FIFO_SIZE 128
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#define SPI_HEADER_LENGTH 2
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#define S2LP_GPIO0 0
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#define S2LP_GPIO1 1
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#define S2LP_GPIO2 2
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#define S2LP_GPIO3 3
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// GPIO modes
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#define DIG_IN 1
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#define DIG_OUT_LOW 2
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#define DIG_OUT_HIGH 3
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// Interrupt events
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#define RX_DATA_READY 0
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#define RX_DATA_DISCARDED 1
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#define TX_DATA_SENT 2
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#define MAX_RE_TX 3
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#define CRC_ERROR 4
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#define TX_FIFO_UNF_OVF 5
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#define RX_FIFO_UNF_OVF 6
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#define TX_FIFO_ALMOST_FULL 7
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#define TX_FIFO_ALMOST_EMPTY 8
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#define RX_FIFO_ALMOST_FULL 9
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#define RX_FIFO_ALMOST_EMPTY 10
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#define MAX_CCA_BACKOFFS 11
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#define VALID_PREAMBLE 12
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#define SYNC_WORD 13
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#define RSSI_ABOVE_THR 14
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#define WAKE_UP_TIMEOUT 15
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#define READY 16
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#define STANDBY_SWITCHING 17
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#define LOW_BATTERY_LVL 18
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#define POWER_ON_RESET 19
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#define RX_TIMER_TIMEOUT 28
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#define SNIFF_TIMER_TIMEOUT 29
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// GPIO signals
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#define NIRQ 0
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#define POR 1
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#define WUT_EXPIRE 2
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#define LOW_BATTERY 3
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#define TX_DATA_OUTPUT 4
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#define TX_STATE 5
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#define TXRX_FIFO_ALMOST_EMPTY 6
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#define TXRX_FIFO_ALMOST_FULL 7
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#define RX_DATA_OUTPUT 8
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#define RX_CLOCK_OUTPUT 9
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#define RX_STATE 10
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#define STATE_OTHER_THAN_SLEEP_OR_STANDBY 11
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#define STANDBY_STATE 12
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#define ANTENNA_SWITCH 13
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#define VALID_PREAMBLE_DETECTED 14
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#define SYNC_WORD_DETECTED 15
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#define RSSI_ABOVE_THRESHOLD 16
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#define TXRX_MODE_INDICATOR 18
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#define VDD 19
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#define GND 20
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#define SMPS_ENABLE 21
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#define SLEEP_STATE 22
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#define READY_STATE 23
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#define LOCK_STATE 24
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#define WAIT_LOCK_DETECTOR 25
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#define TX_DATA_OOK 26
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#define WAIT_READY 27
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#define WAIT_TIMER_EXPIRATION 28
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#define END_OF_CALIBRATION 29
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#define ENABLE_SYNTH_BLOCK 30
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// RF registers
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#define GPIO0_CONF 0x00
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#define GPIO1_CONF 0x01
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#define GPIO2_CONF 0x02
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#define GPIO3_CONF 0x03
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#define SYNT3 0x05
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#define SYNT2 0x06
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#define SYNT1 0x07
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#define SYNT0 0x08
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#define IF_OFFSET_ANA 0x09
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#define IF_OFFSET_DIG 0x0A
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#define CHSPACE 0x0C
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#define CHNUM 0x0D
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#define MOD4 0x0E
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#define MOD3 0x0F
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#define MOD2 0x10
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#define MOD1 0x11
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#define MOD0 0x12
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#define CHFLT 0x13
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#define AFC2 0x14
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#define AFC1 0x15
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#define AFC0 0x16
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#define RSSI_FLT 0x17
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#define RSSI_TH 0x18
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#define AGCCTRL4 0x1A
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#define AGCCTRL3 0x1B
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#define AGCCTRL2 0x1C
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#define AGCCTRL1 0x1D
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#define AGCCTRL0 0x1E
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#define ANT_SELECT_CONF 0x1F
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#define CLOCKREC2 0x20
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#define CLOCKREC1 0x21
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#define PCKTCTRL6 0x2B
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#define PCKTCTRL5 0x2C
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#define PCKTCTRL4 0x2D
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#define PCKTCTRL3 0x2E
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#define PCKTCTRL2 0x2F
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#define PCKTCTRL1 0x30
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#define PCKTLEN1 0x31
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#define PCKTLEN0 0x32
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#define SYNC3 0x33
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#define SYNC2 0x34
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#define SYNC1 0x35
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#define SYNC0 0x36
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#define QI 0x37
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#define PCKT_PSTMBL 0x38
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#define PROTOCOL2 0x39
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#define PROTOCOL1 0x3A
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#define PROTOCOL0 0x3B
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#define FIFO_CONFIG3 0x3C
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#define FIFO_CONFIG2 0x3D
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#define FIFO_CONFIG1 0x3E
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#define FIFO_CONFIG0 0x3F
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#define PCKT_FLT_OPTIONS 0x40
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#define PCKT_FLT_GOALS4 0x41
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#define PCKT_FLT_GOALS3 0x42
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#define PCKT_FLT_GOALS2 0x43
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#define PCKT_FLT_GOALS1 0x44
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#define PCKT_FLT_GOALS0 0x45
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#define TIMERS5 0x46
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#define TIMERS4 0x47
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#define TIMERS3 0x48
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#define TIMERS2 0x49
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#define TIMERS1 0x4A
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#define TIMERS0 0x4B
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#define CSMA_CONF3 0x4C
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#define CSMA_CONF2 0x4D
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#define CSMA_CONF1 0x4E
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#define CSMA_CONF0 0x4F
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#define IRQ_MASK3 0x50
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#define IRQ_MASK2 0x51
|
||||
#define IRQ_MASK1 0x52
|
||||
#define IRQ_MASK0 0x53
|
||||
#define FAST_RX_TIMER 0x54
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||||
#define PA_POWER8 0x5A
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#define PA_POWER7 0x5B
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#define PA_POWER6 0x5C
|
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#define PA_POWER5 0x5D
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||||
#define PA_POWER4 0x5E
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||||
#define PA_POWER3 0x5F
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||||
#define PA_POWER2 0x60
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||||
#define PA_POWER1 0x61
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||||
#define PA_POWER0 0x62
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||||
#define PA_CONFIG1 0x63
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||||
#define PA_CONFIG0 0x64
|
||||
#define SYNTH_CONFIG2 0x65
|
||||
#define VCO_CONFIG 0x68
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||||
#define VCO_CALIBR_IN2 0x69
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||||
#define VCO_CALIBR_IN1 0x6A
|
||||
#define VCO_CALIBR_IN0 0x6B
|
||||
#define XO_RCO_CONF1 0x6C
|
||||
#define XO_RCO_CONF0 0x6D
|
||||
#define RCO_CALIBR_CONF3 0x6E
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||||
#define RCO_CALIBR_CONF2 0x6F
|
||||
#define PM_CONF4 0x75
|
||||
#define PM_CONF3 0x76
|
||||
#define PM_CONF2 0x77
|
||||
#define PM_CONF1 0x78
|
||||
#define PM_CONF0 0x79
|
||||
#define MC_STATE1 0x8D
|
||||
#define MC_STATE0 0x8E
|
||||
#define TX_FIFO_STATUS 0x8F
|
||||
#define RX_FIFO_STATUS 0x90
|
||||
#define RCO_CALIBR_OUT4 0x94
|
||||
#define RCO_CALIBR_OUT3 0x95
|
||||
#define VCO_CALIBR_OUT1 0x99
|
||||
#define VCO_CALIBR_OUT0 0x9A
|
||||
#define TX_PCKT_INFO 0x9C
|
||||
#define RX_PCKT_INFO 0x9D
|
||||
#define AFC_CORR 0x9E
|
||||
#define LINK_QUALIF2 0x9F
|
||||
#define LINK_QUALIF1 0xA0
|
||||
#define RSSI_LEVEL 0xA2
|
||||
#define RX_PCKT_LEN1 0xA4
|
||||
#define RX_PCKT_LEN0 0xA5
|
||||
#define CRC_FIELD3 0xA6
|
||||
#define CRC_FIELD2 0xA7
|
||||
#define CRC_FIELD1 0xA8
|
||||
#define CRC_FIELD0 0xA9
|
||||
#define RX_ADDRE_FIELD1 0xAA
|
||||
#define RX_ADDRE_FIELD0 0xAB
|
||||
#define RSSI_LEVEL_RUN 0xEF
|
||||
#define DEVICE_INFO1 0xF0
|
||||
#define DEVICE_INFO0 0xF1
|
||||
#define IRQ_STATUS3 0xFA
|
||||
#define IRQ_STATUS2 0xFB
|
||||
#define IRQ_STATUS1 0xFC
|
||||
#define IRQ_STATUS0 0xFD
|
||||
#define TX_FIFO 0xFF
|
||||
#define RX_FIFO 0xFF
|
||||
|
||||
#define SFD0 0x90
|
||||
#define SFD1 0x4e
|
||||
|
||||
#define DEVIATION 125000
|
||||
#define RX_FILTER_BANDWIDTH 540000
|
||||
#define RSSI_THRESHOLD -60
|
||||
|
||||
// PCKTCTRL6
|
||||
#define PCKT_SYNCLEN_FIELD 0xFC
|
||||
#define PCKT_SYNCLEN (16 << 2)
|
||||
|
||||
// PCKTCTRL5
|
||||
#define PCKT_PREAMBLE_LEN 32
|
||||
|
||||
// PCKTCTRL3
|
||||
#define PCKT_FORMAT_FIELD 0xC0
|
||||
#define PCKT_FORMAT_802_15_4 (1 << 6)
|
||||
#define PCKT_RXMODE_FIELD 0x30
|
||||
#define PCKT_RXMODE_NORMAL (0 << 4)
|
||||
|
||||
// PCKTCTRL2
|
||||
#define PCKT_FIXVARLEN_FIELD 0x01
|
||||
#define PCKT_VARIABLE_LEN (1 << 0)
|
||||
|
||||
// PCKTCTRL1
|
||||
#define PCKT_CRCMODE_FIELD 0xE0
|
||||
#define PCKT_CRCMODE_0X1021 (3 << 5)
|
||||
#define PCKT_TXSOURCE_FIELD 0x0C
|
||||
#define PCKT_TXSOURCE_NORMAL (0 << 2)
|
||||
#define PCKT_WHITENING_FIELD 0x10
|
||||
#define PCKT_WHITENING_ENABLED (1 << 4)
|
||||
|
||||
// MOD4
|
||||
#define DATARATE_M_MSB 0x47
|
||||
// MOD3
|
||||
#define DATARATE_M_LSB 0xAE
|
||||
|
||||
// MOD2
|
||||
#define MOD_TYPE_FIELD 0xF0
|
||||
#define MOD_2FSK (0 << 4)
|
||||
#define MOD_2GFSK (10 << 4)
|
||||
#define DATARATE_E_FIELD 0x0F
|
||||
#define DATARATE_E (10 << 0)
|
||||
|
||||
// MOD1
|
||||
#define FDEV_E_FIELD 0x0F
|
||||
|
||||
// QI
|
||||
#define PQI_TH_FIELD 0x1E
|
||||
#define PQI_TH (8 << 1)
|
||||
#define SQI_EN_FIELD 0x01
|
||||
#define SQI_EN (1 << 0)
|
||||
|
||||
// SYNT3
|
||||
#define SYNT_FIELD 0x0F
|
||||
|
||||
// CHFLT
|
||||
#define CHFLT_M_FIELD 0xF0
|
||||
#define CHFLT_E_FIELD 0x0F
|
||||
|
||||
// LINK_QUALIF1
|
||||
#define CARRIER_SENSE (1 << 7)
|
||||
|
||||
#define SPI_WR_REG 0x00
|
||||
#define SPI_RD_REG 0x01
|
||||
#define SPI_CMD 0x80
|
||||
|
||||
typedef enum {
|
||||
S2LP_STATE_STANDBY = 0x02,
|
||||
S2LP_STATE_SLEEPA = 0x01,
|
||||
S2LP_STATE_SLEEPB = 0x03,
|
||||
S2LP_STATE_READY = 0x00,
|
||||
S2LP_STATE_LOCK = 0x0C,
|
||||
S2LP_STATE_RX = 0x30,
|
||||
S2LP_STATE_TX = 0x5C,
|
||||
S2LP_STATE_SYNTH_SETUP = 0x50
|
||||
} s2lp_states_e;
|
||||
|
||||
typedef enum {
|
||||
S2LP_CMD_TX = 0x60,
|
||||
S2LP_CMD_RX,
|
||||
S2LP_CMD_READY,
|
||||
S2LP_CMD_STANDBY,
|
||||
S2LP_CMD_SLEEP,
|
||||
S2LP_CMD_LOCKRX,
|
||||
S2LP_CMD_LOCKTX,
|
||||
S2LP_CMD_SABORT,
|
||||
S2LP_CMD_LDC_RELOAD,
|
||||
S2LP_CMD_SRES = 0x70,
|
||||
S2LP_CMD_FLUSHRXFIFO,
|
||||
S2LP_CMD_FLUSHTXFIFO,
|
||||
S2LP_CMD_SEQUPDATE
|
||||
} s2lp_commands_e;
|
||||
|
||||
typedef enum {
|
||||
RF_IDLE,
|
||||
RF_CSMA_STARTED,
|
||||
RF_TX_STARTED,
|
||||
RF_RX_STARTED,
|
||||
RF_TX_ACK
|
||||
} rf_states_e;
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
#endif /* S2LPREG_H_ */
|
||||
|
|
@ -0,0 +1,109 @@
|
|||
/*
|
||||
* Copyright (c) 2018 ARM Limited. All rights reserved.
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
* Licensed under the Apache License, Version 2.0 (the License); you may
|
||||
* not use this file except in compliance with the License.
|
||||
* You may obtain a copy of the License at
|
||||
*
|
||||
* http://www.apache.org/licenses/LICENSE-2.0
|
||||
*
|
||||
* Unless required by applicable law or agreed to in writing, software
|
||||
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
|
||||
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
* See the License for the specific language governing permissions and
|
||||
* limitations under the License.
|
||||
*/
|
||||
|
||||
#ifndef NANOSTACK_PHY_S2LP_H_
|
||||
#define NANOSTACK_PHY_S2LP_H_
|
||||
|
||||
#include "mbed.h"
|
||||
#if defined(MBED_CONF_NANOSTACK_CONFIGURATION) && DEVICE_SPI
|
||||
#include "NanostackRfPhy.h"
|
||||
|
||||
// Uncomment to use testing gpios attached to TX/RX processes
|
||||
//#define TEST_GPIOS_ENABLED
|
||||
|
||||
#if !defined(S2LP_SPI_SDI)
|
||||
#define S2LP_SPI_SDI D11
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_SDO)
|
||||
#define S2LP_SPI_SDO D12
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_SCLK)
|
||||
#define S2LP_SPI_SCLK D13
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_CS)
|
||||
#define S2LP_SPI_CS A1
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_SDN)
|
||||
#define S2LP_SPI_SDN D7
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_TEST1)
|
||||
#define S2LP_SPI_TEST1 D6
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_TEST2)
|
||||
#define S2LP_SPI_TEST2 D5
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_TEST3)
|
||||
#define S2LP_SPI_TEST3 D4
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_TEST4)
|
||||
#define S2LP_SPI_TEST4 D2
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_TEST5)
|
||||
#define S2LP_SPI_TEST5 D8
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO0)
|
||||
#define S2LP_SPI_GPIO0 A0
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO1)
|
||||
#define S2LP_SPI_GPIO1 A2
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO2)
|
||||
#define S2LP_SPI_GPIO2 A3
|
||||
#endif
|
||||
#if !defined(S2LP_SPI_GPIO3)
|
||||
#define S2LP_SPI_GPIO3 A5
|
||||
#endif
|
||||
|
||||
class RFPins;
|
||||
|
||||
class NanostackRfPhys2lp : public NanostackRfPhy {
|
||||
public:
|
||||
NanostackRfPhys2lp(PinName spi_sdi, PinName spi_sdo,
|
||||
PinName spi_sclk, PinName spi_cs, PinName spi_sdn,
|
||||
#ifdef TEST_GPIOS_ENABLED
|
||||
PinName spi_test1, PinName spi_test2, PinName spi_test3, PinName spi_test4, PinName spi_test5,
|
||||
#endif //TEST_GPIOS_ENABLED
|
||||
PinName spi_gpio0, PinName spi_gpio1, PinName spi_gpio2, PinName spi_gpio3);
|
||||
virtual ~NanostackRfPhys2lp();
|
||||
virtual int8_t rf_register();
|
||||
virtual void rf_unregister();
|
||||
virtual void get_mac_address(uint8_t *mac);
|
||||
virtual void set_mac_address(uint8_t *mac);
|
||||
|
||||
private:
|
||||
uint8_t _mac_addr[8];
|
||||
RFPins *_rf;
|
||||
bool _mac_set;
|
||||
|
||||
const PinName _spi_sdi;
|
||||
const PinName _spi_sdo;
|
||||
const PinName _spi_sclk;
|
||||
const PinName _spi_cs;
|
||||
const PinName _spi_sdn;
|
||||
#ifdef TEST_GPIOS_ENABLED
|
||||
const PinName _spi_test1;
|
||||
const PinName _spi_test2;
|
||||
const PinName _spi_test3;
|
||||
const PinName _spi_test4;
|
||||
const PinName _spi_test5;
|
||||
#endif //TEST_GPIOS_ENABLED
|
||||
const PinName _spi_gpio0;
|
||||
const PinName _spi_gpio1;
|
||||
const PinName _spi_gpio2;
|
||||
const PinName _spi_gpio3;
|
||||
};
|
||||
#endif /* MBED_CONF_NANOSTACK_CONFIGURATION && DEVICE_SPI */
|
||||
#endif /* NANOSTACK_PHY_S2LP_H_ */
|
||||
Loading…
Reference in New Issue