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STM32F1 warning compilation 

[-Wparentheses-equality]
pull/10793/head
jeromecoutant 2019-06-07 17:16:10 +02:00
parent 7154ac65f2
commit 8c2ee68be1
5 changed files with 23 additions and 23 deletions
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2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc.c
View File

@ -1765,7 +1765,7 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
{ {
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)) if (sConfig->Channel == ADC_CHANNEL_TEMPSENSOR)
{ {
/* Delay for temperature sensor stabilization time */ /* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */ /* Compute number of CPU cycles to wait for */

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_adc_ex.c
View File

@ -1225,7 +1225,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
{ {
SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE); SET_BIT(hadc->Instance->CR2, ADC_CR2_TSVREFE);
if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)) if (sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR)
{ {
/* Delay for temperature sensor stabilization time */ /* Delay for temperature sensor stabilization time */
/* Compute number of CPU cycles to wait for */ /* Compute number of CPU cycles to wait for */

28
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim.c
View File

@ -389,11 +389,11 @@ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pDat
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((pData == 0U) && (Length > 0U)) if((pData == 0U) && (Length > 0U))
{ {
@ -781,11 +781,11 @@ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0U)) if(((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -1289,11 +1289,11 @@ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channe
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0U)) if(((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -1770,11 +1770,11 @@ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel
assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((pData == 0U) && (Length > 0U)) if((pData == 0U) && (Length > 0U))
{ {
@ -2593,11 +2593,11 @@ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Ch
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance)); assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U)) if((((pData1 == 0U) || (pData2 == 0U) )) && (Length > 0U))
{ {
@ -3340,11 +3340,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((BurstBuffer == 0U) && (BurstLength > 0U)) if((BurstBuffer == 0U) && (BurstLength > 0U))
{ {
@ -3563,11 +3563,11 @@ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t B
assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc)); assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
assert_param(IS_TIM_DMA_LENGTH(BurstLength)); assert_param(IS_TIM_DMA_LENGTH(BurstLength));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if((BurstBuffer == 0U) && (BurstLength > 0U)) if((BurstBuffer == 0U) && (BurstLength > 0U))
{ {

12
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_tim_ex.c
View File

@ -393,11 +393,11 @@ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_XOR_INSTANCE(htim->Instance)); assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0U)) if(((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -683,11 +683,11 @@ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Chan
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0U)) if(((uint32_t)pData == 0U) && (Length > 0U))
{ {
@ -1056,11 +1056,11 @@ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Cha
/* Check the parameters */ /* Check the parameters */
assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel)); assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
if((htim->State == HAL_TIM_STATE_BUSY)) if(htim->State == HAL_TIM_STATE_BUSY)
{ {
return HAL_BUSY; return HAL_BUSY;
} }
else if((htim->State == HAL_TIM_STATE_READY)) else if(htim->State == HAL_TIM_STATE_READY)
{ {
if(((uint32_t)pData == 0U) && (Length > 0U)) if(((uint32_t)pData == 0U) && (Length > 0U))
{ {

2
targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_usart.c
View File

@ -2282,7 +2282,7 @@ static void USART_SetConfig(USART_HandleTypeDef *husart)
CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE)); CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
/*-------------------------- USART BRR Configuration -----------------------*/ /*-------------------------- USART BRR Configuration -----------------------*/
if((husart->Instance == USART1)) if(husart->Instance == USART1)
{ {
husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate); husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
} }