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Remove vk_rz_a1h target

pull/12775/head
MarceloSalazar 2020-04-08 08:54:36 +01:00
parent e43ece13aa
commit 8bf863c181
80 changed files with 5 additions and 50419 deletions
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111
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h
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@ -1,111 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALNAMES_H
#define MBED_PERIPHERALNAMES_H
#include "cmsis.h"
#include "PinNames.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
UART0,
UART1,
UART2,
UART3,
UART4,
UART5,
UART6,
UART7,
} UARTName;
typedef enum {
PWM_PWM1A = 0,
PWM_PWM1B,
PWM_PWM1C,
PWM_PWM1D,
PWM_PWM1E,
PWM_PWM1F,
PWM_PWM1G,
PWM_PWM1H,
PWM_PWM2A,
PWM_PWM2B,
PWM_PWM2C,
PWM_PWM2D,
PWM_PWM2E,
PWM_PWM2F,
PWM_PWM2G,
PWM_PWM2H,
PWM_TIOC0A = 0x20,
PWM_TIOC0C,
PWM_TIOC1A,
PWM_TIOC1B,
PWM_TIOC2A,
PWM_TIOC2B,
PWM_TIOC3A,
PWM_TIOC3C,
PWM_TIOC4A,
PWM_TIOC4C,
} PWMName;
typedef enum {
AN0= 0,
AN1= 1,
AN2= 2,
AN3= 3,
AN4= 4,
AN5= 5,
AN6= 6,
AN7= 7,
} ADCName;
typedef enum {
SPI_0 = 0,
SPI_1,
SPI_2,
SPI_3,
SPI_4,
} SPIName;
typedef enum {
I2C_0 = 0,
I2C_1,
I2C_2,
I2C_3,
} I2CName;
typedef enum {
CAN_0 = 0,
CAN_1,
CAN_2,
CAN_3,
CAN_4,
} CANName;
#define STDIO_UART_TX USBTX
#define STDIO_UART_RX USBRX
#define STDIO_UART UART3
#ifdef __cplusplus
}
#endif
#endif

540
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************IRQ***************/
enum {
IRQ0,IRQ1,
IRQ2,IRQ3,
IRQ4,IRQ5,
IRQ6,IRQ7,
} IRQNo;
const PinMap PinMap_IRQ[] = {
#ifdef MAX_PERI
{P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4},
{P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8},
{P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4},
{P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4},
{P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4},
{P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4},
{P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
{P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8},
{NC, NC, 0}
#else
{P9_1, IRQ0, 4},
{P7_8, IRQ1, 8},
{P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4},
{P1_3, IRQ3, 4}, {P1_9, IRQ3, 3},
{P1_4, IRQ4, 4}, {P1_10, IRQ4, 3},
{P1_5, IRQ5, 4}, {P1_11, IRQ5, 3},
{P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
{NC, NC, 0}
#endif
};
/************PINMAP***************/
const PinFunc PIPC_0_tbl[] = {
#ifdef MAX_PERI
// pin func pm
{P4_0 , 2 , -1}, /* TIOC0A */
{P5_0 , 6 , -1}, /* TIOC0A */
{P7_0 , 7 , -1}, /* TIOC0A */
{P4_1 , 2 , -1}, /* TIOC0B */
{P5_1 , 6 , -1}, /* TIOC0B */
{P7_1 , 7 , -1}, /* TIOC0B */
{P4_2 , 2 , -1}, /* TIOC0C */
{P5_5 , 6 , -1}, /* TIOC0C */
{P7_2 , 7 , -1}, /* TIOC0C */
{P4_3 , 2 , -1}, /* TIOC0D */
{P5_7 , 6 , -1}, /* TIOC0D */
{P7_3 , 7 , -1}, /* TIOC0D */
{P2_11 , 5 , -1}, /* TIOC1A */
{P6_0 , 5 , -1}, /* TIOC1A */
{P7_4 , 7 , -1}, /* TIOC1A */
{P8_8 , 5 , -1}, /* TIOC1A */
{P9_7 , 4 , -1}, /* TIOC1A */
{P2_12 , 8 , -1}, /* TIOC1B */
{P5_2 , 6 , -1}, /* TIOC1B */
{P6_1 , 5 , -1}, /* TIOC1B */
{P7_5 , 7 , -1}, /* TIOC1B */
{P8_9 , 5 , -1}, /* TIOC1B */
{P2_1 , 6 , -1}, /* TIOC2A */
{P6_2 , 6 , -1}, /* TIOC2A */
{P7_6 , 7 , -1}, /* TIOC2A */
{P8_14 , 4 , -1}, /* TIOC2A */
{P2_2 , 6 , -1}, /* TIOC2B */
{P6_3 , 6 , -1}, /* TIOC2B */
{P7_7 , 7 , -1}, /* TIOC2B */
{P8_15 , 4 , -1}, /* TIOC2B */
{P3_4 , 6 , -1}, /* TIOC3A */
{P7_8 , 7 , -1}, /* TIOC3A */
{P8_10 , 4 , -1}, /* TIOC3A */
{P3_5 , 6 , -1}, /* TIOC3B */
{P7_9 , 7 , -1}, /* TIOC3B */
{P8_11 , 4 , -1}, /* TIOC3B */
{P3_6 , 6 , -1}, /* TIOC3C */
{P5_3 , 6 , -1}, /* TIOC3C */
{P7_10 , 7 , -1}, /* TIOC3C */
{P8_12 , 4 , -1}, /* TIOC3C */
{P3_7 , 6 , -1}, /* TIOC3D */
{P5_4 , 6 , -1}, /* TIOC3D */
{P7_11 , 7 , -1}, /* TIOC3D */
{P8_13 , 4 , -1}, /* TIOC3D */
{P3_8 , 6 , -1}, /* TIOC4A */
{P4_4 , 3 , -1}, /* TIOC4A */
{P7_12 , 7 , -1}, /* TIOC4A */
{P3_9 , 6 , -1}, /* TIOC4B */
{P4_5 , 3 , -1}, /* TIOC4B */
{P7_13 , 7 , -1}, /* TIOC4B */
{P3_10 , 6 , -1}, /* TIOC4C */
{P4_6 , 3 , -1}, /* TIOC4C */
{P7_14 , 7 , -1}, /* TIOC4C */
{P3_11 , 6 , -1}, /* TIOC4D */
{P4_7 , 3 , -1}, /* TIOC4D */
{P7_15 , 7 , -1}, /* TIOC4D */
{P5_7 , 1 , 1 }, /* TXOUT0M */
{P5_6 , 1 , 1 }, /* TXOUT0P */
{P5_5 , 1 , 1 }, /* TXOUT1M */
{P5_4 , 1 , 1 }, /* TXOUT1P */
{P5_3 , 1 , 1 }, /* TXOUT2M */
{P5_2 , 1 , 1 }, /* TXOUT2P */
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
{P2_11 , 4 , 0 }, /* SSITxD0 */
{P4_7 , 5 , 0 }, /* SSITxD0 */
{P7_4 , 6 , 0 }, /* SSITxD1 */
{P4_15 , 6 , 0 }, /* SSITxD3 */
{P7_11 , 2 , 0 }, /* SSITxD3 */
{P2_7 , 4 , 0 }, /* SSITxD5 */
{P4_11 , 5 , 0 }, /* SSITxD5 */
{P8_10 , 8 , 0 }, /* SSITxD5 */
{P3_7 , 8 , 0 }, /* WDTOVF */
{NC , 0 , -1}
#else
// pin func pm
{P4_0 , 2 , -1}, // TIOC0A
{P5_0 , 6 , -1}, // TIOC0A
{P4_2 , 2 , -1}, // TIOC0C
{P5_5 , 6 , -1}, // TIOC0C
//
{P8_14 , 4 , -1}, // TIOC2A
//
{P8_10 , 4 , -1}, // TIOC3A
{P5_3 , 6 , -1}, // TIOC3C
{P8_12 , 4 , -1}, // TIOC3C
//
{P3_8 , 6 , -1}, // TIOC4A
{P4_4 , 3 , -1}, // TIOC4A
{P3_10 , 6 , -1}, // TIOC4C
{P4_6 , 3 , -1}, // TIOC4C
//
{P5_7 , 1 , 1 }, // TXOUT0M
{P5_6 , 1 , 1 }, // TXOUT0P
{P5_5 , 1 , 1 }, // TXOUT1M
{P5_4 , 1 , 1 }, // TXOUT1P
{P5_3 , 1 , 1 }, // TXOUT2M
{P5_2 , 1 , 1 }, // TXOUT2P
{P5_1 , 1 , 1 }, // TXCLKOUTM
{P5_0 , 1 , 1 }, // TXCLKOUTP
{P4_7 , 5 , 0 }, // SSITxD0
{P8_10 , 8 , 0 }, // SSITxD5
{P3_7 , 8 , 0 }, // WDTOVF
{NC , 0 , -1}
#endif
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
#ifdef MAX_PERI
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_14, AN6, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
#else
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
#endif
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P1_1 , I2C_0, 1},
{P1_3 , I2C_1, 1},
{P1_5 , I2C_2, 1},
{P1_7 , I2C_3, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P1_0 , I2C_0, 1},
{P1_2 , I2C_1, 1},
{P1_4 , I2C_2, 1},
{P1_6 , I2C_3, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
#ifdef MAX_PERI
{P2_14 , UART0, 6},
{P4_9 , UART0, 7},
{P6_9 , UART0, 5},
{P2_5 , UART1, 6},
{P4_12 , UART1, 7},
{P6_12 , UART1, 5},
{P9_3 , UART1, 4},
{P3_0 , UART2, 6},
{P3_1 , UART2, 4},
{P4_2 , UART2, 5},
{P4_14 , UART2, 7},
{P6_3 , UART2, 7},
{P8_6 , UART2, 7},
{P3_5 , UART3, 7},
{P5_3 , UART3, 5},
{P6_1 , UART3, 7},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P7_1 , UART4, 4},
{P8_14 , UART4, 7},
{P6_6 , UART5, 5},
{P8_1 , UART5, 4},
{P8_13 , UART5, 5},
{P5_6 , UART6, 5},
{P6_14 , UART6, 4},
{P7_4 , UART7, 4},
{NC , NC , 0}
#else
{P3_0 , UART2, 6},
{P3_1 , UART2, 4},
{P4_2 , UART2, 5},
{P5_3 , UART3, 5},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P8_14 , UART4, 7},
{P8_13 , UART5, 5},
{P5_6 , UART6, 5},
{NC , NC , 0}
#endif
};
const PinMap PinMap_UART_RX[] = {
#ifdef MAX_PERI
{P2_15 , UART0, 6},
{P4_10 , UART0, 7},
{P6_10 , UART0, 5},
{P2_6 , UART1, 6},
{P4_13 , UART1, 7},
{P6_13 , UART1, 5},
{P9_4 , UART1, 4},
{P3_2 , UART2, 4},
{P4_3 , UART2, 5},
{P4_15 , UART2, 7},
{P6_2 , UART2, 7},
{P8_4 , UART2, 7},
{P3_6 , UART3, 7},
{P5_4 , UART3, 5},
{P6_0 , UART3, 7},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P7_2 , UART4, 4},
{P8_15 , UART4, 7},
{P6_7 , UART5, 5},
{P8_2 , UART5, 4},
{P8_11 , UART5, 5},
{P5_7 , UART6, 5},
{P6_15 , UART6, 4},
{P7_5 , UART7, 4},
{NC , NC , 0}
#else
{P3_2 , UART2, 4},
{P4_3 , UART2, 5},
{P5_4 , UART3, 5},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P8_15 , UART4, 7},
{P8_11 , UART5, 5},
{P5_7 , UART6, 5},
{NC , NC , 0}
#endif
};
const PinMap PinMap_UART_CTS[] = {
#ifdef MAX_PERI
{P2_3 , UART1, 6},
{P9_5 , UART1, 4},
{P6_3 , UART5, 5},
{P7_15 , UART5, 4},
{P7_6 , UART7, 4},
{NC , NC , 0}
#else
{NC , NC , 0}
#endif
};
const PinMap PinMap_UART_RTS[] = {
#ifdef MAX_PERI
{P2_7 , UART1, 6},
{P9_6 , UART1, 4},
{P6_4 , UART5, 5},
{P8_3 , UART5, 4},
{P7_7 , UART7, 4},
{NC , NC , 0}
#else
{NC , NC , 0}
#endif
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
#ifdef MAX_PERI
{P2_12 , SPI_0, 2},
{P7_15 , SPI_0, 2},
{P4_4 , SPI_1, 2},
{P6_4 , SPI_1, 7},
{P8_3 , SPI_2, 3},
{P8_14 , SPI_2, 5},
{P3_0 , SPI_3, 8},
{P5_0 , SPI_3, 8},
{P2_8 , SPI_4, 8},
{P4_0 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_4 , SPI_1, 2},
{P8_14 , SPI_2, 5},
{P5_0 , SPI_3, 8},
{P4_0 , SPI_4, 7},
{NC , NC , 0}
#endif
};
const PinMap PinMap_SPI_MOSI[] = {
#ifdef MAX_PERI
{P2_14 , SPI_0, 2},
{P8_1 , SPI_0, 2},
{P4_6 , SPI_1, 2},
{P6_6 , SPI_1, 7},
{P8_5 , SPI_2, 3},
{P9_0 , SPI_2, 5},
{P3_2 , SPI_3, 8},
{P5_2 , SPI_3, 8},
{P2_10 , SPI_4, 8},
{P4_2 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_6 , SPI_1, 2},
{P9_0 , SPI_2, 5},
{P5_2 , SPI_3, 8},
{P4_2 , SPI_4, 7},
{NC , NC , 0}
#endif
};
const PinMap PinMap_SPI_MISO[] = {
#ifdef MAX_PERI
{P2_15 , SPI_0, 2},
{P8_2 , SPI_0, 2},
{P4_7 , SPI_1, 2},
{P6_7 , SPI_1, 7},
{P8_6 , SPI_2, 3},
{P9_1 , SPI_2, 5},
{P3_3 , SPI_3, 8},
{P5_3 , SPI_3, 8},
{P2_11 , SPI_4, 8},
{P4_3 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_7 , SPI_1, 2},
{P9_1 , SPI_2, 5},
{P5_3 , SPI_3, 8},
{P4_3 , SPI_4, 7},
{NC , NC , 0}
#endif
};
const PinMap PinMap_SPI_SSEL[] = {
#ifdef MAX_PERI
{P2_13 , SPI_0, 2},
{P8_0 , SPI_0, 2},
{P4_5 , SPI_1, 2},
{P6_5 , SPI_1, 7},
{P8_4 , SPI_2, 3},
{P8_15 , SPI_2, 5},
{P3_1 , SPI_3, 8},
{P5_1 , SPI_3, 8},
{P2_9 , SPI_4, 8},
{P4_1 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_5 , SPI_1, 2},
{P8_15 , SPI_2, 5},
{P5_1 , SPI_3, 8},
{P4_1 , SPI_4, 7},
{NC , NC , 0}
#endif
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
#ifdef MAX_PERI
// TIOC0 A,C
{P4_0 , PWM_TIOC0A, 2}, //TIOC0A
{P5_0 , PWM_TIOC0A, 6}, //TIOC0A
{P7_0 , PWM_TIOC0A, 7}, //TIOC0A
{P4_2 , PWM_TIOC0C, 2}, //TIOC0C
{P5_5 , PWM_TIOC0C, 6}, //TIOC0C
{P7_2 , PWM_TIOC0C, 7}, //TIOC0C
//TIOC1 A
{P2_11 , PWM_TIOC1A, 5}, //TIOC1A
{P6_0 , PWM_TIOC1A, 5}, //TIOC1A
{P7_4 , PWM_TIOC1A, 7}, //TIOC1A
{P8_8 , PWM_TIOC1A, 5}, //TIOC1A
{P9_7 , PWM_TIOC1A, 4}, //TIOC1A
//TIOC2 A
{P2_1 , PWM_TIOC2A, 6}, //TIOC2A
{P6_2 , PWM_TIOC2A, 6}, //TIOC2A
{P7_6 , PWM_TIOC2A, 7}, //TIOC2A
{P8_14 , PWM_TIOC2A, 4}, //TIOC2A
//TIOC3 A,C
{P3_4 , PWM_TIOC3A, 6}, //TIOC3A
{P7_8 , PWM_TIOC3A, 7}, //TIOC3A
{P8_10 , PWM_TIOC3A, 4}, //TIOC3A
{P3_6 , PWM_TIOC3C, 6}, //TIOC3C
{P7_10 , PWM_TIOC3C, 7}, //TIOC3C
{P8_12 , PWM_TIOC3C, 4}, //TIOC3C
//TIOC4 A,C
{P3_8 , PWM_TIOC4A, 6}, //TIOC4A
{P4_4 , PWM_TIOC4A, 3}, //TIOC4A
{P7_12 , PWM_TIOC4A, 7}, //TIOC4A
{P3_10 , PWM_TIOC4C, 6}, //TIOC4C
{P4_6 , PWM_TIOC4C, 3}, //TIOC4C
{P7_14 , PWM_TIOC4C, 7}, //TIOC4C
//PWM1
{P8_8 , PWM_PWM1A , 6}, //PWM1A
{P8_9 , PWM_PWM1B , 6}, //PWM1B
{P8_10 , PWM_PWM1C , 6}, //PWM1C
{P8_11 , PWM_PWM1D , 6}, //PWM1D
{P8_12 , PWM_PWM1E , 6}, //PWM1E
{P8_13 , PWM_PWM1F , 6}, //PWM1F
{P8_14 , PWM_PWM1G , 6}, //PWM1G
{P8_15 , PWM_PWM1H , 6}, //PWM1H
//PWM2
{P3_0 , PWM_PWM2A , 7}, //PWM2A
{P3_1 , PWM_PWM2B , 7}, //PWM2B
{P3_2 , PWM_PWM2C , 7}, //PWM2C
{P3_3 , PWM_PWM2D , 7}, //PWM2D
{P4_4 , PWM_PWM2E , 4}, //PWM2E
{P4_5 , PWM_PWM2F , 4}, //PWM2F
{P4_6 , PWM_PWM2G , 4}, //PWM2G
{P4_7 , PWM_PWM2H , 4}, //PWM2H
{NC , NC , 0}
#else
//TIOC0 A,C
{P4_0 , PWM_TIOC0A, 2}, //TIOC0A
{P5_0 , PWM_TIOC0A, 6}, //TIOC0A
{P4_2 , PWM_TIOC0C, 2}, //TIOC0C
{P5_5 , PWM_TIOC0C, 6}, //TIOC0C
//TIOC2 A
{P8_14 , PWM_TIOC2A, 4}, //TIOC2A
//TIOC3 A,C
{P8_10 , PWM_TIOC3A, 4}, //TIOC3A
{P5_3 , PWM_TIOC3C, 6}, //TIOC3C
{P8_12 , PWM_TIOC3C, 4}, //TIOC3C
//TIOC4 A,C
{P3_8 , PWM_TIOC4A, 6}, //TIOC4A
{P4_4 , PWM_TIOC4A, 3}, //TIOC4A
{P3_10 , PWM_TIOC4C, 6}, //TIOC4C
{P4_6 , PWM_TIOC4C, 3}, //TIOC4C
//PWM1
{P8_10 , PWM_PWM1C , 6}, //PWM1C
{P8_11 , PWM_PWM1D , 6}, //PWM1D
{P8_12 , PWM_PWM1E , 6}, //PWM1E
{P8_13 , PWM_PWM1F , 6}, //PWM1F
{P8_14 , PWM_PWM1G , 6}, //PWM1G
{P8_15 , PWM_PWM1H , 6}, //PWM1H
//PWM2
{P3_0 , PWM_PWM2A , 7}, //PWM2A
{P3_1 , PWM_PWM2B , 7}, //PWM2B
{P3_2 , PWM_PWM2C , 7}, //PWM2C
{P4_4 , PWM_PWM2E , 4}, //PWM2E
{P4_5 , PWM_PWM2F , 4}, //PWM2F
{P4_6 , PWM_PWM2G , 4}, //PWM2G
{P4_7 , PWM_PWM2H , 4}, //PWM2H
{NC , NC , 0}
#endif
};
/************CAN***************/
const PinMap PinMap_CAN_RD[] = {
#ifdef MAX_PERI
{P7_8 , CAN_0, 4},
{P9_1 , CAN_0, 3},
{P1_4 , CAN_1, 3},
{P5_9 , CAN_1, 5},
{P7_11 , CAN_1, 4},
{P4_9 , CAN_2, 6},
{P6_4 , CAN_2, 3},
{P7_2 , CAN_2, 5},
{P2_12 , CAN_3, 5},
{P4_2 , CAN_3, 4},
{P1_5 , CAN_4, 3},
{P2_14 , CAN_4, 5},
{NC , NC , 0}
#else
{P9_1 , CAN_0, 3},
{P1_4 , CAN_1, 3},
{P5_9 , CAN_1, 5},
{P4_2 , CAN_3, 4},
{P1_5 , CAN_4, 3},
{NC , NC , 0}
#endif
};
const PinMap PinMap_CAN_TD[] = {
#ifdef MAX_PERI
{P7_9 , CAN_0, 4},
{P9_0 , CAN_0, 3},
{P5_10 , CAN_1, 5},
{P7_10 , CAN_1, 4},
{P4_8 , CAN_2, 6},
{P6_5 , CAN_2, 3},
{P7_3 , CAN_2, 5},
{P2_13 , CAN_3, 5},
{P4_3 , CAN_3, 4},
{P4_11 , CAN_4, 6},
{P8_10 , CAN_4, 5},
{NC , NC , 0}
#else
{P9_0 , CAN_0, 3},
{P5_10 , CAN_1, 5},
{P4_3 , CAN_3, 4},
{P8_10 , CAN_4, 5},
{NC , NC , 0}
#endif
};

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PinNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PINNAMES_H
#define MBED_PINNAMES_H
#include "cmsis.h"
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
PIN_INPUT,
PIN_OUTPUT
} PinDirection;
#define PORT_SHIFT 4
typedef enum {
P0_0 = 0, P0_1, P0_2, P0_3, P0_4, P0_5,
P1_0 = 16, P1_1, P1_2, P1_3, P1_4, P1_5, P1_6, P1_7, P1_8, P1_9, P1_10, P1_11, P1_12, P1_13, P1_14, P1_15,
P2_0, P2_1, P2_2, P2_3, P2_4, P2_5, P2_6, P2_7, P2_8, P2_9, P2_10, P2_11, P2_12, P2_13, P2_14, P2_15,
P3_0, P3_1, P3_2, P3_3, P3_4, P3_5, P3_6, P3_7, P3_8, P3_9, P3_10, P3_11, P3_12, P3_13, P3_14, P3_15,
P4_0, P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7, P4_8, P4_9, P4_10, P4_11, P4_12, P4_13, P4_14, P4_15,
P5_0, P5_1, P5_2, P5_3, P5_4, P5_5, P5_6, P5_7, P5_8, P5_9, P5_10,
P6_0 = 96, P6_1, P6_2, P6_3, P6_4, P6_5, P6_6, P6_7, P6_8, P6_9, P6_10, P6_11, P6_12, P6_13, P6_14, P6_15,
P7_0, P7_1, P7_2, P7_3, P7_4, P7_5, P7_6, P7_7, P7_8, P7_9, P7_10, P7_11, P7_12, P7_13, P7_14, P7_15,
P8_0, P8_1, P8_2, P8_3, P8_4, P8_5, P8_6, P8_7, P8_8, P8_9, P8_10, P8_11, P8_12, P8_13, P8_14, P8_15,
P9_0, P9_1, P9_2, P9_3, P9_4, P9_5, P9_6, P9_7,
// mbed Pin Names
LED1 = P7_1,
LED_RED = LED1,
// mbed led alias to keep some test happy, becasue physically they are no LED2,LED3 & LED4 on the board
LED2 = LED1,
LED3 = LED2,
LED4 = LED3,
I2C_SCL = P1_0,
I2C_SDA = P1_1,
USBTX = P8_8,
USBRX = P8_9,
//USER_BUTTON0 = P6_0,
// Not connected
NC = (int)0xFFFFFFFF
} PinName;
typedef enum {
PullUp = 0,
PullDown = 3,
PullNone = 2,
OpenDrain = 4,
PullDefault = PullDown
} PinMode;
#define PINGROUP(pin) (((pin)>>PORT_SHIFT)&0x0f)
#define PINNO(pin) ((pin)&0x0f)
#ifdef __cplusplus
}
#endif
#endif

37
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PortNames.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PORTNAMES_H
#define MBED_PORTNAMES_H
#ifdef __cplusplus
extern "C" {
#endif
typedef enum {
Port0 = 0,
Port1 = 1,
Port3 = 3,
Port4 = 4,
Port5 = 5,
Port7 = 7,
Port8 = 8,
Port9 = 9
} PortName;
#ifdef __cplusplus
}
#endif
#endif

22
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/TARGET_MBED_VKRZA1H/reserved_pins.h
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@ -1,22 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef RESERVED_PINS_H
#define RESERVED_PINS_H
#define TARGET_RESERVED_PINS {}
#endif

37
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device.h
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// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches.
// Check the 'features' section of the target description in 'targets.json' for more details.
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DEVICE_H
#define MBED_DEVICE_H
/* ->Take measures about optimization problems of web compiler */
/* Web compiler has problem that inlining code may not be generated correctly */
/* when "-O3 -Otime" was specified. */
#if defined(__CC_ARM) && (__ARMCC_VERSION <= 5040027)
#pragma Ospace
#endif
/* <-Take measures about optimization problems of web compiler */
#define TRANSACTION_QUEUE_SIZE_SPI 16
#define DEVICE_ID_LENGTH 32
#define DEVICE_MAC_OFFSET 20
#include "objects.h"
#include "dma_api.h"
#endif

704
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/RZ_A1_Init.c
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@ -1,704 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/**************************************************************************//**
* @file RZ_A1_Init.c
* $Rev: 624 $
* $Date:: 2013-04-24 13:37:48 +0900#$
* @brief RZ_A1 Initialize
******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "VKRZA1H.h"
#include "RZ_A1_Init.h"
#include "rza_io_regrw.h"
#include "gpio_iobitmask.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define CS2_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFD040)
#define CS3_SDRAM_MODE_16BIT_CAS2_BR_BW (*(volatile uint16_t*)0x3FFFE040)
#define GPIO_PORT0_BOOTMODE_BITMASK (0x000fu)
#if (defined(TARGET_DEBUG) || !defined(RUN_FROM_SDRAM))
#define CS2_SDRAM
#endif
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
static void PORT_Init(void)
{
/* ==== BSC settings ==== */
/* ---- P7_2 : RAS# ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC72_SHIFT, GPIO_PIBC7_PIBC72);
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC72_SHIFT, GPIO_PBDC7_PBDC72);
RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM72_SHIFT, GPIO_PM7_PM72);
RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC72_SHIFT, GPIO_PMC7_PMC72);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC72_SHIFT, GPIO_PIPC7_PIPC72);
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC72_SHIFT, GPIO_PBDC7_PBDC72);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC72_SHIFT, GPIO_PFC7_PFC72);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE72_SHIFT, GPIO_PFCE7_PFCE72);
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE72_SHIFT, GPIO_PFCAE7_PFCAE72);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC72_SHIFT, GPIO_PIPC7_PIPC72);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC72_SHIFT, GPIO_PMC7_PMC72);
/* ---- P7_3 : CAS# ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC73_SHIFT, GPIO_PIBC7_PIBC73);
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC73_SHIFT, GPIO_PBDC7_PBDC73);
RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM73_SHIFT, GPIO_PM7_PM73);
RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC73_SHIFT, GPIO_PMC7_PMC73);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC73_SHIFT, GPIO_PIPC7_PIPC73);
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC73_SHIFT, GPIO_PBDC7_PBDC73);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC73_SHIFT, GPIO_PFC7_PFC73);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE73_SHIFT, GPIO_PFCE7_PFCE73);
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE73_SHIFT, GPIO_PFCAE7_PFCAE73);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC73_SHIFT, GPIO_PIPC7_PIPC73);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC73_SHIFT, GPIO_PMC7_PMC73);
/* ---- P7_4 : CKE ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC74_SHIFT, GPIO_PIBC7_PIBC74);
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC74_SHIFT, GPIO_PBDC7_PBDC74);
RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM74_SHIFT, GPIO_PM7_PM74);
RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC74_SHIFT, GPIO_PMC7_PMC74);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC74_SHIFT, GPIO_PIPC7_PIPC74);
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC74_SHIFT, GPIO_PBDC7_PBDC74);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC74_SHIFT, GPIO_PFC7_PFC74);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE74_SHIFT, GPIO_PFCE7_PFCE74);
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE74_SHIFT, GPIO_PFCAE7_PFCAE74);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC74_SHIFT, GPIO_PIPC7_PIPC74);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC74_SHIFT, GPIO_PMC7_PMC74);
/* ---- P7_5 : RD/WR# ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC75_SHIFT, GPIO_PIBC7_PIBC75);
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC75_SHIFT, GPIO_PBDC7_PBDC75);
RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM75_SHIFT, GPIO_PM7_PM75);
RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC75_SHIFT, GPIO_PMC7_PMC75);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC75_SHIFT, GPIO_PIPC7_PIPC75);
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC75_SHIFT, GPIO_PBDC7_PBDC75);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC75_SHIFT, GPIO_PFC7_PFC75);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE75_SHIFT, GPIO_PFCE7_PFCE75);
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE75_SHIFT, GPIO_PFCAE7_PFCAE75);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC75_SHIFT, GPIO_PIPC7_PIPC75);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC75_SHIFT, GPIO_PMC7_PMC75);
/* ---- P7_6 : DQMLL ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC76_SHIFT, GPIO_PIBC7_PIBC76);
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC76_SHIFT, GPIO_PBDC7_PBDC76);
RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM76_SHIFT, GPIO_PM7_PM76);
RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC76_SHIFT, GPIO_PMC7_PMC76);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC76_SHIFT, GPIO_PIPC7_PIPC76);
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC76_SHIFT, GPIO_PBDC7_PBDC76);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC76_SHIFT, GPIO_PFC7_PFC76);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE76_SHIFT, GPIO_PFCE7_PFCE76);
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE76_SHIFT, GPIO_PFCAE7_PFCAE76);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC76_SHIFT, GPIO_PIPC7_PIPC76);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC76_SHIFT, GPIO_PMC7_PMC76);
/* ---- P7_7 : DQMLU ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC77_SHIFT, GPIO_PIBC7_PIBC77);
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC77_SHIFT, GPIO_PBDC7_PBDC77);
RZA_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM77_SHIFT, GPIO_PM7_PM77);
RZA_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC77_SHIFT, GPIO_PMC7_PMC77);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC77_SHIFT, GPIO_PIPC7_PIPC77);
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC77_SHIFT, GPIO_PBDC7_PBDC77);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC77_SHIFT, GPIO_PFC7_PFC77);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE77_SHIFT, GPIO_PFCE7_PFCE77);
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE77_SHIFT, GPIO_PFCAE7_PFCAE77);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC77_SHIFT, GPIO_PIPC7_PIPC77);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC77_SHIFT, GPIO_PMC7_PMC77);
/* ---- P5_8 : CS2# ---- */
/* Port initialize */
RZA_IO_RegWrite_16(&GPIO.PIBC5, 0, GPIO_PIBC5_PIBC58_SHIFT, GPIO_PIBC5_PIBC58);
RZA_IO_RegWrite_16(&GPIO.PBDC5, 0, GPIO_PBDC5_PBDC58_SHIFT, GPIO_PBDC5_PBDC58);
RZA_IO_RegWrite_16(&GPIO.PM5, 1, GPIO_PM5_PM58_SHIFT, GPIO_PM5_PM58);
RZA_IO_RegWrite_16(&GPIO.PMC5, 0, GPIO_PMC5_PMC58_SHIFT, GPIO_PMC5_PMC58);
RZA_IO_RegWrite_16(&GPIO.PIPC5, 0, GPIO_PIPC5_PIPC58_SHIFT, GPIO_PIPC5_PIPC58);
/* Port mode : Multiplex mode */
/* Port function setting : 6th multiplex function */
/* I/O control mode : Peripheral function */
/* Bidirectional mode : Disable */
RZA_IO_RegWrite_16(&GPIO.PBDC5, 0, GPIO_PBDC5_PBDC58_SHIFT, GPIO_PBDC5_PBDC58);
RZA_IO_RegWrite_16(&GPIO.PFC5, 1, GPIO_PFC5_PFC58_SHIFT, GPIO_PFC5_PFC58);
RZA_IO_RegWrite_16(&GPIO.PFCE5, 0, GPIO_PFCE5_PFCE58_SHIFT, GPIO_PFCE5_PFCE58);
RZA_IO_RegWrite_16(&GPIO.PFCAE5, 1, GPIO_PFCAE5_PFCAE58_SHIFT, GPIO_PFCAE5_PFCAE58);
RZA_IO_RegWrite_16(&GPIO.PIPC5, 1, GPIO_PIPC5_PIPC58_SHIFT, GPIO_PIPC5_PIPC58);
RZA_IO_RegWrite_16(&GPIO.PMC5, 1, GPIO_PMC5_PMC58_SHIFT, GPIO_PMC5_PMC58);
/* ---- P7_1 : CS3# ---- */
/* Port initialize */
// RZA1_IO_RegWrite_16(&GPIO.PIBC7, 0, GPIO_PIBC7_PIBC71_SHIFT, GPIO_PIBC7_PIBC71);
// RZA1_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC71_SHIFT, GPIO_PBDC7_PBDC71);
// RZA1_IO_RegWrite_16(&GPIO.PM7, 1, GPIO_PM7_PM71_SHIFT, GPIO_PM7_PM71);
// RZA1_IO_RegWrite_16(&GPIO.PMC7, 0, GPIO_PMC7_PMC71_SHIFT, GPIO_PMC7_PMC71);
// RZA1_IO_RegWrite_16(&GPIO.PIPC7, 0, GPIO_PIPC7_PIPC71_SHIFT, GPIO_PIPC7_PIPC71);
// /* Port mode : Multiplex mode */
// /* Port function setting : 1st multiplex function */
// /* I/O control mode : Peripheral function */
// /* Bidirectional mode : Disable */
// RZA1_IO_RegWrite_16(&GPIO.PBDC7, 0, GPIO_PBDC7_PBDC71_SHIFT, GPIO_PBDC7_PBDC71);
// RZA1_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC71_SHIFT, GPIO_PFC7_PFC71);
// RZA1_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE71_SHIFT, GPIO_PFCE7_PFCE71);
// RZA1_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE71_SHIFT, GPIO_PFCAE7_PFCAE71);
// RZA1_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC71_SHIFT, GPIO_PIPC7_PIPC71);
// RZA1_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC71_SHIFT, GPIO_PMC7_PMC71);
}
/******************************************************************************
* Function Name: CS2_PORTInit
* Description : Sets the PORT multiplexed pin to use the CS2 and the CS3
* : spaces. In this sample code, the PORT setting is executed to
* : use the NOR flash memory in the CS0 and the CS1 spaces.
* Arguments : none
* Return Value : none
******************************************************************************/
static void CS2_PORTInit(void)
{
/* ---- P6_0 : D0 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE60_SHIFT, GPIO_PFCAE6_PFCAE60);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE60_SHIFT, GPIO_PFCE6_PFCE60);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC60_SHIFT, GPIO_PFC6_PFC60);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC60_SHIFT, GPIO_PMC6_PMC60);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC60_SHIFT, GPIO_PIPC6_PIPC60);
/* ---- P6_1 : D1 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE61_SHIFT, GPIO_PFCAE6_PFCAE61);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE61_SHIFT, GPIO_PFCE6_PFCE61);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC61_SHIFT, GPIO_PFC6_PFC61);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC61_SHIFT, GPIO_PMC6_PMC61);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC61_SHIFT, GPIO_PIPC6_PIPC61);
/* ---- P6_2 : D2 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE62_SHIFT, GPIO_PFCAE6_PFCAE62);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE62_SHIFT, GPIO_PFCE6_PFCE62);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC62_SHIFT, GPIO_PFC6_PFC62);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC62_SHIFT, GPIO_PMC6_PMC62);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC62_SHIFT, GPIO_PIPC6_PIPC62);
/* ---- P6_3 : D3 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE63_SHIFT, GPIO_PFCAE6_PFCAE63);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE63_SHIFT, GPIO_PFCE6_PFCE63);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC63_SHIFT, GPIO_PFC6_PFC63);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC63_SHIFT, GPIO_PMC6_PMC63);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC63_SHIFT, GPIO_PIPC6_PIPC63);
/* ---- P6_4 : D4 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE64_SHIFT, GPIO_PFCAE6_PFCAE64);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE64_SHIFT, GPIO_PFCE6_PFCE64);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC64_SHIFT, GPIO_PFC6_PFC64);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC64_SHIFT, GPIO_PMC6_PMC64);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC64_SHIFT, GPIO_PIPC6_PIPC64);
/* ---- P6_5 : D5 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE65_SHIFT, GPIO_PFCAE6_PFCAE65);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE65_SHIFT, GPIO_PFCE6_PFCE65);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC65_SHIFT, GPIO_PFC6_PFC65);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC65_SHIFT, GPIO_PMC6_PMC65);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC65_SHIFT, GPIO_PIPC6_PIPC65);
/* ---- P6_6 : D6 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE66_SHIFT, GPIO_PFCAE6_PFCAE66);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE66_SHIFT, GPIO_PFCE6_PFCE66);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC66_SHIFT, GPIO_PFC6_PFC66);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC66_SHIFT, GPIO_PMC6_PMC66);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC66_SHIFT, GPIO_PIPC6_PIPC66);
/* ---- P6_7 : D7 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE67_SHIFT, GPIO_PFCAE6_PFCAE67);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE67_SHIFT, GPIO_PFCE6_PFCE67);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC67_SHIFT, GPIO_PFC6_PFC67);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC67_SHIFT, GPIO_PMC6_PMC67);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC67_SHIFT, GPIO_PIPC6_PIPC67);
/* ---- P6_8 : D8 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE68_SHIFT, GPIO_PFCAE6_PFCAE68);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE68_SHIFT, GPIO_PFCE6_PFCE68);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC68_SHIFT, GPIO_PFC6_PFC68);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC68_SHIFT, GPIO_PMC6_PMC68);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC68_SHIFT, GPIO_PIPC6_PIPC68);
/* ---- P6_9 : D9 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE69_SHIFT, GPIO_PFCAE6_PFCAE69);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE69_SHIFT, GPIO_PFCE6_PFCE69);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC69_SHIFT, GPIO_PFC6_PFC69);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC69_SHIFT, GPIO_PMC6_PMC69);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC69_SHIFT, GPIO_PIPC6_PIPC69);
/* ---- P6_10 : D10 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE610_SHIFT, GPIO_PFCAE6_PFCAE610);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE610_SHIFT, GPIO_PFCE6_PFCE610);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC610_SHIFT, GPIO_PFC6_PFC610);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC610_SHIFT, GPIO_PMC6_PMC610);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC610_SHIFT, GPIO_PIPC6_PIPC610);
/* ---- P6_11 : D11 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE611_SHIFT, GPIO_PFCAE6_PFCAE611);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE611_SHIFT, GPIO_PFCE6_PFCE611);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC611_SHIFT, GPIO_PFC6_PFC611);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC611_SHIFT, GPIO_PMC6_PMC611);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC611_SHIFT, GPIO_PIPC6_PIPC611);
/* ---- P6_12 : D12 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE612_SHIFT, GPIO_PFCAE6_PFCAE612);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE612_SHIFT, GPIO_PFCE6_PFCE612);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC612_SHIFT, GPIO_PFC6_PFC612);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC612_SHIFT, GPIO_PMC6_PMC612);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC612_SHIFT, GPIO_PIPC6_PIPC612);
/* ---- P6_13 : D13 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE613_SHIFT, GPIO_PFCAE6_PFCAE613);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE613_SHIFT, GPIO_PFCE6_PFCE613);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC613_SHIFT, GPIO_PFC6_PFC613);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC613_SHIFT, GPIO_PMC6_PMC613);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC613_SHIFT, GPIO_PIPC6_PIPC613);
/* ---- P6_14 : D14 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE614_SHIFT, GPIO_PFCAE6_PFCAE614);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE614_SHIFT, GPIO_PFCE6_PFCE614);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC614_SHIFT, GPIO_PFC6_PFC614);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC614_SHIFT, GPIO_PMC6_PMC614);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC614_SHIFT, GPIO_PIPC6_PIPC614);
/* ---- P6_15 : D15 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE6, 0, GPIO_PFCAE6_PFCAE615_SHIFT, GPIO_PFCAE6_PFCAE615);
RZA_IO_RegWrite_16(&GPIO.PFCE6, 0, GPIO_PFCE6_PFCE615_SHIFT, GPIO_PFCE6_PFCE615);
RZA_IO_RegWrite_16(&GPIO.PFC6, 0, GPIO_PFC6_PFC615_SHIFT, GPIO_PFC6_PFC615);
RZA_IO_RegWrite_16(&GPIO.PMC6, 1, GPIO_PMC6_PMC615_SHIFT, GPIO_PMC6_PMC615);
RZA_IO_RegWrite_16(&GPIO.PIPC6, 1, GPIO_PIPC6_PIPC615_SHIFT, GPIO_PIPC6_PIPC615);
/* ---- P7_9 : A1 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE79_SHIFT, GPIO_PFCAE7_PFCAE79);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE79_SHIFT, GPIO_PFCE7_PFCE79);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC79_SHIFT, GPIO_PFC7_PFC79);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM79_SHIFT, GPIO_PM7_PM79);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC79_SHIFT, GPIO_PMC7_PMC79);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC79_SHIFT, GPIO_PIPC7_PIPC79);
/* ---- P7_10 : A2 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE710_SHIFT, GPIO_PFCAE7_PFCAE710);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE710_SHIFT, GPIO_PFCE7_PFCE710);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC710_SHIFT, GPIO_PFC7_PFC710);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM710_SHIFT, GPIO_PM7_PM710);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC710_SHIFT, GPIO_PMC7_PMC710);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC710_SHIFT, GPIO_PIPC7_PIPC710);
/* ---- P7_11 : A3 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE711_SHIFT, GPIO_PFCAE7_PFCAE711);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE711_SHIFT, GPIO_PFCE7_PFCE711);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC711_SHIFT, GPIO_PFC7_PFC711);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM711_SHIFT, GPIO_PM7_PM711);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC711_SHIFT, GPIO_PMC7_PMC711);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC711_SHIFT, GPIO_PIPC7_PIPC711);
/* ---- P7_12 : A4 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE712_SHIFT, GPIO_PFCAE7_PFCAE712);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE712_SHIFT, GPIO_PFCE7_PFCE712);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC712_SHIFT, GPIO_PFC7_PFC712);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM712_SHIFT, GPIO_PM7_PM712);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC712_SHIFT, GPIO_PMC7_PMC712);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC712_SHIFT, GPIO_PIPC7_PIPC712);
/* ---- P7_13 : A5 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE713_SHIFT, GPIO_PFCAE7_PFCAE713);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE713_SHIFT, GPIO_PFCE7_PFCE713);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC713_SHIFT, GPIO_PFC7_PFC713);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM713_SHIFT, GPIO_PM7_PM713);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC713_SHIFT, GPIO_PMC7_PMC713);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC713_SHIFT, GPIO_PIPC7_PIPC713);
/* ---- P7_14 : A6 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE714_SHIFT, GPIO_PFCAE7_PFCAE714);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE714_SHIFT, GPIO_PFCE7_PFCE714);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC714_SHIFT, GPIO_PFC7_PFC714);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM714_SHIFT, GPIO_PM7_PM714);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC714_SHIFT, GPIO_PMC7_PMC714);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC714_SHIFT, GPIO_PIPC7_PIPC714);
/* ---- P7_15 : A7 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE7, 0, GPIO_PFCAE7_PFCAE715_SHIFT, GPIO_PFCAE7_PFCAE715);
RZA_IO_RegWrite_16(&GPIO.PFCE7, 0, GPIO_PFCE7_PFCE715_SHIFT, GPIO_PFCE7_PFCE715);
RZA_IO_RegWrite_16(&GPIO.PFC7, 0, GPIO_PFC7_PFC715_SHIFT, GPIO_PFC7_PFC715);
RZA_IO_RegWrite_16(&GPIO.PM7, 0, GPIO_PM7_PM715_SHIFT, GPIO_PM7_PM715);
RZA_IO_RegWrite_16(&GPIO.PMC7, 1, GPIO_PMC7_PMC715_SHIFT, GPIO_PMC7_PMC715);
RZA_IO_RegWrite_16(&GPIO.PIPC7, 1, GPIO_PIPC7_PIPC715_SHIFT, GPIO_PIPC7_PIPC715);
/* ---- P8_0 : A8 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE80_SHIFT, GPIO_PFCAE8_PFCAE80);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE80_SHIFT, GPIO_PFCE8_PFCE80);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC80_SHIFT, GPIO_PFC8_PFC80);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC80_SHIFT, GPIO_PMC8_PMC80);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC80_SHIFT, GPIO_PIPC8_PIPC80);
/* ---- P8_1 : A9 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE81_SHIFT, GPIO_PFCAE8_PFCAE81);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE81_SHIFT, GPIO_PFCE8_PFCE81);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC81_SHIFT, GPIO_PFC8_PFC81);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM81_SHIFT, GPIO_PM8_PM81);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC81_SHIFT, GPIO_PMC8_PMC81);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC81_SHIFT, GPIO_PIPC8_PIPC81);
/* ---- P8_2 : A10 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE82_SHIFT, GPIO_PFCAE8_PFCAE82);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE82_SHIFT, GPIO_PFCE8_PFCE82);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC82_SHIFT, GPIO_PFC8_PFC82);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM82_SHIFT, GPIO_PM8_PM82);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC82_SHIFT, GPIO_PMC8_PMC82);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC82_SHIFT, GPIO_PIPC8_PIPC82);
/* ---- P8_3 : A11 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE83_SHIFT, GPIO_PFCAE8_PFCAE83);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE83_SHIFT, GPIO_PFCE8_PFCE83);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC83_SHIFT, GPIO_PFC8_PFC83);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM83_SHIFT, GPIO_PM8_PM83);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC83_SHIFT, GPIO_PMC8_PMC83);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC83_SHIFT, GPIO_PIPC8_PIPC83);
/* ---- P8_4 : A12 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE84_SHIFT, GPIO_PFCAE8_PFCAE84);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE84_SHIFT, GPIO_PFCE8_PFCE84);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC84_SHIFT, GPIO_PFC8_PFC84);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM84_SHIFT, GPIO_PM8_PM84);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC84_SHIFT, GPIO_PMC8_PMC84);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC84_SHIFT, GPIO_PIPC8_PIPC84);
/* ---- P8_5 : A13 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE85_SHIFT, GPIO_PFCAE8_PFCAE85);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE85_SHIFT, GPIO_PFCE8_PFCE85);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC85_SHIFT, GPIO_PFC8_PFC85);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM85_SHIFT, GPIO_PM8_PM85);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC85_SHIFT, GPIO_PMC8_PMC85);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC85_SHIFT, GPIO_PIPC8_PIPC85);
/* ---- P8_6 : A14 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE86_SHIFT, GPIO_PFCAE8_PFCAE86);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE86_SHIFT, GPIO_PFCE8_PFCE86);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC86_SHIFT, GPIO_PFC8_PFC86);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM86_SHIFT, GPIO_PM8_PM86);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC86_SHIFT, GPIO_PMC8_PMC86);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC86_SHIFT, GPIO_PIPC8_PIPC86);
/* ---- P8_7 : A15 ---- */
/* Port mode : Multiplex mode */
/* Port function setting : 1st multiplex function */
/* I/O control mode : Peripheral function */
RZA_IO_RegWrite_16(&GPIO.PFCAE8, 0, GPIO_PFCAE8_PFCAE87_SHIFT, GPIO_PFCAE8_PFCAE87);
RZA_IO_RegWrite_16(&GPIO.PFCE8, 0, GPIO_PFCE8_PFCE87_SHIFT, GPIO_PFCE8_PFCE87);
RZA_IO_RegWrite_16(&GPIO.PFC8, 0, GPIO_PFC8_PFC87_SHIFT, GPIO_PFC8_PFC87);
RZA_IO_RegWrite_16(&GPIO.PM8, 0, GPIO_PM8_PM87_SHIFT, GPIO_PM8_PM87);
RZA_IO_RegWrite_16(&GPIO.PMC8, 1, GPIO_PMC8_PMC87_SHIFT, GPIO_PMC8_PMC87);
RZA_IO_RegWrite_16(&GPIO.PIPC8, 1, GPIO_PIPC8_PIPC87_SHIFT, GPIO_PIPC8_PIPC87);
}
/******************************************************************************
* Function Name: Userdef_BSC_CS2Init
* Description : This is the user-defined function called by the R_BSC_Init
* : function. The setting for initialization of the BSC in the CS2
* : space is required. In this sample code, the setting to use
* : the SDRAM in the CS2 space is executed. Sets the BSC to
* : connect the ISSI IS42S16320B-75 to the CS2 space with 16-bit
* : bus width.
* Arguments : none
* Return Value : none
******************************************************************************/
static void CS2_BSC_Init(void)
{
/* ==== CS2BCR settings ==== */
/* Idle Cycles between Write-read Cycles */
/* and Write-write Cycles : 0 idle cycles */
/* Memory type :SDRAM */
/* Data Bus Size : 16-bit */
BSC.CS2BCR = 0x00004C00ul;
/* ==== CS3BCR settings ==== */
/* SDRAM WORKAROUND - see Note */
/* Idle Cycles between Write-read Cycles */
/* and Write-write Cycles : 0 idle cycles */
/* Memory type :SDRAM */
/* Data Bus Size : 16-bit */
BSC.CS3BCR = 0x00004C00ul;
/* ==== CS2/3WCR settings ==== */
/* Precharge completion wait cycles: 1 cycle */
/* Wait cycles between ACTV command */
/* and READ(A)/WRITE(A) command : 1 cycles */
/* CAS latency for Area 3 : 2 cycles */
/* Auto-precharge startup wait cycles : 2 cycles */
/* Idle cycles from REF command/self-refresh */
/* Release to ACTV/REF/MRS command : 5 cycles */
BSC.CS3WCR = 0x00002492ul;
/* SDRAM WORKAROUND - see Note */
BSC.CS2WCR = 0x00000480ul;
/* ==== SDCR settings ==== */
/* SDRAM WORKAROUND - see Note*/
/* Row address for Area 2 : 13-bit */
/* Column Address for Area 2 : 9-bit */
/* Refresh Control :Refresh */
/* RMODE :Auto-refresh is performed */
/* BACTV :Auto-precharge mode */
/* Row address for Area 3 : 13-bit */
/* Column Address for Area 3 : 9-bit */
BSC.SDCR = 0x00110811ul;
/* ==== RTCOR settings ==== */
/* 7.8usec / 60nsec */
/* = 32(0x40)cycles per refresh */
BSC.RTCOR = 0xA55A0020ul;
/* ==== RTCSR settings ==== */
/* initialisation sequence start */
/* Clock select B-phy/16 */
/* Refresh count :Once */
BSC.RTCSR = 0xA55A0010ul;
/* ==== SDRAM Mode Register ==== */
/* Burst read (burst length 1)./Burst write */
CS2_SDRAM_MODE_16BIT_CAS2_BR_BW = 0;
/* SDRAM WORKAROUND - see Note */
CS3_SDRAM_MODE_16BIT_CAS2_BR_BW = 0;
}
/**************************************************************************//**
* Function Name: RZ_A1_SetSramWriteEnable
* @brief Initialize Board settings
*
* Description:<br>
* Set SRAM write enable
* @param none
* @retval none
******************************************************************************/
void RZ_A1_SetSramWriteEnable(void)
{
/* Enable SRAM write access */
CPG.SYSCR3 = 0x0F;
return;
}
/**************************************************************************//**
* Function Name: RZ_A1_InitClock
* @brief Initialize Board settings
*
* Description:<br>
* Initialize Clock
* @param none
* @retval none
******************************************************************************/
void RZ_A1_InitClock(void)
{
/* Cancel L2C standby status before clock change */
L2CREG15_POWER_CTRL = 0x00000001;
/* Clock settings */
/* ClockMode0 */
CPG.FRQCR = 0x1035; /* CPU Clock =399.99MHz */
CPG.FRQCR2 = 0x0001; /* G Clock =266.66MHz */
return;
}
/**************************************************************************//**
* Function Name: RZ_A1_IsClockMode0
* @brief Query Clock Mode
*
* Description:<br>
* Answer ClockMode0 or not
* @param none
* @retval true : clock mode 0
* @retval false : clock mode 1
******************************************************************************/
int RZ_A1_IsClockMode0(void)
{
/* ClockMode0 */
return true;
}
/**************************************************************************//**
* Function Name: RZ_A1_InitBus
* @brief Initialize Bus
*
* Description:<br>
* Initialize Pin Setting
* @param none
* @retval none
******************************************************************************/
void RZ_A1_InitBus(void)
{
/*************************************************************************/
/* If need Pin Setting before run program, the setting will be wrote here*/
/*************************************************************************/
#if defined(CS2_SDRAM)
PORT_Init();
CS2_PORTInit();
CS2_BSC_Init();
#else
return;
#endif
}
/******************************************************************************
End of file
******************************************************************************/

100
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#! armcc -E -I"../"
;**************************************************
; Copyright (c) 2017 ARM Ltd. All rights reserved.
;**************************************************
; Scatter-file for RTX Example on Versatile Express
; This scatter-file places application code, data, stack and heap at suitable addresses in the memory map.
#include "mbed_config.h"
#ifdef RUN_FROM_SDRAM
#define __ROM_BASE 0x08000000
#define __ROM_SIZE 0x02000000
#define __VECTOR_BASE 0x08000000
#define __DATA_BASE +0 ALIGN 0x100000
#elif defined (RUN_FROM_SRAM)
#define __ROM_BASE 0x200A0000
#define __ROM_SIZE 0x00960000
#define __VECTOR_BASE 0x200A0000
#define __DATA_BASE +0 ALIGN 0x100000 NOCOMPRESS
#else
#define __ROM_BASE 0x18020000
#define __ROM_SIZE 0x01FE0000
#define __VECTOR_BASE 0x18020000
#define __DATA_BASE 0x20020000
#endif
#ifdef RUN_FROM_SDRAM
#define __RAM_BASE 0x08000000
#define __RAM_SIZE 0x02000000
#define __NC_RAM_SIZE 0x00200000
#else
#define __RAM_BASE 0x20000000
#define __RAM_SIZE 0x00A00000
#define __NC_RAM_SIZE 0x00100000
#endif
#define __NM_RAM_SIZE (__RAM_SIZE - __NC_RAM_SIZE)
#define __DATA_NC_BASE (__RAM_BASE + __NM_RAM_SIZE + 0x40000000)
#define __UND_STACK_SIZE 0x00000100
#define __SVC_STACK_SIZE 0x00008000
#define __ABT_STACK_SIZE 0x00000100
#define __FIQ_STACK_SIZE 0x00000100
#define __IRQ_STACK_SIZE 0x0000F000
#define __STACK_SIZE (__UND_STACK_SIZE + __SVC_STACK_SIZE + __ABT_STACK_SIZE + __FIQ_STACK_SIZE + __IRQ_STACK_SIZE)
#define __TTB_BASE 0x20000000
#define __TTB_SIZE 0x00004000
LOAD_TTB __TTB_BASE __TTB_SIZE ; Page 0 of On-Chip Data Retention RAM
{
TTB +0 EMPTY 0x4000
{ } ; Level-1 Translation Table for MMU
}
LR_IROM1 __ROM_BASE __ROM_SIZE ; load region size_region
{
VECTORS __VECTOR_BASE FIXED
{
* (RESET, +FIRST) ; Vector table and other startup code
* (InRoot$$Sections) ; All (library) code that must be in a root region
* (+RO-CODE) ; Application RO code (.text)
}
RO_DATA +0
{ * (+RO-DATA) } ; Application RO data (.constdata)
RW_DATA __DATA_BASE
{ * (+RW) } ; Application RW data (.data)
RW_IRAM1 +0 ALIGN 0x10
{ * (+ZI) } ; Application ZI data (.bss)
ARM_LIB_HEAP +0
{ * (HEAP) } ; Application heap area (HEAP)
ARM_LIB_STACK (__RAM_BASE + __NM_RAM_SIZE) EMPTY -__STACK_SIZE ; Stack region growing down
{ }
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; RAM-NC : Internal non-cached RAM region
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
RW_DATA_NC __DATA_NC_BASE __NC_RAM_SIZE
{ * (NC_DATA) } ; Application RW data Non cached area
ZI_DATA_NC +0
{ * (NC_BSS) } ; Application ZI data Non cached area
}
#ifndef RUN_FROM_SDRAM
SDRAM 0x08000000 0x02000000 ; 32MB External SDRAM region
{
}
#else
SRAM 0x200A0000 0x00960000 ; 9.5MB Internal SRAM region (0.5MB SDCARD Bootloader !!!)
{
}
#endif

151
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/startup_VK_RZ_A1H.S
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@ -1,151 +0,0 @@
;/******************************************************************************
; * @file startup_RZ_A1H.S
; * @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
; *
; * @note
; *
; ******************************************************************************/
;/*
; * Copyright (c) 2009-2017 ARM Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; */
__UND_STACK_SIZE EQU 0x00000100
__SVC_STACK_SIZE EQU 0x00008000
__ABT_STACK_SIZE EQU 0x00000100
__FIQ_STACK_SIZE EQU 0x00000100
__IRQ_STACK_SIZE EQU 0x0000F000
USR_MODE EQU 0x10 ; User mode
FIQ_MODE EQU 0x11 ; Fast Interrupt Request mode
IRQ_MODE EQU 0x12 ; Interrupt Request mode
SVC_MODE EQU 0x13 ; Supervisor mode
ABT_MODE EQU 0x17 ; Abort mode
UND_MODE EQU 0x1B ; Undefined Instruction mode
SYS_MODE EQU 0x1F ; System mode
PRESERVE8
ARM
AREA RESET, CODE, READONLY
Vectors PROC
EXPORT Vectors
IMPORT Undef_Handler
IMPORT SVC_Handler
IMPORT PAbt_Handler
IMPORT DAbt_Handler
IMPORT IRQ_Handler
IMPORT FIQ_Handler
LDR PC, =Reset_Handler
LDR PC, =Undef_Handler
LDR PC, =SVC_Handler
LDR PC, =PAbt_Handler
LDR PC, =DAbt_Handler
NOP
LDR PC, =IRQ_Handler
LDR PC, =FIQ_Handler
ENDP
AREA |.text|, CODE, READONLY
Reset_Handler PROC
EXPORT Reset_Handler
IMPORT SystemInit
IMPORT __main
; Mask interrupts
CPSID if
; Put any cores other than 0 to sleep
MRC p15, 0, R0, c0, c0, 5 ; Read MPIDR
ANDS R0, R0, #3
goToSleep
WFINE
BNE goToSleep
; Reset SCTLR Settings
MRC p15, 0, R0, c1, c0, 0 ; Read CP15 System Control register
BIC R0, R0, #(0x1 << 12) ; Clear I bit 12 to disable I Cache
BIC R0, R0, #(0x1 << 2) ; Clear C bit 2 to disable D Cache
BIC R0, R0, #0x1 ; Clear M bit 0 to disable MMU
BIC R0, R0, #(0x1 << 11) ; Clear Z bit 11 to disable branch prediction
BIC R0, R0, #(0x1 << 13) ; Clear V bit 13 to disable hivecs
MCR p15, 0, R0, c1, c0, 0 ; Write value back to CP15 System Control register
ISB
; Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 ; Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) ; Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 ; Write CP15 Auxiliary Control Register
; Set Vector Base Address Register (VBAR) to point to this application's vector table
LDR R0, =Vectors
MCR p15, 0, R0, c12, c0, 0
; Setup Stack for each exceptional mode
IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit|
LDR R0, =|Image$$ARM_LIB_STACK$$ZI$$Limit|
;Enter Undefined Instruction Mode and set its Stack Pointer
CPS #UND_MODE
MOV SP, R0
SUB R0, R0, #__UND_STACK_SIZE
; Enter Abort Mode and set its Stack Pointer
CPS #ABT_MODE
MOV SP, R0
SUB R0, R0, #__ABT_STACK_SIZE
; Enter FIQ Mode and set its Stack Pointer
CPS #FIQ_MODE
MOV SP, R0
SUB R0, R0, #__FIQ_STACK_SIZE
; Enter IRQ Mode and set its Stack Pointer
CPS #IRQ_MODE
MOV SP, R0
SUB R0, R0, #__IRQ_STACK_SIZE
; Enter Supervisor Mode and set its Stack Pointer
CPS #SVC_MODE
MOV SP, R0
SUB R0, R0, #__SVC_STACK_SIZE
; Enter System Mode to complete initialization and enter kernel
CPS #SYS_MODE
MOV SP, R0
; Call SystemInit
IMPORT SystemInit
BL SystemInit
; Unmask interrupts
CPSIE if
; Call __main
IMPORT __main
BL __main
ENDP
END

61
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/sys.cpp
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@ -1,61 +0,0 @@
/* mbed Microcontroller Library - stackheap
* Setup a fixed single stack/heap memory model,
* between the top of the RW/ZI region and the stackpointer
*******************************************************************************
* Copyright (c) 2017 ARM Limited.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#ifdef __cplusplus
extern "C" {
#endif
#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
#include <arm_compat.h>
#endif
#include <rt_misc.h>
#include <stdint.h>
extern char Image$$ARM_LIB_HEAP$$Base[];
extern char Image$$ARM_LIB_STACK$$Base[];
extern __value_in_regs struct __initial_stackheap _mbed_user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
uint32_t zi_limit = (uint32_t)Image$$ARM_LIB_HEAP$$Base;
uint32_t sp_limit = (uint32_t)Image$$ARM_LIB_STACK$$Base;
zi_limit = (zi_limit + 7) & ~0x7; // ensure zi_limit is 8-byte aligned
struct __initial_stackheap r;
r.heap_base = zi_limit;
r.heap_limit = sp_limit;
return r;
}
#ifdef __cplusplus
}
#endif

91
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_ARM_STD/weak_handler.S
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@ -1,91 +0,0 @@
;/*
; * Copyright (c) 2013-2018 Arm Limited. All rights reserved.
; *
; * SPDX-License-Identifier: Apache-2.0
; *
; * Licensed under the Apache License, Version 2.0 (the License); you may
; * not use this file except in compliance with the License.
; * You may obtain a copy of the License at
; *
; * www.apache.org/licenses/LICENSE-2.0
; *
; * Unless required by applicable law or agreed to in writing, software
; * distributed under the License is distributed on an AS IS BASIS, WITHOUT
; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
; * See the License for the specific language governing permissions and
; * limitations under the License.
; *
; * -----------------------------------------------------------------------------
; *
; * Project: CMSIS-RTOS RTX
; * Title: Cortex-A Exception handlers
; *
; * -----------------------------------------------------------------------------
; */
MODE_SVC EQU 0x13
PRESERVE8
THUMB
AREA |.text|, CODE, READONLY
IRQ_Handler PROC
EXPORT IRQ_Handler [WEAK]
IMPORT IRQ_GetActiveIRQ
IMPORT IRQ_GetHandler
IMPORT IRQ_EndOfInterrupt
SUB LR, LR, #4 ; Pre-adjust LR
SRSFD SP!, #MODE_SVC ; Save LR_irq and SPSR_irq on to the SVC stack
CPS #MODE_SVC ; Change to SVC mode
PUSH {R0-R3, R12, LR} ; Save APCS corruptible registers
MOV R3, SP ; Move SP into R3
AND R3, R3, #4 ; Get stack adjustment to ensure 8-byte alignment
SUB SP, SP, R3 ; Adjust stack
PUSH {R3, R4} ; Store stack adjustment(R3) and user data(R4)
BLX IRQ_GetActiveIRQ ; Retrieve interrupt ID into R0
MOV R4, R0 ; Move interrupt ID to R4
BLX IRQ_GetHandler ; Retrieve interrupt handler address for current ID
CMP R0, #0 ; Check if handler address is 0
BEQ IRQ_End ; If 0, end interrupt and return
CPSIE i ; Re-enable interrupts
BLX R0 ; Call IRQ handler
CPSID i ; Disable interrupts
IRQ_End
MOV R0, R4 ; Move interrupt ID to R0
BLX IRQ_EndOfInterrupt ; Signal end of interrupt
POP {R3, R4} ; Restore stack adjustment(R3) and user data(R4)
ADD SP, SP, R3 ; Unadjust stack
POP {R0-R3, R12, LR} ; Restore stacked APCS registers
RFEFD SP! ; Return from IRQ handler
ENDP
Default_Handler PROC
EXPORT Undef_Handler [WEAK]
EXPORT SVC_Handler [WEAK]
EXPORT PAbt_Handler [WEAK]
EXPORT DAbt_Handler [WEAK]
EXPORT FIQ_Handler [WEAK]
Undef_Handler
SVC_Handler
PAbt_Handler
DAbt_Handler
FIQ_Handler
B .
ENDP
END

241
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/VKRZA1H.ld
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@ -1,241 +0,0 @@
/* Linker script for mbed VK_RZ_A1H */
/* Linker script to configure memory regions. */
/*
#ifdef RUN_FROM_SDRAM
MEMORY
{
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x01E00000
RAM_NC (rwx) : ORIGIN = 0x49E00000, LENGTH = 0x00200000
SRAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00960000
}
REGION_ALIAS("SFLASH", RAM);
TTBOFFSET = 1M;
#elif defined (RUN_FROM_SRAM)
MEMORY
{
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x200A0000, LENGTH = 0x00860000
RAM_NC (rwx) : ORIGIN = 0x60900000, LENGTH = 0x00100000
SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000
}
REGION_ALIAS("SFLASH", RAM);
TTBOFFSET = 1M;
#else
*/
MEMORY
{
ROM (rx) : ORIGIN = 0x00000000, LENGTH = 0x02000000
SFLASH (rx) : ORIGIN = 0x18020000, LENGTH = 0x01FE0000
L_TTB (rw) : ORIGIN = 0x20000000, LENGTH = 0x00004000
RAM (rwx) : ORIGIN = 0x20020000, LENGTH = 0x008E0000
RAM_NC (rwx) : ORIGIN = 0x20900000, LENGTH = 0x00100000
SDRAM (rwx) : ORIGIN = 0x08000000, LENGTH = 0x02000000
}
/*#endif*/
/* Linker script to place sections and symbol values. Should be used together
* with other linker script that defines memory regions FLASH and RAM.
* It references following symbols, which must be defined in code:
* Reset_Handler : Entry of reset handler
*
* It defines following symbols, which code can use without definition:
* __exidx_start
* __exidx_end
* __etext
* __data_start__
* __preinit_array_start
* __preinit_array_end
* __init_array_start
* __init_array_end
* __fini_array_start
* __fini_array_end
* __data_end__
* __bss_start__
* __bss_end__
* __end__
* end
* __HeapLimit
* __StackLimit
* __StackTop
* __stack
*/
ENTRY(Reset_Handler)
SECTIONS
{
.text :
{
Image$$VECTORS$$Base = .;
KEEP(*(.isr_vector))
*(SVC_TABLE)
*(.text*)
KEEP(*(.init))
KEEP(*(.fini))
/* .ctors */
*crtbegin.o(.ctors)
*crtbegin?.o(.ctors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
*(SORT(.ctors.*))
*(.ctors)
/* .dtors */
*crtbegin.o(.dtors)
*crtbegin?.o(.dtors)
*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
*(SORT(.dtors.*))
*(.dtors)
Image$$VECTORS$$Limit = .;
Image$$RO_DATA$$Base = .;
*(.rodata*)
Image$$RO_DATA$$Limit = .;
KEEP(*(.eh_frame*))
} > SFLASH
.ARM.extab :
{
*(.ARM.extab* .gnu.linkonce.armextab.*)
} > SFLASH
__exidx_start = .;
.ARM.exidx :
{
*(.ARM.exidx* .gnu.linkonce.armexidx.*)
} > SFLASH
__exidx_end = .;
.copy.table :
{
. = ALIGN(8);
__copy_table_start__ = .;
LONG (__etext)
LONG (__data_start__)
LONG (__data_end__ - __data_start__)
LONG (__etext2)
LONG (__nc_data_start)
LONG (__nc_data_end - __nc_data_start)
__copy_table_end__ = .;
} > SFLASH
.zero.table :
{
. = ALIGN(8);
__zero_table_start__ = .;
LONG (__bss_start__)
LONG (__bss_end__ - __bss_start__)
LONG (__nc_bss_start)
LONG (__nc_bss_end - __nc_bss_start)
__zero_table_end__ = .;
} > SFLASH
__etext = .;
.ttb :
{
Image$$TTB$$ZI$$Base = .;
. += 0x00004000;
Image$$TTB$$ZI$$Limit = .;
} > L_TTB
.data : AT (__etext)
{
Image$$RW_DATA$$Base = .;
__data_start__ = .;
*(vtable)
*(.data*)
Image$$RW_DATA$$Limit = .;
. = ALIGN(8);
/* preinit data */
PROVIDE (__preinit_array_start = .);
KEEP(*(.preinit_array))
PROVIDE (__preinit_array_end = .);
. = ALIGN(8);
/* init data */
PROVIDE (__init_array_start = .);
KEEP(*(SORT(.init_array.*)))
KEEP(*(.init_array))
PROVIDE (__init_array_end = .);
. = ALIGN(8);
/* finit data */
PROVIDE (__fini_array_start = .);
KEEP(*(SORT(.fini_array.*)))
KEEP(*(.fini_array))
PROVIDE (__fini_array_end = .);
. = ALIGN(8);
/* All data end */
__data_end__ = .;
} > RAM
.bss ALIGN(0x10):
{
Image$$RW_IRAM1$$Base = .;
__bss_start__ = .;
*(.bss*)
*(COMMON)
__bss_end__ = .;
Image$$RW_IRAM1$$Limit = .;
} > RAM
.heap :
{
__end__ = .;
end = __end__;
*(.heap*)
} > RAM
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
} > RAM
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
__StackTop = ORIGIN(RAM) + LENGTH(RAM);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
__HeapLimit = __StackLimit;
PROVIDE(__stack = __StackTop);
/* Check if data + heap + stack exceeds RAM limit */
ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
__etext2 = __etext + SIZEOF(.data);
.nc_data : AT (__etext2)
{
Image$$RW_DATA_NC$$Base = .;
__nc_data_start = .;
*(NC_DATA)
. = ALIGN(8);
__nc_data_end = .;
Image$$RW_DATA_NC$$Limit = .;
} > RAM_NC
.nc_bss (NOLOAD) :
{
Image$$ZI_DATA_NC$$Base = .;
__nc_bss_start = .;
*(NC_BSS)
. = ALIGN(8);
__nc_bss_end = .;
Image$$ZI_DATA_NC$$Limit = .;
} > RAM_NC
}

242
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_GCC_ARM/startup_VKRZ1AH.S
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@ -1,242 +0,0 @@
/* File: startup_ARMCM3.s
* Purpose: startup file for Cortex-M3/M4 devices. Should use with
* GNU Tools for ARM Embedded Processors
* Version: V1.1
* Date: 17 June 2011
*
* Copyright (C) 2011 ARM Limited. All rights reserved.
* ARM Limited (ARM) is supplying this software for use with Cortex-M3/M4
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*/
.syntax unified
.extern _start
@ Standard definitions of mode bits and interrupt (I & F) flags in PSRs
.equ Mode_USR , 0x10
.equ Mode_FIQ , 0x11
.equ Mode_IRQ , 0x12
.equ Mode_SVC , 0x13
.equ Mode_ABT , 0x17
.equ Mode_UND , 0x1B
.equ Mode_SYS , 0x1F
.equ I_Bit , 0x80 @ when I bit is set, IRQ is disabled
.equ F_Bit , 0x40 @ when F bit is set, FIQ is disabled
.equ T_Bit , 0x20 @ when T bit is set, core is in Thumb state
@ Stack Configuration
.EQU UND_Stack_Size , 0x00000100
.EQU SVC_Stack_Size , 0x00008000
.EQU ABT_Stack_Size , 0x00000100
.EQU FIQ_Stack_Size , 0x00000100
.EQU IRQ_Stack_Size , 0x0000F000
.EQU ISR_Stack_Size, (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + FIQ_Stack_Size + IRQ_Stack_Size)
.section .stack
.align 3
.globl __StackTop
.globl __StackLimit
__StackLimit:
.space ISR_Stack_Size
__initial_sp:
.size __StackLimit, . - __StackLimit
__StackTop:
.size __StackTop, . - __StackTop
@ Heap Configuration
.EQU Heap_Size , 0x00080000
.section .heap
.align 3
.globl __HeapBase
.globl __HeapLimit
__HeapBase:
.space Heap_Size
.size __HeapBase, . - __HeapBase
__HeapLimit:
.size __HeapLimit, . - __HeapLimit
.section .isr_vector
.align 2
.globl __isr_vector
__isr_vector:
.long 0xe59ff018 /* 0x00 */
.long 0xe59ff018 /* 0x04 */
.long 0xe59ff018 /* 0x08 */
.long 0xe59ff018 /* 0x0c */
.long 0xe59ff018 /* 0x10 */
.long 0xe59ff018 /* 0x14 */
.long 0xe59ff018 /* 0x18 */
.long 0xe59ff018 /* 0x1c */
.long Reset_Handler /* 0x20 */
.long Undef_Handler /* 0x24 */
.long SVC_Handler /* 0x28 */
.long PAbt_Handler /* 0x2c */
.long DAbt_Handler /* 0x30 */
.long 0 /* Reserved */
.long IRQ_Handler /* IRQ */
.long FIQ_Handler /* FIQ */
.size __isr_vector, . - __isr_vector
.text
.align 2
.globl Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
@ Mask interrupts
CPSID if
@ Put any cores other than 0 to sleep
mrc p15, 0, r0, c0, c0, 5 @ Read MPIDR
ands r0, r0, #3
goToSleep:
wfine
bne goToSleep
@ Reset SCTLR Settings
mrc p15, 0, r0, c1, c0, 0 @ Read CP15 System Control register
bic r0, r0, #(0x1 << 12) @ Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) @ Clear C bit 2 to disable D Cache
bic r0, r0, #0x1 @ Clear M bit 0 to disable MMU
bic r0, r0, #(0x1 << 11) @ Clear Z bit 11 to disable branch prediction
bic r0, r0, #(0x1 << 13) @ Clear V bit 13 to disable hivecs
mcr p15, 0, r0, c1, c0, 0 @ Write value back to CP15 System Control register
isb
@ Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 @ Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) @ Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 @ Write CP15 Auxiliary Control Register
@ Set Vector Base Address Register (VBAR) to point to this application's vector table
ldr r0, =__isr_vector
mcr p15, 0, r0, c12, c0, 0
@ Setup Stack for each exceptional mode
ldr r0, =__StackTop
@ Enter Undefined Instruction Mode and set its Stack Pointer
msr cpsr_c, #(Mode_UND | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #UND_Stack_Size
@ Enter Abort Mode and set its Stack Pointer
msr cpsr_c, #(Mode_ABT | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #ABT_Stack_Size
@ Enter FIQ Mode and set its Stack Pointer
msr cpsr_c, #(Mode_FIQ | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #FIQ_Stack_Size
@ Enter IRQ Mode and set its Stack Pointer
msr cpsr_c, #(Mode_IRQ | I_Bit | F_Bit)
mov sp, r0
sub r0, r0, #IRQ_Stack_Size
@ Enter Supervisor Mode and set its Stack Pointer
msr cpsr_c, #(Mode_SVC | I_Bit | F_Bit)
mov sp, r0
@ Enter System Mode to complete initialization and enter kernel
msr cpsr_c, #(Mode_SYS | I_Bit | F_Bit)
mov sp, r0
@ USR/SYS stack pointer will be set during kernel init
ldr r0, =SystemInit
blx r0
@ Unmask interrupts
CPSIE if
@ data sections copy
ldr r4, =__copy_table_start__
ldr r5, =__copy_table_end__
.L_loop0:
cmp r4, r5
bge .L_loop0_done
ldr r1, [r4]
ldr r2, [r4, #4]
ldr r3, [r4, #8]
.L_loop0_0:
subs r3, #4
ittt ge
ldrge r0, [r1, r3]
strge r0, [r2, r3]
bge .L_loop0_0
adds r4, #12
b .L_loop0
.L_loop0_done:
@ bss sections clear
ldr r3, =__zero_table_start__
ldr r4, =__zero_table_end__
.L_loop2:
cmp r3, r4
bge .L_loop2_done
ldr r1, [r3]
ldr r2, [r3, #4]
movs r0, 0
.L_loop2_0:
subs r2, #4
itt ge
strge r0, [r1, r2]
bge .L_loop2_0
adds r3, #8
b .L_loop2
.L_loop2_done:
ldr r0, =_start
bx r0
.pool
.size Reset_Handler, . - Reset_Handler
.text
/* Macro to define default handlers. Default handler
* will be weak symbol and just dead loops. They can be
* overwritten by other handlers */
.macro def_default_handler handler_name
.align 1
.thumb_func
.weak \handler_name
.type \handler_name, %function
\handler_name :
b .
.size \handler_name, . - \handler_name
.endm
def_default_handler Undef_Handler
def_default_handler SVC_Handler
def_default_handler PAbt_Handler
def_default_handler DAbt_Handler
def_default_handler IRQ_Handler
def_default_handler FIQ_Handler
.END

66
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/VKRZA1H.icf
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@ -1,66 +0,0 @@
/*###ICF### Section handled by ICF editor, don't touch! ****/
/*-Editor annotation file-*/
/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\a_v1_0.xml" */
/*-Specials-*/
define symbol __ICFEDIT_intvec_start__ = 0x18020000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x18020000;
define symbol __ICFEDIT_region_ROM_end__ = 0x19FFFFFF;
define symbol __ICFEDIT_region_TTB_start__ = 0x20000000;
define symbol __ICFEDIT_region_TTB_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x20020000;
define symbol __ICFEDIT_region_RAM_end__ = 0x209FFFFF;
define symbol __ICFEDIT_region_SDRAM_start__ = 0x08000000;
define symbol __ICFEDIT_region_SDRAM_end__ = 0x09FFFFFF;
/*-Sizes-*/
define symbol __ICFEDIT_size_cstack__ = 0x00004000;
define symbol __ICFEDIT_size_svcstack__ = 0x00008000;
define symbol __ICFEDIT_size_irqstack__ = 0x00008000;
define symbol __ICFEDIT_size_fiqstack__ = 0x00000100;
define symbol __ICFEDIT_size_undstack__ = 0x00000100;
define symbol __ICFEDIT_size_abtstack__ = 0x00000100;
define symbol __ICFEDIT_size_heap__ = 0x00080000;
/**** End of ICF editor section. ###ICF###*/
define symbol __ICFEDIT_region_RetRAM_start__ = 0x20000000;
define symbol __ICFEDIT_region_RetRAM_end__ = 0x2001FFFF;
define symbol __ICFEDIT_region_MirrorRAM_start__ = 0x60900000;
define symbol __ICFEDIT_region_MirrorRAM_end__ = 0x609FFFFF;
define symbol __ICFEDIT_region_MirrorRetRAM_start__ = 0x60000000;
define symbol __ICFEDIT_region_MirrorRetRAM_end__ = 0x6001FFFF;
define memory mem with size = 4G;
define region ROM_region = mem:[from __ICFEDIT_region_ROM_start__ to __ICFEDIT_region_ROM_end__];
define region RAM_region = mem:[from __ICFEDIT_region_RAM_start__ to __ICFEDIT_region_RAM_end__];
define region SDRAM_region = mem:[from __ICFEDIT_region_SDRAM_start__ to __ICFEDIT_region_SDRAM_end__];
define region RetRAM_region = mem:[from __ICFEDIT_region_RetRAM_start__ to __ICFEDIT_region_RetRAM_end__];
define region MirrorRAM_region = mem:[from __ICFEDIT_region_MirrorRAM_start__ to __ICFEDIT_region_MirrorRAM_end__];
define region MirrorRetRAM_region = mem:[from __ICFEDIT_region_MirrorRetRAM_start__ to __ICFEDIT_region_MirrorRetRAM_end__];
define block ROM_FIXED_ORDER with fixed order { ro code, ro data };
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block SVC_STACK with alignment = 8, size = __ICFEDIT_size_svcstack__ { };
define block IRQ_STACK with alignment = 8, size = __ICFEDIT_size_irqstack__ { };
define block FIQ_STACK with alignment = 8, size = __ICFEDIT_size_fiqstack__ { };
define block UND_STACK with alignment = 8, size = __ICFEDIT_size_undstack__ { };
define block ABT_STACK with alignment = 8, size = __ICFEDIT_size_abtstack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
initialize by copy { readwrite };
do not initialize { section .noinit };
do not initialize { section .retram };
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in ROM_region { readonly, block ROM_FIXED_ORDER };
place in RAM_region { readwrite,
block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
block UND_STACK, block ABT_STACK, block HEAP };
place in RetRAM_region { section .retram };
place in MirrorRAM_region { section .mirrorram };
place in MirrorRetRAM_region { section .mirrorretram };

218
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/TOOLCHAIN_IAR/startup_VKRZA1H.S
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@ -1,218 +0,0 @@
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Part one of the system initialization code,
;; contains low-level
;; initialization.
;;
;; Copyright 2007 IAR Systems. All rights reserved.
;;
;; $Revision: 49919 $
;;
MODULE ?cstartup
;; Forward declaration of sections.
SECTION SVC_STACK:DATA:NOROOT(3)
SECTION IRQ_STACK:DATA:NOROOT(3)
SECTION ABT_STACK:DATA:NOROOT(3)
SECTION FIQ_STACK:DATA:NOROOT(3)
SECTION UND_STACK:DATA:NOROOT(3)
SECTION CSTACK:DATA:NOROOT(3)
;
; The module in this file are included in the libraries, and may be
; replaced by any user-defined modules that define the PUBLIC symbol
; __iar_program_start or a user defined start symbol.
;
; To override the cstartup defined in the library, simply add your
; modified version to the workbench project.
SECTION .intvec:CODE:NOROOT(2)
PUBLIC __vector_table
PUBLIC __RST_Handler
EXTERN Undef_Handler
EXTERN SVC_Handler
EXTERN PAbt_Handler
EXTERN DAbt_Handler
EXTERN IRQ_Handler
PUBLIC FIQ_Handler
DATA
__iar_init$$done: ; The vector table is not needed
; until after copy initialization is done
__vector_table: ; Make this a DATA label, so that stack usage
; analysis doesn't consider it an uncalled fun
ARM
; All default exception handlers (except reset) are
; defined as weak symbol definitions.
; If a handler is defined by the application it will take precedence.
LDR PC,Reset_Addr ; Reset
LDR PC,Undefined_Addr ; Undefined instructions
LDR PC,SWI_Addr ; Software interrupt (SWI/SVC)
LDR PC,Prefetch_Addr ; Prefetch abort
LDR PC,Abort_Addr ; Data abort
DCD 0 ; RESERVED
LDR PC,IRQ_Addr ; IRQ
LDR PC,FIQ_Addr ; FIQ
DATA
Reset_Addr: DCD __RST_Handler
Undefined_Addr: DCD Undef_Handler
SWI_Addr: DCD SVC_Handler
Prefetch_Addr: DCD PAbt_Handler
Abort_Addr: DCD DAbt_Handler
IRQ_Addr: DCD IRQ_Handler
FIQ_Addr: DCD FIQ_Handler
; --------------------------------------------------
; ?cstartup -- low-level system initialization code.
;
; After a reset execution starts here, the mode is ARM, supervisor
; with interrupts disabled.
;
SECTION .text:CODE:NOROOT(2)
EXTERN SystemInit
EXTERN __iar_program_start
REQUIRE __vector_table
EXTWEAK __iar_init_core
EXTWEAK __iar_init_vfp
ARM
__RST_Handler:
?cstartup:
;;; @ Mask interrupts
CPSID if
;;; @ Put any cores other than 0 to sleep
mrc p15, 0, r0, c0, c0, 5 ;;; @ Read MPIDR
ands r0, r0, #3
goToSleep:
wfine
bne goToSleep
;;; @ Reset SCTLR Settings
mrc p15, 0, r0, c1, c0, 0 ;@ Read CP15 System Control register
bic r0, r0, #(0x1 << 12) ;@ Clear I bit 12 to disable I Cache
bic r0, r0, #(0x1 << 2) ;@ Clear C bit 2 to disable D Cache
bic r0, r0, #0x1 ;@ Clear M bit 0 to disable MMU
bic r0, r0, #(0x1 << 11) ;@ Clear Z bit 11 to disable branch prediction
bic r0, r0, #(0x1 << 13) ;@ Clear V bit 13 to disable hivecs
mcr p15, 0, r0, c1, c0, 0 ;@ Write value back to CP15 System Control register
isb
;;; @ Configure ACTLR
MRC p15, 0, r0, c1, c0, 1 ;@ Read CP15 Auxiliary Control Register
ORR r0, r0, #(1 << 1) ;@ Enable L2 prefetch hint (UNK/WI since r4p1)
MCR p15, 0, r0, c1, c0, 1 ;@ Write CP15 Auxiliary Control Register
;; Set Vector Base Address Register (VBAR) to point to this application's vector table
ldr r0, =__vector_table
mcr p15, 0, r0, c12, c0, 0
;
; Add initialization needed before setup of stackpointers here.
;
;
; Initialize the stack pointers.
; The pattern below can be used for any of the exception stacks:
; FIQ, IRQ, SVC, ABT, UND, SYS.
; The USR mode uses the same stack as SYS.
; The stack segments must be defined in the linker command file,
; and be declared above.
;
; --------------------
; Mode, correspords to bits 0-5 in CPSR
#define MODE_MSK 0x1F ; Bit mask for mode bits in CPSR
#define USR_MODE 0x10 ; User mode
#define FIQ_MODE 0x11 ; Fast Interrupt Request mode
#define IRQ_MODE 0x12 ; Interrupt Request mode
#define SVC_MODE 0x13 ; Supervisor mode
#define ABT_MODE 0x17 ; Abort mode
#define UND_MODE 0x1B ; Undefined Instruction mode
#define SYS_MODE 0x1F ; System mode
MRS r0, cpsr ; Original PSR value
;; Set up the SVC stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #SVC_MODE ; Set SVC mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(SVC_STACK) ; End of SVC_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the interrupt stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #IRQ_MODE ; Set IRQ mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(IRQ_STACK) ; End of IRQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the fast interrupt stack pointer.
BIC r0, r0, #MODE_MSK ; Clear the mode bits
ORR r0, r0, #FIQ_MODE ; Set FIR mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(FIQ_STACK) ; End of FIQ_STACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the ABT stack pointer.
BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
ORR r0 ,r0, #ABT_MODE ; Set System mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(ABT_STACK) ; End of CSTACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the UDF stack pointer.
BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
ORR r0 ,r0, #UND_MODE ; Set System mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(UND_STACK) ; End of CSTACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;; Set up the normal stack pointer.
BIC r0 ,r0, #MODE_MSK ; Clear the mode bits
ORR r0 ,r0, #SYS_MODE ; Set System mode bits
MSR cpsr_c, r0 ; Change the mode
LDR sp, =SFE(CSTACK) ; End of CSTACK
BIC sp,sp,#0x7 ; Make sure SP is 8 aligned
;;;
; USR/SYS stack pointer will be set during kernel init
ldr r0, =SystemInit
blx r0
;;; Continue to __cmain for C-level initialization.
FUNCALL __RST_Handler, __iar_program_start
B __iar_program_start
FIQ_Handler:
B .
END

1
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/VKRZA1H.h
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@ -1 +0,0 @@
#include "VK_RZ_A1H.h"

13
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis.h
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@ -1,13 +0,0 @@
/* mbed Microcontroller Library - CMSIS
* Copyright (C) 2009-2011 ARM Limited. All rights reserved.
*
* A generic CMSIS include header, pulling in LPC1768 specifics
*/
#ifndef MBED_CMSIS_H
#define MBED_CMSIS_H
#include "VKRZA1H.h"
#include "cmsis_nvic.h"
#endif

43
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/cmsis_nvic.c
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@ -1,43 +0,0 @@
/* mbed Microcontroller Library
* CMSIS-style functionality to support dynamic vectors
*******************************************************************************
* Copyright (c) 2015 ARM Limited. All rights reserved.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of ARM Limited nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*******************************************************************************
*/
#include "VKRZA1H.h"
#include "irq_ctrl.h"
void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
{
InterruptHandlerRegister(IRQn, (IRQHandler)vector);
}
uint32_t NVIC_GetVector(IRQn_Type IRQn)
{
uint32_t vectors = (uint32_t)IRQ_GetHandler(IRQn);
return vectors;
}

922
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/VK_RZ_A1H.h
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@ -1,922 +0,0 @@
/******************************************************************************
* @file VK_RZ_A1H.h
* @brief CMSIS Cortex-A9 Core Peripheral Access Layer Header File
* @version V1.00
* @data 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __VK_RZ_A1H_H__
#define __VK_RZ_A1H_H__
#ifdef __cplusplus
extern "C" {
#endif
/* ------------------------- Interrupt Number Definition ------------------------ */
typedef enum IRQn
{
/****** SGI Interrupts Numbers ****************************************/
SGI0_IRQn = 0,
SGI1_IRQn = 1,
SGI2_IRQn = 2,
SGI3_IRQn = 3,
SGI4_IRQn = 4,
SGI5_IRQn = 5,
SGI6_IRQn = 6,
SGI7_IRQn = 7,
SGI8_IRQn = 8,
SGI9_IRQn = 9,
SGI10_IRQn = 10,
SGI11_IRQn = 11,
SGI12_IRQn = 12,
SGI13_IRQn = 13,
SGI14_IRQn = 14,
SGI15_IRQn = 15,
/****** Cortex-A9 Processor Exceptions Numbers ****************************************/
/* 16 - 578 */
PMUIRQ0_IRQn = 16,
COMMRX0_IRQn = 17,
COMMTX0_IRQn = 18,
CTIIRQ0_IRQn = 19,
IRQ0_IRQn = 32,
IRQ1_IRQn = 33,
IRQ2_IRQn = 34,
IRQ3_IRQn = 35,
IRQ4_IRQn = 36,
IRQ5_IRQn = 37,
IRQ6_IRQn = 38,
IRQ7_IRQn = 39,
PL310ERR_IRQn = 40,
DMAINT0_IRQn = 41, /*!< DMAC Interrupt */
DMAINT1_IRQn = 42, /*!< DMAC Interrupt */
DMAINT2_IRQn = 43, /*!< DMAC Interrupt */
DMAINT3_IRQn = 44, /*!< DMAC Interrupt */
DMAINT4_IRQn = 45, /*!< DMAC Interrupt */
DMAINT5_IRQn = 46, /*!< DMAC Interrupt */
DMAINT6_IRQn = 47, /*!< DMAC Interrupt */
DMAINT7_IRQn = 48, /*!< DMAC Interrupt */
DMAINT8_IRQn = 49, /*!< DMAC Interrupt */
DMAINT9_IRQn = 50, /*!< DMAC Interrupt */
DMAINT10_IRQn = 51, /*!< DMAC Interrupt */
DMAINT11_IRQn = 52, /*!< DMAC Interrupt */
DMAINT12_IRQn = 53, /*!< DMAC Interrupt */
DMAINT13_IRQn = 54, /*!< DMAC Interrupt */
DMAINT14_IRQn = 55, /*!< DMAC Interrupt */
DMAINT15_IRQn = 56, /*!< DMAC Interrupt */
DMAERR_IRQn = 57, /*!< DMAC Interrupt */
/* 58-72 Reserved */
USBI0_IRQn = 73,
USBI1_IRQn = 74,
S0_VI_VSYNC0_IRQn = 75,
S0_LO_VSYNC0_IRQn = 76,
S0_VSYNCERR0_IRQn = 77,
GR3_VLINE0_IRQn = 78,
S0_VFIELD0_IRQn = 79,
IV1_VBUFERR0_IRQn = 80,
IV3_VBUFERR0_IRQn = 81,
IV5_VBUFERR0_IRQn = 82,
IV6_VBUFERR0_IRQn = 83,
S0_WLINE0_IRQn = 84,
S1_VI_VSYNC0_IRQn = 85,
S1_LO_VSYNC0_IRQn = 86,
S1_VSYNCERR0_IRQn = 87,
S1_VFIELD0_IRQn = 88,
IV2_VBUFERR0_IRQn = 89,
IV4_VBUFERR0_IRQn = 90,
S1_WLINE0_IRQn = 91,
OIR_VI_VSYNC0_IRQn = 92,
OIR_LO_VSYNC0_IRQn = 93,
OIR_VSYNCERR0_IRQn = 94,
OIR_VFIELD0_IRQn = 95,
IV7_VBUFERR0_IRQn = 96,
IV8_VBUFERR0_IRQn = 97,
/* 98 Reserved */
S0_VI_VSYNC1_IRQn = 99,
S0_LO_VSYNC1_IRQn = 100,
S0_VSYNCERR1_IRQn = 101,
GR3_VLINE1_IRQn = 102,
S0_VFIELD1_IRQn = 103,
IV1_VBUFERR1_IRQn = 104,
IV3_VBUFERR1_IRQn = 105,
IV5_VBUFERR1_IRQn = 106,
IV6_VBUFERR1_IRQn = 107,
S0_WLINE1_IRQn = 108,
S1_VI_VSYNC1_IRQn = 109,
S1_LO_VSYNC1_IRQn = 110,
S1_VSYNCERR1_IRQn = 111,
S1_VFIELD1_IRQn = 112,
IV2_VBUFERR1_IRQn = 113,
IV4_VBUFERR1_IRQn = 114,
S1_WLINE1_IRQn = 115,
OIR_VI_VSYNC1_IRQn = 116,
OIR_LO_VSYNC1_IRQn = 117,
OIR_VSYNCERR1_IRQn = 118,
OIR_VFIELD1_IRQn = 119,
IV7_VBUFERR1_IRQn = 120,
IV8_VBUFERR1_IRQn = 121,
/* Reserved = 122 */
IMRDI_IRQn = 123,
IMR2I0_IRQn = 124,
IMR2I1_IRQn = 125,
JEDI_IRQn = 126,
JDTI_IRQn = 127,
CMP0_IRQn = 128,
CMP1_IRQn = 129,
INT0_IRQn = 130,
INT1_IRQn = 131,
INT2_IRQn = 132,
INT3_IRQn = 133,
OSTMI0TINT_IRQn = 134, /*!< OSTM Interrupt */
OSTMI1TINT_IRQn = 135, /*!< OSTM Interrupt */
CMI_IRQn = 136,
WTOUT_IRQn = 137,
ITI_IRQn = 138,
TGI0A_IRQn = 139,
TGI0B_IRQn = 140,
TGI0C_IRQn = 141,
TGI0D_IRQn = 142,
TGI0V_IRQn = 143,
TGI0E_IRQn = 144,
TGI0F_IRQn = 145,
TGI1A_IRQn = 146,
TGI1B_IRQn = 147,
TGI1V_IRQn = 148,
TGI1U_IRQn = 149,
TGI2A_IRQn = 150,
TGI2B_IRQn = 151,
TGI2V_IRQn = 152,
TGI2U_IRQn = 153,
TGI3A_IRQn = 154,
TGI3B_IRQn = 155,
TGI3C_IRQn = 156,
TGI3D_IRQn = 157,
TGI3V_IRQn = 158,
TGI4A_IRQn = 159,
TGI4B_IRQn = 160,
TGI4C_IRQn = 161,
TGI4D_IRQn = 162,
TGI4V_IRQn = 163,
CMI1_IRQn = 164,
CMI2_IRQn = 165,
SGDEI0_IRQn = 166,
SGDEI1_IRQn = 167,
SGDEI2_IRQn = 168,
SGDEI3_IRQn = 169,
ADI_IRQn = 170,
LMTI_IRQn = 171,
SSII0_IRQn = 172, /*!< SSIF Interrupt */
SSIRXI0_IRQn = 173, /*!< SSIF Interrupt */
SSITXI0_IRQn = 174, /*!< SSIF Interrupt */
SSII1_IRQn = 175, /*!< SSIF Interrupt */
SSIRXI1_IRQn = 176, /*!< SSIF Interrupt */
SSITXI1_IRQn = 177, /*!< SSIF Interrupt */
SSII2_IRQn = 178, /*!< SSIF Interrupt */
SSIRTI2_IRQn = 179, /*!< SSIF Interrupt */
SSII3_IRQn = 180, /*!< SSIF Interrupt */
SSIRXI3_IRQn = 181, /*!< SSIF Interrupt */
SSITXI3_IRQn = 182, /*!< SSIF Interrupt */
SSII4_IRQn = 183, /*!< SSIF Interrupt */
SSIRTI4_IRQn = 184, /*!< SSIF Interrupt */
SSII5_IRQn = 185, /*!< SSIF Interrupt */
SSIRXI5_IRQn = 186, /*!< SSIF Interrupt */
SSITXI5_IRQn = 187, /*!< SSIF Interrupt */
SPDIFI_IRQn = 188,
INTIICTEI0_IRQn = 189, /*!< RIIC Interrupt */
INTIICRI0_IRQn = 190, /*!< RIIC Interrupt */
INTIICTI0_IRQn = 191, /*!< RIIC Interrupt */
INTIICSPI0_IRQn = 192, /*!< RIIC Interrupt */
INTIICSTI0_IRQn = 193, /*!< RIIC Interrupt */
INTIICNAKI0_IRQn = 194, /*!< RIIC Interrupt */
INTIICALI0_IRQn = 195, /*!< RIIC Interrupt */
INTIICTMOI0_IRQn = 196, /*!< RIIC Interrupt */
INTIICTEI1_IRQn = 197, /*!< RIIC Interrupt */
INTIICRI1_IRQn = 198, /*!< RIIC Interrupt */
INTIICTI1_IRQn = 199, /*!< RIIC Interrupt */
INTIICSPI1_IRQn = 200, /*!< RIIC Interrupt */
INTIICSTI1_IRQn = 201, /*!< RIIC Interrupt */
INTIICNAKI1_IRQn = 202, /*!< RIIC Interrupt */
INTIICALI1_IRQn = 203, /*!< RIIC Interrupt */
INTIICTMOI1_IRQn = 204, /*!< RIIC Interrupt */
INTIICTEI2_IRQn = 205, /*!< RIIC Interrupt */
INTIICRI2_IRQn = 206, /*!< RIIC Interrupt */
INTIICTI2_IRQn = 207, /*!< RIIC Interrupt */
INTIICSPI2_IRQn = 208, /*!< RIIC Interrupt */
INTIICSTI2_IRQn = 209, /*!< RIIC Interrupt */
INTIICNAKI2_IRQn = 210, /*!< RIIC Interrupt */
INTIICALI2_IRQn = 211, /*!< RIIC Interrupt */
INTIICTMOI2_IRQn = 212, /*!< RIIC Interrupt */
INTIICTEI3_IRQn = 213, /*!< RIIC Interrupt */
INTIICRI3_IRQn = 214, /*!< RIIC Interrupt */
INTIICTI3_IRQn = 215, /*!< RIIC Interrupt */
INTIICSPI3_IRQn = 216, /*!< RIIC Interrupt */
INTIICSTI3_IRQn = 217, /*!< RIIC Interrupt */
INTIICNAKI3_IRQn = 218, /*!< RIIC Interrupt */
INTIICALI3_IRQn = 219, /*!< RIIC Interrupt */
INTIICTMOI3_IRQn = 220, /*!< RIIC Interrupt */
SCIFBRI0_IRQn = 221, /*!< SCIF Interrupt */
SCIFERI0_IRQn = 222, /*!< SCIF Interrupt */
SCIFRXI0_IRQn = 223, /*!< SCIF Interrupt */
SCIFTXI0_IRQn = 224, /*!< SCIF Interrupt */
SCIFBRI1_IRQn = 225, /*!< SCIF Interrupt */
SCIFERI1_IRQn = 226, /*!< SCIF Interrupt */
SCIFRXI1_IRQn = 227, /*!< SCIF Interrupt */
SCIFTXI1_IRQn = 228, /*!< SCIF Interrupt */
SCIFBRI2_IRQn = 229, /*!< SCIF Interrupt */
SCIFERI2_IRQn = 230, /*!< SCIF Interrupt */
SCIFRXI2_IRQn = 231, /*!< SCIF Interrupt */
SCIFTXI2_IRQn = 232, /*!< SCIF Interrupt */
SCIFBRI3_IRQn = 233, /*!< SCIF Interrupt */
SCIFERI3_IRQn = 234, /*!< SCIF Interrupt */
SCIFRXI3_IRQn = 235, /*!< SCIF Interrupt */
SCIFTXI3_IRQn = 236, /*!< SCIF Interrupt */
SCIFBRI4_IRQn = 237, /*!< SCIF Interrupt */
SCIFERI4_IRQn = 238, /*!< SCIF Interrupt */
SCIFRXI4_IRQn = 239, /*!< SCIF Interrupt */
SCIFTXI4_IRQn = 240, /*!< SCIF Interrupt */
SCIFBRI5_IRQn = 241, /*!< SCIF Interrupt */
SCIFERI5_IRQn = 242, /*!< SCIF Interrupt */
SCIFRXI5_IRQn = 243, /*!< SCIF Interrupt */
SCIFTXI5_IRQn = 244, /*!< SCIF Interrupt */
SCIFBRI6_IRQn = 245, /*!< SCIF Interrupt */
SCIFERI6_IRQn = 246, /*!< SCIF Interrupt */
SCIFRXI6_IRQn = 247, /*!< SCIF Interrupt */
SCIFTXI6_IRQn = 248, /*!< SCIF Interrupt */
SCIFBRI7_IRQn = 249, /*!< SCIF Interrupt */
SCIFERI7_IRQn = 250, /*!< SCIF Interrupt */
SCIFRXI7_IRQn = 251, /*!< SCIF Interrupt */
SCIFTXI7_IRQn = 252, /*!< SCIF Interrupt */
INTRCANGERR_IRQn = 253,
INTRCANGRECC_IRQn = 254,
INTRCAN0REC_IRQn = 255,
INTRCAN0ERR_IRQn = 256,
INTRCAN0TRX_IRQn = 257,
INTRCAN1REC_IRQn = 258,
INTRCAN1ERR_IRQn = 259,
INTRCAN1TRX_IRQn = 260,
INTRCAN2REC_IRQn = 261,
INTRCAN2ERR_IRQn = 262,
INTRCAN2TRX_IRQn = 263,
INTRCAN3REC_IRQn = 264,
INTRCAN3ERR_IRQn = 265,
INTRCAN3TRX_IRQn = 266,
INTRCAN4REC_IRQn = 267,
INTRCAN4ERR_IRQn = 268,
INTRCAN4TRX_IRQn = 269,
RSPISPEI0_IRQn = 270, /*!< RSPI Interrupt */
RSPISPRI0_IRQn = 271, /*!< RSPI Interrupt */
RSPISPTI0_IRQn = 272, /*!< RSPI Interrupt */
RSPISPEI1_IRQn = 273, /*!< RSPI Interrupt */
RSPISPRI1_IRQn = 274, /*!< RSPI Interrupt */
RSPISPTI1_IRQn = 275, /*!< RSPI Interrupt */
RSPISPEI2_IRQn = 276, /*!< RSPI Interrupt */
RSPISPRI2_IRQn = 277, /*!< RSPI Interrupt */
RSPISPTI2_IRQn = 278, /*!< RSPI Interrupt */
RSPISPEI3_IRQn = 279, /*!< RSPI Interrupt */
RSPISPRI3_IRQn = 280, /*!< RSPI Interrupt */
RSPISPTI3_IRQn = 281, /*!< RSPI Interrupt */
RSPISPEI4_IRQn = 282, /*!< RSPI Interrupt */
RSPISPRI4_IRQn = 283, /*!< RSPI Interrupt */
RSPISPTI4_IRQn = 284, /*!< RSPI Interrupt */
IEBBTD_IRQn = 285,
IEBBTERR_IRQn = 286,
IEBBTSTA_IRQn = 287,
IEBBTV_IRQn = 288,
ISY_IRQn = 289,
IERR_IRQn = 290,
ITARG_IRQn = 291,
ISEC_IRQn = 292,
IBUF_IRQn = 293,
IREADY_IRQn = 294,
STERB_IRQn = 295,
FLTENDI_IRQn = 296,
FLTREQ0I_IRQn = 297,
FLTREQ1I_IRQn = 298,
MMC0_IRQn = 299,
MMC1_IRQn = 300,
MMC2_IRQn = 301,
SCHI0_3_IRQn = 302,
SDHI0_0_IRQn = 303,
SDHI0_1_IRQn = 304,
SCHI1_3_IRQn = 305,
SDHI1_0_IRQn = 306,
SDHI1_1_IRQn = 307,
ARM_IRQn = 308,
PRD_IRQn = 309,
CUP_IRQn = 310,
SCUAI0_IRQn = 311,
SCUAI1_IRQn = 312,
SCUFDI0_IRQn = 313,
SCUFDI1_IRQn = 314,
SCUFDI2_IRQn = 315,
SCUFDI3_IRQn = 316,
SCUFUI0_IRQn = 317,
SCUFUI1_IRQn = 318,
SCUFUI2_IRQn = 319,
SCUFUI3_IRQn = 320,
SCUDVI0_IRQn = 321,
SCUDVI1_IRQn = 322,
SCUDVI2_IRQn = 323,
SCUDVI3_IRQn = 324,
MLB_CINT_IRQn = 325,
MLB_SINT_IRQn = 326,
DRC10_IRQn = 327,
DRC11_IRQn = 328,
/* 329-330 Reserved */
LINI0_INT_T_IRQn = 331,
LINI0_INT_R_IRQn = 332,
LINI0_INT_S_IRQn = 333,
LINI0_INT_M_IRQn = 334,
LINI1_INT_T_IRQn = 335,
LINI1_INT_R_IRQn = 336,
LINI1_INT_S_IRQn = 337,
LINI1_INT_M_IRQn = 338,
/* 339-346 Reserved */
SCIERI0_IRQn = 347,
SCIRXI0_IRQn = 348,
SCITXI0_IRQn = 349,
SCITEI0_IRQn = 350,
SCIERI1_IRQn = 351,
SCIRXI1_IRQn = 352,
SCITXI1_IRQn = 353,
SCITEI1_IRQn = 354,
AVBI_DATA = 355,
AVBI_ERROR = 356,
AVBI_MANAGE = 357,
AVBI_MAC = 358,
ETHERI_IRQn = 359,
/* 360-363 Reserved */
CEUI_IRQn = 364,
/* 365-380 Reserved */
H2XMLB_ERRINT_IRQn = 381,
H2XIC1_ERRINT_IRQn = 382,
X2HPERI1_ERRINT_IRQn = 383,
X2HPERR2_ERRINT_IRQn = 384,
X2HPERR34_ERRINT_IRQn= 385,
X2HPERR5_ERRINT_IRQn = 386,
X2HPERR67_ERRINT_IRQn= 387,
X2HDBGR_ERRINT_IRQn = 388,
X2HBSC_ERRINT_IRQn = 389,
X2HSPI1_ERRINT_IRQn = 390,
X2HSPI2_ERRINT_IRQn = 391,
PRRI_IRQn = 392,
IFEI0_IRQn = 393,
OFFI0_IRQn = 394,
PFVEI0_IRQn = 395,
IFEI1_IRQn = 396,
OFFI1_IRQn = 397,
PFVEI1_IRQn = 398,
/* 399-415 Reserved */
TINT0_IRQn = 416,
TINT1_IRQn = 417,
TINT2_IRQn = 418,
TINT3_IRQn = 419,
TINT4_IRQn = 420,
TINT5_IRQn = 421,
TINT6_IRQn = 422,
TINT7_IRQn = 423,
TINT8_IRQn = 424,
TINT9_IRQn = 425,
TINT10_IRQn = 426,
TINT11_IRQn = 427,
TINT12_IRQn = 428,
TINT13_IRQn = 429,
TINT14_IRQn = 430,
TINT15_IRQn = 431,
TINT16_IRQn = 432,
TINT17_IRQn = 433,
TINT18_IRQn = 434,
TINT19_IRQn = 435,
TINT20_IRQn = 436,
TINT21_IRQn = 437,
TINT22_IRQn = 438,
TINT23_IRQn = 439,
TINT24_IRQn = 440,
TINT25_IRQn = 441,
TINT26_IRQn = 442,
TINT27_IRQn = 443,
TINT28_IRQn = 444,
TINT29_IRQn = 445,
TINT30_IRQn = 446,
TINT31_IRQn = 447,
TINT32_IRQn = 448,
TINT33_IRQn = 449,
TINT34_IRQn = 450,
TINT35_IRQn = 451,
TINT36_IRQn = 452,
TINT37_IRQn = 453,
TINT38_IRQn = 454,
TINT39_IRQn = 455,
TINT40_IRQn = 456,
TINT41_IRQn = 457,
TINT42_IRQn = 458,
TINT43_IRQn = 459,
TINT44_IRQn = 460,
TINT45_IRQn = 461,
TINT46_IRQn = 462,
TINT47_IRQn = 463,
TINT48_IRQn = 464,
TINT49_IRQn = 465,
TINT50_IRQn = 466,
TINT51_IRQn = 467,
TINT52_IRQn = 468,
TINT53_IRQn = 469,
TINT54_IRQn = 470,
TINT55_IRQn = 471,
TINT56_IRQn = 472,
TINT57_IRQn = 473,
TINT58_IRQn = 474,
TINT59_IRQn = 475,
TINT60_IRQn = 476,
TINT61_IRQn = 477,
TINT62_IRQn = 478,
TINT63_IRQn = 479,
TINT64_IRQn = 480,
TINT65_IRQn = 481,
TINT66_IRQn = 482,
TINT67_IRQn = 483,
TINT68_IRQn = 484,
TINT69_IRQn = 485,
TINT70_IRQn = 486,
TINT71_IRQn = 487,
TINT72_IRQn = 488,
TINT73_IRQn = 489,
TINT74_IRQn = 490,
TINT75_IRQn = 491,
TINT76_IRQn = 492,
TINT77_IRQn = 493,
TINT78_IRQn = 494,
TINT79_IRQn = 495,
TINT80_IRQn = 496,
TINT81_IRQn = 497,
TINT82_IRQn = 498,
TINT83_IRQn = 499,
TINT84_IRQn = 500,
TINT85_IRQn = 501,
TINT86_IRQn = 502,
TINT87_IRQn = 503,
TINT88_IRQn = 504,
TINT89_IRQn = 505,
TINT90_IRQn = 506,
TINT91_IRQn = 507,
TINT92_IRQn = 508,
TINT93_IRQn = 509,
TINT94_IRQn = 510,
TINT95_IRQn = 511,
TINT96_IRQn = 512,
TINT97_IRQn = 513,
TINT98_IRQn = 514,
TINT99_IRQn = 515,
TINT100_IRQn = 516,
TINT101_IRQn = 517,
TINT102_IRQn = 518,
TINT103_IRQn = 519,
TINT104_IRQn = 520,
TINT105_IRQn = 521,
TINT106_IRQn = 522,
TINT107_IRQn = 523,
TINT108_IRQn = 524,
TINT109_IRQn = 525,
TINT110_IRQn = 526,
TINT111_IRQn = 527,
TINT112_IRQn = 528,
TINT113_IRQn = 529,
TINT114_IRQn = 530,
TINT115_IRQn = 531,
TINT116_IRQn = 532,
TINT117_IRQn = 533,
TINT118_IRQn = 534,
TINT119_IRQn = 535,
TINT120_IRQn = 536,
TINT121_IRQn = 537,
TINT122_IRQn = 538,
TINT123_IRQn = 539,
TINT124_IRQn = 540,
TINT125_IRQn = 541,
TINT126_IRQn = 542,
TINT127_IRQn = 543,
TINT128_IRQn = 544,
TINT129_IRQn = 545,
TINT130_IRQn = 546,
TINT131_IRQn = 547,
TINT132_IRQn = 548,
TINT133_IRQn = 549,
TINT134_IRQn = 550,
TINT135_IRQn = 551,
TINT136_IRQn = 552,
TINT137_IRQn = 553,
TINT138_IRQn = 554,
TINT139_IRQn = 555,
TINT140_IRQn = 556,
TINT141_IRQn = 557,
TINT142_IRQn = 558,
TINT143_IRQn = 559,
TINT144_IRQn = 560,
TINT145_IRQn = 561,
TINT146_IRQn = 562,
TINT147_IRQn = 563,
TINT148_IRQn = 564,
TINT149_IRQn = 565,
TINT150_IRQn = 566,
TINT151_IRQn = 567,
TINT152_IRQn = 568,
TINT153_IRQn = 569,
TINT154_IRQn = 570,
TINT155_IRQn = 571,
TINT156_IRQn = 572,
TINT157_IRQn = 573,
TINT158_IRQn = 574,
TINT159_IRQn = 575,
TINT160_IRQn = 576,
TINT161_IRQn = 577,
TINT162_IRQn = 578,
TINT163_IRQn = 579,
TINT164_IRQn = 580,
TINT165_IRQn = 581,
TINT166_IRQn = 582,
TINT167_IRQn = 583,
TINT168_IRQn = 584,
TINT169_IRQn = 585,
TINT170_IRQn = 586
} IRQn_Type;
#define RZ_A1_IRQ_MAX TINT170_IRQn
/******************************************************************************/
/* Peripheral memory map */
/******************************************************************************/
#define RZ_A1_NORFLASH_BASE0 (0x00000000UL) /*!< (FLASH0 ) Base Address */
#define RZ_A1_NORFLASH_BASE1 (0x04000000UL) /*!< (FLASH1 ) Base Address */
#define RZ_A1_SDRAM_BASE0 (0x08000000UL) /*!< (SDRAM0 ) Base Address */
#define RZ_A1_SDRAM_BASE1 (0x0C000000UL) /*!< (SDRAM1 ) Base Address */
#define RZ_A1_USER_AREA0 (0x10000000UL) /*!< (USER0 ) Base Address */
#define RZ_A1_USER_AREA1 (0x14000000UL) /*!< (USER1 ) Base Address */
#define RZ_A1_SPI_IO0 (0x18000000UL) /*!< (SPI_IO0 ) Base Address */
#define RZ_A1_SPI_IO1 (0x1C000000UL) /*!< (SPI_IO1 ) Base Address */
#define RZ_A1_ONCHIP_SRAM_BASE (0x20000000UL) /*!< (SRAM_OC ) Base Address */
#define RZ_A1_SPI_MIO_BASE (0x3fe00000UL) /*!< (SPI_MIO ) Base Address */
#define RZ_A1_BSC_BASE (0x3ff00000UL) /*!< (BSC ) Base Address */
#define RZ_A1_PERIPH_BASE0 (0xe8000000UL) /*!< (PERIPH0 ) Base Address */
#define RZ_A1_PERIPH_BASE1 (0xfcf00000UL) /*!< (PERIPH1 ) Base Address */
#define RZ_A1_GIC_DISTRIBUTOR_BASE (0xe8201000UL) /*!< (GIC DIST ) Base Address */
#define RZ_A1_GIC_INTERFACE_BASE (0xe8202000UL) /*!< (GIC CPU IF) Base Address */
#define RZ_A1_PL310_BASE (0x3ffff000UL) /*!< (PL310 ) Base Address */
#define RZ_A1_ONCHIP_SRAM_NC_BASE (0x60000000UL) /*!< (SRAM_OC ) Base Address */
#define RZ_A1_PRIVATE_TIMER (0x00000600UL + 0x82000000UL) /*!< (PTIM ) Base Address */
#define GIC_DISTRIBUTOR_BASE RZ_A1_GIC_DISTRIBUTOR_BASE
#define GIC_INTERFACE_BASE RZ_A1_GIC_INTERFACE_BASE
#define L2C_310_BASE RZ_A1_PL310_BASE
#define TIMER_BASE RZ_A1_PRIVATE_TIMER
/* -------- Configuration of the Cortex-A9 Processor and Core Peripherals ------- */
#define __CA_REV 0x0000U /*!< Core revision r0p0 */
#define __CORTEX_A 9U /*!< Cortex-A9 Core */
#if (__FPU_PRESENT != 1)
#undef __FPU_PRESENT
#define __FPU_PRESENT 1U /* FPU present */
#endif
#define __GIC_PRESENT 1U /* GIC present */
#define __TIM_PRESENT 0U /* TIM present */
#define __L2C_PRESENT 1U /* L2C present */
#include "core_ca.h"
#include "nvic_wrapper.h"
#include <system_VK_RZ_A1H.h>
#include "iodefine.h"
/******************************************************************************/
/* Clock Settings */
/******************************************************************************/
/*
* Clock Mode 0 settings
* SW1-4(MD_CLK):ON
* SW1-5(MD_CLKS):ON
* FRQCR=0x1035
* CLKEN2 = 0b - unstable
* CLKEN[1:0]=01b - Output, Low, Low
* IFC[1:0] =00b - CPU clock is 1/1 PLL clock
* FRQCR2=0x0001
* GFC[1:0] =01b - Graphic clock is 2/3 bus clock
*/
#define CM0_RENESAS_RZ_A1_CLKIN ( 13333333u)
#define CM0_RENESAS_RZ_A1_CLKO ( 66666666u)
#define CM0_RENESAS_RZ_A1_I_CLK (400000000u)
#define CM0_RENESAS_RZ_A1_G_CLK (266666666u)
#define CM0_RENESAS_RZ_A1_B_CLK (133333333u)
#define CM0_RENESAS_RZ_A1_P1_CLK ( 66666666u)
#define CM0_RENESAS_RZ_A1_P0_CLK ( 33333333u)
/*
* Clock Mode 1 settings
* SW1-4(MD_CLK):OFF
* SW1-5(MD_CLKS):ON
* FRQCR=0x1335
* CLKEN2 = 0b - unstable
* CLKEN[1:0]=01b - Output, Low, Low
* IFC[1:0] =11b - CPU clock is 1/3 PLL clock
* FRQCR2=0x0003
* GFC[1:0] =11b - graphic clock is 1/3 bus clock
*/
#define CM1_RENESAS_RZ_A1_CLKIN ( 48000000u)
#define CM1_RENESAS_RZ_A1_CLKO ( 64000000u)
#define CM1_RENESAS_RZ_A1_I_CLK (128000000u)
#define CM1_RENESAS_RZ_A1_G_CLK (128000000u)
#define CM1_RENESAS_RZ_A1_B_CLK (128000000u)
#define CM1_RENESAS_RZ_A1_P1_CLK ( 64000000u)
#define CM1_RENESAS_RZ_A1_P0_CLK ( 32000000u)
/******************************************************************************/
/* CPG Settings */
/******************************************************************************/
#define CPG_FRQCR_SHIFT_CKOEN2 (14)
#define CPG_FRQCR_BIT_CKOEN2 (0x1 << CPG_FRQCR_SHIFT_CKOEN2)
#define CPG_FRQCR_SHIFT_CKOEN0 (12)
#define CPG_FRQCR_BITS_CKOEN0 (0x3 << CPG_FRQCR_SHIFT_CKOEN0)
#define CPG_FRQCR_SHIFT_IFC (8)
#define CPG_FRQCR_BITS_IFC (0x3 << CPG_FRQCR_SHIFT_IFC)
#define CPG_FRQCR2_SHIFT_GFC (0)
#define CPG_FRQCR2_BITS_GFC (0x3 << CPG_FRQCR2_SHIFT_GFC)
#define CPG_STBCR1_BIT_STBY (0x80u)
#define CPG_STBCR1_BIT_DEEP (0x40u)
#define CPG_STBCR2_BIT_HIZ (0x80u)
#define CPG_STBCR2_BIT_MSTP20 (0x01u) /* CoreSight */
#define CPG_STBCR3_BIT_MSTP37 (0x80u) /* IEBus */
#define CPG_STBCR3_BIT_MSTP36 (0x40u) /* IrDA */
#define CPG_STBCR3_BIT_MSTP35 (0x20u) /* LIN0 */
#define CPG_STBCR3_BIT_MSTP34 (0x10u) /* LIN1 */
#define CPG_STBCR3_BIT_MSTP33 (0x08u) /* Multi-Function Timer */
#define CPG_STBCR3_BIT_MSTP32 (0x04u) /* CAN */
#define CPG_STBCR3_BIT_MSTP31 (0x02u) /* A/D converter (analog voltage) */
#define CPG_STBCR3_BIT_MSTP30 (0x01u) /* Motor Control PWM Timer */
#define CPG_STBCR4_BIT_MSTP47 (0x80u) /* SCIF0 */
#define CPG_STBCR4_BIT_MSTP46 (0x40u) /* SCIF1 */
#define CPG_STBCR4_BIT_MSTP45 (0x20u) /* SCIF2 */
#define CPG_STBCR4_BIT_MSTP44 (0x10u) /* SCIF3 */
#define CPG_STBCR4_BIT_MSTP43 (0x08u) /* SCIF4 */
#define CPG_STBCR4_BIT_MSTP42 (0x04u) /* SCIF5 */
#define CPG_STBCR4_BIT_MSTP41 (0x02u) /* SCIF6 */
#define CPG_STBCR4_BIT_MSTP40 (0x01u) /* SCIF7 */
#define CPG_STBCR5_BIT_MSTP57 (0x80u) /* SCI0 */
#define CPG_STBCR5_BIT_MSTP56 (0x40u) /* SCI1 */
#define CPG_STBCR5_BIT_MSTP55 (0x20u) /* Sound Generator0 */
#define CPG_STBCR5_BIT_MSTP54 (0x10u) /* Sound Generator1 */
#define CPG_STBCR5_BIT_MSTP53 (0x08u) /* Sound Generator2 */
#define CPG_STBCR5_BIT_MSTP52 (0x04u) /* Sound Generator3 */
#define CPG_STBCR5_BIT_MSTP51 (0x02u) /* OSTM0 */
#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
#define CPG_STBCR6_BIT_MSTP67 (0x80u) /* A/D converter (clock) */
#define CPG_STBCR6_BIT_MSTP66 (0x40u) /* Capture Engine */
#define CPG_STBCR6_BIT_MSTP65 (0x20u) /* Display out comparison0 */
#define CPG_STBCR6_BIT_MSTP64 (0x10u) /* Display out comparison1 */
#define CPG_STBCR6_BIT_MSTP63 (0x08u) /* Dynamic Range compression0 */
#define CPG_STBCR6_BIT_MSTP62 (0x04u) /* Dynamic Range compression1 */
#define CPG_STBCR6_BIT_MSTP61 (0x02u) /* JPEG Decoder */
#define CPG_STBCR6_BIT_MSTP60 (0x01u) /* Realtime Clock */
#define CPG_STBCR7_BIT_MSTP77 (0x80u) /* Video Decoder0 */
#define CPG_STBCR7_BIT_MSTP76 (0x40u) /* Video Decoder1 */
#define CPG_STBCR7_BIT_MSTP74 (0x10u) /* Ethernet */
#define CPG_STBCR7_BIT_MSTP73 (0x04u) /* NAND Flash Memory Controller */
#define CPG_STBCR7_BIT_MSTP71 (0x02u) /* USB0 */
#define CPG_STBCR7_BIT_MSTP70 (0x01u) /* USB1 */
#define CPG_STBCR8_BIT_MSTP87 (0x80u) /* IMR-LS2_0 */
#define CPG_STBCR8_BIT_MSTP86 (0x40u) /* IMR-LS2_1 */
#define CPG_STBCR8_BIT_MSTP85 (0x20u) /* IMR-LSD */
#define CPG_STBCR8_BIT_MSTP84 (0x10u) /* MMC Host Interface */
#define CPG_STBCR8_BIT_MSTP83 (0x08u) /* MediaLB */
#define CPG_STBCR8_BIT_MSTP82 (0x04u) /* EthernetAVB */
#define CPG_STBCR8_BIT_MSTP81 (0x02u) /* SCUX */
#define CPG_STBCR9_BIT_MSTP97 (0x80u) /* RIIC0 */
#define CPG_STBCR9_BIT_MSTP96 (0x40u) /* RIIC1 */
#define CPG_STBCR9_BIT_MSTP95 (0x20u) /* RIIC2 */
#define CPG_STBCR9_BIT_MSTP94 (0x10u) /* RIIC3 */
#define CPG_STBCR9_BIT_MSTP93 (0x08u) /* SPI Multi I/O Bus Controller0 */
#define CPG_STBCR9_BIT_MSTP92 (0x04u) /* SPI Multi I/O Bus Controller1 */
#define CPG_STBCR9_BIT_MSTP91 (0x02u) /* VDC5_0 */
#define CPG_STBCR9_BIT_MSTP90 (0x01u) /* VDC5_1 */
#define CPG_STBCR10_BIT_MSTP107 (0x80u) /* RSPI0 */
#define CPG_STBCR10_BIT_MSTP106 (0x40u) /* RSPI1 */
#define CPG_STBCR10_BIT_MSTP105 (0x20u) /* RSPI2 */
#define CPG_STBCR10_BIT_MSTP104 (0x10u) /* RSPI3 */
#define CPG_STBCR10_BIT_MSTP103 (0x08u) /* RSPI4 */
#define CPG_STBCR10_BIT_MSTP102 (0x04u) /* ROMDEC */
#define CPG_STBCR10_BIT_MSTP101 (0x02u) /* SPIDF */
#define CPG_STBCR10_BIT_MSTP100 (0x01u) /* OpenVG */
#define CPG_STBCR11_BIT_MSTP115 (0x20u) /* SSIF0 */
#define CPG_STBCR11_BIT_MSTP114 (0x10u) /* SSIF1 */
#define CPG_STBCR11_BIT_MSTP113 (0x08u) /* SSIF2 */
#define CPG_STBCR11_BIT_MSTP112 (0x04u) /* SSIF3 */
#define CPG_STBCR11_BIT_MSTP111 (0x02u) /* SSIF4 */
#define CPG_STBCR11_BIT_MSTP110 (0x01u) /* SSIF5 */
#define CPG_STBCR12_BIT_MSTP123 (0x08u) /* SD Host Interface00 */
#define CPG_STBCR12_BIT_MSTP122 (0x04u) /* SD Host Interface01 */
#define CPG_STBCR12_BIT_MSTP121 (0x02u) /* SD Host Interface10 */
#define CPG_STBCR12_BIT_MSTP120 (0x01u) /* SD Host Interface11 */
#define CPG_STBCR13_BIT_MSTP132 (0x04u) /* PFV1 */
#define CPG_STBCR13_BIT_MSTP131 (0x02u) /* PFV0 */
#define CPG_SWRSTCR1_BIT_AXTALE (0x80u) /* AUDIO_X1 */
#define CPG_SWRSTCR1_BIT_SRST16 (0x40u) /* SSIF0 */
#define CPG_SWRSTCR1_BIT_SRST15 (0x20u) /* SSIF1 */
#define CPG_SWRSTCR1_BIT_SRST14 (0x10u) /* SSIF2 */
#define CPG_SWRSTCR1_BIT_SRST13 (0x08u) /* SSIF3 */
#define CPG_SWRSTCR1_BIT_SRST12 (0x04u) /* SSIF4 */
#define CPG_SWRSTCR1_BIT_SRST11 (0x02u) /* SSIF5 */
#define CPG_SWRSTCR2_BIT_SRST21 (0x02u) /* JPEG Decoder */
#define CPG_SWRSTCR3_BIT_SRST32 (0x04u) /* OpenVG */
#define CPG_SYSCR1_BIT_VRAME4 (0x10u) /* VRAM E Page4 */
#define CPG_SYSCR1_BIT_VRAME3 (0x08u) /* VRAM E Page3 */
#define CPG_SYSCR1_BIT_VRAME2 (0x04u) /* VRAM E Page2 */
#define CPG_SYSCR1_BIT_VRAME1 (0x02u) /* VRAM E Page1 */
#define CPG_SYSCR1_BIT_VRAME0 (0x01u) /* VRAM E Page0 */
#define CPG_SYSCR2_BIT_VRAMWE4 (0x10u) /* VRAM WE Page4 */
#define CPG_SYSCR2_BIT_VRAMWE3 (0x08u) /* VRAM WE Page3 */
#define CPG_SYSCR2_BIT_VRAMWE2 (0x04u) /* VRAM WE Page2 */
#define CPG_SYSCR2_BIT_VRAMWE1 (0x02u) /* VRAM WE Page1 */
#define CPG_SYSCR2_BIT_VRAMWE0 (0x01u) /* VRAM WE Page0 */
#define CPG_SYSCR3_BIT_RRAMWE3 (0x08u) /* RRAM WE Page3 */
#define CPG_SYSCR3_BIT_RRAMWE2 (0x04u) /* RRAM WE Page2 */
#define CPG_SYSCR3_BIT_RRAMWE1 (0x02u) /* RRAM WE Page1 */
#define CPG_SYSCR3_BIT_RRAMWE0 (0x01u) /* RRAM WE Page0 */
#define CPG_CPUSTS_BIT_ISBUSY (0x10u) /* State during Changing of the Frequency of CPU and Return from Software Standby */
#define CPG_STBREQ1_BIT_STBRQ15 (0x20u) /* CoreSight */
#define CPG_STBREQ1_BIT_STBRQ13 (0x08u) /* JPEG Control */
#define CPG_STBREQ1_BIT_STBRQ12 (0x04u) /* EthernetAVB */
#define CPG_STBREQ1_BIT_STBRQ10 (0x01u) /* Capture Engine */
#define CPG_STBREQ2_BIT_STBRQ27 (0x80u) /* MediaLB */
#define CPG_STBREQ2_BIT_STBRQ26 (0x40u) /* Ethernet */
#define CPG_STBREQ2_BIT_STBRQ25 (0x20u) /* VDC5_0 */
#define CPG_STBREQ2_BIT_STBRQ24 (0x10u) /* VCD5_1 */
#define CPG_STBREQ2_BIT_STBRQ23 (0x08u) /* IMR_LS2_0 */
#define CPG_STBREQ2_BIT_STBRQ22 (0x04u) /* IMR_LS2_1 */
#define CPG_STBREQ2_BIT_STBRQ21 (0x02u) /* IMR_LSD */
#define CPG_STBREQ2_BIT_STBRQ20 (0x01u) /* OpenVG */
#define CPG_STBACK1_BIT_STBAK15 (0x20u) /* CoreSight */
#define CPG_STBACK1_BIT_STBAK13 (0x08u) /* JPEG Control */
#define CPG_STBACK1_BIT_STBAK12 (0x04u) /* EthernetAVB */
#define CPG_STBACK1_BIT_STBAK10 (0x01u) /* Capture Engine */
#define CPG_STBACK2_BIT_STBAK27 (0x80u) /* MediaLB */
#define CPG_STBACK2_BIT_STBAK26 (0x40u) /* Ethernet */
#define CPG_STBACK2_BIT_STBAK25 (0x20u) /* VDC5_0 */
#define CPG_STBACK2_BIT_STBAK24 (0x10u) /* VCD5_1 */
#define CPG_STBACK2_BIT_STBAK23 (0x08u) /* IMR_LS2_0 */
#define CPG_STBACK2_BIT_STBAK22 (0x04u) /* IMR_LS2_1 */
#define CPG_STBACK2_BIT_STBAK21 (0x02u) /* IMR_LSD */
#define CPG_STBACK2_BIT_STBAK20 (0x01u) /* OpenVG */
#define CPG_RRAMKP_BIT_RRAMKP3 (0x08u) /* RRAM KP Page3 */
#define CPG_RRAMKP_BIT_RRAMKP2 (0x04u) /* RRAM KP Page2 */
#define CPG_RRAMKP_BIT_RRAMKP1 (0x02u) /* RRAM KP Page1 */
#define CPG_RRAMKP_BIT_RRAMKP0 (0x01u) /* RRAM KP Page0 */
#define CPG_DSCTR_BIT_EBUSKEEPE (0x80u) /* Retention of External Memory Control Pin State */
#define CPG_DSCTR_BIT_RAMBOOT (0x40u) /* Selection of Method after Returning from Deep Standby Mode */
#define CPG_DSSSR_BIT_P6_2 (0x4000u) /* P6_2 */
#define CPG_DSSSR_BIT_P3_9 (0x2000u) /* P3_9 */
#define CPG_DSSSR_BIT_P3_1 (0x1000u) /* P3_1 */
#define CPG_DSSSR_BIT_P2_12 (0x0800u) /* P2_12 */
#define CPG_DSSSR_BIT_P8_7 (0x0400u) /* P8_7 */
#define CPG_DSSSR_BIT_P3_3 (0x0200u) /* P3_3 */
#define CPG_DSSSR_BIT_NMI (0x0100u) /* NMI */
#define CPG_DSSSR_BIT_RTCAR (0x0040u) /* RTCAR */
#define CPG_DSSSR_BIT_P6_4 (0x0020u) /* P6_4 */
#define CPG_DSSSR_BIT_P5_9 (0x0010u) /* P5_9 */
#define CPG_DSSSR_BIT_P7_8 (0x0008u) /* P7_8 */
#define CPG_DSSSR_BIT_P2_15 (0x0004u) /* P2_15 */
#define CPG_DSSSR_BIT_P9_1 (0x0002u) /* P9_1 */
#define CPG_DSSSR_BIT_P8_2 (0x0001u) /* P8_2 */
#define CPG_DSESR_BIT_P6_2E (0x4000u) /* P6_2 */
#define CPG_DSESR_BIT_P3_9E (0x2000u) /* P3_9 */
#define CPG_DSESR_BIT_P3_1E (0x1000u) /* P3_1 */
#define CPG_DSESR_BIT_P2_12E (0x0800u) /* P2_12 */
#define CPG_DSESR_BIT_P8_7E (0x0400u) /* P8_7 */
#define CPG_DSESR_BIT_P3_3E (0x0200u) /* P3_3 */
#define CPG_DSESR_BIT_NMIE (0x0100u) /* NMI */
#define CPG_DSESR_BIT_P6_4E (0x0020u) /* P6_4 */
#define CPG_DSESR_BIT_P5_9E (0x0010u) /* P5_9 */
#define CPG_DSESR_BIT_P7_8E (0x0008u) /* P7_8 */
#define CPG_DSESR_BIT_P2_15E (0x0004u) /* P2_15 */
#define CPG_DSESR_BIT_P9_1E (0x0002u) /* P9_1 */
#define CPG_DSESR_BIT_P8_2E (0x0001u) /* P8_2 */
#define CPG_DSFR_BIT_IOKEEP (0x8000u) /* Release of Pin State Retention */
#define CPG_DSFR_BIT_P6_2F (0x4000u) /* P6_2 */
#define CPG_DSFR_BIT_P3_9F (0x2000u) /* P3_9 */
#define CPG_DSFR_BIT_P3_1F (0x1000u) /* P3_1 */
#define CPG_DSFR_BIT_P2_12F (0x0800u) /* P2_12 */
#define CPG_DSFR_BIT_P8_7F (0x0400u) /* P8_7 */
#define CPG_DSFR_BIT_P3_3F (0x0200u) /* P3_3 */
#define CPG_DSFR_BIT_NMIF (0x0100u) /* NMI */
#define CPG_DSFR_BIT_RTCARF (0x0040u) /* RTCAR */
#define CPG_DSFR_BIT_P6_4F (0x0020u) /* P6_4 */
#define CPG_DSFR_BIT_P5_9F (0x0010u) /* P5_9 */
#define CPG_DSFR_BIT_P7_8F (0x0008u) /* P7_8 */
#define CPG_DSFR_BIT_P2_15F (0x0004u) /* P2_15 */
#define CPG_DSFR_BIT_P9_1F (0x0002u) /* P9_1 */
#define CPG_DSFR_BIT_P8_2F (0x0001u) /* P8_2 */
#define CPG_XTALCTR_BIT_GAIN1 (0x02u) /* RTC_X3, RTC_X4 */
#define CPG_XTALCTR_BIT_GAIN0 (0x01u) /* EXTAL, XTAL */
/******************************************************************************/
/* GPIO Settings */
/******************************************************************************/
#define GPIO_BIT_N0 (1u << 0)
#define GPIO_BIT_N1 (1u << 1)
#define GPIO_BIT_N2 (1u << 2)
#define GPIO_BIT_N3 (1u << 3)
#define GPIO_BIT_N4 (1u << 4)
#define GPIO_BIT_N5 (1u << 5)
#define GPIO_BIT_N6 (1u << 6)
#define GPIO_BIT_N7 (1u << 7)
#define GPIO_BIT_N8 (1u << 8)
#define GPIO_BIT_N9 (1u << 9)
#define GPIO_BIT_N10 (1u << 10)
#define GPIO_BIT_N11 (1u << 11)
#define GPIO_BIT_N12 (1u << 12)
#define GPIO_BIT_N13 (1u << 13)
#define GPIO_BIT_N14 (1u << 14)
#define GPIO_BIT_N15 (1u << 15)
#define MD_BOOT10_MASK (0x3)
#define MD_BOOT10_BM0 (0x0)
#define MD_BOOT10_BM1 (0x2)
#define MD_BOOT10_BM3 (0x1)
#define MD_BOOT10_BM4_5 (0x3)
#define MD_CLK (1u << 2)
#define MD_CLKS (1u << 3)
#ifdef __cplusplus
}
#endif
#endif // __VK_RZ_A1H_H__

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/bsc_iobitmask.h
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@ -1,357 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : BSC register define header
*******************************************************************************/
#ifndef BSC_IOBITMASK_H
#define BSC_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define BSC_CMNCR_HIZCNT (0x00000001uL)
#define BSC_CMNCR_HIZMEM (0x00000002uL)
#define BSC_CMNCR_DPRTY (0x00000600uL)
#define BSC_CMNCR_AL0 (0x01000000uL)
#define BSC_CMNCR_TL0 (0x10000000uL)
#define BSC_CS0BCR_BSZ (0x00000600uL)
#define BSC_CS0BCR_TYPE (0x00007000uL)
#define BSC_CS0BCR_IWRRS (0x00070000uL)
#define BSC_CS0BCR_IWRRD (0x00380000uL)
#define BSC_CS0BCR_IWRWS (0x01C00000uL)
#define BSC_CS0BCR_IWRWD (0x0E000000uL)
#define BSC_CS0BCR_IWW (0x70000000uL)
#define BSC_CS1BCR_BSZ (0x00000600uL)
#define BSC_CS1BCR_TYPE (0x00007000uL)
#define BSC_CS1BCR_IWRRS (0x00070000uL)
#define BSC_CS1BCR_IWRRD (0x00380000uL)
#define BSC_CS1BCR_IWRWS (0x01C00000uL)
#define BSC_CS1BCR_IWRWD (0x0E000000uL)
#define BSC_CS1BCR_IWW (0x70000000uL)
#define BSC_CS2BCR_BSZ (0x00000600uL)
#define BSC_CS2BCR_TYPE (0x00007000uL)
#define BSC_CS2BCR_IWRRS (0x00070000uL)
#define BSC_CS2BCR_IWRRD (0x00380000uL)
#define BSC_CS2BCR_IWRWS (0x01C00000uL)
#define BSC_CS2BCR_IWRWD (0x0E000000uL)
#define BSC_CS2BCR_IWW (0x70000000uL)
#define BSC_CS3BCR_BSZ (0x00000600uL)
#define BSC_CS3BCR_TYPE (0x00007000uL)
#define BSC_CS3BCR_IWRRS (0x00070000uL)
#define BSC_CS3BCR_IWRRD (0x00380000uL)
#define BSC_CS3BCR_IWRWS (0x01C00000uL)
#define BSC_CS3BCR_IWRWD (0x0E000000uL)
#define BSC_CS3BCR_IWW (0x70000000uL)
#define BSC_CS4BCR_BSZ (0x00000600uL)
#define BSC_CS4BCR_TYPE (0x00007000uL)
#define BSC_CS4BCR_IWRRS (0x00070000uL)
#define BSC_CS4BCR_IWRRD (0x00380000uL)
#define BSC_CS4BCR_IWRWS (0x01C00000uL)
#define BSC_CS4BCR_IWRWD (0x0E000000uL)
#define BSC_CS4BCR_IWW (0x70000000uL)
#define BSC_CS5BCR_BSZ (0x00000600uL)
#define BSC_CS5BCR_TYPE (0x00007000uL)
#define BSC_CS5BCR_IWRRS (0x00070000uL)
#define BSC_CS5BCR_IWRRD (0x00380000uL)
#define BSC_CS5BCR_IWRWS (0x01C00000uL)
#define BSC_CS5BCR_IWRWD (0x0E000000uL)
#define BSC_CS5BCR_IWW (0x70000000uL)
#define BSC_CS0WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS0WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS0WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS0WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS0WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS1WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS1WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS1WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS1WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS1WCR_NORMAL_WW (0x00070000uL)
#define BSC_CS1WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS2WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS2WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS2WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS3WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS3WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS3WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS4WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS4WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS4WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS4WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS4WCR_NORMAL_WW (0x00070000uL)
#define BSC_CS4WCR_NORMAL_BAS (0x00100000uL)
#define BSC_CS5WCR_NORMAL_HW (0x00000003uL)
#define BSC_CS5WCR_NORMAL_WM (0x00000040uL)
#define BSC_CS5WCR_NORMAL_WR (0x00000780uL)
#define BSC_CS5WCR_NORMAL_SW (0x00001800uL)
#define BSC_CS5WCR_NORMAL_WW (0x00070000uL)
#define BSC_CS5WCR_NORMAL_MPXWBAS (0x00100000uL)
#define BSC_CS5WCR_NORMAL_SZSEL (0x00200000uL)
#define BSC_CS0WCR_BROM_ASY_WM (0x00000040uL)
#define BSC_CS0WCR_BROM_ASY_W (0x00000780uL)
#define BSC_CS0WCR_BROM_ASY_BW (0x00030000uL)
#define BSC_CS0WCR_BROM_ASY_BST (0x00300000uL)
#define BSC_CS4WCR_BROM_ASY_HW (0x00000003uL)
#define BSC_CS4WCR_BROM_ASY_WM (0x00000040uL)
#define BSC_CS4WCR_BROM_ASY_W (0x00000780uL)
#define BSC_CS4WCR_BROM_ASY_SW (0x00001800uL)
#define BSC_CS4WCR_BROM_ASY_BW (0x00030000uL)
#define BSC_CS4WCR_BROM_ASY_BST (0x00300000uL)
#define BSC_CS2WCR_SDRAM_A2CL (0x00000180uL)
#define BSC_CS3WCR_SDRAM_WTRC (0x00000003uL)
#define BSC_CS3WCR_SDRAM_TRWL (0x00000018uL)
#define BSC_CS3WCR_SDRAM_A3CL (0x00000180uL)
#define BSC_CS3WCR_SDRAM_WTRCD (0x00000C00uL)
#define BSC_CS3WCR_SDRAM_WTRP (0x00006000uL)
#define BSC_CS0WCR_BROM_SY_WM (0x00000040uL)
#define BSC_CS0WCR_BROM_SY_W (0x00000780uL)
#define BSC_CS0WCR_BROM_SY_BW (0x00030000uL)
#define BSC_SDCR_A3COL (0x00000003uL)
#define BSC_SDCR_A3ROW (0x00000018uL)
#define BSC_SDCR_BACTV (0x00000100uL)
#define BSC_SDCR_PDOWN (0x00000200uL)
#define BSC_SDCR_RMODE (0x00000400uL)
#define BSC_SDCR_RFSH (0x00000800uL)
#define BSC_SDCR_DEEP (0x00002000uL)
#define BSC_SDCR_A2COL (0x00030000uL)
#define BSC_SDCR_A2ROW (0x00180000uL)
#define BSC_RTCSR_RRC (0x00000007uL)
#define BSC_RTCSR_CKS (0x00000038uL)
#define BSC_RTCSR_CMIE (0x00000040uL)
#define BSC_RTCSR_CMF (0x00000080uL)
#define BSC_RTCNT_D (0xFFFFFFFFuL)
#define BSC_RTCOR_D (0xFFFFFFFFuL)
#define BSC_TOSCOR0_D (0x0000FFFFuL)
#define BSC_TOSCOR1_D (0x0000FFFFuL)
#define BSC_TOSCOR2_D (0x0000FFFFuL)
#define BSC_TOSCOR3_D (0x0000FFFFuL)
#define BSC_TOSCOR4_D (0x0000FFFFuL)
#define BSC_TOSCOR5_D (0x0000FFFFuL)
#define BSC_TOSTR_CS0TOSTF (0x00000001uL)
#define BSC_TOSTR_CS1TOSTF (0x00000002uL)
#define BSC_TOSTR_CS2TOSTF (0x00000004uL)
#define BSC_TOSTR_CS3TOSTF (0x00000008uL)
#define BSC_TOSTR_CS4TOSTF (0x00000010uL)
#define BSC_TOSTR_CS5TOSTF (0x00000020uL)
#define BSC_TOENR_CS0TOEN (0x00000001uL)
#define BSC_TOENR_CS1TOEN (0x00000002uL)
#define BSC_TOENR_CS2TOEN (0x00000004uL)
#define BSC_TOENR_CS3TOEN (0x00000008uL)
#define BSC_TOENR_CS4TOEN (0x00000010uL)
#define BSC_TOENR_CS5TOEN (0x00000020uL)
/* ==== Shift values for IO registers ==== */
#define BSC_CMNCR_HIZCNT_SHIFT (0u)
#define BSC_CMNCR_HIZMEM_SHIFT (1u)
#define BSC_CMNCR_DPRTY_SHIFT (9u)
#define BSC_CMNCR_AL0_SHIFT (24u)
#define BSC_CMNCR_TL0_SHIFT (28u)
#define BSC_CS0BCR_BSZ_SHIFT (9u)
#define BSC_CS0BCR_TYPE_SHIFT (12u)
#define BSC_CS0BCR_IWRRS_SHIFT (16u)
#define BSC_CS0BCR_IWRRD_SHIFT (19u)
#define BSC_CS0BCR_IWRWS_SHIFT (22u)
#define BSC_CS0BCR_IWRWD_SHIFT (25u)
#define BSC_CS0BCR_IWW_SHIFT (28u)
#define BSC_CS1BCR_BSZ_SHIFT (9u)
#define BSC_CS1BCR_TYPE_SHIFT (12u)
#define BSC_CS1BCR_IWRRS_SHIFT (16u)
#define BSC_CS1BCR_IWRRD_SHIFT (19u)
#define BSC_CS1BCR_IWRWS_SHIFT (22u)
#define BSC_CS1BCR_IWRWD_SHIFT (25u)
#define BSC_CS1BCR_IWW_SHIFT (28u)
#define BSC_CS2BCR_BSZ_SHIFT (9u)
#define BSC_CS2BCR_TYPE_SHIFT (12u)
#define BSC_CS2BCR_IWRRS_SHIFT (16u)
#define BSC_CS2BCR_IWRRD_SHIFT (19u)
#define BSC_CS2BCR_IWRWS_SHIFT (22u)
#define BSC_CS2BCR_IWRWD_SHIFT (25u)
#define BSC_CS2BCR_IWW_SHIFT (28u)
#define BSC_CS3BCR_BSZ_SHIFT (9u)
#define BSC_CS3BCR_TYPE_SHIFT (12u)
#define BSC_CS3BCR_IWRRS_SHIFT (16u)
#define BSC_CS3BCR_IWRRD_SHIFT (19u)
#define BSC_CS3BCR_IWRWS_SHIFT (22u)
#define BSC_CS3BCR_IWRWD_SHIFT (25u)
#define BSC_CS3BCR_IWW_SHIFT (28u)
#define BSC_CS4BCR_BSZ_SHIFT (9u)
#define BSC_CS4BCR_TYPE_SHIFT (12u)
#define BSC_CS4BCR_IWRRS_SHIFT (16u)
#define BSC_CS4BCR_IWRRD_SHIFT (19u)
#define BSC_CS4BCR_IWRWS_SHIFT (22u)
#define BSC_CS4BCR_IWRWD_SHIFT (25u)
#define BSC_CS4BCR_IWW_SHIFT (28u)
#define BSC_CS5BCR_BSZ_SHIFT (9u)
#define BSC_CS5BCR_TYPE_SHIFT (12u)
#define BSC_CS5BCR_IWRRS_SHIFT (16u)
#define BSC_CS5BCR_IWRRD_SHIFT (19u)
#define BSC_CS5BCR_IWRWS_SHIFT (22u)
#define BSC_CS5BCR_IWRWD_SHIFT (25u)
#define BSC_CS5BCR_IWW_SHIFT (28u)
#define BSC_CS0WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS0WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS0WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS0WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS0WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS1WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS1WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS1WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS1WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS1WCR_NORMAL_WW_SHIFT (16u)
#define BSC_CS1WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS2WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS2WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS2WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS3WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS3WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS3WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS4WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS4WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS4WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS4WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS4WCR_NORMAL_WW_SHIFT (16u)
#define BSC_CS4WCR_NORMAL_BAS_SHIFT (20u)
#define BSC_CS5WCR_NORMAL_HW_SHIFT (0u)
#define BSC_CS5WCR_NORMAL_WM_SHIFT (6u)
#define BSC_CS5WCR_NORMAL_WR_SHIFT (7u)
#define BSC_CS5WCR_NORMAL_SW_SHIFT (11u)
#define BSC_CS5WCR_NORMAL_WW_SHIFT (16u)
#define BSC_CS5WCR_NORMAL_MPXWBAS_SHIFT (20u)
#define BSC_CS5WCR_NORMAL_SZSEL_SHIFT (21u)
#define BSC_CS0WCR_BROM_ASY_WM_SHIFT (6u)
#define BSC_CS0WCR_BROM_ASY_W_SHIFT (7u)
#define BSC_CS0WCR_BROM_ASY_BW_SHIFT (16u)
#define BSC_CS0WCR_BROM_ASY_BST_SHIFT (20u)
#define BSC_CS4WCR_BROM_ASY_HW_SHIFT (0u)
#define BSC_CS4WCR_BROM_ASY_WM_SHIFT (6u)
#define BSC_CS4WCR_BROM_ASY_W_SHIFT (7u)
#define BSC_CS4WCR_BROM_ASY_SW_SHIFT (11u)
#define BSC_CS4WCR_BROM_ASY_BW_SHIFT (16u)
#define BSC_CS4WCR_BROM_ASY_BST_SHIFT (20u)
#define BSC_CS2WCR_SDRAM_A2CL_SHIFT (7u)
#define BSC_CS3WCR_SDRAM_WTRC_SHIFT (0u)
#define BSC_CS3WCR_SDRAM_TRWL_SHIFT (3u)
#define BSC_CS3WCR_SDRAM_A3CL_SHIFT (7u)
#define BSC_CS3WCR_SDRAM_WTRCD_SHIFT (10u)
#define BSC_CS3WCR_SDRAM_WTRP_SHIFT (13u)
#define BSC_CS0WCR_BROM_SY_WM_SHIFT (6u)
#define BSC_CS0WCR_BROM_SY_W_SHIFT (7u)
#define BSC_CS0WCR_BROM_SY_BW_SHIFT (16u)
#define BSC_SDCR_A3COL_SHIFT (0u)
#define BSC_SDCR_A3ROW_SHIFT (3u)
#define BSC_SDCR_BACTV_SHIFT (8u)
#define BSC_SDCR_PDOWN_SHIFT (9u)
#define BSC_SDCR_RMODE_SHIFT (10u)
#define BSC_SDCR_RFSH_SHIFT (11u)
#define BSC_SDCR_DEEP_SHIFT (13u)
#define BSC_SDCR_A2COL_SHIFT (16u)
#define BSC_SDCR_A2ROW_SHIFT (19u)
#define BSC_RTCSR_RRC_SHIFT (0u)
#define BSC_RTCSR_CKS_SHIFT (3u)
#define BSC_RTCSR_CMIE_SHIFT (6u)
#define BSC_RTCSR_CMF_SHIFT (7u)
#define BSC_RTCNT_D_SHIFT (0u)
#define BSC_RTCOR_D_SHIFT (0u)
#define BSC_TOSCOR0_D_SHIFT (0u)
#define BSC_TOSCOR1_D_SHIFT (0u)
#define BSC_TOSCOR2_D_SHIFT (0u)
#define BSC_TOSCOR3_D_SHIFT (0u)
#define BSC_TOSCOR4_D_SHIFT (0u)
#define BSC_TOSCOR5_D_SHIFT (0u)
#define BSC_TOSTR_CS0TOSTF_SHIFT (0u)
#define BSC_TOSTR_CS1TOSTF_SHIFT (1u)
#define BSC_TOSTR_CS2TOSTF_SHIFT (2u)
#define BSC_TOSTR_CS3TOSTF_SHIFT (3u)
#define BSC_TOSTR_CS4TOSTF_SHIFT (4u)
#define BSC_TOSTR_CS5TOSTF_SHIFT (5u)
#define BSC_TOENR_CS0TOEN_SHIFT (0u)
#define BSC_TOENR_CS1TOEN_SHIFT (1u)
#define BSC_TOENR_CS2TOEN_SHIFT (2u)
#define BSC_TOENR_CS3TOEN_SHIFT (3u)
#define BSC_TOENR_CS4TOEN_SHIFT (4u)
#define BSC_TOENR_CS5TOEN_SHIFT (5u)
#endif /* BSC_IOBITMASK_H */
/* End of File */

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/cpg_iobitmask.h
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@ -1,461 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : cpg_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : CPG register define header
*******************************************************************************/
#ifndef CPG_IOBITMASK_H
#define CPG_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define CPG_FRQCR_IFC (0x0300u)
#define CPG_FRQCR_CKOEN (0x3000u)
#define CPG_FRQCR_CKOEN2 (0x4000u)
#define CPG_FRQCR2_GFC (0x0003u)
#define CPG_CPUSTS_ISBUSY (0x10u)
#define CPG_STBCR1_DEEP (0x40u)
#define CPG_STBCR1_STBY (0x80u)
#define CPG_STBCR2_MSTP20 (0x01u)
#define CPG_STBCR2_HIZ (0x80u)
#define CPG_STBREQ1_STBRQ10 (0x01u)
#define CPG_STBREQ1_STBRQ12 (0x04u)
#define CPG_STBREQ1_STBRQ13 (0x08u)
#define CPG_STBREQ1_STBRQ15 (0x20u)
#define CPG_STBREQ2_STBRQ20 (0x01u)
#define CPG_STBREQ2_STBRQ21 (0x02u)
#define CPG_STBREQ2_STBRQ22 (0x04u)
#define CPG_STBREQ2_STBRQ23 (0x08u)
#define CPG_STBREQ2_STBRQ24 (0x10u)
#define CPG_STBREQ2_STBRQ25 (0x20u)
#define CPG_STBREQ2_STBRQ26 (0x40u)
#define CPG_STBREQ2_STBRQ27 (0x80u)
#define CPG_STBACK1_STBAK10 (0x01u)
#define CPG_STBACK1_STBAK12 (0x04u)
#define CPG_STBACK1_STBAK13 (0x08u)
#define CPG_STBACK1_STBAK15 (0x20u)
#define CPG_STBACK2_STBAK20 (0x01u)
#define CPG_STBACK2_STBAK21 (0x02u)
#define CPG_STBACK2_STBAK22 (0x04u)
#define CPG_STBACK2_STBAK23 (0x08u)
#define CPG_STBACK2_STBAK24 (0x10u)
#define CPG_STBACK2_STBAK25 (0x20u)
#define CPG_STBACK2_STBAK26 (0x40u)
#define CPG_STBACK2_STBAK27 (0x80u)
#define CPG_SYSCR1_VRAME0 (0x01u)
#define CPG_SYSCR1_VRAME1 (0x02u)
#define CPG_SYSCR1_VRAME2 (0x04u)
#define CPG_SYSCR1_VRAME3 (0x08u)
#define CPG_SYSCR1_VRAME4 (0x10u)
#define CPG_SYSCR2_VRAMWE0 (0x01u)
#define CPG_SYSCR2_VRAMWE1 (0x02u)
#define CPG_SYSCR2_VRAMWE2 (0x04u)
#define CPG_SYSCR2_VRAMWE3 (0x08u)
#define CPG_SYSCR2_VRAMWE4 (0x10u)
#define CPG_SYSCR3_RRAMWE0 (0x01u)
#define CPG_SYSCR3_RRAMWE1 (0x02u)
#define CPG_SYSCR3_RRAMWE2 (0x04u)
#define CPG_SYSCR3_RRAMWE3 (0x08u)
#define CPG_STBCR3_MSTP30 (0x01u)
#define CPG_STBCR3_MSTP31 (0x02u)
#define CPG_STBCR3_MSTP32 (0x04u)
#define CPG_STBCR3_MSTP33 (0x08u)
#define CPG_STBCR3_MSTP34 (0x10u)
#define CPG_STBCR3_MSTP35 (0x20u)
#define CPG_STBCR3_MSTP36 (0x40u)
#define CPG_STBCR3_MSTP37 (0x80u)
#define CPG_STBCR4_MSTP40 (0x01u)
#define CPG_STBCR4_MSTP41 (0x02u)
#define CPG_STBCR4_MSTP42 (0x04u)
#define CPG_STBCR4_MSTP43 (0x08u)
#define CPG_STBCR4_MSTP44 (0x10u)
#define CPG_STBCR4_MSTP45 (0x20u)
#define CPG_STBCR4_MSTP46 (0x40u)
#define CPG_STBCR4_MSTP47 (0x80u)
#define CPG_STBCR5_MSTP50 (0x01u)
#define CPG_STBCR5_MSTP51 (0x02u)
#define CPG_STBCR5_MSTP52 (0x04u)
#define CPG_STBCR5_MSTP53 (0x08u)
#define CPG_STBCR5_MSTP54 (0x10u)
#define CPG_STBCR5_MSTP55 (0x20u)
#define CPG_STBCR5_MSTP56 (0x40u)
#define CPG_STBCR5_MSTP57 (0x80u)
#define CPG_STBCR6_MSTP60 (0x01u)
#define CPG_STBCR6_MSTP61 (0x02u)
#define CPG_STBCR6_MSTP62 (0x04u)
#define CPG_STBCR6_MSTP63 (0x08u)
#define CPG_STBCR6_MSTP64 (0x10u)
#define CPG_STBCR6_MSTP65 (0x20u)
#define CPG_STBCR6_MSTP66 (0x40u)
#define CPG_STBCR6_MSTP67 (0x80u)
#define CPG_STBCR7_MSTP70 (0x01u)
#define CPG_STBCR7_MSTP71 (0x02u)
#define CPG_STBCR7_MSTP73 (0x08u)
#define CPG_STBCR7_MSTP74 (0x10u)
#define CPG_STBCR7_MSTP76 (0x40u)
#define CPG_STBCR7_MSTP77 (0x80u)
#define CPG_STBCR8_MSTP81 (0x02u)
#define CPG_STBCR8_MSTP82 (0x04u)
#define CPG_STBCR8_MSTP83 (0x08u)
#define CPG_STBCR8_MSTP84 (0x10u)
#define CPG_STBCR8_MSTP85 (0x20u)
#define CPG_STBCR8_MSTP86 (0x40u)
#define CPG_STBCR8_MSTP87 (0x80u)
#define CPG_STBCR9_MSTP90 (0x01u)
#define CPG_STBCR9_MSTP91 (0x02u)
#define CPG_STBCR9_MSTP92 (0x04u)
#define CPG_STBCR9_MSTP93 (0x08u)
#define CPG_STBCR9_MSTP94 (0x10u)
#define CPG_STBCR9_MSTP95 (0x20u)
#define CPG_STBCR9_MSTP96 (0x40u)
#define CPG_STBCR9_MSTP97 (0x80u)
#define CPG_STBCR10_MSTP100 (0x01u)
#define CPG_STBCR10_MSTP101 (0x02u)
#define CPG_STBCR10_MSTP102 (0x04u)
#define CPG_STBCR10_MSTP103 (0x08u)
#define CPG_STBCR10_MSTP104 (0x10u)
#define CPG_STBCR10_MSTP105 (0x20u)
#define CPG_STBCR10_MSTP106 (0x40u)
#define CPG_STBCR10_MSTP107 (0x80u)
#define CPG_STBCR11_MSTP110 (0x01u)
#define CPG_STBCR11_MSTP111 (0x02u)
#define CPG_STBCR11_MSTP112 (0x04u)
#define CPG_STBCR11_MSTP113 (0x08u)
#define CPG_STBCR11_MSTP114 (0x10u)
#define CPG_STBCR11_MSTP115 (0x20u)
#define CPG_STBCR12_MSTP120 (0x01u)
#define CPG_STBCR12_MSTP121 (0x02u)
#define CPG_STBCR12_MSTP122 (0x04u)
#define CPG_STBCR12_MSTP123 (0x08u)
#define CPG_STBCR13_MSTP131 (0x02u)
#define CPG_STBCR13_MSTP132 (0x04u)
#define CPG_SWRSTCR1_SRST11 (0x02u)
#define CPG_SWRSTCR1_SRST12 (0x04u)
#define CPG_SWRSTCR1_SRST13 (0x08u)
#define CPG_SWRSTCR1_SRST14 (0x10u)
#define CPG_SWRSTCR1_SRST15 (0x20u)
#define CPG_SWRSTCR1_SRST16 (0x40u)
#define CPG_SWRSTCR1_AXTALE (0x80u)
#define CPG_SWRSTCR2_SRST21 (0x02u)
#define CPG_SWRSTCR3_SRST32 (0x04u)
#define CPG_RRAMKP_RRAMKP0 (0x01u)
#define CPG_RRAMKP_RRAMKP1 (0x02u)
#define CPG_RRAMKP_RRAMKP2 (0x04u)
#define CPG_RRAMKP_RRAMKP3 (0x08u)
#define CPG_DSCTR_RAMBOOT (0x40u)
#define CPG_DSCTR_EBUSKEEPE (0x80u)
#define CPG_DSSSR_P8_2 (0x0001u)
#define CPG_DSSSR_P9_1 (0x0002u)
#define CPG_DSSSR_P2_15 (0x0004u)
#define CPG_DSSSR_P7_8 (0x0008u)
#define CPG_DSSSR_P5_9 (0x0010u)
#define CPG_DSSSR_P6_4 (0x0020u)
#define CPG_DSSSR_RTCAR (0x0040u)
#define CPG_DSSSR_NMI (0x0100u)
#define CPG_DSSSR_P3_3 (0x0200u)
#define CPG_DSSSR_P8_7 (0x0400u)
#define CPG_DSSSR_P2_12 (0x0800u)
#define CPG_DSSSR_P3_1 (0x1000u)
#define CPG_DSSSR_P3_9 (0x2000u)
#define CPG_DSSSR_P6_2 (0x4000u)
#define CPG_DSESR_P8_2E (0x0001u)
#define CPG_DSESR_P9_1E (0x0002u)
#define CPG_DSESR_P2_15E (0x0004u)
#define CPG_DSESR_P7_8E (0x0008u)
#define CPG_DSESR_P5_9E (0x0010u)
#define CPG_DSESR_P6_4E (0x0020u)
#define CPG_DSESR_NMIE (0x0100u)
#define CPG_DSESR_P3_3E (0x0200u)
#define CPG_DSESR_P8_7E (0x0400u)
#define CPG_DSESR_P2_12E (0x0800u)
#define CPG_DSESR_P3_1E (0x1000u)
#define CPG_DSESR_P3_9E (0x2000u)
#define CPG_DSESR_P6_2E (0x4000u)
#define CPG_DSFR_P8_2F (0x0001u)
#define CPG_DSFR_P9_1F (0x0002u)
#define CPG_DSFR_P2_15F (0x0004u)
#define CPG_DSFR_P7_8F (0x0008u)
#define CPG_DSFR_P5_9F (0x0010u)
#define CPG_DSFR_P6_4F (0x0020u)
#define CPG_DSFR_RTCARF (0x0040u)
#define CPG_DSFR_NMIF (0x0100u)
#define CPG_DSFR_P3_3F (0x0200u)
#define CPG_DSFR_P8_7F (0x0400u)
#define CPG_DSFR_P2_12F (0x0800u)
#define CPG_DSFR_P3_1F (0x1000u)
#define CPG_DSFR_P3_9F (0x2000u)
#define CPG_DSFR_P6_2F (0x4000u)
#define CPG_DSFR_IOKEEP (0x8000u)
#define CPG_XTALCTR_GAIN0 (0x01u)
#define CPG_XTALCTR_GAIN1 (0x02u)
/* ==== Shift values for IO registers ==== */
#define CPG_FRQCR_IFC_SHIFT (8u)
#define CPG_FRQCR_CKOEN_SHIFT (12u)
#define CPG_FRQCR_CKOEN2_SHIFT (14u)
#define CPG_FRQCR2_GFC_SHIFT (0u)
#define CPG_CPUSTS_ISBUSY_SHIFT (4u)
#define CPG_STBCR1_DEEP_SHIFT (6u)
#define CPG_STBCR1_STBY_SHIFT (7u)
#define CPG_STBCR2_MSTP20_SHIFT (0u)
#define CPG_STBCR2_HIZ_SHIFT (7u)
#define CPG_STBREQ1_STBRQ10_SHIFT (0u)
#define CPG_STBREQ1_STBRQ12_SHIFT (2u)
#define CPG_STBREQ1_STBRQ13_SHIFT (3u)
#define CPG_STBREQ1_STBRQ15_SHIFT (5u)
#define CPG_STBREQ2_STBRQ20_SHIFT (0u)
#define CPG_STBREQ2_STBRQ21_SHIFT (1u)
#define CPG_STBREQ2_STBRQ22_SHIFT (2u)
#define CPG_STBREQ2_STBRQ23_SHIFT (3u)
#define CPG_STBREQ2_STBRQ24_SHIFT (4u)
#define CPG_STBREQ2_STBRQ25_SHIFT (5u)
#define CPG_STBREQ2_STBRQ26_SHIFT (6u)
#define CPG_STBREQ2_STBRQ27_SHIFT (7u)
#define CPG_STBACK1_STBAK10_SHIFT (0u)
#define CPG_STBACK1_STBAK12_SHIFT (2u)
#define CPG_STBACK1_STBAK13_SHIFT (3u)
#define CPG_STBACK1_STBAK15_SHIFT (5u)
#define CPG_STBACK2_STBAK20_SHIFT (0u)
#define CPG_STBACK2_STBAK21_SHIFT (1u)
#define CPG_STBACK2_STBAK22_SHIFT (2u)
#define CPG_STBACK2_STBAK23_SHIFT (3u)
#define CPG_STBACK2_STBAK24_SHIFT (4u)
#define CPG_STBACK2_STBAK25_SHIFT (5u)
#define CPG_STBACK2_STBAK26_SHIFT (6u)
#define CPG_STBACK2_STBAK27_SHIFT (7u)
#define CPG_SYSCR1_VRAME0_SHIFT (0u)
#define CPG_SYSCR1_VRAME1_SHIFT (1u)
#define CPG_SYSCR1_VRAME2_SHIFT (2u)
#define CPG_SYSCR1_VRAME3_SHIFT (3u)
#define CPG_SYSCR1_VRAME4_SHIFT (4u)
#define CPG_SYSCR2_VRAMWE0_SHIFT (0u)
#define CPG_SYSCR2_VRAMWE1_SHIFT (1u)
#define CPG_SYSCR2_VRAMWE2_SHIFT (2u)
#define CPG_SYSCR2_VRAMWE3_SHIFT (3u)
#define CPG_SYSCR2_VRAMWE4_SHIFT (4u)
#define CPG_SYSCR3_RRAMWE0_SHIFT (0u)
#define CPG_SYSCR3_RRAMWE1_SHIFT (1u)
#define CPG_SYSCR3_RRAMWE2_SHIFT (2u)
#define CPG_SYSCR3_RRAMWE3_SHIFT (3u)
#define CPG_STBCR3_MSTP30_SHIFT (0u)
#define CPG_STBCR3_MSTP31_SHIFT (1u)
#define CPG_STBCR3_MSTP32_SHIFT (2u)
#define CPG_STBCR3_MSTP33_SHIFT (3u)
#define CPG_STBCR3_MSTP34_SHIFT (4u)
#define CPG_STBCR3_MSTP35_SHIFT (5u)
#define CPG_STBCR3_MSTP36_SHIFT (6u)
#define CPG_STBCR3_MSTP37_SHIFT (7u)
#define CPG_STBCR4_MSTP40_SHIFT (0u)
#define CPG_STBCR4_MSTP41_SHIFT (1u)
#define CPG_STBCR4_MSTP42_SHIFT (2u)
#define CPG_STBCR4_MSTP43_SHIFT (3u)
#define CPG_STBCR4_MSTP44_SHIFT (4u)
#define CPG_STBCR4_MSTP45_SHIFT (5u)
#define CPG_STBCR4_MSTP46_SHIFT (6u)
#define CPG_STBCR4_MSTP47_SHIFT (7u)
#define CPG_STBCR5_MSTP50_SHIFT (0u)
#define CPG_STBCR5_MSTP51_SHIFT (1u)
#define CPG_STBCR5_MSTP52_SHIFT (2u)
#define CPG_STBCR5_MSTP53_SHIFT (3u)
#define CPG_STBCR5_MSTP54_SHIFT (4u)
#define CPG_STBCR5_MSTP55_SHIFT (5u)
#define CPG_STBCR5_MSTP56_SHIFT (6u)
#define CPG_STBCR5_MSTP57_SHIFT (7u)
#define CPG_STBCR6_MSTP60_SHIFT (0u)
#define CPG_STBCR6_MSTP61_SHIFT (1u)
#define CPG_STBCR6_MSTP62_SHIFT (2u)
#define CPG_STBCR6_MSTP63_SHIFT (3u)
#define CPG_STBCR6_MSTP64_SHIFT (4u)
#define CPG_STBCR6_MSTP65_SHIFT (5u)
#define CPG_STBCR6_MSTP66_SHIFT (6u)
#define CPG_STBCR6_MSTP67_SHIFT (7u)
#define CPG_STBCR7_MSTP70_SHIFT (0u)
#define CPG_STBCR7_MSTP71_SHIFT (1u)
#define CPG_STBCR7_MSTP73_SHIFT (3u)
#define CPG_STBCR7_MSTP74_SHIFT (4u)
#define CPG_STBCR7_MSTP76_SHIFT (6u)
#define CPG_STBCR7_MSTP77_SHIFT (7u)
#define CPG_STBCR8_MSTP81_SHIFT (1u)
#define CPG_STBCR8_MSTP82_SHIFT (2u)
#define CPG_STBCR8_MSTP83_SHIFT (3u)
#define CPG_STBCR8_MSTP84_SHIFT (4u)
#define CPG_STBCR8_MSTP85_SHIFT (5u)
#define CPG_STBCR8_MSTP86_SHIFT (6u)
#define CPG_STBCR8_MSTP87_SHIFT (7u)
#define CPG_STBCR9_MSTP90_SHIFT (0u)
#define CPG_STBCR9_MSTP91_SHIFT (1u)
#define CPG_STBCR9_MSTP92_SHIFT (2u)
#define CPG_STBCR9_MSTP93_SHIFT (3u)
#define CPG_STBCR9_MSTP94_SHIFT (4u)
#define CPG_STBCR9_MSTP95_SHIFT (5u)
#define CPG_STBCR9_MSTP96_SHIFT (6u)
#define CPG_STBCR9_MSTP97_SHIFT (7u)
#define CPG_STBCR10_MSTP100_SHIFT (0u)
#define CPG_STBCR10_MSTP101_SHIFT (1u)
#define CPG_STBCR10_MSTP102_SHIFT (2u)
#define CPG_STBCR10_MSTP103_SHIFT (3u)
#define CPG_STBCR10_MSTP104_SHIFT (4u)
#define CPG_STBCR10_MSTP105_SHIFT (5u)
#define CPG_STBCR10_MSTP106_SHIFT (6u)
#define CPG_STBCR10_MSTP107_SHIFT (7u)
#define CPG_STBCR11_MSTP110_SHIFT (0u)
#define CPG_STBCR11_MSTP111_SHIFT (1u)
#define CPG_STBCR11_MSTP112_SHIFT (2u)
#define CPG_STBCR11_MSTP113_SHIFT (3u)
#define CPG_STBCR11_MSTP114_SHIFT (4u)
#define CPG_STBCR11_MSTP115_SHIFT (5u)
#define CPG_STBCR12_MSTP120_SHIFT (0u)
#define CPG_STBCR12_MSTP121_SHIFT (1u)
#define CPG_STBCR12_MSTP122_SHIFT (2u)
#define CPG_STBCR12_MSTP123_SHIFT (3u)
#define CPG_STBCR13_MSTP131_SHIFT (1u)
#define CPG_STBCR13_MSTP132_SHIFT (2u)
#define CPG_SWRSTCR1_SRST11_SHIFT (1u)
#define CPG_SWRSTCR1_SRST12_SHIFT (2u)
#define CPG_SWRSTCR1_SRST13_SHIFT (3u)
#define CPG_SWRSTCR1_SRST14_SHIFT (4u)
#define CPG_SWRSTCR1_SRST15_SHIFT (5u)
#define CPG_SWRSTCR1_SRST16_SHIFT (6u)
#define CPG_SWRSTCR1_AXTALE_SHIFT (7u)
#define CPG_SWRSTCR2_SRST21_SHIFT (1u)
#define CPG_SWRSTCR3_SRST32_SHIFT (2u)
#define CPG_RRAMKP_RRAMKP0_SHIFT (0u)
#define CPG_RRAMKP_RRAMKP1_SHIFT (1u)
#define CPG_RRAMKP_RRAMKP2_SHIFT (2u)
#define CPG_RRAMKP_RRAMKP3_SHIFT (3u)
#define CPG_DSCTR_RAMBOOT_SHIFT (6u)
#define CPG_DSCTR_EBUSKEEPE_SHIFT (7u)
#define CPG_DSSSR_P8_2_SHIFT (0u)
#define CPG_DSSSR_P9_1_SHIFT (1u)
#define CPG_DSSSR_P2_15_SHIFT (2u)
#define CPG_DSSSR_P7_8_SHIFT (3u)
#define CPG_DSSSR_P5_9_SHIFT (4u)
#define CPG_DSSSR_P6_4_SHIFT (5u)
#define CPG_DSSSR_RTCAR_SHIFT (6u)
#define CPG_DSSSR_NMI_SHIFT (8u)
#define CPG_DSSSR_P3_3_SHIFT (9u)
#define CPG_DSSSR_P8_7_SHIFT (10u)
#define CPG_DSSSR_P2_12_SHIFT (11u)
#define CPG_DSSSR_P3_1_SHIFT (12u)
#define CPG_DSSSR_P3_9_SHIFT (13u)
#define CPG_DSSSR_P6_2_SHIFT (14u)
#define CPG_DSESR_P8_2E_SHIFT (0u)
#define CPG_DSESR_P9_1E_SHIFT (1u)
#define CPG_DSESR_P2_15E_SHIFT (2u)
#define CPG_DSESR_P7_8E_SHIFT (3u)
#define CPG_DSESR_P5_9E_SHIFT (4u)
#define CPG_DSESR_P6_4E_SHIFT (5u)
#define CPG_DSESR_NMIE_SHIFT (8u)
#define CPG_DSESR_P3_3E_SHIFT (9u)
#define CPG_DSESR_P8_7E_SHIFT (10u)
#define CPG_DSESR_P2_12E_SHIFT (11u)
#define CPG_DSESR_P3_1E_SHIFT (12u)
#define CPG_DSESR_P3_9E_SHIFT (13u)
#define CPG_DSESR_P6_2E_SHIFT (14u)
#define CPG_DSFR_P8_2F_SHIFT (0u)
#define CPG_DSFR_P9_1F_SHIFT (1u)
#define CPG_DSFR_P2_15F_SHIFT (2u)
#define CPG_DSFR_P7_8F_SHIFT (3u)
#define CPG_DSFR_P5_9F_SHIFT (4u)
#define CPG_DSFR_P6_4F_SHIFT (5u)
#define CPG_DSFR_RTCARF_SHIFT (6u)
#define CPG_DSFR_NMIF_SHIFT (8u)
#define CPG_DSFR_P3_3F_SHIFT (9u)
#define CPG_DSFR_P8_7F_SHIFT (10u)
#define CPG_DSFR_P2_12F_SHIFT (11u)
#define CPG_DSFR_P3_1F_SHIFT (12u)
#define CPG_DSFR_P3_9F_SHIFT (13u)
#define CPG_DSFR_P6_2F_SHIFT (14u)
#define CPG_DSFR_IOKEEP_SHIFT (15u)
#define CPG_XTALCTR_GAIN0_SHIFT (0u)
#define CPG_XTALCTR_GAIN1_SHIFT (1u)
#endif /* CPG_IOBITMASK_H */
/* End of File */

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mtu2_iobitmask.h
* $Rev: 1138 $
* $Date:: 2014-08-08 11:03:56 +0900#$
* Description : MTU2 register define header
*******************************************************************************/
#ifndef MTU2_IOBITMASK_H
#define MTU2_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define MTU2_TCR_n_TPSC (0x07u)
#define MTU2_TCR_n_CKEG (0x18u)
#define MTU2_TCR_n_CCLR (0xE0u)
#define MTU2_TMDR_n_MD (0x0Fu)
#define MTU2_TIOR_2_IOA (0x0Fu)
#define MTU2_TIOR_2_IOB (0xF0u)
#define MTU2_TIER_n_TGIEA (0x01u)
#define MTU2_TIER_n_TGIEB (0x02u)
#define MTU2_TIER_n_TCIEV (0x10u)
#define MTU2_TIER_2_TCIEU (0x20u)
#define MTU2_TIER_n_TTGE (0x80u)
#define MTU2_TSR_n_TGFA (0x01u)
#define MTU2_TSR_n_TGFB (0x02u)
#define MTU2_TSR_n_TCFV (0x10u)
#define MTU2_TSR_2_TCFU (0x20u)
#define MTU2_TSR_2_TCFD (0x80u)
#define MTU2_TCNT_n_D (0xFFFFu)
#define MTU2_TGRA_n_D (0xFFFFu)
#define MTU2_TGRB_n_D (0xFFFFu)
#define MTU2_TMDR_3_BFA (0x10u)
#define MTU2_TMDR_3_BFB (0x20u)
#define MTU2_TMDR_4_BFA (0x10u)
#define MTU2_TMDR_4_BFB (0x20u)
#define MTU2_TIORH_3_IOA (0x0Fu)
#define MTU2_TIORH_3_IOB (0xF0u)
#define MTU2_TIORL_3_IOC (0x0Fu)
#define MTU2_TIORL_3_IOD (0xF0u)
#define MTU2_TIORH_4_IOA (0x0Fu)
#define MTU2_TIORH_4_IOB (0xF0u)
#define MTU2_TIORL_4_IOC (0x0Fu)
#define MTU2_TIORL_4_IOD (0xF0u)
#define MTU2_TIER_3_TGIEC (0x04u)
#define MTU2_TIER_3_TGIED (0x08u)
#define MTU2_TIER_4_TGIEC (0x04u)
#define MTU2_TIER_4_TGIED (0x08u)
#define MTU2_TIER_4_TTGE2 (0x40u)
#define MTU2_TOER_OE3B (0x01u)
#define MTU2_TOER_OE4A (0x02u)
#define MTU2_TOER_OE4B (0x04u)
#define MTU2_TOER_OE3D (0x08u)
#define MTU2_TOER_OE4C (0x10u)
#define MTU2_TOER_OE4D (0x20u)
#define MTU2_TGCR_UF (0x01u)
#define MTU2_TGCR_VF (0x02u)
#define MTU2_TGCR_WF (0x04u)
#define MTU2_TGCR_FB (0x08u)
#define MTU2_TGCR_P (0x10u)
#define MTU2_TGCR_N (0x20u)
#define MTU2_TGCR_BDC (0x40u)
#define MTU2_TOCR1_OLSP (0x01u)
#define MTU2_TOCR1_OLSN (0x02u)
#define MTU2_TOCR1_TOCS (0x04u)
#define MTU2_TOCR1_TOCL (0x08u)
#define MTU2_TOCR1_PSYE (0x40u)
#define MTU2_TOCR2_OLS1P (0x01u)
#define MTU2_TOCR2_OLS1N (0x02u)
#define MTU2_TOCR2_OLS2P (0x04u)
#define MTU2_TOCR2_OLS2N (0x08u)
#define MTU2_TOCR2_OLS3P (0x10u)
#define MTU2_TOCR2_OLS3N (0x20u)
#define MTU2_TOCR2_BF (0xC0u)
#define MTU2_TCDR_D (0xFFFFu)
#define MTU2_TDDR_D (0xFFFFu)
#define MTU2_TCNTS_D (0xFFFFu)
#define MTU2_TCBR_D (0xFFFFu)
#define MTU2_TGRC_3_D (0xFFFFu)
#define MTU2_TGRD_3_D (0xFFFFu)
#define MTU2_TGRC_4_D (0xFFFFu)
#define MTU2_TGRD_4_D (0xFFFFu)
#define MTU2_TSR_3_TGFC (0x04u)
#define MTU2_TSR_3_TGFD (0x08u)
#define MTU2_TSR_3_TCFD (0x80u)
#define MTU2_TSR_4_TGFC (0x04u)
#define MTU2_TSR_4_TGFD (0x08u)
#define MTU2_TSR_4_TCFD (0x80u)
#define MTU2_TITCR_4VCOR (0x07u)
#define MTU2_TITCR_T4VEN (0x08u)
#define MTU2_TITCR_3ACOR (0x70u)
#define MTU2_TITCR_T3AEN (0x80u)
#define MTU2_TITCNT_4VCNT (0x07u)
#define MTU2_TITCNT_3ACNT (0x70u)
#define MTU2_TBTER_BTE (0x03u)
#define MTU2_TDER_TDER (0x01u)
#define MTU2_TOLBR_OLS1P (0x01u)
#define MTU2_TOLBR_OLS1N (0x02u)
#define MTU2_TOLBR_OLS2P (0x04u)
#define MTU2_TOLBR_OLS2N (0x08u)
#define MTU2_TOLBR_OLS3P (0x10u)
#define MTU2_TOLBR_OLS3N (0x20u)
#define MTU2_TBTM_3_TTSA (0x01u)
#define MTU2_TBTM_3_TTSB (0x02u)
#define MTU2_TBTM_4_TTSA (0x01u)
#define MTU2_TBTM_4_TTSB (0x02u)
#define MTU2_TADCR_ITB4VE (0x0001u)
#define MTU2_TADCR_ITB3AE (0x0002u)
#define MTU2_TADCR_ITA4VE (0x0004u)
#define MTU2_TADCR_ITA3AE (0x0008u)
#define MTU2_TADCR_DT4BE (0x0010u)
#define MTU2_TADCR_UT4BE (0x0020u)
#define MTU2_TADCR_DT4AE (0x0040u)
#define MTU2_TADCR_UT4AE (0x0080u)
#define MTU2_TADCR_BF (0xC000u)
#define MTU2_TADCORA_4_D (0xFFFFu)
#define MTU2_TADCORB_4_D (0xFFFFu)
#define MTU2_TADCOBRA_4_D (0xFFFFu)
#define MTU2_TADCOBRB_4_D (0xFFFFu)
#define MTU2_TWCR_WRE (0x01u)
#define MTU2_TWCR_CCE (0x80u)
#define MTU2_TSTR_CST0 (0x01u)
#define MTU2_TSTR_CST1 (0x02u)
#define MTU2_TSTR_CST2 (0x04u)
#define MTU2_TSTR_CST3 (0x40u)
#define MTU2_TSTR_CST4 (0x80u)
#define MTU2_TSYR_SYNC0 (0x01u)
#define MTU2_TSYR_SYNC1 (0x02u)
#define MTU2_TSYR_SYNC2 (0x04u)
#define MTU2_TSYR_SYNC3 (0x40u)
#define MTU2_TSYR_SYNC4 (0x80u)
#define MTU2_TRWER_RWE (0x01u)
#define MTU2_TMDR_0_BFA (0x10u)
#define MTU2_TMDR_0_BFB (0x20u)
#define MTU2_TMDR_0_BFE (0x40u)
#define MTU2_TIORH_0_IOA (0x0Fu)
#define MTU2_TIORH_0_IOB (0xF0u)
#define MTU2_TIORL_0_IOC (0x0Fu)
#define MTU2_TIORL_0_IOD (0xF0u)
#define MTU2_TIER_0_TGIEC (0x04u)
#define MTU2_TIER_0_TGIED (0x08u)
#define MTU2_TSR_0_TGFC (0x04u)
#define MTU2_TSR_0_TGFD (0x08u)
#define MTU2_TGRC_0_D (0xFFFFu)
#define MTU2_TGRD_0_D (0xFFFFu)
#define MTU2_TGRE_0_D (0xFFFFu)
#define MTU2_TGRF_0_D (0xFFFFu)
#define MTU2_TIER2_0_TGIEE (0x01u)
#define MTU2_TIER2_0_TGIEF (0x02u)
#define MTU2_TSR2_0_TGFE (0x01u)
#define MTU2_TSR2_0_TGFF (0x02u)
#define MTU2_TBTM_0_TTSA (0x01u)
#define MTU2_TBTM_0_TTSB (0x02u)
#define MTU2_TBTM_0_TTSE (0x04u)
#define MTU2_TIOR_1_IOA (0x0Fu)
#define MTU2_TIOR_1_IOB (0xF0u)
#define MTU2_TIER_1_TCIEU (0x20u)
#define MTU2_TSR_1_TCFU (0x20u)
#define MTU2_TSR_1_TCFD (0x80u)
#define MTU2_TICCR_I1AE (0x01u)
#define MTU2_TICCR_I1BE (0x02u)
#define MTU2_TICCR_I2AE (0x04u)
#define MTU2_TICCR_I2BE (0x08u)
/* ==== Shift values for IO registers ==== */
#define MTU2_TCR_n_TPSC_SHIFT (0u)
#define MTU2_TCR_n_CKEG_SHIFT (3u)
#define MTU2_TCR_n_CCLR_SHIFT (5u)
#define MTU2_TMDR_n_MD_SHIFT (0u)
#define MTU2_TIOR_2_IOA_SHIFT (0u)
#define MTU2_TIOR_2_IOB_SHIFT (4u)
#define MTU2_TIER_n_TGIEA_SHIFT (0u)
#define MTU2_TIER_n_TGIEB_SHIFT (1u)
#define MTU2_TIER_n_TCIEV_SHIFT (4u)
#define MTU2_TIER_2_TCIEU_SHIFT (5u)
#define MTU2_TIER_n_TTGE_SHIFT (7u)
#define MTU2_TSR_n_TGFA_SHIFT (0u)
#define MTU2_TSR_n_TGFB_SHIFT (1u)
#define MTU2_TSR_n_TCFV_SHIFT (4u)
#define MTU2_TSR_2_TCFU_SHIFT (5u)
#define MTU2_TSR_2_TCFD_SHIFT (7u)
#define MTU2_TCNT_n_D_SHIFT (0u)
#define MTU2_TGRA_n_D_SHIFT (0u)
#define MTU2_TGRB_n_D_SHIFT (0u)
#define MTU2_TMDR_3_BFA_SHIFT (4u)
#define MTU2_TMDR_3_BFB_SHIFT (5u)
#define MTU2_TMDR_4_BFA_SHIFT (4u)
#define MTU2_TMDR_4_BFB_SHIFT (5u)
#define MTU2_TIORH_3_IOA_SHIFT (0u)
#define MTU2_TIORH_3_IOB_SHIFT (4u)
#define MTU2_TIORL_3_IOC_SHIFT (0u)
#define MTU2_TIORL_3_IOD_SHIFT (4u)
#define MTU2_TIORH_4_IOA_SHIFT (0u)
#define MTU2_TIORH_4_IOB_SHIFT (4u)
#define MTU2_TIORL_4_IOC_SHIFT (0u)
#define MTU2_TIORL_4_IOD_SHIFT (4u)
#define MTU2_TIER_3_TGIEC_SHIFT (2u)
#define MTU2_TIER_3_TGIED_SHIFT (3u)
#define MTU2_TIER_4_TGIEC_SHIFT (2u)
#define MTU2_TIER_4_TGIED_SHIFT (3u)
#define MTU2_TIER_4_TTGE2_SHIFT (6u)
#define MTU2_TOER_OE3B_SHIFT (0u)
#define MTU2_TOER_OE4A_SHIFT (1u)
#define MTU2_TOER_OE4B_SHIFT (2u)
#define MTU2_TOER_OE3D_SHIFT (3u)
#define MTU2_TOER_OE4C_SHIFT (4u)
#define MTU2_TOER_OE4D_SHIFT (5u)
#define MTU2_TGCR_UF_SHIFT (0u)
#define MTU2_TGCR_VF_SHIFT (1u)
#define MTU2_TGCR_WF_SHIFT (2u)
#define MTU2_TGCR_FB_SHIFT (3u)
#define MTU2_TGCR_P_SHIFT (4u)
#define MTU2_TGCR_N_SHIFT (5u)
#define MTU2_TGCR_BDC_SHIFT (6u)
#define MTU2_TOCR1_OLSP_SHIFT (0u)
#define MTU2_TOCR1_OLSN_SHIFT (1u)
#define MTU2_TOCR1_TOCS_SHIFT (2u)
#define MTU2_TOCR1_TOCL_SHIFT (3u)
#define MTU2_TOCR1_PSYE_SHIFT (6u)
#define MTU2_TOCR2_OLS1P_SHIFT (0u)
#define MTU2_TOCR2_OLS1N_SHIFT (1u)
#define MTU2_TOCR2_OLS2P_SHIFT (2u)
#define MTU2_TOCR2_OLS2N_SHIFT (3u)
#define MTU2_TOCR2_OLS3P_SHIFT (4u)
#define MTU2_TOCR2_OLS3N_SHIFT (5u)
#define MTU2_TOCR2_BF_SHIFT (6u)
#define MTU2_TCDR_D_SHIFT (0u)
#define MTU2_TDDR_D_SHIFT (0u)
#define MTU2_TCNTS_D_SHIFT (0u)
#define MTU2_TCBR_D_SHIFT (0u)
#define MTU2_TGRC_3_D_SHIFT (0u)
#define MTU2_TGRD_3_D_SHIFT (0u)
#define MTU2_TGRC_4_D_SHIFT (0u)
#define MTU2_TGRD_4_D_SHIFT (0u)
#define MTU2_TSR_3_TGFC_SHIFT (2u)
#define MTU2_TSR_3_TGFD_SHIFT (3u)
#define MTU2_TSR_3_TCFD_SHIFT (7u)
#define MTU2_TSR_4_TGFC_SHIFT (2u)
#define MTU2_TSR_4_TGFD_SHIFT (3u)
#define MTU2_TSR_4_TCFD_SHIFT (7u)
#define MTU2_TITCR_4VCOR_SHIFT (0u)
#define MTU2_TITCR_T4VEN_SHIFT (3u)
#define MTU2_TITCR_3ACOR_SHIFT (4u)
#define MTU2_TITCR_T3AEN_SHIFT (7u)
#define MTU2_TITCNT_4VCNT_SHIFT (0u)
#define MTU2_TITCNT_3ACNT_SHIFT (4u)
#define MTU2_TBTER_BTE_SHIFT (0u)
#define MTU2_TDER_TDER_SHIFT (0u)
#define MTU2_TOLBR_OLS1P_SHIFT (0u)
#define MTU2_TOLBR_OLS1N_SHIFT (1u)
#define MTU2_TOLBR_OLS2P_SHIFT (2u)
#define MTU2_TOLBR_OLS2N_SHIFT (3u)
#define MTU2_TOLBR_OLS3P_SHIFT (4u)
#define MTU2_TOLBR_OLS3N_SHIFT (5u)
#define MTU2_TBTM_3_TTSA_SHIFT (0u)
#define MTU2_TBTM_3_TTSB_SHIFT (1u)
#define MTU2_TBTM_4_TTSA_SHIFT (0u)
#define MTU2_TBTM_4_TTSB_SHIFT (1u)
#define MTU2_TADCR_ITB4VE_SHIFT (0u)
#define MTU2_TADCR_ITB3AE_SHIFT (1u)
#define MTU2_TADCR_ITA4VE_SHIFT (2u)
#define MTU2_TADCR_ITA3AE_SHIFT (3u)
#define MTU2_TADCR_DT4BE_SHIFT (4u)
#define MTU2_TADCR_UT4BE_SHIFT (5u)
#define MTU2_TADCR_DT4AE_SHIFT (6u)
#define MTU2_TADCR_UT4AE_SHIFT (7u)
#define MTU2_TADCR_BF_SHIFT (14u)
#define MTU2_TADCORA_4_D_SHIFT (0u)
#define MTU2_TADCORB_4_D_SHIFT (0u)
#define MTU2_TADCOBRA_4_D_SHIFT (0u)
#define MTU2_TADCOBRB_4_D_SHIFT (0u)
#define MTU2_TWCR_WRE_SHIFT (0u)
#define MTU2_TWCR_CCE_SHIFT (7u)
#define MTU2_TSTR_CST0_SHIFT (0u)
#define MTU2_TSTR_CST1_SHIFT (1u)
#define MTU2_TSTR_CST2_SHIFT (2u)
#define MTU2_TSTR_CST3_SHIFT (6u)
#define MTU2_TSTR_CST4_SHIFT (7u)
#define MTU2_TSYR_SYNC0_SHIFT (0u)
#define MTU2_TSYR_SYNC1_SHIFT (1u)
#define MTU2_TSYR_SYNC2_SHIFT (2u)
#define MTU2_TSYR_SYNC3_SHIFT (6u)
#define MTU2_TSYR_SYNC4_SHIFT (7u)
#define MTU2_TRWER_RWE_SHIFT (0u)
#define MTU2_TMDR_0_BFA_SHIFT (4u)
#define MTU2_TMDR_0_BFB_SHIFT (5u)
#define MTU2_TMDR_0_BFE_SHIFT (6u)
#define MTU2_TIORH_0_IOA_SHIFT (0u)
#define MTU2_TIORH_0_IOB_SHIFT (4u)
#define MTU2_TIORL_0_IOC_SHIFT (0u)
#define MTU2_TIORL_0_IOD_SHIFT (4u)
#define MTU2_TIER_0_TGIEC_SHIFT (2u)
#define MTU2_TIER_0_TGIED_SHIFT (3u)
#define MTU2_TSR_0_TGFC_SHIFT (2u)
#define MTU2_TSR_0_TGFD_SHIFT (3u)
#define MTU2_TGRC_0_D_SHIFT (0u)
#define MTU2_TGRD_0_D_SHIFT (0u)
#define MTU2_TGRE_0_D_SHIFT (0u)
#define MTU2_TGRF_0_D_SHIFT (0u)
#define MTU2_TIER2_0_TGIEE_SHIFT (0u)
#define MTU2_TIER2_0_TGIEF_SHIFT (1u)
#define MTU2_TSR2_0_TGFE_SHIFT (0u)
#define MTU2_TSR2_0_TGFF_SHIFT (1u)
#define MTU2_TBTM_0_TTSA_SHIFT (0u)
#define MTU2_TBTM_0_TTSB_SHIFT (1u)
#define MTU2_TBTM_0_TTSE_SHIFT (2u)
#define MTU2_TIOR_1_IOA_SHIFT (0u)
#define MTU2_TIOR_1_IOB_SHIFT (4u)
#define MTU2_TIER_1_TCIEU_SHIFT (5u)
#define MTU2_TSR_1_TCFU_SHIFT (5u)
#define MTU2_TSR_1_TCFD_SHIFT (7u)
#define MTU2_TICCR_I1AE_SHIFT (0u)
#define MTU2_TICCR_I1BE_SHIFT (1u)
#define MTU2_TICCR_I2AE_SHIFT (2u)
#define MTU2_TICCR_I2BE_SHIFT (3u)
#endif /* MTU2_IOBITMASK_H */
/* End of File */

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/ostm_iobitmask.h
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@ -1,123 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_iobitmask.h
* $Rev: 1115 $
* $Date:: 2014-07-09 15:35:02 +0900#$
* Description : OSTM register define header
*******************************************************************************/
#ifndef OSTM_IOBITMASK_H
#define OSTM_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
/* ---- OSTM0 ---- */
#define OSTM0_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
#define OSTM0_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
#define OSTM0_OSTMnTE_OSTMnTE (0x01u)
#define OSTM0_OSTMnTS_OSTMnTS (0x01u)
#define OSTM0_OSTMnTT_OSTMnTT (0x01u)
#define OSTM0_OSTMnCTL_MD0 (0x00000001uL)
#define OSTM0_OSTMnCTL_MD1 (0x00000002uL)
/* ---- OSTM1 ---- */
#define OSTM1_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
#define OSTM1_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
#define OSTM1_OSTMnTE_OSTMnTE (0x01u)
#define OSTM1_OSTMnTS_OSTMnTS (0x01u)
#define OSTM1_OSTMnTT_OSTMnTT (0x01u)
#define OSTM1_OSTMnCTL_MD0 (0x00000001uL)
#define OSTM1_OSTMnCTL_MD1 (0x00000002uL)
/* ---- OSTMn ---- */
#define OSTMn_OSTMnCMP_OSTMnCMP (0xFFFFFFFFuL)
#define OSTMn_OSTMnCNT_OSTMnCNT (0xFFFFFFFFuL)
#define OSTMn_OSTMnTE_OSTMnTE (0x01u)
#define OSTMn_OSTMnTS_OSTMnTS (0x01u)
#define OSTMn_OSTMnTT_OSTMnTT (0x01u)
#define OSTMn_OSTMnCTL_MD0 (0x00000001uL)
#define OSTMn_OSTMnCTL_MD1 (0x00000002uL)
/* ==== Shift values for IO registers ==== */
/* ---- OSTM0 ---- */
#define OSTM0_OSTMnCMP_OSTMnCMP_SHIFT (0u)
#define OSTM0_OSTMnCNT_OSTMnCNT_SHIFT (0u)
#define OSTM0_OSTMnTE_OSTMnTE_SHIFT (0u)
#define OSTM0_OSTMnTS_OSTMnTS_SHIFT (0u)
#define OSTM0_OSTMnTT_OSTMnTT_SHIFT (0u)
#define OSTM0_OSTMnCTL_MD0_SHIFT (0u)
#define OSTM0_OSTMnCTL_MD1_SHIFT (1u)
/* ---- OSTM1 ---- */
#define OSTM1_OSTMnCMP_OSTMnCMP_SHIFT (0u)
#define OSTM1_OSTMnCNT_OSTMnCNT_SHIFT (0u)
#define OSTM1_OSTMnTE_OSTMnTE_SHIFT (0u)
#define OSTM1_OSTMnTS_OSTMnTS_SHIFT (0u)
#define OSTM1_OSTMnTT_OSTMnTT_SHIFT (0u)
#define OSTM1_OSTMnCTL_MD0_SHIFT (0u)
#define OSTM1_OSTMnCTL_MD1_SHIFT (1u)
/* ---- OSTMn ---- */
#define OSTMn_OSTMnCMP_OSTMnCMP_SHIFT (0u)
#define OSTMn_OSTMnCNT_OSTMnCNT_SHIFT (0u)
#define OSTMn_OSTMnTE_OSTMnTE_SHIFT (0u)
#define OSTMn_OSTMnTS_OSTMnTS_SHIFT (0u)
#define OSTMn_OSTMnTT_OSTMnTT_SHIFT (0u)
#define OSTMn_OSTMnCTL_MD0_SHIFT (0u)
#define OSTMn_OSTMnCTL_MD1_SHIFT (1u)
#endif /* OSTM_IOBITMASK_H */
/* End of File */

231
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/riic_iobitmask.h
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@ -1,231 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : riic_iobitmask.h
* $Rev: 1114 $
* $Date:: 2014-07-09 14:56:39 +0900#$
* Description : RIIC register define header
*******************************************************************************/
#ifndef RIIC_IOBITMASK_H
#define RIIC_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define RIICn_RIICnCR1_SDAI (0x01u)
#define RIICn_RIICnCR1_SCLI (0x02u)
#define RIICn_RIICnCR1_SDAO (0x04u)
#define RIICn_RIICnCR1_SCLO (0x08u)
#define RIICn_RIICnCR1_SOWP (0x10u)
#define RIICn_RIICnCR1_CLO (0x20u)
#define RIICn_RIICnCR1_IICRST (0x40u)
#define RIICn_RIICnCR1_ICE (0x80u)
#define RIICn_RIICnCR2_ST (0x02u)
#define RIICn_RIICnCR2_RS (0x04u)
#define RIICn_RIICnCR2_SP (0x08u)
#define RIICn_RIICnCR2_TRS (0x20u)
#define RIICn_RIICnCR2_MST (0x40u)
#define RIICn_RIICnCR2_BBSY (0x80u)
#define RIICn_RIICnMR1_BC (0x07u)
#define RIICn_RIICnMR1_BCWP (0x08u)
#define RIICn_RIICnMR1_CKS (0x70u)
#define RIICn_RIICnMR1_MTWP (0x80u)
#define RIICn_RIICnMR2_TMOS (0x01u)
#define RIICn_RIICnMR2_TMOL (0x02u)
#define RIICn_RIICnMR2_TMOH (0x04u)
#define RIICn_RIICnMR2_SDDL (0x70u)
#define RIICn_RIICnMR2_DLCS (0x80u)
#define RIICn_RIICnMR3_NF (0x03u)
#define RIICn_RIICnMR3_ACKBR (0x04u)
#define RIICn_RIICnMR3_ACKBT (0x08u)
#define RIICn_RIICnMR3_ACKWP (0x10u)
#define RIICn_RIICnMR3_RDRFS (0x20u)
#define RIICn_RIICnMR3_WAIT (0x40u)
#define RIICn_RIICnMR3_SMBS (0x80u)
#define RIICn_RIICnFER_TMOE (0x01u)
#define RIICn_RIICnFER_MALE (0x02u)
#define RIICn_RIICnFER_NALE (0x04u)
#define RIICn_RIICnFER_SALE (0x08u)
#define RIICn_RIICnFER_NACKE (0x10u)
#define RIICn_RIICnFER_NFE (0x20u)
#define RIICn_RIICnFER_SCLE (0x40u)
#define RIICn_RIICnFER_FMPE (0x80u)
#define RIICn_RIICnSER_SAR0E (0x01u)
#define RIICn_RIICnSER_SAR1E (0x02u)
#define RIICn_RIICnSER_SAR2E (0x04u)
#define RIICn_RIICnSER_GCAE (0x08u)
#define RIICn_RIICnSER_DIDE (0x20u)
#define RIICn_RIICnSER_HOAE (0x80u)
#define RIICn_RIICnIER_TMOIE (0x01u)
#define RIICn_RIICnIER_ALIE (0x02u)
#define RIICn_RIICnIER_STIE (0x04u)
#define RIICn_RIICnIER_SPIE (0x08u)
#define RIICn_RIICnIER_NAKIE (0x10u)
#define RIICn_RIICnIER_RIE (0x20u)
#define RIICn_RIICnIER_TEIE (0x40u)
#define RIICn_RIICnIER_TIE (0x80u)
#define RIICn_RIICnSR1_AAS0 (0x01u)
#define RIICn_RIICnSR1_AAS1 (0x02u)
#define RIICn_RIICnSR1_AAS2 (0x04u)
#define RIICn_RIICnSR1_GCA (0x08u)
#define RIICn_RIICnSR1_DID (0x20u)
#define RIICn_RIICnSR1_HOA (0x80u)
#define RIICn_RIICnSR2_TMOF (0x01u)
#define RIICn_RIICnSR2_AL (0x02u)
#define RIICn_RIICnSR2_START (0x04u)
#define RIICn_RIICnSR2_STOP (0x08u)
#define RIICn_RIICnSR2_NACKF (0x10u)
#define RIICn_RIICnSR2_RDRF (0x20u)
#define RIICn_RIICnSR2_TEND (0x40u)
#define RIICn_RIICnSR2_TDRE (0x80u)
#define RIICn_RIICnSAR0_SVA0 (0x0001u)
#define RIICn_RIICnSAR0_SVA (0x03FEu)
#define RIICn_RIICnSAR0_FSy (0x8000u)
#define RIICn_RIICnSAR1_SVA0 (0x0001u)
#define RIICn_RIICnSAR1_SVA (0x03FEu)
#define RIICn_RIICnSAR1_FSy (0x8000u)
#define RIICn_RIICnSAR2_SVA0 (0x0001u)
#define RIICn_RIICnSAR2_SVA (0x03FEu)
#define RIICn_RIICnSAR2_FSy (0x8000u)
#define RIICn_RIICnBRL_BRL (0x1Fu)
#define RIICn_RIICnBRH_BRH (0x1Fu)
#define RIICn_RIICnDRT_DRT (0xFFu)
#define RIICn_RIICnDRR_DRR (0xFFu)
/* ==== Shift values for IO registers ==== */
#define RIICn_RIICnCR1_SDAI_SHIFT (0u)
#define RIICn_RIICnCR1_SCLI_SHIFT (1u)
#define RIICn_RIICnCR1_SDAO_SHIFT (2u)
#define RIICn_RIICnCR1_SCLO_SHIFT (3u)
#define RIICn_RIICnCR1_SOWP_SHIFT (4u)
#define RIICn_RIICnCR1_CLO_SHIFT (5u)
#define RIICn_RIICnCR1_IICRST_SHIFT (6u)
#define RIICn_RIICnCR1_ICE_SHIFT (7u)
#define RIICn_RIICnCR2_ST_SHIFT (1u)
#define RIICn_RIICnCR2_RS_SHIFT (2u)
#define RIICn_RIICnCR2_SP_SHIFT (3u)
#define RIICn_RIICnCR2_TRS_SHIFT (5u)
#define RIICn_RIICnCR2_MST_SHIFT (6u)
#define RIICn_RIICnCR2_BBSY_SHIFT (7u)
#define RIICn_RIICnMR1_BC_SHIFT (0u)
#define RIICn_RIICnMR1_BCWP_SHIFT (3u)
#define RIICn_RIICnMR1_CKS_SHIFT (4u)
#define RIICn_RIICnMR1_MTWP_SHIFT (7u)
#define RIICn_RIICnMR2_TMOS_SHIFT (0u)
#define RIICn_RIICnMR2_TMOL_SHIFT (1u)
#define RIICn_RIICnMR2_TMOH_SHIFT (2u)
#define RIICn_RIICnMR2_SDDL_SHIFT (4u)
#define RIICn_RIICnMR2_DLCS_SHIFT (7u)
#define RIICn_RIICnMR3_NF_SHIFT (0u)
#define RIICn_RIICnMR3_ACKBR_SHIFT (2u)
#define RIICn_RIICnMR3_ACKBT_SHIFT (3u)
#define RIICn_RIICnMR3_ACKWP_SHIFT (4u)
#define RIICn_RIICnMR3_RDRFS_SHIFT (5u)
#define RIICn_RIICnMR3_WAIT_SHIFT (6u)
#define RIICn_RIICnMR3_SMBS_SHIFT (7u)
#define RIICn_RIICnFER_TMOE_SHIFT (0u)
#define RIICn_RIICnFER_MALE_SHIFT (1u)
#define RIICn_RIICnFER_NALE_SHIFT (2u)
#define RIICn_RIICnFER_SALE_SHIFT (3u)
#define RIICn_RIICnFER_NACKE_SHIFT (4u)
#define RIICn_RIICnFER_NFE_SHIFT (5u)
#define RIICn_RIICnFER_SCLE_SHIFT (6u)
#define RIICn_RIICnFER_FMPE_SHIFT (7u)
#define RIICn_RIICnSER_SAR0E_SHIFT (0u)
#define RIICn_RIICnSER_SAR1E_SHIFT (1u)
#define RIICn_RIICnSER_SAR2E_SHIFT (2u)
#define RIICn_RIICnSER_GCAE_SHIFT (3u)
#define RIICn_RIICnSER_DIDE_SHIFT (5u)
#define RIICn_RIICnSER_HOAE_SHIFT (7u)
#define RIICn_RIICnIER_TMOIE_SHIFT (0u)
#define RIICn_RIICnIER_ALIE_SHIFT (1u)
#define RIICn_RIICnIER_STIE_SHIFT (2u)
#define RIICn_RIICnIER_SPIE_SHIFT (3u)
#define RIICn_RIICnIER_NAKIE_SHIFT (4u)
#define RIICn_RIICnIER_RIE_SHIFT (5u)
#define RIICn_RIICnIER_TEIE_SHIFT (6u)
#define RIICn_RIICnIER_TIE_SHIFT (7u)
#define RIICn_RIICnSR1_AAS0_SHIFT (0u)
#define RIICn_RIICnSR1_AAS1_SHIFT (1u)
#define RIICn_RIICnSR1_AAS2_SHIFT (2u)
#define RIICn_RIICnSR1_GCA_SHIFT (3u)
#define RIICn_RIICnSR1_DID_SHIFT (5u)
#define RIICn_RIICnSR1_HOA_SHIFT (7u)
#define RIICn_RIICnSR2_TMOF_SHIFT (0u)
#define RIICn_RIICnSR2_AL_SHIFT (1u)
#define RIICn_RIICnSR2_START_SHIFT (2u)
#define RIICn_RIICnSR2_STOP_SHIFT (3u)
#define RIICn_RIICnSR2_NACKF_SHIFT (4u)
#define RIICn_RIICnSR2_RDRF_SHIFT (5u)
#define RIICn_RIICnSR2_TEND_SHIFT (6u)
#define RIICn_RIICnSR2_TDRE_SHIFT (7u)
#define RIICn_RIICnSAR0_SVA0_SHIFT (0u)
#define RIICn_RIICnSAR0_SVA_SHIFT (1u)
#define RIICn_RIICnSAR0_FSy_SHIFT (15u)
#define RIICn_RIICnSAR1_SVA0_SHIFT (0u)
#define RIICn_RIICnSAR1_SVA_SHIFT (1u)
#define RIICn_RIICnSAR1_FSy_SHIFT (15u)
#define RIICn_RIICnSAR2_SVA0_SHIFT (0u)
#define RIICn_RIICnSAR2_SVA_SHIFT (1u)
#define RIICn_RIICnSAR2_FSy_SHIFT (15u)
#define RIICn_RIICnBRL_BRL_SHIFT (0u)
#define RIICn_RIICnBRH_BRH_SHIFT (0u)
#define RIICn_RIICnDRT_DRT_SHIFT (0u)
#define RIICn_RIICnDRR_DRR_SHIFT (0u)
#endif /* RIIC_IOBITMASK_H */
/* End of File */

215
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/rspi_iobitmask.h
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@ -1,215 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rspi_iobitmask.h
* $Rev: 1114 $
* $Date:: 2014-07-09 14:56:39 +0900#$
* Description : Renesas Serial Peripheral Interface register define header
*******************************************************************************/
#ifndef RSPI_IOBITMASK_H
#define RSPI_IOBITMASK_H
/* ==== Mask values for IO registers ==== */
#define RSPIn_SPCR_MODFEN (0x04u)
#define RSPIn_SPCR_MSTR (0x08u)
#define RSPIn_SPCR_SPEIE (0x10u)
#define RSPIn_SPCR_SPTIE (0x20u)
#define RSPIn_SPCR_SPE (0x40u)
#define RSPIn_SPCR_SPRIE (0x80u)
#define RSPIn_SSLP_SSL0P (0x01u)
#define RSPIn_SPPCR_SPLP (0x01u)
#define RSPIn_SPPCR_MOIFV (0x10u)
#define RSPIn_SPPCR_MOIFE (0x20u)
#define RSPIn_SPSR_OVRF (0x01u)
#define RSPIn_SPSR_MODF (0x04u)
#define RSPIn_SPSR_SPTEF (0x20u)
#define RSPIn_SPSR_TEND (0x40u)
#define RSPIn_SPSR_SPRF (0x80u)
#define RSPIn_SPDR_UINT32 (0xFFFFFFFFuL)
#define RSPIn_SPDR_UINT16 (0xFFFFu)
#define RSPIn_SPDR_UINT8 (0xFFu)
#define RSPIn_SPSCR_SPSLN (0x03u)
#define RSPIn_SPSSR_SPCP (0x03u)
#define RSPIn_SPBR_SPR (0xFFu)
#define RSPIn_SPDCR_SPLW (0x60u)
#define RSPIn_SPDCR_TXDMY (0x80u)
#define RSPIn_SPCKD_SCKDL (0x07u)
#define RSPIn_SSLND_SLNDL (0x07u)
#define RSPIn_SPND_SPNDL (0x07u)
#define RSPIn_SPCMD0_CPHA (0x0001u)
#define RSPIn_SPCMD0_CPOL (0x0002u)
#define RSPIn_SPCMD0_BRDV (0x000Cu)
#define RSPIn_SPCMD0_SSLKP (0x0080u)
#define RSPIn_SPCMD0_SPB (0x0F00u)
#define RSPIn_SPCMD0_LSBF (0x1000u)
#define RSPIn_SPCMD0_SPNDEN (0x2000u)
#define RSPIn_SPCMD0_SLNDEN (0x4000u)
#define RSPIn_SPCMD0_SCKDEN (0x8000u)
#define RSPIn_SPCMD1_CPHA (0x0001u)
#define RSPIn_SPCMD1_CPOL (0x0002u)
#define RSPIn_SPCMD1_BRDV (0x000Cu)
#define RSPIn_SPCMD1_SSLKP (0x0080u)
#define RSPIn_SPCMD1_SPB (0x0F00u)
#define RSPIn_SPCMD1_LSBF (0x1000u)
#define RSPIn_SPCMD1_SPNDEN (0x2000u)
#define RSPIn_SPCMD1_SLNDEN (0x4000u)
#define RSPIn_SPCMD1_SCKDEN (0x8000u)
#define RSPIn_SPCMD2_CPHA (0x0001u)
#define RSPIn_SPCMD2_CPOL (0x0002u)
#define RSPIn_SPCMD2_BRDV (0x000Cu)
#define RSPIn_SPCMD2_SSLKP (0x0080u)
#define RSPIn_SPCMD2_SPB (0x0F00u)
#define RSPIn_SPCMD2_LSBF (0x1000u)
#define RSPIn_SPCMD2_SPNDEN (0x2000u)
#define RSPIn_SPCMD2_SLNDEN (0x4000u)
#define RSPIn_SPCMD2_SCKDEN (0x8000u)
#define RSPIn_SPCMD3_CPHA (0x0001u)
#define RSPIn_SPCMD3_CPOL (0x0002u)
#define RSPIn_SPCMD3_BRDV (0x000Cu)
#define RSPIn_SPCMD3_SSLKP (0x0080u)
#define RSPIn_SPCMD3_SPB (0x0F00u)
#define RSPIn_SPCMD3_LSBF (0x1000u)
#define RSPIn_SPCMD3_SPNDEN (0x2000u)
#define RSPIn_SPCMD3_SLNDEN (0x4000u)
#define RSPIn_SPCMD3_SCKDEN (0x8000u)
#define RSPIn_SPBFCR_RXTRG (0x07u)
#define RSPIn_SPBFCR_TXTRG (0x30u)
#define RSPIn_SPBFCR_RXRST (0x40u)
#define RSPIn_SPBFCR_TXRST (0x80u)
#define RSPIn_SPBFDR_R (0x003Fu)
#define RSPIn_SPBFDR_T (0x0F00u)
/* ==== Shift values for IO registers ==== */
#define RSPIn_SPCR_MODFEN_SHIFT (2u)
#define RSPIn_SPCR_MSTR_SHIFT (3u)
#define RSPIn_SPCR_SPEIE_SHIFT (4u)
#define RSPIn_SPCR_SPTIE_SHIFT (5u)
#define RSPIn_SPCR_SPE_SHIFT (6u)
#define RSPIn_SPCR_SPRIE_SHIFT (7u)
#define RSPIn_SSLP_SSL0P_SHIFT (0u)
#define RSPIn_SPPCR_SPLP_SHIFT (0u)
#define RSPIn_SPPCR_MOIFV_SHIFT (4u)
#define RSPIn_SPPCR_MOIFE_SHIFT (5u)
#define RSPIn_SPSR_OVRF_SHIFT (0u)
#define RSPIn_SPSR_MODF_SHIFT (2u)
#define RSPIn_SPSR_SPTEF_SHIFT (5u)
#define RSPIn_SPSR_TEND_SHIFT (6u)
#define RSPIn_SPSR_SPRF_SHIFT (7u)
#define RSPIn_SPDR_UINT32_SHIFT (0u)
#define RSPIn_SPDR_UINT16_SHIFT (0u)
#define RSPIn_SPDR_UINT8_SHIFT (0u)
#define RSPIn_SPSCR_SPSLN_SHIFT (0u)
#define RSPIn_SPSSR_SPCP_SHIFT (0u)
#define RSPIn_SPBR_SPR_SHIFT (0u)
#define RSPIn_SPDCR_SPLW_SHIFT (5u)
#define RSPIn_SPDCR_TXDMY_SHIFT (7u)
#define RSPIn_SPCKD_SCKDL_SHIFT (0u)
#define RSPIn_SSLND_SLNDL_SHIFT (0u)
#define RSPIn_SPND_SPNDL_SHIFT (0u)
#define RSPIn_SPCMD0_CPHA_SHIFT (0u)
#define RSPIn_SPCMD0_CPOL_SHIFT (1u)
#define RSPIn_SPCMD0_BRDV_SHIFT (2u)
#define RSPIn_SPCMD0_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD0_SPB_SHIFT (8u)
#define RSPIn_SPCMD0_LSBF_SHIFT (12u)
#define RSPIn_SPCMD0_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD0_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD0_SCKDEN_SHIFT (15u)
#define RSPIn_SPCMD1_CPHA_SHIFT (0u)
#define RSPIn_SPCMD1_CPOL_SHIFT (1u)
#define RSPIn_SPCMD1_BRDV_SHIFT (2u)
#define RSPIn_SPCMD1_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD1_SPB_SHIFT (8u)
#define RSPIn_SPCMD1_LSBF_SHIFT (12u)
#define RSPIn_SPCMD1_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD1_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD1_SCKDEN_SHIFT (15u)
#define RSPIn_SPCMD2_CPHA_SHIFT (0u)
#define RSPIn_SPCMD2_CPOL_SHIFT (1u)
#define RSPIn_SPCMD2_BRDV_SHIFT (2u)
#define RSPIn_SPCMD2_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD2_SPB_SHIFT (8u)
#define RSPIn_SPCMD2_LSBF_SHIFT (12u)
#define RSPIn_SPCMD2_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD2_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD2_SCKDEN_SHIFT (15u)
#define RSPIn_SPCMD3_CPHA_SHIFT (0u)
#define RSPIn_SPCMD3_CPOL_SHIFT (1u)
#define RSPIn_SPCMD3_BRDV_SHIFT (2u)
#define RSPIn_SPCMD3_SSLKP_SHIFT (7u)
#define RSPIn_SPCMD3_SPB_SHIFT (8u)
#define RSPIn_SPCMD3_LSBF_SHIFT (12u)
#define RSPIn_SPCMD3_SPNDEN_SHIFT (13u)
#define RSPIn_SPCMD3_SLNDEN_SHIFT (14u)
#define RSPIn_SPCMD3_SCKDEN_SHIFT (15u)
#define RSPIn_SPBFCR_RXTRG_SHIFT (0u)
#define RSPIn_SPBFCR_TXTRG_SHIFT (4u)
#define RSPIn_SPBFCR_RXRST_SHIFT (6u)
#define RSPIn_SPBFCR_TXRST_SHIFT (7u)
#define RSPIn_SPBFDR_R_SHIFT (0u)
#define RSPIn_SPBFDR_T_SHIFT (8u)
#endif /* RSPI_IOBITMASK_H */
/* End of File */

1065
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/scif_iobitmask.h
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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iobitmasks/usb_iobitmask.h
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@ -1,731 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : usb_iobitmask.h
* $Rev: 1116 $
* $Date:: 2014-07-09 16:29:19 +0900#$
* Description : USB register define header
*******************************************************************************/
#ifndef USB_IOBITMASK_H
#define USB_IOBITMASK_H
/*==============================================*/
/* SYSCFG */
/*==============================================*/
#define USB_SYSCFG_USBE (0x0001u)
#define USB_SYSCFG_UPLLE (0x0002u)
#define USB_SYSCFG_UCKSEL (0x0004u)
/* #define USB_SYSCFG_RESERVED1 (0x0008u) */
#define USB_SYSCFG_DPRPU (0x0010u)
#define USB_SYSCFG_DRPD (0x0020u)
#define USB_SYSCFG_DCFM (0x0040u)
#define USB_SYSCFG_HSE (0x0080u)
/* #define USB_SYSCFG_RESERVED2 (0xFF00u) */
#define USB_SYSCFG_USBE_SHIFT (0)
#define USB_SYSCFG_UPLLE_SHIFT (1)
#define USB_SYSCFG_UCKSEL_SHIFT (2)
/* #define USB_SYSCFG_RESERVED1_SHIFT (3) */
#define USB_SYSCFG_DPRPU_SHIFT (4)
#define USB_SYSCFG_DRPD_SHIFT (5)
#define USB_SYSCFG_DCFM_SHIFT (6)
#define USB_SYSCFG_HSE_SHIFT (7)
/* #define USB_SYSCFG_RESERVED2_SHIFT (8) */
/*==============================================*/
/* BUSWAIT */
/*==============================================*/
#define USB_BUSWAIT_BWAIT (0x003Fu)
#define USB_BUSWAIT_BWAIT_SHIFT (0)
/*==============================================*/
/* SYSSTS0 */
/*==============================================*/
#define USB_SYSSTS0_LNST (0x0003u)
#define USB_SYSSTS0_SOFEA (0x0020u)
#define USB_SYSSTS0_HTACT (0x0040u)
#define USB_SYSSTS0_LNST_SHIFT (0)
#define USB_SYSSTS0_SOFEA_SHIFT (5)
#define USB_SYSSTS0_HTACT_SHIFT (6)
/*==============================================*/
/* DVSTCTR0 */
/*==============================================*/
#define USB_DVSTCTR0_RHST (0x0007u)
/* #define USB_DVSTCTR0_RESERVED (0x0008u) */
#define USB_DVSTCTR0_UACT (0x0010u)
#define USB_DVSTCTR0_RESUME (0x0020u)
#define USB_DVSTCTR0_USBRST (0x0040u)
#define USB_DVSTCTR0_RWUPE (0x0080u)
#define USB_DVSTCTR0_WKUP (0x0100u)
#define USB_DVSTCTR0_RHST_SHIFT (0)
/* #define USB_DVSTCTR0_RESERVED_SHIFT (3) */
#define USB_DVSTCTR0_UACT_SHIFT (4)
#define USB_DVSTCTR0_RESUME_SHIFT (5)
#define USB_DVSTCTR0_USBRST_SHIFT (6)
#define USB_DVSTCTR0_RWUPE_SHIFT (7)
#define USB_DVSTCTR0_WKUP_SHIFT (8)
/*==============================================*/
/* TESTMODE */
/*==============================================*/
#define USB_TESTMODE_UTST (0x000Fu)
/* #define USB_TESTMODE_RESERVED (0xFFF0u) */
#define USB_TESTMODE_UTST_SHIFT (0)
/* #define USB_TESTMODE_RESERVED_SHIFT (4) */
/*==============================================*/
/* DnFBCFG */
/*==============================================*/
/* #define USB_DnFBCFG_RESERVED1 (0x000Fu) */
#define USB_DnFBCFG_TENDE (0x0010u)
/* #define USB_DnFBCFG_RESERVED2 (0x0FE0u) */
#define USB_DnFBCFG_DFACC (0x3000u)
/* #define USB_DnFBCFG_RESERVED3 (0xC000u) */
/* #define USB_DnFBCFG_RESERVED1_SHIFT (0) */
#define USB_DnFBCFG_TENDE_SHIFT (4)
/* #define USB_DnFBCFG_RESERVED2_SHIFT (5) */
#define USB_DnFBCFG_DFACC_SHIFT (12)
/* #define USB_DnFBCFG_RESERVED3_SHIFT (14) */
/*==============================================*/
/* CFIFO */
/*==============================================*/
#define USB_CFIFO_FIFOPORT (0xFFFFFFFFuL)
#define USB_CFIFO_FIFOPORT_SHIFT (0)
/*==============================================*/
/* DnFIFO */
/*==============================================*/
#define USB_DnFIFO_FIFOPORT (0xFFFFFFFFuL)
#define USB_DnFIFO_FIFOPORT_SHIFT (0)
/*==============================================*/
/* CFIFOSEL */
/*==============================================*/
#define USB_CFIFOSEL_CURPIPE (0x000Fu)
/* #define USB_CFIFOSEL_RESERVED1 (0x0010u) */
#define USB_CFIFOSEL_ISEL_ (0x0020u)
/* #define USB_CFIFOSEL_RESERVED2 (0x00C0u) */
#define USB_CFIFOSEL_BIGEND (0x0100u)
/* #define USB_CFIFOSEL_RESERVED3 (0x0200u) */
#define USB_CFIFOSEL_MBW (0x0C00u)
/* #define USB_CFIFOSEL_RESERVED4 (0x3000u) */
#define USB_CFIFOSEL_REW (0x4000u)
#define USB_CFIFOSEL_RCNT (0x8000u)
#define USB_CFIFOSEL_CURPIPE_SHIFT (0)
/* #define USB_CFIFOSEL_RESERVED1_SHIFT (4) */
#define USB_CFIFOSEL_ISEL_SHIFT_ (5)
/* #define USB_CFIFOSEL_RESERVED2_SHIFT (6) */
#define USB_CFIFOSEL_BIGEND_SHIFT (8)
/* #define USB_CFIFOSEL_RESERVED3_SHIFT (9) */
#define USB_CFIFOSEL_MBW_SHIFT (10)
/* #define USB_CFIFOSEL_RESERVED4_SHIFT (12) */
#define USB_CFIFOSEL_REW_SHIFT (14)
#define USB_CFIFOSEL_RCNT_SHIFT (15)
/*==============================================*/
/* DnFIFOSEL */
/*==============================================*/
#define USB_DnFIFOSEL_CURPIPE (0x000Fu)
/* #define USB_DnFIFOSEL_RESERVED1 (0x00F0u) */
#define USB_DnFIFOSEL_BIGEND (0x0100u)
/* #define USB_DnFIFOSEL_RESERVED2 (0x0200u) */
#define USB_DnFIFOSEL_MBW (0x0C00u)
#define USB_DnFIFOSEL_DREQE (0x1000u)
#define USB_DnFIFOSEL_DCLRM (0x2000u)
#define USB_DnFIFOSEL_REW (0x4000u)
#define USB_DnFIFOSEL_RCNT (0x8000u)
#define USB_DnFIFOSEL_CURPIPE_SHIFT (0)
/* #define USB_DnFIFOSEL_RESERVED1_SHIFT (4) */
#define USB_DnFIFOSEL_BIGEND_SHIFT (8)
/* #define USB_DnFIFOSEL_RESERVED2_SHIFT (9) */
#define USB_DnFIFOSEL_MBW_SHIFT (10)
#define USB_DnFIFOSEL_DREQE_SHIFT (12)
#define USB_DnFIFOSEL_DCLRM_SHIFT (13)
#define USB_DnFIFOSEL_REW_SHIFT (14)
#define USB_DnFIFOSEL_RCNT_SHIFT (15)
/*==============================================*/
/* CFIFOCTR */
/*==============================================*/
#define USB_CFIFOCTR_DTLN (0x0FFFu)
/* #define USB_CFIFOCTR_RESERVED (0x1000u) */
#define USB_CFIFOCTR_FRDY (0x2000u)
#define USB_CFIFOCTR_BCLR (0x4000u)
#define USB_CFIFOCTR_BVAL (0x8000u)
#define USB_CFIFOCTR_DTLN_SHIFT (0)
/* #define USB_CFIFOCTR_RESERVED_SHIFT (12) */
#define USB_CFIFOCTR_FRDY_SHIFT (13)
#define USB_CFIFOCTR_BCLR_SHIFT (14)
#define USB_CFIFOCTR_BVAL_SHIFT (15)
/*==============================================*/
/* DnFIFOCTR */
/*==============================================*/
#define USB_DnFIFOCTR_DTLN (0x0FFFu)
/* #define USB_DnFIFOCTR_RESERVED (0x1000u) */
#define USB_DnFIFOCTR_FRDY (0x2000u)
#define USB_DnFIFOCTR_BCLR (0x4000u)
#define USB_DnFIFOCTR_BVAL (0x8000u)
#define USB_DnFIFOCTR_DTLN_SHIFT (0)
/* #define USB_DnFIFOCTR_RESERVED_SHIFT (12) */
#define USB_DnFIFOCTR_FRDY_SHIFT (13)
#define USB_DnFIFOCTR_BCLR_SHIFT (14)
#define USB_DnFIFOCTR_BVAL_SHIFT (15)
/*==============================================*/
/* INTENB0 */
/*==============================================*/
/* #define USB_INTENB0_RESERVED (0x00FFu) */
#define USB_INTENB0_BRDYE (0x0100u)
#define USB_INTENB0_NRDYE (0x0200u)
#define USB_INTENB0_BEMPE (0x0400u)
#define USB_INTENB0_CTRE (0x0800u)
#define USB_INTENB0_DVSE (0x1000u)
#define USB_INTENB0_SOFE (0x2000u)
#define USB_INTENB0_RSME (0x4000u)
#define USB_INTENB0_VBSE (0x8000u)
/* #define USB_INTENB0_RESERVED_SHIFT (0) */
#define USB_INTENB0_BRDYE_SHIFT (8)
#define USB_INTENB0_NRDYE_SHIFT (9)
#define USB_INTENB0_BEMPE_SHIFT (10)
#define USB_INTENB0_CTRE_SHIFT (11)
#define USB_INTENB0_DVSE_SHIFT (12)
#define USB_INTENB0_SOFE_SHIFT (13)
#define USB_INTENB0_RSME_SHIFT (14)
#define USB_INTENB0_VBSE_SHIFT (15)
/*==============================================*/
/* INTENB1 */
/*==============================================*/
/* #define USB_INTENB1_RESERVED1 (0x000Fu) */
#define USB_INTENB1_SACKE (0x0010u)
#define USB_INTENB1_SIGNE (0x0020u)
#define USB_INTENB1_EOFERRE (0x0040u)
/* #define USB_INTENB1_RESERVED2 (0x0780u) */
#define USB_INTENB1_ATTCHE (0x0800u)
#define USB_INTENB1_DTCHE (0x1000u)
/* #define USB_INTENB1_RESERVED3 (0x2000u) */
#define USB_INTENB1_BCHGE (0x4000u)
/* #define USB_INTENB1_RESERVED4 (0x8000u) */
/* #define USB_INTENB1_RESERVED1_SHIFT (0) */
#define USB_INTENB1_SACKE_SHIFT (4)
#define USB_INTENB1_SIGNE_SHIFT (5)
#define USB_INTENB1_EOFERRE_SHIFT (6)
/* #define USB_INTENB1_RESERVED2_SHIFT (7) */
#define USB_INTENB1_ATTCHE_SHIFT (11)
#define USB_INTENB1_DTCHE_SHIFT (12)
/* #define USB_INTENB1_RESERVED3_SHIFT (13) */
#define USB_INTENB1_BCHGE_SHIFT (14)
/* #define USB_INTENB1_RESERVED4_SHIFT (15) */
/*==============================================*/
/* BRDYENB */
/*==============================================*/
#define USB_BRDYENB (0xFFFFu)
#define USB_BRDYENB_SHIFT (0)
/*==============================================*/
/* NRDYENB */
/*==============================================*/
#define USB_NRDYENB (0xFFFFu)
#define USB_NRDYENB_SHIFT (0)
/*==============================================*/
/* BEMPENB */
/*==============================================*/
#define USB_BEMPENB (0xFFFFu)
#define USB_BEMPENB_SHIFT (0)
/*==============================================*/
/* SOFCFG */
/*==============================================*/
/* #define USB_SOFCFG_RESERVED1 (0x003Fu) */
#define USB_SOFCFG_BRDYM (0x0040u)
/* #define USB_SOFCFG_RESERVED2 (0x0080u) */
#define USB_SOFCFG_TRNENSEL (0x0100u)
/* #define USB_SOFCFG_RESERVED3 (0xFE00u) */
/* #define USB_SOFCFG_RESERVED1_SHIFT (0) */
#define USB_SOFCFG_BRDYM_SHIFT (6)
/* #define USB_SOFCFG_RESERVED2_SHIFT (7) */
#define USB_SOFCFG_TRNENSEL_SHIFT (8)
/* #define USB_SOFCFG_RESERVED3_SHIFT (9) */
/*==============================================*/
/* INTSTS0 */
/*==============================================*/
#define USB_INTSTS0_CTSQ (0x0007u)
#define USB_INTSTS0_VALID (0x0008u)
#define USB_INTSTS0_DVSQ (0x0070u)
#define USB_INTSTS0_VBSTS (0x0080u)
#define USB_INTSTS0_BRDY (0x0100u)
#define USB_INTSTS0_NRDY (0x0200u)
#define USB_INTSTS0_BEMP (0x0400u)
#define USB_INTSTS0_CTRT (0x0800u)
#define USB_INTSTS0_DVST (0x1000u)
#define USB_INTSTS0_SOFR (0x2000u)
#define USB_INTSTS0_RESM (0x4000u)
#define USB_INTSTS0_VBINT (0x8000u)
#define USB_INTSTS0_CTSQ_SHIFT (0)
#define USB_INTSTS0_VALID_SHIFT (3)
#define USB_INTSTS0_DVSQ_SHIFT (4)
#define USB_INTSTS0_VBSTS_SHIFT (7)
#define USB_INTSTS0_BRDY_SHIFT (8)
#define USB_INTSTS0_NRDY_SHIFT (9)
#define USB_INTSTS0_BEMP_SHIFT (10)
#define USB_INTSTS0_CTRT_SHIFT (11)
#define USB_INTSTS0_DVST_SHIFT (12)
#define USB_INTSTS0_SOFR_SHIFT (13)
#define USB_INTSTS0_RESM_SHIFT (14)
#define USB_INTSTS0_VBINT_SHIFT (15)
/*==============================================*/
/* INTSTS1 */
/*==============================================*/
/* #define USB_INTSTS1_RESERVED1 (0x000Fu) */
#define USB_INTSTS1_SACK (0x0010u)
#define USB_INTSTS1_SIGN (0x0020u)
#define USB_INTSTS1_EOFERR (0x0040u)
/* #define USB_INTSTS1_RESERVED2 (0x0780u) */
#define USB_INTSTS1_ATTCH (0x0800u)
#define USB_INTSTS1_DTCH (0x1000u)
/* #define USB_INTSTS1_RESERVED3 (0x2000u) */
#define USB_INTSTS1_BCHG (0x4000u)
/* #define USB_INTSTS1_RESERVED4 (0x8000u) */
/* #define USB_INTSTS1_RESERVED1_SHIFT (0) */
#define USB_INTSTS1_SACK_SHIFT (4)
#define USB_INTSTS1_SIGN_SHIFT (5)
#define USB_INTSTS1_EOFERR_SHIFT (6)
/* #define USB_INTSTS1_RESERVED2_SHIFT (7) */
#define USB_INTSTS1_ATTCH_SHIFT (11)
#define USB_INTSTS1_DTCH_SHIFT (12)
/* #define USB_INTSTS1_RESERVED3_SHIFT (13) */
#define USB_INTSTS1_BCHG_SHIFT (14)
/* #define USB_INTSTS1_RESERVED4_SHIFT (15) */
/*==============================================*/
/* BRDYSTS */
/*==============================================*/
#define USB_BRDYSTS (0xFFFFu)
#define USB_BRDYSTS_SHIFT (0)
/*==============================================*/
/* NRDYSTS */
/*==============================================*/
#define USB_NRDYSTS (0xFFFFu)
#define USB_NRDYSTS_SHIFT (0)
/*==============================================*/
/* BEMPSTS */
/*==============================================*/
#define USB_BEMPSTS (0xFFFFu)
#define USB_BEMPSTS_SHIFT (0)
/*==============================================*/
/* FRMNUM */
/*==============================================*/
#define USB_FRMNUM_FRNM (0x07FFu)
/* #define USB_FRMNUM_RESERVED (0x3800u) */
#define USB_FRMNUM_CRCE (0x4000u)
#define USB_FRMNUM_OVRN (0x8000u)
#define USB_FRMNUM_FRNM_SHIFT (0)
/* #define USB_FRMNUM_RESERVED_SHIFT (11) */
#define USB_FRMNUM_CRCE_SHIFT (14)
#define USB_FRMNUM_OVRN_SHIFT (15)
/*==============================================*/
/* UFRMNUM */
/*==============================================*/
#define USB_UFRMNUM_UFRNM (0x0007u)
/* #define USB_UFRMNUM_RESERVED (0xFFF8u) */
#define USB_UFRMNUM_UFRNM_SHIFT (0)
/* #define USB_UFRMNUM_RESERVED_SHIFT (3) */
/*==============================================*/
/* USBADDR */
/*==============================================*/
#define USB_USBADDR_USBADDR (0x007Fu)
/* #define USB_USBADDR_RESERVED (0xFF80u) */
#define USB_USBADDR_USBADDR_SHIFT (0)
/* #define USB_USBADDR_RESERVED_SHIFT (7) */
/*==============================================*/
/* USBREQ */
/*==============================================*/
#define USB_USBREQ_BMREQUESTTYPE (0x00FFu)
#define USB_USBREQ_BREQUEST (0xFF00u)
#define USB_USBREQ_BMREQUESTTYPE_SHIFT (0)
#define USB_USBREQ_BREQUEST_SHIFT (8)
/*==============================================*/
/* USBVAL */
/*==============================================*/
#define USB_USBVAL (0xFFFFu)
#define USB_USBVAL_SHIFT (0)
/*==============================================*/
/* USBINDX */
/*==============================================*/
#define USB_USBINDX (0xFFFFu)
#define USB_USBINDX_SHIFT (0)
/*==============================================*/
/* USBLENG */
/*==============================================*/
#define USB_USBLENG (0xFFFFu)
#define USB_USBLENG_SHIFT (0)
/*==============================================*/
/* DCPCFG */
/*==============================================*/
/* #define USB_DCPCFG_RESERVED1 (0x000Fu) */
#define USB_DCPCFG_DIR (0x0010u)
/* #define USB_DCPCFG_RESERVED2 (0x0060u) */
#define USB_DCPCFG_SHTNAK (0x0080u)
#define USB_DCPCFG_CNTMD (0x0100u)
/* #define USB_DCPCFG_RESERVED3 (0xFE00u) */
/* #define USB_DCPCFG_RESERVED1_SHIFT (0) */
#define USB_DCPCFG_DIR_SHIFT (4)
/* #define USB_DCPCFG_RESERVED2_SHIFT (5) */
#define USB_DCPCFG_SHTNK_SHIFT (7)
#define USB_DCPCFG_CNTMD_SHIFT (8)
/* #define USB_DCPCFG_RESERVED3 (9) */
/*==============================================*/
/* DCPMAXP */
/*==============================================*/
#define USB_DCPMAXP_MXPS (0x007Fu)
/* #define USB_DCPMAXP_RESERVED (0x0F80u) */
#define USB_DCPMAXP_DEVSEL (0xF000u)
#define USB_DCPMAXP_MXPS_SHIFT (0)
/* #define USB_DCPMAXP_RESERVED_SHIFT (7) */
#define USB_DCPMAXP_DEVSEL_SHIFT (12)
/*==============================================*/
/* DCPCTR */
/*==============================================*/
#define USB_DCPCTR_PID (0x0003u)
#define USB_DCPCTR_CCPL (0x0004u)
/* #define USB_DCPCTR_RESERVED1 (0x0008u) */
#define USB_DCPCTR_PINGE (0x0010u)
#define USB_DCPCTR_PBUSY (0x0020u)
#define USB_DCPCTR_SQMON (0x0040u)
#define USB_DCPCTR_SQSET (0x0080u)
#define USB_DCPCTR_SQCLR (0x0100u)
/* #define USB_DCPCTR_RESERVED2 (0x0600u) */
#define USB_DCPCTR_SUREQCLR (0x0800u)
#define USB_DCPCTR_CSSTS (0x1000u)
#define USB_DCPCTR_CSCLR (0x2000u)
#define USB_DCPCTR_SUREQ (0x4000u)
#define USB_DCPCTR_BSTS (0x8000u)
#define USB_DCPCTR_PID_SHIFT (0)
#define USB_DCPCTR_CCPL_SHIFT (2)
/* #define USB_DCPCTR_RESERVED1_SHIFT (3) */
#define USB_DCPCTR_PINGE_SHIFT (4)
#define USB_DCPCTR_PBUSY_SHIFT (5)
#define USB_DCPCTR_SQMON_SHIFT (6)
#define USB_DCPCTR_SQSET_SHIFT (7)
#define USB_DCPCTR_SQCLR_SHIFT (8)
/* #define USB_DCPCTR_RESERVED2_SHIFT (9) */
#define USB_DCPCTR_SUREQCLR_SHIFT (11)
#define USB_DCPCTR_CSSTS_SHIFT (12)
#define USB_DCPCTR_CSCLR_SHIFT (13)
#define USB_DCPCTR_SUREQ_SHIFT (14)
#define USB_DCPCTR_BSTS_SHIFT (15)
/*==============================================*/
/* PIPESEL */
/*==============================================*/
#define USB_PIPESEL_PIPESEL (0x000Fu)
/* #define USB_PIPESEL_RESERVED (0xFFF0u) */
#define USB_PIPESEL_PIPESEL_SHIFT (0)
/* #define USB_PIPESEL_RESERVED_SHIFT (4) */
/*==============================================*/
/* PIPECFG */
/*==============================================*/
#define USB_PIPECFG_EPNUM (0x000Fu)
#define USB_PIPECFG_DIR (0x0010u)
/* #define USB_PIPECFG_RESERVED1 (0x0060u) */
#define USB_PIPECFG_SHTNAK (0x0080u)
#define USB_PIPECFG_CNTMD (0x0100u)
#define USB_PIPECFG_DBLB (0x0200u)
#define USB_PIPECFG_BFRE (0x0400u)
/* #define USB_PIPECFG_RESERVED2 (0x3800u) */
#define USB_PIPECFG_TYPE (0xC000u)
#define USB_PIPECFG_EPNUM_SHIFT (0)
#define USB_PIPECFG_DIR_SHIFT (4)
/* #define USB_PIPECFG_RESERVED1_SHIFT (5) */
#define USB_PIPECFG_SHTNAK_SHIFT (7)
#define USB_PIPECFG_CNTMD_SHIFT (8)
#define USB_PIPECFG_DBLB_SHIFT (9)
#define USB_PIPECFG_BFRE_SHIFT (10)
/* #define USB_PIPECFG_RESERVED2_SHIFT (11) */
#define USB_PIPECFG_TYPE_SHIFT (14)
/*==============================================*/
/* PIPEBUF */
/*==============================================*/
#define USB_PIPEBUF_BUFNMB (0x00FFu)
/* #define USB_PIPEBUF_RESERVED1 (0x0300u) */
#define USB_PIPEBUF_BUFSIZE (0x7C00u)
/* #define USB_PIPEBUF_RESERVED2 (0x8000u) */
#define USB_PIPEBUF_BUFNMB_SHIFT (0)
/* #define USB_PIPEBUF_RESERVED1_SHIFT (8) */
#define USB_PIPEBUF_BUFSIZE_SHIFT (10)
/* #define USB_PIPEBUF_RESERVED2_SHIFT (15) */
/*==============================================*/
/* PIPEMAXP */
/*==============================================*/
#define USB_PIPEMAXP_MXPS (0x07FFu)
/* #define USB_PIPEMAXP_RESERVED (0x0800u) */
#define USB_PIPEMAXP_DEVSEL (0xF000u)
#define USB_PIPEMAXP_MXPS_SHIFT (0)
/* #define USB_PIPEMAXP_RESERVED_SHIFT (11) */
#define USB_PIPEMAXP_DEVSEL_SHIFT (12)
/*==============================================*/
/* PIPEPERI */
/*==============================================*/
#define USB_PIPEPERI_IITV (0x0007u)
/* #define USB_PIPEPERI_RESERVED1 (0x0FF8u) */
#define USB_PIPEPERI_IFIS (0x1000u)
/* #define USB_PIPEPERI_RESERVED2 (0xE000u) */
#define USB_PIPEPERI_IITV_SHIFT (0)
/* #define USB_PIPEPERI_RESERVED1_SHIFT (3) */
#define USB_PIPEPERI_IFIS_SHIFT (12)
/* #define USB_PIPEPERI_RESERVED2_SHIFT (13) */
/*==============================================*/
/* PIPEnCTR_1_5 */
/*==============================================*/
#define USB_PIPEnCTR_1_5_PID (0x0003u)
/* #define USB_PIPEnCTR_1_5_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_1_5_PBUSY (0x0020u)
#define USB_PIPEnCTR_1_5_SQMON (0x0040u)
#define USB_PIPEnCTR_1_5_SQSET (0x0080u)
#define USB_PIPEnCTR_1_5_SQCLR (0x0100u)
#define USB_PIPEnCTR_1_5_ACLRM (0x0200u)
#define USB_PIPEnCTR_1_5_ATREPM (0x0400u)
/* #define USB_PIPEnCTR_1_5_RESERVED2 (0x0800u) */
#define USB_PIPEnCTR_1_5_CSSTS (0x1000u)
#define USB_PIPEnCTR_1_5_CSCLR (0x2000u)
#define USB_PIPEnCTR_1_5_INBUFM (0x4000u)
#define USB_PIPEnCTR_1_5_BSTS (0x8000u)
#define USB_PIPEnCTR_1_5_PID_SHIFT (0)
/* #define USB_PIPEnCTR_1_5_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_1_5_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_1_5_SQMON_SHIFT (6)
#define USB_PIPEnCTR_1_5_SQSET_SHIFT (7)
#define USB_PIPEnCTR_1_5_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_1_5_ACLRM_SHIFT (9)
#define USB_PIPEnCTR_1_5_ATREPM_SHIFT (10)
/* #define USB_PIPEnCTR_1_5_RESERVED2_SHIFT (11) */
#define USB_PIPEnCTR_1_5_CSSTS_SHIFT (12)
#define USB_PIPEnCTR_1_5_CSCLR_SHIFT (13)
#define USB_PIPEnCTR_1_5_INBUFM_SHIFT (14)
#define USB_PIPEnCTR_1_5_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnCTR_6_8 */
/*==============================================*/
#define USB_PIPEnCTR_6_8_PID (0x0003u)
/* #define USB_PIPEnCTR_6_8_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_6_8_PBUSY (0x0020u)
#define USB_PIPEnCTR_6_8_SQMON (0x0040u)
#define USB_PIPEnCTR_6_8_SQSET (0x0080u)
#define USB_PIPEnCTR_6_8_SQCLR (0x0100u)
#define USB_PIPEnCTR_6_8_ACLRM (0x0200u)
/* #define USB_PIPEnCTR_6_8_RESERVED2 (0x0C00u) */
#define USB_PIPEnCTR_6_8_CSSTS (0x1000u)
#define USB_PIPEnCTR_6_8_CSCLR (0x2000u)
/* #define USB_PIPEnCTR_6_8_RESERVED3 (0x4000u) */
#define USB_PIPEnCTR_6_8_BSTS (0x8000u)
#define USB_PIPEnCTR_6_8_PID_SHIFT (0)
/* #define USB_PIPEnCTR_6_8_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_6_8_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_6_8_SQMON_SHIFT (6)
#define USB_PIPEnCTR_6_8_SQSET_SHIFT (7)
#define USB_PIPEnCTR_6_8_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_6_8_ACLRM_SHIFT (9)
/* #define USB_PIPEnCTR_6_8_RESERVED2_SHIFT (10) */
#define USB_PIPEnCTR_6_8_CSSTS_SHIFT (12)
#define USB_PIPEnCTR_6_8_CSCLR_SHIFT (13)
/* #define USB_PIPEnCTR_6_8_RESERVED3_SHIFT (14) */
#define USB_PIPEnCTR_6_8_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnCTR_9 */
/*==============================================*/
#define USB_PIPEnCTR_9_PID (0x0003u)
/* #define USB_PIPEnCTR_9_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_9_PBUSY (0x0020u)
#define USB_PIPEnCTR_9_SQMON (0x0040u)
#define USB_PIPEnCTR_9_SQSET (0x0080u)
#define USB_PIPEnCTR_9_SQCLR (0x0100u)
#define USB_PIPEnCTR_9_ACLRM (0x0200u)
#define USB_PIPEnCTR_9_ATREPM (0x0400u)
/* #define USB_PIPEnCTR_9_RESERVED2 (0x0800u) */
#define USB_PIPEnCTR_9_CSSTS (0x1000u)
#define USB_PIPEnCTR_9_CSCLR (0x2000u)
#define USB_PIPEnCTR_9_INBUFM (0x4000u)
#define USB_PIPEnCTR_9_BSTS (0x8000u)
#define USB_PIPEnCTR_9_PID_SHIFT (0)
/* #define USB_PIPEnCTR_9_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_9_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_9_SQMON_SHIFT (6)
#define USB_PIPEnCTR_9_SQSET_SHIFT (7)
#define USB_PIPEnCTR_9_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_9_ACLRM_SHIFT (9)
#define USB_PIPEnCTR_9_ATREPM_SHIFT (10)
/* #define USB_PIPEnCTR_9_RESERVED2_SHIFT (11) */
#define USB_PIPEnCTR_9_CSSTS_SHIFT (12)
#define USB_PIPEnCTR_9_CSCLR_SHIFT (13)
#define USB_PIPEnCTR_9_INBUFM_SHIFT (14)
#define USB_PIPEnCTR_9_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnCTR_A_F */
/*==============================================*/
#define USB_PIPEnCTR_A_F_PID (0x0003u)
/* #define USB_PIPEnCTR_A_F_RESERVED1 (0x001Cu) */
#define USB_PIPEnCTR_A_F_PBUSY (0x0020u)
#define USB_PIPEnCTR_A_F_SQMON (0x0040u)
#define USB_PIPEnCTR_A_F_SQSET (0x0080u)
#define USB_PIPEnCTR_A_F_SQCLR (0x0100u)
#define USB_PIPEnCTR_A_F_ACLRM (0x0200u)
#define USB_PIPEnCTR_A_F_ATREPM (0x0400u)
/* #define USB_PIPEnCTR_A_F_RESERVED2 (0x3800u) */
#define USB_PIPEnCTR_A_F_INBUFM (0x4000u)
#define USB_PIPEnCTR_A_F_BSTS (0x8000u)
#define USB_PIPEnCTR_A_F_PID_SHIFT (0)
/* #define USB_PIPEnCTR_A_F_RESERVED1_SHIFT (2) */
#define USB_PIPEnCTR_A_F_PBUSY_SHIFT (5)
#define USB_PIPEnCTR_A_F_SQMON_SHIFT (6)
#define USB_PIPEnCTR_A_F_SQSET_SHIFT (7)
#define USB_PIPEnCTR_A_F_SQCLR_SHIFT (8)
#define USB_PIPEnCTR_A_F_ACLRM_SHIFT (9)
#define USB_PIPEnCTR_A_F_ATREPM_SHIFT (10)
/* #define USB_PIPEnCTR_A_F_RESERVED2_SHIFT (11) */
#define USB_PIPEnCTR_A_F_INBUFM_SHIFT (14)
#define USB_PIPEnCTR_A_F_BSTS_SHIFT (15)
/*==============================================*/
/* PIPEnTRE */
/*==============================================*/
/* #define USB_PIPEnTRE_RESERVED1 (0x00FFu) */
#define USB_PIPEnTRE_TRCLR (0x0100u)
#define USB_PIPEnTRE_TRENB (0x0200u)
/* #define USB_PIPEnTRE_RESERVED2 (0xFC00u) */
/* #define USB_PIPEnTRE_RESERVED1_SHIFT (0) */
#define USB_PIPEnTRE_TRCLR_SHIFT (8)
#define USB_PIPEnTRE_TRENB_SHIFT (9)
/* #define USB_PIPEnTRE_RESERVED2_SHIFT (10) */
/*==============================================*/
/* PIPEnTRN */
/*==============================================*/
#define USB_PIPEnTRN (0xFFFFu)
#define USB_PIPEnTRN_SHIFT (0)
/*==============================================*/
/* DEVADDn */
/*==============================================*/
/* #define USB_DEVADDn_RESERVED1 (0x003Fu) */
#define USB_DEVADDn_USBSPD (0x00C0u)
#define USB_DEVADDn_HUBPORT (0x0700u)
#define USB_DEVADDn_UPPHUB (0x7800u)
/* #define USB_DEVADDn_RESERVED2 (0x8000u) */
/* #define USB_DEVADDn_RESERVED1_SHIFT (0) */
#define USB_DEVADDn_USBSPD_SHIFT (6)
#define USB_DEVADDn_HUBPORT_SHIFT (8)
#define USB_DEVADDn_UPPHUB_SHIFT (11)
/* #define USB_DEVADDn_RESERVED2_SHIFT (15) */
/*==============================================*/
/* SUSPMODE */
/*==============================================*/
/* #define USB_SUSPMODE_RESERVED1 (0x3FFFu) */
#define USB_SUSPMODE_SUSPM (0x4000u)
/* #define USB_SUSPMODE_RESERVED2 (0x8000u) */
/* #define USB_SUSPMODE_RESERVED1_SHIFT (0) */
#define USB_SUSPMODE_SUSPM_SHIFT (14)
/* #define USB_SUSPMODE_RESERVED2_SHIFT (15) */
/*==============================================*/
/* DnFIFOBm */
/*==============================================*/
#define USB_DnFIFOBm (0xFFFFu)
#define USB_DnFIFOBm_SHIFT (0)
#endif /* USB_IOBITMASK_H */
/* End of File */

73
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefine.h
View File

@ -1,73 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef R7S721000_IODEFINE_H
#define R7S721000_IODEFINE_H
#include "iodefines/iodefine_typedef.h" /* (V2.00h) */
#include "iodefines/adc_iodefine.h" /* (V2.00h) */
#include "iodefines/bsc_iodefine.h" /* (V2.00h) */
#include "iodefines/ceu_iodefine.h" /* (V2.00h) */
#include "iodefines/cpg_iodefine.h" /* (V2.00h) */
#include "iodefines/disc_iodefine.h" /* (V2.00h) */
#include "iodefines/dmac_iodefine.h" /* (V2.00h) */
#include "iodefines/dvdec_iodefine.h" /* (V2.00h) */
#include "iodefines/ether_iodefine.h" /* (V2.00h) */
#include "iodefines/flctl_iodefine.h" /* (V2.00h) */
#include "iodefines/gpio_iodefine.h" /* (V2.00h) */
#include "iodefines/ieb_iodefine.h" /* (V2.00h) */
#include "iodefines/inb_iodefine.h" /* (V2.00h) */
#include "iodefines/intc_iodefine.h" /* (V2.00h) */
#include "iodefines/irda_iodefine.h" /* (V2.00h) */
#include "iodefines/jcu_iodefine.h" /* (V2.00h) */
#include "iodefines/l2c_iodefine.h" /* (V2.00h) */
#include "iodefines/lin_iodefine.h" /* (V2.00h) */
#include "iodefines/lvds_iodefine.h" /* (V2.00h) */
#include "iodefines/mlb_iodefine.h" /* (V2.00h) */
#include "iodefines/mmc_iodefine.h" /* (V2.00h) */
#include "iodefines/mtu2_iodefine.h" /* (V2.00h) */
#include "iodefines/ostm_iodefine.h" /* (V2.00h) */
#include "iodefines/pfv_iodefine.h" /* (V2.00h) */
#include "iodefines/pwm_iodefine.h" /* (V2.00h) */
#include "iodefines/riic_iodefine.h" /* (V2.00h) */
#include "iodefines/romdec_iodefine.h" /* (V2.00h) */
#include "iodefines/rscan0_iodefine.h" /* (V2.00h) */
#include "iodefines/rspi_iodefine.h" /* (V2.00h) */
#include "iodefines/rtc_iodefine.h" /* (V2.00h) */
#include "iodefines/scif_iodefine.h" /* (V2.00h) */
#include "iodefines/scim_iodefine.h" /* (V2.00h) */
#include "iodefines/scux_iodefine.h" /* (V2.00h) */
#include "iodefines/sdg_iodefine.h" /* (V2.00h) */
#include "iodefines/spdif_iodefine.h" /* (V2.00h) */
#include "iodefines/spibsc_iodefine.h" /* (V2.00h) */
#include "iodefines/ssif_iodefine.h" /* (V2.00h) */
#include "iodefines/usb20_iodefine.h" /* (V2.00h) */
#include "iodefines/vdc5_iodefine.h" /* (V2.00h) */
#include "iodefines/wdt_iodefine.h" /* (V2.00h) */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : adc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef ADC_IODEFINE_H
#define ADC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define ADC (*(struct st_adc *)0xE8005800uL) /* ADC */
#define ADCADDRA (ADC.ADDRA)
#define ADCADDRB (ADC.ADDRB)
#define ADCADDRC (ADC.ADDRC)
#define ADCADDRD (ADC.ADDRD)
#define ADCADDRE (ADC.ADDRE)
#define ADCADDRF (ADC.ADDRF)
#define ADCADDRG (ADC.ADDRG)
#define ADCADDRH (ADC.ADDRH)
#define ADCADCMPHA (ADC.ADCMPHA)
#define ADCADCMPLA (ADC.ADCMPLA)
#define ADCADCMPHB (ADC.ADCMPHB)
#define ADCADCMPLB (ADC.ADCMPLB)
#define ADCADCMPHC (ADC.ADCMPHC)
#define ADCADCMPLC (ADC.ADCMPLC)
#define ADCADCMPHD (ADC.ADCMPHD)
#define ADCADCMPLD (ADC.ADCMPLD)
#define ADCADCMPHE (ADC.ADCMPHE)
#define ADCADCMPLE (ADC.ADCMPLE)
#define ADCADCMPHF (ADC.ADCMPHF)
#define ADCADCMPLF (ADC.ADCMPLF)
#define ADCADCMPHG (ADC.ADCMPHG)
#define ADCADCMPLG (ADC.ADCMPLG)
#define ADCADCMPHH (ADC.ADCMPHH)
#define ADCADCMPLH (ADC.ADCMPLH)
#define ADCADCSR (ADC.ADCSR)
#define ADCADCMPER (ADC.ADCMPER)
#define ADCADCMPSR (ADC.ADCMPSR)
typedef struct st_adc
{
/* ADC */
volatile uint16_t ADDRA; /* ADDRA */
volatile uint16_t ADDRB; /* ADDRB */
volatile uint16_t ADDRC; /* ADDRC */
volatile uint16_t ADDRD; /* ADDRD */
volatile uint16_t ADDRE; /* ADDRE */
volatile uint16_t ADDRF; /* ADDRF */
volatile uint16_t ADDRG; /* ADDRG */
volatile uint16_t ADDRH; /* ADDRH */
volatile uint8_t dummy32[16]; /* */
volatile uint16_t ADCMPHA; /* ADCMPHA */
volatile uint16_t ADCMPLA; /* ADCMPLA */
volatile uint16_t ADCMPHB; /* ADCMPHB */
volatile uint16_t ADCMPLB; /* ADCMPLB */
volatile uint16_t ADCMPHC; /* ADCMPHC */
volatile uint16_t ADCMPLC; /* ADCMPLC */
volatile uint16_t ADCMPHD; /* ADCMPHD */
volatile uint16_t ADCMPLD; /* ADCMPLD */
volatile uint16_t ADCMPHE; /* ADCMPHE */
volatile uint16_t ADCMPLE; /* ADCMPLE */
volatile uint16_t ADCMPHF; /* ADCMPHF */
volatile uint16_t ADCMPLF; /* ADCMPLF */
volatile uint16_t ADCMPHG; /* ADCMPHG */
volatile uint16_t ADCMPLG; /* ADCMPLG */
volatile uint16_t ADCMPHH; /* ADCMPHH */
volatile uint16_t ADCMPLH; /* ADCMPLH */
volatile uint8_t dummy33[32]; /* */
volatile uint16_t ADCSR; /* ADCSR */
volatile uint16_t ADCMPER; /* ADCMPER */
volatile uint16_t ADCMPSR; /* ADCMPSR */
} r_io_adc_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : bsc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef BSC_IODEFINE_H
#define BSC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define BSC (*(struct st_bsc *)0x3FFFC000uL) /* BSC */
#define BSCCMNCR (BSC.CMNCR)
#define BSCCS0BCR (BSC.CS0BCR)
#define BSCCS1BCR (BSC.CS1BCR)
#define BSCCS2BCR (BSC.CS2BCR)
#define BSCCS3BCR (BSC.CS3BCR)
#define BSCCS4BCR (BSC.CS4BCR)
#define BSCCS5BCR (BSC.CS5BCR)
#define BSCCS0WCR (BSC.CS0WCR)
#define BSCCS1WCR (BSC.CS1WCR)
#define BSCCS2WCR (BSC.CS2WCR)
#define BSCCS3WCR (BSC.CS3WCR)
#define BSCCS4WCR (BSC.CS4WCR)
#define BSCCS5WCR (BSC.CS5WCR)
#define BSCSDCR (BSC.SDCR)
#define BSCRTCSR (BSC.RTCSR)
#define BSCRTCNT (BSC.RTCNT)
#define BSCRTCOR (BSC.RTCOR)
#define BSCTOSCOR0 (BSC.TOSCOR0)
#define BSCTOSCOR1 (BSC.TOSCOR1)
#define BSCTOSCOR2 (BSC.TOSCOR2)
#define BSCTOSCOR3 (BSC.TOSCOR3)
#define BSCTOSCOR4 (BSC.TOSCOR4)
#define BSCTOSCOR5 (BSC.TOSCOR5)
#define BSCTOSTR (BSC.TOSTR)
#define BSCTOENR (BSC.TOENR)
#define BSC_CSnBCR_COUNT (6)
#define BSC_CSnWCR_COUNT (6)
#define BSC_TOSCORn_COUNT (6)
typedef struct st_bsc
{
/* BSC */
volatile uint32_t CMNCR; /* CMNCR */
/* #define BSC_CSnBCR_COUNT (6) */
volatile uint32_t CS0BCR; /* CS0BCR */
volatile uint32_t CS1BCR; /* CS1BCR */
volatile uint32_t CS2BCR; /* CS2BCR */
volatile uint32_t CS3BCR; /* CS3BCR */
volatile uint32_t CS4BCR; /* CS4BCR */
volatile uint32_t CS5BCR; /* CS5BCR */
volatile uint8_t dummy4[12]; /* */
/* #define BSC_CSnWCR_COUNT (6) */
volatile uint32_t CS0WCR; /* CS0WCR */
volatile uint32_t CS1WCR; /* CS1WCR */
volatile uint32_t CS2WCR; /* CS2WCR */
volatile uint32_t CS3WCR; /* CS3WCR */
volatile uint32_t CS4WCR; /* CS4WCR */
volatile uint32_t CS5WCR; /* CS5WCR */
volatile uint8_t dummy5[12]; /* */
volatile uint32_t SDCR; /* SDCR */
volatile uint32_t RTCSR; /* RTCSR */
volatile uint32_t RTCNT; /* RTCNT */
volatile uint32_t RTCOR; /* RTCOR */
volatile uint8_t dummy6[4]; /* */
/* #define BSC_TOSCORn_COUNT (6) */
volatile uint32_t TOSCOR0; /* TOSCOR0 */
volatile uint32_t TOSCOR1; /* TOSCOR1 */
volatile uint32_t TOSCOR2; /* TOSCOR2 */
volatile uint32_t TOSCOR3; /* TOSCOR3 */
volatile uint32_t TOSCOR4; /* TOSCOR4 */
volatile uint32_t TOSCOR5; /* TOSCOR5 */
volatile uint8_t dummy7[8]; /* */
volatile uint32_t TOSTR; /* TOSTR */
volatile uint32_t TOENR; /* TOENR */
} r_io_bsc_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ceu_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef CEU_IODEFINE_H
#define CEU_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define CEU (*(struct st_ceu *)0xE8210000uL) /* CEU */
/* Start of channel array defines of CEU */
/* Channel array defines of CEUn */
/*(Sample) value = CEUn[ channel ]->CAMOR; */
#define CEUn_COUNT (3)
#define CEUn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
(volatile struct st_ceu_n*)&CEU_A, \
(volatile struct st_ceu_n*)&CEU_B, \
(volatile struct st_ceu_n*)&CEU_M \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CEU_A (*(struct st_ceu_n *)&CEU.CAPSR) /* CEU_A */
#define CEU_B (*(struct st_ceu_n *)&CEU.dummy3111) /* CEU_B */
#define CEU_M (*(struct st_ceu_n *)&CEU.dummy3151) /* CEU_M */
/* End of channel array defines of CEU */
#define CEUCAPSR (CEU.CAPSR)
#define CEUCAPCR (CEU.CAPCR)
#define CEUCAMCR (CEU.CAMCR)
#define CEUCMCYR (CEU.CMCYR)
#define CEUCAMOR_A (CEU.CAMOR_A)
#define CEUCAPWR_A (CEU.CAPWR_A)
#define CEUCAIFR (CEU.CAIFR)
#define CEUCRCNTR (CEU.CRCNTR)
#define CEUCRCMPR (CEU.CRCMPR)
#define CEUCFLCR_A (CEU.CFLCR_A)
#define CEUCFSZR_A (CEU.CFSZR_A)
#define CEUCDWDR_A (CEU.CDWDR_A)
#define CEUCDAYR_A (CEU.CDAYR_A)
#define CEUCDACR_A (CEU.CDACR_A)
#define CEUCDBYR_A (CEU.CDBYR_A)
#define CEUCDBCR_A (CEU.CDBCR_A)
#define CEUCBDSR_A (CEU.CBDSR_A)
#define CEUCFWCR (CEU.CFWCR)
#define CEUCLFCR_A (CEU.CLFCR_A)
#define CEUCDOCR_A (CEU.CDOCR_A)
#define CEUCEIER (CEU.CEIER)
#define CEUCETCR (CEU.CETCR)
#define CEUCSTSR (CEU.CSTSR)
#define CEUCDSSR (CEU.CDSSR)
#define CEUCDAYR2_A (CEU.CDAYR2_A)
#define CEUCDACR2_A (CEU.CDACR2_A)
#define CEUCDBYR2_A (CEU.CDBYR2_A)
#define CEUCDBCR2_A (CEU.CDBCR2_A)
#define CEUCAMOR_B (CEU.CAMOR_B)
#define CEUCAPWR_B (CEU.CAPWR_B)
#define CEUCFLCR_B (CEU.CFLCR_B)
#define CEUCFSZR_B (CEU.CFSZR_B)
#define CEUCDWDR_B (CEU.CDWDR_B)
#define CEUCDAYR_B (CEU.CDAYR_B)
#define CEUCDACR_B (CEU.CDACR_B)
#define CEUCDBYR_B (CEU.CDBYR_B)
#define CEUCDBCR_B (CEU.CDBCR_B)
#define CEUCBDSR_B (CEU.CBDSR_B)
#define CEUCLFCR_B (CEU.CLFCR_B)
#define CEUCDOCR_B (CEU.CDOCR_B)
#define CEUCDAYR2_B (CEU.CDAYR2_B)
#define CEUCDACR2_B (CEU.CDACR2_B)
#define CEUCDBYR2_B (CEU.CDBYR2_B)
#define CEUCDBCR2_B (CEU.CDBCR2_B)
#define CEUCAMOR_M (CEU.CAMOR_M)
#define CEUCAPWR_M (CEU.CAPWR_M)
#define CEUCFLCR_M (CEU.CFLCR_M)
#define CEUCFSZR_M (CEU.CFSZR_M)
#define CEUCDWDR_M (CEU.CDWDR_M)
#define CEUCDAYR_M (CEU.CDAYR_M)
#define CEUCDACR_M (CEU.CDACR_M)
#define CEUCDBYR_M (CEU.CDBYR_M)
#define CEUCDBCR_M (CEU.CDBCR_M)
#define CEUCBDSR_M (CEU.CBDSR_M)
#define CEUCLFCR_M (CEU.CLFCR_M)
#define CEUCDOCR_M (CEU.CDOCR_M)
#define CEUCDAYR2_M (CEU.CDAYR2_M)
#define CEUCDACR2_M (CEU.CDACR2_M)
#define CEUCDBYR2_M (CEU.CDBYR2_M)
#define CEUCDBCR2_M (CEU.CDBCR2_M)
typedef struct st_ceu
{
/* CEU */
/* start of struct st_ceu_n */
volatile uint32_t CAPSR; /* CAPSR */
volatile uint32_t CAPCR; /* CAPCR */
volatile uint32_t CAMCR; /* CAMCR */
volatile uint32_t CMCYR; /* CMCYR */
volatile uint32_t CAMOR_A; /* CAMOR_A */
volatile uint32_t CAPWR_A; /* CAPWR_A */
volatile uint32_t CAIFR; /* CAIFR */
volatile uint8_t dummy305[12]; /* */
volatile uint32_t CRCNTR; /* CRCNTR */
volatile uint32_t CRCMPR; /* CRCMPR */
volatile uint32_t CFLCR_A; /* CFLCR_A */
volatile uint32_t CFSZR_A; /* CFSZR_A */
volatile uint32_t CDWDR_A; /* CDWDR_A */
volatile uint32_t CDAYR_A; /* CDAYR_A */
volatile uint32_t CDACR_A; /* CDACR_A */
volatile uint32_t CDBYR_A; /* CDBYR_A */
volatile uint32_t CDBCR_A; /* CDBCR_A */
volatile uint32_t CBDSR_A; /* CBDSR_A */
volatile uint8_t dummy306[12]; /* */
volatile uint32_t CFWCR; /* CFWCR */
volatile uint32_t CLFCR_A; /* CLFCR_A */
volatile uint32_t CDOCR_A; /* CDOCR_A */
volatile uint8_t dummy307[8]; /* */
volatile uint32_t CEIER; /* CEIER */
volatile uint32_t CETCR; /* CETCR */
volatile uint8_t dummy308[4]; /* */
volatile uint32_t CSTSR; /* CSTSR */
volatile uint8_t dummy309[4]; /* */
volatile uint32_t CDSSR; /* CDSSR */
volatile uint8_t dummy310[8]; /* */
volatile uint32_t CDAYR2_A; /* CDAYR2_A */
volatile uint32_t CDACR2_A; /* CDACR2_A */
volatile uint32_t CDBYR2_A; /* CDBYR2_A */
volatile uint32_t CDBCR2_A; /* CDBCR2_A */
/* end of struct st_ceu_n */
volatile uint8_t dummy3110[3936]; /* */
/* start of struct st_ceu_n */
volatile uint8_t dummy3111[4]; /* */
volatile uint8_t dummy3112[4]; /* */
volatile uint8_t dummy3113[4]; /* */
volatile uint8_t dummy3114[4]; /* */
volatile uint32_t CAMOR_B; /* CAMOR_B */
volatile uint32_t CAPWR_B; /* CAPWR_B */
volatile uint8_t dummy3120[4]; /* */
volatile uint8_t dummy3121[12]; /* */
volatile uint8_t dummy3122[4]; /* */
volatile uint8_t dummy3123[4]; /* */
volatile uint32_t CFLCR_B; /* CFLCR_B */
volatile uint32_t CFSZR_B; /* CFSZR_B */
volatile uint32_t CDWDR_B; /* CDWDR_B */
volatile uint32_t CDAYR_B; /* CDAYR_B */
volatile uint32_t CDACR_B; /* CDACR_B */
volatile uint32_t CDBYR_B; /* CDBYR_B */
volatile uint32_t CDBCR_B; /* CDBCR_B */
volatile uint32_t CBDSR_B; /* CBDSR_B */
volatile uint8_t dummy3130[12]; /* */
volatile uint8_t dummy3131[4]; /* */
volatile uint32_t CLFCR_B; /* CLFCR_B */
volatile uint32_t CDOCR_B; /* CDOCR_B */
volatile uint8_t dummy3140[8]; /* */
volatile uint8_t dummy3141[4]; /* */
volatile uint8_t dummy3142[4]; /* */
volatile uint8_t dummy3143[4]; /* */
volatile uint8_t dummy3144[4]; /* */
volatile uint8_t dummy3145[4]; /* */
volatile uint8_t dummy3146[4]; /* */
volatile uint8_t dummy3147[8]; /* */
volatile uint32_t CDAYR2_B; /* CDAYR2_B */
volatile uint32_t CDACR2_B; /* CDACR2_B */
volatile uint32_t CDBYR2_B; /* CDBYR2_B */
volatile uint32_t CDBCR2_B; /* CDBCR2_B */
/* end of struct st_ceu_n */
volatile uint8_t dummy3150[3936]; /* */
/* start of struct st_ceu_n */
volatile uint8_t dummy3151[4]; /* */
volatile uint8_t dummy3152[4]; /* */
volatile uint8_t dummy3153[4]; /* */
volatile uint8_t dummy3154[4]; /* */
volatile uint32_t CAMOR_M; /* CAMOR_M */
volatile uint32_t CAPWR_M; /* CAPWR_M */
volatile uint8_t dummy3160[4]; /* */
volatile uint8_t dummy3161[12]; /* */
volatile uint8_t dummy3162[4]; /* */
volatile uint8_t dummy3163[4]; /* */
volatile uint32_t CFLCR_M; /* CFLCR_M */
volatile uint32_t CFSZR_M; /* CFSZR_M */
volatile uint32_t CDWDR_M; /* CDWDR_M */
volatile uint32_t CDAYR_M; /* CDAYR_M */
volatile uint32_t CDACR_M; /* CDACR_M */
volatile uint32_t CDBYR_M; /* CDBYR_M */
volatile uint32_t CDBCR_M; /* CDBCR_M */
volatile uint32_t CBDSR_M; /* CBDSR_M */
volatile uint8_t dummy3170[12]; /* */
volatile uint8_t dummy3171[4]; /* */
volatile uint32_t CLFCR_M; /* CLFCR_M */
volatile uint32_t CDOCR_M; /* CDOCR_M */
volatile uint8_t dummy3180[8]; /* */
volatile uint8_t dummy3181[4]; /* */
volatile uint8_t dummy3182[4]; /* */
volatile uint8_t dummy3183[4]; /* */
volatile uint8_t dummy3184[4]; /* */
volatile uint8_t dummy3185[4]; /* */
volatile uint8_t dummy3186[4]; /* */
volatile uint8_t dummy3187[8]; /* */
volatile uint32_t CDAYR2_M; /* CDAYR2_M */
volatile uint32_t CDACR2_M; /* CDACR2_M */
volatile uint32_t CDBYR2_M; /* CDBYR2_M */
volatile uint32_t CDBCR2_M; /* CDBCR2_M */
/* end of struct st_ceu_n */
} r_io_ceu_t;
typedef struct st_ceu_n
{
volatile uint32_t not_common1; /* */
volatile uint32_t not_common2; /* */
volatile uint32_t not_common3; /* */
volatile uint32_t not_common4; /* */
volatile uint32_t CAMOR; /* CAMOR */
volatile uint32_t CAPWR; /* CAPWR */
volatile uint32_t not_common5; /* */
volatile uint8_t dummy322[12]; /* */
volatile uint32_t not_common6; /* */
volatile uint32_t not_common7; /* */
volatile uint32_t CFLCR; /* CFLCR */
volatile uint32_t CFSZR; /* CFSZR */
volatile uint32_t CDWDR; /* CDWDR */
volatile uint32_t CDAYR; /* CDAYR */
volatile uint32_t CDACR; /* CDACR */
volatile uint32_t CDBYR; /* CDBYR */
volatile uint32_t CDBCR; /* CDBCR */
volatile uint32_t CBDSR; /* CBDSR */
volatile uint8_t dummy323[12]; /* */
volatile uint32_t not_common8; /* */
volatile uint32_t CLFCR; /* CLFCR */
volatile uint32_t CDOCR; /* CDOCR */
volatile uint8_t dummy324[8]; /* */
volatile uint32_t not_common9; /* */
volatile uint32_t not_common10; /* */
volatile uint8_t dummy325[4]; /* */
volatile uint32_t not_common11; /* */
volatile uint8_t dummy326[4]; /* */
volatile uint32_t not_common12; /* */
volatile uint8_t dummy327[8]; /* */
volatile uint32_t CDAYR2; /* CDAYR2 */
volatile uint32_t CDACR2; /* CDACR2 */
volatile uint32_t CDBYR2; /* CDBYR2 */
volatile uint32_t CDBCR2; /* CDBCR2 */
} r_io_ceu_n_t;
/* Channel array defines of CEUn (2)*/
#ifdef DECLARE_CEUn_CHANNELS
volatile struct st_ceu_n* CEUn[ CEUn_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CEUn_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CEUn_CHANNELS */
/* End of channel array defines of CEUn (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : cpg_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef CPG_IODEFINE_H
#define CPG_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define CPG (*(struct st_cpg *)0xFCFE0010uL) /* CPG */
/* Start of channel array defines of CPG */
/* Channel array defines of CPG_FROM_SWRSTCR1_ARRAY */
/*(Sample) value = CPG_FROM_SWRSTCR1_ARRAY[ channel ]->SWRSTCR1; */
#define CPG_FROM_SWRSTCR1_ARRAY_COUNT (3)
#define CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SWRSTCR1, &CPG_FROM_SWRSTCR2, &CPG_FROM_SWRSTCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SWRSTCR1 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR1) /* CPG_FROM_SWRSTCR1 */
#define CPG_FROM_SWRSTCR2 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR2) /* CPG_FROM_SWRSTCR2 */
#define CPG_FROM_SWRSTCR3 (*(struct st_cpg_from_swrstcr1 *)&CPG.SWRSTCR3) /* CPG_FROM_SWRSTCR3 */
/* Channel array defines of CPG_FROM_STBCR3_ARRAY */
/*(Sample) value = CPG_FROM_STBCR3_ARRAY[ channel ]->STBCR3; */
#define CPG_FROM_STBCR3_ARRAY_COUNT (10)
#define CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_STBCR3, &CPG_FROM_STBCR4, &CPG_FROM_STBCR5, &CPG_FROM_STBCR6, &CPG_FROM_STBCR7, &CPG_FROM_STBCR8, &CPG_FROM_STBCR9, &CPG_FROM_STBCR10, \
&CPG_FROM_STBCR11, &CPG_FROM_STBCR12 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_STBCR3 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR3) /* CPG_FROM_STBCR3 */
#define CPG_FROM_STBCR4 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR4) /* CPG_FROM_STBCR4 */
#define CPG_FROM_STBCR5 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR5) /* CPG_FROM_STBCR5 */
#define CPG_FROM_STBCR6 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR6) /* CPG_FROM_STBCR6 */
#define CPG_FROM_STBCR7 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR7) /* CPG_FROM_STBCR7 */
#define CPG_FROM_STBCR8 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR8) /* CPG_FROM_STBCR8 */
#define CPG_FROM_STBCR9 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR9) /* CPG_FROM_STBCR9 */
#define CPG_FROM_STBCR10 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR10) /* CPG_FROM_STBCR10 */
#define CPG_FROM_STBCR11 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR11) /* CPG_FROM_STBCR11 */
#define CPG_FROM_STBCR12 (*(struct st_cpg_from_stbcr3 *)&CPG.STBCR12) /* CPG_FROM_STBCR12 */
/* Channel array defines of CPG_FROM_SYSCR1_ARRAY */
/*(Sample) value = CPG_FROM_SYSCR1_ARRAY[ channel ]->SYSCR1; */
#define CPG_FROM_SYSCR1_ARRAY_COUNT (3)
#define CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&CPG_FROM_SYSCR1, &CPG_FROM_SYSCR2, &CPG_FROM_SYSCR3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define CPG_FROM_SYSCR1 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR1) /* CPG_FROM_SYSCR1 */
#define CPG_FROM_SYSCR2 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR2) /* CPG_FROM_SYSCR2 */
#define CPG_FROM_SYSCR3 (*(struct st_cpg_from_syscr1 *)&CPG.SYSCR3) /* CPG_FROM_SYSCR3 */
/* End of channel array defines of CPG */
#define CPGFRQCR (CPG.FRQCR)
#define CPGFRQCR2 (CPG.FRQCR2)
#define CPGCPUSTS (CPG.CPUSTS)
#define CPGSTBCR1 (CPG.STBCR1)
#define CPGSTBCR2 (CPG.STBCR2)
#define CPGSTBREQ1 (CPG.STBREQ1)
#define CPGSTBREQ2 (CPG.STBREQ2)
#define CPGSTBACK1 (CPG.STBACK1)
#define CPGSTBACK2 (CPG.STBACK2)
#define CPGSYSCR1 (CPG.SYSCR1)
#define CPGSYSCR2 (CPG.SYSCR2)
#define CPGSYSCR3 (CPG.SYSCR3)
#define CPGSTBCR3 (CPG.STBCR3)
#define CPGSTBCR4 (CPG.STBCR4)
#define CPGSTBCR5 (CPG.STBCR5)
#define CPGSTBCR6 (CPG.STBCR6)
#define CPGSTBCR7 (CPG.STBCR7)
#define CPGSTBCR8 (CPG.STBCR8)
#define CPGSTBCR9 (CPG.STBCR9)
#define CPGSTBCR10 (CPG.STBCR10)
#define CPGSTBCR11 (CPG.STBCR11)
#define CPGSTBCR12 (CPG.STBCR12)
#define CPGSWRSTCR1 (CPG.SWRSTCR1)
#define CPGSWRSTCR2 (CPG.SWRSTCR2)
#define CPGSWRSTCR3 (CPG.SWRSTCR3)
#define CPGSTBCR13 (CPG.STBCR13)
#define CPGRRAMKP (CPG.RRAMKP)
#define CPGDSCTR (CPG.DSCTR)
#define CPGDSSSR (CPG.DSSSR)
#define CPGDSESR (CPG.DSESR)
#define CPGDSFR (CPG.DSFR)
#define CPGXTALCTR (CPG.XTALCTR)
typedef struct st_cpg
{
/* CPG */
volatile uint16_t FRQCR; /* FRQCR */
volatile uint8_t dummy319[2]; /* */
volatile uint16_t FRQCR2; /* FRQCR2 */
volatile uint8_t dummy320[2]; /* */
volatile uint8_t CPUSTS; /* CPUSTS */
volatile uint8_t dummy321[7]; /* */
volatile uint8_t STBCR1; /* STBCR1 */
volatile uint8_t dummy322[3]; /* */
volatile uint8_t STBCR2; /* STBCR2 */
volatile uint8_t dummy323[11]; /* */
volatile uint8_t STBREQ1; /* STBREQ1 */
volatile uint8_t dummy324[3]; /* */
volatile uint8_t STBREQ2; /* STBREQ2 */
volatile uint8_t dummy325[11]; /* */
volatile uint8_t STBACK1; /* STBACK1 */
volatile uint8_t dummy326[3]; /* */
volatile uint8_t STBACK2; /* STBACK2 */
volatile uint8_t dummy327[955]; /* */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR1; /* SYSCR1 */
volatile uint8_t dummy328[3]; /* */
/* end of struct st_cpg_from_syscr1 */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR2; /* SYSCR2 */
volatile uint8_t dummy329[3]; /* */
/* end of struct st_cpg_from_syscr1 */
/* start of struct st_cpg_from_syscr1 */
volatile uint8_t SYSCR3; /* SYSCR3 */
volatile uint8_t dummy3300[3]; /* */
/* end of struct st_cpg_from_syscr1 */
volatile uint8_t dummy3301[20]; /* */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR3; /* STBCR3 */
volatile uint8_t dummy331[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR4; /* STBCR4 */
volatile uint8_t dummy332[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR5; /* STBCR5 */
volatile uint8_t dummy333[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR6; /* STBCR6 */
volatile uint8_t dummy334[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR7; /* STBCR7 */
volatile uint8_t dummy335[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR8; /* STBCR8 */
volatile uint8_t dummy336[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR9; /* STBCR9 */
volatile uint8_t dummy337[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR10; /* STBCR10 */
volatile uint8_t dummy338[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR11; /* STBCR11 */
volatile uint8_t dummy339[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
/* start of struct st_cpg_from_stbcr3 */
volatile uint8_t STBCR12; /* STBCR12 */
volatile uint8_t dummy3400[3]; /* */
/* end of struct st_cpg_from_stbcr3 */
volatile uint8_t dummy3401[24]; /* */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
volatile uint8_t dummy341[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR2; /* SWRSTCR2 */
volatile uint8_t dummy342[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
/* start of struct st_cpg_from_swrstcr1 */
volatile uint8_t SWRSTCR3; /* SWRSTCR3 */
volatile uint8_t dummy3430[3]; /* */
/* end of struct st_cpg_from_swrstcr1 */
volatile uint8_t dummy3431[4]; /* */
volatile uint8_t STBCR13; /* STBCR13 */
volatile uint8_t dummy344[70543]; /* */
volatile uint8_t RRAMKP; /* RRAMKP */
volatile uint8_t dummy345[1]; /* */
volatile uint8_t DSCTR; /* DSCTR */
volatile uint8_t dummy346[1]; /* */
volatile uint16_t DSSSR; /* DSSSR */
volatile uint16_t DSESR; /* DSESR */
volatile uint16_t DSFR; /* DSFR */
volatile uint8_t dummy347[6]; /* */
volatile uint8_t XTALCTR; /* XTALCTR */
} r_io_cpg_t;
typedef struct st_cpg_from_syscr1
{
volatile uint8_t SYSCR1; /* SYSCR1 */
volatile uint8_t dummy1[3]; /* */
} r_io_cpg_from_syscr1_t;
typedef struct st_cpg_from_stbcr3
{
volatile uint8_t STBCR3; /* STBCR3 */
volatile uint8_t dummy1[3]; /* */
} r_io_cpg_from_stbcr3_t;
typedef struct st_cpg_from_swrstcr1
{
volatile uint8_t SWRSTCR1; /* SWRSTCR1 */
volatile uint8_t dummy1[3]; /* */
} r_io_cpg_from_swrstcr1_t;
/* Channel array defines of CPG (2)*/
#ifdef DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS
volatile struct st_cpg_from_swrstcr1* CPG_FROM_SWRSTCR1_ARRAY[ CPG_FROM_SWRSTCR1_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CPG_FROM_SWRSTCR1_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CPG_FROM_SWRSTCR1_ARRAY_CHANNELS */
#ifdef DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS
volatile struct st_cpg_from_stbcr3* CPG_FROM_STBCR3_ARRAY[ CPG_FROM_STBCR3_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CPG_FROM_STBCR3_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CPG_FROM_STBCR3_ARRAY_CHANNELS */
#ifdef DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS
volatile struct st_cpg_from_syscr1* CPG_FROM_SYSCR1_ARRAY[ CPG_FROM_SYSCR1_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
CPG_FROM_SYSCR1_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_CPG_FROM_SYSCR1_ARRAY_CHANNELS */
/* End of channel array defines of CPG (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,112 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : disc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef DISC_IODEFINE_H
#define DISC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define DISC0 (*(struct st_disc *)0xFCFFA800uL) /* DISC0 */
#define DISC1 (*(struct st_disc *)0xFCFFB000uL) /* DISC1 */
/* Start of channel array defines of DISC */
/* Channel array defines of DISC */
/*(Sample) value = DISC[ channel ]->DOCMCR; */
#define DISC_COUNT (2)
#define DISC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DISC0, &DISC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of DISC */
#define DISC0DOCMCR (DISC0.DOCMCR)
#define DISC0DOCMSTR (DISC0.DOCMSTR)
#define DISC0DOCMCLSTR (DISC0.DOCMCLSTR)
#define DISC0DOCMIENR (DISC0.DOCMIENR)
#define DISC0DOCMPMR (DISC0.DOCMPMR)
#define DISC0DOCMECRCR (DISC0.DOCMECRCR)
#define DISC0DOCMCCRCR (DISC0.DOCMCCRCR)
#define DISC0DOCMSPXR (DISC0.DOCMSPXR)
#define DISC0DOCMSPYR (DISC0.DOCMSPYR)
#define DISC0DOCMSZXR (DISC0.DOCMSZXR)
#define DISC0DOCMSZYR (DISC0.DOCMSZYR)
#define DISC0DOCMCRCIR (DISC0.DOCMCRCIR)
#define DISC1DOCMCR (DISC1.DOCMCR)
#define DISC1DOCMSTR (DISC1.DOCMSTR)
#define DISC1DOCMCLSTR (DISC1.DOCMCLSTR)
#define DISC1DOCMIENR (DISC1.DOCMIENR)
#define DISC1DOCMPMR (DISC1.DOCMPMR)
#define DISC1DOCMECRCR (DISC1.DOCMECRCR)
#define DISC1DOCMCCRCR (DISC1.DOCMCCRCR)
#define DISC1DOCMSPXR (DISC1.DOCMSPXR)
#define DISC1DOCMSPYR (DISC1.DOCMSPYR)
#define DISC1DOCMSZXR (DISC1.DOCMSZXR)
#define DISC1DOCMSZYR (DISC1.DOCMSZYR)
#define DISC1DOCMCRCIR (DISC1.DOCMCRCIR)
typedef struct st_disc
{
/* DISC */
volatile uint32_t DOCMCR; /* DOCMCR */
volatile uint32_t DOCMSTR; /* DOCMSTR */
volatile uint32_t DOCMCLSTR; /* DOCMCLSTR */
volatile uint32_t DOCMIENR; /* DOCMIENR */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t DOCMPMR; /* DOCMPMR */
volatile uint32_t DOCMECRCR; /* DOCMECRCR */
volatile uint32_t DOCMCCRCR; /* DOCMCCRCR */
volatile uint32_t DOCMSPXR; /* DOCMSPXR */
volatile uint32_t DOCMSPYR; /* DOCMSPYR */
volatile uint32_t DOCMSZXR; /* DOCMSZXR */
volatile uint32_t DOCMSZYR; /* DOCMSZYR */
volatile uint32_t DOCMCRCIR; /* DOCMCRCIR */
} r_io_disc_t;
/* Channel array defines of DISC (2)*/
#ifdef DECLARE_DISC_CHANNELS
volatile struct st_disc* DISC[ DISC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DISC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DISC_CHANNELS */
/* End of channel array defines of DISC (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,807 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : dmac_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef DMAC_IODEFINE_H
#define DMAC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
/* Channel array defines of DMACmm */
#define DMACmm_COUNT (8)
#define DMACmm_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DMAC01, &DMAC23, &DMAC45, &DMAC67, &DMAC89, &DMAC1011, &DMAC1213, &DMAC1415 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define DMAC01 (*(struct st_dmars_mm *)&DMAC.DMARS0) /* DMAC0-1 */
#define DMAC23 (*(struct st_dmars_mm *)&DMAC.DMARS1) /* DMAC2-3 */
#define DMAC45 (*(struct st_dmars_mm *)&DMAC.DMARS2) /* DMAC4-5 */
#define DMAC67 (*(struct st_dmars_mm *)&DMAC.DMARS3) /* DMAC6-7 */
#define DMAC89 (*(struct st_dmars_mm *)&DMAC.DMARS4) /* DMAC8-9 */
#define DMAC1011 (*(struct st_dmars_mm *)&DMAC.DMARS5) /* DMAC10-11 */
#define DMAC1213 (*(struct st_dmars_mm *)&DMAC.DMARS6) /* DMAC12-13 */
#define DMAC1415 (*(struct st_dmars_mm *)&DMAC.DMARS7) /* DMAC14-15 */
/*(Sample) value = DMACmm[ channel / 2 ]->DMARS; */
#define DMAC (*(struct st_dmac *)0xE8200000uL) /* DMAC */
/* Start of channel array defines of DMAC */
/* Channel array defines of DMACn */
/*(Sample) value = DMACn[ channel ]->N0SA_n; */
#define DMACn_COUNT (16)
#define DMACn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DMAC0, &DMAC1, &DMAC2, &DMAC3, &DMAC4, &DMAC5, &DMAC6, &DMAC7, \
&DMAC8, &DMAC9, &DMAC10, &DMAC11, &DMAC12, &DMAC13, &DMAC14, &DMAC15 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define DMAC0 (*(struct st_dmac_n *)&DMAC.N0SA_0) /* DMAC0 */
#define DMAC1 (*(struct st_dmac_n *)&DMAC.N0SA_1) /* DMAC1 */
#define DMAC2 (*(struct st_dmac_n *)&DMAC.N0SA_2) /* DMAC2 */
#define DMAC3 (*(struct st_dmac_n *)&DMAC.N0SA_3) /* DMAC3 */
#define DMAC4 (*(struct st_dmac_n *)&DMAC.N0SA_4) /* DMAC4 */
#define DMAC5 (*(struct st_dmac_n *)&DMAC.N0SA_5) /* DMAC5 */
#define DMAC6 (*(struct st_dmac_n *)&DMAC.N0SA_6) /* DMAC6 */
#define DMAC7 (*(struct st_dmac_n *)&DMAC.N0SA_7) /* DMAC7 */
#define DMAC8 (*(struct st_dmac_n *)&DMAC.N0SA_8) /* DMAC8 */
#define DMAC9 (*(struct st_dmac_n *)&DMAC.N0SA_9) /* DMAC9 */
#define DMAC10 (*(struct st_dmac_n *)&DMAC.N0SA_10) /* DMAC10 */
#define DMAC11 (*(struct st_dmac_n *)&DMAC.N0SA_11) /* DMAC11 */
#define DMAC12 (*(struct st_dmac_n *)&DMAC.N0SA_12) /* DMAC12 */
#define DMAC13 (*(struct st_dmac_n *)&DMAC.N0SA_13) /* DMAC13 */
#define DMAC14 (*(struct st_dmac_n *)&DMAC.N0SA_14) /* DMAC14 */
#define DMAC15 (*(struct st_dmac_n *)&DMAC.N0SA_15) /* DMAC15 */
/* Channel array defines of DMACnn */
/*(Sample) value = DMACnn[ channel / 8 ]->DCTRL_0_7; */
#define DMACnn_COUNT (2)
#define DMACnn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DMAC07, &DMAC815 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define DMAC07 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_0_7) /* DMAC07 */
#define DMAC815 (*(struct st_dmaccommon_n *)&DMAC.DCTRL_8_15) /* DMAC815 */
/* End of channel array defines of DMAC */
#define DMACN0SA_0 (DMAC.N0SA_0)
#define DMACN0DA_0 (DMAC.N0DA_0)
#define DMACN0TB_0 (DMAC.N0TB_0)
#define DMACN1SA_0 (DMAC.N1SA_0)
#define DMACN1DA_0 (DMAC.N1DA_0)
#define DMACN1TB_0 (DMAC.N1TB_0)
#define DMACCRSA_0 (DMAC.CRSA_0)
#define DMACCRDA_0 (DMAC.CRDA_0)
#define DMACCRTB_0 (DMAC.CRTB_0)
#define DMACCHSTAT_0 (DMAC.CHSTAT_0)
#define DMACCHCTRL_0 (DMAC.CHCTRL_0)
#define DMACCHCFG_0 (DMAC.CHCFG_0)
#define DMACCHITVL_0 (DMAC.CHITVL_0)
#define DMACCHEXT_0 (DMAC.CHEXT_0)
#define DMACNXLA_0 (DMAC.NXLA_0)
#define DMACCRLA_0 (DMAC.CRLA_0)
#define DMACN0SA_1 (DMAC.N0SA_1)
#define DMACN0DA_1 (DMAC.N0DA_1)
#define DMACN0TB_1 (DMAC.N0TB_1)
#define DMACN1SA_1 (DMAC.N1SA_1)
#define DMACN1DA_1 (DMAC.N1DA_1)
#define DMACN1TB_1 (DMAC.N1TB_1)
#define DMACCRSA_1 (DMAC.CRSA_1)
#define DMACCRDA_1 (DMAC.CRDA_1)
#define DMACCRTB_1 (DMAC.CRTB_1)
#define DMACCHSTAT_1 (DMAC.CHSTAT_1)
#define DMACCHCTRL_1 (DMAC.CHCTRL_1)
#define DMACCHCFG_1 (DMAC.CHCFG_1)
#define DMACCHITVL_1 (DMAC.CHITVL_1)
#define DMACCHEXT_1 (DMAC.CHEXT_1)
#define DMACNXLA_1 (DMAC.NXLA_1)
#define DMACCRLA_1 (DMAC.CRLA_1)
#define DMACN0SA_2 (DMAC.N0SA_2)
#define DMACN0DA_2 (DMAC.N0DA_2)
#define DMACN0TB_2 (DMAC.N0TB_2)
#define DMACN1SA_2 (DMAC.N1SA_2)
#define DMACN1DA_2 (DMAC.N1DA_2)
#define DMACN1TB_2 (DMAC.N1TB_2)
#define DMACCRSA_2 (DMAC.CRSA_2)
#define DMACCRDA_2 (DMAC.CRDA_2)
#define DMACCRTB_2 (DMAC.CRTB_2)
#define DMACCHSTAT_2 (DMAC.CHSTAT_2)
#define DMACCHCTRL_2 (DMAC.CHCTRL_2)
#define DMACCHCFG_2 (DMAC.CHCFG_2)
#define DMACCHITVL_2 (DMAC.CHITVL_2)
#define DMACCHEXT_2 (DMAC.CHEXT_2)
#define DMACNXLA_2 (DMAC.NXLA_2)
#define DMACCRLA_2 (DMAC.CRLA_2)
#define DMACN0SA_3 (DMAC.N0SA_3)
#define DMACN0DA_3 (DMAC.N0DA_3)
#define DMACN0TB_3 (DMAC.N0TB_3)
#define DMACN1SA_3 (DMAC.N1SA_3)
#define DMACN1DA_3 (DMAC.N1DA_3)
#define DMACN1TB_3 (DMAC.N1TB_3)
#define DMACCRSA_3 (DMAC.CRSA_3)
#define DMACCRDA_3 (DMAC.CRDA_3)
#define DMACCRTB_3 (DMAC.CRTB_3)
#define DMACCHSTAT_3 (DMAC.CHSTAT_3)
#define DMACCHCTRL_3 (DMAC.CHCTRL_3)
#define DMACCHCFG_3 (DMAC.CHCFG_3)
#define DMACCHITVL_3 (DMAC.CHITVL_3)
#define DMACCHEXT_3 (DMAC.CHEXT_3)
#define DMACNXLA_3 (DMAC.NXLA_3)
#define DMACCRLA_3 (DMAC.CRLA_3)
#define DMACN0SA_4 (DMAC.N0SA_4)
#define DMACN0DA_4 (DMAC.N0DA_4)
#define DMACN0TB_4 (DMAC.N0TB_4)
#define DMACN1SA_4 (DMAC.N1SA_4)
#define DMACN1DA_4 (DMAC.N1DA_4)
#define DMACN1TB_4 (DMAC.N1TB_4)
#define DMACCRSA_4 (DMAC.CRSA_4)
#define DMACCRDA_4 (DMAC.CRDA_4)
#define DMACCRTB_4 (DMAC.CRTB_4)
#define DMACCHSTAT_4 (DMAC.CHSTAT_4)
#define DMACCHCTRL_4 (DMAC.CHCTRL_4)
#define DMACCHCFG_4 (DMAC.CHCFG_4)
#define DMACCHITVL_4 (DMAC.CHITVL_4)
#define DMACCHEXT_4 (DMAC.CHEXT_4)
#define DMACNXLA_4 (DMAC.NXLA_4)
#define DMACCRLA_4 (DMAC.CRLA_4)
#define DMACN0SA_5 (DMAC.N0SA_5)
#define DMACN0DA_5 (DMAC.N0DA_5)
#define DMACN0TB_5 (DMAC.N0TB_5)
#define DMACN1SA_5 (DMAC.N1SA_5)
#define DMACN1DA_5 (DMAC.N1DA_5)
#define DMACN1TB_5 (DMAC.N1TB_5)
#define DMACCRSA_5 (DMAC.CRSA_5)
#define DMACCRDA_5 (DMAC.CRDA_5)
#define DMACCRTB_5 (DMAC.CRTB_5)
#define DMACCHSTAT_5 (DMAC.CHSTAT_5)
#define DMACCHCTRL_5 (DMAC.CHCTRL_5)
#define DMACCHCFG_5 (DMAC.CHCFG_5)
#define DMACCHITVL_5 (DMAC.CHITVL_5)
#define DMACCHEXT_5 (DMAC.CHEXT_5)
#define DMACNXLA_5 (DMAC.NXLA_5)
#define DMACCRLA_5 (DMAC.CRLA_5)
#define DMACN0SA_6 (DMAC.N0SA_6)
#define DMACN0DA_6 (DMAC.N0DA_6)
#define DMACN0TB_6 (DMAC.N0TB_6)
#define DMACN1SA_6 (DMAC.N1SA_6)
#define DMACN1DA_6 (DMAC.N1DA_6)
#define DMACN1TB_6 (DMAC.N1TB_6)
#define DMACCRSA_6 (DMAC.CRSA_6)
#define DMACCRDA_6 (DMAC.CRDA_6)
#define DMACCRTB_6 (DMAC.CRTB_6)
#define DMACCHSTAT_6 (DMAC.CHSTAT_6)
#define DMACCHCTRL_6 (DMAC.CHCTRL_6)
#define DMACCHCFG_6 (DMAC.CHCFG_6)
#define DMACCHITVL_6 (DMAC.CHITVL_6)
#define DMACCHEXT_6 (DMAC.CHEXT_6)
#define DMACNXLA_6 (DMAC.NXLA_6)
#define DMACCRLA_6 (DMAC.CRLA_6)
#define DMACN0SA_7 (DMAC.N0SA_7)
#define DMACN0DA_7 (DMAC.N0DA_7)
#define DMACN0TB_7 (DMAC.N0TB_7)
#define DMACN1SA_7 (DMAC.N1SA_7)
#define DMACN1DA_7 (DMAC.N1DA_7)
#define DMACN1TB_7 (DMAC.N1TB_7)
#define DMACCRSA_7 (DMAC.CRSA_7)
#define DMACCRDA_7 (DMAC.CRDA_7)
#define DMACCRTB_7 (DMAC.CRTB_7)
#define DMACCHSTAT_7 (DMAC.CHSTAT_7)
#define DMACCHCTRL_7 (DMAC.CHCTRL_7)
#define DMACCHCFG_7 (DMAC.CHCFG_7)
#define DMACCHITVL_7 (DMAC.CHITVL_7)
#define DMACCHEXT_7 (DMAC.CHEXT_7)
#define DMACNXLA_7 (DMAC.NXLA_7)
#define DMACCRLA_7 (DMAC.CRLA_7)
#define DMACDCTRL_0_7 (DMAC.DCTRL_0_7)
#define DMACDSTAT_EN_0_7 (DMAC.DSTAT_EN_0_7)
#define DMACDSTAT_ER_0_7 (DMAC.DSTAT_ER_0_7)
#define DMACDSTAT_END_0_7 (DMAC.DSTAT_END_0_7)
#define DMACDSTAT_TC_0_7 (DMAC.DSTAT_TC_0_7)
#define DMACDSTAT_SUS_0_7 (DMAC.DSTAT_SUS_0_7)
#define DMACN0SA_8 (DMAC.N0SA_8)
#define DMACN0DA_8 (DMAC.N0DA_8)
#define DMACN0TB_8 (DMAC.N0TB_8)
#define DMACN1SA_8 (DMAC.N1SA_8)
#define DMACN1DA_8 (DMAC.N1DA_8)
#define DMACN1TB_8 (DMAC.N1TB_8)
#define DMACCRSA_8 (DMAC.CRSA_8)
#define DMACCRDA_8 (DMAC.CRDA_8)
#define DMACCRTB_8 (DMAC.CRTB_8)
#define DMACCHSTAT_8 (DMAC.CHSTAT_8)
#define DMACCHCTRL_8 (DMAC.CHCTRL_8)
#define DMACCHCFG_8 (DMAC.CHCFG_8)
#define DMACCHITVL_8 (DMAC.CHITVL_8)
#define DMACCHEXT_8 (DMAC.CHEXT_8)
#define DMACNXLA_8 (DMAC.NXLA_8)
#define DMACCRLA_8 (DMAC.CRLA_8)
#define DMACN0SA_9 (DMAC.N0SA_9)
#define DMACN0DA_9 (DMAC.N0DA_9)
#define DMACN0TB_9 (DMAC.N0TB_9)
#define DMACN1SA_9 (DMAC.N1SA_9)
#define DMACN1DA_9 (DMAC.N1DA_9)
#define DMACN1TB_9 (DMAC.N1TB_9)
#define DMACCRSA_9 (DMAC.CRSA_9)
#define DMACCRDA_9 (DMAC.CRDA_9)
#define DMACCRTB_9 (DMAC.CRTB_9)
#define DMACCHSTAT_9 (DMAC.CHSTAT_9)
#define DMACCHCTRL_9 (DMAC.CHCTRL_9)
#define DMACCHCFG_9 (DMAC.CHCFG_9)
#define DMACCHITVL_9 (DMAC.CHITVL_9)
#define DMACCHEXT_9 (DMAC.CHEXT_9)
#define DMACNXLA_9 (DMAC.NXLA_9)
#define DMACCRLA_9 (DMAC.CRLA_9)
#define DMACN0SA_10 (DMAC.N0SA_10)
#define DMACN0DA_10 (DMAC.N0DA_10)
#define DMACN0TB_10 (DMAC.N0TB_10)
#define DMACN1SA_10 (DMAC.N1SA_10)
#define DMACN1DA_10 (DMAC.N1DA_10)
#define DMACN1TB_10 (DMAC.N1TB_10)
#define DMACCRSA_10 (DMAC.CRSA_10)
#define DMACCRDA_10 (DMAC.CRDA_10)
#define DMACCRTB_10 (DMAC.CRTB_10)
#define DMACCHSTAT_10 (DMAC.CHSTAT_10)
#define DMACCHCTRL_10 (DMAC.CHCTRL_10)
#define DMACCHCFG_10 (DMAC.CHCFG_10)
#define DMACCHITVL_10 (DMAC.CHITVL_10)
#define DMACCHEXT_10 (DMAC.CHEXT_10)
#define DMACNXLA_10 (DMAC.NXLA_10)
#define DMACCRLA_10 (DMAC.CRLA_10)
#define DMACN0SA_11 (DMAC.N0SA_11)
#define DMACN0DA_11 (DMAC.N0DA_11)
#define DMACN0TB_11 (DMAC.N0TB_11)
#define DMACN1SA_11 (DMAC.N1SA_11)
#define DMACN1DA_11 (DMAC.N1DA_11)
#define DMACN1TB_11 (DMAC.N1TB_11)
#define DMACCRSA_11 (DMAC.CRSA_11)
#define DMACCRDA_11 (DMAC.CRDA_11)
#define DMACCRTB_11 (DMAC.CRTB_11)
#define DMACCHSTAT_11 (DMAC.CHSTAT_11)
#define DMACCHCTRL_11 (DMAC.CHCTRL_11)
#define DMACCHCFG_11 (DMAC.CHCFG_11)
#define DMACCHITVL_11 (DMAC.CHITVL_11)
#define DMACCHEXT_11 (DMAC.CHEXT_11)
#define DMACNXLA_11 (DMAC.NXLA_11)
#define DMACCRLA_11 (DMAC.CRLA_11)
#define DMACN0SA_12 (DMAC.N0SA_12)
#define DMACN0DA_12 (DMAC.N0DA_12)
#define DMACN0TB_12 (DMAC.N0TB_12)
#define DMACN1SA_12 (DMAC.N1SA_12)
#define DMACN1DA_12 (DMAC.N1DA_12)
#define DMACN1TB_12 (DMAC.N1TB_12)
#define DMACCRSA_12 (DMAC.CRSA_12)
#define DMACCRDA_12 (DMAC.CRDA_12)
#define DMACCRTB_12 (DMAC.CRTB_12)
#define DMACCHSTAT_12 (DMAC.CHSTAT_12)
#define DMACCHCTRL_12 (DMAC.CHCTRL_12)
#define DMACCHCFG_12 (DMAC.CHCFG_12)
#define DMACCHITVL_12 (DMAC.CHITVL_12)
#define DMACCHEXT_12 (DMAC.CHEXT_12)
#define DMACNXLA_12 (DMAC.NXLA_12)
#define DMACCRLA_12 (DMAC.CRLA_12)
#define DMACN0SA_13 (DMAC.N0SA_13)
#define DMACN0DA_13 (DMAC.N0DA_13)
#define DMACN0TB_13 (DMAC.N0TB_13)
#define DMACN1SA_13 (DMAC.N1SA_13)
#define DMACN1DA_13 (DMAC.N1DA_13)
#define DMACN1TB_13 (DMAC.N1TB_13)
#define DMACCRSA_13 (DMAC.CRSA_13)
#define DMACCRDA_13 (DMAC.CRDA_13)
#define DMACCRTB_13 (DMAC.CRTB_13)
#define DMACCHSTAT_13 (DMAC.CHSTAT_13)
#define DMACCHCTRL_13 (DMAC.CHCTRL_13)
#define DMACCHCFG_13 (DMAC.CHCFG_13)
#define DMACCHITVL_13 (DMAC.CHITVL_13)
#define DMACCHEXT_13 (DMAC.CHEXT_13)
#define DMACNXLA_13 (DMAC.NXLA_13)
#define DMACCRLA_13 (DMAC.CRLA_13)
#define DMACN0SA_14 (DMAC.N0SA_14)
#define DMACN0DA_14 (DMAC.N0DA_14)
#define DMACN0TB_14 (DMAC.N0TB_14)
#define DMACN1SA_14 (DMAC.N1SA_14)
#define DMACN1DA_14 (DMAC.N1DA_14)
#define DMACN1TB_14 (DMAC.N1TB_14)
#define DMACCRSA_14 (DMAC.CRSA_14)
#define DMACCRDA_14 (DMAC.CRDA_14)
#define DMACCRTB_14 (DMAC.CRTB_14)
#define DMACCHSTAT_14 (DMAC.CHSTAT_14)
#define DMACCHCTRL_14 (DMAC.CHCTRL_14)
#define DMACCHCFG_14 (DMAC.CHCFG_14)
#define DMACCHITVL_14 (DMAC.CHITVL_14)
#define DMACCHEXT_14 (DMAC.CHEXT_14)
#define DMACNXLA_14 (DMAC.NXLA_14)
#define DMACCRLA_14 (DMAC.CRLA_14)
#define DMACN0SA_15 (DMAC.N0SA_15)
#define DMACN0DA_15 (DMAC.N0DA_15)
#define DMACN0TB_15 (DMAC.N0TB_15)
#define DMACN1SA_15 (DMAC.N1SA_15)
#define DMACN1DA_15 (DMAC.N1DA_15)
#define DMACN1TB_15 (DMAC.N1TB_15)
#define DMACCRSA_15 (DMAC.CRSA_15)
#define DMACCRDA_15 (DMAC.CRDA_15)
#define DMACCRTB_15 (DMAC.CRTB_15)
#define DMACCHSTAT_15 (DMAC.CHSTAT_15)
#define DMACCHCTRL_15 (DMAC.CHCTRL_15)
#define DMACCHCFG_15 (DMAC.CHCFG_15)
#define DMACCHITVL_15 (DMAC.CHITVL_15)
#define DMACCHEXT_15 (DMAC.CHEXT_15)
#define DMACNXLA_15 (DMAC.NXLA_15)
#define DMACCRLA_15 (DMAC.CRLA_15)
#define DMACDCTRL_8_15 (DMAC.DCTRL_8_15)
#define DMACDSTAT_EN_8_15 (DMAC.DSTAT_EN_8_15)
#define DMACDSTAT_ER_8_15 (DMAC.DSTAT_ER_8_15)
#define DMACDSTAT_END_8_15 (DMAC.DSTAT_END_8_15)
#define DMACDSTAT_TC_8_15 (DMAC.DSTAT_TC_8_15)
#define DMACDSTAT_SUS_8_15 (DMAC.DSTAT_SUS_8_15)
#define DMACDMARS0 (DMAC.DMARS0)
#define DMACDMARS1 (DMAC.DMARS1)
#define DMACDMARS2 (DMAC.DMARS2)
#define DMACDMARS3 (DMAC.DMARS3)
#define DMACDMARS4 (DMAC.DMARS4)
#define DMACDMARS5 (DMAC.DMARS5)
#define DMACDMARS6 (DMAC.DMARS6)
#define DMACDMARS7 (DMAC.DMARS7)
typedef struct st_dmars_mm
{
volatile uint32_t DMARS; /* DMARS */
} r_io_dmars_mm_t;
typedef struct st_dmac
{
/* DMAC */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_0; /* N0SA_0 */
volatile uint32_t N0DA_0; /* N0DA_0 */
volatile uint32_t N0TB_0; /* N0TB_0 */
volatile uint32_t N1SA_0; /* N1SA_0 */
volatile uint32_t N1DA_0; /* N1DA_0 */
volatile uint32_t N1TB_0; /* N1TB_0 */
volatile uint32_t CRSA_0; /* CRSA_0 */
volatile uint32_t CRDA_0; /* CRDA_0 */
volatile uint32_t CRTB_0; /* CRTB_0 */
volatile uint32_t CHSTAT_0; /* CHSTAT_0 */
volatile uint32_t CHCTRL_0; /* CHCTRL_0 */
volatile uint32_t CHCFG_0; /* CHCFG_0 */
volatile uint32_t CHITVL_0; /* CHITVL_0 */
volatile uint32_t CHEXT_0; /* CHEXT_0 */
volatile uint32_t NXLA_0; /* NXLA_0 */
volatile uint32_t CRLA_0; /* CRLA_0 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_1; /* N0SA_1 */
volatile uint32_t N0DA_1; /* N0DA_1 */
volatile uint32_t N0TB_1; /* N0TB_1 */
volatile uint32_t N1SA_1; /* N1SA_1 */
volatile uint32_t N1DA_1; /* N1DA_1 */
volatile uint32_t N1TB_1; /* N1TB_1 */
volatile uint32_t CRSA_1; /* CRSA_1 */
volatile uint32_t CRDA_1; /* CRDA_1 */
volatile uint32_t CRTB_1; /* CRTB_1 */
volatile uint32_t CHSTAT_1; /* CHSTAT_1 */
volatile uint32_t CHCTRL_1; /* CHCTRL_1 */
volatile uint32_t CHCFG_1; /* CHCFG_1 */
volatile uint32_t CHITVL_1; /* CHITVL_1 */
volatile uint32_t CHEXT_1; /* CHEXT_1 */
volatile uint32_t NXLA_1; /* NXLA_1 */
volatile uint32_t CRLA_1; /* CRLA_1 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_2; /* N0SA_2 */
volatile uint32_t N0DA_2; /* N0DA_2 */
volatile uint32_t N0TB_2; /* N0TB_2 */
volatile uint32_t N1SA_2; /* N1SA_2 */
volatile uint32_t N1DA_2; /* N1DA_2 */
volatile uint32_t N1TB_2; /* N1TB_2 */
volatile uint32_t CRSA_2; /* CRSA_2 */
volatile uint32_t CRDA_2; /* CRDA_2 */
volatile uint32_t CRTB_2; /* CRTB_2 */
volatile uint32_t CHSTAT_2; /* CHSTAT_2 */
volatile uint32_t CHCTRL_2; /* CHCTRL_2 */
volatile uint32_t CHCFG_2; /* CHCFG_2 */
volatile uint32_t CHITVL_2; /* CHITVL_2 */
volatile uint32_t CHEXT_2; /* CHEXT_2 */
volatile uint32_t NXLA_2; /* NXLA_2 */
volatile uint32_t CRLA_2; /* CRLA_2 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_3; /* N0SA_3 */
volatile uint32_t N0DA_3; /* N0DA_3 */
volatile uint32_t N0TB_3; /* N0TB_3 */
volatile uint32_t N1SA_3; /* N1SA_3 */
volatile uint32_t N1DA_3; /* N1DA_3 */
volatile uint32_t N1TB_3; /* N1TB_3 */
volatile uint32_t CRSA_3; /* CRSA_3 */
volatile uint32_t CRDA_3; /* CRDA_3 */
volatile uint32_t CRTB_3; /* CRTB_3 */
volatile uint32_t CHSTAT_3; /* CHSTAT_3 */
volatile uint32_t CHCTRL_3; /* CHCTRL_3 */
volatile uint32_t CHCFG_3; /* CHCFG_3 */
volatile uint32_t CHITVL_3; /* CHITVL_3 */
volatile uint32_t CHEXT_3; /* CHEXT_3 */
volatile uint32_t NXLA_3; /* NXLA_3 */
volatile uint32_t CRLA_3; /* CRLA_3 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_4; /* N0SA_4 */
volatile uint32_t N0DA_4; /* N0DA_4 */
volatile uint32_t N0TB_4; /* N0TB_4 */
volatile uint32_t N1SA_4; /* N1SA_4 */
volatile uint32_t N1DA_4; /* N1DA_4 */
volatile uint32_t N1TB_4; /* N1TB_4 */
volatile uint32_t CRSA_4; /* CRSA_4 */
volatile uint32_t CRDA_4; /* CRDA_4 */
volatile uint32_t CRTB_4; /* CRTB_4 */
volatile uint32_t CHSTAT_4; /* CHSTAT_4 */
volatile uint32_t CHCTRL_4; /* CHCTRL_4 */
volatile uint32_t CHCFG_4; /* CHCFG_4 */
volatile uint32_t CHITVL_4; /* CHITVL_4 */
volatile uint32_t CHEXT_4; /* CHEXT_4 */
volatile uint32_t NXLA_4; /* NXLA_4 */
volatile uint32_t CRLA_4; /* CRLA_4 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_5; /* N0SA_5 */
volatile uint32_t N0DA_5; /* N0DA_5 */
volatile uint32_t N0TB_5; /* N0TB_5 */
volatile uint32_t N1SA_5; /* N1SA_5 */
volatile uint32_t N1DA_5; /* N1DA_5 */
volatile uint32_t N1TB_5; /* N1TB_5 */
volatile uint32_t CRSA_5; /* CRSA_5 */
volatile uint32_t CRDA_5; /* CRDA_5 */
volatile uint32_t CRTB_5; /* CRTB_5 */
volatile uint32_t CHSTAT_5; /* CHSTAT_5 */
volatile uint32_t CHCTRL_5; /* CHCTRL_5 */
volatile uint32_t CHCFG_5; /* CHCFG_5 */
volatile uint32_t CHITVL_5; /* CHITVL_5 */
volatile uint32_t CHEXT_5; /* CHEXT_5 */
volatile uint32_t NXLA_5; /* NXLA_5 */
volatile uint32_t CRLA_5; /* CRLA_5 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_6; /* N0SA_6 */
volatile uint32_t N0DA_6; /* N0DA_6 */
volatile uint32_t N0TB_6; /* N0TB_6 */
volatile uint32_t N1SA_6; /* N1SA_6 */
volatile uint32_t N1DA_6; /* N1DA_6 */
volatile uint32_t N1TB_6; /* N1TB_6 */
volatile uint32_t CRSA_6; /* CRSA_6 */
volatile uint32_t CRDA_6; /* CRDA_6 */
volatile uint32_t CRTB_6; /* CRTB_6 */
volatile uint32_t CHSTAT_6; /* CHSTAT_6 */
volatile uint32_t CHCTRL_6; /* CHCTRL_6 */
volatile uint32_t CHCFG_6; /* CHCFG_6 */
volatile uint32_t CHITVL_6; /* CHITVL_6 */
volatile uint32_t CHEXT_6; /* CHEXT_6 */
volatile uint32_t NXLA_6; /* NXLA_6 */
volatile uint32_t CRLA_6; /* CRLA_6 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_7; /* N0SA_7 */
volatile uint32_t N0DA_7; /* N0DA_7 */
volatile uint32_t N0TB_7; /* N0TB_7 */
volatile uint32_t N1SA_7; /* N1SA_7 */
volatile uint32_t N1DA_7; /* N1DA_7 */
volatile uint32_t N1TB_7; /* N1TB_7 */
volatile uint32_t CRSA_7; /* CRSA_7 */
volatile uint32_t CRDA_7; /* CRDA_7 */
volatile uint32_t CRTB_7; /* CRTB_7 */
volatile uint32_t CHSTAT_7; /* CHSTAT_7 */
volatile uint32_t CHCTRL_7; /* CHCTRL_7 */
volatile uint32_t CHCFG_7; /* CHCFG_7 */
volatile uint32_t CHITVL_7; /* CHITVL_7 */
volatile uint32_t CHEXT_7; /* CHEXT_7 */
volatile uint32_t NXLA_7; /* NXLA_7 */
volatile uint32_t CRLA_7; /* CRLA_7 */
/* end of struct st_dmac_n */
volatile uint8_t dummy187[256]; /* */
/* start of struct st_dmaccommon_n */
volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
volatile uint8_t dummy188[12]; /* */
volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
/* end of struct st_dmaccommon_n */
volatile uint8_t dummy189[220]; /* */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_8; /* N0SA_8 */
volatile uint32_t N0DA_8; /* N0DA_8 */
volatile uint32_t N0TB_8; /* N0TB_8 */
volatile uint32_t N1SA_8; /* N1SA_8 */
volatile uint32_t N1DA_8; /* N1DA_8 */
volatile uint32_t N1TB_8; /* N1TB_8 */
volatile uint32_t CRSA_8; /* CRSA_8 */
volatile uint32_t CRDA_8; /* CRDA_8 */
volatile uint32_t CRTB_8; /* CRTB_8 */
volatile uint32_t CHSTAT_8; /* CHSTAT_8 */
volatile uint32_t CHCTRL_8; /* CHCTRL_8 */
volatile uint32_t CHCFG_8; /* CHCFG_8 */
volatile uint32_t CHITVL_8; /* CHITVL_8 */
volatile uint32_t CHEXT_8; /* CHEXT_8 */
volatile uint32_t NXLA_8; /* NXLA_8 */
volatile uint32_t CRLA_8; /* CRLA_8 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_9; /* N0SA_9 */
volatile uint32_t N0DA_9; /* N0DA_9 */
volatile uint32_t N0TB_9; /* N0TB_9 */
volatile uint32_t N1SA_9; /* N1SA_9 */
volatile uint32_t N1DA_9; /* N1DA_9 */
volatile uint32_t N1TB_9; /* N1TB_9 */
volatile uint32_t CRSA_9; /* CRSA_9 */
volatile uint32_t CRDA_9; /* CRDA_9 */
volatile uint32_t CRTB_9; /* CRTB_9 */
volatile uint32_t CHSTAT_9; /* CHSTAT_9 */
volatile uint32_t CHCTRL_9; /* CHCTRL_9 */
volatile uint32_t CHCFG_9; /* CHCFG_9 */
volatile uint32_t CHITVL_9; /* CHITVL_9 */
volatile uint32_t CHEXT_9; /* CHEXT_9 */
volatile uint32_t NXLA_9; /* NXLA_9 */
volatile uint32_t CRLA_9; /* CRLA_9 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_10; /* N0SA_10 */
volatile uint32_t N0DA_10; /* N0DA_10 */
volatile uint32_t N0TB_10; /* N0TB_10 */
volatile uint32_t N1SA_10; /* N1SA_10 */
volatile uint32_t N1DA_10; /* N1DA_10 */
volatile uint32_t N1TB_10; /* N1TB_10 */
volatile uint32_t CRSA_10; /* CRSA_10 */
volatile uint32_t CRDA_10; /* CRDA_10 */
volatile uint32_t CRTB_10; /* CRTB_10 */
volatile uint32_t CHSTAT_10; /* CHSTAT_10 */
volatile uint32_t CHCTRL_10; /* CHCTRL_10 */
volatile uint32_t CHCFG_10; /* CHCFG_10 */
volatile uint32_t CHITVL_10; /* CHITVL_10 */
volatile uint32_t CHEXT_10; /* CHEXT_10 */
volatile uint32_t NXLA_10; /* NXLA_10 */
volatile uint32_t CRLA_10; /* CRLA_10 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_11; /* N0SA_11 */
volatile uint32_t N0DA_11; /* N0DA_11 */
volatile uint32_t N0TB_11; /* N0TB_11 */
volatile uint32_t N1SA_11; /* N1SA_11 */
volatile uint32_t N1DA_11; /* N1DA_11 */
volatile uint32_t N1TB_11; /* N1TB_11 */
volatile uint32_t CRSA_11; /* CRSA_11 */
volatile uint32_t CRDA_11; /* CRDA_11 */
volatile uint32_t CRTB_11; /* CRTB_11 */
volatile uint32_t CHSTAT_11; /* CHSTAT_11 */
volatile uint32_t CHCTRL_11; /* CHCTRL_11 */
volatile uint32_t CHCFG_11; /* CHCFG_11 */
volatile uint32_t CHITVL_11; /* CHITVL_11 */
volatile uint32_t CHEXT_11; /* CHEXT_11 */
volatile uint32_t NXLA_11; /* NXLA_11 */
volatile uint32_t CRLA_11; /* CRLA_11 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_12; /* N0SA_12 */
volatile uint32_t N0DA_12; /* N0DA_12 */
volatile uint32_t N0TB_12; /* N0TB_12 */
volatile uint32_t N1SA_12; /* N1SA_12 */
volatile uint32_t N1DA_12; /* N1DA_12 */
volatile uint32_t N1TB_12; /* N1TB_12 */
volatile uint32_t CRSA_12; /* CRSA_12 */
volatile uint32_t CRDA_12; /* CRDA_12 */
volatile uint32_t CRTB_12; /* CRTB_12 */
volatile uint32_t CHSTAT_12; /* CHSTAT_12 */
volatile uint32_t CHCTRL_12; /* CHCTRL_12 */
volatile uint32_t CHCFG_12; /* CHCFG_12 */
volatile uint32_t CHITVL_12; /* CHITVL_12 */
volatile uint32_t CHEXT_12; /* CHEXT_12 */
volatile uint32_t NXLA_12; /* NXLA_12 */
volatile uint32_t CRLA_12; /* CRLA_12 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_13; /* N0SA_13 */
volatile uint32_t N0DA_13; /* N0DA_13 */
volatile uint32_t N0TB_13; /* N0TB_13 */
volatile uint32_t N1SA_13; /* N1SA_13 */
volatile uint32_t N1DA_13; /* N1DA_13 */
volatile uint32_t N1TB_13; /* N1TB_13 */
volatile uint32_t CRSA_13; /* CRSA_13 */
volatile uint32_t CRDA_13; /* CRDA_13 */
volatile uint32_t CRTB_13; /* CRTB_13 */
volatile uint32_t CHSTAT_13; /* CHSTAT_13 */
volatile uint32_t CHCTRL_13; /* CHCTRL_13 */
volatile uint32_t CHCFG_13; /* CHCFG_13 */
volatile uint32_t CHITVL_13; /* CHITVL_13 */
volatile uint32_t CHEXT_13; /* CHEXT_13 */
volatile uint32_t NXLA_13; /* NXLA_13 */
volatile uint32_t CRLA_13; /* CRLA_13 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_14; /* N0SA_14 */
volatile uint32_t N0DA_14; /* N0DA_14 */
volatile uint32_t N0TB_14; /* N0TB_14 */
volatile uint32_t N1SA_14; /* N1SA_14 */
volatile uint32_t N1DA_14; /* N1DA_14 */
volatile uint32_t N1TB_14; /* N1TB_14 */
volatile uint32_t CRSA_14; /* CRSA_14 */
volatile uint32_t CRDA_14; /* CRDA_14 */
volatile uint32_t CRTB_14; /* CRTB_14 */
volatile uint32_t CHSTAT_14; /* CHSTAT_14 */
volatile uint32_t CHCTRL_14; /* CHCTRL_14 */
volatile uint32_t CHCFG_14; /* CHCFG_14 */
volatile uint32_t CHITVL_14; /* CHITVL_14 */
volatile uint32_t CHEXT_14; /* CHEXT_14 */
volatile uint32_t NXLA_14; /* NXLA_14 */
volatile uint32_t CRLA_14; /* CRLA_14 */
/* end of struct st_dmac_n */
/* start of struct st_dmac_n */
volatile uint32_t N0SA_15; /* N0SA_15 */
volatile uint32_t N0DA_15; /* N0DA_15 */
volatile uint32_t N0TB_15; /* N0TB_15 */
volatile uint32_t N1SA_15; /* N1SA_15 */
volatile uint32_t N1DA_15; /* N1DA_15 */
volatile uint32_t N1TB_15; /* N1TB_15 */
volatile uint32_t CRSA_15; /* CRSA_15 */
volatile uint32_t CRDA_15; /* CRDA_15 */
volatile uint32_t CRTB_15; /* CRTB_15 */
volatile uint32_t CHSTAT_15; /* CHSTAT_15 */
volatile uint32_t CHCTRL_15; /* CHCTRL_15 */
volatile uint32_t CHCFG_15; /* CHCFG_15 */
volatile uint32_t CHITVL_15; /* CHITVL_15 */
volatile uint32_t CHEXT_15; /* CHEXT_15 */
volatile uint32_t NXLA_15; /* NXLA_15 */
volatile uint32_t CRLA_15; /* CRLA_15 */
/* end of struct st_dmac_n */
volatile uint8_t dummy190[256]; /* */
/* start of struct st_dmaccommon_n */
volatile uint32_t DCTRL_8_15; /* DCTRL_8_15 */
volatile uint8_t dummy191[12]; /* */
volatile uint32_t DSTAT_EN_8_15; /* DSTAT_EN_8_15 */
volatile uint32_t DSTAT_ER_8_15; /* DSTAT_ER_8_15 */
volatile uint32_t DSTAT_END_8_15; /* DSTAT_END_8_15 */
volatile uint32_t DSTAT_TC_8_15; /* DSTAT_TC_8_15 */
volatile uint32_t DSTAT_SUS_8_15; /* DSTAT_SUS_8_15 */
/* end of struct st_dmaccommon_n */
volatile uint8_t dummy192[350095580]; /* */
volatile uint32_t DMARS0; /* DMARS0 */
volatile uint32_t DMARS1; /* DMARS1 */
volatile uint32_t DMARS2; /* DMARS2 */
volatile uint32_t DMARS3; /* DMARS3 */
volatile uint32_t DMARS4; /* DMARS4 */
volatile uint32_t DMARS5; /* DMARS5 */
volatile uint32_t DMARS6; /* DMARS6 */
volatile uint32_t DMARS7; /* DMARS7 */
} r_io_dmac_t;
typedef struct st_dmaccommon_n
{
volatile uint32_t DCTRL_0_7; /* DCTRL_0_7 */
volatile uint8_t dummy1[12]; /* */
volatile uint32_t DSTAT_EN_0_7; /* DSTAT_EN_0_7 */
volatile uint32_t DSTAT_ER_0_7; /* DSTAT_ER_0_7 */
volatile uint32_t DSTAT_END_0_7; /* DSTAT_END_0_7 */
volatile uint32_t DSTAT_TC_0_7; /* DSTAT_TC_0_7 */
volatile uint32_t DSTAT_SUS_0_7; /* DSTAT_SUS_0_7 */
} r_io_dmaccommon_n_t;
typedef struct st_dmac_n
{
volatile uint32_t N0SA_n; /* N0SA_n */
volatile uint32_t N0DA_n; /* N0DA_n */
volatile uint32_t N0TB_n; /* N0TB_n */
volatile uint32_t N1SA_n; /* N1SA_n */
volatile uint32_t N1DA_n; /* N1DA_n */
volatile uint32_t N1TB_n; /* N1TB_n */
volatile uint32_t CRSA_n; /* CRSA_n */
volatile uint32_t CRDA_n; /* CRDA_n */
volatile uint32_t CRTB_n; /* CRTB_n */
volatile uint32_t CHSTAT_n; /* CHSTAT_n */
volatile uint32_t CHCTRL_n; /* CHCTRL_n */
volatile uint32_t CHCFG_n; /* CHCFG_n */
volatile uint32_t CHITVL_n; /* CHITVL_n */
volatile uint32_t CHEXT_n; /* CHEXT_n */
volatile uint32_t NXLA_n; /* NXLA_n */
volatile uint32_t CRLA_n; /* CRLA_n */
} r_io_dmac_n_t;
/* Channel array defines of DMAC (2)*/
#ifdef DECLARE_DMACmm_CHANNELS
volatile struct st_dmars_mm* DMACmm[ DMACmm_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DMACmm_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DMACmm_CHANNELS */
#ifdef DECLARE_DMACn_CHANNELS
volatile struct st_dmac_n* DMACn[ DMACn_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DMACn_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DMACn_CHANNELS */
#ifdef DECLARE_DMACnn_CHANNELS
volatile struct st_dmaccommon_n* DMACnn[ DMACnn_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DMACnn_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DMACnn_CHANNELS */
/* End of channel array defines of DMAC (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

441
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/dvdec_iodefine.h
View File

@ -1,441 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : dvdec_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef DVDEC_IODEFINE_H
#define DVDEC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define DVDEC1 (*(struct st_dvdec *)0xFCFFA008uL) /* DVDEC1 */
#define DVDEC0 (*(struct st_dvdec *)0xFCFFB808uL) /* DVDEC0 */
/* Start of channel array defines of DVDEC */
/* Channel array defines of DVDEC */
/*(Sample) value = DVDEC[ channel ]->ADCCR1; */
#define DVDEC_COUNT (2)
#define DVDEC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&DVDEC0, &DVDEC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of DVDEC */
#define ADCCR1_1 (DVDEC1.ADCCR1)
#define TGCR1_1 (DVDEC1.TGCR1)
#define TGCR2_1 (DVDEC1.TGCR2)
#define TGCR3_1 (DVDEC1.TGCR3)
#define SYNSCR1_1 (DVDEC1.SYNSCR1)
#define SYNSCR2_1 (DVDEC1.SYNSCR2)
#define SYNSCR3_1 (DVDEC1.SYNSCR3)
#define SYNSCR4_1 (DVDEC1.SYNSCR4)
#define SYNSCR5_1 (DVDEC1.SYNSCR5)
#define HAFCCR1_1 (DVDEC1.HAFCCR1)
#define HAFCCR2_1 (DVDEC1.HAFCCR2)
#define HAFCCR3_1 (DVDEC1.HAFCCR3)
#define VCDWCR1_1 (DVDEC1.VCDWCR1)
#define DCPCR1_1 (DVDEC1.DCPCR1)
#define DCPCR2_1 (DVDEC1.DCPCR2)
#define DCPCR3_1 (DVDEC1.DCPCR3)
#define DCPCR4_1 (DVDEC1.DCPCR4)
#define DCPCR5_1 (DVDEC1.DCPCR5)
#define DCPCR6_1 (DVDEC1.DCPCR6)
#define DCPCR7_1 (DVDEC1.DCPCR7)
#define DCPCR8_1 (DVDEC1.DCPCR8)
#define NSDCR_1 (DVDEC1.NSDCR)
#define BTLCR_1 (DVDEC1.BTLCR)
#define BTGPCR_1 (DVDEC1.BTGPCR)
#define ACCCR1_1 (DVDEC1.ACCCR1)
#define ACCCR2_1 (DVDEC1.ACCCR2)
#define ACCCR3_1 (DVDEC1.ACCCR3)
#define TINTCR_1 (DVDEC1.TINTCR)
#define YCDCR_1 (DVDEC1.YCDCR)
#define AGCCR1_1 (DVDEC1.AGCCR1)
#define AGCCR2_1 (DVDEC1.AGCCR2)
#define PKLIMITCR_1 (DVDEC1.PKLIMITCR)
#define RGORCR1_1 (DVDEC1.RGORCR1)
#define RGORCR2_1 (DVDEC1.RGORCR2)
#define RGORCR3_1 (DVDEC1.RGORCR3)
#define RGORCR4_1 (DVDEC1.RGORCR4)
#define RGORCR5_1 (DVDEC1.RGORCR5)
#define RGORCR6_1 (DVDEC1.RGORCR6)
#define RGORCR7_1 (DVDEC1.RGORCR7)
#define AFCPFCR_1 (DVDEC1.AFCPFCR)
#define RUPDCR_1 (DVDEC1.RUPDCR)
#define VSYNCSR_1 (DVDEC1.VSYNCSR)
#define HSYNCSR_1 (DVDEC1.HSYNCSR)
#define DCPSR1_1 (DVDEC1.DCPSR1)
#define DCPSR2_1 (DVDEC1.DCPSR2)
#define NSDSR_1 (DVDEC1.NSDSR)
#define CROMASR1_1 (DVDEC1.CROMASR1)
#define CROMASR2_1 (DVDEC1.CROMASR2)
#define SYNCSSR_1 (DVDEC1.SYNCSSR)
#define AGCCSR1_1 (DVDEC1.AGCCSR1)
#define AGCCSR2_1 (DVDEC1.AGCCSR2)
#define YCSCR3_1 (DVDEC1.YCSCR3)
#define YCSCR4_1 (DVDEC1.YCSCR4)
#define YCSCR5_1 (DVDEC1.YCSCR5)
#define YCSCR6_1 (DVDEC1.YCSCR6)
#define YCSCR7_1 (DVDEC1.YCSCR7)
#define YCSCR8_1 (DVDEC1.YCSCR8)
#define YCSCR9_1 (DVDEC1.YCSCR9)
#define YCSCR11_1 (DVDEC1.YCSCR11)
#define YCSCR12_1 (DVDEC1.YCSCR12)
#define DCPCR9_1 (DVDEC1.DCPCR9)
#define YCTWA_F0_1 (DVDEC1.YCTWA_F0)
#define YCTWA_F1_1 (DVDEC1.YCTWA_F1)
#define YCTWA_F2_1 (DVDEC1.YCTWA_F2)
#define YCTWA_F3_1 (DVDEC1.YCTWA_F3)
#define YCTWA_F4_1 (DVDEC1.YCTWA_F4)
#define YCTWA_F5_1 (DVDEC1.YCTWA_F5)
#define YCTWA_F6_1 (DVDEC1.YCTWA_F6)
#define YCTWA_F7_1 (DVDEC1.YCTWA_F7)
#define YCTWA_F8_1 (DVDEC1.YCTWA_F8)
#define YCTWB_F0_1 (DVDEC1.YCTWB_F0)
#define YCTWB_F1_1 (DVDEC1.YCTWB_F1)
#define YCTWB_F2_1 (DVDEC1.YCTWB_F2)
#define YCTWB_F3_1 (DVDEC1.YCTWB_F3)
#define YCTWB_F4_1 (DVDEC1.YCTWB_F4)
#define YCTWB_F5_1 (DVDEC1.YCTWB_F5)
#define YCTWB_F6_1 (DVDEC1.YCTWB_F6)
#define YCTWB_F7_1 (DVDEC1.YCTWB_F7)
#define YCTWB_F8_1 (DVDEC1.YCTWB_F8)
#define YCTNA_F0_1 (DVDEC1.YCTNA_F0)
#define YCTNA_F1_1 (DVDEC1.YCTNA_F1)
#define YCTNA_F2_1 (DVDEC1.YCTNA_F2)
#define YCTNA_F3_1 (DVDEC1.YCTNA_F3)
#define YCTNA_F4_1 (DVDEC1.YCTNA_F4)
#define YCTNA_F5_1 (DVDEC1.YCTNA_F5)
#define YCTNA_F6_1 (DVDEC1.YCTNA_F6)
#define YCTNA_F7_1 (DVDEC1.YCTNA_F7)
#define YCTNA_F8_1 (DVDEC1.YCTNA_F8)
#define YCTNB_F0_1 (DVDEC1.YCTNB_F0)
#define YCTNB_F1_1 (DVDEC1.YCTNB_F1)
#define YCTNB_F2_1 (DVDEC1.YCTNB_F2)
#define YCTNB_F3_1 (DVDEC1.YCTNB_F3)
#define YCTNB_F4_1 (DVDEC1.YCTNB_F4)
#define YCTNB_F5_1 (DVDEC1.YCTNB_F5)
#define YCTNB_F6_1 (DVDEC1.YCTNB_F6)
#define YCTNB_F7_1 (DVDEC1.YCTNB_F7)
#define YCTNB_F8_1 (DVDEC1.YCTNB_F8)
#define YGAINCR_1 (DVDEC1.YGAINCR)
#define CBGAINCR_1 (DVDEC1.CBGAINCR)
#define CRGAINCR_1 (DVDEC1.CRGAINCR)
#define PGA_UPDATE_1 (DVDEC1.PGA_UPDATE)
#define PGACR_1 (DVDEC1.PGACR)
#define ADCCR2_1 (DVDEC1.ADCCR2)
#define ADCCR1_0 (DVDEC0.ADCCR1)
#define TGCR1_0 (DVDEC0.TGCR1)
#define TGCR2_0 (DVDEC0.TGCR2)
#define TGCR3_0 (DVDEC0.TGCR3)
#define SYNSCR1_0 (DVDEC0.SYNSCR1)
#define SYNSCR2_0 (DVDEC0.SYNSCR2)
#define SYNSCR3_0 (DVDEC0.SYNSCR3)
#define SYNSCR4_0 (DVDEC0.SYNSCR4)
#define SYNSCR5_0 (DVDEC0.SYNSCR5)
#define HAFCCR1_0 (DVDEC0.HAFCCR1)
#define HAFCCR2_0 (DVDEC0.HAFCCR2)
#define HAFCCR3_0 (DVDEC0.HAFCCR3)
#define VCDWCR1_0 (DVDEC0.VCDWCR1)
#define DCPCR1_0 (DVDEC0.DCPCR1)
#define DCPCR2_0 (DVDEC0.DCPCR2)
#define DCPCR3_0 (DVDEC0.DCPCR3)
#define DCPCR4_0 (DVDEC0.DCPCR4)
#define DCPCR5_0 (DVDEC0.DCPCR5)
#define DCPCR6_0 (DVDEC0.DCPCR6)
#define DCPCR7_0 (DVDEC0.DCPCR7)
#define DCPCR8_0 (DVDEC0.DCPCR8)
#define NSDCR_0 (DVDEC0.NSDCR)
#define BTLCR_0 (DVDEC0.BTLCR)
#define BTGPCR_0 (DVDEC0.BTGPCR)
#define ACCCR1_0 (DVDEC0.ACCCR1)
#define ACCCR2_0 (DVDEC0.ACCCR2)
#define ACCCR3_0 (DVDEC0.ACCCR3)
#define TINTCR_0 (DVDEC0.TINTCR)
#define YCDCR_0 (DVDEC0.YCDCR)
#define AGCCR1_0 (DVDEC0.AGCCR1)
#define AGCCR2_0 (DVDEC0.AGCCR2)
#define PKLIMITCR_0 (DVDEC0.PKLIMITCR)
#define RGORCR1_0 (DVDEC0.RGORCR1)
#define RGORCR2_0 (DVDEC0.RGORCR2)
#define RGORCR3_0 (DVDEC0.RGORCR3)
#define RGORCR4_0 (DVDEC0.RGORCR4)
#define RGORCR5_0 (DVDEC0.RGORCR5)
#define RGORCR6_0 (DVDEC0.RGORCR6)
#define RGORCR7_0 (DVDEC0.RGORCR7)
#define AFCPFCR_0 (DVDEC0.AFCPFCR)
#define RUPDCR_0 (DVDEC0.RUPDCR)
#define VSYNCSR_0 (DVDEC0.VSYNCSR)
#define HSYNCSR_0 (DVDEC0.HSYNCSR)
#define DCPSR1_0 (DVDEC0.DCPSR1)
#define DCPSR2_0 (DVDEC0.DCPSR2)
#define NSDSR_0 (DVDEC0.NSDSR)
#define CROMASR1_0 (DVDEC0.CROMASR1)
#define CROMASR2_0 (DVDEC0.CROMASR2)
#define SYNCSSR_0 (DVDEC0.SYNCSSR)
#define AGCCSR1_0 (DVDEC0.AGCCSR1)
#define AGCCSR2_0 (DVDEC0.AGCCSR2)
#define YCSCR3_0 (DVDEC0.YCSCR3)
#define YCSCR4_0 (DVDEC0.YCSCR4)
#define YCSCR5_0 (DVDEC0.YCSCR5)
#define YCSCR6_0 (DVDEC0.YCSCR6)
#define YCSCR7_0 (DVDEC0.YCSCR7)
#define YCSCR8_0 (DVDEC0.YCSCR8)
#define YCSCR9_0 (DVDEC0.YCSCR9)
#define YCSCR11_0 (DVDEC0.YCSCR11)
#define YCSCR12_0 (DVDEC0.YCSCR12)
#define DCPCR9_0 (DVDEC0.DCPCR9)
#define YCTWA_F0_0 (DVDEC0.YCTWA_F0)
#define YCTWA_F1_0 (DVDEC0.YCTWA_F1)
#define YCTWA_F2_0 (DVDEC0.YCTWA_F2)
#define YCTWA_F3_0 (DVDEC0.YCTWA_F3)
#define YCTWA_F4_0 (DVDEC0.YCTWA_F4)
#define YCTWA_F5_0 (DVDEC0.YCTWA_F5)
#define YCTWA_F6_0 (DVDEC0.YCTWA_F6)
#define YCTWA_F7_0 (DVDEC0.YCTWA_F7)
#define YCTWA_F8_0 (DVDEC0.YCTWA_F8)
#define YCTWB_F0_0 (DVDEC0.YCTWB_F0)
#define YCTWB_F1_0 (DVDEC0.YCTWB_F1)
#define YCTWB_F2_0 (DVDEC0.YCTWB_F2)
#define YCTWB_F3_0 (DVDEC0.YCTWB_F3)
#define YCTWB_F4_0 (DVDEC0.YCTWB_F4)
#define YCTWB_F5_0 (DVDEC0.YCTWB_F5)
#define YCTWB_F6_0 (DVDEC0.YCTWB_F6)
#define YCTWB_F7_0 (DVDEC0.YCTWB_F7)
#define YCTWB_F8_0 (DVDEC0.YCTWB_F8)
#define YCTNA_F0_0 (DVDEC0.YCTNA_F0)
#define YCTNA_F1_0 (DVDEC0.YCTNA_F1)
#define YCTNA_F2_0 (DVDEC0.YCTNA_F2)
#define YCTNA_F3_0 (DVDEC0.YCTNA_F3)
#define YCTNA_F4_0 (DVDEC0.YCTNA_F4)
#define YCTNA_F5_0 (DVDEC0.YCTNA_F5)
#define YCTNA_F6_0 (DVDEC0.YCTNA_F6)
#define YCTNA_F7_0 (DVDEC0.YCTNA_F7)
#define YCTNA_F8_0 (DVDEC0.YCTNA_F8)
#define YCTNB_F0_0 (DVDEC0.YCTNB_F0)
#define YCTNB_F1_0 (DVDEC0.YCTNB_F1)
#define YCTNB_F2_0 (DVDEC0.YCTNB_F2)
#define YCTNB_F3_0 (DVDEC0.YCTNB_F3)
#define YCTNB_F4_0 (DVDEC0.YCTNB_F4)
#define YCTNB_F5_0 (DVDEC0.YCTNB_F5)
#define YCTNB_F6_0 (DVDEC0.YCTNB_F6)
#define YCTNB_F7_0 (DVDEC0.YCTNB_F7)
#define YCTNB_F8_0 (DVDEC0.YCTNB_F8)
#define YGAINCR_0 (DVDEC0.YGAINCR)
#define CBGAINCR_0 (DVDEC0.CBGAINCR)
#define CRGAINCR_0 (DVDEC0.CRGAINCR)
#define PGA_UPDATE_0 (DVDEC0.PGA_UPDATE)
#define PGACR_0 (DVDEC0.PGACR)
#define ADCCR2_0 (DVDEC0.ADCCR2)
#define DVDEC_TGCRn_COUNT (3)
#define DVDEC_SYNSCRn_COUNT (5)
#define DVDEC_HAFCCRn_COUNT (3)
#define DVDEC_DCPCRn_COUNT (8)
#define DVDEC_ACCCRn_COUNT (3)
#define DVDEC_AGCCRn_COUNT (2)
#define DVDEC_RGORCRn_COUNT (7)
#define DVDEC_DCPSRn_COUNT (2)
#define DVDEC_CROMASRn_COUNT (2)
#define DVDEC_AGCCSRn_COUNT (2)
#define DVDEC_YCSCRn_COUNT (7)
#define DVDEC_YCTWA_Fn_COUNT (9)
#define DVDEC_YCTWB_Fn_COUNT (9)
#define DVDEC_YCTNA_Fn_COUNT (9)
#define DVDEC_YCTNB_Fn_COUNT (9)
typedef struct st_dvdec
{
/* DVDEC */
volatile uint16_t ADCCR1; /* ADCCR1 */
volatile uint8_t dummy1[4]; /* */
/* #define DVDEC_TGCRn_COUNT (3) */
volatile uint16_t TGCR1; /* TGCR1 */
volatile uint16_t TGCR2; /* TGCR2 */
volatile uint16_t TGCR3; /* TGCR3 */
volatile uint8_t dummy2[6]; /* */
/* #define DVDEC_SYNSCRn_COUNT (5) */
volatile uint16_t SYNSCR1; /* SYNSCR1 */
volatile uint16_t SYNSCR2; /* SYNSCR2 */
volatile uint16_t SYNSCR3; /* SYNSCR3 */
volatile uint16_t SYNSCR4; /* SYNSCR4 */
volatile uint16_t SYNSCR5; /* SYNSCR5 */
/* #define DVDEC_HAFCCRn_COUNT (3) */
volatile uint16_t HAFCCR1; /* HAFCCR1 */
volatile uint16_t HAFCCR2; /* HAFCCR2 */
volatile uint16_t HAFCCR3; /* HAFCCR3 */
volatile uint16_t VCDWCR1; /* VCDWCR1 */
volatile uint8_t dummy3[4]; /* */
/* #define DVDEC_DCPCRn_COUNT (8) */
volatile uint16_t DCPCR1; /* DCPCR1 */
volatile uint16_t DCPCR2; /* DCPCR2 */
volatile uint16_t DCPCR3; /* DCPCR3 */
volatile uint16_t DCPCR4; /* DCPCR4 */
volatile uint16_t DCPCR5; /* DCPCR5 */
volatile uint16_t DCPCR6; /* DCPCR6 */
volatile uint16_t DCPCR7; /* DCPCR7 */
volatile uint16_t DCPCR8; /* DCPCR8 */
volatile uint16_t NSDCR; /* NSDCR */
volatile uint16_t BTLCR; /* BTLCR */
volatile uint16_t BTGPCR; /* BTGPCR */
/* #define DVDEC_ACCCRn_COUNT (3) */
volatile uint16_t ACCCR1; /* ACCCR1 */
volatile uint16_t ACCCR2; /* ACCCR2 */
volatile uint16_t ACCCR3; /* ACCCR3 */
volatile uint16_t TINTCR; /* TINTCR */
volatile uint16_t YCDCR; /* YCDCR */
/* #define DVDEC_AGCCRn_COUNT (2) */
volatile uint16_t AGCCR1; /* AGCCR1 */
volatile uint16_t AGCCR2; /* AGCCR2 */
volatile uint16_t PKLIMITCR; /* PKLIMITCR */
/* #define DVDEC_RGORCRn_COUNT (7) */
volatile uint16_t RGORCR1; /* RGORCR1 */
volatile uint16_t RGORCR2; /* RGORCR2 */
volatile uint16_t RGORCR3; /* RGORCR3 */
volatile uint16_t RGORCR4; /* RGORCR4 */
volatile uint16_t RGORCR5; /* RGORCR5 */
volatile uint16_t RGORCR6; /* RGORCR6 */
volatile uint16_t RGORCR7; /* RGORCR7 */
volatile uint8_t dummy4[24]; /* */
volatile uint16_t AFCPFCR; /* AFCPFCR */
volatile uint16_t RUPDCR; /* RUPDCR */
volatile uint16_t VSYNCSR; /* VSYNCSR */
volatile uint16_t HSYNCSR; /* HSYNCSR */
/* #define DVDEC_DCPSRn_COUNT (2) */
volatile uint16_t DCPSR1; /* DCPSR1 */
volatile uint16_t DCPSR2; /* DCPSR2 */
volatile uint8_t dummy5[4]; /* */
volatile uint16_t NSDSR; /* NSDSR */
/* #define DVDEC_CROMASRn_COUNT (2) */
volatile uint16_t CROMASR1; /* CROMASR1 */
volatile uint16_t CROMASR2; /* CROMASR2 */
volatile uint16_t SYNCSSR; /* SYNCSSR */
/* #define DVDEC_AGCCSRn_COUNT (2) */
volatile uint16_t AGCCSR1; /* AGCCSR1 */
volatile uint16_t AGCCSR2; /* AGCCSR2 */
volatile uint8_t dummy6[108]; /* */
/* #define DVDEC_YCSCRn_COUNT (7) */
volatile uint16_t YCSCR3; /* YCSCR3 */
volatile uint16_t YCSCR4; /* YCSCR4 */
volatile uint16_t YCSCR5; /* YCSCR5 */
volatile uint16_t YCSCR6; /* YCSCR6 */
volatile uint16_t YCSCR7; /* YCSCR7 */
volatile uint16_t YCSCR8; /* YCSCR8 */
volatile uint16_t YCSCR9; /* YCSCR9 */
volatile uint8_t dummy7[2]; /* */
volatile uint16_t YCSCR11; /* YCSCR11 */
volatile uint16_t YCSCR12; /* YCSCR12 */
volatile uint8_t dummy8[104]; /* */
volatile uint16_t DCPCR9; /* DCPCR9 */
volatile uint8_t dummy9[16]; /* */
/* #define DVDEC_YCTWA_Fn_COUNT (9) */
volatile uint16_t YCTWA_F0; /* YCTWA_F0 */
volatile uint16_t YCTWA_F1; /* YCTWA_F1 */
volatile uint16_t YCTWA_F2; /* YCTWA_F2 */
volatile uint16_t YCTWA_F3; /* YCTWA_F3 */
volatile uint16_t YCTWA_F4; /* YCTWA_F4 */
volatile uint16_t YCTWA_F5; /* YCTWA_F5 */
volatile uint16_t YCTWA_F6; /* YCTWA_F6 */
volatile uint16_t YCTWA_F7; /* YCTWA_F7 */
volatile uint16_t YCTWA_F8; /* YCTWA_F8 */
/* #define DVDEC_YCTWB_Fn_COUNT (9) */
volatile uint16_t YCTWB_F0; /* YCTWB_F0 */
volatile uint16_t YCTWB_F1; /* YCTWB_F1 */
volatile uint16_t YCTWB_F2; /* YCTWB_F2 */
volatile uint16_t YCTWB_F3; /* YCTWB_F3 */
volatile uint16_t YCTWB_F4; /* YCTWB_F4 */
volatile uint16_t YCTWB_F5; /* YCTWB_F5 */
volatile uint16_t YCTWB_F6; /* YCTWB_F6 */
volatile uint16_t YCTWB_F7; /* YCTWB_F7 */
volatile uint16_t YCTWB_F8; /* YCTWB_F8 */
/* #define DVDEC_YCTNA_Fn_COUNT (9) */
volatile uint16_t YCTNA_F0; /* YCTNA_F0 */
volatile uint16_t YCTNA_F1; /* YCTNA_F1 */
volatile uint16_t YCTNA_F2; /* YCTNA_F2 */
volatile uint16_t YCTNA_F3; /* YCTNA_F3 */
volatile uint16_t YCTNA_F4; /* YCTNA_F4 */
volatile uint16_t YCTNA_F5; /* YCTNA_F5 */
volatile uint16_t YCTNA_F6; /* YCTNA_F6 */
volatile uint16_t YCTNA_F7; /* YCTNA_F7 */
volatile uint16_t YCTNA_F8; /* YCTNA_F8 */
/* #define DVDEC_YCTNB_Fn_COUNT (9) */
volatile uint16_t YCTNB_F0; /* YCTNB_F0 */
volatile uint16_t YCTNB_F1; /* YCTNB_F1 */
volatile uint16_t YCTNB_F2; /* YCTNB_F2 */
volatile uint16_t YCTNB_F3; /* YCTNB_F3 */
volatile uint16_t YCTNB_F4; /* YCTNB_F4 */
volatile uint16_t YCTNB_F5; /* YCTNB_F5 */
volatile uint16_t YCTNB_F6; /* YCTNB_F6 */
volatile uint16_t YCTNB_F7; /* YCTNB_F7 */
volatile uint16_t YCTNB_F8; /* YCTNB_F8 */
volatile uint8_t dummy10[38]; /* */
volatile uint16_t YGAINCR; /* YGAINCR */
volatile uint16_t CBGAINCR; /* CBGAINCR */
volatile uint16_t CRGAINCR; /* CRGAINCR */
volatile uint8_t dummy11[122]; /* */
volatile uint16_t PGA_UPDATE; /* PGA_UPDATE */
volatile uint16_t PGACR; /* PGACR */
volatile uint16_t ADCCR2; /* ADCCR2 */
} r_io_dvdec_t;
/* Channel array defines of DVDEC (2)*/
#ifdef DECLARE_DVDEC_CHANNELS
volatile struct st_dvdec* DVDEC[ DVDEC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
DVDEC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_DVDEC_CHANNELS */
/* End of channel array defines of DVDEC (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

509
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/ether_iodefine.h
View File

@ -1,509 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ether_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef ETHER_IODEFINE_H
#define ETHER_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define ETHER (*(struct st_ether *)0xE8203000uL) /* ETHER */
/* Start of channel array defines of ETHER */
/* Channel array defines of ETHER_FROM_TSU_ADRH0_ARRAY */
/*(Sample) value = ETHER_FROM_TSU_ADRH0_ARRAY[ channel ]->TSU_ADRH0; */
#define ETHER_FROM_TSU_ADRH0_ARRAY_COUNT (32)
#define ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&ETHER_FROM_TSU_ADRH0, &ETHER_FROM_TSU_ADRH1, &ETHER_FROM_TSU_ADRH2, &ETHER_FROM_TSU_ADRH3, &ETHER_FROM_TSU_ADRH4, &ETHER_FROM_TSU_ADRH5, &ETHER_FROM_TSU_ADRH6, &ETHER_FROM_TSU_ADRH7, \
&ETHER_FROM_TSU_ADRH8, &ETHER_FROM_TSU_ADRH9, &ETHER_FROM_TSU_ADRH10, &ETHER_FROM_TSU_ADRH11, &ETHER_FROM_TSU_ADRH12, &ETHER_FROM_TSU_ADRH13, &ETHER_FROM_TSU_ADRH14, &ETHER_FROM_TSU_ADRH15, \
&ETHER_FROM_TSU_ADRH16, &ETHER_FROM_TSU_ADRH17, &ETHER_FROM_TSU_ADRH18, &ETHER_FROM_TSU_ADRH19, &ETHER_FROM_TSU_ADRH20, &ETHER_FROM_TSU_ADRH21, &ETHER_FROM_TSU_ADRH22, &ETHER_FROM_TSU_ADRH23, \
&ETHER_FROM_TSU_ADRH24, &ETHER_FROM_TSU_ADRH25, &ETHER_FROM_TSU_ADRH26, &ETHER_FROM_TSU_ADRH27, &ETHER_FROM_TSU_ADRH28, &ETHER_FROM_TSU_ADRH29, &ETHER_FROM_TSU_ADRH30, &ETHER_FROM_TSU_ADRH31 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define ETHER_FROM_TSU_ADRH0 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH0) /* ETHER_FROM_TSU_ADRH0 */
#define ETHER_FROM_TSU_ADRH1 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH1) /* ETHER_FROM_TSU_ADRH1 */
#define ETHER_FROM_TSU_ADRH2 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH2) /* ETHER_FROM_TSU_ADRH2 */
#define ETHER_FROM_TSU_ADRH3 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH3) /* ETHER_FROM_TSU_ADRH3 */
#define ETHER_FROM_TSU_ADRH4 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH4) /* ETHER_FROM_TSU_ADRH4 */
#define ETHER_FROM_TSU_ADRH5 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH5) /* ETHER_FROM_TSU_ADRH5 */
#define ETHER_FROM_TSU_ADRH6 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH6) /* ETHER_FROM_TSU_ADRH6 */
#define ETHER_FROM_TSU_ADRH7 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH7) /* ETHER_FROM_TSU_ADRH7 */
#define ETHER_FROM_TSU_ADRH8 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH8) /* ETHER_FROM_TSU_ADRH8 */
#define ETHER_FROM_TSU_ADRH9 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH9) /* ETHER_FROM_TSU_ADRH9 */
#define ETHER_FROM_TSU_ADRH10 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH10) /* ETHER_FROM_TSU_ADRH10 */
#define ETHER_FROM_TSU_ADRH11 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH11) /* ETHER_FROM_TSU_ADRH11 */
#define ETHER_FROM_TSU_ADRH12 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH12) /* ETHER_FROM_TSU_ADRH12 */
#define ETHER_FROM_TSU_ADRH13 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH13) /* ETHER_FROM_TSU_ADRH13 */
#define ETHER_FROM_TSU_ADRH14 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH14) /* ETHER_FROM_TSU_ADRH14 */
#define ETHER_FROM_TSU_ADRH15 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH15) /* ETHER_FROM_TSU_ADRH15 */
#define ETHER_FROM_TSU_ADRH16 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH16) /* ETHER_FROM_TSU_ADRH16 */
#define ETHER_FROM_TSU_ADRH17 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH17) /* ETHER_FROM_TSU_ADRH17 */
#define ETHER_FROM_TSU_ADRH18 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH18) /* ETHER_FROM_TSU_ADRH18 */
#define ETHER_FROM_TSU_ADRH19 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH19) /* ETHER_FROM_TSU_ADRH19 */
#define ETHER_FROM_TSU_ADRH20 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH20) /* ETHER_FROM_TSU_ADRH20 */
#define ETHER_FROM_TSU_ADRH21 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH21) /* ETHER_FROM_TSU_ADRH21 */
#define ETHER_FROM_TSU_ADRH22 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH22) /* ETHER_FROM_TSU_ADRH22 */
#define ETHER_FROM_TSU_ADRH23 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH23) /* ETHER_FROM_TSU_ADRH23 */
#define ETHER_FROM_TSU_ADRH24 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH24) /* ETHER_FROM_TSU_ADRH24 */
#define ETHER_FROM_TSU_ADRH25 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH25) /* ETHER_FROM_TSU_ADRH25 */
#define ETHER_FROM_TSU_ADRH26 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH26) /* ETHER_FROM_TSU_ADRH26 */
#define ETHER_FROM_TSU_ADRH27 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH27) /* ETHER_FROM_TSU_ADRH27 */
#define ETHER_FROM_TSU_ADRH28 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH28) /* ETHER_FROM_TSU_ADRH28 */
#define ETHER_FROM_TSU_ADRH29 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH29) /* ETHER_FROM_TSU_ADRH29 */
#define ETHER_FROM_TSU_ADRH30 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH30) /* ETHER_FROM_TSU_ADRH30 */
#define ETHER_FROM_TSU_ADRH31 (*(struct st_ether_from_tsu_adrh0 *)&ETHER.TSU_ADRH31) /* ETHER_FROM_TSU_ADRH31 */
/* End of channel array defines of ETHER */
#define ETHEREDSR0 (ETHER.EDSR0)
#define ETHERTDLAR0 (ETHER.TDLAR0)
#define ETHERTDFAR0 (ETHER.TDFAR0)
#define ETHERTDFXR0 (ETHER.TDFXR0)
#define ETHERTDFFR0 (ETHER.TDFFR0)
#define ETHERRDLAR0 (ETHER.RDLAR0)
#define ETHERRDFAR0 (ETHER.RDFAR0)
#define ETHERRDFXR0 (ETHER.RDFXR0)
#define ETHERRDFFR0 (ETHER.RDFFR0)
#define ETHEREDMR0 (ETHER.EDMR0)
#define ETHEREDTRR0 (ETHER.EDTRR0)
#define ETHEREDRRR0 (ETHER.EDRRR0)
#define ETHEREESR0 (ETHER.EESR0)
#define ETHEREESIPR0 (ETHER.EESIPR0)
#define ETHERTRSCER0 (ETHER.TRSCER0)
#define ETHERRMFCR0 (ETHER.RMFCR0)
#define ETHERTFTR0 (ETHER.TFTR0)
#define ETHERFDR0 (ETHER.FDR0)
#define ETHERRMCR0 (ETHER.RMCR0)
#define ETHERRPADIR0 (ETHER.RPADIR0)
#define ETHERFCFTR0 (ETHER.FCFTR0)
#define ETHERCSMR (ETHER.CSMR)
#define ETHERCSSBM (ETHER.CSSBM)
#define ETHERCSSMR (ETHER.CSSMR)
#define ETHERECMR0 (ETHER.ECMR0)
#define ETHERRFLR0 (ETHER.RFLR0)
#define ETHERECSR0 (ETHER.ECSR0)
#define ETHERECSIPR0 (ETHER.ECSIPR0)
#define ETHERPIR0 (ETHER.PIR0)
#define ETHERAPR0 (ETHER.APR0)
#define ETHERMPR0 (ETHER.MPR0)
#define ETHERPFTCR0 (ETHER.PFTCR0)
#define ETHERPFRCR0 (ETHER.PFRCR0)
#define ETHERTPAUSER0 (ETHER.TPAUSER0)
#define ETHERMAHR0 (ETHER.MAHR0)
#define ETHERMALR0 (ETHER.MALR0)
#define ETHERCEFCR0 (ETHER.CEFCR0)
#define ETHERFRECR0 (ETHER.FRECR0)
#define ETHERTSFRCR0 (ETHER.TSFRCR0)
#define ETHERTLFRCR0 (ETHER.TLFRCR0)
#define ETHERRFCR0 (ETHER.RFCR0)
#define ETHERMAFCR0 (ETHER.MAFCR0)
#define ETHERARSTR (ETHER.ARSTR)
#define ETHERTSU_CTRST (ETHER.TSU_CTRST)
#define ETHERTSU_VTAG0 (ETHER.TSU_VTAG0)
#define ETHERTSU_ADSBSY (ETHER.TSU_ADSBSY)
#define ETHERTSU_TEN (ETHER.TSU_TEN)
#define ETHERTXNLCR0 (ETHER.TXNLCR0)
#define ETHERTXALCR0 (ETHER.TXALCR0)
#define ETHERRXNLCR0 (ETHER.RXNLCR0)
#define ETHERRXALCR0 (ETHER.RXALCR0)
#define ETHERTSU_ADRH0 (ETHER.TSU_ADRH0)
#define ETHERTSU_ADRL0 (ETHER.TSU_ADRL0)
#define ETHERTSU_ADRH1 (ETHER.TSU_ADRH1)
#define ETHERTSU_ADRL1 (ETHER.TSU_ADRL1)
#define ETHERTSU_ADRH2 (ETHER.TSU_ADRH2)
#define ETHERTSU_ADRL2 (ETHER.TSU_ADRL2)
#define ETHERTSU_ADRH3 (ETHER.TSU_ADRH3)
#define ETHERTSU_ADRL3 (ETHER.TSU_ADRL3)
#define ETHERTSU_ADRH4 (ETHER.TSU_ADRH4)
#define ETHERTSU_ADRL4 (ETHER.TSU_ADRL4)
#define ETHERTSU_ADRH5 (ETHER.TSU_ADRH5)
#define ETHERTSU_ADRL5 (ETHER.TSU_ADRL5)
#define ETHERTSU_ADRH6 (ETHER.TSU_ADRH6)
#define ETHERTSU_ADRL6 (ETHER.TSU_ADRL6)
#define ETHERTSU_ADRH7 (ETHER.TSU_ADRH7)
#define ETHERTSU_ADRL7 (ETHER.TSU_ADRL7)
#define ETHERTSU_ADRH8 (ETHER.TSU_ADRH8)
#define ETHERTSU_ADRL8 (ETHER.TSU_ADRL8)
#define ETHERTSU_ADRH9 (ETHER.TSU_ADRH9)
#define ETHERTSU_ADRL9 (ETHER.TSU_ADRL9)
#define ETHERTSU_ADRH10 (ETHER.TSU_ADRH10)
#define ETHERTSU_ADRL10 (ETHER.TSU_ADRL10)
#define ETHERTSU_ADRH11 (ETHER.TSU_ADRH11)
#define ETHERTSU_ADRL11 (ETHER.TSU_ADRL11)
#define ETHERTSU_ADRH12 (ETHER.TSU_ADRH12)
#define ETHERTSU_ADRL12 (ETHER.TSU_ADRL12)
#define ETHERTSU_ADRH13 (ETHER.TSU_ADRH13)
#define ETHERTSU_ADRL13 (ETHER.TSU_ADRL13)
#define ETHERTSU_ADRH14 (ETHER.TSU_ADRH14)
#define ETHERTSU_ADRL14 (ETHER.TSU_ADRL14)
#define ETHERTSU_ADRH15 (ETHER.TSU_ADRH15)
#define ETHERTSU_ADRL15 (ETHER.TSU_ADRL15)
#define ETHERTSU_ADRH16 (ETHER.TSU_ADRH16)
#define ETHERTSU_ADRL16 (ETHER.TSU_ADRL16)
#define ETHERTSU_ADRH17 (ETHER.TSU_ADRH17)
#define ETHERTSU_ADRL17 (ETHER.TSU_ADRL17)
#define ETHERTSU_ADRH18 (ETHER.TSU_ADRH18)
#define ETHERTSU_ADRL18 (ETHER.TSU_ADRL18)
#define ETHERTSU_ADRH19 (ETHER.TSU_ADRH19)
#define ETHERTSU_ADRL19 (ETHER.TSU_ADRL19)
#define ETHERTSU_ADRH20 (ETHER.TSU_ADRH20)
#define ETHERTSU_ADRL20 (ETHER.TSU_ADRL20)
#define ETHERTSU_ADRH21 (ETHER.TSU_ADRH21)
#define ETHERTSU_ADRL21 (ETHER.TSU_ADRL21)
#define ETHERTSU_ADRH22 (ETHER.TSU_ADRH22)
#define ETHERTSU_ADRL22 (ETHER.TSU_ADRL22)
#define ETHERTSU_ADRH23 (ETHER.TSU_ADRH23)
#define ETHERTSU_ADRL23 (ETHER.TSU_ADRL23)
#define ETHERTSU_ADRH24 (ETHER.TSU_ADRH24)
#define ETHERTSU_ADRL24 (ETHER.TSU_ADRL24)
#define ETHERTSU_ADRH25 (ETHER.TSU_ADRH25)
#define ETHERTSU_ADRL25 (ETHER.TSU_ADRL25)
#define ETHERTSU_ADRH26 (ETHER.TSU_ADRH26)
#define ETHERTSU_ADRL26 (ETHER.TSU_ADRL26)
#define ETHERTSU_ADRH27 (ETHER.TSU_ADRH27)
#define ETHERTSU_ADRL27 (ETHER.TSU_ADRL27)
#define ETHERTSU_ADRH28 (ETHER.TSU_ADRH28)
#define ETHERTSU_ADRL28 (ETHER.TSU_ADRL28)
#define ETHERTSU_ADRH29 (ETHER.TSU_ADRH29)
#define ETHERTSU_ADRL29 (ETHER.TSU_ADRL29)
#define ETHERTSU_ADRH30 (ETHER.TSU_ADRH30)
#define ETHERTSU_ADRL30 (ETHER.TSU_ADRL30)
#define ETHERTSU_ADRH31 (ETHER.TSU_ADRH31)
#define ETHERTSU_ADRL31 (ETHER.TSU_ADRL31)
typedef struct st_ether
{
/* ETHER */
volatile uint32_t EDSR0; /* EDSR0 */
volatile uint8_t dummy207[12]; /* */
volatile uint32_t TDLAR0; /* TDLAR0 */
volatile uint32_t TDFAR0; /* TDFAR0 */
volatile uint32_t TDFXR0; /* TDFXR0 */
volatile uint32_t TDFFR0; /* TDFFR0 */
volatile uint8_t dummy208[16]; /* */
volatile uint32_t RDLAR0; /* RDLAR0 */
volatile uint32_t RDFAR0; /* RDFAR0 */
volatile uint32_t RDFXR0; /* RDFXR0 */
volatile uint32_t RDFFR0; /* RDFFR0 */
volatile uint8_t dummy209[960]; /* */
volatile uint32_t EDMR0; /* EDMR0 */
volatile uint8_t dummy210[4]; /* */
volatile uint32_t EDTRR0; /* EDTRR0 */
volatile uint8_t dummy211[4]; /* */
volatile uint32_t EDRRR0; /* EDRRR0 */
volatile uint8_t dummy212[20]; /* */
volatile uint32_t EESR0; /* EESR0 */
volatile uint8_t dummy213[4]; /* */
volatile uint32_t EESIPR0; /* EESIPR0 */
volatile uint8_t dummy214[4]; /* */
volatile uint32_t TRSCER0; /* TRSCER0 */
volatile uint8_t dummy215[4]; /* */
volatile uint32_t RMFCR0; /* RMFCR0 */
volatile uint8_t dummy216[4]; /* */
volatile uint32_t TFTR0; /* TFTR0 */
volatile uint8_t dummy217[4]; /* */
volatile uint32_t FDR0; /* FDR0 */
volatile uint8_t dummy218[4]; /* */
volatile uint32_t RMCR0; /* RMCR0 */
volatile uint8_t dummy219[4]; /* */
volatile uint32_t RPADIR0; /* RPADIR0 */
volatile uint8_t dummy220[4]; /* */
volatile uint32_t FCFTR0; /* FCFTR0 */
volatile uint8_t dummy221[120]; /* */
volatile uint32_t CSMR; /* CSMR */
volatile uint32_t CSSBM; /* CSSBM */
volatile uint32_t CSSMR; /* CSSMR */
volatile uint8_t dummy222[16]; /* */
volatile uint32_t ECMR0; /* ECMR0 */
volatile uint8_t dummy223[4]; /* */
volatile uint32_t RFLR0; /* RFLR0 */
volatile uint8_t dummy224[4]; /* */
volatile uint32_t ECSR0; /* ECSR0 */
volatile uint8_t dummy225[4]; /* */
volatile uint32_t ECSIPR0; /* ECSIPR0 */
volatile uint8_t dummy226[4]; /* */
volatile uint32_t PIR0; /* PIR0 */
volatile uint8_t dummy227[48]; /* */
volatile uint32_t APR0; /* APR0 */
volatile uint32_t MPR0; /* MPR0 */
volatile uint32_t PFTCR0; /* PFTCR0 */
volatile uint32_t PFRCR0; /* PFRCR0 */
volatile uint32_t TPAUSER0; /* TPAUSER0 */
volatile uint8_t dummy228[88]; /* */
volatile uint32_t MAHR0; /* MAHR0 */
volatile uint8_t dummy229[4]; /* */
volatile uint32_t MALR0; /* MALR0 */
volatile uint8_t dummy230[372]; /* */
volatile uint32_t CEFCR0; /* CEFCR0 */
volatile uint8_t dummy231[4]; /* */
volatile uint32_t FRECR0; /* FRECR0 */
volatile uint8_t dummy232[4]; /* */
volatile uint32_t TSFRCR0; /* TSFRCR0 */
volatile uint8_t dummy233[4]; /* */
volatile uint32_t TLFRCR0; /* TLFRCR0 */
volatile uint8_t dummy234[4]; /* */
volatile uint32_t RFCR0; /* RFCR0 */
volatile uint8_t dummy235[20]; /* */
volatile uint32_t MAFCR0; /* MAFCR0 */
volatile uint8_t dummy236[4228]; /* */
volatile uint32_t ARSTR; /* ARSTR */
volatile uint32_t TSU_CTRST; /* TSU_CTRST */
volatile uint8_t dummy237[80]; /* */
volatile uint32_t TSU_VTAG0; /* TSU_VTAG0 */
volatile uint8_t dummy238[4]; /* */
volatile uint32_t TSU_ADSBSY; /* TSU_ADSBSY */
volatile uint32_t TSU_TEN; /* TSU_TEN */
volatile uint8_t dummy239[24]; /* */
volatile uint32_t TXNLCR0; /* TXNLCR0 */
volatile uint32_t TXALCR0; /* TXALCR0 */
volatile uint32_t RXNLCR0; /* RXNLCR0 */
volatile uint32_t RXALCR0; /* RXALCR0 */
volatile uint8_t dummy240[112]; /* */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH1; /* TSU_ADRH1 */
volatile uint32_t TSU_ADRL1; /* TSU_ADRL1 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH2; /* TSU_ADRH2 */
volatile uint32_t TSU_ADRL2; /* TSU_ADRL2 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH3; /* TSU_ADRH3 */
volatile uint32_t TSU_ADRL3; /* TSU_ADRL3 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH4; /* TSU_ADRH4 */
volatile uint32_t TSU_ADRL4; /* TSU_ADRL4 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH5; /* TSU_ADRH5 */
volatile uint32_t TSU_ADRL5; /* TSU_ADRL5 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH6; /* TSU_ADRH6 */
volatile uint32_t TSU_ADRL6; /* TSU_ADRL6 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH7; /* TSU_ADRH7 */
volatile uint32_t TSU_ADRL7; /* TSU_ADRL7 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH8; /* TSU_ADRH8 */
volatile uint32_t TSU_ADRL8; /* TSU_ADRL8 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH9; /* TSU_ADRH9 */
volatile uint32_t TSU_ADRL9; /* TSU_ADRL9 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH10; /* TSU_ADRH10 */
volatile uint32_t TSU_ADRL10; /* TSU_ADRL10 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH11; /* TSU_ADRH11 */
volatile uint32_t TSU_ADRL11; /* TSU_ADRL11 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH12; /* TSU_ADRH12 */
volatile uint32_t TSU_ADRL12; /* TSU_ADRL12 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH13; /* TSU_ADRH13 */
volatile uint32_t TSU_ADRL13; /* TSU_ADRL13 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH14; /* TSU_ADRH14 */
volatile uint32_t TSU_ADRL14; /* TSU_ADRL14 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH15; /* TSU_ADRH15 */
volatile uint32_t TSU_ADRL15; /* TSU_ADRL15 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH16; /* TSU_ADRH16 */
volatile uint32_t TSU_ADRL16; /* TSU_ADRL16 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH17; /* TSU_ADRH17 */
volatile uint32_t TSU_ADRL17; /* TSU_ADRL17 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH18; /* TSU_ADRH18 */
volatile uint32_t TSU_ADRL18; /* TSU_ADRL18 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH19; /* TSU_ADRH19 */
volatile uint32_t TSU_ADRL19; /* TSU_ADRL19 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH20; /* TSU_ADRH20 */
volatile uint32_t TSU_ADRL20; /* TSU_ADRL20 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH21; /* TSU_ADRH21 */
volatile uint32_t TSU_ADRL21; /* TSU_ADRL21 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH22; /* TSU_ADRH22 */
volatile uint32_t TSU_ADRL22; /* TSU_ADRL22 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH23; /* TSU_ADRH23 */
volatile uint32_t TSU_ADRL23; /* TSU_ADRL23 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH24; /* TSU_ADRH24 */
volatile uint32_t TSU_ADRL24; /* TSU_ADRL24 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH25; /* TSU_ADRH25 */
volatile uint32_t TSU_ADRL25; /* TSU_ADRL25 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH26; /* TSU_ADRH26 */
volatile uint32_t TSU_ADRL26; /* TSU_ADRL26 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH27; /* TSU_ADRH27 */
volatile uint32_t TSU_ADRL27; /* TSU_ADRL27 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH28; /* TSU_ADRH28 */
volatile uint32_t TSU_ADRL28; /* TSU_ADRL28 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH29; /* TSU_ADRH29 */
volatile uint32_t TSU_ADRL29; /* TSU_ADRL29 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH30; /* TSU_ADRH30 */
volatile uint32_t TSU_ADRL30; /* TSU_ADRL30 */
/* end of struct st_ether_from_tsu_adrh0 */
/* start of struct st_ether_from_tsu_adrh0 */
volatile uint32_t TSU_ADRH31; /* TSU_ADRH31 */
volatile uint32_t TSU_ADRL31; /* TSU_ADRL31 */
/* end of struct st_ether_from_tsu_adrh0 */
} r_io_ether_t;
typedef struct st_ether_from_tsu_adrh0
{
volatile uint32_t TSU_ADRH0; /* TSU_ADRH0 */
volatile uint32_t TSU_ADRL0; /* TSU_ADRL0 */
} r_io_ether_from_tsu_adrh0_t;
/* Channel array defines of ETHER (2)*/
#ifdef DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS
volatile struct st_ether_from_tsu_adrh0* ETHER_FROM_TSU_ADRH0_ARRAY[ ETHER_FROM_TSU_ADRH0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
ETHER_FROM_TSU_ADRH0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_ETHER_FROM_TSU_ADRH0_ARRAY_CHANNELS */
/* End of channel array defines of ETHER (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,78 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : flctl_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef FLCTL_IODEFINE_H
#define FLCTL_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define FLCTL (*(struct st_flctl *)0xFCFF4000uL) /* FLCTL */
#define FLCTLFLCMNCR (FLCTL.FLCMNCR)
#define FLCTLFLCMDCR (FLCTL.FLCMDCR)
#define FLCTLFLCMCDR (FLCTL.FLCMCDR)
#define FLCTLFLADR (FLCTL.FLADR)
#define FLCTLFLDATAR (FLCTL.FLDATAR)
#define FLCTLFLDTCNTR (FLCTL.FLDTCNTR)
#define FLCTLFLINTDMACR (FLCTL.FLINTDMACR)
#define FLCTLFLBSYTMR (FLCTL.FLBSYTMR)
#define FLCTLFLBSYCNT (FLCTL.FLBSYCNT)
#define FLCTLFLTRCR (FLCTL.FLTRCR)
#define FLCTLFLADR2 (FLCTL.FLADR2)
#define FLCTLFLDTFIFO (FLCTL.FLDTFIFO)
typedef struct st_flctl
{
/* FLCTL */
volatile uint32_t FLCMNCR; /* FLCMNCR */
volatile uint32_t FLCMDCR; /* FLCMDCR */
volatile uint32_t FLCMCDR; /* FLCMCDR */
volatile uint32_t FLADR; /* FLADR */
volatile uint32_t FLDATAR; /* FLDATAR */
volatile uint32_t FLDTCNTR; /* FLDTCNTR */
volatile uint32_t FLINTDMACR; /* FLINTDMACR */
volatile uint32_t FLBSYTMR; /* FLBSYTMR */
volatile uint32_t FLBSYCNT; /* FLBSYCNT */
volatile uint8_t dummy555[8]; /* */
volatile uint8_t FLTRCR; /* FLTRCR */
volatile uint8_t dummy556[15]; /* */
volatile uint32_t FLADR2; /* FLADR2 */
volatile uint8_t dummy557[16]; /* */
volatile uint32_t FLDTFIFO; /* FLDTFIFO */
} r_io_flctl_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,128 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ieb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef IEB_IODEFINE_H
#define IEB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define IEB (*(struct st_ieb *)0xFCFEF000uL) /* IEB */
#define IEBB0BCR (IEB.B0BCR)
#define IEBB0PSR (IEB.B0PSR)
#define IEBB0UAR (IEB.B0UAR)
#define IEBB0SAR (IEB.B0SAR)
#define IEBB0PAR (IEB.B0PAR)
#define IEBB0RSA (IEB.B0RSA)
#define IEBB0CDR (IEB.B0CDR)
#define IEBB0TCD (IEB.B0TCD)
#define IEBB0RCD (IEB.B0RCD)
#define IEBB0DLR (IEB.B0DLR)
#define IEBB0TDL (IEB.B0TDL)
#define IEBB0RDL (IEB.B0RDL)
#define IEBB0CKS (IEB.B0CKS)
#define IEBB0TMS (IEB.B0TMS)
#define IEBB0PCR (IEB.B0PCR)
#define IEBB0BSR (IEB.B0BSR)
#define IEBB0SSR (IEB.B0SSR)
#define IEBB0USR (IEB.B0USR)
#define IEBB0ISR (IEB.B0ISR)
#define IEBB0ESR (IEB.B0ESR)
#define IEBB0FSR (IEB.B0FSR)
#define IEBB0SCR (IEB.B0SCR)
#define IEBB0CCR (IEB.B0CCR)
#define IEBB0STC0 (IEB.B0STC0)
#define IEBB0STC1 (IEB.B0STC1)
#define IEBB0DR (IEB.B0DR)
typedef struct st_ieb
{
/* IEB */
volatile uint8_t B0BCR; /* B0BCR */
volatile uint8_t dummy495[3]; /* */
volatile uint8_t B0PSR; /* B0PSR */
volatile uint8_t dummy496[3]; /* */
volatile uint16_t B0UAR; /* B0UAR */
volatile uint8_t dummy497[2]; /* */
volatile uint16_t B0SAR; /* B0SAR */
volatile uint8_t dummy498[2]; /* */
volatile uint16_t B0PAR; /* B0PAR */
volatile uint8_t dummy499[2]; /* */
volatile uint16_t B0RSA; /* B0RSA */
volatile uint8_t dummy500[2]; /* */
volatile uint8_t B0CDR; /* B0CDR */
volatile uint8_t dummy501[3]; /* */
volatile uint8_t B0TCD; /* B0TCD */
volatile uint8_t dummy502[3]; /* */
volatile uint8_t B0RCD; /* B0RCD */
volatile uint8_t dummy503[3]; /* */
volatile uint8_t B0DLR; /* B0DLR */
volatile uint8_t dummy504[3]; /* */
volatile uint8_t B0TDL; /* B0TDL */
volatile uint8_t dummy505[3]; /* */
volatile uint8_t B0RDL; /* B0RDL */
volatile uint8_t dummy506[3]; /* */
volatile uint8_t B0CKS; /* B0CKS */
volatile uint8_t dummy507[3]; /* */
volatile uint8_t B0TMS; /* B0TMS */
volatile uint8_t dummy508[3]; /* */
volatile uint8_t B0PCR; /* B0PCR */
volatile uint8_t dummy509[3]; /* */
volatile uint16_t B0BSR; /* B0BSR */
volatile uint8_t dummy510[2]; /* */
volatile uint8_t B0SSR; /* B0SSR */
volatile uint8_t dummy511[3]; /* */
volatile uint8_t B0USR; /* B0USR */
volatile uint8_t dummy512[3]; /* */
volatile uint8_t B0ISR; /* B0ISR */
volatile uint8_t dummy513[3]; /* */
volatile uint8_t B0ESR; /* B0ESR */
volatile uint8_t dummy514[3]; /* */
volatile uint8_t B0FSR; /* B0FSR */
volatile uint8_t dummy515[3]; /* */
volatile uint8_t B0SCR; /* B0SCR */
volatile uint8_t dummy516[3]; /* */
volatile uint8_t B0CCR; /* B0CCR */
volatile uint8_t dummy517[3]; /* */
volatile uint8_t B0STC0; /* B0STC0 */
volatile uint8_t dummy518[3]; /* */
volatile uint8_t B0STC1; /* B0STC1 */
volatile uint8_t dummy519[3]; /* */
volatile uint8_t B0DR; /* B0DR */
} r_io_ieb_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,112 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : inb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef INB_IODEFINE_H
#define INB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define INB (*(struct st_inb *)0xFCFE1A00uL) /* INB */
#define INBRMPR (INB.RMPR)
#define INBAXIBUSCTL0 (INB.AXIBUSCTL0)
#define INBAXIBUSCTL1 (INB.AXIBUSCTL1)
#define INBAXIBUSCTL2 (INB.AXIBUSCTL2)
#define INBAXIBUSCTL3 (INB.AXIBUSCTL3)
#define INBAXIBUSCTL4 (INB.AXIBUSCTL4)
#define INBAXIBUSCTL5 (INB.AXIBUSCTL5)
#define INBAXIBUSCTL6 (INB.AXIBUSCTL6)
#define INBAXIBUSCTL7 (INB.AXIBUSCTL7)
#define INBAXIBUSCTL8 (INB.AXIBUSCTL8)
#define INBAXIBUSCTL9 (INB.AXIBUSCTL9)
#define INBAXIBUSCTL10 (INB.AXIBUSCTL10)
#define INBAXIRERRCTL0 (INB.AXIRERRCTL0)
#define INBAXIRERRCTL1 (INB.AXIRERRCTL1)
#define INBAXIRERRCTL2 (INB.AXIRERRCTL2)
#define INBAXIRERRCTL3 (INB.AXIRERRCTL3)
#define INBAXIRERRST0 (INB.AXIRERRST0)
#define INBAXIRERRST1 (INB.AXIRERRST1)
#define INBAXIRERRST2 (INB.AXIRERRST2)
#define INBAXIRERRST3 (INB.AXIRERRST3)
#define INBAXIRERRCLR0 (INB.AXIRERRCLR0)
#define INBAXIRERRCLR1 (INB.AXIRERRCLR1)
#define INBAXIRERRCLR2 (INB.AXIRERRCLR2)
#define INBAXIRERRCLR3 (INB.AXIRERRCLR3)
#define INB_AXIBUSCTLn_COUNT (11)
#define INB_AXIRERRCTLn_COUNT (4)
#define INB_AXIRERRSTn_COUNT (4)
#define INB_AXIRERRCLRn_COUNT (4)
typedef struct st_inb
{
/* INB */
volatile uint32_t RMPR; /* RMPR */
/* #define INB_AXIBUSCTLn_COUNT (11) */
volatile uint32_t AXIBUSCTL0; /* AXIBUSCTL0 */
volatile uint32_t AXIBUSCTL1; /* AXIBUSCTL1 */
volatile uint32_t AXIBUSCTL2; /* AXIBUSCTL2 */
volatile uint32_t AXIBUSCTL3; /* AXIBUSCTL3 */
volatile uint32_t AXIBUSCTL4; /* AXIBUSCTL4 */
volatile uint32_t AXIBUSCTL5; /* AXIBUSCTL5 */
volatile uint32_t AXIBUSCTL6; /* AXIBUSCTL6 */
volatile uint32_t AXIBUSCTL7; /* AXIBUSCTL7 */
volatile uint32_t AXIBUSCTL8; /* AXIBUSCTL8 */
volatile uint32_t AXIBUSCTL9; /* AXIBUSCTL9 */
volatile uint32_t AXIBUSCTL10; /* AXIBUSCTL10 */
/* #define INB_AXIRERRCTLn_COUNT (4) */
volatile uint32_t AXIRERRCTL0; /* AXIRERRCTL0 */
volatile uint32_t AXIRERRCTL1; /* AXIRERRCTL1 */
volatile uint32_t AXIRERRCTL2; /* AXIRERRCTL2 */
volatile uint32_t AXIRERRCTL3; /* AXIRERRCTL3 */
/* #define INB_AXIRERRSTn_COUNT (4) */
volatile uint32_t AXIRERRST0; /* AXIRERRST0 */
volatile uint32_t AXIRERRST1; /* AXIRERRST1 */
volatile uint32_t AXIRERRST2; /* AXIRERRST2 */
volatile uint32_t AXIRERRST3; /* AXIRERRST3 */
/* #define INB_AXIRERRCLRn_COUNT (4) */
volatile uint32_t AXIRERRCLR0; /* AXIRERRCLR0 */
volatile uint32_t AXIRERRCLR1; /* AXIRERRCLR1 */
volatile uint32_t AXIRERRCLR2; /* AXIRERRCLR2 */
volatile uint32_t AXIRERRCLR3; /* AXIRERRCLR3 */
} r_io_inb_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,118 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : iodefine_typedef.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef IODEFINE_TYPEDEF_H
#define IODEFINE_TYPEDEF_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
/* Shared types and macros for iodefine.h */
/***********************************************************************
* Macro: IODEFINE_H_VERSION
************************************************************************/
#define IODEFINE_H_VERSION (200)
/***********************************************************************
* Enum: iodefine_byte_select_t
*
* R_IO_L - Low 16bit or Low 8 bit
* R_IO_H - High 16bit or Low 8 bit
* R_IO_LL - Low 8 bit
* R_IO_LH - Middle Low 8 bit
* R_IO_HL - Middle High 8 bit
* R_IO_HH - High 8 bit
************************************************************************/
typedef enum iodefine_byte_select_t
{
R_IO_L = 0, R_IO_H = 1,
R_IO_LL= 0, R_IO_LH = 1, R_IO_HL = 2, R_IO_HH = 3,
L = 0, H = 1,
LL= 0, LH = 1, HL = 2, HH = 3
} iodefine_byte_select_t;
/***********************************************************************
* Type: iodefine_reg32_t
* 32/16/8 bit access register
*
* - Padding : sizeof(iodefine_reg32_t) == 4
* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
* &UINT8[0]==0, &UINT8[1]==1, &UINT8[2]==2, &UINT8[3]==3
* - Endian : Independent (Same as CPU endian as register endian)
* - Bit-Order : Independent
************************************************************************/
typedef union iodefine_reg32_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
volatile uint8_t UINT8[4]; /* 8-bit Access */
} iodefine_reg32_t;
/***********************************************************************
* Type: iodefine_reg32_16_t
* 32/16 bit access register
*
* - Padding : sizeof(iodefine_reg32_16_t) == 4
* - Alignment(Offset) : &UINT32==0, &UINT16[0]==0, &UINT16[1]==2
* - Endian : Independent (Same as CPU endian as register endian)
* - Bit-Order : Independent
************************************************************************/
typedef union iodefine_reg32_16_t
{
volatile uint32_t UINT32; /* 32-bit Access */
volatile uint16_t UINT16[2]; /* 16-bit Access */
} iodefine_reg32_16_t;
/***********************************************************************
* Type: iodefine_reg16_8_t
* 16/8 bit access register
*
* - Padding : sizeof(iodefine_reg16_8_t) == 2
* - Alignment(Offset) : &UINT16==0, &UINT8[0]==0, &UINT8[1]==1
* - Endian : Independent (Same as CPU endian as register endian)
* - Bit-Order : Independent
************************************************************************/
typedef union iodefine_reg16_8_t
{
volatile uint16_t UINT16; /* 16-bit Access */
volatile uint8_t UINT8[2]; /* 8-bit Access */
} iodefine_reg16_8_t;
/* End of shared types and macros for iodefine.h */
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,53 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : irda_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef IRDA_IODEFINE_H
#define IRDA_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define IRDA (*(struct st_irda *)0xE8014000uL) /* IRDA */
#define IRDAIRCR (IRDA.IRCR)
typedef struct st_irda
{
/* IRDA */
volatile uint8_t IRCR; /* IRCR */
} r_io_irda_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,197 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : jcu_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef JCU_IODEFINE_H
#define JCU_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define JCU (*(struct st_jcu *)0xE8017000uL) /* JCU */
/* Start of channel array defines of JCU */
/* Channel array defines of JCU_JCQTBL0 */
/*(Sample) value = JCU_JCQTBL0[ channel ]->JCQTBL0; */
#define JCU_JCQTBL0_COUNT (4)
#define JCU_JCQTBL0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&JCU_FROM_JCQTBL0, &JCU_FROM_JCQTBL1, &JCU_FROM_JCQTBL2, &JCU_FROM_JCQTBL3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define JCU_FROM_JCQTBL0 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL0) /* JCU_FROM_JCQTBL0 */
#define JCU_FROM_JCQTBL1 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL1) /* JCU_FROM_JCQTBL1 */
#define JCU_FROM_JCQTBL2 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL2) /* JCU_FROM_JCQTBL2 */
#define JCU_FROM_JCQTBL3 (*(struct st_jcu_from_jcqtbl0 *)&JCU.JCQTBL3) /* JCU_FROM_JCQTBL3 */
/* End of channel array defines of JCU */
#define JCUJCMOD (JCU.JCMOD)
#define JCUJCCMD (JCU.JCCMD)
#define JCUJCQTN (JCU.JCQTN)
#define JCUJCHTN (JCU.JCHTN)
#define JCUJCDRIU (JCU.JCDRIU)
#define JCUJCDRID (JCU.JCDRID)
#define JCUJCVSZU (JCU.JCVSZU)
#define JCUJCVSZD (JCU.JCVSZD)
#define JCUJCHSZU (JCU.JCHSZU)
#define JCUJCHSZD (JCU.JCHSZD)
#define JCUJCDTCU (JCU.JCDTCU)
#define JCUJCDTCM (JCU.JCDTCM)
#define JCUJCDTCD (JCU.JCDTCD)
#define JCUJINTE0 (JCU.JINTE0)
#define JCUJINTS0 (JCU.JINTS0)
#define JCUJCDERR (JCU.JCDERR)
#define JCUJCRST (JCU.JCRST)
#define JCUJIFECNT (JCU.JIFECNT)
#define JCUJIFESA (JCU.JIFESA)
#define JCUJIFESOFST (JCU.JIFESOFST)
#define JCUJIFEDA (JCU.JIFEDA)
#define JCUJIFESLC (JCU.JIFESLC)
#define JCUJIFEDDC (JCU.JIFEDDC)
#define JCUJIFDCNT (JCU.JIFDCNT)
#define JCUJIFDSA (JCU.JIFDSA)
#define JCUJIFDDOFST (JCU.JIFDDOFST)
#define JCUJIFDDA (JCU.JIFDDA)
#define JCUJIFDSDC (JCU.JIFDSDC)
#define JCUJIFDDLC (JCU.JIFDDLC)
#define JCUJIFDADT (JCU.JIFDADT)
#define JCUJINTE1 (JCU.JINTE1)
#define JCUJINTS1 (JCU.JINTS1)
#define JCUJIFESVSZ (JCU.JIFESVSZ)
#define JCUJIFESHSZ (JCU.JIFESHSZ)
#define JCUJCQTBL0 (JCU.JCQTBL0)
#define JCUJCQTBL1 (JCU.JCQTBL1)
#define JCUJCQTBL2 (JCU.JCQTBL2)
#define JCUJCQTBL3 (JCU.JCQTBL3)
#define JCUJCHTBD0 (JCU.JCHTBD0)
#define JCUJCHTBA0 (JCU.JCHTBA0)
#define JCUJCHTBD1 (JCU.JCHTBD1)
#define JCUJCHTBA1 (JCU.JCHTBA1)
typedef struct st_jcu
{
/* JCU */
volatile uint8_t JCMOD; /* JCMOD */
volatile uint8_t JCCMD; /* JCCMD */
volatile uint8_t dummy145[1]; /* */
volatile uint8_t JCQTN; /* JCQTN */
volatile uint8_t JCHTN; /* JCHTN */
volatile uint8_t JCDRIU; /* JCDRIU */
volatile uint8_t JCDRID; /* JCDRID */
volatile uint8_t JCVSZU; /* JCVSZU */
volatile uint8_t JCVSZD; /* JCVSZD */
volatile uint8_t JCHSZU; /* JCHSZU */
volatile uint8_t JCHSZD; /* JCHSZD */
volatile uint8_t JCDTCU; /* JCDTCU */
volatile uint8_t JCDTCM; /* JCDTCM */
volatile uint8_t JCDTCD; /* JCDTCD */
volatile uint8_t JINTE0; /* JINTE0 */
volatile uint8_t JINTS0; /* JINTS0 */
volatile uint8_t JCDERR; /* JCDERR */
volatile uint8_t JCRST; /* JCRST */
volatile uint8_t dummy146[46]; /* */
volatile uint32_t JIFECNT; /* JIFECNT */
volatile uint32_t JIFESA; /* JIFESA */
volatile uint32_t JIFESOFST; /* JIFESOFST */
volatile uint32_t JIFEDA; /* JIFEDA */
volatile uint32_t JIFESLC; /* JIFESLC */
volatile uint32_t JIFEDDC; /* JIFEDDC */
volatile uint32_t JIFDCNT; /* JIFDCNT */
volatile uint32_t JIFDSA; /* JIFDSA */
volatile uint32_t JIFDDOFST; /* JIFDDOFST */
volatile uint32_t JIFDDA; /* JIFDDA */
volatile uint32_t JIFDSDC; /* JIFDSDC */
volatile uint32_t JIFDDLC; /* JIFDDLC */
volatile uint32_t JIFDADT; /* JIFDADT */
volatile uint8_t dummy147[24]; /* */
volatile uint32_t JINTE1; /* JINTE1 */
volatile uint32_t JINTS1; /* JINTS1 */
volatile uint32_t JIFESVSZ; /* JIFESVSZ */
volatile uint32_t JIFESHSZ; /* JIFESHSZ */
volatile uint8_t dummy148[100]; /* */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL0; /* JCQTBL0 */
volatile uint8_t dummy149[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL1; /* JCQTBL1 */
volatile uint8_t dummy150[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL2; /* JCQTBL2 */
volatile uint8_t dummy151[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
/* start of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCQTBL3; /* JCQTBL3 */
volatile uint8_t dummy152[63]; /* */
/* end of struct st_jcu_from_jcqtbl0 */
volatile uint8_t JCHTBD0; /* JCHTBD0 */
volatile uint8_t dummy153[31]; /* */
volatile uint8_t JCHTBA0; /* JCHTBA0 */
volatile uint8_t dummy154[223]; /* */
volatile uint8_t JCHTBD1; /* JCHTBD1 */
volatile uint8_t dummy155[31]; /* */
volatile uint8_t JCHTBA1; /* JCHTBA1 */
} r_io_jcu_t;
typedef struct st_jcu_from_jcqtbl0
{
volatile uint8_t JCQTBL0; /* JCQTBL0 */
volatile uint8_t dummy1[63]; /* */
} r_io_jcu_from_jcqtbl0_t;
/* Channel array defines of JCU (2)*/
#ifdef DECLARE_JCU_JCQTBL0_CHANNELS
volatile struct st_jcu_from_jcqtbl0* JCU_JCQTBL0[ JCU_JCQTBL0_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
JCU_JCQTBL0_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_JCU_JCQTBL0_CHANNELS */
/* End of channel array defines of JCU (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,231 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : l2c_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef L2C_IODEFINE_H
#define L2C_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define L2C (*(struct st_l2c *)0x3FFFF000uL) /* L2C */
/* Start of channel array defines of L2C */
/* Channel array defines of L2C_FROM_REG9_D_LOCKDOWN0_ARRAY */
/*(Sample) value = L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ channel ]->REG9_D_LOCKDOWN0; */
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT (8)
#define L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&L2C_FROM_REG9_D_LOCKDOWN0, &L2C_FROM_REG9_D_LOCKDOWN1, &L2C_FROM_REG9_D_LOCKDOWN2, &L2C_FROM_REG9_D_LOCKDOWN3, &L2C_FROM_REG9_D_LOCKDOWN4, &L2C_FROM_REG9_D_LOCKDOWN5, &L2C_FROM_REG9_D_LOCKDOWN6, &L2C_FROM_REG9_D_LOCKDOWN7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define L2C_FROM_REG9_D_LOCKDOWN0 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN0) /* L2C_FROM_REG9_D_LOCKDOWN0 */
#define L2C_FROM_REG9_D_LOCKDOWN1 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN1) /* L2C_FROM_REG9_D_LOCKDOWN1 */
#define L2C_FROM_REG9_D_LOCKDOWN2 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN2) /* L2C_FROM_REG9_D_LOCKDOWN2 */
#define L2C_FROM_REG9_D_LOCKDOWN3 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN3) /* L2C_FROM_REG9_D_LOCKDOWN3 */
#define L2C_FROM_REG9_D_LOCKDOWN4 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN4) /* L2C_FROM_REG9_D_LOCKDOWN4 */
#define L2C_FROM_REG9_D_LOCKDOWN5 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN5) /* L2C_FROM_REG9_D_LOCKDOWN5 */
#define L2C_FROM_REG9_D_LOCKDOWN6 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN6) /* L2C_FROM_REG9_D_LOCKDOWN6 */
#define L2C_FROM_REG9_D_LOCKDOWN7 (*(struct st_l2c_from_reg9_d_lockdown0 *)&L2C.REG9_D_LOCKDOWN7) /* L2C_FROM_REG9_D_LOCKDOWN7 */
/* End of channel array defines of L2C */
#define L2CREG0_CACHE_ID (L2C.REG0_CACHE_ID)
#define L2CREG0_CACHE_TYPE (L2C.REG0_CACHE_TYPE)
#define L2CREG1_CONTROL (L2C.REG1_CONTROL)
#define L2CREG1_AUX_CONTROL (L2C.REG1_AUX_CONTROL)
#define L2CREG1_TAG_RAM_CONTROL (L2C.REG1_TAG_RAM_CONTROL)
#define L2CREG1_DATA_RAM_CONTROL (L2C.REG1_DATA_RAM_CONTROL)
#define L2CREG2_EV_COUNTER_CTRL (L2C.REG2_EV_COUNTER_CTRL)
#define L2CREG2_EV_COUNTER1_CFG (L2C.REG2_EV_COUNTER1_CFG)
#define L2CREG2_EV_COUNTER0_CFG (L2C.REG2_EV_COUNTER0_CFG)
#define L2CREG2_EV_COUNTER1 (L2C.REG2_EV_COUNTER1)
#define L2CREG2_EV_COUNTER0 (L2C.REG2_EV_COUNTER0)
#define L2CREG2_INT_MASK (L2C.REG2_INT_MASK)
#define L2CREG2_INT_MASK_STATUS (L2C.REG2_INT_MASK_STATUS)
#define L2CREG2_INT_RAW_STATUS (L2C.REG2_INT_RAW_STATUS)
#define L2CREG2_INT_CLEAR (L2C.REG2_INT_CLEAR)
#define L2CREG7_CACHE_SYNC (L2C.REG7_CACHE_SYNC)
#define L2CREG7_INV_PA (L2C.REG7_INV_PA)
#define L2CREG7_INV_WAY (L2C.REG7_INV_WAY)
#define L2CREG7_CLEAN_PA (L2C.REG7_CLEAN_PA)
#define L2CREG7_CLEAN_INDEX (L2C.REG7_CLEAN_INDEX)
#define L2CREG7_CLEAN_WAY (L2C.REG7_CLEAN_WAY)
#define L2CREG7_CLEAN_INV_PA (L2C.REG7_CLEAN_INV_PA)
#define L2CREG7_CLEAN_INV_INDEX (L2C.REG7_CLEAN_INV_INDEX)
#define L2CREG7_CLEAN_INV_WAY (L2C.REG7_CLEAN_INV_WAY)
#define L2CREG9_D_LOCKDOWN0 (L2C.REG9_D_LOCKDOWN0)
#define L2CREG9_I_LOCKDOWN0 (L2C.REG9_I_LOCKDOWN0)
#define L2CREG9_D_LOCKDOWN1 (L2C.REG9_D_LOCKDOWN1)
#define L2CREG9_I_LOCKDOWN1 (L2C.REG9_I_LOCKDOWN1)
#define L2CREG9_D_LOCKDOWN2 (L2C.REG9_D_LOCKDOWN2)
#define L2CREG9_I_LOCKDOWN2 (L2C.REG9_I_LOCKDOWN2)
#define L2CREG9_D_LOCKDOWN3 (L2C.REG9_D_LOCKDOWN3)
#define L2CREG9_I_LOCKDOWN3 (L2C.REG9_I_LOCKDOWN3)
#define L2CREG9_D_LOCKDOWN4 (L2C.REG9_D_LOCKDOWN4)
#define L2CREG9_I_LOCKDOWN4 (L2C.REG9_I_LOCKDOWN4)
#define L2CREG9_D_LOCKDOWN5 (L2C.REG9_D_LOCKDOWN5)
#define L2CREG9_I_LOCKDOWN5 (L2C.REG9_I_LOCKDOWN5)
#define L2CREG9_D_LOCKDOWN6 (L2C.REG9_D_LOCKDOWN6)
#define L2CREG9_I_LOCKDOWN6 (L2C.REG9_I_LOCKDOWN6)
#define L2CREG9_D_LOCKDOWN7 (L2C.REG9_D_LOCKDOWN7)
#define L2CREG9_I_LOCKDOWN7 (L2C.REG9_I_LOCKDOWN7)
#define L2CREG9_LOCK_LINE_EN (L2C.REG9_LOCK_LINE_EN)
#define L2CREG9_UNLOCK_WAY (L2C.REG9_UNLOCK_WAY)
#define L2CREG12_ADDR_FILTERING_START (L2C.REG12_ADDR_FILTERING_START)
#define L2CREG12_ADDR_FILTERING_END (L2C.REG12_ADDR_FILTERING_END)
#define L2CREG15_DEBUG_CTRL (L2C.REG15_DEBUG_CTRL)
#define L2CREG15_PREFETCH_CTRL (L2C.REG15_PREFETCH_CTRL)
#define L2CREG15_POWER_CTRL (L2C.REG15_POWER_CTRL)
typedef struct st_l2c
{
/* L2C */
volatile uint32_t REG0_CACHE_ID; /* REG0_CACHE_ID */
volatile uint32_t REG0_CACHE_TYPE; /* REG0_CACHE_TYPE */
volatile uint8_t dummy8[248]; /* */
volatile uint32_t REG1_CONTROL; /* REG1_CONTROL */
volatile uint32_t REG1_AUX_CONTROL; /* REG1_AUX_CONTROL */
volatile uint32_t REG1_TAG_RAM_CONTROL; /* REG1_TAG_RAM_CONTROL */
volatile uint32_t REG1_DATA_RAM_CONTROL; /* REG1_DATA_RAM_CONTROL */
volatile uint8_t dummy9[240]; /* */
volatile uint32_t REG2_EV_COUNTER_CTRL; /* REG2_EV_COUNTER_CTRL */
volatile uint32_t REG2_EV_COUNTER1_CFG; /* REG2_EV_COUNTER1_CFG */
volatile uint32_t REG2_EV_COUNTER0_CFG; /* REG2_EV_COUNTER0_CFG */
volatile uint32_t REG2_EV_COUNTER1; /* REG2_EV_COUNTER1 */
volatile uint32_t REG2_EV_COUNTER0; /* REG2_EV_COUNTER0 */
volatile uint32_t REG2_INT_MASK; /* REG2_INT_MASK */
volatile uint32_t REG2_INT_MASK_STATUS; /* REG2_INT_MASK_STATUS */
volatile uint32_t REG2_INT_RAW_STATUS; /* REG2_INT_RAW_STATUS */
volatile uint32_t REG2_INT_CLEAR; /* REG2_INT_CLEAR */
volatile uint8_t dummy10[1292]; /* */
volatile uint32_t REG7_CACHE_SYNC; /* REG7_CACHE_SYNC */
volatile uint8_t dummy11[60]; /* */
volatile uint32_t REG7_INV_PA; /* REG7_INV_PA */
volatile uint8_t dummy12[8]; /* */
volatile uint32_t REG7_INV_WAY; /* REG7_INV_WAY */
volatile uint8_t dummy13[48]; /* */
volatile uint32_t REG7_CLEAN_PA; /* REG7_CLEAN_PA */
volatile uint8_t dummy14[4]; /* */
volatile uint32_t REG7_CLEAN_INDEX; /* REG7_CLEAN_INDEX */
volatile uint32_t REG7_CLEAN_WAY; /* REG7_CLEAN_WAY */
volatile uint8_t dummy15[48]; /* */
volatile uint32_t REG7_CLEAN_INV_PA; /* REG7_CLEAN_INV_PA */
volatile uint8_t dummy16[4]; /* */
volatile uint32_t REG7_CLEAN_INV_INDEX; /* REG7_CLEAN_INV_INDEX */
volatile uint32_t REG7_CLEAN_INV_WAY; /* REG7_CLEAN_INV_WAY */
volatile uint8_t dummy17[256]; /* */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN1; /* REG9_D_LOCKDOWN1 */
volatile uint32_t REG9_I_LOCKDOWN1; /* REG9_I_LOCKDOWN1 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN2; /* REG9_D_LOCKDOWN2 */
volatile uint32_t REG9_I_LOCKDOWN2; /* REG9_I_LOCKDOWN2 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN3; /* REG9_D_LOCKDOWN3 */
volatile uint32_t REG9_I_LOCKDOWN3; /* REG9_I_LOCKDOWN3 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN4; /* REG9_D_LOCKDOWN4 */
volatile uint32_t REG9_I_LOCKDOWN4; /* REG9_I_LOCKDOWN4 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN5; /* REG9_D_LOCKDOWN5 */
volatile uint32_t REG9_I_LOCKDOWN5; /* REG9_I_LOCKDOWN5 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN6; /* REG9_D_LOCKDOWN6 */
volatile uint32_t REG9_I_LOCKDOWN6; /* REG9_I_LOCKDOWN6 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
/* start of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint32_t REG9_D_LOCKDOWN7; /* REG9_D_LOCKDOWN7 */
volatile uint32_t REG9_I_LOCKDOWN7; /* REG9_I_LOCKDOWN7 */
/* end of struct st_l2c_from_reg9_d_lockdown0 */
volatile uint8_t dummy18[16]; /* */
volatile uint32_t REG9_LOCK_LINE_EN; /* REG9_LOCK_LINE_EN */
volatile uint32_t REG9_UNLOCK_WAY; /* REG9_UNLOCK_WAY */
volatile uint8_t dummy19[680]; /* */
volatile uint32_t REG12_ADDR_FILTERING_START; /* REG12_ADDR_FILTERING_START */
volatile uint32_t REG12_ADDR_FILTERING_END; /* REG12_ADDR_FILTERING_END */
volatile uint8_t dummy20[824]; /* */
volatile uint32_t REG15_DEBUG_CTRL; /* REG15_DEBUG_CTRL */
volatile uint8_t dummy21[28]; /* */
volatile uint32_t REG15_PREFETCH_CTRL; /* REG15_PREFETCH_CTRL */
volatile uint8_t dummy22[28]; /* */
volatile uint32_t REG15_POWER_CTRL; /* REG15_POWER_CTRL */
} r_io_l2c_t;
typedef struct st_l2c_from_reg9_d_lockdown0
{
volatile uint32_t REG9_D_LOCKDOWN0; /* REG9_D_LOCKDOWN0 */
volatile uint32_t REG9_I_LOCKDOWN0; /* REG9_I_LOCKDOWN0 */
} r_io_l2c_from_reg9_d_lockdown_t /* Short of r_io_l2c_from_reg9_d_lockdown0_t */;
/* Channel array defines of L2C (2)*/
#ifdef DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS
volatile struct st_l2c_from_reg9_d_lockdown0* L2C_FROM_REG9_D_LOCKDOWN0_ARRAY[ L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_L2C_FROM_REG9_D_LOCKDOWN0_ARRAY_CHANNELS */
/* End of channel array defines of L2C (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,161 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : lin_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef LIN_IODEFINE_H
#define LIN_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define LIN0 (*(struct st_lin *)0xFCFE9000uL) /* LIN0 */
#define LIN1 (*(struct st_lin *)0xFCFE9800uL) /* LIN1 */
/* Start of channel array defines of LIN */
/* Channel array defines of LIN */
/*(Sample) value = LIN[ channel ]->RLN3nLWBR; */
#define LIN_COUNT (2)
#define LIN_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&LIN0, &LIN1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of LIN */
#define LIN0RLN30LWBR (LIN0.RLN3nLWBR)
#define LIN0RLN30LBRP0 (LIN0.RLN3nLBRP0)
#define LIN0RLN30LBRP1 (LIN0.RLN3nLBRP1)
#define LIN0RLN30LSTC (LIN0.RLN3nLSTC)
#define LIN0RLN30LMD (LIN0.RLN3nLMD)
#define LIN0RLN30LBFC (LIN0.RLN3nLBFC)
#define LIN0RLN30LSC (LIN0.RLN3nLSC)
#define LIN0RLN30LWUP (LIN0.RLN3nLWUP)
#define LIN0RLN30LIE (LIN0.RLN3nLIE)
#define LIN0RLN30LEDE (LIN0.RLN3nLEDE)
#define LIN0RLN30LCUC (LIN0.RLN3nLCUC)
#define LIN0RLN30LTRC (LIN0.RLN3nLTRC)
#define LIN0RLN30LMST (LIN0.RLN3nLMST)
#define LIN0RLN30LST (LIN0.RLN3nLST)
#define LIN0RLN30LEST (LIN0.RLN3nLEST)
#define LIN0RLN30LDFC (LIN0.RLN3nLDFC)
#define LIN0RLN30LIDB (LIN0.RLN3nLIDB)
#define LIN0RLN30LCBR (LIN0.RLN3nLCBR)
#define LIN0RLN30LDBR1 (LIN0.RLN3nLDBR1)
#define LIN0RLN30LDBR2 (LIN0.RLN3nLDBR2)
#define LIN0RLN30LDBR3 (LIN0.RLN3nLDBR3)
#define LIN0RLN30LDBR4 (LIN0.RLN3nLDBR4)
#define LIN0RLN30LDBR5 (LIN0.RLN3nLDBR5)
#define LIN0RLN30LDBR6 (LIN0.RLN3nLDBR6)
#define LIN0RLN30LDBR7 (LIN0.RLN3nLDBR7)
#define LIN0RLN30LDBR8 (LIN0.RLN3nLDBR8)
#define LIN1RLN31LWBR (LIN1.RLN3nLWBR)
#define LIN1RLN31LBRP0 (LIN1.RLN3nLBRP0)
#define LIN1RLN31LBRP1 (LIN1.RLN3nLBRP1)
#define LIN1RLN31LSTC (LIN1.RLN3nLSTC)
#define LIN1RLN31LMD (LIN1.RLN3nLMD)
#define LIN1RLN31LBFC (LIN1.RLN3nLBFC)
#define LIN1RLN31LSC (LIN1.RLN3nLSC)
#define LIN1RLN31LWUP (LIN1.RLN3nLWUP)
#define LIN1RLN31LIE (LIN1.RLN3nLIE)
#define LIN1RLN31LEDE (LIN1.RLN3nLEDE)
#define LIN1RLN31LCUC (LIN1.RLN3nLCUC)
#define LIN1RLN31LTRC (LIN1.RLN3nLTRC)
#define LIN1RLN31LMST (LIN1.RLN3nLMST)
#define LIN1RLN31LST (LIN1.RLN3nLST)
#define LIN1RLN31LEST (LIN1.RLN3nLEST)
#define LIN1RLN31LDFC (LIN1.RLN3nLDFC)
#define LIN1RLN31LIDB (LIN1.RLN3nLIDB)
#define LIN1RLN31LCBR (LIN1.RLN3nLCBR)
#define LIN1RLN31LDBR1 (LIN1.RLN3nLDBR1)
#define LIN1RLN31LDBR2 (LIN1.RLN3nLDBR2)
#define LIN1RLN31LDBR3 (LIN1.RLN3nLDBR3)
#define LIN1RLN31LDBR4 (LIN1.RLN3nLDBR4)
#define LIN1RLN31LDBR5 (LIN1.RLN3nLDBR5)
#define LIN1RLN31LDBR6 (LIN1.RLN3nLDBR6)
#define LIN1RLN31LDBR7 (LIN1.RLN3nLDBR7)
#define LIN1RLN31LDBR8 (LIN1.RLN3nLDBR8)
#define LIN_LDBn_COUNT (8)
typedef struct st_lin
{
/* LIN */
volatile uint8_t dummy1[1]; /* */
volatile uint8_t RLN3nLWBR; /* RLN3nLWBR */
volatile uint8_t RLN3nLBRP0; /* RLN3nLBRP0 */
volatile uint8_t RLN3nLBRP1; /* RLN3nLBRP1 */
volatile uint8_t RLN3nLSTC; /* RLN3nLSTC */
volatile uint8_t dummy2[3]; /* */
volatile uint8_t RLN3nLMD; /* RLN3nLMD */
volatile uint8_t RLN3nLBFC; /* RLN3nLBFC */
volatile uint8_t RLN3nLSC; /* RLN3nLSC */
volatile uint8_t RLN3nLWUP; /* RLN3nLWUP */
volatile uint8_t RLN3nLIE; /* RLN3nLIE */
volatile uint8_t RLN3nLEDE; /* RLN3nLEDE */
volatile uint8_t RLN3nLCUC; /* RLN3nLCUC */
volatile uint8_t dummy3[1]; /* */
volatile uint8_t RLN3nLTRC; /* RLN3nLTRC */
volatile uint8_t RLN3nLMST; /* RLN3nLMST */
volatile uint8_t RLN3nLST; /* RLN3nLST */
volatile uint8_t RLN3nLEST; /* RLN3nLEST */
volatile uint8_t RLN3nLDFC; /* RLN3nLDFC */
volatile uint8_t RLN3nLIDB; /* RLN3nLIDB */
volatile uint8_t RLN3nLCBR; /* RLN3nLCBR */
volatile uint8_t dummy4[1]; /* */
/* #define LIN_LDBn_COUNT (8) */
volatile uint8_t RLN3nLDBR1; /* RLN3nLDBR1 */
volatile uint8_t RLN3nLDBR2; /* RLN3nLDBR2 */
volatile uint8_t RLN3nLDBR3; /* RLN3nLDBR3 */
volatile uint8_t RLN3nLDBR4; /* RLN3nLDBR4 */
volatile uint8_t RLN3nLDBR5; /* RLN3nLDBR5 */
volatile uint8_t RLN3nLDBR6; /* RLN3nLDBR6 */
volatile uint8_t RLN3nLDBR7; /* RLN3nLDBR7 */
volatile uint8_t RLN3nLDBR8; /* RLN3nLDBR8 */
} r_io_lin_t;
/* Channel array defines of LIN (2)*/
#ifdef DECLARE_LIN_CHANNELS
volatile struct st_lin* LIN[ LIN_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
LIN_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_LIN_CHANNELS */
/* End of channel array defines of LIN (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,63 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : lvds_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef LVDS_IODEFINE_H
#define LVDS_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define LVDS (*(struct st_lvds *)0xFCFF7A30uL) /* LVDS */
#define LVDSLVDS_UPDATE (LVDS.LVDS_UPDATE)
#define LVDSLVDSFCL (LVDS.LVDSFCL)
#define LVDSLCLKSELR (LVDS.LCLKSELR)
#define LVDSLPLLSETR (LVDS.LPLLSETR)
#define LVDSLPHYACC (LVDS.LPHYACC)
typedef struct st_lvds
{
/* LVDS */
volatile uint32_t LVDS_UPDATE; /* LVDS_UPDATE */
volatile uint32_t LVDSFCL; /* LVDSFCL */
volatile uint8_t dummy608[24]; /* */
volatile uint32_t LCLKSELR; /* LCLKSELR */
volatile uint32_t LPLLSETR; /* LPLLSETR */
volatile uint8_t dummy609[4]; /* */
volatile uint32_t LPHYACC; /* LPHYACC */
} r_io_lvds_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mlb_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef MLB_IODEFINE_H
#define MLB_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define MLB (*(struct st_mlb *)0xE8034000uL) /* MLB */
/* Start of channel array defines of MLB */
/* Channel array defines of MLB_FROM_CECR0_ARRAY */
/*(Sample) value = MLB_FROM_CECR0_ARRAY[ channel ]->CECR0; */
#define MLB_FROM_CECR0_ARRAY_COUNT (31)
#define MLB_FROM_CECR0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&MLB_FROM_CECR0, &MLB_FROM_CECR1, &MLB_FROM_CECR2, &MLB_FROM_CECR3, &MLB_FROM_CECR4, &MLB_FROM_CECR5, &MLB_FROM_CECR6, &MLB_FROM_CECR7, \
&MLB_FROM_CECR8, &MLB_FROM_CECR9, &MLB_FROM_CECR10, &MLB_FROM_CECR11, &MLB_FROM_CECR12, &MLB_FROM_CECR13, &MLB_FROM_CECR14, &MLB_FROM_CECR15, \
&MLB_FROM_CECR16, &MLB_FROM_CECR17, &MLB_FROM_CECR18, &MLB_FROM_CECR19, &MLB_FROM_CECR20, &MLB_FROM_CECR21, &MLB_FROM_CECR22, &MLB_FROM_CECR23, \
&MLB_FROM_CECR24, &MLB_FROM_CECR25, &MLB_FROM_CECR26, &MLB_FROM_CECR27, &MLB_FROM_CECR28, &MLB_FROM_CECR29, &MLB_FROM_CECR30 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define MLB_FROM_CECR0 (*(struct st_mlb_from_cecr0 *)&MLB.CECR0) /* MLB_FROM_CECR0 */
#define MLB_FROM_CECR1 (*(struct st_mlb_from_cecr0 *)&MLB.CECR1) /* MLB_FROM_CECR1 */
#define MLB_FROM_CECR2 (*(struct st_mlb_from_cecr0 *)&MLB.CECR2) /* MLB_FROM_CECR2 */
#define MLB_FROM_CECR3 (*(struct st_mlb_from_cecr0 *)&MLB.CECR3) /* MLB_FROM_CECR3 */
#define MLB_FROM_CECR4 (*(struct st_mlb_from_cecr0 *)&MLB.CECR4) /* MLB_FROM_CECR4 */
#define MLB_FROM_CECR5 (*(struct st_mlb_from_cecr0 *)&MLB.CECR5) /* MLB_FROM_CECR5 */
#define MLB_FROM_CECR6 (*(struct st_mlb_from_cecr0 *)&MLB.CECR6) /* MLB_FROM_CECR6 */
#define MLB_FROM_CECR7 (*(struct st_mlb_from_cecr0 *)&MLB.CECR7) /* MLB_FROM_CECR7 */
#define MLB_FROM_CECR8 (*(struct st_mlb_from_cecr0 *)&MLB.CECR8) /* MLB_FROM_CECR8 */
#define MLB_FROM_CECR9 (*(struct st_mlb_from_cecr0 *)&MLB.CECR9) /* MLB_FROM_CECR9 */
#define MLB_FROM_CECR10 (*(struct st_mlb_from_cecr0 *)&MLB.CECR10) /* MLB_FROM_CECR10 */
#define MLB_FROM_CECR11 (*(struct st_mlb_from_cecr0 *)&MLB.CECR11) /* MLB_FROM_CECR11 */
#define MLB_FROM_CECR12 (*(struct st_mlb_from_cecr0 *)&MLB.CECR12) /* MLB_FROM_CECR12 */
#define MLB_FROM_CECR13 (*(struct st_mlb_from_cecr0 *)&MLB.CECR13) /* MLB_FROM_CECR13 */
#define MLB_FROM_CECR14 (*(struct st_mlb_from_cecr0 *)&MLB.CECR14) /* MLB_FROM_CECR14 */
#define MLB_FROM_CECR15 (*(struct st_mlb_from_cecr0 *)&MLB.CECR15) /* MLB_FROM_CECR15 */
#define MLB_FROM_CECR16 (*(struct st_mlb_from_cecr0 *)&MLB.CECR16) /* MLB_FROM_CECR16 */
#define MLB_FROM_CECR17 (*(struct st_mlb_from_cecr0 *)&MLB.CECR17) /* MLB_FROM_CECR17 */
#define MLB_FROM_CECR18 (*(struct st_mlb_from_cecr0 *)&MLB.CECR18) /* MLB_FROM_CECR18 */
#define MLB_FROM_CECR19 (*(struct st_mlb_from_cecr0 *)&MLB.CECR19) /* MLB_FROM_CECR19 */
#define MLB_FROM_CECR20 (*(struct st_mlb_from_cecr0 *)&MLB.CECR20) /* MLB_FROM_CECR20 */
#define MLB_FROM_CECR21 (*(struct st_mlb_from_cecr0 *)&MLB.CECR21) /* MLB_FROM_CECR21 */
#define MLB_FROM_CECR22 (*(struct st_mlb_from_cecr0 *)&MLB.CECR22) /* MLB_FROM_CECR22 */
#define MLB_FROM_CECR23 (*(struct st_mlb_from_cecr0 *)&MLB.CECR23) /* MLB_FROM_CECR23 */
#define MLB_FROM_CECR24 (*(struct st_mlb_from_cecr0 *)&MLB.CECR24) /* MLB_FROM_CECR24 */
#define MLB_FROM_CECR25 (*(struct st_mlb_from_cecr0 *)&MLB.CECR25) /* MLB_FROM_CECR25 */
#define MLB_FROM_CECR26 (*(struct st_mlb_from_cecr0 *)&MLB.CECR26) /* MLB_FROM_CECR26 */
#define MLB_FROM_CECR27 (*(struct st_mlb_from_cecr0 *)&MLB.CECR27) /* MLB_FROM_CECR27 */
#define MLB_FROM_CECR28 (*(struct st_mlb_from_cecr0 *)&MLB.CECR28) /* MLB_FROM_CECR28 */
#define MLB_FROM_CECR29 (*(struct st_mlb_from_cecr0 *)&MLB.CECR29) /* MLB_FROM_CECR29 */
#define MLB_FROM_CECR30 (*(struct st_mlb_from_cecr0 *)&MLB.CECR30) /* MLB_FROM_CECR30 */
/* End of channel array defines of MLB */
#define MLBDCCR (MLB.DCCR)
#define MLBSSCR (MLB.SSCR)
#define MLBSDCR (MLB.SDCR)
#define MLBSMCR (MLB.SMCR)
#define MLBVCCR (MLB.VCCR)
#define MLBSBCR (MLB.SBCR)
#define MLBABCR (MLB.ABCR)
#define MLBCBCR (MLB.CBCR)
#define MLBIBCR (MLB.IBCR)
#define MLBCICR (MLB.CICR)
#define MLBCECR0 (MLB.CECR0)
#define MLBCSCR0 (MLB.CSCR0)
#define MLBCCBCR0 (MLB.CCBCR0)
#define MLBCNBCR0 (MLB.CNBCR0)
#define MLBCECR1 (MLB.CECR1)
#define MLBCSCR1 (MLB.CSCR1)
#define MLBCCBCR1 (MLB.CCBCR1)
#define MLBCNBCR1 (MLB.CNBCR1)
#define MLBCECR2 (MLB.CECR2)
#define MLBCSCR2 (MLB.CSCR2)
#define MLBCCBCR2 (MLB.CCBCR2)
#define MLBCNBCR2 (MLB.CNBCR2)
#define MLBCECR3 (MLB.CECR3)
#define MLBCSCR3 (MLB.CSCR3)
#define MLBCCBCR3 (MLB.CCBCR3)
#define MLBCNBCR3 (MLB.CNBCR3)
#define MLBCECR4 (MLB.CECR4)
#define MLBCSCR4 (MLB.CSCR4)
#define MLBCCBCR4 (MLB.CCBCR4)
#define MLBCNBCR4 (MLB.CNBCR4)
#define MLBCECR5 (MLB.CECR5)
#define MLBCSCR5 (MLB.CSCR5)
#define MLBCCBCR5 (MLB.CCBCR5)
#define MLBCNBCR5 (MLB.CNBCR5)
#define MLBCECR6 (MLB.CECR6)
#define MLBCSCR6 (MLB.CSCR6)
#define MLBCCBCR6 (MLB.CCBCR6)
#define MLBCNBCR6 (MLB.CNBCR6)
#define MLBCECR7 (MLB.CECR7)
#define MLBCSCR7 (MLB.CSCR7)
#define MLBCCBCR7 (MLB.CCBCR7)
#define MLBCNBCR7 (MLB.CNBCR7)
#define MLBCECR8 (MLB.CECR8)
#define MLBCSCR8 (MLB.CSCR8)
#define MLBCCBCR8 (MLB.CCBCR8)
#define MLBCNBCR8 (MLB.CNBCR8)
#define MLBCECR9 (MLB.CECR9)
#define MLBCSCR9 (MLB.CSCR9)
#define MLBCCBCR9 (MLB.CCBCR9)
#define MLBCNBCR9 (MLB.CNBCR9)
#define MLBCECR10 (MLB.CECR10)
#define MLBCSCR10 (MLB.CSCR10)
#define MLBCCBCR10 (MLB.CCBCR10)
#define MLBCNBCR10 (MLB.CNBCR10)
#define MLBCECR11 (MLB.CECR11)
#define MLBCSCR11 (MLB.CSCR11)
#define MLBCCBCR11 (MLB.CCBCR11)
#define MLBCNBCR11 (MLB.CNBCR11)
#define MLBCECR12 (MLB.CECR12)
#define MLBCSCR12 (MLB.CSCR12)
#define MLBCCBCR12 (MLB.CCBCR12)
#define MLBCNBCR12 (MLB.CNBCR12)
#define MLBCECR13 (MLB.CECR13)
#define MLBCSCR13 (MLB.CSCR13)
#define MLBCCBCR13 (MLB.CCBCR13)
#define MLBCNBCR13 (MLB.CNBCR13)
#define MLBCECR14 (MLB.CECR14)
#define MLBCSCR14 (MLB.CSCR14)
#define MLBCCBCR14 (MLB.CCBCR14)
#define MLBCNBCR14 (MLB.CNBCR14)
#define MLBCECR15 (MLB.CECR15)
#define MLBCSCR15 (MLB.CSCR15)
#define MLBCCBCR15 (MLB.CCBCR15)
#define MLBCNBCR15 (MLB.CNBCR15)
#define MLBCECR16 (MLB.CECR16)
#define MLBCSCR16 (MLB.CSCR16)
#define MLBCCBCR16 (MLB.CCBCR16)
#define MLBCNBCR16 (MLB.CNBCR16)
#define MLBCECR17 (MLB.CECR17)
#define MLBCSCR17 (MLB.CSCR17)
#define MLBCCBCR17 (MLB.CCBCR17)
#define MLBCNBCR17 (MLB.CNBCR17)
#define MLBCECR18 (MLB.CECR18)
#define MLBCSCR18 (MLB.CSCR18)
#define MLBCCBCR18 (MLB.CCBCR18)
#define MLBCNBCR18 (MLB.CNBCR18)
#define MLBCECR19 (MLB.CECR19)
#define MLBCSCR19 (MLB.CSCR19)
#define MLBCCBCR19 (MLB.CCBCR19)
#define MLBCNBCR19 (MLB.CNBCR19)
#define MLBCECR20 (MLB.CECR20)
#define MLBCSCR20 (MLB.CSCR20)
#define MLBCCBCR20 (MLB.CCBCR20)
#define MLBCNBCR20 (MLB.CNBCR20)
#define MLBCECR21 (MLB.CECR21)
#define MLBCSCR21 (MLB.CSCR21)
#define MLBCCBCR21 (MLB.CCBCR21)
#define MLBCNBCR21 (MLB.CNBCR21)
#define MLBCECR22 (MLB.CECR22)
#define MLBCSCR22 (MLB.CSCR22)
#define MLBCCBCR22 (MLB.CCBCR22)
#define MLBCNBCR22 (MLB.CNBCR22)
#define MLBCECR23 (MLB.CECR23)
#define MLBCSCR23 (MLB.CSCR23)
#define MLBCCBCR23 (MLB.CCBCR23)
#define MLBCNBCR23 (MLB.CNBCR23)
#define MLBCECR24 (MLB.CECR24)
#define MLBCSCR24 (MLB.CSCR24)
#define MLBCCBCR24 (MLB.CCBCR24)
#define MLBCNBCR24 (MLB.CNBCR24)
#define MLBCECR25 (MLB.CECR25)
#define MLBCSCR25 (MLB.CSCR25)
#define MLBCCBCR25 (MLB.CCBCR25)
#define MLBCNBCR25 (MLB.CNBCR25)
#define MLBCECR26 (MLB.CECR26)
#define MLBCSCR26 (MLB.CSCR26)
#define MLBCCBCR26 (MLB.CCBCR26)
#define MLBCNBCR26 (MLB.CNBCR26)
#define MLBCECR27 (MLB.CECR27)
#define MLBCSCR27 (MLB.CSCR27)
#define MLBCCBCR27 (MLB.CCBCR27)
#define MLBCNBCR27 (MLB.CNBCR27)
#define MLBCECR28 (MLB.CECR28)
#define MLBCSCR28 (MLB.CSCR28)
#define MLBCCBCR28 (MLB.CCBCR28)
#define MLBCNBCR28 (MLB.CNBCR28)
#define MLBCECR29 (MLB.CECR29)
#define MLBCSCR29 (MLB.CSCR29)
#define MLBCCBCR29 (MLB.CCBCR29)
#define MLBCNBCR29 (MLB.CNBCR29)
#define MLBCECR30 (MLB.CECR30)
#define MLBCSCR30 (MLB.CSCR30)
#define MLBCCBCR30 (MLB.CCBCR30)
#define MLBCNBCR30 (MLB.CNBCR30)
#define MLBLCBCR0 (MLB.LCBCR0)
#define MLBLCBCR1 (MLB.LCBCR1)
#define MLBLCBCR2 (MLB.LCBCR2)
#define MLBLCBCR3 (MLB.LCBCR3)
#define MLBLCBCR4 (MLB.LCBCR4)
#define MLBLCBCR5 (MLB.LCBCR5)
#define MLBLCBCR6 (MLB.LCBCR6)
#define MLBLCBCR7 (MLB.LCBCR7)
#define MLBLCBCR8 (MLB.LCBCR8)
#define MLBLCBCR9 (MLB.LCBCR9)
#define MLBLCBCR10 (MLB.LCBCR10)
#define MLBLCBCR11 (MLB.LCBCR11)
#define MLBLCBCR12 (MLB.LCBCR12)
#define MLBLCBCR13 (MLB.LCBCR13)
#define MLBLCBCR14 (MLB.LCBCR14)
#define MLBLCBCR15 (MLB.LCBCR15)
#define MLBLCBCR16 (MLB.LCBCR16)
#define MLBLCBCR17 (MLB.LCBCR17)
#define MLBLCBCR18 (MLB.LCBCR18)
#define MLBLCBCR19 (MLB.LCBCR19)
#define MLBLCBCR20 (MLB.LCBCR20)
#define MLBLCBCR21 (MLB.LCBCR21)
#define MLBLCBCR22 (MLB.LCBCR22)
#define MLBLCBCR23 (MLB.LCBCR23)
#define MLBLCBCR24 (MLB.LCBCR24)
#define MLBLCBCR25 (MLB.LCBCR25)
#define MLBLCBCR26 (MLB.LCBCR26)
#define MLBLCBCR27 (MLB.LCBCR27)
#define MLBLCBCR28 (MLB.LCBCR28)
#define MLBLCBCR29 (MLB.LCBCR29)
#define MLBLCBCR30 (MLB.LCBCR30)
#define MLB_LCBCR0_COUNT (31)
typedef struct st_mlb
{
/* MLB */
volatile uint32_t DCCR; /* DCCR */
volatile uint32_t SSCR; /* SSCR */
volatile uint32_t SDCR; /* SDCR */
volatile uint32_t SMCR; /* SMCR */
volatile uint8_t dummy156[12]; /* */
volatile uint32_t VCCR; /* VCCR */
volatile uint32_t SBCR; /* SBCR */
volatile uint32_t ABCR; /* ABCR */
volatile uint32_t CBCR; /* CBCR */
volatile uint32_t IBCR; /* IBCR */
volatile uint32_t CICR; /* CICR */
volatile uint8_t dummy157[12]; /* */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR1; /* CECR1 */
volatile uint32_t CSCR1; /* CSCR1 */
volatile uint32_t CCBCR1; /* CCBCR1 */
volatile uint32_t CNBCR1; /* CNBCR1 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR2; /* CECR2 */
volatile uint32_t CSCR2; /* CSCR2 */
volatile uint32_t CCBCR2; /* CCBCR2 */
volatile uint32_t CNBCR2; /* CNBCR2 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR3; /* CECR3 */
volatile uint32_t CSCR3; /* CSCR3 */
volatile uint32_t CCBCR3; /* CCBCR3 */
volatile uint32_t CNBCR3; /* CNBCR3 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR4; /* CECR4 */
volatile uint32_t CSCR4; /* CSCR4 */
volatile uint32_t CCBCR4; /* CCBCR4 */
volatile uint32_t CNBCR4; /* CNBCR4 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR5; /* CECR5 */
volatile uint32_t CSCR5; /* CSCR5 */
volatile uint32_t CCBCR5; /* CCBCR5 */
volatile uint32_t CNBCR5; /* CNBCR5 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR6; /* CECR6 */
volatile uint32_t CSCR6; /* CSCR6 */
volatile uint32_t CCBCR6; /* CCBCR6 */
volatile uint32_t CNBCR6; /* CNBCR6 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR7; /* CECR7 */
volatile uint32_t CSCR7; /* CSCR7 */
volatile uint32_t CCBCR7; /* CCBCR7 */
volatile uint32_t CNBCR7; /* CNBCR7 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR8; /* CECR8 */
volatile uint32_t CSCR8; /* CSCR8 */
volatile uint32_t CCBCR8; /* CCBCR8 */
volatile uint32_t CNBCR8; /* CNBCR8 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR9; /* CECR9 */
volatile uint32_t CSCR9; /* CSCR9 */
volatile uint32_t CCBCR9; /* CCBCR9 */
volatile uint32_t CNBCR9; /* CNBCR9 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR10; /* CECR10 */
volatile uint32_t CSCR10; /* CSCR10 */
volatile uint32_t CCBCR10; /* CCBCR10 */
volatile uint32_t CNBCR10; /* CNBCR10 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR11; /* CECR11 */
volatile uint32_t CSCR11; /* CSCR11 */
volatile uint32_t CCBCR11; /* CCBCR11 */
volatile uint32_t CNBCR11; /* CNBCR11 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR12; /* CECR12 */
volatile uint32_t CSCR12; /* CSCR12 */
volatile uint32_t CCBCR12; /* CCBCR12 */
volatile uint32_t CNBCR12; /* CNBCR12 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR13; /* CECR13 */
volatile uint32_t CSCR13; /* CSCR13 */
volatile uint32_t CCBCR13; /* CCBCR13 */
volatile uint32_t CNBCR13; /* CNBCR13 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR14; /* CECR14 */
volatile uint32_t CSCR14; /* CSCR14 */
volatile uint32_t CCBCR14; /* CCBCR14 */
volatile uint32_t CNBCR14; /* CNBCR14 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR15; /* CECR15 */
volatile uint32_t CSCR15; /* CSCR15 */
volatile uint32_t CCBCR15; /* CCBCR15 */
volatile uint32_t CNBCR15; /* CNBCR15 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR16; /* CECR16 */
volatile uint32_t CSCR16; /* CSCR16 */
volatile uint32_t CCBCR16; /* CCBCR16 */
volatile uint32_t CNBCR16; /* CNBCR16 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR17; /* CECR17 */
volatile uint32_t CSCR17; /* CSCR17 */
volatile uint32_t CCBCR17; /* CCBCR17 */
volatile uint32_t CNBCR17; /* CNBCR17 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR18; /* CECR18 */
volatile uint32_t CSCR18; /* CSCR18 */
volatile uint32_t CCBCR18; /* CCBCR18 */
volatile uint32_t CNBCR18; /* CNBCR18 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR19; /* CECR19 */
volatile uint32_t CSCR19; /* CSCR19 */
volatile uint32_t CCBCR19; /* CCBCR19 */
volatile uint32_t CNBCR19; /* CNBCR19 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR20; /* CECR20 */
volatile uint32_t CSCR20; /* CSCR20 */
volatile uint32_t CCBCR20; /* CCBCR20 */
volatile uint32_t CNBCR20; /* CNBCR20 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR21; /* CECR21 */
volatile uint32_t CSCR21; /* CSCR21 */
volatile uint32_t CCBCR21; /* CCBCR21 */
volatile uint32_t CNBCR21; /* CNBCR21 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR22; /* CECR22 */
volatile uint32_t CSCR22; /* CSCR22 */
volatile uint32_t CCBCR22; /* CCBCR22 */
volatile uint32_t CNBCR22; /* CNBCR22 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR23; /* CECR23 */
volatile uint32_t CSCR23; /* CSCR23 */
volatile uint32_t CCBCR23; /* CCBCR23 */
volatile uint32_t CNBCR23; /* CNBCR23 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR24; /* CECR24 */
volatile uint32_t CSCR24; /* CSCR24 */
volatile uint32_t CCBCR24; /* CCBCR24 */
volatile uint32_t CNBCR24; /* CNBCR24 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR25; /* CECR25 */
volatile uint32_t CSCR25; /* CSCR25 */
volatile uint32_t CCBCR25; /* CCBCR25 */
volatile uint32_t CNBCR25; /* CNBCR25 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR26; /* CECR26 */
volatile uint32_t CSCR26; /* CSCR26 */
volatile uint32_t CCBCR26; /* CCBCR26 */
volatile uint32_t CNBCR26; /* CNBCR26 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR27; /* CECR27 */
volatile uint32_t CSCR27; /* CSCR27 */
volatile uint32_t CCBCR27; /* CCBCR27 */
volatile uint32_t CNBCR27; /* CNBCR27 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR28; /* CECR28 */
volatile uint32_t CSCR28; /* CSCR28 */
volatile uint32_t CCBCR28; /* CCBCR28 */
volatile uint32_t CNBCR28; /* CNBCR28 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR29; /* CECR29 */
volatile uint32_t CSCR29; /* CSCR29 */
volatile uint32_t CCBCR29; /* CCBCR29 */
volatile uint32_t CNBCR29; /* CNBCR29 */
/* end of struct st_mlb_from_cecr0 */
/* start of struct st_mlb_from_cecr0 */
volatile uint32_t CECR30; /* CECR30 */
volatile uint32_t CSCR30; /* CSCR30 */
volatile uint32_t CCBCR30; /* CCBCR30 */
volatile uint32_t CNBCR30; /* CNBCR30 */
/* end of struct st_mlb_from_cecr0 */
volatile uint8_t dummy158[80]; /* */
/* #define MLB_LCBCR0_COUNT (31) */
volatile uint32_t LCBCR0; /* LCBCR0 */
volatile uint32_t LCBCR1; /* LCBCR1 */
volatile uint32_t LCBCR2; /* LCBCR2 */
volatile uint32_t LCBCR3; /* LCBCR3 */
volatile uint32_t LCBCR4; /* LCBCR4 */
volatile uint32_t LCBCR5; /* LCBCR5 */
volatile uint32_t LCBCR6; /* LCBCR6 */
volatile uint32_t LCBCR7; /* LCBCR7 */
volatile uint32_t LCBCR8; /* LCBCR8 */
volatile uint32_t LCBCR9; /* LCBCR9 */
volatile uint32_t LCBCR10; /* LCBCR10 */
volatile uint32_t LCBCR11; /* LCBCR11 */
volatile uint32_t LCBCR12; /* LCBCR12 */
volatile uint32_t LCBCR13; /* LCBCR13 */
volatile uint32_t LCBCR14; /* LCBCR14 */
volatile uint32_t LCBCR15; /* LCBCR15 */
volatile uint32_t LCBCR16; /* LCBCR16 */
volatile uint32_t LCBCR17; /* LCBCR17 */
volatile uint32_t LCBCR18; /* LCBCR18 */
volatile uint32_t LCBCR19; /* LCBCR19 */
volatile uint32_t LCBCR20; /* LCBCR20 */
volatile uint32_t LCBCR21; /* LCBCR21 */
volatile uint32_t LCBCR22; /* LCBCR22 */
volatile uint32_t LCBCR23; /* LCBCR23 */
volatile uint32_t LCBCR24; /* LCBCR24 */
volatile uint32_t LCBCR25; /* LCBCR25 */
volatile uint32_t LCBCR26; /* LCBCR26 */
volatile uint32_t LCBCR27; /* LCBCR27 */
volatile uint32_t LCBCR28; /* LCBCR28 */
volatile uint32_t LCBCR29; /* LCBCR29 */
volatile uint32_t LCBCR30; /* LCBCR30 */
} r_io_mlb_t;
typedef struct st_mlb_from_cecr0
{
volatile uint32_t CECR0; /* CECR0 */
volatile uint32_t CSCR0; /* CSCR0 */
volatile uint32_t CCBCR0; /* CCBCR0 */
volatile uint32_t CNBCR0; /* CNBCR0 */
} r_io_mlb_from_cecr0_t;
/* Channel array defines of MLB (2)*/
#ifdef DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS
volatile struct st_mlb_from_cecr0* MLB_FROM_CECR0_ARRAY[ MLB_FROM_CECR0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
MLB_FROM_CECR0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_MLB_FROM_CECR0_ARRAY_CHANNELS */
/* End of channel array defines of MLB (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,104 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mmc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef MMC_IODEFINE_H
#define MMC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define MMC (*(struct st_mmc *)0xE804C800uL) /* MMC */
#define MMCCE_CMD_SETH (MMC.CE_CMD_SETH)
#define MMCCE_CMD_SETL (MMC.CE_CMD_SETL)
#define MMCCE_ARG (MMC.CE_ARG)
#define MMCCE_ARG_CMD12 (MMC.CE_ARG_CMD12)
#define MMCCE_CMD_CTRL (MMC.CE_CMD_CTRL)
#define MMCCE_BLOCK_SET (MMC.CE_BLOCK_SET)
#define MMCCE_CLK_CTRL (MMC.CE_CLK_CTRL)
#define MMCCE_BUF_ACC (MMC.CE_BUF_ACC)
#define MMCCE_RESP3 (MMC.CE_RESP3)
#define MMCCE_RESP2 (MMC.CE_RESP2)
#define MMCCE_RESP1 (MMC.CE_RESP1)
#define MMCCE_RESP0 (MMC.CE_RESP0)
#define MMCCE_RESP_CMD12 (MMC.CE_RESP_CMD12)
#define MMCCE_DATA (MMC.CE_DATA)
#define MMCCE_INT (MMC.CE_INT)
#define MMCCE_INT_EN (MMC.CE_INT_EN)
#define MMCCE_HOST_STS1 (MMC.CE_HOST_STS1)
#define MMCCE_HOST_STS2 (MMC.CE_HOST_STS2)
#define MMCCE_DMA_MODE (MMC.CE_DMA_MODE)
#define MMCCE_DETECT (MMC.CE_DETECT)
#define MMCCE_ADD_MODE (MMC.CE_ADD_MODE)
#define MMCCE_VERSION (MMC.CE_VERSION)
#define MMC_CE_RESPn_COUNT (4)
typedef struct st_mmc
{
/* MMC */
volatile uint16_t CE_CMD_SETH; /* CE_CMD_SETH */
volatile uint16_t CE_CMD_SETL; /* CE_CMD_SETL */
volatile uint8_t dummy182[4]; /* */
volatile uint32_t CE_ARG; /* CE_ARG */
volatile uint32_t CE_ARG_CMD12; /* CE_ARG_CMD12 */
volatile uint32_t CE_CMD_CTRL; /* CE_CMD_CTRL */
volatile uint32_t CE_BLOCK_SET; /* CE_BLOCK_SET */
volatile uint32_t CE_CLK_CTRL; /* CE_CLK_CTRL */
volatile uint32_t CE_BUF_ACC; /* CE_BUF_ACC */
/* #define MMC_CE_RESPn_COUNT (4) */
volatile uint32_t CE_RESP3; /* CE_RESP3 */
volatile uint32_t CE_RESP2; /* CE_RESP2 */
volatile uint32_t CE_RESP1; /* CE_RESP1 */
volatile uint32_t CE_RESP0; /* CE_RESP0 */
volatile uint32_t CE_RESP_CMD12; /* CE_RESP_CMD12 */
volatile uint32_t CE_DATA; /* CE_DATA */
volatile uint8_t dummy183[8]; /* */
volatile uint32_t CE_INT; /* CE_INT */
volatile uint32_t CE_INT_EN; /* CE_INT_EN */
volatile uint32_t CE_HOST_STS1; /* CE_HOST_STS1 */
volatile uint32_t CE_HOST_STS2; /* CE_HOST_STS2 */
volatile uint8_t dummy184[12]; /* */
volatile uint32_t CE_DMA_MODE; /* CE_DMA_MODE */
volatile uint8_t dummy185[16]; /* */
volatile uint32_t CE_DETECT; /* CE_DETECT */
volatile uint32_t CE_ADD_MODE; /* CE_ADD_MODE */
volatile uint8_t dummy186[4]; /* */
volatile uint32_t CE_VERSION; /* CE_VERSION */
} r_io_mmc_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

226
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@ -1,226 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : mtu2_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef MTU2_IODEFINE_H
#define MTU2_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define MTU2 (*(struct st_mtu2 *)0xFCFF0000uL) /* MTU2 */
#define MTU2TCR_2 (MTU2.TCR_2)
#define MTU2TMDR_2 (MTU2.TMDR_2)
#define MTU2TIOR_2 (MTU2.TIOR_2)
#define MTU2TIER_2 (MTU2.TIER_2)
#define MTU2TSR_2 (MTU2.TSR_2)
#define MTU2TCNT_2 (MTU2.TCNT_2)
#define MTU2TGRA_2 (MTU2.TGRA_2)
#define MTU2TGRB_2 (MTU2.TGRB_2)
#define MTU2TCR_3 (MTU2.TCR_3)
#define MTU2TCR_4 (MTU2.TCR_4)
#define MTU2TMDR_3 (MTU2.TMDR_3)
#define MTU2TMDR_4 (MTU2.TMDR_4)
#define MTU2TIORH_3 (MTU2.TIORH_3)
#define MTU2TIORL_3 (MTU2.TIORL_3)
#define MTU2TIORH_4 (MTU2.TIORH_4)
#define MTU2TIORL_4 (MTU2.TIORL_4)
#define MTU2TIER_3 (MTU2.TIER_3)
#define MTU2TIER_4 (MTU2.TIER_4)
#define MTU2TOER (MTU2.TOER)
#define MTU2TGCR (MTU2.TGCR)
#define MTU2TOCR1 (MTU2.TOCR1)
#define MTU2TOCR2 (MTU2.TOCR2)
#define MTU2TCNT_3 (MTU2.TCNT_3)
#define MTU2TCNT_4 (MTU2.TCNT_4)
#define MTU2TCDR (MTU2.TCDR)
#define MTU2TDDR (MTU2.TDDR)
#define MTU2TGRA_3 (MTU2.TGRA_3)
#define MTU2TGRB_3 (MTU2.TGRB_3)
#define MTU2TGRA_4 (MTU2.TGRA_4)
#define MTU2TGRB_4 (MTU2.TGRB_4)
#define MTU2TCNTS (MTU2.TCNTS)
#define MTU2TCBR (MTU2.TCBR)
#define MTU2TGRC_3 (MTU2.TGRC_3)
#define MTU2TGRD_3 (MTU2.TGRD_3)
#define MTU2TGRC_4 (MTU2.TGRC_4)
#define MTU2TGRD_4 (MTU2.TGRD_4)
#define MTU2TSR_3 (MTU2.TSR_3)
#define MTU2TSR_4 (MTU2.TSR_4)
#define MTU2TITCR (MTU2.TITCR)
#define MTU2TITCNT (MTU2.TITCNT)
#define MTU2TBTER (MTU2.TBTER)
#define MTU2TDER (MTU2.TDER)
#define MTU2TOLBR (MTU2.TOLBR)
#define MTU2TBTM_3 (MTU2.TBTM_3)
#define MTU2TBTM_4 (MTU2.TBTM_4)
#define MTU2TADCR (MTU2.TADCR)
#define MTU2TADCORA_4 (MTU2.TADCORA_4)
#define MTU2TADCORB_4 (MTU2.TADCORB_4)
#define MTU2TADCOBRA_4 (MTU2.TADCOBRA_4)
#define MTU2TADCOBRB_4 (MTU2.TADCOBRB_4)
#define MTU2TWCR (MTU2.TWCR)
#define MTU2TSTR (MTU2.TSTR)
#define MTU2TSYR (MTU2.TSYR)
#define MTU2TRWER (MTU2.TRWER)
#define MTU2TCR_0 (MTU2.TCR_0)
#define MTU2TMDR_0 (MTU2.TMDR_0)
#define MTU2TIORH_0 (MTU2.TIORH_0)
#define MTU2TIORL_0 (MTU2.TIORL_0)
#define MTU2TIER_0 (MTU2.TIER_0)
#define MTU2TSR_0 (MTU2.TSR_0)
#define MTU2TCNT_0 (MTU2.TCNT_0)
#define MTU2TGRA_0 (MTU2.TGRA_0)
#define MTU2TGRB_0 (MTU2.TGRB_0)
#define MTU2TGRC_0 (MTU2.TGRC_0)
#define MTU2TGRD_0 (MTU2.TGRD_0)
#define MTU2TGRE_0 (MTU2.TGRE_0)
#define MTU2TGRF_0 (MTU2.TGRF_0)
#define MTU2TIER2_0 (MTU2.TIER2_0)
#define MTU2TSR2_0 (MTU2.TSR2_0)
#define MTU2TBTM_0 (MTU2.TBTM_0)
#define MTU2TCR_1 (MTU2.TCR_1)
#define MTU2TMDR_1 (MTU2.TMDR_1)
#define MTU2TIOR_1 (MTU2.TIOR_1)
#define MTU2TIER_1 (MTU2.TIER_1)
#define MTU2TSR_1 (MTU2.TSR_1)
#define MTU2TCNT_1 (MTU2.TCNT_1)
#define MTU2TGRA_1 (MTU2.TGRA_1)
#define MTU2TGRB_1 (MTU2.TGRB_1)
#define MTU2TICCR (MTU2.TICCR)
typedef struct st_mtu2
{
/* MTU2 */
volatile uint8_t TCR_2; /* TCR_2 */
volatile uint8_t TMDR_2; /* TMDR_2 */
volatile uint8_t TIOR_2; /* TIOR_2 */
volatile uint8_t dummy520[1]; /* */
volatile uint8_t TIER_2; /* TIER_2 */
volatile uint8_t TSR_2; /* TSR_2 */
volatile uint16_t TCNT_2; /* TCNT_2 */
volatile uint16_t TGRA_2; /* TGRA_2 */
volatile uint16_t TGRB_2; /* TGRB_2 */
volatile uint8_t dummy521[500]; /* */
volatile uint8_t TCR_3; /* TCR_3 */
volatile uint8_t TCR_4; /* TCR_4 */
volatile uint8_t TMDR_3; /* TMDR_3 */
volatile uint8_t TMDR_4; /* TMDR_4 */
volatile uint8_t TIORH_3; /* TIORH_3 */
volatile uint8_t TIORL_3; /* TIORL_3 */
volatile uint8_t TIORH_4; /* TIORH_4 */
volatile uint8_t TIORL_4; /* TIORL_4 */
volatile uint8_t TIER_3; /* TIER_3 */
volatile uint8_t TIER_4; /* TIER_4 */
volatile uint8_t TOER; /* TOER */
volatile uint8_t dummy522[2]; /* */
volatile uint8_t TGCR; /* TGCR */
volatile uint8_t TOCR1; /* TOCR1 */
volatile uint8_t TOCR2; /* TOCR2 */
volatile uint16_t TCNT_3; /* TCNT_3 */
volatile uint16_t TCNT_4; /* TCNT_4 */
volatile uint16_t TCDR; /* TCDR */
volatile uint16_t TDDR; /* TDDR */
volatile uint16_t TGRA_3; /* TGRA_3 */
volatile uint16_t TGRB_3; /* TGRB_3 */
volatile uint16_t TGRA_4; /* TGRA_4 */
volatile uint16_t TGRB_4; /* TGRB_4 */
volatile uint16_t TCNTS; /* TCNTS */
volatile uint16_t TCBR; /* TCBR */
volatile uint16_t TGRC_3; /* TGRC_3 */
volatile uint16_t TGRD_3; /* TGRD_3 */
volatile uint16_t TGRC_4; /* TGRC_4 */
volatile uint16_t TGRD_4; /* TGRD_4 */
volatile uint8_t TSR_3; /* TSR_3 */
volatile uint8_t TSR_4; /* TSR_4 */
volatile uint8_t dummy523[2]; /* */
volatile uint8_t TITCR; /* TITCR */
volatile uint8_t TITCNT; /* TITCNT */
volatile uint8_t TBTER; /* TBTER */
volatile uint8_t dummy524[1]; /* */
volatile uint8_t TDER; /* TDER */
volatile uint8_t dummy525[1]; /* */
volatile uint8_t TOLBR; /* TOLBR */
volatile uint8_t dummy526[1]; /* */
volatile uint8_t TBTM_3; /* TBTM_3 */
volatile uint8_t TBTM_4; /* TBTM_4 */
volatile uint8_t dummy527[6]; /* */
volatile uint16_t TADCR; /* TADCR */
volatile uint8_t dummy528[2]; /* */
volatile uint16_t TADCORA_4; /* TADCORA_4 */
volatile uint16_t TADCORB_4; /* TADCORB_4 */
volatile uint16_t TADCOBRA_4; /* TADCOBRA_4 */
volatile uint16_t TADCOBRB_4; /* TADCOBRB_4 */
volatile uint8_t dummy529[20]; /* */
volatile uint8_t TWCR; /* TWCR */
volatile uint8_t dummy530[31]; /* */
volatile uint8_t TSTR; /* TSTR */
volatile uint8_t TSYR; /* TSYR */
volatile uint8_t dummy531[2]; /* */
volatile uint8_t TRWER; /* TRWER */
volatile uint8_t dummy532[123]; /* */
volatile uint8_t TCR_0; /* TCR_0 */
volatile uint8_t TMDR_0; /* TMDR_0 */
volatile uint8_t TIORH_0; /* TIORH_0 */
volatile uint8_t TIORL_0; /* TIORL_0 */
volatile uint8_t TIER_0; /* TIER_0 */
volatile uint8_t TSR_0; /* TSR_0 */
volatile uint16_t TCNT_0; /* TCNT_0 */
volatile uint16_t TGRA_0; /* TGRA_0 */
volatile uint16_t TGRB_0; /* TGRB_0 */
volatile uint16_t TGRC_0; /* TGRC_0 */
volatile uint16_t TGRD_0; /* TGRD_0 */
volatile uint8_t dummy533[16]; /* */
volatile uint16_t TGRE_0; /* TGRE_0 */
volatile uint16_t TGRF_0; /* TGRF_0 */
volatile uint8_t TIER2_0; /* TIER2_0 */
volatile uint8_t TSR2_0; /* TSR2_0 */
volatile uint8_t TBTM_0; /* TBTM_0 */
volatile uint8_t dummy534[89]; /* */
volatile uint8_t TCR_1; /* TCR_1 */
volatile uint8_t TMDR_1; /* TMDR_1 */
volatile uint8_t TIOR_1; /* TIOR_1 */
volatile uint8_t dummy535[1]; /* */
volatile uint8_t TIER_1; /* TIER_1 */
volatile uint8_t TSR_1; /* TSR_1 */
volatile uint16_t TCNT_1; /* TCNT_1 */
volatile uint16_t TGRA_1; /* TGRA_1 */
volatile uint16_t TGRB_1; /* TGRB_1 */
volatile uint8_t dummy536[4]; /* */
volatile uint8_t TICCR; /* TICCR */
} r_io_mtu2_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ostm_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef OSTM_IODEFINE_H
#define OSTM_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define OSTM0 (*(struct st_ostm *)0xFCFEC000uL) /* OSTM0 */
#define OSTM1 (*(struct st_ostm *)0xFCFEC400uL) /* OSTM1 */
/* Start of channel array defines of OSTM */
/* Channel array defines of OSTM */
/*(Sample) value = OSTM[ channel ]->OSTMnCMP; */
#define OSTM_COUNT (2)
#define OSTM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&OSTM0, &OSTM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of OSTM */
#define OSTM0CMP (OSTM0.OSTMnCMP)
#define OSTM0CNT (OSTM0.OSTMnCNT)
#define OSTM0TE (OSTM0.OSTMnTE)
#define OSTM0TS (OSTM0.OSTMnTS)
#define OSTM0TT (OSTM0.OSTMnTT)
#define OSTM0CTL (OSTM0.OSTMnCTL)
#define OSTM1CMP (OSTM1.OSTMnCMP)
#define OSTM1CNT (OSTM1.OSTMnCNT)
#define OSTM1TE (OSTM1.OSTMnTE)
#define OSTM1TS (OSTM1.OSTMnTS)
#define OSTM1TT (OSTM1.OSTMnTT)
#define OSTM1CTL (OSTM1.OSTMnCTL)
typedef struct st_ostm
{
/* OSTM */
volatile uint32_t OSTMnCMP; /* OSTMnCMP */
volatile uint32_t OSTMnCNT; /* OSTMnCNT */
volatile uint8_t dummy1[8]; /* */
volatile uint8_t OSTMnTE; /* OSTMnTE */
volatile uint8_t dummy2[3]; /* */
volatile uint8_t OSTMnTS; /* OSTMnTS */
volatile uint8_t dummy3[3]; /* */
volatile uint8_t OSTMnTT; /* OSTMnTT */
volatile uint8_t dummy4[7]; /* */
volatile uint8_t OSTMnCTL; /* OSTMnCTL */
} r_io_ostm_t;
/* Channel array defines of OSTM (2)*/
#ifdef DECLARE_OSTM_CHANNELS
volatile struct st_ostm* OSTM[ OSTM_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
OSTM_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_OSTM_CHANNELS */
/* End of channel array defines of OSTM (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : pfv_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef PFV_IODEFINE_H
#define PFV_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define PFV0 (*(struct st_pfv *)0xE8205000uL) /* PFV0 */
#define PFV1 (*(struct st_pfv *)0xE8205800uL) /* PFV1 */
/* Start of channel array defines of PFV */
/* Channel array defines of PFV */
/*(Sample) value = PFV[ channel ]->PFVCR; */
#define PFV_COUNT (2)
#define PFV_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PFV0, &PFV1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of PFV */
#define PFV0PFVCR (PFV0.PFVCR)
#define PFV0PFVICR (PFV0.PFVICR)
#define PFV0PFVISR (PFV0.PFVISR)
#define PFV0PFVID0 (PFV0.PFVID0)
#define PFV0PFVID1 (PFV0.PFVID1)
#define PFV0PFVID2 (PFV0.PFVID2)
#define PFV0PFVID3 (PFV0.PFVID3)
#define PFV0PFVID4 (PFV0.PFVID4)
#define PFV0PFVID5 (PFV0.PFVID5)
#define PFV0PFVID6 (PFV0.PFVID6)
#define PFV0PFVID7 (PFV0.PFVID7)
#define PFV0PFVOD0 (PFV0.PFVOD0)
#define PFV0PFVOD1 (PFV0.PFVOD1)
#define PFV0PFVOD2 (PFV0.PFVOD2)
#define PFV0PFVOD3 (PFV0.PFVOD3)
#define PFV0PFVOD4 (PFV0.PFVOD4)
#define PFV0PFVOD5 (PFV0.PFVOD5)
#define PFV0PFVOD6 (PFV0.PFVOD6)
#define PFV0PFVOD7 (PFV0.PFVOD7)
#define PFV0PFVIFSR (PFV0.PFVIFSR)
#define PFV0PFVOFSR (PFV0.PFVOFSR)
#define PFV0PFVACR (PFV0.PFVACR)
#define PFV0PFV_MTX_MODE (PFV0.PFV_MTX_MODE)
#define PFV0PFV_MTX_YG_ADJ0 (PFV0.PFV_MTX_YG_ADJ0)
#define PFV0PFV_MTX_YG_ADJ1 (PFV0.PFV_MTX_YG_ADJ1)
#define PFV0PFV_MTX_CBB_ADJ0 (PFV0.PFV_MTX_CBB_ADJ0)
#define PFV0PFV_MTX_CBB_ADJ1 (PFV0.PFV_MTX_CBB_ADJ1)
#define PFV0PFV_MTX_CRR_ADJ0 (PFV0.PFV_MTX_CRR_ADJ0)
#define PFV0PFV_MTX_CRR_ADJ1 (PFV0.PFV_MTX_CRR_ADJ1)
#define PFV0PFVSZR (PFV0.PFVSZR)
#define PFV1PFVCR (PFV1.PFVCR)
#define PFV1PFVICR (PFV1.PFVICR)
#define PFV1PFVISR (PFV1.PFVISR)
#define PFV1PFVID0 (PFV1.PFVID0)
#define PFV1PFVID1 (PFV1.PFVID1)
#define PFV1PFVID2 (PFV1.PFVID2)
#define PFV1PFVID3 (PFV1.PFVID3)
#define PFV1PFVID4 (PFV1.PFVID4)
#define PFV1PFVID5 (PFV1.PFVID5)
#define PFV1PFVID6 (PFV1.PFVID6)
#define PFV1PFVID7 (PFV1.PFVID7)
#define PFV1PFVOD0 (PFV1.PFVOD0)
#define PFV1PFVOD1 (PFV1.PFVOD1)
#define PFV1PFVOD2 (PFV1.PFVOD2)
#define PFV1PFVOD3 (PFV1.PFVOD3)
#define PFV1PFVOD4 (PFV1.PFVOD4)
#define PFV1PFVOD5 (PFV1.PFVOD5)
#define PFV1PFVOD6 (PFV1.PFVOD6)
#define PFV1PFVOD7 (PFV1.PFVOD7)
#define PFV1PFVIFSR (PFV1.PFVIFSR)
#define PFV1PFVOFSR (PFV1.PFVOFSR)
#define PFV1PFVACR (PFV1.PFVACR)
#define PFV1PFV_MTX_MODE (PFV1.PFV_MTX_MODE)
#define PFV1PFV_MTX_YG_ADJ0 (PFV1.PFV_MTX_YG_ADJ0)
#define PFV1PFV_MTX_YG_ADJ1 (PFV1.PFV_MTX_YG_ADJ1)
#define PFV1PFV_MTX_CBB_ADJ0 (PFV1.PFV_MTX_CBB_ADJ0)
#define PFV1PFV_MTX_CBB_ADJ1 (PFV1.PFV_MTX_CBB_ADJ1)
#define PFV1PFV_MTX_CRR_ADJ0 (PFV1.PFV_MTX_CRR_ADJ0)
#define PFV1PFV_MTX_CRR_ADJ1 (PFV1.PFV_MTX_CRR_ADJ1)
#define PFV1PFVSZR (PFV1.PFVSZR)
#define PFVID_COUNT (8)
#define PFVOD_COUNT (8)
typedef struct st_pfv
{
/* PFV */
volatile uint32_t PFVCR; /* PFVCR */
volatile uint32_t PFVICR; /* PFVICR */
volatile uint32_t PFVISR; /* PFVISR */
volatile uint8_t dummy1[20]; /* */
/* #define PFVID_COUNT (8) */
volatile uint32_t PFVID0; /* PFVID0 */
volatile uint32_t PFVID1; /* PFVID1 */
volatile uint32_t PFVID2; /* PFVID2 */
volatile uint32_t PFVID3; /* PFVID3 */
volatile uint32_t PFVID4; /* PFVID4 */
volatile uint32_t PFVID5; /* PFVID5 */
volatile uint32_t PFVID6; /* PFVID6 */
volatile uint32_t PFVID7; /* PFVID7 */
/* #define PFVOD_COUNT (8) */
volatile uint32_t PFVOD0; /* PFVOD0 */
volatile uint32_t PFVOD1; /* PFVOD1 */
volatile uint32_t PFVOD2; /* PFVOD2 */
volatile uint32_t PFVOD3; /* PFVOD3 */
volatile uint32_t PFVOD4; /* PFVOD4 */
volatile uint32_t PFVOD5; /* PFVOD5 */
volatile uint32_t PFVOD6; /* PFVOD6 */
volatile uint32_t PFVOD7; /* PFVOD7 */
volatile uint8_t dummy2[4]; /* */
volatile uint32_t PFVIFSR; /* PFVIFSR */
volatile uint32_t PFVOFSR; /* PFVOFSR */
volatile uint32_t PFVACR; /* PFVACR */
volatile uint32_t PFV_MTX_MODE; /* PFV_MTX_MODE */
volatile uint32_t PFV_MTX_YG_ADJ0; /* PFV_MTX_YG_ADJ0 */
volatile uint32_t PFV_MTX_YG_ADJ1; /* PFV_MTX_YG_ADJ1 */
volatile uint32_t PFV_MTX_CBB_ADJ0; /* PFV_MTX_CBB_ADJ0 */
volatile uint32_t PFV_MTX_CBB_ADJ1; /* PFV_MTX_CBB_ADJ1 */
volatile uint32_t PFV_MTX_CRR_ADJ0; /* PFV_MTX_CRR_ADJ0 */
volatile uint32_t PFV_MTX_CRR_ADJ1; /* PFV_MTX_CRR_ADJ1 */
volatile uint32_t PFVSZR; /* PFVSZR */
} r_io_pfv_t;
/* Channel array defines of PFV (2)*/
#ifdef DECLARE_PFV_CHANNELS
volatile struct st_pfv* PFV[ PFV_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
PFV_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_PFV_CHANNELS */
/* End of channel array defines of PFV (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : pwm_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef PWM_IODEFINE_H
#define PWM_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define PWM (*(struct st_pwm *)0xFCFF5004uL) /* PWM */
/* Start of channel array defines of PWM */
/* Channel array defines of PWMn */
/*(Sample) value = PWMn[ channel ]->PWCR_1; */
#define PWMn_COUNT (2)
#define PWMn_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&PWM1, &PWM2 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define PWM1 (*(struct st_pwm_common *)&PWM.PWCR_1) /* PWM1 */
#define PWM2 (*(struct st_pwm_common *)&PWM.PWCR_2) /* PWM2 */
/* End of channel array defines of PWM */
#define PWMPWBTCR (PWM.PWBTCR)
#define PWMPWCR_1 (PWM.PWCR_1)
#define PWMPWPR_1 (PWM.PWPR_1)
#define PWMPWCYR_1 (PWM.PWCYR_1)
#define PWMPWBFR_1A (PWM.PWBFR_1A)
#define PWMPWBFR_1C (PWM.PWBFR_1C)
#define PWMPWBFR_1E (PWM.PWBFR_1E)
#define PWMPWBFR_1G (PWM.PWBFR_1G)
#define PWMPWCR_2 (PWM.PWCR_2)
#define PWMPWPR_2 (PWM.PWPR_2)
#define PWMPWCYR_2 (PWM.PWCYR_2)
#define PWMPWBFR_2A (PWM.PWBFR_2A)
#define PWMPWBFR_2C (PWM.PWBFR_2C)
#define PWMPWBFR_2E (PWM.PWBFR_2E)
#define PWMPWBFR_2G (PWM.PWBFR_2G)
typedef struct st_pwm
{
/* PWM */
volatile uint8_t dummy559[2]; /* */
volatile uint8_t PWBTCR; /* PWBTCR */
volatile uint8_t dummy560[217]; /* */
/* start of struct st_pwm_common */
volatile uint8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy561[3]; /* */
volatile uint8_t PWPR_1; /* PWPR_1 */
volatile uint8_t dummy562[1]; /* */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
/* end of struct st_pwm_common */
/* start of struct st_pwm_common */
volatile uint8_t PWCR_2; /* PWCR_2 */
volatile uint8_t dummy563[3]; /* */
volatile uint8_t PWPR_2; /* PWPR_2 */
volatile uint8_t dummy564[1]; /* */
volatile uint16_t PWCYR_2; /* PWCYR_2 */
volatile uint16_t PWBFR_2A; /* PWBFR_2A */
volatile uint16_t PWBFR_2C; /* PWBFR_2C */
volatile uint16_t PWBFR_2E; /* PWBFR_2E */
volatile uint16_t PWBFR_2G; /* PWBFR_2G */
/* end of struct st_pwm_common */
} r_io_pwm_t;
typedef struct st_pwm_common
{
volatile uint8_t PWCR_1; /* PWCR_1 */
volatile uint8_t dummy562[3]; /* */
volatile uint8_t PWPR_1; /* PWPR_1 */
volatile uint8_t dummy563[1]; /* */
volatile uint16_t PWCYR_1; /* PWCYR_1 */
volatile uint16_t PWBFR_1A; /* PWBFR_1A */
volatile uint16_t PWBFR_1C; /* PWBFR_1C */
volatile uint16_t PWBFR_1E; /* PWBFR_1E */
volatile uint16_t PWBFR_1G; /* PWBFR_1G */
} r_io_pwm_common_t;
/* Channel array defines of PWMn (2)*/
#ifdef DECLARE_PWMn_CHANNELS
volatile struct st_pwm_common* PWMn[ PWMn_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
PWMn_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_PWMn_CHANNELS */
/* End of channel array defines of PWMn (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : riic_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef RIIC_IODEFINE_H
#define RIIC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define RIIC0 (*(struct st_riic *)0xFCFEE000uL) /* RIIC0 */
#define RIIC1 (*(struct st_riic *)0xFCFEE400uL) /* RIIC1 */
#define RIIC2 (*(struct st_riic *)0xFCFEE800uL) /* RIIC2 */
#define RIIC3 (*(struct st_riic *)0xFCFEEC00uL) /* RIIC3 */
/* Start of channel array defines of RIIC */
/* Channel array defines of RIIC */
/*(Sample) value = RIIC[ channel ]->RIICnCR1.UINT32; */
#define RIIC_COUNT (4)
#define RIIC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&RIIC0, &RIIC1, &RIIC2, &RIIC3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of RIIC */
#define RIIC0CR1 (RIIC0.RIICnCR1.UINT32)
#define RIIC0CR1L (RIIC0.RIICnCR1.UINT16[R_IO_L])
#define RIIC0CR1LL (RIIC0.RIICnCR1.UINT8[R_IO_LL])
#define RIIC0CR1LH (RIIC0.RIICnCR1.UINT8[R_IO_LH])
#define RIIC0CR1H (RIIC0.RIICnCR1.UINT16[R_IO_H])
#define RIIC0CR1HL (RIIC0.RIICnCR1.UINT8[R_IO_HL])
#define RIIC0CR1HH (RIIC0.RIICnCR1.UINT8[R_IO_HH])
#define RIIC0CR2 (RIIC0.RIICnCR2.UINT32)
#define RIIC0CR2L (RIIC0.RIICnCR2.UINT16[R_IO_L])
#define RIIC0CR2LL (RIIC0.RIICnCR2.UINT8[R_IO_LL])
#define RIIC0CR2LH (RIIC0.RIICnCR2.UINT8[R_IO_LH])
#define RIIC0CR2H (RIIC0.RIICnCR2.UINT16[R_IO_H])
#define RIIC0CR2HL (RIIC0.RIICnCR2.UINT8[R_IO_HL])
#define RIIC0CR2HH (RIIC0.RIICnCR2.UINT8[R_IO_HH])
#define RIIC0MR1 (RIIC0.RIICnMR1.UINT32)
#define RIIC0MR1L (RIIC0.RIICnMR1.UINT16[R_IO_L])
#define RIIC0MR1LL (RIIC0.RIICnMR1.UINT8[R_IO_LL])
#define RIIC0MR1LH (RIIC0.RIICnMR1.UINT8[R_IO_LH])
#define RIIC0MR1H (RIIC0.RIICnMR1.UINT16[R_IO_H])
#define RIIC0MR1HL (RIIC0.RIICnMR1.UINT8[R_IO_HL])
#define RIIC0MR1HH (RIIC0.RIICnMR1.UINT8[R_IO_HH])
#define RIIC0MR2 (RIIC0.RIICnMR2.UINT32)
#define RIIC0MR2L (RIIC0.RIICnMR2.UINT16[R_IO_L])
#define RIIC0MR2LL (RIIC0.RIICnMR2.UINT8[R_IO_LL])
#define RIIC0MR2LH (RIIC0.RIICnMR2.UINT8[R_IO_LH])
#define RIIC0MR2H (RIIC0.RIICnMR2.UINT16[R_IO_H])
#define RIIC0MR2HL (RIIC0.RIICnMR2.UINT8[R_IO_HL])
#define RIIC0MR2HH (RIIC0.RIICnMR2.UINT8[R_IO_HH])
#define RIIC0MR3 (RIIC0.RIICnMR3.UINT32)
#define RIIC0MR3L (RIIC0.RIICnMR3.UINT16[R_IO_L])
#define RIIC0MR3LL (RIIC0.RIICnMR3.UINT8[R_IO_LL])
#define RIIC0MR3LH (RIIC0.RIICnMR3.UINT8[R_IO_LH])
#define RIIC0MR3H (RIIC0.RIICnMR3.UINT16[R_IO_H])
#define RIIC0MR3HL (RIIC0.RIICnMR3.UINT8[R_IO_HL])
#define RIIC0MR3HH (RIIC0.RIICnMR3.UINT8[R_IO_HH])
#define RIIC0FER (RIIC0.RIICnFER.UINT32)
#define RIIC0FERL (RIIC0.RIICnFER.UINT16[R_IO_L])
#define RIIC0FERLL (RIIC0.RIICnFER.UINT8[R_IO_LL])
#define RIIC0FERLH (RIIC0.RIICnFER.UINT8[R_IO_LH])
#define RIIC0FERH (RIIC0.RIICnFER.UINT16[R_IO_H])
#define RIIC0FERHL (RIIC0.RIICnFER.UINT8[R_IO_HL])
#define RIIC0FERHH (RIIC0.RIICnFER.UINT8[R_IO_HH])
#define RIIC0SER (RIIC0.RIICnSER.UINT32)
#define RIIC0SERL (RIIC0.RIICnSER.UINT16[R_IO_L])
#define RIIC0SERLL (RIIC0.RIICnSER.UINT8[R_IO_LL])
#define RIIC0SERLH (RIIC0.RIICnSER.UINT8[R_IO_LH])
#define RIIC0SERH (RIIC0.RIICnSER.UINT16[R_IO_H])
#define RIIC0SERHL (RIIC0.RIICnSER.UINT8[R_IO_HL])
#define RIIC0SERHH (RIIC0.RIICnSER.UINT8[R_IO_HH])
#define RIIC0IER (RIIC0.RIICnIER.UINT32)
#define RIIC0IERL (RIIC0.RIICnIER.UINT16[R_IO_L])
#define RIIC0IERLL (RIIC0.RIICnIER.UINT8[R_IO_LL])
#define RIIC0IERLH (RIIC0.RIICnIER.UINT8[R_IO_LH])
#define RIIC0IERH (RIIC0.RIICnIER.UINT16[R_IO_H])
#define RIIC0IERHL (RIIC0.RIICnIER.UINT8[R_IO_HL])
#define RIIC0IERHH (RIIC0.RIICnIER.UINT8[R_IO_HH])
#define RIIC0SR1 (RIIC0.RIICnSR1.UINT32)
#define RIIC0SR1L (RIIC0.RIICnSR1.UINT16[R_IO_L])
#define RIIC0SR1LL (RIIC0.RIICnSR1.UINT8[R_IO_LL])
#define RIIC0SR1LH (RIIC0.RIICnSR1.UINT8[R_IO_LH])
#define RIIC0SR1H (RIIC0.RIICnSR1.UINT16[R_IO_H])
#define RIIC0SR1HL (RIIC0.RIICnSR1.UINT8[R_IO_HL])
#define RIIC0SR1HH (RIIC0.RIICnSR1.UINT8[R_IO_HH])
#define RIIC0SR2 (RIIC0.RIICnSR2.UINT32)
#define RIIC0SR2L (RIIC0.RIICnSR2.UINT16[R_IO_L])
#define RIIC0SR2LL (RIIC0.RIICnSR2.UINT8[R_IO_LL])
#define RIIC0SR2LH (RIIC0.RIICnSR2.UINT8[R_IO_LH])
#define RIIC0SR2H (RIIC0.RIICnSR2.UINT16[R_IO_H])
#define RIIC0SR2HL (RIIC0.RIICnSR2.UINT8[R_IO_HL])
#define RIIC0SR2HH (RIIC0.RIICnSR2.UINT8[R_IO_HH])
#define RIIC0SAR0 (RIIC0.RIICnSAR0.UINT32)
#define RIIC0SAR0L (RIIC0.RIICnSAR0.UINT16[R_IO_L])
#define RIIC0SAR0LL (RIIC0.RIICnSAR0.UINT8[R_IO_LL])
#define RIIC0SAR0LH (RIIC0.RIICnSAR0.UINT8[R_IO_LH])
#define RIIC0SAR0H (RIIC0.RIICnSAR0.UINT16[R_IO_H])
#define RIIC0SAR0HL (RIIC0.RIICnSAR0.UINT8[R_IO_HL])
#define RIIC0SAR0HH (RIIC0.RIICnSAR0.UINT8[R_IO_HH])
#define RIIC0SAR1 (RIIC0.RIICnSAR1.UINT32)
#define RIIC0SAR1L (RIIC0.RIICnSAR1.UINT16[R_IO_L])
#define RIIC0SAR1LL (RIIC0.RIICnSAR1.UINT8[R_IO_LL])
#define RIIC0SAR1LH (RIIC0.RIICnSAR1.UINT8[R_IO_LH])
#define RIIC0SAR1H (RIIC0.RIICnSAR1.UINT16[R_IO_H])
#define RIIC0SAR1HL (RIIC0.RIICnSAR1.UINT8[R_IO_HL])
#define RIIC0SAR1HH (RIIC0.RIICnSAR1.UINT8[R_IO_HH])
#define RIIC0SAR2 (RIIC0.RIICnSAR2.UINT32)
#define RIIC0SAR2L (RIIC0.RIICnSAR2.UINT16[R_IO_L])
#define RIIC0SAR2LL (RIIC0.RIICnSAR2.UINT8[R_IO_LL])
#define RIIC0SAR2LH (RIIC0.RIICnSAR2.UINT8[R_IO_LH])
#define RIIC0SAR2H (RIIC0.RIICnSAR2.UINT16[R_IO_H])
#define RIIC0SAR2HL (RIIC0.RIICnSAR2.UINT8[R_IO_HL])
#define RIIC0SAR2HH (RIIC0.RIICnSAR2.UINT8[R_IO_HH])
#define RIIC0BRL (RIIC0.RIICnBRL.UINT32)
#define RIIC0BRLL (RIIC0.RIICnBRL.UINT16[R_IO_L])
#define RIIC0BRLLL (RIIC0.RIICnBRL.UINT8[R_IO_LL])
#define RIIC0BRLLH (RIIC0.RIICnBRL.UINT8[R_IO_LH])
#define RIIC0BRLH (RIIC0.RIICnBRL.UINT16[R_IO_H])
#define RIIC0BRLHL (RIIC0.RIICnBRL.UINT8[R_IO_HL])
#define RIIC0BRLHH (RIIC0.RIICnBRL.UINT8[R_IO_HH])
#define RIIC0BRH (RIIC0.RIICnBRH.UINT32)
#define RIIC0BRHL (RIIC0.RIICnBRH.UINT16[R_IO_L])
#define RIIC0BRHLL (RIIC0.RIICnBRH.UINT8[R_IO_LL])
#define RIIC0BRHLH (RIIC0.RIICnBRH.UINT8[R_IO_LH])
#define RIIC0BRHH (RIIC0.RIICnBRH.UINT16[R_IO_H])
#define RIIC0BRHHL (RIIC0.RIICnBRH.UINT8[R_IO_HL])
#define RIIC0BRHHH (RIIC0.RIICnBRH.UINT8[R_IO_HH])
#define RIIC0DRT (RIIC0.RIICnDRT.UINT32)
#define RIIC0DRTL (RIIC0.RIICnDRT.UINT16[R_IO_L])
#define RIIC0DRTLL (RIIC0.RIICnDRT.UINT8[R_IO_LL])
#define RIIC0DRTLH (RIIC0.RIICnDRT.UINT8[R_IO_LH])
#define RIIC0DRTH (RIIC0.RIICnDRT.UINT16[R_IO_H])
#define RIIC0DRTHL (RIIC0.RIICnDRT.UINT8[R_IO_HL])
#define RIIC0DRTHH (RIIC0.RIICnDRT.UINT8[R_IO_HH])
#define RIIC0DRR (RIIC0.RIICnDRR.UINT32)
#define RIIC0DRRL (RIIC0.RIICnDRR.UINT16[R_IO_L])
#define RIIC0DRRLL (RIIC0.RIICnDRR.UINT8[R_IO_LL])
#define RIIC0DRRLH (RIIC0.RIICnDRR.UINT8[R_IO_LH])
#define RIIC0DRRH (RIIC0.RIICnDRR.UINT16[R_IO_H])
#define RIIC0DRRHL (RIIC0.RIICnDRR.UINT8[R_IO_HL])
#define RIIC0DRRHH (RIIC0.RIICnDRR.UINT8[R_IO_HH])
#define RIIC1CR1 (RIIC1.RIICnCR1.UINT32)
#define RIIC1CR1L (RIIC1.RIICnCR1.UINT16[R_IO_L])
#define RIIC1CR1LL (RIIC1.RIICnCR1.UINT8[R_IO_LL])
#define RIIC1CR1LH (RIIC1.RIICnCR1.UINT8[R_IO_LH])
#define RIIC1CR1H (RIIC1.RIICnCR1.UINT16[R_IO_H])
#define RIIC1CR1HL (RIIC1.RIICnCR1.UINT8[R_IO_HL])
#define RIIC1CR1HH (RIIC1.RIICnCR1.UINT8[R_IO_HH])
#define RIIC1CR2 (RIIC1.RIICnCR2.UINT32)
#define RIIC1CR2L (RIIC1.RIICnCR2.UINT16[R_IO_L])
#define RIIC1CR2LL (RIIC1.RIICnCR2.UINT8[R_IO_LL])
#define RIIC1CR2LH (RIIC1.RIICnCR2.UINT8[R_IO_LH])
#define RIIC1CR2H (RIIC1.RIICnCR2.UINT16[R_IO_H])
#define RIIC1CR2HL (RIIC1.RIICnCR2.UINT8[R_IO_HL])
#define RIIC1CR2HH (RIIC1.RIICnCR2.UINT8[R_IO_HH])
#define RIIC1MR1 (RIIC1.RIICnMR1.UINT32)
#define RIIC1MR1L (RIIC1.RIICnMR1.UINT16[R_IO_L])
#define RIIC1MR1LL (RIIC1.RIICnMR1.UINT8[R_IO_LL])
#define RIIC1MR1LH (RIIC1.RIICnMR1.UINT8[R_IO_LH])
#define RIIC1MR1H (RIIC1.RIICnMR1.UINT16[R_IO_H])
#define RIIC1MR1HL (RIIC1.RIICnMR1.UINT8[R_IO_HL])
#define RIIC1MR1HH (RIIC1.RIICnMR1.UINT8[R_IO_HH])
#define RIIC1MR2 (RIIC1.RIICnMR2.UINT32)
#define RIIC1MR2L (RIIC1.RIICnMR2.UINT16[R_IO_L])
#define RIIC1MR2LL (RIIC1.RIICnMR2.UINT8[R_IO_LL])
#define RIIC1MR2LH (RIIC1.RIICnMR2.UINT8[R_IO_LH])
#define RIIC1MR2H (RIIC1.RIICnMR2.UINT16[R_IO_H])
#define RIIC1MR2HL (RIIC1.RIICnMR2.UINT8[R_IO_HL])
#define RIIC1MR2HH (RIIC1.RIICnMR2.UINT8[R_IO_HH])
#define RIIC1MR3 (RIIC1.RIICnMR3.UINT32)
#define RIIC1MR3L (RIIC1.RIICnMR3.UINT16[R_IO_L])
#define RIIC1MR3LL (RIIC1.RIICnMR3.UINT8[R_IO_LL])
#define RIIC1MR3LH (RIIC1.RIICnMR3.UINT8[R_IO_LH])
#define RIIC1MR3H (RIIC1.RIICnMR3.UINT16[R_IO_H])
#define RIIC1MR3HL (RIIC1.RIICnMR3.UINT8[R_IO_HL])
#define RIIC1MR3HH (RIIC1.RIICnMR3.UINT8[R_IO_HH])
#define RIIC1FER (RIIC1.RIICnFER.UINT32)
#define RIIC1FERL (RIIC1.RIICnFER.UINT16[R_IO_L])
#define RIIC1FERLL (RIIC1.RIICnFER.UINT8[R_IO_LL])
#define RIIC1FERLH (RIIC1.RIICnFER.UINT8[R_IO_LH])
#define RIIC1FERH (RIIC1.RIICnFER.UINT16[R_IO_H])
#define RIIC1FERHL (RIIC1.RIICnFER.UINT8[R_IO_HL])
#define RIIC1FERHH (RIIC1.RIICnFER.UINT8[R_IO_HH])
#define RIIC1SER (RIIC1.RIICnSER.UINT32)
#define RIIC1SERL (RIIC1.RIICnSER.UINT16[R_IO_L])
#define RIIC1SERLL (RIIC1.RIICnSER.UINT8[R_IO_LL])
#define RIIC1SERLH (RIIC1.RIICnSER.UINT8[R_IO_LH])
#define RIIC1SERH (RIIC1.RIICnSER.UINT16[R_IO_H])
#define RIIC1SERHL (RIIC1.RIICnSER.UINT8[R_IO_HL])
#define RIIC1SERHH (RIIC1.RIICnSER.UINT8[R_IO_HH])
#define RIIC1IER (RIIC1.RIICnIER.UINT32)
#define RIIC1IERL (RIIC1.RIICnIER.UINT16[R_IO_L])
#define RIIC1IERLL (RIIC1.RIICnIER.UINT8[R_IO_LL])
#define RIIC1IERLH (RIIC1.RIICnIER.UINT8[R_IO_LH])
#define RIIC1IERH (RIIC1.RIICnIER.UINT16[R_IO_H])
#define RIIC1IERHL (RIIC1.RIICnIER.UINT8[R_IO_HL])
#define RIIC1IERHH (RIIC1.RIICnIER.UINT8[R_IO_HH])
#define RIIC1SR1 (RIIC1.RIICnSR1.UINT32)
#define RIIC1SR1L (RIIC1.RIICnSR1.UINT16[R_IO_L])
#define RIIC1SR1LL (RIIC1.RIICnSR1.UINT8[R_IO_LL])
#define RIIC1SR1LH (RIIC1.RIICnSR1.UINT8[R_IO_LH])
#define RIIC1SR1H (RIIC1.RIICnSR1.UINT16[R_IO_H])
#define RIIC1SR1HL (RIIC1.RIICnSR1.UINT8[R_IO_HL])
#define RIIC1SR1HH (RIIC1.RIICnSR1.UINT8[R_IO_HH])
#define RIIC1SR2 (RIIC1.RIICnSR2.UINT32)
#define RIIC1SR2L (RIIC1.RIICnSR2.UINT16[R_IO_L])
#define RIIC1SR2LL (RIIC1.RIICnSR2.UINT8[R_IO_LL])
#define RIIC1SR2LH (RIIC1.RIICnSR2.UINT8[R_IO_LH])
#define RIIC1SR2H (RIIC1.RIICnSR2.UINT16[R_IO_H])
#define RIIC1SR2HL (RIIC1.RIICnSR2.UINT8[R_IO_HL])
#define RIIC1SR2HH (RIIC1.RIICnSR2.UINT8[R_IO_HH])
#define RIIC1SAR0 (RIIC1.RIICnSAR0.UINT32)
#define RIIC1SAR0L (RIIC1.RIICnSAR0.UINT16[R_IO_L])
#define RIIC1SAR0LL (RIIC1.RIICnSAR0.UINT8[R_IO_LL])
#define RIIC1SAR0LH (RIIC1.RIICnSAR0.UINT8[R_IO_LH])
#define RIIC1SAR0H (RIIC1.RIICnSAR0.UINT16[R_IO_H])
#define RIIC1SAR0HL (RIIC1.RIICnSAR0.UINT8[R_IO_HL])
#define RIIC1SAR0HH (RIIC1.RIICnSAR0.UINT8[R_IO_HH])
#define RIIC1SAR1 (RIIC1.RIICnSAR1.UINT32)
#define RIIC1SAR1L (RIIC1.RIICnSAR1.UINT16[R_IO_L])
#define RIIC1SAR1LL (RIIC1.RIICnSAR1.UINT8[R_IO_LL])
#define RIIC1SAR1LH (RIIC1.RIICnSAR1.UINT8[R_IO_LH])
#define RIIC1SAR1H (RIIC1.RIICnSAR1.UINT16[R_IO_H])
#define RIIC1SAR1HL (RIIC1.RIICnSAR1.UINT8[R_IO_HL])
#define RIIC1SAR1HH (RIIC1.RIICnSAR1.UINT8[R_IO_HH])
#define RIIC1SAR2 (RIIC1.RIICnSAR2.UINT32)
#define RIIC1SAR2L (RIIC1.RIICnSAR2.UINT16[R_IO_L])
#define RIIC1SAR2LL (RIIC1.RIICnSAR2.UINT8[R_IO_LL])
#define RIIC1SAR2LH (RIIC1.RIICnSAR2.UINT8[R_IO_LH])
#define RIIC1SAR2H (RIIC1.RIICnSAR2.UINT16[R_IO_H])
#define RIIC1SAR2HL (RIIC1.RIICnSAR2.UINT8[R_IO_HL])
#define RIIC1SAR2HH (RIIC1.RIICnSAR2.UINT8[R_IO_HH])
#define RIIC1BRL (RIIC1.RIICnBRL.UINT32)
#define RIIC1BRLL (RIIC1.RIICnBRL.UINT16[R_IO_L])
#define RIIC1BRLLL (RIIC1.RIICnBRL.UINT8[R_IO_LL])
#define RIIC1BRLLH (RIIC1.RIICnBRL.UINT8[R_IO_LH])
#define RIIC1BRLH (RIIC1.RIICnBRL.UINT16[R_IO_H])
#define RIIC1BRLHL (RIIC1.RIICnBRL.UINT8[R_IO_HL])
#define RIIC1BRLHH (RIIC1.RIICnBRL.UINT8[R_IO_HH])
#define RIIC1BRH (RIIC1.RIICnBRH.UINT32)
#define RIIC1BRHL (RIIC1.RIICnBRH.UINT16[R_IO_L])
#define RIIC1BRHLL (RIIC1.RIICnBRH.UINT8[R_IO_LL])
#define RIIC1BRHLH (RIIC1.RIICnBRH.UINT8[R_IO_LH])
#define RIIC1BRHH (RIIC1.RIICnBRH.UINT16[R_IO_H])
#define RIIC1BRHHL (RIIC1.RIICnBRH.UINT8[R_IO_HL])
#define RIIC1BRHHH (RIIC1.RIICnBRH.UINT8[R_IO_HH])
#define RIIC1DRT (RIIC1.RIICnDRT.UINT32)
#define RIIC1DRTL (RIIC1.RIICnDRT.UINT16[R_IO_L])
#define RIIC1DRTLL (RIIC1.RIICnDRT.UINT8[R_IO_LL])
#define RIIC1DRTLH (RIIC1.RIICnDRT.UINT8[R_IO_LH])
#define RIIC1DRTH (RIIC1.RIICnDRT.UINT16[R_IO_H])
#define RIIC1DRTHL (RIIC1.RIICnDRT.UINT8[R_IO_HL])
#define RIIC1DRTHH (RIIC1.RIICnDRT.UINT8[R_IO_HH])
#define RIIC1DRR (RIIC1.RIICnDRR.UINT32)
#define RIIC1DRRL (RIIC1.RIICnDRR.UINT16[R_IO_L])
#define RIIC1DRRLL (RIIC1.RIICnDRR.UINT8[R_IO_LL])
#define RIIC1DRRLH (RIIC1.RIICnDRR.UINT8[R_IO_LH])
#define RIIC1DRRH (RIIC1.RIICnDRR.UINT16[R_IO_H])
#define RIIC1DRRHL (RIIC1.RIICnDRR.UINT8[R_IO_HL])
#define RIIC1DRRHH (RIIC1.RIICnDRR.UINT8[R_IO_HH])
#define RIIC2CR1 (RIIC2.RIICnCR1.UINT32)
#define RIIC2CR1L (RIIC2.RIICnCR1.UINT16[R_IO_L])
#define RIIC2CR1LL (RIIC2.RIICnCR1.UINT8[R_IO_LL])
#define RIIC2CR1LH (RIIC2.RIICnCR1.UINT8[R_IO_LH])
#define RIIC2CR1H (RIIC2.RIICnCR1.UINT16[R_IO_H])
#define RIIC2CR1HL (RIIC2.RIICnCR1.UINT8[R_IO_HL])
#define RIIC2CR1HH (RIIC2.RIICnCR1.UINT8[R_IO_HH])
#define RIIC2CR2 (RIIC2.RIICnCR2.UINT32)
#define RIIC2CR2L (RIIC2.RIICnCR2.UINT16[R_IO_L])
#define RIIC2CR2LL (RIIC2.RIICnCR2.UINT8[R_IO_LL])
#define RIIC2CR2LH (RIIC2.RIICnCR2.UINT8[R_IO_LH])
#define RIIC2CR2H (RIIC2.RIICnCR2.UINT16[R_IO_H])
#define RIIC2CR2HL (RIIC2.RIICnCR2.UINT8[R_IO_HL])
#define RIIC2CR2HH (RIIC2.RIICnCR2.UINT8[R_IO_HH])
#define RIIC2MR1 (RIIC2.RIICnMR1.UINT32)
#define RIIC2MR1L (RIIC2.RIICnMR1.UINT16[R_IO_L])
#define RIIC2MR1LL (RIIC2.RIICnMR1.UINT8[R_IO_LL])
#define RIIC2MR1LH (RIIC2.RIICnMR1.UINT8[R_IO_LH])
#define RIIC2MR1H (RIIC2.RIICnMR1.UINT16[R_IO_H])
#define RIIC2MR1HL (RIIC2.RIICnMR1.UINT8[R_IO_HL])
#define RIIC2MR1HH (RIIC2.RIICnMR1.UINT8[R_IO_HH])
#define RIIC2MR2 (RIIC2.RIICnMR2.UINT32)
#define RIIC2MR2L (RIIC2.RIICnMR2.UINT16[R_IO_L])
#define RIIC2MR2LL (RIIC2.RIICnMR2.UINT8[R_IO_LL])
#define RIIC2MR2LH (RIIC2.RIICnMR2.UINT8[R_IO_LH])
#define RIIC2MR2H (RIIC2.RIICnMR2.UINT16[R_IO_H])
#define RIIC2MR2HL (RIIC2.RIICnMR2.UINT8[R_IO_HL])
#define RIIC2MR2HH (RIIC2.RIICnMR2.UINT8[R_IO_HH])
#define RIIC2MR3 (RIIC2.RIICnMR3.UINT32)
#define RIIC2MR3L (RIIC2.RIICnMR3.UINT16[R_IO_L])
#define RIIC2MR3LL (RIIC2.RIICnMR3.UINT8[R_IO_LL])
#define RIIC2MR3LH (RIIC2.RIICnMR3.UINT8[R_IO_LH])
#define RIIC2MR3H (RIIC2.RIICnMR3.UINT16[R_IO_H])
#define RIIC2MR3HL (RIIC2.RIICnMR3.UINT8[R_IO_HL])
#define RIIC2MR3HH (RIIC2.RIICnMR3.UINT8[R_IO_HH])
#define RIIC2FER (RIIC2.RIICnFER.UINT32)
#define RIIC2FERL (RIIC2.RIICnFER.UINT16[R_IO_L])
#define RIIC2FERLL (RIIC2.RIICnFER.UINT8[R_IO_LL])
#define RIIC2FERLH (RIIC2.RIICnFER.UINT8[R_IO_LH])
#define RIIC2FERH (RIIC2.RIICnFER.UINT16[R_IO_H])
#define RIIC2FERHL (RIIC2.RIICnFER.UINT8[R_IO_HL])
#define RIIC2FERHH (RIIC2.RIICnFER.UINT8[R_IO_HH])
#define RIIC2SER (RIIC2.RIICnSER.UINT32)
#define RIIC2SERL (RIIC2.RIICnSER.UINT16[R_IO_L])
#define RIIC2SERLL (RIIC2.RIICnSER.UINT8[R_IO_LL])
#define RIIC2SERLH (RIIC2.RIICnSER.UINT8[R_IO_LH])
#define RIIC2SERH (RIIC2.RIICnSER.UINT16[R_IO_H])
#define RIIC2SERHL (RIIC2.RIICnSER.UINT8[R_IO_HL])
#define RIIC2SERHH (RIIC2.RIICnSER.UINT8[R_IO_HH])
#define RIIC2IER (RIIC2.RIICnIER.UINT32)
#define RIIC2IERL (RIIC2.RIICnIER.UINT16[R_IO_L])
#define RIIC2IERLL (RIIC2.RIICnIER.UINT8[R_IO_LL])
#define RIIC2IERLH (RIIC2.RIICnIER.UINT8[R_IO_LH])
#define RIIC2IERH (RIIC2.RIICnIER.UINT16[R_IO_H])
#define RIIC2IERHL (RIIC2.RIICnIER.UINT8[R_IO_HL])
#define RIIC2IERHH (RIIC2.RIICnIER.UINT8[R_IO_HH])
#define RIIC2SR1 (RIIC2.RIICnSR1.UINT32)
#define RIIC2SR1L (RIIC2.RIICnSR1.UINT16[R_IO_L])
#define RIIC2SR1LL (RIIC2.RIICnSR1.UINT8[R_IO_LL])
#define RIIC2SR1LH (RIIC2.RIICnSR1.UINT8[R_IO_LH])
#define RIIC2SR1H (RIIC2.RIICnSR1.UINT16[R_IO_H])
#define RIIC2SR1HL (RIIC2.RIICnSR1.UINT8[R_IO_HL])
#define RIIC2SR1HH (RIIC2.RIICnSR1.UINT8[R_IO_HH])
#define RIIC2SR2 (RIIC2.RIICnSR2.UINT32)
#define RIIC2SR2L (RIIC2.RIICnSR2.UINT16[R_IO_L])
#define RIIC2SR2LL (RIIC2.RIICnSR2.UINT8[R_IO_LL])
#define RIIC2SR2LH (RIIC2.RIICnSR2.UINT8[R_IO_LH])
#define RIIC2SR2H (RIIC2.RIICnSR2.UINT16[R_IO_H])
#define RIIC2SR2HL (RIIC2.RIICnSR2.UINT8[R_IO_HL])
#define RIIC2SR2HH (RIIC2.RIICnSR2.UINT8[R_IO_HH])
#define RIIC2SAR0 (RIIC2.RIICnSAR0.UINT32)
#define RIIC2SAR0L (RIIC2.RIICnSAR0.UINT16[R_IO_L])
#define RIIC2SAR0LL (RIIC2.RIICnSAR0.UINT8[R_IO_LL])
#define RIIC2SAR0LH (RIIC2.RIICnSAR0.UINT8[R_IO_LH])
#define RIIC2SAR0H (RIIC2.RIICnSAR0.UINT16[R_IO_H])
#define RIIC2SAR0HL (RIIC2.RIICnSAR0.UINT8[R_IO_HL])
#define RIIC2SAR0HH (RIIC2.RIICnSAR0.UINT8[R_IO_HH])
#define RIIC2SAR1 (RIIC2.RIICnSAR1.UINT32)
#define RIIC2SAR1L (RIIC2.RIICnSAR1.UINT16[R_IO_L])
#define RIIC2SAR1LL (RIIC2.RIICnSAR1.UINT8[R_IO_LL])
#define RIIC2SAR1LH (RIIC2.RIICnSAR1.UINT8[R_IO_LH])
#define RIIC2SAR1H (RIIC2.RIICnSAR1.UINT16[R_IO_H])
#define RIIC2SAR1HL (RIIC2.RIICnSAR1.UINT8[R_IO_HL])
#define RIIC2SAR1HH (RIIC2.RIICnSAR1.UINT8[R_IO_HH])
#define RIIC2SAR2 (RIIC2.RIICnSAR2.UINT32)
#define RIIC2SAR2L (RIIC2.RIICnSAR2.UINT16[R_IO_L])
#define RIIC2SAR2LL (RIIC2.RIICnSAR2.UINT8[R_IO_LL])
#define RIIC2SAR2LH (RIIC2.RIICnSAR2.UINT8[R_IO_LH])
#define RIIC2SAR2H (RIIC2.RIICnSAR2.UINT16[R_IO_H])
#define RIIC2SAR2HL (RIIC2.RIICnSAR2.UINT8[R_IO_HL])
#define RIIC2SAR2HH (RIIC2.RIICnSAR2.UINT8[R_IO_HH])
#define RIIC2BRL (RIIC2.RIICnBRL.UINT32)
#define RIIC2BRLL (RIIC2.RIICnBRL.UINT16[R_IO_L])
#define RIIC2BRLLL (RIIC2.RIICnBRL.UINT8[R_IO_LL])
#define RIIC2BRLLH (RIIC2.RIICnBRL.UINT8[R_IO_LH])
#define RIIC2BRLH (RIIC2.RIICnBRL.UINT16[R_IO_H])
#define RIIC2BRLHL (RIIC2.RIICnBRL.UINT8[R_IO_HL])
#define RIIC2BRLHH (RIIC2.RIICnBRL.UINT8[R_IO_HH])
#define RIIC2BRH (RIIC2.RIICnBRH.UINT32)
#define RIIC2BRHL (RIIC2.RIICnBRH.UINT16[R_IO_L])
#define RIIC2BRHLL (RIIC2.RIICnBRH.UINT8[R_IO_LL])
#define RIIC2BRHLH (RIIC2.RIICnBRH.UINT8[R_IO_LH])
#define RIIC2BRHH (RIIC2.RIICnBRH.UINT16[R_IO_H])
#define RIIC2BRHHL (RIIC2.RIICnBRH.UINT8[R_IO_HL])
#define RIIC2BRHHH (RIIC2.RIICnBRH.UINT8[R_IO_HH])
#define RIIC2DRT (RIIC2.RIICnDRT.UINT32)
#define RIIC2DRTL (RIIC2.RIICnDRT.UINT16[R_IO_L])
#define RIIC2DRTLL (RIIC2.RIICnDRT.UINT8[R_IO_LL])
#define RIIC2DRTLH (RIIC2.RIICnDRT.UINT8[R_IO_LH])
#define RIIC2DRTH (RIIC2.RIICnDRT.UINT16[R_IO_H])
#define RIIC2DRTHL (RIIC2.RIICnDRT.UINT8[R_IO_HL])
#define RIIC2DRTHH (RIIC2.RIICnDRT.UINT8[R_IO_HH])
#define RIIC2DRR (RIIC2.RIICnDRR.UINT32)
#define RIIC2DRRL (RIIC2.RIICnDRR.UINT16[R_IO_L])
#define RIIC2DRRLL (RIIC2.RIICnDRR.UINT8[R_IO_LL])
#define RIIC2DRRLH (RIIC2.RIICnDRR.UINT8[R_IO_LH])
#define RIIC2DRRH (RIIC2.RIICnDRR.UINT16[R_IO_H])
#define RIIC2DRRHL (RIIC2.RIICnDRR.UINT8[R_IO_HL])
#define RIIC2DRRHH (RIIC2.RIICnDRR.UINT8[R_IO_HH])
#define RIIC3CR1 (RIIC3.RIICnCR1.UINT32)
#define RIIC3CR1L (RIIC3.RIICnCR1.UINT16[R_IO_L])
#define RIIC3CR1LL (RIIC3.RIICnCR1.UINT8[R_IO_LL])
#define RIIC3CR1LH (RIIC3.RIICnCR1.UINT8[R_IO_LH])
#define RIIC3CR1H (RIIC3.RIICnCR1.UINT16[R_IO_H])
#define RIIC3CR1HL (RIIC3.RIICnCR1.UINT8[R_IO_HL])
#define RIIC3CR1HH (RIIC3.RIICnCR1.UINT8[R_IO_HH])
#define RIIC3CR2 (RIIC3.RIICnCR2.UINT32)
#define RIIC3CR2L (RIIC3.RIICnCR2.UINT16[R_IO_L])
#define RIIC3CR2LL (RIIC3.RIICnCR2.UINT8[R_IO_LL])
#define RIIC3CR2LH (RIIC3.RIICnCR2.UINT8[R_IO_LH])
#define RIIC3CR2H (RIIC3.RIICnCR2.UINT16[R_IO_H])
#define RIIC3CR2HL (RIIC3.RIICnCR2.UINT8[R_IO_HL])
#define RIIC3CR2HH (RIIC3.RIICnCR2.UINT8[R_IO_HH])
#define RIIC3MR1 (RIIC3.RIICnMR1.UINT32)
#define RIIC3MR1L (RIIC3.RIICnMR1.UINT16[R_IO_L])
#define RIIC3MR1LL (RIIC3.RIICnMR1.UINT8[R_IO_LL])
#define RIIC3MR1LH (RIIC3.RIICnMR1.UINT8[R_IO_LH])
#define RIIC3MR1H (RIIC3.RIICnMR1.UINT16[R_IO_H])
#define RIIC3MR1HL (RIIC3.RIICnMR1.UINT8[R_IO_HL])
#define RIIC3MR1HH (RIIC3.RIICnMR1.UINT8[R_IO_HH])
#define RIIC3MR2 (RIIC3.RIICnMR2.UINT32)
#define RIIC3MR2L (RIIC3.RIICnMR2.UINT16[R_IO_L])
#define RIIC3MR2LL (RIIC3.RIICnMR2.UINT8[R_IO_LL])
#define RIIC3MR2LH (RIIC3.RIICnMR2.UINT8[R_IO_LH])
#define RIIC3MR2H (RIIC3.RIICnMR2.UINT16[R_IO_H])
#define RIIC3MR2HL (RIIC3.RIICnMR2.UINT8[R_IO_HL])
#define RIIC3MR2HH (RIIC3.RIICnMR2.UINT8[R_IO_HH])
#define RIIC3MR3 (RIIC3.RIICnMR3.UINT32)
#define RIIC3MR3L (RIIC3.RIICnMR3.UINT16[R_IO_L])
#define RIIC3MR3LL (RIIC3.RIICnMR3.UINT8[R_IO_LL])
#define RIIC3MR3LH (RIIC3.RIICnMR3.UINT8[R_IO_LH])
#define RIIC3MR3H (RIIC3.RIICnMR3.UINT16[R_IO_H])
#define RIIC3MR3HL (RIIC3.RIICnMR3.UINT8[R_IO_HL])
#define RIIC3MR3HH (RIIC3.RIICnMR3.UINT8[R_IO_HH])
#define RIIC3FER (RIIC3.RIICnFER.UINT32)
#define RIIC3FERL (RIIC3.RIICnFER.UINT16[R_IO_L])
#define RIIC3FERLL (RIIC3.RIICnFER.UINT8[R_IO_LL])
#define RIIC3FERLH (RIIC3.RIICnFER.UINT8[R_IO_LH])
#define RIIC3FERH (RIIC3.RIICnFER.UINT16[R_IO_H])
#define RIIC3FERHL (RIIC3.RIICnFER.UINT8[R_IO_HL])
#define RIIC3FERHH (RIIC3.RIICnFER.UINT8[R_IO_HH])
#define RIIC3SER (RIIC3.RIICnSER.UINT32)
#define RIIC3SERL (RIIC3.RIICnSER.UINT16[R_IO_L])
#define RIIC3SERLL (RIIC3.RIICnSER.UINT8[R_IO_LL])
#define RIIC3SERLH (RIIC3.RIICnSER.UINT8[R_IO_LH])
#define RIIC3SERH (RIIC3.RIICnSER.UINT16[R_IO_H])
#define RIIC3SERHL (RIIC3.RIICnSER.UINT8[R_IO_HL])
#define RIIC3SERHH (RIIC3.RIICnSER.UINT8[R_IO_HH])
#define RIIC3IER (RIIC3.RIICnIER.UINT32)
#define RIIC3IERL (RIIC3.RIICnIER.UINT16[R_IO_L])
#define RIIC3IERLL (RIIC3.RIICnIER.UINT8[R_IO_LL])
#define RIIC3IERLH (RIIC3.RIICnIER.UINT8[R_IO_LH])
#define RIIC3IERH (RIIC3.RIICnIER.UINT16[R_IO_H])
#define RIIC3IERHL (RIIC3.RIICnIER.UINT8[R_IO_HL])
#define RIIC3IERHH (RIIC3.RIICnIER.UINT8[R_IO_HH])
#define RIIC3SR1 (RIIC3.RIICnSR1.UINT32)
#define RIIC3SR1L (RIIC3.RIICnSR1.UINT16[R_IO_L])
#define RIIC3SR1LL (RIIC3.RIICnSR1.UINT8[R_IO_LL])
#define RIIC3SR1LH (RIIC3.RIICnSR1.UINT8[R_IO_LH])
#define RIIC3SR1H (RIIC3.RIICnSR1.UINT16[R_IO_H])
#define RIIC3SR1HL (RIIC3.RIICnSR1.UINT8[R_IO_HL])
#define RIIC3SR1HH (RIIC3.RIICnSR1.UINT8[R_IO_HH])
#define RIIC3SR2 (RIIC3.RIICnSR2.UINT32)
#define RIIC3SR2L (RIIC3.RIICnSR2.UINT16[R_IO_L])
#define RIIC3SR2LL (RIIC3.RIICnSR2.UINT8[R_IO_LL])
#define RIIC3SR2LH (RIIC3.RIICnSR2.UINT8[R_IO_LH])
#define RIIC3SR2H (RIIC3.RIICnSR2.UINT16[R_IO_H])
#define RIIC3SR2HL (RIIC3.RIICnSR2.UINT8[R_IO_HL])
#define RIIC3SR2HH (RIIC3.RIICnSR2.UINT8[R_IO_HH])
#define RIIC3SAR0 (RIIC3.RIICnSAR0.UINT32)
#define RIIC3SAR0L (RIIC3.RIICnSAR0.UINT16[R_IO_L])
#define RIIC3SAR0LL (RIIC3.RIICnSAR0.UINT8[R_IO_LL])
#define RIIC3SAR0LH (RIIC3.RIICnSAR0.UINT8[R_IO_LH])
#define RIIC3SAR0H (RIIC3.RIICnSAR0.UINT16[R_IO_H])
#define RIIC3SAR0HL (RIIC3.RIICnSAR0.UINT8[R_IO_HL])
#define RIIC3SAR0HH (RIIC3.RIICnSAR0.UINT8[R_IO_HH])
#define RIIC3SAR1 (RIIC3.RIICnSAR1.UINT32)
#define RIIC3SAR1L (RIIC3.RIICnSAR1.UINT16[R_IO_L])
#define RIIC3SAR1LL (RIIC3.RIICnSAR1.UINT8[R_IO_LL])
#define RIIC3SAR1LH (RIIC3.RIICnSAR1.UINT8[R_IO_LH])
#define RIIC3SAR1H (RIIC3.RIICnSAR1.UINT16[R_IO_H])
#define RIIC3SAR1HL (RIIC3.RIICnSAR1.UINT8[R_IO_HL])
#define RIIC3SAR1HH (RIIC3.RIICnSAR1.UINT8[R_IO_HH])
#define RIIC3SAR2 (RIIC3.RIICnSAR2.UINT32)
#define RIIC3SAR2L (RIIC3.RIICnSAR2.UINT16[R_IO_L])
#define RIIC3SAR2LL (RIIC3.RIICnSAR2.UINT8[R_IO_LL])
#define RIIC3SAR2LH (RIIC3.RIICnSAR2.UINT8[R_IO_LH])
#define RIIC3SAR2H (RIIC3.RIICnSAR2.UINT16[R_IO_H])
#define RIIC3SAR2HL (RIIC3.RIICnSAR2.UINT8[R_IO_HL])
#define RIIC3SAR2HH (RIIC3.RIICnSAR2.UINT8[R_IO_HH])
#define RIIC3BRL (RIIC3.RIICnBRL.UINT32)
#define RIIC3BRLL (RIIC3.RIICnBRL.UINT16[R_IO_L])
#define RIIC3BRLLL (RIIC3.RIICnBRL.UINT8[R_IO_LL])
#define RIIC3BRLLH (RIIC3.RIICnBRL.UINT8[R_IO_LH])
#define RIIC3BRLH (RIIC3.RIICnBRL.UINT16[R_IO_H])
#define RIIC3BRLHL (RIIC3.RIICnBRL.UINT8[R_IO_HL])
#define RIIC3BRLHH (RIIC3.RIICnBRL.UINT8[R_IO_HH])
#define RIIC3BRH (RIIC3.RIICnBRH.UINT32)
#define RIIC3BRHL (RIIC3.RIICnBRH.UINT16[R_IO_L])
#define RIIC3BRHLL (RIIC3.RIICnBRH.UINT8[R_IO_LL])
#define RIIC3BRHLH (RIIC3.RIICnBRH.UINT8[R_IO_LH])
#define RIIC3BRHH (RIIC3.RIICnBRH.UINT16[R_IO_H])
#define RIIC3BRHHL (RIIC3.RIICnBRH.UINT8[R_IO_HL])
#define RIIC3BRHHH (RIIC3.RIICnBRH.UINT8[R_IO_HH])
#define RIIC3DRT (RIIC3.RIICnDRT.UINT32)
#define RIIC3DRTL (RIIC3.RIICnDRT.UINT16[R_IO_L])
#define RIIC3DRTLL (RIIC3.RIICnDRT.UINT8[R_IO_LL])
#define RIIC3DRTLH (RIIC3.RIICnDRT.UINT8[R_IO_LH])
#define RIIC3DRTH (RIIC3.RIICnDRT.UINT16[R_IO_H])
#define RIIC3DRTHL (RIIC3.RIICnDRT.UINT8[R_IO_HL])
#define RIIC3DRTHH (RIIC3.RIICnDRT.UINT8[R_IO_HH])
#define RIIC3DRR (RIIC3.RIICnDRR.UINT32)
#define RIIC3DRRL (RIIC3.RIICnDRR.UINT16[R_IO_L])
#define RIIC3DRRLL (RIIC3.RIICnDRR.UINT8[R_IO_LL])
#define RIIC3DRRLH (RIIC3.RIICnDRR.UINT8[R_IO_LH])
#define RIIC3DRRH (RIIC3.RIICnDRR.UINT16[R_IO_H])
#define RIIC3DRRHL (RIIC3.RIICnDRR.UINT8[R_IO_HL])
#define RIIC3DRRHH (RIIC3.RIICnDRR.UINT8[R_IO_HH])
#define RIICnCRm_COUNT (2)
#define RIICnMRm_COUNT (3)
#define RIICnSRm_COUNT (2)
#define RIICnSARm_COUNT (3)
typedef struct st_riic
{
/* RIIC */
/* #define RIICnCRm_COUNT (2) */
union iodefine_reg32_t RIICnCR1; /* RIICnCR1 */
union iodefine_reg32_t RIICnCR2; /* RIICnCR2 */
/* #define RIICnMRm_COUNT (3) */
union iodefine_reg32_t RIICnMR1; /* RIICnMR1 */
union iodefine_reg32_t RIICnMR2; /* RIICnMR2 */
union iodefine_reg32_t RIICnMR3; /* RIICnMR3 */
union iodefine_reg32_t RIICnFER; /* RIICnFER */
union iodefine_reg32_t RIICnSER; /* RIICnSER */
union iodefine_reg32_t RIICnIER; /* RIICnIER */
/* #define RIICnSRm_COUNT (2) */
union iodefine_reg32_t RIICnSR1; /* RIICnSR1 */
union iodefine_reg32_t RIICnSR2; /* RIICnSR2 */
/* #define RIICnSARm_COUNT (3) */
union iodefine_reg32_t RIICnSAR0; /* RIICnSAR0 */
union iodefine_reg32_t RIICnSAR1; /* RIICnSAR1 */
union iodefine_reg32_t RIICnSAR2; /* RIICnSAR2 */
union iodefine_reg32_t RIICnBRL; /* RIICnBRL */
union iodefine_reg32_t RIICnBRH; /* RIICnBRH */
union iodefine_reg32_t RIICnDRT; /* RIICnDRT */
union iodefine_reg32_t RIICnDRR; /* RIICnDRR */
} r_io_riic_t;
/* Channel array defines of RIIC (2)*/
#ifdef DECLARE_RIIC_CHANNELS
volatile struct st_riic* RIIC[ RIIC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
RIIC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_RIIC_CHANNELS */
/* End of channel array defines of RIIC (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

194
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/romdec_iodefine.h
View File

@ -1,194 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : romdec_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef ROMDEC_IODEFINE_H
#define ROMDEC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define ROMDEC (*(struct st_romdec *)0xE8005000uL) /* ROMDEC */
#define ROMDECCROMEN (ROMDEC.CROMEN)
#define ROMDECCROMSY0 (ROMDEC.CROMSY0)
#define ROMDECCROMCTL0 (ROMDEC.CROMCTL0)
#define ROMDECCROMCTL1 (ROMDEC.CROMCTL1)
#define ROMDECCROMCTL3 (ROMDEC.CROMCTL3)
#define ROMDECCROMCTL4 (ROMDEC.CROMCTL4)
#define ROMDECCROMCTL5 (ROMDEC.CROMCTL5)
#define ROMDECCROMST0 (ROMDEC.CROMST0)
#define ROMDECCROMST1 (ROMDEC.CROMST1)
#define ROMDECCROMST3 (ROMDEC.CROMST3)
#define ROMDECCROMST4 (ROMDEC.CROMST4)
#define ROMDECCROMST5 (ROMDEC.CROMST5)
#define ROMDECCROMST6 (ROMDEC.CROMST6)
#define ROMDECCBUFST0 (ROMDEC.CBUFST0)
#define ROMDECCBUFST1 (ROMDEC.CBUFST1)
#define ROMDECCBUFST2 (ROMDEC.CBUFST2)
#define ROMDECHEAD00 (ROMDEC.HEAD00)
#define ROMDECHEAD01 (ROMDEC.HEAD01)
#define ROMDECHEAD02 (ROMDEC.HEAD02)
#define ROMDECHEAD03 (ROMDEC.HEAD03)
#define ROMDECSHEAD00 (ROMDEC.SHEAD00)
#define ROMDECSHEAD01 (ROMDEC.SHEAD01)
#define ROMDECSHEAD02 (ROMDEC.SHEAD02)
#define ROMDECSHEAD03 (ROMDEC.SHEAD03)
#define ROMDECSHEAD04 (ROMDEC.SHEAD04)
#define ROMDECSHEAD05 (ROMDEC.SHEAD05)
#define ROMDECSHEAD06 (ROMDEC.SHEAD06)
#define ROMDECSHEAD07 (ROMDEC.SHEAD07)
#define ROMDECHEAD20 (ROMDEC.HEAD20)
#define ROMDECHEAD21 (ROMDEC.HEAD21)
#define ROMDECHEAD22 (ROMDEC.HEAD22)
#define ROMDECHEAD23 (ROMDEC.HEAD23)
#define ROMDECSHEAD20 (ROMDEC.SHEAD20)
#define ROMDECSHEAD21 (ROMDEC.SHEAD21)
#define ROMDECSHEAD22 (ROMDEC.SHEAD22)
#define ROMDECSHEAD23 (ROMDEC.SHEAD23)
#define ROMDECSHEAD24 (ROMDEC.SHEAD24)
#define ROMDECSHEAD25 (ROMDEC.SHEAD25)
#define ROMDECSHEAD26 (ROMDEC.SHEAD26)
#define ROMDECSHEAD27 (ROMDEC.SHEAD27)
#define ROMDECCBUFCTL0 (ROMDEC.CBUFCTL0)
#define ROMDECCBUFCTL1 (ROMDEC.CBUFCTL1)
#define ROMDECCBUFCTL2 (ROMDEC.CBUFCTL2)
#define ROMDECCBUFCTL3 (ROMDEC.CBUFCTL3)
#define ROMDECCROMST0M (ROMDEC.CROMST0M)
#define ROMDECROMDECRST (ROMDEC.ROMDECRST)
#define ROMDECRSTSTAT (ROMDEC.RSTSTAT)
#define ROMDECSSI (ROMDEC.SSI)
#define ROMDECINTHOLD (ROMDEC.INTHOLD)
#define ROMDECINHINT (ROMDEC.INHINT)
#define ROMDECSTRMDIN0 (ROMDEC.STRMDIN0)
#define ROMDECSTRMDIN2 (ROMDEC.STRMDIN2)
#define ROMDECSTRMDOUT0 (ROMDEC.STRMDOUT0)
#define ROMDEC_CROMCTL0_COUNT (2)
#define ROMDEC_CROMST0_COUNT (2)
#define ROMDEC_CBUFST0_COUNT (3)
#define ROMDEC_HEAD00_COUNT (4)
#define ROMDEC_SHEAD00_COUNT (8)
#define ROMDEC_HEAD20_COUNT (4)
#define ROMDEC_SHEAD20_COUNT (8)
#define ROMDEC_CBUFCTL0_COUNT (4)
#define ROMDEC_STRMDIN0_COUNT (2)
typedef struct st_romdec
{
/* ROMDEC */
volatile uint8_t CROMEN; /* CROMEN */
volatile uint8_t CROMSY0; /* CROMSY0 */
/* #define ROMDEC_CROMCTL0_COUNT (2) */
volatile uint8_t CROMCTL0; /* CROMCTL0 */
volatile uint8_t CROMCTL1; /* CROMCTL1 */
volatile uint8_t dummy23[1]; /* */
volatile uint8_t CROMCTL3; /* CROMCTL3 */
volatile uint8_t CROMCTL4; /* CROMCTL4 */
volatile uint8_t CROMCTL5; /* CROMCTL5 */
/* #define ROMDEC_CROMST0_COUNT (2) */
volatile uint8_t CROMST0; /* CROMST0 */
volatile uint8_t CROMST1; /* CROMST1 */
volatile uint8_t dummy24[1]; /* */
volatile uint8_t CROMST3; /* CROMST3 */
volatile uint8_t CROMST4; /* CROMST4 */
volatile uint8_t CROMST5; /* CROMST5 */
volatile uint8_t CROMST6; /* CROMST6 */
volatile uint8_t dummy25[5]; /* */
/* #define ROMDEC_CBUFST0_COUNT (3) */
volatile uint8_t CBUFST0; /* CBUFST0 */
volatile uint8_t CBUFST1; /* CBUFST1 */
volatile uint8_t CBUFST2; /* CBUFST2 */
volatile uint8_t dummy26[1]; /* */
/* #define ROMDEC_HEAD00_COUNT (4) */
volatile uint8_t HEAD00; /* HEAD00 */
volatile uint8_t HEAD01; /* HEAD01 */
volatile uint8_t HEAD02; /* HEAD02 */
volatile uint8_t HEAD03; /* HEAD03 */
/* #define ROMDEC_SHEAD00_COUNT (8) */
volatile uint8_t SHEAD00; /* SHEAD00 */
volatile uint8_t SHEAD01; /* SHEAD01 */
volatile uint8_t SHEAD02; /* SHEAD02 */
volatile uint8_t SHEAD03; /* SHEAD03 */
volatile uint8_t SHEAD04; /* SHEAD04 */
volatile uint8_t SHEAD05; /* SHEAD05 */
volatile uint8_t SHEAD06; /* SHEAD06 */
volatile uint8_t SHEAD07; /* SHEAD07 */
/* #define ROMDEC_HEAD20_COUNT (4) */
volatile uint8_t HEAD20; /* HEAD20 */
volatile uint8_t HEAD21; /* HEAD21 */
volatile uint8_t HEAD22; /* HEAD22 */
volatile uint8_t HEAD23; /* HEAD23 */
/* #define ROMDEC_SHEAD20_COUNT (8) */
volatile uint8_t SHEAD20; /* SHEAD20 */
volatile uint8_t SHEAD21; /* SHEAD21 */
volatile uint8_t SHEAD22; /* SHEAD22 */
volatile uint8_t SHEAD23; /* SHEAD23 */
volatile uint8_t SHEAD24; /* SHEAD24 */
volatile uint8_t SHEAD25; /* SHEAD25 */
volatile uint8_t SHEAD26; /* SHEAD26 */
volatile uint8_t SHEAD27; /* SHEAD27 */
volatile uint8_t dummy27[16]; /* */
/* #define ROMDEC_CBUFCTL0_COUNT (4) */
volatile uint8_t CBUFCTL0; /* CBUFCTL0 */
volatile uint8_t CBUFCTL1; /* CBUFCTL1 */
volatile uint8_t CBUFCTL2; /* CBUFCTL2 */
volatile uint8_t CBUFCTL3; /* CBUFCTL3 */
volatile uint8_t dummy28[1]; /* */
volatile uint8_t CROMST0M; /* CROMST0M */
volatile uint8_t dummy29[186]; /* */
volatile uint8_t ROMDECRST; /* ROMDECRST */
volatile uint8_t RSTSTAT; /* RSTSTAT */
volatile uint8_t SSI; /* SSI */
volatile uint8_t dummy30[5]; /* */
volatile uint8_t INTHOLD; /* INTHOLD */
volatile uint8_t INHINT; /* INHINT */
volatile uint8_t dummy31[246]; /* */
/* #define ROMDEC_STRMDIN0_COUNT (2) */
volatile uint16_t STRMDIN0; /* STRMDIN0 */
volatile uint16_t STRMDIN2; /* STRMDIN2 */
volatile uint16_t STRMDOUT0; /* STRMDOUT0 */
} r_io_romdec_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rspi_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef RSPI_IODEFINE_H
#define RSPI_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define RSPI0 (*(struct st_rspi *)0xE800C800uL) /* RSPI0 */
#define RSPI1 (*(struct st_rspi *)0xE800D000uL) /* RSPI1 */
#define RSPI2 (*(struct st_rspi *)0xE800D800uL) /* RSPI2 */
#define RSPI3 (*(struct st_rspi *)0xE800E000uL) /* RSPI3 */
#define RSPI4 (*(struct st_rspi *)0xE800E800uL) /* RSPI4 */
/* Start of channel array defines of RSPI */
/* Channel array defines of RSPI */
/*(Sample) value = RSPI[ channel ]->SPCR; */
#define RSPI_COUNT (5)
#define RSPI_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&RSPI0, &RSPI1, &RSPI2, &RSPI3, &RSPI4 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of RSPI */
#define SPCR_0 (RSPI0.SPCR)
#define SSLP_0 (RSPI0.SSLP)
#define SPPCR_0 (RSPI0.SPPCR)
#define SPSR_0 (RSPI0.SPSR)
#define SPDR_0 (RSPI0.SPDR.UINT32)
#define SPDR_0L (RSPI0.SPDR.UINT16[R_IO_L])
#define SPDR_0H (RSPI0.SPDR.UINT16[R_IO_H])
#define SPDR_0LL (RSPI0.SPDR.UINT8[R_IO_LL])
#define SPDR_0LH (RSPI0.SPDR.UINT8[R_IO_LH])
#define SPDR_0HL (RSPI0.SPDR.UINT8[R_IO_HL])
#define SPDR_0HH (RSPI0.SPDR.UINT8[R_IO_HH])
#define SPSCR_0 (RSPI0.SPSCR)
#define SPSSR_0 (RSPI0.SPSSR)
#define SPBR_0 (RSPI0.SPBR)
#define SPDCR_0 (RSPI0.SPDCR)
#define SPCKD_0 (RSPI0.SPCKD)
#define SSLND_0 (RSPI0.SSLND)
#define SPND_0 (RSPI0.SPND)
#define SPCMD0_0 (RSPI0.SPCMD0)
#define SPCMD1_0 (RSPI0.SPCMD1)
#define SPCMD2_0 (RSPI0.SPCMD2)
#define SPCMD3_0 (RSPI0.SPCMD3)
#define SPBFCR_0 (RSPI0.SPBFCR)
#define SPBFDR_0 (RSPI0.SPBFDR)
#define SPCR_1 (RSPI1.SPCR)
#define SSLP_1 (RSPI1.SSLP)
#define SPPCR_1 (RSPI1.SPPCR)
#define SPSR_1 (RSPI1.SPSR)
#define SPDR_1 (RSPI1.SPDR.UINT32)
#define SPDR_1L (RSPI1.SPDR.UINT16[R_IO_L])
#define SPDR_1H (RSPI1.SPDR.UINT16[R_IO_H])
#define SPDR_1LL (RSPI1.SPDR.UINT8[R_IO_LL])
#define SPDR_1LH (RSPI1.SPDR.UINT8[R_IO_LH])
#define SPDR_1HL (RSPI1.SPDR.UINT8[R_IO_HL])
#define SPDR_1HH (RSPI1.SPDR.UINT8[R_IO_HH])
#define SPSCR_1 (RSPI1.SPSCR)
#define SPSSR_1 (RSPI1.SPSSR)
#define SPBR_1 (RSPI1.SPBR)
#define SPDCR_1 (RSPI1.SPDCR)
#define SPCKD_1 (RSPI1.SPCKD)
#define SSLND_1 (RSPI1.SSLND)
#define SPND_1 (RSPI1.SPND)
#define SPCMD0_1 (RSPI1.SPCMD0)
#define SPCMD1_1 (RSPI1.SPCMD1)
#define SPCMD2_1 (RSPI1.SPCMD2)
#define SPCMD3_1 (RSPI1.SPCMD3)
#define SPBFCR_1 (RSPI1.SPBFCR)
#define SPBFDR_1 (RSPI1.SPBFDR)
#define SPCR_2 (RSPI2.SPCR)
#define SSLP_2 (RSPI2.SSLP)
#define SPPCR_2 (RSPI2.SPPCR)
#define SPSR_2 (RSPI2.SPSR)
#define SPDR_2 (RSPI2.SPDR.UINT32)
#define SPDR_2L (RSPI2.SPDR.UINT16[R_IO_L])
#define SPDR_2H (RSPI2.SPDR.UINT16[R_IO_H])
#define SPDR_2LL (RSPI2.SPDR.UINT8[R_IO_LL])
#define SPDR_2LH (RSPI2.SPDR.UINT8[R_IO_LH])
#define SPDR_2HL (RSPI2.SPDR.UINT8[R_IO_HL])
#define SPDR_2HH (RSPI2.SPDR.UINT8[R_IO_HH])
#define SPSCR_2 (RSPI2.SPSCR)
#define SPSSR_2 (RSPI2.SPSSR)
#define SPBR_2 (RSPI2.SPBR)
#define SPDCR_2 (RSPI2.SPDCR)
#define SPCKD_2 (RSPI2.SPCKD)
#define SSLND_2 (RSPI2.SSLND)
#define SPND_2 (RSPI2.SPND)
#define SPCMD0_2 (RSPI2.SPCMD0)
#define SPCMD1_2 (RSPI2.SPCMD1)
#define SPCMD2_2 (RSPI2.SPCMD2)
#define SPCMD3_2 (RSPI2.SPCMD3)
#define SPBFCR_2 (RSPI2.SPBFCR)
#define SPBFDR_2 (RSPI2.SPBFDR)
#define SPCR_3 (RSPI3.SPCR)
#define SSLP_3 (RSPI3.SSLP)
#define SPPCR_3 (RSPI3.SPPCR)
#define SPSR_3 (RSPI3.SPSR)
#define SPDR_3 (RSPI3.SPDR.UINT32)
#define SPDR_3L (RSPI3.SPDR.UINT16[R_IO_L])
#define SPDR_3H (RSPI3.SPDR.UINT16[R_IO_H])
#define SPDR_3LL (RSPI3.SPDR.UINT8[R_IO_LL])
#define SPDR_3LH (RSPI3.SPDR.UINT8[R_IO_LH])
#define SPDR_3HL (RSPI3.SPDR.UINT8[R_IO_HL])
#define SPDR_3HH (RSPI3.SPDR.UINT8[R_IO_HH])
#define SPSCR_3 (RSPI3.SPSCR)
#define SPSSR_3 (RSPI3.SPSSR)
#define SPBR_3 (RSPI3.SPBR)
#define SPDCR_3 (RSPI3.SPDCR)
#define SPCKD_3 (RSPI3.SPCKD)
#define SSLND_3 (RSPI3.SSLND)
#define SPND_3 (RSPI3.SPND)
#define SPCMD0_3 (RSPI3.SPCMD0)
#define SPCMD1_3 (RSPI3.SPCMD1)
#define SPCMD2_3 (RSPI3.SPCMD2)
#define SPCMD3_3 (RSPI3.SPCMD3)
#define SPBFCR_3 (RSPI3.SPBFCR)
#define SPBFDR_3 (RSPI3.SPBFDR)
#define SPCR_4 (RSPI4.SPCR)
#define SSLP_4 (RSPI4.SSLP)
#define SPPCR_4 (RSPI4.SPPCR)
#define SPSR_4 (RSPI4.SPSR)
#define SPDR_4 (RSPI4.SPDR.UINT32)
#define SPDR_4L (RSPI4.SPDR.UINT16[R_IO_L])
#define SPDR_4H (RSPI4.SPDR.UINT16[R_IO_H])
#define SPDR_4LL (RSPI4.SPDR.UINT8[R_IO_LL])
#define SPDR_4LH (RSPI4.SPDR.UINT8[R_IO_LH])
#define SPDR_4HL (RSPI4.SPDR.UINT8[R_IO_HL])
#define SPDR_4HH (RSPI4.SPDR.UINT8[R_IO_HH])
#define SPSCR_4 (RSPI4.SPSCR)
#define SPSSR_4 (RSPI4.SPSSR)
#define SPBR_4 (RSPI4.SPBR)
#define SPDCR_4 (RSPI4.SPDCR)
#define SPCKD_4 (RSPI4.SPCKD)
#define SSLND_4 (RSPI4.SSLND)
#define SPND_4 (RSPI4.SPND)
#define SPCMD0_4 (RSPI4.SPCMD0)
#define SPCMD1_4 (RSPI4.SPCMD1)
#define SPCMD2_4 (RSPI4.SPCMD2)
#define SPCMD3_4 (RSPI4.SPCMD3)
#define SPBFCR_4 (RSPI4.SPBFCR)
#define SPBFDR_4 (RSPI4.SPBFDR)
#define SPCMD_COUNT (4)
typedef struct st_rspi
{
/* RSPI */
volatile uint8_t SPCR; /* SPCR */
volatile uint8_t SSLP; /* SSLP */
volatile uint8_t SPPCR; /* SPPCR */
volatile uint8_t SPSR; /* SPSR */
union iodefine_reg32_t SPDR; /* SPDR */
volatile uint8_t SPSCR; /* SPSCR */
volatile uint8_t SPSSR; /* SPSSR */
volatile uint8_t SPBR; /* SPBR */
volatile uint8_t SPDCR; /* SPDCR */
volatile uint8_t SPCKD; /* SPCKD */
volatile uint8_t SSLND; /* SSLND */
volatile uint8_t SPND; /* SPND */
volatile uint8_t dummy1[1]; /* */
/* #define SPCMD_COUNT (4) */
volatile uint16_t SPCMD0; /* SPCMD0 */
volatile uint16_t SPCMD1; /* SPCMD1 */
volatile uint16_t SPCMD2; /* SPCMD2 */
volatile uint16_t SPCMD3; /* SPCMD3 */
volatile uint8_t dummy2[8]; /* */
volatile uint8_t SPBFCR; /* SPBFCR */
volatile uint8_t dummy3[1]; /* */
volatile uint16_t SPBFDR; /* SPBFDR */
} r_io_rspi_t;
/* Channel array defines of RSPI (2)*/
#ifdef DECLARE_RSPI_CHANNELS
volatile struct st_rspi* RSPI[ RSPI_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
RSPI_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_RSPI_CHANNELS */
/* End of channel array defines of RSPI (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,111 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : rtc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef RTC_IODEFINE_H
#define RTC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define RTC (*(struct st_rtc *)0xFCFF1000uL) /* RTC */
#define RTCR64CNT (RTC.R64CNT)
#define RTCRSECCNT (RTC.RSECCNT)
#define RTCRMINCNT (RTC.RMINCNT)
#define RTCRHRCNT (RTC.RHRCNT)
#define RTCRWKCNT (RTC.RWKCNT)
#define RTCRDAYCNT (RTC.RDAYCNT)
#define RTCRMONCNT (RTC.RMONCNT)
#define RTCRYRCNT (RTC.RYRCNT)
#define RTCRSECAR (RTC.RSECAR)
#define RTCRMINAR (RTC.RMINAR)
#define RTCRHRAR (RTC.RHRAR)
#define RTCRWKAR (RTC.RWKAR)
#define RTCRDAYAR (RTC.RDAYAR)
#define RTCRMONAR (RTC.RMONAR)
#define RTCRCR1 (RTC.RCR1)
#define RTCRCR2 (RTC.RCR2)
#define RTCRYRAR (RTC.RYRAR)
#define RTCRCR3 (RTC.RCR3)
#define RTCRCR5 (RTC.RCR5)
#define RTCRFRH (RTC.RFRH)
#define RTCRFRL (RTC.RFRL)
typedef struct st_rtc
{
/* RTC */
volatile uint8_t R64CNT; /* R64CNT */
volatile uint8_t dummy537[1]; /* */
volatile uint8_t RSECCNT; /* RSECCNT */
volatile uint8_t dummy538[1]; /* */
volatile uint8_t RMINCNT; /* RMINCNT */
volatile uint8_t dummy539[1]; /* */
volatile uint8_t RHRCNT; /* RHRCNT */
volatile uint8_t dummy540[1]; /* */
volatile uint8_t RWKCNT; /* RWKCNT */
volatile uint8_t dummy541[1]; /* */
volatile uint8_t RDAYCNT; /* RDAYCNT */
volatile uint8_t dummy542[1]; /* */
volatile uint8_t RMONCNT; /* RMONCNT */
volatile uint8_t dummy543[1]; /* */
volatile uint16_t RYRCNT; /* RYRCNT */
volatile uint8_t RSECAR; /* RSECAR */
volatile uint8_t dummy544[1]; /* */
volatile uint8_t RMINAR; /* RMINAR */
volatile uint8_t dummy545[1]; /* */
volatile uint8_t RHRAR; /* RHRAR */
volatile uint8_t dummy546[1]; /* */
volatile uint8_t RWKAR; /* RWKAR */
volatile uint8_t dummy547[1]; /* */
volatile uint8_t RDAYAR; /* RDAYAR */
volatile uint8_t dummy548[1]; /* */
volatile uint8_t RMONAR; /* RMONAR */
volatile uint8_t dummy549[1]; /* */
volatile uint8_t RCR1; /* RCR1 */
volatile uint8_t dummy550[1]; /* */
volatile uint8_t RCR2; /* RCR2 */
volatile uint8_t dummy551[1]; /* */
volatile uint16_t RYRAR; /* RYRAR */
volatile uint8_t dummy552[2]; /* */
volatile uint8_t RCR3; /* RCR3 */
volatile uint8_t dummy553[1]; /* */
volatile uint8_t RCR5; /* RCR5 */
volatile uint8_t dummy554[3]; /* */
volatile uint16_t RFRH; /* RFRH */
volatile uint16_t RFRL; /* RFRL */
} r_io_rtc_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SCIF_IODEFINE_H
#define SCIF_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SCIF0 (*(struct st_scif *)0xE8007000uL) /* SCIF0 */
#define SCIF1 (*(struct st_scif *)0xE8007800uL) /* SCIF1 */
#define SCIF2 (*(struct st_scif *)0xE8008000uL) /* SCIF2 */
#define SCIF3 (*(struct st_scif *)0xE8008800uL) /* SCIF3 */
#define SCIF4 (*(struct st_scif *)0xE8009000uL) /* SCIF4 */
#define SCIF5 (*(struct st_scif *)0xE8009800uL) /* SCIF5 */
#define SCIF6 (*(struct st_scif *)0xE800A000uL) /* SCIF6 */
#define SCIF7 (*(struct st_scif *)0xE800A800uL) /* SCIF7 */
/* Start of channel array defines of SCIF */
/* Channel array defines of SCIF */
/*(Sample) value = SCIF[ channel ]->SCSMR; */
#define SCIF_COUNT (8)
#define SCIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIF0, &SCIF1, &SCIF2, &SCIF3, &SCIF4, &SCIF5, &SCIF6, &SCIF7 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SCIF */
#define SCSMR_0 (SCIF0.SCSMR)
#define SCBRR_0 (SCIF0.SCBRR)
#define SCSCR_0 (SCIF0.SCSCR)
#define SCFTDR_0 (SCIF0.SCFTDR)
#define SCFSR_0 (SCIF0.SCFSR)
#define SCFRDR_0 (SCIF0.SCFRDR)
#define SCFCR_0 (SCIF0.SCFCR)
#define SCFDR_0 (SCIF0.SCFDR)
#define SCSPTR_0 (SCIF0.SCSPTR)
#define SCLSR_0 (SCIF0.SCLSR)
#define SCEMR_0 (SCIF0.SCEMR)
#define SCSMR_1 (SCIF1.SCSMR)
#define SCBRR_1 (SCIF1.SCBRR)
#define SCSCR_1 (SCIF1.SCSCR)
#define SCFTDR_1 (SCIF1.SCFTDR)
#define SCFSR_1 (SCIF1.SCFSR)
#define SCFRDR_1 (SCIF1.SCFRDR)
#define SCFCR_1 (SCIF1.SCFCR)
#define SCFDR_1 (SCIF1.SCFDR)
#define SCSPTR_1 (SCIF1.SCSPTR)
#define SCLSR_1 (SCIF1.SCLSR)
#define SCEMR_1 (SCIF1.SCEMR)
#define SCSMR_2 (SCIF2.SCSMR)
#define SCBRR_2 (SCIF2.SCBRR)
#define SCSCR_2 (SCIF2.SCSCR)
#define SCFTDR_2 (SCIF2.SCFTDR)
#define SCFSR_2 (SCIF2.SCFSR)
#define SCFRDR_2 (SCIF2.SCFRDR)
#define SCFCR_2 (SCIF2.SCFCR)
#define SCFDR_2 (SCIF2.SCFDR)
#define SCSPTR_2 (SCIF2.SCSPTR)
#define SCLSR_2 (SCIF2.SCLSR)
#define SCEMR_2 (SCIF2.SCEMR)
#define SCSMR_3 (SCIF3.SCSMR)
#define SCBRR_3 (SCIF3.SCBRR)
#define SCSCR_3 (SCIF3.SCSCR)
#define SCFTDR_3 (SCIF3.SCFTDR)
#define SCFSR_3 (SCIF3.SCFSR)
#define SCFRDR_3 (SCIF3.SCFRDR)
#define SCFCR_3 (SCIF3.SCFCR)
#define SCFDR_3 (SCIF3.SCFDR)
#define SCSPTR_3 (SCIF3.SCSPTR)
#define SCLSR_3 (SCIF3.SCLSR)
#define SCEMR_3 (SCIF3.SCEMR)
#define SCSMR_4 (SCIF4.SCSMR)
#define SCBRR_4 (SCIF4.SCBRR)
#define SCSCR_4 (SCIF4.SCSCR)
#define SCFTDR_4 (SCIF4.SCFTDR)
#define SCFSR_4 (SCIF4.SCFSR)
#define SCFRDR_4 (SCIF4.SCFRDR)
#define SCFCR_4 (SCIF4.SCFCR)
#define SCFDR_4 (SCIF4.SCFDR)
#define SCSPTR_4 (SCIF4.SCSPTR)
#define SCLSR_4 (SCIF4.SCLSR)
#define SCEMR_4 (SCIF4.SCEMR)
#define SCSMR_5 (SCIF5.SCSMR)
#define SCBRR_5 (SCIF5.SCBRR)
#define SCSCR_5 (SCIF5.SCSCR)
#define SCFTDR_5 (SCIF5.SCFTDR)
#define SCFSR_5 (SCIF5.SCFSR)
#define SCFRDR_5 (SCIF5.SCFRDR)
#define SCFCR_5 (SCIF5.SCFCR)
#define SCFDR_5 (SCIF5.SCFDR)
#define SCSPTR_5 (SCIF5.SCSPTR)
#define SCLSR_5 (SCIF5.SCLSR)
#define SCEMR_5 (SCIF5.SCEMR)
#define SCSMR_6 (SCIF6.SCSMR)
#define SCBRR_6 (SCIF6.SCBRR)
#define SCSCR_6 (SCIF6.SCSCR)
#define SCFTDR_6 (SCIF6.SCFTDR)
#define SCFSR_6 (SCIF6.SCFSR)
#define SCFRDR_6 (SCIF6.SCFRDR)
#define SCFCR_6 (SCIF6.SCFCR)
#define SCFDR_6 (SCIF6.SCFDR)
#define SCSPTR_6 (SCIF6.SCSPTR)
#define SCLSR_6 (SCIF6.SCLSR)
#define SCEMR_6 (SCIF6.SCEMR)
#define SCSMR_7 (SCIF7.SCSMR)
#define SCBRR_7 (SCIF7.SCBRR)
#define SCSCR_7 (SCIF7.SCSCR)
#define SCFTDR_7 (SCIF7.SCFTDR)
#define SCFSR_7 (SCIF7.SCFSR)
#define SCFRDR_7 (SCIF7.SCFRDR)
#define SCFCR_7 (SCIF7.SCFCR)
#define SCFDR_7 (SCIF7.SCFDR)
#define SCSPTR_7 (SCIF7.SCSPTR)
#define SCLSR_7 (SCIF7.SCLSR)
#define SCEMR_7 (SCIF7.SCEMR)
typedef struct st_scif
{
/* SCIF */
volatile uint16_t SCSMR; /* SCSMR */
volatile uint8_t dummy1[2]; /* */
volatile uint8_t SCBRR; /* SCBRR */
volatile uint8_t dummy2[3]; /* */
volatile uint16_t SCSCR; /* SCSCR */
volatile uint8_t dummy3[2]; /* */
volatile uint8_t SCFTDR; /* SCFTDR */
volatile uint8_t dummy4[3]; /* */
volatile uint16_t SCFSR; /* SCFSR */
volatile uint8_t dummy5[2]; /* */
volatile uint8_t SCFRDR; /* SCFRDR */
volatile uint8_t dummy6[3]; /* */
volatile uint16_t SCFCR; /* SCFCR */
volatile uint8_t dummy7[2]; /* */
volatile uint16_t SCFDR; /* SCFDR */
volatile uint8_t dummy8[2]; /* */
volatile uint16_t SCSPTR; /* SCSPTR */
volatile uint8_t dummy9[2]; /* */
volatile uint16_t SCLSR; /* SCLSR */
volatile uint8_t dummy10[2]; /* */
volatile uint16_t SCEMR; /* SCEMR */
} r_io_scif_t;
/* Channel array defines of SCIF (2)*/
#ifdef DECLARE_SCIF_CHANNELS
volatile struct st_scif* SCIF[ SCIF_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCIF_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCIF_CHANNELS */
/* End of channel array defines of SCIF (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,106 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scim_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SCIM_IODEFINE_H
#define SCIM_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SCIM0 (*(struct st_scim *)0xE800B000uL) /* SCIM0 */
#define SCIM1 (*(struct st_scim *)0xE800B800uL) /* SCIM1 */
/* Start of channel array defines of SCIM */
/* Channel array defines of SCIM */
/*(Sample) value = SCIM[ channel ]->SMR; */
#define SCIM_COUNT (2)
#define SCIM_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCIM0, &SCIM1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SCIM */
#define SMR0 (SCIM0.SMR)
#define BRR0 (SCIM0.BRR)
#define SCR0 (SCIM0.SCR)
#define TDR0 (SCIM0.TDR)
#define SSR0 (SCIM0.SSR)
#define RDR0 (SCIM0.RDR)
#define SCMR0 (SCIM0.SCMR)
#define SEMR0 (SCIM0.SEMR)
#define SNFR0 (SCIM0.SNFR)
#define SECR0 (SCIM0.SECR)
#define SMR1 (SCIM1.SMR)
#define BRR1 (SCIM1.BRR)
#define SCR1 (SCIM1.SCR)
#define TDR1 (SCIM1.TDR)
#define SSR1 (SCIM1.SSR)
#define RDR1 (SCIM1.RDR)
#define SCMR1 (SCIM1.SCMR)
#define SEMR1 (SCIM1.SEMR)
#define SNFR1 (SCIM1.SNFR)
#define SECR1 (SCIM1.SECR)
typedef struct st_scim
{
/* SCIM */
volatile uint8_t SMR; /* SMR */
volatile uint8_t BRR; /* BRR */
volatile uint8_t SCR; /* SCR */
volatile uint8_t TDR; /* TDR */
volatile uint8_t SSR; /* SSR */
volatile uint8_t RDR; /* RDR */
volatile uint8_t SCMR; /* SCMR */
volatile uint8_t SEMR; /* SEMR */
volatile uint8_t SNFR; /* SNFR */
volatile uint8_t dummy1[4]; /* */
volatile uint8_t SECR; /* SECR */
} r_io_scim_t;
/* Channel array defines of SCIM (2)*/
#ifdef DECLARE_SCIM_CHANNELS
volatile struct st_scim* SCIM[ SCIM_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCIM_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCIM_CHANNELS */
/* End of channel array defines of SCIM (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,921 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : scux_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SCUX_IODEFINE_H
#define SCUX_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SCUX (*(struct st_scux *)0xE8208000uL) /* SCUX */
/* Start of channel array defines of SCUX */
/* Channel array defines of SCUX_FROM_DVUIR_DVU0_0_ARRAY */
/*(Sample) value = SCUX_FROM_DVUIR_DVU0_0_ARRAY[ channel ]->DVUIR_DVU0_0; */
#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT (4)
#define SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_DVUIR_DVU0_0, &SCUX_FROM_DVUIR_DVU0_1, &SCUX_FROM_DVUIR_DVU0_2, &SCUX_FROM_DVUIR_DVU0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_DVUIR_DVU0_0 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_0) /* SCUX_FROM_DVUIR_DVU0_0 */
#define SCUX_FROM_DVUIR_DVU0_1 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_1) /* SCUX_FROM_DVUIR_DVU0_1 */
#define SCUX_FROM_DVUIR_DVU0_2 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_2) /* SCUX_FROM_DVUIR_DVU0_2 */
#define SCUX_FROM_DVUIR_DVU0_3 (*(struct st_scux_from_dvuir_dvu0_n *)&SCUX.DVUIR_DVU0_3) /* SCUX_FROM_DVUIR_DVU0_3 */
/* Channel array defines of SCUX_FROM_SRCIR0_2SRC0_0_ARRAY */
/*(Sample) value = SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ channel ]->SRCIR0_2SRC0_0; */
#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT (2)
#define SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_SRCIR0_2SRC0_0, &SCUX_FROM_SRCIR0_2SRC0_1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_SRCIR0_2SRC0_0 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_0) /* SCUX_FROM_SRCIR0_2SRC0_0 */
#define SCUX_FROM_SRCIR0_2SRC0_1 (*(struct st_scux_from_srcir0_2src0_n *)&SCUX.SRCIR0_2SRC0_1) /* SCUX_FROM_SRCIR0_2SRC0_1 */
/* Channel array defines of SCUX_FROM_FFUIR_FFU0_0_ARRAY */
/*(Sample) value = SCUX_FROM_FFUIR_FFU0_0_ARRAY[ channel ]->FFUIR_FFU0_0; */
#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT (4)
#define SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_FFUIR_FFU0_0, &SCUX_FROM_FFUIR_FFU0_1, &SCUX_FROM_FFUIR_FFU0_2, &SCUX_FROM_FFUIR_FFU0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_FFUIR_FFU0_0 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_0) /* SCUX_FROM_FFUIR_FFU0_0 */
#define SCUX_FROM_FFUIR_FFU0_1 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_1) /* SCUX_FROM_FFUIR_FFU0_1 */
#define SCUX_FROM_FFUIR_FFU0_2 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_2) /* SCUX_FROM_FFUIR_FFU0_2 */
#define SCUX_FROM_FFUIR_FFU0_3 (*(struct st_scux_from_ffuir_ffu0_n *)&SCUX.FFUIR_FFU0_3) /* SCUX_FROM_FFUIR_FFU0_3 */
/* Channel array defines of SCUX_FROM_FFDIR_FFD0_0_ARRAY */
/*(Sample) value = SCUX_FROM_FFDIR_FFD0_0_ARRAY[ channel ]->FFDIR_FFD0_0; */
#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT (4)
#define SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_FFDIR_FFD0_0, &SCUX_FROM_FFDIR_FFD0_1, &SCUX_FROM_FFDIR_FFD0_2, &SCUX_FROM_FFDIR_FFD0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_FFDIR_FFD0_0 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_0) /* SCUX_FROM_FFDIR_FFD0_0 */
#define SCUX_FROM_FFDIR_FFD0_1 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_1) /* SCUX_FROM_FFDIR_FFD0_1 */
#define SCUX_FROM_FFDIR_FFD0_2 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_2) /* SCUX_FROM_FFDIR_FFD0_2 */
#define SCUX_FROM_FFDIR_FFD0_3 (*(struct st_scux_from_ffdir_ffd0_n *)&SCUX.FFDIR_FFD0_3) /* SCUX_FROM_FFDIR_FFD0_3 */
/* Channel array defines of SCUX_FROM_OPCIR_OPC0_0_ARRAY */
/*(Sample) value = SCUX_FROM_OPCIR_OPC0_0_ARRAY[ channel ]->OPCIR_OPC0_0; */
#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT (4)
#define SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_OPCIR_OPC0_0, &SCUX_FROM_OPCIR_OPC0_1, &SCUX_FROM_OPCIR_OPC0_2, &SCUX_FROM_OPCIR_OPC0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_OPCIR_OPC0_0 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_0) /* SCUX_FROM_OPCIR_OPC0_0 */
#define SCUX_FROM_OPCIR_OPC0_1 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_1) /* SCUX_FROM_OPCIR_OPC0_1 */
#define SCUX_FROM_OPCIR_OPC0_2 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_2) /* SCUX_FROM_OPCIR_OPC0_2 */
#define SCUX_FROM_OPCIR_OPC0_3 (*(struct st_scux_from_opcir_opc0_n *)&SCUX.OPCIR_OPC0_3) /* SCUX_FROM_OPCIR_OPC0_3 */
/* Channel array defines of SCUX_FROM_IPCIR_IPC0_0_ARRAY */
/*(Sample) value = SCUX_FROM_IPCIR_IPC0_0_ARRAY[ channel ]->IPCIR_IPC0_0; */
#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT (4)
#define SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SCUX_FROM_IPCIR_IPC0_0, &SCUX_FROM_IPCIR_IPC0_1, &SCUX_FROM_IPCIR_IPC0_2, &SCUX_FROM_IPCIR_IPC0_3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define SCUX_FROM_IPCIR_IPC0_0 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_0) /* SCUX_FROM_IPCIR_IPC0_0 */
#define SCUX_FROM_IPCIR_IPC0_1 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_1) /* SCUX_FROM_IPCIR_IPC0_1 */
#define SCUX_FROM_IPCIR_IPC0_2 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_2) /* SCUX_FROM_IPCIR_IPC0_2 */
#define SCUX_FROM_IPCIR_IPC0_3 (*(struct st_scux_from_ipcir_ipc0_n *)&SCUX.IPCIR_IPC0_3) /* SCUX_FROM_IPCIR_IPC0_3 */
/* End of channel array defines of SCUX */
#define SCUXIPCIR_IPC0_0 (SCUX.IPCIR_IPC0_0)
#define SCUXIPSLR_IPC0_0 (SCUX.IPSLR_IPC0_0)
#define SCUXIPCIR_IPC0_1 (SCUX.IPCIR_IPC0_1)
#define SCUXIPSLR_IPC0_1 (SCUX.IPSLR_IPC0_1)
#define SCUXIPCIR_IPC0_2 (SCUX.IPCIR_IPC0_2)
#define SCUXIPSLR_IPC0_2 (SCUX.IPSLR_IPC0_2)
#define SCUXIPCIR_IPC0_3 (SCUX.IPCIR_IPC0_3)
#define SCUXIPSLR_IPC0_3 (SCUX.IPSLR_IPC0_3)
#define SCUXOPCIR_OPC0_0 (SCUX.OPCIR_OPC0_0)
#define SCUXOPSLR_OPC0_0 (SCUX.OPSLR_OPC0_0)
#define SCUXOPCIR_OPC0_1 (SCUX.OPCIR_OPC0_1)
#define SCUXOPSLR_OPC0_1 (SCUX.OPSLR_OPC0_1)
#define SCUXOPCIR_OPC0_2 (SCUX.OPCIR_OPC0_2)
#define SCUXOPSLR_OPC0_2 (SCUX.OPSLR_OPC0_2)
#define SCUXOPCIR_OPC0_3 (SCUX.OPCIR_OPC0_3)
#define SCUXOPSLR_OPC0_3 (SCUX.OPSLR_OPC0_3)
#define SCUXFFDIR_FFD0_0 (SCUX.FFDIR_FFD0_0)
#define SCUXFDAIR_FFD0_0 (SCUX.FDAIR_FFD0_0)
#define SCUXDRQSR_FFD0_0 (SCUX.DRQSR_FFD0_0)
#define SCUXFFDPR_FFD0_0 (SCUX.FFDPR_FFD0_0)
#define SCUXFFDBR_FFD0_0 (SCUX.FFDBR_FFD0_0)
#define SCUXDEVMR_FFD0_0 (SCUX.DEVMR_FFD0_0)
#define SCUXDEVCR_FFD0_0 (SCUX.DEVCR_FFD0_0)
#define SCUXFFDIR_FFD0_1 (SCUX.FFDIR_FFD0_1)
#define SCUXFDAIR_FFD0_1 (SCUX.FDAIR_FFD0_1)
#define SCUXDRQSR_FFD0_1 (SCUX.DRQSR_FFD0_1)
#define SCUXFFDPR_FFD0_1 (SCUX.FFDPR_FFD0_1)
#define SCUXFFDBR_FFD0_1 (SCUX.FFDBR_FFD0_1)
#define SCUXDEVMR_FFD0_1 (SCUX.DEVMR_FFD0_1)
#define SCUXDEVCR_FFD0_1 (SCUX.DEVCR_FFD0_1)
#define SCUXFFDIR_FFD0_2 (SCUX.FFDIR_FFD0_2)
#define SCUXFDAIR_FFD0_2 (SCUX.FDAIR_FFD0_2)
#define SCUXDRQSR_FFD0_2 (SCUX.DRQSR_FFD0_2)
#define SCUXFFDPR_FFD0_2 (SCUX.FFDPR_FFD0_2)
#define SCUXFFDBR_FFD0_2 (SCUX.FFDBR_FFD0_2)
#define SCUXDEVMR_FFD0_2 (SCUX.DEVMR_FFD0_2)
#define SCUXDEVCR_FFD0_2 (SCUX.DEVCR_FFD0_2)
#define SCUXFFDIR_FFD0_3 (SCUX.FFDIR_FFD0_3)
#define SCUXFDAIR_FFD0_3 (SCUX.FDAIR_FFD0_3)
#define SCUXDRQSR_FFD0_3 (SCUX.DRQSR_FFD0_3)
#define SCUXFFDPR_FFD0_3 (SCUX.FFDPR_FFD0_3)
#define SCUXFFDBR_FFD0_3 (SCUX.FFDBR_FFD0_3)
#define SCUXDEVMR_FFD0_3 (SCUX.DEVMR_FFD0_3)
#define SCUXDEVCR_FFD0_3 (SCUX.DEVCR_FFD0_3)
#define SCUXFFUIR_FFU0_0 (SCUX.FFUIR_FFU0_0)
#define SCUXFUAIR_FFU0_0 (SCUX.FUAIR_FFU0_0)
#define SCUXURQSR_FFU0_0 (SCUX.URQSR_FFU0_0)
#define SCUXFFUPR_FFU0_0 (SCUX.FFUPR_FFU0_0)
#define SCUXUEVMR_FFU0_0 (SCUX.UEVMR_FFU0_0)
#define SCUXUEVCR_FFU0_0 (SCUX.UEVCR_FFU0_0)
#define SCUXFFUIR_FFU0_1 (SCUX.FFUIR_FFU0_1)
#define SCUXFUAIR_FFU0_1 (SCUX.FUAIR_FFU0_1)
#define SCUXURQSR_FFU0_1 (SCUX.URQSR_FFU0_1)
#define SCUXFFUPR_FFU0_1 (SCUX.FFUPR_FFU0_1)
#define SCUXUEVMR_FFU0_1 (SCUX.UEVMR_FFU0_1)
#define SCUXUEVCR_FFU0_1 (SCUX.UEVCR_FFU0_1)
#define SCUXFFUIR_FFU0_2 (SCUX.FFUIR_FFU0_2)
#define SCUXFUAIR_FFU0_2 (SCUX.FUAIR_FFU0_2)
#define SCUXURQSR_FFU0_2 (SCUX.URQSR_FFU0_2)
#define SCUXFFUPR_FFU0_2 (SCUX.FFUPR_FFU0_2)
#define SCUXUEVMR_FFU0_2 (SCUX.UEVMR_FFU0_2)
#define SCUXUEVCR_FFU0_2 (SCUX.UEVCR_FFU0_2)
#define SCUXFFUIR_FFU0_3 (SCUX.FFUIR_FFU0_3)
#define SCUXFUAIR_FFU0_3 (SCUX.FUAIR_FFU0_3)
#define SCUXURQSR_FFU0_3 (SCUX.URQSR_FFU0_3)
#define SCUXFFUPR_FFU0_3 (SCUX.FFUPR_FFU0_3)
#define SCUXUEVMR_FFU0_3 (SCUX.UEVMR_FFU0_3)
#define SCUXUEVCR_FFU0_3 (SCUX.UEVCR_FFU0_3)
#define SCUXSRCIR0_2SRC0_0 (SCUX.SRCIR0_2SRC0_0)
#define SCUXSADIR0_2SRC0_0 (SCUX.SADIR0_2SRC0_0)
#define SCUXSRCBR0_2SRC0_0 (SCUX.SRCBR0_2SRC0_0)
#define SCUXIFSCR0_2SRC0_0 (SCUX.IFSCR0_2SRC0_0)
#define SCUXIFSVR0_2SRC0_0 (SCUX.IFSVR0_2SRC0_0)
#define SCUXSRCCR0_2SRC0_0 (SCUX.SRCCR0_2SRC0_0)
#define SCUXMNFSR0_2SRC0_0 (SCUX.MNFSR0_2SRC0_0)
#define SCUXBFSSR0_2SRC0_0 (SCUX.BFSSR0_2SRC0_0)
#define SCUXSC2SR0_2SRC0_0 (SCUX.SC2SR0_2SRC0_0)
#define SCUXWATSR0_2SRC0_0 (SCUX.WATSR0_2SRC0_0)
#define SCUXSEVMR0_2SRC0_0 (SCUX.SEVMR0_2SRC0_0)
#define SCUXSEVCR0_2SRC0_0 (SCUX.SEVCR0_2SRC0_0)
#define SCUXSRCIR1_2SRC0_0 (SCUX.SRCIR1_2SRC0_0)
#define SCUXSADIR1_2SRC0_0 (SCUX.SADIR1_2SRC0_0)
#define SCUXSRCBR1_2SRC0_0 (SCUX.SRCBR1_2SRC0_0)
#define SCUXIFSCR1_2SRC0_0 (SCUX.IFSCR1_2SRC0_0)
#define SCUXIFSVR1_2SRC0_0 (SCUX.IFSVR1_2SRC0_0)
#define SCUXSRCCR1_2SRC0_0 (SCUX.SRCCR1_2SRC0_0)
#define SCUXMNFSR1_2SRC0_0 (SCUX.MNFSR1_2SRC0_0)
#define SCUXBFSSR1_2SRC0_0 (SCUX.BFSSR1_2SRC0_0)
#define SCUXSC2SR1_2SRC0_0 (SCUX.SC2SR1_2SRC0_0)
#define SCUXWATSR1_2SRC0_0 (SCUX.WATSR1_2SRC0_0)
#define SCUXSEVMR1_2SRC0_0 (SCUX.SEVMR1_2SRC0_0)
#define SCUXSEVCR1_2SRC0_0 (SCUX.SEVCR1_2SRC0_0)
#define SCUXSRCIRR_2SRC0_0 (SCUX.SRCIRR_2SRC0_0)
#define SCUXSRCIR0_2SRC0_1 (SCUX.SRCIR0_2SRC0_1)
#define SCUXSADIR0_2SRC0_1 (SCUX.SADIR0_2SRC0_1)
#define SCUXSRCBR0_2SRC0_1 (SCUX.SRCBR0_2SRC0_1)
#define SCUXIFSCR0_2SRC0_1 (SCUX.IFSCR0_2SRC0_1)
#define SCUXIFSVR0_2SRC0_1 (SCUX.IFSVR0_2SRC0_1)
#define SCUXSRCCR0_2SRC0_1 (SCUX.SRCCR0_2SRC0_1)
#define SCUXMNFSR0_2SRC0_1 (SCUX.MNFSR0_2SRC0_1)
#define SCUXBFSSR0_2SRC0_1 (SCUX.BFSSR0_2SRC0_1)
#define SCUXSC2SR0_2SRC0_1 (SCUX.SC2SR0_2SRC0_1)
#define SCUXWATSR0_2SRC0_1 (SCUX.WATSR0_2SRC0_1)
#define SCUXSEVMR0_2SRC0_1 (SCUX.SEVMR0_2SRC0_1)
#define SCUXSEVCR0_2SRC0_1 (SCUX.SEVCR0_2SRC0_1)
#define SCUXSRCIR1_2SRC0_1 (SCUX.SRCIR1_2SRC0_1)
#define SCUXSADIR1_2SRC0_1 (SCUX.SADIR1_2SRC0_1)
#define SCUXSRCBR1_2SRC0_1 (SCUX.SRCBR1_2SRC0_1)
#define SCUXIFSCR1_2SRC0_1 (SCUX.IFSCR1_2SRC0_1)
#define SCUXIFSVR1_2SRC0_1 (SCUX.IFSVR1_2SRC0_1)
#define SCUXSRCCR1_2SRC0_1 (SCUX.SRCCR1_2SRC0_1)
#define SCUXMNFSR1_2SRC0_1 (SCUX.MNFSR1_2SRC0_1)
#define SCUXBFSSR1_2SRC0_1 (SCUX.BFSSR1_2SRC0_1)
#define SCUXSC2SR1_2SRC0_1 (SCUX.SC2SR1_2SRC0_1)
#define SCUXWATSR1_2SRC0_1 (SCUX.WATSR1_2SRC0_1)
#define SCUXSEVMR1_2SRC0_1 (SCUX.SEVMR1_2SRC0_1)
#define SCUXSEVCR1_2SRC0_1 (SCUX.SEVCR1_2SRC0_1)
#define SCUXSRCIRR_2SRC0_1 (SCUX.SRCIRR_2SRC0_1)
#define SCUXDVUIR_DVU0_0 (SCUX.DVUIR_DVU0_0)
#define SCUXVADIR_DVU0_0 (SCUX.VADIR_DVU0_0)
#define SCUXDVUBR_DVU0_0 (SCUX.DVUBR_DVU0_0)
#define SCUXDVUCR_DVU0_0 (SCUX.DVUCR_DVU0_0)
#define SCUXZCMCR_DVU0_0 (SCUX.ZCMCR_DVU0_0)
#define SCUXVRCTR_DVU0_0 (SCUX.VRCTR_DVU0_0)
#define SCUXVRPDR_DVU0_0 (SCUX.VRPDR_DVU0_0)
#define SCUXVRDBR_DVU0_0 (SCUX.VRDBR_DVU0_0)
#define SCUXVRWTR_DVU0_0 (SCUX.VRWTR_DVU0_0)
#define SCUXVOL0R_DVU0_0 (SCUX.VOL0R_DVU0_0)
#define SCUXVOL1R_DVU0_0 (SCUX.VOL1R_DVU0_0)
#define SCUXVOL2R_DVU0_0 (SCUX.VOL2R_DVU0_0)
#define SCUXVOL3R_DVU0_0 (SCUX.VOL3R_DVU0_0)
#define SCUXVOL4R_DVU0_0 (SCUX.VOL4R_DVU0_0)
#define SCUXVOL5R_DVU0_0 (SCUX.VOL5R_DVU0_0)
#define SCUXVOL6R_DVU0_0 (SCUX.VOL6R_DVU0_0)
#define SCUXVOL7R_DVU0_0 (SCUX.VOL7R_DVU0_0)
#define SCUXDVUER_DVU0_0 (SCUX.DVUER_DVU0_0)
#define SCUXDVUSR_DVU0_0 (SCUX.DVUSR_DVU0_0)
#define SCUXVEVMR_DVU0_0 (SCUX.VEVMR_DVU0_0)
#define SCUXVEVCR_DVU0_0 (SCUX.VEVCR_DVU0_0)
#define SCUXDVUIR_DVU0_1 (SCUX.DVUIR_DVU0_1)
#define SCUXVADIR_DVU0_1 (SCUX.VADIR_DVU0_1)
#define SCUXDVUBR_DVU0_1 (SCUX.DVUBR_DVU0_1)
#define SCUXDVUCR_DVU0_1 (SCUX.DVUCR_DVU0_1)
#define SCUXZCMCR_DVU0_1 (SCUX.ZCMCR_DVU0_1)
#define SCUXVRCTR_DVU0_1 (SCUX.VRCTR_DVU0_1)
#define SCUXVRPDR_DVU0_1 (SCUX.VRPDR_DVU0_1)
#define SCUXVRDBR_DVU0_1 (SCUX.VRDBR_DVU0_1)
#define SCUXVRWTR_DVU0_1 (SCUX.VRWTR_DVU0_1)
#define SCUXVOL0R_DVU0_1 (SCUX.VOL0R_DVU0_1)
#define SCUXVOL1R_DVU0_1 (SCUX.VOL1R_DVU0_1)
#define SCUXVOL2R_DVU0_1 (SCUX.VOL2R_DVU0_1)
#define SCUXVOL3R_DVU0_1 (SCUX.VOL3R_DVU0_1)
#define SCUXVOL4R_DVU0_1 (SCUX.VOL4R_DVU0_1)
#define SCUXVOL5R_DVU0_1 (SCUX.VOL5R_DVU0_1)
#define SCUXVOL6R_DVU0_1 (SCUX.VOL6R_DVU0_1)
#define SCUXVOL7R_DVU0_1 (SCUX.VOL7R_DVU0_1)
#define SCUXDVUER_DVU0_1 (SCUX.DVUER_DVU0_1)
#define SCUXDVUSR_DVU0_1 (SCUX.DVUSR_DVU0_1)
#define SCUXVEVMR_DVU0_1 (SCUX.VEVMR_DVU0_1)
#define SCUXVEVCR_DVU0_1 (SCUX.VEVCR_DVU0_1)
#define SCUXDVUIR_DVU0_2 (SCUX.DVUIR_DVU0_2)
#define SCUXVADIR_DVU0_2 (SCUX.VADIR_DVU0_2)
#define SCUXDVUBR_DVU0_2 (SCUX.DVUBR_DVU0_2)
#define SCUXDVUCR_DVU0_2 (SCUX.DVUCR_DVU0_2)
#define SCUXZCMCR_DVU0_2 (SCUX.ZCMCR_DVU0_2)
#define SCUXVRCTR_DVU0_2 (SCUX.VRCTR_DVU0_2)
#define SCUXVRPDR_DVU0_2 (SCUX.VRPDR_DVU0_2)
#define SCUXVRDBR_DVU0_2 (SCUX.VRDBR_DVU0_2)
#define SCUXVRWTR_DVU0_2 (SCUX.VRWTR_DVU0_2)
#define SCUXVOL0R_DVU0_2 (SCUX.VOL0R_DVU0_2)
#define SCUXVOL1R_DVU0_2 (SCUX.VOL1R_DVU0_2)
#define SCUXVOL2R_DVU0_2 (SCUX.VOL2R_DVU0_2)
#define SCUXVOL3R_DVU0_2 (SCUX.VOL3R_DVU0_2)
#define SCUXVOL4R_DVU0_2 (SCUX.VOL4R_DVU0_2)
#define SCUXVOL5R_DVU0_2 (SCUX.VOL5R_DVU0_2)
#define SCUXVOL6R_DVU0_2 (SCUX.VOL6R_DVU0_2)
#define SCUXVOL7R_DVU0_2 (SCUX.VOL7R_DVU0_2)
#define SCUXDVUER_DVU0_2 (SCUX.DVUER_DVU0_2)
#define SCUXDVUSR_DVU0_2 (SCUX.DVUSR_DVU0_2)
#define SCUXVEVMR_DVU0_2 (SCUX.VEVMR_DVU0_2)
#define SCUXVEVCR_DVU0_2 (SCUX.VEVCR_DVU0_2)
#define SCUXDVUIR_DVU0_3 (SCUX.DVUIR_DVU0_3)
#define SCUXVADIR_DVU0_3 (SCUX.VADIR_DVU0_3)
#define SCUXDVUBR_DVU0_3 (SCUX.DVUBR_DVU0_3)
#define SCUXDVUCR_DVU0_3 (SCUX.DVUCR_DVU0_3)
#define SCUXZCMCR_DVU0_3 (SCUX.ZCMCR_DVU0_3)
#define SCUXVRCTR_DVU0_3 (SCUX.VRCTR_DVU0_3)
#define SCUXVRPDR_DVU0_3 (SCUX.VRPDR_DVU0_3)
#define SCUXVRDBR_DVU0_3 (SCUX.VRDBR_DVU0_3)
#define SCUXVRWTR_DVU0_3 (SCUX.VRWTR_DVU0_3)
#define SCUXVOL0R_DVU0_3 (SCUX.VOL0R_DVU0_3)
#define SCUXVOL1R_DVU0_3 (SCUX.VOL1R_DVU0_3)
#define SCUXVOL2R_DVU0_3 (SCUX.VOL2R_DVU0_3)
#define SCUXVOL3R_DVU0_3 (SCUX.VOL3R_DVU0_3)
#define SCUXVOL4R_DVU0_3 (SCUX.VOL4R_DVU0_3)
#define SCUXVOL5R_DVU0_3 (SCUX.VOL5R_DVU0_3)
#define SCUXVOL6R_DVU0_3 (SCUX.VOL6R_DVU0_3)
#define SCUXVOL7R_DVU0_3 (SCUX.VOL7R_DVU0_3)
#define SCUXDVUER_DVU0_3 (SCUX.DVUER_DVU0_3)
#define SCUXDVUSR_DVU0_3 (SCUX.DVUSR_DVU0_3)
#define SCUXVEVMR_DVU0_3 (SCUX.VEVMR_DVU0_3)
#define SCUXVEVCR_DVU0_3 (SCUX.VEVCR_DVU0_3)
#define SCUXMIXIR_MIX0_0 (SCUX.MIXIR_MIX0_0)
#define SCUXMADIR_MIX0_0 (SCUX.MADIR_MIX0_0)
#define SCUXMIXBR_MIX0_0 (SCUX.MIXBR_MIX0_0)
#define SCUXMIXMR_MIX0_0 (SCUX.MIXMR_MIX0_0)
#define SCUXMVPDR_MIX0_0 (SCUX.MVPDR_MIX0_0)
#define SCUXMDBAR_MIX0_0 (SCUX.MDBAR_MIX0_0)
#define SCUXMDBBR_MIX0_0 (SCUX.MDBBR_MIX0_0)
#define SCUXMDBCR_MIX0_0 (SCUX.MDBCR_MIX0_0)
#define SCUXMDBDR_MIX0_0 (SCUX.MDBDR_MIX0_0)
#define SCUXMDBER_MIX0_0 (SCUX.MDBER_MIX0_0)
#define SCUXMIXSR_MIX0_0 (SCUX.MIXSR_MIX0_0)
#define SCUXSWRSR_CIM (SCUX.SWRSR_CIM)
#define SCUXDMACR_CIM (SCUX.DMACR_CIM)
#define SCUXDMATD0_CIM (SCUX.DMATD0_CIM.UINT32)
#define SCUXDMATD0_CIML (SCUX.DMATD0_CIM.UINT16[R_IO_L])
#define SCUXDMATD0_CIMH (SCUX.DMATD0_CIM.UINT16[R_IO_H])
#define SCUXDMATD1_CIM (SCUX.DMATD1_CIM.UINT32)
#define SCUXDMATD1_CIML (SCUX.DMATD1_CIM.UINT16[R_IO_L])
#define SCUXDMATD1_CIMH (SCUX.DMATD1_CIM.UINT16[R_IO_H])
#define SCUXDMATD2_CIM (SCUX.DMATD2_CIM.UINT32)
#define SCUXDMATD2_CIML (SCUX.DMATD2_CIM.UINT16[R_IO_L])
#define SCUXDMATD2_CIMH (SCUX.DMATD2_CIM.UINT16[R_IO_H])
#define SCUXDMATD3_CIM (SCUX.DMATD3_CIM.UINT32)
#define SCUXDMATD3_CIML (SCUX.DMATD3_CIM.UINT16[R_IO_L])
#define SCUXDMATD3_CIMH (SCUX.DMATD3_CIM.UINT16[R_IO_H])
#define SCUXDMATU0_CIM (SCUX.DMATU0_CIM.UINT32)
#define SCUXDMATU0_CIML (SCUX.DMATU0_CIM.UINT16[R_IO_L])
#define SCUXDMATU0_CIMH (SCUX.DMATU0_CIM.UINT16[R_IO_H])
#define SCUXDMATU1_CIM (SCUX.DMATU1_CIM.UINT32)
#define SCUXDMATU1_CIML (SCUX.DMATU1_CIM.UINT16[R_IO_L])
#define SCUXDMATU1_CIMH (SCUX.DMATU1_CIM.UINT16[R_IO_H])
#define SCUXDMATU2_CIM (SCUX.DMATU2_CIM.UINT32)
#define SCUXDMATU2_CIML (SCUX.DMATU2_CIM.UINT16[R_IO_L])
#define SCUXDMATU2_CIMH (SCUX.DMATU2_CIM.UINT16[R_IO_H])
#define SCUXDMATU3_CIM (SCUX.DMATU3_CIM.UINT32)
#define SCUXDMATU3_CIML (SCUX.DMATU3_CIM.UINT16[R_IO_L])
#define SCUXDMATU3_CIMH (SCUX.DMATU3_CIM.UINT16[R_IO_H])
#define SCUXSSIRSEL_CIM (SCUX.SSIRSEL_CIM)
#define SCUXFDTSEL0_CIM (SCUX.FDTSEL0_CIM)
#define SCUXFDTSEL1_CIM (SCUX.FDTSEL1_CIM)
#define SCUXFDTSEL2_CIM (SCUX.FDTSEL2_CIM)
#define SCUXFDTSEL3_CIM (SCUX.FDTSEL3_CIM)
#define SCUXFUTSEL0_CIM (SCUX.FUTSEL0_CIM)
#define SCUXFUTSEL1_CIM (SCUX.FUTSEL1_CIM)
#define SCUXFUTSEL2_CIM (SCUX.FUTSEL2_CIM)
#define SCUXFUTSEL3_CIM (SCUX.FUTSEL3_CIM)
#define SCUXSSIPMD_CIM (SCUX.SSIPMD_CIM)
#define SCUXSSICTRL_CIM (SCUX.SSICTRL_CIM)
#define SCUXSRCRSEL0_CIM (SCUX.SRCRSEL0_CIM)
#define SCUXSRCRSEL1_CIM (SCUX.SRCRSEL1_CIM)
#define SCUXSRCRSEL2_CIM (SCUX.SRCRSEL2_CIM)
#define SCUXSRCRSEL3_CIM (SCUX.SRCRSEL3_CIM)
#define SCUXMIXRSEL_CIM (SCUX.MIXRSEL_CIM)
#define SCUX_DMATDnCIM_COUNT (4)
#define SCUX_DMATUnCIM_COUNT (4)
#define SCUX_FDTSELnCIM_COUNT (4)
#define SCUX_FUTSELnCIM_COUNT (4)
#define SCUX_SRCRSELnCIM_COUNT (4)
typedef struct st_scux
{
/* SCUX */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
volatile uint8_t dummy259[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_1; /* IPCIR_IPC0_1 */
volatile uint32_t IPSLR_IPC0_1; /* IPSLR_IPC0_1 */
volatile uint8_t dummy260[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_2; /* IPCIR_IPC0_2 */
volatile uint32_t IPSLR_IPC0_2; /* IPSLR_IPC0_2 */
volatile uint8_t dummy261[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_ipcir_ipc0_n */
volatile uint32_t IPCIR_IPC0_3; /* IPCIR_IPC0_3 */
volatile uint32_t IPSLR_IPC0_3; /* IPSLR_IPC0_3 */
volatile uint8_t dummy262[248]; /* */
/* end of struct st_scux_from_ipcir_ipc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
volatile uint8_t dummy263[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_1; /* OPCIR_OPC0_1 */
volatile uint32_t OPSLR_OPC0_1; /* OPSLR_OPC0_1 */
volatile uint8_t dummy264[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_2; /* OPCIR_OPC0_2 */
volatile uint32_t OPSLR_OPC0_2; /* OPSLR_OPC0_2 */
volatile uint8_t dummy265[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_opcir_opc0_n */
volatile uint32_t OPCIR_OPC0_3; /* OPCIR_OPC0_3 */
volatile uint32_t OPSLR_OPC0_3; /* OPSLR_OPC0_3 */
volatile uint8_t dummy266[248]; /* */
/* end of struct st_scux_from_opcir_opc0_n */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
volatile uint8_t dummy267[4]; /* */
volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy268[224]; /* */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_1; /* FFDIR_FFD0_1 */
volatile uint32_t FDAIR_FFD0_1; /* FDAIR_FFD0_1 */
volatile uint32_t DRQSR_FFD0_1; /* DRQSR_FFD0_1 */
volatile uint32_t FFDPR_FFD0_1; /* FFDPR_FFD0_1 */
volatile uint32_t FFDBR_FFD0_1; /* FFDBR_FFD0_1 */
volatile uint32_t DEVMR_FFD0_1; /* DEVMR_FFD0_1 */
volatile uint8_t dummy269[4]; /* */
volatile uint32_t DEVCR_FFD0_1; /* DEVCR_FFD0_1 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy270[224]; /* */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_2; /* FFDIR_FFD0_2 */
volatile uint32_t FDAIR_FFD0_2; /* FDAIR_FFD0_2 */
volatile uint32_t DRQSR_FFD0_2; /* DRQSR_FFD0_2 */
volatile uint32_t FFDPR_FFD0_2; /* FFDPR_FFD0_2 */
volatile uint32_t FFDBR_FFD0_2; /* FFDBR_FFD0_2 */
volatile uint32_t DEVMR_FFD0_2; /* DEVMR_FFD0_2 */
volatile uint8_t dummy271[4]; /* */
volatile uint32_t DEVCR_FFD0_2; /* DEVCR_FFD0_2 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy272[224]; /* */
/* start of struct st_scux_from_ffdir_ffd0_n */
volatile uint32_t FFDIR_FFD0_3; /* FFDIR_FFD0_3 */
volatile uint32_t FDAIR_FFD0_3; /* FDAIR_FFD0_3 */
volatile uint32_t DRQSR_FFD0_3; /* DRQSR_FFD0_3 */
volatile uint32_t FFDPR_FFD0_3; /* FFDPR_FFD0_3 */
volatile uint32_t FFDBR_FFD0_3; /* FFDBR_FFD0_3 */
volatile uint32_t DEVMR_FFD0_3; /* DEVMR_FFD0_3 */
volatile uint8_t dummy273[4]; /* */
volatile uint32_t DEVCR_FFD0_3; /* DEVCR_FFD0_3 */
/* end of struct st_scux_from_ffdir_ffd0_n */
volatile uint8_t dummy274[224]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
volatile uint8_t dummy275[4]; /* */
volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy276[228]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_1; /* FFUIR_FFU0_1 */
volatile uint32_t FUAIR_FFU0_1; /* FUAIR_FFU0_1 */
volatile uint32_t URQSR_FFU0_1; /* URQSR_FFU0_1 */
volatile uint32_t FFUPR_FFU0_1; /* FFUPR_FFU0_1 */
volatile uint32_t UEVMR_FFU0_1; /* UEVMR_FFU0_1 */
volatile uint8_t dummy277[4]; /* */
volatile uint32_t UEVCR_FFU0_1; /* UEVCR_FFU0_1 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy278[228]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_2; /* FFUIR_FFU0_2 */
volatile uint32_t FUAIR_FFU0_2; /* FUAIR_FFU0_2 */
volatile uint32_t URQSR_FFU0_2; /* URQSR_FFU0_2 */
volatile uint32_t FFUPR_FFU0_2; /* FFUPR_FFU0_2 */
volatile uint32_t UEVMR_FFU0_2; /* UEVMR_FFU0_2 */
volatile uint8_t dummy279[4]; /* */
volatile uint32_t UEVCR_FFU0_2; /* UEVCR_FFU0_2 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy280[228]; /* */
/* start of struct st_scux_from_ffuir_ffu0_n */
volatile uint32_t FFUIR_FFU0_3; /* FFUIR_FFU0_3 */
volatile uint32_t FUAIR_FFU0_3; /* FUAIR_FFU0_3 */
volatile uint32_t URQSR_FFU0_3; /* URQSR_FFU0_3 */
volatile uint32_t FFUPR_FFU0_3; /* FFUPR_FFU0_3 */
volatile uint32_t UEVMR_FFU0_3; /* UEVMR_FFU0_3 */
volatile uint8_t dummy281[4]; /* */
volatile uint32_t UEVCR_FFU0_3; /* UEVCR_FFU0_3 */
/* end of struct st_scux_from_ffuir_ffu0_n */
volatile uint8_t dummy282[228]; /* */
/* start of struct st_scux_from_srcir0_2src0_n */
volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
volatile uint8_t dummy283[4]; /* */
volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
volatile uint8_t dummy284[4]; /* */
volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
/* end of struct st_scux_from_srcir0_2src0_n */
volatile uint8_t dummy285[148]; /* */
/* start of struct st_scux_from_srcir0_2src0_n */
volatile uint32_t SRCIR0_2SRC0_1; /* SRCIR0_2SRC0_1 */
volatile uint32_t SADIR0_2SRC0_1; /* SADIR0_2SRC0_1 */
volatile uint32_t SRCBR0_2SRC0_1; /* SRCBR0_2SRC0_1 */
volatile uint32_t IFSCR0_2SRC0_1; /* IFSCR0_2SRC0_1 */
volatile uint32_t IFSVR0_2SRC0_1; /* IFSVR0_2SRC0_1 */
volatile uint32_t SRCCR0_2SRC0_1; /* SRCCR0_2SRC0_1 */
volatile uint32_t MNFSR0_2SRC0_1; /* MNFSR0_2SRC0_1 */
volatile uint32_t BFSSR0_2SRC0_1; /* BFSSR0_2SRC0_1 */
volatile uint32_t SC2SR0_2SRC0_1; /* SC2SR0_2SRC0_1 */
volatile uint32_t WATSR0_2SRC0_1; /* WATSR0_2SRC0_1 */
volatile uint32_t SEVMR0_2SRC0_1; /* SEVMR0_2SRC0_1 */
volatile uint8_t dummy286[4]; /* */
volatile uint32_t SEVCR0_2SRC0_1; /* SEVCR0_2SRC0_1 */
volatile uint32_t SRCIR1_2SRC0_1; /* SRCIR1_2SRC0_1 */
volatile uint32_t SADIR1_2SRC0_1; /* SADIR1_2SRC0_1 */
volatile uint32_t SRCBR1_2SRC0_1; /* SRCBR1_2SRC0_1 */
volatile uint32_t IFSCR1_2SRC0_1; /* IFSCR1_2SRC0_1 */
volatile uint32_t IFSVR1_2SRC0_1; /* IFSVR1_2SRC0_1 */
volatile uint32_t SRCCR1_2SRC0_1; /* SRCCR1_2SRC0_1 */
volatile uint32_t MNFSR1_2SRC0_1; /* MNFSR1_2SRC0_1 */
volatile uint32_t BFSSR1_2SRC0_1; /* BFSSR1_2SRC0_1 */
volatile uint32_t SC2SR1_2SRC0_1; /* SC2SR1_2SRC0_1 */
volatile uint32_t WATSR1_2SRC0_1; /* WATSR1_2SRC0_1 */
volatile uint32_t SEVMR1_2SRC0_1; /* SEVMR1_2SRC0_1 */
volatile uint8_t dummy287[4]; /* */
volatile uint32_t SEVCR1_2SRC0_1; /* SEVCR1_2SRC0_1 */
volatile uint32_t SRCIRR_2SRC0_1; /* SRCIRR_2SRC0_1 */
/* end of struct st_scux_from_srcir0_2src0_n */
volatile uint8_t dummy288[148]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
volatile uint8_t dummy289[4]; /* */
volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy290[168]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_1; /* DVUIR_DVU0_1 */
volatile uint32_t VADIR_DVU0_1; /* VADIR_DVU0_1 */
volatile uint32_t DVUBR_DVU0_1; /* DVUBR_DVU0_1 */
volatile uint32_t DVUCR_DVU0_1; /* DVUCR_DVU0_1 */
volatile uint32_t ZCMCR_DVU0_1; /* ZCMCR_DVU0_1 */
volatile uint32_t VRCTR_DVU0_1; /* VRCTR_DVU0_1 */
volatile uint32_t VRPDR_DVU0_1; /* VRPDR_DVU0_1 */
volatile uint32_t VRDBR_DVU0_1; /* VRDBR_DVU0_1 */
volatile uint32_t VRWTR_DVU0_1; /* VRWTR_DVU0_1 */
volatile uint32_t VOL0R_DVU0_1; /* VOL0R_DVU0_1 */
volatile uint32_t VOL1R_DVU0_1; /* VOL1R_DVU0_1 */
volatile uint32_t VOL2R_DVU0_1; /* VOL2R_DVU0_1 */
volatile uint32_t VOL3R_DVU0_1; /* VOL3R_DVU0_1 */
volatile uint32_t VOL4R_DVU0_1; /* VOL4R_DVU0_1 */
volatile uint32_t VOL5R_DVU0_1; /* VOL5R_DVU0_1 */
volatile uint32_t VOL6R_DVU0_1; /* VOL6R_DVU0_1 */
volatile uint32_t VOL7R_DVU0_1; /* VOL7R_DVU0_1 */
volatile uint32_t DVUER_DVU0_1; /* DVUER_DVU0_1 */
volatile uint32_t DVUSR_DVU0_1; /* DVUSR_DVU0_1 */
volatile uint32_t VEVMR_DVU0_1; /* VEVMR_DVU0_1 */
volatile uint8_t dummy291[4]; /* */
volatile uint32_t VEVCR_DVU0_1; /* VEVCR_DVU0_1 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy292[168]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_2; /* DVUIR_DVU0_2 */
volatile uint32_t VADIR_DVU0_2; /* VADIR_DVU0_2 */
volatile uint32_t DVUBR_DVU0_2; /* DVUBR_DVU0_2 */
volatile uint32_t DVUCR_DVU0_2; /* DVUCR_DVU0_2 */
volatile uint32_t ZCMCR_DVU0_2; /* ZCMCR_DVU0_2 */
volatile uint32_t VRCTR_DVU0_2; /* VRCTR_DVU0_2 */
volatile uint32_t VRPDR_DVU0_2; /* VRPDR_DVU0_2 */
volatile uint32_t VRDBR_DVU0_2; /* VRDBR_DVU0_2 */
volatile uint32_t VRWTR_DVU0_2; /* VRWTR_DVU0_2 */
volatile uint32_t VOL0R_DVU0_2; /* VOL0R_DVU0_2 */
volatile uint32_t VOL1R_DVU0_2; /* VOL1R_DVU0_2 */
volatile uint32_t VOL2R_DVU0_2; /* VOL2R_DVU0_2 */
volatile uint32_t VOL3R_DVU0_2; /* VOL3R_DVU0_2 */
volatile uint32_t VOL4R_DVU0_2; /* VOL4R_DVU0_2 */
volatile uint32_t VOL5R_DVU0_2; /* VOL5R_DVU0_2 */
volatile uint32_t VOL6R_DVU0_2; /* VOL6R_DVU0_2 */
volatile uint32_t VOL7R_DVU0_2; /* VOL7R_DVU0_2 */
volatile uint32_t DVUER_DVU0_2; /* DVUER_DVU0_2 */
volatile uint32_t DVUSR_DVU0_2; /* DVUSR_DVU0_2 */
volatile uint32_t VEVMR_DVU0_2; /* VEVMR_DVU0_2 */
volatile uint8_t dummy293[4]; /* */
volatile uint32_t VEVCR_DVU0_2; /* VEVCR_DVU0_2 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy294[168]; /* */
/* start of struct st_scux_from_dvuir_dvu0_n */
volatile uint32_t DVUIR_DVU0_3; /* DVUIR_DVU0_3 */
volatile uint32_t VADIR_DVU0_3; /* VADIR_DVU0_3 */
volatile uint32_t DVUBR_DVU0_3; /* DVUBR_DVU0_3 */
volatile uint32_t DVUCR_DVU0_3; /* DVUCR_DVU0_3 */
volatile uint32_t ZCMCR_DVU0_3; /* ZCMCR_DVU0_3 */
volatile uint32_t VRCTR_DVU0_3; /* VRCTR_DVU0_3 */
volatile uint32_t VRPDR_DVU0_3; /* VRPDR_DVU0_3 */
volatile uint32_t VRDBR_DVU0_3; /* VRDBR_DVU0_3 */
volatile uint32_t VRWTR_DVU0_3; /* VRWTR_DVU0_3 */
volatile uint32_t VOL0R_DVU0_3; /* VOL0R_DVU0_3 */
volatile uint32_t VOL1R_DVU0_3; /* VOL1R_DVU0_3 */
volatile uint32_t VOL2R_DVU0_3; /* VOL2R_DVU0_3 */
volatile uint32_t VOL3R_DVU0_3; /* VOL3R_DVU0_3 */
volatile uint32_t VOL4R_DVU0_3; /* VOL4R_DVU0_3 */
volatile uint32_t VOL5R_DVU0_3; /* VOL5R_DVU0_3 */
volatile uint32_t VOL6R_DVU0_3; /* VOL6R_DVU0_3 */
volatile uint32_t VOL7R_DVU0_3; /* VOL7R_DVU0_3 */
volatile uint32_t DVUER_DVU0_3; /* DVUER_DVU0_3 */
volatile uint32_t DVUSR_DVU0_3; /* DVUSR_DVU0_3 */
volatile uint32_t VEVMR_DVU0_3; /* VEVMR_DVU0_3 */
volatile uint8_t dummy295[4]; /* */
volatile uint32_t VEVCR_DVU0_3; /* VEVCR_DVU0_3 */
/* end of struct st_scux_from_dvuir_dvu0_n */
volatile uint8_t dummy296[168]; /* */
volatile uint32_t MIXIR_MIX0_0; /* MIXIR_MIX0_0 */
volatile uint32_t MADIR_MIX0_0; /* MADIR_MIX0_0 */
volatile uint32_t MIXBR_MIX0_0; /* MIXBR_MIX0_0 */
volatile uint32_t MIXMR_MIX0_0; /* MIXMR_MIX0_0 */
volatile uint32_t MVPDR_MIX0_0; /* MVPDR_MIX0_0 */
volatile uint32_t MDBAR_MIX0_0; /* MDBAR_MIX0_0 */
volatile uint32_t MDBBR_MIX0_0; /* MDBBR_MIX0_0 */
volatile uint32_t MDBCR_MIX0_0; /* MDBCR_MIX0_0 */
volatile uint32_t MDBDR_MIX0_0; /* MDBDR_MIX0_0 */
volatile uint32_t MDBER_MIX0_0; /* MDBER_MIX0_0 */
volatile uint32_t MIXSR_MIX0_0; /* MIXSR_MIX0_0 */
volatile uint8_t dummy297[212]; /* */
volatile uint32_t SWRSR_CIM; /* SWRSR_CIM */
volatile uint32_t DMACR_CIM; /* DMACR_CIM */
/* #define SCUX_DMATDnCIM_COUNT (4) */
union iodefine_reg32_16_t DMATD0_CIM; /* DMATD0_CIM */
union iodefine_reg32_16_t DMATD1_CIM; /* DMATD1_CIM */
union iodefine_reg32_16_t DMATD2_CIM; /* DMATD2_CIM */
union iodefine_reg32_16_t DMATD3_CIM; /* DMATD3_CIM */
/* #define SCUX_DMATUnCIM_COUNT (4) */
union iodefine_reg32_16_t DMATU0_CIM; /* DMATU0_CIM */
union iodefine_reg32_16_t DMATU1_CIM; /* DMATU1_CIM */
union iodefine_reg32_16_t DMATU2_CIM; /* DMATU2_CIM */
union iodefine_reg32_16_t DMATU3_CIM; /* DMATU3_CIM */
volatile uint8_t dummy298[16]; /* */
volatile uint32_t SSIRSEL_CIM; /* SSIRSEL_CIM */
/* #define SCUX_FDTSELnCIM_COUNT (4) */
volatile uint32_t FDTSEL0_CIM; /* FDTSEL0_CIM */
volatile uint32_t FDTSEL1_CIM; /* FDTSEL1_CIM */
volatile uint32_t FDTSEL2_CIM; /* FDTSEL2_CIM */
volatile uint32_t FDTSEL3_CIM; /* FDTSEL3_CIM */
/* #define SCUX_FUTSELnCIM_COUNT (4) */
volatile uint32_t FUTSEL0_CIM; /* FUTSEL0_CIM */
volatile uint32_t FUTSEL1_CIM; /* FUTSEL1_CIM */
volatile uint32_t FUTSEL2_CIM; /* FUTSEL2_CIM */
volatile uint32_t FUTSEL3_CIM; /* FUTSEL3_CIM */
volatile uint32_t SSIPMD_CIM; /* SSIPMD_CIM */
volatile uint32_t SSICTRL_CIM; /* SSICTRL_CIM */
/* #define SCUX_SRCRSELnCIM_COUNT (4) */
volatile uint32_t SRCRSEL0_CIM; /* SRCRSEL0_CIM */
volatile uint32_t SRCRSEL1_CIM; /* SRCRSEL1_CIM */
volatile uint32_t SRCRSEL2_CIM; /* SRCRSEL2_CIM */
volatile uint32_t SRCRSEL3_CIM; /* SRCRSEL3_CIM */
volatile uint32_t MIXRSEL_CIM; /* MIXRSEL_CIM */
} r_io_scux_t;
typedef struct st_scux_from_ipcir_ipc0_n
{
volatile uint32_t IPCIR_IPC0_0; /* IPCIR_IPC0_0 */
volatile uint32_t IPSLR_IPC0_0; /* IPSLR_IPC0_0 */
volatile uint8_t dummy1[248]; /* */
} r_io_scux_from_ipcir_ipc0_n_t;
typedef struct st_scux_from_opcir_opc0_n
{
volatile uint32_t OPCIR_OPC0_0; /* OPCIR_OPC0_0 */
volatile uint32_t OPSLR_OPC0_0; /* OPSLR_OPC0_0 */
volatile uint8_t dummy1[248]; /* */
} r_io_scux_from_opcir_opc0_n_t;
typedef struct st_scux_from_ffdir_ffd0_n
{
volatile uint32_t FFDIR_FFD0_0; /* FFDIR_FFD0_0 */
volatile uint32_t FDAIR_FFD0_0; /* FDAIR_FFD0_0 */
volatile uint32_t DRQSR_FFD0_0; /* DRQSR_FFD0_0 */
volatile uint32_t FFDPR_FFD0_0; /* FFDPR_FFD0_0 */
volatile uint32_t FFDBR_FFD0_0; /* FFDBR_FFD0_0 */
volatile uint32_t DEVMR_FFD0_0; /* DEVMR_FFD0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t DEVCR_FFD0_0; /* DEVCR_FFD0_0 */
} r_io_scux_from_ffdir_ffd0_n_t;
typedef struct st_scux_from_ffuir_ffu0_n
{
volatile uint32_t FFUIR_FFU0_0; /* FFUIR_FFU0_0 */
volatile uint32_t FUAIR_FFU0_0; /* FUAIR_FFU0_0 */
volatile uint32_t URQSR_FFU0_0; /* URQSR_FFU0_0 */
volatile uint32_t FFUPR_FFU0_0; /* FFUPR_FFU0_0 */
volatile uint32_t UEVMR_FFU0_0; /* UEVMR_FFU0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t UEVCR_FFU0_0; /* UEVCR_FFU0_0 */
} r_io_scux_from_ffuir_ffu0_n_t;
typedef struct st_scux_from_srcir0_2src0_n
{
volatile uint32_t SRCIR0_2SRC0_0; /* SRCIR0_2SRC0_0 */
volatile uint32_t SADIR0_2SRC0_0; /* SADIR0_2SRC0_0 */
volatile uint32_t SRCBR0_2SRC0_0; /* SRCBR0_2SRC0_0 */
volatile uint32_t IFSCR0_2SRC0_0; /* IFSCR0_2SRC0_0 */
volatile uint32_t IFSVR0_2SRC0_0; /* IFSVR0_2SRC0_0 */
volatile uint32_t SRCCR0_2SRC0_0; /* SRCCR0_2SRC0_0 */
volatile uint32_t MNFSR0_2SRC0_0; /* MNFSR0_2SRC0_0 */
volatile uint32_t BFSSR0_2SRC0_0; /* BFSSR0_2SRC0_0 */
volatile uint32_t SC2SR0_2SRC0_0; /* SC2SR0_2SRC0_0 */
volatile uint32_t WATSR0_2SRC0_0; /* WATSR0_2SRC0_0 */
volatile uint32_t SEVMR0_2SRC0_0; /* SEVMR0_2SRC0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t SEVCR0_2SRC0_0; /* SEVCR0_2SRC0_0 */
volatile uint32_t SRCIR1_2SRC0_0; /* SRCIR1_2SRC0_0 */
volatile uint32_t SADIR1_2SRC0_0; /* SADIR1_2SRC0_0 */
volatile uint32_t SRCBR1_2SRC0_0; /* SRCBR1_2SRC0_0 */
volatile uint32_t IFSCR1_2SRC0_0; /* IFSCR1_2SRC0_0 */
volatile uint32_t IFSVR1_2SRC0_0; /* IFSVR1_2SRC0_0 */
volatile uint32_t SRCCR1_2SRC0_0; /* SRCCR1_2SRC0_0 */
volatile uint32_t MNFSR1_2SRC0_0; /* MNFSR1_2SRC0_0 */
volatile uint32_t BFSSR1_2SRC0_0; /* BFSSR1_2SRC0_0 */
volatile uint32_t SC2SR1_2SRC0_0; /* SC2SR1_2SRC0_0 */
volatile uint32_t WATSR1_2SRC0_0; /* WATSR1_2SRC0_0 */
volatile uint32_t SEVMR1_2SRC0_0; /* SEVMR1_2SRC0_0 */
volatile uint8_t dummy2[4]; /* */
volatile uint32_t SEVCR1_2SRC0_0; /* SEVCR1_2SRC0_0 */
volatile uint32_t SRCIRR_2SRC0_0; /* SRCIRR_2SRC0_0 */
} r_io_scux_from_srcir0_2src0_n_t;
typedef struct st_scux_from_dvuir_dvu0_n
{
volatile uint32_t DVUIR_DVU0_0; /* DVUIR_DVU0_0 */
volatile uint32_t VADIR_DVU0_0; /* VADIR_DVU0_0 */
volatile uint32_t DVUBR_DVU0_0; /* DVUBR_DVU0_0 */
volatile uint32_t DVUCR_DVU0_0; /* DVUCR_DVU0_0 */
volatile uint32_t ZCMCR_DVU0_0; /* ZCMCR_DVU0_0 */
volatile uint32_t VRCTR_DVU0_0; /* VRCTR_DVU0_0 */
volatile uint32_t VRPDR_DVU0_0; /* VRPDR_DVU0_0 */
volatile uint32_t VRDBR_DVU0_0; /* VRDBR_DVU0_0 */
volatile uint32_t VRWTR_DVU0_0; /* VRWTR_DVU0_0 */
volatile uint32_t VOL0R_DVU0_0; /* VOL0R_DVU0_0 */
volatile uint32_t VOL1R_DVU0_0; /* VOL1R_DVU0_0 */
volatile uint32_t VOL2R_DVU0_0; /* VOL2R_DVU0_0 */
volatile uint32_t VOL3R_DVU0_0; /* VOL3R_DVU0_0 */
volatile uint32_t VOL4R_DVU0_0; /* VOL4R_DVU0_0 */
volatile uint32_t VOL5R_DVU0_0; /* VOL5R_DVU0_0 */
volatile uint32_t VOL6R_DVU0_0; /* VOL6R_DVU0_0 */
volatile uint32_t VOL7R_DVU0_0; /* VOL7R_DVU0_0 */
volatile uint32_t DVUER_DVU0_0; /* DVUER_DVU0_0 */
volatile uint32_t DVUSR_DVU0_0; /* DVUSR_DVU0_0 */
volatile uint32_t VEVMR_DVU0_0; /* VEVMR_DVU0_0 */
volatile uint8_t dummy1[4]; /* */
volatile uint32_t VEVCR_DVU0_0; /* VEVCR_DVU0_0 */
} r_io_scux_from_dvuir_dvu0_n_t;
/* Channel array defines of SCUX (2)*/
#ifdef DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS
volatile struct st_scux_from_dvuir_dvu0_n* SCUX_FROM_DVUIR_DVU0_0_ARRAY[ SCUX_FROM_DVUIR_DVU0_0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCUX_FROM_DVUIR_DVU0_0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCUX_FROM_DVUIR_DVU0_0_ARRAY_CHANNELS */
#ifdef DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS
volatile struct st_scux_from_srcir0_2src0_n* SCUX_FROM_SRCIR0_2SRC0_0_ARRAY[ SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCUX_FROM_SRCIR0_2SRC0_0_ARRAY_CHANNELS */
#ifdef DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS
volatile struct st_scux_from_ffuir_ffu0_n* SCUX_FROM_FFUIR_FFU0_0_ARRAY[ SCUX_FROM_FFUIR_FFU0_0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCUX_FROM_FFUIR_FFU0_0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCUX_FROM_FFUIR_FFU0_0_ARRAY_CHANNELS */
#ifdef DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS
volatile struct st_scux_from_ffdir_ffd0_n* SCUX_FROM_FFDIR_FFD0_0_ARRAY[ SCUX_FROM_FFDIR_FFD0_0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCUX_FROM_FFDIR_FFD0_0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCUX_FROM_FFDIR_FFD0_0_ARRAY_CHANNELS */
#ifdef DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS
volatile struct st_scux_from_opcir_opc0_n* SCUX_FROM_OPCIR_OPC0_0_ARRAY[ SCUX_FROM_OPCIR_OPC0_0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCUX_FROM_OPCIR_OPC0_0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCUX_FROM_OPCIR_OPC0_0_ARRAY_CHANNELS */
#ifdef DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS
volatile struct st_scux_from_ipcir_ipc0_n* SCUX_FROM_IPCIR_IPC0_0_ARRAY[ SCUX_FROM_IPCIR_IPC0_0_ARRAY_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SCUX_FROM_IPCIR_IPC0_0_ARRAY_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SCUX_FROM_IPCIR_IPC0_0_ARRAY_CHANNELS */
/* End of channel array defines of SCUX (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : sdg_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SDG_IODEFINE_H
#define SDG_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SDG0 (*(struct st_sdg *)0xFCFF4800uL) /* SDG0 */
#define SDG1 (*(struct st_sdg *)0xFCFF4A00uL) /* SDG1 */
#define SDG2 (*(struct st_sdg *)0xFCFF4C00uL) /* SDG2 */
#define SDG3 (*(struct st_sdg *)0xFCFF4E00uL) /* SDG3 */
/* Start of channel array defines of SDG */
/* Channel array defines of SDG */
/*(Sample) value = SDG[ channel ]->SGCR1; */
#define SDG_COUNT (4)
#define SDG_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SDG0, &SDG1, &SDG2, &SDG3 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SDG */
#define SGCR1_0 (SDG0.SGCR1)
#define SGCSR_0 (SDG0.SGCSR)
#define SGCR2_0 (SDG0.SGCR2)
#define SGLR_0 (SDG0.SGLR)
#define SGTFR_0 (SDG0.SGTFR)
#define SGSFR_0 (SDG0.SGSFR)
#define SGCR1_1 (SDG1.SGCR1)
#define SGCSR_1 (SDG1.SGCSR)
#define SGCR2_1 (SDG1.SGCR2)
#define SGLR_1 (SDG1.SGLR)
#define SGTFR_1 (SDG1.SGTFR)
#define SGSFR_1 (SDG1.SGSFR)
#define SGCR1_2 (SDG2.SGCR1)
#define SGCSR_2 (SDG2.SGCSR)
#define SGCR2_2 (SDG2.SGCR2)
#define SGLR_2 (SDG2.SGLR)
#define SGTFR_2 (SDG2.SGTFR)
#define SGSFR_2 (SDG2.SGSFR)
#define SGCR1_3 (SDG3.SGCR1)
#define SGCSR_3 (SDG3.SGCSR)
#define SGCR2_3 (SDG3.SGCR2)
#define SGLR_3 (SDG3.SGLR)
#define SGTFR_3 (SDG3.SGTFR)
#define SGSFR_3 (SDG3.SGSFR)
typedef struct st_sdg
{
/* SDG */
volatile uint8_t SGCR1; /* SGCR1 */
volatile uint8_t SGCSR; /* SGCSR */
volatile uint8_t SGCR2; /* SGCR2 */
volatile uint8_t SGLR; /* SGLR */
volatile uint8_t SGTFR; /* SGTFR */
volatile uint8_t SGSFR; /* SGSFR */
} r_io_sdg_t;
/* Channel array defines of SDG (2)*/
#ifdef DECLARE_SDG_CHANNELS
volatile struct st_sdg* SDG[ SDG_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SDG_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SDG_CHANNELS */
/* End of channel array defines of SDG (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,79 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spdif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SPDIF_IODEFINE_H
#define SPDIF_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SPDIF (*(struct st_spdif *)0xE8012000uL) /* SPDIF */
#define SPDIFTLCA (SPDIF.TLCA)
#define SPDIFTRCA (SPDIF.TRCA)
#define SPDIFTLCS (SPDIF.TLCS)
#define SPDIFTRCS (SPDIF.TRCS)
#define SPDIFTUI (SPDIF.TUI)
#define SPDIFRLCA (SPDIF.RLCA)
#define SPDIFRRCA (SPDIF.RRCA)
#define SPDIFRLCS (SPDIF.RLCS)
#define SPDIFRRCS (SPDIF.RRCS)
#define SPDIFRUI (SPDIF.RUI)
#define SPDIFCTRL (SPDIF.CTRL)
#define SPDIFSTAT (SPDIF.STAT)
#define SPDIFTDAD (SPDIF.TDAD)
#define SPDIFRDAD (SPDIF.RDAD)
typedef struct st_spdif
{
/* SPDIF */
volatile uint32_t TLCA; /* TLCA */
volatile uint32_t TRCA; /* TRCA */
volatile uint32_t TLCS; /* TLCS */
volatile uint32_t TRCS; /* TRCS */
volatile uint32_t TUI; /* TUI */
volatile uint32_t RLCA; /* RLCA */
volatile uint32_t RRCA; /* RRCA */
volatile uint32_t RLCS; /* RLCS */
volatile uint32_t RRCS; /* RRCS */
volatile uint32_t RUI; /* RUI */
volatile uint32_t CTRL; /* CTRL */
volatile uint32_t STAT; /* STAT */
volatile uint32_t TDAD; /* TDAD */
volatile uint32_t RDAD; /* RDAD */
} r_io_spdif_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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@ -1,199 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : spibsc_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SPIBSC_IODEFINE_H
#define SPIBSC_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SPIBSC0 (*(struct st_spibsc *)0x3FEFA000uL) /* SPIBSC0 */
#define SPIBSC1 (*(struct st_spibsc *)0x3FEFB000uL) /* SPIBSC1 */
/* Start of channel array defines of SPIBSC */
/* Channel array defines of SPIBSC */
/*(Sample) value = SPIBSC[ channel ]->CMNCR; */
#define SPIBSC_COUNT (2)
#define SPIBSC_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SPIBSC0, &SPIBSC1 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SPIBSC */
#define CMNCR_0 (SPIBSC0.CMNCR)
#define SSLDR_0 (SPIBSC0.SSLDR)
#define SPBCR_0 (SPIBSC0.SPBCR)
#define DRCR_0 (SPIBSC0.DRCR)
#define DRCMR_0 (SPIBSC0.DRCMR)
#define DREAR_0 (SPIBSC0.DREAR)
#define DROPR_0 (SPIBSC0.DROPR)
#define DRENR_0 (SPIBSC0.DRENR)
#define SMCR_0 (SPIBSC0.SMCR)
#define SMCMR_0 (SPIBSC0.SMCMR)
#define SMADR_0 (SPIBSC0.SMADR)
#define SMOPR_0 (SPIBSC0.SMOPR)
#define SMENR_0 (SPIBSC0.SMENR)
#define SMRDR0_0 (SPIBSC0.SMRDR0.UINT32)
#define SMRDR0_0L (SPIBSC0.SMRDR0.UINT16[R_IO_L])
#define SMRDR0_0H (SPIBSC0.SMRDR0.UINT16[R_IO_H])
#define SMRDR0_0LL (SPIBSC0.SMRDR0.UINT8[R_IO_LL])
#define SMRDR0_0LH (SPIBSC0.SMRDR0.UINT8[R_IO_LH])
#define SMRDR0_0HL (SPIBSC0.SMRDR0.UINT8[R_IO_HL])
#define SMRDR0_0HH (SPIBSC0.SMRDR0.UINT8[R_IO_HH])
#define SMRDR1_0 (SPIBSC0.SMRDR1.UINT32)
#define SMRDR1_0L (SPIBSC0.SMRDR1.UINT16[R_IO_L])
#define SMRDR1_0H (SPIBSC0.SMRDR1.UINT16[R_IO_H])
#define SMRDR1_0LL (SPIBSC0.SMRDR1.UINT8[R_IO_LL])
#define SMRDR1_0LH (SPIBSC0.SMRDR1.UINT8[R_IO_LH])
#define SMRDR1_0HL (SPIBSC0.SMRDR1.UINT8[R_IO_HL])
#define SMRDR1_0HH (SPIBSC0.SMRDR1.UINT8[R_IO_HH])
#define SMWDR0_0 (SPIBSC0.SMWDR0.UINT32)
#define SMWDR0_0L (SPIBSC0.SMWDR0.UINT16[R_IO_L])
#define SMWDR0_0H (SPIBSC0.SMWDR0.UINT16[R_IO_H])
#define SMWDR0_0LL (SPIBSC0.SMWDR0.UINT8[R_IO_LL])
#define SMWDR0_0LH (SPIBSC0.SMWDR0.UINT8[R_IO_LH])
#define SMWDR0_0HL (SPIBSC0.SMWDR0.UINT8[R_IO_HL])
#define SMWDR0_0HH (SPIBSC0.SMWDR0.UINT8[R_IO_HH])
#define SMWDR1_0 (SPIBSC0.SMWDR1.UINT32)
#define SMWDR1_0L (SPIBSC0.SMWDR1.UINT16[R_IO_L])
#define SMWDR1_0H (SPIBSC0.SMWDR1.UINT16[R_IO_H])
#define SMWDR1_0LL (SPIBSC0.SMWDR1.UINT8[R_IO_LL])
#define SMWDR1_0LH (SPIBSC0.SMWDR1.UINT8[R_IO_LH])
#define SMWDR1_0HL (SPIBSC0.SMWDR1.UINT8[R_IO_HL])
#define SMWDR1_0HH (SPIBSC0.SMWDR1.UINT8[R_IO_HH])
#define CMNSR_0 (SPIBSC0.CMNSR)
#define CKDLY_0 (SPIBSC0.CKDLY)
#define DRDMCR_0 (SPIBSC0.DRDMCR)
#define DRDRENR_0 (SPIBSC0.DRDRENR)
#define SMDMCR_0 (SPIBSC0.SMDMCR)
#define SMDRENR_0 (SPIBSC0.SMDRENR)
#define SPODLY_0 (SPIBSC0.SPODLY)
#define CMNCR_1 (SPIBSC1.CMNCR)
#define SSLDR_1 (SPIBSC1.SSLDR)
#define SPBCR_1 (SPIBSC1.SPBCR)
#define DRCR_1 (SPIBSC1.DRCR)
#define DRCMR_1 (SPIBSC1.DRCMR)
#define DREAR_1 (SPIBSC1.DREAR)
#define DROPR_1 (SPIBSC1.DROPR)
#define DRENR_1 (SPIBSC1.DRENR)
#define SMCR_1 (SPIBSC1.SMCR)
#define SMCMR_1 (SPIBSC1.SMCMR)
#define SMADR_1 (SPIBSC1.SMADR)
#define SMOPR_1 (SPIBSC1.SMOPR)
#define SMENR_1 (SPIBSC1.SMENR)
#define SMRDR0_1 (SPIBSC1.SMRDR0.UINT32)
#define SMRDR0_1L (SPIBSC1.SMRDR0.UINT16[R_IO_L])
#define SMRDR0_1H (SPIBSC1.SMRDR0.UINT16[R_IO_H])
#define SMRDR0_1LL (SPIBSC1.SMRDR0.UINT8[R_IO_LL])
#define SMRDR0_1LH (SPIBSC1.SMRDR0.UINT8[R_IO_LH])
#define SMRDR0_1HL (SPIBSC1.SMRDR0.UINT8[R_IO_HL])
#define SMRDR0_1HH (SPIBSC1.SMRDR0.UINT8[R_IO_HH])
#define SMRDR1_1 (SPIBSC1.SMRDR1.UINT32)
#define SMRDR1_1L (SPIBSC1.SMRDR1.UINT16[R_IO_L])
#define SMRDR1_1H (SPIBSC1.SMRDR1.UINT16[R_IO_H])
#define SMRDR1_1LL (SPIBSC1.SMRDR1.UINT8[R_IO_LL])
#define SMRDR1_1LH (SPIBSC1.SMRDR1.UINT8[R_IO_LH])
#define SMRDR1_1HL (SPIBSC1.SMRDR1.UINT8[R_IO_HL])
#define SMRDR1_1HH (SPIBSC1.SMRDR1.UINT8[R_IO_HH])
#define SMWDR0_1 (SPIBSC1.SMWDR0.UINT32)
#define SMWDR0_1L (SPIBSC1.SMWDR0.UINT16[R_IO_L])
#define SMWDR0_1H (SPIBSC1.SMWDR0.UINT16[R_IO_H])
#define SMWDR0_1LL (SPIBSC1.SMWDR0.UINT8[R_IO_LL])
#define SMWDR0_1LH (SPIBSC1.SMWDR0.UINT8[R_IO_LH])
#define SMWDR0_1HL (SPIBSC1.SMWDR0.UINT8[R_IO_HL])
#define SMWDR0_1HH (SPIBSC1.SMWDR0.UINT8[R_IO_HH])
#define SMWDR1_1 (SPIBSC1.SMWDR1.UINT32)
#define SMWDR1_1L (SPIBSC1.SMWDR1.UINT16[R_IO_L])
#define SMWDR1_1H (SPIBSC1.SMWDR1.UINT16[R_IO_H])
#define SMWDR1_1LL (SPIBSC1.SMWDR1.UINT8[R_IO_LL])
#define SMWDR1_1LH (SPIBSC1.SMWDR1.UINT8[R_IO_LH])
#define SMWDR1_1HL (SPIBSC1.SMWDR1.UINT8[R_IO_HL])
#define SMWDR1_1HH (SPIBSC1.SMWDR1.UINT8[R_IO_HH])
#define CMNSR_1 (SPIBSC1.CMNSR)
#define CKDLY_1 (SPIBSC1.CKDLY)
#define DRDMCR_1 (SPIBSC1.DRDMCR)
#define DRDRENR_1 (SPIBSC1.DRDRENR)
#define SMDMCR_1 (SPIBSC1.SMDMCR)
#define SMDRENR_1 (SPIBSC1.SMDRENR)
#define SPODLY_1 (SPIBSC1.SPODLY)
typedef struct st_spibsc
{
/* SPIBSC */
volatile uint32_t CMNCR; /* CMNCR */
volatile uint32_t SSLDR; /* SSLDR */
volatile uint32_t SPBCR; /* SPBCR */
volatile uint32_t DRCR; /* DRCR */
volatile uint32_t DRCMR; /* DRCMR */
volatile uint32_t DREAR; /* DREAR */
volatile uint32_t DROPR; /* DROPR */
volatile uint32_t DRENR; /* DRENR */
volatile uint32_t SMCR; /* SMCR */
volatile uint32_t SMCMR; /* SMCMR */
volatile uint32_t SMADR; /* SMADR */
volatile uint32_t SMOPR; /* SMOPR */
volatile uint32_t SMENR; /* SMENR */
volatile uint8_t dummy1[4]; /* */
union iodefine_reg32_t SMRDR0; /* SMRDR0 */
union iodefine_reg32_t SMRDR1; /* SMRDR1 */
union iodefine_reg32_t SMWDR0; /* SMWDR0 */
union iodefine_reg32_t SMWDR1; /* SMWDR1 */
volatile uint32_t CMNSR; /* CMNSR */
volatile uint8_t dummy2[4]; /* */
volatile uint32_t CKDLY; /* CKDLY */
volatile uint8_t dummy3[4]; /* */
volatile uint32_t DRDMCR; /* DRDMCR */
volatile uint32_t DRDRENR; /* DRDRENR */
volatile uint32_t SMDMCR; /* SMDMCR */
volatile uint32_t SMDRENR; /* SMDRENR */
volatile uint32_t SPODLY; /* SPODLY */
} r_io_spibsc_t;
/* Channel array defines of SPIBSC (2)*/
#ifdef DECLARE_SPIBSC_CHANNELS
volatile struct st_spibsc* SPIBSC[ SPIBSC_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SPIBSC_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SPIBSC_CHANNELS */
/* End of channel array defines of SPIBSC (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : ssif_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef SSIF_IODEFINE_H
#define SSIF_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */
#define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */
#define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */
#define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */
#define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */
#define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */
/* Start of channel array defines of SSIF */
/* Channel array defines of SSIF */
/*(Sample) value = SSIF[ channel ]->SSICR; */
#define SSIF_COUNT (6)
#define SSIF_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* End of channel array defines of SSIF */
#define SSICR_0 (SSIF0.SSICR)
#define SSISR_0 (SSIF0.SSISR)
#define SSIFCR_0 (SSIF0.SSIFCR)
#define SSIFSR_0 (SSIF0.SSIFSR)
#define SSIFTDR_0 (SSIF0.SSIFTDR)
#define SSIFRDR_0 (SSIF0.SSIFRDR)
#define SSITDMR_0 (SSIF0.SSITDMR)
#define SSIFCCR_0 (SSIF0.SSIFCCR)
#define SSIFCMR_0 (SSIF0.SSIFCMR)
#define SSIFCSR_0 (SSIF0.SSIFCSR)
#define SSICR_1 (SSIF1.SSICR)
#define SSISR_1 (SSIF1.SSISR)
#define SSIFCR_1 (SSIF1.SSIFCR)
#define SSIFSR_1 (SSIF1.SSIFSR)
#define SSIFTDR_1 (SSIF1.SSIFTDR)
#define SSIFRDR_1 (SSIF1.SSIFRDR)
#define SSITDMR_1 (SSIF1.SSITDMR)
#define SSIFCCR_1 (SSIF1.SSIFCCR)
#define SSIFCMR_1 (SSIF1.SSIFCMR)
#define SSIFCSR_1 (SSIF1.SSIFCSR)
#define SSICR_2 (SSIF2.SSICR)
#define SSISR_2 (SSIF2.SSISR)
#define SSIFCR_2 (SSIF2.SSIFCR)
#define SSIFSR_2 (SSIF2.SSIFSR)
#define SSIFTDR_2 (SSIF2.SSIFTDR)
#define SSIFRDR_2 (SSIF2.SSIFRDR)
#define SSITDMR_2 (SSIF2.SSITDMR)
#define SSIFCCR_2 (SSIF2.SSIFCCR)
#define SSIFCMR_2 (SSIF2.SSIFCMR)
#define SSIFCSR_2 (SSIF2.SSIFCSR)
#define SSICR_3 (SSIF3.SSICR)
#define SSISR_3 (SSIF3.SSISR)
#define SSIFCR_3 (SSIF3.SSIFCR)
#define SSIFSR_3 (SSIF3.SSIFSR)
#define SSIFTDR_3 (SSIF3.SSIFTDR)
#define SSIFRDR_3 (SSIF3.SSIFRDR)
#define SSITDMR_3 (SSIF3.SSITDMR)
#define SSIFCCR_3 (SSIF3.SSIFCCR)
#define SSIFCMR_3 (SSIF3.SSIFCMR)
#define SSIFCSR_3 (SSIF3.SSIFCSR)
#define SSICR_4 (SSIF4.SSICR)
#define SSISR_4 (SSIF4.SSISR)
#define SSIFCR_4 (SSIF4.SSIFCR)
#define SSIFSR_4 (SSIF4.SSIFSR)
#define SSIFTDR_4 (SSIF4.SSIFTDR)
#define SSIFRDR_4 (SSIF4.SSIFRDR)
#define SSITDMR_4 (SSIF4.SSITDMR)
#define SSIFCCR_4 (SSIF4.SSIFCCR)
#define SSIFCMR_4 (SSIF4.SSIFCMR)
#define SSIFCSR_4 (SSIF4.SSIFCSR)
#define SSICR_5 (SSIF5.SSICR)
#define SSISR_5 (SSIF5.SSISR)
#define SSIFCR_5 (SSIF5.SSIFCR)
#define SSIFSR_5 (SSIF5.SSIFSR)
#define SSIFTDR_5 (SSIF5.SSIFTDR)
#define SSIFRDR_5 (SSIF5.SSIFRDR)
#define SSITDMR_5 (SSIF5.SSITDMR)
#define SSIFCCR_5 (SSIF5.SSIFCCR)
#define SSIFCMR_5 (SSIF5.SSIFCMR)
#define SSIFCSR_5 (SSIF5.SSIFCSR)
typedef struct st_ssif
{
/* SSIF */
volatile uint32_t SSICR; /* SSICR */
volatile uint32_t SSISR; /* SSISR */
volatile uint8_t dummy1[8]; /* */
volatile uint32_t SSIFCR; /* SSIFCR */
volatile uint32_t SSIFSR; /* SSIFSR */
volatile uint32_t SSIFTDR; /* SSIFTDR */
volatile uint32_t SSIFRDR; /* SSIFRDR */
volatile uint32_t SSITDMR; /* SSITDMR */
volatile uint32_t SSIFCCR; /* SSIFCCR */
volatile uint32_t SSIFCMR; /* SSIFCMR */
volatile uint32_t SSIFCSR; /* SSIFCSR */
} r_io_ssif_t;
/* Channel array defines of SSIF (2)*/
#ifdef DECLARE_SSIF_CHANNELS
volatile struct st_ssif* SSIF[ SSIF_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
SSIF_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_SSIF_CHANNELS */
/* End of channel array defines of SSIF (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : usb20_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef USB20_IODEFINE_H
#define USB20_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define USB200 (*(struct st_usb20 *)0xE8010000uL) /* USB200 */
#define USB201 (*(struct st_usb20 *)0xE8207000uL) /* USB201 */
/* Start of channel array defines of USB20 */
/* Channel array defines of USB20 */
/*(Sample) value = USB20[ channel ]->SYSCFG0; */
#define USB20_COUNT (2)
#define USB20_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
&USB200, &USB201 \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
/* Channel array defines of USB20_FROM_D0FIFOB0 */
/*(Sample) value = USB20_FROM_D0FIFOB0[ channel ][ index ]->D0FIFOB0; */
#define USB20_FROM_D0FIFOB0_COUNT (2)
#define USB20_FROM_D0FIFOB0_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOB0, &USB200_FROM_D1FIFOB0 },{ \
&USB201_FROM_D0FIFOB0, &USB201_FROM_D1FIFOB0 \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D0FIFOB0) /* USB200_FROM_D0FIFOB0 */
#define USB200_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB200.D1FIFOB0) /* USB200_FROM_D1FIFOB0 */
#define USB201_FROM_D0FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D0FIFOB0) /* USB201_FROM_D0FIFOB0 */
#define USB201_FROM_D1FIFOB0 (*(struct st_usb20_from_dmfifob0 *)&USB201.D1FIFOB0) /* USB201_FROM_D1FIFOB0 */
/* Channel array defines of USB20_FROM_PIPE1ATRE */
/*(Sample) value = USB20_FROM_PIPE1ATRE[ channel ][ index ]->PIPE1TRE; */
#define USB20_FROM_PIPE1ATRE_COUNT (5)
#define USB20_FROM_PIPE1ATRE_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_PIPE1TRE, &USB200_FROM_PIPE2TRE, &USB200_FROM_PIPE3TRE, &USB200_FROM_PIPE4TRE, &USB200_FROM_PIPE5TRE },{ \
&USB201_FROM_PIPE1TRE, &USB201_FROM_PIPE2TRE, &USB201_FROM_PIPE3TRE, &USB201_FROM_PIPE4TRE, &USB201_FROM_PIPE5TRE \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE1TRE) /* USB200_FROM_PIPE1TRE */
#define USB200_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE2TRE) /* USB200_FROM_PIPE2TRE */
#define USB200_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE3TRE) /* USB200_FROM_PIPE3TRE */
#define USB200_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE4TRE) /* USB200_FROM_PIPE4TRE */
#define USB200_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB200.PIPE5TRE) /* USB200_FROM_PIPE5TRE */
#define USB201_FROM_PIPE1TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE1TRE) /* USB201_FROM_PIPE1TRE */
#define USB201_FROM_PIPE2TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE2TRE) /* USB201_FROM_PIPE2TRE */
#define USB201_FROM_PIPE3TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE3TRE) /* USB201_FROM_PIPE3TRE */
#define USB201_FROM_PIPE4TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE4TRE) /* USB201_FROM_PIPE4TRE */
#define USB201_FROM_PIPE5TRE (*(struct st_usb20_from_pipe1tre *)&USB201.PIPE5TRE) /* USB201_FROM_PIPE5TRE */
/* Channel array defines of USB20_FROM_D0FIFOSEL */
/*(Sample) value = USB20_FROM_D0FIFOSEL[ channel ][ index ]->D0FIFOSEL; */
#define USB20_FROM_D0FIFOSEL_COUNT (2)
#define USB20_FROM_D0FIFOSEL_ADDRESS_LIST \
{ /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \
{ \
&USB200_FROM_D0FIFOSEL, &USB200_FROM_D1FIFOSEL },{ \
&USB201_FROM_D0FIFOSEL, &USB201_FROM_D1FIFOSEL \
} \
} /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */
#define USB200_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D0FIFOSEL) /* USB200_FROM_D0FIFOSEL */
#define USB200_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB200.D1FIFOSEL) /* USB200_FROM_D1FIFOSEL */
#define USB201_FROM_D0FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D0FIFOSEL) /* USB201_FROM_D0FIFOSEL */
#define USB201_FROM_D1FIFOSEL (*(struct st_usb20_from_d0fifosel *)&USB201.D1FIFOSEL) /* USB201_FROM_D1FIFOSEL */
/* End of channel array defines of USB20 */
#define SYSCFG0_0 (USB200.SYSCFG0)
#define BUSWAIT_0 (USB200.BUSWAIT)
#define SYSSTS0_0 (USB200.SYSSTS0)
#define DVSTCTR0_0 (USB200.DVSTCTR0)
#define TESTMODE_0 (USB200.TESTMODE)
#define D0FBCFG_0 (USB200.D0FBCFG)
#define D1FBCFG_0 (USB200.D1FBCFG)
#define CFIFO_0 (USB200.CFIFO.UINT32)
#define CFIFO_0L (USB200.CFIFO.UINT16[R_IO_L])
#define CFIFO_0H (USB200.CFIFO.UINT16[R_IO_H])
#define CFIFO_0LL (USB200.CFIFO.UINT8[R_IO_LL])
#define CFIFO_0LH (USB200.CFIFO.UINT8[R_IO_LH])
#define CFIFO_0HL (USB200.CFIFO.UINT8[R_IO_HL])
#define CFIFO_0HH (USB200.CFIFO.UINT8[R_IO_HH])
#define D0FIFO_0 (USB200.D0FIFO.UINT32)
#define D0FIFO_0L (USB200.D0FIFO.UINT16[R_IO_L])
#define D0FIFO_0H (USB200.D0FIFO.UINT16[R_IO_H])
#define D0FIFO_0LL (USB200.D0FIFO.UINT8[R_IO_LL])
#define D0FIFO_0LH (USB200.D0FIFO.UINT8[R_IO_LH])
#define D0FIFO_0HL (USB200.D0FIFO.UINT8[R_IO_HL])
#define D0FIFO_0HH (USB200.D0FIFO.UINT8[R_IO_HH])
#define D1FIFO_0 (USB200.D1FIFO.UINT32)
#define D1FIFO_0L (USB200.D1FIFO.UINT16[R_IO_L])
#define D1FIFO_0H (USB200.D1FIFO.UINT16[R_IO_H])
#define D1FIFO_0LL (USB200.D1FIFO.UINT8[R_IO_LL])
#define D1FIFO_0LH (USB200.D1FIFO.UINT8[R_IO_LH])
#define D1FIFO_0HL (USB200.D1FIFO.UINT8[R_IO_HL])
#define D1FIFO_0HH (USB200.D1FIFO.UINT8[R_IO_HH])
#define CFIFOSEL_0 (USB200.CFIFOSEL)
#define CFIFOCTR_0 (USB200.CFIFOCTR)
#define D0FIFOSEL_0 (USB200.D0FIFOSEL)
#define D0FIFOCTR_0 (USB200.D0FIFOCTR)
#define D1FIFOSEL_0 (USB200.D1FIFOSEL)
#define D1FIFOCTR_0 (USB200.D1FIFOCTR)
#define INTENB0_0 (USB200.INTENB0)
#define INTENB1_0 (USB200.INTENB1)
#define BRDYENB_0 (USB200.BRDYENB)
#define NRDYENB_0 (USB200.NRDYENB)
#define BEMPENB_0 (USB200.BEMPENB)
#define SOFCFG_0 (USB200.SOFCFG)
#define INTSTS0_0 (USB200.INTSTS0)
#define INTSTS1_0 (USB200.INTSTS1)
#define BRDYSTS_0 (USB200.BRDYSTS)
#define NRDYSTS_0 (USB200.NRDYSTS)
#define BEMPSTS_0 (USB200.BEMPSTS)
#define FRMNUM_0 (USB200.FRMNUM)
#define UFRMNUM_0 (USB200.UFRMNUM)
#define USBADDR_0 (USB200.USBADDR)
#define USBREQ_0 (USB200.USBREQ)
#define USBVAL_0 (USB200.USBVAL)
#define USBINDX_0 (USB200.USBINDX)
#define USBLENG_0 (USB200.USBLENG)
#define DCPCFG_0 (USB200.DCPCFG)
#define DCPMAXP_0 (USB200.DCPMAXP)
#define DCPCTR_0 (USB200.DCPCTR)
#define PIPESEL_0 (USB200.PIPESEL)
#define PIPECFG_0 (USB200.PIPECFG)
#define PIPEBUF_0 (USB200.PIPEBUF)
#define PIPEMAXP_0 (USB200.PIPEMAXP)
#define PIPEPERI_0 (USB200.PIPEPERI)
#define PIPE1CTR_0 (USB200.PIPE1CTR)
#define PIPE2CTR_0 (USB200.PIPE2CTR)
#define PIPE3CTR_0 (USB200.PIPE3CTR)
#define PIPE4CTR_0 (USB200.PIPE4CTR)
#define PIPE5CTR_0 (USB200.PIPE5CTR)
#define PIPE6CTR_0 (USB200.PIPE6CTR)
#define PIPE7CTR_0 (USB200.PIPE7CTR)
#define PIPE8CTR_0 (USB200.PIPE8CTR)
#define PIPE9CTR_0 (USB200.PIPE9CTR)
#define PIPEACTR_0 (USB200.PIPEACTR)
#define PIPEBCTR_0 (USB200.PIPEBCTR)
#define PIPECCTR_0 (USB200.PIPECCTR)
#define PIPEDCTR_0 (USB200.PIPEDCTR)
#define PIPEECTR_0 (USB200.PIPEECTR)
#define PIPEFCTR_0 (USB200.PIPEFCTR)
#define PIPE1TRE_0 (USB200.PIPE1TRE)
#define PIPE1TRN_0 (USB200.PIPE1TRN)
#define PIPE2TRE_0 (USB200.PIPE2TRE)
#define PIPE2TRN_0 (USB200.PIPE2TRN)
#define PIPE3TRE_0 (USB200.PIPE3TRE)
#define PIPE3TRN_0 (USB200.PIPE3TRN)
#define PIPE4TRE_0 (USB200.PIPE4TRE)
#define PIPE4TRN_0 (USB200.PIPE4TRN)
#define PIPE5TRE_0 (USB200.PIPE5TRE)
#define PIPE5TRN_0 (USB200.PIPE5TRN)
#define PIPEBTRE_0 (USB200.PIPEBTRE)
#define PIPEBTRN_0 (USB200.PIPEBTRN)
#define PIPECTRE_0 (USB200.PIPECTRE)
#define PIPECTRN_0 (USB200.PIPECTRN)
#define PIPEDTRE_0 (USB200.PIPEDTRE)
#define PIPEDTRN_0 (USB200.PIPEDTRN)
#define PIPEETRE_0 (USB200.PIPEETRE)
#define PIPEETRN_0 (USB200.PIPEETRN)
#define PIPEFTRE_0 (USB200.PIPEFTRE)
#define PIPEFTRN_0 (USB200.PIPEFTRN)
#define PIPE9TRE_0 (USB200.PIPE9TRE)
#define PIPE9TRN_0 (USB200.PIPE9TRN)
#define PIPEATRE_0 (USB200.PIPEATRE)
#define PIPEATRN_0 (USB200.PIPEATRN)
#define DEVADD0_0 (USB200.DEVADD0)
#define DEVADD1_0 (USB200.DEVADD1)
#define DEVADD2_0 (USB200.DEVADD2)
#define DEVADD3_0 (USB200.DEVADD3)
#define DEVADD4_0 (USB200.DEVADD4)
#define DEVADD5_0 (USB200.DEVADD5)
#define DEVADD6_0 (USB200.DEVADD6)
#define DEVADD7_0 (USB200.DEVADD7)
#define DEVADD8_0 (USB200.DEVADD8)
#define DEVADD9_0 (USB200.DEVADD9)
#define DEVADDA_0 (USB200.DEVADDA)
#define SUSPMODE_0 (USB200.SUSPMODE)
#define D0FIFOB0_0 (USB200.D0FIFOB0)
#define D0FIFOB1_0 (USB200.D0FIFOB1)
#define D0FIFOB2_0 (USB200.D0FIFOB2)
#define D0FIFOB3_0 (USB200.D0FIFOB3)
#define D0FIFOB4_0 (USB200.D0FIFOB4)
#define D0FIFOB5_0 (USB200.D0FIFOB5)
#define D0FIFOB6_0 (USB200.D0FIFOB6)
#define D0FIFOB7_0 (USB200.D0FIFOB7)
#define D1FIFOB0_0 (USB200.D1FIFOB0)
#define D1FIFOB1_0 (USB200.D1FIFOB1)
#define D1FIFOB2_0 (USB200.D1FIFOB2)
#define D1FIFOB3_0 (USB200.D1FIFOB3)
#define D1FIFOB4_0 (USB200.D1FIFOB4)
#define D1FIFOB5_0 (USB200.D1FIFOB5)
#define D1FIFOB6_0 (USB200.D1FIFOB6)
#define D1FIFOB7_0 (USB200.D1FIFOB7)
#define SYSCFG0_1 (USB201.SYSCFG0)
#define BUSWAIT_1 (USB201.BUSWAIT)
#define SYSSTS0_1 (USB201.SYSSTS0)
#define DVSTCTR0_1 (USB201.DVSTCTR0)
#define TESTMODE_1 (USB201.TESTMODE)
#define D0FBCFG_1 (USB201.D0FBCFG)
#define D1FBCFG_1 (USB201.D1FBCFG)
#define CFIFO_1 (USB201.CFIFO.UINT32)
#define CFIFO_1L (USB201.CFIFO.UINT16[R_IO_L])
#define CFIFO_1H (USB201.CFIFO.UINT16[R_IO_H])
#define CFIFO_1LL (USB201.CFIFO.UINT8[R_IO_LL])
#define CFIFO_1LH (USB201.CFIFO.UINT8[R_IO_LH])
#define CFIFO_1HL (USB201.CFIFO.UINT8[R_IO_HL])
#define CFIFO_1HH (USB201.CFIFO.UINT8[R_IO_HH])
#define D0FIFO_1 (USB201.D0FIFO.UINT32)
#define D0FIFO_1L (USB201.D0FIFO.UINT16[R_IO_L])
#define D0FIFO_1H (USB201.D0FIFO.UINT16[R_IO_H])
#define D0FIFO_1LL (USB201.D0FIFO.UINT8[R_IO_LL])
#define D0FIFO_1LH (USB201.D0FIFO.UINT8[R_IO_LH])
#define D0FIFO_1HL (USB201.D0FIFO.UINT8[R_IO_HL])
#define D0FIFO_1HH (USB201.D0FIFO.UINT8[R_IO_HH])
#define D1FIFO_1 (USB201.D1FIFO.UINT32)
#define D1FIFO_1L (USB201.D1FIFO.UINT16[R_IO_L])
#define D1FIFO_1H (USB201.D1FIFO.UINT16[R_IO_H])
#define D1FIFO_1LL (USB201.D1FIFO.UINT8[R_IO_LL])
#define D1FIFO_1LH (USB201.D1FIFO.UINT8[R_IO_LH])
#define D1FIFO_1HL (USB201.D1FIFO.UINT8[R_IO_HL])
#define D1FIFO_1HH (USB201.D1FIFO.UINT8[R_IO_HH])
#define CFIFOSEL_1 (USB201.CFIFOSEL)
#define CFIFOCTR_1 (USB201.CFIFOCTR)
#define D0FIFOSEL_1 (USB201.D0FIFOSEL)
#define D0FIFOCTR_1 (USB201.D0FIFOCTR)
#define D1FIFOSEL_1 (USB201.D1FIFOSEL)
#define D1FIFOCTR_1 (USB201.D1FIFOCTR)
#define INTENB0_1 (USB201.INTENB0)
#define INTENB1_1 (USB201.INTENB1)
#define BRDYENB_1 (USB201.BRDYENB)
#define NRDYENB_1 (USB201.NRDYENB)
#define BEMPENB_1 (USB201.BEMPENB)
#define SOFCFG_1 (USB201.SOFCFG)
#define INTSTS0_1 (USB201.INTSTS0)
#define INTSTS1_1 (USB201.INTSTS1)
#define BRDYSTS_1 (USB201.BRDYSTS)
#define NRDYSTS_1 (USB201.NRDYSTS)
#define BEMPSTS_1 (USB201.BEMPSTS)
#define FRMNUM_1 (USB201.FRMNUM)
#define UFRMNUM_1 (USB201.UFRMNUM)
#define USBADDR_1 (USB201.USBADDR)
#define USBREQ_1 (USB201.USBREQ)
#define USBVAL_1 (USB201.USBVAL)
#define USBINDX_1 (USB201.USBINDX)
#define USBLENG_1 (USB201.USBLENG)
#define DCPCFG_1 (USB201.DCPCFG)
#define DCPMAXP_1 (USB201.DCPMAXP)
#define DCPCTR_1 (USB201.DCPCTR)
#define PIPESEL_1 (USB201.PIPESEL)
#define PIPECFG_1 (USB201.PIPECFG)
#define PIPEBUF_1 (USB201.PIPEBUF)
#define PIPEMAXP_1 (USB201.PIPEMAXP)
#define PIPEPERI_1 (USB201.PIPEPERI)
#define PIPE1CTR_1 (USB201.PIPE1CTR)
#define PIPE2CTR_1 (USB201.PIPE2CTR)
#define PIPE3CTR_1 (USB201.PIPE3CTR)
#define PIPE4CTR_1 (USB201.PIPE4CTR)
#define PIPE5CTR_1 (USB201.PIPE5CTR)
#define PIPE6CTR_1 (USB201.PIPE6CTR)
#define PIPE7CTR_1 (USB201.PIPE7CTR)
#define PIPE8CTR_1 (USB201.PIPE8CTR)
#define PIPE9CTR_1 (USB201.PIPE9CTR)
#define PIPEACTR_1 (USB201.PIPEACTR)
#define PIPEBCTR_1 (USB201.PIPEBCTR)
#define PIPECCTR_1 (USB201.PIPECCTR)
#define PIPEDCTR_1 (USB201.PIPEDCTR)
#define PIPEECTR_1 (USB201.PIPEECTR)
#define PIPEFCTR_1 (USB201.PIPEFCTR)
#define PIPE1TRE_1 (USB201.PIPE1TRE)
#define PIPE1TRN_1 (USB201.PIPE1TRN)
#define PIPE2TRE_1 (USB201.PIPE2TRE)
#define PIPE2TRN_1 (USB201.PIPE2TRN)
#define PIPE3TRE_1 (USB201.PIPE3TRE)
#define PIPE3TRN_1 (USB201.PIPE3TRN)
#define PIPE4TRE_1 (USB201.PIPE4TRE)
#define PIPE4TRN_1 (USB201.PIPE4TRN)
#define PIPE5TRE_1 (USB201.PIPE5TRE)
#define PIPE5TRN_1 (USB201.PIPE5TRN)
#define PIPEBTRE_1 (USB201.PIPEBTRE)
#define PIPEBTRN_1 (USB201.PIPEBTRN)
#define PIPECTRE_1 (USB201.PIPECTRE)
#define PIPECTRN_1 (USB201.PIPECTRN)
#define PIPEDTRE_1 (USB201.PIPEDTRE)
#define PIPEDTRN_1 (USB201.PIPEDTRN)
#define PIPEETRE_1 (USB201.PIPEETRE)
#define PIPEETRN_1 (USB201.PIPEETRN)
#define PIPEFTRE_1 (USB201.PIPEFTRE)
#define PIPEFTRN_1 (USB201.PIPEFTRN)
#define PIPE9TRE_1 (USB201.PIPE9TRE)
#define PIPE9TRN_1 (USB201.PIPE9TRN)
#define PIPEATRE_1 (USB201.PIPEATRE)
#define PIPEATRN_1 (USB201.PIPEATRN)
#define DEVADD0_1 (USB201.DEVADD0)
#define DEVADD1_1 (USB201.DEVADD1)
#define DEVADD2_1 (USB201.DEVADD2)
#define DEVADD3_1 (USB201.DEVADD3)
#define DEVADD4_1 (USB201.DEVADD4)
#define DEVADD5_1 (USB201.DEVADD5)
#define DEVADD6_1 (USB201.DEVADD6)
#define DEVADD7_1 (USB201.DEVADD7)
#define DEVADD8_1 (USB201.DEVADD8)
#define DEVADD9_1 (USB201.DEVADD9)
#define DEVADDA_1 (USB201.DEVADDA)
#define SUSPMODE_1 (USB201.SUSPMODE)
#define D0FIFOB0_1 (USB201.D0FIFOB0)
#define D0FIFOB1_1 (USB201.D0FIFOB1)
#define D0FIFOB2_1 (USB201.D0FIFOB2)
#define D0FIFOB3_1 (USB201.D0FIFOB3)
#define D0FIFOB4_1 (USB201.D0FIFOB4)
#define D0FIFOB5_1 (USB201.D0FIFOB5)
#define D0FIFOB6_1 (USB201.D0FIFOB6)
#define D0FIFOB7_1 (USB201.D0FIFOB7)
#define D1FIFOB0_1 (USB201.D1FIFOB0)
#define D1FIFOB1_1 (USB201.D1FIFOB1)
#define D1FIFOB2_1 (USB201.D1FIFOB2)
#define D1FIFOB3_1 (USB201.D1FIFOB3)
#define D1FIFOB4_1 (USB201.D1FIFOB4)
#define D1FIFOB5_1 (USB201.D1FIFOB5)
#define D1FIFOB6_1 (USB201.D1FIFOB6)
#define D1FIFOB7_1 (USB201.D1FIFOB7)
#define USB20_D0FBCFG_COUNT (2)
#define USB20_D0FIFO_COUNT (2)
#define USB20_INTENB0_COUNT (2)
#define USB20_INTSTS0_COUNT (2)
#define USB20_PIPE1CTR_COUNT (0xF)
#define USB20_DEVADD0_COUNT (0xB)
#define USB20_D0FIFOB0_COUNT (0x8)
typedef struct st_usb20
{
/* USB20 */
volatile uint16_t SYSCFG0; /* SYSCFG0 */
volatile uint16_t BUSWAIT; /* BUSWAIT */
volatile uint16_t SYSSTS0; /* SYSSTS0 */
volatile uint8_t dummy1[2]; /* */
volatile uint16_t DVSTCTR0; /* DVSTCTR0 */
volatile uint8_t dummy2[2]; /* */
volatile uint16_t TESTMODE; /* TESTMODE */
volatile uint8_t dummy3[2]; /* */
/* #define USB20_D0FBCFG_COUNT (2) */
volatile uint16_t D0FBCFG; /* D0FBCFG */
volatile uint16_t D1FBCFG; /* D1FBCFG */
union iodefine_reg32_t CFIFO; /* CFIFO */
/* #define USB20_D0FIFO_COUNT (2) */
union iodefine_reg32_t D0FIFO; /* D0FIFO */
union iodefine_reg32_t D1FIFO; /* D1FIFO */
volatile uint16_t CFIFOSEL; /* CFIFOSEL */
volatile uint16_t CFIFOCTR; /* CFIFOCTR */
volatile uint8_t dummy4[4]; /* */
/* start of struct st_usb20_from_d0fifosel */
volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
/* end of struct st_usb20_from_d0fifosel */
/* start of struct st_usb20_from_d0fifosel */
volatile uint16_t D1FIFOSEL; /* D1FIFOSEL */
volatile uint16_t D1FIFOCTR; /* D1FIFOCTR */
/* end of struct st_usb20_from_d0fifosel */
/* #define USB20_INTENB0_COUNT (2) */
volatile uint16_t INTENB0; /* INTENB0 */
volatile uint16_t INTENB1; /* INTENB1 */
volatile uint8_t dummy5[2]; /* */
volatile uint16_t BRDYENB; /* BRDYENB */
volatile uint16_t NRDYENB; /* NRDYENB */
volatile uint16_t BEMPENB; /* BEMPENB */
volatile uint16_t SOFCFG; /* SOFCFG */
volatile uint8_t dummy6[2]; /* */
/* #define USB20_INTSTS0_COUNT (2) */
volatile uint16_t INTSTS0; /* INTSTS0 */
volatile uint16_t INTSTS1; /* INTSTS1 */
volatile uint8_t dummy7[2]; /* */
volatile uint16_t BRDYSTS; /* BRDYSTS */
volatile uint16_t NRDYSTS; /* NRDYSTS */
volatile uint16_t BEMPSTS; /* BEMPSTS */
volatile uint16_t FRMNUM; /* FRMNUM */
volatile uint16_t UFRMNUM; /* UFRMNUM */
volatile uint16_t USBADDR; /* USBADDR */
volatile uint8_t dummy8[2]; /* */
volatile uint16_t USBREQ; /* USBREQ */
volatile uint16_t USBVAL; /* USBVAL */
volatile uint16_t USBINDX; /* USBINDX */
volatile uint16_t USBLENG; /* USBLENG */
volatile uint16_t DCPCFG; /* DCPCFG */
volatile uint16_t DCPMAXP; /* DCPMAXP */
volatile uint16_t DCPCTR; /* DCPCTR */
volatile uint8_t dummy9[2]; /* */
volatile uint16_t PIPESEL; /* PIPESEL */
volatile uint8_t dummy10[2]; /* */
volatile uint16_t PIPECFG; /* PIPECFG */
volatile uint16_t PIPEBUF; /* PIPEBUF */
volatile uint16_t PIPEMAXP; /* PIPEMAXP */
volatile uint16_t PIPEPERI; /* PIPEPERI */
/* #define USB20_PIPE1CTR_COUNT (0xF) */
volatile uint16_t PIPE1CTR; /* PIPE1CTR */
volatile uint16_t PIPE2CTR; /* PIPE2CTR */
volatile uint16_t PIPE3CTR; /* PIPE3CTR */
volatile uint16_t PIPE4CTR; /* PIPE4CTR */
volatile uint16_t PIPE5CTR; /* PIPE5CTR */
volatile uint16_t PIPE6CTR; /* PIPE6CTR */
volatile uint16_t PIPE7CTR; /* PIPE7CTR */
volatile uint16_t PIPE8CTR; /* PIPE8CTR */
volatile uint16_t PIPE9CTR; /* PIPE9CTR */
volatile uint16_t PIPEACTR; /* PIPEACTR */
volatile uint16_t PIPEBCTR; /* PIPEBCTR */
volatile uint16_t PIPECCTR; /* PIPECCTR */
volatile uint16_t PIPEDCTR; /* PIPEDCTR */
volatile uint16_t PIPEECTR; /* PIPEECTR */
volatile uint16_t PIPEFCTR; /* PIPEFCTR */
volatile uint8_t dummy11[2]; /* */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE1TRE; /* PIPE1TRE */
volatile uint16_t PIPE1TRN; /* PIPE1TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE2TRE; /* PIPE2TRE */
volatile uint16_t PIPE2TRN; /* PIPE2TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE3TRE; /* PIPE3TRE */
volatile uint16_t PIPE3TRN; /* PIPE3TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE4TRE; /* PIPE4TRE */
volatile uint16_t PIPE4TRN; /* PIPE4TRN */
/* end of struct st_usb20_from_pipe1tre */
/* start of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPE5TRE; /* PIPE5TRE */
volatile uint16_t PIPE5TRN; /* PIPE5TRN */
/* end of struct st_usb20_from_pipe1tre */
volatile uint16_t PIPEBTRE; /* PIPEBTRE */
volatile uint16_t PIPEBTRN; /* PIPEBTRN */
volatile uint16_t PIPECTRE; /* PIPECTRE */
volatile uint16_t PIPECTRN; /* PIPECTRN */
volatile uint16_t PIPEDTRE; /* PIPEDTRE */
volatile uint16_t PIPEDTRN; /* PIPEDTRN */
volatile uint16_t PIPEETRE; /* PIPEETRE */
volatile uint16_t PIPEETRN; /* PIPEETRN */
volatile uint16_t PIPEFTRE; /* PIPEFTRE */
volatile uint16_t PIPEFTRN; /* PIPEFTRN */
volatile uint16_t PIPE9TRE; /* PIPE9TRE */
volatile uint16_t PIPE9TRN; /* PIPE9TRN */
volatile uint16_t PIPEATRE; /* PIPEATRE */
volatile uint16_t PIPEATRN; /* PIPEATRN */
volatile uint8_t dummy12[16]; /* */
/* #define USB20_DEVADD0_COUNT (0xB) */
volatile uint16_t DEVADD0; /* DEVADD0 */
volatile uint16_t DEVADD1; /* DEVADD1 */
volatile uint16_t DEVADD2; /* DEVADD2 */
volatile uint16_t DEVADD3; /* DEVADD3 */
volatile uint16_t DEVADD4; /* DEVADD4 */
volatile uint16_t DEVADD5; /* DEVADD5 */
volatile uint16_t DEVADD6; /* DEVADD6 */
volatile uint16_t DEVADD7; /* DEVADD7 */
volatile uint16_t DEVADD8; /* DEVADD8 */
volatile uint16_t DEVADD9; /* DEVADD9 */
volatile uint16_t DEVADDA; /* DEVADDA */
volatile uint8_t dummy13[28]; /* */
volatile uint16_t SUSPMODE; /* SUSPMODE */
volatile uint8_t dummy14[92]; /* */
/* start of struct st_usb20_from_dmfifob0 */
volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
/* end of struct st_usb20_from_dmfifob0 */
/* start of struct st_usb20_from_dmfifob0 */
volatile uint32_t D1FIFOB0; /* D1FIFOB0 */
volatile uint32_t D1FIFOB1; /* D1FIFOB1 */
volatile uint32_t D1FIFOB2; /* D1FIFOB2 */
volatile uint32_t D1FIFOB3; /* D1FIFOB3 */
volatile uint32_t D1FIFOB4; /* D1FIFOB4 */
volatile uint32_t D1FIFOB5; /* D1FIFOB5 */
volatile uint32_t D1FIFOB6; /* D1FIFOB6 */
volatile uint32_t D1FIFOB7; /* D1FIFOB7 */
/* end of struct st_usb20_from_dmfifob0 */
} r_io_usb20_t;
typedef struct st_usb20_from_d0fifosel
{
volatile uint16_t D0FIFOSEL; /* D0FIFOSEL */
volatile uint16_t D0FIFOCTR; /* D0FIFOCTR */
} r_io_usb20_from_d0fifosel_t;
typedef struct st_usb20_from_pipe1tre
{
volatile uint16_t PIPE1TRE; /* PIPE1TRE */
volatile uint16_t PIPE1TRN; /* PIPE1TRN */
} r_io_usb20_from_pipe1tre_t;
typedef struct st_usb20_from_dmfifob0
{
/* #define USB20_D0FIFOB0_COUNT (0x8) */
volatile uint32_t D0FIFOB0; /* D0FIFOB0 */
volatile uint32_t D0FIFOB1; /* D0FIFOB1 */
volatile uint32_t D0FIFOB2; /* D0FIFOB2 */
volatile uint32_t D0FIFOB3; /* D0FIFOB3 */
volatile uint32_t D0FIFOB4; /* D0FIFOB4 */
volatile uint32_t D0FIFOB5; /* D0FIFOB5 */
volatile uint32_t D0FIFOB6; /* D0FIFOB6 */
volatile uint32_t D0FIFOB7; /* D0FIFOB7 */
} r_io_usb20_from_dmfifob0_t;
/* Channel array defines of USB20 (2)*/
#ifdef DECLARE_USB20_CHANNELS
volatile struct st_usb20* USB20[ USB20_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_CHANNELS */
#ifdef DECLARE_USB20_FROM_D0FIFOB0_CHANNELS
volatile struct st_usb20_from_dmfifob0* USB20_FROM_D0FIFOB0[ USB20_COUNT ][ USB20_FROM_D0FIFOB0_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_FROM_D0FIFOB0_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_FROM_D0FIFOB0_CHANNELS */
#ifdef DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS
volatile struct st_usb20_from_pipe1tre* USB20_FROM_PIPE1ATRE[ USB20_COUNT ][ USB20_FROM_PIPE1ATRE_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_FROM_PIPE1ATRE_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_FROM_PIPE1ATRE_CHANNELS */
#ifdef DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS
volatile struct st_usb20_from_d0fifosel* USB20_FROM_D0FIFOSEL[ USB20_COUNT ][ USB20_FROM_D0FIFOSEL_COUNT ] =
/* ->MISRA 11.3 */ /* ->SEC R2.7.1 */
USB20_FROM_D0FIFOSEL_ADDRESS_LIST;
/* <-MISRA 11.3 */ /* <-SEC R2.7.1 */
#endif /* DECLARE_USB20_FROM_D0FIFOSEL_CHANNELS */
/* End of channel array defines of USB20 (2)*/
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/vdc5_iodefine.h
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57
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/iodefines/wdt_iodefine.h
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@ -1,57 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer*
* Copyright (C) 2013-2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/*******************************************************************************
* File Name : wdt_iodefine.h
* $Rev: $
* $Date:: $
* Description : Definition of I/O Register for RZ/A1H,M (V2.00h)
******************************************************************************/
#ifndef WDT_IODEFINE_H
#define WDT_IODEFINE_H
/* ->QAC 0639 : Over 127 members (C90) */
/* ->QAC 0857 : Over 1024 #define (C90) */
/* ->MISRA 18.4 : Pack unpack union */ /* ->SEC M1.6.2 */
/* ->SEC M1.10.1 : Not magic number */
#define WDT (*(struct st_wdt *)0xFCFE0000uL) /* WDT */
#define WDTWTCSR (WDT.WTCSR)
#define WDTWTCNT (WDT.WTCNT)
#define WDTWRCSR (WDT.WRCSR)
typedef struct st_wdt
{
/* WDT */
volatile uint16_t WTCSR; /* WTCSR */
volatile uint16_t WTCNT; /* WTCNT */
volatile uint16_t WRCSR; /* WRCSR */
} r_io_wdt_t;
/* <-SEC M1.10.1 */
/* <-MISRA 18.4 */ /* <-SEC M1.6.2 */
/* <-QAC 0857 */
/* <-QAC 0639 */
#endif

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/inc/reg32_t.h
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#ifndef __REG32_T
#define __REG32_T
union reg32_t {
volatile uint32_t UINT32;
volatile uint16_t UINT16[2];
volatile uint8_t UINT8[4];
};
#endif

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targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/mmu_VK_RZ_A1H.c
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/**************************************************************************//**
* @file mmu_VK_RZ_A1H.c
* @brief MMU Configuration for RZ_A1H Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
/* Memory map description from: Renesas RZ_A1H_05E_121130.pdf
Memory Type
0xffffffff |--------------------------| ------------
| Peripherals | Device
0xfcf00000 |--------------------------| ------------
| Page Fault | Fault
0xe8300000 |--------------------------| ------------
| Peripherals | Device
0xe8000000 |--------------------------| ------------
| Page Fault | Fault
0x60A00000 |--------------------------| ------------
| On Chip RAM (10M) Mirror | Fault
0x60000000 |--------------------------| ------------
| SPI multi I/O 64MB | Fault
0x5c000000 |--------------------------| ------------
| SPI multi I/O 64MB | Fault
0x58000000 |--------------------------| ------------
| CS5 Mirror | Fault
0x54000000 |--------------------------| ------------
| CS4 Mirror | Fault
0x50000000 |--------------------------| ------------
| CS3 Mirror | Fault
0x4c000000 |--------------------------| ------------
| CS2 Mirror | Fault
0x48000000 |--------------------------| ------------
| CS1 Mirror | Fault
0x44000000 |--------------------------| ------------
| CS0 Mirror | Fault
0x40000000 |--------------------------| ------------
| BSC | RW
0x3ff00000 |--------------------------| ------------
| SPI_MIO_BASE | RW
0x3fe00000 |--------------------------| ------------
| Page Fault | Fault
0x20A00000 |--------------------------| ------------
| On Chip RAM (10M) | RW
0x20000000 |--------------------------| ------------
| SPI multi I/O 64MB | RO
0x1c000000 |--------------------------| ------------
| SPI multi I/O 64MB | RO
0x18000000 |--------------------------| ------------
| CS5 User Area 64MB | RW
0x14000000 |--------------------------| ------------
| CS4 User Area 64MB | RW
0x10000000 |--------------------------| ------------
| CS3 SDRAM 64MB | RW
0x0c000000 |--------------------------| ------------
| CS2 SDRAM 64MB | RW
0x08000000 |--------------------------| ------------
| CS1 NOR Flash 64MB | RO
0x04000000 |--------------------------| ------------
| CS0 NOR Flash 64MB | RO
0x00000000 |--------------------------| ------------
*/
// L1 Cache info and restrictions about architecture of the caches (CCSIR register):
// Write-Through support *not* available
// Write-Back support available.
// Read allocation support available.
// Write allocation support available.
//Note: You should use the Shareable attribute carefully.
//For cores without coherency logic (such as SCU) marking a region as shareable forces the processor to not cache that region regardless of the inner cache settings.
//Cortex-A versions of RTX use LDREX/STREX instructions relying on Local monitors. Local monitors will be used only when the region gets cached, regions that are not cached will use the Global Monitor.
//Some Cortex-A implementations do not include Global Monitors, so wrongly setting the attribute Shareable may cause STREX to fail.
//Recall: When the Shareable attribute is applied to a memory region that is not Write-Back, Normal memory, data held in this region is treated as Non-cacheable.
//When SMP bit = 0, Inner WB/WA Cacheable Shareable attributes are treated as Non-cacheable.
//When SMP bit = 1, Inner WB/WA Cacheable Shareable attributes are treated as Cacheable.
//Following MMU configuration is expected
//SCTLR.AFE == 1 (Simplified access permissions model - AP[2:1] define access permissions, AP[0] is an access flag)
//SCTLR.TRE == 0 (TEX remap disabled, so memory type and attributes are described directly by bits in the descriptor)
//Domain 0 is always the Client domain
//Descriptors should place all memory in domain 0
//There are no restrictions by privilege level (PL0 can access all memory)
#include "VK_RZ_A1H.h"
//Import symbols from linker
extern uint32_t Image$$VECTORS$$Base;
extern uint32_t Image$$RO_DATA$$Base;
extern uint32_t Image$$RW_DATA$$Base;
extern uint32_t Image$$RW_IRAM1$$Base;
#if !defined ( __ICCARM__ )
extern uint32_t Image$$TTB$$ZI$$Base;
#endif
#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#elif defined( __ICCARM__ )
#else
extern uint32_t Image$$RW_DATA_NC$$Base;
extern uint32_t Image$$ZI_DATA_NC$$Base;
#endif
extern uint32_t Image$$VECTORS$$Limit;
extern uint32_t Image$$RO_DATA$$Limit;
extern uint32_t Image$$RW_DATA$$Limit;
extern uint32_t Image$$RW_IRAM1$$Limit;
#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
extern uint32_t Image$$RW_DATA_NC$$Limit;
extern uint32_t Image$$ZI_DATA_NC$$Limit;
#endif
#if defined( __ICCARM__ )
#define VECTORS_SIZE (((uint32_t)Image$$VECTORS$$Limit >> 20) - ((uint32_t)Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)Image$$RO_DATA$$Limit >> 20) - ((uint32_t)Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)Image$$RW_DATA$$Limit >> 20) - ((uint32_t)Image$$RW_DATA$$Base >> 20) + 1)
#define RW_IRAM1_SIZE (((uint32_t)Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)Image$$RW_IRAM1$$Base >> 20) + 1)
#else
#define VECTORS_SIZE (((uint32_t)&Image$$VECTORS$$Limit >> 20) - ((uint32_t)&Image$$VECTORS$$Base >> 20) + 1)
#define RO_DATA_SIZE (((uint32_t)&Image$$RO_DATA$$Limit >> 20) - ((uint32_t)&Image$$RO_DATA$$Base >> 20) + 1)
#define RW_DATA_SIZE (((uint32_t)&Image$$RW_DATA$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA$$Base >> 20) + 1)
#define RW_IRAM1_SIZE (((uint32_t)&Image$$RW_IRAM1$$Limit >> 20) - ((uint32_t)&Image$$RW_IRAM1$$Base >> 20) + 1)
#endif
#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
#else
#define RW_DATA_NC_SIZE (((uint32_t)&Image$$RW_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$RW_DATA_NC$$Base >> 20) + 1)
#define ZI_DATA_NC_SIZE (((uint32_t)&Image$$ZI_DATA_NC$$Limit >> 20) - ((uint32_t)&Image$$ZI_DATA_NC$$Base >> 20) + 1)
#endif
static uint32_t Sect_Normal; //outer & inner wb/wa, non-shareable, executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_NC; //non-shareable, non-executable, rw, domain 0, base addr 0
static uint32_t Sect_Normal_Cod; //outer & inner wb/wa, non-shareable, executable, ro, domain 0, base addr 0
static uint32_t Sect_Normal_RO; //as Sect_Normal_Cod, but not executable
static uint32_t Sect_Normal_RW; //as Sect_Normal_Cod, but writeable and not executable
static uint32_t Sect_Device_RO; //device, non-shareable, non-executable, ro, domain 0, base addr 0
static uint32_t Sect_Device_RW; //as Sect_Device_RO, but writeable
/* Define global descriptors */
static uint32_t Page_L1_4k = 0x0; //generic
static uint32_t Page_L1_64k = 0x0; //generic
static uint32_t Page_4k_Device_RW; //Shared device, not executable, rw, domain 0
static uint32_t Page_64k_Device_RW; //Shared device, not executable, rw, domain 0
#if defined ( __ICCARM__ )
__no_init uint32_t Image$$TTB$$ZI$$Base @ ".retram";
uint32_t Image$$VECTORS$$Base;
uint32_t Image$$RO_DATA$$Base;
uint32_t Image$$RW_DATA$$Base;
uint32_t Image$$RW_IRAM1$$Base;
uint32_t Image$$VECTORS$$Limit;
uint32_t Image$$RO_DATA$$Limit;
uint32_t Image$$RW_DATA$$Limit;
uint32_t Image$$RW_IRAM1$$Limit;
#endif
void MMU_CreateTranslationTable(void)
{
mmu_region_attributes_Type region;
#if defined ( __ICCARM__ )
#pragma section=".intvec"
#pragma section=".rodata"
#pragma section=".rwdata"
#pragma section=".bss"
Image$$VECTORS$$Base = (uint32_t) __section_begin(".intvec");
Image$$VECTORS$$Limit= ((uint32_t)__section_begin(".intvec")+(uint32_t)__section_size(".intvec"));
Image$$RO_DATA$$Base = (uint32_t) __section_begin(".rodata");
Image$$RO_DATA$$Limit= ((uint32_t)__section_begin(".rodata")+(uint32_t)__section_size(".rodata"));
Image$$RW_DATA$$Base = (uint32_t) __section_begin(".rwdata");
Image$$RW_DATA$$Limit= ((uint32_t)__section_begin(".rwdata")+(uint32_t)__section_size(".rwdata"));
Image$$RW_IRAM1$$Base = (uint32_t) __section_begin(".bss");
Image$$RW_IRAM1$$Limit= ((uint32_t)__section_begin(".bss")+(uint32_t)__section_size(".bss"));
#endif
/*
* Generate descriptors. Refer to core_ca.h to get information about attributes
*
*/
//Create descriptors for Vectors, RO, RW, ZI sections
section_normal(Sect_Normal, region);
section_normal_cod(Sect_Normal_Cod, region);
section_normal_ro(Sect_Normal_RO, region);
section_normal_rw(Sect_Normal_RW, region);
//Create descriptors for peripherals
section_device_ro(Sect_Device_RO, region);
section_device_rw(Sect_Device_RW, region);
section_normal_nc(Sect_Normal_NC, region);
//Create descriptors for 64k pages
page64k_device_rw(Page_L1_64k, Page_64k_Device_RW, region);
//Create descriptors for 4k pages
page4k_device_rw(Page_L1_4k, Page_4k_Device_RW, region);
/*
* Define MMU flat-map regions and attributes
*
*/
//Create 4GB of faulting entries
MMU_TTSection (&Image$$TTB$$ZI$$Base, 0, 4096, DESCRIPTOR_FAULT);
// R7S72100 memory map.
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE0 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_NORFLASH_BASE1 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE0 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SDRAM_BASE1 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA0 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_USER_AREA1 , 64, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO0 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_IO1 , 64, Sect_Normal_RO);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_BASE , 10, Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_SPI_MIO_BASE , 1, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_BSC_BASE , 1, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE0 , 3, Sect_Device_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_PERIPH_BASE1 , 49, Sect_Device_RW);
#if defined( __ICCARM__ )
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#else
//Define Image
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RO_DATA$$Base , RO_DATA_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$VECTORS$$Base , VECTORS_SIZE , Sect_Normal_Cod);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA$$Base , RW_DATA_SIZE , Sect_Normal_RW);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_IRAM1$$Base, RW_IRAM1_SIZE, Sect_Normal_RW);
#endif
#if defined( __CC_ARM ) || defined( __ARMCC_VERSION )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#elif defined ( __ICCARM__ )
MMU_TTSection (&Image$$TTB$$ZI$$Base, RZ_A1_ONCHIP_SRAM_NC_BASE , 10, Sect_Normal_NC);
#else
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$RW_DATA_NC$$Base, RW_DATA_NC_SIZE, Sect_Normal_NC);
MMU_TTSection (&Image$$TTB$$ZI$$Base, (uint32_t)&Image$$ZI_DATA_NC$$Base, ZI_DATA_NC_SIZE, Sect_Normal_NC);
#endif
/* Set location of level 1 page table
; 31:14 - Translation table base addr (31:14-TTBCR.N, TTBCR.N is 0 out of reset)
; 13:7 - 0x0
; 6 - IRGN[0] 0x0 (Inner WB WA)
; 5 - NOS 0x0 (Non-shared)
; 4:3 - RGN 0x1 (Outer WB WA)
; 2 - IMP 0x0 (Implementation Defined)
; 1 - S 0x0 (Non-shared)
; 0 - IRGN[1] 0x1 (Inner WB WA) */
__set_TTBR0(((uint32_t)&Image$$TTB$$ZI$$Base) | 9);
__ISB();
/* Set up domain access control register
; We set domain 0 to Client and all other domains to No Access.
; All translation table entries specify domain 0 */
__set_DACR(1);
__ISB();
}

230
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/nvic_wrapper.c
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@ -1,230 +0,0 @@
/*******************************************************************************
* DISCLAIMER
* This software is supplied by Renesas Electronics Corporation and is only
* intended for use with Renesas products. No other uses are authorized. This
* software is owned by Renesas Electronics Corporation and is protected under
* all applicable laws, including copyright laws.
* THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
* LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
* AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
* TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
* ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
* FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
* ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
* BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
* Renesas reserves the right, without notice, to make changes to this software
* and to discontinue the availability of this software. By using this software,
* you agree to the additional terms and conditions found by accessing the
* following link:
* http://www.renesas.com/disclaimer
* Copyright (C) 2012 - 2015 Renesas Electronics Corporation. All rights reserved.
*******************************************************************************/
/**************************************************************************//**
* @file nvic_wrapper.c
* $Rev: $
* $Date:: $
* @brief Wrapper between NVIC(for Cortex-M) and GIC(for Cortex-A9)
******************************************************************************/
/******************************************************************************
Includes <System Includes> , "Project Includes"
******************************************************************************/
#include "VKRZA1H.h"
#include "wdt_iodefine.h"
#include "nvic_wrapper.h"
/******************************************************************************
Typedef definitions
******************************************************************************/
/******************************************************************************
Macro definitions
******************************************************************************/
#define PRIO_BITS (7) /* Set binary point to 0 in gic.c */
#define WDT_WTCNT_WRITE (0x5A00)
#define WDT_WTCSR_WRITE (0xA500)
#define WDT_WRCSR_WOVF_WRITE (0xA500)
#define WDT_WRCSR_RSTE_WRITE (0x5A00)
/******************************************************************************
Imported global variables and functions (from other files)
******************************************************************************/
/******************************************************************************
Exported global variables and functions (to be accessed by other files)
******************************************************************************/
/******************************************************************************
Private global variables and functions
******************************************************************************/
/* ########################## NVIC functions #################################### */
void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
{
GIC_SetBinaryPoint(PriorityGroup);
}
uint32_t NVIC_GetPriorityGrouping(void)
{
return GIC_GetBinaryPoint();
}
void NVIC_EnableIRQ(IRQn_Type IRQn)
{
GIC_EnableIRQ(IRQn);
}
void NVIC_DisableIRQ(IRQn_Type IRQn)
{
GIC_DisableIRQ(IRQn);
}
uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
{
uint32_t pending;
pending = GIC_GetIRQStatus(IRQn);
pending = (pending & 0x00000001);
return pending;
}
void NVIC_SetPendingIRQ(IRQn_Type IRQn)
{
GIC_SetPendingIRQ(IRQn);
}
void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
{
GIC_ClearPendingIRQ(IRQn);
}
uint32_t NVIC_GetActive(IRQn_Type IRQn)
{
uint32_t active;
active = GIC_GetIRQStatus(IRQn);
active = ((active >> 1) & 0x00000001);
return active;
}
void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
{
GIC_SetPriority(IRQn, (priority << 3));
}
uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
uint32_t priority_field;
priority_field = GIC_GetPriority(IRQn);
priority_field = (priority_field >> 3);
return priority_field;
}
uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
return (
((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
((SubPriority & ((1 << (SubPriorityBits )) - 1)))
);
}
void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
{
uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
uint32_t PreemptPriorityBits;
uint32_t SubPriorityBits;
PreemptPriorityBits = ((7 - PriorityGroupTmp) > PRIO_BITS) ? PRIO_BITS : 7 - PriorityGroupTmp;
SubPriorityBits = ((PriorityGroupTmp + PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + PRIO_BITS;
*pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
*pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
}
void NVIC_SystemReset(void)
{
uint16_t reg;
uint8_t dummy_read;
/* Use Watch Dog Timer to system reset */
/* Set WT/IT bit of WTCSR to 1 = Watch Dog */
/* CLK = 000, 1xP0phi(=33.3333MHz) = 7.7us */
reg = (WDT_WTCSR_WRITE | 0x0058);
WDTWTCSR = reg;
/* Clear Count reg */
reg = (WDT_WTCNT_WRITE | 0x0000);
WDTWTCNT = reg;
/* Clear WOVF flag */
dummy_read = WDTWRCSR;
reg = (WDT_WRCSR_WOVF_WRITE | (dummy_read & 0x0000));
WDTWRCSR = reg;
/* Enable Internal Reset */
reg = (WDT_WRCSR_RSTE_WRITE | 0x005F);
WDTWRCSR = reg;
/* Watch Dog start */
reg = (WDT_WTCSR_WRITE | 0x0078);
WDTWTCSR = reg;
while(1); /* wait Internal Reset */
}
/* ################################## SysTick function ############################################ */
uint32_t SysTick_Config(uint32_t ticks)
{
/* Not support this function */
/* Use mbed Ticker */
return (1); /* impossible */
}
/* ##################################### Debug In/Output function ########################################### */
uint32_t ITM_SendChar (uint32_t ch)
{
/* Not support this function */
/* Use mbed Serial */
return (ch);
}
int32_t ITM_ReceiveChar (void)
{
/* Not support this function */
/* Use mbed Serial */
return (-1); /* no character available */
}
int32_t ITM_CheckChar (void)
{
/* Not support this function */
/* Use mbed Serial */
return (0); /* no character available */
}

196
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/os_tick_ostm.c
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@ -1,196 +0,0 @@
/**************************************************************************//**
* @file os_tick_ostm.c
* @brief CMSIS OS Tick implementation for OS Timer
* @version V1.0.1
* @date 19. September 2017
******************************************************************************/
/*
* Copyright (c) 2017-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "irq_ctrl.h"
#include "cmsis.h"
#include "mbed_drv_cfg.h"
// Define OS Timer channel and interrupt number
#define OSTM (OSTM0)
#define OSTM_IRQn ((IRQn_ID_t)OSTMI0TINT_IRQn)
#ifdef MBED_CONF_RTOS_PRESENT
#include "os_tick.h"
// Define OS TImer interrupt priority
#ifndef OSTM_IRQ_PRIORITY
#define OSTM_IRQ_PRIORITY 0xFFU
#endif
static uint32_t OSTM_Clock; // Timer tick frequency
static uint8_t OSTM_PendIRQ; // Timer interrupt pending flag
// Setup OS Tick.
int32_t OS_Tick_Setup (uint32_t freq, IRQHandler_t handler)
{
uint32_t clock;
uint32_t prio;
uint32_t bits;
if (freq == 0U) {
return (-1);
}
OSTM_PendIRQ = 0U;
// Get CPG.FRQCR[IFC] bits
clock = (CPG.FRQCR >> 8) & 0x03;
// Determine Divider 2 output clock by using RENESAS_RZ_A1_P0_CLK
if (clock == 0x03U) {
clock = (RENESAS_RZ_A1_P0_CLK * 3U);
}
else if (clock == 0x01U) {
clock = (RENESAS_RZ_A1_P0_CLK * 3U)/2U;
}
else {
clock = RENESAS_RZ_A1_P0_CLK;
}
// Determine tick frequency
clock = clock / freq;
// Save frequency for later
OSTM_Clock = clock;
// Enable OSTM clock
CPG.STBCR5 &= ~(CPG_STBCR5_BIT_MSTP51);
// Stop the OSTM counter
OSTM.OSTMnTT = 0x01U;
// Set interval timer mode and disable interrupts when counting starts
OSTM.OSTMnCTL = 0x00U;
// Set compare value
OSTM.OSTMnCMP = clock - 1U;
// Disable corresponding IRQ
IRQ_Disable (OSTM_IRQn);
IRQ_ClearPending(OSTM_IRQn);
// Determine number of implemented priority bits
IRQ_SetPriority (OSTM_IRQn, 0xFFU);
prio = IRQ_GetPriority (OSTM_IRQn);
// At least bits [7:4] must be implemented
if ((prio & 0xF0U) == 0U) {
return (-1);
}
for (bits = 0; bits < 4; bits++) {
if ((prio & 0x01) != 0) {
break;
}
prio >>= 1;
}
// Adjust configured priority to the number of implemented priority bits
prio = (OSTM_IRQ_PRIORITY << bits) & 0xFFUL;
// Set OSTM interrupt priority
IRQ_SetPriority(OSTM_IRQn, prio-1U);
// Set edge-triggered, non-secure, single CPU targeted IRQ
IRQ_SetMode (OSTM_IRQn, IRQ_MODE_TRIG_EDGE);
// Register tick interrupt handler function
IRQ_SetHandler(OSTM_IRQn, (IRQHandler_t)handler);
// Enable corresponding IRQ
IRQ_Enable (OSTM_IRQn);
return (0);
}
/// Enable OS Tick.
void OS_Tick_Enable (void)
{
if (OSTM_PendIRQ != 0U) {
OSTM_PendIRQ = 0U;
IRQ_SetPending (OSTM_IRQn);
}
// Start the OSTM counter
OSTM.OSTMnTS = 0x01U;
}
/// Disable OS Tick.
void OS_Tick_Disable (void)
{
// Stop the OSTM counter
OSTM.OSTMnTT = 0x01U;
if (IRQ_GetPending(OSTM_IRQn) != 0) {
IRQ_ClearPending (OSTM_IRQn);
OSTM_PendIRQ = 1U;
}
}
// Acknowledge OS Tick IRQ.
void OS_Tick_AcknowledgeIRQ (void)
{
IRQ_ClearPending (OSTM_IRQn);
}
// Get OS Tick IRQ number.
int32_t OS_Tick_GetIRQn (void)
{
return (OSTM_IRQn);
}
// Get OS Tick clock.
uint32_t OS_Tick_GetClock (void)
{
return (OSTM_Clock);
}
// Get OS Tick interval.
uint32_t OS_Tick_GetInterval (void)
{
return (OSTM.OSTMnCMP + 1U);
}
// Get OS Tick count value.
uint32_t OS_Tick_GetCount (void)
{
uint32_t cmp = OSTM.OSTMnCMP;
return (cmp - OSTM.OSTMnCNT);
}
// Get OS Tick overflow status.
uint32_t OS_Tick_GetOverflow (void)
{
return (IRQ_GetPending(OSTM_IRQn));
}
#endif
// Get Cortex-A9 OS Timer interrupt number
IRQn_ID_t mbed_get_a9_tick_irqn(){
return OSTM_IRQn;
}

140
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.c
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@ -1,140 +0,0 @@
/******************************************************************************
* @file system_VK_RZ_A1H_H.c
* @brief CMSIS Device System Source File for ARM Cortex-A9 Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2013-2014 Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "VK_RZ_A1H.h"
#include "RZ_A1_Init.h"
#include "irq_ctrl.h"
#include "mbed_drv_cfg.h"
/*
Port 0 (P0) MD pin assignment
P0_0: MD_BOOT0
P0_1: MD_BOOT1
P0_2: MD_CLK
P0_3: MD_CLKS
*/
/*----------------------------------------------------------------------------
System Core Clock Variable
*----------------------------------------------------------------------------*/
uint32_t SystemCoreClock = RENESAS_RZ_A1_SYS_CLK;
/*----------------------------------------------------------------------------
System Core Clock update function
*----------------------------------------------------------------------------*/
void SystemCoreClockUpdate (void)
{
uint32_t freq;
uint16_t ifc;
freq = RENESAS_RZ_A1_SYS_CLK;
/* Get CPG.FRQCR[IFC] bits */
ifc = (CPG.FRQCR >> 8U) & 0x03U;
/* Determine Divider 2 output clock */
if (ifc == 0x03U) {
/* Division ratio is 1/3 */
freq = (freq / 3U);
} else if (ifc == 0x01U) {
/* Division ratio is 2/3 */
freq = (freq * 2U) / 3U;
} else {
/* do nothing */
}
SystemCoreClock = freq;
}
/*----------------------------------------------------------------------------
IRQ Handler Register/Unregister
*----------------------------------------------------------------------------*/
uint32_t InterruptHandlerRegister (IRQn_Type irq, IRQHandler handler)
{
return IRQ_SetHandler(irq, handler);
}
uint32_t InterruptHandlerUnregister (IRQn_Type irq)
{
return IRQ_SetHandler(irq, (IRQHandler_t)NULL);
}
/*----------------------------------------------------------------------------
System Initialization
*----------------------------------------------------------------------------*/
void SystemInit (void)
{
/* do not use global variables because this function is called before
reaching pre-main. RW section maybe overwritten afterwards. */
#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
// Enable FPU
__FPU_Enable();
#endif
// Enable SRAM write access
CPG.SYSCR3 = 0x0F;
RZ_A1_InitClock();
RZ_A1_InitBus();
// Invalidate entire Unified TLB
__set_TLBIALL(0);
// Invalidate entire branch predictor array
__set_BPIALL(0);
__DSB();
__ISB();
// Invalidate instruction cache and flush branch target cache
__set_ICIALLU(0);
__DSB();
__ISB();
// Invalidate data cache
L1C_InvalidateDCacheAll();
// Create Translation Table
MMU_CreateTranslationTable();
// Enable MMU
MMU_Enable();
// Enable Caches
L1C_EnableCaches();
L1C_EnableBTAC();
#if (__L2C_PRESENT == 1)
L2C_InvAllByWay();
// Enable L2C
L2C_Enable();
#endif
// IRQ Initialize
IRQ_Initialize();
}

81
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/device/system_VK_RZ_A1H.h
View File

@ -1,81 +0,0 @@
/******************************************************************************
* @file system_VK_RZ_A1H.h
* @brief CMSIS Device System Header File for ARM Cortex-A Device Series
* @version V1.00
* @date 10 Mar 2017
*
* @note
*
******************************************************************************/
/*
* Copyright (c) 2009-2017 ARM Limited. All rights reserved.
*
* SPDX-License-Identifier: Apache-2.0
*
* Licensed under the Apache License, Version 2.0 (the License); you may
* not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an AS IS BASIS, WITHOUT
* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef __SYSTEM_VK_RZ_A1H_H
#define __SYSTEM_VK_RZ_A1H_H
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
typedef void(*IRQHandler)(); /*!< Type Definition for Interrupt Handlers */
/**
\brief Setup the microcontroller system.
Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
/**
\brief Update SystemCoreClock variable.
Updates the SystemCoreClock with current core Clock retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
/**
\brief Interrupt Handler Register.
Registers an Interrupt Handler into the IRQ Table.
*/
extern uint32_t InterruptHandlerRegister(IRQn_Type, IRQHandler);
/**
\brief Interrupt Handler Unregister.
Unregisters an Interrupt Handler from the IRQ Table.
*/
extern uint32_t InterruptHandlerUnregister(IRQn_Type);
/**
\brief Create Translation Table.
Creates Memory Management Unit Translation Table.
*/
extern void MMU_CreateTranslationTable(void);
#ifdef __cplusplus
}
#endif
#endif /* __SYSTEM_VK_RZ_A1H_H */

42
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h
View File

@ -1,42 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2017 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_DRV_CFG_H
#define MBED_DRV_CFG_H
/* can_api.c */
#define CAN_TEST_GLOBAL_CH 1
/* gpio_api.c */
#define GPIO_GROUP_MAX 9
/* pwmout_api.c */
#define FUNC_MOTOR_CTL_PWM
#define FUMC_MTU2_PWM
/* rtc_api.c */
#define USE_RTCX1_CLK
//#define USE_EXTAL_CLK
//#define USE_RTCX3_CLK
#define RENESAS_RZ_A1_P0_CLK CM0_RENESAS_RZ_A1_P0_CLK
/* Clock Mode 0 */
/* CLKIN is between 10MHz and 13.33MHz */
/* Divider 1 uses 1/1 ratio, PLL x30 is ON */
#define RENESAS_RZ_A1_SYS_CLK (CM0_RENESAS_RZ_A1_CLKIN * 30U)
#endif

10
targets/TARGET_RENESAS/TARGET_RZ_A1XX/sleep.c
View File

@ -30,7 +30,7 @@ static volatile uint8_t wk_CPGSTBCR9;
static volatile uint8_t wk_CPGSTBCR10;
static volatile uint8_t wk_CPGSTBCR11;
static volatile uint8_t wk_CPGSTBCR12;
#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
#if defined(TARGET_RZA1H)
static volatile uint8_t wk_CPGSTBCR13;
#endif
static volatile uint8_t wk_CPGSTBREQ1;
@ -52,7 +52,7 @@ static const module_stanby_t module_stanby[] = {
{&wk_CPGSTBCR7, &CPGSTBCR7, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR7_BIT_MSTP74, CPG_STBREQ2_BIT_STBRQ26}, /* Ethernet */
{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP83, CPG_STBREQ2_BIT_STBRQ27}, /* MediaLB */
{&wk_CPGSTBCR9, &CPGSTBCR9, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR9_BIT_MSTP91, CPG_STBREQ2_BIT_STBRQ25}, /* VDC5_0 */
#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
#if defined(TARGET_RZA1H)
{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP85, CPG_STBREQ2_BIT_STBRQ21}, /* IMR-LSD */
{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP86, CPG_STBREQ2_BIT_STBRQ22}, /* IMR-LS2_1 */
{&wk_CPGSTBCR8, &CPGSTBCR8, &CPGSTBREQ2, &CPGSTBACK2, CPG_STBCR8_BIT_MSTP87, CPG_STBREQ2_BIT_STBRQ23}, /* IMR-LS2_0 */
@ -124,7 +124,7 @@ void hal_deepsleep(void) {
wk_CPGSTBCR10 = CPGSTBCR10;
wk_CPGSTBCR11 = CPGSTBCR11;
wk_CPGSTBCR12 = CPGSTBCR12;
#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
#if defined(TARGET_RZA1H)
wk_CPGSTBCR13 = CPGSTBCR13;
#endif
@ -165,7 +165,7 @@ void hal_deepsleep(void) {
dummy_8 = CPGSTBCR11;
CPGSTBCR12 = 0xFF;
dummy_8 = CPGSTBCR12;
#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
#if defined(TARGET_RZA1H)
CPGSTBCR13 = 0xFF;
dummy_8 = CPGSTBCR13;
#endif
@ -196,7 +196,7 @@ void hal_deepsleep(void) {
dummy_8 = CPGSTBCR11;
CPGSTBCR12 = wk_CPGSTBCR12;
dummy_8 = CPGSTBCR12;
#if defined(TARGET_RZA1H) || defined(TARGET_VK_RZ_A1H)
#if defined(TARGET_RZA1H)
CPGSTBCR13 = wk_CPGSTBCR13;
dummy_8 = CPGSTBCR13;
#endif

20
targets/targets.json
View File

@ -8801,26 +8801,6 @@
"5500"
]
},
"VK_RZ_A1H": {
"inherits": [
"RZ_A1XX"
],
"extra_labels_add": [
"RZA1H",
"VKRZA1H",
"RZ_A1_EMAC"
],
"device_has_add": [
"EMAC"
],
"release_versions": [
"2",
"5"
],
"detect_code": [
"C002"
]
},
"GR_LYCHEE": {
"inherits": [
"RZ_A1XX"