Merge pull request #6832 from bcostm/PULL_REQUEST_CUBE_UPDATE_F3_V1.9.0

STM32F3: Update with STM32CubeF3 V1.9.0

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f302x8.S

@@ -1,33 +1,41 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f302x8.s
-; STM32F302x8 Devices vector table for MDK ARM_MICRO toolchain
+;* Author             : MCD Application Team
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;* Description        : STM32F302x6/x8 devices vector table for MDK-ARM toolchain.
-; Copyright (c) 2014, STMicroelectronics
+;*                      This module performs:
-; All rights reserved.
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*
+;*******************************************************************************
 ;
-; Redistribution and use in source and binary forms, with or without
+;* Redistribution and use in source and binary forms, with or without modification,
-; modification, are permitted provided that the following conditions are met:
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;
-; 1. Redistributions of source code must retain the above copyright notice,
+;*******************************************************************************
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 ; Amount of memory (in bytes) allocated for Stack
 ; Tailor this value to your application needs

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_ARM_STD/startup_stm32f302x8.S

@@ -1,33 +1,41 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f302x8.s
-; STM32F302x8 Devices vector table for MDK ARM_STD toolchain
+;* Author             : MCD Application Team
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;* Description        : STM32F302x6/x8 devices vector table for MDK-ARM toolchain.
-; Copyright (c) 2014, STMicroelectronics
+;*                      This module performs:
-; All rights reserved.
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;*
+;*******************************************************************************
 ;
-; Redistribution and use in source and binary forms, with or without
+;* Redistribution and use in source and binary forms, with or without modification,
-; modification, are permitted provided that the following conditions are met:
+;* are permitted provided that the following conditions are met:
+;*   1. Redistributions of source code must retain the above copyright notice,
+;*      this list of conditions and the following disclaimer.
+;*   2. Redistributions in binary form must reproduce the above copyright notice,
+;*      this list of conditions and the following disclaimer in the documentation
+;*      and/or other materials provided with the distribution.
+;*   3. Neither the name of STMicroelectronics nor the names of its contributors
+;*      may be used to endorse or promote products derived from this software
+;*      without specific prior written permission.
+;*
+;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 ;
-; 1. Redistributions of source code must retain the above copyright notice,
+;*******************************************************************************
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
 
 __initial_sp    EQU     0x20004000 ; Top of RAM
 

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_GCC_ARM/startup_stm32f302x8.S

@@ -2,10 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f302x8.s
   * @author    MCD Application Team
-  * @version   V1.1.0
+  * @brief     STM32F302x6/STM32F302x8 devices vector table for GCC toolchain.
-  * @date      12-Sept-2014
-  * @brief     STM32F302x6/STM32F302x8 devices vector table for 
-  *            Atollic TrueSTUDIO toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -16,21 +13,28 @@
   *            After Reset the Cortex-M4 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * You may not use this file except in compliance with the License.
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * You may obtain a copy of the License at:
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  *
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  *        http://www.st.com/software_license_agreement_liberty_v2
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  *
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * Unless required by applicable law or agreed to in writing, software 
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * See the License for the specific language governing permissions and
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * limitations under the License.
   *
   ******************************************************************************
   */
@@ -50,6 +54,10 @@ defined in linker script */
 .word	_sdata
 /* end address for the .data section. defined in linker script */
 .word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
 
 .equ  BootRAM,        0xF1E0F85F
 /**
@@ -83,6 +91,17 @@ LoopCopyDataInit:
 	adds	r2, r0, r1
 	cmp	r2, r3
 	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
 
 /* Call the clock system intitialization function.*/
     bl  SystemInit

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/TOOLCHAIN_IAR/startup_stm32f302x8.S

@@ -1,8 +1,6 @@
 ;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f302x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F302x6/STM32F302x8 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/hal_tick.h

@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/stm32f302x8.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f302x8.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F302x8 Devices Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -7138,9 +7136,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
 #endif
 
+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
 #define EXTI_IMR2_IM_Pos           (0U)                                        
 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */
 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#else
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#endif
 
 /*******************  Bit definition for EXTI_EMR2 ****************************/
 #define EXTI_EMR2_MR32_Pos         (0U)                                        
@@ -7159,6 +7167,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
 #endif
 
+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#else
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#endif
+
 /******************  Bit definition for EXTI_RTSR2 register ********************/
 #define EXTI_RTSR2_TR32_Pos        (0U)                                        
 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
@@ -7408,21 +7430,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
 
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define OB_WRP2_WRP2_Pos     (0U)                                              
-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
-#define OB_WRP2_nWRP2_Pos    (8U)                                              
-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define OB_WRP3_WRP3_Pos     (16U)                                             
-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
-#define OB_WRP3_nWRP3_Pos    (24U)                                             
-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
 
 /******************************************************************************/
 /*                                                                            */
@@ -9059,9 +9066,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
+#define RTC_CR_BKP_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -9111,6 +9118,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -121,11 +119,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.2
   */
 #define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
 #define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\
                                        |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F302x8/device/system_stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303x8.S

@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F303x6/x8 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_ARM_STD/startup_stm32f303x8.S

@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F303x6/x8 devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_GCC_ARM/startup_stm32f303x8.S

@@ -2,10 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f303x8.s
   * @author    MCD Application Team
-  * @version   
+  * @brief     STM32F303x6/STM32F303x8 devices vector table for GCC toolchain.
-  * @date      12-Sept-2014
-  * @brief     STM32F303x6/STM32F303x8 devices vector table for 
-  *            Atollic TrueSTUDIO toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -16,21 +13,28 @@
   *            After Reset the Cortex-M4 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * You may not use this file except in compliance with the License.
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * You may obtain a copy of the License at:
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  *
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  *        http://www.st.com/software_license_agreement_liberty_v2
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  *
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * Unless required by applicable law or agreed to in writing, software 
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * See the License for the specific language governing permissions and
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * limitations under the License.
   *
   ******************************************************************************
   */
@@ -50,6 +54,10 @@ defined in linker script */
 .word	_sdata
 /* end address for the .data section. defined in linker script */
 .word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
 
 .equ  BootRAM,        0xF1E0F85F
 /**
@@ -83,6 +91,17 @@ LoopCopyDataInit:
 	adds	r2, r0, r1
 	cmp	r2, r3
 	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
 
 /* Call the clock system intitialization function.*/
     bl  SystemInit

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/TOOLCHAIN_IAR/startup_stm32f303x8.S

@@ -1,8 +1,6 @@
 ;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F303x6/STM32F303x8 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/hal_tick.h

@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/stm32f303x8.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f303x8.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F303x8 Devices Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -7152,9 +7150,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
 #endif
 
+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
 #define EXTI_IMR2_IM_Pos           (0U)                                        
 #define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */
 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#else
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#endif
 
 /*******************  Bit definition for EXTI_EMR2 ****************************/
 #define EXTI_EMR2_MR32_Pos         (0U)                                        
@@ -7173,6 +7181,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
 #endif
 
+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#else
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#endif
+
 /******************  Bit definition for EXTI_RTSR2 register ********************/
 #define EXTI_RTSR2_TR32_Pos        (0U)                                        
 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
@@ -7422,21 +7444,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
 
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define OB_WRP2_WRP2_Pos     (0U)                                              
-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
-#define OB_WRP2_nWRP2_Pos    (8U)                                              
-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define OB_WRP3_WRP3_Pos     (16U)                                             
-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
-#define OB_WRP3_nWRP3_Pos    (24U)                                             
-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
 
 /******************************************************************************/
 /*                                                                            */
@@ -9013,9 +9020,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
+#define RTC_CR_BKP_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -9065,6 +9072,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -9606,12 +9618,6 @@ typedef struct
 #define SPI_SR_TXE_Pos              (1U)                                       
 #define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)                                       
-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)                                       
-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
 #define SPI_SR_CRCERR_Pos           (4U)                                       
 #define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -121,11 +119,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.2
   */
 #define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
 #define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\
                                        |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303x8/device/system_stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xc.S

@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303xc.s
 ;* Author             : MCD Application Team
-;* Version            : $VERSION$
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F303xB/xC devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_ARM_STD/startup_stm32f303xc.S

@@ -1,8 +1,6 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303xc.s
 ;* Author             : MCD Application Team
-;* Version            : $VERSION$
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F303xB/xC devices vector table for MDK-ARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xc.S

@@ -2,10 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f303xc.s
   * @author    MCD Application Team
-  * @version   V1.1.0
+  * @brief     STM32F303xB/STM32F303xC devices vector table for GCC toolchain.
-  * @date      12-Sept-2014
-  * @brief     STM32F303xB/STM32F303xC devices vector table for Atollic 
-  *            TrueSTUDIO toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -16,21 +13,28 @@
   *            After Reset the Cortex-M4 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * You may not use this file except in compliance with the License.
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * You may obtain a copy of the License at:
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  *
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  *        http://www.st.com/software_license_agreement_liberty_v2
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  *
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * Unless required by applicable law or agreed to in writing, software 
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * See the License for the specific language governing permissions and
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * limitations under the License.
   *
   ******************************************************************************
   */
@@ -50,6 +54,10 @@ defined in linker script */
 .word	_sdata
 /* end address for the .data section. defined in linker script */
 .word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
 
 .equ  BootRAM,        0xF1E0F85F
 /**
@@ -83,6 +91,18 @@ LoopCopyDataInit:
 	adds	r2, r0, r1
 	cmp	r2, r3
 	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
+
 /* Call the clock system intitialization function.*/
     bl  SystemInit
 /* Call static constructors */

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/hal_tick.h

@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/stm32f303xc.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f303xc.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F303xC Devices Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -7912,6 +7910,10 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
 
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+
 /******************  Bit definition for EXTI_RTSR2 register ********************/
 #define EXTI_RTSR2_TR32_Pos        (0U)                                        
 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
@@ -9898,9 +9900,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
+#define RTC_CR_BKP_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -9950,6 +9952,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -121,11 +119,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.2
   */
 #define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
 #define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\
                                        |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/system_stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f303xe.S

@@ -1,9 +1,7 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303xe.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
+;* Description        : STM32F303xE devices vector table for MDK-ARM toolchain.
-;* Date               : 12-Sept-2014
-;* Description        : STM32F303xE devices vector table for MDK-ARM_MICRO toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_ARM_STD/startup_stm32f303xe.S

@@ -1,9 +1,7 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303xe.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
+;* Description        : STM32F303xE devices vector table for MDK-ARM toolchain.
-;* Date               : 12-Sept-2014
-;* Description        : STM32F303xE devices vector table for MDK-ARM_STD toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f303xe.S

@@ -2,10 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f303xe.s
   * @author    MCD Application Team
-  * @version   
+  * @brief     STM32F303xE devices vector table for GCC toolchain.
-  * @date      12-Sept-2014
-  * @brief     STM32F303xE devices vector table for Atollic 
-  *            TrueSTUDIO toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -16,21 +13,28 @@
   *            After Reset the Cortex-M4 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * You may not use this file except in compliance with the License.
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * You may obtain a copy of the License at:
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  *
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  *        http://www.st.com/software_license_agreement_liberty_v2
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  *
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * Unless required by applicable law or agreed to in writing, software 
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * See the License for the specific language governing permissions and
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * limitations under the License.
   *
   ******************************************************************************
   */
@@ -50,6 +54,10 @@ defined in linker script */
 .word	_sdata
 /* end address for the .data section. defined in linker script */
 .word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
 
 .equ  BootRAM,        0xF1E0F85F
 /**
@@ -83,6 +91,17 @@ LoopCopyDataInit:
 	adds	r2, r0, r1
 	cmp	r2, r3
 	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
 
 /* Call the clock system intitialization function.*/
     bl  SystemInit

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/TOOLCHAIN_IAR/startup_stm32f303xe.S

@@ -1,8 +1,6 @@
 ;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f303xe.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F303RE/STM32F303VE/STM32F303ZE devices vector table 
 ;*                      for EWARM toolchain.
 ;*                      This module performs:
@@ -16,8 +14,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/hal_tick.h

@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/stm32f303xe.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f303xe.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F303xE Devices Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -7918,6 +7916,10 @@ typedef struct
 #define EXTI_EMR2_EM34 EXTI_EMR2_MR34
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
 
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+
 /******************  Bit definition for EXTI_RTSR2 register ********************/
 #define EXTI_RTSR2_TR32_Pos        (0U)                                        
 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
@@ -11563,9 +11565,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
+#define RTC_CR_BKP_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -11615,6 +11617,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -121,11 +119,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.2
   */
 #define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
 #define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\
                                        |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xE/device/system_stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f334x8.S

@@ -1,9 +1,7 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f334x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
+;* Description        : STM32F334x4/x6/x8 devices vector table for MDK-ARM toolchain.
-;* Date               : 12-Sept-2014
-;* Description        : STM32F334x4/x6/x8 devices vector table for MDK-ARM_MICRO toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_ARM_STD/startup_stm32f334x8.S

@@ -1,9 +1,7 @@
 ;******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f334x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
+;* Description        : STM32F334x4/x6/x8 devices vector table for MDK-ARM toolchain.
-;* Date               : 12-Sept-2014
-;* Description        : STM32F334x4/x6/x8 devices vector table for MDK-ARM_STD toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
 ;*                      - Set the initial PC == Reset_Handler
@@ -12,7 +10,7 @@
 ;*                        calls main()).
 ;*                      After Reset the CortexM4 processor is in Thread mode,
 ;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
+;*
 ;*******************************************************************************
 ;
 ;* Redistribution and use in source and binary forms, with or without modification,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_GCC_ARM/startup_stm32f334x8.S

@@ -2,10 +2,7 @@
   ******************************************************************************
   * @file      startup_stm32f334x8.s
   * @author    MCD Application Team
-  * @version   V1.1.0
+  * @brief     STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for GCC toolchain.
-  * @date      12-Sept-2014
-  * @brief     STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for 
-  *            Atollic TrueSTUDIO toolchain.
   *            This module performs:
   *                - Set the initial SP
   *                - Set the initial PC == Reset_Handler,
@@ -16,21 +13,28 @@
   *            After Reset the Cortex-M4 processor is in Thread mode,
   *            priority is Privileged, and the Stack is set to Main.
   ******************************************************************************
-  * @attention
   *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of STMicroelectronics nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
   *
-  * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * You may not use this file except in compliance with the License.
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * You may obtain a copy of the License at:
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  *
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  *        http://www.st.com/software_license_agreement_liberty_v2
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  *
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * Unless required by applicable law or agreed to in writing, software 
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * distributed under the License is distributed on an "AS IS" BASIS, 
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * See the License for the specific language governing permissions and
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  * limitations under the License.
   *
   ******************************************************************************
   */
@@ -50,6 +54,10 @@ defined in linker script */
 .word	_sdata
 /* end address for the .data section. defined in linker script */
 .word	_edata
+/* start address for the .bss section. defined in linker script */
+.word	_sbss
+/* end address for the .bss section. defined in linker script */
+.word	_ebss
 
 .equ  BootRAM,        0xF1E0F85F
 /**
@@ -83,6 +91,17 @@ LoopCopyDataInit:
 	adds	r2, r0, r1
 	cmp	r2, r3
 	bcc	CopyDataInit
+	ldr	r2, =_sbss
+	b	LoopFillZerobss
+/* Zero fill the bss segment. */
+FillZerobss:
+	movs	r3, #0
+	str	r3, [r2], #4
+
+LoopFillZerobss:
+	ldr	r3, = _ebss
+	cmp	r2, r3
+	bcc	FillZerobss
 
 /* Call the clock system intitialization function.*/
     bl  SystemInit

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/TOOLCHAIN_IAR/startup_stm32f334x8.S

@@ -1,8 +1,6 @@
 ;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
 ;* File Name          : startup_stm32f334x8.s
 ;* Author             : MCD Application Team
-;* Version            : V2.1.0
-;* Date               : 12-Sept-2014
 ;* Description        : STM32F334x4/STM32F334x6/STM32F334x8 devices vector table for EWARM toolchain.
 ;*                      This module performs:
 ;*                      - Set the initial SP
@@ -15,8 +13,6 @@
 ;*                      priority is Privileged, and the Stack is set to Main.
 ;********************************************************************************
 ;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
 ;* Redistribution and use in source and binary forms, with or without modification,
 ;* are permitted provided that the following conditions are met:
 ;*   1. Redistributions of source code must retain the above copyright notice,

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/hal_tick.h

@@ -45,11 +45,11 @@
    
 #define TIM_MST      TIM2
 #define TIM_MST_IRQ  TIM2_IRQn
-#define TIM_MST_RCC  __TIM2_CLK_ENABLE()
+#define TIM_MST_RCC  __HAL_RCC_TIM2_CLK_ENABLE()
 #define TIM_MST_DBGMCU_FREEZE  __HAL_DBGMCU_FREEZE_TIM2()
 
-#define TIM_MST_RESET_ON   __TIM2_FORCE_RESET()
+#define TIM_MST_RESET_ON   __HAL_RCC_TIM2_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM2_RELEASE_RESET()
+#define TIM_MST_RESET_OFF  __HAL_RCC_TIM2_RELEASE_RESET()
 
 #define TIM_MST_16BIT  0 // 1=16-bit timer, 0=32-bit timer
 

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/stm32f334x8.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f334x8.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F334x8 Devices Peripheral Access Layer Header File.
   *
   *          This file contains:
@@ -7340,9 +7338,19 @@ typedef struct
 #define EXTI_IMR2_IM35 EXTI_IMR2_MR35
 #endif
 
+#if defined(EXTI_IMR2_MR33) && defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0xFU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000F */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#elif defined(EXTI_IMR2_MR34) && defined(EXTI_IMR2_MR35)
+#define EXTI_IMR2_IM_Pos           (0U)                                        
+#define EXTI_IMR2_IM_Msk           (0xDU << EXTI_IMR2_IM_Pos)                  /*!< 0x0000000D */
+#define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#else
 #define EXTI_IMR2_IM_Pos           (0U)                                        
 #define EXTI_IMR2_IM_Msk           (0x1U << EXTI_IMR2_IM_Pos)                  /*!< 0x00000001 */
 #define EXTI_IMR2_IM               EXTI_IMR2_IM_Msk                            
+#endif
 
 /*******************  Bit definition for EXTI_EMR2 ****************************/
 #define EXTI_EMR2_MR32_Pos         (0U)                                        
@@ -7361,6 +7369,20 @@ typedef struct
 #define EXTI_EMR2_EM35 EXTI_EMR2_MR35
 #endif
 
+#if defined(EXTI_EMR2_MR33) && defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xFU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000F */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#elif defined(EXTI_EMR2_MR34) && defined(EXTI_EMR2_MR35)
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0xDU << EXTI_EMR2_EM_Pos)                  /*!< 0x0000000D */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#else
+#define EXTI_EMR2_EM_Pos           (0U)                                        
+#define EXTI_EMR2_EM_Msk           (0x1U << EXTI_EMR2_EM_Pos)                  /*!< 0x00000001 */
+#define EXTI_EMR2_EM               EXTI_EMR2_EM_Msk                            
+#endif
+
 /******************  Bit definition for EXTI_RTSR2 register ********************/
 #define EXTI_RTSR2_TR32_Pos        (0U)                                        
 #define EXTI_RTSR2_TR32_Msk        (0x1U << EXTI_RTSR2_TR32_Pos)               /*!< 0x00000001 */
@@ -7610,21 +7632,6 @@ typedef struct
 #define OB_WRP1_nWRP1_Msk    (0xFFU << OB_WRP1_nWRP1_Pos)                      /*!< 0xFF000000 */
 #define OB_WRP1_nWRP1        OB_WRP1_nWRP1_Msk                                 /*!< Flash memory write protection complemented option bytes */
 
-/******************  Bit definition for FLASH_WRP2 register  ******************/
-#define OB_WRP2_WRP2_Pos     (0U)                                              
-#define OB_WRP2_WRP2_Msk     (0xFFU << OB_WRP2_WRP2_Pos)                       /*!< 0x000000FF */
-#define OB_WRP2_WRP2         OB_WRP2_WRP2_Msk                                  /*!< Flash memory write protection option bytes */
-#define OB_WRP2_nWRP2_Pos    (8U)                                              
-#define OB_WRP2_nWRP2_Msk    (0xFFU << OB_WRP2_nWRP2_Pos)                      /*!< 0x0000FF00 */
-#define OB_WRP2_nWRP2        OB_WRP2_nWRP2_Msk                                 /*!< Flash memory write protection complemented option bytes */
-
-/******************  Bit definition for FLASH_WRP3 register  ******************/
-#define OB_WRP3_WRP3_Pos     (16U)                                             
-#define OB_WRP3_WRP3_Msk     (0xFFU << OB_WRP3_WRP3_Pos)                       /*!< 0x00FF0000 */
-#define OB_WRP3_WRP3         OB_WRP3_WRP3_Msk                                  /*!< Flash memory write protection option bytes */
-#define OB_WRP3_nWRP3_Pos    (24U)                                             
-#define OB_WRP3_nWRP3_Msk    (0xFFU << OB_WRP3_nWRP3_Pos)                      /*!< 0xFF000000 */
-#define OB_WRP3_nWRP3        OB_WRP3_nWRP3_Msk                                 /*!< Flash memory write protection complemented option bytes */
 
 /******************************************************************************/
 /*                                                                            */
@@ -11959,9 +11966,9 @@ typedef struct
 #define RTC_CR_COSEL_Pos             (19U)                                     
 #define RTC_CR_COSEL_Msk             (0x1U << RTC_CR_COSEL_Pos)                /*!< 0x00080000 */
 #define RTC_CR_COSEL                 RTC_CR_COSEL_Msk                          
-#define RTC_CR_BCK_Pos               (18U)                                     
+#define RTC_CR_BKP_Pos               (18U)                                     
-#define RTC_CR_BCK_Msk               (0x1U << RTC_CR_BCK_Pos)                  /*!< 0x00040000 */
+#define RTC_CR_BKP_Msk               (0x1U << RTC_CR_BKP_Pos)                  /*!< 0x00040000 */
-#define RTC_CR_BCK                   RTC_CR_BCK_Msk                            
+#define RTC_CR_BKP                   RTC_CR_BKP_Msk                            
 #define RTC_CR_SUB1H_Pos             (17U)                                     
 #define RTC_CR_SUB1H_Msk             (0x1U << RTC_CR_SUB1H_Pos)                /*!< 0x00020000 */
 #define RTC_CR_SUB1H                 RTC_CR_SUB1H_Msk                          
@@ -12011,6 +12018,11 @@ typedef struct
 #define RTC_CR_WUCKSEL_1             (0x2U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000002 */
 #define RTC_CR_WUCKSEL_2             (0x4U << RTC_CR_WUCKSEL_Pos)              /*!< 0x00000004 */
 
+/* Legacy defines */
+#define RTC_CR_BCK_Pos               RTC_CR_BKP_Pos
+#define RTC_CR_BCK_Msk               RTC_CR_BKP_Msk
+#define RTC_CR_BCK                   RTC_CR_BKP
+
 /********************  Bits definition for RTC_ISR register  ******************/
 #define RTC_ISR_RECALPF_Pos          (16U)                                     
 #define RTC_ISR_RECALPF_Msk          (0x1U << RTC_ISR_RECALPF_Pos)             /*!< 0x00010000 */
@@ -12552,12 +12564,6 @@ typedef struct
 #define SPI_SR_TXE_Pos              (1U)                                       
 #define SPI_SR_TXE_Msk              (0x1U << SPI_SR_TXE_Pos)                   /*!< 0x00000002 */
 #define SPI_SR_TXE                  SPI_SR_TXE_Msk                             /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE_Pos           (2U)                                       
-#define SPI_SR_CHSIDE_Msk           (0x1U << SPI_SR_CHSIDE_Pos)                /*!< 0x00000004 */
-#define SPI_SR_CHSIDE               SPI_SR_CHSIDE_Msk                          /*!< Channel side */
-#define SPI_SR_UDR_Pos              (3U)                                       
-#define SPI_SR_UDR_Msk              (0x1U << SPI_SR_UDR_Pos)                   /*!< 0x00000008 */
-#define SPI_SR_UDR                  SPI_SR_UDR_Msk                             /*!< Underrun flag */
 #define SPI_SR_CRCERR_Pos           (4U)                                       
 #define SPI_SR_CRCERR_Msk           (0x1U << SPI_SR_CRCERR_Pos)                /*!< 0x00000010 */
 #define SPI_SR_CRCERR               SPI_SR_CRCERR_Msk                          /*!< CRC Error flag */

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS STM32F3xx Device Peripheral Access Layer Header File.           
   *            
   *          The file is the unique include file that the application programmer
@@ -121,11 +119,11 @@
 #endif /* USE_HAL_DRIVER */
 
 /**
-  * @brief CMSIS Device version number V2.3.1
+  * @brief CMSIS Device version number V2.3.2
   */
 #define __STM32F3_CMSIS_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
 #define __STM32F3_CMSIS_VERSION_SUB1   (0x03) /*!< [23:16] sub1 version */
-#define __STM32F3_CMSIS_VERSION_SUB2   (0x01) /*!< [15:8]  sub2 version */
+#define __STM32F3_CMSIS_VERSION_SUB2   (0x02) /*!< [15:8]  sub2 version */
 #define __STM32F3_CMSIS_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
 #define __STM32F3_CMSIS_VERSION        ((__STM32F3_CMSIS_VERSION_MAIN     << 24)\
                                        |(__STM32F3_CMSIS_VERSION_SUB1 << 16)\

targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F334x8/device/system_stm32f3xx.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    system_stm32f3xx.h
   * @author  MCD Application Team
-  * @version V2.3.1
-  * @date    16-December-2016
   * @brief   CMSIS Cortex-M4 Device System Source File for STM32F3xx devices.  
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/analogin_device.c

@@ -73,7 +73,7 @@ void analogin_init(analogin_t *obj, PinName pin)
     obj->handle.Init.Resolution            = ADC_RESOLUTION_12B;
     obj->handle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
     obj->handle.Init.ScanConvMode          = DISABLE;
-    obj->handle.Init.EOCSelection          = EOC_SINGLE_CONV;
+    obj->handle.Init.EOCSelection          = ADC_EOC_SINGLE_CONV;
     obj->handle.Init.LowPowerAutoWait      = DISABLE;
     obj->handle.Init.ContinuousConvMode    = DISABLE;
     obj->handle.Init.NbrOfConversion       = 1;
@@ -82,7 +82,7 @@ void analogin_init(analogin_t *obj, PinName pin)
     obj->handle.Init.ExternalTrigConv      = ADC_EXTERNALTRIGCONV_T1_CC1;
     obj->handle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
     obj->handle.Init.DMAContinuousRequests = DISABLE;
-    obj->handle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
+    obj->handle.Init.Overrun               = ADC_OVR_DATA_OVERWRITTEN;
 
 #if defined(ADC1)
     if ((ADCName)obj->handle.Instance == ADC_1) {

targets/TARGET_STM/TARGET_STM32F3/analogout_device.c

@@ -73,11 +73,11 @@ void analogout_init(dac_t *obj, PinName pin) {
 
     // Enable DAC clock
     if (obj->dac == DAC_1) {
-        __DAC1_CLK_ENABLE();
+        __HAL_RCC_DAC1_CLK_ENABLE();
     }
 #if defined(DAC2)
     if (obj->dac == DAC_2) {
-        __DAC2_CLK_ENABLE();
+        __HAL_RCC_DAC2_CLK_ENABLE();
     }
 #endif
 
@@ -121,16 +121,16 @@ void analogout_free(dac_t *obj) {
     if (obj->pin == PA_5) pa5_used = 0;
 
     if ((pa4_used == 0) && (pa5_used == 0)) {
-        __DAC1_FORCE_RESET();
+        __HAL_RCC_DAC1_FORCE_RESET();
-        __DAC1_RELEASE_RESET();
+        __HAL_RCC_DAC1_RELEASE_RESET();
-        __DAC1_CLK_DISABLE();
+        __HAL_RCC_DAC1_CLK_DISABLE();
     }
 
 #if defined(DAC2)
     if (obj->pin == PA_6) {
-        __DAC2_FORCE_RESET();
+        __HAL_RCC_DAC2_FORCE_RESET();
-        __DAC2_RELEASE_RESET();
+        __HAL_RCC_DAC2_RELEASE_RESET();
-        __DAC2_CLK_DISABLE();
+        __HAL_RCC_DAC2_CLK_DISABLE();
     }
 #endif
 

targets/TARGET_STM/TARGET_STM32F3/device/stm32_hal_legacy.h

@@ -2,14 +2,12 @@
   ******************************************************************************
   * @file    stm32_hal_legacy.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   This file contains aliases definition for the STM32Cube HAL constants 
   *          macros and functions maintained for legacy purpose.
   ******************************************************************************
   * @attention
   *
-  * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+  * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -382,7 +380,7 @@
 /** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
   * @{
   */
-#if defined(STM32L4) || defined(STM32F7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
 #define FMC_NAND_PCC_WAIT_FEATURE_DISABLE       FMC_NAND_WAIT_FEATURE_DISABLE
 #define FMC_NAND_PCC_WAIT_FEATURE_ENABLE        FMC_NAND_WAIT_FEATURE_ENABLE
 #define FMC_NAND_PCC_MEM_BUS_WIDTH_8            FMC_NAND_MEM_BUS_WIDTH_8
@@ -946,12 +944,9 @@
 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD        0x00000100U  /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD        0x00000200U  /* Rx FIFO fill level: fill-level above flow-control activate threshold */
 #define ETH_MAC_RXFIFO_FULL                   0x00000300U  /* Rx FIFO fill level: full */
-#if defined(STM32F1)
-#else
 #define ETH_MAC_READCONTROLLER_IDLE           0x00000000U  /* Rx FIFO read controller IDLE state */
 #define ETH_MAC_READCONTROLLER_READING_DATA   0x00000020U  /* Rx FIFO read controller Reading frame data */
 #define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U  /* Rx FIFO read controller Reading frame status (or time-stamp) */
-#endif
 #define ETH_MAC_READCONTROLLER_FLUSHING       0x00000060U  /* Rx FIFO read controller Flushing the frame data and status */
 #define ETH_MAC_RXFIFO_WRITE_ACTIVE           0x00000010U  /* Rx FIFO write controller active */
 #define ETH_MAC_SMALL_FIFO_NOTACTIVE          0x00000000U  /* MAC small FIFO read / write controllers not active */
@@ -980,7 +975,7 @@
   * @}
   */  
   
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
     defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
 /** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
   * @{
@@ -1005,7 +1000,7 @@
 /**
   * @}
   */    
-#endif  /* STM32L4xx ||  STM32F7*/
+#endif  /* STM32L4 ||  STM32F7*/
 
 /** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
   * @{
@@ -1190,6 +1185,9 @@
   * @{
   */ 
 #define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod           HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig  HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig  HAL_LTDCEx_StructInitFromAdaptedCommandConfig
 /**
   * @}
   */  
@@ -1625,7 +1623,11 @@
   
 #define __HAL_I2C_RESET_CR2             I2C_RESET_CR2
 #define __HAL_I2C_GENERATE_START        I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE            I2C_FREQRANGE
+#else
 #define __HAL_I2C_FREQ_RANGE            I2C_FREQ_RANGE
+#endif /* STM32F1 */
 #define __HAL_I2C_RISE_TIME             I2C_RISE_TIME
 #define __HAL_I2C_SPEED_STANDARD        I2C_SPEED_STANDARD
 #define __HAL_I2C_SPEED_FAST            I2C_SPEED_FAST
@@ -2792,6 +2794,15 @@
 #define RCC_SWPMI1CLKSOURCE_PCLK    RCC_SWPMI1CLKSOURCE_PCLK1
 #define RCC_LPTIM1CLKSOURCE_PCLK    RCC_LPTIM1CLKSOURCE_PCLK1
 #define RCC_LPTIM2CLKSOURCE_PCLK    RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1    RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2    RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2            RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2            RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB            RCC_FMPI2C1CLKSOURCE_PCLK1
+
 /**
   * @}
   */
@@ -2921,6 +2932,14 @@
 #define  SDIO_IRQn                  SDMMC1_IRQn
 #define  SDIO_IRQHandler            SDMMC1_IRQHandler
 #endif
+
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
+#define  HAL_SD_CardCIDTypedef       HAL_SD_CardCIDTypeDef
+#define  HAL_SD_CardCSDTypedef       HAL_SD_CardCSDTypeDef
+#define  HAL_SD_CardStatusTypedef    HAL_SD_CardStatusTypeDef
+#define  HAL_SD_CardStateTypedef     HAL_SD_CardStateTypeDef
+#endif
+
 /**
   * @}
   */
@@ -3109,6 +3128,7 @@
   * @{
   */
 #define __HAL_LTDC_LAYER LTDC_LAYER
+#define __HAL_LTDC_RELOAD_CONFIG  __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   HAL module driver.
   *          This is the common part of the HAL initialization
   *
@@ -70,10 +68,10 @@
   * @{
   */
 /**
- * @brief STM32F3xx HAL Driver version number V1.4.0
+ * @brief STM32F3xx HAL Driver version number V1.5.0
    */
 #define __STM32F3xx_HAL_VERSION_MAIN   (0x01U) /*!< [31:24] main version */
-#define __STM32F3xx_HAL_VERSION_SUB1   (0x04U) /*!< [23:16] sub1 version */
+#define __STM32F3xx_HAL_VERSION_SUB1   (0x05U) /*!< [23:16] sub1 version */
 #define __STM32F3xx_HAL_VERSION_SUB2   (0x00U) /*!< [15:8]  sub2 version */
 #define __STM32F3xx_HAL_VERSION_RC     (0x00U) /*!< [7:0]  release candidate */
 #define __STM32F3xx_HAL_VERSION         ((__STM32F3xx_HAL_VERSION_MAIN << 24U)\
@@ -231,7 +229,7 @@ __weak void HAL_MspDeInit(void)
   *         than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
   *         The function is declared as __Weak  to be overwritten  in case of other
   *         implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
+  * @param TickPriority Tick interrupt priority.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
@@ -306,13 +304,21 @@ __weak uint32_t HAL_GetTick(void)
   *         is incremented.
   *         The function is declared as __Weak  to be overwritten  in case of other
   *         implementations  in user file.
-  * @param  Delay: specifies the delay time length, in milliseconds.
+  * @param  Delay specifies the delay time length, in milliseconds.
   * @retval None
   */
 __weak void HAL_Delay(__IO uint32_t Delay)
 {
   uint32_t tickstart = HAL_GetTick();
-  while((HAL_GetTick() - tickstart) < Delay)
+  uint32_t wait = Delay;
+  
+  /* Add a period to guarantee minimum wait */
+  if (wait < HAL_MAX_DELAY)
+  {
+     wait++;
+  }
+  
+  while((HAL_GetTick() - tickstart) < wait)
   {
   }
 }
@@ -379,6 +385,33 @@ uint32_t HAL_GetDEVID(void)
   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
 }
 
+/**
+  * @brief  Returns first word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw0(void)
+{
+   return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+  * @brief  Returns second word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw1(void)
+{
+   return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+  * @brief  Returns third word of the unique device identifier (UID based on 96 bits)
+  * @retval Device identifier
+  */
+uint32_t HAL_GetUIDw2(void)
+{
+   return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
 /**
   * @brief  Enable the Debug Module during SLEEP mode
   * @retval None

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   This file contains all the functions prototypes for the HAL 
   *          module driver.
   ******************************************************************************
@@ -81,7 +79,7 @@
 /* --- CFGR2 Register ---*/
 /* Alias word address of BYP_ADDR_PAR bit */
 #define CFGR2_OFFSET                 (SYSCFG_OFFSET + 0x18U)
-#define BYPADDRPAR_BitNumber          0x04
+#define BYPADDRPAR_BitNumber          0x04U
 #define CFGR2_BYPADDRPAR_BB          (PERIPH_BB_BASE + (CFGR2_OFFSET * 32U) + (BYPADDRPAR_BitNumber * 4U))
 /**
   * @}
@@ -97,53 +95,53 @@
   * @{
   */
 #define HAL_REMAPDMA_ADC24_DMA2_CH34         (0x00000100U) /*!< ADC24 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
-                                                                          1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4U) */
+                                                                          1: Remap (ADC24 DMA requests mapped on DMA2 channels 3 and 4) */
 #define HAL_REMAPDMA_TIM16_DMA1_CH6          (0x00000800U) /*!< TIM16 DMA request remap
-                                                                         1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6U) */
+                                                                         1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA1 channel 6) */
 #define HAL_REMAPDMA_TIM17_DMA1_CH7          (0x00001000U) /*!< TIM17 DMA request remap
-                                                                         1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7U) */
+                                                                         1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA1 channel 7) */
 #define HAL_REMAPDMA_TIM6_DAC1_CH1_DMA1_CH3  (0x00002000U) /*!< TIM6 and DAC channel1 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
-                                                                         1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3U) */
+                                                                         1: Remap (TIM6_UP and DAC_CH1 DMA requests mapped on DMA1 channel 3) */
 #define HAL_REMAPDMA_TIM7_DAC1_CH2_DMA1_CH4  (0x00004000U) /*!< TIM7 and DAC channel2 DMA remap (STM32F303xB/C/E, STM32F358xx and STM32F398xx devices)
-                                                                         1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4U) */
+                                                                         1: Remap (TIM7_UP and DAC_CH2 DMA requests mapped on DMA1 channel 4) */
-#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5       (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_DAC2_CH1_DMA1_CH5       (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
-                                                                         1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */
+                                                                         1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
-#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_TIM18_DAC2_CH1_DMA1_CH5 (0x00008000U) /*!< DAC2 channel1 DMA remap (STM32F303x4/6/8 devices only)
-                                                                         1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5U) */
+                                                                         1: Remap (DAC2_CH1 DMA requests mapped on DMA1 channel 5) */
 #if defined(SYSCFG_CFGR3_DMA_RMP)
 #if !defined(HAL_REMAP_CFGR3_MASK) 
 #define HAL_REMAP_CFGR3_MASK                 (0x01000000U)
 #endif
 
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2        (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH2        (0x01000003U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         11: Map on DMA1 channel 2U */
+                                                                         11: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4        (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH4        (0x01000001U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         01: Map on DMA1 channel 4U */
+                                                                         01: Map on DMA1 channel 4 */
-#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6        (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_SPI1_RX_DMA1_CH6        (0x01000002U) /*!< SPI1_RX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         10: Map on DMA1 channel 6U */
+                                                                         10: Map on DMA1 channel 6 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3        (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH3        (0x0100000CU) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         11: Map on DMA1 channel 3U */
+                                                                         11: Map on DMA1 channel 3 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5        (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH5        (0x01000004U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         01: Map on DMA1 channel 5U */
+                                                                         01: Map on DMA1 channel 5 */
-#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7        (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_SPI1_TX_DMA1_CH7        (0x01000008U) /*!< SPI1_TX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         10: Map on DMA1 channel 7U */
+                                                                         10: Map on DMA1 channel 7 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7        (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH7        (0x01000030U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         11: Map on DMA1 channel 7U */
+                                                                         11: Map on DMA1 channel 7 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3        (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH3        (0x01000010U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         01: Map on DMA1 channel 3U */
+                                                                         01: Map on DMA1 channel 3 */
-#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5        (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_I2C1_RX_DMA1_CH5        (0x01000020U) /*!< I2C1_RX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         10: Map on DMA1 channel 5U */
+                                                                         10: Map on DMA1 channel 5 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6        (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH6        (0x010000C0U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         11: Map on DMA1 channel 6U */
+                                                                         11: Map on DMA1 channel 6 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2        (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH2        (0x01000040U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         01: Map on DMA1 channel 2U */
+                                                                         01: Map on DMA1 channel 2 */
-#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4        (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6U/8 devices only)
+#define HAL_REMAPDMA_I2C1_TX_DMA1_CH4        (0x01000080U) /*!< I2C1_TX DMA remap (STM32F303x4/6/8 devices only)
-                                                                         10: Map on DMA1 channel 4U */
+                                                                         10: Map on DMA1 channel 4 */
 #define HAL_REMAPDMA_ADC2_DMA1_CH2           (0x01000100U) /*!< ADC2 DMA remap
                                                                          x0: No remap (ADC2 on DMA2)
-                                                                         10: Map on DMA1 channel 2U */
+                                                                         10: Map on DMA1 channel 2 */
 #define HAL_REMAPDMA_ADC2_DMA1_CH4           (0x01000300U) /*!< ADC2 DMA remap
-                                                                         11: Map on DMA1 channel 4U */
+                                                                         11: Map on DMA1 channel 4 */
 #endif /* SYSCFG_CFGR3_DMA_RMP */
 
 #if defined(SYSCFG_CFGR3_DMA_RMP)
@@ -241,7 +239,7 @@
                                                                                  0: No remap (TIM2_CC1)
                                                                                  1: Remap (TIM20_TRGO) */
 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6       SYSCFG_CFGR4_ADC12_JEXT6_RMP  /*!< Input trigger of ADC12 injected channel JEXT6
-                                                                                 0: No remap (EXTI line 15U)
+                                                                                 0: No remap (EXTI line 15)
                                                                                  1: Remap (TIM20_TRGO2) */
 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13      SYSCFG_CFGR4_ADC12_JEXT13_RMP  /*!< Input trigger of ADC12 injected channel JEXT13
                                                                                  0: No remap (TIM3_CC1)
@@ -250,11 +248,11 @@
 #define IS_HAL_REMAPADCTRIGGER(RMP)  ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2)   == HAL_REMAPADCTRIGGER_ADC12_EXT2)   || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3)   == HAL_REMAPADCTRIGGER_ADC12_EXT3)   || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5)   == HAL_REMAPADCTRIGGER_ADC12_EXT5)   || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U)  == HAL_REMAPADCTRIGGER_ADC12_EXT13U)  || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13)  == HAL_REMAPADCTRIGGER_ADC12_EXT13)  || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U)  == HAL_REMAPADCTRIGGER_ADC12_EXT15U)  || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15)  == HAL_REMAPADCTRIGGER_ADC12_EXT15)  || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3)  == HAL_REMAPADCTRIGGER_ADC12_JEXT3)  || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6)  == HAL_REMAPADCTRIGGER_ADC12_JEXT6)  || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U))
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13))
 /**
   * @}
   */
@@ -283,13 +281,13 @@
                                                                                  0: No remap (TIM2_CC1)
                                                                                  1: Remap (TIM20_TRGO) */
 #define HAL_REMAPADCTRIGGER_ADC12_JEXT6       SYSCFG_CFGR4_ADC12_JEXT6_RMP  /*!< Input trigger of ADC12 injected channel JEXT6
-                                                                                 0: No remap (EXTI line 15U)
+                                                                                 0: No remap (EXTI line 15)
                                                                                  1: Remap (TIM20_TRGO2) */
 #define HAL_REMAPADCTRIGGER_ADC12_JEXT13      SYSCFG_CFGR4_ADC12_JEXT13_RMP  /*!< Input trigger of ADC12 injected channel JEXT13
                                                                                  0: No remap (TIM3_CC1)
                                                                                  1: Remap (TIM20_CC4) */
 #define HAL_REMAPADCTRIGGER_ADC34_EXT5        SYSCFG_CFGR4_ADC34_EXT5_RMP   /*!< Input trigger of ADC34 regular channel EXT5
-                                                                                 0: No remap (EXTI line 2U)
+                                                                                 0: No remap (EXTI line 2)
                                                                                  1: Remap (TIM20_TRGO) */
 #define HAL_REMAPADCTRIGGER_ADC34_EXT6        SYSCFG_CFGR4_ADC34_EXT6_RMP   /*!< Input trigger of ADC34 regular channel EXT6
                                                                                  0: No remap (TIM4_CC1)
@@ -310,17 +308,17 @@
 #define IS_HAL_REMAPADCTRIGGER(RMP)  ((((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT2)   == HAL_REMAPADCTRIGGER_ADC12_EXT2)   || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT3)   == HAL_REMAPADCTRIGGER_ADC12_EXT3)   || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT5)   == HAL_REMAPADCTRIGGER_ADC12_EXT5)   || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13U)  == HAL_REMAPADCTRIGGER_ADC12_EXT13U)  || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT13)  == HAL_REMAPADCTRIGGER_ADC12_EXT13)  || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15U)  == HAL_REMAPADCTRIGGER_ADC12_EXT15U)  || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_EXT15)  == HAL_REMAPADCTRIGGER_ADC12_EXT15)  || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT3)  == HAL_REMAPADCTRIGGER_ADC12_JEXT3)  || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT6)  == HAL_REMAPADCTRIGGER_ADC12_JEXT6)  || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13U) == HAL_REMAPADCTRIGGER_ADC12_JEXT13U) || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC12_JEXT13) == HAL_REMAPADCTRIGGER_ADC12_JEXT13) || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT5)   == HAL_REMAPADCTRIGGER_ADC34_EXT5)   || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT6)   == HAL_REMAPADCTRIGGER_ADC34_EXT6)   || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15U)  == HAL_REMAPADCTRIGGER_ADC34_EXT15U)  || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC34_EXT15)  == HAL_REMAPADCTRIGGER_ADC34_EXT15)  || \
                                       (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT5)  == HAL_REMAPADCTRIGGER_ADC34_JEXT5)  || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11U) == HAL_REMAPADCTRIGGER_ADC34_JEXT11U) || \
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT11) == HAL_REMAPADCTRIGGER_ADC34_JEXT11) || \
-                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14U) == HAL_REMAPADCTRIGGER_ADC34_JEXT14U))
+                                      (((RMP) & HAL_REMAPADCTRIGGER_ADC34_JEXT14) == HAL_REMAPADCTRIGGER_ADC34_JEXT14))
 /**
   * @}
   */
@@ -356,26 +354,26 @@
 /** @defgroup HAL_Page_Write_Protection HAL CCM RAM page write protection
   * @{
   */
-#define HAL_SYSCFG_WP_PAGE0                    (SYSCFG_RCR_PAGE0)  /*!< ICODE SRAM Write protection page 0U */
+#define HAL_SYSCFG_WP_PAGE0                    (SYSCFG_RCR_PAGE0)  /*!< ICODE SRAM Write protection page 0 */
-#define HAL_SYSCFG_WP_PAGE1                    (SYSCFG_RCR_PAGE1)  /*!< ICODE SRAM Write protection page 1U */
+#define HAL_SYSCFG_WP_PAGE1                    (SYSCFG_RCR_PAGE1)  /*!< ICODE SRAM Write protection page 1 */
-#define HAL_SYSCFG_WP_PAGE2                    (SYSCFG_RCR_PAGE2)  /*!< ICODE SRAM Write protection page 2U */
+#define HAL_SYSCFG_WP_PAGE2                    (SYSCFG_RCR_PAGE2)  /*!< ICODE SRAM Write protection page 2 */
-#define HAL_SYSCFG_WP_PAGE3                    (SYSCFG_RCR_PAGE3)  /*!< ICODE SRAM Write protection page 3U */
+#define HAL_SYSCFG_WP_PAGE3                    (SYSCFG_RCR_PAGE3)  /*!< ICODE SRAM Write protection page 3 */
 #if defined(SYSCFG_RCR_PAGE4)
 /* More than 4KB CCM-SRAM defined */
-#define HAL_SYSCFG_WP_PAGE4                    (SYSCFG_RCR_PAGE4)  /*!< ICODE SRAM Write protection page 4U */
+#define HAL_SYSCFG_WP_PAGE4                    (SYSCFG_RCR_PAGE4)  /*!< ICODE SRAM Write protection page 4 */
-#define HAL_SYSCFG_WP_PAGE5                    (SYSCFG_RCR_PAGE5)  /*!< ICODE SRAM Write protection page 5U */
+#define HAL_SYSCFG_WP_PAGE5                    (SYSCFG_RCR_PAGE5)  /*!< ICODE SRAM Write protection page 5 */
-#define HAL_SYSCFG_WP_PAGE6                    (SYSCFG_RCR_PAGE6)  /*!< ICODE SRAM Write protection page 6U */
+#define HAL_SYSCFG_WP_PAGE6                    (SYSCFG_RCR_PAGE6)  /*!< ICODE SRAM Write protection page 6 */
-#define HAL_SYSCFG_WP_PAGE7                    (SYSCFG_RCR_PAGE7)  /*!< ICODE SRAM Write protection page 7U */
+#define HAL_SYSCFG_WP_PAGE7                    (SYSCFG_RCR_PAGE7)  /*!< ICODE SRAM Write protection page 7 */
 #endif /* SYSCFG_RCR_PAGE4 */
 #if defined(SYSCFG_RCR_PAGE8)
-#define HAL_SYSCFG_WP_PAGE8                    (SYSCFG_RCR_PAGE8)  /*!< ICODE SRAM Write protection page 8U */
+#define HAL_SYSCFG_WP_PAGE8                    (SYSCFG_RCR_PAGE8)  /*!< ICODE SRAM Write protection page 8 */
-#define HAL_SYSCFG_WP_PAGE9                    (SYSCFG_RCR_PAGE9)  /*!< ICODE SRAM Write protection page 9U */
+#define HAL_SYSCFG_WP_PAGE9                    (SYSCFG_RCR_PAGE9)  /*!< ICODE SRAM Write protection page 9 */
-#define HAL_SYSCFG_WP_PAGE10                   (SYSCFG_RCR_PAGE10U) /*!< ICODE SRAM Write protection page 10U */
+#define HAL_SYSCFG_WP_PAGE10                   (SYSCFG_RCR_PAGE10) /*!< ICODE SRAM Write protection page 10 */
-#define HAL_SYSCFG_WP_PAGE11                   (SYSCFG_RCR_PAGE11U) /*!< ICODE SRAM Write protection page 11U */
+#define HAL_SYSCFG_WP_PAGE11                   (SYSCFG_RCR_PAGE11) /*!< ICODE SRAM Write protection page 11 */
-#define HAL_SYSCFG_WP_PAGE12                   (SYSCFG_RCR_PAGE12U) /*!< ICODE SRAM Write protection page 12U */
+#define HAL_SYSCFG_WP_PAGE12                   (SYSCFG_RCR_PAGE12) /*!< ICODE SRAM Write protection page 12 */
-#define HAL_SYSCFG_WP_PAGE13                   (SYSCFG_RCR_PAGE13U) /*!< ICODE SRAM Write protection page 13U */
+#define HAL_SYSCFG_WP_PAGE13                   (SYSCFG_RCR_PAGE13) /*!< ICODE SRAM Write protection page 13 */
-#define HAL_SYSCFG_WP_PAGE14                   (SYSCFG_RCR_PAGE14U) /*!< ICODE SRAM Write protection page 14U */
+#define HAL_SYSCFG_WP_PAGE14                   (SYSCFG_RCR_PAGE14) /*!< ICODE SRAM Write protection page 14 */
-#define HAL_SYSCFG_WP_PAGE15                   (SYSCFG_RCR_PAGE15U) /*!< ICODE SRAM Write protection page 15U */
+#define HAL_SYSCFG_WP_PAGE15                   (SYSCFG_RCR_PAGE15) /*!< ICODE SRAM Write protection page 15 */
 #endif /* SYSCFG_RCR_PAGE8 */
 
 #if defined(SYSCFG_RCR_PAGE8)
@@ -632,7 +630,7 @@
   */
 #if defined(SYSCFG_CFGR3_DMA_RMP) && defined(SYSCFG_CFGR1_DMA_RMP)
 /** @brief  DMA remapping enable/disable macros
-  * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
+  * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
   */
 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)   do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
                                                            (((__DMA_REMAP__) & HAL_REMAP_CFGR3_MASK) ?                      \
@@ -646,7 +644,7 @@
                                                          }while(0U)
 #elif defined(SYSCFG_CFGR1_DMA_RMP)
 /** @brief  DMA remapping enable/disable macros
-  * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping
+  * @param __DMA_REMAP__ This parameter can be a value of @ref HAL_DMA_Remapping
   */
 #define __HAL_DMA_REMAP_CHANNEL_ENABLE(__DMA_REMAP__)   do {assert_param(IS_DMA_REMAP((__DMA_REMAP__)));                  \
                                                            SYSCFG->CFGR1 |= (__DMA_REMAP__);                                \
@@ -663,7 +661,7 @@
   * @{
   */
 /** @brief  Fast-mode Plus driving capability enable/disable macros
-  * @param __FASTMODEPLUS__: This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
+  * @param __FASTMODEPLUS__ This parameter can be a value of @ref SYSCFG_FastModePlus_GPIO values.
   *                          That you can find above these macros.
   */
 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__)  do {assert_param(IS_SYSCFG_FASTMODEPLUS((__FASTMODEPLUS__)));\
@@ -681,7 +679,7 @@
   * @{
   */
 /** @brief  SYSCFG interrupt enable/disable macros
-  * @param __INTERRUPT__: This parameter can be a value of @ref HAL_SYSCFG_Interrupts
+  * @param __INTERRUPT__ This parameter can be a value of @ref HAL_SYSCFG_Interrupts
   */
 #define __HAL_SYSCFG_INTERRUPT_ENABLE(__INTERRUPT__)        do {assert_param(IS_HAL_SYSCFG_INTERRUPT((__INTERRUPT__))); \
                                                                 SYSCFG->CFGR1 |= (__INTERRUPT__);                       \
@@ -773,7 +771,7 @@
   */
 #if defined(SYSCFG_CFGR3_TRIGGER_RMP)
 /** @brief  Trigger remapping enable/disable macros
-  * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
+  * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
   */
 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__)   do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
                                                            (((__TRIGGER_REMAP__) & HAL_REMAP_CFGR3_MASK) ?                     \
@@ -787,7 +785,7 @@
                                                          }while(0U)
 #else
 /** @brief  Trigger remapping enable/disable macros
-  * @param __TRIGGER_REMAP__: This parameter can be a value of @ref HAL_Trigger_Remapping
+  * @param __TRIGGER_REMAP__ This parameter can be a value of @ref HAL_Trigger_Remapping
   */
 #define __HAL_REMAPTRIGGER_ENABLE(__TRIGGER_REMAP__)   do {assert_param(IS_HAL_REMAPTRIGGER((__TRIGGER_REMAP__)));             \
                                                            (SYSCFG->CFGR1 |= (__TRIGGER_REMAP__));                           \
@@ -805,7 +803,7 @@
   * @{
   */
 /** @brief  ADC trigger remapping enable/disable macros
-  * @param __ADCTRIGGER_REMAP__: This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
+  * @param __ADCTRIGGER_REMAP__ This parameter can be a value of @ref HAL_ADC_Trigger_Remapping
   */
 #define __HAL_REMAPADCTRIGGER_ENABLE(__ADCTRIGGER_REMAP__)   do {assert_param(IS_HAL_REMAPADCTRIGGER((__ADCTRIGGER_REMAP__)));   \
                                                              (SYSCFG->CFGR4 |= (__ADCTRIGGER_REMAP__));                          \
@@ -838,7 +836,7 @@
   * @{
   */
 /** @brief  CCM RAM page write protection enable macro
-  * @param __PAGE_WP__: This parameter can be a value of @ref HAL_Page_Write_Protection
+  * @param __PAGE_WP__ This parameter can be a value of @ref HAL_Page_Write_Protection
   * @note   write protection can only be disabled by a system reset
   */
 #define __HAL_SYSCFG_SRAM_WRP_ENABLE(__PAGE_WP__)      do {assert_param(IS_HAL_SYSCFG_WP_PAGE((__PAGE_WP__))); \
@@ -884,6 +882,9 @@ uint32_t HAL_GetTick(void);
 uint32_t HAL_GetHalVersion(void);
 uint32_t HAL_GetREVID(void);
 uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
 void     HAL_DBGMCU_EnableDBGSleepMode(void);
 void     HAL_DBGMCU_DisableDBGSleepMode(void);
 void     HAL_DBGMCU_EnableDBGStopMode(void);

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_adc.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
@@ -416,7 +414,7 @@
   *         bypassed without error reporting: it can be the intended behaviour in
   *         case of update of a parameter of ADC_InitTypeDef on the fly,
   *         without  disabling the other ADCs sharing the same common group.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -447,7 +445,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   *         let commented below.
   *         If needed, the example code can be copied and uncommented into
   *         function HAL_ADC_MspDeInit().
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -464,7 +462,7 @@ __weak HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
     
 /**
   * @brief  Initializes the ADC MSP.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
@@ -479,7 +477,7 @@ __weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  DeInitializes the ADC MSP.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
@@ -525,7 +523,7 @@ __weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
   *         function must be called for ADC slave first, then ADC master. 
   *         For ADC slave, ADC is enabled only (conversion is not started).  
   *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -548,7 +546,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
   *         For ADC master, converson is stopped and ADC is disabled. 
   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
   *         has already stopped conversion of ADC slave).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 __weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -565,8 +563,8 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Wait for regular group conversion to be completed.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -584,15 +582,15 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint
 
 /**
   * @brief  Poll for conversion event.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  EventType: the ADC event type.
+  * @param  EventType the ADC event type.
   *          This parameter can be one of the following values:
   *            @arg ADC_AWD_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
   *            @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, present only on STM32F3 devices)
   *            @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, present only on STM32F3 devices)
   *            @arg ADC_OVR_EVENT: ADC Overrun event
   *            @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -621,7 +619,7 @@ __weak HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t
   *         function must be called for ADC slave first, then ADC master. 
   *         For ADC slave, ADC is enabled only (conversion is not started).  
   *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -648,7 +646,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   *         For ADC master, conversion is stopped and ADC is disabled. 
   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
   *         has already stopped conversion of ADC slave).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -674,9 +672,9 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
   * @note:  Case of multimode enabled (for devices with several ADCs): This 
   *         function is for single-ADC mode only. For multimode, use the 
   *         dedicated MultimodeStart function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  pData: The destination Buffer address.
+  * @param  pData The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
   * @retval None
   */
 __weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -703,7 +701,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pD
   * @note:  Case of multimode enabled (for devices with several ADCs): This 
   *         function is for single-ADC mode only. For multimode, use the 
   *         dedicated MultimodeStop function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 __weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -724,7 +722,7 @@ __weak HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
   *         regular group) flag.
   *         Additionally, this functions clears EOS (end of sequence of
   *         regular group) flag, in case of the end of the sequence is reached.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval Converted value
   */
 __weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -738,7 +736,7 @@ __weak uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Handles ADC interrupt request.  
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -752,7 +750,7 @@ __weak void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Conversion complete callback in non blocking mode 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
@@ -767,7 +765,7 @@ __weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Conversion DMA half-transfer callback in non blocking mode 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
@@ -782,7 +780,7 @@ __weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Analog watchdog callback in non blocking mode. 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
@@ -798,7 +796,7 @@ __weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
 /**
   * @brief  ADC error callback in non blocking mode
   *        (ADC conversion with interruption or transfer by DMA)
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
@@ -849,8 +847,8 @@ __weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_ChannelConfTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  sConfig: Structure of ADC channel for regular group.
+  * @param  sConfig Structure of ADC channel for regular group.
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -876,8 +874,8 @@ __weak HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_Chan
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_AnalogWDGConfTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
+  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
   * @retval HAL status
   */
 __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -921,7 +919,7 @@ __weak HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_An
   *         For example:                                                         
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_REG_BUSY)) "
   *           " if (HAL_IS_BIT_SET(HAL_ADC_GetState(hadc1), HAL_ADC_STATE_AWD1)    ) "
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL state
   */
 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
@@ -935,7 +933,7 @@ uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Return the ADC error code
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval ADC Error Code
   */
 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_adc.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file containing functions prototypes of ADC HAL library.
   ******************************************************************************
   * @attention
@@ -142,7 +140,7 @@ typedef struct __ADC_HandleTypeDef
   * @{
   */
 /** @brief  Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_adc_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   This file provides firmware functions to manage the following 
   *          functionalities of the Analog to Digital Convertor (ADC)
   *          peripheral:
@@ -246,7 +244,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma);
   *         bypassed without error reporting: it can be the intended behaviour in
   *         case of update of a parameter of ADC_InitTypeDef on the fly,
   *         without  disabling the other ADCs sharing the same common group.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -567,7 +565,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   * @note   This function configures the ADC within 2 scopes: scope of entire 
   *         ADC and scope of regular group. For parameters details, see comments 
   *         of structure "ADC_InitTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
@@ -785,7 +783,7 @@ HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
   *         let commented below.
   *         If needed, the example code can be copied and uncommented into
   *         function HAL_ADC_MspDeInit().
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -1010,7 +1008,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
 #if defined(STM32F373xC) || defined(STM32F378xx)
 /**
   * @brief  Deinitialize the ADC peripheral registers to its default reset values.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
@@ -1200,7 +1198,7 @@ HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
   * @note   Case of multimode enabled (for devices with several ADCs):
   *         if ADC is slave, ADC is enabled only (conversion is not started).
   *         if ADC is master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -1314,7 +1312,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Enables ADC, starts conversion of regular group.
   *         Interruptions enabled in this function: None.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
@@ -1406,7 +1404,7 @@ HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
   *         To stop ADC conversion only on ADC group regular
   *         while letting ADC group injected conversions running,
   *         use function @ref HAL_ADCEx_RegularStop().
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -1456,7 +1454,7 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
   * @note   ADC peripheral disable is forcing interruption of potential 
   *         conversion on injected group. If injected group is under use, it
   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
@@ -1508,8 +1506,8 @@ HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
   *         performed on each conversion. Nevertheless, polling can still 
   *         be performed on the complete sequence (ADC init
   *         parameter "EOCSelection" set to ADC_EOC_SEQ_CONV).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @note   Depending on init parameter "EOCSelection", flags EOS or EOC is 
   *         checked and cleared depending on autodelay status (bit AUTDLY).     
   * @retval HAL status
@@ -1674,8 +1672,8 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
   *         (several ranks selected): polling cannot be done on each 
   *         conversion inside the sequence. In this case, polling is replaced by
   *         wait for maximum conversion time.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -1806,15 +1804,15 @@ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Ti
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /**
   * @brief  Poll for conversion event.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  EventType: the ADC event type.
+  * @param  EventType the ADC event type.
   *          This parameter can be one of the following values:
   *            @arg ADC_AWD1_EVENT: ADC Analog watchdog 1 event (main analog watchdog, present on all STM32 devices)
   *            @arg ADC_AWD2_EVENT: ADC Analog watchdog 2 event (additional analog watchdog, not present on all STM32 families)
   *            @arg ADC_AWD3_EVENT: ADC Analog watchdog 3 event (additional analog watchdog, not present on all STM32 families)
   *            @arg ADC_OVR_EVENT: ADC Overrun event
   *            @arg ADC_JQOVF_EVENT: ADC Injected context queue overflow event
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -1928,11 +1926,11 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
 #if defined(STM32F373xC) || defined(STM32F378xx)
 /**
   * @brief  Poll for conversion event.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  EventType: the ADC event type.
+  * @param  EventType the ADC event type.
   *          This parameter can be one of the following values:
   *            @arg ADC_AWD_EVENT: ADC Analog watchdog event.
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
@@ -1992,7 +1990,7 @@ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventTy
   *         function must be called for ADC slave first, then ADC master. 
   *         For ADC slave, ADC is enabled only (conversion is not started).  
   *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -2132,7 +2130,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   *         Interruptions enabled in this function:
   *          - EOC (end of conversion of regular group)
   *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
@@ -2229,7 +2227,7 @@ HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
   *         To stop ADC conversion only on ADC group regular
   *         while letting ADC group injected conversions running,
   *         use function @ref HAL_ADCEx_RegularStop_IT().
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -2281,7 +2279,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
   * @brief  Stop ADC conversion of regular group (and injected group in 
   *         case of auto_injection mode), disable interrution of 
   *         end-of-conversion, disable ADC peripheral.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
@@ -2333,9 +2331,9 @@ HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
   * @note   Case of multimode enabled (for devices with several ADCs): This 
   *         function is for single-ADC mode only. For multimode, use the 
   *         dedicated MultimodeStart function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  pData: The destination Buffer address.
+  * @param  pData The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -2486,9 +2484,9 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
   *         Each of these interruptions has its dedicated callback function.
   * @note   For devices with several ADCs: This function is for single-ADC mode 
   *         only. For multimode, use the dedicated MultimodeStart function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  pData: The destination Buffer address.
+  * @param  pData The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -2606,7 +2604,7 @@ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, ui
   * @note   Case of multimode enabled (for devices with several ADCs): This 
   *         function is for single-ADC mode only. For multimode, use the 
   *         dedicated MultimodeStop function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -2686,7 +2684,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
   *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
   * @note   For devices with several ADCs: This function is for single-ADC mode 
   *         only. For multimode, use the dedicated MultimodeStop function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
@@ -2756,7 +2754,7 @@ HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
   *         model polling: @ref HAL_ADC_PollForConversion() 
   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval ADC group regular conversion data
   */
 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -2792,7 +2790,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
   *         model polling: @ref HAL_ADC_PollForConversion() 
   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_EOS).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval ADC group regular conversion data
   */
 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
@@ -2814,7 +2812,7 @@ uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /**
   * @brief  Handles ADC interrupt request.  
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -3114,7 +3112,7 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
 #if defined(STM32F373xC) || defined(STM32F378xx)
 /**
   * @brief  Handles ADC interrupt request  
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
@@ -3237,8 +3235,8 @@ void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
   * @brief  Perform an ADC automatic self-calibration
   *         Calibration prerequisite: ADC must be disabled (execute this
   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  SingleDiff: Selection of single-ended or differential input
+  * @param  SingleDiff Selection of single-ended or differential input
   *          This parameter can be one of the following values:
   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
@@ -3301,11 +3299,6 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
                       HAL_ADC_STATE_BUSY_INTERNAL,
                       HAL_ADC_STATE_READY);
   }
-  else
-  {
-    /* Update ADC state machine to error */
-    tmp_hal_status = HAL_ERROR;
-  }
   
   /* Process unlocked */
   __HAL_UNLOCK(hadc);
@@ -3325,7 +3318,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc, uint32_t
   *         function before HAL_ADC_Start() or after HAL_ADC_Stop() ).
   *         During calibration process, ADC is enabled. ADC is let enabled at
   *         the completion of this function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
@@ -3431,8 +3424,8 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_Start(ADC_HandleTypeDef* hadc)
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /**
   * @brief  Get the calibration factor from automatic conversion result
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  SingleDiff: Selection of single-ended or differential input
+  * @param  SingleDiff Selection of single-ended or differential input
   *          This parameter can be one of the following values:
   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
@@ -3465,12 +3458,12 @@ uint32_t HAL_ADCEx_Calibration_GetValue(ADC_HandleTypeDef* hadc, uint32_t Single
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /**
   * @brief  Set the calibration factor to overwrite automatic conversion result. ADC must be enabled and no conversion on going.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  SingleDiff: Selection of single-ended or differential input
+  * @param  SingleDiff Selection of single-ended or differential input
   *          This parameter can be one of the following values:
   *            @arg ADC_SINGLE_ENDED: Channel in mode input single ended
   *            @arg ADC_DIFFERENTIAL_ENDED: Channel in mode input differential ended
-  * @param  CalibrationFactor: Calibration factor (coded on 7 bits maximum)
+  * @param  CalibrationFactor Calibration factor (coded on 7 bits maximum)
   * @retval HAL state
   */
 HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32_t SingleDiff, uint32_t CalibrationFactor)
@@ -3535,7 +3528,7 @@ HAL_StatusTypeDef HAL_ADCEx_Calibration_SetValue(ADC_HandleTypeDef* hadc, uint32
   *         function must be called for ADC slave first, then ADC master. 
   *         For ADC slave, ADC is enabled only (conversion is not started).  
   *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
@@ -3632,7 +3625,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
 /**
   * @brief  Enables ADC, starts conversion of injected group.
   *         Interruptions enabled in this function: None.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
@@ -3723,7 +3716,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
   *         has already stopped conversion of ADC slave).
   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
@@ -3808,7 +3801,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
   *         regular group, function HAL_ADC_Stop must be used to stop both
   *         injected and regular groups, and disable the ADC.
   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
@@ -3865,8 +3858,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
     defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
 /**
   * @brief  Wait for injected group conversion to be completed.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -3964,8 +3957,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
 #if defined(STM32F373xC) || defined(STM32F378xx)
 /**
   * @brief  Wait for injected group conversion to be completed.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  Timeout: Timeout value in millisecond.
+  * @param  Timeout Timeout value in millisecond.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
@@ -4093,7 +4086,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, u
   *         function must be called for ADC slave first, then ADC master. 
   *         For ADC slave, ADC is enabled only (conversion is not started).  
   *         For ADC master, ADC is enabled and multimode conversion is started.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
@@ -4213,7 +4206,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
   *         Interruptions enabled in this function:
   *          - JEOC (end of conversion of injected group)
   *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
@@ -4313,7 +4306,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
   *         For ADC slave, ADC is disabled only (conversion stop of ADC master
   *         has already stopped conversion of ADC slave).
   * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
@@ -4401,7 +4394,7 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
   * @note   If ADC must be disabled and if conversion is on going on 
   *         regular group, function HAL_ADC_Stop must be used to stop both
   *         injected and regular groups, and disable the ADC.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
@@ -4471,9 +4464,9 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
   *         Each of these interruptions has its dedicated callback function.
   * @note   ADC slave must be preliminarily enabled using single-mode  
   *         HAL_ADC_Start() function.
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
-  * @param  pData: The destination Buffer address.
+  * @param  pData The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
+  * @param  Length The length of data to be transferred from ADC peripheral to memory.
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
@@ -4613,7 +4606,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t
   * @note   In case of DMA configured in circular mode, function 
   *         HAL_ADC_Stop_DMA must be called after this function with handle of
   *         ADC slave, to properly disable the DMA channel of ADC slave.
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
@@ -4733,7 +4726,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc)
   * @note   Reading register CDR does not clear flag ADC flag EOC
   *         (ADC group regular end of unitary conversion),
   *         as it is the case for independent mode data register.
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
   * @retval The converted data value.
   */
 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
@@ -4778,8 +4771,8 @@ uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc)
   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion() 
   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  InjectedRank: the converted ADC injected rank.
+  * @param  InjectedRank the converted ADC injected rank.
   *          This parameter can be one of the following values:
   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
@@ -4844,8 +4837,8 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
   *         in programming model IT: @ref HAL_ADC_IRQHandler(), in programming
   *         model polling: @ref HAL_ADCEx_InjectedPollForConversion() 
   *         or @ref __HAL_ADC_CLEAR_FLAG(&hadc, ADC_FLAG_JEOS).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  InjectedRank: the converted ADC injected rank.
+  * @param  InjectedRank the converted ADC injected rank.
   *          This parameter can be one of the following values:
   *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
   *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
@@ -4898,7 +4891,7 @@ uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRa
   *         use function @ref HAL_ADC_Stop().
   * @note   In case of auto-injection mode, this function also stop conversion
   *         on ADC group injected.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
@@ -4972,7 +4965,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop(ADC_HandleTypeDef* hadc)
   *         use function @ref HAL_ADC_Stop().
   * @note   In case of auto-injection mode, this function also stop conversion
   *         on ADC group injected.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
@@ -5052,7 +5045,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_IT(ADC_HandleTypeDef* hadc)
   * @note   Case of multimode enabled (for devices with several ADCs): This 
   *         function is for single-ADC mode only. For multimode, use the 
   *         dedicated MultimodeStop function.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
@@ -5164,7 +5157,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularStop_DMA(ADC_HandleTypeDef* hadc)
   * @note   In case of DMA configured in circular mode, function 
   *         HAL_ADC_Stop_DMA must be called after this function with handle of
   *         ADC slave, to properly disable the DMA channel of ADC slave.
-  * @param  hadc: ADC handle of ADC master (handle of ADC slave must not be used)
+  * @param  hadc ADC handle of ADC master (handle of ADC slave must not be used)
   * @retval None
   */
 HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
@@ -5309,7 +5302,7 @@ HAL_StatusTypeDef HAL_ADCEx_RegularMultiModeStop_DMA(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Injected conversion complete callback in non blocking mode 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
@@ -5332,7 +5325,7 @@ __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
             (parameter "QueueInjectedContext" in injected channel configuration)
             and if a new injected context is set when queue is full (maximum 2
             contexts).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
@@ -5348,7 +5341,7 @@ __weak void HAL_ADCEx_InjectedQueueOverflowCallback(ADC_HandleTypeDef* hadc)
                         
 /**
   * @brief  Analog watchdog 2 callback in non blocking mode. 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
@@ -5363,7 +5356,7 @@ __weak void HAL_ADCEx_LevelOutOfWindow2Callback(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Analog watchdog 3 callback in non blocking mode. 
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval None
   */
 __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
@@ -5425,8 +5418,8 @@ __weak void HAL_ADCEx_LevelOutOfWindow3Callback(ADC_HandleTypeDef* hadc)
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_ChannelConfTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  sConfig: Structure ADC channel for regular group.
+  * @param  sConfig Structure ADC channel for regular group.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -5759,8 +5752,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_ChannelConfTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  sConfig: Structure of ADC channel for regular group.
+  * @param  sConfig Structure of ADC channel for regular group.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
@@ -5890,8 +5883,8 @@ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConf
   *    HAL_ADCEx_InjectedConfigChannel() must be called once for each channel and  
   *    for each context (3 channels x 2 contexts = 6 calls). Conversion can  
   *    start once the 1st context is set. The 2nd context can be set on the fly.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
+  * @param  sConfigInjected Structure of ADC injected group and ADC channel for
   *         injected group.
   * @retval None
   */
@@ -6396,8 +6389,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   *            Vbat/VrefInt/TempSensor.
   *         These internal paths can be be disabled using function 
   *         HAL_ADC_DeInit().
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
+  * @param  sConfigInjected Structure of ADC injected group and ADC channel for
   *         injected group.
   * @retval None
   */
@@ -6643,8 +6636,8 @@ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_I
   *         The setting of these parameters is conditioned to ADC state.
   *         For parameters constraints, see comments of structure 
   *         "ADC_AnalogWDGConfTypeDef".
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
+  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -6848,8 +6841,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
   *         Considering that registers write delay may happen due to
   *         bus activity, this might cause an uncertainty on the
   *         effective timing of the new programmed threshold values.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
+  * @param  AnalogWDGConfig Structure of ADC analog watchdog configuration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
@@ -6928,8 +6921,8 @@ HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDG
   *         "ADC_MultiModeTypeDef".
   * @note   To change back configuration from multimode to single mode, ADC must
   *         be reset (using function HAL_ADC_Init() ).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  multimode : Structure of ADC multimode configuration
+  * @param  multimode Structure of ADC multimode configuration
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode)
@@ -6947,12 +6940,16 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
     assert_param(IS_ADC_SAMPLING_DELAY(multimode->TwoSamplingDelay));
   }
   
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  
   /* Set handle of the other ADC sharing the same common register             */
   ADC_COMMON_ADC_OTHER(hadc, &tmphadcSharingSameCommonRegister);
+  if (tmphadcSharingSameCommonRegister.Instance == NULL)
+  {
+    /* Return function status */
+    return HAL_ERROR;
+  }
+
+  /* Process locked */
+  __HAL_LOCK(hadc);
   
   /* Parameters update conditioned to ADC state:                              */
   /* Parameters that can be updated when ADC is disabled or enabled without   */
@@ -7055,7 +7052,7 @@ HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_
   */
 /**
   * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
@@ -7098,7 +7095,7 @@ static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
@@ -7112,7 +7109,7 @@ static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
@@ -7138,7 +7135,7 @@ static void ADC_DMAError(DMA_HandleTypeDef *hdma)
   * @brief  Enable the selected ADC.
   * @note   Prerequisite condition to use this function: ADC must be disabled
   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
@@ -7192,7 +7189,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
   * @brief  Disable the selected ADC.
   * @note   Prerequisite condition to use this function: ADC conversions must be
   *         stopped.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
@@ -7246,8 +7243,8 @@ static HAL_StatusTypeDef ADC_Disable(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Stop ADC conversion.
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
-  * @param  ConversionGroup: ADC group regular and/or injected.
+  * @param  ConversionGroup ADC group regular and/or injected.
   *          This parameter can be one of the following values:
   *            @arg ADC_REGULAR_GROUP: ADC regular conversion type.
   *            @arg ADC_INJECTED_GROUP: ADC injected conversion type.
@@ -7372,7 +7369,7 @@ static HAL_StatusTypeDef ADC_ConversionStop(ADC_HandleTypeDef* hadc, uint32_t Co
   * @brief  Enable the selected ADC.
   * @note   Prerequisite condition to use this function: ADC must be disabled
   *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
@@ -7425,7 +7422,7 @@ static HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
 
 /**
   * @brief  Stop ADC conversion and disable the selected ADC
-  * @param  hadc: ADC handle
+  * @param  hadc ADC handle
   * @retval HAL status.
   */
 static HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_adc_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_adc_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file containing functions prototypes of ADC HAL library.
   ******************************************************************************
   * @attention
@@ -797,7 +795,6 @@ typedef struct
   */
 #define ADC_EOC_SINGLE_CONV         ((uint32_t) ADC_ISR_EOC)
 #define ADC_EOC_SEQ_CONV            ((uint32_t) ADC_ISR_EOS)
-#define ADC_EOC_SINGLE_SEQ_CONV     ((uint32_t)(ADC_ISR_EOC | ADC_ISR_EOS))  /*!< reserved for future use */
 /**
   * @}
   */
@@ -1345,7 +1342,7 @@ typedef struct
 /* External triggers of regular group for ADC1 */
 #define ADC_EXTERNALTRIGCONV_T2_CC2      ADC_EXTERNALTRIG_T2_CC2
 #define ADC_EXTERNALTRIGCONV_T3_TRGO     ADC_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC2      ADC_EXTERNALTRIG_T4_CC2
+#define ADC_EXTERNALTRIGCONV_T4_CC4      ADC_EXTERNALTRIG_T4_CC4
 #define ADC_EXTERNALTRIGCONV_T19_TRGO    ADC_EXTERNALTRIG_T19_TRGO
 #define ADC_EXTERNALTRIGCONV_T19_CC3     ADC_EXTERNALTRIG_T19_CC3
 #define ADC_EXTERNALTRIGCONV_T19_CC4     ADC_EXTERNALTRIG_T19_CC4
@@ -1824,7 +1821,7 @@ typedef struct
 #define ADC_EXTERNALTRIG_T19_CC4           ((uint32_t)ADC_CR2_EXTSEL_1)
 #define ADC_EXTERNALTRIG_T2_CC2            ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 #define ADC_EXTERNALTRIG_T3_TRGO           ((uint32_t)ADC_CR2_EXTSEL_2)
-#define ADC_EXTERNALTRIG_T4_CC2            ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
+#define ADC_EXTERNALTRIG_T4_CC4            ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
 #define ADC_EXTERNALTRIG_EXT_IT11          ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
 #define ADC_SWSTART                        ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
 /**
@@ -1922,7 +1919,7 @@ typedef struct
 
 /**
   * @brief Enable the ADC peripheral
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @note ADC enable requires a delay for ADC stabilization time
   *       (refer to device datasheet, parameter tSTAB)
   * @note On STM32F3 devices, some hardware constraints must be strictly
@@ -1939,7 +1936,7 @@ typedef struct
 
 /**
   * @brief Disable the ADC peripheral
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @note On STM32F3 devices, some hardware constraints must be strictly
   *       respected before using this macro:
   *        - ADC state requirements: ADC must be enabled, no conversion on 
@@ -1955,8 +1952,8 @@ typedef struct
 
 /**
   * @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
+  * @param __INTERRUPT__ ADC Interrupt
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_RDY:   ADC Ready (ADRDY) interrupt source
   *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
@@ -1976,8 +1973,8 @@ typedef struct
 
 /**
   * @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
+  * @param __INTERRUPT__ ADC Interrupt
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_RDY:   ADC Ready (ADRDY) interrupt source
   *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
@@ -1996,8 +1993,8 @@ typedef struct
   (CLEAR_BIT((__HANDLE__)->Instance->IER, (__INTERRUPT__)))
 
 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__: ADC interrupt source to check
+  * @param __INTERRUPT__ ADC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_RDY:   ADC Ready (ADRDY) interrupt source
   *            @arg ADC_IT_EOSMP: ADC End of Sampling interrupt source
@@ -2017,8 +2014,8 @@ typedef struct
 
 /**
   * @brief Get the selected ADC's flag status.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __FLAG__: ADC flag
+  * @param __FLAG__ ADC flag
   *          This parameter can be any combination of the following values:
   *            @arg ADC_FLAG_RDY:   ADC Ready (ADRDY) flag
   *            @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
@@ -2038,8 +2035,8 @@ typedef struct
 
 /**
   * @brief Clear the ADC's pending flags
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __FLAG__: ADC flag
+  * @param __FLAG__ ADC flag
   *          This parameter can be any combination of the following values:
   *            @arg ADC_FLAG_RDY:   ADC Ready (ADRDY) flag
   *            @arg ADC_FLAG_EOSMP: ADC End of Sampling flag
@@ -2060,7 +2057,7 @@ typedef struct
   (WRITE_REG((__HANDLE__)->Instance->ISR, (__FLAG__)))
 
 /** @brief  Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
@@ -2079,7 +2076,7 @@ typedef struct
   *       (refer to device datasheet, parameter tSTAB)
   * @note On STM32F37x devices, if ADC is already enabled this macro trigs
   *       a conversion SW start on regular group.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_ENABLE(__HANDLE__)                                           \
@@ -2087,15 +2084,15 @@ typedef struct
   
 /**
   * @brief Disable the ADC peripheral
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_DISABLE(__HANDLE__)                                          \
   (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_ADON)))
     
 /** @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
+  * @param __INTERRUPT__ ADC Interrupt
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
@@ -2106,8 +2103,8 @@ typedef struct
   (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
 
 /** @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
+  * @param __INTERRUPT__ ADC Interrupt
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
@@ -2118,8 +2115,8 @@ typedef struct
   (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
 
 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __INTERRUPT__: ADC interrupt source to check
+  * @param __INTERRUPT__ ADC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg ADC_IT_EOC: ADC End of Regular Conversion interrupt source
   *            @arg ADC_IT_JEOC: ADC End of Injected Conversion interrupt source
@@ -2130,8 +2127,8 @@ typedef struct
   (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /** @brief Get the selected ADC's flag status.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __FLAG__: ADC flag
+  * @param __FLAG__ ADC flag
   *          This parameter can be any combination of the following values:
   *            @arg ADC_FLAG_STRT: ADC Regular group start flag
   *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
@@ -2144,8 +2141,8 @@ typedef struct
   ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
     
 /** @brief Clear the ADC's pending flags
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __FLAG__: ADC flag
+  * @param __FLAG__ ADC flag
   *          This parameter can be any combination of the following values:
   *            @arg ADC_FLAG_STRT: ADC Regular group start flag
   *            @arg ADC_FLAG_JSTRT: ADC Injected group start flag
@@ -2158,7 +2155,7 @@ typedef struct
   (WRITE_REG((__HANDLE__)->Instance->SR, ~(__FLAG__)))
 
 /** @brief  Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
+  * @param  __HANDLE__ ADC handle
   * @retval None
   */
 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__)                               \
@@ -2184,7 +2181,7 @@ typedef struct
 
 /**
   * @brief Verification of hardware constraints before ADC can be enabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC can be enabled) or RESET (ADC cannot be enabled)
   */
 #define ADC_ENABLING_CONDITIONS(__HANDLE__)                                    \
@@ -2196,7 +2193,7 @@ typedef struct
 
 /**
   * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC enabled) or RESET (ADC disabled)
   */
 #define ADC_IS_ENABLE(__HANDLE__)                                                      \
@@ -2207,7 +2204,7 @@ typedef struct
 /**
   * @brief Test if conversion trigger of regular group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
@@ -2216,7 +2213,7 @@ typedef struct
 /**
   * @brief Test if conversion trigger of injected group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
@@ -2224,7 +2221,7 @@ typedef struct
 
 /**
   * @brief Check if no conversion on going on regular and/or injected groups
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (conversion is on going) or RESET (no conversion is on going)
   */
 #define ADC_IS_CONVERSION_ONGOING_REGULAR_INJECTED(__HANDLE__)                     \
@@ -2233,7 +2230,7 @@ typedef struct
 
 /**
   * @brief Check if no conversion on going on regular group
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (conversion is on going) or RESET (no conversion is on going)
   */
 #define ADC_IS_CONVERSION_ONGOING_REGULAR(__HANDLE__)                          \
@@ -2242,7 +2239,7 @@ typedef struct
 
 /**
   * @brief Check if no conversion on going on injected group
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (conversion is on going) or RESET (no conversion is on going)
   */
 #define ADC_IS_CONVERSION_ONGOING_INJECTED(__HANDLE__)                         \
@@ -2252,7 +2249,7 @@ typedef struct
 /**
   * @brief Returns resolution bits in CFGR1 register: RES[1:0].
   *        Returned value is among parameters to @ref ADCEx_Resolution.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CFGR) & ADC_CFGR_RES)
@@ -2268,63 +2265,63 @@ typedef struct
 
 /**
   * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_CLEAR_ERRORCODE(__HANDLE__) ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
          
 /**
   * @brief Set the ADC's sample time for Channels numbers between 0 and 9.
-  * @param _SAMPLETIME_: Sample time parameter.
+  * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
+  * @param _CHANNELNB_ Channel number.  
   * @retval None
   */
 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (_CHANNELNB_)))
     
 /**
   * @brief Set the ADC's sample time for Channels numbers between 10 and 18.
-  * @param _SAMPLETIME_: Sample time parameter.
+  * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
+  * @param _CHANNELNB_ Channel number.  
   * @retval None
   */
 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((_CHANNELNB_) - 10U)))
 
 /**
   * @brief Set the selected regular Channel rank for rank between 1 and 4.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_)))
 
 /**
   * @brief Set the selected regular Channel rank for rank between 5 and 9.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 5U)))
 
 /**
   * @brief Set the selected regular Channel rank for rank between 10 and 14.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 10U)))
 
 /**
   * @brief Set the selected regular Channel rank for rank between 15 and 16.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * ((_RANKNB_) - 15U)))
 
 /**
   * @brief Set the selected injected Channel rank.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.   
+  * @param _RANKNB_ Rank number.   
   * @retval None
   */
 #define ADC_JSQR_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (6U * (_RANKNB_) +2U))
@@ -2332,70 +2329,70 @@ typedef struct
 
 /**
   * @brief Set the Analog Watchdog 1 channel.
-  * @param _CHANNEL_: channel to be monitored by Analog Watchdog 1.
+  * @param _CHANNEL_ channel to be monitored by Analog Watchdog 1.
   * @retval None
   */
 #define ADC_CFGR_AWD1CH_SHIFT(_CHANNEL_) ((_CHANNEL_) << 26U)
 
 /**
   * @brief Configure the channel number into Analog Watchdog 2 or 3.
-  * @param _CHANNEL_: ADC Channel
+  * @param _CHANNEL_ ADC Channel
   * @retval None
   */
 #define ADC_CFGR_AWD23CR(_CHANNEL_) (1U << (_CHANNEL_)) 
 
 /**
   * @brief Enable automatic conversion of injected group
-  * @param _INJECT_AUTO_CONVERSION_: Injected automatic conversion.
+  * @param _INJECT_AUTO_CONVERSION_ Injected automatic conversion.
   * @retval None
   */
 #define ADC_CFGR_INJECT_AUTO_CONVERSION(_INJECT_AUTO_CONVERSION_) ((_INJECT_AUTO_CONVERSION_) << 25U)
 
 /**
   * @brief Enable ADC injected context queue
-  * @param _INJECT_CONTEXT_QUEUE_MODE_: Injected context queue mode.
+  * @param _INJECT_CONTEXT_QUEUE_MODE_ Injected context queue mode.
   * @retval None
   */
 #define ADC_CFGR_INJECT_CONTEXT_QUEUE(_INJECT_CONTEXT_QUEUE_MODE_) ((_INJECT_CONTEXT_QUEUE_MODE_) << 21U)
 
 /**
   * @brief Enable ADC discontinuous conversion mode for injected group
-  * @param _INJECT_DISCONTINUOUS_MODE_: Injected discontinuous mode.
+  * @param _INJECT_DISCONTINUOUS_MODE_ Injected discontinuous mode.
   * @retval None
   */
 #define ADC_CFGR_INJECT_DISCCONTINUOUS(_INJECT_DISCONTINUOUS_MODE_) ((_INJECT_DISCONTINUOUS_MODE_) << 20U)
 
 /**
   * @brief Enable ADC discontinuous conversion mode for regular group
-  * @param _REG_DISCONTINUOUS_MODE_: Regular discontinuous mode.
+  * @param _REG_DISCONTINUOUS_MODE_ Regular discontinuous mode.
   * @retval None
   */
 #define ADC_CFGR_REG_DISCCONTINUOUS(_REG_DISCONTINUOUS_MODE_) ((_REG_DISCONTINUOUS_MODE_) << 16U)
 
 /**
   * @brief Configures the number of discontinuous conversions for regular group.
-  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+  * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
   * @retval None
   */
 #define ADC_CFGR_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1U) << 17U)
 
 /**
   * @brief Enable the ADC auto delay mode.
-  * @param _AUTOWAIT_: Auto delay bit enable or disable.
+  * @param _AUTOWAIT_ Auto delay bit enable or disable.
   * @retval None
   */
 #define ADC_CFGR_AUTOWAIT(_AUTOWAIT_) ((_AUTOWAIT_) << 14U)
 
 /**
   * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_: Continuous mode.
+  * @param _CONTINUOUS_MODE_ Continuous mode.
   * @retval None
   */
 #define ADC_CFGR_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 13U)
     
 /**
   * @brief Enable ADC overrun mode.
-  * @param _OVERRUN_MODE_: Overrun mode.
+  * @param _OVERRUN_MODE_ Overrun mode.
   * @retval Overrun bit setting to be programmed into CFGR register
   */
 /* Note: Bit ADC_CFGR_OVRMOD not used directly in constant                    */
@@ -2408,7 +2405,7 @@ typedef struct
 
 /**
   * @brief Enable the ADC DMA continuous request.
-  * @param _DMACONTREQ_MODE_: DMA continuous request mode.
+  * @param _DMACONTREQ_MODE_ DMA continuous request mode.
   * @retval None
   */
 #define ADC_CFGR_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << 1U)
@@ -2423,8 +2420,8 @@ typedef struct
   *        exceptions below are circular and do not point to any other trigger
   *        with direct treatment.
   *        For devices with 2 ADCs or less: this macro makes no change.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __EXT_TRIG_CONV__: External trigger selected for regular group.
+  * @param __EXT_TRIG_CONV__ External trigger selected for regular group.
   * @retval External trigger to be programmed into EXTSEL bits of CFGR register
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2513,8 +2510,8 @@ typedef struct
   *        with direct treatment, except trigger
   *        ADC_EXTERNALTRIGINJECCONV_T4_CC3 differentiated with SW offset.
   *        For devices with 2 ADCs or less: this macro makes no change.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __EXT_TRIG_INJECTCONV__: External trigger selected for injected group
+  * @param __EXT_TRIG_INJECTCONV__ External trigger selected for injected group
   * @retval External trigger to be programmed into JEXTSEL bits of JSQR register
   */
 #if defined(STM32F303xC) || defined(STM32F303xE) || defined(STM32F398xx) || defined(STM32F358xx)
@@ -2599,49 +2596,49 @@ typedef struct
 
 /**
   * @brief Configure the channel number into offset OFRx register
-  * @param _CHANNEL_: ADC Channel
+  * @param _CHANNEL_ ADC Channel
   * @retval None
   */
 #define ADC_OFR_CHANNEL(_CHANNEL_) ((_CHANNEL_) << 26U)
 
 /**
   * @brief Configure the channel number into differential mode selection register
-  * @param _CHANNEL_: ADC Channel
+  * @param _CHANNEL_ ADC Channel
   * @retval None
   */
 #define ADC_DIFSEL_CHANNEL(_CHANNEL_) (1U << (_CHANNEL_)) 
 
 /**
   * @brief Calibration factor in differential mode to be set into calibration register
-  * @param _Calibration_Factor_: Calibration factor value
+  * @param _Calibration_Factor_ Calibration factor value
   * @retval None
   */
 #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_) ((_Calibration_Factor_) << 16U)
 
 /**
   * @brief Calibration factor in differential mode to be retrieved from calibration register
-  * @param _Calibration_Factor_: Calibration factor value
+  * @param _Calibration_Factor_ Calibration factor value
   * @retval None
   */
 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_) ((_Calibration_Factor_) >> 16U)
      
 /**
   * @brief Configure the analog watchdog high threshold into registers TR1, TR2 or TR3.
-  * @param _Threshold_: Threshold value
+  * @param _Threshold_ Threshold value
   * @retval None
   */
 #define ADC_TRX_HIGHTHRESHOLD(_Threshold_) ((_Threshold_) << 16U)
 
 /**
   * @brief Enable the ADC DMA continuous request for ADC multimode.
-  * @param _DMAContReq_MODE_: DMA continuous request mode.
+  * @param _DMAContReq_MODE_ DMA continuous request mode.
   * @retval None
   */
 #define ADC_CCR_MULTI_DMACONTREQ(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 13U)
     
 /**
   * @brief Verification of hardware constraints before ADC can be disabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC can be disabled) or RESET (ADC cannot be disabled)
   */
 #define ADC_DISABLING_CONDITIONS(__HANDLE__)                                   \
@@ -2658,8 +2655,8 @@ typedef struct
   *        If resolution 8 bits, shift of 4 ranks on the left.
   *        If resolution 6 bits, shift of 6 ranks on the left.
   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param _Offset_: Value to be shifted
+  * @param _Offset_ Value to be shifted
   * @retval None
   */
 #define ADC_OFFSET_SHIFT_RESOLUTION(__HANDLE__, _Offset_)                      \
@@ -2673,8 +2670,8 @@ typedef struct
   *        If resolution 8 bits, shift of 4 ranks on the left.
   *        If resolution 6 bits, shift of 6 ranks on the left.
   *        therefore, shift = (12 - resolution) = 12 - (12- (((RES[1:0]) >> 3)*2))
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param _Threshold_: Value to be shifted
+  * @param _Threshold_ Value to be shifted
   * @retval None
   */
 #define ADC_AWD1THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)            \
@@ -2687,8 +2684,8 @@ typedef struct
   *        If resolution 10 bits, shift of 2 ranks on the right (the 2 LSB are discarded)
   *        If resolution 8 bits, no shift.
   *        If resolution 6 bits, shift of 2 ranks on the left (the 2 LSB are set to 0)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param _Threshold_: Value to be shifted
+  * @param _Threshold_ Value to be shifted
   * @retval None
   */
 #define ADC_AWD23THRESHOLD_SHIFT_RESOLUTION(__HANDLE__, _Threshold_)           \
@@ -2699,7 +2696,7 @@ typedef struct
 /**
   * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval Common control register ADC1_2 or ADC3_4
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2728,7 +2725,7 @@ typedef struct
 /**
   * @brief Defines if the selected ADC is within ADC common register ADC1_2 or ADC3_4
   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval Common control register ADC1_2 or ADC3_4
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2756,7 +2753,7 @@ typedef struct
        
 /**
   * @brief Selection of ADC common register CCR bits MULTI[4:0]corresponding to the selected ADC (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2787,7 +2784,7 @@ typedef struct
 
 /**
   * @brief Verification of condition for ADC start conversion: ADC must be in non-multimode, or multimode with handle of ADC master (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2807,7 +2804,7 @@ typedef struct
 
 /**
   * @brief Verification of condition for ADC group regular start conversion: ADC must be in non-multimode or multimode on group injected only, or multimode with handle of ADC master (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle.
+  * @param __HANDLE__ ADC handle.
   * @retval None
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2829,7 +2826,7 @@ typedef struct
 
 /**
   * @brief Verification of condition for ADC group injected start conversion: ADC must be in non-multimode or multimode on group regular only, or multimode with handle of ADC master (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle.
+  * @param __HANDLE__ ADC handle.
   * @retval None
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2851,7 +2848,7 @@ typedef struct
 
 /**
   * @brief Check ADC multimode setting: In case of multimode, check whether ADC master of the selected ADC has feature auto-injection enabled (applicable for devices with several ADCs)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2881,8 +2878,8 @@ typedef struct
 /**
   * @brief Set handle of the other ADC sharing the same common register ADC1_2 or ADC3_4
   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
-  * @param __HANDLE_OTHER_ADC__: other ADC handle
+  * @param __HANDLE_OTHER_ADC__ other ADC handle
   * @retval None
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2934,8 +2931,8 @@ typedef struct
 /**
   * @brief Set handle of the ADC slave associated to the ADC master
   * if available (ADC2, ADC3, ADC4 availability depends on STM32 product)
-  * @param __HANDLE_MASTER__: ADC master handle
+  * @param __HANDLE_MASTER__ ADC master handle
-  * @param __HANDLE_SLAVE__: ADC slave handle
+  * @param __HANDLE_SLAVE__ ADC slave handle
   * @retval None
   */
 #if defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -2986,8 +2983,7 @@ typedef struct
                                      ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
 
 #define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == ADC_EOC_SINGLE_CONV)    || \
-                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)       || \
+                                             ((EOC_SELECTION) == ADC_EOC_SEQ_CONV)   )
-                                             ((EOC_SELECTION) == ADC_EOC_SINGLE_SEQ_CONV)  )
 
 #define IS_ADC_OVERRUN(OVR) (((OVR) == ADC_OVR_DATA_PRESERVED)  || \
                              ((OVR) == ADC_OVR_DATA_OVERWRITTEN)  )
@@ -3497,7 +3493,7 @@ typedef struct
   */
 /**
   * @brief Calibration factor length verification (7 bits maximum)
-  * @param _Calibration_Factor_: Calibration factor value
+  * @param _Calibration_Factor_ Calibration factor value
   * @retval None
   */
 #define IS_ADC_CALFACT(_Calibration_Factor_) ((_Calibration_Factor_) <= (0x7FU))
@@ -3515,7 +3511,7 @@ typedef struct
 
 /**
   * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (ADC enabled) or RESET (ADC disabled)
   */
 #define ADC_IS_ENABLE(__HANDLE__)                                              \
@@ -3525,7 +3521,7 @@ typedef struct
 /**
   * @brief Test if conversion trigger of regular group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                              \
@@ -3534,7 +3530,7 @@ typedef struct
 /**
   * @brief Test if conversion trigger of injected group is software start
   *        or external trigger.
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval SET (software start) or RESET (external trigger)
   */
 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                             \
@@ -3551,7 +3547,7 @@ typedef struct
 
 /**
   * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval None
   */
 #define ADC_CLEAR_ERRORCODE(__HANDLE__)                                        \
@@ -3559,7 +3555,7 @@ typedef struct
 
 /**
   * @brief Set ADC number of conversions into regular channel sequence length.
-  * @param _NbrOfConversion_: Regular channel sequence length 
+  * @param _NbrOfConversion_ Regular channel sequence length 
   * @retval None
   */
 #define ADC_SQR1_L_SHIFT(_NbrOfConversion_)                                    \
@@ -3567,8 +3563,8 @@ typedef struct
 
 /**
   * @brief Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param _SAMPLETIME_: Sample time parameter.
+  * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
+  * @param _CHANNELNB_ Channel number.  
   * @retval None
   */
 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_)                                   \
@@ -3576,8 +3572,8 @@ typedef struct
 
 /**
   * @brief Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param _SAMPLETIME_: Sample time parameter.
+  * @param _SAMPLETIME_ Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
+  * @param _CHANNELNB_ Channel number.  
   * @retval None
   */
 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_)                                   \
@@ -3585,8 +3581,8 @@ typedef struct
 
 /**
   * @brief Set the selected regular channel rank for rank between 1 and 6.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_)                                     \
@@ -3594,8 +3590,8 @@ typedef struct
 
 /**
   * @brief Set the selected regular channel rank for rank between 7 and 12.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_)                                     \
@@ -3603,8 +3599,8 @@ typedef struct
 
 /**
   * @brief Set the selected regular channel rank for rank between 13 and 16.
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.    
+  * @param _RANKNB_ Rank number.    
   * @retval None
   */
 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_)                                     \
@@ -3612,7 +3608,7 @@ typedef struct
 
 /**
   * @brief Set the injected sequence length.
-  * @param _JSQR_JL_: Sequence length.
+  * @param _JSQR_JL_ Sequence length.
   * @retval None
   */
 #define ADC_JSQR_JL_SHIFT(_JSQR_JL_)                                           \
@@ -3623,9 +3619,9 @@ typedef struct
   *        Note: on STM32F37x devices, channel rank position in JSQR register
   *              is depending on total number of ranks selected into
   *              injected sequencer (ranks sequence starting from 4-JL)
-  * @param _CHANNELNB_: Channel number.
+  * @param _CHANNELNB_ Channel number.
-  * @param _RANKNB_: Rank number.
+  * @param _RANKNB_ Rank number.
-  * @param _JSQR_JL_: Sequence length.
+  * @param _JSQR_JL_ Sequence length.
   * @retval None
   */
 #define ADC_JSQR_RK_JL(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                       \
@@ -3633,7 +3629,7 @@ typedef struct
 
 /**
   * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_: Continuous mode.
+  * @param _CONTINUOUS_MODE_ Continuous mode.
   * @retval None
   */
 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_)                                  \
@@ -3641,7 +3637,7 @@ typedef struct
 
 /**
   * @brief Configures the number of discontinuous conversions for the regular group channels.
-  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
+  * @param _NBR_DISCONTINUOUS_CONV_ Number of discontinuous conversions.
   * @retval None
   */
 #define ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_)                    \
@@ -3649,7 +3645,7 @@ typedef struct
    
 /**
   * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
-  * @param _SCAN_MODE_: Scan conversion mode.
+  * @param _SCAN_MODE_ Scan conversion mode.
   * @retval None
   */
 /* Note: Scan mode is compared to ENABLE for legacy purpose, this parameter   */
@@ -3661,7 +3657,7 @@ typedef struct
     
 /**
   * @brief Calibration factor in differential mode to be set into calibration register
-  * @param _Calibration_Factor_: Calibration factor value
+  * @param _Calibration_Factor_ Calibration factor value
   * @retval None
   */
 #define ADC_CALFACT_DIFF_SET(_Calibration_Factor_)                             \
@@ -3669,7 +3665,7 @@ typedef struct
 
 /**
   * @brief Calibration factor in differential mode to be retrieved from calibration register
-  * @param _Calibration_Factor_: Calibration factor value
+  * @param _Calibration_Factor_ Calibration factor value
   * @retval None
   */
 #define ADC_CALFACT_DIFF_GET(_Calibration_Factor_)                             \
@@ -3685,7 +3681,7 @@ typedef struct
   *   between 41.5 cycles and 71.5 cycles {41.5 cycles; 55.5 cycles; 71.5cycles}
   *   equal to 239.5 cycles
   * Unit: ADC clock cycles
-  * @param __HANDLE__: ADC handle
+  * @param __HANDLE__ ADC handle
   * @retval ADC conversion cycles on all channels
   */   
 #define ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                                     \
@@ -3784,7 +3780,7 @@ typedef struct
 
 #define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC2)   || \
+                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_TRGO) || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC3)  || \
                                  ((REGTRIG) == ADC_EXTERNALTRIGCONV_T19_CC4)  || \

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_can.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_can.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of CAN HAL module.
   ******************************************************************************
   * @attention
@@ -73,10 +71,14 @@ typedef enum
   HAL_CAN_STATE_READY             = 0x01U,  /*!< CAN initialized and ready for use   */
   HAL_CAN_STATE_BUSY              = 0x02U,  /*!< CAN process is ongoing              */
   HAL_CAN_STATE_BUSY_TX           = 0x12U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_RX           = 0x22U,  /*!< CAN process is ongoing              */ 
+  HAL_CAN_STATE_BUSY_RX0          = 0x22U,  /*!< CAN process is ongoing              */
-  HAL_CAN_STATE_BUSY_TX_RX        = 0x32U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX1          = 0x32U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX0       = 0x42U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX1       = 0x52U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_RX0_RX1      = 0x62U,  /*!< CAN process is ongoing              */
+  HAL_CAN_STATE_BUSY_TX_RX0_RX1   = 0x72U,  /*!< CAN process is ongoing              */
   HAL_CAN_STATE_TIMEOUT           = 0x03U,  /*!< CAN in Timeout state                */
-  HAL_CAN_STATE_ERROR             = 0x04   /*!< CAN error state                     */  
+  HAL_CAN_STATE_ERROR             = 0x04U   /*!< CAN error state                     */
 
 }HAL_CAN_StateTypeDef;
 
@@ -232,7 +234,9 @@ typedef struct
   
   CanTxMsgTypeDef*            pTxMsg;     /*!< Pointer to transmit structure  */
 
-  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure */
+  CanRxMsgTypeDef*            pRxMsg;     /*!< Pointer to reception structure for RX FIFO0 msg */
+
+  CanRxMsgTypeDef*            pRx1Msg;    /*!< Pointer to reception structure for RX FIFO1 msg */
 
   HAL_LockTypeDef             Lock;       /*!< CAN locking object             */
   
@@ -265,6 +269,9 @@ typedef struct
 #define HAL_CAN_ERROR_BR            (0x00000040U)  /*!< Bit recessive        */
 #define HAL_CAN_ERROR_BD            (0x00000080U)  /*!< LEC dominant         */
 #define HAL_CAN_ERROR_CRC           (0x00000100U)  /*!< LEC transfer error   */
+#define HAL_CAN_ERROR_FOV0          (0x00000200U)  /*!< FIFO0 overrun error  */
+#define HAL_CAN_ERROR_FOV1          (0x00000400U)  /*!< FIFO1 overrun error  */
+#define HAL_CAN_ERROR_TXFAIL        (0x00000800U)  /*!< Transmit failure     */
 /**
   * @}
   */
@@ -420,8 +427,10 @@ typedef struct
 #define CAN_FLAG_FOV1              (0x00000404U)  /*!< FIFO 1 Overrun flag */
 
 /* Operating Mode Flags */
-#define CAN_FLAG_WKU               (0x00000103U)  /*!< Wake up flag           */
+#define CAN_FLAG_INAK              (0x00000100U)  /*!< Initialization acknowledge flag */
 #define CAN_FLAG_SLAK              (0x00000101U)  /*!< Sleep acknowledge flag          */
+#define CAN_FLAG_ERRI              (0x00000102U)  /*!< Error flag                      */
+#define CAN_FLAG_WKU               (0x00000103U)  /*!< Wake up flag                    */
 #define CAN_FLAG_SLAKI             (0x00000104U)  /*!< Sleep acknowledge flag          */
 /* @note When SLAK interrupt is disabled (SLKIE=0U), no polling on SLAKI is possible. 
          In this case the SLAK bit can be polled.*/
@@ -485,39 +494,39 @@ typedef struct
   */
 
 /** @brief  Reset CAN handle state
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
   * @retval None
   */
 #define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
 
 /**
   * @brief  Enable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt
+  * @param  __INTERRUPT__ CAN Interrupt
   * @retval None
   */
 #define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
 
 /**
   * @brief  Disable the specified CAN interrupts.
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
-  * @param  __INTERRUPT__: CAN Interrupt
+  * @param  __INTERRUPT__ CAN Interrupt
   * @retval None
   */
 #define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
 
 /**
   * @brief  Return the number of pending received messages.
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
   * @retval The number of pending message.
   */
 #define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
 ((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
 
 /** @brief  Check whether the specified CAN flag is set or not.
-  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
@@ -550,8 +559,8 @@ typedef struct
  ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
 
 /** @brief  Clear the specified CAN pending flag.
-  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *         This parameter can be one of the following values:
   *            @arg CAN_TSR_RQCP0: Request MailBox0 Flag
   *            @arg CAN_TSR_RQCP1: Request MailBox1 Flag
@@ -583,8 +592,8 @@ typedef struct
 
 
 /** @brief  Check if the specified CAN interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __INTERRUPT__: specifies the CAN interrupt source to check.
+  * @param  __INTERRUPT__ specifies the CAN interrupt source to check.
   *         This parameter can be one of the following values:
   *            @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
   *            @arg CAN_IT_FMP0: FIFO0 message pending interrupt enablev
@@ -595,21 +604,19 @@ typedef struct
 
 /**
   * @brief  Check the transmission status of a CAN Frame.
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @param  __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
   * @retval The new status of transmission  (TRUE or FALSE).
   */
 #define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TME2)))
-
-
 
  /**
   * @brief  Release the specified receive FIFO.
-  * @param  __HANDLE__: CAN handle.
+  * @param  __HANDLE__ CAN handle.
-  * @param  __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
   * @retval None
   */
 #define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
@@ -617,8 +624,8 @@ typedef struct
 
 /**
   * @brief  Cancel a transmit request.
-  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
+  * @param  __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
   * @retval None
   */
 #define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
@@ -628,8 +635,8 @@ typedef struct
 
 /**
   * @brief  Enable or disables the DBG Freeze for CAN.
-  * @param  __HANDLE__: specifies the CAN Handle.
+  * @param  __HANDLE__ specifies the CAN Handle.
-  * @param  __NEWSTATE__: new state of the CAN peripheral. 
+  * @param  __NEWSTATE__ new state of the CAN peripheral. 
   *         This parameter can be: ENABLE (CAN reception/transmission is frozen
   *         during debug. Reception FIFOs can still be accessed/controlled normally) 
   *         or DISABLE (CAN is working during debug).

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cec.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_cec.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   CEC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the High Definition Multimedia Interface 
@@ -142,7 +140,7 @@
 /**
   * @brief Initializes the CEC mode according to the specified
   *         parameters in the CEC_InitTypeDef and creates the associated handle .
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
@@ -212,7 +210,7 @@ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec)
 
 /**
   * @brief DeInitializes the CEC peripheral 
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
@@ -265,8 +263,8 @@ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec)
 
 /**
   * @brief Initializes the Own Address of the CEC device
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
-  * @param  CEC_OwnAddress: The CEC own address.  
+  * @param  CEC_OwnAddress The CEC own address.  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress)
@@ -312,7 +310,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
 
 /**
   * @brief CEC MSP Init
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec)
@@ -326,7 +324,7 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
 
 /**
   * @brief CEC MSP DeInit
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec)
@@ -378,11 +376,11 @@ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC
 
 /**
   * @brief Send data in interrupt mode 
-  * @param hcec: CEC handle 
+  * @param hcec CEC handle 
-  * @param InitiatorAddress: Initiator address
+  * @param InitiatorAddress Initiator address
-  * @param DestinationAddress: destination logical address      
+  * @param DestinationAddress destination logical address      
-  * @param pData: pointer to input byte data buffer
+  * @param pData pointer to input byte data buffer
-  * @param Size: amount of data to be sent in bytes (without counting the header).
+  * @param Size amount of data to be sent in bytes (without counting the header).
   *              0 means only the header is sent (ping operation).
   *              Maximum TX size is 15 bytes (1 opcode and up to 14 operands).
   * @retval HAL status
@@ -438,7 +436,7 @@ HAL_StatusTypeDef HAL_CEC_Transmit_IT(CEC_HandleTypeDef *hcec, uint8_t Initiator
 
 /**
   * @brief Get size of the received frame.
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval Frame size
   */
 uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
@@ -448,8 +446,8 @@ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec)
 
 /**
   * @brief Change Rx Buffer.
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
-  * @param Rxbuffer: Rx Buffer
+  * @param Rxbuffer Rx Buffer
   * @note  This function can be called only inside the HAL_CEC_RxCpltCallback() 
   * @retval Frame size
   */
@@ -460,7 +458,7 @@ void HAL_CEC_ChangeRxBuffer(CEC_HandleTypeDef *hcec, uint8_t* Rxbuffer)
   
 /**
   * @brief This function handles CEC interrupt requests.
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
 void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
@@ -565,7 +563,7 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 
 /**
   * @brief Tx Transfer completed callback
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec)
@@ -579,8 +577,8 @@ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec)
 
 /**
   * @brief Rx Transfer completed callback
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
-  * @param RxFrameSize: Size of frame
+  * @param RxFrameSize Size of frame
   * @retval None
   */
 __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize)
@@ -595,7 +593,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
 
 /**
   * @brief CEC error callbacks
-  * @param hcec: CEC handle
+  * @param hcec CEC handle
   * @retval None
   */
  __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec)
@@ -626,7 +624,7 @@ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize
   */
 /**
   * @brief return the CEC state
-  * @param hcec: pointer to a CEC_HandleTypeDef structure that contains
+  * @param hcec pointer to a CEC_HandleTypeDef structure that contains
   *              the configuration information for the specified CEC module.
   * @retval HAL state
   */
@@ -641,7 +639,7 @@ HAL_CEC_StateTypeDef HAL_CEC_GetState(CEC_HandleTypeDef *hcec)
 
 /**
   * @brief  Return the CEC error code
-  * @param  hcec : pointer to a CEC_HandleTypeDef structure that contains
+  * @param  hcec pointer to a CEC_HandleTypeDef structure that contains
   *              the configuration information for the specified CEC.
   * @retval CEC Error Code
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cec.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_cec.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of CEC HAL module.
   ******************************************************************************
   * @attention
@@ -428,7 +426,7 @@ typedef struct
   */
 
 /** @brief  Reset CEC handle gstate & RxState
-  * @param  __HANDLE__: CEC handle.
+  * @param  __HANDLE__ CEC handle.
   * @retval None
   */
 #define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{                                                   \
@@ -437,8 +435,8 @@ typedef struct
                                                      } while(0U)
 
 /** @brief  Checks whether or not the specified CEC interrupt flag is set.
-  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __HANDLE__ specifies the CEC Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
   *            @arg CEC_FLAG_TXERR: Tx Error.
   *            @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@@ -457,8 +455,8 @@ typedef struct
 #define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->ISR & (__FLAG__)) 
 
 /** @brief  Clears the interrupt or status flag when raised (write at 1U)
-  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __HANDLE__ specifies the CEC Handle.
-  * @param  __FLAG__: specifies the interrupt/status flag to clear.
+  * @param  __FLAG__ specifies the interrupt/status flag to clear.
   *        This parameter can be one of the following values:
   *            @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
   *            @arg CEC_FLAG_TXERR: Tx Error.
@@ -478,8 +476,8 @@ typedef struct
 #define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__)         ((__HANDLE__)->Instance->ISR |= (__FLAG__)) 
 
 /** @brief  Enables the specified CEC interrupt.
-  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __HANDLE__ specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the CEC interrupt to enable.
+  * @param  __INTERRUPT__ specifies the CEC interrupt to enable.
   *          This parameter can be one of the following values:
   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 
   *            @arg CEC_IT_TXERR: Tx Error IT Enable 
@@ -499,8 +497,8 @@ typedef struct
 #define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))  
 
 /** @brief  Disables the specified CEC interrupt.
-  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __HANDLE__ specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the CEC interrupt to disable.
+  * @param  __INTERRUPT__ specifies the CEC interrupt to disable.
   *          This parameter can be one of the following values:
   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 
   *            @arg CEC_IT_TXERR: Tx Error IT Enable 
@@ -520,8 +518,8 @@ typedef struct
 #define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))  
 
 /** @brief  Checks whether or not the specified CEC interrupt is enabled.
-  * @param  __HANDLE__: specifies the CEC Handle.
+  * @param  __HANDLE__ specifies the CEC Handle.
-  * @param  __INTERRUPT__: specifies the CEC interrupt to check.
+  * @param  __INTERRUPT__ specifies the CEC interrupt to check.
   *          This parameter can be one of the following values:
   *            @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable 
   *            @arg CEC_IT_TXERR: Tx Error IT Enable 
@@ -541,52 +539,52 @@ typedef struct
 #define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
 
 /** @brief  Enables the CEC device
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR |=  CEC_CR_CECEN)
 
 /** @brief  Disables the CEC device
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR &=  ~CEC_CR_CECEN)
 
 /** @brief  Set Transmission Start flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__)        ((__HANDLE__)->Instance->CR |=  CEC_CR_TXSOM)
 
 /** @brief  Set Transmission End flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   * If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.  
   */
 #define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__)         ((__HANDLE__)->Instance->CR |=  CEC_CR_TXEOM)
 
 /** @brief  Get Transmission Start flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval FlagStatus 
   */
 #define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
 
 /** @brief  Get Transmission End flag
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval FlagStatus 
   */
 #define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__)   ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)   
 
 /** @brief  Clear OAR register
-  * @param  __HANDLE__: specifies the CEC Handle.               
+  * @param  __HANDLE__ specifies the CEC Handle.               
   * @retval none 
   */
 #define __HAL_CEC_CLEAR_OAR(__HANDLE__)   CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
 
 /** @brief  Set OAR register (without resetting previously set address in case of multi-address mode)
   *          To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
-  * @param  __HANDLE__: specifies the CEC Handle. 
+  * @param  __HANDLE__ specifies the CEC Handle. 
-  * @param  __ADDRESS__: Own Address value (CEC logical address is identified by bit position)                   
+  * @param  __ADDRESS__ Own Address value (CEC logical address is identified by bit position)                   
   * @retval none 
   */
 #define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__)   SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
@@ -701,21 +699,21 @@ uint32_t HAL_CEC_GetError(CEC_HandleTypeDef *hcec);
   *       The message size is the payload size: without counting the header, 
   *       it varies from 0 byte (ping operation, one header only, no payload) to 
   *       15 bytes (1 opcode and up to 14 operands following the header). 
-  * @param  __SIZE__: CEC message size.               
+  * @param  __SIZE__ CEC message size.               
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)  
                                                  
 /** @brief Check CEC device Own Address Register (OAR) setting.
   *        OAR address is written in a 15-bit field within CEC_CFGR register. 
-  * @param  __ADDRESS__: CEC own address.               
+  * @param  __ADDRESS__ CEC own address.               
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
 
 /** @brief Check CEC initiator or destination logical address setting.
   *        Initiator and destination addresses are coded over 4 bits. 
-  * @param  __ADDRESS__: CEC initiator or logical address.               
+  * @param  __ADDRESS__ CEC initiator or logical address.               
   * @retval Test result (TRUE or FALSE).
   */
 #define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU) 

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_comp.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   COMP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the COMP peripheral:

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_comp.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of COMP HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_comp_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_comp_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of COMP HAL Extended module.
   ******************************************************************************
   * @attention
@@ -1491,7 +1489,7 @@
     defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
 /**
   * @brief  Get the specified EXTI line for a comparator instance
-  * @param  __INSTANCE__: specifies the COMP instance.
+  * @param  __INSTANCE__ specifies the COMP instance.
   * @retval value of @ref COMPEx_ExtiLineEvent
   */
 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP2) ? COMP_EXTI_LINE_COMP2 : \
@@ -1504,7 +1502,7 @@
     defined(STM32F302xC)
 /**
   * @brief  Get the specified EXTI line for a comparator instance
-  * @param  __INSTANCE__: specifies the COMP instance.
+  * @param  __INSTANCE__ specifies the COMP instance.
   * @retval value of @ref COMPEx_ExtiLineEvent
   */
 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
@@ -1518,7 +1516,7 @@
     defined(STM32F303xC) || defined(STM32F358xx)
 /**
   * @brief  Get the specified EXTI line for a comparator instance
-  * @param  __INSTANCE__: specifies the COMP instance.
+  * @param  __INSTANCE__ specifies the COMP instance.
   * @retval value of @ref COMPEx_ExtiLineEvent
   */
 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
@@ -1534,7 +1532,7 @@
 #if defined(STM32F373xC) || defined(STM32F378xx)
 /**
   * @brief  Get the specified EXTI line for a comparator instance
-  * @param  __INSTANCE__: specifies the COMP instance.
+  * @param  __INSTANCE__ specifies the COMP instance.
   * @retval value of @ref COMPEx_ExtiLineEvent
   */
 #define COMP_GET_EXTI_LINE(__INSTANCE__) (((__INSTANCE__) == COMP1) ? COMP_EXTI_LINE_COMP1 : \
@@ -1605,7 +1603,7 @@
 
 /**
   * @brief  Enable the Exti Line rising edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1613,7 +1611,7 @@
 
 /**
   * @brief  Disable the Exti Line rising edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1621,7 +1619,7 @@
 
 /**
   * @brief  Enable the Exti Line falling edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1629,7 +1627,7 @@
 
 /**
   * @brief  Disable the Exti Line falling edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1637,7 +1635,7 @@
 
 /**
   * @brief  Enable the COMP Exti Line interrupt generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1645,7 +1643,7 @@
                                              
 /**
   * @brief  Disable the COMP Exti Line interrupt generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */
@@ -1653,7 +1651,7 @@
 
 /**
   * @brief  Enable the COMP Exti Line event generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1661,7 +1659,7 @@
                                              
 /**
   * @brief  Disable the COMP Exti Line event generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */
@@ -1669,7 +1667,7 @@
 
 /**
   * @brief  Check whether the specified EXTI line flag is set or not.
-  * @param  __FLAG__: specifies the COMP Exti sources to be checked.
+  * @param  __FLAG__ specifies the COMP Exti sources to be checked.
   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval The state of __FLAG__ (SET or RESET).
   */
@@ -1677,7 +1675,7 @@
      
 /**
   * @brief Clear the COMP Exti flags.
-  * @param  __FLAG__: specifies the COMP Exti sources to be cleared.
+  * @param  __FLAG__ specifies the COMP Exti sources to be cleared.
   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */
@@ -1716,7 +1714,7 @@
 
 /**
   * @brief  Enable the Exti Line rising edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1724,7 +1722,7 @@
 
 /**
   * @brief  Disable the Exti Line rising edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1732,7 +1730,7 @@
 
 /**
   * @brief  Enable the Exti Line falling edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1740,7 +1738,7 @@
 
 /**
   * @brief  Disable the Exti Line falling edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1748,7 +1746,7 @@
 
 /**
   * @brief  Enable the COMP Exti Line interrupt generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1756,7 +1754,7 @@
                                              
 /**
   * @brief  Disable the COMP Exti Line interrupt generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */
@@ -1764,7 +1762,7 @@
 
 /**
   * @brief  Enable the COMP Exti Line event generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be enabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */                                         
@@ -1772,7 +1770,7 @@
                                              
 /**
   * @brief  Disable the COMP Exti Line event generation.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
+  * @param  __EXTILINE__ specifies the COMP Exti sources to be disabled.
   *         This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */
@@ -1780,7 +1778,7 @@
 
 /**
   * @brief  Check whether the specified EXTI line flag is set or not.
-  * @param  __FLAG__: specifies the COMP Exti sources to be checked.
+  * @param  __FLAG__ specifies the COMP Exti sources to be checked.
   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval The state of __FLAG__ (SET or RESET).
   */
@@ -1788,7 +1786,7 @@
      
 /**
   * @brief Clear the COMP Exti flags.
-  * @param  __FLAG__: specifies the COMP Exti sources to be cleared.
+  * @param  __FLAG__ specifies the COMP Exti sources to be cleared.
   *          This parameter can be a value of @ref COMPEx_ExtiLineEvent 
   * @retval None.
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_conf.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_conf.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   HAL configuration file.
   ******************************************************************************
   * @attention
@@ -162,10 +160,11 @@
   */     
 #define  VDD_VALUE                    (3300U) /*!< Value of VDD in mv */
 #define  TICK_INT_PRIORITY            ((uint32_t)(1U<<__NVIC_PRIO_BITS) - 1U)   /*!< tick interrupt priority (lowest by default) */
-#define  USE_RTOS                     0
+#define  USE_RTOS                     0U
-#define  PREFETCH_ENABLE              1
+#define  PREFETCH_ENABLE              1U
-#define  INSTRUCTION_CACHE_ENABLE     0
+#define  INSTRUCTION_CACHE_ENABLE     0U
-#define  DATA_CACHE_ENABLE            0
+#define  DATA_CACHE_ENABLE            0U
+#define  USE_SPI_CRC                  1U
 
 /* ########################## Assert Selection ############################## */
 /**
@@ -313,7 +312,18 @@
 
 /* Exported macro ------------------------------------------------------------*/
 #ifdef  USE_FULL_ASSERT
-/* ALL MBED targets use same stm32_assert.h */
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr If expr is false, it calls assert_failed function
+  *         which reports the name of the source file and the source
+  *         line number of the call that failed. 
+  *         If expr is true, it returns no value.
+  * @retval None
+  */
+  //#define assert_param(expr) ((expr) ? (void)0U : assert_failed((char *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  //void assert_failed(char* file, uint32_t line);
+// MBED patch. All targets use same stm32_assert.h
 #include "stm32_assert.h"
 #else
   #define assert_param(expr) ((void)0U)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_cortex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   CORTEX HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the CORTEX:
@@ -168,7 +166,7 @@
 /**
   * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
   *         using the required unlock sequence.
-  * @param  PriorityGroup: The priority grouping bits length.
+  * @param  PriorityGroup The priority grouping bits length.
   *         This parameter can be one of the following values:
   *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
   *                                    4 bits for subpriority
@@ -195,13 +193,13 @@ void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 
 /**
   * @brief  Sets the priority of an interrupt.
-  * @param  IRQn: External interrupt number
+  * @param  IRQn External interrupt number
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
-  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
+  * @param  PreemptPriority The pre-emption priority for the IRQn channel.
   *         This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
   *         A lower priority value indicates a higher priority
-  * @param  SubPriority: the subpriority level for the IRQ channel.
+  * @param  SubPriority the subpriority level for the IRQ channel.
   *         This parameter can be a value between 0 and 15 as described in the table CORTEX_NVIC_Priority_Table
   *         A lower priority value indicates a higher priority.
   * @retval None
@@ -266,7 +264,7 @@ void HAL_NVIC_SystemReset(void)
 /**
   * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
   *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
+  * @param  TicksNumb Specifies the ticks Number of ticks between two interrupts.
   * @retval status:  - 0  Function succeeded.
   *                  - 1  Function failed.
   */
@@ -311,7 +309,7 @@ void HAL_MPU_Disable(void)
 
 /**
   * @brief  Enables the MPU
-  * @param  MPU_Control: Specifies the control mode of the MPU during hard fault, 
+  * @param  MPU_Control Specifies the control mode of the MPU during hard fault, 
   *          NMI, FAULTMASK and privileged access to the default memory 
   *          This parameter can be one of the following values:
   *            @arg MPU_HFNMI_PRIVDEF_NONE
@@ -331,7 +329,7 @@ void HAL_MPU_Enable(uint32_t MPU_Control)
 	
 	/**
   * @brief  Initializes and configures the Region and the memory to be protected.
-  * @param  MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains
+  * @param  MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains
   *                the initialization and configuration information.
   * @retval None
   */
@@ -387,7 +385,7 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
 
 /**
   * @brief  Gets the priority of an interrupt.
-  * @param  IRQn: External interrupt number
+  * @param  IRQn External interrupt number
   *         This parameter can be an enumerator of IRQn_Type enumeration
   *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f3xxxx.h))
   * @param   PriorityGroup: the priority grouping bits length.
@@ -402,8 +400,8 @@ uint32_t HAL_NVIC_GetPriorityGrouping(void)
   *                                      1 bits for subpriority
   *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
   *                                      0 bits for subpriority
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
+  * @param  pPreemptPriority Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
+  * @param  pSubPriority Pointer on the Subpriority value (starting from 0).
   * @retval None
   */
 void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
@@ -471,7 +469,7 @@ uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
 
 /**
   * @brief  Configures the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
+  * @param  CLKSource specifies the SysTick clock source.
   *         This parameter can be one of the following values:
   *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
   *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_cortex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_cortex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of CORTEX HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_crc.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   CRC HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
@@ -115,7 +113,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
 /**
   * @brief  Initialize the CRC according to the specified
   *         parameters in the CRC_InitTypeDef and initialize the associated handle.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
@@ -192,7 +190,7 @@ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
 
 /**
   * @brief  DeInitialize the CRC peripheral. 
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
@@ -236,7 +234,7 @@ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
 
 /**
   * @brief  Initializes the CRC MSP.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
@@ -251,7 +249,7 @@ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
 
 /**
   * @brief  DeInitialize the CRC MSP.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
   * @retval None
   */
 __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
@@ -291,10 +289,10 @@ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
 /**                  
   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
   *         starting with the previously computed CRC as initialization value.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
   *         provided by hcrc->InputDataFormat.  
-  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
   *         number of words if pBuffer type is * uint32_t).
   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
@@ -351,10 +349,10 @@ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_
 /**                  
   * @brief  Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer
   *         starting with hcrc->Instance->INIT as initialization value.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  pBuffer: pointer to the input data buffer, exact input data format is
+  * @param  pBuffer pointer to the input data buffer, exact input data format is
   *         provided by hcrc->InputDataFormat.  
-  * @param  BufferLength: input data buffer length (number of bytes if pBuffer
+  * @param  BufferLength input data buffer length (number of bytes if pBuffer
   *         type is * uint8_t, number of half-words if pBuffer type is * uint16_t,
   *         number of words if pBuffer type is * uint32_t).
   * @note  By default, the API expects a uint32_t pointer as input buffer parameter.
@@ -433,7 +431,7 @@ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t
 
 /**
   * @brief  Return the CRC handle state.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
   * @retval HAL state
   */
 HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
@@ -454,6 +452,7 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
   * @{
   */
 
+// MBED patch
 #if __GNUC__
 #    define MAY_ALIAS __attribute__ ((__may_alias__))
 #else
@@ -462,13 +461,14 @@ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
 
 typedef __IO uint8_t  MAY_ALIAS uint8_io_t;
 typedef __IO uint16_t MAY_ALIAS uint16_io_t;
+// MBED patch
 
 /**             
   * @brief  Enter 8-bit input data to the CRC calculator.
   *         Specific data handling to optimize processing time.  
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  pBuffer: pointer to the input data buffer
+  * @param  pBuffer pointer to the input data buffer
-  * @param  BufferLength: input data buffer length
+  * @param  BufferLength input data buffer length
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */
 static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength)
@@ -487,16 +487,16 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
    {
      if  (BufferLength%4U == 1U)
      {
-       *(uint8_io_t*) (&hcrc->Instance->DR) = pBuffer[4*i];
+       *(uint8_io_t*) (&hcrc->Instance->DR) = pBuffer[4*i]; // MBED patch
      }
      if  (BufferLength%4U == 2U)
      {
-       *(uint16_io_t*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+       *(uint16_io_t*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; // MBED patch
      }
      if  (BufferLength%4U == 3U)
      {
-       *(uint16_io_t*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1];
+       *(uint16_io_t*) (&hcrc->Instance->DR) = ((uint32_t)pBuffer[4*i]<<8) | (uint32_t)pBuffer[4*i+1]; // MBED patch
-       *(uint8_io_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2];
+       *(uint8_io_t*) (&hcrc->Instance->DR) = pBuffer[4*i+2]; // MBED patch
      }
    }
   
@@ -509,9 +509,9 @@ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_
 /**             
   * @brief  Enter 16-bit input data to the CRC calculator.
   *         Specific data handling to optimize processing time.  
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  pBuffer: pointer to the input data buffer
+  * @param  pBuffer pointer to the input data buffer
-  * @param  BufferLength: input data buffer length
+  * @param  BufferLength input data buffer length
   * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits)
   */  
 static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength)
@@ -527,7 +527,7 @@ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint3
   }
   if ((BufferLength%2U) != 0U)
   {
-       *(uint16_io_t*) (&hcrc->Instance->DR) = pBuffer[2*i];
+       *(uint16_io_t*) (&hcrc->Instance->DR) = pBuffer[2*i]; // MBED patch
   }
    
   /* Return the CRC computed value */ 

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_crc.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of CRC HAL module.
   ******************************************************************************
   * @attention
@@ -231,37 +229,37 @@ typedef struct
   */
 
 /** @brief Reset CRC handle state.
-  * @param  __HANDLE__: CRC handle.
+  * @param  __HANDLE__ CRC handle.
   * @retval None
   */
 #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
 
 /**
   * @brief  Reset CRC Data Register.
-  * @param  __HANDLE__: CRC handle
+  * @param  __HANDLE__ CRC handle
   * @retval None
   */
 #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET)
 
 /**
   * @brief  Set CRC INIT non-default value
-* @param  __HANDLE__: CRC handle
+* @param  __HANDLE__ CRC handle
-  * @param  __INIT__: 32-bit initial value  
+  * @param  __INIT__ 32-bit initial value  
   * @retval None
   */
 #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__))    
 
 /**
   * @brief Store a 8-bit data in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
+  * @param __HANDLE__ CRC handle
-  * @param __VALUE__: 8-bit value to be stored in the ID register
+  * @param __VALUE__ 8-bit value to be stored in the ID register
   * @retval None
   */
 #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__)))
 
 /**
   * @brief Return the 8-bit data stored in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
+  * @param __HANDLE__ CRC handle
   * @retval 8-bit value of the ID register 
   */
 #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_crc_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Extended CRC HAL module driver.
   *          This file provides firmware functions to manage the extended 
   *          functionalities of the CRC peripheral.  
@@ -91,12 +89,12 @@
 
 /**
   * @brief  Initialize the CRC polynomial if different from default one.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  Pol: CRC generating polynomial (7, 8, 16 or 32-bit long).
+  * @param  Pol CRC generating polynomial (7, 8, 16 or 32-bit long).
   *         This parameter is written in normal representation, e.g.
   *         @arg for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 
   *         @arg for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021     
-  * @param  PolyLength: CRC polynomial length. 
+  * @param  PolyLength CRC polynomial length. 
   *         This parameter can be one of the following values:
   *          @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7)
   *          @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8)
@@ -159,8 +157,8 @@ HAL_StatusTypeDef HAL_CRCEx_Polynomial_Set(CRC_HandleTypeDef *hcrc, uint32_t Pol
 
 /**
   * @brief  Set the Reverse Input data mode.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  InputReverseMode: Input Data inversion mode.
+  * @param  InputReverseMode Input Data inversion mode.
   *         This parameter can be one of the following values:
   *          @arg CRC_INPUTDATA_NOINVERSION: no change in bit order (default value)
   *          @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal
@@ -187,8 +185,8 @@ HAL_StatusTypeDef HAL_CRCEx_Input_Data_Reverse(CRC_HandleTypeDef *hcrc, uint32_t
 
 /**
   * @brief  Set the Reverse Output data mode.
-  * @param  hcrc: CRC handle
+  * @param  hcrc CRC handle
-  * @param  OutputReverseMode: Output Data inversion mode.
+  * @param  OutputReverseMode Output Data inversion mode.
   *         This parameter can be one of the following values:
   *          @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value)
   *          @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g. for a 8-bit CRC: 0xB5 becomes 0xAD)            

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_crc_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_crc_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of CRC HAL extension module.
   ******************************************************************************
   * @attention
@@ -92,22 +90,22 @@
     
 /**
   * @brief  Set CRC output reversal
-  * @param  __HANDLE__: CRC handle
+  * @param  __HANDLE__ CRC handle
   * @retval None.
   */
 #define  __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)   
 
 /**
   * @brief  Unset CRC output reversal
-  * @param  __HANDLE__: CRC handle
+  * @param  __HANDLE__ CRC handle
   * @retval None.
   */
 #define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))   
 
 /**
   * @brief  Set CRC non-default polynomial
-  * @param  __HANDLE__: CRC handle
+  * @param  __HANDLE__ CRC handle
-  * @param  __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial  
+  * @param  __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial  
   * @retval None.
   */
 #define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dac.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   DAC HAL module driver.
   *         This file provides firmware functions to manage the following 
   *         functionalities of the Digital to Analog Converter (DAC) peripheral:
@@ -274,7 +272,7 @@
 /**
   * @brief  Initialize the DAC peripheral according to the specified parameters
   *         in the DAC_InitStruct and initialize the associated handle.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL status
   */
@@ -312,7 +310,7 @@ HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Deinitialize the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL status
   */
@@ -348,7 +346,7 @@ HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Initialize the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -364,7 +362,7 @@ __weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  DeInitialize the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.  
   * @retval None
   */
@@ -403,9 +401,9 @@ __weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
@@ -427,9 +425,9 @@ __weak HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel
 
 /**
   * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
@@ -453,9 +451,9 @@ HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
 
 /**
   * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
@@ -520,9 +518,9 @@ HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
 
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
@@ -544,7 +542,7 @@ __weak uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
 
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval The selected DAC channel data output value.
   */
@@ -584,10 +582,10 @@ __weak uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
+  * @param  sConfig DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
@@ -659,7 +657,7 @@ __weak HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_
 
 /**
   * @brief  return the DAC handle state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval HAL state
   */
@@ -671,7 +669,7 @@ HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval DAC Error Code
   */
@@ -690,7 +688,7 @@ uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
 
 /**
   * @brief  Conversion complete callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -706,7 +704,7 @@ __weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -722,7 +720,7 @@ __weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -739,7 +737,7 @@ __weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
 
 /**
   * @brief  DMA underrun DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dac.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of DAC HAL module.
   ******************************************************************************
   * @attention
@@ -226,48 +224,48 @@ typedef struct __DAC_HandleTypeDef
   */
 
 /** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __HANDLE__ specifies the DAC handle.
   * @retval None
   */
 #define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
 
 /** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
+  * @param  __DAC_Channel__ specifies the DAC channel
   * @retval None
   */
 #define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
 ((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
 
 /** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
+  * @param  __DAC_Channel__ specifies the DAC channel.
   * @retval None
   */
 #define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
 ((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
  
 /** @brief Set DHR12R1 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) ((0x00000008U) + (__ALIGNMENT__))
 
 /** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) ((0x00000014U) + (__ALIGNMENT__))
 
 /** @brief  Set DHR12RD alignment
-  * @param  __ALIGNMENT__: specifies the DAC alignment
+  * @param  __ALIGNMENT__ specifies the DAC alignment
   * @retval None
   */
 #define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) ((0x00000020U) + (__ALIGNMENT__))
 
 /** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -276,8 +274,8 @@ typedef struct __DAC_HandleTypeDef
 #define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
 
 /** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
+  * @param  __HANDLE__ specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
+  * @param  __INTERRUPT__ specifies the DAC interrupt.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -286,8 +284,8 @@ typedef struct __DAC_HandleTypeDef
 #define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
 
 /** @brief  Check whether the specified DAC interrupt source is enabled or not
-  * @param __HANDLE__: DAC handle
+  * @param __HANDLE__ DAC handle
-  * @param __INTERRUPT__: DAC interrupt source to check
+  * @param __INTERRUPT__ DAC interrupt source to check
   *          This parameter can be any combination of the following values:
   *            @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
   *            @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -296,8 +294,8 @@ typedef struct __DAC_HandleTypeDef
 #define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
 
 /** @brief  Get the selected DAC's flag status
-  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to get.
+  * @param  __FLAG__ specifies the DAC flag to get.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag
@@ -306,8 +304,8 @@ typedef struct __DAC_HandleTypeDef
 #define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief  Clear the DAC's flag
-  * @param  __HANDLE__: specifies the DAC handle.
+  * @param  __HANDLE__ specifies the DAC handle.
-  * @param  __FLAG__: specifies the DAC flag to clear.
+  * @param  __FLAG__ specifies the DAC flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DAC_FLAG_DMAUDR1: DAC channel 1 DMA underrun flag
   *            @arg DAC_FLAG_DMAUDR2: DAC channel 2 DMA underrun flag

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dac_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   DACEx HAL module driver.
   *          This file provides firmware functions to manage the extended 
   *          functionalities of the DAC peripheral.  
@@ -116,15 +114,15 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma);
 
 /**
   * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
   *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
+  * @param  Data Data to be loaded in the selected data holding register.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
@@ -172,9 +170,9 @@ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, ui
 /* DAC channel 2 is present in DAC 1U */
 /**
   * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
+  * @param  Alignment Specifies the data alignment for dual channel DAC.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -249,9 +247,9 @@ HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Align
 /* DAC 1 has 2 channels 1U & 2U - DAC 2 has one channel 1U */
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 or DAC2 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -310,9 +308,9 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
 /* DAC 1 has 1 channels 1U */
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   * @retval HAL status 
@@ -360,15 +358,15 @@ HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
 /* DAC 1 has 2 channels 1U & 2U */
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
+  * @param  pData The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -494,14 +492,14 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
 /* DAC 1 has 1 channel (channel 1U)  */
 /**
   * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
-  * @param  pData: The destination peripheral Buffer address.
+  * @param  pData The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
+  * @param  Length The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
+  * @param  Alignment Specifies the data alignment for DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
   *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
@@ -581,9 +579,9 @@ HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, u
 /* DAC 1 has 2 channels 1U & 2U */
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
@@ -615,9 +613,9 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
 /* DAC 1 has 1 channel (channel 1U)  */
 /**
   * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  channel: The selected DAC channel. 
+  * @param  channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   * @retval The selected DAC channel data output value.
@@ -636,7 +634,7 @@ uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
 
 /**
   * @brief  Return the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval The selected DAC channel data output value.
   */
@@ -670,7 +668,7 @@ uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
   * @brief  Handles DAC interrupt request
   *         This function uses the interruption of DMA
   *         underrun.  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -733,7 +731,7 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
   * @brief  Handles DAC interrupt request
   *         This function uses the interruption of DMA
   *         underrun.  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -767,10 +765,10 @@ void HAL_DAC_IRQHandler(struct __DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
+  * @param  sConfig DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
+  * @param  Channel The selected DAC channel. 
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected  
@@ -854,13 +852,13 @@ HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConf
 
 /**
   * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
-  * @param  Amplitude: Select max triangle amplitude.
+  * @param  Amplitude Select max triangle amplitude.
   *          This parameter can be one of the following values:
   *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
   *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
@@ -904,13 +902,13 @@ HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32
 
 /**
   * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel.
+  * @param  Channel The selected DAC channel.
   *          This parameter can be one of the following values:
   *            @arg DAC_CHANNEL_1: DAC1 Channel1 selected
   *            @arg DAC_CHANNEL_2: DAC1 Channel2 selected
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation.
+  * @param  Amplitude Unmask DAC channel LFSR for noise wave generation.
   *          This parameter can be one of the following values:
   *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
   *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation
@@ -958,7 +956,7 @@ HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t
 /* DAC channel 2 is available on top of DAC channel 1U */
 /**
   * @brief  Conversion complete callback in non blocking mode for Channel2
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -974,7 +972,7 @@ __weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -990,7 +988,7 @@ __weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
 
 /**
   * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -1006,7 +1004,7 @@ __weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
 
 /**
   * @brief  DMA underrun DAC callback for channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
+  * @param  hdac pointer to a DAC_HandleTypeDef structure that contains
   *         the configuration information for the specified DAC.
   * @retval None
   */
@@ -1041,7 +1039,7 @@ __weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
   
 /**
   * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
@@ -1055,7 +1053,7 @@ static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
@@ -1067,7 +1065,7 @@ static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
@@ -1089,7 +1087,7 @@ static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)
 /* DAC channel 2 is available on top of DAC channel 1U */
 /**
   * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
@@ -1103,7 +1101,7 @@ static void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
@@ -1115,7 +1113,7 @@ static void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA error callback 
-  * @param  hdma: pointer to DMA handle.
+  * @param  hdma pointer to DMA handle.
   * @retval None
   */
 static void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dac_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dac_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of DAC HAL Extended module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_def.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_def.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   This file contains HAL common defines, enumeration, macros and 
   *          structures definitions. 
   ******************************************************************************
@@ -46,7 +44,9 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx.h"
-#include "stm32_hal_legacy.h"
+#if defined USE_LEGACY
+#include "stm32_hal_legacy.h" // MBED patch
+#endif
 #include <stdio.h>
 
 /* Exported types ------------------------------------------------------------*/
@@ -86,7 +86,7 @@ typedef enum
 #define UNUSED(x) ((void)(x))
                          
 /** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
+  * @param __HANDLE__ specifies the Peripheral Handle.
   * @note  This macro can be used for the following purpose:
   *          - When the Handle is declared as local variable; before passing it as parameter
   *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro
@@ -122,9 +122,13 @@ typedef enum
                                       (__HANDLE__)->Lock = HAL_UNLOCKED;    \
                                     }while (0U)
 #endif /* USE_RTOS */
+
+// MBED patch
 #if defined (__CC_ARM)
 #pragma diag_suppress 3731
 #endif
+
+// MBED patch
 static inline  void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
 {
 	uint32_t newValue;
@@ -134,7 +138,7 @@ static inline  void atomic_set_u32(volatile uint32_t *ptr, uint32_t mask)
 	} while (__STREXW(newValue, ptr));
 }
 
-
+// MBED patch
 static inline  void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
 {
 	uint32_t newValue;
@@ -144,6 +148,7 @@ static inline  void atomic_clr_u32(volatile uint32_t *ptr, uint32_t mask)
 	} while (__STREXW(newValue, ptr));
 }
 
+// MBED patch
 #if  defined ( __GNUC__ ) && !defined ( __CC_ARM )
   #ifndef __weak
     #define __weak   __attribute__((weak))

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dma.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   DMA HAL module driver.
   *    
   *         This file provides firmware functions to manage the following 
@@ -148,7 +146,7 @@ static void DMA_CalcBaseAndBitshift(DMA_HandleTypeDef *hdma);
 /**
   * @brief  Initialize the DMA according to the specified
   *         parameters in the DMA_InitTypeDef and initialize the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval HAL status
   */
@@ -216,7 +214,7 @@ HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
   
 /**
   * @brief  DeInitialize the DMA peripheral 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval HAL status
   */
@@ -291,9 +289,9 @@ HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
   * @brief  Start the DMA Transfer.
   * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
+  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -336,11 +334,11 @@ HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, ui
 
 /**
   * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
+  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -465,10 +463,10 @@ HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Polling for transfer complete.
-  * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma    pointer to a DMA_HandleTypeDef structure that contains
   *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel: Specifies the DMA level complete.  
+  * @param  CompleteLevel Specifies the DMA level complete.  
-  * @param  Timeout:       Timeout duration.
+  * @param  Timeout       Timeout duration.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
@@ -568,7 +566,7 @@ HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t Comp
 
 /**
   * @brief  Handle DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval None
   */
@@ -656,11 +654,11 @@ void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Register callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
   *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
+  * @param  CallbackID           User Callback identifer
   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
-  * @param  pCallback:            pointer to private callback function which has pointer to 
+  * @param  pCallback            pointer to private callback function which has pointer to 
   *                               a DMA_HandleTypeDef structure as parameter.
   * @retval HAL status
   */                          
@@ -709,9 +707,9 @@ HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Call
 
 /**
   * @brief  UnRegister callbacks
-  * @param  hdma:                 pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma                 pointer to a DMA_HandleTypeDef structure that contains
   *                               the configuration information for the specified DMA Stream.
-  * @param  CallbackID:           User Callback identifer
+  * @param  CallbackID           User Callback identifer
   *                               a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
   * @retval HAL status
   */              
@@ -787,7 +785,7 @@ HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_Ca
 
 /**
   * @brief  Returns the DMA state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA Channel.  
   * @retval HAL state
   */
@@ -798,7 +796,7 @@ HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Return the DMA error code
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *              the configuration information for the specified DMA Channel.
   * @retval DMA Error Code
   */
@@ -821,11 +819,11 @@ uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  Set the DMA Transfer parameters.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
+  * @param  SrcAddress The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
+  * @param  DstAddress The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
+  * @param  DataLength The length of data to be transferred from source to destination
   * @retval HAL status
   */
 static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -858,7 +856,7 @@ static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t
 
 /**
   * @brief  Set the DMA base address and channel index depending on DMA instance
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma       pointer to a DMA_HandleTypeDef structure that contains
   *                     the configuration information for the specified DMA Stream. 
   * @retval None
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dma.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of DMA HAL module.
   ******************************************************************************
   * @attention
@@ -299,21 +297,21 @@ typedef struct __DMA_HandleTypeDef
   */
 
 /** @brief  Reset DMA handle state
-  * @param  __HANDLE__: DMA handle.
+  * @param  __HANDLE__ DMA handle.
   * @retval None
   */
 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
 
 /**
   * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval None
   */
 #define __HAL_DMA_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
 
 /**
   * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval None
   */
 #define __HAL_DMA_DISABLE(__HANDLE__)       ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
@@ -323,8 +321,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Enables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -335,8 +333,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Disables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
+  * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled. 
   *          This parameter can be any combination of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -347,8 +345,8 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Checks whether the specified DMA Channel interrupt is enabled or disabled.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
+  * @param  __INTERRUPT__ specifies the DMA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg DMA_IT_TC:  Transfer complete interrupt mask
   *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
@@ -359,7 +357,7 @@ typedef struct __DMA_HandleTypeDef
 
 /**
   * @brief  Returns the number of remaining data units in the current DMAy Channelx transfer.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   *   
   * @retval The number of remaining data units in the current DMA Channel transfer.
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_dma_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_dma_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of DMA HAL extension module.
   ******************************************************************************
   * @attention
@@ -67,7 +65,7 @@
     defined(STM32F373xC) || defined(STM32F378xx)
 /**
   * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer complete flag index.
   */
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -86,7 +84,7 @@
 
 /**
   * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -105,7 +103,7 @@
 
 /**
   * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -124,7 +122,7 @@
 
 /**
   * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@@ -143,8 +141,8 @@
 
 /**
   * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __FLAG__ Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -158,8 +156,8 @@
 
 /**
   * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -182,7 +180,7 @@
 
 /**
   * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer complete flag index.
   */
 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -196,7 +194,7 @@
 
 /**
   * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified half transfer complete flag index.
   */      
 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -210,7 +208,7 @@
 
 /**
   * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -224,7 +222,7 @@
 
 /**
   * @brief  Return the current DMA Channel Global interrupt flag.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
   * @retval The specified transfer error flag index.
   */
 #define __HAL_DMA_GET_GI_FLAG_INDEX(__HANDLE__)\
@@ -238,8 +236,8 @@
 
 /**
   * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__: Get the specified flag.
+  * @param  __FLAG__ Get the specified flag.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag
@@ -252,8 +250,8 @@
 
 /**
   * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
+  * @param  __HANDLE__ DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
+  * @param  __FLAG__ specifies the flag to clear.
   *          This parameter can be any combination of the following values:
   *            @arg DMA_FLAG_TCx:  Transfer complete flag
   *            @arg DMA_FLAG_HTx:  Half transfer complete flag

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_flash.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   FLASH HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the internal FLASH memory:
@@ -437,7 +435,7 @@ void HAL_FLASH_IRQHandler(void)
 
 /**
   * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                 - Mass Erase: No return value expected
   *                 - Pages Erase: Address of the page which has been erased 
   *                    (if 0xFFFFFFFF, it means that all the selected pages have been erased)
@@ -456,7 +454,7 @@ __weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
 
 /**
   * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
+  * @param  ReturnValue The value saved in this parameter depends on the ongoing procedure
   *                 - Mass Erase: No return value expected
   *                 - Pages Erase: Address of the page which returned an error
   *                 - Program: Address which was selected for data program

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_flash.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of Flash HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_flash_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Extended FLASH HAL module driver.
   *    
   *          This file provides firmware functions to manage the following 
@@ -912,7 +910,6 @@ static uint32_t FLASH_OB_GetWRP(void)
   */
 static uint32_t FLASH_OB_GetRDP(void)
 {
-  uint32_t readstatus = OB_RDP_LEVEL_0;
   uint32_t tmp_reg = 0U;
   
   /* Read RDP level bits */
@@ -930,7 +927,7 @@ static uint32_t FLASH_OB_GetRDP(void)
   if (tmp_reg == FLASH_OBR_LEVEL1_PROT)
 #endif /* FLASH_OBR_LEVEL1_PROT */
   {
-    readstatus = OB_RDP_LEVEL_1;
+    return OB_RDP_LEVEL_1;
   }
 #if   defined(FLASH_OBR_RDPRT)
   else if (tmp_reg == FLASH_OBR_RDPRT_2)
@@ -938,14 +935,12 @@ static uint32_t FLASH_OB_GetRDP(void)
   else if (tmp_reg == FLASH_OBR_LEVEL2_PROT)
 #endif
   {
-    readstatus = OB_RDP_LEVEL_2;
+    return OB_RDP_LEVEL_2;
   }
   else 
   {
-    readstatus = OB_RDP_LEVEL_0;
+    return OB_RDP_LEVEL_0;
   }
-
-  return readstatus;
 }
 
 /**

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_flash_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_flash_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of Flash HAL Extended module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_gpio.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   GPIO HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
@@ -182,8 +180,8 @@
 
 /**
   * @brief  Initialize the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family devices
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
+  * @param  GPIO_Init pointer to a GPIO_InitTypeDef structure that contains
   *         the configuration information for the specified GPIO peripheral.
   * @retval None
   */
@@ -307,8 +305,8 @@ void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
 
 /**
   * @brief  De-initialize the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F30X device or STM32F37X device
-  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  GPIO_Pin specifies the port bit to be written.
   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
   * @retval None
   */
@@ -389,8 +387,8 @@ void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
 
 /**
   * @brief  Read the specified input port pin.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
-  * @param  GPIO_Pin: specifies the port bit to read.
+  * @param  GPIO_Pin specifies the port bit to read.
   *         This parameter can be GPIO_PIN_x where x can be (0..15).
   * @retval The input port pin value.
   */
@@ -419,10 +417,10 @@ GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   *         accesses. In this way, there is no risk of an IRQ occurring between
   *         the read and the modify access.
   *
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
-  * @param  GPIO_Pin: specifies the port bit to be written.
+  * @param  GPIO_Pin specifies the port bit to be written.
   *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
+  * @param  PinState specifies the value to be written to the selected bit.
   *         This parameter can be one of the GPIO_PinState enum values:
   *            @arg GPIO_PIN_RESET: to clear the port pin
   *            @arg GPIO_PIN_SET: to set the port pin
@@ -446,8 +444,8 @@ void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState Pin
 
 /**
   * @brief  Toggle the specified GPIO pin.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
-  * @param  GPIO_Pin: specifies the pin to be toggled.
+  * @param  GPIO_Pin specifies the pin to be toggled.
   * @retval None
   */
 void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
@@ -464,8 +462,8 @@ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
   *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
   * @note   The configuration of the locked GPIO pins can no longer be modified
   *         until the next reset.
-  * @param  GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F3 family
+  * @param  GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F3 family
-  * @param  GPIO_Pin: specifies the port bits to be locked.
+  * @param  GPIO_Pin specifies the port bits to be locked.
   *         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
   * @retval None
   */
@@ -500,7 +498,7 @@ HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
 
 /**
   * @brief  Handle EXTI interrupt request.
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
   * @retval None
   */
 void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
@@ -515,7 +513,7 @@ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
 
 /**
   * @brief  EXTI line detection callback.
-  * @param  GPIO_Pin: Specifies the port pin connected to corresponding EXTI line.
+  * @param  GPIO_Pin Specifies the port pin connected to corresponding EXTI line.
   * @retval None
   */
 __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_gpio.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of GPIO HAL module.
   ******************************************************************************
   * @attention
@@ -181,7 +179,7 @@ typedef enum
   
 /**
   * @brief  Check whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line flag to check.
   *         This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -189,7 +187,7 @@ typedef enum
 
 /**
   * @brief  Clear the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
+  * @param  __EXTI_LINE__ specifies the EXTI lines flags to clear.
   *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -197,7 +195,7 @@ typedef enum
 
 /**
   * @brief  Check whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval The new state of __EXTI_LINE__ (SET or RESET).
   */
@@ -205,7 +203,7 @@ typedef enum
 
 /**
   * @brief  Clear the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
+  * @param  __EXTI_LINE__ specifies the EXTI lines to clear.
   *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
   * @retval None
   */
@@ -213,7 +211,7 @@ typedef enum
 
 /**
   * @brief  Generate a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
+  * @param  __EXTI_LINE__ specifies the EXTI line to check.
   *          This parameter can be GPIO_PIN_x where x can be(0..15)
   * @retval None
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_gpio_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_gpio_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of GPIO HAL Extended module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_hrtim.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_hrtim.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of HRTIM HAL module.
   ******************************************************************************
   * @attention
@@ -1330,8 +1328,9 @@ typedef struct {
   * @brief Constants defining whether or not an external event is programmed in
            fast mode
   */
-#define HRTIM_EVENTFASTMODE_DISABLE         (0x00000000U)            /*!< External Event is acting asynchronously on outputs (low latency mode) */
+
-#define HRTIM_EVENTFASTMODE_ENABLE          (HRTIM_EECR1_EE1FAST)    /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define HRTIM_EVENTFASTMODE_ENABLE 	(0x00000000U) 		/*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
+#define HRTIM_EVENTFASTMODE_DISABLE 	(HRTIM_EECR1_EE1FAST) 	/*!< External Event is acting asynchronously on outputs (low latency mode) */
 /**
   * @}
   */
@@ -2701,14 +2700,14 @@ typedef struct {
   */
 
 /** @brief Reset HRTIM handle state
-  * @param  __HANDLE__: HRTIM handle.
+  * @param  __HANDLE__ HRTIM handle.
   * @retval None
   */
 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
 
 /** @brief  Enables or disables the timer counter(s)
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __TIMERS__: timers to enable/disable
+  * @param  __TIMERS__ timers to enable/disable
   *        This parameter can be any combinations of the following values:
   *            @arg HRTIM_TIMERID_MASTER: Master timer identifier
   *            @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
@@ -2771,8 +2770,8 @@ typedef struct {
   } while(0U)
                        
 /** @brief  Enables or disables the specified HRTIM common interrupts.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
@@ -2788,8 +2787,8 @@ typedef struct {
 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
 
 /** @brief  Enables or disables the specified HRTIM Master timer interrupts.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
@@ -2804,9 +2803,9 @@ typedef struct {
 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
 
 /** @brief  Enables or disables the specified HRTIM Timerx interrupts.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __TIMER__: specified the timing unit (Timer A to E)
+  * @param  __TIMER__ specified the timing unit (Timer A to E)
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
@@ -2828,8 +2827,8 @@ typedef struct {
 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
 
 /** @brief  Checks if the specified HRTIM common interrupt  source  is enabled or disabled.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to check.
+  * @param  __INTERRUPT__ specifies the interrupt source to check.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
@@ -2844,8 +2843,8 @@ typedef struct {
 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks if the specified HRTIM Master interrupt source  is enabled or disabled.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to check.
+  * @param  __INTERRUPT__ specifies the interrupt source to check.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
@@ -2859,9 +2858,9 @@ typedef struct {
 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks if the specified HRTIM Timerx interrupt source  is enabled or disabled.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __TIMER__: specified the timing unit (Timer A to E)
+  * @param  __TIMER__ specified the timing unit (Timer A to E)
-  * @param  __INTERRUPT__: specifies the interrupt source to check.
+  * @param  __INTERRUPT__ specifies the interrupt source to check.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
@@ -2889,8 +2888,8 @@ typedef struct {
 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__)     ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Clears the specified HRTIM common pending flag.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
@@ -2905,8 +2904,8 @@ typedef struct {
 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__)) 
 
 /** @brief  Clears the specified HRTIM Master pending flag.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
   *            @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
@@ -2920,9 +2919,9 @@ typedef struct {
 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__)) 
 
 /** @brief  Clears the specified HRTIM Timerx pending flag.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __TIMER__: specified the timing unit (Timer A to E)
+  * @param  __TIMER__ specified the timing unit (Timer A to E)
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
+  * @param  __INTERRUPT__ specifies the interrupt pending bit to clear.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
   *            @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
@@ -2944,8 +2943,8 @@ typedef struct {
 
 /* DMA HANDLING */
 /** @brief  Enables or disables the specified HRTIM common interrupts.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
   *            @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
@@ -2961,8 +2960,8 @@ typedef struct {
 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
 
 /** @brief  Enables or disables the specified HRTIM Master timer DMA requets.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __DMA__: specifies the DMA request to enable or disable.
+  * @param  __DMA__ specifies the DMA request to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
   *            @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
@@ -2977,9 +2976,9 @@ typedef struct {
 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
 
 /** @brief  Enables or disables the specified HRTIM Timerx DMA requests.
-  * @param  __HANDLE__: specifies the HRTIM Handle.
+  * @param  __HANDLE__ specifies the HRTIM Handle.
-  * @param  __TIMER__: specified the timing unit (Timer A to E)
+  * @param  __TIMER__ specified the timing unit (Timer A to E)
-  * @param  __DMA__: specifies the DMA request to enable or disable.
+  * @param  __DMA__ specifies the DMA request to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
   *            @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
@@ -3010,12 +3009,12 @@ typedef struct {
 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__,  __TIMER__, __FLAG__)      ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
 
 /** @brief  Sets the HRTIM timer Counter Register value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x5 for master timer
   *                   @arg 0x0 to 0x4 for timers A to E 
-  * @param  __COUNTER__: specifies the Counter Register new value.
+  * @param  __COUNTER__ specifies the Counter Register new value.
   * @retval None
   */
 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
@@ -3023,8 +3022,8 @@ typedef struct {
    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
     
 /** @brief  Gets the HRTIM timer Counter Register value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x5 for master timer
   *                   @arg 0x0 to 0x4 for timers A to E 
@@ -3035,12 +3034,12 @@ typedef struct {
    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
     
 /** @brief  Sets the HRTIM timer Period value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x5 for master timer
   *                   @arg 0x0 to 0x4 for timers A to E 
-  * @param  __PERIOD__: specifies the Period Register new value.
+  * @param  __PERIOD__ specifies the Period Register new value.
   * @retval None
   */
 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
@@ -3048,8 +3047,8 @@ typedef struct {
    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
     
 /** @brief  Gets the HRTIM timer Period Register value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x5 for master timer
   *                   @arg 0x0 to 0x4 for timers A to E 
@@ -3060,12 +3059,12 @@ typedef struct {
    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
     
 /** @brief  Sets the HRTIM timer clock prescaler value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x5 for master timer
   *                   @arg 0x0 to 0x4 for timers A to E 
-  * @param  __PRESCALER__: specifies the clock prescaler new value.
+  * @param  __PRESCALER__ specifies the clock prescaler new value.
   *                   This parameter can be one of the following values:
   *                   @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
   *                   @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
@@ -3078,12 +3077,12 @@ typedef struct {
   * @retval None
   */
 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
-  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__PRESCALER__)) :\
+  (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
-   ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR |= (__PRESCALER__)))
+   (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
 
 /** @brief  Gets the HRTIM timer clock prescaler value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x5 for master timer
   *                   @arg 0x0 to 0x4 for timers A to E 
@@ -3094,17 +3093,17 @@ typedef struct {
    ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR  & HRTIM_TIMCR_CK_PSC))
 
 /** @brief  Sets the HRTIM timer Compare Register value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x0 to 0x4 for timers A to E 
-  * @param  __COMPAREUNIT__: timer compare unit
+  * @param  __COMPAREUNIT__ timer compare unit
   *                   This parameter can be one of the following values:
   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2
   *                   @arg HRTIM_COMPAREUNIT_3: Compare unit 3
   *                   @arg HRTIM_COMPAREUNIT_4: Compare unit 4
-  * @param  __COMPARE__: specifies the Compare new value.
+  * @param  __COMPARE__ specifies the Compare new value.
   * @retval None
   */
 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
@@ -3120,11 +3119,11 @@ typedef struct {
          ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
         
 /** @brief  Gets the HRTIM timer Compare Register value on runtime
-  * @param  __HANDLE__: HRTIM Handle.
+  * @param  __HANDLE__ HRTIM Handle.
-  * @param  __TIMER__: HRTIM timer
+  * @param  __TIMER__ HRTIM timer
   *                   This parameter can be one of the following values:
   *                   @arg 0x0 to 0x4 for timers A to E 
-  * @param  __COMPAREUNIT__: timer compare unit
+  * @param  __COMPAREUNIT__ timer compare unit
   *                   This parameter can be one of the following values:
   *                   @arg HRTIM_COMPAREUNIT_1: Compare unit 1
   *                   @arg HRTIM_COMPAREUNIT_2: Compare unit 2

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2c.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   I2C HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -1833,7 +1831,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress
         }
       }
 
-    }while(hi2c->XferCount > 0U);
+    }
+    while (hi2c->XferCount > 0U);
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is reset */
@@ -1978,7 +1977,8 @@ HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress,
           I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
         }
       }
-    }while(hi2c->XferCount > 0U);
+    }
+    while (hi2c->XferCount > 0U);
 
     /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
     /* Wait until STOPF flag is reset */
@@ -2544,7 +2544,8 @@ HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAdd
         /* Clear STOP Flag */
         __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
       }
-    }while(I2C_Trials < Trials);
+    }
+    while (I2C_Trials < Trials);
 
     hi2c->State = HAL_I2C_STATE_READY;
 
@@ -2591,7 +2592,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
-    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED patch
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If size > MAX_NBYTE_SIZE, use reload mode */
@@ -2606,6 +2607,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c,
       xfermode = hi2c->XferOptions;
     }
 
+    /* If transfer direction not change, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    // MBED patch
+    /*if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }*/
+
     /* Send Slave Address and set NBYTES to write */
     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
 
@@ -2657,7 +2666,7 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
     /* Prepare transfer parameters */
     hi2c->pBuffPtr    = pData;
     hi2c->XferCount   = Size;
-    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+    hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED patch
     hi2c->XferISR     = I2C_Master_ISR_IT;
 
     /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
@@ -2672,6 +2681,14 @@ HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c,
       xfermode = hi2c->XferOptions;
     }
 
+    /* If transfer direction not change, do not generate Restart Condition */
+    /* Mean Previous state is same as current state */
+    // MBED patch
+    /*if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+    {
+      xferrequest = I2C_NO_STARTSTOP;
+    }*/
+
     /* Send Slave Address and set NBYTES to read */
     I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
 
@@ -3077,8 +3094,8 @@ __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
   * @brief  Slave Address Match callback.
   * @param  hi2c Pointer to a I2C_HandleTypeDef structure that contains
   *                the configuration information for the specified I2C.
-  * @param  TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+  * @param  TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
-  * @param  AddrMatchCode: Address Match Code
+  * @param  AddrMatchCode Address Match Code
   * @retval None
   */
 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -4417,7 +4434,7 @@ static void I2C_DMAError(DMA_HandleTypeDef *hdma)
 /**
   * @brief DMA I2C communication abort callback
   *        (To be called at end of DMA Abort procedure).
-  * @param hdma: DMA handle.
+  * @param hdma DMA handle.
   * @retval None
   */
 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2c.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of I2C HAL module.
   ******************************************************************************
   * @attention
@@ -506,7 +504,7 @@ typedef struct __I2C_HandleTypeDef
 #define __HAL_I2C_DISABLE(__HANDLE__)                           (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 
 /** @brief  Generate a Non-Acknowledge I2C peripheral in Slave mode.
-  * @param  __HANDLE__: specifies the I2C Handle. 
+  * @param  __HANDLE__ specifies the I2C Handle.
   * @retval None
   */
 #define __HAL_I2C_GENERATE_NACK(__HANDLE__)                     (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2c_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   I2C Extended HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of I2C Extended peripheral:

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2c_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2c_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of I2C HAL Extended module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2s.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   I2S HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -343,13 +341,13 @@ HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
   * @brief Transmit an amount of data in blocking mode
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
+  * @param pData a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
   *       the Size parameter means the number of 16-bit data length. 
-  * @param  Timeout: Timeout duration
+  * @param  Timeout Timeout duration
   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
   *       between Master and Slave(example: audio streaming).
   * @retval HAL status
@@ -434,13 +432,13 @@ HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uin
   * @brief Receive an amount of data in blocking mode 
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
+  * @param pData a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
   *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
+  * @param Timeout Timeout duration
   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
   *       between Master and Slave(example: audio streaming).
   * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
@@ -537,8 +535,8 @@ HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint
   * @brief Transmit an amount of data in non-blocking mode with Interrupt
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
+  * @param pData a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -600,8 +598,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   * @brief Receive an amount of data in non-blocking mode with Interrupt
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
+  * @param pData a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -664,8 +662,8 @@ HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, u
   * @brief Transmit an amount of data in non-blocking mode with DMA
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Transmit data buffer.
+  * @param pData a 16-bit pointer to the Transmit data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -742,8 +740,8 @@ HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData,
   * @brief Receive an amount of data in non-blocking mode with DMA 
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
+  * @param pData a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -1133,7 +1131,7 @@ uint32_t HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
   */
 /**
   * @brief DMA I2S transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1154,7 +1152,7 @@ static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief DMA I2S transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1167,7 +1165,7 @@ static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief DMA I2S receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1187,7 +1185,7 @@ static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief DMA I2S receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1200,7 +1198,7 @@ static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief DMA I2S communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma pointer to a DMA_HandleTypeDef structure that contains
   *                the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1267,9 +1265,9 @@ static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
   * @brief This function handles I2S Communication Timeout.
   * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
   *         the configuration information for I2S module
-  * @param Flag: Flag checked
+  * @param Flag Flag checked
-  * @param State: Value of the flag expected
+  * @param State Value of the flag expected
-  * @param Timeout: Duration of the timeout
+  * @param Timeout Duration of the timeout
   * @retval HAL status
   */
 static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State, uint32_t Timeout)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2s.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of I2S HAL module.
   ******************************************************************************
   * @attention
@@ -324,21 +322,21 @@ typedef struct
   */
 
 /** @brief  Reset I2S handle state
-  * @param  __HANDLE__: I2S handle.
+  * @param  __HANDLE__ I2S handle.
   * @retval None
   */
 #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
 
 /** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
+  * @param  __HANDLE__ specifies the I2S Handle. 
   * @retval None
   */
 #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
 #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= (uint16_t)(~SPI_I2SCFGR_I2SE))
 
 /** @brief  Enable or disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -349,9 +347,9 @@ typedef struct
 #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (uint16_t)(~(__INTERRUPT__)))
  
 /** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
+  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -361,8 +359,8 @@ typedef struct
 #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -376,7 +374,7 @@ typedef struct
 #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */                                                                                                   
 #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{ \
@@ -386,7 +384,7 @@ typedef struct
                                                UNUSED(tmpreg); \
                                               }while(0U)
 /** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */                                                                                                   
 #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) do{\

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2s_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   I2S Extended HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of I2S Extended peripheral:
@@ -19,21 +17,7 @@
         called I2Sxext ie. I2S2ext for SPI2 and I2S3ext for SPI3).
     (#) The Extended block is not a full SPI IP, it is used only as I2S slave to
         implement full duplex mode. The Extended block uses the same clock sources
-        as its master (refer to the following Figure).
+        as its master.
-
-                +-----------------------+
-    I2Sx_SCK    |                       |
-  ----------+-->|          I2Sx         |------------------->I2Sx_SD(in/out)
-         +--|-->|                       |
-        |   |   +-----------------------+
-        |   |          
- I2S_WS |   |           
- ------>|   |          
-        |   |   +-----------------------+
-        |   +-->|                       |
-        |       |       I2Sx_ext        |------------------->I2Sx_extSD(in/out)
-         +----->|                       |
-                +-----------------------+
 
     (#) Both I2Sx and I2Sx_ext can be configured as transmitters or receivers.
 
@@ -114,6 +98,23 @@
   *
   ******************************************************************************
   */
+/*
+  Additional Figure: The Extended block uses the same clock sources as its master.
+
+                +-----------------------+
+    I2Sx_SCK    |                       |
+  ----------+-->|          I2Sx         |------------------->I2Sx_SD(in/out)
+         +--|-->|                       |
+        |   |   +-----------------------+
+        |   |          
+ I2S_WS |   |           
+ ------>|   |          
+        |   |   +-----------------------+
+        |   +-->|                       |
+        |       |       I2Sx_ext        |------------------->I2Sx_extSD(in/out)
+         +----->|                       |
+                +-----------------------+
+*/
 
 /* Includes ------------------------------------------------------------------*/
 #include "stm32f3xx_hal.h"
@@ -157,6 +158,7 @@ typedef enum
   * @{
   */
 static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma);
+static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
 static void I2S_TxRxDMAError(DMA_HandleTypeDef *hdma);
 static void I2S_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
 static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
@@ -535,7 +537,22 @@ __weak void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
   UNUSED(hi2s);
 
   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxRxCpltCallback could be implenetd in the user file
+            the HAL_I2S_TxRxCpltCallback could be implemented in the user file
+   */
+}
+
+/**
+  * @brief Tx and Rx Transfer half completed callbacks
+  * @param hi2s: I2S handle
+  * @retval None
+  */
+__weak void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+  /* Prevent unused argument(s) compilation warning */
+  UNUSED(hi2s);
+
+  /* NOTE : This function Should not be modified, when the callback is needed,
+            the HAL_I2S_TxRxHalfCpltCallback could be implemented in the user file
    */
 }
 
@@ -752,6 +769,7 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
 
     (#) A set of Transfer Complete Callbacks are provided in No_Blocking mode:
         (++) HAL_I2S_TxRxCpltCallback()
+        (++) HAL_I2S_TxRxHalfCpltCallback()
         (++) HAL_I2S_TxRxErrorCallback()
 
 @endverbatim
@@ -761,14 +779,14 @@ HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
 /**
   * @brief Full-Duplex Transmit/Receive data in blocking mode.
   * @param hi2s: I2S handle
-  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+  * @param pTxData a 16-bit pointer to the Transmit data buffer.
-  * @param pRxData: a 16-bit pointer to the Receive data buffer.
+  * @param pRxData a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
   *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
+  * @param Timeout Timeout duration
   * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
   *       between Master and Slave(example: audio streaming).
   * @retval HAL status
@@ -999,9 +1017,9 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive(I2S_HandleTypeDef *hi2s, uint16_t *p
 /**
   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt 
   * @param hi2s: I2S handle
-  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+  * @param pTxData a 16-bit pointer to the Transmit data buffer.
-  * @param pRxData: a 16-bit pointer to the Receive data buffer.
+  * @param pRxData a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -1147,9 +1165,9 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_IT(I2S_HandleTypeDef *hi2s, uint16_t
 /**
   * @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA  
   * @param hi2s: I2S handle
-  * @param pTxData: a 16-bit pointer to the Transmit data buffer.
+  * @param pTxData a 16-bit pointer to the Transmit data buffer.
-  * @param pRxData: a 16-bit pointer to the Receive data buffer.
+  * @param pRxData a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
+  * @param Size number of data sample to be sent:
   * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
   *       configuration phase, the Size parameter means the number of 16-bit data length 
   *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
@@ -1201,13 +1219,18 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
     /* Set the I2S Rx DMA transfer complete callback */
     hi2s->hdmarx->XferCpltCallback = I2S_TxRxDMACplt;
 
-    /* Set the DMA error callback */
+    /* Set the I2S Rx DMA Half transfer complete callback */
+    hi2s->hdmarx->XferHalfCpltCallback = I2S_TxRxDMAHalfCplt;
+
+    /* Set the I2S Rx DMA error callback */
     hi2s->hdmarx->XferErrorCallback = I2S_TxRxDMAError;
 
-    /* Set the I2S Tx DMA transfer complete callback */
+    /* Set the I2S Tx DMA transfer callbacks as NULL because the
-    hi2s->hdmatx->XferCpltCallback = I2S_TxRxDMACplt;
+    communication closing is performed in DMA reception callbacks */
+    hi2s->hdmatx->XferCpltCallback = NULL;
+    hi2s->hdmatx->XferHalfCpltCallback = NULL;
 
-    /* Set the DMA error callback */
+    /* Set the I2S Tx DMA error callback */
     hi2s->hdmatx->XferErrorCallback = I2S_TxRxDMAError;
     
     /* Check if the I2S_MODE_MASTER_TX or I2S_MODE_SLAVE_TX Mode is selected */
@@ -1297,56 +1320,42 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
 
 /**
   * @brief DMA I2S transmit receive process complete callback 
-  * @param hdma: DMA handle
+  * @param hdma DMA handle
   * @retval None
   */
 static void I2S_TxRxDMACplt(DMA_HandleTypeDef *hdma)   
 {
   I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
 
-  if (hi2s->hdmarx == hdma)
+  /* DMA Normal Mode */
+  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0U)
   {
-    /* Disable Rx DMA Request */
+    /* Disable Rx/Tx DMA Request */
     if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
     {
+      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
     }
     else
     {
       hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_RXDMAEN);
-    }
-
-    hi2s->RxXferCount = 0U;
-
-    if (hi2s->TxXferCount == 0U)
-    {
-      hi2s->State = HAL_I2S_STATE_READY;
-
-      HAL_I2S_TxRxCpltCallback(hi2s); 
-    }
-  }
-  
-  if (hi2s->hdmatx == hdma)
-  {
-    /* Disable Tx DMA Request */
-    if(((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_TX) || ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_SLAVE_TX))
-    {
-      hi2s->Instance->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
-    }
-    else
-    {
       I2SxEXT(hi2s->Instance)->CR2 &= (uint32_t)(~SPI_CR2_TXDMAEN);
     }
 
+    hi2s->RxXferCount = 0U;
     hi2s->TxXferCount = 0U;
 
-    if (hi2s->RxXferCount == 0U)
-    {
     hi2s->State = HAL_I2S_STATE_READY;
+  }
 
   HAL_I2S_TxRxCpltCallback(hi2s);
 }
-  }
+
+static void I2S_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+  I2S_HandleTypeDef* hi2s = ( I2S_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+
+  HAL_I2S_TxRxHalfCpltCallback(hi2s);
 }
       
 /**
@@ -1467,9 +1476,9 @@ static void I2S_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
 /**
   * @brief This function handles I2S Communication Timeout.
   * @param hi2s: I2S handle
-  * @param Flag: Flag checked
+  * @param Flag Flag checked
-  * @param State: Value of the flag expected
+  * @param State Value of the flag expected
-  * @param Timeout: Duration of the timeout
+  * @param Timeout Duration of the timeout
   * @param i2sUsed: I2S instance reference
   * @retval HAL status
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_i2s_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_i2s_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of I2S HAL Extended module.
   ******************************************************************************
   * @attention
@@ -69,15 +67,15 @@
 #define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
 
 /** @brief  Enable or disable the specified I2SExt peripheral.
-  * @param  __HANDLE__: specifies the I2S Handle. 
+  * @param  __HANDLE__ specifies the I2S Handle. 
   * @retval None
   */
 #define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
 #define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
 
 /** @brief  Enable or disable the specified I2SExt interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
+  * @param  __INTERRUPT__ specifies the interrupt source to enable or disable.
   *        This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -88,9 +86,9 @@
 #define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
 
 /** @brief  Checks if the specified I2SExt interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
+  * @param  __INTERRUPT__ specifies the I2S interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
   *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -100,8 +98,8 @@
 #define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 
 /** @brief  Checks whether the specified I2SExt flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
   *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -115,13 +113,13 @@
 #define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
 
 /** @brief Clears the I2SExt OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */                                                                                                   
 #define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{(I2SxEXT((__HANDLE__)->Instance)->DR;\
                                                   (I2SxEXT((__HANDLE__)->Instance)->SR;}while(0U)
 /** @brief Clears the I2SExt UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
+  * @param  __HANDLE__ specifies the I2S Handle.
   * @retval None
   */                                                                                                   
 #define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__)(I2SxEXT((__HANDLE__)->Instance)->SR)    
@@ -176,6 +174,8 @@ HAL_StatusTypeDef HAL_I2SEx_TransmitReceive_DMA(I2S_HandleTypeDef *hi2s, uint16_
 /* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
 void HAL_I2S_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
 void HAL_I2S_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
+/* Callback used in non blocking modes (DMA only) */
+void HAL_I2S_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
 /**
   * @}
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_irda.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   IRDA HAL module driver.
   *          This file provides firmware functions to manage the following
   *          functionalities of the IrDA (Infrared Data Association) Peripheral
@@ -1569,7 +1567,7 @@ __weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
 
 /**
   * @brief  Rx Half Transfer complete callback.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
+  * @param  hirda Pointer to a IRDA_HandleTypeDef structure that contains
   *                the configuration information for the specified IRDA module.
   * @retval None
   */
@@ -1942,7 +1940,7 @@ static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief  DMA IRDA receive process complete callback.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param  hdma Pointer to a DMA_HandleTypeDef structure that contains
   *               the configuration information for the specified DMA module.
   * @retval None
   */
@@ -1972,7 +1970,7 @@ static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
 
 /**
   * @brief DMA IRDA receive process half complete callback.
-  * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+  * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
   *              the configuration information for the specified DMA module.
   * @retval None
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_irda.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   This file contains all the functions prototypes for the IRDA 
   *          firmware library.
   ******************************************************************************
@@ -400,7 +398,7 @@ typedef enum
   */
 
 /** @brief  Reset IRDA handle state.
-  * @param  __HANDLE__: IRDA handle.
+  * @param  __HANDLE__ IRDA handle.
   * @retval None
   */
 #define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__)  do{                                                   \
@@ -409,7 +407,7 @@ typedef enum
                                                      } while(0U)
 
 /** @brief  Flush the IRDA DR register.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__)                            \
@@ -419,8 +417,8 @@ typedef enum
       } while(0U)
 
 /** @brief  Clear the specified IRDA pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *          This parameter can be any combination of the following values:
   *            @arg @ref IRDA_CLEAR_PEF
   *            @arg @ref IRDA_CLEAR_FEF
@@ -433,39 +431,39 @@ typedef enum
 #define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 
 /** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
 
 
 /** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
 
 /** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
 
 /** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__)    __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
 
 /** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__)   __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
 
 /** @brief  Check whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __FLAG__: specifies the flag to check.
+  * @param  __FLAG__ specifies the flag to check.
   *        This parameter can be one of the following values:
   *            @arg @ref IRDA_FLAG_REACK Receive enable acknowledge flag
   *            @arg @ref IRDA_FLAG_TEACK Transmit enable acknowledge flag
@@ -485,8 +483,8 @@ typedef enum
 
 
 /** @brief  Enable the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to enable.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
@@ -501,8 +499,8 @@ typedef enum
                                                            ((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & IRDA_IT_MASK))))
 
 /** @brief  Disable the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
+  * @param  __INTERRUPT__ specifies the IRDA interrupt source to disable.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE  Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC   Transmission complete interrupt
@@ -518,8 +516,8 @@ typedef enum
 
 
 /** @brief  Check whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __IT__: specifies the IRDA interrupt source to check.
+  * @param  __IT__ specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
@@ -534,8 +532,8 @@ typedef enum
 #define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & (1U << ((__IT__)>> 0x08U)))
 
 /** @brief  Check whether the specified IRDA interrupt source is enabled or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __IT__: specifies the IRDA interrupt source to check.
+  * @param  __IT__ specifies the IRDA interrupt source to check.
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_IT_TXE Transmit Data Register empty interrupt
   *            @arg @ref IRDA_IT_TC  Transmission complete interrupt
@@ -550,8 +548,8 @@ typedef enum
 
 
 /** @brief  Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+  * @param  __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
   *                       to clear the corresponding interrupt
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_CLEAR_PEF Parity Error Clear Flag
@@ -565,8 +563,8 @@ typedef enum
 
 
 /** @brief  Set a specific IRDA request flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __REQ__: specifies the request flag to set
+  * @param  __REQ__ specifies the request flag to set
   *          This parameter can be one of the following values:
   *            @arg @ref IRDA_AUTOBAUD_REQUEST Auto-Baud Rate Request
   *            @arg @ref IRDA_RXDATA_FLUSH_REQUEST Receive Data flush Request
@@ -577,25 +575,25 @@ typedef enum
 #define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
 
 /** @brief  Enable the IRDA one bit sample method.
-  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @param  __HANDLE__ specifies the IRDA Handle.  
   * @retval None
   */
 #define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
 
 /** @brief  Disable the IRDA one bit sample method.
-  * @param  __HANDLE__: specifies the IRDA Handle.  
+  * @param  __HANDLE__ specifies the IRDA Handle.  
   * @retval None
   */
 #define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
 
 /** @brief  Enable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_ENABLE(__HANDLE__)                   ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
 
 /** @brief  Disable UART/USART associated to IRDA Handle.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None
   */
 #define __HAL_IRDA_DISABLE(__HANDLE__)                  ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
@@ -610,20 +608,20 @@ typedef enum
   */
 
 /** @brief  Ensure that IRDA Baud rate is less or equal to maximum value.
-  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+  * @param  __BAUDRATE__ specifies the IRDA Baudrate set by the user.
   * @retval True or False
   */
 #define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201U)
 
 /** @brief  Ensure that IRDA prescaler value is strictly larger than 0.
-  * @param  __PRESCALER__: specifies the IRDA prescaler value set by the user.
+  * @param  __PRESCALER__ specifies the IRDA prescaler value set by the user.
   * @retval True or False
   */
 #define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0U)
 
 /**
   * @brief Ensure that IRDA frame parity is valid.
-  * @param __PARITY__: IRDA frame parity. 
+  * @param __PARITY__ IRDA frame parity. 
   * @retval SET (__PARITY__ is valid) or RESET (__PARITY__ is invalid)
   */ 
 #define IS_IRDA_PARITY(__PARITY__) (((__PARITY__) == IRDA_PARITY_NONE) || \
@@ -632,14 +630,14 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA communication mode is valid.
-  * @param __MODE__: IRDA communication mode. 
+  * @param __MODE__ IRDA communication mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_IRDA_TX_RX_MODE(__MODE__) ((((__MODE__) & (~((uint32_t)(IRDA_MODE_TX_RX)))) == 0x00U) && ((__MODE__) != 0x00U))
 
 /**
   * @brief Ensure that IRDA power mode is valid.
-  * @param __MODE__: IRDA power mode. 
+  * @param __MODE__ IRDA power mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_IRDA_POWERMODE(__MODE__) (((__MODE__) == IRDA_POWERMODE_LOWPOWER) || \
@@ -647,7 +645,7 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA state is valid.
-  * @param __STATE__: IRDA state mode. 
+  * @param __STATE__ IRDA state mode. 
   * @retval SET (__STATE__ is valid) or RESET (__STATE__ is invalid)
   */ 
 #define IS_IRDA_STATE(__STATE__) (((__STATE__) == IRDA_STATE_DISABLE) || \
@@ -655,7 +653,7 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA associated UART/USART mode is valid.
-  * @param __MODE__: IRDA associated UART/USART mode. 
+  * @param __MODE__ IRDA associated UART/USART mode. 
   * @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
   */ 
 #define IS_IRDA_MODE(__MODE__)  (((__MODE__) == IRDA_MODE_DISABLE) || \
@@ -663,7 +661,7 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA sampling rate is valid.
-  * @param __ONEBIT__: IRDA sampling rate. 
+  * @param __ONEBIT__ IRDA sampling rate. 
   * @retval SET (__ONEBIT__ is valid) or RESET (__ONEBIT__ is invalid)
   */ 
 #define IS_IRDA_ONE_BIT_SAMPLE(__ONEBIT__)      (((__ONEBIT__) == IRDA_ONE_BIT_SAMPLE_DISABLE) || \
@@ -671,7 +669,7 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA DMA TX mode is valid.
-  * @param __DMATX__: IRDA DMA TX mode. 
+  * @param __DMATX__ IRDA DMA TX mode. 
   * @retval SET (__DMATX__ is valid) or RESET (__DMATX__ is invalid)
   */ 
 #define IS_IRDA_DMA_TX(__DMATX__)     (((__DMATX__) == IRDA_DMA_TX_DISABLE) || \
@@ -679,7 +677,7 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA DMA RX mode is valid.
-  * @param __DMARX__: IRDA DMA RX mode. 
+  * @param __DMARX__ IRDA DMA RX mode. 
   * @retval SET (__DMARX__ is valid) or RESET (__DMARX__ is invalid)
   */ 
 #define IS_IRDA_DMA_RX(__DMARX__) (((__DMARX__) == IRDA_DMA_RX_DISABLE) || \
@@ -687,7 +685,7 @@ typedef enum
 
 /**
   * @brief Ensure that IRDA request is valid.
-  * @param __PARAM__: IRDA request. 
+  * @param __PARAM__ IRDA request. 
   * @retval SET (__PARAM__ is valid) or RESET (__PARAM__ is invalid)
   */ 
 #define IS_IRDA_REQUEST_PARAMETER(__PARAM__) (((__PARAM__) == IRDA_AUTOBAUD_REQUEST) || \

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_irda_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_irda_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of IRDA HAL Extended module.
   ******************************************************************************
   * @attention
@@ -93,8 +91,8 @@
   */
 
 /** @brief  Report the IRDA clock source.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
-  * @param  __CLOCKSOURCE__: output variable.
+  * @param  __CLOCKSOURCE__ output variable.
   * @retval IRDA clocking source, written in __CLOCKSOURCE__.
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -330,7 +328,7 @@
   *         by the reception API().
   *         This masking operation is not carried out in the case of
   *         DMA transfers.
-  * @param  __HANDLE__: specifies the IRDA Handle.
+  * @param  __HANDLE__ specifies the IRDA Handle.
   * @retval None, the mask to apply to the associated UART RDR register is stored in (__HANDLE__)->Mask field.
   */
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
@@ -403,7 +401,7 @@
        /* STM32F334x8                                  */
 /**
   * @brief Ensure that IRDA frame length is valid.
-  * @param __LENGTH__: IRDA frame length. 
+  * @param __LENGTH__ IRDA frame length. 
   * @retval SET (__LENGTH__ is valid) or RESET (__LENGTH__ is invalid)
   */ 
 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_iwdg.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   IWDG HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the Independent Watchdog (IWDG) peripheral:

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_iwdg.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_iwdg.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of IWDG HAL module.
   ******************************************************************************
   * @attention

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nand.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_nand.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of NAND HAL module.
   ******************************************************************************
   * @attention
@@ -55,70 +53,6 @@
   * @{
   */ 
 
-/** @addtogroup NAND_Private_Constants
-  * @{
-  */
-
-#define NAND_DEVICE1               FMC_BANK2
-#define NAND_DEVICE2               FMC_BANK3
-#define NAND_WRITE_TIMEOUT         (1000U)
-
-#define CMD_AREA                   ((uint32_t)(1U<<16U))  /* A16U = CLE high */
-#define ADDR_AREA                  ((uint32_t)(1U<<17U))  /* A17U = ALE high */
-
-#define NAND_CMD_AREA_A            ((uint8_t)0x00U)
-#define NAND_CMD_AREA_B            ((uint8_t)0x01U)
-#define NAND_CMD_AREA_C            ((uint8_t)0x50U)
-#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
-
-#define NAND_CMD_WRITE0            ((uint8_t)0x80U)
-#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)  
-#define NAND_CMD_ERASE0            ((uint8_t)0x60U)
-#define NAND_CMD_ERASE1            ((uint8_t)0xD0U)  
-#define NAND_CMD_READID            ((uint8_t)0x90U)  
-#define NAND_CMD_STATUS            ((uint8_t)0x70U)
-#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
-#define NAND_CMD_RESET             ((uint8_t)0xFFU)
-
-/* NAND memory status */
-#define NAND_VALID_ADDRESS         (0x00000100U)
-#define NAND_INVALID_ADDRESS       (0x00000200U)
-#define NAND_TIMEOUT_ERROR         (0x00000400U)
-#define NAND_BUSY                  (0x00000000U)
-#define NAND_ERROR                 (0x00000001U)
-#define NAND_READY                 (0x00000040U)
-
-/**
-  * @}
-  */
-
-/** @addtogroup NAND_Private_Macros
-  * @{
-  */
-
-/**
-  * @brief  NAND memory address computation.
-  * @param  __ADDRESS__: NAND memory address.
-  * @param  __HANDLE__ : NAND handle.
-  * @retval NAND Raw address value
-  */
-#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) (((__ADDRESS__)->Page) + \
-                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.ZoneSize)))* ((__HANDLE__)->Info.BlockSize * ((__HANDLE__)->Info.PageSize + (__HANDLE__)->Info.SpareAreaSize))))
-
-/**
-  * @brief  NAND memory address cycling.
-  * @param  __ADDRESS__: NAND memory address.
-  * @retval NAND address cycling value.
-  */
-#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
-#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8U)       /* 2nd addressing cycle */
-#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16U)      /* 3rd addressing cycle */
-#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24U)      /* 4th addressing cycle */
-
-/**
-  * @}
-  */
-
 /* Exported typedef ----------------------------------------------------------*/
 /* Exported types ------------------------------------------------------------*/
 /** @defgroup NAND_Exported_Types NAND Exported Types
@@ -133,7 +67,7 @@ typedef enum
   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
-  HAL_NAND_STATE_ERROR     = 0x03   /*!< NAND error state                     */
+  HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
 }HAL_NAND_StateTypeDef;
    
 /** 
@@ -159,7 +93,7 @@ typedef struct
 {
   uint16_t Page;   /*!< NAND memory Page address    */
 
-  uint16_t Zone;   /*!< NAND memory Zone address  */
+  uint16_t Plane;   /*!< NAND memory Plane address  */
 
   uint16_t Block;  /*!< NAND memory Block address   */
 
@@ -170,16 +104,27 @@ typedef struct
   */ 
 typedef struct
 {
-  uint32_t PageSize;       /*!< NAND memory page (without spare area) size measured in K. bytes */
+  uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes 
+                                              for 8 bits adressing or words for 16 bits addressing             */
 
-  uint32_t SpareAreaSize;  /*!< NAND memory spare area size measured in K. bytes                */
+  uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes 
+                                              for 8 bits adressing or words for 16 bits addressing             */
   
-  uint32_t BlockSize;      /*!< NAND memory block size number of pages                          */
+  uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
 
-  uint32_t BlockNbr;       /*!< NAND memory number of blocks                                    */
+  uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
      
-  uint32_t ZoneSize;       /*!< NAND memory zone size measured in number of blocks              */
+  uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
-}NAND_InfoTypeDef;
+
+  uint32_t        PlaneSize;             /*!< NAND memory plane size measured in number of blocks               */
+
+  FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This 
+                                              parameter is mandatory for some NAND parts after the read 
+                                              command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence. 
+                                              Example: Toshiba THTH58BYG3S0HBAI6.
+                                              This parameter could be ENABLE or DISABLE
+                                              Please check the Read Mode sequnece in the NAND device datasheet */
+}NAND_DeviceConfigTypeDef; 
 
 /** 
   * @brief  NAND handle Structure definition
@@ -194,21 +139,21 @@ typedef struct
 
   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 
-  NAND_InfoTypeDef             Info;       /*!< NAND characteristic information structure    */
+  NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
-}NAND_HandleTypeDef;
 
+}NAND_HandleTypeDef;
 /**
   * @}
   */
 
 /* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros ------------------------------------------------------------*/
 /** @defgroup NAND_Exported_Macros NAND Exported Macros
  * @{
  */ 
 
 /** @brief Reset NAND handle state
-  * @param  __HANDLE__: specifies the NAND handle.
+  * @param  __HANDLE__ specifies the NAND handle.
   * @retval None
   */
 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
@@ -226,9 +171,15 @@ typedef struct
   * @{
   */
 
+/* Initialization/de-initialization functions  ********************************/
 /* Initialization/de-initialization functions  ********************************/
 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
+
+HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
+
+HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
+
 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
@@ -243,13 +194,20 @@ void        HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
   */
 
 /* IO operation functions  ****************************************************/
-HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
-HAL_StatusTypeDef  HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
+
-HAL_StatusTypeDef  HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
-HAL_StatusTypeDef  HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
-HAL_StatusTypeDef  HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
+HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
+HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
+HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
+
 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
+
 uint32_t           HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 
@@ -273,11 +231,8 @@ HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval,
 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions 
   * @{
   */
-
 /* NAND State functions *******************************************************/
 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
-uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
-
 /**
   * @}
   */
@@ -286,6 +241,90 @@ uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
   * @}
   */
     
+/* Private types -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup NAND_Private_Constants NAND Private Constants
+  * @{
+  */
+#define NAND_DEVICE1               FMC_BANK2
+#define NAND_DEVICE2               FMC_BANK3
+#define NAND_WRITE_TIMEOUT         0x01000000U
+
+#define CMD_AREA                   ((uint32_t)(1U<<16U))  /* A16 = CLE high */
+#define ADDR_AREA                  ((uint32_t)(1U<<17U))  /* A17 = ALE high */
+
+#define NAND_CMD_AREA_A            ((uint8_t)0x00)
+#define NAND_CMD_AREA_B            ((uint8_t)0x01)
+#define NAND_CMD_AREA_C            ((uint8_t)0x50)
+#define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30)
+
+#define NAND_CMD_WRITE0            ((uint8_t)0x80)
+#define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10)
+#define NAND_CMD_ERASE0            ((uint8_t)0x60)
+#define NAND_CMD_ERASE1            ((uint8_t)0xD0)
+#define NAND_CMD_READID            ((uint8_t)0x90)
+#define NAND_CMD_STATUS            ((uint8_t)0x70)
+#define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7A)
+#define NAND_CMD_RESET             ((uint8_t)0xFF)
+
+/* NAND memory status */
+#define NAND_VALID_ADDRESS         0x00000100U
+#define NAND_INVALID_ADDRESS       0x00000200U
+#define NAND_TIMEOUT_ERROR         0x00000400U
+#define NAND_BUSY                  0x00000000U
+#define NAND_ERROR                 0x00000001U
+#define NAND_READY                 0x00000040U
+/**
+  * @}
+  */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup NAND_Private_Macros NAND Private Macros
+  * @{
+  */
+
+/**
+  * @brief  NAND memory address computation.
+  * @param  __ADDRESS__ NAND memory address.
+  * @param  __HANDLE__ NAND handle.
+  * @retval NAND Raw address value
+  */
+#define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
+                         (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
+
+/**
+  * @brief  NAND memory Column address computation.
+  * @param  __HANDLE__ NAND handle.
+  * @retval NAND Raw address value
+  */
+#define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
+
+/**
+  * @brief  NAND memory address cycling.
+  * @param  __ADDRESS__ NAND memory address.
+  * @retval NAND address cycling value.
+  */
+#define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
+#define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
+#define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
+#define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
+
+/**
+  * @brief  NAND memory Columns cycling.
+  * @param  __ADDRESS__ NAND memory address.
+  * @retval NAND Column address cycling value.
+  */
+#define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
+#define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
 /**
   * @}
   */ 

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_nor.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   NOR HAL module driver.
   *          This file provides a generic firmware to drive NOR memories mounted 
   *          as external device.
@@ -179,10 +177,10 @@ static uint32_t uwNORMemoryDataWidth  = NOR_MEMORY_8B;
     
 /**
   * @brief  Perform the NOR memory Initialization sequence
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  Timing: pointer to NOR control timing structure 
+  * @param  Timing pointer to NOR control timing structure 
-  * @param  ExtTiming: pointer to NOR extended mode timing structure    
+  * @param  ExtTiming pointer to NOR extended mode timing structure    
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -232,7 +230,7 @@ HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDe
 
 /**
   * @brief  Perform NOR memory De-Initialization sequence
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
@@ -255,7 +253,7 @@ HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  NOR MSP Init
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval None
   */
@@ -271,7 +269,7 @@ __weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  NOR MSP DeInit
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval None
   */
@@ -287,9 +285,9 @@ __weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  NOR MSP Wait fro Ready/Busy signal
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  Timeout: Maximum timeout value
+  * @param  Timeout Maximum timeout value
   * @retval None
   */
 __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
@@ -323,9 +321,9 @@ __weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
   
 /**
   * @brief  Read NOR flash IDs
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  pNOR_ID: pointer to NOR ID structure
+  * @param  pNOR_ID pointer to NOR ID structure
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
@@ -384,7 +382,7 @@ HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_I
 
 /**
   * @brief  Returns the NOR memory to Read mode.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
@@ -432,10 +430,10 @@ HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  Read data from NOR memory 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  pAddress: pointer to Device address
+  * @param  pAddress pointer to Device address
-  * @param  pData: pointer to read data  
+  * @param  pData pointer to read data  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -491,10 +489,10 @@ HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint
 
 /**
   * @brief  Program data to NOR memory 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  pAddress: Device address
+  * @param  pAddress Device address
-  * @param  pData: pointer to the data to write   
+  * @param  pData pointer to the data to write   
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -550,12 +548,12 @@ HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, u
 
 /**
   * @brief  Reads a block of data from the FMC NOR memory.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  uwAddress: NOR memory internal address to read from.
+  * @param  uwAddress NOR memory internal address to read from.
-  * @param  pData: pointer to the buffer that receives the data read from the 
+  * @param  pData pointer to the buffer that receives the data read from the 
   *         NOR memory.
-  * @param  uwBufferSize: number of Half word to read.
+  * @param  uwBufferSize number of Half word to read.
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
@@ -617,13 +615,13 @@ HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress
 /**
   * @brief  Writes a half-word buffer to the FMC NOR memory. This function 
   *         must be used only with S29GL128P NOR memory. 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  uwAddress: NOR memory internal address from which the data 
+  * @param  uwAddress NOR memory internal address from which the data 
   * @note   Some NOR memory need Address aligned to xx bytes (can be aligned to 
   *          64 bytes boundary for example).
-  * @param  pData: pointer to source data buffer. 
+  * @param  pData pointer to source data buffer. 
-  * @param  uwBufferSize: number of Half words to write. 
+  * @param  uwBufferSize number of Half words to write. 
   * @note   The maximum buffer size allowed is NOR memory dependent
   *         (can be 64 Bytes max for example).
   * @retval HAL status
@@ -702,10 +700,10 @@ HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddr
 
 /**
   * @brief  Erase the specified block of the NOR memory 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  BlockAddress: Block to erase address 
+  * @param  BlockAddress Block to erase address 
-  * @param  Address: Device address
+  * @param  Address Device address
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
@@ -762,9 +760,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAdd
 
 /**
   * @brief  Erase the entire NOR chip.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  Address: Device address  
+  * @param  Address Device address  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
@@ -820,9 +818,9 @@ HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
 
 /**
   * @brief  Read NOR flash CFI IDs
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
-  * @param  pNOR_CFI: pointer to NOR CFI IDs structure  
+  * @param  pNOR_CFI pointer to NOR CFI IDs structure  
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
@@ -898,7 +896,7 @@ HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR
     
 /**
   * @brief  Enables dynamically NOR write operation.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
@@ -921,7 +919,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  Disables dynamically NOR write operation.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval HAL status
   */
@@ -966,7 +964,7 @@ HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
   
 /**
   * @brief  return the NOR controller state
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.
   * @retval NOR controller state
   */
@@ -977,10 +975,10 @@ HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
 
 /**
   * @brief  Returns the NOR operation status.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
+  * @param  hnor pointer to a NOR_HandleTypeDef structure that contains
   *                the configuration information for NOR module.   
-  * @param  Address: Device address
+  * @param  Address Device address
-  * @param  Timeout: NOR progamming Timeout
+  * @param  Timeout NOR progamming Timeout
   * @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
   *         or HAL_NOR_STATUS_TIMEOUT
   */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_nor.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_nor.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of NOR HAL module.
   ******************************************************************************
   * @attention
@@ -92,9 +90,9 @@
 
 /**
   * @brief  NOR memory address shifting.
-  * @param  __NOR_ADDRESS: NOR base address 
+  * @param  __NOR_ADDRESS NOR base address 
-  * @param  __NOR_MEMORY_WIDTH_: NOR memory width
+  * @param  __NOR_MEMORY_WIDTH_ NOR memory width
-  * @param  __ADDRESS__: NOR memory address 
+  * @param  __ADDRESS__ NOR memory address 
   * @retval NOR shifted address value
   */
 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
@@ -104,8 +102,8 @@
 
 /**
   * @brief  NOR memory write data to specified address.
-  * @param  __ADDRESS__: NOR memory address 
+  * @param  __ADDRESS__ NOR memory address 
-  * @param  __DATA__: Data to write
+  * @param  __DATA__ Data to write
   * @retval None
   */
 #define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
@@ -203,7 +201,7 @@ typedef struct
   */
 
 /** @brief Reset NOR handle state
-  * @param  __HANDLE__: NOR handle
+  * @param  __HANDLE__ NOR handle
   * @retval None
   */
 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_opamp.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   OPAMP HAL module driver.
   *          This file provides firmware functions to manage the following 
   *          functionalities of the operational amplifiers (OPAMP1,...OPAMP4) 
@@ -170,14 +168,14 @@
     |-----------------|--------|--------|--------|--------|--------|
     |                 | No conn|   X    |   X    |   X    |   X    |
     | Inverting Input | VM0    |  PC5   |  PC5   |  PB10  |  PB10  |
-    | (1U)             | VM1    |  PA3   |  PA5   |  PB2   |  PD8   |
+    | (1)             | VM1    |  PA3   |  PA5   |  PB2   |  PD8   |
     |-----------------|--------|--------|--------|--------|--------|
     |                 | VP0    |  PA1   |  PA7   |  PB0   |  PB13  |
     |  Non Inverting  | VP1    |  PA7   |  PD14  |  PB13  |  PD11  |
     |    Input        | VP2    |  PA3   |  PB0   |  PA1   |  PA4   |
     |                 | VP3    |  PA5   |  PB14  |  PA5   |  PB11  |
     +--------------------------------------------------------------+  
-    (1U): NA in follower mode.
+    (1): NA in follower mode.
            
     Table 2.  OPAMPs outputs for the STM32F3 devices:
     +--------------------------------------------------------------+     
@@ -245,7 +243,7 @@
   *         parameters in the OPAMP_InitTypeDef and create the associated handle.
   * @note   If the selected opamp is locked, initialization can't be performed.
   *         To unlock the configuration, perform a system reset.
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
@@ -376,7 +374,7 @@ HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp)
   * @brief  DeInitializes the OPAMP peripheral 
   * @note   Deinitialization can't be performed if the OPAMP configuration is locked.
   *         To unlock the configuration, perform a system reset.
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
@@ -416,17 +414,17 @@ HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef *hopamp)
 
       /* The OPAMP state is NOT updated */      
     }
-  }
 
     /* Process unlocked */
     __HAL_UNLOCK(hopamp);
+  }
   
   return status;
 }
 
 /**
   * @brief  Initializes the OPAMP MSP.
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval None
   */
 __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
@@ -443,7 +441,7 @@ __weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  DeInitializes OPAMP MSP.
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval None
   */
 __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
@@ -479,7 +477,7 @@ __weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  Start the opamp
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval HAL status
   */
 
@@ -520,7 +518,7 @@ HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  Stop the opamp 
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp)
@@ -760,7 +758,7 @@ HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  Lock the selected opamp configuration. 
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval HAL status
   */
 HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
@@ -815,7 +813,7 @@ HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  Return the OPAMP state
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
   * @retval HAL state
   */
 HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
@@ -834,8 +832,8 @@ HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp)
 
 /**
   * @brief  Return the OPAMP factory trimming value
-  * @param  hopamp: OPAMP handle
+  * @param  hopamp OPAMP handle
-  * @param  trimmingoffset: Trimming offset (P or N)
+  * @param  trimmingoffset Trimming offset (P or N)
   * @retval Trimming value (P or N): range: 0->31
   *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
  */

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_opamp.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of OPAMP HAL module.
   ******************************************************************************
   * @attention
@@ -308,10 +306,10 @@ typedef  uint32_t OPAMP_TrimmingValueTypeDef;
   * @{
   */
 
-#define OPAMP_PGA_GAIN_2                (0x00000000U)                        /*!< PGA gain =  2U */
+#define OPAMP_PGA_GAIN_2                (0x00000000U)                        /*!< PGA gain =  2 */
-#define OPAMP_PGA_GAIN_4                OPAMP_CSR_PGGAIN_0                            /*!< PGA gain =  4U */
+#define OPAMP_PGA_GAIN_4                OPAMP_CSR_PGGAIN_0                            /*!< PGA gain =  4 */
-#define OPAMP_PGA_GAIN_8                OPAMP_CSR_PGGAIN_1                            /*!< PGA gain =  8U */
+#define OPAMP_PGA_GAIN_8                OPAMP_CSR_PGGAIN_1                            /*!< PGA gain =  8 */
-#define OPAMP_PGA_GAIN_16              (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)      /*!< PGA gain = 16U */
+#define OPAMP_PGA_GAIN_16              (OPAMP_CSR_PGGAIN_0 | OPAMP_CSR_PGGAIN_1)      /*!< PGA gain = 16 */
 
 #define IS_OPAMP_PGA_GAIN(GAIN) (((GAIN) == OPAMP_PGA_GAIN_2) || \
                                  ((GAIN) == OPAMP_PGA_GAIN_4) || \
@@ -416,7 +414,7 @@ typedef  uint32_t OPAMP_TrimmingValueTypeDef;
   */
 
 /** @brief Reset OPAMP handle state
-  * @param  __HANDLE__: OPAMP handle.
+  * @param  __HANDLE__ OPAMP handle.
   * @retval None
   */
 #define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp_ex.c

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_opamp_ex.c
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Extended OPAMP HAL module driver.
   *
   *          This file provides firmware functions to manage the following

targets/TARGET_STM/TARGET_STM32F3/device/stm32f3xx_hal_opamp_ex.h

@@ -2,8 +2,6 @@
   ******************************************************************************
   * @file    stm32f3xx_hal_opamp_ex.h
   * @author  MCD Application Team
-  * @version V1.4.0
-  * @date    16-December-2016
   * @brief   Header file of OPAMP HAL Extended module.
   ******************************************************************************
   * @attention