From 8bc92bdd22e79b474ed87e5bac1d52d217ca110c Mon Sep 17 00:00:00 2001 From: jeromecoutant Date: Wed, 13 Dec 2017 10:32:58 +0100 Subject: [PATCH] STM32F4 : compilation issue Issue comes only when ST HAL macro USE_FULL_ASSERT is enabled --- .../TARGET_NUCLEO_F412ZG/system_clock.c | 8 ++++++-- .../TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c | 8 ++++++-- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c index 2ffdfc51c0..191ecaf3ea 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c @@ -176,11 +176,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -241,11 +243,13 @@ uint8_t SetSysClock_PLL_HSI(void) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); diff --git a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c index 34aa173313..66575fd3f6 100644 --- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c @@ -177,11 +177,13 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass) } /* Select PLLSAI output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 8; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct); @@ -242,11 +244,13 @@ uint8_t SetSysClock_PLL_HSI(void) } /* Select PLLI2S output as USB clock source */ + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; PeriphClkInitStruct.PLLI2S.PLLI2SM = 16; PeriphClkInitStruct.PLLI2S.PLLI2SN = 192; PeriphClkInitStruct.PLLI2S.PLLI2SQ = 4; - PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; + PeriphClkInitStruct.PLLI2S.PLLI2SR = 2; PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48CLKSOURCE_PLLI2SQ; + PeriphClkInitStruct.PLLI2SSelection = RCC_PLLI2SCLKSOURCE_PLLSRC; HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);