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Commonalize the files in "targets/TARGET_RENESAS/TARGET_RZ_A1XX" directory 

I made be available in common whatever the board related to RZ_A1 in the below files.
- Since there are the table code of Pinmap differs for each board, I moved the code to "PeripheralPins" file for each board, and changed to include PeripheralPins.h.
  analogin_api.c, can_api.c, gpio_irq_api.c, i2c_api.c, pinmap.c, port_api.c, pwmout_api.c, serial_api.c, spi_api.c and us_ticker.c

- Since there are some board-specific processes, I enclosed the processes with "#ifdef" and rearranged the functions to make be easier to enclose.
  can_api.c, ethernet_api.c and serial_api.c

- Since there are the driver configuration values differs for each board, I added "mbed_drv_cfg.h" file for each board and defined macros for the values, and changed to refer to the macros.
  can_api.c, gpio_api.c, pwmout_api.c and rtc_api.c
pull/5813/head
TomoYamanaka 2018-01-09 18:20:50 +09:00
parent 6f851a820c
commit 8b7e2abdb7
37 changed files with 1699 additions and 6590 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

64
targets/TARGET_RENESAS/TARGET_RZ_A1XX/PeripheralPins.h Normal file
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@ -0,0 +1,64 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_PERIPHERALPINS_H
#define MBED_PERIPHERALPINS_H
#include "pinmap.h"
#include "PeripheralNames.h"
typedef struct {
PinName pin;
int function;
int pm;
} PinFunc;
/************IRQ***************/
extern const PinMap PinMap_IRQ[];
/************PINMAP***************/
extern const PinFunc PIPC_0_tbl[];
/************ADC***************/
extern const PinMap PinMap_ADC[];
/************DAC***************/
extern const PinMap PinMap_DAC[];
/************I2C***************/
extern const PinMap PinMap_I2C_SDA[];
extern const PinMap PinMap_I2C_SCL[];
/************UART***************/
extern const PinMap PinMap_UART_TX[];
extern const PinMap PinMap_UART_RX[];
extern const PinMap PinMap_UART_CTS[];
extern const PinMap PinMap_UART_RTS[];
/************SPI***************/
extern const PinMap PinMap_SPI_SCLK[];
extern const PinMap PinMap_SPI_MOSI[];
extern const PinMap PinMap_SPI_MISO[];
extern const PinMap PinMap_SPI_SSEL[];
/************PWM***************/
extern const PinMap PinMap_PWM[];
/************CAN***************/
extern const PinMap PinMap_CAN_RD[];
extern const PinMap PinMap_CAN_TD[];
#endif

106
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralNames.h
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@ -34,82 +34,31 @@ typedef enum {
UART7, UART7,
} UARTName; } UARTName;
// PWMType & 1 == 1 then have to use PWDTR[12] == 1
typedef enum { typedef enum {
PWM1A = 0, PWM_PWM1A = 0,
PWM1B, PWM_PWM1B,
PWM1C, PWM_PWM1C,
PWM1D, PWM_PWM1D,
PWM1E, PWM_PWM1E,
PWM1F, PWM_PWM1F,
PWM1G, PWM_PWM1G,
PWM1H, PWM_PWM1H,
PWM2A = 0x10, PWM_PWM2A,
PWM2B, PWM_PWM2B,
PWM2C, PWM_PWM2C,
PWM2D, PWM_PWM2D,
PWM2E, PWM_PWM2E,
PWM2F, PWM_PWM2F,
PWM2G, PWM_PWM2G,
PWM2H, PWM_PWM2H,
} PWMType; PWM_TIOC0A = 0x20,
PWM_TIOC0C,
typedef enum { PWM_TIOC1A,
TIOC0A = 0, PWM_TIOC2A,
TIOC0B, PWM_TIOC3A,
TIOC0C, PWM_TIOC3C,
TIOC0D, PWM_TIOC4A,
TIOC1A = 0x10, PWM_TIOC4C,
TIOC1B,
TIOC2A = 0x20,
TIOC2B,
TIOC3A = 0x30,
TIOC3B,
TIOC3C,
TIOC3D,
TIOC4A = 0x40,
TIOC4B,
TIOC4C,
TIOC4D,
} MTU2_PWMType;
typedef enum {
PWM0_PIN = 0,
PWM1_PIN,
PWM2_PIN,
PWM3_PIN,
PWM4_PIN,
PWM5_PIN,
PWM6_PIN,
PWM7_PIN,
PWM8_PIN,
PWM9_PIN,
PWM10_PIN,
PWM11_PIN,
PWM12_PIN,
PWM13_PIN,
MTU2_PWM0_PIN = 0x20,
MTU2_PWM1_PIN,
MTU2_PWM2_PIN,
MTU2_PWM3_PIN,
MTU2_PWM4_PIN,
MTU2_PWM5_PIN,
MTU2_PWM6_PIN,
MTU2_PWM7_PIN,
MTU2_PWM8_PIN,
MTU2_PWM9_PIN,
MTU2_PWM10_PIN,
MTU2_PWM11_PIN,
MTU2_PWM12_PIN,
MTU2_PWM13_PIN,
MTU2_PWM14_PIN,
MTU2_PWM15_PIN,
MTU2_PWM16_PIN,
MTU2_PWM17_PIN,
MTU2_PWM18_PIN,
MTU2_PWM19_PIN,
MTU2_PWM20_PIN,
MTU2_PWM21_PIN,
} PWMName; } PWMName;
typedef enum { typedef enum {
@ -128,21 +77,22 @@ typedef enum {
SPI_1, SPI_1,
SPI_2, SPI_2,
SPI_3, SPI_3,
SPI_4,
} SPIName; } SPIName;
typedef enum { typedef enum {
I2C_0 = 0, I2C_0 = 0,
I2C_1, I2C_1,
I2C_2, I2C_2,
I2C_3 I2C_3,
} I2CName; } I2CName;
typedef enum { typedef enum {
CAN_0 = 0, CAN_0 = 0,
CAN_1, CAN_1,
CAN_2, CAN_2,
CAN_3, CAN_3,
CAN_4 CAN_4,
} CANName; } CANName;

343
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PeripheralPins.c Normal file
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@ -0,0 +1,343 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************IRQ***************/
enum {
IRQ0,IRQ1,
IRQ2,IRQ3,
IRQ4,IRQ5,
IRQ6,IRQ7,
} IRQNo;
const PinMap PinMap_IRQ[] = {
{P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
{P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
{P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
{P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
{P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
{P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
{P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
{P3_9, IRQ6, 8}, // 20
{P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
{P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
{P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
{P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
{P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
{P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
{P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
{P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
{P6_15, IRQ7, 8}, // 44
{P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
{P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
{P7_14, IRQ6, 8}, // 51
{P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
{P9_1, IRQ0, 4}, // 55
{P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
{NC, NC, 0}
};
/************PINMAP***************/
const PinFunc PIPC_0_tbl[] = {
// pin func pm
{P4_0 , 2 , -1}, /* TIOC0A */
{P5_0 , 6 , -1}, /* TIOC0A */
{P7_0 , 7 , -1}, /* TIOC0A */
{P10_4 , 2 , -1}, /* TIOC0A */
{P4_1 , 2 , -1}, /* TIOC0B */
{P5_1 , 6 , -1}, /* TIOC0B */
{P7_1 , 7 , -1}, /* TIOC0B */
{P10_5 , 2 , -1}, /* TIOC0B */
{P4_2 , 2 , -1}, /* TIOC0C */
{P5_5 , 6 , -1}, /* TIOC0C */
{P7_2 , 7 , -1}, /* TIOC0C */
{P10_6 , 2 , -1}, /* TIOC0C */
{P4_3 , 2 , -1}, /* TIOC0D */
{P5_7 , 6 , -1}, /* TIOC0D */
{P7_3 , 7 , -1}, /* TIOC0D */
{P10_7 , 2 , -1}, /* TIOC0D */
{P2_11 , 5 , -1}, /* TIOC1A */
{P6_0 , 5 , -1}, /* TIOC1A */
{P7_4 , 7 , -1}, /* TIOC1A */
{P8_8 , 5 , -1}, /* TIOC1A */
{P9_7 , 4 , -1}, /* TIOC1A */
{P10_8 , 2 , -1}, /* TIOC1A */
{P2_12 , 8 , -1}, /* TIOC1B */
{P5_2 , 6 , -1}, /* TIOC1B */
{P6_1 , 5 , -1}, /* TIOC1B */
{P7_5 , 7 , -1}, /* TIOC1B */
{P8_9 , 5 , -1}, /* TIOC1B */
{P10_9 , 2 , -1}, /* TIOC1B */
{P2_1 , 6 , -1}, /* TIOC2A */
{P6_2 , 6 , -1}, /* TIOC2A */
{P7_6 , 7 , -1}, /* TIOC2A */
{P8_14 , 4 , -1}, /* TIOC2A */
{P10_10 , 2 , -1}, /* TIOC2A */
{P2_2 , 6 , -1}, /* TIOC2B */
{P6_3 , 6 , -1}, /* TIOC2B */
{P7_7 , 7 , -1}, /* TIOC2B */
{P8_15 , 4 , -1}, /* TIOC2B */
{P10_11 , 2 , -1}, /* TIOC2B */
{P10_11 , 2 , -1}, /* TIOC2B */
{P3_4 , 6 , -1}, /* TIOC3A */
{P7_8 , 7 , -1}, /* TIOC3A */
{P8_10 , 4 , -1}, /* TIOC3A */
{P3_5 , 6 , -1}, /* TIOC3B */
{P7_9 , 7 , -1}, /* TIOC3B */
{P8_11 , 4 , -1}, /* TIOC3B */
{P3_6 , 6 , -1}, /* TIOC3C */
{P5_3 , 6 , -1}, /* TIOC3C */
{P7_10 , 7 , -1}, /* TIOC3C */
{P8_12 , 4 , -1}, /* TIOC3C */
{P3_7 , 6 , -1}, /* TIOC3D */
{P5_4 , 6 , -1}, /* TIOC3D */
{P7_11 , 7 , -1}, /* TIOC3D */
{P8_13 , 4 , -1}, /* TIOC3D */
{P3_8 , 6 , -1}, /* TIOC4A */
{P4_4 , 3 , -1}, /* TIOC4A */
{P7_12 , 7 , -1}, /* TIOC4A */
{P11_0 , 2 , -1}, /* TIOC4A */
{P3_9 , 6 , -1}, /* TIOC4B */
{P4_5 , 3 , -1}, /* TIOC4B */
{P7_13 , 7 , -1}, /* TIOC4B */
{P11_1 , 2 , -1}, /* TIOC4B */
{P3_10 , 6 , -1}, /* TIOC4C */
{P4_6 , 3 , -1}, /* TIOC4C */
{P7_14 , 7 , -1}, /* TIOC4C */
{P11_2 , 2 , -1}, /* TIOC4C */
{P3_11 , 6 , -1}, /* TIOC4D */
{P4_7 , 3 , -1}, /* TIOC4D */
{P7_15 , 7 , -1}, /* TIOC4D */
{P11_3 , 2 , -1}, /* TIOC4D */
{P5_7 , 1 , 1 }, /* TXOUT0M */
{P5_6 , 1 , 1 }, /* TXOUT0P */
{P5_5 , 1 , 1 }, /* TXOUT1M */
{P5_4 , 1 , 1 }, /* TXOUT1P */
{P5_3 , 1 , 1 }, /* TXOUT2M */
{P5_2 , 1 , 1 }, /* TXOUT2P */
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
{P2_11 , 4 , 0 }, /* SSITxD0 */
{P4_7 , 5 , 0 }, /* SSITxD0 */
{P7_4 , 6 , 0 }, /* SSITxD1 */
{P10_15 , 2 , 0 }, /* SSITxD1 */
{P4_15 , 6 , 0 }, /* SSITxD3 */
{P7_11 , 2 , 0 }, /* SSITxD3 */
{P2_7 , 4 , 0 }, /* SSITxD5 */
{P4_11 , 5 , 0 }, /* SSITxD5 */
{P8_10 , 8 , 0 }, /* SSITxD5 */
{P3_7 , 8 , 0 }, /* WDTOVF */
{NC , 0 , -1}
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_14, AN6, 1},
{P1_15, AN7, 1},
{NC , NC , 0}
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P1_1 , I2C_0, 1},
{P1_3 , I2C_1, 1},
{P1_7 , I2C_3, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P1_0 , I2C_0, 1},
{P1_2 , I2C_1, 1},
{P1_6 , I2C_3, 1},
{NC , NC , 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
{P2_14 , UART0, 6},
{P2_5 , UART1, 6},
{P4_12 , UART1, 7},
{P6_3 , UART2, 7},
{P4_14 , UART2, 7},
{P5_3 , UART3, 5},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P8_14 , UART4, 7},
{P8_13 , UART5, 5},
{P11_10, UART5, 3},
{P6_6 , UART5, 5},
{P5_6 , UART6, 5},
{P11_1 , UART6, 4},
{P7_4 , UART7, 4},
{NC , NC , 0}
};
const PinMap PinMap_UART_RX[] = {
{P2_15 , UART0, 6},
{P2_6 , UART1, 6},
{P4_13 , UART1, 7},
{P6_2 , UART2, 7},
{P4_15 , UART2, 7},
{P5_4 , UART3, 5},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P8_15 , UART4, 7},
{P8_11 , UART5, 5},
{P11_11, UART5, 3},
{P6_7 , UART5, 5},
{P5_7 , UART6, 5},
{P11_2 , UART6, 4},
{P7_5 , UART7, 4},
{NC , NC , 0}
};
const PinMap PinMap_UART_CTS[] = {
{P2_3 , UART1, 6},
{P11_7 , UART5, 3},
{P7_6 , UART7, 4},
{NC , NC , 0}
};
const PinMap PinMap_UART_RTS[] = {
{P2_7 , UART1, 6},
{P11_8 , UART5, 3},
{P7_7 , UART7, 4},
{NC , NC , 0}
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
{P10_12, SPI_0, 4},
{P4_4 , SPI_1, 2},
{P6_4 , SPI_1, 7},
{P11_12, SPI_1, 2},
{P8_3 , SPI_2, 3},
{P5_0 , SPI_3, 8},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MOSI[] = {
{P10_14, SPI_0, 4},
{P4_6 , SPI_1, 2},
{P6_6 , SPI_1, 7},
{P11_14, SPI_1, 2},
{P8_5 , SPI_2, 3},
{P5_2 , SPI_3, 8},
{NC , NC , 0}
};
const PinMap PinMap_SPI_MISO[] = {
{P10_15, SPI_0, 4},
{P4_7 , SPI_1, 2},
{P6_7 , SPI_1, 7},
{P11_15, SPI_1, 2},
{P8_6 , SPI_2, 3},
{P5_3 , SPI_3, 8},
{NC , NC , 0}
};
const PinMap PinMap_SPI_SSEL[] = {
{P10_13, SPI_0, 4},
{P4_5 , SPI_1, 2},
{P6_5 , SPI_1, 7},
{P11_13, SPI_1, 2},
{P8_4 , SPI_2, 3},
{P5_1 , SPI_3, 8},
{NC , NC , 0}
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
{P2_1 , PWM_TIOC2A, 6},
{P2_11 , PWM_TIOC1A, 5},
{P3_8 , PWM_TIOC4A, 6},
{P3_10 , PWM_TIOC4C, 6},
{P4_0 , PWM_TIOC0A, 2},
{P4_4 , PWM_TIOC4A, 3},
{P4_6 , PWM_TIOC4C, 3},
{P5_0 , PWM_TIOC0A, 6},
{P5_3 , PWM_TIOC3C, 6},
{P5_5 , PWM_TIOC0C, 6},
{P7_2 , PWM_TIOC0C, 7},
{P7_4 , PWM_TIOC1A, 7},
{P7_6 , PWM_TIOC2A, 7},
{P7_10 , PWM_TIOC3C, 7},
{P7_12 , PWM_TIOC4A, 7},
{P7_14 , PWM_TIOC4C, 7},
{P8_8 , PWM_TIOC1A, 5},
{P8_10 , PWM_TIOC3A, 4},
{P8_12 , PWM_TIOC3C, 4},
{P8_14 , PWM_TIOC2A, 4},
{P11_0 , PWM_TIOC4A, 2},
{P11_2 , PWM_TIOC4C, 2},
{P4_4 , PWM_PWM2E , 4},
{P3_2 , PWM_PWM2C , 7},
{P4_6 , PWM_PWM2G , 4},
{P4_7 , PWM_PWM2H , 4},
{P8_14 , PWM_PWM1G , 6},
{P8_15 , PWM_PWM1H , 6},
{P8_13 , PWM_PWM1F , 6},
{P8_11 , PWM_PWM1D , 6},
{P8_8 , PWM_PWM1A , 6},
{P10_0 , PWM_PWM2A , 3},
{P8_12 , PWM_PWM1E , 6},
{P8_9 , PWM_PWM1B , 6},
{P8_10 , PWM_PWM1C , 6},
{P4_5 , PWM_PWM2F , 4},
{NC , NC , 0}
};
/************CAN***************/
const PinMap PinMap_CAN_RD[] = {
{P7_8 , CAN_0, 4},
{P9_1 , CAN_0, 3},
{P1_4 , CAN_1, 3},
{P5_9 , CAN_1, 5},
{P7_11 , CAN_1, 4},
{P11_12, CAN_1, 1},
{P4_9 , CAN_2, 6},
{P6_4 , CAN_2, 3},
{P7_2 , CAN_2, 5},
{P2_12 , CAN_3, 5},
{P4_2 , CAN_3, 4},
{P1_5 , CAN_4, 3},
{P2_14 , CAN_4, 5},
{NC , NC , 0}
};
const PinMap PinMap_CAN_TD[] = {
{P7_9 , CAN_0, 4},
{P9_0 , CAN_0, 3},
{P5_10 , CAN_1, 5},
{P7_10 , CAN_1, 4},
{P11_13, CAN_1, 1},
{P4_8 , CAN_2, 6},
{P6_5 , CAN_2, 3},
{P7_3 , CAN_2, 5},
{P2_13 , CAN_3, 5},
{P4_3 , CAN_3, 4},
{P4_11 , CAN_4, 6},
{P8_10 , CAN_4, 5},
{NC , NC , 0}
};

9
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/PortNames.h
View File

@ -25,7 +25,14 @@ typedef enum {
Port1 = 1, Port1 = 1,
Port2 = 2, Port2 = 2,
Port3 = 3, Port3 = 3,
Port4 = 4 Port4 = 4,
Port5 = 5,
Port6 = 6,
Port7 = 7,
Port8 = 8,
Port9 = 9,
Port10 = 10,
Port11 = 11
} PortName; } PortName;
#ifdef __cplusplus #ifdef __cplusplus

57
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_api.c
View File

@ -1,57 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "gpio_api.h"
#include "pinmap.h"
#include "gpio_addrdefine.h"
uint32_t gpio_set(PinName pin) {
pin_function(pin, 0);
return (1 << PINNO(pin));
}
void gpio_init(gpio_t *obj, PinName pin) {
int group ;
obj->pin = pin;
if(pin == NC) return;
obj->mask = gpio_set(pin);
group = PINGROUP(pin);
if (group > 11) return;
obj->reg_set = (volatile uint32_t *) PSR(group);
obj->reg_in = (volatile uint32_t *) PPR(group);
obj->reg_dir = (volatile uint32_t *)PMSR(group);
obj->reg_buf = (volatile uint32_t *)PIBC(group);
}
void gpio_mode(gpio_t *obj, PinMode mode) {
/* Pull up and Pull down settings aren't supported because RZ/A1H doesn't have pull up/down for pins(signals). */
}
void gpio_dir(gpio_t *obj, PinDirection direction) {
switch (direction) {
case PIN_INPUT :
*obj->reg_dir = (obj->mask << 16) | obj->mask;
*obj->reg_buf |= obj->mask;
break;
case PIN_OUTPUT:
*obj->reg_dir = (obj->mask << 16) | 0;
*obj->reg_buf &= ~obj->mask;
break;
}
}

19
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/mbed_drv_cfg.h Normal file
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@ -0,0 +1,19 @@
#ifndef MBED_DRV_CFG_H
#define MBED_DRV_CFG_H
/* can_api.c */
#define CAN_TEST_GLOBAL_CH 1
/* gpio_api.c */
#define GPIO_GROUP_MAX 11
/* pwmout_api.c */
#define FUNC_MOTOR_CTL_PWM
#define FUMC_MTU2_PWM
/* rtc_api.c */
//#define USE_RTCX1_CLK
#define USE_EXTAL_CLK
//#define USE_RTCX3_CLK
#endif

84
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/objects.h
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#ifndef MBED_OBJECTS_H
#define MBED_OBJECTS_H
#include <stdint.h>
#include "cmsis.h"
#include "PortNames.h"
#include "PeripheralNames.h"
#include "PinNames.h"
#include "gpio_object.h"
#include "rspi_iodefine.h"
#ifdef __cplusplus
extern "C" {
#endif
struct i2c_s {
uint32_t i2c;
uint32_t dummy;
uint8_t pclk_bit;
uint8_t width_low;
uint8_t width_hi;
int bbsy_wait_cnt;
int last_stop_flag;
};
struct spi_s {
struct st_rspi *spi;
uint32_t bits;
int index;
};
struct gpio_irq_s {
uint32_t port;
uint32_t pin;
uint32_t ch;
uint8_t int_enable;
};
struct port_s {
__IO uint32_t *reg_dir;
__IO uint32_t *reg_out;
__I uint32_t *reg_in;
PortName port;
uint32_t mask;
};
struct serial_s {
struct st_scif *uart;
int index;
};
struct pwmout_s {
uint32_t ch;
PWMName pwm;
};
struct analogin_s {
ADCName adc;
};
struct can_s {
uint32_t ch;
};
#ifdef __cplusplus
}
#endif
#endif

172
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pinmap.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_addrdefine.h"
PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
typedef struct {
PinName pin;
int function;
int pm;
} PinFunc;
static const PinFunc PIPC_0_tbl[] = {
// pin func pm
{P4_0 , 2 , -1}, /* TIOC0A */
{P5_0 , 6 , -1}, /* TIOC0A */
{P7_0 , 7 , -1}, /* TIOC0A */
{P10_4 , 2 , -1}, /* TIOC0A */
{P4_1 , 2 , -1}, /* TIOC0B */
{P5_1 , 6 , -1}, /* TIOC0B */
{P7_1 , 7 , -1}, /* TIOC0B */
{P10_5 , 2 , -1}, /* TIOC0B */
{P4_2 , 2 , -1}, /* TIOC0C */
{P5_5 , 6 , -1}, /* TIOC0C */
{P7_2 , 7 , -1}, /* TIOC0C */
{P10_6 , 2 , -1}, /* TIOC0C */
{P4_3 , 2 , -1}, /* TIOC0D */
{P5_7 , 6 , -1}, /* TIOC0D */
{P7_3 , 7 , -1}, /* TIOC0D */
{P10_7 , 2 , -1}, /* TIOC0D */
{P2_11 , 5 , -1}, /* TIOC1A */
{P6_0 , 5 , -1}, /* TIOC1A */
{P7_4 , 7 , -1}, /* TIOC1A */
{P8_8 , 5 , -1}, /* TIOC1A */
{P9_7 , 4 , -1}, /* TIOC1A */
{P10_8 , 2 , -1}, /* TIOC1A */
{P2_12 , 8 , -1}, /* TIOC1B */
{P5_2 , 6 , -1}, /* TIOC1B */
{P6_1 , 5 , -1}, /* TIOC1B */
{P7_5 , 7 , -1}, /* TIOC1B */
{P8_9 , 5 , -1}, /* TIOC1B */
{P10_9 , 2 , -1}, /* TIOC1B */
{P2_1 , 6 , -1}, /* TIOC2A */
{P6_2 , 6 , -1}, /* TIOC2A */
{P7_6 , 7 , -1}, /* TIOC2A */
{P8_14 , 4 , -1}, /* TIOC2A */
{P10_10 , 2 , -1}, /* TIOC2A */
{P2_2 , 6 , -1}, /* TIOC2B */
{P6_3 , 6 , -1}, /* TIOC2B */
{P7_7 , 7 , -1}, /* TIOC2B */
{P8_15 , 4 , -1}, /* TIOC2B */
{P10_11 , 2 , -1}, /* TIOC2B */
{P10_11 , 2 , -1}, /* TIOC2B */
{P3_4 , 6 , -1}, /* TIOC3A */
{P7_8 , 7 , -1}, /* TIOC3A */
{P8_10 , 4 , -1}, /* TIOC3A */
{P3_5 , 6 , -1}, /* TIOC3B */
{P7_9 , 7 , -1}, /* TIOC3B */
{P8_11 , 4 , -1}, /* TIOC3B */
{P3_6 , 6 , -1}, /* TIOC3C */
{P5_3 , 6 , -1}, /* TIOC3C */
{P7_10 , 7 , -1}, /* TIOC3C */
{P8_12 , 4 , -1}, /* TIOC3C */
{P3_7 , 6 , -1}, /* TIOC3D */
{P5_4 , 6 , -1}, /* TIOC3D */
{P7_11 , 7 , -1}, /* TIOC3D */
{P8_13 , 4 , -1}, /* TIOC3D */
{P3_8 , 6 , -1}, /* TIOC4A */
{P4_4 , 3 , -1}, /* TIOC4A */
{P7_12 , 7 , -1}, /* TIOC4A */
{P11_0 , 2 , -1}, /* TIOC4A */
{P3_9 , 6 , -1}, /* TIOC4B */
{P4_5 , 3 , -1}, /* TIOC4B */
{P7_13 , 7 , -1}, /* TIOC4B */
{P11_1 , 2 , -1}, /* TIOC4B */
{P3_10 , 6 , -1}, /* TIOC4C */
{P4_6 , 3 , -1}, /* TIOC4C */
{P7_14 , 7 , -1}, /* TIOC4C */
{P11_2 , 2 , -1}, /* TIOC4C */
{P3_11 , 6 , -1}, /* TIOC4D */
{P4_7 , 3 , -1}, /* TIOC4D */
{P7_15 , 7 , -1}, /* TIOC4D */
{P11_3 , 2 , -1}, /* TIOC4D */
{P5_7 , 1 , 1 }, /* TXOUT0M */
{P5_6 , 1 , 1 }, /* TXOUT0P */
{P5_5 , 1 , 1 }, /* TXOUT1M */
{P5_4 , 1 , 1 }, /* TXOUT1P */
{P5_3 , 1 , 1 }, /* TXOUT2M */
{P5_2 , 1 , 1 }, /* TXOUT2P */
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
{P2_11 , 4 , 0 }, /* SSITxD0 */
{P4_7 , 5 , 0 }, /* SSITxD0 */
{P7_4 , 6 , 0 }, /* SSITxD1 */
{P10_15 , 2 , 0 }, /* SSITxD1 */
{P4_15 , 6 , 0 }, /* SSITxD3 */
{P7_11 , 2 , 0 }, /* SSITxD3 */
{P2_7 , 4 , 0 }, /* SSITxD5 */
{P4_11 , 5 , 0 }, /* SSITxD5 */
{P8_10 , 8 , 0 }, /* SSITxD5 */
{P3_7 , 8 , 0 }, /* WDTOVF */
{NC , 0 , -1}
};
void pin_function(PinName pin, int function) {
if (pin == (PinName)NC) return;
int n = pin >> 4;
int bitmask = 1<<(pin & 0xf);
const PinFunc * Pipc_0_func = PIPC_0_tbl;
int pipc_data = 1;
if (gpio_multi_guard != pin) {
if (function == 0) {
// means GPIO mode
*PMC(n) &= ~bitmask;
} else {
// alt-function mode
--function;
if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;}
if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;}
if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;}
while (Pipc_0_func->pin != NC) {
if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
pipc_data = 0;
if (Pipc_0_func->pm == 0) {
*PMSR(n) = (bitmask << 16) | 0;
} else if (Pipc_0_func->pm == 1) {
*PMSR(n) = (bitmask << 16) | bitmask;
} else {
// Do Nothing
}
break;
}
Pipc_0_func++;
}
if (pipc_data == 1) {
*PIPC(n) |= bitmask;
} else {
*PIPC(n) &= ~bitmask;
}
if (P1_0 <= pin && pin <= P1_7 && function == 0) {
*PBDC(n) |= bitmask;
}
*PMC(n) |= bitmask;
}
} else {
gpio_multi_guard = (PinName)NC;
}
}
void pin_mode(PinName pin, PinMode mode) {
// if (pin == (PinName)NC) { return; }
}

65
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/port_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "port_api.h"
#include "pinmap.h"
#include "gpio_api.h"
PinName port_pin(PortName port, int pin_n) {
return (PinName)(0);
}
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
obj->port = port;
obj->mask = mask;
// Do not use masking, because it prevents the use of the unmasked pins
// port_reg->FIOMASK = ~mask;
uint32_t i;
// The function is set per pin: reuse gpio logic
for (i=0; i<32; i++) {
if (obj->mask & (1<<i)) {
gpio_set(port_pin(obj->port, i));
}
}
port_dir(obj, dir);
}
void port_mode(port_t *obj, PinMode mode) {
uint32_t i;
// The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) {
if (obj->mask & (1<<i)) {
pin_mode(port_pin(obj->port, i), mode);
}
}
}
void port_dir(port_t *obj, PinDirection dir) {
switch (dir) {
case PIN_INPUT : *obj->reg_dir &= ~obj->mask; break;
case PIN_OUTPUT: *obj->reg_dir |= obj->mask; break;
}
}
void port_write(port_t *obj, int value) {
*obj->reg_out = (*obj->reg_in & ~obj->mask) | (value & obj->mask);
}
int port_read(port_t *obj) {
return (*obj->reg_in & obj->mask);
}

381
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/rtc_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "device.h"
#if DEVICE_RTC
#include "rtc_api.h"
#include "rtc_iodefine.h"
#include "mbed_mktime.h"
#define RCR1_VAL_ON (0x08u) // AIE = 1
#define RCR1_VAL_OFF (0x00u)
#define RCR2_VAL_ALLSTOP (0x00u)
#define RCR2_VAL_START (0x01u) // START = 1
#define RCR2_VAL_RESET (0x02u) // RESET = 1
#define RCR3_VAL (0x00u)
#define RCR5_VAL_EXTAL (0x01u) // RCKSEL = connect EXTAL
#define RCR5_VAL_RTCX1 (0x00u) // RCKSEL = disconnect EXTAL
#define RFRH_VAL_13333 (0x8003u) // 13.3333MHz (= 64Hz * 0x32DCD)
#define RFRL_VAL_13333 (0x2DCDu) //
#define RFRH_VAL_MAX (0x0007u) // MAX value (= 128Hz * 0x7FFFF)
#define RFRL_VAL_MAX (0xFFFFu) //
#define MASK_00_03_POS (0x000Fu)
#define MASK_04_07_POS (0x00F0u)
#define MASK_08_11_POS (0x0F00u)
#define MASK_12_15_POS (0xF000u)
#define MASK_16_20_POS (0x000F0000u)
#define SHIFT_1_HBYTE (4u)
#define SHIFT_2_HBYTE (8u)
#define SHIFT_3_HBYTE (12u)
#define SHIFT_1BYTE (8u)
#define SHIFT_2BYTE (16u)
#define TIME_ERROR_VAL (0u)
static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val);
static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val);
static uint8_t rtc_hex8_to_dec(uint8_t hex_val);
static uint16_t rtc_hex16_to_dec(uint16_t hex_val);
/*
* Setup the RTC based on a time structure.
* The rtc_init function should be executed first.
* [in]
* None.
* [out]
* None.
*/
void rtc_init(void) {
volatile uint8_t dummy_read;
// Set control register
RTC.RCR2 = RCR2_VAL_ALLSTOP;
RTC.RCR1 = RCR1_VAL_ON;
RTC.RCR3 = RCR3_VAL;
RTC.RCR5 = RCR5_VAL_EXTAL;
RTC.RFRH = RFRH_VAL_13333;
RTC.RFRL = RFRL_VAL_13333;
// Dummy read
dummy_read = RTC.RCR2;
dummy_read = RTC.RCR2;
RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
// Dummy read
dummy_read = RTC.RCR2;
dummy_read = RTC.RCR2;
// Set timer and alarm. Default value :01-01-1970 00:00:00
RTC.RSECCNT = 0;
RTC.RMINCNT = 0;
RTC.RHRCNT = 0;
RTC.RWKCNT = 0;
RTC.RDAYCNT = 1;
RTC.RMONCNT = 1;
RTC.RYRCNT = 0x1970;
RTC.RSECAR = 0;
RTC.RMINAR = 0;
RTC.RHRAR = 0;
RTC.RWKAR = 0;
RTC.RDAYAR = 1;
RTC.RMONAR = 1;
RTC.RYRAR = 0x1970;
// Dummy read
dummy_read = RTC.RYRCNT;
dummy_read = RTC.RYRCNT;
}
/*
* Release the RTC based on a time structure.
* [in]
* None.
* [out]
* None.
*/
void rtc_free(void) {
volatile uint8_t dummy_read;
// Set control register
RTC.RCR2 = RCR2_VAL_ALLSTOP;
RTC.RCR1 = RCR1_VAL_OFF;
RTC.RCR3 = RCR3_VAL;
RTC.RCR5 = RCR5_VAL_RTCX1;
RTC.RFRH = RFRH_VAL_MAX;
RTC.RFRL = RFRL_VAL_MAX;
// Dummy read
dummy_read = RTC.RCR2;
dummy_read = RTC.RCR2;
RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
// Dummy read
dummy_read = RTC.RCR2;
dummy_read = RTC.RCR2;
// Set timer and alarm. Default value :01-01-1970 00:00:00
RTC.RSECCNT = 0;
RTC.RMINCNT = 0;
RTC.RHRCNT = 0;
RTC.RWKCNT = 0;
RTC.RDAYCNT = 1;
RTC.RMONCNT = 1;
RTC.RYRCNT = 0x1970;
RTC.RSECAR = 0;
RTC.RMINAR = 0;
RTC.RHRAR = 0;
RTC.RWKAR = 0;
RTC.RDAYAR = 1;
RTC.RMONAR = 1;
RTC.RYRAR = 0x1970;
// Dummy read
dummy_read = RTC.RYRCNT;
dummy_read = RTC.RYRCNT;
}
/*
* Check the RTC has been enabled.
* Clock Control Register RTC.RCR1(bit3): 0 = Disabled, 1 = Enabled.
* [in]
* None.
* [out]
* 0:Disabled, 1:Enabled.
*/
int rtc_isenabled(void) {
int ret_val = 0;
if ((RTC.RCR1 & RCR1_VAL_ON) != 0) { // RTC ON ?
ret_val = 1;
}
return ret_val;
}
/*
* RTC read function.
* [in]
* None.
* [out]
* UNIX timestamp value.
*/
time_t rtc_read(void) {
struct tm timeinfo;
int err = 0;
uint8_t tmp_regdata;
time_t t;
if (rtc_isenabled() != 0) {
RTC.RCR1 &= ~0x10u; // CIE = 0
do {
// before reading process
tmp_regdata = RTC.RCR1;
tmp_regdata &= ~0x80u; // CF = 0
tmp_regdata |= 0x01u; // AF = 1
RTC.RCR1 = tmp_regdata;
// Read RTC register
err = rtc_dec8_to_hex(RTC.RSECCNT , 0 , &timeinfo.tm_sec);
err += rtc_dec8_to_hex(RTC.RMINCNT , 0 , &timeinfo.tm_min);
err += rtc_dec8_to_hex(RTC.RHRCNT , 0 , &timeinfo.tm_hour);
err += rtc_dec8_to_hex(RTC.RDAYCNT , 0 , &timeinfo.tm_mday);
err += rtc_dec8_to_hex(RTC.RMONCNT , 1 , &timeinfo.tm_mon);
err += rtc_dec16_to_hex(RTC.RYRCNT , 1900 , &timeinfo.tm_year);
} while ((RTC.RCR1 & 0x80u) != 0);
} else {
err = 1;
}
if (err == 0) {
// Convert to timestamp
if (_rtc_maketime(&timeinfo, &t, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
return TIME_ERROR_VAL;
}
} else {
// Error
t = TIME_ERROR_VAL;
}
return t;
}
/*
* Dec(8bit) to Hex function for RTC.
* [in]
* dec_val:Decimal value (from 0x00 to 0x99).
* offset:Subtract offset from dec_val.
* hex_val:Pointer of output hexadecimal value.
* [out]
* 0:Success
* 1:Error
*/
static int rtc_dec8_to_hex(uint8_t dec_val, uint8_t offset, int *hex_val) {
int err = 0;
uint8_t ret_val;
if (hex_val != NULL) {
if (((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
((dec_val & MASK_00_03_POS) >= 0x0A)) {
err = 1;
} else {
ret_val = ((dec_val & MASK_04_07_POS) >> SHIFT_1_HBYTE) * 10 +
(dec_val & MASK_00_03_POS);
if (ret_val < offset) {
err = 1;
} else {
*hex_val = ret_val - offset;
}
}
} else {
err = 1;
}
return err;
}
/*
* Dec(16bit) to Hex function for RTC
* [in]
* dec_val:Decimal value (from 0x0000 to 0x9999).
* offset:Subtract offset from dec_val.
* hex_val:Pointer of output hexadecimal value.
* [out]
* 0:Success
* 1:Error
*/
static int rtc_dec16_to_hex(uint16_t dec_val, uint16_t offset, int *hex_val) {
int err = 0;
uint16_t ret_val;
if (hex_val != NULL) {
if (((dec_val & MASK_12_15_POS) >= (0x0A << SHIFT_3_HBYTE)) ||
((dec_val & MASK_08_11_POS) >= (0x0A << SHIFT_2_HBYTE)) ||
((dec_val & MASK_04_07_POS) >= (0x0A << SHIFT_1_HBYTE)) ||
((dec_val & MASK_00_03_POS) >= 0x0A)) {
err = 1;
*hex_val = 0;
} else {
ret_val = (((dec_val & MASK_12_15_POS)) >> SHIFT_3_HBYTE) * 1000 +
(((dec_val & MASK_08_11_POS)) >> SHIFT_2_HBYTE) * 100 +
(((dec_val & MASK_04_07_POS)) >> SHIFT_1_HBYTE) * 10 +
(dec_val & MASK_00_03_POS);
if (ret_val < offset) {
err = 1;
} else {
*hex_val = ret_val - offset;
}
}
} else {
err = 1;
}
return err;
}
/*
* RTC write function
* [in]
* t:UNIX timestamp value
* [out]
* None.
*/
void rtc_write(time_t t) {
struct tm timeinfo;
if (_rtc_localtime(t, &timeinfo, RTC_FULL_LEAP_YEAR_SUPPORT) == false) {
return;
}
volatile uint16_t dummy_read;
if (rtc_isenabled() != 0) {
RTC.RCR2 = RCR2_VAL_ALLSTOP;
dummy_read = (uint16_t)RTC.RCR2;
dummy_read = (uint16_t)RTC.RCR2;
RTC.RCR2 = RCR2_VAL_RESET; // RESET = 1
dummy_read = (uint16_t)RTC.RCR2;
dummy_read = (uint16_t)RTC.RCR2;
RTC.RSECCNT = rtc_hex8_to_dec(timeinfo.tm_sec);
RTC.RMINCNT = rtc_hex8_to_dec(timeinfo.tm_min);
RTC.RHRCNT = rtc_hex8_to_dec(timeinfo.tm_hour);
RTC.RDAYCNT = rtc_hex8_to_dec(timeinfo.tm_mday);
RTC.RMONCNT = rtc_hex8_to_dec(timeinfo.tm_mon + 1);
RTC.RYRCNT = rtc_hex16_to_dec(timeinfo.tm_year + 1900);
dummy_read = (uint16_t)RTC.RYRCNT;
dummy_read = (uint16_t)RTC.RYRCNT;
RTC.RCR2 = RCR2_VAL_START; // START = 1
dummy_read = (uint16_t)RTC.RCR2;
dummy_read = (uint16_t)RTC.RCR2;
}
}
/*
* HEX to Dec(8bit) function for RTC.
* [in]
* hex_val:Hexadecimal value.
* [out]
* decimal value:From 0x00 to 0x99.
*/
static uint8_t rtc_hex8_to_dec(uint8_t hex_val) {
uint32_t calc_data;
calc_data = hex_val / 10 * 0x10;
calc_data += hex_val % 10;
if (calc_data > 0x99) {
calc_data = 0;
}
return (uint8_t)calc_data;
}
/*
* HEX to Dec(16bit) function for RTC.
* [in]
* hex_val:Hexadecimal value.
* [out]
* decimal value:From 0x0000 to 0x9999.
*/
static uint16_t rtc_hex16_to_dec(uint16_t hex_val) {
uint32_t calc_data;
calc_data = hex_val / 1000 * 0x1000;
calc_data += ((hex_val / 100) % 10) * 0x100;
calc_data += ((hex_val / 10) % 10) * 0x10;
calc_data += hex_val % 10;
if (calc_data > 0x9999) {
calc_data = 0;
}
return (uint16_t)calc_data;
}
#endif /* DEVICE_RTC */

129
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralNames.h
View File

@ -34,105 +34,31 @@ typedef enum {
UART7, UART7,
} UARTName; } UARTName;
// PWMType & 1 == 1 then have to use PWDTR[12] == 1
typedef enum { typedef enum {
PWM1A = 0, PWM_PWM1A = 0,
PWM1B, PWM_PWM1B,
PWM1C, PWM_PWM1C,
PWM1D, PWM_PWM1D,
PWM1E, PWM_PWM1E,
PWM1F, PWM_PWM1F,
PWM1G, PWM_PWM1G,
PWM1H, PWM_PWM1H,
PWM2A = 0x10, PWM_PWM2A,
PWM2B, PWM_PWM2B,
PWM2C, PWM_PWM2C,
PWM2D, PWM_PWM2D,
PWM2E, PWM_PWM2E,
PWM2F, PWM_PWM2F,
PWM2G, PWM_PWM2G,
PWM2H, PWM_PWM2H,
} PWMType; PWM_TIOC0A = 0x20,
PWM_TIOC0C,
typedef enum { PWM_TIOC1A,
TIOC0A = 0, PWM_TIOC2A,
TIOC0B, PWM_TIOC3A,
TIOC0C, PWM_TIOC3C,
TIOC0D, PWM_TIOC4A,
TIOC1A = 0x10, PWM_TIOC4C,
TIOC1B,
TIOC2A = 0x20,
TIOC2B,
TIOC3A = 0x30,
TIOC3B,
TIOC3C,
TIOC3D,
TIOC4A = 0x40,
TIOC4B,
TIOC4C,
TIOC4D,
} MTU2_PWMType;
typedef enum {
PWM0_PIN = 0,
PWM1_PIN,
PWM2_PIN,
PWM3_PIN,
PWM4_PIN,
PWM5_PIN,
PWM6_PIN,
PWM7_PIN,
PWM8_PIN,
PWM9_PIN,
PWM10_PIN,
PWM11_PIN,
PWM12_PIN,
#ifdef MAX_PERI
PWM13_PIN,
PWM14_PIN,
PWM15_PIN,
MTU2_PWM0_PIN = 0x20,
MTU2_PWM1_PIN,
MTU2_PWM2_PIN,
MTU2_PWM3_PIN,
MTU2_PWM4_PIN,
MTU2_PWM5_PIN,
MTU2_PWM6_PIN,
MTU2_PWM7_PIN,
MTU2_PWM8_PIN,
MTU2_PWM9_PIN,
MTU2_PWM10_PIN,
MTU2_PWM11_PIN,
MTU2_PWM12_PIN,
MTU2_PWM13_PIN,
MTU2_PWM14_PIN,
MTU2_PWM15_PIN,
MTU2_PWM16_PIN,
MTU2_PWM17_PIN,
MTU2_PWM18_PIN,
MTU2_PWM19_PIN,
MTU2_PWM20_PIN,
MTU2_PWM21_PIN,
MTU2_PWM22_PIN,
MTU2_PWM23_PIN,
MTU2_PWM23_PIN,
MTU2_PWM24_PIN,
MTU2_PWM25_PIN,
MTU2_PWM26_PIN,
#else
MTU2_PWM0_PIN = 0x20,
MTU2_PWM1_PIN,
MTU2_PWM2_PIN,
MTU2_PWM3_PIN,
MTU2_PWM4_PIN,
MTU2_PWM5_PIN,
MTU2_PWM6_PIN,
MTU2_PWM7_PIN,
MTU2_PWM8_PIN,
MTU2_PWM9_PIN,
MTU2_PWM10_PIN,
MTU2_PWM11_PIN,
#endif
} PWMName; } PWMName;
typedef enum { typedef enum {
@ -147,7 +73,8 @@ typedef enum {
} ADCName; } ADCName;
typedef enum { typedef enum {
SPI_1 = 1, SPI_0 = 0,
SPI_1,
SPI_2, SPI_2,
SPI_3, SPI_3,
SPI_4, SPI_4,
@ -157,7 +84,7 @@ typedef enum {
I2C_0 = 0, I2C_0 = 0,
I2C_1, I2C_1,
I2C_2, I2C_2,
I2C_3 I2C_3,
} I2CName; } I2CName;
typedef enum { typedef enum {
@ -165,7 +92,7 @@ typedef enum {
CAN_1, CAN_1,
CAN_2, CAN_2,
CAN_3, CAN_3,
CAN_4 CAN_4,
} CANName; } CANName;

540
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/PeripheralPins.c Normal file
View File

@ -0,0 +1,540 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
/************IRQ***************/
enum {
IRQ0,IRQ1,
IRQ2,IRQ3,
IRQ4,IRQ5,
IRQ6,IRQ7,
} IRQNo;
const PinMap PinMap_IRQ[] = {
#ifdef MAX_PERI
{P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4},
{P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8},
{P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4},
{P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4},
{P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4},
{P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4},
{P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
{P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8},
{NC, NC, 0}
#else
{P9_1, IRQ0, 4},
{P7_8, IRQ1, 8},
{P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4},
{P1_3, IRQ3, 4}, {P1_9, IRQ3, 3},
{P1_4, IRQ4, 4}, {P1_10, IRQ4, 3},
{P1_5, IRQ5, 4}, {P1_11, IRQ5, 3},
{P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
{NC, NC, 0}
#endif
};
/************PINMAP***************/
const PinFunc PIPC_0_tbl[] = {
#ifdef MAX_PERI
// pin func pm
{P4_0 , 2 , -1}, /* TIOC0A */
{P5_0 , 6 , -1}, /* TIOC0A */
{P7_0 , 7 , -1}, /* TIOC0A */
{P4_1 , 2 , -1}, /* TIOC0B */
{P5_1 , 6 , -1}, /* TIOC0B */
{P7_1 , 7 , -1}, /* TIOC0B */
{P4_2 , 2 , -1}, /* TIOC0C */
{P5_5 , 6 , -1}, /* TIOC0C */
{P7_2 , 7 , -1}, /* TIOC0C */
{P4_3 , 2 , -1}, /* TIOC0D */
{P5_7 , 6 , -1}, /* TIOC0D */
{P7_3 , 7 , -1}, /* TIOC0D */
{P2_11 , 5 , -1}, /* TIOC1A */
{P6_0 , 5 , -1}, /* TIOC1A */
{P7_4 , 7 , -1}, /* TIOC1A */
{P8_8 , 5 , -1}, /* TIOC1A */
{P9_7 , 4 , -1}, /* TIOC1A */
{P2_12 , 8 , -1}, /* TIOC1B */
{P5_2 , 6 , -1}, /* TIOC1B */
{P6_1 , 5 , -1}, /* TIOC1B */
{P7_5 , 7 , -1}, /* TIOC1B */
{P8_9 , 5 , -1}, /* TIOC1B */
{P2_1 , 6 , -1}, /* TIOC2A */
{P6_2 , 6 , -1}, /* TIOC2A */
{P7_6 , 7 , -1}, /* TIOC2A */
{P8_14 , 4 , -1}, /* TIOC2A */
{P2_2 , 6 , -1}, /* TIOC2B */
{P6_3 , 6 , -1}, /* TIOC2B */
{P7_7 , 7 , -1}, /* TIOC2B */
{P8_15 , 4 , -1}, /* TIOC2B */
{P3_4 , 6 , -1}, /* TIOC3A */
{P7_8 , 7 , -1}, /* TIOC3A */
{P8_10 , 4 , -1}, /* TIOC3A */
{P3_5 , 6 , -1}, /* TIOC3B */
{P7_9 , 7 , -1}, /* TIOC3B */
{P8_11 , 4 , -1}, /* TIOC3B */
{P3_6 , 6 , -1}, /* TIOC3C */
{P5_3 , 6 , -1}, /* TIOC3C */
{P7_10 , 7 , -1}, /* TIOC3C */
{P8_12 , 4 , -1}, /* TIOC3C */
{P3_7 , 6 , -1}, /* TIOC3D */
{P5_4 , 6 , -1}, /* TIOC3D */
{P7_11 , 7 , -1}, /* TIOC3D */
{P8_13 , 4 , -1}, /* TIOC3D */
{P3_8 , 6 , -1}, /* TIOC4A */
{P4_4 , 3 , -1}, /* TIOC4A */
{P7_12 , 7 , -1}, /* TIOC4A */
{P3_9 , 6 , -1}, /* TIOC4B */
{P4_5 , 3 , -1}, /* TIOC4B */
{P7_13 , 7 , -1}, /* TIOC4B */
{P3_10 , 6 , -1}, /* TIOC4C */
{P4_6 , 3 , -1}, /* TIOC4C */
{P7_14 , 7 , -1}, /* TIOC4C */
{P3_11 , 6 , -1}, /* TIOC4D */
{P4_7 , 3 , -1}, /* TIOC4D */
{P7_15 , 7 , -1}, /* TIOC4D */
{P5_7 , 1 , 1 }, /* TXOUT0M */
{P5_6 , 1 , 1 }, /* TXOUT0P */
{P5_5 , 1 , 1 }, /* TXOUT1M */
{P5_4 , 1 , 1 }, /* TXOUT1P */
{P5_3 , 1 , 1 }, /* TXOUT2M */
{P5_2 , 1 , 1 }, /* TXOUT2P */
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
{P2_11 , 4 , 0 }, /* SSITxD0 */
{P4_7 , 5 , 0 }, /* SSITxD0 */
{P7_4 , 6 , 0 }, /* SSITxD1 */
{P4_15 , 6 , 0 }, /* SSITxD3 */
{P7_11 , 2 , 0 }, /* SSITxD3 */
{P2_7 , 4 , 0 }, /* SSITxD5 */
{P4_11 , 5 , 0 }, /* SSITxD5 */
{P8_10 , 8 , 0 }, /* SSITxD5 */
{P3_7 , 8 , 0 }, /* WDTOVF */
{NC , 0 , -1}
#else
// pin func pm
{P4_0 , 2 , -1}, // TIOC0A
{P5_0 , 6 , -1}, // TIOC0A
{P4_2 , 2 , -1}, // TIOC0C
{P5_5 , 6 , -1}, // TIOC0C
//
{P8_14 , 4 , -1}, // TIOC2A
//
{P8_10 , 4 , -1}, // TIOC3A
{P5_3 , 6 , -1}, // TIOC3C
{P8_12 , 4 , -1}, // TIOC3C
//
{P3_8 , 6 , -1}, // TIOC4A
{P4_4 , 3 , -1}, // TIOC4A
{P3_10 , 6 , -1}, // TIOC4C
{P4_6 , 3 , -1}, // TIOC4C
//
{P5_7 , 1 , 1 }, // TXOUT0M
{P5_6 , 1 , 1 }, // TXOUT0P
{P5_5 , 1 , 1 }, // TXOUT1M
{P5_4 , 1 , 1 }, // TXOUT1P
{P5_3 , 1 , 1 }, // TXOUT2M
{P5_2 , 1 , 1 }, // TXOUT2P
{P5_1 , 1 , 1 }, // TXCLKOUTM
{P5_0 , 1 , 1 }, // TXCLKOUTP
{P4_7 , 5 , 0 }, // SSITxD0
{P8_10 , 8 , 0 }, // SSITxD5
{P3_7 , 8 , 0 }, // WDTOVF
{NC , 0 , -1}
#endif
};
/************ADC***************/
const PinMap PinMap_ADC[] = {
#ifdef MAX_PERI
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_14, AN6, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
#else
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
#endif
};
/************I2C***************/
const PinMap PinMap_I2C_SDA[] = {
{P1_1 , I2C_0, 1},
{P1_3 , I2C_1, 1},
{P1_5 , I2C_2, 1},
{P1_7 , I2C_3, 1},
{NC , NC , 0}
};
const PinMap PinMap_I2C_SCL[] = {
{P1_0 , I2C_0, 1},
{P1_2 , I2C_1, 1},
{P1_4 , I2C_2, 1},
{P1_6 , I2C_3, 1},
{NC , NC, 0}
};
/************UART***************/
const PinMap PinMap_UART_TX[] = {
#ifdef MAX_PERI
{P2_14 , UART0, 6},
{P4_9 , UART0, 7},
{P6_9 , UART0, 5},
{P2_5 , UART1, 6},
{P4_12 , UART1, 7},
{P6_12 , UART1, 5},
{P9_3 , UART1, 4},
{P3_0 , UART2, 6},
{P3_1 , UART2, 4},
{P4_2 , UART2, 5},
{P4_14 , UART2, 7},
{P6_3 , UART2, 7},
{P8_6 , UART2, 7},
{P3_5 , UART3, 7},
{P5_3 , UART3, 5},
{P6_1 , UART3, 7},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P7_1 , UART4, 4},
{P8_14 , UART4, 7},
{P6_6 , UART5, 5},
{P8_1 , UART5, 4},
{P8_13 , UART5, 5},
{P5_6 , UART6, 5},
{P6_14 , UART6, 4},
{P7_4 , UART7, 4},
{NC , NC , 0}
#else
{P3_0 , UART2, 6},
{P3_1 , UART2, 4},
{P4_2 , UART2, 5},
{P5_3 , UART3, 5},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P8_14 , UART4, 7},
{P8_13 , UART5, 5},
{P5_6 , UART6, 5},
{NC , NC , 0}
#endif
};
const PinMap PinMap_UART_RX[] = {
#ifdef MAX_PERI
{P2_15 , UART0, 6},
{P4_10 , UART0, 7},
{P6_10 , UART0, 5},
{P2_6 , UART1, 6},
{P4_13 , UART1, 7},
{P6_13 , UART1, 5},
{P9_4 , UART1, 4},
{P3_2 , UART2, 4},
{P4_3 , UART2, 5},
{P4_15 , UART2, 7},
{P6_2 , UART2, 7},
{P8_4 , UART2, 7},
{P3_6 , UART3, 7},
{P5_4 , UART3, 5},
{P6_0 , UART3, 7},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P7_2 , UART4, 4},
{P8_15 , UART4, 7},
{P6_7 , UART5, 5},
{P8_2 , UART5, 4},
{P8_11 , UART5, 5},
{P5_7 , UART6, 5},
{P6_15 , UART6, 4},
{P7_5 , UART7, 4},
{NC , NC , 0}
#else
{P3_2 , UART2, 4},
{P4_3 , UART2, 5},
{P5_4 , UART3, 5},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P8_15 , UART4, 7},
{P8_11 , UART5, 5},
{P5_7 , UART6, 5},
{NC , NC , 0}
#endif
};
const PinMap PinMap_UART_CTS[] = {
#ifdef MAX_PERI
{P2_3 , UART1, 6},
{P9_5 , UART1, 4},
{P6_3 , UART5, 5},
{P7_15 , UART5, 4},
{P7_6 , UART7, 4},
{NC , NC , 0}
#else
{NC , NC , 0}
#endif
};
const PinMap PinMap_UART_RTS[] = {
#ifdef MAX_PERI
{P2_7 , UART1, 6},
{P9_6 , UART1, 4},
{P6_4 , UART5, 5},
{P8_3 , UART5, 4},
{P7_7 , UART7, 4},
{NC , NC , 0}
#else
{NC , NC , 0}
#endif
};
/************SPI***************/
const PinMap PinMap_SPI_SCLK[] = {
#ifdef MAX_PERI
{P2_12 , SPI_0, 2},
{P7_15 , SPI_0, 2},
{P4_4 , SPI_1, 2},
{P6_4 , SPI_1, 7},
{P8_3 , SPI_2, 3},
{P8_14 , SPI_2, 5},
{P3_0 , SPI_3, 8},
{P5_0 , SPI_3, 8},
{P2_8 , SPI_4, 8},
{P4_0 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_4 , SPI_1, 2},
{P8_14 , SPI_2, 5},
{P5_0 , SPI_3, 8},
{P4_0 , SPI_4, 7},
{NC , NC , 0}
#endif
};
const PinMap PinMap_SPI_MOSI[] = {
#ifdef MAX_PERI
{P2_14 , SPI_0, 2},
{P8_1 , SPI_0, 2},
{P4_6 , SPI_1, 2},
{P6_6 , SPI_1, 7},
{P8_5 , SPI_2, 3},
{P9_0 , SPI_2, 5},
{P3_2 , SPI_3, 8},
{P5_2 , SPI_3, 8},
{P2_10 , SPI_4, 8},
{P4_2 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_6 , SPI_1, 2},
{P9_0 , SPI_2, 5},
{P5_2 , SPI_3, 8},
{P4_2 , SPI_4, 7},
{NC , NC , 0}
#endif
};
const PinMap PinMap_SPI_MISO[] = {
#ifdef MAX_PERI
{P2_15 , SPI_0, 2},
{P8_2 , SPI_0, 2},
{P4_7 , SPI_1, 2},
{P6_7 , SPI_1, 7},
{P8_6 , SPI_2, 3},
{P9_1 , SPI_2, 5},
{P3_3 , SPI_3, 8},
{P5_3 , SPI_3, 8},
{P2_11 , SPI_4, 8},
{P4_3 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_7 , SPI_1, 2},
{P9_1 , SPI_2, 5},
{P5_3 , SPI_3, 8},
{P4_3 , SPI_4, 7},
{NC , NC , 0}
#endif
};
const PinMap PinMap_SPI_SSEL[] = {
#ifdef MAX_PERI
{P2_13 , SPI_0, 2},
{P8_0 , SPI_0, 2},
{P4_5 , SPI_1, 2},
{P6_5 , SPI_1, 7},
{P8_4 , SPI_2, 3},
{P8_15 , SPI_2, 5},
{P3_1 , SPI_3, 8},
{P5_1 , SPI_3, 8},
{P2_9 , SPI_4, 8},
{P4_1 , SPI_4, 7},
{NC , NC , 0}
#else
{P4_5 , SPI_1, 2},
{P8_15 , SPI_2, 5},
{P5_1 , SPI_3, 8},
{P4_1 , SPI_4, 7},
{NC , NC , 0}
#endif
};
/************PWM***************/
const PinMap PinMap_PWM[] = {
#ifdef MAX_PERI
// TIOC0 A,C
{P4_0 , PWM_TIOC0A, 2}, //TIOC0A
{P5_0 , PWM_TIOC0A, 6}, //TIOC0A
{P7_0 , PWM_TIOC0A, 7}, //TIOC0A
{P4_2 , PWM_TIOC0C, 2}, //TIOC0C
{P5_5 , PWM_TIOC0C, 6}, //TIOC0C
{P7_2 , PWM_TIOC0C, 7}, //TIOC0C
//TIOC1 A
{P2_11 , PWM_TIOC1A, 5}, //TIOC1A
{P6_0 , PWM_TIOC1A, 5}, //TIOC1A
{P7_4 , PWM_TIOC1A, 7}, //TIOC1A
{P8_8 , PWM_TIOC1A, 5}, //TIOC1A
{P9_7 , PWM_TIOC1A, 4}, //TIOC1A
//TIOC2 A
{P2_1 , PWM_TIOC2A, 6}, //TIOC2A
{P6_2 , PWM_TIOC2A, 6}, //TIOC2A
{P7_6 , PWM_TIOC2A, 7}, //TIOC2A
{P8_14 , PWM_TIOC2A, 4}, //TIOC2A
//TIOC3 A,C
{P3_4 , PWM_TIOC3A, 6}, //TIOC3A
{P7_8 , PWM_TIOC3A, 7}, //TIOC3A
{P8_10 , PWM_TIOC3A, 4}, //TIOC3A
{P3_6 , PWM_TIOC3C, 6}, //TIOC3C
{P7_10 , PWM_TIOC3C, 7}, //TIOC3C
{P8_12 , PWM_TIOC3C, 4}, //TIOC3C
//TIOC4 A,C
{P3_8 , PWM_TIOC4A, 6}, //TIOC4A
{P4_4 , PWM_TIOC4A, 3}, //TIOC4A
{P7_12 , PWM_TIOC4A, 7}, //TIOC4A
{P3_10 , PWM_TIOC4C, 6}, //TIOC4C
{P4_6 , PWM_TIOC4C, 3}, //TIOC4C
{P7_14 , PWM_TIOC4C, 7}, //TIOC4C
//PWM1
{P8_8 , PWM_PWM1A , 6}, //PWM1A
{P8_9 , PWM_PWM1B , 6}, //PWM1B
{P8_10 , PWM_PWM1C , 6}, //PWM1C
{P8_11 , PWM_PWM1D , 6}, //PWM1D
{P8_12 , PWM_PWM1E , 6}, //PWM1E
{P8_13 , PWM_PWM1F , 6}, //PWM1F
{P8_14 , PWM_PWM1G , 6}, //PWM1G
{P8_15 , PWM_PWM1H , 6}, //PWM1H
//PWM2
{P3_0 , PWM_PWM2A , 7}, //PWM2A
{P3_1 , PWM_PWM2B , 7}, //PWM2B
{P3_2 , PWM_PWM2C , 7}, //PWM2C
{P3_3 , PWM_PWM2D , 7}, //PWM2D
{P4_4 , PWM_PWM2E , 4}, //PWM2E
{P4_5 , PWM_PWM2F , 4}, //PWM2F
{P4_6 , PWM_PWM2G , 4}, //PWM2G
{P4_7 , PWM_PWM2H , 4}, //PWM2H
{NC , NC , 0}
#else
//TIOC0 A,C
{P4_0 , PWM_TIOC0A, 2}, //TIOC0A
{P5_0 , PWM_TIOC0A, 6}, //TIOC0A
{P4_2 , PWM_TIOC0C, 2}, //TIOC0C
{P5_5 , PWM_TIOC0C, 6}, //TIOC0C
//TIOC2 A
{P8_14 , PWM_TIOC2A, 4}, //TIOC2A
//TIOC3 A,C
{P8_10 , PWM_TIOC3A, 4}, //TIOC3A
{P5_3 , PWM_TIOC3C, 6}, //TIOC3C
{P8_12 , PWM_TIOC3C, 4}, //TIOC3C
//TIOC4 A,C
{P3_8 , PWM_TIOC4A, 6}, //TIOC4A
{P4_4 , PWM_TIOC4A, 3}, //TIOC4A
{P3_10 , PWM_TIOC4C, 6}, //TIOC4C
{P4_6 , PWM_TIOC4C, 3}, //TIOC4C
//PWM1
{P8_10 , PWM_PWM1C , 6}, //PWM1C
{P8_11 , PWM_PWM1D , 6}, //PWM1D
{P8_12 , PWM_PWM1E , 6}, //PWM1E
{P8_13 , PWM_PWM1F , 6}, //PWM1F
{P8_14 , PWM_PWM1G , 6}, //PWM1G
{P8_15 , PWM_PWM1H , 6}, //PWM1H
//PWM2
{P3_0 , PWM_PWM2A , 7}, //PWM2A
{P3_1 , PWM_PWM2B , 7}, //PWM2B
{P3_2 , PWM_PWM2C , 7}, //PWM2C
{P4_4 , PWM_PWM2E , 4}, //PWM2E
{P4_5 , PWM_PWM2F , 4}, //PWM2F
{P4_6 , PWM_PWM2G , 4}, //PWM2G
{P4_7 , PWM_PWM2H , 4}, //PWM2H
{NC , NC , 0}
#endif
};
/************CAN***************/
const PinMap PinMap_CAN_RD[] = {
#ifdef MAX_PERI
{P7_8 , CAN_0, 4},
{P9_1 , CAN_0, 3},
{P1_4 , CAN_1, 3},
{P5_9 , CAN_1, 5},
{P7_11 , CAN_1, 4},
{P4_9 , CAN_2, 6},
{P6_4 , CAN_2, 3},
{P7_2 , CAN_2, 5},
{P2_12 , CAN_3, 5},
{P4_2 , CAN_3, 4},
{P1_5 , CAN_4, 3},
{P2_14 , CAN_4, 5},
{NC , NC , 0}
#else
{P9_1 , CAN_0, 3},
{P1_4 , CAN_1, 3},
{P5_9 , CAN_1, 5},
{P4_2 , CAN_3, 4},
{P1_5 , CAN_4, 3},
{NC , NC , 0}
#endif
};
const PinMap PinMap_CAN_TD[] = {
#ifdef MAX_PERI
{P7_9 , CAN_0, 4},
{P9_0 , CAN_0, 3},
{P5_10 , CAN_1, 5},
{P7_10 , CAN_1, 4},
{P4_8 , CAN_2, 6},
{P6_5 , CAN_2, 3},
{P7_3 , CAN_2, 5},
{P2_13 , CAN_3, 5},
{P4_3 , CAN_3, 4},
{P4_11 , CAN_4, 6},
{P8_10 , CAN_4, 5},
{NC , NC , 0}
#else
{P9_0 , CAN_0, 3},
{P5_10 , CAN_1, 5},
{P4_3 , CAN_3, 4},
{P8_10 , CAN_4, 5},
{NC , NC , 0}
#endif
};

133
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/analogin_api.c
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@ -1,133 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "analogin_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "adc_iodefine.h"
#include "cpg_iodefine.h"
#define ANALOGIN_MEDIAN_FILTER 0
#ifdef MAX_PERI
static const PinMap PinMap_ADC[] = {
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_14, AN6, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
};
#else
static const PinMap PinMap_ADC[] = {
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
};
#endif
static volatile uint16_t *ADCDR[] = {
&ADCADDRA,
&ADCADDRB,
&ADCADDRC,
&ADCADDRD,
&ADCADDRE,
&ADCADDRF,
&ADCADDRG,
&ADCADDRH,
};
void analogin_init(analogin_t *obj, PinName pin) {
obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
MBED_ASSERT(obj->adc != (ADCName)NC);
CPGSTBCR3 &= ~(1 << 1);
CPGSTBCR6 &= ~(1 << 7);
// 15: ADF 14: ADIE 13: ADST, [12:9] TRGS..0
// [8:6] CKS 010 :: 340tclk
// [5:3] MDS 000 :: single mode
// [2:0] CH 000 :: AN0
ADCADCSR = 0x0080;
pinmap_pinout(pin, PinMap_ADC);
}
static inline uint32_t adc_read(analogin_t *obj) {
volatile uint16_t data;
// Select the appropriate channel and start conversion
ADCADCSR &= 0xfff8;
ADCADCSR |= (1 << 13 | (obj->adc & 0x7));
// Wait end of conversion
do {
data = ADCADCSR;
} while (((data & (1 << 15)) == 0) || ((data & (1 << 13)) != 0));
// clear flag
ADCADCSR &= ~(1 << 15);
return ((*(ADCDR[obj->adc])) >> 4) & 0x0FFF; // 12 bits range
}
#if ANALOGIN_MEDIAN_FILTER
static inline void order(uint32_t *a, uint32_t *b) {
if (*a > *b) {
uint32_t t = *a;
*a = *b;
*b = t;
}
}
#endif
static inline uint32_t adc_read_u32(analogin_t *obj) {
uint32_t value;
#if ANALOGIN_MEDIAN_FILTER
uint32_t v1 = adc_read(obj);
uint32_t v2 = adc_read(obj);
uint32_t v3 = adc_read(obj);
order(&v1, &v2);
order(&v2, &v3);
order(&v1, &v2);
value = v2;
#else
value = adc_read(obj);
#endif
return value;
}
uint16_t analogin_read_u16(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (value << 4) | ((value >> 8) & 0x000F); // 12-bit to 16-bit conversion
}
float analogin_read(analogin_t *obj) {
uint32_t value = adc_read_u32(obj);
return (float)value * (1.0f / (float)0x0FFF); // 12 bits range
}

1042
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/can_api.c
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695
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/ethernet_api.c
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/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <string.h>
#include "ethernet_api.h"
#include "cmsis.h"
#include "mbed_interface.h"
#include "mbed_toolchain.h"
#include "mbed_error.h"
#include "ether_iodefine.h"
#include "ethernetext_api.h"
/* Descriptor info */
#define NUM_OF_TX_DESCRIPTOR (16)
#define NUM_OF_RX_DESCRIPTOR (16)
#define SIZE_OF_BUFFER (1600) /* Must be an integral multiple of 32 */
#define MAX_SEND_SIZE (1514)
/* Ethernet Descriptor Value Define */
#define TD0_TFP_TOP_BOTTOM (0x30000000)
#define TD0_TACT (0x80000000)
#define TD0_TDLE (0x40000000)
#define RD0_RACT (0x80000000)
#define RD0_RDLE (0x40000000)
#define RD0_RFE (0x08000000)
#define RD0_RCSE (0x04000000)
#define RD0_RFS (0x03FF0000)
#define RD0_RCS (0x0000FFFF)
#define RD0_RFS_RFOF (0x02000000)
#define RD0_RFS_RUAF (0x00400000)
#define RD0_RFS_RRF (0x00100000)
#define RD0_RFS_RTLF (0x00080000)
#define RD0_RFS_RTSF (0x00040000)
#define RD0_RFS_PRE (0x00020000)
#define RD0_RFS_CERF (0x00010000)
#define RD0_RFS_ERROR (RD0_RFS_RFOF | RD0_RFS_RUAF | RD0_RFS_RRF | RD0_RFS_RTLF | \
RD0_RFS_RTSF | RD0_RFS_PRE | RD0_RFS_CERF)
#define RD1_RDL_MSK (0x0000FFFF)
/* PHY Register */
#define BASIC_MODE_CONTROL_REG (0)
#define BASIC_MODE_STATUS_REG (1)
#define PHY_IDENTIFIER1_REG (2)
#define PHY_IDENTIFIER2_REG (3)
#define PHY_SP_CTL_STS_REG (31)
/* MII management interface access */
#define PHY_ADDR (0) /* Confirm the pin connection of the PHY-LSI */
#define PHY_ST (1)
#define PHY_WRITE (1)
#define PHY_READ (2)
#define MDC_WAIT (6) /* 400ns/4 */
#define BASIC_STS_MSK_LINK (0x0004) /* Link Status */
#define BASIC_STS_MSK_AUTO_CMP (0x0020) /* Auto-Negotiate Complete */
#define M_PHY_ID (0xFFFFFFF0)
#define PHY_ID_LAN8710A (0x0007C0F0)
/* ETHERPIR0 */
#define PIR0_MDI (0x00000008)
#define PIR0_MDO (0x00000004)
#define PIR0_MMD (0x00000002)
#define PIR0_MDC (0x00000001)
#define PIR0_MDC_HIGH (0x00000001)
#define PIR0_MDC_LOW (0x00000000)
/* ETHEREDRRR0 */
#define EDRRR0_RR (0x00000001)
/* ETHEREDTRR0 */
#define EDTRR0_TR (0x00000003)
/* software wait */
#define LOOP_100us (6700) /* Loop counter for software wait 6666=100us/((1/400MHz)*6cyc) */
#define EDMAC_EESIPR_INI_RECV (0x0205001F) /* 0x02000000 : Detect reception suspended */
/* 0x00040000 : Detect frame reception */
/* 0x00010000 : Receive FIFO overflow */
/* 0x00000010 : Residual bit frame reception */
/* 0x00000008 : Long frame reception */
/* 0x00000004 : Short frame reception */
/* 0x00000002 : PHY-LSI reception error */
/* 0x00000001 : Receive frame CRC error */
#define EDMAC_EESIPR_INI_EtherC (0x00400000) /* 0x00400000 : E-MAC status register */
/* Send descriptor */
typedef struct tag_edmac_send_desc {
uint32_t td0;
uint32_t td1;
uint8_t *td2;
uint32_t padding4;
} edmac_send_desc_t;
/* Receive descriptor */
typedef struct tag_edmac_recv_desc {
uint32_t rd0;
uint32_t rd1;
uint8_t *rd2;
uint32_t padding4;
} edmac_recv_desc_t;
/* memory */
/* The whole transmit/receive descriptors (must be allocated in 16-byte boundaries) */
/* Transmit/receive buffers (must be allocated in 16-byte boundaries) */
#if defined(__ICCARM__)
#pragma data_alignment=16
static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
(sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
(NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
(NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)] //16 bytes aligned!
@ ".mirrorram";
#else
static uint8_t ethernet_nc_memory[(sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR) +
(sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR) +
(NUM_OF_TX_DESCRIPTOR * SIZE_OF_BUFFER) +
(NUM_OF_RX_DESCRIPTOR * SIZE_OF_BUFFER)]
__attribute((section("NC_BSS"),aligned(16))); //16 bytes aligned!
#endif
static int32_t rx_read_offset; /* read offset */
static int32_t tx_wite_offset; /* write offset */
static uint32_t send_top_index;
static uint32_t recv_top_index;
static int32_t Interrupt_priority;
static edmac_send_desc_t *p_eth_desc_dsend = NULL;
static edmac_recv_desc_t *p_eth_desc_drecv = NULL;
static edmac_recv_desc_t *p_recv_end_desc = NULL;
static ethernetext_cb_fnc *p_recv_cb_fnc = NULL;
static char mac_addr[6] = {0x00, 0x02, 0xF7, 0xF0, 0x00, 0x00}; /* MAC Address */
static uint32_t phy_id = 0;
static uint32_t start_stop = 1; /* 0:stop 1:start */
/* function */
static void lan_reg_reset(void);
static void lan_desc_create(void);
static void lan_reg_set(int32_t link);
static uint16_t phy_reg_read(uint16_t reg_addr);
static void phy_reg_write(uint16_t reg_addr, uint16_t data);
static void mii_preamble(void);
static void mii_cmd(uint16_t reg_addr, uint32_t option);
static void mii_reg_read(uint16_t *data);
static void mii_reg_write(uint16_t data);
static void mii_z(void);
static void mii_write_1(void);
static void mii_write_0(void);
static void set_ether_pir(uint32_t set_data);
static void wait_100us(int32_t wait_cnt);
int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
int32_t i;
uint16_t val;
CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
/* -->4F<-- P1_14(ET_COL) */
GPIOPMC1 |= 0x4000;
GPIOPFCAE1 &= ~0x4000;
GPIOPFCE1 |= 0x4000;
GPIOPFC1 |= 0x4000;
GPIOPIPC1 |= 0x4000;
/* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0),
P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */
GPIOPMC2 |= 0x0FFF;
GPIOPFCAE2 &= ~0x0FFF;
GPIOPFCE2 &= ~0x0FFF;
GPIOPFC2 |= 0x0FFF;
GPIOPIPC2 |= 0x0FFF;
/* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
GPIOPMC3 |= 0x0078;
GPIOPFCAE3 &= ~0x0078;
GPIOPFCE3 &= ~0x0078;
GPIOPFC3 |= 0x0078;
GPIOPIPC3 |= 0x0078;
/* -->3F<-- P7_0(ET_MDC) */
GPIOPMC7 |= 0x0001;
GPIOPFCAE7 &= ~0x0001;
GPIOPFCE7 |= 0x0001;
GPIOPFC7 &= ~0x0001;
GPIOPIPC7 |= 0x0001;
/* Resets the E-MAC,E-DMAC */
lan_reg_reset();
/* Resets the PHY-LSI */
phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
for (i = 10000; i > 0; i--) {
val = phy_reg_read(BASIC_MODE_CONTROL_REG);
if (((uint32_t)val & 0x8000uL) == 0) {
break; /* Reset complete */
}
}
phy_id = ((uint32_t)phy_reg_read(PHY_IDENTIFIER1_REG) << 16)
| (uint32_t)phy_reg_read(PHY_IDENTIFIER2_REG);
Interrupt_priority = p_ethcfg->int_priority;
p_recv_cb_fnc = p_ethcfg->recv_cb;
start_stop = 1;
if (p_ethcfg->ether_mac != NULL) {
(void)memcpy(mac_addr, p_ethcfg->ether_mac, sizeof(mac_addr));
} else {
ethernet_address(mac_addr); /* Get MAC Address */
}
return 0;
}
void ethernetext_start_stop(int32_t mode) {
if (mode == 1) {
/* start */
ETHEREDTRR0 |= EDTRR0_TR;
ETHEREDRRR0 |= EDRRR0_RR;
start_stop = 1;
} else {
/* stop */
ETHEREDTRR0 &= ~EDTRR0_TR;
ETHEREDRRR0 &= ~EDRRR0_RR;
start_stop = 0;
}
}
int ethernetext_chk_link_mode(void) {
int32_t link;
uint16_t data;
if ((phy_id & M_PHY_ID) == PHY_ID_LAN8710A) {
data = phy_reg_read(PHY_SP_CTL_STS_REG);
switch (((uint32_t)data >> 2) & 0x00000007) {
case 0x0001:
link = HALF_10M;
break;
case 0x0005:
link = FULL_10M;
break;
case 0x0002:
link = HALF_TX;
break;
case 0x0006:
link = FULL_TX;
break;
default:
link = NEGO_FAIL;
break;
}
} else {
link = NEGO_FAIL;
}
return link;
}
void ethernetext_set_link_mode(int32_t link) {
lan_reg_reset(); /* Resets the E-MAC,E-DMAC */
lan_desc_create(); /* Initialize of buffer memory */
lan_reg_set(link); /* E-DMAC, E-MAC initialization */
}
int ethernet_init() {
ethernet_cfg_t ethcfg;
ethcfg.int_priority = 5;
ethcfg.recv_cb = NULL;
ethcfg.ether_mac = NULL;
ethernetext_init(&ethcfg);
ethernet_set_link(-1, 0); /* Auto-Negotiation */
return 0;
}
void ethernet_free() {
ETHERARSTR |= 0x00000001; /* ETHER software reset */
CPGSTBCR7 |= CPG_STBCR7_BIT_MSTP74; /* disable ETHER clock */
}
int ethernet_write(const char *data, int slen) {
edmac_send_desc_t *p_send_desc;
int32_t copy_size;
if ((p_eth_desc_dsend == NULL) || (data == NULL) || (slen < 0)
|| (tx_wite_offset < 0) || (tx_wite_offset >= MAX_SEND_SIZE)) {
copy_size = 0;
} else {
p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
if ((p_send_desc->td0 & TD0_TACT) != 0) {
copy_size = 0;
} else {
copy_size = MAX_SEND_SIZE - tx_wite_offset;
if (copy_size > slen) {
copy_size = slen;
}
(void)memcpy(&p_send_desc->td2[tx_wite_offset], data, copy_size);
tx_wite_offset += copy_size;
}
}
return copy_size;
}
int ethernet_send() {
edmac_send_desc_t *p_send_desc;
int32_t ret;
if ((p_eth_desc_dsend == NULL) || (tx_wite_offset <= 0)) {
ret = 0;
} else {
/* Transfer 1 frame */
p_send_desc = &p_eth_desc_dsend[send_top_index]; /* Current descriptor */
/* Sets the frame length */
p_send_desc->td1 = ((uint32_t)tx_wite_offset << 16);
tx_wite_offset = 0;
/* Sets the transmit descriptor to transmit again */
p_send_desc->td0 &= (TD0_TACT | TD0_TDLE | TD0_TFP_TOP_BOTTOM);
p_send_desc->td0 |= TD0_TACT;
if ((start_stop == 1) && ((ETHEREDTRR0 & EDTRR0_TR) != EDTRR0_TR)) {
ETHEREDTRR0 |= EDTRR0_TR;
}
/* Update the current descriptor */
send_top_index++;
if (send_top_index >= NUM_OF_TX_DESCRIPTOR) {
send_top_index = 0;
}
ret = 1;
}
return ret;
}
int ethernet_receive() {
edmac_recv_desc_t *p_recv_desc;
int32_t receive_size = 0;
if (p_eth_desc_drecv != NULL) {
if (p_recv_end_desc != NULL) {
/* Sets the receive descriptor to receive again */
p_recv_end_desc->rd0 &= (RD0_RACT | RD0_RDLE);
p_recv_end_desc->rd0 |= RD0_RACT;
if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
ETHEREDRRR0 |= EDRRR0_RR;
}
p_recv_end_desc = NULL;
}
p_recv_desc = &p_eth_desc_drecv[recv_top_index]; /* Current descriptor */
if ((p_recv_desc->rd0 & RD0_RACT) == 0) {
/* Receives 1 frame */
if (((p_recv_desc->rd0 & RD0_RFE) != 0) && ((p_recv_desc->rd0 & RD0_RFS_ERROR) != 0)) {
/* Receive frame error */
/* Sets the receive descriptor to receive again */
p_recv_desc->rd0 &= (RD0_RACT | RD0_RDLE);
p_recv_desc->rd0 |= RD0_RACT;
if ((start_stop == 1) && ((ETHEREDRRR0 & EDRRR0_RR) == 0)) {
ETHEREDRRR0 |= EDRRR0_RR;
}
} else {
/* Copies the received frame */
rx_read_offset = 0;
p_recv_end_desc = p_recv_desc;
receive_size = (p_recv_desc->rd1 & RD1_RDL_MSK); /* number of bytes received */
}
/* Update the current descriptor */
recv_top_index++;
if (recv_top_index >= NUM_OF_TX_DESCRIPTOR) {
recv_top_index = 0;
}
}
}
return receive_size;
}
int ethernet_read(char *data, int dlen) {
edmac_recv_desc_t *p_recv_desc = p_recv_end_desc; /* Read top descriptor */
int32_t copy_size;
if ((data == NULL) || (dlen < 0) || (p_recv_desc == NULL)) {
copy_size = 0;
} else {
copy_size = (p_recv_desc->rd1 & RD1_RDL_MSK) - rx_read_offset;
if (copy_size > dlen) {
copy_size = dlen;
}
(void)memcpy(data, &p_recv_desc->rd2[rx_read_offset], (size_t)copy_size);
rx_read_offset += copy_size;
}
return copy_size;
}
void ethernet_address(char *mac) {
if (mac != NULL) {
mbed_mac_address(mac); /* Get MAC Address */
}
}
int ethernet_link(void) {
int32_t ret;
uint16_t data;
data = phy_reg_read(BASIC_MODE_STATUS_REG);
if (((uint32_t)data & BASIC_STS_MSK_LINK) != 0) {
ret = 1;
} else {
ret = 0;
}
return ret;
}
void ethernet_set_link(int speed, int duplex) {
uint16_t data;
int32_t i;
int32_t link;
if ((speed < 0) || (speed > 1)) {
data = 0x1000; /* Auto-Negotiation Enable */
phy_reg_write(BASIC_MODE_CONTROL_REG, data);
for (i = 0; i < 1000; i++) {
data = phy_reg_read(BASIC_MODE_STATUS_REG);
if (((uint32_t)data & BASIC_STS_MSK_AUTO_CMP) != 0) {
break;
}
wait_100us(10);
}
} else {
data = (uint16_t)(((uint32_t)speed << 13) | ((uint32_t)duplex << 8));
phy_reg_write(BASIC_MODE_CONTROL_REG, data);
wait_100us(1);
}
link = ethernetext_chk_link_mode();
ethernetext_set_link_mode(link);
}
void INT_Ether(void) {
uint32_t stat_edmac;
uint32_t stat_etherc;
/* Clear the interrupt request flag */
stat_edmac = (ETHEREESR0 & ETHEREESIPR0); /* Targets are restricted to allowed interrupts */
ETHEREESR0 = stat_edmac;
/* Reception-related */
if (stat_edmac & EDMAC_EESIPR_INI_RECV) {
if (p_recv_cb_fnc != NULL) {
p_recv_cb_fnc();
}
}
/* E-MAC-related */
if (stat_edmac & EDMAC_EESIPR_INI_EtherC) {
/* Clear the interrupt request flag */
stat_etherc = (ETHERECSR0 & ETHERECSIPR0); /* Targets are restricted to allowed interrupts */
ETHERECSR0 = stat_etherc;
}
}
static void lan_reg_reset(void) {
volatile int32_t j = 400; /* Wait for B dia 256 cycles ((I dia/B dia)*256)/6cyc = 8*256/6 = 342 */
ETHERARSTR |= 0x00000001; /* ETHER software reset */
while (j--) {
/* Do Nothing */
}
ETHEREDSR0 |= 0x00000003; /* E-DMAC software reset */
ETHEREDMR0 |= 0x00000003; /* Set SWRR and SWRT simultaneously */
/* Check clear software reset */
while ((ETHEREDMR0 & 0x00000003) != 0) {
/* Do Nothing */
}
}
static void lan_desc_create(void) {
int32_t i;
uint8_t *p_memory_top;
(void)memset((void *)ethernet_nc_memory, 0, sizeof(ethernet_nc_memory));
p_memory_top = ethernet_nc_memory;
/* Descriptor area configuration */
p_eth_desc_dsend = (edmac_send_desc_t *)p_memory_top;
p_memory_top += (sizeof(edmac_send_desc_t) * NUM_OF_TX_DESCRIPTOR);
p_eth_desc_drecv = (edmac_recv_desc_t *)p_memory_top;
p_memory_top += (sizeof(edmac_recv_desc_t) * NUM_OF_RX_DESCRIPTOR);
/* Transmit descriptor */
for (i = 0; i < NUM_OF_TX_DESCRIPTOR; i++) {
p_eth_desc_dsend[i].td2 = p_memory_top; /* TD2 TBA */
p_memory_top += SIZE_OF_BUFFER;
p_eth_desc_dsend[i].td1 = 0; /* TD1 TDL */
p_eth_desc_dsend[i].td0 = TD0_TFP_TOP_BOTTOM; /* TD0:1frame/1buf1buf, transmission disabled */
}
p_eth_desc_dsend[i - 1].td0 |= TD0_TDLE; /* Set the last descriptor */
/* Receive descriptor */
for (i = 0; i < NUM_OF_RX_DESCRIPTOR; i++) {
p_eth_desc_drecv[i].rd2 = p_memory_top; /* RD2 RBA */
p_memory_top += SIZE_OF_BUFFER;
p_eth_desc_drecv[i].rd1 = ((uint32_t)SIZE_OF_BUFFER << 16); /* RD1 RBL */
p_eth_desc_drecv[i].rd0 = RD0_RACT; /* RD0:reception enabled */
}
p_eth_desc_drecv[i - 1].rd0 |= RD0_RDLE; /* Set the last descriptor */
/* Initialize descriptor management information */
send_top_index = 0;
recv_top_index = 0;
rx_read_offset = 0;
tx_wite_offset = 0;
p_recv_end_desc = NULL;
}
static void lan_reg_set(int32_t link) {
/* MAC address setting */
ETHERMAHR0 = ((uint32_t)mac_addr[0] << 24)
| ((uint32_t)mac_addr[1] << 16)
| ((uint32_t)mac_addr[2] << 8)
| (uint32_t)mac_addr[3];
ETHERMALR0 = ((uint32_t)mac_addr[4] << 8)
| (uint32_t)mac_addr[5];
/* E-DMAC */
ETHERTDLAR0 = (uint32_t)&p_eth_desc_dsend[0];
ETHERRDLAR0 = (uint32_t)&p_eth_desc_drecv[0];
ETHERTDFAR0 = (uint32_t)&p_eth_desc_dsend[0];
ETHERRDFAR0 = (uint32_t)&p_eth_desc_drecv[0];
ETHERTDFXR0 = (uint32_t)&p_eth_desc_dsend[NUM_OF_TX_DESCRIPTOR - 1];
ETHERRDFXR0 = (uint32_t)&p_eth_desc_drecv[NUM_OF_RX_DESCRIPTOR - 1];
ETHERTDFFR0 |= 0x00000001; /* TDLF Transmit Descriptor Queue Last Flag : Last descriptor (1) */
ETHERRDFFR0 |= 0x00000001; /* RDLF Receive Descriptor Queue Last Flag : Last descriptor (1) */
ETHEREDMR0 |= 0x00000040; /* Little endian */
ETHERTRSCER0 &= ~0x0003009F; /* All clear */
ETHERTFTR0 &= ~0x000007FF; /* TFT[10:0] Transmit FIFO Threshold : Store and forward modes (H'000) */
ETHERFDR0 |= 0x00000707; /* Transmit FIFO Size:2048 bytes, Receive FIFO Size:2048 bytes */
ETHERRMCR0 |= 0x00000001; /* RNC Receive Enable Control : Continuous reception enabled (1) */
ETHERFCFTR0 &= ~0x001F00FF;
ETHERFCFTR0 |= 0x00070007;
ETHERRPADIR0 &= ~0x001FFFFF; /* Padding Size:No padding insertion, Padding Slot:Inserts at first byte */
/* E-MAC */
ETHERECMR0 &= ~0x04BF2063; /* All clear */
ETHERRFLR0 &= ~0x0003FFFF; /* RFL[17:0] Receive Frame Length : 1518 bytes (H'00000) */
ETHERAPR0 &= ~0x0000FFFF; /* AP[15:0] Automatic PAUSE : Flow control is disabled (H'0000) */
ETHERMPR0 &= ~0x0000FFFF; /* MP[15:0] Manual PAUSE : Flow control is disabled (H'0000) */
ETHERTPAUSER0 &= ~0x0000FFFF; /* Upper Limit for Automatic PAUSE Frame : Retransmit count is unlimited */
ETHERCSMR &= ~0xC000003F; /* The result of checksum is not written back to the receive descriptor */
if ((link == FULL_TX) || (link == FULL_10M) || (link == NEGO_FAIL)) {
ETHERECMR0 |= 0x00000002; /* Set to full-duplex mode */
} else {
ETHERECMR0 &= ~0x00000002; /* Set to half-duplex mode */
}
/* Interrupt-related */
if (p_recv_cb_fnc != NULL) {
ETHEREESR0 |= 0xFF7F009F; /* Clear all status (by writing 1) */
ETHEREESIPR0 |= 0x00040000; /* FR Frame Reception (1) */
ETHERECSR0 |= 0x00000011; /* Clear all status (clear by writing 1) */
ETHERECSIPR0 &= ~0x00000011; /* PFROIP Disable, ICDIP Disable */
InterruptHandlerRegister(ETHERI_IRQn, INT_Ether); /* Ethernet interrupt handler registration */
GIC_SetPriority(ETHERI_IRQn, Interrupt_priority); /* Ethernet interrupt priority */
GIC_EnableIRQ(ETHERI_IRQn); /* Enables the E-DMAC interrupt */
}
ETHERECMR0 |= 0x00000060; /* RE Enable, TE Enable */
/* Enable transmission/reception */
if ((start_stop == 1) && ((ETHEREDRRR0 & 0x00000001) == 0)) {
ETHEREDRRR0 |= 0x00000001; /* RR */
}
}
static uint16_t phy_reg_read(uint16_t reg_addr) {
uint16_t data;
mii_preamble();
mii_cmd(reg_addr, PHY_READ);
mii_z();
mii_reg_read(&data);
mii_z();
return data;
}
static void phy_reg_write(uint16_t reg_addr, uint16_t data) {
mii_preamble();
mii_cmd(reg_addr, PHY_WRITE);
mii_write_1();
mii_write_0();
mii_reg_write(data);
mii_z();
}
static void mii_preamble(void) {
int32_t i = 32;
for (i = 32; i > 0; i--) {
/* 1 is output via the MII (Media Independent Interface) block. */
mii_write_1();
}
}
static void mii_cmd(uint16_t reg_addr, uint32_t option) {
int32_t i;
uint16_t data = 0;
data |= (PHY_ST << 14); /* ST code */
data |= (option << 12); /* OP code */
data |= (PHY_ADDR << 7); /* PHY Address */
data |= (uint16_t)(reg_addr << 2); /* Reg Address */
for (i = 14; i > 0; i--) {
if ((data & 0x8000) == 0) {
mii_write_0();
} else {
mii_write_1();
}
data <<= 1;
}
}
static void mii_reg_read(uint16_t *data) {
int32_t i;
uint16_t reg_data = 0;
/* Data are read in one bit at a time */
for (i = 16; i > 0; i--) {
set_ether_pir(PIR0_MDC_LOW);
set_ether_pir(PIR0_MDC_HIGH);
reg_data <<= 1;
reg_data |= (uint16_t)((ETHERPIR0 & PIR0_MDI) >> 3); /* MDI read */
set_ether_pir(PIR0_MDC_HIGH);
set_ether_pir(PIR0_MDC_LOW);
}
*data = reg_data;
}
static void mii_reg_write(uint16_t data) {
int32_t i;
/* Data are written one bit at a time */
for (i = 16; i > 0; i--) {
if ((data & 0x8000) == 0) {
mii_write_0();
} else {
mii_write_1();
}
data <<= 1;
}
}
static void mii_z(void) {
set_ether_pir(PIR0_MDC_LOW);
set_ether_pir(PIR0_MDC_HIGH);
set_ether_pir(PIR0_MDC_HIGH);
set_ether_pir(PIR0_MDC_LOW);
}
static void mii_write_1(void) {
set_ether_pir(PIR0_MDO | PIR0_MMD);
set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MDO | PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MDO | PIR0_MMD);
}
static void mii_write_0(void) {
set_ether_pir(PIR0_MMD);
set_ether_pir(PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MMD | PIR0_MDC);
set_ether_pir(PIR0_MMD);
}
static void set_ether_pir(uint32_t set_data) {
int32_t i;
for (i = MDC_WAIT; i > 0; i--) {
ETHERPIR0 = set_data;
}
}
static void wait_100us(int32_t wait_cnt) {
volatile int32_t j = LOOP_100us * wait_cnt;
while (--j) {
/* Do Nothing */
}
}

223
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_irq_api.c
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@ -1,223 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "gpio_irq_api.h"
#include "intc_iodefine.h"
#include "pinmap.h"
#include "cmsis.h"
#include "gpio_addrdefine.h"
#define CHANNEL_NUM 8
static void gpio_irq0(void);
static void gpio_irq1(void);
static void gpio_irq2(void);
static void gpio_irq3(void);
static void gpio_irq4(void);
static void gpio_irq5(void);
static void gpio_irq6(void);
static void gpio_irq7(void);
static gpio_irq_t *channel_obj[CHANNEL_NUM] = {NULL};
static gpio_irq_handler irq_handler;
static const int nIRQn_h = 32;
extern PinName gpio_multi_guard;
enum {
IRQ0,IRQ1,
IRQ2,IRQ3,
IRQ4,IRQ5,
IRQ6,IRQ7,
} IRQNo;
static const IRQHandler irq_tbl[CHANNEL_NUM] = {
&gpio_irq0,
&gpio_irq1,
&gpio_irq2,
&gpio_irq3,
&gpio_irq4,
&gpio_irq5,
&gpio_irq6,
&gpio_irq7,
};
#ifdef MAX_PERI
static const PinMap PinMap_IRQ[] = {
{P1_0, IRQ0, 4}, {P4_8, IRQ0, 8}, {P6_8, IRQ0, 8}, {P7_9, IRQ0, 8}, {P8_2, IRQ0, 5}, {P2_14, IRQ0, 8}, {P5_8, IRQ0, 2}, {P9_1, IRQ0, 4},
{P1_1, IRQ1, 4}, {P4_9, IRQ1, 8}, {P6_9, IRQ1, 8}, {P7_8, IRQ1, 8}, {P8_3, IRQ1, 6}, {P2_15, IRQ1, 8},
{P1_2, IRQ2, 4}, {P4_10, IRQ2, 8}, {P6_10, IRQ2, 8}, {P7_10, IRQ2, 8}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4}, {P6_3, IRQ2, 4},
{P1_3, IRQ3, 4}, {P4_11, IRQ3, 8}, {P6_11, IRQ3, 8}, {P7_11, IRQ3, 8}, {P1_9, IRQ3, 3}, {P6_4, IRQ3, 4},
{P1_4, IRQ4, 4}, {P4_12, IRQ4, 8}, {P6_12, IRQ4, 8}, {P7_12, IRQ4, 8}, {P1_10, IRQ4, 3}, {P3_3, IRQ4, 3}, {P6_1, IRQ4, 4},
{P1_5, IRQ5, 4}, {P4_13, IRQ5, 8}, {P6_13, IRQ5, 8}, {P7_13, IRQ5, 8}, {P1_11, IRQ5, 3}, {P2_0, IRQ5, 6}, {P6_0, IRQ5, 6}, {P8_7, IRQ5, 4},
{P1_6, IRQ6, 4}, {P4_14, IRQ6, 8}, {P6_14, IRQ6, 8}, {P7_14, IRQ6, 8}, {P2_12, IRQ6, 6}, {P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
{P1_7, IRQ7, 4}, {P4_15, IRQ7, 8}, {P6_15, IRQ7, 8}, {P6_2, IRQ7, 4}, {P2_13, IRQ7, 8},
{NC, NC, 0}
};
#else
static const PinMap PinMap_IRQ[] = {
{P9_1, IRQ0, 4},
{P7_8, IRQ1, 8},
{P1_2, IRQ2, 4}, {P1_8, IRQ2, 3}, {P3_0, IRQ2, 3}, {P5_9, IRQ2, 4},
{P1_3, IRQ3, 4}, {P1_9, IRQ3, 3},
{P1_4, IRQ4, 4}, {P1_10, IRQ4, 3},
{P1_5, IRQ5, 4}, {P1_11, IRQ5, 3},
{P3_1, IRQ6, 3}, {P3_9, IRQ6, 8}, {P5_6, IRQ6, 6},
{NC, NC, 0}
};
#endif
static void handle_interrupt_in(int irq_num) {
uint16_t irqs;
uint16_t edge_req;
gpio_irq_t *obj;
gpio_irq_event irq_event;
irqs = INTCIRQRR;
if (irqs & (1 << irq_num)) {
obj = channel_obj[irq_num];
if (obj != NULL) {
edge_req = ((INTCICR1 >> (obj->ch * 2)) & 3);
if (edge_req == 1) {
irq_event = IRQ_FALL;
} else if (edge_req == 2) {
irq_event = IRQ_RISE;
} else {
uint32_t mask = (1 << (obj->pin & 0x0F));
__I uint32_t *reg_in = (volatile uint32_t *) PPR((int)PINGROUP(obj->pin));
if ((*reg_in & mask) == 0) {
irq_event = IRQ_FALL;
} else {
irq_event = IRQ_RISE;
}
}
irq_handler(obj->port, irq_event);
}
INTCIRQRR &= ~(1 << irq_num);
}
}
static void gpio_irq0(void) {
handle_interrupt_in(0);
}
static void gpio_irq1(void) {
handle_interrupt_in(1);
}
static void gpio_irq2(void) {
handle_interrupt_in(2);
}
static void gpio_irq3(void) {
handle_interrupt_in(3);
}
static void gpio_irq4(void) {
handle_interrupt_in(4);
}
static void gpio_irq5(void) {
handle_interrupt_in(5);
}
static void gpio_irq6(void) {
handle_interrupt_in(6);
}
static void gpio_irq7(void) {
handle_interrupt_in(7);
}
int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id) {
int shift;
if (pin == NC) return -1;
obj->ch = pinmap_peripheral(pin, PinMap_IRQ);
obj->pin = (int)pin ;
obj->port = (int)id ;
shift = obj->ch*2;
channel_obj[obj->ch] = obj;
irq_handler = handler;
pinmap_pinout(pin, PinMap_IRQ);
gpio_multi_guard = pin; /* Set multi guard */
// INTC settings
InterruptHandlerRegister((IRQn_Type)(nIRQn_h+obj->ch), (void (*)(uint32_t))irq_tbl[obj->ch]);
INTCICR1 &= ~(0x3 << shift);
INTCICR1 |= (0x3 << shift);
GIC_SetPriority((IRQn_Type)(nIRQn_h+obj->ch), 5);
GIC_EnableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
obj->int_enable = 1;
__enable_irq();
return 0;
}
void gpio_irq_free(gpio_irq_t *obj) {
channel_obj[obj->ch] = NULL;
}
void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable) {
int shift = obj->ch*2;
uint16_t val = event == IRQ_RISE ? 2 :
event == IRQ_FALL ? 1 : 0;
uint16_t work_icr_val;
/* check edge interrupt setting */
work_icr_val = INTCICR1;
if (enable == 1) {
/* Set interrupt serect */
work_icr_val |= (val << shift);
} else {
/* Clear interrupt serect */
work_icr_val &= ~(val << shift);
}
if ((work_icr_val & (3 << shift)) == 0) {
/* No edge interrupt setting */
GIC_DisableIRQ((IRQn_Type)(nIRQn_h+obj->ch));
/* Clear Interrupt flags */
INTCIRQRR &= ~(1 << obj->ch);
INTCICR1 = work_icr_val;
} else if (obj->int_enable == 1) {
INTCICR1 = work_icr_val;
GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
} else {
INTCICR1 = work_icr_val;
}
}
void gpio_irq_enable(gpio_irq_t *obj) {
int shift = obj->ch*2;
uint16_t work_icr_val = INTCICR1;
/* check edge interrupt setting */
if ((work_icr_val & (3 << shift)) != 0) {
GIC_EnableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
}
obj->int_enable = 1;
}
void gpio_irq_disable(gpio_irq_t *obj) {
GIC_DisableIRQ((IRQn_Type)(nIRQn_h + obj->ch));
obj->int_enable = 0;
}

760
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/i2c_api.c
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@ -1,760 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "i2c_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "r_typedefs.h"
#include "riic_iodefine.h"
#include "RZ_A1_Init.h"
#include "VKRZA1H.h"
volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
#define REG(N) \
RIIC[obj->i2c]->RIICn##N
/* RIICnCR1 */
#define CR1_RST (1 << 6)
#define CR1_ICE (1 << 7)
/* RIICnCR2 */
#define CR2_ST (1 << 1)
#define CR2_RS (1 << 2)
#define CR2_SP (1 << 3)
#define CR2_TRS (1 << 5)
#define CR2_BBSY (1 << 7)
/* RIICnMR3 */
#define MR3_ACKBT (1 << 3)
#define MR3_ACKWP (1 << 4)
#define MR3_WAIT (1 << 6)
/* RIICnSER */
#define SER_SAR0E (1 << 0)
/* RIICnSR1 */
#define SR1_AAS0 (1 << 0)
/* RIICnSR2 */
#define SR2_START (1 << 2)
#define SR2_STOP (1 << 3)
#define SR2_NACKF (1 << 4)
#define SR2_RDRF (1 << 5)
#define SR2_TEND (1 << 6)
#define SR2_TDRE (1 << 7)
#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
static const PinMap PinMap_I2C_SDA[] = {
{P1_1 , I2C_0, 1},
{P1_3 , I2C_1, 1},
{P1_5 , I2C_2, 1},
{P1_7 , I2C_3, 1},
{NC , NC , 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{P1_0 , I2C_0, 1},
{P1_2 , I2C_1, 1},
{P1_4 , I2C_2, 1},
{P1_6 , I2C_3, 1},
{NC , NC, 0}
};
static inline int i2c_status(i2c_t *obj) {
return REG(SR2.UINT8[0]);
}
static void i2c_reg_reset(i2c_t *obj) {
/* full reset */
REG(CR1.UINT8[0]) &= ~CR1_ICE; // CR1.ICE off
REG(CR1.UINT8[0]) |= CR1_RST; // CR1.IICRST on
REG(CR1.UINT8[0]) |= CR1_ICE; // CR1.ICE on
REG(MR1.UINT8[0]) = 0x08; // P_phi /x 9bit (including Ack)
REG(SER.UINT8[0]) = 0x00; // no slave addr enabled
/* set frequency */
REG(MR1.UINT8[0]) |= obj->pclk_bit;
REG(BRL.UINT8[0]) = obj->width_low;
REG(BRH.UINT8[0]) = obj->width_hi;
REG(MR2.UINT8[0]) = 0x07;
REG(MR3.UINT8[0]) = 0x00;
REG(FER.UINT8[0]) = 0x72; // SCLE, NFE enabled, TMOT
REG(IER.UINT8[0]) = 0x00; // no interrupt
REG(CR1.UINT32) &= ~CR1_RST; // CR1.IICRST negate reset
}
static inline int i2c_wait_RDRF(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_RDRF) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
return 0;
}
static int i2c_wait_TDRE(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_TDRE) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
return 0;
}
static int i2c_wait_TEND(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_TEND) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
return 0;
}
static int i2c_wait_START(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_START) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
return 0;
}
static int i2c_wait_STOP(i2c_t *obj) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_STOP) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
return 0;
}
static int i2c_set_STOP(i2c_t *obj) {
/* SR2.STOP = 0 */
REG(SR2.UINT32) &= ~SR2_STOP;
/* Stop condition */
REG(CR2.UINT32) |= CR2_SP;
return 0;
}
static void i2c_set_SR2_NACKF_STOP(i2c_t *obj) {
/* SR2.NACKF = 0 */
REG(SR2.UINT32) &= ~SR2_NACKF;
/* SR2.STOP = 0 */
REG(SR2.UINT32) &= ~SR2_STOP;
}
static void i2c_set_MR3_NACK(i2c_t *obj) {
/* send a NOT ACK */
REG(MR3.UINT32) |= MR3_ACKWP;
REG(MR3.UINT32) |= MR3_ACKBT;
REG(MR3.UINT32) &= ~MR3_ACKWP;
}
static void i2c_set_MR3_ACK(i2c_t *obj) {
/* send a ACK */
REG(MR3.UINT32) |= MR3_ACKWP;
REG(MR3.UINT32) &= ~MR3_ACKBT;
REG(MR3.UINT32) &= ~MR3_ACKWP;
}
static inline void i2c_power_enable(i2c_t *obj) {
volatile uint8_t dummy;
switch ((int)obj->i2c) {
case I2C_0:
CPGSTBCR9 &= ~(0x80);
break;
case I2C_1:
CPGSTBCR9 &= ~(0x40);
break;
case I2C_2:
CPGSTBCR9 &= ~(0x20);
break;
case I2C_3:
CPGSTBCR9 &= ~(0x10);
break;
}
dummy = CPGSTBCR9;
}
void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
/* determine the I2C to use */
I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
obj->i2c = pinmap_merge(i2c_sda, i2c_scl);
MBED_ASSERT((int)obj->i2c != NC);
/* enable power */
i2c_power_enable(obj);
/* set default frequency at 100k */
i2c_frequency(obj, 100000);
pinmap_pinout(sda, PinMap_I2C_SDA);
pinmap_pinout(scl, PinMap_I2C_SCL);
obj->last_stop_flag = 1;
}
inline int i2c_start(i2c_t *obj) {
int timeout = 0;
while ((REG(CR2.UINT32) & CR2_BBSY) != 0) {
timeout ++;
if (timeout >= obj->bbsy_wait_cnt) {
break;
}
}
/* Start Condition */
REG(CR2.UINT8[0]) |= CR2_ST;
return 0;
}
static inline int i2c_restart(i2c_t *obj) {
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
/* ReStart condition */
REG(CR2.UINT32) |= CR2_RS;
return 0;
}
inline int i2c_stop(i2c_t *obj) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
return 0;
}
static void i2c_set_err_noslave(i2c_t *obj) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
obj->last_stop_flag = 1;
}
static inline int i2c_do_write(i2c_t *obj, int value) {
int timeout = 0;
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while ((i2c_status(obj) & SR2_TDRE) == 0) {
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
/* write the data */
REG(DRT.UINT32) = value;
return 0;
}
static inline int i2c_read_address_write(i2c_t *obj, int value) {
int status;
status = i2c_wait_TDRE(obj);
if (status == 0) {
/* write the data */
REG(DRT.UINT32) = value;
}
return status;
}
static inline int i2c_do_read(i2c_t *obj, int last) {
if (last == 2) {
/* this time is befor last byte read */
/* Set MR3 WAIT bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
} else if (last == 1) {
i2c_set_MR3_NACK(obj);
} else {
i2c_set_MR3_ACK(obj);
}
/* return the data */
return (REG(DRR.UINT32) & 0xFF);
}
void i2c_frequency(i2c_t *obj, int hz) {
float64_t pclk_val;
float64_t wait_utime;
volatile float64_t bps;
volatile float64_t L_time; /* H Width period */
volatile float64_t H_time; /* L Width period */
uint32_t tmp_L_width;
uint32_t tmp_H_width;
uint32_t remainder;
uint32_t wk_cks = 0;
/* set PCLK */
if (false == RZ_A1_IsClockMode0()) {
pclk_val = (float64_t)CM1_RENESAS_RZ_A1_P0_CLK;
} else {
pclk_val = (float64_t)CM0_RENESAS_RZ_A1_P0_CLK;
}
/* Min 10kHz, Max 400kHz */
if (hz < 10000) {
bps = 10000;
} else if (hz > 400000) {
bps = 400000;
} else {
bps = (float64_t)hz;
}
/* Calculation L width time */
L_time = (1 / (2 * bps)); /* Harf period of frequency */
H_time = L_time;
/* Check I2C mode of Speed */
if (bps > 100000) {
/* Fast-mode */
L_time -= 102E-9; /* Falling time of SCL clock. */
H_time -= 138E-9; /* Rising time of SCL clock. */
/* Check L wideth */
if (L_time < 1.3E-6) {
/* Wnen L width less than 1.3us */
/* Subtract Rise up and down time for SCL from H/L width */
L_time = 1.3E-6;
H_time = (1 / bps) - L_time - 138E-9 - 102E-9;
}
}
tmp_L_width = (uint32_t)(L_time * pclk_val * 10);
tmp_L_width >>= 1;
wk_cks++;
while (tmp_L_width >= 341) {
tmp_L_width >>= 1;
wk_cks++;
}
remainder = tmp_L_width % 10;
tmp_L_width = ((tmp_L_width + 9) / 10) - 3; /* carry */
tmp_H_width = (uint32_t)(H_time * pclk_val * 10);
tmp_H_width >>= wk_cks;
if (remainder == 0) {
tmp_H_width = ((tmp_H_width + 9) / 10) - 3; /* carry */
} else {
remainder += tmp_H_width % 10;
tmp_H_width = (tmp_H_width / 10) - 3;
if (remainder > 10) {
tmp_H_width += 1; /* fine adjustment */
}
}
/* timeout of BBSY bit is minimum low width by frequency */
/* so timeout calculates "(low width) * 2" by frequency */
wait_utime = (L_time * 2) * 1000000;
/* 1 wait of BBSY bit is about 0.3us. if it's below 0.3us, wait count is set as 1. */
if (wait_utime <= 0.3) {
obj->bbsy_wait_cnt = 1;
} else {
obj->bbsy_wait_cnt = (int)(wait_utime / 0.3);
}
/* I2C Rate */
obj->pclk_bit = (uint8_t)(0x10 * wk_cks); /* P_phi / xx */
obj->width_low = (uint8_t)(tmp_L_width | 0x000000E0);
obj->width_hi = (uint8_t)(tmp_H_width | 0x000000E0);
/* full reset */
i2c_reg_reset(obj);
}
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count = 0;
int status;
int value;
volatile uint32_t work_reg = 0;
i2c_set_MR3_ACK(obj);
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
status = i2c_start(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_BUS_BUSY;
}
}
obj->last_stop_flag = stop;
/* Send Slave address */
status = i2c_read_address_write(obj, (address | 0x01));
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* wait RDRF */
status = i2c_wait_RDRF(obj);
/* check ACK/NACK */
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
(void)i2c_set_STOP(obj);
/* dummy read */
value = REG(DRR.UINT32);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
obj->last_stop_flag = 1;
return I2C_ERROR_NO_SLAVE;
}
if (length != 0) {
/* Read in all except last byte */
if (length > 2) {
/* dummy read */
value = REG(DRR.UINT32);
for (count = 0; count < (length - 1); count++) {
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Recieve the data */
if (count == (length - 2)) {
value = i2c_do_read(obj, 1);
} else if ((length >= 3) && (count == (length - 3))) {
value = i2c_do_read(obj, 2);
} else {
value = i2c_do_read(obj, 0);
}
data[count] = (char)value;
}
} else if (length == 2) {
/* Set MR3 WAIT bit is 1 */
REG(MR3.UINT32) |= MR3_WAIT;
/* dummy read */
value = REG(DRR.UINT32);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
i2c_set_MR3_NACK(obj);
data[count] = (char)REG(DRR.UINT32);
count++;
} else {
/* length == 1 */
/* Set MR3 WAIT bit is 1 */;
REG(MR3.UINT32) |= MR3_WAIT;
i2c_set_MR3_NACK(obj);
/* dummy read */
value = REG(DRR.UINT32);
}
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
/* RIICnDRR read */
value = (REG(DRR.UINT32) & 0xFF);
data[count] = (char)value;
/* RIICnMR3.WAIT = 0 */
REG(MR3.UINT32) &= ~MR3_WAIT;
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
} else {
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
}
return length;
}
int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop) {
int cnt;
int status;
/* There is a STOP condition for last processing */
if (obj->last_stop_flag != 0) {
status = i2c_start(obj);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_BUS_BUSY;
}
}
obj->last_stop_flag = stop;
/* Send Slave address */
status = i2c_do_write(obj, address);
if (status != 0) {
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Wait send end */
status = i2c_wait_TEND(obj);
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
/* Send Write data */
for (cnt=0; cnt<length; cnt++) {
status = i2c_do_write(obj, data[cnt]);
if(status != 0) {
i2c_set_err_noslave(obj);
return cnt;
} else {
/* Wait send end */
status = i2c_wait_TEND(obj);
if ((status != 0) || ((REG(SR2.UINT32) & SR2_NACKF) != 0)) {
/* Slave sends NACK */
i2c_set_err_noslave(obj);
return I2C_ERROR_NO_SLAVE;
}
}
}
/* If not repeated start, send stop. */
if (stop) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
} else {
(void)i2c_restart(obj);
(void)i2c_wait_START(obj);
/* SR2.START = 0 */
REG(SR2.UINT32) &= ~SR2_START;
}
return length;
}
void i2c_reset(i2c_t *obj) {
(void)i2c_set_STOP(obj);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
}
int i2c_byte_read(i2c_t *obj, int last) {
int status;
int data;
data = i2c_do_read(obj, last);
/* wait for it to arrive */
status = i2c_wait_RDRF(obj);
if (status != 0) {
i2c_set_SR2_NACKF_STOP(obj);
return I2C_ERROR_NO_SLAVE;
}
return data;
}
int i2c_byte_write(i2c_t *obj, int data) {
int ack = 0;
int status;
int timeout = 0;
status = i2c_do_write(obj, (data & 0xFF));
if (status != 0) {
i2c_set_SR2_NACKF_STOP(obj);
} else {
while (((i2c_status(obj) & SR2_RDRF) == 0) && ((i2c_status(obj) & SR2_TEND) == 0)) {
timeout++;
if (timeout >= WAIT_TIMEOUT) {
return ack;
}
}
/* check ACK/NACK */
if ((REG(SR2.UINT32) & SR2_NACKF) != 0) {
/* NACK */
i2c_set_SR2_NACKF_STOP(obj);
} else {
ack = 1;
}
}
return ack;
}
void i2c_slave_mode(i2c_t *obj, int enable_slave) {
if (enable_slave != 0) {
REG(SER.UINT32) |= SER_SAR0E; // only slave addr 0 is enabled
} else {
REG(SER.UINT32) &= ~SER_SAR0E; // no slave addr enabled
}
}
int i2c_slave_receive(i2c_t *obj) {
int status;
int retval;
status = (REG(SR1.UINT8[0]) & SR1_AAS0);
status |= (REG(CR2.UINT8[0]) & CR2_TRS) >> 4;
switch(status) {
case 0x01:
/* the master is writing to this slave */
retval = 3;
break;
case 0x02:
/* the master is writing to all slave */
retval = 2;
break;
case 0x03:
/* the master has requested a read from this slave */
retval = 1;
break;
default :
/* no data */
retval = 0;
break;
}
return retval;
}
int i2c_slave_read(i2c_t *obj, char *data, int length) {
int timeout = 0;
int count;
int break_flg = 0;
if(length <= 0) {
return 0;
}
for (count = 0; ((count < (length + 1)) && (break_flg == 0)); count++) {
/* There is no timeout, but the upper limit value is set to avoid an infinite loop. */
while (((i2c_status(obj) & SR2_STOP) != 0) || ((i2c_status(obj) & SR2_RDRF) == 0)) {
if ((i2c_status(obj) & SR2_STOP) != 0) {
break_flg = 1;
break;
}
timeout ++;
if (timeout >= WAIT_TIMEOUT) {
return -1;
}
}
if (break_flg == 0) {
if (count == 0) {
/* dummy read */
(void)REG(DRR.UINT32);
} else {
data[count - 1] = (char)(REG(DRR.UINT32) & 0xFF);
}
}
}
if (break_flg == 0) {
(void)i2c_wait_STOP(obj);
} else {
if ((i2c_status(obj) & SR2_RDRF) != 0) {
if (count <= 1) {
/* fail safe */
/* dummy read */
(void)REG(DRR.UINT32);
} else {
data[count - 2] = (char)(REG(DRR.UINT32) & 0xFF);
}
}
}
/* SR2.STOP = 0 */
REG(SR2.UINT32) &= ~SR2_STOP;
return (count - 1);
}
int i2c_slave_write(i2c_t *obj, const char *data, int length) {
int count = 0;
int status = 0;
if(length <= 0) {
return 0;
}
while ((count < length) && (status == 0)) {
status = i2c_do_write(obj, data[count]);
if(status == 0) {
/* Wait send end */
status = i2c_wait_TEND(obj);
if ((status != 0) || ((count < (length - 1)) && ((REG(SR2.UINT32) & SR2_NACKF) != 0))) {
/* NACK */
break;
}
}
count++;
}
/* dummy read */
(void)REG(DRR.UINT32);
(void)i2c_wait_STOP(obj);
i2c_set_SR2_NACKF_STOP(obj);
return count;
}
void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask) {
REG(SAR0.UINT32) = (address & 0xfffffffe);
}

19
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/mbed_drv_cfg.h Normal file
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@ -0,0 +1,19 @@
#ifndef MBED_DRV_CFG_H
#define MBED_DRV_CFG_H
/* can_api.c */
#define CAN_TEST_GLOBAL_CH 1
/* gpio_api.c */
#define GPIO_GROUP_MAX 9
/* pwmout_api.c */
#define FUNC_MOTOR_CTL_PWM
#define FUMC_MTU2_PWM
/* rtc_api.c */
#define USE_RTCX1_CLK
//#define USE_EXTAL_CLK
//#define USE_RTCX3_CLK
#endif

192
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pinmap.c
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@ -1,192 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "pinmap.h"
#include "mbed_error.h"
#include "gpio_addrdefine.h"
PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
typedef struct {
PinName pin;
int function;
int pm;
} PinFunc;
#ifdef MAX_PERI
static const PinFunc PIPC_0_tbl[] = {
// pin func pm
{P4_0 , 2 , -1}, /* TIOC0A */
{P5_0 , 6 , -1}, /* TIOC0A */
{P7_0 , 7 , -1}, /* TIOC0A */
{P4_1 , 2 , -1}, /* TIOC0B */
{P5_1 , 6 , -1}, /* TIOC0B */
{P7_1 , 7 , -1}, /* TIOC0B */
{P4_2 , 2 , -1}, /* TIOC0C */
{P5_5 , 6 , -1}, /* TIOC0C */
{P7_2 , 7 , -1}, /* TIOC0C */
{P4_3 , 2 , -1}, /* TIOC0D */
{P5_7 , 6 , -1}, /* TIOC0D */
{P7_3 , 7 , -1}, /* TIOC0D */
{P2_11 , 5 , -1}, /* TIOC1A */
{P6_0 , 5 , -1}, /* TIOC1A */
{P7_4 , 7 , -1}, /* TIOC1A */
{P8_8 , 5 , -1}, /* TIOC1A */
{P9_7 , 4 , -1}, /* TIOC1A */
{P2_12 , 8 , -1}, /* TIOC1B */
{P5_2 , 6 , -1}, /* TIOC1B */
{P6_1 , 5 , -1}, /* TIOC1B */
{P7_5 , 7 , -1}, /* TIOC1B */
{P8_9 , 5 , -1}, /* TIOC1B */
{P2_1 , 6 , -1}, /* TIOC2A */
{P6_2 , 6 , -1}, /* TIOC2A */
{P7_6 , 7 , -1}, /* TIOC2A */
{P8_14 , 4 , -1}, /* TIOC2A */
{P2_2 , 6 , -1}, /* TIOC2B */
{P6_3 , 6 , -1}, /* TIOC2B */
{P7_7 , 7 , -1}, /* TIOC2B */
{P8_15 , 4 , -1}, /* TIOC2B */
{P3_4 , 6 , -1}, /* TIOC3A */
{P7_8 , 7 , -1}, /* TIOC3A */
{P8_10 , 4 , -1}, /* TIOC3A */
{P3_5 , 6 , -1}, /* TIOC3B */
{P7_9 , 7 , -1}, /* TIOC3B */
{P8_11 , 4 , -1}, /* TIOC3B */
{P3_6 , 6 , -1}, /* TIOC3C */
{P5_3 , 6 , -1}, /* TIOC3C */
{P7_10 , 7 , -1}, /* TIOC3C */
{P8_12 , 4 , -1}, /* TIOC3C */
{P3_7 , 6 , -1}, /* TIOC3D */
{P5_4 , 6 , -1}, /* TIOC3D */
{P7_11 , 7 , -1}, /* TIOC3D */
{P8_13 , 4 , -1}, /* TIOC3D */
{P3_8 , 6 , -1}, /* TIOC4A */
{P4_4 , 3 , -1}, /* TIOC4A */
{P7_12 , 7 , -1}, /* TIOC4A */
{P3_9 , 6 , -1}, /* TIOC4B */
{P4_5 , 3 , -1}, /* TIOC4B */
{P7_13 , 7 , -1}, /* TIOC4B */
{P3_10 , 6 , -1}, /* TIOC4C */
{P4_6 , 3 , -1}, /* TIOC4C */
{P7_14 , 7 , -1}, /* TIOC4C */
{P3_11 , 6 , -1}, /* TIOC4D */
{P4_7 , 3 , -1}, /* TIOC4D */
{P7_15 , 7 , -1}, /* TIOC4D */
{P5_7 , 1 , 1 }, /* TXOUT0M */
{P5_6 , 1 , 1 }, /* TXOUT0P */
{P5_5 , 1 , 1 }, /* TXOUT1M */
{P5_4 , 1 , 1 }, /* TXOUT1P */
{P5_3 , 1 , 1 }, /* TXOUT2M */
{P5_2 , 1 , 1 }, /* TXOUT2P */
{P5_1 , 1 , 1 }, /* TXCLKOUTM */
{P5_0 , 1 , 1 }, /* TXCLKOUTP */
{P2_11 , 4 , 0 }, /* SSITxD0 */
{P4_7 , 5 , 0 }, /* SSITxD0 */
{P7_4 , 6 , 0 }, /* SSITxD1 */
{P4_15 , 6 , 0 }, /* SSITxD3 */
{P7_11 , 2 , 0 }, /* SSITxD3 */
{P2_7 , 4 , 0 }, /* SSITxD5 */
{P4_11 , 5 , 0 }, /* SSITxD5 */
{P8_10 , 8 , 0 }, /* SSITxD5 */
{P3_7 , 8 , 0 }, /* WDTOVF */
{NC , 0 , -1}
};
#else
static const PinFunc PIPC_0_tbl[] = {
// pin func pm
{P4_0 , 2 , -1}, // TIOC0A
{P5_0 , 6 , -1}, // TIOC0A
{P4_2 , 2 , -1}, // TIOC0C
{P5_5 , 6 , -1}, // TIOC0C
//
{P8_14 , 4 , -1}, // TIOC2A
//
{P8_10 , 4 , -1}, // TIOC3A
{P5_3 , 6 , -1}, // TIOC3C
{P8_12 , 4 , -1}, // TIOC3C
//
{P3_8 , 6 , -1}, // TIOC4A
{P4_4 , 3 , -1}, // TIOC4A
{P3_10 , 6 , -1}, // TIOC4C
{P4_6 , 3 , -1}, // TIOC4C
//
{P5_7 , 1 , 1 }, // TXOUT0M
{P5_6 , 1 , 1 }, // TXOUT0P
{P5_5 , 1 , 1 }, // TXOUT1M
{P5_4 , 1 , 1 }, // TXOUT1P
{P5_3 , 1 , 1 }, // TXOUT2M
{P5_2 , 1 , 1 }, // TXOUT2P
{P5_1 , 1 , 1 }, // TXCLKOUTM
{P5_0 , 1 , 1 }, // TXCLKOUTP
{P4_7 , 5 , 0 }, // SSITxD0
{P8_10 , 8 , 0 }, // SSITxD5
{P3_7 , 8 , 0 }, // WDTOVF
{NC , 0 , -1}
};
#endif
void pin_function(PinName pin, int function) {
if (pin == (PinName)NC) return;
int n = pin >> 4;
int bitmask = 1<<(pin & 0xf);
const PinFunc * Pipc_0_func = PIPC_0_tbl;
int pipc_data = 1;
if (gpio_multi_guard != pin) {
if (function == 0) {
// means GPIO mode
*PMC(n) &= ~bitmask;
} else {
// alt-function mode
--function;
if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;}
if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;}
if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;}
while (Pipc_0_func->pin != NC) {
if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
pipc_data = 0;
if (Pipc_0_func->pm == 0) {
*PMSR(n) = (bitmask << 16) | 0;
} else if (Pipc_0_func->pm == 1) {
*PMSR(n) = (bitmask << 16) | bitmask;
} else {
// Do Nothing
}
break;
}
Pipc_0_func++;
}
if (pipc_data == 1) {
*PIPC(n) |= bitmask;
} else {
*PIPC(n) &= ~bitmask;
}
if (P1_0 <= pin && pin <= P1_7 && function == 0) {
*PBDC(n) |= bitmask;
}
*PMC(n) |= bitmask;
}
} else {
gpio_multi_guard = (PinName)NC;
}
}
void pin_mode(PinName pin, PinMode mode) {
// if (pin == (PinName)NC) { return; }
}

700
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/pwmout_api.c
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@ -1,700 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include "pwmout_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "RZ_A1_Init.h"
#include "cpg_iodefine.h"
#include "pwm_iodefine.h"
#include "gpio_addrdefine.h"
#ifdef MAX_PERI
#define MTU2_PWM_NUM 27
#define MTU2_PWM_SIGNAL 2
#define MTU2_PWM_OFFSET 0x20
// PORT ID, PWM ID, Pin function
static const PinMap PinMap_PWM[] = {
// TIOC0 A,C
{P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A
{P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A
{P7_0 , MTU2_PWM2_PIN , 7}, //TIOC0A
{P4_2 , MTU2_PWM3_PIN , 2}, //TIOC0C
{P5_5 , MTU2_PWM4_PIN , 6}, //TIOC0C
{P7_2 , MTU2_PWM5_PIN , 7}, //TIOC0C
//TIOC1 A
{P2_11 , MTU2_PWM6_PIN , 5}, //TIOC1A
{P6_0 , MTU2_PWM7_PIN , 5}, //TIOC1A
{P7_4 , MTU2_PWM8_PIN , 7}, //TIOC1A
{P8_8 , MTU2_PWM9_PIN , 5}, //TIOC1A
{P9_7 , MTU2_PWM10_PIN , 4}, //TIOC1A
//TIOC2 A
{P2_1 , MTU2_PWM11_PIN , 6}, //TIOC2A
{P6_2 , MTU2_PWM12_PIN , 6}, //TIOC2A
{P7_6 , MTU2_PWM13_PIN , 7}, //TIOC2A
{P8_14 , MTU2_PWM14_PIN , 4}, //TIOC2A
//TIOC3 A,C
{P3_4 , MTU2_PWM15_PIN , 6}, //TIOC3A
{P7_8 , MTU2_PWM16_PIN , 7}, //TIOC3A
{P8_10 , MTU2_PWM17_PIN , 4}, //TIOC3A
{P3_6 , MTU2_PWM18_PIN , 6}, //TIOC3C
{P7_10 , MTU2_PWM19_PIN , 7}, //TIOC3C
{P8_12 , MTU2_PWM20_PIN , 4}, //TIOC3C
//TIOC4 A,C
{P3_8 , MTU2_PWM21_PIN , 6}, //TIOC4A
{P4_4 , MTU2_PWM22_PIN , 3}, //TIOC4A
{P7_12 , MTU2_PWM23_PIN , 7}, //TIOC4A
{P3_10 , MTU2_PWM24_PIN , 6}, //TIOC4C
{P4_6 , MTU2_PWM25_PIN , 3}, //TIOC4C
{P7_14 , MTU2_PWM26_PIN , 7}, //TIOC4C
//PWM1
{P8_8 , PWM0_PIN , 6}, //PWM1A
{P8_9 , PWM1_PIN , 6}, //PWM1B
{P8_10 , PWM2_PIN , 6}, //PWM1C
{P8_11 , PWM3_PIN , 6}, //PWM1D
{P8_12 , PWM4_PIN , 6}, //PWM1E
{P8_13 , PWM5_PIN , 6}, //PWM1F
{P8_14 , PWM6_PIN , 6}, //PWM1G
{P8_15 , PWM7_PIN , 6}, //PWM1H
//PWM2
{P3_0 , PWM8_PIN , 7}, //PWM2A
{P3_1 , PWM9_PIN , 7}, //PWM2B
{P3_2 , PWM10_PIN , 7}, //PWM2C
{P3_3 , PWM11_PIN , 7}, //PWM2D
{P4_4 , PWM12_PIN , 4}, //PWM2E
{P4_5 , PWM13_PIN , 4}, //PWM2F
{P4_6 , PWM14_PIN , 4}, //PWM2G
{P4_7 , PWM15_PIN , 4}, //PWM2H
{NC , NC , 0}
};
static const PWMType PORT[] = {
PWM1A, // PWM0_PIN
PWM1B, // PWM1_PIN
PWM1C, // PWM2_PIN
PWM1D, // PWM3_PIN
PWM1E, // PWM4_PIN
PWM1F, // PWM5_PIN
PWM1G, // PWM6_PIN
PWM1H, // PWM7_PIN
PWM2A, // PWM8_PIN
PWM2B, // PWM9_PIN
PWM2C, // PWM10_PIN
PWM2D, // PWM11_PIN
PWM2E, // PWM12_PIN
PWM2F, // PWM13_PIN
PWM2G, // PWM14_PIN
PWM2H, // PWM15_PIN
};
static const MTU2_PWMType MTU2_PORT[] = {
TIOC0A, // MTU2_PWM0_PIN
TIOC0A, // MTU2_PWM1_PIN
TIOC0A, // MTU2_PWM2_PIN
TIOC0C, // MTU2_PWM3_PIN
TIOC0C, // MTU2_PWM4_PIN
TIOC0C, // MTU2_PWM5_PIN
TIOC1A, // MTU2_PWM6_PIN
TIOC1A, // MTU2_PWM7_PIN
TIOC1A, // MTU2_PWM8_PIN
TIOC1A, // MTU2_PWM9_PIN
TIOC1A, // MTU2_PWM10_PIN
TIOC2A, // MTU2_PWM11_PIN
TIOC2A, // MTU2_PWM12_PIN
TIOC2A, // MTU2_PWM13_PIN
TIOC2A, // MTU2_PWM14_PIN
TIOC3A, // MTU2_PWM15_PIN
TIOC3A, // MTU2_PWM16_PIN
TIOC3A, // MTU2_PWM17_PIN
TIOC3C, // MTU2_PWM18_PIN
TIOC3C, // MTU2_PWM19_PIN
TIOC3C, // MTU2_PWM20_PIN
TIOC4A, // MTU2_PWM21_PIN
TIOC4A, // MTU2_PWM22_PIN
TIOC4A, // MTU2_PWM23_PIN
TIOC4C, // MTU2_PWM24_PIN
TIOC4C, // MTU2_PWM25_PIN
TIOC4C, // MTU2_PWM26_PIN
};
static __IO uint16_t *PWM_MATCH[] = {
&PWMPWBFR_1A, // PWM0_PIN
&PWMPWBFR_1A, // PWM1_PIN
&PWMPWBFR_1C, // PWM2_PIN
&PWMPWBFR_1C, // PWM3_PIN
&PWMPWBFR_1E, // PWM4_PIN
&PWMPWBFR_1E, // PWM5_PIN
&PWMPWBFR_1G, // PWM6_PIN
&PWMPWBFR_1G, // PWM7_PIN
&PWMPWBFR_2A, // PWM8_PIN
&PWMPWBFR_2A, // PWM9_PIN
&PWMPWBFR_2C, // PWM10_PIN
&PWMPWBFR_2C, // PWM11_PIN
&PWMPWBFR_2E, // PWM12_PIN
&PWMPWBFR_2E, // PWM13_PIN
&PWMPWBFR_2G, // PWM14_PIN
&PWMPWBFR_2G, // PWM15_PIN
};
static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
{ &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM0_PIN
{ &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM1_PIN
{ &MTU2TGRA_0, &MTU2TGRB_0 } // MTU2_PWM2_PIN
{ &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM3_PIN
{ &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM4_PIN
{ &MTU2TGRC_0, &MTU2TGRD_0 } // MTU2_PWM5_PIN
{ &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM6_PIN
{ &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM7_PIN
{ &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM8_PIN
{ &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM9_PIN
{ &MTU2TGRA_1, &MTU2TGRB_1 } // MTU2_PWM10_PIN
{ &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM11_PIN
{ &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM12_PIN
{ &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM13_PIN
{ &MTU2TGRA_2, &MTU2TGRB_2 } // MTU2_PWM14_PIN
{ &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM15_PIN
{ &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM16_PIN
{ &MTU2TGRA_3, &MTU2TGRB_3 } // MTU2_PWM17_PIN
{ &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM18_PIN
{ &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM19_PIN
{ &MTU2TGRC_3, &MTU2TGRD_3 } // MTU2_PWM20_PIN
{ &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM21_PIN
{ &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM22_PIN
{ &MTU2TGRA_4, &MTU2TGRB_2 } // MTU2_PWM23_PIN
{ &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM24_PIN
{ &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM25_PIN
{ &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM26_PIN
};
#else
#define MTU2_PWM_NUM 12
#define MTU2_PWM_SIGNAL 2
#define MTU2_PWM_OFFSET 0x20
// PORT ID, PWM ID, Pin function
static const PinMap PinMap_PWM[] = {
//TIOC0 A,C
{P4_0 , MTU2_PWM0_PIN , 2}, //TIOC0A
{P5_0 , MTU2_PWM1_PIN , 6}, //TIOC0A
{P4_2 , MTU2_PWM2_PIN , 2}, //TIOC0C
{P5_5 , MTU2_PWM3_PIN , 6}, //TIOC0C
//TIOC2 A
{P8_14 , MTU2_PWM4_PIN , 4}, //TIOC2A
//TIOC3 A,C
{P8_10 , MTU2_PWM5_PIN , 4}, //TIOC3A
{P5_3 , MTU2_PWM6_PIN , 6}, //TIOC3C
{P8_12 , MTU2_PWM7_PIN , 4}, //TIOC3C
//TIOC4 A,C
{P3_8 , MTU2_PWM8_PIN , 6}, //TIOC4A
{P4_4 , MTU2_PWM9_PIN , 3}, //TIOC4A
{P3_10 , MTU2_PWM10_PIN , 6}, //TIOC4C
{P4_6 , MTU2_PWM11_PIN , 3}, //TIOC4C
//PWM1
{P8_10 , PWM0_PIN , 6}, //PWM1C
{P8_11 , PWM1_PIN , 6}, //PWM1D
{P8_12 , PWM2_PIN , 6}, //PWM1E
{P8_13 , PWM3_PIN , 6}, //PWM1F
{P8_14 , PWM4_PIN , 6}, //PWM1G
{P8_15 , PWM5_PIN , 6}, //PWM1H
//PWM2
{P3_0 , PWM6_PIN , 7}, //PWM2A
{P3_1 , PWM7_PIN , 7}, //PWM2B
{P3_2 , PWM8_PIN , 7}, //PWM2C
{P4_4 , PWM9_PIN , 4}, //PWM2E
{P4_5 , PWM10_PIN , 4}, //PWM2F
{P4_6 , PWM11_PIN , 4}, //PWM2G
{P4_7 , PWM12_PIN , 4}, //PWM2H
{NC , NC , 0}
};
static const PWMType PORT[] = {
PWM1C, // PWM0_PIN
PWM1D, // PWM1_PIN
PWM1E, // PWM2_PIN
PWM1F, // PWM3_PIN
PWM1G, // PWM4_PIN
PWM1H, // PWM5_PIN
PWM2A, // PWM6_PIN
PWM2B, // PWM7_PIN
PWM2C, // PWM8_PIN
PWM2E, // PWM9_PIN
PWM2F, // PWM10_PIN
PWM2G, // PWM11_PIN
PWM2H, // PWM12_PIN
};
static const MTU2_PWMType MTU2_PORT[] = {
TIOC0A, // MTU2_PWM0_PIN
TIOC0A, // MTU2_PWM1_PIN
TIOC0C, // MTU2_PWM2_PIN
TIOC0C, // MTU2_PWM3_PIN
TIOC2A, // MTU2_PWM4_PIN
TIOC3A, // MTU2_PWM5_PIN
TIOC3C, // MTU2_PWM6_PIN
TIOC3C, // MTU2_PWM7_PIN
TIOC4A, // MTU2_PWM8_PIN
TIOC4A, // MTU2_PWM9_PIN
TIOC4C, // MTU2_PWM10_PIN
TIOC4C, // MTU2_PWM11_PIN
};
static __IO uint16_t *PWM_MATCH[] = {
&PWMPWBFR_1C, // PWM0_PIN
&PWMPWBFR_1C, // PWM1_PIN
&PWMPWBFR_1E, // PWM2_PIN
&PWMPWBFR_1E, // PWM3_PIN
&PWMPWBFR_1G, // PWM4_PIN
&PWMPWBFR_1G, // PWM5_PIN
&PWMPWBFR_2A, // PWM6_PIN
&PWMPWBFR_2A, // PWM7_PIN
&PWMPWBFR_2C, // PWM8_PIN
&PWMPWBFR_2E, // PWM9_PIN
&PWMPWBFR_2E, // PWM10_PIN
&PWMPWBFR_2G, // PWM11_PIN
&PWMPWBFR_2G, // PWM12_PIN
};
static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = {
{ &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM0_PIN
{ &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM1_PIN
{ &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM2_PIN
{ &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM3_PIN
{ &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM4_PIN
{ &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM5_PIN
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM6_PIN
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM7_PIN
{ &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM8_PIN
{ &MTU2TGRA_4, &MTU2TGRB_2 }, // MTU2_PWM9_PIN
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM10_PIN
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM11_PIN
};
#endif
static __IO uint8_t *TCR_MATCH[] = {
&MTU2TCR_0,
&MTU2TCR_1,
&MTU2TCR_2,
&MTU2TCR_3,
&MTU2TCR_4,
};
static __IO uint8_t *TIORH_MATCH[] = {
&MTU2TIORH_0,
&MTU2TIOR_1,
&MTU2TIOR_2,
&MTU2TIORH_3,
&MTU2TIORH_4,
};
static __IO uint8_t *TIORL_MATCH[] = {
&MTU2TIORL_0,
NULL,
NULL,
&MTU2TIORL_3,
&MTU2TIORL_4,
};
static __IO uint16_t *TGRA_MATCH[] = {
&MTU2TGRA_0,
&MTU2TGRA_1,
&MTU2TGRA_2,
&MTU2TGRA_3,
&MTU2TGRA_4,
};
static __IO uint16_t *TGRC_MATCH[] = {
&MTU2TGRC_0,
NULL,
NULL,
&MTU2TGRC_3,
&MTU2TGRC_4,
};
static __IO uint8_t *TMDR_MATCH[] = {
&MTU2TMDR_0,
&MTU2TMDR_1,
&MTU2TMDR_2,
&MTU2TMDR_3,
&MTU2TMDR_4,
};
static int MAX_PERIOD[] = {
125000,
503000,
2000000,
2000000,
2000000,
};
typedef enum {
MODE_PWM = 0,
MODE_MTU2
} PWMmode;
typedef enum {
MTU2_PULSE = 0,
MTU2_PERIOD
} MTU2Signal;
static int pwm_mode = MODE_PWM;
static uint16_t init_period_ch1 = 0;
static uint16_t init_period_ch2 = 0;
static uint16_t init_mtu2_period_ch[5] = {0};
static int32_t period_ch1 = 1;
static int32_t period_ch2 = 1;
static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
void pwmout_init(pwmout_t* obj, PinName pin) {
// determine the channel
PWMName pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
MBED_ASSERT(pwm != (PWMName)NC);
if (pwm >= MTU2_PWM_OFFSET) {
/* PWM by MTU2 */
int tmp_pwm;
pwm_mode = MODE_MTU2;
// power on
CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP33);
obj->pwm = pwm;
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000040) == 0x00000040) {
obj->ch = 4;
MTU2TOER |= 0x36;
} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000030) == 0x00000030) {
obj->ch = 3;
MTU2TOER |= 0x09;
} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000020) == 0x00000020) {
obj->ch = 2;
} else if (((uint32_t)MTU2_PORT[tmp_pwm] & 0x00000010) == 0x00000010) {
obj->ch = 1;
} else {
obj->ch = 0;
}
// Wire pinout
pinmap_pinout(pin, PinMap_PWM);
int bitmask = 1 << (pin & 0xf);
*PMSR(PINGROUP(pin)) = (bitmask << 16) | 0;
// default duty 0.0f
pwmout_write(obj, 0);
if (init_mtu2_period_ch[obj->ch] == 0) {
// default period 1ms
pwmout_period_us(obj, 1000);
init_mtu2_period_ch[obj->ch] = 1;
}
} else {
/* PWM */
pwm_mode = MODE_PWM;
// power on
CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
obj->pwm = pwm;
if (((uint32_t)PORT[obj->pwm] & 0x00000010) == 0x00000010) {
obj->ch = 2;
PWMPWPR_2_BYTE_L = 0x00;
} else {
obj->ch = 1;
PWMPWPR_1_BYTE_L = 0x00;
}
// Wire pinout
pinmap_pinout(pin, PinMap_PWM);
// default to 491us: standard for servos, and fine for e.g. brightness control
pwmout_write(obj, 0);
if ((obj->ch == 2) && (init_period_ch2 == 0)) {
pwmout_period_us(obj, 491);
init_period_ch2 = 1;
}
if ((obj->ch == 1) && (init_period_ch1 == 0)) {
pwmout_period_us(obj, 491);
init_period_ch1 = 1;
}
}
}
void pwmout_free(pwmout_t* obj) {
pwmout_write(obj, 0);
}
void pwmout_write(pwmout_t* obj, float value) {
uint32_t wk_cycle;
uint16_t v;
if (pwm_mode == MODE_MTU2) {
/* PWM by MTU2 */
int tmp_pwm;
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
value = 1.0f;
} else {
// Do Nothing
}
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
// set channel match to percentage
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
} else {
/* PWM */
if (value < 0.0f) {
value = 0.0f;
} else if (value > 1.0f) {
value = 1.0f;
} else {
// Do Nothing
}
if (obj->ch == 2) {
wk_cycle = PWMPWCYR_2 & 0x03ff;
} else {
wk_cycle = PWMPWCYR_1 & 0x03ff;
}
// set channel match to percentage
v = (uint16_t)((float)wk_cycle * value);
*PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
}
}
float pwmout_read(pwmout_t* obj) {
uint32_t wk_cycle;
float value;
if (pwm_mode == MODE_MTU2) {
/* PWM by MTU2 */
uint32_t wk_pulse;
int tmp_pwm;
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
value = ((float)wk_pulse / (float)wk_cycle);
} else {
/* PWM */
if (obj->ch == 2) {
wk_cycle = PWMPWCYR_2 & 0x03ff;
} else {
wk_cycle = PWMPWCYR_1 & 0x03ff;
}
value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
}
return (value > 1.0f) ? (1.0f) : (value);
}
void pwmout_period(pwmout_t* obj, float seconds) {
pwmout_period_us(obj, seconds * 1000000.0f);
}
void pwmout_period_ms(pwmout_t* obj, int ms) {
pwmout_period_us(obj, ms * 1000);
}
static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
uint16_t wk_pwmpbfr;
float value;
uint16_t v;
wk_pwmpbfr = *p_pwmpbfr;
value = ((float)(wk_pwmpbfr & 0x03ff) / (float)last_cycle);
v = (uint16_t)((float)new_cycle * value);
*p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
}
static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
uint16_t wk_pwmpbfr;
float value;
wk_pwmpbfr = *p_pwmpbfr;
value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
*p_pwmpbfr = (uint16_t)((float)new_cycle * value);
}
// Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) {
uint64_t wk_cycle_mtu2;
uint32_t pclk_base;
uint32_t wk_cycle;
uint32_t wk_cks = 0;
uint16_t wk_last_cycle;
int max_us = 0;
if (pwm_mode == MODE_MTU2) {
/* PWM by MTU2 */
int tmp_pwm;
uint8_t tmp_tcr_up;
uint8_t tmp_tstr_sp;
uint8_t tmp_tstr_st;
max_us = MAX_PERIOD[obj->ch];
if (us > max_us) {
us = max_us;
} else if (us < 1) {
us = 1;
} else {
// Do Nothing
}
if (RZ_A1_IsClockMode0() == false) {
pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK;
} else {
pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK;
}
wk_cycle_mtu2 = (uint64_t)pclk_base * us;
while (wk_cycle_mtu2 >= 65535000000) {
if ((obj->ch == 1) && (wk_cks == 3)) {
wk_cks+=2;
} else if ((obj->ch == 2) && (wk_cks == 3)) {
wk_cycle_mtu2 >>= 2;
wk_cks+=3;
}
wk_cycle_mtu2 >>= 2;
wk_cks++;
}
wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
tmp_tcr_up = 0xC0;
} else {
tmp_tcr_up = 0x40;
}
if ((obj->ch == 4) || (obj->ch == 3)) {
tmp_tstr_sp = ~(0x38 | (1 << (obj->ch + 3)));
tmp_tstr_st = (1 << (obj->ch + 3));
} else {
tmp_tstr_sp = ~(0x38 | (1 << obj->ch));
tmp_tstr_st = (1 << obj->ch);
}
// Counter Stop
MTU2TSTR &= tmp_tstr_sp;
wk_last_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
*TCR_MATCH[obj->ch] = tmp_tcr_up | wk_cks;
*TIORH_MATCH[obj->ch] = 0x21;
if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
*TIORL_MATCH[obj->ch] = 0x21;
}
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] = (uint16_t)wk_cycle; // Set period
// Set duty again(TGRA)
set_mtu2_duty_again(TGRA_MATCH[obj->ch], wk_last_cycle, wk_cycle);
if ((obj->ch == 0) || (obj->ch == 3) || (obj->ch == 4)) {
// Set duty again(TGRC)
set_mtu2_duty_again(TGRC_MATCH[obj->ch], wk_last_cycle, wk_cycle);
}
*TMDR_MATCH[obj->ch] = 0x02; // PWM mode 1
// Counter Start
MTU2TSTR |= tmp_tstr_st;
// Save for future use
mtu2_period_ch[obj->ch] = us;
} else {
/* PWM */
if (us > 491) {
us = 491;
} else if (us < 1) {
us = 1;
} else {
// Do Nothing
}
if (RZ_A1_IsClockMode0() == false) {
pclk_base = (uint32_t)CM1_RENESAS_RZ_A1_P0_CLK / 10000;
} else {
pclk_base = (uint32_t)CM0_RENESAS_RZ_A1_P0_CLK / 10000;
}
wk_cycle = pclk_base * us;
while (wk_cycle >= 102350) {
wk_cycle >>= 1;
wk_cks++;
}
wk_cycle = (wk_cycle + 50) / 100;
if (obj->ch == 2) {
wk_last_cycle = PWMPWCYR_2 & 0x03ff;
PWMPWCR_2_BYTE_L = 0xc0 | wk_cks;
PWMPWCYR_2 = (uint16_t)wk_cycle;
// Set duty again
set_duty_again(&PWMPWBFR_2A, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_2C, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_2E, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_2G, wk_last_cycle, wk_cycle);
// Counter Start
PWMPWCR_2_BYTE_L |= 0x08;
// Save for future use
period_ch2 = us;
} else {
wk_last_cycle = PWMPWCYR_1 & 0x03ff;
PWMPWCR_1_BYTE_L = 0xc0 | wk_cks;
PWMPWCYR_1 = (uint16_t)wk_cycle;
// Set duty again
set_duty_again(&PWMPWBFR_1A, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_1C, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_1E, wk_last_cycle, wk_cycle);
set_duty_again(&PWMPWBFR_1G, wk_last_cycle, wk_cycle);
// Counter Start
PWMPWCR_1_BYTE_L |= 0x08;
// Save for future use
period_ch1 = us;
}
}
}
void pwmout_pulsewidth(pwmout_t* obj, float seconds) {
pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
}
void pwmout_pulsewidth_ms(pwmout_t* obj, int ms) {
pwmout_pulsewidth_us(obj, ms * 1000);
}
void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
float value = 0;
if (pwm_mode == MODE_MTU2) {
/* PWM by MTU2 */
if (mtu2_period_ch[obj->ch] != 0) {
value = (float)us / (float)mtu2_period_ch[obj->ch];
}
} else {
/* PWM */
if (obj->ch == 2) {
if (period_ch2 != 0) {
value = (float)us / (float)period_ch2;
}
} else {
if (period_ch1 != 0) {
value = (float)us / (float)period_ch1;
}
}
}
pwmout_write(obj, value);
}

672
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/serial_api.c
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@ -1,672 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2015 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
// math.h required for floating point operations for baud rate calculation
#include "mbed_assert.h"
#include <math.h>
#include <string.h>
#include <stdlib.h>
#include "serial_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "gpio_api.h"
#include "mbed_critical.h"
#include "scif_iodefine.h"
#include "cpg_iodefine.h"
/******************************************************************************
* INITIALIZATION
******************************************************************************/
#define PCLK (66666666) // Define the peripheral clock P1 frequency.
#define UART_NUM 8
#define IRQ_NUM 2
static void uart0_tx_irq(void);
static void uart1_tx_irq(void);
static void uart2_tx_irq(void);
static void uart3_tx_irq(void);
static void uart4_tx_irq(void);
static void uart5_tx_irq(void);
static void uart6_tx_irq(void);
static void uart7_tx_irq(void);
static void uart0_rx_irq(void);
static void uart1_rx_irq(void);
static void uart2_rx_irq(void);
static void uart3_rx_irq(void);
static void uart4_rx_irq(void);
static void uart5_rx_irq(void);
static void uart6_rx_irq(void);
static void uart7_rx_irq(void);
#ifdef MAX_PERI
static const PinMap PinMap_UART_TX[] = {
{P2_14 , UART0, 6},
{P4_9 , UART0, 7},
{P6_9 , UART0, 5},
{P2_5 , UART1, 6},
{P4_12 , UART1, 7},
{P6_12 , UART1, 5},
{P9_3 , UART1, 4},
{P3_0 , UART2, 6},
{P3_1 , UART2, 4},
{P4_2 , UART2, 5},
{P4_14 , UART2, 7},
{P6_3 , UART2, 7},
{P8_6 , UART2, 7},
{P3_5 , UART3, 7},
{P5_3 , UART3, 5},
{P6_1 , UART3, 7},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P7_1 , UART4, 4},
{P8_14 , UART4, 7},
{P6_6 , UART5, 5},
{P8_1 , UART5, 4},
{P8_13 , UART5, 5},
{P5_6 , UART6, 5},
{P6_14 , UART6, 4},
{P7_4 , UART7, 4},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{P2_15 , UART0, 6},
{P4_10 , UART0, 7},
{P6_10 , UART0, 5},
{P2_6 , UART1, 6},
{P4_13 , UART1, 7},
{P6_13 , UART1, 5},
{P9_4 , UART1, 4},
{P3_2 , UART2, 4},
{P4_3 , UART2, 5},
{P4_15 , UART2, 7},
{P6_2 , UART2, 7},
{P8_4 , UART2, 7},
{P3_6 , UART3, 7},
{P5_4 , UART3, 5},
{P6_0 , UART3, 7},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P7_2 , UART4, 4},
{P8_15 , UART4, 7},
{P6_7 , UART5, 5},
{P8_2 , UART5, 4},
{P8_11 , UART5, 5},
{P5_7 , UART6, 5},
{P6_15 , UART6, 4},
{P7_5 , UART7, 4},
{NC , NC , 0}
};
static const PinMap PinMap_UART_CTS[] = {
{P2_3 , UART1, 6},
{P9_5 , UART1, 4},
{P6_3 , UART5, 5},
{P7_15 , UART5, 4},
{P7_6 , UART7, 4},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RTS[] = {
{P2_7 , UART1, 6},
{P9_6 , UART1, 4},
{P6_4 , UART5, 5},
{P8_3 , UART5, 4},
{P7_7 , UART7, 4},
{NC , NC , 0}
};
#else
static const PinMap PinMap_UART_TX[] = {
{P3_0 , UART2, 6},
{P3_1 , UART2, 4},
{P4_2 , UART2, 5},
{P5_3 , UART3, 5},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P8_14 , UART4, 7},
{P8_13 , UART5, 5},
{P5_6 , UART6, 5},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{P3_2 , UART2, 4},
{P4_3 , UART2, 5},
{P5_4 , UART3, 5},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P8_15 , UART4, 7},
{P8_11 , UART5, 5},
{P5_7 , UART6, 5},
{NC , NC , 0}
};
static const PinMap PinMap_UART_CTS[] = {
{NC , NC , 0}
};
static const PinMap PinMap_UART_RTS[] = {
{NC , NC , 0}
};
#endif
static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
static uart_irq_handler irq_handler;
int stdio_uart_inited = 0;
serial_t stdio_uart;
struct serial_global_data_s {
uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts;
uint8_t count, rx_irq_set_flow, rx_irq_set_api;
};
static struct serial_global_data_s uart_data[UART_NUM];
static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
{SCIFRXI0_IRQn, SCIFTXI0_IRQn},
{SCIFRXI1_IRQn, SCIFTXI1_IRQn},
{SCIFRXI2_IRQn, SCIFTXI2_IRQn},
{SCIFRXI3_IRQn, SCIFTXI3_IRQn},
{SCIFRXI4_IRQn, SCIFTXI4_IRQn},
{SCIFRXI5_IRQn, SCIFTXI5_IRQn},
{SCIFRXI6_IRQn, SCIFTXI6_IRQn},
{SCIFRXI7_IRQn, SCIFTXI7_IRQn}
};
static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
{uart0_rx_irq, uart0_tx_irq},
{uart1_rx_irq, uart1_tx_irq},
{uart2_rx_irq, uart2_tx_irq},
{uart3_rx_irq, uart3_tx_irq},
{uart4_rx_irq, uart4_tx_irq},
{uart5_rx_irq, uart5_tx_irq},
{uart6_rx_irq, uart6_tx_irq},
{uart7_rx_irq, uart7_tx_irq}
};
static __IO uint16_t *SCSCR_MATCH[] = {
&SCSCR_0,
&SCSCR_1,
&SCSCR_2,
&SCSCR_3,
&SCSCR_4,
&SCSCR_5,
&SCSCR_6,
&SCSCR_7,
};
static __IO uint16_t *SCFSR_MATCH[] = {
&SCFSR_0,
&SCFSR_1,
&SCFSR_2,
&SCFSR_3,
&SCFSR_4,
&SCFSR_5,
&SCFSR_6,
&SCFSR_7,
};
void serial_init(serial_t *obj, PinName tx, PinName rx) {
volatile uint8_t dummy ;
int is_stdio_uart = 0;
// determine the UART to use
uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
uint32_t uart = pinmap_merge(uart_tx, uart_rx);
MBED_ASSERT((int)uart != NC);
obj->uart = (struct st_scif *)SCIF[uart];
// enable power
switch (uart) {
case UART0:
CPG.STBCR4 &= ~(1 << 7);
break;
case UART1:
CPG.STBCR4 &= ~(1 << 6);
break;
case UART2:
CPG.STBCR4 &= ~(1 << 5);
break;
case UART3:
CPG.STBCR4 &= ~(1 << 4);
break;
case UART4:
CPG.STBCR4 &= ~(1 << 3);
break;
case UART5:
CPG.STBCR4 &= ~(1 << 2);
break;
case UART6:
CPG.STBCR4 &= ~(1 << 1);
break;
case UART7:
CPG.STBCR4 &= ~(1 << 0);
break;
}
dummy = CPG.STBCR4;
/* if this uart has been previously configured to tx, wait tx completion befor loading new configuration */
if(obj->uart->SCSCR & 0xA0)
while(!(obj->uart->SCFSR & 0x0040));
/* ==== SCIF initial setting ==== */
/* ---- Serial control register (SCSCR) setting ---- */
/* B'00 : Internal CLK */
obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
/* ---- FIFO control register (SCFCR) setting ---- */
/* Transmit FIFO reset & Receive FIFO data register reset */
obj->uart->SCFCR = 0x0006;
/* ---- Serial status register (SCFSR) setting ---- */
dummy = obj->uart->SCFSR;
obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
/* ---- Line status register (SCLSR) setting ---- */
/* ORER bit clear */
obj->uart->SCLSR = 0;
/* ---- Serial extension mode register (SCEMR) setting ----
b7 BGDM - Baud rate generator double-speed mode : Normal mode
b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
obj->uart->SCEMR = 0x0000u;
/* ---- Bit rate register (SCBRR) setting ---- */
serial_baud (obj, 9600);
serial_format(obj, 8, ParityNone, 1);
/* ---- FIFO control register (SCFCR) setting ---- */
obj->uart->SCFCR = 0x0030u;
/* ---- Serial port register (SCSPTR) setting ----
b1 SPB2IO - Serial port break output : disabled
b0 SPB2DT - Serial port break data : High-level */
obj->uart->SCSPTR = 0x0003u; // SPB2IO = 1, SPB2DT = 1
/* ---- Line status register (SCLSR) setting ----
b0 ORER - Overrun error detect : clear */
if (obj->uart->SCLSR & 0x0001) {
obj->uart->SCLSR = 0u; // ORER clear
}
// pinout the chosen uart
pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) {
case UART0:
obj->index = 0;
break;
case UART1:
obj->index = 1;
break;
case UART2:
obj->index = 2;
break;
case UART3:
obj->index = 3;
break;
case UART4:
obj->index = 4;
break;
case UART5:
obj->index = 5;
break;
case UART6:
obj->index = 6;
break;
case UART7:
obj->index = 7;
break;
}
uart_data[obj->index].sw_rts.pin = NC;
uart_data[obj->index].sw_cts.pin = NC;
/* ---- Serial control register (SCSCR) setting ---- */
/* Setting the TE and RE bits enables the TxD and RxD pins to be used. */
obj->uart->SCSCR = (((uart_tx != (uint32_t)NC)? 0xA0 : 0) | ((uart_rx != (uint32_t)NC)? 0x50 : 0 )); //0x00F0;
is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
if (is_stdio_uart) {
stdio_uart_inited = 1;
memcpy(&stdio_uart, obj, sizeof(serial_t));
}
}
void serial_free(serial_t *obj) {
uart_data[obj->index].serial_irq_id = 0;
}
// serial_baud
// set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) {
uint16_t DL;
obj->uart->SCSMR &= ~0x0003;
if (baudrate > 32552) {
obj->uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
DL = PCLK / (8 * baudrate);
if (DL > 0) {
DL--;
}
obj->uart->SCBRR = (uint8_t)DL;
} else if (baudrate > 16276) {
obj->uart->SCEMR = 0x0080; // BGDM = 1
obj->uart->SCBRR = PCLK / (16 * baudrate) - 1;
} else if (baudrate > 8138) {
obj->uart->SCEMR = 0x0000;
obj->uart->SCBRR = PCLK / (32 * baudrate) - 1;
} else if (baudrate > 4169) {
obj->uart->SCSMR |= 0x0001;
obj->uart->SCEMR = 0x0080; // BGDM = 1
obj->uart->SCBRR = PCLK / (64 * baudrate) - 1;
} else if (baudrate > 2034) {
obj->uart->SCSMR |= 0x0001;
obj->uart->SCEMR = 0x0000;
obj->uart->SCBRR = PCLK / (128 * baudrate) - 1;
} else if (baudrate > 1017) {
obj->uart->SCSMR |= 0x0002;
obj->uart->SCEMR = 0x0080; // BGDM = 1
obj->uart->SCBRR = PCLK / (256 * baudrate) - 1;
} else if (baudrate > 508) {
obj->uart->SCSMR |= 0x0002;
obj->uart->SCEMR = 0x0000;
obj->uart->SCBRR = PCLK / (512 * baudrate) - 1;
} else if (baudrate > 254) {
obj->uart->SCSMR |= 0x0003;
obj->uart->SCEMR = 0x0080; // BGDM = 1
obj->uart->SCBRR = PCLK / (1024 * baudrate) - 1;
} else if (baudrate > 127) {
obj->uart->SCSMR |= 0x0003;
obj->uart->SCEMR = 0x0000;
obj->uart->SCBRR = PCLK / (2048 * baudrate) - 1;
} else {
obj->uart->SCSMR |= 0x0003;
obj->uart->SCEMR = 0x0000;
obj->uart->SCBRR = 0xFFu;
}
}
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
int parity_enable;
int parity_select;
MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
MBED_ASSERT((data_bits > 4) && (data_bits < 9)); // 5: 5 data bits ... 3: 8 data bits
MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
(parity == ParityForced1) || (parity == ParityForced0));
stop_bits = (stop_bits == 1)? 0:
(stop_bits == 2)? 1:
0; // must not to be
data_bits = (data_bits == 8)? 0:
(data_bits == 7)? 1:
0; // must not to be
switch (parity) {
case ParityNone:
parity_enable = 0;
parity_select = 0;
break;
case ParityOdd:
parity_enable = 1;
parity_select = 1;
break;
case ParityEven:
parity_enable = 1;
parity_select = 0;
break;
case ParityForced1:
case ParityForced0:
default:
parity_enable = 0;
parity_select = 0;
break;
}
obj->uart->SCSMR = data_bits << 6
| parity_enable << 5
| parity_select << 4
| stop_bits << 3;
}
/******************************************************************************
* INTERRUPTS HANDLING
******************************************************************************/
static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
__IO uint16_t *dmy_rd_scscr;
__IO uint16_t *dmy_rd_scfsr;
dmy_rd_scscr = SCSCR_MATCH[index];
*dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
dmy_rd_scfsr = SCFSR_MATCH[index];
*dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE
irq_handler(uart_data[index].serial_irq_id, TxIrq);
}
static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
__IO uint16_t *dmy_rd_scscr;
__IO uint16_t *dmy_rd_scfsr;
dmy_rd_scscr = SCSCR_MATCH[index];
*dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
dmy_rd_scfsr = SCFSR_MATCH[index];
*dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
irq_handler(uart_data[index].serial_irq_id, RxIrq);
}
/* TX handler */
static void uart0_tx_irq(void) {
uart_tx_irq(SCIFTXI0_IRQn, 0);
}
static void uart1_tx_irq(void) {
uart_tx_irq(SCIFTXI1_IRQn, 1);
}
static void uart2_tx_irq(void) {
uart_tx_irq(SCIFTXI2_IRQn, 2);
}
static void uart3_tx_irq(void) {
uart_tx_irq(SCIFTXI3_IRQn, 3);
}
static void uart4_tx_irq(void) {
uart_tx_irq(SCIFTXI4_IRQn, 4);
}
static void uart5_tx_irq(void) {
uart_tx_irq(SCIFTXI5_IRQn, 5);
}
static void uart6_tx_irq(void) {
uart_tx_irq(SCIFTXI6_IRQn, 6);
}
static void uart7_tx_irq(void) {
uart_tx_irq(SCIFTXI7_IRQn, 7);
}
/* RX handler */
static void uart0_rx_irq(void) {
uart_rx_irq(SCIFRXI0_IRQn, 0);
}
static void uart1_rx_irq(void) {
uart_rx_irq(SCIFRXI1_IRQn, 1);
}
static void uart2_rx_irq(void) {
uart_rx_irq(SCIFRXI2_IRQn, 2);
}
static void uart3_rx_irq(void) {
uart_rx_irq(SCIFRXI3_IRQn, 3);
}
static void uart4_rx_irq(void) {
uart_rx_irq(SCIFRXI4_IRQn, 4);
}
static void uart5_rx_irq(void) {
uart_rx_irq(SCIFRXI5_IRQn, 5);
}
static void uart6_rx_irq(void) {
uart_rx_irq(SCIFRXI6_IRQn, 6);
}
static void uart7_rx_irq(void) {
uart_rx_irq(SCIFRXI7_IRQn, 7);
}
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler;
uart_data[obj->index].serial_irq_id = id;
}
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type IRQn;
IRQHandler handler;
IRQn = irq_set_tbl[obj->index][irq];
handler = hander_set_tbl[obj->index][irq];
if ((obj->index >= 0) && (obj->index <= 7)) {
if (enable) {
InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
GIC_SetPriority(IRQn, 5);
GIC_EnableIRQ(IRQn);
} else {
GIC_DisableIRQ(IRQn);
}
}
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
if (RxIrq == irq) {
uart_data[obj->index].rx_irq_set_api = enable;
}
serial_irq_set_internal(obj, irq, enable);
}
static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
uart_data[obj->index].rx_irq_set_flow = enable;
serial_irq_set_internal(obj, RxIrq, enable);
}
/******************************************************************************
* READ/WRITE
******************************************************************************/
int serial_getc(serial_t *obj) {
uint16_t err_read;
int data;
core_util_critical_section_enter();
if (obj->uart->SCFSR & 0x93) {
err_read = obj->uart->SCFSR;
obj->uart->SCFSR = (err_read & ~0x93);
}
obj->uart->SCSCR |= 0x0040; // Set RIE
core_util_critical_section_exit();
if (obj->uart->SCLSR & 0x0001) {
obj->uart->SCLSR = 0u; // ORER clear
}
while (!serial_readable(obj));
data = obj->uart->SCFRDR & 0xff;
core_util_critical_section_enter();
err_read = obj->uart->SCFSR;
obj->uart->SCFSR = (err_read & 0xfffD); // Clear RDF
core_util_critical_section_exit();
if (err_read & 0x80) {
data = -1; //err
}
return data;
}
void serial_putc(serial_t *obj, int c) {
uint16_t dummy_read;
core_util_critical_section_enter();
obj->uart->SCSCR |= 0x0080; // Set TIE
core_util_critical_section_exit();
while (!serial_writable(obj));
obj->uart->SCFTDR = c;
core_util_critical_section_enter();
dummy_read = obj->uart->SCFSR;
obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
core_util_critical_section_exit();
uart_data[obj->index].count++;
}
int serial_readable(serial_t *obj) {
return ((obj->uart->SCFSR & 0x02) != 0); // RDF
}
int serial_writable(serial_t *obj) {
return ((obj->uart->SCFSR & 0x20) != 0); // TDFE
}
void serial_clear(serial_t *obj) {
core_util_critical_section_enter();
obj->uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1
obj->uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0
obj->uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
core_util_critical_section_exit();
}
void serial_pinout_tx(PinName tx) {
pinmap_pinout(tx, PinMap_UART_TX);
}
void serial_break_set(serial_t *obj) {
core_util_critical_section_enter();
// TxD Output(L)
obj->uart->SCSPTR &= ~0x0001u; // SPB2DT = 0
obj->uart->SCSCR &= ~0x0020u; // TE = 0 (Output disable)
core_util_critical_section_exit();
}
void serial_break_clear(serial_t *obj) {
core_util_critical_section_enter();
obj->uart->SCSCR |= 0x0020u; // TE = 1 (Output enable)
obj->uart->SCSPTR |= 0x0001u; // SPB2DT = 1
core_util_critical_section_exit();
}
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
// determine the UART to use
serial_flow_irq_set(obj, 0);
if (type == FlowControlRTSCTS) {
core_util_critical_section_enter();
obj->uart->SCFCR = 0x0008u; // CTS/RTS enable
core_util_critical_section_exit();
pinmap_pinout(rxflow, PinMap_UART_RTS);
pinmap_pinout(txflow, PinMap_UART_CTS);
} else {
core_util_critical_section_enter();
obj->uart->SCFCR = 0x0000u; // CTS/RTS diable
core_util_critical_section_exit();
}
}

343
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/spi_api.c
View File

@ -1,343 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "mbed_assert.h"
#include <math.h>
#include "spi_api.h"
#include "cmsis.h"
#include "pinmap.h"
#include "mbed_error.h"
#include "RZ_A1_Init.h"
#ifdef MAX_PERI
static const PinMap PinMap_SPI_SCLK[] = {
{P2_12 , SPI_0, 2},
{P7_15 , SPI_0, 2},
{P4_4 , SPI_1, 2},
{P6_4 , SPI_1, 7},
{P8_3 , SPI_2, 3},
{P8_14 , SPI_2, 5},
{P3_0 , SPI_3, 8},
{P5_0 , SPI_3, 8},
{P2_8 , SPI_4, 8},
{P4_0 , SPI_4, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{P2_13 , SPI_0, 2},
{P8_0 , SPI_0, 2},
{P4_5 , SPI_1, 2},
{P6_5 , SPI_1, 7},
{P8_4 , SPI_2, 3},
{P8_15 , SPI_2, 5},
{P3_1 , SPI_3, 8},
{P5_1 , SPI_3, 8},
{P2_9 , SPI_4, 8},
{P4_1 , SPI_4, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{P2_14 , SPI_0, 2},
{P8_1 , SPI_0, 2},
{P4_6 , SPI_1, 2},
{P6_6 , SPI_1, 7},
{P8_5 , SPI_2, 3},
{P9_0 , SPI_2, 5},
{P3_2 , SPI_3, 8},
{P5_2 , SPI_3, 8},
{P2_10 , SPI_4, 8},
{P4_2 , SPI_4, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{P2_15 , SPI_0, 2},
{P8_2 , SPI_0, 2},
{P4_7 , SPI_1, 2},
{P6_7 , SPI_1, 7},
{P8_6 , SPI_2, 3},
{P9_1 , SPI_2, 5},
{P3_3 , SPI_3, 8},
{P5_3 , SPI_3, 8},
{P2_11 , SPI_4, 8},
{P4_3 , SPI_4, 7},
{NC , NC , 0}
};
#else
static const PinMap PinMap_SPI_SCLK[] = {
{P4_4 , SPI_1, 2},
{P8_14 , SPI_2, 5},
{P5_0 , SPI_3, 8},
{P4_0 , SPI_4, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{P4_5 , SPI_1, 2},
{P8_15 , SPI_2, 5},
{P5_1 , SPI_3, 8},
{P4_1 , SPI_4, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{P4_6 , SPI_1, 2},
{P9_0 , SPI_2, 5},
{P5_2 , SPI_3, 8},
{P4_2 , SPI_4, 7},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{P4_7 , SPI_1, 2},
{P9_1 , SPI_2, 5},
{P5_3 , SPI_3, 8},
{P4_3 , SPI_4, 7},
{NC , NC , 0}
};
#endif
static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
static inline void spi_disable(spi_t *obj);
static inline void spi_enable(spi_t *obj);
static inline int spi_readable(spi_t *obj);
static inline void spi_write(spi_t *obj, int value);
static inline int spi_read(spi_t *obj);
void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
// determine the SPI to use
volatile uint8_t dummy;
uint32_t spi_mosi = pinmap_peripheral(mosi, PinMap_SPI_MOSI);
uint32_t spi_miso = pinmap_peripheral(miso, PinMap_SPI_MISO);
uint32_t spi_sclk = pinmap_peripheral(sclk, PinMap_SPI_SCLK);
uint32_t spi_ssel = pinmap_peripheral(ssel, PinMap_SPI_SSEL);
uint32_t spi_data = pinmap_merge(spi_mosi, spi_miso);
uint32_t spi_cntl = pinmap_merge(spi_sclk, spi_ssel);
uint32_t spi = pinmap_merge(spi_data, spi_cntl);
MBED_ASSERT((int)spi != NC);
obj->spi = (struct st_rspi *)RSPI[spi];
// enable power and clocking
switch (spi) {
case SPI_1: CPGSTBCR10 &= ~(0x40); break;
case SPI_2: CPGSTBCR10 &= ~(0x20); break;
case SPI_3: CPGSTBCR10 &= ~(0x10); break;
case SPI_4: CPGSTBCR10 &= ~(0x08); break;
}
dummy = CPGSTBCR10;
obj->spi->SPCR = 0x00; // CTRL to 0
obj->spi->SPSCR = 0x00; // no sequential operation
obj->spi->SSLP = 0x00; // SSL 'L' active
obj->spi->SPDCR = 0x20; // byte access
obj->spi->SPCKD = 0x00; // SSL -> enable CLK delay : 1RSPCK
obj->spi->SSLND = 0x00; // CLK end -> SSL neg delay : 1RSPCK
obj->spi->SPND = 0x00; // delay between CMD : 1RSPCK + 2P1CLK
obj->spi->SPPCR = 0x20; // MOSI Idle fixed value equals 0
obj->spi->SPBFCR = 0xf0; // and set trigger count: read 1, write 1
obj->spi->SPBFCR = 0x30; // and reset buffer
// pin out the spi pins
pinmap_pinout(mosi, PinMap_SPI_MOSI);
pinmap_pinout(miso, PinMap_SPI_MISO);
pinmap_pinout(sclk, PinMap_SPI_SCLK);
if ((int)ssel != NC) {
pinmap_pinout(ssel, PinMap_SPI_SSEL);
}
}
void spi_free(spi_t *obj) {}
void spi_format(spi_t *obj, int bits, int mode, int slave) {
int DSS; // DSS (data select size)
int polarity = (mode & 0x2) ? 1 : 0;
int phase = (mode & 0x1) ? 1 : 0;
uint16_t tmp = 0;
uint16_t mask = 0xf03;
uint16_t wk_spcmd0;
uint8_t splw;
switch (mode) {
case 0:
case 1:
case 2:
case 3:
// Do Nothing
break;
default:
error("SPI format error");
return;
}
switch (bits) {
case 8:
DSS = 0x7;
splw = 0x20;
break;
case 16:
DSS = 0xf;
splw = 0x40;
break;
case 32:
DSS = 0x2;
splw = 0x60;
break;
default:
error("SPI module don't support other than 8/16/32bits");
return;
}
tmp |= phase;
tmp |= (polarity << 1);
tmp |= (DSS << 8);
obj->bits = bits;
spi_disable(obj);
wk_spcmd0 = obj->spi->SPCMD0;
wk_spcmd0 &= ~mask;
wk_spcmd0 |= (mask & tmp);
obj->spi->SPCMD0 = wk_spcmd0;
obj->spi->SPDCR = splw;
if (slave) {
obj->spi->SPCR &=~(1 << 3); // MSTR to 0
} else {
obj->spi->SPCR |= (1 << 3); // MSTR to 1
}
spi_enable(obj);
}
void spi_frequency(spi_t *obj, int hz) {
uint32_t pclk_base;
uint32_t div;
uint32_t brdv = 0;
uint32_t hz_max;
uint32_t hz_min;
uint16_t mask = 0x000c;
uint16_t wk_spcmd0;
/* set PCLK */
if (RZ_A1_IsClockMode0() == false) {
pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
} else {
pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
}
hz_min = pclk_base / 2 / 256 / 8;
hz_max = pclk_base / 2;
if ((hz < hz_min) || (hz > hz_max)) {
error("Couldn't setup requested SPI frequency");
return;
}
div = (pclk_base / hz / 2);
while (div > 256) {
div >>= 1;
brdv++;
}
div -= 1;
brdv = (brdv << 2);
spi_disable(obj);
obj->spi->SPBR = div;
wk_spcmd0 = obj->spi->SPCMD0;
wk_spcmd0 &= ~mask;
wk_spcmd0 |= (mask & brdv);
obj->spi->SPCMD0 = wk_spcmd0;
spi_enable(obj);
}
static inline void spi_disable(spi_t *obj) {
obj->spi->SPCR &= ~(1 << 6); // SPE to 0
}
static inline void spi_enable(spi_t *obj) {
obj->spi->SPCR |= (1 << 6); // SPE to 1
}
static inline int spi_readable(spi_t *obj) {
return obj->spi->SPSR & (1 << 7); // SPRF
}
static inline int spi_tend(spi_t *obj) {
return obj->spi->SPSR & (1 << 6); // TEND
}
static inline void spi_write(spi_t *obj, int value) {
if (obj->bits == 8) {
obj->spi->SPDR.UINT8[0] = (uint8_t)value;
} else if (obj->bits == 16) {
obj->spi->SPDR.UINT16[0] = (uint16_t)value;
} else {
obj->spi->SPDR.UINT32 = (uint32_t)value;
}
}
static inline int spi_read(spi_t *obj) {
int read_data;
if (obj->bits == 8) {
read_data = obj->spi->SPDR.UINT8[0];
} else if (obj->bits == 16) {
read_data = obj->spi->SPDR.UINT16[0];
} else {
read_data = obj->spi->SPDR.UINT32;
}
return read_data;
}
int spi_master_write(spi_t *obj, int value) {
spi_write(obj, value);
while(!spi_tend(obj));
return spi_read(obj);
}
int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
char *rx_buffer, int rx_length, char write_fill) {
int total = (tx_length > rx_length) ? tx_length : rx_length;
for (int i = 0; i < total; i++) {
char out = (i < tx_length) ? tx_buffer[i] : write_fill;
char in = spi_master_write(obj, out);
if (i < rx_length) {
rx_buffer[i] = in;
}
}
return total;
}
int spi_slave_receive(spi_t *obj) {
return (spi_readable(obj) && !spi_busy(obj)) ? (1) : (0);
}
int spi_slave_read(spi_t *obj) {
return spi_read(obj);
}
void spi_slave_write(spi_t *obj, int value) {
spi_write(obj, value);
}
int spi_busy(spi_t *obj) {
return 0;
}

136
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/us_ticker.c
View File

@ -1,136 +0,0 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include <stddef.h>
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "ostm_iodefine.h"
#include "RZ_A1_Init.h"
#include "VKRZA1H.h"
#include "mbed_critical.h"
#define US_TICKER_TIMER_IRQn (OSTMI1TINT_IRQn)
#define CPG_STBCR5_BIT_MSTP50 (0x01u) /* OSTM1 */
#define US_TICKER_CLOCK_US_DEV (1000000)
int us_ticker_inited = 0;
static double count_clock = 0;
static uint32_t last_read = 0;
static uint32_t wrap_arround = 0;
static uint64_t ticker_us_last64 = 0;
void us_ticker_interrupt(void) {
us_ticker_irq_handler();
}
void us_ticker_init(void) {
if (us_ticker_inited) return;
us_ticker_inited = 1;
/* set Counter Clock(us) */
if (false == RZ_A1_IsClockMode0()) {
count_clock = ((double)CM1_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
} else {
count_clock = ((double)CM0_RENESAS_RZ_A1_P0_CLK / (double)US_TICKER_CLOCK_US_DEV);
}
/* Power Control for Peripherals */
CPGSTBCR5 &= ~(CPG_STBCR5_BIT_MSTP50); /* enable OSTM1 clock */
// timer settings
OSTM1TT = 0x01; /* Stop the counter and clears the OSTM1TE bit. */
OSTM1CTL = 0x02; /* Free running timer mode. Interrupt disabled when star counter */
OSTM1TS = 0x1; /* Start the counter and sets the OSTM0TE bit. */
// INTC settings
InterruptHandlerRegister(US_TICKER_TIMER_IRQn, (void (*)(uint32_t))us_ticker_interrupt);
GIC_SetPriority(US_TICKER_TIMER_IRQn, 5);
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
static uint64_t ticker_read_counter64(void) {
uint32_t cnt_val;
uint64_t cnt_val64;
if (!us_ticker_inited)
us_ticker_init();
/* read counter */
cnt_val = OSTM1CNT;
if (last_read > cnt_val) {
wrap_arround++;
}
last_read = cnt_val;
cnt_val64 = ((uint64_t)wrap_arround << 32) + cnt_val;
return cnt_val64;
}
uint32_t us_ticker_read() {
uint64_t cnt_val64;
uint64_t us_val64;
core_util_critical_section_enter();
cnt_val64 = ticker_read_counter64();
us_val64 = (cnt_val64 / count_clock);
ticker_us_last64 = us_val64;
core_util_critical_section_exit();
/* clock to us */
return (uint32_t)us_val64;
}
void us_ticker_set_interrupt(timestamp_t timestamp) {
// set match value
uint64_t timestamp64;
uint64_t set_cmp_val64;
volatile uint32_t set_cmp_val;
uint64_t count_val_64;
/* calc compare mach timestamp */
timestamp64 = (ticker_us_last64 & 0xFFFFFFFF00000000) + timestamp;
if (timestamp < (ticker_us_last64 & 0x00000000FFFFFFFF)) {
/* This event is wrap arround */
timestamp64 += 0x100000000;
}
/* calc compare mach timestamp */
set_cmp_val64 = timestamp64 * count_clock;
set_cmp_val = (uint32_t)(set_cmp_val64 & 0x00000000FFFFFFFF);
count_val_64 = ticker_read_counter64();
if (set_cmp_val64 <= (count_val_64 + 500)) {
GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
return;
}
OSTM1CMP = set_cmp_val;
GIC_EnableIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_fire_interrupt(void) {
GIC_SetPendingIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_disable_interrupt(void) {
GIC_DisableIRQ(US_TICKER_TIMER_IRQn);
}
void us_ticker_clear_interrupt(void) {
GIC_ClearPendingIRQ(US_TICKER_TIMER_IRQn);
}

17
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/analogin_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/analogin_api.c
View File

@ -17,25 +17,12 @@
#include "analogin_api.h" #include "analogin_api.h"
#include "cmsis.h" #include "cmsis.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "adc_iodefine.h" #include "iodefine.h"
#include "cpg_iodefine.h"
#define ANALOGIN_MEDIAN_FILTER 0 #define ANALOGIN_MEDIAN_FILTER 0
static const PinMap PinMap_ADC[] = {
{P1_8, AN0, 1},
{P1_9, AN1, 1},
{P1_10, AN2, 1},
{P1_11, AN3, 1},
{P1_12, AN4, 1},
{P1_13, AN5, 1},
{P1_14, AN6, 1},
{P1_15, AN7, 1},
{NC, NC, 0}
};
static volatile uint16_t *ADCDR[] = { static volatile uint16_t *ADCDR[] = {
&ADCADDRA, &ADCADDRA,
&ADCADDRB, &ADCADDRB,

349
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/can_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/can_api.c
View File

@ -18,12 +18,16 @@
#include "can_api.h" #include "can_api.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "cmsis.h" #include "cmsis.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "rscan0_iodefine.h" #include "iodefine.h"
#include "r_typedefs.h" #include "r_typedefs.h"
#include "MBRZA1H.h" #include "mbed_drv_cfg.h"
#if defined(TARGET_RZA1H)
#define CAN_NUM 5 #define CAN_NUM 5
#else
#define CAN_NUM 2
#endif
#define CAN_SND_RCV 2 #define CAN_SND_RCV 2
#define IRQ_NUM 8 #define IRQ_NUM 8
@ -31,40 +35,43 @@ static void can_rec_irq(uint32_t ch);
static void can_trx_irq(uint32_t ch); static void can_trx_irq(uint32_t ch);
static void can_err_irq(uint32_t ch, CanIrqType type); static void can_err_irq(uint32_t ch, CanIrqType type);
static void can0_rec_irq(void); static void can0_rec_irq(void);
static void can1_rec_irq(void);
static void can2_rec_irq(void);
static void can3_rec_irq(void);
static void can4_rec_irq(void);
static void can0_trx_irq(void); static void can0_trx_irq(void);
static void can1_trx_irq(void);
static void can2_trx_irq(void);
static void can3_trx_irq(void);
static void can4_trx_irq(void);
static void can0_err_warning_irq(void); static void can0_err_warning_irq(void);
static void can1_err_warning_irq(void);
static void can2_err_warning_irq(void);
static void can3_err_warning_irq(void);
static void can4_err_warning_irq(void);
static void can0_overrun_irq(void); static void can0_overrun_irq(void);
static void can1_overrun_irq(void);
static void can2_overrun_irq(void);
static void can3_overrun_irq(void);
static void can4_overrun_irq(void);
static void can0_passive_irq(void); static void can0_passive_irq(void);
static void can1_passive_irq(void);
static void can2_passive_irq(void);
static void can3_passive_irq(void);
static void can4_passive_irq(void);
static void can0_arb_lost_irq(void); static void can0_arb_lost_irq(void);
static void can1_arb_lost_irq(void);
static void can2_arb_lost_irq(void);
static void can3_arb_lost_irq(void);
static void can4_arb_lost_irq(void);
static void can0_bus_err_irq(void); static void can0_bus_err_irq(void);
static void can1_rec_irq(void);
static void can1_trx_irq(void);
static void can1_err_warning_irq(void);
static void can1_overrun_irq(void);
static void can1_passive_irq(void);
static void can1_arb_lost_irq(void);
static void can1_bus_err_irq(void); static void can1_bus_err_irq(void);
#if defined(TARGET_RZA1H)
static void can2_rec_irq(void);
static void can2_trx_irq(void);
static void can2_err_warning_irq(void);
static void can2_overrun_irq(void);
static void can2_passive_irq(void);
static void can2_arb_lost_irq(void);
static void can2_bus_err_irq(void); static void can2_bus_err_irq(void);
static void can3_rec_irq(void);
static void can3_trx_irq(void);
static void can3_err_warning_irq(void);
static void can3_overrun_irq(void);
static void can3_passive_irq(void);
static void can3_arb_lost_irq(void);
static void can3_bus_err_irq(void); static void can3_bus_err_irq(void);
static void can4_rec_irq(void);
static void can4_trx_irq(void);
static void can4_err_warning_irq(void);
static void can4_overrun_irq(void);
static void can4_passive_irq(void);
static void can4_arb_lost_irq(void);
static void can4_bus_err_irq(void); static void can4_bus_err_irq(void);
#endif
static void can_reset_reg(can_t *obj); static void can_reset_reg(can_t *obj);
static void can_reset_recv_rule(can_t *obj); static void can_reset_recv_rule(can_t *obj);
static void can_reset_buffer(can_t *obj); static void can_reset_buffer(can_t *obj);
@ -99,53 +106,25 @@ static can_irq_handler irq_handler;
static uint32_t can_irq_id[CAN_NUM]; static uint32_t can_irq_id[CAN_NUM];
static int can_initialized[CAN_NUM] = {0}; static int can_initialized[CAN_NUM] = {0};
static const PinMap PinMap_CAN_RD[] = {
{P7_8 , CAN_0, 4},
{P9_1 , CAN_0, 3},
{P1_4 , CAN_1, 3},
{P5_9 , CAN_1, 5},
{P7_11 , CAN_1, 4},
{P11_12, CAN_1, 1},
{P4_9 , CAN_2, 6},
{P6_4 , CAN_2, 3},
{P7_2 , CAN_2, 5},
{P2_12 , CAN_3, 5},
{P4_2 , CAN_3, 4},
{P1_5 , CAN_4, 3},
{P2_14 , CAN_4, 5},
{NC , NC , 0}
};
static const PinMap PinMap_CAN_TD[] = {
{P7_9 , CAN_0, 4},
{P9_0 , CAN_0, 3},
{P5_10 , CAN_1, 5},
{P7_10 , CAN_1, 4},
{P11_13, CAN_1, 1},
{P4_8 , CAN_2, 6},
{P6_5 , CAN_2, 3},
{P7_3 , CAN_2, 5},
{P2_13 , CAN_3, 5},
{P4_3 , CAN_3, 4},
{P4_11 , CAN_4, 6},
{P8_10 , CAN_4, 5},
{NC , NC , 0}
};
static __IO uint32_t *CTR_MATCH[] = { static __IO uint32_t *CTR_MATCH[] = {
&RSCAN0C0CTR, &RSCAN0C0CTR,
&RSCAN0C1CTR, &RSCAN0C1CTR,
#if defined(TARGET_RZA1H)
&RSCAN0C2CTR, &RSCAN0C2CTR,
&RSCAN0C3CTR, &RSCAN0C3CTR,
&RSCAN0C4CTR, &RSCAN0C4CTR,
#endif
}; };
static __IO uint32_t *CFG_MATCH[] = { static __IO uint32_t *CFG_MATCH[] = {
&RSCAN0C0CFG, &RSCAN0C0CFG,
&RSCAN0C1CFG, &RSCAN0C1CFG,
#if defined(TARGET_RZA1H)
&RSCAN0C2CFG, &RSCAN0C2CFG,
&RSCAN0C3CFG, &RSCAN0C3CFG,
&RSCAN0C4CFG, &RSCAN0C4CFG,
#endif
}; };
static __IO uint32_t *RFCC_MATCH[] = { static __IO uint32_t *RFCC_MATCH[] = {
@ -162,89 +141,111 @@ static __IO uint32_t *RFCC_MATCH[] = {
static __IO uint32_t *TXQCC_MATCH[] = { static __IO uint32_t *TXQCC_MATCH[] = {
&RSCAN0TXQCC0, &RSCAN0TXQCC0,
&RSCAN0TXQCC1, &RSCAN0TXQCC1,
#if defined(TARGET_RZA1H)
&RSCAN0TXQCC2, &RSCAN0TXQCC2,
&RSCAN0TXQCC3, &RSCAN0TXQCC3,
&RSCAN0TXQCC4, &RSCAN0TXQCC4,
#endif
}; };
static __IO uint32_t *THLCC_MATCH[] = { static __IO uint32_t *THLCC_MATCH[] = {
&RSCAN0THLCC0, &RSCAN0THLCC0,
&RSCAN0THLCC1, &RSCAN0THLCC1,
#if defined(TARGET_RZA1H)
&RSCAN0THLCC2, &RSCAN0THLCC2,
&RSCAN0THLCC3, &RSCAN0THLCC3,
&RSCAN0THLCC4, &RSCAN0THLCC4,
#endif
}; };
static __IO uint32_t *STS_MATCH[] = { static __IO uint32_t *STS_MATCH[] = {
&RSCAN0C0STS, &RSCAN0C0STS,
&RSCAN0C1STS, &RSCAN0C1STS,
#if defined(TARGET_RZA1H)
&RSCAN0C2STS, &RSCAN0C2STS,
&RSCAN0C3STS, &RSCAN0C3STS,
&RSCAN0C4STS, &RSCAN0C4STS,
#endif
}; };
static __IO uint32_t *ERFL_MATCH[] = { static __IO uint32_t *ERFL_MATCH[] = {
&RSCAN0C0ERFL, &RSCAN0C0ERFL,
&RSCAN0C1ERFL, &RSCAN0C1ERFL,
#if defined(TARGET_RZA1H)
&RSCAN0C2ERFL, &RSCAN0C2ERFL,
&RSCAN0C3ERFL, &RSCAN0C3ERFL,
&RSCAN0C4ERFL, &RSCAN0C4ERFL,
#endif
}; };
static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFCC_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFCC0 , &RSCAN0CFCC1 }, { &RSCAN0CFCC0 , &RSCAN0CFCC1 },
{ &RSCAN0CFCC3 , &RSCAN0CFCC4 }, { &RSCAN0CFCC3 , &RSCAN0CFCC4 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFCC6 , &RSCAN0CFCC7 }, { &RSCAN0CFCC6 , &RSCAN0CFCC7 },
{ &RSCAN0CFCC9 , &RSCAN0CFCC10 }, { &RSCAN0CFCC9 , &RSCAN0CFCC10 },
{ &RSCAN0CFCC12, &RSCAN0CFCC13 } { &RSCAN0CFCC12, &RSCAN0CFCC13 },
#endif
}; };
static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFSTS_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFSTS0 , &RSCAN0CFSTS1 }, { &RSCAN0CFSTS0 , &RSCAN0CFSTS1 },
{ &RSCAN0CFSTS3 , &RSCAN0CFSTS4 }, { &RSCAN0CFSTS3 , &RSCAN0CFSTS4 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFSTS6 , &RSCAN0CFSTS7 }, { &RSCAN0CFSTS6 , &RSCAN0CFSTS7 },
{ &RSCAN0CFSTS9 , &RSCAN0CFSTS10 }, { &RSCAN0CFSTS9 , &RSCAN0CFSTS10 },
{ &RSCAN0CFSTS12, &RSCAN0CFSTS13 } { &RSCAN0CFSTS12, &RSCAN0CFSTS13 },
#endif
}; };
static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFPCTR_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 }, { &RSCAN0CFPCTR0 , &RSCAN0CFPCTR1 },
{ &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 }, { &RSCAN0CFPCTR3 , &RSCAN0CFPCTR4 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 }, { &RSCAN0CFPCTR6 , &RSCAN0CFPCTR7 },
{ &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 }, { &RSCAN0CFPCTR9 , &RSCAN0CFPCTR10 },
{ &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 } { &RSCAN0CFPCTR12, &RSCAN0CFPCTR13 },
#endif
}; };
static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFID_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFID0 , &RSCAN0CFID1 }, { &RSCAN0CFID0 , &RSCAN0CFID1 },
{ &RSCAN0CFID3 , &RSCAN0CFID4 }, { &RSCAN0CFID3 , &RSCAN0CFID4 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFID6 , &RSCAN0CFID7 }, { &RSCAN0CFID6 , &RSCAN0CFID7 },
{ &RSCAN0CFID9 , &RSCAN0CFID10 }, { &RSCAN0CFID9 , &RSCAN0CFID10 },
{ &RSCAN0CFID12, &RSCAN0CFID13 } { &RSCAN0CFID12, &RSCAN0CFID13 },
#endif
}; };
static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFPTR_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFPTR0 , &RSCAN0CFPTR1 }, { &RSCAN0CFPTR0 , &RSCAN0CFPTR1 },
{ &RSCAN0CFPTR3 , &RSCAN0CFPTR4 }, { &RSCAN0CFPTR3 , &RSCAN0CFPTR4 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFPTR6 , &RSCAN0CFPTR7 }, { &RSCAN0CFPTR6 , &RSCAN0CFPTR7 },
{ &RSCAN0CFPTR9 , &RSCAN0CFPTR10 }, { &RSCAN0CFPTR9 , &RSCAN0CFPTR10 },
{ &RSCAN0CFPTR12, &RSCAN0CFPTR13 } { &RSCAN0CFPTR12, &RSCAN0CFPTR13 }
#endif
}; };
static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFDF0_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFDF00 , &RSCAN0CFDF01 }, { &RSCAN0CFDF00 , &RSCAN0CFDF01 },
{ &RSCAN0CFDF03 , &RSCAN0CFDF04 }, { &RSCAN0CFDF03 , &RSCAN0CFDF04 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFDF06 , &RSCAN0CFDF07 }, { &RSCAN0CFDF06 , &RSCAN0CFDF07 },
{ &RSCAN0CFDF09 , &RSCAN0CFDF010 }, { &RSCAN0CFDF09 , &RSCAN0CFDF010 },
{ &RSCAN0CFDF012, &RSCAN0CFDF013 } { &RSCAN0CFDF012, &RSCAN0CFDF013 },
#endif
}; };
static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = { static __IO uint32_t *CFDF1_TBL[CAN_NUM][CAN_SND_RCV] = {
{ &RSCAN0CFDF10 , &RSCAN0CFDF11 }, { &RSCAN0CFDF10 , &RSCAN0CFDF11 },
{ &RSCAN0CFDF13 , &RSCAN0CFDF14 }, { &RSCAN0CFDF13 , &RSCAN0CFDF14 },
#if defined(TARGET_RZA1H)
{ &RSCAN0CFDF16 , &RSCAN0CFDF17 }, { &RSCAN0CFDF16 , &RSCAN0CFDF17 },
{ &RSCAN0CFDF19 , &RSCAN0CFDF110 }, { &RSCAN0CFDF19 , &RSCAN0CFDF110 },
{ &RSCAN0CFDF112, &RSCAN0CFDF113 } { &RSCAN0CFDF112, &RSCAN0CFDF113 },
#endif
}; };
static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] = static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
@ -269,6 +270,7 @@ static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
{ INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */ { INTRCAN1ERR_IRQn, can1_arb_lost_irq }, /* AlIrq */
{ INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */ { INTRCAN1ERR_IRQn, can1_bus_err_irq } /* BeIrq */
}, },
#if defined(TARGET_RZA1H)
{ /* ch2 */ { /* ch2 */
{ INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */ { INTRCAN2REC_IRQn, can2_rec_irq }, /* RxIrq */
{ INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */ { INTRCAN2TRX_IRQn, can2_trx_irq }, /* TxIrq */
@ -298,7 +300,8 @@ static const can_info_int_t can_int_info[CAN_NUM][IRQ_NUM] =
{ INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */ { INTRCAN4ERR_IRQn, can4_passive_irq }, /* EpIrq */
{ INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */ { INTRCAN4ERR_IRQn, can4_arb_lost_irq }, /* AlIrq */
{ INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */ { INTRCAN4ERR_IRQn, can4_bus_err_irq } /* BeIrq */
} },
#endif
}; };
static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0; static __IO uint32_t *dmy_gaflid = &RSCAN0GAFLID0;
@ -404,141 +407,143 @@ static void can0_rec_irq(void) {
can_rec_irq(CAN_0); can_rec_irq(CAN_0);
} }
static void can1_rec_irq(void) {
can_rec_irq(CAN_1);
}
static void can2_rec_irq(void) {
can_rec_irq(CAN_2);
}
static void can3_rec_irq(void) {
can_rec_irq(CAN_3);
}
static void can4_rec_irq(void) {
can_rec_irq(CAN_4);
}
static void can0_trx_irq(void) { static void can0_trx_irq(void) {
can_trx_irq(CAN_0); can_trx_irq(CAN_0);
} }
static void can1_trx_irq(void) {
can_trx_irq(CAN_1);
}
static void can2_trx_irq(void) {
can_trx_irq(CAN_2);
}
static void can3_trx_irq(void) {
can_trx_irq(CAN_3);
}
static void can4_trx_irq(void) {
can_trx_irq(CAN_4);
}
static void can0_err_warning_irq(void) { static void can0_err_warning_irq(void) {
can_err_irq(CAN_0, IRQ_ERROR); can_err_irq(CAN_0, IRQ_ERROR);
} }
static void can1_err_warning_irq(void) {
can_err_irq(CAN_1, IRQ_ERROR);
}
static void can2_err_warning_irq(void) {
can_err_irq(CAN_2, IRQ_ERROR);
}
static void can3_err_warning_irq(void) {
can_err_irq(CAN_3, IRQ_ERROR);
}
static void can4_err_warning_irq(void) {
can_err_irq(CAN_4, IRQ_ERROR);
}
static void can0_overrun_irq(void) { static void can0_overrun_irq(void) {
can_err_irq(CAN_0, IRQ_OVERRUN); can_err_irq(CAN_0, IRQ_OVERRUN);
} }
static void can1_overrun_irq(void) {
can_err_irq(CAN_1, IRQ_OVERRUN);
}
static void can2_overrun_irq(void) {
can_err_irq(CAN_2, IRQ_OVERRUN);
}
static void can3_overrun_irq(void) {
can_err_irq(CAN_3, IRQ_OVERRUN);
}
static void can4_overrun_irq(void) {
can_err_irq(CAN_4, IRQ_OVERRUN);
}
static void can0_passive_irq(void) { static void can0_passive_irq(void) {
can_err_irq(CAN_0, IRQ_PASSIVE); can_err_irq(CAN_0, IRQ_PASSIVE);
} }
static void can1_passive_irq(void) {
can_err_irq(CAN_1, IRQ_PASSIVE);
}
static void can2_passive_irq(void) {
can_err_irq(CAN_2, IRQ_PASSIVE);
}
static void can3_passive_irq(void) {
can_err_irq(CAN_3, IRQ_PASSIVE);
}
static void can4_passive_irq(void) {
can_err_irq(CAN_4, IRQ_PASSIVE);
}
static void can0_arb_lost_irq(void) { static void can0_arb_lost_irq(void) {
can_err_irq(CAN_0, IRQ_ARB); can_err_irq(CAN_0, IRQ_ARB);
} }
static void can1_arb_lost_irq(void) {
can_err_irq(CAN_1, IRQ_ARB);
}
static void can2_arb_lost_irq(void) {
can_err_irq(CAN_2, IRQ_ARB);
}
static void can3_arb_lost_irq(void) {
can_err_irq(CAN_3, IRQ_ARB);
}
static void can4_arb_lost_irq(void) {
can_err_irq(CAN_4, IRQ_ARB);
}
static void can0_bus_err_irq(void) { static void can0_bus_err_irq(void) {
can_err_irq(CAN_0, IRQ_BUS); can_err_irq(CAN_0, IRQ_BUS);
} }
static void can1_rec_irq(void) {
can_rec_irq(CAN_1);
}
static void can1_trx_irq(void) {
can_trx_irq(CAN_1);
}
static void can1_err_warning_irq(void) {
can_err_irq(CAN_1, IRQ_ERROR);
}
static void can1_overrun_irq(void) {
can_err_irq(CAN_1, IRQ_OVERRUN);
}
static void can1_passive_irq(void) {
can_err_irq(CAN_1, IRQ_PASSIVE);
}
static void can1_arb_lost_irq(void) {
can_err_irq(CAN_1, IRQ_ARB);
}
static void can1_bus_err_irq(void) { static void can1_bus_err_irq(void) {
can_err_irq(CAN_1, IRQ_BUS); can_err_irq(CAN_1, IRQ_BUS);
} }
#if defined(TARGET_RZA1H)
static void can2_rec_irq(void) {
can_rec_irq(CAN_2);
}
static void can2_trx_irq(void) {
can_trx_irq(CAN_2);
}
static void can2_err_warning_irq(void) {
can_err_irq(CAN_2, IRQ_ERROR);
}
static void can2_overrun_irq(void) {
can_err_irq(CAN_2, IRQ_OVERRUN);
}
static void can2_passive_irq(void) {
can_err_irq(CAN_2, IRQ_PASSIVE);
}
static void can2_arb_lost_irq(void) {
can_err_irq(CAN_2, IRQ_ARB);
}
static void can2_bus_err_irq(void) { static void can2_bus_err_irq(void) {
can_err_irq(CAN_2, IRQ_BUS); can_err_irq(CAN_2, IRQ_BUS);
} }
static void can3_rec_irq(void) {
can_rec_irq(CAN_3);
}
static void can3_trx_irq(void) {
can_trx_irq(CAN_3);
}
static void can3_err_warning_irq(void) {
can_err_irq(CAN_3, IRQ_ERROR);
}
static void can3_overrun_irq(void) {
can_err_irq(CAN_3, IRQ_OVERRUN);
}
static void can3_passive_irq(void) {
can_err_irq(CAN_3, IRQ_PASSIVE);
}
static void can3_arb_lost_irq(void) {
can_err_irq(CAN_3, IRQ_ARB);
}
static void can3_bus_err_irq(void) { static void can3_bus_err_irq(void) {
can_err_irq(CAN_3, IRQ_BUS); can_err_irq(CAN_3, IRQ_BUS);
} }
static void can4_rec_irq(void) {
can_rec_irq(CAN_4);
}
static void can4_trx_irq(void) {
can_trx_irq(CAN_4);
}
static void can4_err_warning_irq(void) {
can_err_irq(CAN_4, IRQ_ERROR);
}
static void can4_overrun_irq(void) {
can_err_irq(CAN_4, IRQ_OVERRUN);
}
static void can4_passive_irq(void) {
can_err_irq(CAN_4, IRQ_PASSIVE);
}
static void can4_arb_lost_irq(void) {
can_err_irq(CAN_4, IRQ_ARB);
}
static void can4_bus_err_irq(void) { static void can4_bus_err_irq(void) {
can_err_irq(CAN_4, IRQ_BUS); can_err_irq(CAN_4, IRQ_BUS);
} }
#endif
void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) { void can_init_freq(can_t *obj, PinName rd, PinName td, int hz) {
__IO uint32_t *dmy_ctr; __IO uint32_t *dmy_ctr;
@ -763,9 +768,9 @@ int can_mode(can_t *obj, CanMode mode) {
can_set_channel_mode(obj->ch, CH_COMM); can_set_channel_mode(obj->ch, CH_COMM);
break; break;
case MODE_TEST_GLOBAL: case MODE_TEST_GLOBAL:
/* set the channel between the communication test on channel 1 and channel 2 */ /* set the channel between the communication test on CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */
/* set Channel Hold mode */ /* set Channel Hold mode */
for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) {
dmy_sts = STS_MATCH[tmp_obj->ch]; dmy_sts = STS_MATCH[tmp_obj->ch];
if ((*dmy_sts & 0x04) == 0x04) { if ((*dmy_sts & 0x04) == 0x04) {
/* Channel Stop mode */ /* Channel Stop mode */
@ -777,11 +782,11 @@ int can_mode(can_t *obj, CanMode mode) {
can_set_channel_mode(tmp_obj->ch, CH_HOLD); can_set_channel_mode(tmp_obj->ch, CH_HOLD);
} }
can_set_global_mode(GL_TEST); can_set_global_mode(GL_TEST);
/* enable communication test between channel1 and channel2 */ /* enable communication test between CAN_TEST_GLOBAL_CH and CAN_TEST_GLOBAL_CH+1 */
RSCAN0GTSTCFG = 0x06; RSCAN0GTSTCFG = 0x06;
RSCAN0GTSTCTR = 0x01; RSCAN0GTSTCTR = 0x01;
/* send and receive setting of channel1 and channel2 */ /* send and receive setting of channel1 and channel2 */
for (tmp_obj->ch = CAN_1; tmp_obj->ch <= CAN_2; tmp_obj->ch++) { for (tmp_obj->ch = CAN_TEST_GLOBAL_CH; tmp_obj->ch <= (CAN_TEST_GLOBAL_CH + 1); tmp_obj->ch++) {
can_reset_buffer(tmp_obj); can_reset_buffer(tmp_obj);
/* set global interrrupt */ /* set global interrrupt */
/* THLEIE, MEIE and DEIE interrupts are disable */ /* THLEIE, MEIE and DEIE interrupts are disable */
@ -888,7 +893,9 @@ static void can_reset_reg(can_t *obj) {
static void can_reset_recv_rule(can_t *obj) { static void can_reset_recv_rule(can_t *obj) {
/* number of receive rules of each chanel = 64 */ /* number of receive rules of each chanel = 64 */
RSCAN0GAFLCFG0 = 0x40404040; RSCAN0GAFLCFG0 = 0x40404040;
#if defined(TARGET_RZA1H)
RSCAN0GAFLCFG1 = 0x40000000; RSCAN0GAFLCFG1 = 0x40000000;
#endif
/* enable receive rule table writing */ /* enable receive rule table writing */
RSCAN0GAFLECTR = 0x00000100; RSCAN0GAFLECTR = 0x00000100;
/* set the page number of receive rule table(ex: id ch = 1, page number = 4) */ /* set the page number of receive rule table(ex: id ch = 1, page number = 4) */
@ -939,8 +946,10 @@ static void can_reset_buffer(can_t *obj) {
*dmy_cfcc |= 0x02; *dmy_cfcc |= 0x02;
/* TMIEp interrupt is disable */ /* TMIEp interrupt is disable */
RSCAN0TMIEC0 = 0x00000000; RSCAN0TMIEC0 = 0x00000000;
#if defined(TARGET_RZA1H)
RSCAN0TMIEC1 = 0x00000000; RSCAN0TMIEC1 = 0x00000000;
RSCAN0TMIEC2 = 0x00000000; RSCAN0TMIEC2 = 0x00000000;
#endif
} }
static void can_reconfigure_channel(void) { static void can_reconfigure_channel(void) {
@ -1003,9 +1012,9 @@ static void can_set_frequency(can_t *obj, int f) {
static void can_set_global_mode(int mode) { static void can_set_global_mode(int mode) {
/* set Global mode */ /* set Global mode */
RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | mode); RSCAN0GCTR = ((RSCAN0GCTR & 0xFFFFFFFC) | (uint32_t)mode);
/* Wait to cahnge into Global XXXX mode */ /* Wait to cahnge into Global XXXX mode */
while ((RSCAN0GSTS & 0x07) != mode) { while ((RSCAN0GSTS & 0x07) != (uint32_t)mode) {
__NOP(); __NOP();
} }
} }
@ -1016,10 +1025,10 @@ static void can_set_channel_mode(uint32_t ch, int mode) {
/* set Channel mode */ /* set Channel mode */
dmy_ctr = CTR_MATCH[ch]; dmy_ctr = CTR_MATCH[ch];
*dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | mode); *dmy_ctr = ((*dmy_ctr & 0xFFFFFFFC) | (uint32_t)mode);
/* Wait to cahnge into Channel XXXX mode */ /* Wait to cahnge into Channel XXXX mode */
dmy_sts = STS_MATCH[ch]; dmy_sts = STS_MATCH[ch];
while ((*dmy_sts & 0x07) != mode) { while ((*dmy_sts & 0x07) != (uint32_t)mode) {
__NOP(); __NOP();
} }
} }

41
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/ethernet_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/ethernet_api.c
View File

@ -19,9 +19,11 @@
#include "mbed_interface.h" #include "mbed_interface.h"
#include "mbed_toolchain.h" #include "mbed_toolchain.h"
#include "mbed_error.h" #include "mbed_error.h"
#include "ether_iodefine.h" #include "iodefine.h"
#include "ethernetext_api.h" #include "ethernetext_api.h"
#if DEVICE_ETHERNET
/* Descriptor info */ /* Descriptor info */
#define NUM_OF_TX_DESCRIPTOR (16) #define NUM_OF_TX_DESCRIPTOR (16)
#define NUM_OF_RX_DESCRIPTOR (16) #define NUM_OF_RX_DESCRIPTOR (16)
@ -160,6 +162,7 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */ CPGSTBCR7 &= ~(CPG_STBCR7_BIT_MSTP74); /* enable ETHER clock */
#if defined(TARGET_RZ_A1H)
/* P4_2(PHY Reset) */ /* P4_2(PHY Reset) */
GPIOP4 &= ~0x0004; /* Outputs low level */ GPIOP4 &= ~0x0004; /* Outputs low level */
GPIOPMC4 &= ~0x0004; /* Port mode */ GPIOPMC4 &= ~0x0004; /* Port mode */
@ -201,6 +204,41 @@ int ethernetext_init(ethernet_cfg_t *p_ethcfg) {
wait_100us(250); /* 25msec */ wait_100us(250); /* 25msec */
GPIOP4 |= 0x0004; /* P4_2 Outputs high level */ GPIOP4 |= 0x0004; /* P4_2 Outputs high level */
wait_100us(100); /* 10msec */ wait_100us(100); /* 10msec */
#elif defined(TARGET_VK_RZ_A1H)
/* -->4F<-- P1_14(ET_COL) */
GPIOPMC1 |= 0x4000;
GPIOPFCAE1 &= ~0x4000;
GPIOPFCE1 |= 0x4000;
GPIOPFC1 |= 0x4000;
GPIOPIPC1 |= 0x4000;
/* -->2F<-- P2_0(ET_TXCLK), P2_1(ET_TXER), P2_2(ET_TXEN), P2_3(ET_CRS), P2_4(ET_TXD0),
P2_5(ET_TXD1), P2_6(ET_TXD2), P2_7(ET_TXD3), P2_8(ET_RXD0), P2_9(ET_RXD1), P2_10(ET_RXD2) P2_11(ET_RXD3) */
GPIOPMC2 |= 0x0FFF;
GPIOPFCAE2 &= ~0x0FFF;
GPIOPFCE2 &= ~0x0FFF;
GPIOPFC2 |= 0x0FFF;
GPIOPIPC2 |= 0x0FFF;
/* -->3F<-- P3_3(ET_MDIO), P3_4(ET_RXCLK), P3_5(ET_RXER), P3_6(ET_RXDV) */
GPIOPMC3 |= 0x0078;
GPIOPFCAE3 &= ~0x0078;
GPIOPFCE3 &= ~0x0078;
GPIOPFC3 |= 0x0078;
GPIOPIPC3 |= 0x0078;
/* -->3F<-- P7_0(ET_MDC) */
GPIOPMC7 |= 0x0001;
GPIOPFCAE7 &= ~0x0001;
GPIOPFCE7 |= 0x0001;
GPIOPFC7 &= ~0x0001;
GPIOPIPC7 |= 0x0001;
/* Resets the E-MAC,E-DMAC */
lan_reg_reset();
#else
#error "There is no initialization processing."
#endif
/* Resets the PHY-LSI */ /* Resets the PHY-LSI */
phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000); phy_reg_write(BASIC_MODE_CONTROL_REG, 0x8000);
@ -708,3 +746,4 @@ static void wait_100us(int32_t wait_cnt) {
/* Do Nothing */ /* Do Nothing */
} }
} }
#endif /* DEVICE_ETHERNET */

3
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/gpio_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_api.c
View File

@ -16,6 +16,7 @@
#include "gpio_api.h" #include "gpio_api.h"
#include "pinmap.h" #include "pinmap.h"
#include "gpio_addrdefine.h" #include "gpio_addrdefine.h"
#include "mbed_drv_cfg.h"
uint32_t gpio_set(PinName pin) { uint32_t gpio_set(PinName pin) {
@ -31,7 +32,7 @@ void gpio_init(gpio_t *obj, PinName pin) {
obj->mask = gpio_set(pin); obj->mask = gpio_set(pin);
group = PINGROUP(pin); group = PINGROUP(pin);
if (group > 9) return; if (group > GPIO_GROUP_MAX) return;
obj->reg_set = (volatile uint32_t *) PSR(group); obj->reg_set = (volatile uint32_t *) PSR(group);
obj->reg_in = (volatile uint32_t *) PPR(group); obj->reg_in = (volatile uint32_t *) PPR(group);

40
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/gpio_irq_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/gpio_irq_api.c
View File

@ -16,8 +16,8 @@
#include <stddef.h> #include <stddef.h>
#include "gpio_irq_api.h" #include "gpio_irq_api.h"
#include "intc_iodefine.h" #include "iodefine.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "cmsis.h" #include "cmsis.h"
#include "gpio_addrdefine.h" #include "gpio_addrdefine.h"
@ -37,14 +37,6 @@ static gpio_irq_handler irq_handler;
static const int nIRQn_h = 32; static const int nIRQn_h = 32;
extern PinName gpio_multi_guard; extern PinName gpio_multi_guard;
enum {
IRQ0,IRQ1,
IRQ2,IRQ3,
IRQ4,IRQ5,
IRQ6,IRQ7,
} IRQNo;
static const IRQHandler irq_tbl[CHANNEL_NUM] = { static const IRQHandler irq_tbl[CHANNEL_NUM] = {
&gpio_irq0, &gpio_irq0,
&gpio_irq1, &gpio_irq1,
@ -56,34 +48,6 @@ static const IRQHandler irq_tbl[CHANNEL_NUM] = {
&gpio_irq7, &gpio_irq7,
}; };
static const PinMap PinMap_IRQ[] = {
{P1_0, IRQ0, 4}, {P1_1, IRQ1, 4}, {P1_2, IRQ2, 4},
{P1_3, IRQ3, 4}, {P1_4, IRQ4, 4}, {P1_5, IRQ5, 4},
{P1_6, IRQ6, 4}, {P1_7, IRQ7, 4}, {P1_8, IRQ2, 3},
{P1_9, IRQ3, 3}, {P1_10, IRQ4, 3}, {P1_11, IRQ5, 3}, // 11
{P2_0, IRQ5, 6}, {P2_12, IRQ6, 6}, {P2_13, IRQ7, 8},
{P2_14, IRQ0, 8}, {P2_15, IRQ1, 8}, // 16
{P3_0, IRQ2, 3}, {P3_1, IRQ6, 3}, {P3_3, IRQ4, 3},
{P3_9, IRQ6, 8}, // 20
{P4_8, IRQ0, 8}, {P4_9, IRQ1, 8}, {P4_10, IRQ2, 8},
{P4_11, IRQ3, 8}, {P4_12, IRQ4, 8}, {P4_13, IRQ5, 8},
{P4_14, IRQ6, 8}, {P4_15, IRQ7, 8}, // 28
{P5_6, IRQ6, 6}, {P5_8, IRQ0, 2}, {P5_9, IRQ2, 4}, // 31
{P6_0, IRQ5, 6}, {P6_1, IRQ4, 4}, {P6_2, IRQ7, 4},
{P6_3, IRQ2, 4}, {P6_4, IRQ3, 4}, {P6_8, IRQ0, 8},
{P6_9, IRQ1, 8}, {P6_10, IRQ2, 8}, {P6_11, IRQ3, 8},
{P6_12, IRQ4, 8}, {P6_13, IRQ5, 8}, {P6_14, IRQ6, 8},
{P6_15, IRQ7, 8}, // 44
{P7_8, IRQ1, 8}, {P7_9, IRQ0, 8}, {P7_10, IRQ2, 8},
{P7_11, IRQ3, 8}, {P7_12, IRQ4, 8}, {P7_13, IRQ5, 8},
{P7_14, IRQ6, 8}, // 51
{P8_2, IRQ0, 5}, {P8_3, IRQ1, 6}, {P8_7, IRQ5, 4},
{P9_1, IRQ0, 4}, // 55
{P11_12,IRQ3, 3}, {P11_15,IRQ1, 3}, // 57
{NC, NC, 0}
};
static void handle_interrupt_in(int irq_num) { static void handle_interrupt_in(int irq_num) {
uint16_t irqs; uint16_t irqs;
uint16_t edge_req; uint16_t edge_req;

21
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/i2c_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/i2c_api.c
View File

@ -17,12 +17,11 @@
#include "dma_api.h" #include "dma_api.h"
#include "i2c_api.h" #include "i2c_api.h"
#include "cmsis.h" #include "cmsis.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "r_typedefs.h" #include "r_typedefs.h"
#include "riic_iodefine.h" #include "iodefine.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "MBRZA1H.h"
volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST; volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
@ -61,20 +60,6 @@ volatile struct st_riic *RIIC[] = RIIC_ADDRESS_LIST;
#define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */ #define WAIT_TIMEOUT (3600000) /* Loop counter : Time-out is about 1s. By 3600000 loops, measured value is 969ms. */
static const PinMap PinMap_I2C_SDA[] = {
{P1_1 , I2C_0, 1},
{P1_3 , I2C_1, 1},
{P1_7 , I2C_3, 1},
{NC , NC , 0}
};
static const PinMap PinMap_I2C_SCL[] = {
{P1_0 , I2C_0, 1},
{P1_2 , I2C_1, 1},
{P1_6 , I2C_3, 1},
{NC , NC, 0}
};
static inline int i2c_status(i2c_t *obj) { static inline int i2c_status(i2c_t *obj) {
return REG(SR2.UINT8[0]); return REG(SR2.UINT8[0]);
} }
@ -220,6 +205,7 @@ static inline void i2c_power_enable(i2c_t *obj) {
break; break;
} }
dummy = CPGSTBCR9; dummy = CPGSTBCR9;
(void)dummy;
} }
void i2c_init(i2c_t *obj, PinName sda, PinName scl) { void i2c_init(i2c_t *obj, PinName sda, PinName scl) {
@ -414,7 +400,6 @@ int i2c_read(i2c_t *obj, int address, char *data, int length, int stop) {
int count = 0; int count = 0;
int status; int status;
int value; int value;
volatile uint32_t work_reg = 0;
i2c_set_MR3_ACK(obj); i2c_set_MR3_ACK(obj);
/* There is a STOP condition for last processing */ /* There is a STOP condition for last processing */

2
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/objects.h → targets/TARGET_RENESAS/TARGET_RZ_A1XX/objects.h
View File

@ -22,7 +22,6 @@
#include "PeripheralNames.h" #include "PeripheralNames.h"
#include "PinNames.h" #include "PinNames.h"
#include "gpio_object.h" #include "gpio_object.h"
#include "rspi_iodefine.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
@ -41,6 +40,7 @@ struct i2c_s {
struct spi_s { struct spi_s {
struct st_rspi *spi; struct st_rspi *spi;
uint32_t bits; uint32_t bits;
int index;
}; };
struct gpio_irq_s { struct gpio_irq_s {

74
targets/TARGET_RENESAS/TARGET_RZ_A1XX/pinmap.c Normal file
View File

@ -0,0 +1,74 @@
/* mbed Microcontroller Library
* Copyright (c) 2006-2013 ARM Limited
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
* http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*/
#include "PeripheralPins.h"
#include "mbed_error.h"
#include "gpio_addrdefine.h"
PinName gpio_multi_guard = (PinName)NC; /* If set pin name here, setting of the "pin" is just one time */
void pin_function(PinName pin, int function) {
if (pin == (PinName)NC) return;
int n = pin >> 4;
int bitmask = 1<<(pin & 0xf);
const PinFunc * Pipc_0_func = PIPC_0_tbl;
int pipc_data = 1;
if (gpio_multi_guard != pin) {
if (function == 0) {
// means GPIO mode
*PMC(n) &= ~bitmask;
} else {
// alt-function mode
--function;
if (function & (1 << 2)) { *PFCAE(n) |= bitmask;}else { *PFCAE(n) &= ~bitmask;}
if (function & (1 << 1)) { *PFCE(n) |= bitmask;}else { *PFCE(n) &= ~bitmask;}
if (function & (1 << 0)) { *PFC(n) |= bitmask;}else { *PFC(n) &= ~bitmask;}
while (Pipc_0_func->pin != NC) {
if ((Pipc_0_func->pin == pin) && ((Pipc_0_func->function - 1) == function)) {
pipc_data = 0;
if (Pipc_0_func->pm == 0) {
*PMSR(n) = (bitmask << 16) | 0;
} else if (Pipc_0_func->pm == 1) {
*PMSR(n) = (bitmask << 16) | bitmask;
} else {
// Do Nothing
}
break;
}
Pipc_0_func++;
}
if (pipc_data == 1) {
*PIPC(n) |= bitmask;
} else {
*PIPC(n) &= ~bitmask;
}
if (P1_0 <= pin && pin <= P1_7 && function == 0) {
*PBDC(n) |= bitmask;
}
*PMC(n) |= bitmask;
}
} else {
gpio_multi_guard = (PinName)NC;
}
}
void pin_mode(PinName pin, PinMode mode) {
// if (pin == (PinName)NC) { return; }
}

25
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/port_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/port_api.c
View File

@ -23,20 +23,20 @@ PinName port_pin(PortName port, int pin_n) {
} }
void port_init(port_t *obj, PortName port, int mask, PinDirection dir) { void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
uint32_t i;
obj->port = port; obj->port = port;
obj->mask = mask; obj->mask = mask;
obj->reg_dir = (volatile uint32_t *)PMSR(port); obj->reg_dir = (volatile uint32_t *)PMSR(port);
obj->reg_out = (volatile uint32_t *)PORT(port); obj->reg_out = (volatile uint32_t *)PORT(port);
obj->reg_in = (volatile uint32_t *)PPR(port); obj->reg_in = (volatile uint32_t *)PPR(port);
obj->reg_buf = (volatile uint32_t *)PIBC(port); obj->reg_buf = (volatile uint32_t *)PIBC(port);
// Do not use masking, because it prevents the use of the unmasked pins // Do not use masking, because it prevents the use of the unmasked pins
// port_reg->FIOMASK = ~mask; // port_reg->FIOMASK = ~mask;
uint32_t i;
// The function is set per pin: reuse gpio logic // The function is set per pin: reuse gpio logic
for (i=0; i<32; i++) { for (i = 0; i < 32; i++) {
if (obj->mask & (1<<i)) { if (obj->mask & (1 << i)) {
gpio_set(port_pin(obj->port, i)); gpio_set(port_pin(obj->port, i));
} }
} }
@ -47,8 +47,8 @@ void port_init(port_t *obj, PortName port, int mask, PinDirection dir) {
void port_mode(port_t *obj, PinMode mode) { void port_mode(port_t *obj, PinMode mode) {
uint32_t i; uint32_t i;
// The mode is set per pin: reuse pinmap logic // The mode is set per pin: reuse pinmap logic
for (i=0; i<32; i++) { for (i = 0; i < 32; i++) {
if (obj->mask & (1<<i)) { if (obj->mask & (1 << i)) {
pin_mode(port_pin(obj->port, i), mode); pin_mode(port_pin(obj->port, i), mode);
} }
} }
@ -57,11 +57,14 @@ void port_mode(port_t *obj, PinMode mode) {
void port_dir(port_t *obj, PinDirection dir) { void port_dir(port_t *obj, PinDirection dir) {
switch (dir) { switch (dir) {
case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask; case PIN_INPUT : *obj->reg_dir = (obj->mask << 16) | obj->mask;
*obj->reg_buf |= obj->mask; *obj->reg_buf |= obj->mask;
break; break;
case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask; case PIN_OUTPUT: *obj->reg_dir = (obj->mask << 16) | ~obj->mask;
*obj->reg_buf &= ~obj->mask; *obj->reg_buf &= ~obj->mask;
break; break;
default:
// do nothing
break;
} }
} }

270
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/pwmout_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/pwmout_api.c
View File

@ -16,139 +16,120 @@
#include "mbed_assert.h" #include "mbed_assert.h"
#include "pwmout_api.h" #include "pwmout_api.h"
#include "cmsis.h" #include "cmsis.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "cpg_iodefine.h" #include "iodefine.h"
#include "pwm_iodefine.h"
#include "gpio_addrdefine.h" #include "gpio_addrdefine.h"
#include "mbed_drv_cfg.h"
#define MTU2_PWM_NUM 22
#define MTU2_PWM_SIGNAL 2
#define MTU2_PWM_OFFSET 0x20 #define MTU2_PWM_OFFSET 0x20
// PORT ID, PWM ID, Pin function #ifdef FUNC_MOTOR_CTL_PWM
static const PinMap PinMap_PWM[] = { typedef enum {
{P2_1 , MTU2_PWM0_PIN , 6}, PWM1A = 0,
{P2_11 , MTU2_PWM1_PIN , 5}, PWM1B,
{P3_8 , MTU2_PWM2_PIN , 6}, PWM1C,
{P3_10 , MTU2_PWM3_PIN , 6}, PWM1D,
{P4_0 , MTU2_PWM4_PIN , 2}, PWM1E,
{P4_4 , MTU2_PWM5_PIN , 3}, PWM1F,
{P4_6 , MTU2_PWM6_PIN , 3}, PWM1G,
{P5_0 , MTU2_PWM7_PIN , 6}, PWM1H,
{P5_3 , MTU2_PWM8_PIN , 6}, PWM2A = 0x10,
{P5_5 , MTU2_PWM9_PIN , 6}, PWM2B,
{P7_2 , MTU2_PWM10_PIN , 7}, PWM2C,
{P7_4 , MTU2_PWM11_PIN , 7}, PWM2D,
{P7_6 , MTU2_PWM12_PIN , 7}, PWM2E,
{P7_10 , MTU2_PWM13_PIN , 7}, PWM2F,
{P7_12 , MTU2_PWM14_PIN , 7}, PWM2G,
{P7_14 , MTU2_PWM15_PIN , 7}, PWM2H,
{P8_8 , MTU2_PWM16_PIN , 5}, } PWMType;
{P8_10 , MTU2_PWM17_PIN , 4},
{P8_12 , MTU2_PWM18_PIN , 4},
{P8_14 , MTU2_PWM19_PIN , 4},
{P11_0 , MTU2_PWM20_PIN , 2},
{P11_2 , MTU2_PWM21_PIN , 2},
{P4_4 , PWM0_PIN , 4},
{P3_2 , PWM1_PIN , 7},
{P4_6 , PWM2_PIN , 4},
{P4_7 , PWM3_PIN , 4},
{P8_14 , PWM4_PIN , 6},
{P8_15 , PWM5_PIN , 6},
{P8_13 , PWM6_PIN , 6},
{P8_11 , PWM7_PIN , 6},
{P8_8 , PWM8_PIN , 6},
{P10_0 , PWM9_PIN , 3},
{P8_12 , PWM10_PIN , 6},
{P8_9 , PWM11_PIN , 6},
{P8_10 , PWM12_PIN , 6},
{P4_5 , PWM13_PIN , 4},
{NC , NC , 0}
};
static const PWMType PORT[] = { static const PWMType PORT[] = {
PWM2E, // PWM0_PIN PWM1A, // PWM_PWM1A
PWM2C, // PWM1_PIN PWM1B, // PWM_PWM1B
PWM2G, // PWM2_PIN PWM1C, // PWM_PWM1C
PWM2H, // PWM3_PIN PWM1D, // PWM_PWM1D
PWM1G, // PWM4_PIN PWM1E, // PWM_PWM1E
PWM1H, // PWM5_PIN PWM1F, // PWM_PWM1F
PWM1F, // PWM6_PIN PWM1G, // PWM_PWM1G
PWM1D, // PWM7_PIN PWM1H, // PWM_PWM1H
PWM1A, // PWM8_PIN PWM2A, // PWM_PWM2A
PWM2A, // PWM9_PIN PWM2B, // PWM_PWM2B
PWM1E, // PWM10_PIN PWM2C, // PWM_PWM2C
PWM1B, // PWM11_PIN PWM2D, // PWM_PWM2D
PWM1C, // PWM12_PIN PWM2E, // PWM_PWM2E
PWM2F, // PWM13_PIN PWM2F, // PWM_PWM2F
}; PWM2G, // PWM_PWM2G
PWM2H, // PWM_PWM2H
static const MTU2_PWMType MTU2_PORT[] = {
TIOC2A, // MTU2_PWM0_PIN
TIOC1A, // MTU2_PWM1_PIN
TIOC4A, // MTU2_PWM2_PIN
TIOC4C, // MTU2_PWM3_PIN
TIOC0A, // MTU2_PWM4_PIN
TIOC4A, // MTU2_PWM5_PIN
TIOC4C, // MTU2_PWM6_PIN
TIOC0A, // MTU2_PWM7_PIN
TIOC3C, // MTU2_PWM8_PIN
TIOC0C, // MTU2_PWM9_PIN
TIOC0C, // MTU2_PWM10_PIN
TIOC1A, // MTU2_PWM11_PIN
TIOC2A, // MTU2_PWM12_PIN
TIOC3C, // MTU2_PWM13_PIN
TIOC4A, // MTU2_PWM14_PIN
TIOC4C, // MTU2_PWM15_PIN
TIOC1A, // MTU2_PWM16_PIN
TIOC3A, // MTU2_PWM17_PIN
TIOC3C, // MTU2_PWM18_PIN
TIOC2A, // MTU2_PWM19_PIN
TIOC4A, // MTU2_PWM20_PIN
TIOC4C, // MTU2_PWM21_PIN
}; };
static __IO uint16_t *PWM_MATCH[] = { static __IO uint16_t *PWM_MATCH[] = {
&PWMPWBFR_2E, // PWM0_PIN &PWMPWBFR_1A, // PWM_PWM1A
&PWMPWBFR_2C, // PWM1_PIN &PWMPWBFR_1A, // PWM_PWM1B
&PWMPWBFR_2G, // PWM2_PIN &PWMPWBFR_1C, // PWM_PWM1C
&PWMPWBFR_2G, // PWM3_PIN &PWMPWBFR_1C, // PWM_PWM1D
&PWMPWBFR_1G, // PWM4_PIN &PWMPWBFR_1E, // PWM_PWM1E
&PWMPWBFR_1G, // PWM5_PIN &PWMPWBFR_1E, // PWM_PWM1F
&PWMPWBFR_1E, // PWM6_PIN &PWMPWBFR_1G, // PWM_PWM1G
&PWMPWBFR_1C, // PWM7_PIN &PWMPWBFR_1G, // PWM_PWM1H
&PWMPWBFR_1A, // PWM8_PIN &PWMPWBFR_2A, // PWM_PWM2A
&PWMPWBFR_2A, // PWM9_PIN &PWMPWBFR_2A, // PWM_PWM2B
&PWMPWBFR_1E, // PWM10_PIN &PWMPWBFR_2C, // PWM_PWM2C
&PWMPWBFR_1A, // PWM11_PIN &PWMPWBFR_2C, // PWM_PWM2D
&PWMPWBFR_1C, // PWM12_PIN &PWMPWBFR_2E, // PWM_PWM2E
&PWMPWBFR_2E, // PWM13_PIN &PWMPWBFR_2E, // PWM_PWM2F
&PWMPWBFR_2G, // PWM_PWM2G
&PWMPWBFR_2G, // PWM_PWM2H
}; };
static __IO uint16_t *MTU2_PWM_MATCH[MTU2_PWM_NUM][MTU2_PWM_SIGNAL] = { static uint16_t init_period_ch1 = 0;
{ &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM0_PIN static uint16_t init_period_ch2 = 0;
{ &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM1_PIN static int32_t period_ch1 = 1;
{ &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM2_PIN static int32_t period_ch2 = 1;
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM3_PIN #endif
{ &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM4_PIN
{ &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM5_PIN #ifdef FUMC_MTU2_PWM
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM6_PIN #define MTU2_PWM_SIGNAL 2
{ &MTU2TGRA_0, &MTU2TGRB_0 }, // MTU2_PWM7_PIN
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM8_PIN typedef enum {
{ &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM9_PIN TIOC0A = 0,
{ &MTU2TGRC_0, &MTU2TGRD_0 }, // MTU2_PWM10_PIN TIOC0B,
{ &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM11_PIN TIOC0C,
{ &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM12_PIN TIOC0D,
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM13_PIN TIOC1A = 0x10,
{ &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM14_PIN TIOC1B,
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // MTU2_PWM15_PIN TIOC2A = 0x20,
{ &MTU2TGRA_1, &MTU2TGRB_1 }, // MTU2_PWM16_PIN TIOC2B,
{ &MTU2TGRA_3, &MTU2TGRB_3 }, // MTU2_PWM17_PIN TIOC3A = 0x30,
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // MTU2_PWM18_PIN TIOC3B,
{ &MTU2TGRA_2, &MTU2TGRB_2 }, // MTU2_PWM19_PIN TIOC3C,
{ &MTU2TGRA_4, &MTU2TGRB_4 }, // MTU2_PWM20_PIN TIOC3D,
{ &MTU2TGRC_4, &MTU2TGRD_4 } // MTU2_PWM21_PIN TIOC4A = 0x40,
TIOC4B,
TIOC4C,
TIOC4D,
} MTU2_PWMType;
static const MTU2_PWMType MTU2_PORT[] = {
TIOC0A, // PWM_TIOC0A
TIOC0C, // PWM_TIOC0C
TIOC1A, // PWM_TIOC1A
TIOC2A, // PWM_TIOC2A
TIOC3A, // PWM_TIOC3A
TIOC3C, // PWM_TIOC3C
TIOC4A, // PWM_TIOC4A
TIOC4C, // PWM_TIOC4C
};
static __IO uint16_t *MTU2_PWM_MATCH[][MTU2_PWM_SIGNAL] = {
{ &MTU2TGRA_0, &MTU2TGRB_0 }, // PWM_TIOC0A
{ &MTU2TGRC_0, &MTU2TGRD_0 }, // PWM_TIOC0C
{ &MTU2TGRA_1, &MTU2TGRB_1 }, // PWM_TIOC1A
{ &MTU2TGRA_2, &MTU2TGRB_2 }, // PWM_TIOC2A
{ &MTU2TGRA_3, &MTU2TGRB_3 }, // PWM_TIOC3A
{ &MTU2TGRC_3, &MTU2TGRD_3 }, // PWM_TIOC3C
{ &MTU2TGRA_4, &MTU2TGRB_4 }, // PWM_TIOC4A
{ &MTU2TGRC_4, &MTU2TGRD_4 }, // PWM_TIOC4C
}; };
static __IO uint8_t *TCR_MATCH[] = { static __IO uint8_t *TCR_MATCH[] = {
@ -212,12 +193,9 @@ typedef enum {
MTU2_PERIOD MTU2_PERIOD
} MTU2Signal; } MTU2Signal;
static uint16_t init_period_ch1 = 0;
static uint16_t init_period_ch2 = 0;
static uint16_t init_mtu2_period_ch[5] = {0}; static uint16_t init_mtu2_period_ch[5] = {0};
static int32_t period_ch1 = 1;
static int32_t period_ch2 = 1;
static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1}; static int32_t mtu2_period_ch[5] = {1, 1, 1, 1, 1};
#endif
void pwmout_init(pwmout_t* obj, PinName pin) { void pwmout_init(pwmout_t* obj, PinName pin) {
// determine the channel // determine the channel
@ -225,6 +203,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
MBED_ASSERT(pwm != (PWMName)NC); MBED_ASSERT(pwm != (PWMName)NC);
if (pwm >= MTU2_PWM_OFFSET) { if (pwm >= MTU2_PWM_OFFSET) {
#ifdef FUMC_MTU2_PWM
/* PWM by MTU2 */ /* PWM by MTU2 */
int tmp_pwm; int tmp_pwm;
@ -260,7 +239,9 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
pwmout_period_us(obj, 1000); pwmout_period_us(obj, 1000);
init_mtu2_period_ch[obj->ch] = 1; init_mtu2_period_ch[obj->ch] = 1;
} }
#endif
} else { } else {
#ifdef FUNC_MOTOR_CTL_PWM
/* PWM */ /* PWM */
// power on // power on
CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30); CPGSTBCR3 &= ~(CPG_STBCR3_BIT_MSTP30);
@ -287,6 +268,7 @@ void pwmout_init(pwmout_t* obj, PinName pin) {
pwmout_period_us(obj, 491); pwmout_period_us(obj, 491);
init_period_ch1 = 1; init_period_ch1 = 1;
} }
#endif
} }
} }
@ -296,12 +278,12 @@ void pwmout_free(pwmout_t* obj) {
void pwmout_write(pwmout_t* obj, float value) { void pwmout_write(pwmout_t* obj, float value) {
uint32_t wk_cycle; uint32_t wk_cycle;
uint16_t v;
if (obj->pwm >= MTU2_PWM_OFFSET) { if (obj->pwm >= MTU2_PWM_OFFSET) {
#ifdef FUMC_MTU2_PWM
/* PWM by MTU2 */ /* PWM by MTU2 */
int tmp_pwm; int tmp_pwm;
if (value < 0.0f) { if (value < 0.0f) {
value = 0.0f; value = 0.0f;
} else if (value > 1.0f) { } else if (value > 1.0f) {
@ -312,8 +294,16 @@ void pwmout_write(pwmout_t* obj, float value) {
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
// set channel match to percentage // set channel match to percentage
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value); if (value == 1.0f) {
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)(wk_cycle - 1);
} else {
*MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] = (uint16_t)((float)wk_cycle * value);
}
#endif
} else { } else {
#ifdef FUNC_MOTOR_CTL_PWM
uint16_t v;
/* PWM */ /* PWM */
if (value < 0.0f) { if (value < 0.0f) {
value = 0.0f; value = 0.0f;
@ -332,6 +322,7 @@ void pwmout_write(pwmout_t* obj, float value) {
// set channel match to percentage // set channel match to percentage
v = (uint16_t)((float)wk_cycle * value); v = (uint16_t)((float)wk_cycle * value);
*PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12)); *PWM_MATCH[obj->pwm] = (v | ((PORT[obj->pwm] & 1) << 12));
#endif
} }
} }
@ -340,6 +331,7 @@ float pwmout_read(pwmout_t* obj) {
float value; float value;
if (obj->pwm >= MTU2_PWM_OFFSET) { if (obj->pwm >= MTU2_PWM_OFFSET) {
#ifdef FUMC_MTU2_PWM
/* PWM by MTU2 */ /* PWM by MTU2 */
uint32_t wk_pulse; uint32_t wk_pulse;
int tmp_pwm; int tmp_pwm;
@ -348,7 +340,9 @@ float pwmout_read(pwmout_t* obj) {
wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff; wk_cycle = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PERIOD] & 0xffff;
wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff; wk_pulse = *MTU2_PWM_MATCH[tmp_pwm][MTU2_PULSE] & 0xffff;
value = ((float)wk_pulse / (float)wk_cycle); value = ((float)wk_pulse / (float)wk_cycle);
#endif
} else { } else {
#ifdef FUNC_MOTOR_CTL_PWM
/* PWM */ /* PWM */
if (obj->ch == 2) { if (obj->ch == 2) {
wk_cycle = PWMPWCYR_2 & 0x03ff; wk_cycle = PWMPWCYR_2 & 0x03ff;
@ -356,6 +350,7 @@ float pwmout_read(pwmout_t* obj) {
wk_cycle = PWMPWCYR_1 & 0x03ff; wk_cycle = PWMPWCYR_1 & 0x03ff;
} }
value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle); value = ((float)(*PWM_MATCH[obj->pwm] & 0x03ff) / (float)wk_cycle);
#endif
} }
return (value > 1.0f) ? (1.0f) : (value); return (value > 1.0f) ? (1.0f) : (value);
@ -369,6 +364,7 @@ void pwmout_period_ms(pwmout_t* obj, int ms) {
pwmout_period_us(obj, ms * 1000); pwmout_period_us(obj, ms * 1000);
} }
#ifdef FUNC_MOTOR_CTL_PWM
static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
uint16_t wk_pwmpbfr; uint16_t wk_pwmpbfr;
float value; float value;
@ -379,7 +375,9 @@ static void set_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16
v = (uint16_t)((float)new_cycle * value); v = (uint16_t)((float)new_cycle * value);
*p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000)); *p_pwmpbfr = (v | (wk_pwmpbfr & 0x1000));
} }
#endif
#ifdef FUMC_MTU2_PWM
static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){ static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, uint16_t new_cycle){
uint16_t wk_pwmpbfr; uint16_t wk_pwmpbfr;
float value; float value;
@ -388,17 +386,20 @@ static void set_mtu2_duty_again(__IO uint16_t *p_pwmpbfr, uint16_t last_cycle, u
value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle); value = ((float)(wk_pwmpbfr & 0xffff) / (float)last_cycle);
*p_pwmpbfr = (uint16_t)((float)new_cycle * value); *p_pwmpbfr = (uint16_t)((float)new_cycle * value);
} }
#endif
// Set the PWM period, keeping the duty cycle the same. // Set the PWM period, keeping the duty cycle the same.
void pwmout_period_us(pwmout_t* obj, int us) { void pwmout_period_us(pwmout_t* obj, int us) {
uint64_t wk_cycle_mtu2;
uint32_t pclk_base; uint32_t pclk_base;
uint32_t wk_cycle; uint32_t wk_cycle;
uint32_t wk_cks = 0; uint32_t wk_cks = 0;
uint16_t wk_last_cycle; uint16_t wk_last_cycle;
int max_us = 0;
if (obj->pwm >= MTU2_PWM_OFFSET) { if (obj->pwm >= MTU2_PWM_OFFSET) {
#ifdef FUMC_MTU2_PWM
uint64_t wk_cycle_mtu2;
int max_us = 0;
/* PWM by MTU2 */ /* PWM by MTU2 */
int tmp_pwm; int tmp_pwm;
uint8_t tmp_tcr_up; uint8_t tmp_tcr_up;
@ -432,7 +433,7 @@ void pwmout_period_us(pwmout_t* obj, int us) {
wk_cks++; wk_cks++;
} }
wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000); wk_cycle = (uint32_t)(wk_cycle_mtu2 / 1000000);
tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET); tmp_pwm = (int)(obj->pwm - MTU2_PWM_OFFSET);
if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) { if (((uint8_t)MTU2_PORT[tmp_pwm] & 0x02) == 0x02) {
tmp_tcr_up = 0xC0; tmp_tcr_up = 0xC0;
@ -468,7 +469,9 @@ void pwmout_period_us(pwmout_t* obj, int us) {
MTU2TSTR |= tmp_tstr_st; MTU2TSTR |= tmp_tstr_st;
// Save for future use // Save for future use
mtu2_period_ch[obj->ch] = us; mtu2_period_ch[obj->ch] = us;
#endif
} else { } else {
#ifdef FUNC_MOTOR_CTL_PWM
/* PWM */ /* PWM */
if (us > 491) { if (us > 491) {
us = 491; us = 491;
@ -524,6 +527,7 @@ void pwmout_period_us(pwmout_t* obj, int us) {
// Save for future use // Save for future use
period_ch1 = us; period_ch1 = us;
} }
#endif
} }
} }
@ -539,11 +543,14 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
float value = 0; float value = 0;
if (obj->pwm >= MTU2_PWM_OFFSET) { if (obj->pwm >= MTU2_PWM_OFFSET) {
#ifdef FUMC_MTU2_PWM
/* PWM by MTU2 */ /* PWM by MTU2 */
if (mtu2_period_ch[obj->ch] != 0) { if (mtu2_period_ch[obj->ch] != 0) {
value = (float)us / (float)mtu2_period_ch[obj->ch]; value = (float)us / (float)mtu2_period_ch[obj->ch];
} }
#endif
} else { } else {
#ifdef FUNC_MOTOR_CTL_PWM
/* PWM */ /* PWM */
if (obj->ch == 2) { if (obj->ch == 2) {
if (period_ch2 != 0) { if (period_ch2 != 0) {
@ -554,6 +561,7 @@ void pwmout_pulsewidth_us(pwmout_t* obj, int us) {
value = (float)us / (float)period_ch1; value = (float)us / (float)period_ch1;
} }
} }
#endif
} }
pwmout_write(obj, value); pwmout_write(obj, value);
} }

11
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_VK_RZ_A1H/rtc_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/rtc_api.c
View File

@ -19,15 +19,11 @@
#if DEVICE_RTC #if DEVICE_RTC
#define USE_RTCX1_CLK
//#define USE_EXTAL_CLK
//#define USE_RTCX3_CLK
#include "rtc_api.h" #include "rtc_api.h"
#include "rtc_iodefine.h" #include "iodefine.h"
#include "mbed_drv_cfg.h"
#include "mbed_mktime.h" #include "mbed_mktime.h"
#define RCR1_VAL_ON (0x08u) // AIE = 1 #define RCR1_VAL_ON (0x08u) // AIE = 1
#define RCR1_VAL_OFF (0x00u) #define RCR1_VAL_OFF (0x00u)
#define RCR3_VAL (0x00u) #define RCR3_VAL (0x00u)
@ -138,6 +134,7 @@ void rtc_init(void) {
// Dummy read // Dummy read
dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT;
dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT;
(void)dummy_read;
} }
@ -188,6 +185,7 @@ void rtc_free(void) {
// Dummy read // Dummy read
dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT;
dummy_read = RTC.RYRCNT; dummy_read = RTC.RYRCNT;
(void)dummy_read;
} }
@ -368,6 +366,7 @@ void rtc_write(time_t t) {
dummy_read = (uint16_t)RTC.RCR2; dummy_read = (uint16_t)RTC.RCR2;
dummy_read = (uint16_t)RTC.RCR2; dummy_read = (uint16_t)RTC.RCR2;
(void)dummy_read;
} }
} }

417
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/serial_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/serial_api.c
View File

@ -21,103 +21,55 @@
#include "serial_api.h" #include "serial_api.h"
#include "cmsis.h" #include "cmsis.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "gpio_api.h" #include "gpio_api.h"
#include "RZ_A1_Init.h"
#include "scif_iodefine.h" #include "iodefine.h"
#include "cpg_iodefine.h" #include "mbed_drv_cfg.h"
#include "mbed_critical.h" #include "mbed_critical.h"
/****************************************************************************** /******************************************************************************
* INITIALIZATION * INITIALIZATION
******************************************************************************/ ******************************************************************************/
#define PCLK (66666666) // Define the peripheral clock P1 frequency. #if defined(TARGET_RZA1H)
#define UART_NUM 8 #define UART_NUM 8
#else
#define UART_NUM 5
#endif
#define IRQ_NUM 4 #define IRQ_NUM 4
static void uart0_tx_irq(void); static void uart0_tx_irq(void);
static void uart1_tx_irq(void);
static void uart2_tx_irq(void);
static void uart3_tx_irq(void);
static void uart4_tx_irq(void);
static void uart5_tx_irq(void);
static void uart6_tx_irq(void);
static void uart7_tx_irq(void);
static void uart0_rx_irq(void); static void uart0_rx_irq(void);
static void uart1_rx_irq(void);
static void uart2_rx_irq(void);
static void uart3_rx_irq(void);
static void uart4_rx_irq(void);
static void uart5_rx_irq(void);
static void uart6_rx_irq(void);
static void uart7_rx_irq(void);
static void uart0_er_irq(void); static void uart0_er_irq(void);
static void uart1_tx_irq(void);
static void uart1_rx_irq(void);
static void uart1_er_irq(void); static void uart1_er_irq(void);
static void uart2_tx_irq(void);
static void uart2_rx_irq(void);
static void uart2_er_irq(void); static void uart2_er_irq(void);
static void uart3_tx_irq(void);
static void uart3_rx_irq(void);
static void uart3_er_irq(void); static void uart3_er_irq(void);
static void uart4_tx_irq(void);
static void uart4_rx_irq(void);
static void uart4_er_irq(void); static void uart4_er_irq(void);
#if defined(TARGET_RZA1H)
static void uart5_tx_irq(void);
static void uart5_rx_irq(void);
static void uart5_er_irq(void); static void uart5_er_irq(void);
static void uart6_tx_irq(void);
static void uart6_rx_irq(void);
static void uart6_er_irq(void); static void uart6_er_irq(void);
static void uart7_tx_irq(void);
static void uart7_rx_irq(void);
static void uart7_er_irq(void); static void uart7_er_irq(void);
#endif
static void serial_put_done(serial_t *obj); static void serial_put_done(serial_t *obj);
static uint8_t serial_available_buffer(serial_t *obj); static uint8_t serial_available_buffer(serial_t *obj);
static void serial_irq_err_set(serial_t *obj, uint32_t enable); static void serial_irq_err_set(serial_t *obj, uint32_t enable);
static const PinMap PinMap_UART_TX[] = {
{P2_14 , UART0, 6},
{P2_5 , UART1, 6},
{P4_12 , UART1, 7},
{P6_3 , UART2, 7},
{P4_14 , UART2, 7},
{P5_3 , UART3, 5},
{P8_8 , UART3, 7},
{P5_0 , UART4, 5},
{P8_14 , UART4, 7},
{P8_13 , UART5, 5},
{P11_10, UART5, 3},
{P6_6 , UART5, 5},
{P5_6 , UART6, 5},
{P11_1 , UART6, 4},
{P7_4 , UART7, 4},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RX[] = {
{P2_15 , UART0, 6},
{P2_6 , UART1, 6},
{P4_13 , UART1, 7},
{P6_2 , UART2, 7},
{P4_15 , UART2, 7},
{P5_4 , UART3, 5},
{P8_9 , UART3, 7},
{P5_1 , UART4, 5},
{P8_15 , UART4, 7},
{P8_11 , UART5, 5},
{P11_11, UART5, 3},
{P6_7 , UART5, 5},
{P5_7 , UART6, 5},
{P11_2 , UART6, 4},
{P7_5 , UART7, 4},
{NC , NC , 0}
};
static const PinMap PinMap_UART_CTS[] = {
{P2_3 , UART1, 6},
{P11_7 , UART5, 3},
{P7_6 , UART7, 4},
{NC , NC , 0}
};
static const PinMap PinMap_UART_RTS[] = {
{P2_7 , UART1, 6},
{P11_8 , UART5, 3},
{P7_7 , UART7, 4},
{NC , NC , 0}
};
static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST; static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
static uart_irq_handler irq_handler; static uart_irq_handler irq_handler;
@ -127,7 +79,6 @@ serial_t stdio_uart;
struct serial_global_data_s { struct serial_global_data_s {
uint32_t serial_irq_id; uint32_t serial_irq_id;
gpio_t sw_rts, sw_cts; gpio_t sw_rts, sw_cts;
uint8_t rx_irq_set_flow, rx_irq_set_api;
serial_t *tranferring_obj, *receiving_obj; serial_t *tranferring_obj, *receiving_obj;
uint32_t async_tx_callback, async_rx_callback; uint32_t async_tx_callback, async_rx_callback;
int event, wanted_rx_events; int event, wanted_rx_events;
@ -141,9 +92,11 @@ static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
{SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn}, {SCIFRXI2_IRQn, SCIFTXI2_IRQn, SCIFBRI2_IRQn, SCIFERI2_IRQn},
{SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn}, {SCIFRXI3_IRQn, SCIFTXI3_IRQn, SCIFBRI3_IRQn, SCIFERI3_IRQn},
{SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn}, {SCIFRXI4_IRQn, SCIFTXI4_IRQn, SCIFBRI4_IRQn, SCIFERI4_IRQn},
#if defined(TARGET_RZA1H)
{SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn}, {SCIFRXI5_IRQn, SCIFTXI5_IRQn, SCIFBRI5_IRQn, SCIFERI5_IRQn},
{SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn}, {SCIFRXI6_IRQn, SCIFTXI6_IRQn, SCIFBRI6_IRQn, SCIFERI6_IRQn},
{SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn} {SCIFRXI7_IRQn, SCIFTXI7_IRQn, SCIFBRI7_IRQn, SCIFERI7_IRQn},
#endif
}; };
static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = { static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
@ -152,9 +105,11 @@ static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
{uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq}, {uart2_rx_irq, uart2_tx_irq, uart2_er_irq, uart2_er_irq},
{uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq}, {uart3_rx_irq, uart3_tx_irq, uart3_er_irq, uart3_er_irq},
{uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq}, {uart4_rx_irq, uart4_tx_irq, uart4_er_irq, uart4_er_irq},
#if defined(TARGET_RZA1H)
{uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq}, {uart5_rx_irq, uart5_tx_irq, uart5_er_irq, uart5_er_irq},
{uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq}, {uart6_rx_irq, uart6_tx_irq, uart6_er_irq, uart6_er_irq},
{uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq} {uart7_rx_irq, uart7_tx_irq, uart7_er_irq, uart7_er_irq},
#endif
}; };
static __IO uint16_t *SCSCR_MATCH[] = { static __IO uint16_t *SCSCR_MATCH[] = {
@ -163,9 +118,11 @@ static __IO uint16_t *SCSCR_MATCH[] = {
&SCSCR_2, &SCSCR_2,
&SCSCR_3, &SCSCR_3,
&SCSCR_4, &SCSCR_4,
#if defined(TARGET_RZA1H)
&SCSCR_5, &SCSCR_5,
&SCSCR_6, &SCSCR_6,
&SCSCR_7, &SCSCR_7,
#endif
}; };
static __IO uint16_t *SCFSR_MATCH[] = { static __IO uint16_t *SCFSR_MATCH[] = {
@ -174,9 +131,11 @@ static __IO uint16_t *SCFSR_MATCH[] = {
&SCFSR_2, &SCFSR_2,
&SCFSR_3, &SCFSR_3,
&SCFSR_4, &SCFSR_4,
#if defined(TARGET_RZA1H)
&SCFSR_5, &SCFSR_5,
&SCFSR_6, &SCFSR_6,
&SCFSR_7, &SCFSR_7,
#endif
}; };
@ -192,32 +151,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
obj->serial.uart = (struct st_scif *)SCIF[uart]; obj->serial.uart = (struct st_scif *)SCIF[uart];
// enable power // enable power
switch (uart) { CPG.STBCR4 &= ~(1 << (7 - uart));
case UART0:
CPG.STBCR4 &= ~(1 << 7);
break;
case UART1:
CPG.STBCR4 &= ~(1 << 6);
break;
case UART2:
CPG.STBCR4 &= ~(1 << 5);
break;
case UART3:
CPG.STBCR4 &= ~(1 << 4);
break;
case UART4:
CPG.STBCR4 &= ~(1 << 3);
break;
case UART5:
CPG.STBCR4 &= ~(1 << 2);
break;
case UART6:
CPG.STBCR4 &= ~(1 << 1);
break;
case UART7:
CPG.STBCR4 &= ~(1 << 0);
break;
}
dummy = CPG.STBCR4; dummy = CPG.STBCR4;
/* ==== SCIF initial setting ==== */ /* ==== SCIF initial setting ==== */
@ -227,7 +161,7 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
/* ---- FIFO control register (SCFCR) setting ---- */ /* ---- FIFO control register (SCFCR) setting ---- */
/* Transmit FIFO reset & Receive FIFO data register reset */ /* Transmit FIFO reset & Receive FIFO data register reset */
obj->serial.uart->SCFCR = 0x0006; obj->serial.uart->SCFCR = 0x0006u;
/* ---- Serial status register (SCFSR) setting ---- */ /* ---- Serial status register (SCFSR) setting ---- */
dummy = obj->serial.uart->SCFSR; dummy = obj->serial.uart->SCFSR;
@ -265,32 +199,8 @@ void serial_init(serial_t *obj, PinName tx, PinName rx) {
pinmap_pinout(tx, PinMap_UART_TX); pinmap_pinout(tx, PinMap_UART_TX);
pinmap_pinout(rx, PinMap_UART_RX); pinmap_pinout(rx, PinMap_UART_RX);
switch (uart) { obj->serial.index = uart;
case UART0:
obj->serial.index = 0;
break;
case UART1:
obj->serial.index = 1;
break;
case UART2:
obj->serial.index = 2;
break;
case UART3:
obj->serial.index = 3;
break;
case UART4:
obj->serial.index = 4;
break;
case UART5:
obj->serial.index = 5;
break;
case UART6:
obj->serial.index = 6;
break;
case UART7:
obj->serial.index = 7;
break;
}
uart_data[obj->serial.index].sw_rts.pin = NC; uart_data[obj->serial.index].sw_rts.pin = NC;
uart_data[obj->serial.index].sw_cts.pin = NC; uart_data[obj->serial.index].sw_cts.pin = NC;
@ -313,51 +223,43 @@ void serial_free(serial_t *obj) {
// serial_baud // serial_baud
// set the baud rate, taking in to account the current SystemFrequency // set the baud rate, taking in to account the current SystemFrequency
void serial_baud(serial_t *obj, int baudrate) { void serial_baud(serial_t *obj, int baudrate) {
uint16_t DL; uint32_t pclk_base;
uint32_t bgdm = 1;
uint32_t cks = 0;
uint32_t DL;
obj->serial.uart->SCSMR &= ~0x0003; if (RZ_A1_IsClockMode0() == false) {
pclk_base = CM1_RENESAS_RZ_A1_P1_CLK;
} else {
pclk_base = CM0_RENESAS_RZ_A1_P1_CLK;
}
if (baudrate > 32552) { if (baudrate > (int)(pclk_base / 0x800)) {
obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1 obj->serial.uart->SCSMR &= ~0x0003;
DL = PCLK / (8 * baudrate); obj->serial.uart->SCEMR = 0x0081; // BGDM = 1, ABCS = 1
DL = (pclk_base + (4 * baudrate)) / (8 * baudrate); // Rounding
if (DL > 0) { if (DL > 0) {
DL--; DL--;
} }
obj->serial.uart->SCBRR = (uint8_t)DL; obj->serial.uart->SCBRR = (uint8_t)DL;
} else if (baudrate > 16276) { } else if (baudrate < (int)(pclk_base / 0x80000)) {
obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
obj->serial.uart->SCBRR = PCLK / (16 * baudrate) - 1;
} else if (baudrate > 8138) {
obj->serial.uart->SCEMR = 0x0000;
obj->serial.uart->SCBRR = PCLK / (32 * baudrate) - 1;
} else if (baudrate > 4169) {
obj->serial.uart->SCSMR |= 0x0001;
obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
obj->serial.uart->SCBRR = PCLK / (64 * baudrate) - 1;
} else if (baudrate > 2034) {
obj->serial.uart->SCSMR |= 0x0001;
obj->serial.uart->SCEMR = 0x0000;
obj->serial.uart->SCBRR = PCLK / (128 * baudrate) - 1;
} else if (baudrate > 1017) {
obj->serial.uart->SCSMR |= 0x0002;
obj->serial.uart->SCEMR = 0x0080; // BGDM = 1
obj->serial.uart->SCBRR = PCLK / (256 * baudrate) - 1;
} else if (baudrate > 508) {
obj->serial.uart->SCSMR |= 0x0002;
obj->serial.uart->SCEMR = 0x0000;
obj->serial.uart->SCBRR = PCLK / (512 * baudrate) - 1;
} else if (baudrate > 254) {
obj->serial.uart->SCSMR |= 0x0003; obj->serial.uart->SCSMR |= 0x0003;
obj->serial.uart->SCEMR = 0x0080; // BGDM = 1 obj->serial.uart->SCEMR = 0x0000;
obj->serial.uart->SCBRR = PCLK / (1024 * baudrate) - 1; obj->serial.uart->SCBRR = 0xFFu;
} else if (baudrate > 127) {
obj->serial.uart->SCSMR |= 0x0003;
obj->serial.uart->SCEMR = 0x0000;
obj->serial.uart->SCBRR = PCLK / (2048 * baudrate) - 1;
} else { } else {
obj->serial.uart->SCSMR |= 0x0003; DL = (pclk_base + (8 * baudrate)) / (16 * baudrate); // Rounding
obj->serial.uart->SCEMR = 0x0000; while (DL > 256) {
obj->serial.uart->SCBRR = 0xFFu; DL >>= 1;
if (bgdm == 1) {
bgdm = 0;
} else {
bgdm = 1;
cks++;
}
}
obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0003) | (uint8_t)cks;
obj->serial.uart->SCEMR = (uint8_t)(bgdm << 7);
obj->serial.uart->SCBRR = (uint8_t)(DL - 1);
} }
} }
@ -399,11 +301,10 @@ void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_b
break; break;
} }
obj->serial.uart->SCSMR = (obj->serial.uart->SCSMR & ~0x0078) obj->serial.uart->SCSMR = data_bits << 6
| (data_bits << 6) | parity_enable << 5
| (parity_enable << 5) | parity_select << 4
| (parity_select << 4) | stop_bits << 3;
| (stop_bits << 3);
} }
/****************************************************************************** /******************************************************************************
@ -538,89 +439,87 @@ static void uart_err_irq(IRQn_Type irq_num, uint32_t index) {
} }
} }
/* TX handler */ static void uart0_tx_irq(void) {
static void uart0_tx_irq(void) {
uart_tx_irq(SCIFTXI0_IRQn, 0); uart_tx_irq(SCIFTXI0_IRQn, 0);
} }
static void uart1_tx_irq(void) { static void uart0_rx_irq(void) {
uart_tx_irq(SCIFTXI1_IRQn, 1);
}
static void uart2_tx_irq(void) {
uart_tx_irq(SCIFTXI2_IRQn, 2);
}
static void uart3_tx_irq(void) {
uart_tx_irq(SCIFTXI3_IRQn, 3);
}
static void uart4_tx_irq(void) {
uart_tx_irq(SCIFTXI4_IRQn, 4);
}
static void uart5_tx_irq(void) {
uart_tx_irq(SCIFTXI5_IRQn, 5);
}
static void uart6_tx_irq(void) {
uart_tx_irq(SCIFTXI6_IRQn, 6);
}
static void uart7_tx_irq(void) {
uart_tx_irq(SCIFTXI7_IRQn, 7);
}
/* RX handler */
static void uart0_rx_irq(void) {
uart_rx_irq(SCIFRXI0_IRQn, 0); uart_rx_irq(SCIFRXI0_IRQn, 0);
} }
static void uart1_rx_irq(void) { static void uart0_er_irq(void) {
uart_rx_irq(SCIFRXI1_IRQn, 1);
}
static void uart2_rx_irq(void) {
uart_rx_irq(SCIFRXI2_IRQn, 2);
}
static void uart3_rx_irq(void) {
uart_rx_irq(SCIFRXI3_IRQn, 3);
}
static void uart4_rx_irq(void) {
uart_rx_irq(SCIFRXI4_IRQn, 4);
}
static void uart5_rx_irq(void) {
uart_rx_irq(SCIFRXI5_IRQn, 5);
}
static void uart6_rx_irq(void) {
uart_rx_irq(SCIFRXI6_IRQn, 6);
}
static void uart7_rx_irq(void) {
uart_rx_irq(SCIFRXI7_IRQn, 7);
}
/* Error handler */
static void uart0_er_irq(void)
{
uart_err_irq(SCIFERI0_IRQn, 0); uart_err_irq(SCIFERI0_IRQn, 0);
} }
static void uart1_er_irq(void)
{ static void uart1_tx_irq(void) {
uart_err_irq(SCIFERI0_IRQn, 1); uart_tx_irq(SCIFTXI1_IRQn, 1);
} }
static void uart2_er_irq(void) static void uart1_rx_irq(void) {
{ uart_rx_irq(SCIFRXI1_IRQn, 1);
uart_err_irq(SCIFERI0_IRQn, 2);
} }
static void uart3_er_irq(void) static void uart1_er_irq(void) {
{ uart_err_irq(SCIFERI1_IRQn, 1);
uart_err_irq(SCIFERI0_IRQn, 3);
} }
static void uart4_er_irq(void)
{ static void uart2_tx_irq(void) {
uart_err_irq(SCIFERI0_IRQn, 4); uart_tx_irq(SCIFTXI2_IRQn, 2);
} }
static void uart5_er_irq(void) static void uart2_rx_irq(void) {
{ uart_rx_irq(SCIFRXI2_IRQn, 2);
uart_err_irq(SCIFERI0_IRQn, 5);
} }
static void uart6_er_irq(void) static void uart2_er_irq(void) {
{ uart_err_irq(SCIFERI2_IRQn, 2);
uart_err_irq(SCIFERI0_IRQn, 6);
} }
static void uart7_er_irq(void)
{ static void uart3_tx_irq(void) {
uart_err_irq(SCIFERI0_IRQn, 7); uart_tx_irq(SCIFTXI3_IRQn, 3);
} }
static void uart3_rx_irq(void) {
uart_rx_irq(SCIFRXI3_IRQn, 3);
}
static void uart3_er_irq(void) {
uart_err_irq(SCIFERI3_IRQn, 3);
}
static void uart4_tx_irq(void) {
uart_tx_irq(SCIFTXI4_IRQn, 4);
}
static void uart4_rx_irq(void) {
uart_rx_irq(SCIFRXI4_IRQn, 4);
}
static void uart4_er_irq(void) {
uart_err_irq(SCIFERI4_IRQn, 4);
}
#if defined(TARGET_RZA1H)
static void uart5_tx_irq(void) {
uart_tx_irq(SCIFTXI5_IRQn, 5);
}
static void uart5_rx_irq(void) {
uart_rx_irq(SCIFRXI5_IRQn, 5);
}
static void uart5_er_irq(void) {
uart_err_irq(SCIFERI5_IRQn, 5);
}
static void uart6_tx_irq(void) {
uart_tx_irq(SCIFTXI6_IRQn, 6);
}
static void uart6_rx_irq(void) {
uart_rx_irq(SCIFRXI6_IRQn, 6);
}
static void uart6_er_irq(void) {
uart_err_irq(SCIFERI6_IRQn, 6);
}
static void uart7_tx_irq(void) {
uart_tx_irq(SCIFTXI7_IRQn, 7);
}
static void uart7_rx_irq(void) {
uart_rx_irq(SCIFRXI7_IRQn, 7);
}
static void uart7_er_irq(void) {
uart_err_irq(SCIFERI7_IRQn, 7);
}
#endif
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) { void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
irq_handler = handler; irq_handler = handler;
@ -638,7 +537,13 @@ static void serial_irq_set_irq(IRQn_Type IRQn, IRQHandler handler, uint32_t enab
} }
} }
static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) { static void serial_irq_err_set(serial_t *obj, uint32_t enable)
{
serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
IRQn_Type IRQn; IRQn_Type IRQn;
IRQHandler handler; IRQHandler handler;
@ -650,24 +555,6 @@ static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enabl
} }
} }
static void serial_irq_err_set(serial_t *obj, uint32_t enable)
{
serial_irq_set_irq(irq_set_tbl[obj->serial.index][2], hander_set_tbl[obj->serial.index][2], enable);
serial_irq_set_irq(irq_set_tbl[obj->serial.index][3], hander_set_tbl[obj->serial.index][3], enable);
}
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
if (RxIrq == irq) {
uart_data[obj->serial.index].rx_irq_set_api = enable;
}
serial_irq_set_internal(obj, irq, enable);
}
static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
uart_data[obj->serial.index].rx_irq_set_flow = enable;
serial_irq_set_internal(obj, RxIrq, enable);
}
/****************************************************************************** /******************************************************************************
* READ/WRITE * READ/WRITE
******************************************************************************/ ******************************************************************************/
@ -729,8 +616,8 @@ int serial_writable(serial_t *obj) {
void serial_clear(serial_t *obj) { void serial_clear(serial_t *obj) {
core_util_critical_section_enter(); core_util_critical_section_enter();
obj->serial.uart->SCFCR |= 0x06; // TFRST = 1, RFRST = 1 obj->serial.uart->SCFCR |= 0x0006u; // TFRST = 1, RFRST = 1
obj->serial.uart->SCFCR &= ~0x06; // TFRST = 0, RFRST = 0 obj->serial.uart->SCFCR &= ~0x0006u; // TFRST = 0, RFRST = 0
obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0 obj->serial.uart->SCFSR &= ~0x0093u; // ER, BRK, RDF, DR = 0
core_util_critical_section_exit(); core_util_critical_section_exit();
@ -755,23 +642,23 @@ void serial_break_clear(serial_t *obj) {
core_util_critical_section_exit(); core_util_critical_section_exit();
} }
#if DEVICE_SERIAL_FC
void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) { void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
// determine the UART to use // determine the UART to use
serial_flow_irq_set(obj, 0);
if (type == FlowControlRTSCTS) { if (type == FlowControlRTSCTS) {
core_util_critical_section_enter(); core_util_critical_section_enter();
obj->serial.uart->SCFCR = 0x0008u; // CTS/RTS enable obj->serial.uart->SCFCR |= 0x0008u; // CTS/RTS enable
core_util_critical_section_exit(); core_util_critical_section_exit();
pinmap_pinout(rxflow, PinMap_UART_RTS); pinmap_pinout(rxflow, PinMap_UART_RTS);
pinmap_pinout(txflow, PinMap_UART_CTS); pinmap_pinout(txflow, PinMap_UART_CTS);
} else { } else {
core_util_critical_section_enter(); core_util_critical_section_enter();
obj->serial.uart->SCFCR = 0x0000u; // CTS/RTS diable obj->serial.uart->SCFCR &= ~0x0008u; // CTS/RTS diable
core_util_critical_section_exit(); core_util_critical_section_exit();
} }
} }
#endif
static uint8_t serial_available_buffer(serial_t *obj) static uint8_t serial_available_buffer(serial_t *obj)
{ {

131
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/spi_api.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/spi_api.c
View File

@ -18,49 +18,10 @@
#include "spi_api.h" #include "spi_api.h"
#include "cmsis.h" #include "cmsis.h"
#include "pinmap.h" #include "PeripheralPins.h"
#include "mbed_error.h" #include "mbed_error.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "mbed_drv_cfg.h"
static const PinMap PinMap_SPI_SCLK[] = {
{P10_12, SPI_0, 4},
{P4_4 , SPI_1, 2},
{P6_4 , SPI_1, 7},
{P11_12, SPI_1, 2},
{P8_3 , SPI_2, 3},
{P5_0 , SPI_3, 8},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_SSEL[] = {
{P10_13, SPI_0, 4},
{P4_5 , SPI_1, 2},
{P6_5 , SPI_1, 7},
{P11_13, SPI_1, 2},
{P8_4 , SPI_2, 3},
{P5_1 , SPI_3, 8},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MOSI[] = {
{P10_14, SPI_0, 4},
{P4_6 , SPI_1, 2},
{P6_6 , SPI_1, 7},
{P11_14, SPI_1, 2},
{P8_5 , SPI_2, 3},
{P5_2 , SPI_3, 8},
{NC , NC , 0}
};
static const PinMap PinMap_SPI_MISO[] = {
{P10_15, SPI_0, 4},
{P4_7 , SPI_1, 2},
{P6_7 , SPI_1, 7},
{P11_15, SPI_1, 2},
{P8_6 , SPI_2, 3},
{P5_3 , SPI_3, 8},
{NC , NC , 0}
};
static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST; static const struct st_rspi *RSPI[] = RSPI_ADDRESS_LIST;
@ -87,13 +48,9 @@ void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel
obj->spi.index = spi; obj->spi.index = spi;
// enable power and clocking // enable power and clocking
switch (spi) { CPGSTBCR10 &= ~(0x80 >> spi);
case SPI_0: CPGSTBCR10 &= ~(0x80); break;
case SPI_1: CPGSTBCR10 &= ~(0x40); break;
case SPI_2: CPGSTBCR10 &= ~(0x20); break;
case SPI_3: CPGSTBCR10 &= ~(0x10); break;
}
dummy = CPGSTBCR10; dummy = CPGSTBCR10;
(void)dummy;
obj->spi.spi->SPCR = 0x00; // CTRL to 0 obj->spi.spi->SPCR = 0x00; // CTRL to 0
obj->spi.spi->SPSCR = 0x00; // no sequential operation obj->spi.spi->SPSCR = 0x00; // no sequential operation
@ -192,7 +149,7 @@ void spi_frequency(spi_t *obj, int hz) {
hz_min = pclk_base / 2 / 256 / 8; hz_min = pclk_base / 2 / 256 / 8;
hz_max = pclk_base / 2; hz_max = pclk_base / 2;
if ((hz < hz_min) || (hz > hz_max)) { if (((uint32_t)hz < hz_min) || ((uint32_t)hz > hz_max)) {
error("Couldn't setup requested SPI frequency"); error("Couldn't setup requested SPI frequency");
return; return;
} }
@ -293,37 +250,38 @@ int spi_busy(spi_t *obj) {
#if DEVICE_SPI_ASYNCH #if DEVICE_SPI_ASYNCH
#define IRQ_NUM 2 #define SPI_NUM 5
#define IRQ_NUM 2
static void spi_irqs_set(spi_t *obj, uint32_t enable); static void spi_irqs_set(spi_t *obj, uint32_t enable);
static void spi_async_write(spi_t *obj); static void spi_async_write(spi_t *obj);
static void spi_async_read(spi_t *obj); static void spi_async_read(spi_t *obj);
static void spi0_rx_irq(void); static void spi0_rx_irq(void);
static void spi1_rx_irq(void);
static void spi2_rx_irq(void);
static void spi3_rx_irq(void);
static void spi4_rx_irq(void);
static void spi0_er_irq(void); static void spi0_er_irq(void);
static void spi1_rx_irq(void);
static void spi1_er_irq(void); static void spi1_er_irq(void);
static void spi2_rx_irq(void);
static void spi2_er_irq(void); static void spi2_er_irq(void);
static void spi3_rx_irq(void);
static void spi3_er_irq(void); static void spi3_er_irq(void);
static void spi4_rx_irq(void);
static void spi4_er_irq(void); static void spi4_er_irq(void);
static const IRQn_Type irq_set_tbl[RSPI_COUNT][IRQ_NUM] = { static const IRQn_Type irq_set_tbl[SPI_NUM][IRQ_NUM] = {
{RSPISPRI0_IRQn, RSPISPEI0_IRQn}, {RSPISPRI0_IRQn, RSPISPEI0_IRQn},
{RSPISPRI1_IRQn, RSPISPEI1_IRQn}, {RSPISPRI1_IRQn, RSPISPEI1_IRQn},
{RSPISPRI2_IRQn, RSPISPEI2_IRQn}, {RSPISPRI2_IRQn, RSPISPEI2_IRQn},
{RSPISPRI3_IRQn, RSPISPEI3_IRQn}, {RSPISPRI3_IRQn, RSPISPEI3_IRQn},
{RSPISPRI4_IRQn, RSPISPEI4_IRQn} {RSPISPRI4_IRQn, RSPISPEI4_IRQn},
}; };
static const IRQHandler hander_set_tbl[RSPI_COUNT][IRQ_NUM] = { static const IRQHandler hander_set_tbl[SPI_NUM][IRQ_NUM] = {
{spi0_rx_irq, spi0_er_irq}, {spi0_rx_irq, spi0_er_irq},
{spi1_rx_irq, spi1_er_irq}, {spi1_rx_irq, spi1_er_irq},
{spi2_rx_irq, spi2_er_irq}, {spi2_rx_irq, spi2_er_irq},
{spi3_rx_irq, spi3_er_irq}, {spi3_rx_irq, spi3_er_irq},
{spi4_rx_irq, spi4_er_irq} {spi4_rx_irq, spi4_er_irq},
}; };
struct spi_global_data_s { struct spi_global_data_s {
@ -331,7 +289,7 @@ struct spi_global_data_s {
uint32_t async_callback, event, wanted_events; uint32_t async_callback, event, wanted_events;
}; };
static struct spi_global_data_s spi_data[RSPI_COUNT]; static struct spi_global_data_s spi_data[SPI_NUM];
static void spi_rx_irq(IRQn_Type irq_num, uint32_t index) static void spi_rx_irq(IRQn_Type irq_num, uint32_t index)
{ {
@ -388,53 +346,34 @@ static void spi_err_irq(IRQn_Type irq_num, uint32_t index)
} }
} }
static void spi0_rx_irq(void) static void spi0_rx_irq(void) {
{
spi_rx_irq(RSPISPRI0_IRQn, 0); spi_rx_irq(RSPISPRI0_IRQn, 0);
} }
static void spi0_er_irq(void) {
static void spi1_rx_irq(void)
{
spi_rx_irq(RSPISPRI1_IRQn, 1);
}
static void spi2_rx_irq(void)
{
spi_rx_irq(RSPISPRI2_IRQn, 2);
}
static void spi3_rx_irq(void)
{
spi_rx_irq(RSPISPRI3_IRQn, 3);
}
static void spi4_rx_irq(void)
{
spi_rx_irq(RSPISPRI4_IRQn, 4);
}
static void spi0_er_irq(void)
{
spi_err_irq(RSPISPEI0_IRQn, 0); spi_err_irq(RSPISPEI0_IRQn, 0);
} }
static void spi1_rx_irq(void) {
static void spi1_er_irq(void) spi_rx_irq(RSPISPRI1_IRQn, 1);
{ }
static void spi1_er_irq(void) {
spi_err_irq(RSPISPEI1_IRQn, 1); spi_err_irq(RSPISPEI1_IRQn, 1);
} }
static void spi2_rx_irq(void) {
static void spi2_er_irq(void) spi_rx_irq(RSPISPRI2_IRQn, 2);
{ }
static void spi2_er_irq(void) {
spi_err_irq(RSPISPEI2_IRQn, 2); spi_err_irq(RSPISPEI2_IRQn, 2);
} }
static void spi3_rx_irq(void) {
static void spi3_er_irq(void) spi_rx_irq(RSPISPRI3_IRQn, 3);
{ }
static void spi3_er_irq(void) {
spi_err_irq(RSPISPEI3_IRQn, 3); spi_err_irq(RSPISPEI3_IRQn, 3);
} }
static void spi4_rx_irq(void) {
static void spi4_er_irq(void) spi_rx_irq(RSPISPRI4_IRQn, 4);
{ }
static void spi4_er_irq(void) {
spi_err_irq(RSPISPEI4_IRQn, 4); spi_err_irq(RSPISPEI4_IRQn, 4);
} }
@ -562,7 +501,7 @@ void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx,
obj->rx_buff.length = rx_length * bit_width / 8; obj->rx_buff.length = rx_length * bit_width / 8;
obj->rx_buff.pos = 0; obj->rx_buff.pos = 0;
obj->rx_buff.width = bit_width; obj->rx_buff.width = bit_width;
for (i = 0; i < obj->rx_buff.length; i++) { for (i = 0; i < (int)obj->rx_buff.length; i++) {
((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD; ((uint8_t *)obj->rx_buff.buffer)[i] = SPI_FILL_WORD;
} }

4
targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/us_ticker.c → targets/TARGET_RENESAS/TARGET_RZ_A1XX/us_ticker.c
View File

@ -16,10 +16,10 @@
#include <stddef.h> #include <stddef.h>
#include "us_ticker_api.h" #include "us_ticker_api.h"
#include "PeripheralNames.h" #include "PeripheralNames.h"
#include "ostm_iodefine.h" #include "iodefine.h"
#include "cmsis.h"
#include "RZ_A1_Init.h" #include "RZ_A1_Init.h"
#include "MBRZA1H.h"
#include "vfp_neon_push_pop.h" #include "vfp_neon_push_pop.h"
#include "mbed_critical.h" #include "mbed_critical.h"